Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2571583a | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
8b10b0b3 MR |
946 | |
947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
948 | Needed for broken assembly produced by some GCC versions and some | |
949 | sloppy code out there, where branches to data labels are present. */ | |
950 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 951 | \f |
4d7206a2 RS |
952 | /* The expansion of many macros depends on the type of symbol that |
953 | they refer to. For example, when generating position-dependent code, | |
954 | a macro that refers to a symbol may have two different expansions, | |
955 | one which uses GP-relative addresses and one which uses absolute | |
956 | addresses. When generating SVR4-style PIC, a macro may have | |
957 | different expansions for local and global symbols. | |
958 | ||
959 | We handle these situations by generating both sequences and putting | |
960 | them in variant frags. In position-dependent code, the first sequence | |
961 | will be the GP-relative one and the second sequence will be the | |
962 | absolute one. In SVR4 PIC, the first sequence will be for global | |
963 | symbols and the second will be for local symbols. | |
964 | ||
584892a6 RS |
965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
966 | SECOND are the lengths of the two sequences in bytes. These fields | |
967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
968 | the subtype has the following flags: | |
4d7206a2 | 969 | |
ce8ad872 MR |
970 | RELAX_PIC |
971 | Set if generating PIC code. | |
972 | ||
584892a6 RS |
973 | RELAX_USE_SECOND |
974 | Set if it has been decided that we should use the second | |
975 | sequence instead of the first. | |
976 | ||
977 | RELAX_SECOND_LONGER | |
978 | Set in the first variant frag if the macro's second implementation | |
979 | is longer than its first. This refers to the macro as a whole, | |
980 | not an individual relaxation. | |
981 | ||
982 | RELAX_NOMACRO | |
983 | Set in the first variant frag if the macro appeared in a .set nomacro | |
984 | block and if one alternative requires a warning but the other does not. | |
985 | ||
986 | RELAX_DELAY_SLOT | |
987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
988 | delay slot. | |
4d7206a2 | 989 | |
df58fc94 RS |
990 | RELAX_DELAY_SLOT_16BIT |
991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
992 | 16-bit instruction. | |
993 | ||
994 | RELAX_DELAY_SLOT_SIZE_FIRST | |
995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
996 | the macro is of the wrong size for the branch delay slot. | |
997 | ||
998 | RELAX_DELAY_SLOT_SIZE_SECOND | |
999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1000 | the macro is of the wrong size for the branch delay slot. | |
1001 | ||
4d7206a2 RS |
1002 | The frag's "opcode" points to the first fixup for relaxable code. |
1003 | ||
1004 | Relaxable macros are generated using a sequence such as: | |
1005 | ||
1006 | relax_start (SYMBOL); | |
1007 | ... generate first expansion ... | |
1008 | relax_switch (); | |
1009 | ... generate second expansion ... | |
1010 | relax_end (); | |
1011 | ||
1012 | The code and fixups for the unwanted alternative are discarded | |
1013 | by md_convert_frag. */ | |
ce8ad872 MR |
1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1016 | |
584892a6 RS |
1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1018 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1020 | #define RELAX_USE_SECOND 0x20000 | |
1021 | #define RELAX_SECOND_LONGER 0x40000 | |
1022 | #define RELAX_NOMACRO 0x80000 | |
1023 | #define RELAX_DELAY_SLOT 0x100000 | |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
134c0c8b | 1030 | beq reg1, reg2, label |
4a6a3df4 AO |
1031 | delay slot |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1096 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1097 | ((relax_substateT) \ |
1098 | (0xc0000000 \ | |
1099 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1100 | | ((pic) ? 0x20 : 0) \ |
1101 | | ((toofar) ? 0x40 : 0) \ | |
1102 | | ((link) ? 0x80 : 0) \ | |
1103 | | ((likely) ? 0x100 : 0) \ | |
1104 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1112 | |
252b5132 RH |
1113 | /* For mips16 code, we use an entirely different form of relaxation. |
1114 | mips16 supports two versions of most instructions which take | |
1115 | immediate values: a small one which takes some small value, and a | |
1116 | larger one which takes a 16 bit value. Since branches also follow | |
1117 | this pattern, relaxing these values is required. | |
1118 | ||
1119 | We can assemble both mips16 and normal MIPS code in a single | |
1120 | object. Therefore, we need to support this type of relaxation at | |
1121 | the same time that we support the relaxation described above. We | |
1122 | use the high bit of the subtype field to distinguish these cases. | |
1123 | ||
1124 | The information we store for this type of relaxation is the | |
1125 | argument code found in the opcode file for this relocation, whether | |
1126 | the user explicitly requested a small or extended form, and whether | |
1127 | the relocation is in a jump or jal delay slot. That tells us the | |
1128 | size of the value, and how it should be stored. We also store | |
1129 | whether the fragment is considered to be extended or not. We also | |
1130 | store whether this is known to be a branch to a different section, | |
1131 | whether we have tried to relax this frag yet, and whether we have | |
1132 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1133 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1134 | small, ext, \ |
1135 | dslot, jal_dslot) \ | |
252b5132 RH |
1136 | (0x80000000 \ |
1137 | | ((type) & 0xff) \ | |
25499ac7 MR |
1138 | | ((e2) ? 0x100 : 0) \ |
1139 | | ((pic) ? 0x200 : 0) \ | |
1140 | | ((sym32) ? 0x400 : 0) \ | |
1141 | | ((nomacro) ? 0x800 : 0) \ | |
1142 | | ((small) ? 0x1000 : 0) \ | |
1143 | | ((ext) ? 0x2000 : 0) \ | |
1144 | | ((dslot) ? 0x4000 : 0) \ | |
1145 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1146 | |
4a6a3df4 | 1147 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1148 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1149 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1150 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1151 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1152 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1153 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1154 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1155 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1156 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1157 | ||
1158 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1159 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1160 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1161 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1162 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1163 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1164 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1165 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1166 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1167 | |
df58fc94 RS |
1168 | /* For microMIPS code, we use relaxation similar to one we use for |
1169 | MIPS16 code. Some instructions that take immediate values support | |
1170 | two encodings: a small one which takes some small value, and a | |
1171 | larger one which takes a 16 bit value. As some branches also follow | |
1172 | this pattern, relaxing these values is required. | |
1173 | ||
1174 | We can assemble both microMIPS and normal MIPS code in a single | |
1175 | object. Therefore, we need to support this type of relaxation at | |
1176 | the same time that we support the relaxation described above. We | |
1177 | use one of the high bits of the subtype field to distinguish these | |
1178 | cases. | |
1179 | ||
1180 | The information we store for this type of relaxation is the argument | |
1181 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1182 | selected as the assembler temporary, whether in the 32-bit |
1183 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1184 | compact, whether there is no delay-slot instruction available to fill |
1185 | in, whether it stores the link address implicitly in $ra, whether | |
1186 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1187 | instructions is enabled, and whether the displacement of a branch is |
1188 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1189 | branch, respectively. */ | |
ce8ad872 | 1190 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1191 | uncond, compact, link, nods, \ |
40209cad MR |
1192 | relax32, toofar16, toofar32) \ |
1193 | (0x40000000 \ | |
1194 | | ((type) & 0xff) \ | |
1195 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1196 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1197 | | ((pic) ? 0x4000 : 0) \ |
1198 | | ((uncond) ? 0x8000 : 0) \ | |
1199 | | ((compact) ? 0x10000 : 0) \ | |
1200 | | ((link) ? 0x20000 : 0) \ | |
1201 | | ((nods) ? 0x40000 : 0) \ | |
1202 | | ((relax32) ? 0x80000 : 0) \ | |
1203 | | ((toofar16) ? 0x100000 : 0) \ | |
1204 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1205 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1206 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1207 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1208 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1209 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1210 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1211 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1212 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1213 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1214 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1215 | ||
1216 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1217 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1218 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1219 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1220 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1221 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1222 | |
43c0598f RS |
1223 | /* Sign-extend 16-bit value X. */ |
1224 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1225 | ||
885add95 CD |
1226 | /* Is the given value a sign-extended 32-bit value? */ |
1227 | #define IS_SEXT_32BIT_NUM(x) \ | |
1228 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1229 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1230 | ||
1231 | /* Is the given value a sign-extended 16-bit value? */ | |
1232 | #define IS_SEXT_16BIT_NUM(x) \ | |
1233 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1234 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1235 | ||
df58fc94 RS |
1236 | /* Is the given value a sign-extended 12-bit value? */ |
1237 | #define IS_SEXT_12BIT_NUM(x) \ | |
1238 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1239 | ||
7f3c4072 CM |
1240 | /* Is the given value a sign-extended 9-bit value? */ |
1241 | #define IS_SEXT_9BIT_NUM(x) \ | |
1242 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1243 | ||
2051e8c4 MR |
1244 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1245 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1246 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1247 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1248 | ||
bf12938e RS |
1249 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1250 | SHIFT places. */ | |
1251 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1252 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1253 | ||
bf12938e | 1254 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1255 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1256 | (!(MICROMIPS) \ | |
1257 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1258 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1259 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1260 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1261 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1262 | MIPS16OP_MASK_##FIELD, \ | |
1263 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1264 | |
1265 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1266 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1267 | \f |
df58fc94 RS |
1268 | /* Whether or not we are emitting a branch-likely macro. */ |
1269 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1270 | ||
4d7206a2 RS |
1271 | /* Global variables used when generating relaxable macros. See the |
1272 | comment above RELAX_ENCODE for more details about how relaxation | |
1273 | is used. */ | |
1274 | static struct { | |
1275 | /* 0 if we're not emitting a relaxable macro. | |
1276 | 1 if we're emitting the first of the two relaxation alternatives. | |
1277 | 2 if we're emitting the second alternative. */ | |
1278 | int sequence; | |
1279 | ||
1280 | /* The first relaxable fixup in the current frag. (In other words, | |
1281 | the first fixup that refers to relaxable code.) */ | |
1282 | fixS *first_fixup; | |
1283 | ||
1284 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1285 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1286 | unsigned int sizes[2]; | |
1287 | ||
1288 | /* The symbol on which the choice of sequence depends. */ | |
1289 | symbolS *symbol; | |
1290 | } mips_relax; | |
252b5132 | 1291 | \f |
584892a6 RS |
1292 | /* Global variables used to decide whether a macro needs a warning. */ |
1293 | static struct { | |
1294 | /* True if the macro is in a branch delay slot. */ | |
1295 | bfd_boolean delay_slot_p; | |
1296 | ||
df58fc94 RS |
1297 | /* Set to the length in bytes required if the macro is in a delay slot |
1298 | that requires a specific length of instruction, otherwise zero. */ | |
1299 | unsigned int delay_slot_length; | |
1300 | ||
584892a6 RS |
1301 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1302 | in bytes and sizes[1] is the length of the second alternative. | |
1303 | For non-relaxable macros, both elements give the length of the | |
1304 | macro in bytes. */ | |
1305 | unsigned int sizes[2]; | |
1306 | ||
df58fc94 RS |
1307 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1308 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1309 | is the length of the first instruction of the second alternative. | |
1310 | For non-relaxable macros, both elements give the length of the first | |
1311 | instruction in bytes. | |
1312 | ||
1313 | Set to zero if we haven't yet seen the first instruction. */ | |
1314 | unsigned int first_insn_sizes[2]; | |
1315 | ||
1316 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1317 | first alternative and insns[1] is the number of instructions for the | |
1318 | second alternative. | |
1319 | ||
1320 | For non-relaxable macros, both elements give the number of | |
1321 | instructions for the macro. */ | |
1322 | unsigned int insns[2]; | |
1323 | ||
584892a6 RS |
1324 | /* The first variant frag for this macro. */ |
1325 | fragS *first_frag; | |
1326 | } mips_macro_warning; | |
1327 | \f | |
252b5132 RH |
1328 | /* Prototypes for static functions. */ |
1329 | ||
252b5132 RH |
1330 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1331 | ||
b34976b6 | 1332 | static void append_insn |
df58fc94 RS |
1333 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1334 | bfd_boolean expansionp); | |
7d10b47d | 1335 | static void mips_no_prev_insn (void); |
c67a084a | 1336 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1337 | static void mips16_macro_build |
03ea81db | 1338 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1339 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1340 | static void macro_start (void); |
1341 | static void macro_end (void); | |
833794fc | 1342 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1343 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1344 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1345 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1346 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1347 | static void mips16_immed |
3b4dbbbf | 1348 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1349 | unsigned int, unsigned long *); |
5e0116d5 | 1350 | static size_t my_getSmallExpression |
17a2f251 TS |
1351 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1352 | static void my_getExpression (expressionS *, char *); | |
1353 | static void s_align (int); | |
1354 | static void s_change_sec (int); | |
1355 | static void s_change_section (int); | |
1356 | static void s_cons (int); | |
1357 | static void s_float_cons (int); | |
1358 | static void s_mips_globl (int); | |
1359 | static void s_option (int); | |
1360 | static void s_mipsset (int); | |
1361 | static void s_abicalls (int); | |
1362 | static void s_cpload (int); | |
1363 | static void s_cpsetup (int); | |
1364 | static void s_cplocal (int); | |
1365 | static void s_cprestore (int); | |
1366 | static void s_cpreturn (int); | |
741d6ea8 JM |
1367 | static void s_dtprelword (int); |
1368 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1369 | static void s_tprelword (int); |
1370 | static void s_tpreldword (int); | |
17a2f251 TS |
1371 | static void s_gpvalue (int); |
1372 | static void s_gpword (int); | |
1373 | static void s_gpdword (int); | |
a3f278e2 | 1374 | static void s_ehword (int); |
17a2f251 TS |
1375 | static void s_cpadd (int); |
1376 | static void s_insn (int); | |
ba92f887 | 1377 | static void s_nan (int); |
919731af | 1378 | static void s_module (int); |
17a2f251 TS |
1379 | static void s_mips_ent (int); |
1380 | static void s_mips_end (int); | |
1381 | static void s_mips_frame (int); | |
1382 | static void s_mips_mask (int reg_type); | |
1383 | static void s_mips_stab (int); | |
1384 | static void s_mips_weakext (int); | |
1385 | static void s_mips_file (int); | |
1386 | static void s_mips_loc (int); | |
9e009953 | 1387 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1388 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1389 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1390 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1391 | static void file_mips_check_options (void); |
e7af610e NC |
1392 | |
1393 | /* Table and functions used to map between CPU/ISA names, and | |
1394 | ISA levels, and CPU numbers. */ | |
1395 | ||
e972090a NC |
1396 | struct mips_cpu_info |
1397 | { | |
e7af610e | 1398 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1399 | int flags; /* MIPS_CPU_* flags. */ |
1400 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1401 | int isa; /* ISA level. */ |
1402 | int cpu; /* CPU number (default CPU if ISA). */ | |
1403 | }; | |
1404 | ||
ad3fea08 | 1405 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1406 | |
17a2f251 TS |
1407 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1408 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1409 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1410 | \f |
c31f3936 RS |
1411 | /* Command-line options. */ |
1412 | const char *md_shortopts = "O::g::G:"; | |
1413 | ||
1414 | enum options | |
1415 | { | |
1416 | OPTION_MARCH = OPTION_MD_BASE, | |
1417 | OPTION_MTUNE, | |
1418 | OPTION_MIPS1, | |
1419 | OPTION_MIPS2, | |
1420 | OPTION_MIPS3, | |
1421 | OPTION_MIPS4, | |
1422 | OPTION_MIPS5, | |
1423 | OPTION_MIPS32, | |
1424 | OPTION_MIPS64, | |
1425 | OPTION_MIPS32R2, | |
ae52f483 AB |
1426 | OPTION_MIPS32R3, |
1427 | OPTION_MIPS32R5, | |
7361da2c | 1428 | OPTION_MIPS32R6, |
c31f3936 | 1429 | OPTION_MIPS64R2, |
ae52f483 AB |
1430 | OPTION_MIPS64R3, |
1431 | OPTION_MIPS64R5, | |
7361da2c | 1432 | OPTION_MIPS64R6, |
c31f3936 RS |
1433 | OPTION_MIPS16, |
1434 | OPTION_NO_MIPS16, | |
1435 | OPTION_MIPS3D, | |
1436 | OPTION_NO_MIPS3D, | |
1437 | OPTION_MDMX, | |
1438 | OPTION_NO_MDMX, | |
1439 | OPTION_DSP, | |
1440 | OPTION_NO_DSP, | |
1441 | OPTION_MT, | |
1442 | OPTION_NO_MT, | |
1443 | OPTION_VIRT, | |
1444 | OPTION_NO_VIRT, | |
56d438b1 CF |
1445 | OPTION_MSA, |
1446 | OPTION_NO_MSA, | |
c31f3936 RS |
1447 | OPTION_SMARTMIPS, |
1448 | OPTION_NO_SMARTMIPS, | |
1449 | OPTION_DSPR2, | |
1450 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1451 | OPTION_DSPR3, |
1452 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1453 | OPTION_EVA, |
1454 | OPTION_NO_EVA, | |
7d64c587 AB |
1455 | OPTION_XPA, |
1456 | OPTION_NO_XPA, | |
c31f3936 RS |
1457 | OPTION_MICROMIPS, |
1458 | OPTION_NO_MICROMIPS, | |
1459 | OPTION_MCU, | |
1460 | OPTION_NO_MCU, | |
25499ac7 MR |
1461 | OPTION_MIPS16E2, |
1462 | OPTION_NO_MIPS16E2, | |
c31f3936 RS |
1463 | OPTION_COMPAT_ARCH_BASE, |
1464 | OPTION_M4650, | |
1465 | OPTION_NO_M4650, | |
1466 | OPTION_M4010, | |
1467 | OPTION_NO_M4010, | |
1468 | OPTION_M4100, | |
1469 | OPTION_NO_M4100, | |
1470 | OPTION_M3900, | |
1471 | OPTION_NO_M3900, | |
1472 | OPTION_M7000_HILO_FIX, | |
1473 | OPTION_MNO_7000_HILO_FIX, | |
1474 | OPTION_FIX_24K, | |
1475 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1476 | OPTION_FIX_RM7000, |
1477 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1478 | OPTION_FIX_LOONGSON2F_JUMP, |
1479 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1480 | OPTION_FIX_LOONGSON2F_NOP, | |
1481 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1482 | OPTION_FIX_VR4120, | |
1483 | OPTION_NO_FIX_VR4120, | |
1484 | OPTION_FIX_VR4130, | |
1485 | OPTION_NO_FIX_VR4130, | |
1486 | OPTION_FIX_CN63XXP1, | |
1487 | OPTION_NO_FIX_CN63XXP1, | |
1488 | OPTION_TRAP, | |
1489 | OPTION_BREAK, | |
1490 | OPTION_EB, | |
1491 | OPTION_EL, | |
1492 | OPTION_FP32, | |
1493 | OPTION_GP32, | |
1494 | OPTION_CONSTRUCT_FLOATS, | |
1495 | OPTION_NO_CONSTRUCT_FLOATS, | |
1496 | OPTION_FP64, | |
351cdf24 | 1497 | OPTION_FPXX, |
c31f3936 RS |
1498 | OPTION_GP64, |
1499 | OPTION_RELAX_BRANCH, | |
1500 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1501 | OPTION_IGNORE_BRANCH_ISA, |
1502 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1503 | OPTION_INSN32, |
1504 | OPTION_NO_INSN32, | |
c31f3936 RS |
1505 | OPTION_MSHARED, |
1506 | OPTION_MNO_SHARED, | |
1507 | OPTION_MSYM32, | |
1508 | OPTION_MNO_SYM32, | |
1509 | OPTION_SOFT_FLOAT, | |
1510 | OPTION_HARD_FLOAT, | |
1511 | OPTION_SINGLE_FLOAT, | |
1512 | OPTION_DOUBLE_FLOAT, | |
1513 | OPTION_32, | |
c31f3936 RS |
1514 | OPTION_CALL_SHARED, |
1515 | OPTION_CALL_NONPIC, | |
1516 | OPTION_NON_SHARED, | |
1517 | OPTION_XGOT, | |
1518 | OPTION_MABI, | |
1519 | OPTION_N32, | |
1520 | OPTION_64, | |
1521 | OPTION_MDEBUG, | |
1522 | OPTION_NO_MDEBUG, | |
1523 | OPTION_PDR, | |
1524 | OPTION_NO_PDR, | |
1525 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1526 | OPTION_NAN, |
351cdf24 MF |
1527 | OPTION_ODD_SPREG, |
1528 | OPTION_NO_ODD_SPREG, | |
c31f3936 RS |
1529 | OPTION_END_OF_ENUM |
1530 | }; | |
1531 | ||
1532 | struct option md_longopts[] = | |
1533 | { | |
1534 | /* Options which specify architecture. */ | |
1535 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1536 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1537 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1538 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1539 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1540 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1541 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1542 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1543 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1544 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1545 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1546 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1547 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1548 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1549 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1550 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1551 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1552 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1553 | |
1554 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1555 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1556 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1557 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1558 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1559 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1560 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1561 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1562 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1563 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1564 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1565 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1566 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1567 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1568 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1569 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1570 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1571 | {"meva", no_argument, NULL, OPTION_EVA}, |
1572 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1573 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1574 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1575 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1576 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1577 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1578 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1579 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1580 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1581 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1582 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1583 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1584 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
c31f3936 RS |
1585 | |
1586 | /* Old-style architecture options. Don't add more of these. */ | |
1587 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1588 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1589 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1590 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1591 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1592 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1593 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1594 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1595 | ||
1596 | /* Options which enable bug fixes. */ | |
1597 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1598 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1599 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1600 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1601 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1602 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1603 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1604 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1605 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1606 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1607 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1608 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1609 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1610 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1611 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1612 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1613 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1614 | ||
1615 | /* Miscellaneous options. */ | |
1616 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1617 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1618 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1619 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1620 | {"EB", no_argument, NULL, OPTION_EB}, | |
1621 | {"EL", no_argument, NULL, OPTION_EL}, | |
1622 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1623 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1624 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1625 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1626 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1627 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1628 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1629 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1630 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1631 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1632 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1633 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1634 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1635 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1636 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1637 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1638 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1639 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1640 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1641 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1642 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1643 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1644 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1645 | |
1646 | /* Strictly speaking this next option is ELF specific, | |
1647 | but we allow it for other ports as well in order to | |
1648 | make testing easier. */ | |
1649 | {"32", no_argument, NULL, OPTION_32}, | |
1650 | ||
1651 | /* ELF-specific options. */ | |
c31f3936 RS |
1652 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1653 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1654 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1655 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1656 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1657 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1658 | {"n32", no_argument, NULL, OPTION_N32}, | |
1659 | {"64", no_argument, NULL, OPTION_64}, | |
1660 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1661 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1662 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1663 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1664 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1665 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1666 | |
1667 | {NULL, no_argument, NULL, 0} | |
1668 | }; | |
1669 | size_t md_longopts_size = sizeof (md_longopts); | |
1670 | \f | |
c6278170 RS |
1671 | /* Information about either an Application Specific Extension or an |
1672 | optional architecture feature that, for simplicity, we treat in the | |
1673 | same way as an ASE. */ | |
1674 | struct mips_ase | |
1675 | { | |
1676 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1677 | const char *name; | |
1678 | ||
1679 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1680 | and 64-bit architectures, the flags here refer to the subset that | |
1681 | is available on both. */ | |
1682 | unsigned int flags; | |
1683 | ||
1684 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1685 | architectures but that are not included in FLAGS. */ | |
1686 | unsigned int flags64; | |
1687 | ||
1688 | /* The command-line options that turn the ASE on and off. */ | |
1689 | int option_on; | |
1690 | int option_off; | |
1691 | ||
1692 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1693 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1694 | int mips32_rev; | |
1695 | int mips64_rev; | |
1696 | int micromips32_rev; | |
1697 | int micromips64_rev; | |
7361da2c AB |
1698 | |
1699 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1700 | been removed. */ | |
1701 | int rem_rev; | |
c6278170 RS |
1702 | }; |
1703 | ||
1704 | /* A table of all supported ASEs. */ | |
1705 | static const struct mips_ase mips_ases[] = { | |
1706 | { "dsp", ASE_DSP, ASE_DSP64, | |
1707 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1708 | 2, 2, 2, 2, |
1709 | -1 }, | |
c6278170 RS |
1710 | |
1711 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1712 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1713 | 2, 2, 2, 2, |
1714 | -1 }, | |
c6278170 | 1715 | |
8f4f9071 MF |
1716 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1717 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1718 | 6, 6, -1, -1, | |
1719 | -1 }, | |
1720 | ||
c6278170 RS |
1721 | { "eva", ASE_EVA, 0, |
1722 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1723 | 2, 2, 2, 2, |
1724 | -1 }, | |
c6278170 RS |
1725 | |
1726 | { "mcu", ASE_MCU, 0, | |
1727 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1728 | 2, 2, 2, 2, |
1729 | -1 }, | |
c6278170 RS |
1730 | |
1731 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1732 | { "mdmx", ASE_MDMX, 0, | |
1733 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1734 | -1, 1, -1, -1, |
1735 | 6 }, | |
c6278170 RS |
1736 | |
1737 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1738 | { "mips3d", ASE_MIPS3D, 0, | |
1739 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1740 | 2, 1, -1, -1, |
1741 | 6 }, | |
c6278170 RS |
1742 | |
1743 | { "mt", ASE_MT, 0, | |
1744 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1745 | 2, 2, -1, -1, |
1746 | -1 }, | |
c6278170 RS |
1747 | |
1748 | { "smartmips", ASE_SMARTMIPS, 0, | |
1749 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1750 | 1, -1, -1, -1, |
1751 | 6 }, | |
c6278170 RS |
1752 | |
1753 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1754 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1755 | 2, 2, 2, 2, |
1756 | -1 }, | |
56d438b1 CF |
1757 | |
1758 | { "msa", ASE_MSA, ASE_MSA64, | |
1759 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1760 | 2, 2, 2, 2, |
1761 | -1 }, | |
7d64c587 AB |
1762 | |
1763 | { "xpa", ASE_XPA, 0, | |
1764 | OPTION_XPA, OPTION_NO_XPA, | |
7361da2c AB |
1765 | 2, 2, -1, -1, |
1766 | -1 }, | |
25499ac7 MR |
1767 | |
1768 | { "mips16e2", ASE_MIPS16E2, 0, | |
1769 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1770 | 2, 2, -1, -1, | |
1771 | 6 }, | |
c6278170 RS |
1772 | }; |
1773 | ||
1774 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1775 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1776 | |
1777 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1778 | static const unsigned int mips_ase_groups[] = { | |
8f4f9071 | 1779 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
c6278170 RS |
1780 | }; |
1781 | \f | |
252b5132 RH |
1782 | /* Pseudo-op table. |
1783 | ||
1784 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1785 | should be defined here, but are currently unsupported: .alias, | |
1786 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1787 | ||
1788 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1789 | specific to the type of debugging information being generated, and | |
1790 | should be defined by the object format: .aent, .begin, .bend, | |
1791 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1792 | .vreg. | |
1793 | ||
1794 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1795 | not MIPS CPU specific, but are also not specific to the object file | |
1796 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1797 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1798 | |
e972090a NC |
1799 | static const pseudo_typeS mips_pseudo_table[] = |
1800 | { | |
beae10d5 | 1801 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1802 | {"option", s_option, 0}, |
1803 | {"set", s_mipsset, 0}, | |
1804 | {"rdata", s_change_sec, 'r'}, | |
1805 | {"sdata", s_change_sec, 's'}, | |
1806 | {"livereg", s_ignore, 0}, | |
1807 | {"abicalls", s_abicalls, 0}, | |
1808 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1809 | {"cpsetup", s_cpsetup, 0}, |
1810 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1811 | {"cprestore", s_cprestore, 0}, |
6478892d | 1812 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1813 | {"dtprelword", s_dtprelword, 0}, |
1814 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1815 | {"tprelword", s_tprelword, 0}, |
1816 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1817 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1818 | {"gpword", s_gpword, 0}, |
10181a0d | 1819 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1820 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1821 | {"cpadd", s_cpadd, 0}, |
1822 | {"insn", s_insn, 0}, | |
ba92f887 | 1823 | {"nan", s_nan, 0}, |
919731af | 1824 | {"module", s_module, 0}, |
252b5132 | 1825 | |
beae10d5 | 1826 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1827 | chips. */ |
38a57ae7 | 1828 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1829 | {"bss", s_change_sec, 'b'}, |
1830 | {"err", s_err, 0}, | |
1831 | {"half", s_cons, 1}, | |
1832 | {"dword", s_cons, 3}, | |
1833 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1834 | {"origin", s_org, 0}, |
1835 | {"repeat", s_rept, 0}, | |
252b5132 | 1836 | |
998b3c36 MR |
1837 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1838 | {"sbss", s_change_sec, 'B'}, | |
1839 | ||
beae10d5 | 1840 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1841 | here for one reason or another. */ |
1842 | {"align", s_align, 0}, | |
1843 | {"byte", s_cons, 0}, | |
1844 | {"data", s_change_sec, 'd'}, | |
1845 | {"double", s_float_cons, 'd'}, | |
1846 | {"float", s_float_cons, 'f'}, | |
1847 | {"globl", s_mips_globl, 0}, | |
1848 | {"global", s_mips_globl, 0}, | |
1849 | {"hword", s_cons, 1}, | |
1850 | {"int", s_cons, 2}, | |
1851 | {"long", s_cons, 2}, | |
1852 | {"octa", s_cons, 4}, | |
1853 | {"quad", s_cons, 3}, | |
cca86cc8 | 1854 | {"section", s_change_section, 0}, |
252b5132 RH |
1855 | {"short", s_cons, 1}, |
1856 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1857 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1858 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1859 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1860 | {"text", s_change_sec, 't'}, |
1861 | {"word", s_cons, 2}, | |
add56521 | 1862 | |
add56521 | 1863 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1864 | |
43841e91 | 1865 | { NULL, NULL, 0 }, |
252b5132 RH |
1866 | }; |
1867 | ||
e972090a NC |
1868 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1869 | { | |
beae10d5 KH |
1870 | /* These pseudo-ops should be defined by the object file format. |
1871 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1872 | {"aent", s_mips_ent, 1}, |
1873 | {"bgnb", s_ignore, 0}, | |
1874 | {"end", s_mips_end, 0}, | |
1875 | {"endb", s_ignore, 0}, | |
1876 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1877 | {"file", s_mips_file, 0}, |
252b5132 RH |
1878 | {"fmask", s_mips_mask, 'F'}, |
1879 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1880 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1881 | {"mask", s_mips_mask, 'R'}, |
1882 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1883 | { NULL, NULL, 0 }, |
252b5132 RH |
1884 | }; |
1885 | ||
3ae8dd8d MR |
1886 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1887 | purpose of the `.dc.a' internal pseudo-op. */ | |
1888 | ||
1889 | int | |
1890 | mips_address_bytes (void) | |
1891 | { | |
919731af | 1892 | file_mips_check_options (); |
3ae8dd8d MR |
1893 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1894 | } | |
1895 | ||
17a2f251 | 1896 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1897 | |
1898 | void | |
17a2f251 | 1899 | mips_pop_insert (void) |
252b5132 RH |
1900 | { |
1901 | pop_insert (mips_pseudo_table); | |
1902 | if (! ECOFF_DEBUGGING) | |
1903 | pop_insert (mips_nonecoff_pseudo_table); | |
1904 | } | |
1905 | \f | |
1906 | /* Symbols labelling the current insn. */ | |
1907 | ||
e972090a NC |
1908 | struct insn_label_list |
1909 | { | |
252b5132 RH |
1910 | struct insn_label_list *next; |
1911 | symbolS *label; | |
1912 | }; | |
1913 | ||
252b5132 | 1914 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1915 | #define label_list tc_segment_info_data.labels |
252b5132 | 1916 | |
17a2f251 | 1917 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1918 | static void mips_mark_labels (void); |
1919 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1920 | |
1921 | static inline void | |
17a2f251 | 1922 | mips_clear_insn_labels (void) |
252b5132 | 1923 | { |
ed9e98c2 | 1924 | struct insn_label_list **pl; |
a8dbcb85 | 1925 | segment_info_type *si; |
252b5132 | 1926 | |
a8dbcb85 TS |
1927 | if (now_seg) |
1928 | { | |
1929 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1930 | ; | |
3739860c | 1931 | |
a8dbcb85 TS |
1932 | si = seg_info (now_seg); |
1933 | *pl = si->label_list; | |
1934 | si->label_list = NULL; | |
1935 | } | |
252b5132 | 1936 | } |
a8dbcb85 | 1937 | |
df58fc94 RS |
1938 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1939 | ||
1940 | static inline void | |
1941 | mips_mark_labels (void) | |
1942 | { | |
1943 | if (HAVE_CODE_COMPRESSION) | |
1944 | mips_compressed_mark_labels (); | |
1945 | } | |
252b5132 RH |
1946 | \f |
1947 | static char *expr_end; | |
1948 | ||
e423441d | 1949 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1950 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1951 | |
1952 | static expressionS imm_expr; | |
252b5132 | 1953 | |
77bd4346 RS |
1954 | /* The relocatable field in an instruction and the relocs associated |
1955 | with it. These variables are used for instructions like LUI and | |
1956 | JAL as well as true offsets. They are also used for address | |
1957 | operands in macros. */ | |
252b5132 | 1958 | |
77bd4346 | 1959 | static expressionS offset_expr; |
f6688943 TS |
1960 | static bfd_reloc_code_real_type offset_reloc[3] |
1961 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1962 | |
df58fc94 RS |
1963 | /* This is set to the resulting size of the instruction to be produced |
1964 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1965 | explicit size is supplied. */ | |
252b5132 | 1966 | |
df58fc94 | 1967 | static unsigned int forced_insn_length; |
252b5132 | 1968 | |
e1b47bd5 RS |
1969 | /* True if we are assembling an instruction. All dot symbols defined during |
1970 | this time should be treated as code labels. */ | |
1971 | ||
1972 | static bfd_boolean mips_assembling_insn; | |
1973 | ||
ecb4347a DJ |
1974 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1975 | ECOFF debugging. */ | |
252b5132 RH |
1976 | |
1977 | static segT pdr_seg; | |
252b5132 | 1978 | |
e013f690 TS |
1979 | /* The default target format to use. */ |
1980 | ||
aeffff67 RS |
1981 | #if defined (TE_FreeBSD) |
1982 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1983 | #elif defined (TE_TMIPS) | |
1984 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1985 | #else | |
1986 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1987 | #endif | |
1988 | ||
e013f690 | 1989 | const char * |
17a2f251 | 1990 | mips_target_format (void) |
e013f690 TS |
1991 | { |
1992 | switch (OUTPUT_FLAVOR) | |
1993 | { | |
e013f690 | 1994 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1995 | #ifdef TE_VXWORKS |
1996 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1997 | return (target_big_endian | |
1998 | ? "elf32-bigmips-vxworks" | |
1999 | : "elf32-littlemips-vxworks"); | |
2000 | #endif | |
e013f690 | 2001 | return (target_big_endian |
cfe86eaa | 2002 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2003 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2004 | : (HAVE_NEWABI |
aeffff67 RS |
2005 | ? ELF_TARGET ("elf32-n", "big") |
2006 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2007 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2008 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2009 | : (HAVE_NEWABI |
aeffff67 RS |
2010 | ? ELF_TARGET ("elf32-n", "little") |
2011 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2012 | default: |
2013 | abort (); | |
2014 | return NULL; | |
2015 | } | |
2016 | } | |
2017 | ||
c6278170 RS |
2018 | /* Return the ISA revision that is currently in use, or 0 if we are |
2019 | generating code for MIPS V or below. */ | |
2020 | ||
2021 | static int | |
2022 | mips_isa_rev (void) | |
2023 | { | |
2024 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2025 | return 2; | |
2026 | ||
ae52f483 AB |
2027 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2028 | return 3; | |
2029 | ||
2030 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2031 | return 5; | |
2032 | ||
7361da2c AB |
2033 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2034 | return 6; | |
2035 | ||
c6278170 RS |
2036 | /* microMIPS implies revision 2 or above. */ |
2037 | if (mips_opts.micromips) | |
2038 | return 2; | |
2039 | ||
2040 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2041 | return 1; | |
2042 | ||
2043 | return 0; | |
2044 | } | |
2045 | ||
2046 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2047 | ||
2048 | static unsigned int | |
2049 | mips_ase_mask (unsigned int flags) | |
2050 | { | |
2051 | unsigned int i; | |
2052 | ||
2053 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2054 | if (flags & mips_ase_groups[i]) | |
2055 | flags |= mips_ase_groups[i]; | |
2056 | return flags; | |
2057 | } | |
2058 | ||
2059 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2060 | appropriate. */ | |
2061 | ||
2062 | static void | |
2063 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2064 | { | |
2065 | const char *base; | |
2066 | int min_rev, size; | |
2067 | static unsigned int warned_isa; | |
2068 | static unsigned int warned_fp32; | |
2069 | ||
2070 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2071 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2072 | else | |
2073 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2074 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2075 | && (warned_isa & ase->flags) != ase->flags) | |
2076 | { | |
2077 | warned_isa |= ase->flags; | |
2078 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2079 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2080 | if (min_rev < 0) | |
1661c76c | 2081 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2082 | " `%s' extension"), size, base, ase->name); |
2083 | else | |
1661c76c | 2084 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2085 | ase->name, base, size, min_rev); |
2086 | } | |
7361da2c AB |
2087 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2088 | && (warned_isa & ase->flags) != ase->flags) | |
2089 | { | |
2090 | warned_isa |= ase->flags; | |
2091 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2092 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2093 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2094 | ase->name, base, size, ase->rem_rev); | |
2095 | } | |
2096 | ||
c6278170 | 2097 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2098 | && mips_opts.fp != 64 |
c6278170 RS |
2099 | && (warned_fp32 & ase->flags) != ase->flags) |
2100 | { | |
2101 | warned_fp32 |= ase->flags; | |
1661c76c | 2102 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2103 | } |
2104 | } | |
2105 | ||
2106 | /* Check all enabled ASEs to see whether they are supported by the | |
2107 | chosen architecture. */ | |
2108 | ||
2109 | static void | |
2110 | mips_check_isa_supports_ases (void) | |
2111 | { | |
2112 | unsigned int i, mask; | |
2113 | ||
2114 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2115 | { | |
2116 | mask = mips_ase_mask (mips_ases[i].flags); | |
2117 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2118 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2119 | } | |
2120 | } | |
2121 | ||
2122 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2123 | that were affected. */ | |
2124 | ||
2125 | static unsigned int | |
919731af | 2126 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2127 | bfd_boolean enabled_p) | |
c6278170 RS |
2128 | { |
2129 | unsigned int mask; | |
2130 | ||
2131 | mask = mips_ase_mask (ase->flags); | |
919731af | 2132 | opts->ase &= ~mask; |
c6278170 | 2133 | if (enabled_p) |
919731af | 2134 | opts->ase |= ase->flags; |
25499ac7 MR |
2135 | |
2136 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) | |
2137 | { | |
2138 | opts->ase |= ASE_MIPS16E2_MT; | |
2139 | mask |= ASE_MIPS16E2_MT; | |
2140 | } | |
2141 | ||
c6278170 RS |
2142 | return mask; |
2143 | } | |
2144 | ||
2145 | /* Return the ASE called NAME, or null if none. */ | |
2146 | ||
2147 | static const struct mips_ase * | |
2148 | mips_lookup_ase (const char *name) | |
2149 | { | |
2150 | unsigned int i; | |
2151 | ||
2152 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2153 | if (strcmp (name, mips_ases[i].name) == 0) | |
2154 | return &mips_ases[i]; | |
2155 | return NULL; | |
2156 | } | |
2157 | ||
df58fc94 | 2158 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2159 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2160 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2161 | |
2162 | static inline unsigned int | |
2163 | micromips_insn_length (const struct mips_opcode *mo) | |
2164 | { | |
7fd53920 | 2165 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2166 | } |
2167 | ||
5c04167a RS |
2168 | /* Return the length of MIPS16 instruction OPCODE. */ |
2169 | ||
2170 | static inline unsigned int | |
2171 | mips16_opcode_length (unsigned long opcode) | |
2172 | { | |
2173 | return (opcode >> 16) == 0 ? 2 : 4; | |
2174 | } | |
2175 | ||
1e915849 RS |
2176 | /* Return the length of instruction INSN. */ |
2177 | ||
2178 | static inline unsigned int | |
2179 | insn_length (const struct mips_cl_insn *insn) | |
2180 | { | |
df58fc94 RS |
2181 | if (mips_opts.micromips) |
2182 | return micromips_insn_length (insn->insn_mo); | |
2183 | else if (mips_opts.mips16) | |
5c04167a | 2184 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2185 | else |
1e915849 | 2186 | return 4; |
1e915849 RS |
2187 | } |
2188 | ||
2189 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2190 | ||
2191 | static void | |
2192 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2193 | { | |
2194 | size_t i; | |
2195 | ||
2196 | insn->insn_mo = mo; | |
1e915849 RS |
2197 | insn->insn_opcode = mo->match; |
2198 | insn->frag = NULL; | |
2199 | insn->where = 0; | |
2200 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2201 | insn->fixp[i] = NULL; | |
2202 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2203 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2204 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2205 | insn->complete_p = 0; |
e407c74b | 2206 | insn->cleared_p = 0; |
1e915849 RS |
2207 | } |
2208 | ||
fc76e730 RS |
2209 | /* Get a list of all the operands in INSN. */ |
2210 | ||
2211 | static const struct mips_operand_array * | |
2212 | insn_operands (const struct mips_cl_insn *insn) | |
2213 | { | |
2214 | if (insn->insn_mo >= &mips_opcodes[0] | |
2215 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2216 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2217 | ||
2218 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2219 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2220 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2221 | ||
2222 | if (insn->insn_mo >= µmips_opcodes[0] | |
2223 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2224 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2225 | ||
2226 | abort (); | |
2227 | } | |
2228 | ||
2229 | /* Get a description of operand OPNO of INSN. */ | |
2230 | ||
2231 | static const struct mips_operand * | |
2232 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2233 | { | |
2234 | const struct mips_operand_array *operands; | |
2235 | ||
2236 | operands = insn_operands (insn); | |
2237 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2238 | abort (); | |
2239 | return operands->operand[opno]; | |
2240 | } | |
2241 | ||
e077a1c8 RS |
2242 | /* Install UVAL as the value of OPERAND in INSN. */ |
2243 | ||
2244 | static inline void | |
2245 | insn_insert_operand (struct mips_cl_insn *insn, | |
2246 | const struct mips_operand *operand, unsigned int uval) | |
2247 | { | |
25499ac7 MR |
2248 | if (mips_opts.mips16 |
2249 | && operand->type == OP_INT && operand->lsb == 0 | |
2250 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2251 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2252 | else | |
2253 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2254 | } |
2255 | ||
fc76e730 RS |
2256 | /* Extract the value of OPERAND from INSN. */ |
2257 | ||
2258 | static inline unsigned | |
2259 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2260 | const struct mips_operand *operand) | |
2261 | { | |
2262 | return mips_extract_operand (operand, insn->insn_opcode); | |
2263 | } | |
2264 | ||
df58fc94 | 2265 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2266 | |
2267 | static void | |
df58fc94 | 2268 | mips_record_compressed_mode (void) |
742a56fe RS |
2269 | { |
2270 | segment_info_type *si; | |
2271 | ||
2272 | si = seg_info (now_seg); | |
2273 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2274 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2275 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2276 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2277 | } |
2278 | ||
4d68580a RS |
2279 | /* Read a standard MIPS instruction from BUF. */ |
2280 | ||
2281 | static unsigned long | |
2282 | read_insn (char *buf) | |
2283 | { | |
2284 | if (target_big_endian) | |
2285 | return bfd_getb32 ((bfd_byte *) buf); | |
2286 | else | |
2287 | return bfd_getl32 ((bfd_byte *) buf); | |
2288 | } | |
2289 | ||
2290 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2291 | the next byte. */ | |
2292 | ||
2293 | static char * | |
2294 | write_insn (char *buf, unsigned int insn) | |
2295 | { | |
2296 | md_number_to_chars (buf, insn, 4); | |
2297 | return buf + 4; | |
2298 | } | |
2299 | ||
2300 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2301 | has length LENGTH. */ | |
2302 | ||
2303 | static unsigned long | |
2304 | read_compressed_insn (char *buf, unsigned int length) | |
2305 | { | |
2306 | unsigned long insn; | |
2307 | unsigned int i; | |
2308 | ||
2309 | insn = 0; | |
2310 | for (i = 0; i < length; i += 2) | |
2311 | { | |
2312 | insn <<= 16; | |
2313 | if (target_big_endian) | |
2314 | insn |= bfd_getb16 ((char *) buf); | |
2315 | else | |
2316 | insn |= bfd_getl16 ((char *) buf); | |
2317 | buf += 2; | |
2318 | } | |
2319 | return insn; | |
2320 | } | |
2321 | ||
5c04167a RS |
2322 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2323 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2324 | ||
2325 | static char * | |
2326 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2327 | { | |
2328 | unsigned int i; | |
2329 | ||
2330 | for (i = 0; i < length; i += 2) | |
2331 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2332 | return buf + length; | |
2333 | } | |
2334 | ||
1e915849 RS |
2335 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2336 | ||
2337 | static void | |
2338 | install_insn (const struct mips_cl_insn *insn) | |
2339 | { | |
2340 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2341 | if (HAVE_CODE_COMPRESSION) |
2342 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2343 | else |
4d68580a | 2344 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2345 | mips_record_compressed_mode (); |
1e915849 RS |
2346 | } |
2347 | ||
2348 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2349 | and install the opcode in the new location. */ | |
2350 | ||
2351 | static void | |
2352 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2353 | { | |
2354 | size_t i; | |
2355 | ||
2356 | insn->frag = frag; | |
2357 | insn->where = where; | |
2358 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2359 | if (insn->fixp[i] != NULL) | |
2360 | { | |
2361 | insn->fixp[i]->fx_frag = frag; | |
2362 | insn->fixp[i]->fx_where = where; | |
2363 | } | |
2364 | install_insn (insn); | |
2365 | } | |
2366 | ||
2367 | /* Add INSN to the end of the output. */ | |
2368 | ||
2369 | static void | |
2370 | add_fixed_insn (struct mips_cl_insn *insn) | |
2371 | { | |
2372 | char *f = frag_more (insn_length (insn)); | |
2373 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2374 | } | |
2375 | ||
2376 | /* Start a variant frag and move INSN to the start of the variant part, | |
2377 | marking it as fixed. The other arguments are as for frag_var. */ | |
2378 | ||
2379 | static void | |
2380 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2381 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2382 | { | |
2383 | frag_grow (max_chars); | |
2384 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2385 | insn->fixed_p = 1; | |
2386 | frag_var (rs_machine_dependent, max_chars, var, | |
2387 | subtype, symbol, offset, NULL); | |
2388 | } | |
2389 | ||
2390 | /* Insert N copies of INSN into the history buffer, starting at | |
2391 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2392 | ||
2393 | static void | |
2394 | insert_into_history (unsigned int first, unsigned int n, | |
2395 | const struct mips_cl_insn *insn) | |
2396 | { | |
2397 | if (mips_relax.sequence != 2) | |
2398 | { | |
2399 | unsigned int i; | |
2400 | ||
2401 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2402 | if (i >= first + n) | |
2403 | history[i] = history[i - n]; | |
2404 | else | |
2405 | history[i] = *insn; | |
2406 | } | |
2407 | } | |
2408 | ||
e3de51ce RS |
2409 | /* Clear the error in insn_error. */ |
2410 | ||
2411 | static void | |
2412 | clear_insn_error (void) | |
2413 | { | |
2414 | memset (&insn_error, 0, sizeof (insn_error)); | |
2415 | } | |
2416 | ||
2417 | /* Possibly record error message MSG for the current instruction. | |
2418 | If the error is about a particular argument, ARGNUM is the 1-based | |
2419 | number of that argument, otherwise it is 0. FORMAT is the format | |
2420 | of MSG. Return true if MSG was used, false if the current message | |
2421 | was kept. */ | |
2422 | ||
2423 | static bfd_boolean | |
2424 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2425 | const char *msg) | |
2426 | { | |
2427 | if (argnum == 0) | |
2428 | { | |
2429 | /* Give priority to errors against specific arguments, and to | |
2430 | the first whole-instruction message. */ | |
2431 | if (insn_error.msg) | |
2432 | return FALSE; | |
2433 | } | |
2434 | else | |
2435 | { | |
2436 | /* Keep insn_error if it is against a later argument. */ | |
2437 | if (argnum < insn_error.min_argnum) | |
2438 | return FALSE; | |
2439 | ||
2440 | /* If both errors are against the same argument but are different, | |
2441 | give up on reporting a specific error for this argument. | |
2442 | See the comment about mips_insn_error for details. */ | |
2443 | if (argnum == insn_error.min_argnum | |
2444 | && insn_error.msg | |
2445 | && strcmp (insn_error.msg, msg) != 0) | |
2446 | { | |
2447 | insn_error.msg = 0; | |
2448 | insn_error.min_argnum += 1; | |
2449 | return FALSE; | |
2450 | } | |
2451 | } | |
2452 | insn_error.min_argnum = argnum; | |
2453 | insn_error.format = format; | |
2454 | insn_error.msg = msg; | |
2455 | return TRUE; | |
2456 | } | |
2457 | ||
2458 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2459 | as for set_insn_error_format. */ | |
2460 | ||
2461 | static void | |
2462 | set_insn_error (int argnum, const char *msg) | |
2463 | { | |
2464 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2465 | } | |
2466 | ||
2467 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2468 | as for set_insn_error_format. */ | |
2469 | ||
2470 | static void | |
2471 | set_insn_error_i (int argnum, const char *msg, int i) | |
2472 | { | |
2473 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2474 | insn_error.u.i = i; | |
2475 | } | |
2476 | ||
2477 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2478 | are as for set_insn_error_format. */ | |
2479 | ||
2480 | static void | |
2481 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2482 | { | |
2483 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2484 | { | |
2485 | insn_error.u.ss[0] = s1; | |
2486 | insn_error.u.ss[1] = s2; | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2491 | ||
2492 | static void | |
2493 | report_insn_error (const char *str) | |
2494 | { | |
e1fa0163 | 2495 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2496 | |
e3de51ce RS |
2497 | switch (insn_error.format) |
2498 | { | |
2499 | case ERR_FMT_PLAIN: | |
2500 | as_bad (msg, str); | |
2501 | break; | |
2502 | ||
2503 | case ERR_FMT_I: | |
2504 | as_bad (msg, insn_error.u.i, str); | |
2505 | break; | |
2506 | ||
2507 | case ERR_FMT_SS: | |
2508 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2509 | break; | |
2510 | } | |
e1fa0163 NC |
2511 | |
2512 | free ((char *) msg); | |
e3de51ce RS |
2513 | } |
2514 | ||
71400594 RS |
2515 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2516 | the idea is to make it obvious at a glance that each errata is | |
2517 | included. */ | |
2518 | ||
2519 | static void | |
2520 | init_vr4120_conflicts (void) | |
2521 | { | |
2522 | #define CONFLICT(FIRST, SECOND) \ | |
2523 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2524 | ||
2525 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2526 | CONFLICT (MACC, DIV); | |
2527 | CONFLICT (DMACC, DIV); | |
2528 | ||
2529 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2530 | CONFLICT (DMULT, DMULT); | |
2531 | CONFLICT (DMULT, DMACC); | |
2532 | CONFLICT (DMACC, DMULT); | |
2533 | CONFLICT (DMACC, DMACC); | |
2534 | ||
2535 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2536 | CONFLICT (MACC, MTHILO); | |
2537 | CONFLICT (DMACC, MTHILO); | |
2538 | ||
2539 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2540 | instruction is executed immediately after a MACC or DMACC | |
2541 | instruction, the result of [either instruction] is incorrect." */ | |
2542 | CONFLICT (MACC, MULT); | |
2543 | CONFLICT (MACC, DMULT); | |
2544 | CONFLICT (DMACC, MULT); | |
2545 | CONFLICT (DMACC, DMULT); | |
2546 | ||
2547 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2548 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2549 | DDIV or DDIVU instruction, the result of the MACC or | |
2550 | DMACC instruction is incorrect.". */ | |
2551 | CONFLICT (DMULT, MACC); | |
2552 | CONFLICT (DMULT, DMACC); | |
2553 | CONFLICT (DIV, MACC); | |
2554 | CONFLICT (DIV, DMACC); | |
2555 | ||
2556 | #undef CONFLICT | |
2557 | } | |
2558 | ||
707bfff6 TS |
2559 | struct regname { |
2560 | const char *name; | |
2561 | unsigned int num; | |
2562 | }; | |
2563 | ||
14daeee3 | 2564 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2565 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2566 | #define RTYPE_NUM 0x0000100 |
2567 | #define RTYPE_FPU 0x0000200 | |
2568 | #define RTYPE_FCC 0x0000400 | |
2569 | #define RTYPE_VEC 0x0000800 | |
2570 | #define RTYPE_GP 0x0001000 | |
2571 | #define RTYPE_CP0 0x0002000 | |
2572 | #define RTYPE_PC 0x0004000 | |
2573 | #define RTYPE_ACC 0x0008000 | |
2574 | #define RTYPE_CCC 0x0010000 | |
2575 | #define RTYPE_VI 0x0020000 | |
2576 | #define RTYPE_VF 0x0040000 | |
2577 | #define RTYPE_R5900_I 0x0080000 | |
2578 | #define RTYPE_R5900_Q 0x0100000 | |
2579 | #define RTYPE_R5900_R 0x0200000 | |
2580 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2581 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2582 | #define RWARN 0x8000000 |
707bfff6 TS |
2583 | |
2584 | #define GENERIC_REGISTER_NUMBERS \ | |
2585 | {"$0", RTYPE_NUM | 0}, \ | |
2586 | {"$1", RTYPE_NUM | 1}, \ | |
2587 | {"$2", RTYPE_NUM | 2}, \ | |
2588 | {"$3", RTYPE_NUM | 3}, \ | |
2589 | {"$4", RTYPE_NUM | 4}, \ | |
2590 | {"$5", RTYPE_NUM | 5}, \ | |
2591 | {"$6", RTYPE_NUM | 6}, \ | |
2592 | {"$7", RTYPE_NUM | 7}, \ | |
2593 | {"$8", RTYPE_NUM | 8}, \ | |
2594 | {"$9", RTYPE_NUM | 9}, \ | |
2595 | {"$10", RTYPE_NUM | 10}, \ | |
2596 | {"$11", RTYPE_NUM | 11}, \ | |
2597 | {"$12", RTYPE_NUM | 12}, \ | |
2598 | {"$13", RTYPE_NUM | 13}, \ | |
2599 | {"$14", RTYPE_NUM | 14}, \ | |
2600 | {"$15", RTYPE_NUM | 15}, \ | |
2601 | {"$16", RTYPE_NUM | 16}, \ | |
2602 | {"$17", RTYPE_NUM | 17}, \ | |
2603 | {"$18", RTYPE_NUM | 18}, \ | |
2604 | {"$19", RTYPE_NUM | 19}, \ | |
2605 | {"$20", RTYPE_NUM | 20}, \ | |
2606 | {"$21", RTYPE_NUM | 21}, \ | |
2607 | {"$22", RTYPE_NUM | 22}, \ | |
2608 | {"$23", RTYPE_NUM | 23}, \ | |
2609 | {"$24", RTYPE_NUM | 24}, \ | |
2610 | {"$25", RTYPE_NUM | 25}, \ | |
2611 | {"$26", RTYPE_NUM | 26}, \ | |
2612 | {"$27", RTYPE_NUM | 27}, \ | |
2613 | {"$28", RTYPE_NUM | 28}, \ | |
2614 | {"$29", RTYPE_NUM | 29}, \ | |
2615 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2616 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2617 | |
2618 | #define FPU_REGISTER_NAMES \ | |
2619 | {"$f0", RTYPE_FPU | 0}, \ | |
2620 | {"$f1", RTYPE_FPU | 1}, \ | |
2621 | {"$f2", RTYPE_FPU | 2}, \ | |
2622 | {"$f3", RTYPE_FPU | 3}, \ | |
2623 | {"$f4", RTYPE_FPU | 4}, \ | |
2624 | {"$f5", RTYPE_FPU | 5}, \ | |
2625 | {"$f6", RTYPE_FPU | 6}, \ | |
2626 | {"$f7", RTYPE_FPU | 7}, \ | |
2627 | {"$f8", RTYPE_FPU | 8}, \ | |
2628 | {"$f9", RTYPE_FPU | 9}, \ | |
2629 | {"$f10", RTYPE_FPU | 10}, \ | |
2630 | {"$f11", RTYPE_FPU | 11}, \ | |
2631 | {"$f12", RTYPE_FPU | 12}, \ | |
2632 | {"$f13", RTYPE_FPU | 13}, \ | |
2633 | {"$f14", RTYPE_FPU | 14}, \ | |
2634 | {"$f15", RTYPE_FPU | 15}, \ | |
2635 | {"$f16", RTYPE_FPU | 16}, \ | |
2636 | {"$f17", RTYPE_FPU | 17}, \ | |
2637 | {"$f18", RTYPE_FPU | 18}, \ | |
2638 | {"$f19", RTYPE_FPU | 19}, \ | |
2639 | {"$f20", RTYPE_FPU | 20}, \ | |
2640 | {"$f21", RTYPE_FPU | 21}, \ | |
2641 | {"$f22", RTYPE_FPU | 22}, \ | |
2642 | {"$f23", RTYPE_FPU | 23}, \ | |
2643 | {"$f24", RTYPE_FPU | 24}, \ | |
2644 | {"$f25", RTYPE_FPU | 25}, \ | |
2645 | {"$f26", RTYPE_FPU | 26}, \ | |
2646 | {"$f27", RTYPE_FPU | 27}, \ | |
2647 | {"$f28", RTYPE_FPU | 28}, \ | |
2648 | {"$f29", RTYPE_FPU | 29}, \ | |
2649 | {"$f30", RTYPE_FPU | 30}, \ | |
2650 | {"$f31", RTYPE_FPU | 31} | |
2651 | ||
2652 | #define FPU_CONDITION_CODE_NAMES \ | |
2653 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2654 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2655 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2656 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2657 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2658 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2659 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2660 | {"$fcc7", RTYPE_FCC | 7} | |
2661 | ||
2662 | #define COPROC_CONDITION_CODE_NAMES \ | |
2663 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2664 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2665 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2666 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2667 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2668 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2669 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2670 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2671 | ||
2672 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2673 | {"$a4", RTYPE_GP | 8}, \ | |
2674 | {"$a5", RTYPE_GP | 9}, \ | |
2675 | {"$a6", RTYPE_GP | 10}, \ | |
2676 | {"$a7", RTYPE_GP | 11}, \ | |
2677 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2678 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2679 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2680 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2681 | {"$t0", RTYPE_GP | 12}, \ | |
2682 | {"$t1", RTYPE_GP | 13}, \ | |
2683 | {"$t2", RTYPE_GP | 14}, \ | |
2684 | {"$t3", RTYPE_GP | 15} | |
2685 | ||
2686 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2687 | {"$t0", RTYPE_GP | 8}, \ | |
2688 | {"$t1", RTYPE_GP | 9}, \ | |
2689 | {"$t2", RTYPE_GP | 10}, \ | |
2690 | {"$t3", RTYPE_GP | 11}, \ | |
2691 | {"$t4", RTYPE_GP | 12}, \ | |
2692 | {"$t5", RTYPE_GP | 13}, \ | |
2693 | {"$t6", RTYPE_GP | 14}, \ | |
2694 | {"$t7", RTYPE_GP | 15}, \ | |
2695 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2696 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2697 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2698 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2699 | |
2700 | /* Remaining symbolic register names */ | |
2701 | #define SYMBOLIC_REGISTER_NAMES \ | |
2702 | {"$zero", RTYPE_GP | 0}, \ | |
2703 | {"$at", RTYPE_GP | 1}, \ | |
2704 | {"$AT", RTYPE_GP | 1}, \ | |
2705 | {"$v0", RTYPE_GP | 2}, \ | |
2706 | {"$v1", RTYPE_GP | 3}, \ | |
2707 | {"$a0", RTYPE_GP | 4}, \ | |
2708 | {"$a1", RTYPE_GP | 5}, \ | |
2709 | {"$a2", RTYPE_GP | 6}, \ | |
2710 | {"$a3", RTYPE_GP | 7}, \ | |
2711 | {"$s0", RTYPE_GP | 16}, \ | |
2712 | {"$s1", RTYPE_GP | 17}, \ | |
2713 | {"$s2", RTYPE_GP | 18}, \ | |
2714 | {"$s3", RTYPE_GP | 19}, \ | |
2715 | {"$s4", RTYPE_GP | 20}, \ | |
2716 | {"$s5", RTYPE_GP | 21}, \ | |
2717 | {"$s6", RTYPE_GP | 22}, \ | |
2718 | {"$s7", RTYPE_GP | 23}, \ | |
2719 | {"$t8", RTYPE_GP | 24}, \ | |
2720 | {"$t9", RTYPE_GP | 25}, \ | |
2721 | {"$k0", RTYPE_GP | 26}, \ | |
2722 | {"$kt0", RTYPE_GP | 26}, \ | |
2723 | {"$k1", RTYPE_GP | 27}, \ | |
2724 | {"$kt1", RTYPE_GP | 27}, \ | |
2725 | {"$gp", RTYPE_GP | 28}, \ | |
2726 | {"$sp", RTYPE_GP | 29}, \ | |
2727 | {"$s8", RTYPE_GP | 30}, \ | |
2728 | {"$fp", RTYPE_GP | 30}, \ | |
2729 | {"$ra", RTYPE_GP | 31} | |
2730 | ||
2731 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2732 | {"$pc", RTYPE_PC | 0} | |
2733 | ||
2734 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2735 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2736 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2737 | {"$v2", RTYPE_VEC | 2}, \ | |
2738 | {"$v3", RTYPE_VEC | 3}, \ | |
2739 | {"$v4", RTYPE_VEC | 4}, \ | |
2740 | {"$v5", RTYPE_VEC | 5}, \ | |
2741 | {"$v6", RTYPE_VEC | 6}, \ | |
2742 | {"$v7", RTYPE_VEC | 7}, \ | |
2743 | {"$v8", RTYPE_VEC | 8}, \ | |
2744 | {"$v9", RTYPE_VEC | 9}, \ | |
2745 | {"$v10", RTYPE_VEC | 10}, \ | |
2746 | {"$v11", RTYPE_VEC | 11}, \ | |
2747 | {"$v12", RTYPE_VEC | 12}, \ | |
2748 | {"$v13", RTYPE_VEC | 13}, \ | |
2749 | {"$v14", RTYPE_VEC | 14}, \ | |
2750 | {"$v15", RTYPE_VEC | 15}, \ | |
2751 | {"$v16", RTYPE_VEC | 16}, \ | |
2752 | {"$v17", RTYPE_VEC | 17}, \ | |
2753 | {"$v18", RTYPE_VEC | 18}, \ | |
2754 | {"$v19", RTYPE_VEC | 19}, \ | |
2755 | {"$v20", RTYPE_VEC | 20}, \ | |
2756 | {"$v21", RTYPE_VEC | 21}, \ | |
2757 | {"$v22", RTYPE_VEC | 22}, \ | |
2758 | {"$v23", RTYPE_VEC | 23}, \ | |
2759 | {"$v24", RTYPE_VEC | 24}, \ | |
2760 | {"$v25", RTYPE_VEC | 25}, \ | |
2761 | {"$v26", RTYPE_VEC | 26}, \ | |
2762 | {"$v27", RTYPE_VEC | 27}, \ | |
2763 | {"$v28", RTYPE_VEC | 28}, \ | |
2764 | {"$v29", RTYPE_VEC | 29}, \ | |
2765 | {"$v30", RTYPE_VEC | 30}, \ | |
2766 | {"$v31", RTYPE_VEC | 31} | |
2767 | ||
14daeee3 RS |
2768 | #define R5900_I_NAMES \ |
2769 | {"$I", RTYPE_R5900_I | 0} | |
2770 | ||
2771 | #define R5900_Q_NAMES \ | |
2772 | {"$Q", RTYPE_R5900_Q | 0} | |
2773 | ||
2774 | #define R5900_R_NAMES \ | |
2775 | {"$R", RTYPE_R5900_R | 0} | |
2776 | ||
2777 | #define R5900_ACC_NAMES \ | |
2778 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2779 | ||
707bfff6 TS |
2780 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2781 | {"$ac0", RTYPE_ACC | 0}, \ | |
2782 | {"$ac1", RTYPE_ACC | 1}, \ | |
2783 | {"$ac2", RTYPE_ACC | 2}, \ | |
2784 | {"$ac3", RTYPE_ACC | 3} | |
2785 | ||
2786 | static const struct regname reg_names[] = { | |
2787 | GENERIC_REGISTER_NUMBERS, | |
2788 | FPU_REGISTER_NAMES, | |
2789 | FPU_CONDITION_CODE_NAMES, | |
2790 | COPROC_CONDITION_CODE_NAMES, | |
2791 | ||
2792 | /* The $txx registers depends on the abi, | |
2793 | these will be added later into the symbol table from | |
3739860c | 2794 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2795 | parsing of arguments from the command line. */ |
2796 | SYMBOLIC_REGISTER_NAMES, | |
2797 | ||
2798 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2799 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2800 | R5900_I_NAMES, |
2801 | R5900_Q_NAMES, | |
2802 | R5900_R_NAMES, | |
2803 | R5900_ACC_NAMES, | |
707bfff6 TS |
2804 | MIPS_DSP_ACCUMULATOR_NAMES, |
2805 | {0, 0} | |
2806 | }; | |
2807 | ||
2808 | static const struct regname reg_names_o32[] = { | |
2809 | O32_SYMBOLIC_REGISTER_NAMES, | |
2810 | {0, 0} | |
2811 | }; | |
2812 | ||
2813 | static const struct regname reg_names_n32n64[] = { | |
2814 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2815 | {0, 0} | |
2816 | }; | |
2817 | ||
a92713e6 RS |
2818 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2819 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2820 | of these register symbols, return the associated vector register, | |
2821 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2822 | |
a92713e6 RS |
2823 | static unsigned int |
2824 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2825 | { |
a92713e6 RS |
2826 | if ((symval & -2) == (RTYPE_GP | 2)) |
2827 | return RTYPE_VEC | (symval & 1); | |
2828 | return symval; | |
2829 | } | |
2830 | ||
14daeee3 RS |
2831 | /* Return true if string [S, E) is a valid register name, storing its |
2832 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2833 | |
2834 | static bfd_boolean | |
14daeee3 | 2835 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2836 | { |
707bfff6 | 2837 | char save_c; |
14daeee3 | 2838 | symbolS *symbol; |
707bfff6 TS |
2839 | |
2840 | /* Terminate name. */ | |
2841 | save_c = *e; | |
2842 | *e = '\0'; | |
2843 | ||
a92713e6 RS |
2844 | /* Look up the name. */ |
2845 | symbol = symbol_find (s); | |
2846 | *e = save_c; | |
2847 | ||
2848 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2849 | return FALSE; | |
2850 | ||
14daeee3 RS |
2851 | *symval_ptr = S_GET_VALUE (symbol); |
2852 | return TRUE; | |
2853 | } | |
2854 | ||
2855 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2856 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2857 | is nonnull. | |
2858 | ||
2859 | When returning true, move *SPTR past the register, store the | |
2860 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2861 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2862 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2863 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2864 | ||
2865 | static bfd_boolean | |
2866 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2867 | unsigned int *channels_ptr) | |
2868 | { | |
2869 | char *s, *e, *m; | |
2870 | const char *q; | |
2871 | unsigned int channels, symval, bit; | |
2872 | ||
2873 | /* Find end of name. */ | |
2874 | s = e = *sptr; | |
2875 | if (is_name_beginner (*e)) | |
2876 | ++e; | |
2877 | while (is_part_of_name (*e)) | |
2878 | ++e; | |
2879 | ||
2880 | channels = 0; | |
2881 | if (!mips_parse_register_1 (s, e, &symval)) | |
2882 | { | |
2883 | if (!channels_ptr) | |
2884 | return FALSE; | |
2885 | ||
2886 | /* Eat characters from the end of the string that are valid | |
2887 | channel suffixes. The preceding register must be $ACC or | |
2888 | end with a digit, so there is no ambiguity. */ | |
2889 | bit = 1; | |
2890 | m = e; | |
2891 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2892 | if (m > s && m[-1] == *q) | |
2893 | { | |
2894 | --m; | |
2895 | channels |= bit; | |
2896 | } | |
2897 | ||
2898 | if (channels == 0 | |
2899 | || !mips_parse_register_1 (s, m, &symval) | |
2900 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2901 | return FALSE; | |
2902 | } | |
2903 | ||
a92713e6 | 2904 | *sptr = e; |
14daeee3 RS |
2905 | *symval_ptr = symval; |
2906 | if (channels_ptr) | |
2907 | *channels_ptr = channels; | |
a92713e6 RS |
2908 | return TRUE; |
2909 | } | |
2910 | ||
2911 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2912 | If so, then return 1, advance S to consume the specifier and store | |
2913 | the register's number in REGNOP, otherwise return 0. */ | |
2914 | ||
2915 | static int | |
2916 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2917 | { | |
2918 | unsigned int regno; | |
2919 | ||
14daeee3 | 2920 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2921 | { |
a92713e6 RS |
2922 | if (types & RTYPE_VEC) |
2923 | regno = mips_prefer_vec_regno (regno); | |
2924 | if (regno & types) | |
2925 | regno &= RNUM_MASK; | |
2926 | else | |
2927 | regno = ~0; | |
707bfff6 | 2928 | } |
a92713e6 | 2929 | else |
707bfff6 | 2930 | { |
a92713e6 | 2931 | if (types & RWARN) |
1661c76c | 2932 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2933 | regno = ~0; |
707bfff6 | 2934 | } |
707bfff6 | 2935 | if (regnop) |
a92713e6 RS |
2936 | *regnop = regno; |
2937 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2938 | } |
2939 | ||
14daeee3 RS |
2940 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2941 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2942 | ||
2943 | static char * | |
2944 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2945 | { | |
2946 | unsigned int i; | |
2947 | ||
2948 | *channels = 0; | |
2949 | for (i = 0; i < 4; i++) | |
2950 | if (*s == "xyzw"[i]) | |
2951 | { | |
2952 | *channels |= 1 << (3 - i); | |
2953 | ++s; | |
2954 | } | |
2955 | return s; | |
2956 | } | |
2957 | ||
a92713e6 RS |
2958 | /* Token types for parsed operand lists. */ |
2959 | enum mips_operand_token_type { | |
2960 | /* A plain register, e.g. $f2. */ | |
2961 | OT_REG, | |
df58fc94 | 2962 | |
14daeee3 RS |
2963 | /* A 4-bit XYZW channel mask. */ |
2964 | OT_CHANNELS, | |
2965 | ||
56d438b1 CF |
2966 | /* A constant vector index, e.g. [1]. */ |
2967 | OT_INTEGER_INDEX, | |
2968 | ||
2969 | /* A register vector index, e.g. [$2]. */ | |
2970 | OT_REG_INDEX, | |
df58fc94 | 2971 | |
a92713e6 RS |
2972 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2973 | OT_REG_RANGE, | |
2974 | ||
2975 | /* A (possibly relocated) expression. */ | |
2976 | OT_INTEGER, | |
2977 | ||
2978 | /* A floating-point value. */ | |
2979 | OT_FLOAT, | |
2980 | ||
2981 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
2982 | before OT_REGs. */ | |
2983 | OT_CHAR, | |
2984 | ||
14daeee3 RS |
2985 | /* A doubled character, either "--" or "++". */ |
2986 | OT_DOUBLE_CHAR, | |
2987 | ||
a92713e6 RS |
2988 | /* The end of the operand list. */ |
2989 | OT_END | |
2990 | }; | |
2991 | ||
2992 | /* A parsed operand token. */ | |
2993 | struct mips_operand_token | |
2994 | { | |
2995 | /* The type of token. */ | |
2996 | enum mips_operand_token_type type; | |
2997 | union | |
2998 | { | |
56d438b1 | 2999 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3000 | unsigned int regno; |
3001 | ||
14daeee3 RS |
3002 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3003 | unsigned int channels; | |
3004 | ||
56d438b1 CF |
3005 | /* The integer value of an OT_INTEGER_INDEX. */ |
3006 | addressT index; | |
a92713e6 RS |
3007 | |
3008 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3009 | struct { | |
3010 | unsigned int regno1; | |
3011 | unsigned int regno2; | |
3012 | } reg_range; | |
3013 | ||
3014 | /* The value of an OT_INTEGER. The value is represented as an | |
3015 | expression and the relocation operators that were applied to | |
3016 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3017 | relocation operators were used. */ | |
3018 | struct { | |
3019 | expressionS value; | |
3020 | bfd_reloc_code_real_type relocs[3]; | |
3021 | } integer; | |
3022 | ||
3023 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3024 | in the constant. */ | |
3025 | struct { | |
3026 | unsigned char data[8]; | |
3027 | int length; | |
3028 | } flt; | |
3029 | ||
14daeee3 | 3030 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3031 | char ch; |
3032 | } u; | |
3033 | }; | |
3034 | ||
3035 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3036 | static struct obstack mips_operand_tokens; | |
3037 | ||
3038 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3039 | ||
3040 | static void | |
3041 | mips_add_token (struct mips_operand_token *token, | |
3042 | enum mips_operand_token_type type) | |
3043 | { | |
3044 | token->type = type; | |
3045 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3046 | } | |
3047 | ||
3048 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3049 | and OT_REG tokens for them if so, and return a pointer to the first | |
3050 | unconsumed character. Return null otherwise. */ | |
3051 | ||
3052 | static char * | |
3053 | mips_parse_base_start (char *s) | |
3054 | { | |
3055 | struct mips_operand_token token; | |
14daeee3 RS |
3056 | unsigned int regno, channels; |
3057 | bfd_boolean decrement_p; | |
df58fc94 | 3058 | |
a92713e6 RS |
3059 | if (*s != '(') |
3060 | return 0; | |
3061 | ||
3062 | ++s; | |
3063 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3064 | |
3065 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3066 | is a double negative. */ | |
3067 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3068 | if (decrement_p) | |
3069 | { | |
3070 | s += 2; | |
3071 | SKIP_SPACE_TABS (s); | |
3072 | } | |
3073 | ||
3074 | /* Allow a channel specifier because that leads to better error messages | |
3075 | than treating something like "$vf0x++" as an expression. */ | |
3076 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3077 | return 0; |
3078 | ||
3079 | token.u.ch = '('; | |
3080 | mips_add_token (&token, OT_CHAR); | |
3081 | ||
14daeee3 RS |
3082 | if (decrement_p) |
3083 | { | |
3084 | token.u.ch = '-'; | |
3085 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3086 | } | |
3087 | ||
a92713e6 RS |
3088 | token.u.regno = regno; |
3089 | mips_add_token (&token, OT_REG); | |
3090 | ||
14daeee3 RS |
3091 | if (channels) |
3092 | { | |
3093 | token.u.channels = channels; | |
3094 | mips_add_token (&token, OT_CHANNELS); | |
3095 | } | |
3096 | ||
3097 | /* For consistency, only match "++" as part of base expressions too. */ | |
3098 | SKIP_SPACE_TABS (s); | |
3099 | if (s[0] == '+' && s[1] == '+') | |
3100 | { | |
3101 | s += 2; | |
3102 | token.u.ch = '+'; | |
3103 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3104 | } | |
3105 | ||
a92713e6 RS |
3106 | return s; |
3107 | } | |
3108 | ||
3109 | /* Parse one or more tokens from S. Return a pointer to the first | |
3110 | unconsumed character on success. Return null if an error was found | |
3111 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3112 | mips_parse_arguments. */ | |
3113 | ||
3114 | static char * | |
3115 | mips_parse_argument_token (char *s, char float_format) | |
3116 | { | |
6d4af3c2 AM |
3117 | char *end, *save_in; |
3118 | const char *err; | |
14daeee3 | 3119 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3120 | struct mips_operand_token token; |
3121 | ||
3122 | /* First look for "($reg", since we want to treat that as an | |
3123 | OT_CHAR and OT_REG rather than an expression. */ | |
3124 | end = mips_parse_base_start (s); | |
3125 | if (end) | |
3126 | return end; | |
3127 | ||
3128 | /* Handle other characters that end up as OT_CHARs. */ | |
3129 | if (*s == ')' || *s == ',') | |
3130 | { | |
3131 | token.u.ch = *s; | |
3132 | mips_add_token (&token, OT_CHAR); | |
3133 | ++s; | |
3134 | return s; | |
3135 | } | |
3136 | ||
3137 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3138 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3139 | { |
14daeee3 RS |
3140 | if (channels) |
3141 | { | |
3142 | /* A register and a VU0 channel suffix. */ | |
3143 | token.u.regno = regno1; | |
3144 | mips_add_token (&token, OT_REG); | |
3145 | ||
3146 | token.u.channels = channels; | |
3147 | mips_add_token (&token, OT_CHANNELS); | |
3148 | return s; | |
3149 | } | |
3150 | ||
a92713e6 RS |
3151 | SKIP_SPACE_TABS (s); |
3152 | if (*s == '-') | |
df58fc94 | 3153 | { |
a92713e6 RS |
3154 | /* A register range. */ |
3155 | ++s; | |
3156 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3157 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3158 | { |
1661c76c | 3159 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3160 | return 0; |
3161 | } | |
df58fc94 | 3162 | |
a92713e6 RS |
3163 | token.u.reg_range.regno1 = regno1; |
3164 | token.u.reg_range.regno2 = regno2; | |
3165 | mips_add_token (&token, OT_REG_RANGE); | |
3166 | return s; | |
3167 | } | |
a92713e6 | 3168 | |
56d438b1 CF |
3169 | /* Add the register itself. */ |
3170 | token.u.regno = regno1; | |
3171 | mips_add_token (&token, OT_REG); | |
3172 | ||
3173 | /* Check for a vector index. */ | |
3174 | if (*s == '[') | |
3175 | { | |
a92713e6 RS |
3176 | ++s; |
3177 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3178 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3179 | mips_add_token (&token, OT_REG_INDEX); | |
3180 | else | |
a92713e6 | 3181 | { |
56d438b1 CF |
3182 | expressionS element; |
3183 | ||
3184 | my_getExpression (&element, s); | |
3185 | if (element.X_op != O_constant) | |
3186 | { | |
3187 | set_insn_error (0, _("vector element must be constant")); | |
3188 | return 0; | |
3189 | } | |
3190 | s = expr_end; | |
3191 | token.u.index = element.X_add_number; | |
3192 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3193 | } |
a92713e6 RS |
3194 | SKIP_SPACE_TABS (s); |
3195 | if (*s != ']') | |
3196 | { | |
1661c76c | 3197 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3198 | return 0; |
3199 | } | |
3200 | ++s; | |
df58fc94 | 3201 | } |
a92713e6 | 3202 | return s; |
df58fc94 RS |
3203 | } |
3204 | ||
a92713e6 RS |
3205 | if (float_format) |
3206 | { | |
3207 | /* First try to treat expressions as floats. */ | |
3208 | save_in = input_line_pointer; | |
3209 | input_line_pointer = s; | |
3210 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3211 | &token.u.flt.length); | |
3212 | end = input_line_pointer; | |
3213 | input_line_pointer = save_in; | |
3214 | if (err && *err) | |
3215 | { | |
e3de51ce | 3216 | set_insn_error (0, err); |
a92713e6 RS |
3217 | return 0; |
3218 | } | |
3219 | if (s != end) | |
3220 | { | |
3221 | mips_add_token (&token, OT_FLOAT); | |
3222 | return end; | |
3223 | } | |
3224 | } | |
3225 | ||
3226 | /* Treat everything else as an integer expression. */ | |
3227 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3228 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3229 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3230 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3231 | s = expr_end; | |
3232 | mips_add_token (&token, OT_INTEGER); | |
3233 | return s; | |
3234 | } | |
3235 | ||
3236 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3237 | if expressions should be treated as 32-bit floating-point constants, | |
3238 | 'd' if they should be treated as 64-bit floating-point constants, | |
3239 | or 0 if they should be treated as integer expressions (the usual case). | |
3240 | ||
3241 | Return a list of tokens on success, otherwise return 0. The caller | |
3242 | must obstack_free the list after use. */ | |
3243 | ||
3244 | static struct mips_operand_token * | |
3245 | mips_parse_arguments (char *s, char float_format) | |
3246 | { | |
3247 | struct mips_operand_token token; | |
3248 | ||
3249 | SKIP_SPACE_TABS (s); | |
3250 | while (*s) | |
3251 | { | |
3252 | s = mips_parse_argument_token (s, float_format); | |
3253 | if (!s) | |
3254 | { | |
3255 | obstack_free (&mips_operand_tokens, | |
3256 | obstack_finish (&mips_operand_tokens)); | |
3257 | return 0; | |
3258 | } | |
3259 | SKIP_SPACE_TABS (s); | |
3260 | } | |
3261 | mips_add_token (&token, OT_END); | |
3262 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3263 | } |
3264 | ||
d301a56b RS |
3265 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3266 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3267 | |
3268 | static bfd_boolean | |
f79e2745 | 3269 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3270 | { |
3271 | int isa = mips_opts.isa; | |
846ef2d0 | 3272 | int ase = mips_opts.ase; |
037b32b9 | 3273 | int fp_s, fp_d; |
c6278170 | 3274 | unsigned int i; |
037b32b9 | 3275 | |
be0fcbee | 3276 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3277 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3278 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3279 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3280 | |
d301a56b | 3281 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3282 | return FALSE; |
3283 | ||
3284 | /* Check whether the instruction or macro requires single-precision or | |
3285 | double-precision floating-point support. Note that this information is | |
3286 | stored differently in the opcode table for insns and macros. */ | |
3287 | if (mo->pinfo == INSN_MACRO) | |
3288 | { | |
3289 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3290 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3291 | } | |
3292 | else | |
3293 | { | |
3294 | fp_s = mo->pinfo & FP_S; | |
3295 | fp_d = mo->pinfo & FP_D; | |
3296 | } | |
3297 | ||
3298 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3299 | return FALSE; | |
3300 | ||
3301 | if (fp_s && mips_opts.soft_float) | |
3302 | return FALSE; | |
3303 | ||
3304 | return TRUE; | |
3305 | } | |
3306 | ||
3307 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3308 | selected ISA and architecture. */ | |
3309 | ||
3310 | static bfd_boolean | |
3311 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3312 | { | |
25499ac7 MR |
3313 | int isa = mips_opts.isa; |
3314 | int ase = mips_opts.ase; | |
3315 | unsigned int i; | |
3316 | ||
3317 | if (ISA_HAS_64BIT_REGS (isa)) | |
3318 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3319 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3320 | ase |= mips_ases[i].flags64; | |
3321 | ||
3322 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3323 | } |
3324 | ||
df58fc94 | 3325 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3326 | explicitly requested. Always TRUE in the standard MIPS mode. |
3327 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3328 | |
3329 | static bfd_boolean | |
3330 | is_size_valid (const struct mips_opcode *mo) | |
3331 | { | |
3332 | if (!mips_opts.micromips) | |
3333 | return TRUE; | |
3334 | ||
833794fc MR |
3335 | if (mips_opts.insn32) |
3336 | { | |
3337 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3338 | return FALSE; | |
3339 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3340 | return FALSE; | |
3341 | } | |
df58fc94 RS |
3342 | if (!forced_insn_length) |
3343 | return TRUE; | |
3344 | if (mo->pinfo == INSN_MACRO) | |
3345 | return FALSE; | |
3346 | return forced_insn_length == micromips_insn_length (mo); | |
3347 | } | |
3348 | ||
7fd53920 MR |
3349 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3350 | explicitly requested. */ | |
3351 | ||
3352 | static bfd_boolean | |
3353 | is_size_valid_16 (const struct mips_opcode *mo) | |
3354 | { | |
3355 | if (!forced_insn_length) | |
3356 | return TRUE; | |
3357 | if (mo->pinfo == INSN_MACRO) | |
3358 | return FALSE; | |
3359 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3360 | return FALSE; | |
0674ee5d MR |
3361 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3362 | return FALSE; | |
7fd53920 MR |
3363 | return TRUE; |
3364 | } | |
3365 | ||
df58fc94 | 3366 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3367 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3368 | ||
3369 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3370 | a macro expansion fails because it relies on a preceding 32-bit real | |
3371 | instruction to have matched and does not handle the operands correctly. | |
3372 | The only macros that may expand to 16-bit instructions are JAL that | |
3373 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3374 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3375 | a NOP. In all these cases the macros precede any corresponding real | |
3376 | instruction definitions in the opcode table, so they will match in the | |
3377 | second pass where the size of the delay slot is ignored and therefore | |
3378 | produce correct code. */ | |
df58fc94 RS |
3379 | |
3380 | static bfd_boolean | |
3381 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3382 | { | |
3383 | if (!mips_opts.micromips) | |
3384 | return TRUE; | |
3385 | ||
3386 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3387 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3388 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3389 | && micromips_insn_length (mo) != 4) | |
3390 | return FALSE; | |
3391 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3392 | && micromips_insn_length (mo) != 2) | |
3393 | return FALSE; | |
3394 | ||
3395 | return TRUE; | |
3396 | } | |
3397 | ||
fc76e730 RS |
3398 | /* For consistency checking, verify that all bits of OPCODE are specified |
3399 | either by the match/mask part of the instruction definition, or by the | |
3400 | operand list. Also build up a list of operands in OPERANDS. | |
3401 | ||
3402 | INSN_BITS says which bits of the instruction are significant. | |
3403 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3404 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3405 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3406 | |
3407 | static int | |
3408 | validate_mips_insn (const struct mips_opcode *opcode, | |
3409 | unsigned long insn_bits, | |
fc76e730 RS |
3410 | const struct mips_operand *(*decode_operand) (const char *), |
3411 | struct mips_operand_array *operands) | |
ab902481 RS |
3412 | { |
3413 | const char *s; | |
fc76e730 | 3414 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3415 | const struct mips_operand *operand; |
3416 | ||
fc76e730 RS |
3417 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3418 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3419 | { |
3420 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3421 | opcode->name, opcode->args); | |
3422 | return 0; | |
3423 | } | |
3424 | used_bits = 0; | |
fc76e730 | 3425 | opno = 0; |
14daeee3 RS |
3426 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3427 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3428 | for (s = opcode->args; *s; ++s) |
3429 | switch (*s) | |
3430 | { | |
3431 | case ',': | |
3432 | case '(': | |
3433 | case ')': | |
3434 | break; | |
3435 | ||
14daeee3 RS |
3436 | case '#': |
3437 | s++; | |
3438 | break; | |
3439 | ||
ab902481 | 3440 | default: |
fc76e730 | 3441 | if (!decode_operand) |
7fd53920 | 3442 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3443 | else |
3444 | operand = decode_operand (s); | |
3445 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3446 | { |
3447 | as_bad (_("internal: unknown operand type: %s %s"), | |
3448 | opcode->name, opcode->args); | |
3449 | return 0; | |
3450 | } | |
fc76e730 RS |
3451 | gas_assert (opno < MAX_OPERANDS); |
3452 | operands->operand[opno] = operand; | |
25499ac7 MR |
3453 | if (!decode_operand && operand |
3454 | && operand->type == OP_INT && operand->lsb == 0 | |
3455 | && mips_opcode_32bit_p (opcode)) | |
3456 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3457 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3458 | { |
14daeee3 | 3459 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3460 | if (operand->type == OP_MDMX_IMM_REG) |
3461 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3462 | has separate entries for each format. */ | |
3463 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3464 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3465 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3466 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3467 | operand field that cannot be fully described with LSB/SIZE. */ | |
3468 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3469 | used_bits &= ~0x6000; | |
fc76e730 | 3470 | } |
ab902481 | 3471 | /* Skip prefix characters. */ |
7361da2c | 3472 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3473 | ++s; |
fc76e730 | 3474 | opno += 1; |
ab902481 RS |
3475 | break; |
3476 | } | |
fc76e730 | 3477 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3478 | if (doubled) |
3479 | { | |
3480 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3481 | " %s %s"), doubled, opcode->name, opcode->args); | |
3482 | return 0; | |
3483 | } | |
fc76e730 | 3484 | used_bits |= mask; |
ab902481 | 3485 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3486 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3487 | { |
3488 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3489 | undefined, opcode->name, opcode->args); | |
3490 | return 0; | |
3491 | } | |
3492 | used_bits &= ~insn_bits; | |
3493 | if (used_bits) | |
3494 | { | |
3495 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3496 | used_bits, opcode->name, opcode->args); | |
3497 | return 0; | |
3498 | } | |
3499 | return 1; | |
3500 | } | |
3501 | ||
fc76e730 RS |
3502 | /* The MIPS16 version of validate_mips_insn. */ |
3503 | ||
3504 | static int | |
3505 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3506 | struct mips_operand_array *operands) | |
3507 | { | |
7fd53920 | 3508 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3509 | |
7fd53920 | 3510 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3511 | } |
3512 | ||
ab902481 RS |
3513 | /* The microMIPS version of validate_mips_insn. */ |
3514 | ||
3515 | static int | |
fc76e730 RS |
3516 | validate_micromips_insn (const struct mips_opcode *opc, |
3517 | struct mips_operand_array *operands) | |
ab902481 RS |
3518 | { |
3519 | unsigned long insn_bits; | |
3520 | unsigned long major; | |
3521 | unsigned int length; | |
3522 | ||
fc76e730 RS |
3523 | if (opc->pinfo == INSN_MACRO) |
3524 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3525 | operands); | |
3526 | ||
ab902481 RS |
3527 | length = micromips_insn_length (opc); |
3528 | if (length != 2 && length != 4) | |
3529 | { | |
1661c76c | 3530 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3531 | "%s %s"), length, opc->name, opc->args); |
3532 | return 0; | |
3533 | } | |
3534 | major = opc->match >> (10 + 8 * (length - 2)); | |
3535 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3536 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3537 | { | |
1661c76c | 3538 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3539 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3540 | return 0; | |
3541 | } | |
3542 | ||
3543 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3544 | insn_bits = 1 << 4 * length; | |
3545 | insn_bits <<= 4 * length; | |
3546 | insn_bits -= 1; | |
fc76e730 RS |
3547 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3548 | operands); | |
ab902481 RS |
3549 | } |
3550 | ||
707bfff6 TS |
3551 | /* This function is called once, at assembler startup time. It should set up |
3552 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3553 | |
252b5132 | 3554 | void |
17a2f251 | 3555 | md_begin (void) |
252b5132 | 3556 | { |
3994f87e | 3557 | const char *retval = NULL; |
156c2f8b | 3558 | int i = 0; |
252b5132 | 3559 | int broken = 0; |
1f25f5d3 | 3560 | |
0a44bf69 RS |
3561 | if (mips_pic != NO_PIC) |
3562 | { | |
3563 | if (g_switch_seen && g_switch_value != 0) | |
3564 | as_bad (_("-G may not be used in position-independent code")); | |
3565 | g_switch_value = 0; | |
3566 | } | |
00acd688 CM |
3567 | else if (mips_abicalls) |
3568 | { | |
3569 | if (g_switch_seen && g_switch_value != 0) | |
3570 | as_bad (_("-G may not be used with abicalls")); | |
3571 | g_switch_value = 0; | |
3572 | } | |
0a44bf69 | 3573 | |
0b35dfee | 3574 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3575 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3576 | |
252b5132 RH |
3577 | op_hash = hash_new (); |
3578 | ||
fc76e730 | 3579 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3580 | for (i = 0; i < NUMOPCODES;) |
3581 | { | |
3582 | const char *name = mips_opcodes[i].name; | |
3583 | ||
17a2f251 | 3584 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3585 | if (retval != NULL) |
3586 | { | |
3587 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3588 | mips_opcodes[i].name, retval); | |
3589 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3590 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3591 | } |
3592 | do | |
3593 | { | |
fc76e730 RS |
3594 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3595 | decode_mips_operand, &mips_operands[i])) | |
3596 | broken = 1; | |
3597 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3598 | { |
fc76e730 RS |
3599 | create_insn (&nop_insn, mips_opcodes + i); |
3600 | if (mips_fix_loongson2f_nop) | |
3601 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3602 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3603 | } |
3604 | ++i; | |
3605 | } | |
3606 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3607 | } | |
3608 | ||
3609 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3610 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3611 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3612 | |
3613 | i = 0; | |
3614 | while (i < bfd_mips16_num_opcodes) | |
3615 | { | |
3616 | const char *name = mips16_opcodes[i].name; | |
3617 | ||
17a2f251 | 3618 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3619 | if (retval != NULL) |
3620 | as_fatal (_("internal: can't hash `%s': %s"), | |
3621 | mips16_opcodes[i].name, retval); | |
3622 | do | |
3623 | { | |
fc76e730 RS |
3624 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3625 | broken = 1; | |
1e915849 RS |
3626 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3627 | { | |
3628 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3629 | mips16_nop_insn.fixed_p = 1; | |
3630 | } | |
252b5132 RH |
3631 | ++i; |
3632 | } | |
3633 | while (i < bfd_mips16_num_opcodes | |
3634 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3635 | } | |
3636 | ||
df58fc94 | 3637 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3638 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3639 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3640 | |
3641 | i = 0; | |
3642 | while (i < bfd_micromips_num_opcodes) | |
3643 | { | |
3644 | const char *name = micromips_opcodes[i].name; | |
3645 | ||
3646 | retval = hash_insert (micromips_op_hash, name, | |
3647 | (void *) µmips_opcodes[i]); | |
3648 | if (retval != NULL) | |
3649 | as_fatal (_("internal: can't hash `%s': %s"), | |
3650 | micromips_opcodes[i].name, retval); | |
3651 | do | |
fc76e730 RS |
3652 | { |
3653 | struct mips_cl_insn *micromips_nop_insn; | |
3654 | ||
3655 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3656 | µmips_operands[i])) | |
3657 | broken = 1; | |
3658 | ||
3659 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3660 | { | |
3661 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3662 | micromips_nop_insn = µmips_nop16_insn; | |
3663 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3664 | micromips_nop_insn = µmips_nop32_insn; | |
3665 | else | |
3666 | continue; | |
3667 | ||
3668 | if (micromips_nop_insn->insn_mo == NULL | |
3669 | && strcmp (name, "nop") == 0) | |
3670 | { | |
3671 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3672 | micromips_nop_insn->fixed_p = 1; | |
3673 | } | |
3674 | } | |
3675 | } | |
df58fc94 RS |
3676 | while (++i < bfd_micromips_num_opcodes |
3677 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3678 | } | |
3679 | ||
252b5132 | 3680 | if (broken) |
1661c76c | 3681 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3682 | |
3683 | /* We add all the general register names to the symbol table. This | |
3684 | helps us detect invalid uses of them. */ | |
3739860c | 3685 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3686 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3687 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3688 | &zero_address_frag)); |
3689 | if (HAVE_NEWABI) | |
3739860c | 3690 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3691 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3692 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3693 | &zero_address_frag)); |
707bfff6 | 3694 | else |
3739860c | 3695 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3696 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3697 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3698 | &zero_address_frag)); |
6047c971 | 3699 | |
14daeee3 RS |
3700 | for (i = 0; i < 32; i++) |
3701 | { | |
92fce9bd | 3702 | char regname[6]; |
14daeee3 RS |
3703 | |
3704 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3705 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3706 | symbol_table_insert (symbol_new (regname, reg_section, |
3707 | RTYPE_VF | i, &zero_address_frag)); | |
3708 | ||
3709 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3710 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3711 | symbol_table_insert (symbol_new (regname, reg_section, |
3712 | RTYPE_VI | i, &zero_address_frag)); | |
3713 | ||
56d438b1 | 3714 | /* MSA register. */ |
92fce9bd | 3715 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3716 | symbol_table_insert (symbol_new (regname, reg_section, |
3717 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3718 | } |
3719 | ||
a92713e6 RS |
3720 | obstack_init (&mips_operand_tokens); |
3721 | ||
7d10b47d | 3722 | mips_no_prev_insn (); |
252b5132 RH |
3723 | |
3724 | mips_gprmask = 0; | |
3725 | mips_cprmask[0] = 0; | |
3726 | mips_cprmask[1] = 0; | |
3727 | mips_cprmask[2] = 0; | |
3728 | mips_cprmask[3] = 0; | |
3729 | ||
3730 | /* set the default alignment for the text section (2**2) */ | |
3731 | record_alignment (text_section, 2); | |
3732 | ||
4d0d148d | 3733 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3734 | |
f3ded42a RS |
3735 | /* On a native system other than VxWorks, sections must be aligned |
3736 | to 16 byte boundaries. When configured for an embedded ELF | |
3737 | target, we don't bother. */ | |
3738 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3739 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3740 | { |
f3ded42a RS |
3741 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3742 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3743 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3744 | } | |
252b5132 | 3745 | |
f3ded42a RS |
3746 | /* Create a .reginfo section for register masks and a .mdebug |
3747 | section for debugging information. */ | |
3748 | { | |
3749 | segT seg; | |
3750 | subsegT subseg; | |
3751 | flagword flags; | |
3752 | segT sec; | |
3753 | ||
3754 | seg = now_seg; | |
3755 | subseg = now_subseg; | |
3756 | ||
3757 | /* The ABI says this section should be loaded so that the | |
3758 | running program can access it. However, we don't load it | |
3759 | if we are configured for an embedded target */ | |
3760 | flags = SEC_READONLY | SEC_DATA; | |
3761 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3762 | flags |= SEC_ALLOC | SEC_LOAD; | |
3763 | ||
3764 | if (mips_abi != N64_ABI) | |
252b5132 | 3765 | { |
f3ded42a | 3766 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3767 | |
f3ded42a RS |
3768 | bfd_set_section_flags (stdoutput, sec, flags); |
3769 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3770 | |
f3ded42a RS |
3771 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3772 | } | |
3773 | else | |
3774 | { | |
3775 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3776 | .reginfo section. */ | |
3777 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3778 | bfd_set_section_flags (stdoutput, sec, flags); | |
3779 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3780 | |
f3ded42a RS |
3781 | /* Set up the option header. */ |
3782 | { | |
3783 | Elf_Internal_Options opthdr; | |
3784 | char *f; | |
3785 | ||
3786 | opthdr.kind = ODK_REGINFO; | |
3787 | opthdr.size = (sizeof (Elf_External_Options) | |
3788 | + sizeof (Elf64_External_RegInfo)); | |
3789 | opthdr.section = 0; | |
3790 | opthdr.info = 0; | |
3791 | f = frag_more (sizeof (Elf_External_Options)); | |
3792 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3793 | (Elf_External_Options *) f); | |
3794 | ||
3795 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3796 | } | |
3797 | } | |
252b5132 | 3798 | |
351cdf24 MF |
3799 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3800 | bfd_set_section_flags (stdoutput, sec, | |
3801 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3802 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3803 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3804 | ||
f3ded42a RS |
3805 | if (ECOFF_DEBUGGING) |
3806 | { | |
3807 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3808 | (void) bfd_set_section_flags (stdoutput, sec, | |
3809 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3810 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3811 | } |
f3ded42a RS |
3812 | else if (mips_flag_pdr) |
3813 | { | |
3814 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3815 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3816 | SEC_READONLY | SEC_RELOC | |
3817 | | SEC_DEBUGGING); | |
3818 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3819 | } | |
3820 | ||
3821 | subseg_set (seg, subseg); | |
3822 | } | |
252b5132 | 3823 | |
71400594 RS |
3824 | if (mips_fix_vr4120) |
3825 | init_vr4120_conflicts (); | |
252b5132 RH |
3826 | } |
3827 | ||
351cdf24 MF |
3828 | static inline void |
3829 | fpabi_incompatible_with (int fpabi, const char *what) | |
3830 | { | |
3831 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3832 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3833 | } | |
3834 | ||
3835 | static inline void | |
3836 | fpabi_requires (int fpabi, const char *what) | |
3837 | { | |
3838 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3839 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3840 | } | |
3841 | ||
3842 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3843 | static void | |
3844 | check_fpabi (int fpabi) | |
3845 | { | |
351cdf24 MF |
3846 | switch (fpabi) |
3847 | { | |
3848 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3849 | if (file_mips_opts.soft_float) |
3850 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3851 | else if (file_mips_opts.single_float) | |
3852 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3853 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3854 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3855 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3856 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3857 | break; |
3858 | ||
3859 | case Val_GNU_MIPS_ABI_FP_XX: | |
3860 | if (mips_abi != O32_ABI) | |
3861 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3862 | else if (file_mips_opts.soft_float) |
3863 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3864 | else if (file_mips_opts.single_float) | |
3865 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3866 | else if (file_mips_opts.fp != 0) |
3867 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3868 | break; |
3869 | ||
3870 | case Val_GNU_MIPS_ABI_FP_64A: | |
3871 | case Val_GNU_MIPS_ABI_FP_64: | |
3872 | if (mips_abi != O32_ABI) | |
3873 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3874 | else if (file_mips_opts.soft_float) |
3875 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3876 | else if (file_mips_opts.single_float) | |
3877 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3878 | else if (file_mips_opts.fp != 64) |
3879 | fpabi_requires (fpabi, "fp=64"); | |
3880 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3881 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3882 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3883 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3884 | break; |
3885 | ||
3886 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3887 | if (file_mips_opts.soft_float) | |
3888 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3889 | else if (!file_mips_opts.single_float) | |
3890 | fpabi_requires (fpabi, "singlefloat"); | |
3891 | break; | |
3892 | ||
3893 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3894 | if (!file_mips_opts.soft_float) | |
3895 | fpabi_requires (fpabi, "softfloat"); | |
3896 | break; | |
3897 | ||
3898 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3899 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3900 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3901 | break; | |
3902 | ||
3350cc01 CM |
3903 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3904 | /* Silently ignore compatibility value. */ | |
3905 | break; | |
3906 | ||
351cdf24 MF |
3907 | default: |
3908 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3909 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3910 | break; | |
3911 | } | |
351cdf24 MF |
3912 | } |
3913 | ||
919731af | 3914 | /* Perform consistency checks on the current options. */ |
3915 | ||
3916 | static void | |
3917 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3918 | { | |
3919 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3920 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3921 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3922 | else if (abi_checks | |
3923 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3924 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3925 | else if (abi_checks | |
3926 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3927 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3928 | ||
3929 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3930 | switch (opts->fp) | |
3931 | { | |
351cdf24 MF |
3932 | case 0: |
3933 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3934 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3935 | else if (opts->single_float == 1) | |
3936 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3937 | break; | |
919731af | 3938 | case 64: |
3939 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3940 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3941 | else if (abi_checks | |
3942 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3943 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3944 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3945 | break; | |
3946 | case 32: | |
3947 | if (abi_checks | |
3948 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3949 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 3950 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 3951 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 3952 | break; |
3953 | default: | |
3954 | as_bad (_("Unknown size of floating point registers")); | |
3955 | break; | |
3956 | } | |
3957 | ||
351cdf24 MF |
3958 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
3959 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
3960 | ||
919731af | 3961 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 3962 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 3963 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
3964 | && (opts->micromips == 1 |
3965 | || opts->mips16 == 1)) | |
1357373c | 3966 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 3967 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 3968 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
3969 | |
3970 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
3971 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
3972 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 3973 | } |
3974 | ||
3975 | /* Perform consistency checks on the module level options exactly once. | |
3976 | This is a deferred check that happens: | |
3977 | at the first .set directive | |
3978 | or, at the first pseudo op that generates code (inc .dc.a) | |
3979 | or, at the first instruction | |
3980 | or, at the end. */ | |
3981 | ||
3982 | static void | |
3983 | file_mips_check_options (void) | |
3984 | { | |
3985 | const struct mips_cpu_info *arch_info = 0; | |
3986 | ||
3987 | if (file_mips_opts_checked) | |
3988 | return; | |
3989 | ||
3990 | /* The following code determines the register size. | |
3991 | Similar code was added to GCC 3.3 (see override_options() in | |
3992 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
3993 | as much as possible. */ | |
3994 | ||
3995 | if (file_mips_opts.gp < 0) | |
3996 | { | |
3997 | /* Infer the integer register size from the ABI and processor. | |
3998 | Restrict ourselves to 32-bit registers if that's all the | |
3999 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4000 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4001 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4002 | ? 32 : 64; | |
4003 | } | |
4004 | ||
4005 | if (file_mips_opts.fp < 0) | |
4006 | { | |
4007 | /* No user specified float register size. | |
4008 | ??? GAS treats single-float processors as though they had 64-bit | |
4009 | float registers (although it complains when double-precision | |
4010 | instructions are used). As things stand, saying they have 32-bit | |
4011 | registers would lead to spurious "register must be even" messages. | |
4012 | So here we assume float registers are never smaller than the | |
4013 | integer ones. */ | |
4014 | if (file_mips_opts.gp == 64) | |
4015 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4016 | file_mips_opts.fp = 64; | |
4017 | else if ((file_mips_opts.ase & FP64_ASES) | |
4018 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4019 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4020 | file_mips_opts.fp = 64; | |
7361da2c AB |
4021 | else if (ISA_IS_R6 (mips_opts.isa)) |
4022 | /* R6 implies 64-bit float registers. */ | |
4023 | file_mips_opts.fp = 64; | |
919731af | 4024 | else |
4025 | /* 32-bit float registers. */ | |
4026 | file_mips_opts.fp = 32; | |
4027 | } | |
4028 | ||
4029 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
4030 | ||
351cdf24 MF |
4031 | /* Disable operations on odd-numbered floating-point registers by default |
4032 | when using the FPXX ABI. */ | |
4033 | if (file_mips_opts.oddspreg < 0) | |
4034 | { | |
4035 | if (file_mips_opts.fp == 0) | |
4036 | file_mips_opts.oddspreg = 0; | |
4037 | else | |
4038 | file_mips_opts.oddspreg = 1; | |
4039 | } | |
4040 | ||
919731af | 4041 | /* End of GCC-shared inference code. */ |
4042 | ||
4043 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4044 | 32-bit wide registers. Note that EABI does not use it. */ | |
4045 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4046 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4047 | || mips_abi == O32_ABI)) | |
4048 | mips_32bitmode = 1; | |
4049 | ||
4050 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4051 | as_bad (_("trap exception not supported at ISA 1")); | |
4052 | ||
4053 | /* If the selected architecture includes support for ASEs, enable | |
4054 | generation of code for them. */ | |
4055 | if (file_mips_opts.mips16 == -1) | |
4056 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4057 | if (file_mips_opts.micromips == -1) | |
4058 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4059 | ? 1 : 0; | |
4060 | ||
7361da2c AB |
4061 | if (mips_nan2008 == -1) |
4062 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4063 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4064 | as_fatal (_("`%s' does not support legacy NaN"), | |
4065 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4066 | ||
919731af | 4067 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4068 | being selected implicitly. */ | |
4069 | if (file_mips_opts.fp != 64) | |
4070 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4071 | ||
4072 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4073 | use the default setting for the CPU. */ | |
4074 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4075 | ||
4076 | /* Set up the current options. These may change throughout assembly. */ | |
4077 | mips_opts = file_mips_opts; | |
4078 | ||
4079 | mips_check_isa_supports_ases (); | |
4080 | mips_check_options (&file_mips_opts, TRUE); | |
4081 | file_mips_opts_checked = TRUE; | |
4082 | ||
4083 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4084 | as_warn (_("could not set architecture and machine")); | |
4085 | } | |
4086 | ||
252b5132 | 4087 | void |
17a2f251 | 4088 | md_assemble (char *str) |
252b5132 RH |
4089 | { |
4090 | struct mips_cl_insn insn; | |
f6688943 TS |
4091 | bfd_reloc_code_real_type unused_reloc[3] |
4092 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4093 | |
919731af | 4094 | file_mips_check_options (); |
4095 | ||
252b5132 | 4096 | imm_expr.X_op = O_absent; |
252b5132 | 4097 | offset_expr.X_op = O_absent; |
f6688943 TS |
4098 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4099 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4100 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4101 | |
e1b47bd5 RS |
4102 | mips_mark_labels (); |
4103 | mips_assembling_insn = TRUE; | |
e3de51ce | 4104 | clear_insn_error (); |
e1b47bd5 | 4105 | |
252b5132 RH |
4106 | if (mips_opts.mips16) |
4107 | mips16_ip (str, &insn); | |
4108 | else | |
4109 | { | |
4110 | mips_ip (str, &insn); | |
beae10d5 KH |
4111 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4112 | str, insn.insn_opcode)); | |
252b5132 RH |
4113 | } |
4114 | ||
e3de51ce RS |
4115 | if (insn_error.msg) |
4116 | report_insn_error (str); | |
e1b47bd5 | 4117 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4118 | { |
584892a6 | 4119 | macro_start (); |
252b5132 RH |
4120 | if (mips_opts.mips16) |
4121 | mips16_macro (&insn); | |
4122 | else | |
833794fc | 4123 | macro (&insn, str); |
584892a6 | 4124 | macro_end (); |
252b5132 RH |
4125 | } |
4126 | else | |
4127 | { | |
77bd4346 | 4128 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4129 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4130 | else |
df58fc94 | 4131 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4132 | } |
e1b47bd5 RS |
4133 | |
4134 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4135 | } |
4136 | ||
738e5348 RS |
4137 | /* Convenience functions for abstracting away the differences between |
4138 | MIPS16 and non-MIPS16 relocations. */ | |
4139 | ||
4140 | static inline bfd_boolean | |
4141 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4142 | { | |
4143 | switch (reloc) | |
4144 | { | |
4145 | case BFD_RELOC_MIPS16_JMP: | |
4146 | case BFD_RELOC_MIPS16_GPREL: | |
4147 | case BFD_RELOC_MIPS16_GOT16: | |
4148 | case BFD_RELOC_MIPS16_CALL16: | |
4149 | case BFD_RELOC_MIPS16_HI16_S: | |
4150 | case BFD_RELOC_MIPS16_HI16: | |
4151 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4152 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4153 | return TRUE; |
4154 | ||
4155 | default: | |
4156 | return FALSE; | |
4157 | } | |
4158 | } | |
4159 | ||
df58fc94 RS |
4160 | static inline bfd_boolean |
4161 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4162 | { | |
4163 | switch (reloc) | |
4164 | { | |
4165 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4166 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4167 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4168 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4169 | case BFD_RELOC_MICROMIPS_JMP: | |
4170 | case BFD_RELOC_MICROMIPS_HI16: | |
4171 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4172 | case BFD_RELOC_MICROMIPS_LO16: | |
4173 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4174 | case BFD_RELOC_MICROMIPS_GOT16: | |
4175 | case BFD_RELOC_MICROMIPS_CALL16: | |
4176 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4177 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4178 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4179 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4180 | case BFD_RELOC_MICROMIPS_SUB: | |
4181 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4182 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4183 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4184 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4185 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4186 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4187 | case BFD_RELOC_MICROMIPS_JALR: | |
4188 | return TRUE; | |
4189 | ||
4190 | default: | |
4191 | return FALSE; | |
4192 | } | |
4193 | } | |
4194 | ||
2309ddf2 MR |
4195 | static inline bfd_boolean |
4196 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4197 | { | |
4198 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4199 | } | |
4200 | ||
0e9c5a5c MR |
4201 | static inline bfd_boolean |
4202 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4203 | { | |
4204 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4205 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4206 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4207 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4208 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4209 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4210 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4211 | } | |
4212 | ||
738e5348 RS |
4213 | static inline bfd_boolean |
4214 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4215 | { | |
2309ddf2 | 4216 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4217 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4218 | } |
4219 | ||
4220 | static inline bfd_boolean | |
4221 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4222 | { | |
2309ddf2 | 4223 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4224 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4225 | } |
4226 | ||
4227 | static inline bfd_boolean | |
4228 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4229 | { | |
2309ddf2 | 4230 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4231 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4232 | } | |
4233 | ||
df58fc94 RS |
4234 | static inline bfd_boolean |
4235 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4236 | { | |
2309ddf2 | 4237 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4238 | } |
4239 | ||
f2ae14a1 RS |
4240 | static inline bfd_boolean |
4241 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4242 | { | |
4243 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4244 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4245 | } | |
4246 | ||
2de39019 CM |
4247 | /* Return true if RELOC is a PC-relative relocation that does not have |
4248 | full address range. */ | |
4249 | ||
4250 | static inline bfd_boolean | |
4251 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4252 | { | |
4253 | switch (reloc) | |
4254 | { | |
4255 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4256 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4257 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4258 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4259 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4260 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4261 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4262 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4263 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4264 | return TRUE; |
4265 | ||
b47468a6 | 4266 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4267 | case BFD_RELOC_HI16_S_PCREL: |
4268 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4269 | return HAVE_64BIT_ADDRESSES; |
4270 | ||
2de39019 CM |
4271 | default: |
4272 | return FALSE; | |
4273 | } | |
4274 | } | |
b47468a6 | 4275 | |
5919d012 | 4276 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4277 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4278 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4279 | |
4280 | static inline bfd_boolean | |
17a2f251 | 4281 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4282 | { |
3b91255e | 4283 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4284 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4285 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4286 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4287 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4288 | } | |
4289 | ||
4290 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4291 | reloc_needs_lo_p. */ | |
4292 | ||
4293 | static inline bfd_reloc_code_real_type | |
4294 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4295 | { | |
df58fc94 RS |
4296 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4297 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4298 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4299 | } |
4300 | ||
4301 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4302 | relocation. */ | |
4303 | ||
4304 | static inline bfd_boolean | |
17a2f251 | 4305 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4306 | { |
4307 | return (fixp->fx_next != NULL | |
738e5348 | 4308 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4309 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4310 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4311 | } | |
4312 | ||
462427c4 RS |
4313 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4314 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4315 | |
4316 | static void | |
462427c4 | 4317 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4318 | { |
4319 | struct insn_label_list *l; | |
4320 | valueT val; | |
4321 | ||
462427c4 | 4322 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4323 | { |
9c2799c2 | 4324 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4325 | symbol_set_frag (l->label, frag_now); |
4326 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4327 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4328 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4329 | ++val; |
4330 | S_SET_VALUE (l->label, val); | |
4331 | } | |
4332 | } | |
4333 | ||
462427c4 RS |
4334 | /* Move all labels in insn_labels to the current insertion point |
4335 | and treat them as text labels. */ | |
4336 | ||
4337 | static void | |
4338 | mips_move_text_labels (void) | |
4339 | { | |
4340 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4341 | } | |
4342 | ||
9e009953 MR |
4343 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4344 | ||
5f0fe04b TS |
4345 | static bfd_boolean |
4346 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4347 | { | |
4348 | bfd_boolean linkonce = FALSE; | |
4349 | segT symseg = S_GET_SEGMENT (sym); | |
4350 | ||
4351 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4352 | { | |
4353 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4354 | linkonce = TRUE; | |
5f0fe04b TS |
4355 | /* The GNU toolchain uses an extension for ELF: a section |
4356 | beginning with the magic string .gnu.linkonce is a | |
4357 | linkonce section. */ | |
4358 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4359 | sizeof ".gnu.linkonce" - 1) == 0) | |
4360 | linkonce = TRUE; | |
5f0fe04b TS |
4361 | } |
4362 | return linkonce; | |
4363 | } | |
4364 | ||
e1b47bd5 | 4365 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4366 | linker to handle them specially, such as generating jalx instructions |
4367 | when needed. We also make them odd for the duration of the assembly, | |
4368 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4369 | in the adjust_symtab routine, while leaving them marked. This is |
4370 | convenient for the debugger and the disassembler. The linker knows | |
4371 | to make them odd again. */ | |
4372 | ||
4373 | static void | |
e1b47bd5 | 4374 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4375 | { |
df58fc94 | 4376 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4377 | |
f3ded42a RS |
4378 | if (mips_opts.mips16) |
4379 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4380 | else | |
4381 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4382 | if ((S_GET_VALUE (label) & 1) == 0 |
4383 | /* Don't adjust the address if the label is global or weak, or | |
4384 | in a link-once section, since we'll be emitting symbol reloc | |
4385 | references to it which will be patched up by the linker, and | |
4386 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4387 | && !S_IS_WEAK (label) | |
4388 | && !S_IS_EXTERNAL (label) | |
4389 | && !s_is_linkonce (label, now_seg)) | |
4390 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4391 | } | |
4392 | ||
4393 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4394 | ||
4395 | static void | |
4396 | mips_compressed_mark_labels (void) | |
4397 | { | |
4398 | struct insn_label_list *l; | |
4399 | ||
4400 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4401 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4402 | } |
4403 | ||
4d7206a2 RS |
4404 | /* End the current frag. Make it a variant frag and record the |
4405 | relaxation info. */ | |
4406 | ||
4407 | static void | |
4408 | relax_close_frag (void) | |
4409 | { | |
584892a6 | 4410 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4411 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4412 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4413 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4414 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4415 | ||
4416 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4417 | mips_relax.first_fixup = 0; | |
4418 | } | |
4419 | ||
4420 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4421 | See the comment above RELAX_ENCODE for more details. */ | |
4422 | ||
4423 | static void | |
4424 | relax_start (symbolS *symbol) | |
4425 | { | |
9c2799c2 | 4426 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4427 | mips_relax.sequence = 1; |
4428 | mips_relax.symbol = symbol; | |
4429 | } | |
4430 | ||
4431 | /* Start generating the second version of a relaxable sequence. | |
4432 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4433 | |
4434 | static void | |
4d7206a2 RS |
4435 | relax_switch (void) |
4436 | { | |
9c2799c2 | 4437 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4438 | mips_relax.sequence = 2; |
4439 | } | |
4440 | ||
4441 | /* End the current relaxable sequence. */ | |
4442 | ||
4443 | static void | |
4444 | relax_end (void) | |
4445 | { | |
9c2799c2 | 4446 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4447 | relax_close_frag (); |
4448 | mips_relax.sequence = 0; | |
4449 | } | |
4450 | ||
11625dd8 RS |
4451 | /* Return true if IP is a delayed branch or jump. */ |
4452 | ||
4453 | static inline bfd_boolean | |
4454 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4455 | { | |
4456 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4457 | | INSN_COND_BRANCH_DELAY | |
4458 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4459 | } | |
4460 | ||
4461 | /* Return true if IP is a compact branch or jump. */ | |
4462 | ||
4463 | static inline bfd_boolean | |
4464 | compact_branch_p (const struct mips_cl_insn *ip) | |
4465 | { | |
26545944 RS |
4466 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4467 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4468 | } |
4469 | ||
4470 | /* Return true if IP is an unconditional branch or jump. */ | |
4471 | ||
4472 | static inline bfd_boolean | |
4473 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4474 | { | |
4475 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4476 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4477 | } |
4478 | ||
4479 | /* Return true if IP is a branch-likely instruction. */ | |
4480 | ||
4481 | static inline bfd_boolean | |
4482 | branch_likely_p (const struct mips_cl_insn *ip) | |
4483 | { | |
4484 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4485 | } | |
4486 | ||
14fe068b RS |
4487 | /* Return the type of nop that should be used to fill the delay slot |
4488 | of delayed branch IP. */ | |
4489 | ||
4490 | static struct mips_cl_insn * | |
4491 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4492 | { | |
4493 | if (mips_opts.micromips | |
4494 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4495 | return µmips_nop32_insn; | |
4496 | return NOP_INSN; | |
4497 | } | |
4498 | ||
fc76e730 RS |
4499 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4500 | in operand N. */ | |
df58fc94 RS |
4501 | |
4502 | static unsigned int | |
fc76e730 | 4503 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4504 | { |
fc76e730 RS |
4505 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4506 | } | |
df58fc94 | 4507 | |
fc76e730 RS |
4508 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4509 | in operand N. */ | |
4510 | ||
4511 | static unsigned int | |
4512 | insn_write_mask (const struct mips_opcode *opcode) | |
4513 | { | |
4514 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4515 | } | |
4516 | ||
4517 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4518 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4519 | is set. */ | |
4520 | ||
4521 | static unsigned int | |
4522 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4523 | const struct mips_operand *operand, | |
4524 | unsigned int type_mask) | |
4525 | { | |
4526 | unsigned int uval, vsel; | |
4527 | ||
4528 | switch (operand->type) | |
df58fc94 | 4529 | { |
fc76e730 RS |
4530 | case OP_INT: |
4531 | case OP_MAPPED_INT: | |
4532 | case OP_MSB: | |
4533 | case OP_PCREL: | |
4534 | case OP_PERF_REG: | |
4535 | case OP_ADDIUSP_INT: | |
4536 | case OP_ENTRY_EXIT_LIST: | |
4537 | case OP_REPEAT_DEST_REG: | |
4538 | case OP_REPEAT_PREV_REG: | |
4539 | case OP_PC: | |
14daeee3 RS |
4540 | case OP_VU0_SUFFIX: |
4541 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4542 | case OP_IMM_INDEX: |
fc76e730 RS |
4543 | abort (); |
4544 | ||
25499ac7 MR |
4545 | case OP_REG28: |
4546 | return 1 << 28; | |
4547 | ||
fc76e730 | 4548 | case OP_REG: |
0f35dbc4 | 4549 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4550 | { |
4551 | const struct mips_reg_operand *reg_op; | |
4552 | ||
4553 | reg_op = (const struct mips_reg_operand *) operand; | |
4554 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4555 | return 0; | |
4556 | uval = insn_extract_operand (insn, operand); | |
4557 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4558 | } | |
4559 | ||
4560 | case OP_REG_PAIR: | |
4561 | { | |
4562 | const struct mips_reg_pair_operand *pair_op; | |
4563 | ||
4564 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4565 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4566 | return 0; | |
4567 | uval = insn_extract_operand (insn, operand); | |
4568 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4569 | } | |
4570 | ||
4571 | case OP_CLO_CLZ_DEST: | |
4572 | if (!(type_mask & (1 << OP_REG_GP))) | |
4573 | return 0; | |
4574 | uval = insn_extract_operand (insn, operand); | |
4575 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4576 | ||
7361da2c AB |
4577 | case OP_SAME_RS_RT: |
4578 | if (!(type_mask & (1 << OP_REG_GP))) | |
4579 | return 0; | |
4580 | uval = insn_extract_operand (insn, operand); | |
4581 | gas_assert ((uval & 31) == (uval >> 5)); | |
4582 | return 1 << (uval & 31); | |
4583 | ||
4584 | case OP_CHECK_PREV: | |
4585 | case OP_NON_ZERO_REG: | |
4586 | if (!(type_mask & (1 << OP_REG_GP))) | |
4587 | return 0; | |
4588 | uval = insn_extract_operand (insn, operand); | |
4589 | return 1 << (uval & 31); | |
4590 | ||
fc76e730 RS |
4591 | case OP_LWM_SWM_LIST: |
4592 | abort (); | |
4593 | ||
4594 | case OP_SAVE_RESTORE_LIST: | |
4595 | abort (); | |
4596 | ||
4597 | case OP_MDMX_IMM_REG: | |
4598 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4599 | return 0; | |
4600 | uval = insn_extract_operand (insn, operand); | |
4601 | vsel = uval >> 5; | |
4602 | if ((vsel & 0x18) == 0x18) | |
4603 | return 0; | |
4604 | return 1 << (uval & 31); | |
56d438b1 CF |
4605 | |
4606 | case OP_REG_INDEX: | |
4607 | if (!(type_mask & (1 << OP_REG_GP))) | |
4608 | return 0; | |
4609 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4610 | } |
fc76e730 RS |
4611 | abort (); |
4612 | } | |
4613 | ||
4614 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4615 | where bit N of OPNO_MASK is set if operand N should be included. | |
4616 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4617 | is set. */ | |
4618 | ||
4619 | static unsigned int | |
4620 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4621 | unsigned int type_mask, unsigned int opno_mask) | |
4622 | { | |
4623 | unsigned int opno, reg_mask; | |
4624 | ||
4625 | opno = 0; | |
4626 | reg_mask = 0; | |
4627 | while (opno_mask != 0) | |
4628 | { | |
4629 | if (opno_mask & 1) | |
4630 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4631 | opno_mask >>= 1; | |
4632 | opno += 1; | |
4633 | } | |
4634 | return reg_mask; | |
df58fc94 RS |
4635 | } |
4636 | ||
4c260379 RS |
4637 | /* Return the mask of core registers that IP reads. */ |
4638 | ||
4639 | static unsigned int | |
4640 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4641 | { | |
4642 | unsigned long pinfo, pinfo2; | |
4643 | unsigned int mask; | |
4644 | ||
fc76e730 | 4645 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4646 | pinfo = ip->insn_mo->pinfo; |
4647 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4648 | if (pinfo & INSN_UDI) |
4c260379 | 4649 | { |
fc76e730 RS |
4650 | /* UDI instructions have traditionally been assumed to read RS |
4651 | and RT. */ | |
4652 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4653 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4654 | } |
fc76e730 RS |
4655 | if (pinfo & INSN_READ_GPR_24) |
4656 | mask |= 1 << 24; | |
4657 | if (pinfo2 & INSN2_READ_GPR_16) | |
4658 | mask |= 1 << 16; | |
4659 | if (pinfo2 & INSN2_READ_SP) | |
4660 | mask |= 1 << SP; | |
26545944 | 4661 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4662 | mask |= 1 << 31; |
fe35f09f RS |
4663 | /* Don't include register 0. */ |
4664 | return mask & ~1; | |
4c260379 RS |
4665 | } |
4666 | ||
4667 | /* Return the mask of core registers that IP writes. */ | |
4668 | ||
4669 | static unsigned int | |
4670 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4671 | { | |
4672 | unsigned long pinfo, pinfo2; | |
4673 | unsigned int mask; | |
4674 | ||
fc76e730 | 4675 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4676 | pinfo = ip->insn_mo->pinfo; |
4677 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4678 | if (pinfo & INSN_WRITE_GPR_24) |
4679 | mask |= 1 << 24; | |
4680 | if (pinfo & INSN_WRITE_GPR_31) | |
4681 | mask |= 1 << 31; | |
4682 | if (pinfo & INSN_UDI) | |
4683 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4684 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4685 | if (pinfo2 & INSN2_WRITE_SP) | |
4686 | mask |= 1 << SP; | |
fe35f09f RS |
4687 | /* Don't include register 0. */ |
4688 | return mask & ~1; | |
4c260379 RS |
4689 | } |
4690 | ||
4691 | /* Return the mask of floating-point registers that IP reads. */ | |
4692 | ||
4693 | static unsigned int | |
4694 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4695 | { | |
fc76e730 | 4696 | unsigned long pinfo; |
4c260379 RS |
4697 | unsigned int mask; |
4698 | ||
9d5de888 CF |
4699 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4700 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4701 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4702 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4703 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4704 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4705 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4706 | mask |= mask << 1; |
4707 | return mask; | |
4708 | } | |
4709 | ||
4710 | /* Return the mask of floating-point registers that IP writes. */ | |
4711 | ||
4712 | static unsigned int | |
4713 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4714 | { | |
fc76e730 | 4715 | unsigned long pinfo; |
4c260379 RS |
4716 | unsigned int mask; |
4717 | ||
9d5de888 CF |
4718 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4719 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4720 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4721 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4722 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4723 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4724 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4725 | mask |= mask << 1; |
4726 | return mask; | |
4727 | } | |
4728 | ||
a1d78564 RS |
4729 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4730 | Check whether that is allowed. */ | |
4731 | ||
4732 | static bfd_boolean | |
4733 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4734 | { | |
4735 | const char *s = insn->name; | |
351cdf24 MF |
4736 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4737 | || FPR_SIZE == 64) | |
4738 | && mips_opts.oddspreg; | |
a1d78564 RS |
4739 | |
4740 | if (insn->pinfo == INSN_MACRO) | |
4741 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4742 | return TRUE; | |
4743 | ||
351cdf24 MF |
4744 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4745 | otherwise it depends on oddspreg. */ | |
4746 | if ((insn->pinfo & FP_S) | |
4747 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4748 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4749 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4750 | |
351cdf24 MF |
4751 | /* Allow odd registers for single-precision ops and double-precision if the |
4752 | floating-point registers are 64-bit wide. */ | |
4753 | switch (insn->pinfo & (FP_S | FP_D)) | |
4754 | { | |
4755 | case FP_S: | |
4756 | case 0: | |
4757 | return oddspreg; | |
4758 | case FP_D: | |
4759 | return FPR_SIZE == 64; | |
4760 | default: | |
4761 | break; | |
a1d78564 RS |
4762 | } |
4763 | ||
351cdf24 MF |
4764 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4765 | s = strchr (insn->name, '.'); | |
4766 | if (s != NULL && opnum == 2) | |
4767 | s = strchr (s + 1, '.'); | |
4768 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4769 | return oddspreg; | |
a1d78564 | 4770 | |
351cdf24 | 4771 | return FPR_SIZE == 64; |
a1d78564 RS |
4772 | } |
4773 | ||
a1d78564 RS |
4774 | /* Information about an instruction argument that we're trying to match. */ |
4775 | struct mips_arg_info | |
4776 | { | |
4777 | /* The instruction so far. */ | |
4778 | struct mips_cl_insn *insn; | |
4779 | ||
a92713e6 RS |
4780 | /* The first unconsumed operand token. */ |
4781 | struct mips_operand_token *token; | |
4782 | ||
a1d78564 RS |
4783 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4784 | int opnum; | |
4785 | ||
4786 | /* The 1-based argument number, for error reporting. This does not | |
4787 | count elided optional registers, etc.. */ | |
4788 | int argnum; | |
4789 | ||
4790 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4791 | unsigned int last_regno; | |
4792 | ||
4793 | /* If the first operand was an OP_REG, this is the register that it | |
4794 | specified, otherwise it is ILLEGAL_REG. */ | |
4795 | unsigned int dest_regno; | |
4796 | ||
4797 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4798 | where it gives the lsb position. */ | |
4799 | unsigned int last_op_int; | |
4800 | ||
60f20e8b | 4801 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4802 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4803 | possible. Match routines should not report errors if something |
4804 | is only invalid for !LAX_MATCH. */ | |
4805 | bfd_boolean lax_match; | |
a1d78564 | 4806 | |
a1d78564 RS |
4807 | /* True if a reference to the current AT register was seen. */ |
4808 | bfd_boolean seen_at; | |
4809 | }; | |
4810 | ||
1a00e612 RS |
4811 | /* Record that the argument is out of range. */ |
4812 | ||
4813 | static void | |
4814 | match_out_of_range (struct mips_arg_info *arg) | |
4815 | { | |
4816 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4817 | } | |
4818 | ||
4819 | /* Record that the argument isn't constant but needs to be. */ | |
4820 | ||
4821 | static void | |
4822 | match_not_constant (struct mips_arg_info *arg) | |
4823 | { | |
4824 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4825 | arg->argnum); | |
4826 | } | |
4827 | ||
a92713e6 RS |
4828 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4829 | and return true on success, otherwise return false. */ | |
a1d78564 | 4830 | |
a92713e6 RS |
4831 | static bfd_boolean |
4832 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4833 | { |
a92713e6 RS |
4834 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4835 | { | |
4836 | ++arg->token; | |
4837 | if (ch == ',') | |
4838 | arg->argnum += 1; | |
4839 | return TRUE; | |
4840 | } | |
4841 | return FALSE; | |
4842 | } | |
a1d78564 | 4843 | |
a92713e6 RS |
4844 | /* Try to get an expression from the next tokens in ARG. Consume the |
4845 | tokens and return true on success, storing the expression value in | |
4846 | VALUE and relocation types in R. */ | |
4847 | ||
4848 | static bfd_boolean | |
4849 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4850 | bfd_reloc_code_real_type *r) | |
4851 | { | |
d436c1c2 RS |
4852 | /* If the next token is a '(' that was parsed as being part of a base |
4853 | expression, assume we have an elided offset. The later match will fail | |
4854 | if this turns out to be wrong. */ | |
4855 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4856 | { |
d436c1c2 RS |
4857 | value->X_op = O_constant; |
4858 | value->X_add_number = 0; | |
4859 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4860 | return TRUE; |
4861 | } | |
4862 | ||
d436c1c2 RS |
4863 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4864 | For plain registers the default error seems more appropriate. */ | |
4865 | if (arg->token->type == OT_INTEGER | |
4866 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4867 | { |
d436c1c2 RS |
4868 | set_insn_error (arg->argnum, _("register value used as expression")); |
4869 | return FALSE; | |
a1d78564 | 4870 | } |
d436c1c2 RS |
4871 | |
4872 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4873 | { |
d436c1c2 RS |
4874 | *value = arg->token->u.integer.value; |
4875 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4876 | ++arg->token; | |
4877 | return TRUE; | |
a92713e6 | 4878 | } |
a92713e6 | 4879 | |
d436c1c2 RS |
4880 | set_insn_error_i |
4881 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4882 | arg->argnum); | |
4883 | return FALSE; | |
a92713e6 RS |
4884 | } |
4885 | ||
4886 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
4887 | the tokens and return return true on success, storing the constant value | |
a54d5f8b | 4888 | in *VALUE. */ |
a92713e6 RS |
4889 | |
4890 | static bfd_boolean | |
1a00e612 | 4891 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4892 | { |
4893 | expressionS ex; | |
4894 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4895 | |
a92713e6 RS |
4896 | if (!match_expression (arg, &ex, r)) |
4897 | return FALSE; | |
4898 | ||
4899 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4900 | *value = ex.X_add_number; |
4901 | else | |
4902 | { | |
c96425c5 MR |
4903 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
4904 | match_out_of_range (arg); | |
4905 | else | |
4906 | match_not_constant (arg); | |
1a00e612 | 4907 | return FALSE; |
a1d78564 | 4908 | } |
a92713e6 | 4909 | return TRUE; |
a1d78564 RS |
4910 | } |
4911 | ||
4912 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4913 | appears in instruction OPCODE. */ | |
4914 | ||
4915 | static unsigned int | |
4916 | convert_reg_type (const struct mips_opcode *opcode, | |
4917 | enum mips_reg_operand_type type) | |
4918 | { | |
4919 | switch (type) | |
4920 | { | |
4921 | case OP_REG_GP: | |
4922 | return RTYPE_NUM | RTYPE_GP; | |
4923 | ||
4924 | case OP_REG_FP: | |
4925 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4926 | FPR load, store or move (including moves to and from GPRs). */ | |
4927 | if ((mips_opts.ase & ASE_MDMX) | |
4928 | && (opcode->pinfo & FP_D) | |
43885403 | 4929 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4930 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4931 | | INSN_LOAD_COPROC |
67dc82bc | 4932 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4933 | | INSN_STORE_MEMORY))) |
4934 | return RTYPE_FPU | RTYPE_VEC; | |
4935 | return RTYPE_FPU; | |
4936 | ||
4937 | case OP_REG_CCC: | |
4938 | if (opcode->pinfo & (FP_D | FP_S)) | |
4939 | return RTYPE_CCC | RTYPE_FCC; | |
4940 | return RTYPE_CCC; | |
4941 | ||
4942 | case OP_REG_VEC: | |
4943 | if (opcode->membership & INSN_5400) | |
4944 | return RTYPE_FPU; | |
4945 | return RTYPE_FPU | RTYPE_VEC; | |
4946 | ||
4947 | case OP_REG_ACC: | |
4948 | return RTYPE_ACC; | |
4949 | ||
4950 | case OP_REG_COPRO: | |
4951 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4952 | return RTYPE_NUM | RTYPE_CP0; | |
4953 | return RTYPE_NUM; | |
4954 | ||
4955 | case OP_REG_HW: | |
4956 | return RTYPE_NUM; | |
14daeee3 RS |
4957 | |
4958 | case OP_REG_VI: | |
4959 | return RTYPE_NUM | RTYPE_VI; | |
4960 | ||
4961 | case OP_REG_VF: | |
4962 | return RTYPE_NUM | RTYPE_VF; | |
4963 | ||
4964 | case OP_REG_R5900_I: | |
4965 | return RTYPE_R5900_I; | |
4966 | ||
4967 | case OP_REG_R5900_Q: | |
4968 | return RTYPE_R5900_Q; | |
4969 | ||
4970 | case OP_REG_R5900_R: | |
4971 | return RTYPE_R5900_R; | |
4972 | ||
4973 | case OP_REG_R5900_ACC: | |
4974 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4975 | |
4976 | case OP_REG_MSA: | |
4977 | return RTYPE_MSA; | |
4978 | ||
4979 | case OP_REG_MSA_CTRL: | |
4980 | return RTYPE_NUM; | |
a1d78564 RS |
4981 | } |
4982 | abort (); | |
4983 | } | |
4984 | ||
4985 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
4986 | ||
4987 | static void | |
4988 | check_regno (struct mips_arg_info *arg, | |
4989 | enum mips_reg_operand_type type, unsigned int regno) | |
4990 | { | |
4991 | if (AT && type == OP_REG_GP && regno == AT) | |
4992 | arg->seen_at = TRUE; | |
4993 | ||
4994 | if (type == OP_REG_FP | |
4995 | && (regno & 1) != 0 | |
a1d78564 | 4996 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
4997 | { |
4998 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
4999 | so maintain a warning for FP32 but raise an error for the new | |
5000 | cases. */ | |
5001 | if (FPR_SIZE == 32) | |
5002 | as_warn (_("float register should be even, was %d"), regno); | |
5003 | else | |
5004 | as_bad (_("float register should be even, was %d"), regno); | |
5005 | } | |
a1d78564 RS |
5006 | |
5007 | if (type == OP_REG_CCC) | |
5008 | { | |
5009 | const char *name; | |
5010 | size_t length; | |
5011 | ||
5012 | name = arg->insn->insn_mo->name; | |
5013 | length = strlen (name); | |
5014 | if ((regno & 1) != 0 | |
5015 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5016 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5017 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5018 | name, regno); |
5019 | ||
5020 | if ((regno & 3) != 0 | |
5021 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5022 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5023 | name, regno); |
5024 | } | |
5025 | } | |
5026 | ||
a92713e6 RS |
5027 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5028 | a register of type TYPE. Return true on success, storing the register | |
5029 | number in *REGNO and warning about any dubious uses. */ | |
5030 | ||
5031 | static bfd_boolean | |
5032 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5033 | unsigned int symval, unsigned int *regno) | |
5034 | { | |
5035 | if (type == OP_REG_VEC) | |
5036 | symval = mips_prefer_vec_regno (symval); | |
5037 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5038 | return FALSE; | |
5039 | ||
5040 | *regno = symval & RNUM_MASK; | |
5041 | check_regno (arg, type, *regno); | |
5042 | return TRUE; | |
5043 | } | |
5044 | ||
5045 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5046 | Consume the token and return true on success, storing the register | |
5047 | number in *REGNO. Return false on failure. */ | |
5048 | ||
5049 | static bfd_boolean | |
5050 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5051 | unsigned int *regno) | |
5052 | { | |
5053 | if (arg->token->type == OT_REG | |
5054 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5055 | { | |
5056 | ++arg->token; | |
5057 | return TRUE; | |
5058 | } | |
5059 | return FALSE; | |
5060 | } | |
5061 | ||
5062 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5063 | Consume the token and return true on success, storing the register numbers | |
5064 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5065 | ||
5066 | static bfd_boolean | |
5067 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5068 | unsigned int *regno1, unsigned int *regno2) | |
5069 | { | |
5070 | if (match_reg (arg, type, regno1)) | |
5071 | { | |
5072 | *regno2 = *regno1; | |
5073 | return TRUE; | |
5074 | } | |
5075 | if (arg->token->type == OT_REG_RANGE | |
5076 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5077 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5078 | && *regno1 <= *regno2) | |
5079 | { | |
5080 | ++arg->token; | |
5081 | return TRUE; | |
5082 | } | |
5083 | return FALSE; | |
5084 | } | |
5085 | ||
a1d78564 RS |
5086 | /* OP_INT matcher. */ |
5087 | ||
a92713e6 | 5088 | static bfd_boolean |
a1d78564 | 5089 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5090 | const struct mips_operand *operand_base) |
a1d78564 RS |
5091 | { |
5092 | const struct mips_int_operand *operand; | |
3ccad066 | 5093 | unsigned int uval; |
a1d78564 RS |
5094 | int min_val, max_val, factor; |
5095 | offsetT sval; | |
a1d78564 RS |
5096 | |
5097 | operand = (const struct mips_int_operand *) operand_base; | |
5098 | factor = 1 << operand->shift; | |
3ccad066 RS |
5099 | min_val = mips_int_operand_min (operand); |
5100 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5101 | |
d436c1c2 RS |
5102 | if (operand_base->lsb == 0 |
5103 | && operand_base->size == 16 | |
5104 | && operand->shift == 0 | |
5105 | && operand->bias == 0 | |
5106 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5107 | { |
5108 | /* The operand can be relocated. */ | |
a92713e6 RS |
5109 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5110 | return FALSE; | |
5111 | ||
c96425c5 MR |
5112 | if (offset_expr.X_op == O_big) |
5113 | { | |
5114 | match_out_of_range (arg); | |
5115 | return FALSE; | |
5116 | } | |
5117 | ||
a92713e6 | 5118 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5119 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5120 | leave the relocation value in offset_expr and offset_relocs |
5121 | for the caller to process. */ | |
a92713e6 RS |
5122 | return TRUE; |
5123 | ||
5124 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5125 | { |
60f20e8b RS |
5126 | /* Accept non-constant operands if no later alternative matches, |
5127 | leaving it for the caller to process. */ | |
5128 | if (!arg->lax_match) | |
602b88e3 MR |
5129 | { |
5130 | match_not_constant (arg); | |
5131 | return FALSE; | |
5132 | } | |
a92713e6 RS |
5133 | offset_reloc[0] = BFD_RELOC_LO16; |
5134 | return TRUE; | |
a1d78564 | 5135 | } |
a92713e6 | 5136 | |
a1d78564 RS |
5137 | /* Clear the global state; we're going to install the operand |
5138 | ourselves. */ | |
a92713e6 | 5139 | sval = offset_expr.X_add_number; |
a1d78564 | 5140 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5141 | |
5142 | /* For compatibility with older assemblers, we accept | |
5143 | 0x8000-0xffff as signed 16-bit numbers when only | |
5144 | signed numbers are allowed. */ | |
5145 | if (sval > max_val) | |
5146 | { | |
5147 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5148 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5149 | { |
5150 | match_out_of_range (arg); | |
5151 | return FALSE; | |
5152 | } | |
60f20e8b | 5153 | } |
a1d78564 RS |
5154 | } |
5155 | else | |
5156 | { | |
1a00e612 | 5157 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5158 | return FALSE; |
a1d78564 RS |
5159 | } |
5160 | ||
5161 | arg->last_op_int = sval; | |
5162 | ||
1a00e612 | 5163 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5164 | { |
1a00e612 RS |
5165 | match_out_of_range (arg); |
5166 | return FALSE; | |
a1d78564 RS |
5167 | } |
5168 | ||
5169 | uval = (unsigned int) sval >> operand->shift; | |
5170 | uval -= operand->bias; | |
5171 | ||
5172 | /* Handle -mfix-cn63xxp1. */ | |
5173 | if (arg->opnum == 1 | |
5174 | && mips_fix_cn63xxp1 | |
5175 | && !mips_opts.micromips | |
5176 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5177 | switch (uval) | |
5178 | { | |
5179 | case 5: | |
5180 | case 25: | |
5181 | case 26: | |
5182 | case 27: | |
5183 | case 28: | |
5184 | case 29: | |
5185 | case 30: | |
5186 | case 31: | |
5187 | /* These are ok. */ | |
5188 | break; | |
5189 | ||
5190 | default: | |
5191 | /* The rest must be changed to 28. */ | |
5192 | uval = 28; | |
5193 | break; | |
5194 | } | |
5195 | ||
5196 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5197 | return TRUE; |
a1d78564 RS |
5198 | } |
5199 | ||
5200 | /* OP_MAPPED_INT matcher. */ | |
5201 | ||
a92713e6 | 5202 | static bfd_boolean |
a1d78564 | 5203 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5204 | const struct mips_operand *operand_base) |
a1d78564 RS |
5205 | { |
5206 | const struct mips_mapped_int_operand *operand; | |
5207 | unsigned int uval, num_vals; | |
5208 | offsetT sval; | |
5209 | ||
5210 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5211 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5212 | return FALSE; |
a1d78564 RS |
5213 | |
5214 | num_vals = 1 << operand_base->size; | |
5215 | for (uval = 0; uval < num_vals; uval++) | |
5216 | if (operand->int_map[uval] == sval) | |
5217 | break; | |
5218 | if (uval == num_vals) | |
1a00e612 RS |
5219 | { |
5220 | match_out_of_range (arg); | |
5221 | return FALSE; | |
5222 | } | |
a1d78564 RS |
5223 | |
5224 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5225 | return TRUE; |
a1d78564 RS |
5226 | } |
5227 | ||
5228 | /* OP_MSB matcher. */ | |
5229 | ||
a92713e6 | 5230 | static bfd_boolean |
a1d78564 | 5231 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5232 | const struct mips_operand *operand_base) |
a1d78564 RS |
5233 | { |
5234 | const struct mips_msb_operand *operand; | |
5235 | int min_val, max_val, max_high; | |
5236 | offsetT size, sval, high; | |
5237 | ||
5238 | operand = (const struct mips_msb_operand *) operand_base; | |
5239 | min_val = operand->bias; | |
5240 | max_val = min_val + (1 << operand_base->size) - 1; | |
5241 | max_high = operand->opsize; | |
5242 | ||
1a00e612 | 5243 | if (!match_const_int (arg, &size)) |
a92713e6 | 5244 | return FALSE; |
a1d78564 RS |
5245 | |
5246 | high = size + arg->last_op_int; | |
5247 | sval = operand->add_lsb ? high : size; | |
5248 | ||
5249 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5250 | { | |
1a00e612 RS |
5251 | match_out_of_range (arg); |
5252 | return FALSE; | |
a1d78564 RS |
5253 | } |
5254 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5255 | return TRUE; |
a1d78564 RS |
5256 | } |
5257 | ||
5258 | /* OP_REG matcher. */ | |
5259 | ||
a92713e6 | 5260 | static bfd_boolean |
a1d78564 | 5261 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5262 | const struct mips_operand *operand_base) |
a1d78564 RS |
5263 | { |
5264 | const struct mips_reg_operand *operand; | |
a92713e6 | 5265 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5266 | |
5267 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5268 | if (!match_reg (arg, operand->reg_type, ®no)) |
5269 | return FALSE; | |
a1d78564 RS |
5270 | |
5271 | if (operand->reg_map) | |
5272 | { | |
5273 | num_vals = 1 << operand->root.size; | |
5274 | for (uval = 0; uval < num_vals; uval++) | |
5275 | if (operand->reg_map[uval] == regno) | |
5276 | break; | |
5277 | if (num_vals == uval) | |
a92713e6 | 5278 | return FALSE; |
a1d78564 RS |
5279 | } |
5280 | else | |
5281 | uval = regno; | |
5282 | ||
a1d78564 RS |
5283 | arg->last_regno = regno; |
5284 | if (arg->opnum == 1) | |
5285 | arg->dest_regno = regno; | |
5286 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5287 | return TRUE; |
a1d78564 RS |
5288 | } |
5289 | ||
5290 | /* OP_REG_PAIR matcher. */ | |
5291 | ||
a92713e6 | 5292 | static bfd_boolean |
a1d78564 | 5293 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5294 | const struct mips_operand *operand_base) |
a1d78564 RS |
5295 | { |
5296 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5297 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5298 | |
5299 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5300 | if (!match_reg (arg, operand->reg_type, ®no1) |
5301 | || !match_char (arg, ',') | |
5302 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5303 | return FALSE; | |
a1d78564 RS |
5304 | |
5305 | num_vals = 1 << operand_base->size; | |
5306 | for (uval = 0; uval < num_vals; uval++) | |
5307 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5308 | break; | |
5309 | if (uval == num_vals) | |
a92713e6 | 5310 | return FALSE; |
a1d78564 | 5311 | |
a1d78564 | 5312 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5313 | return TRUE; |
a1d78564 RS |
5314 | } |
5315 | ||
5316 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5317 | ||
a92713e6 RS |
5318 | static bfd_boolean |
5319 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5320 | { |
a92713e6 RS |
5321 | bfd_reloc_code_real_type r[3]; |
5322 | ||
5323 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5324 | } |
5325 | ||
5326 | /* OP_PERF_REG matcher. */ | |
5327 | ||
a92713e6 | 5328 | static bfd_boolean |
a1d78564 | 5329 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5330 | const struct mips_operand *operand) |
a1d78564 RS |
5331 | { |
5332 | offsetT sval; | |
5333 | ||
1a00e612 | 5334 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5335 | return FALSE; |
a1d78564 RS |
5336 | |
5337 | if (sval != 0 | |
5338 | && (sval != 1 | |
5339 | || (mips_opts.arch == CPU_R5900 | |
5340 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5341 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5342 | { | |
1a00e612 RS |
5343 | set_insn_error (arg->argnum, _("invalid performance register")); |
5344 | return FALSE; | |
a1d78564 RS |
5345 | } |
5346 | ||
5347 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5348 | return TRUE; |
a1d78564 RS |
5349 | } |
5350 | ||
5351 | /* OP_ADDIUSP matcher. */ | |
5352 | ||
a92713e6 | 5353 | static bfd_boolean |
a1d78564 | 5354 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5355 | const struct mips_operand *operand) |
a1d78564 RS |
5356 | { |
5357 | offsetT sval; | |
5358 | unsigned int uval; | |
5359 | ||
1a00e612 | 5360 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5361 | return FALSE; |
a1d78564 RS |
5362 | |
5363 | if (sval % 4) | |
1a00e612 RS |
5364 | { |
5365 | match_out_of_range (arg); | |
5366 | return FALSE; | |
5367 | } | |
a1d78564 RS |
5368 | |
5369 | sval /= 4; | |
5370 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5371 | { |
5372 | match_out_of_range (arg); | |
5373 | return FALSE; | |
5374 | } | |
a1d78564 RS |
5375 | |
5376 | uval = (unsigned int) sval; | |
5377 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5378 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5379 | return TRUE; |
a1d78564 RS |
5380 | } |
5381 | ||
5382 | /* OP_CLO_CLZ_DEST matcher. */ | |
5383 | ||
a92713e6 | 5384 | static bfd_boolean |
a1d78564 | 5385 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5386 | const struct mips_operand *operand) |
a1d78564 RS |
5387 | { |
5388 | unsigned int regno; | |
5389 | ||
a92713e6 RS |
5390 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5391 | return FALSE; | |
a1d78564 | 5392 | |
a1d78564 | 5393 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5394 | return TRUE; |
a1d78564 RS |
5395 | } |
5396 | ||
7361da2c AB |
5397 | /* OP_CHECK_PREV matcher. */ |
5398 | ||
5399 | static bfd_boolean | |
5400 | match_check_prev_operand (struct mips_arg_info *arg, | |
5401 | const struct mips_operand *operand_base) | |
5402 | { | |
5403 | const struct mips_check_prev_operand *operand; | |
5404 | unsigned int regno; | |
5405 | ||
5406 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5407 | ||
5408 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5409 | return FALSE; | |
5410 | ||
5411 | if (!operand->zero_ok && regno == 0) | |
5412 | return FALSE; | |
5413 | ||
5414 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5415 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5416 | || (operand->equal_ok && regno == arg->last_regno)) | |
5417 | { | |
5418 | arg->last_regno = regno; | |
5419 | insn_insert_operand (arg->insn, operand_base, regno); | |
5420 | return TRUE; | |
5421 | } | |
5422 | ||
5423 | return FALSE; | |
5424 | } | |
5425 | ||
5426 | /* OP_SAME_RS_RT matcher. */ | |
5427 | ||
5428 | static bfd_boolean | |
5429 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5430 | const struct mips_operand *operand) | |
5431 | { | |
5432 | unsigned int regno; | |
5433 | ||
5434 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5435 | return FALSE; | |
5436 | ||
5437 | if (regno == 0) | |
5438 | { | |
5439 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5440 | return FALSE; | |
5441 | } | |
5442 | ||
5443 | arg->last_regno = regno; | |
5444 | ||
5445 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5446 | return TRUE; | |
5447 | } | |
5448 | ||
a1d78564 RS |
5449 | /* OP_LWM_SWM_LIST matcher. */ |
5450 | ||
a92713e6 | 5451 | static bfd_boolean |
a1d78564 | 5452 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5453 | const struct mips_operand *operand) |
a1d78564 | 5454 | { |
a92713e6 RS |
5455 | unsigned int reglist, sregs, ra, regno1, regno2; |
5456 | struct mips_arg_info reset; | |
a1d78564 | 5457 | |
a92713e6 RS |
5458 | reglist = 0; |
5459 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5460 | return FALSE; | |
5461 | do | |
5462 | { | |
5463 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5464 | { | |
5465 | reglist |= 1 << FP; | |
5466 | regno2 = S7; | |
5467 | } | |
5468 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5469 | reset = *arg; | |
5470 | } | |
5471 | while (match_char (arg, ',') | |
5472 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5473 | *arg = reset; | |
a1d78564 RS |
5474 | |
5475 | if (operand->size == 2) | |
5476 | { | |
5477 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5478 | ||
5479 | s0, ra | |
5480 | s0, s1, ra, s2, s3 | |
5481 | s0-s2, ra | |
5482 | ||
5483 | and any permutations of these. */ | |
5484 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5485 | return FALSE; |
a1d78564 RS |
5486 | |
5487 | sregs = (reglist >> 17) & 7; | |
5488 | ra = 0; | |
5489 | } | |
5490 | else | |
5491 | { | |
5492 | /* The list must include at least one of ra and s0-sN, | |
5493 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5494 | which are $23 and $30 respectively.) E.g.: | |
5495 | ||
5496 | ra | |
5497 | s0 | |
5498 | ra, s0, s1, s2 | |
5499 | s0-s8 | |
5500 | s0-s5, ra | |
5501 | ||
5502 | and any permutations of these. */ | |
5503 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5504 | return FALSE; |
a1d78564 RS |
5505 | |
5506 | ra = (reglist >> 27) & 0x10; | |
5507 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5508 | } | |
5509 | sregs += 1; | |
5510 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5511 | return FALSE; |
a1d78564 RS |
5512 | |
5513 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5514 | return TRUE; |
a1d78564 RS |
5515 | } |
5516 | ||
364215c8 RS |
5517 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5518 | ||
a92713e6 | 5519 | static unsigned int |
364215c8 | 5520 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5521 | const struct mips_operand *operand) |
364215c8 RS |
5522 | { |
5523 | unsigned int mask; | |
5524 | bfd_boolean is_exit; | |
5525 | ||
5526 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5527 | are different. */ | |
5528 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5529 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5530 | do |
364215c8 RS |
5531 | { |
5532 | unsigned int regno1, regno2; | |
5533 | bfd_boolean is_freg; | |
5534 | ||
a92713e6 | 5535 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5536 | is_freg = FALSE; |
a92713e6 | 5537 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5538 | is_freg = TRUE; |
5539 | else | |
a92713e6 | 5540 | return FALSE; |
364215c8 RS |
5541 | |
5542 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5543 | { | |
5544 | mask &= ~(7 << 3); | |
5545 | mask |= (5 + regno2) << 3; | |
5546 | } | |
5547 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5548 | mask |= (regno2 - 3) << 3; | |
5549 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5550 | mask |= (regno2 - 15) << 1; | |
5551 | else if (regno1 == RA && regno2 == RA) | |
5552 | mask |= 1; | |
5553 | else | |
a92713e6 | 5554 | return FALSE; |
364215c8 | 5555 | } |
a92713e6 RS |
5556 | while (match_char (arg, ',')); |
5557 | ||
364215c8 | 5558 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5559 | return TRUE; |
364215c8 RS |
5560 | } |
5561 | ||
38bf472a MR |
5562 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5563 | the argument register mask AMASK, the number of static registers | |
5564 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5565 | respectively, and the frame size FRAME_SIZE. */ | |
5566 | ||
5567 | static unsigned int | |
5568 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5569 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5570 | unsigned int frame_size) | |
5571 | { | |
5572 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5573 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5574 | } | |
5575 | ||
5576 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5577 | argument register mask AMASK, the number of static registers saved | |
5578 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5579 | respectively, and the frame size FRAME_SIZE. */ | |
5580 | ||
5581 | static unsigned int | |
5582 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5583 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5584 | unsigned int frame_size) | |
5585 | { | |
5586 | unsigned int args; | |
5587 | ||
5588 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5589 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5590 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5591 | | ((frame_size & 0xf0) << 16)); | |
5592 | return args; | |
5593 | } | |
5594 | ||
364215c8 RS |
5595 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5596 | ||
a92713e6 RS |
5597 | static bfd_boolean |
5598 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5599 | { |
5600 | unsigned int opcode, args, statics, sregs; | |
5601 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5602 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5603 | offsetT frame_size; |
364215c8 | 5604 | |
364215c8 RS |
5605 | opcode = arg->insn->insn_opcode; |
5606 | frame_size = 0; | |
5607 | num_frame_sizes = 0; | |
5608 | args = 0; | |
5609 | statics = 0; | |
5610 | sregs = 0; | |
38bf472a MR |
5611 | ra = 0; |
5612 | s0 = 0; | |
5613 | s1 = 0; | |
a92713e6 | 5614 | do |
364215c8 RS |
5615 | { |
5616 | unsigned int regno1, regno2; | |
5617 | ||
a92713e6 | 5618 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5619 | { |
5620 | /* Handle the frame size. */ | |
1a00e612 | 5621 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5622 | return FALSE; |
364215c8 | 5623 | num_frame_sizes += 1; |
364215c8 RS |
5624 | } |
5625 | else | |
5626 | { | |
a92713e6 RS |
5627 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5628 | return FALSE; | |
364215c8 RS |
5629 | |
5630 | while (regno1 <= regno2) | |
5631 | { | |
5632 | if (regno1 >= 4 && regno1 <= 7) | |
5633 | { | |
5634 | if (num_frame_sizes == 0) | |
5635 | /* args $a0-$a3 */ | |
5636 | args |= 1 << (regno1 - 4); | |
5637 | else | |
5638 | /* statics $a0-$a3 */ | |
5639 | statics |= 1 << (regno1 - 4); | |
5640 | } | |
5641 | else if (regno1 >= 16 && regno1 <= 23) | |
5642 | /* $s0-$s7 */ | |
5643 | sregs |= 1 << (regno1 - 16); | |
5644 | else if (regno1 == 30) | |
5645 | /* $s8 */ | |
5646 | sregs |= 1 << 8; | |
5647 | else if (regno1 == 31) | |
5648 | /* Add $ra to insn. */ | |
38bf472a | 5649 | ra = 1; |
364215c8 | 5650 | else |
a92713e6 | 5651 | return FALSE; |
364215c8 RS |
5652 | regno1 += 1; |
5653 | if (regno1 == 24) | |
5654 | regno1 = 30; | |
5655 | } | |
5656 | } | |
364215c8 | 5657 | } |
a92713e6 | 5658 | while (match_char (arg, ',')); |
364215c8 RS |
5659 | |
5660 | /* Encode args/statics combination. */ | |
5661 | if (args & statics) | |
a92713e6 | 5662 | return FALSE; |
364215c8 RS |
5663 | else if (args == 0xf) |
5664 | /* All $a0-$a3 are args. */ | |
38bf472a | 5665 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5666 | else if (statics == 0xf) |
5667 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5668 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5669 | else |
5670 | { | |
5671 | /* Count arg registers. */ | |
5672 | num_args = 0; | |
5673 | while (args & 0x1) | |
5674 | { | |
5675 | args >>= 1; | |
5676 | num_args += 1; | |
5677 | } | |
5678 | if (args != 0) | |
a92713e6 | 5679 | return FALSE; |
364215c8 RS |
5680 | |
5681 | /* Count static registers. */ | |
5682 | num_statics = 0; | |
5683 | while (statics & 0x8) | |
5684 | { | |
5685 | statics = (statics << 1) & 0xf; | |
5686 | num_statics += 1; | |
5687 | } | |
5688 | if (statics != 0) | |
a92713e6 | 5689 | return FALSE; |
364215c8 RS |
5690 | |
5691 | /* Encode args/statics. */ | |
38bf472a | 5692 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5693 | } |
5694 | ||
5695 | /* Encode $s0/$s1. */ | |
5696 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5697 | s0 = 1; |
364215c8 | 5698 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5699 | s1 = 1; |
364215c8 RS |
5700 | sregs >>= 2; |
5701 | ||
5702 | /* Encode $s2-$s8. */ | |
5703 | num_sregs = 0; | |
5704 | while (sregs & 1) | |
5705 | { | |
5706 | sregs >>= 1; | |
5707 | num_sregs += 1; | |
5708 | } | |
5709 | if (sregs != 0) | |
a92713e6 | 5710 | return FALSE; |
364215c8 RS |
5711 | |
5712 | /* Encode frame size. */ | |
5713 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5714 | { |
5715 | set_insn_error (arg->argnum, _("missing frame size")); | |
5716 | return FALSE; | |
5717 | } | |
5718 | if (num_frame_sizes > 1) | |
5719 | { | |
5720 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5721 | return FALSE; | |
5722 | } | |
5723 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5724 | { | |
5725 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5726 | return FALSE; | |
5727 | } | |
38bf472a | 5728 | frame_size /= 8; |
364215c8 | 5729 | |
364215c8 | 5730 | /* Finally build the instruction. */ |
38bf472a MR |
5731 | if (mips_opts.mips16) |
5732 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5733 | frame_size); | |
5734 | else if (!mips_opts.micromips) | |
5735 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5736 | frame_size); | |
5737 | else | |
5738 | abort (); | |
5739 | ||
364215c8 | 5740 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5741 | return TRUE; |
364215c8 RS |
5742 | } |
5743 | ||
a1d78564 RS |
5744 | /* OP_MDMX_IMM_REG matcher. */ |
5745 | ||
a92713e6 | 5746 | static bfd_boolean |
a1d78564 | 5747 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5748 | const struct mips_operand *operand) |
a1d78564 | 5749 | { |
a92713e6 | 5750 | unsigned int regno, uval; |
a1d78564 RS |
5751 | bfd_boolean is_qh; |
5752 | const struct mips_opcode *opcode; | |
5753 | ||
5754 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5755 | instruction. Start out with that bit in place. */ | |
5756 | opcode = arg->insn->insn_mo; | |
5757 | uval = mips_extract_operand (operand, opcode->match); | |
5758 | is_qh = (uval != 0); | |
5759 | ||
56d438b1 | 5760 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5761 | { |
5762 | if ((opcode->membership & INSN_5400) | |
5763 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5764 | { | |
1a00e612 RS |
5765 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5766 | arg->argnum); | |
5767 | return FALSE; | |
a1d78564 RS |
5768 | } |
5769 | ||
56d438b1 CF |
5770 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5771 | return FALSE; | |
5772 | ++arg->token; | |
5773 | ||
a1d78564 RS |
5774 | /* Check whether this is a vector register or a broadcast of |
5775 | a single element. */ | |
56d438b1 | 5776 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5777 | { |
56d438b1 | 5778 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5779 | { |
1a00e612 RS |
5780 | set_insn_error (arg->argnum, _("invalid element selector")); |
5781 | return FALSE; | |
a1d78564 | 5782 | } |
56d438b1 CF |
5783 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5784 | ++arg->token; | |
a1d78564 RS |
5785 | } |
5786 | else | |
5787 | { | |
5788 | /* A full vector. */ | |
5789 | if ((opcode->membership & INSN_5400) | |
5790 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5791 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5792 | { | |
1a00e612 RS |
5793 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5794 | arg->argnum); | |
5795 | return FALSE; | |
a1d78564 RS |
5796 | } |
5797 | ||
5798 | if (is_qh) | |
5799 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5800 | else | |
5801 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5802 | } | |
a1d78564 RS |
5803 | uval |= regno; |
5804 | } | |
5805 | else | |
5806 | { | |
5807 | offsetT sval; | |
5808 | ||
1a00e612 | 5809 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5810 | return FALSE; |
a1d78564 RS |
5811 | if (sval < 0 || sval > 31) |
5812 | { | |
1a00e612 RS |
5813 | match_out_of_range (arg); |
5814 | return FALSE; | |
a1d78564 RS |
5815 | } |
5816 | uval |= (sval & 31); | |
5817 | if (is_qh) | |
5818 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5819 | else | |
5820 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5821 | } | |
5822 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5823 | return TRUE; |
a1d78564 RS |
5824 | } |
5825 | ||
56d438b1 CF |
5826 | /* OP_IMM_INDEX matcher. */ |
5827 | ||
5828 | static bfd_boolean | |
5829 | match_imm_index_operand (struct mips_arg_info *arg, | |
5830 | const struct mips_operand *operand) | |
5831 | { | |
5832 | unsigned int max_val; | |
5833 | ||
5834 | if (arg->token->type != OT_INTEGER_INDEX) | |
5835 | return FALSE; | |
5836 | ||
5837 | max_val = (1 << operand->size) - 1; | |
5838 | if (arg->token->u.index > max_val) | |
5839 | { | |
5840 | match_out_of_range (arg); | |
5841 | return FALSE; | |
5842 | } | |
5843 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5844 | ++arg->token; | |
5845 | return TRUE; | |
5846 | } | |
5847 | ||
5848 | /* OP_REG_INDEX matcher. */ | |
5849 | ||
5850 | static bfd_boolean | |
5851 | match_reg_index_operand (struct mips_arg_info *arg, | |
5852 | const struct mips_operand *operand) | |
5853 | { | |
5854 | unsigned int regno; | |
5855 | ||
5856 | if (arg->token->type != OT_REG_INDEX) | |
5857 | return FALSE; | |
5858 | ||
5859 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5860 | return FALSE; | |
5861 | ||
5862 | insn_insert_operand (arg->insn, operand, regno); | |
5863 | ++arg->token; | |
5864 | return TRUE; | |
5865 | } | |
5866 | ||
a1d78564 RS |
5867 | /* OP_PC matcher. */ |
5868 | ||
a92713e6 RS |
5869 | static bfd_boolean |
5870 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5871 | { |
a92713e6 RS |
5872 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5873 | { | |
5874 | ++arg->token; | |
5875 | return TRUE; | |
5876 | } | |
5877 | return FALSE; | |
a1d78564 RS |
5878 | } |
5879 | ||
25499ac7 MR |
5880 | /* OP_REG28 matcher. */ |
5881 | ||
5882 | static bfd_boolean | |
5883 | match_reg28_operand (struct mips_arg_info *arg) | |
5884 | { | |
5885 | unsigned int regno; | |
5886 | ||
5887 | if (arg->token->type == OT_REG | |
5888 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
5889 | && regno == GP) | |
5890 | { | |
5891 | ++arg->token; | |
5892 | return TRUE; | |
5893 | } | |
5894 | return FALSE; | |
5895 | } | |
5896 | ||
7361da2c AB |
5897 | /* OP_NON_ZERO_REG matcher. */ |
5898 | ||
5899 | static bfd_boolean | |
5900 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5901 | const struct mips_operand *operand) | |
5902 | { | |
5903 | unsigned int regno; | |
5904 | ||
5905 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5906 | return FALSE; | |
5907 | ||
5908 | if (regno == 0) | |
5909 | return FALSE; | |
5910 | ||
5911 | arg->last_regno = regno; | |
5912 | insn_insert_operand (arg->insn, operand, regno); | |
5913 | return TRUE; | |
5914 | } | |
5915 | ||
a1d78564 RS |
5916 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5917 | register that we need to match. */ | |
5918 | ||
a92713e6 RS |
5919 | static bfd_boolean |
5920 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5921 | { |
5922 | unsigned int regno; | |
5923 | ||
a92713e6 | 5924 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5925 | } |
5926 | ||
89565f1b RS |
5927 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
5928 | the length of the value in bytes (4 for float, 8 for double) and | |
5929 | USING_GPRS says whether the destination is a GPR rather than an FPR. | |
5930 | ||
5931 | Return the constant in IMM and OFFSET as follows: | |
5932 | ||
5933 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5934 | OFFSET to the memory address. | |
5935 | ||
5936 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5937 | set IMM to the O_constant to load into the high register and OFFSET | |
5938 | to the corresponding value for the low register. | |
5939 | ||
5940 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5941 | ||
5942 | These constants only appear as the last operand in an instruction, | |
5943 | and every instruction that accepts them in any variant accepts them | |
5944 | in all variants. This means we don't have to worry about backing out | |
5945 | any changes if the instruction does not match. We just match | |
5946 | unconditionally and report an error if the constant is invalid. */ | |
5947 | ||
a92713e6 RS |
5948 | static bfd_boolean |
5949 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5950 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5951 | { |
a92713e6 | 5952 | char *p; |
89565f1b RS |
5953 | segT seg, new_seg; |
5954 | subsegT subseg; | |
5955 | const char *newname; | |
a92713e6 | 5956 | unsigned char *data; |
89565f1b RS |
5957 | |
5958 | /* Where the constant is placed is based on how the MIPS assembler | |
5959 | does things: | |
5960 | ||
5961 | length == 4 && using_gprs -- immediate value only | |
5962 | length == 8 && using_gprs -- .rdata or immediate value | |
5963 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5964 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5965 | ||
5966 | The .lit4 and .lit8 sections are only used if permitted by the | |
5967 | -G argument. */ | |
a92713e6 | 5968 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5969 | { |
5970 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5971 | return FALSE; | |
5972 | } | |
a92713e6 RS |
5973 | |
5974 | gas_assert (arg->token->u.flt.length == length); | |
5975 | data = arg->token->u.flt.data; | |
5976 | ++arg->token; | |
89565f1b RS |
5977 | |
5978 | /* Handle 32-bit constants for which an immediate value is best. */ | |
5979 | if (length == 4 | |
5980 | && (using_gprs | |
5981 | || g_switch_value < 4 | |
5982 | || (data[0] == 0 && data[1] == 0) | |
5983 | || (data[2] == 0 && data[3] == 0))) | |
5984 | { | |
5985 | imm->X_op = O_constant; | |
5986 | if (!target_big_endian) | |
5987 | imm->X_add_number = bfd_getl32 (data); | |
5988 | else | |
5989 | imm->X_add_number = bfd_getb32 (data); | |
5990 | offset->X_op = O_absent; | |
a92713e6 | 5991 | return TRUE; |
89565f1b RS |
5992 | } |
5993 | ||
5994 | /* Handle 64-bit constants for which an immediate value is best. */ | |
5995 | if (length == 8 | |
5996 | && !mips_disable_float_construction | |
351cdf24 MF |
5997 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
5998 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
5999 | Unlike most tests for 32-bit floating-point registers this check | |
6000 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6001 | permit 64-bit moves without MXHC1. | |
6002 | Force the constant into memory otherwise. */ | |
6003 | && (using_gprs | |
6004 | || GPR_SIZE == 64 | |
6005 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6006 | || FPR_SIZE == 32) | |
89565f1b RS |
6007 | && ((data[0] == 0 && data[1] == 0) |
6008 | || (data[2] == 0 && data[3] == 0)) | |
6009 | && ((data[4] == 0 && data[5] == 0) | |
6010 | || (data[6] == 0 && data[7] == 0))) | |
6011 | { | |
6012 | /* The value is simple enough to load with a couple of instructions. | |
6013 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6014 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6015 | 64 bit constant. */ | |
351cdf24 | 6016 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6017 | { |
6018 | imm->X_op = O_constant; | |
6019 | offset->X_op = O_constant; | |
6020 | if (!target_big_endian) | |
6021 | { | |
6022 | imm->X_add_number = bfd_getl32 (data + 4); | |
6023 | offset->X_add_number = bfd_getl32 (data); | |
6024 | } | |
6025 | else | |
6026 | { | |
6027 | imm->X_add_number = bfd_getb32 (data); | |
6028 | offset->X_add_number = bfd_getb32 (data + 4); | |
6029 | } | |
6030 | if (offset->X_add_number == 0) | |
6031 | offset->X_op = O_absent; | |
6032 | } | |
6033 | else | |
6034 | { | |
6035 | imm->X_op = O_constant; | |
6036 | if (!target_big_endian) | |
6037 | imm->X_add_number = bfd_getl64 (data); | |
6038 | else | |
6039 | imm->X_add_number = bfd_getb64 (data); | |
6040 | offset->X_op = O_absent; | |
6041 | } | |
a92713e6 | 6042 | return TRUE; |
89565f1b RS |
6043 | } |
6044 | ||
6045 | /* Switch to the right section. */ | |
6046 | seg = now_seg; | |
6047 | subseg = now_subseg; | |
6048 | if (length == 4) | |
6049 | { | |
6050 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6051 | newname = ".lit4"; | |
6052 | } | |
6053 | else | |
6054 | { | |
6055 | if (using_gprs || g_switch_value < 8) | |
6056 | newname = RDATA_SECTION_NAME; | |
6057 | else | |
6058 | newname = ".lit8"; | |
6059 | } | |
6060 | ||
6061 | new_seg = subseg_new (newname, (subsegT) 0); | |
6062 | bfd_set_section_flags (stdoutput, new_seg, | |
6063 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6064 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6065 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6066 | record_alignment (new_seg, 4); | |
6067 | else | |
6068 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6069 | if (seg == now_seg) | |
1661c76c | 6070 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6071 | |
6072 | /* Set the argument to the current address in the section. */ | |
6073 | imm->X_op = O_absent; | |
6074 | offset->X_op = O_symbol; | |
6075 | offset->X_add_symbol = symbol_temp_new_now (); | |
6076 | offset->X_add_number = 0; | |
6077 | ||
6078 | /* Put the floating point number into the section. */ | |
6079 | p = frag_more (length); | |
6080 | memcpy (p, data, length); | |
6081 | ||
6082 | /* Switch back to the original section. */ | |
6083 | subseg_set (seg, subseg); | |
a92713e6 | 6084 | return TRUE; |
89565f1b RS |
6085 | } |
6086 | ||
14daeee3 RS |
6087 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6088 | them. */ | |
6089 | ||
6090 | static bfd_boolean | |
6091 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6092 | const struct mips_operand *operand, | |
6093 | bfd_boolean match_p) | |
6094 | { | |
6095 | unsigned int uval; | |
6096 | ||
6097 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6098 | (with X being 0). */ | |
6099 | gas_assert (operand->size == 2 || operand->size == 4); | |
6100 | ||
ee5734f0 | 6101 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6102 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6103 | return match_p; |
14daeee3 RS |
6104 | |
6105 | uval = arg->token->u.channels; | |
6106 | if (operand->size == 2) | |
6107 | { | |
6108 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6109 | if ((uval & -uval) != uval) | |
6110 | return FALSE; | |
6111 | uval = 4 - ffs (uval); | |
6112 | } | |
6113 | ||
6114 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6115 | return FALSE; | |
6116 | ||
6117 | ++arg->token; | |
6118 | if (!match_p) | |
6119 | insn_insert_operand (arg->insn, operand, uval); | |
6120 | return TRUE; | |
6121 | } | |
6122 | ||
a1d78564 RS |
6123 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
6124 | of the argument text if the match is successful, otherwise return null. */ | |
6125 | ||
a92713e6 | 6126 | static bfd_boolean |
a1d78564 | 6127 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6128 | const struct mips_operand *operand) |
a1d78564 RS |
6129 | { |
6130 | switch (operand->type) | |
6131 | { | |
6132 | case OP_INT: | |
a92713e6 | 6133 | return match_int_operand (arg, operand); |
a1d78564 RS |
6134 | |
6135 | case OP_MAPPED_INT: | |
a92713e6 | 6136 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6137 | |
6138 | case OP_MSB: | |
a92713e6 | 6139 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6140 | |
6141 | case OP_REG: | |
0f35dbc4 | 6142 | case OP_OPTIONAL_REG: |
a92713e6 | 6143 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6144 | |
6145 | case OP_REG_PAIR: | |
a92713e6 | 6146 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6147 | |
6148 | case OP_PCREL: | |
a92713e6 | 6149 | return match_pcrel_operand (arg); |
a1d78564 RS |
6150 | |
6151 | case OP_PERF_REG: | |
a92713e6 | 6152 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6153 | |
6154 | case OP_ADDIUSP_INT: | |
a92713e6 | 6155 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6156 | |
6157 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6158 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6159 | |
6160 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6161 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6162 | |
6163 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6164 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6165 | |
a1d78564 | 6166 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6167 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6168 | |
6169 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6170 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6171 | |
6172 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6173 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6174 | |
6175 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6176 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6177 | |
6178 | case OP_PC: | |
a92713e6 | 6179 | return match_pc_operand (arg); |
14daeee3 | 6180 | |
25499ac7 MR |
6181 | case OP_REG28: |
6182 | return match_reg28_operand (arg); | |
6183 | ||
14daeee3 RS |
6184 | case OP_VU0_SUFFIX: |
6185 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6186 | ||
6187 | case OP_VU0_MATCH_SUFFIX: | |
6188 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6189 | |
6190 | case OP_IMM_INDEX: | |
6191 | return match_imm_index_operand (arg, operand); | |
6192 | ||
6193 | case OP_REG_INDEX: | |
6194 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6195 | |
6196 | case OP_SAME_RS_RT: | |
6197 | return match_same_rs_rt_operand (arg, operand); | |
6198 | ||
6199 | case OP_CHECK_PREV: | |
6200 | return match_check_prev_operand (arg, operand); | |
6201 | ||
6202 | case OP_NON_ZERO_REG: | |
6203 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6204 | } |
6205 | abort (); | |
6206 | } | |
6207 | ||
6208 | /* ARG is the state after successfully matching an instruction. | |
6209 | Issue any queued-up warnings. */ | |
6210 | ||
6211 | static void | |
6212 | check_completed_insn (struct mips_arg_info *arg) | |
6213 | { | |
6214 | if (arg->seen_at) | |
6215 | { | |
6216 | if (AT == ATREG) | |
1661c76c | 6217 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6218 | else |
1661c76c | 6219 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6220 | } |
6221 | } | |
a1d78564 | 6222 | |
85fcb30f RS |
6223 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6224 | ||
6225 | static bfd_boolean | |
6226 | reg_needs_delay (unsigned int reg) | |
6227 | { | |
6228 | unsigned long prev_pinfo; | |
6229 | ||
6230 | prev_pinfo = history[0].insn_mo->pinfo; | |
6231 | if (!mips_opts.noreorder | |
67dc82bc | 6232 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6233 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6234 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6235 | return TRUE; | |
6236 | ||
6237 | return FALSE; | |
6238 | } | |
6239 | ||
71400594 RS |
6240 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6241 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6242 | by VR4120 errata. */ | |
4d7206a2 | 6243 | |
71400594 RS |
6244 | static unsigned int |
6245 | classify_vr4120_insn (const char *name) | |
252b5132 | 6246 | { |
71400594 RS |
6247 | if (strncmp (name, "macc", 4) == 0) |
6248 | return FIX_VR4120_MACC; | |
6249 | if (strncmp (name, "dmacc", 5) == 0) | |
6250 | return FIX_VR4120_DMACC; | |
6251 | if (strncmp (name, "mult", 4) == 0) | |
6252 | return FIX_VR4120_MULT; | |
6253 | if (strncmp (name, "dmult", 5) == 0) | |
6254 | return FIX_VR4120_DMULT; | |
6255 | if (strstr (name, "div")) | |
6256 | return FIX_VR4120_DIV; | |
6257 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6258 | return FIX_VR4120_MTHILO; | |
6259 | return NUM_FIX_VR4120_CLASSES; | |
6260 | } | |
252b5132 | 6261 | |
a8d14a88 CM |
6262 | #define INSN_ERET 0x42000018 |
6263 | #define INSN_DERET 0x4200001f | |
6264 | #define INSN_DMULT 0x1c | |
6265 | #define INSN_DMULTU 0x1d | |
ff239038 | 6266 | |
71400594 RS |
6267 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6268 | where INSN1 is the earlier instruction. Return the worst-case value | |
6269 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6270 | |
71400594 RS |
6271 | static unsigned int |
6272 | insns_between (const struct mips_cl_insn *insn1, | |
6273 | const struct mips_cl_insn *insn2) | |
6274 | { | |
6275 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6276 | unsigned int mask; |
71400594 | 6277 | |
85fcb30f RS |
6278 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6279 | the second instruction. */ | |
71400594 RS |
6280 | pinfo1 = insn1->insn_mo->pinfo; |
6281 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6282 | |
71400594 RS |
6283 | /* For most targets, write-after-read dependencies on the HI and LO |
6284 | registers must be separated by at least two instructions. */ | |
6285 | if (!hilo_interlocks) | |
252b5132 | 6286 | { |
71400594 RS |
6287 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6288 | return 2; | |
6289 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6290 | return 2; | |
6291 | } | |
6292 | ||
6293 | /* If we're working around r7000 errata, there must be two instructions | |
6294 | between an mfhi or mflo and any instruction that uses the result. */ | |
6295 | if (mips_7000_hilo_fix | |
df58fc94 | 6296 | && !mips_opts.micromips |
71400594 | 6297 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6298 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6299 | return 2; |
6300 | ||
ff239038 CM |
6301 | /* If we're working around 24K errata, one instruction is required |
6302 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6303 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6304 | { |
6305 | if (insn1->insn_opcode == INSN_ERET | |
6306 | || insn1->insn_opcode == INSN_DERET) | |
6307 | { | |
6308 | if (insn2 == NULL | |
6309 | || insn2->insn_opcode == INSN_ERET | |
6310 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6311 | || delayed_branch_p (insn2)) |
ff239038 CM |
6312 | return 1; |
6313 | } | |
6314 | } | |
6315 | ||
a8d14a88 CM |
6316 | /* If we're working around PMC RM7000 errata, there must be three |
6317 | nops between a dmult and a load instruction. */ | |
6318 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6319 | { | |
6320 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6321 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6322 | { | |
6323 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6324 | return 3; | |
6325 | } | |
6326 | } | |
6327 | ||
71400594 RS |
6328 | /* If working around VR4120 errata, check for combinations that need |
6329 | a single intervening instruction. */ | |
df58fc94 | 6330 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6331 | { |
6332 | unsigned int class1, class2; | |
252b5132 | 6333 | |
71400594 RS |
6334 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6335 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6336 | { |
71400594 RS |
6337 | if (insn2 == NULL) |
6338 | return 1; | |
6339 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6340 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6341 | return 1; | |
252b5132 | 6342 | } |
71400594 RS |
6343 | } |
6344 | ||
df58fc94 | 6345 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6346 | { |
6347 | /* Check for GPR or coprocessor load delays. All such delays | |
6348 | are on the RT register. */ | |
6349 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6350 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6351 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6352 | { |
85fcb30f | 6353 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6354 | return 1; |
6355 | } | |
6356 | ||
6357 | /* Check for generic coprocessor hazards. | |
6358 | ||
6359 | This case is not handled very well. There is no special | |
6360 | knowledge of CP0 handling, and the coprocessors other than | |
6361 | the floating point unit are not distinguished at all. */ | |
6362 | /* Itbl support may require additional care here. FIXME! | |
6363 | Need to modify this to include knowledge about | |
6364 | user specified delays! */ | |
43885403 | 6365 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6366 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6367 | { | |
6368 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6369 | register. There must be a one instruction delay before INSN2 | |
6370 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6371 | mask = fpr_write_mask (insn1); |
6372 | if (mask != 0) | |
252b5132 | 6373 | { |
4c260379 | 6374 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6375 | return 1; |
252b5132 RH |
6376 | } |
6377 | else | |
6378 | { | |
71400594 RS |
6379 | /* Read-after-write dependencies on the control registers |
6380 | require a two-instruction gap. */ | |
6381 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6382 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6383 | return 2; | |
6384 | ||
6385 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6386 | also a coprocessor instruction, assume there must be | |
6387 | a one instruction gap. */ | |
6388 | if (pinfo2 & INSN_COP) | |
6389 | return 1; | |
252b5132 RH |
6390 | } |
6391 | } | |
6b76fefe | 6392 | |
71400594 RS |
6393 | /* Check for read-after-write dependencies on the coprocessor |
6394 | control registers in cases where INSN1 does not need a general | |
6395 | coprocessor delay. This means that INSN1 is a floating point | |
6396 | comparison instruction. */ | |
6397 | /* Itbl support may require additional care here. */ | |
6398 | else if (!cop_interlocks | |
6399 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6400 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6401 | return 1; | |
6402 | } | |
6b76fefe | 6403 | |
7361da2c AB |
6404 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6405 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6406 | and pause. */ | |
6407 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6408 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6409 | || (insn2 && delayed_branch_p (insn2)))) | |
6410 | return 1; | |
6411 | ||
71400594 RS |
6412 | return 0; |
6413 | } | |
6b76fefe | 6414 | |
7d8e00cf RS |
6415 | /* Return the number of nops that would be needed to work around the |
6416 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6417 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6418 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6419 | |
6420 | static int | |
932d1a1b | 6421 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6422 | const struct mips_cl_insn *insn) |
6423 | { | |
4c260379 RS |
6424 | int i, j; |
6425 | unsigned int mask; | |
7d8e00cf RS |
6426 | |
6427 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6428 | are not affected by the errata. */ | |
6429 | if (insn != 0 | |
6430 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6431 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6432 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6433 | return 0; | |
6434 | ||
6435 | /* Search for the first MFLO or MFHI. */ | |
6436 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6437 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6438 | { |
6439 | /* Extract the destination register. */ | |
4c260379 | 6440 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6441 | |
6442 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6443 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6444 | return 0; |
6445 | ||
6446 | /* ...or if any of the intervening instructions do. */ | |
6447 | for (j = 0; j < i; j++) | |
4c260379 | 6448 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6449 | return 0; |
6450 | ||
932d1a1b RS |
6451 | if (i >= ignore) |
6452 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6453 | } |
6454 | return 0; | |
6455 | } | |
6456 | ||
134c0c8b MR |
6457 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6458 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6459 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6460 | ||
6461 | /* Return the minimum alignment for this store instruction. */ | |
6462 | ||
6463 | static int | |
6464 | fix_24k_align_to (const struct mips_opcode *mo) | |
6465 | { | |
6466 | if (strcmp (mo->name, "sh") == 0) | |
6467 | return 2; | |
6468 | ||
6469 | if (strcmp (mo->name, "swc1") == 0 | |
6470 | || strcmp (mo->name, "swc2") == 0 | |
6471 | || strcmp (mo->name, "sw") == 0 | |
6472 | || strcmp (mo->name, "sc") == 0 | |
6473 | || strcmp (mo->name, "s.s") == 0) | |
6474 | return 4; | |
6475 | ||
6476 | if (strcmp (mo->name, "sdc1") == 0 | |
6477 | || strcmp (mo->name, "sdc2") == 0 | |
6478 | || strcmp (mo->name, "s.d") == 0) | |
6479 | return 8; | |
6480 | ||
6481 | /* sb, swl, swr */ | |
6482 | return 1; | |
6483 | } | |
6484 | ||
6485 | struct fix_24k_store_info | |
6486 | { | |
6487 | /* Immediate offset, if any, for this store instruction. */ | |
6488 | short off; | |
6489 | /* Alignment required by this store instruction. */ | |
6490 | int align_to; | |
6491 | /* True for register offsets. */ | |
6492 | int register_offset; | |
6493 | }; | |
6494 | ||
6495 | /* Comparison function used by qsort. */ | |
6496 | ||
6497 | static int | |
6498 | fix_24k_sort (const void *a, const void *b) | |
6499 | { | |
6500 | const struct fix_24k_store_info *pos1 = a; | |
6501 | const struct fix_24k_store_info *pos2 = b; | |
6502 | ||
6503 | return (pos1->off - pos2->off); | |
6504 | } | |
6505 | ||
6506 | /* INSN is a store instruction. Try to record the store information | |
6507 | in STINFO. Return false if the information isn't known. */ | |
6508 | ||
6509 | static bfd_boolean | |
6510 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6511 | const struct mips_cl_insn *insn) |
15be625d CM |
6512 | { |
6513 | /* The instruction must have a known offset. */ | |
6514 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6515 | return FALSE; | |
6516 | ||
6517 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6518 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6519 | return TRUE; | |
6520 | } | |
6521 | ||
932d1a1b RS |
6522 | /* Return the number of nops that would be needed to work around the 24k |
6523 | "lost data on stores during refill" errata if instruction INSN | |
6524 | immediately followed the 2 instructions described by HIST. | |
6525 | Ignore hazards that are contained within the first IGNORE | |
6526 | instructions of HIST. | |
6527 | ||
6528 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6529 | for the data cache refills and store data. The following describes | |
6530 | the scenario where the store data could be lost. | |
6531 | ||
6532 | * A data cache miss, due to either a load or a store, causing fill | |
6533 | data to be supplied by the memory subsystem | |
6534 | * The first three doublewords of fill data are returned and written | |
6535 | into the cache | |
6536 | * A sequence of four stores occurs in consecutive cycles around the | |
6537 | final doubleword of the fill: | |
6538 | * Store A | |
6539 | * Store B | |
6540 | * Store C | |
6541 | * Zero, One or more instructions | |
6542 | * Store D | |
6543 | ||
6544 | The four stores A-D must be to different doublewords of the line that | |
6545 | is being filled. The fourth instruction in the sequence above permits | |
6546 | the fill of the final doubleword to be transferred from the FSB into | |
6547 | the cache. In the sequence above, the stores may be either integer | |
6548 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6549 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6550 | different doublewords on the line. If the floating point unit is | |
6551 | running in 1:2 mode, it is not possible to create the sequence above | |
6552 | using only floating point store instructions. | |
15be625d CM |
6553 | |
6554 | In this case, the cache line being filled is incorrectly marked | |
6555 | invalid, thereby losing the data from any store to the line that | |
6556 | occurs between the original miss and the completion of the five | |
6557 | cycle sequence shown above. | |
6558 | ||
932d1a1b | 6559 | The workarounds are: |
15be625d | 6560 | |
932d1a1b RS |
6561 | * Run the data cache in write-through mode. |
6562 | * Insert a non-store instruction between | |
6563 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6564 | |
15be625d | 6565 | static int |
932d1a1b | 6566 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6567 | const struct mips_cl_insn *insn) |
6568 | { | |
6569 | struct fix_24k_store_info pos[3]; | |
6570 | int align, i, base_offset; | |
6571 | ||
932d1a1b RS |
6572 | if (ignore >= 2) |
6573 | return 0; | |
6574 | ||
ab9794cf RS |
6575 | /* If the previous instruction wasn't a store, there's nothing to |
6576 | worry about. */ | |
15be625d CM |
6577 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6578 | return 0; | |
6579 | ||
ab9794cf RS |
6580 | /* If the instructions after the previous one are unknown, we have |
6581 | to assume the worst. */ | |
6582 | if (!insn) | |
15be625d CM |
6583 | return 1; |
6584 | ||
ab9794cf RS |
6585 | /* Check whether we are dealing with three consecutive stores. */ |
6586 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6587 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6588 | return 0; |
6589 | ||
6590 | /* If we don't know the relationship between the store addresses, | |
6591 | assume the worst. */ | |
ab9794cf | 6592 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6593 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6594 | return 1; | |
6595 | ||
6596 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6597 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6598 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6599 | return 1; | |
6600 | ||
6601 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6602 | ||
6603 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6604 | X bytes and such that the base register + X is known to be aligned | |
6605 | to align bytes. */ | |
6606 | ||
6607 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6608 | align = 8; | |
6609 | else | |
6610 | { | |
6611 | align = pos[0].align_to; | |
6612 | base_offset = pos[0].off; | |
6613 | for (i = 1; i < 3; i++) | |
6614 | if (align < pos[i].align_to) | |
6615 | { | |
6616 | align = pos[i].align_to; | |
6617 | base_offset = pos[i].off; | |
6618 | } | |
6619 | for (i = 0; i < 3; i++) | |
6620 | pos[i].off -= base_offset; | |
6621 | } | |
6622 | ||
6623 | pos[0].off &= ~align + 1; | |
6624 | pos[1].off &= ~align + 1; | |
6625 | pos[2].off &= ~align + 1; | |
6626 | ||
6627 | /* If any two stores write to the same chunk, they also write to the | |
6628 | same doubleword. The offsets are still sorted at this point. */ | |
6629 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6630 | return 0; | |
6631 | ||
6632 | /* A range of at least 9 bytes is needed for the stores to be in | |
6633 | non-overlapping doublewords. */ | |
6634 | if (pos[2].off - pos[0].off <= 8) | |
6635 | return 0; | |
6636 | ||
6637 | if (pos[2].off - pos[1].off >= 24 | |
6638 | || pos[1].off - pos[0].off >= 24 | |
6639 | || pos[2].off - pos[0].off >= 32) | |
6640 | return 0; | |
6641 | ||
6642 | return 1; | |
6643 | } | |
6644 | ||
71400594 | 6645 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6646 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6647 | where HIST[0] is the most recent instruction. Ignore hazards |
6648 | between INSN and the first IGNORE instructions in HIST. | |
6649 | ||
6650 | If INSN is null, return the worse-case number of nops for any | |
6651 | instruction. */ | |
bdaaa2e1 | 6652 | |
71400594 | 6653 | static int |
932d1a1b | 6654 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6655 | const struct mips_cl_insn *insn) |
6656 | { | |
6657 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6658 | |
71400594 | 6659 | nops = 0; |
932d1a1b | 6660 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6661 | { |
91d6fa6a | 6662 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6663 | if (tmp_nops > nops) |
6664 | nops = tmp_nops; | |
6665 | } | |
7d8e00cf | 6666 | |
df58fc94 | 6667 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6668 | { |
932d1a1b | 6669 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6670 | if (tmp_nops > nops) |
6671 | nops = tmp_nops; | |
6672 | } | |
6673 | ||
df58fc94 | 6674 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6675 | { |
932d1a1b | 6676 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6677 | if (tmp_nops > nops) |
6678 | nops = tmp_nops; | |
6679 | } | |
6680 | ||
71400594 RS |
6681 | return nops; |
6682 | } | |
252b5132 | 6683 | |
71400594 | 6684 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6685 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6686 | would be needed after the extended sequence, ignoring hazards |
6687 | in the first IGNORE instructions. */ | |
252b5132 | 6688 | |
71400594 | 6689 | static int |
932d1a1b RS |
6690 | nops_for_sequence (int num_insns, int ignore, |
6691 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6692 | { |
6693 | va_list args; | |
6694 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6695 | struct mips_cl_insn *cursor; | |
6696 | int nops; | |
6697 | ||
91d6fa6a | 6698 | va_start (args, hist); |
71400594 | 6699 | cursor = buffer + num_insns; |
91d6fa6a | 6700 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6701 | while (cursor > buffer) |
6702 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6703 | ||
932d1a1b | 6704 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6705 | va_end (args); |
6706 | return nops; | |
6707 | } | |
252b5132 | 6708 | |
71400594 RS |
6709 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6710 | worst-case delay for the branch target. */ | |
252b5132 | 6711 | |
71400594 | 6712 | static int |
932d1a1b | 6713 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6714 | const struct mips_cl_insn *insn) |
6715 | { | |
6716 | int nops, tmp_nops; | |
60b63b72 | 6717 | |
932d1a1b | 6718 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6719 | if (delayed_branch_p (insn)) |
71400594 | 6720 | { |
932d1a1b | 6721 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6722 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6723 | if (tmp_nops > nops) |
6724 | nops = tmp_nops; | |
6725 | } | |
11625dd8 | 6726 | else if (compact_branch_p (insn)) |
71400594 | 6727 | { |
932d1a1b | 6728 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6729 | if (tmp_nops > nops) |
6730 | nops = tmp_nops; | |
6731 | } | |
6732 | return nops; | |
6733 | } | |
6734 | ||
c67a084a NC |
6735 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6736 | ||
6737 | static void | |
6738 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6739 | { | |
df58fc94 | 6740 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6741 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6742 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6743 | } | |
6744 | ||
6745 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6746 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6747 | ||
6748 | static void | |
6749 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6750 | { | |
df58fc94 | 6751 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6752 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6753 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6754 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6755 | { | |
6756 | int sreg; | |
6757 | expressionS ep; | |
6758 | ||
6759 | if (! mips_opts.at) | |
6760 | return; | |
6761 | ||
df58fc94 | 6762 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6763 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6764 | return; | |
6765 | ||
6766 | ep.X_op = O_constant; | |
6767 | ep.X_add_number = 0xcfff0000; | |
6768 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6769 | ep.X_add_number = 0xffff; | |
6770 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6771 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6772 | } | |
6773 | } | |
6774 | ||
6775 | static void | |
6776 | fix_loongson2f (struct mips_cl_insn * ip) | |
6777 | { | |
6778 | if (mips_fix_loongson2f_nop) | |
6779 | fix_loongson2f_nop (ip); | |
6780 | ||
6781 | if (mips_fix_loongson2f_jump) | |
6782 | fix_loongson2f_jump (ip); | |
6783 | } | |
6784 | ||
a4e06468 RS |
6785 | /* IP is a branch that has a delay slot, and we need to fill it |
6786 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6787 | with the previous instruction. |
6788 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6789 | RELOC_TYPE. */ | |
a4e06468 RS |
6790 | |
6791 | static bfd_boolean | |
e407c74b | 6792 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6793 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6794 | { |
2b0c8b40 | 6795 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6796 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6797 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6798 | |
6799 | /* -O2 and above is required for this optimization. */ | |
6800 | if (mips_optimize < 2) | |
6801 | return FALSE; | |
6802 | ||
6803 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6804 | if (mips_opts.nomove) | |
6805 | return FALSE; | |
6806 | ||
6807 | /* We can't swap if the previous instruction's position is fixed. */ | |
6808 | if (history[0].fixed_p) | |
6809 | return FALSE; | |
6810 | ||
6811 | /* If the previous previous insn was in a .set noreorder, we can't | |
6812 | swap. Actually, the MIPS assembler will swap in this situation. | |
6813 | However, gcc configured -with-gnu-as will generate code like | |
6814 | ||
6815 | .set noreorder | |
6816 | lw $4,XXX | |
6817 | .set reorder | |
6818 | INSN | |
6819 | bne $4,$0,foo | |
6820 | ||
6821 | in which we can not swap the bne and INSN. If gcc is not configured | |
6822 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6823 | if (history[1].noreorder_p) | |
6824 | return FALSE; | |
6825 | ||
87333bb7 MR |
6826 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6827 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6828 | if (mips_opts.mips16 && history[0].fixp[0]) |
6829 | return FALSE; | |
6830 | ||
6831 | /* If the branch is itself the target of a branch, we can not swap. | |
6832 | We cheat on this; all we check for is whether there is a label on | |
6833 | this instruction. If there are any branches to anything other than | |
6834 | a label, users must use .set noreorder. */ | |
6835 | if (seg_info (now_seg)->label_list) | |
6836 | return FALSE; | |
6837 | ||
6838 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6839 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6840 | MIPS16 code, which uses variant frags for different purposes. */ |
6841 | if (!mips_opts.mips16 | |
a4e06468 RS |
6842 | && history[0].frag |
6843 | && history[0].frag->fr_type == rs_machine_dependent) | |
6844 | return FALSE; | |
6845 | ||
bcd530a7 RS |
6846 | /* We do not swap with instructions that cannot architecturally |
6847 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6848 | also refrain from swapping with a trap instruction, since it | |
6849 | complicates trap handlers to have the trap instruction be in | |
6850 | a delay slot. */ | |
a4e06468 | 6851 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6852 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6853 | return FALSE; |
6854 | ||
6855 | /* Check for conflicts between the branch and the instructions | |
6856 | before the candidate delay slot. */ | |
6857 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6858 | return FALSE; | |
6859 | ||
6860 | /* Check for conflicts between the swapped sequence and the | |
6861 | target of the branch. */ | |
6862 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6863 | return FALSE; | |
6864 | ||
6865 | /* If the branch reads a register that the previous | |
6866 | instruction sets, we can not swap. */ | |
6867 | gpr_read = gpr_read_mask (ip); | |
6868 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6869 | if (gpr_read & prev_gpr_write) | |
6870 | return FALSE; | |
6871 | ||
9d5de888 CF |
6872 | fpr_read = fpr_read_mask (ip); |
6873 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6874 | if (fpr_read & prev_fpr_write) | |
6875 | return FALSE; | |
6876 | ||
a4e06468 RS |
6877 | /* If the branch writes a register that the previous |
6878 | instruction sets, we can not swap. */ | |
6879 | gpr_write = gpr_write_mask (ip); | |
6880 | if (gpr_write & prev_gpr_write) | |
6881 | return FALSE; | |
6882 | ||
6883 | /* If the branch writes a register that the previous | |
6884 | instruction reads, we can not swap. */ | |
6885 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6886 | if (gpr_write & prev_gpr_read) | |
6887 | return FALSE; | |
6888 | ||
6889 | /* If one instruction sets a condition code and the | |
6890 | other one uses a condition code, we can not swap. */ | |
6891 | pinfo = ip->insn_mo->pinfo; | |
6892 | if ((pinfo & INSN_READ_COND_CODE) | |
6893 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6894 | return FALSE; | |
6895 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6896 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6897 | return FALSE; | |
6898 | ||
6899 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6900 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6901 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6902 | return FALSE; |
a4e06468 | 6903 | |
df58fc94 RS |
6904 | /* If the previous instruction has an incorrect size for a fixed |
6905 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6906 | pinfo2 = ip->insn_mo->pinfo2; |
6907 | if (mips_opts.micromips | |
6908 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6909 | && insn_length (history) != 2) | |
6910 | return FALSE; | |
6911 | if (mips_opts.micromips | |
6912 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6913 | && insn_length (history) != 4) | |
6914 | return FALSE; | |
6915 | ||
e407c74b NC |
6916 | /* On R5900 short loops need to be fixed by inserting a nop in |
6917 | the branch delay slots. | |
6918 | A short loop can be terminated too early. */ | |
6919 | if (mips_opts.arch == CPU_R5900 | |
6920 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6921 | && (address_expr != NULL) | |
6922 | /* Parameter must be 16 bit. */ | |
6923 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6924 | /* Branch to same segment. */ | |
41065f5e | 6925 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 6926 | /* Branch to same code fragment. */ |
41065f5e | 6927 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 6928 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 6929 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
6930 | /* Check if branch is really conditional. */ |
6931 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6932 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6933 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6934 | { | |
6935 | int distance; | |
6936 | /* Check if loop is shorter than 6 instructions including | |
6937 | branch and delay slot. */ | |
41065f5e | 6938 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
6939 | if (distance <= 20) |
6940 | { | |
6941 | int i; | |
6942 | int rv; | |
6943 | ||
6944 | rv = FALSE; | |
6945 | /* When the loop includes branches or jumps, | |
6946 | it is not a short loop. */ | |
6947 | for (i = 0; i < (distance / 4); i++) | |
6948 | { | |
6949 | if ((history[i].cleared_p) | |
41065f5e | 6950 | || delayed_branch_p (&history[i])) |
e407c74b NC |
6951 | { |
6952 | rv = TRUE; | |
6953 | break; | |
6954 | } | |
6955 | } | |
535b785f | 6956 | if (!rv) |
e407c74b NC |
6957 | { |
6958 | /* Insert nop after branch to fix short loop. */ | |
6959 | return FALSE; | |
6960 | } | |
6961 | } | |
6962 | } | |
6963 | ||
a4e06468 RS |
6964 | return TRUE; |
6965 | } | |
6966 | ||
e407c74b NC |
6967 | /* Decide how we should add IP to the instruction stream. |
6968 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6969 | RELOC_TYPE. */ | |
a4e06468 RS |
6970 | |
6971 | static enum append_method | |
e407c74b | 6972 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6973 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6974 | { |
a4e06468 RS |
6975 | /* The relaxed version of a macro sequence must be inherently |
6976 | hazard-free. */ | |
6977 | if (mips_relax.sequence == 2) | |
6978 | return APPEND_ADD; | |
6979 | ||
3b821a28 | 6980 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
6981 | if (mips_opts.noreorder) |
6982 | return APPEND_ADD; | |
6983 | ||
6984 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 6985 | if (delayed_branch_p (ip)) |
a4e06468 | 6986 | { |
e407c74b NC |
6987 | if (!branch_likely_p (ip) |
6988 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
6989 | return APPEND_SWAP; |
6990 | ||
6991 | if (mips_opts.mips16 | |
6992 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 6993 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
6994 | return APPEND_ADD_COMPACT; |
6995 | ||
7bd374a4 MR |
6996 | if (mips_opts.micromips |
6997 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
6998 | || (!forced_insn_length | |
6999 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7000 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7001 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7002 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7003 | return APPEND_ADD_COMPACT; | |
7004 | ||
a4e06468 RS |
7005 | return APPEND_ADD_WITH_NOP; |
7006 | } | |
7007 | ||
a4e06468 RS |
7008 | return APPEND_ADD; |
7009 | } | |
7010 | ||
7bd374a4 MR |
7011 | /* IP is an instruction whose opcode we have just changed, END points |
7012 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7013 | new opcode's definition. */ | |
ceb94aa5 RS |
7014 | |
7015 | static void | |
7bd374a4 | 7016 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7017 | { |
7bd374a4 | 7018 | const struct mips_opcode *mo; |
ceb94aa5 | 7019 | |
ceb94aa5 | 7020 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7021 | if (mo->pinfo != INSN_MACRO |
7022 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7023 | { |
7024 | ip->insn_mo = mo; | |
7025 | return; | |
7026 | } | |
7027 | abort (); | |
7028 | } | |
7029 | ||
7bd374a4 MR |
7030 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7031 | Point IP->insn_mo to the new opcode's definition. */ | |
7032 | ||
7033 | static void | |
7034 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7035 | { | |
7036 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7037 | } | |
7038 | ||
7039 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7040 | Point IP->insn_mo to the new opcode's definition. */ | |
7041 | ||
7042 | static void | |
7043 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7044 | { | |
7045 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7046 | } | |
7047 | ||
df58fc94 RS |
7048 | /* For microMIPS macros, we need to generate a local number label |
7049 | as the target of branches. */ | |
7050 | #define MICROMIPS_LABEL_CHAR '\037' | |
7051 | static unsigned long micromips_target_label; | |
7052 | static char micromips_target_name[32]; | |
7053 | ||
7054 | static char * | |
7055 | micromips_label_name (void) | |
7056 | { | |
7057 | char *p = micromips_target_name; | |
7058 | char symbol_name_temporary[24]; | |
7059 | unsigned long l; | |
7060 | int i; | |
7061 | ||
7062 | if (*p) | |
7063 | return p; | |
7064 | ||
7065 | i = 0; | |
7066 | l = micromips_target_label; | |
7067 | #ifdef LOCAL_LABEL_PREFIX | |
7068 | *p++ = LOCAL_LABEL_PREFIX; | |
7069 | #endif | |
7070 | *p++ = 'L'; | |
7071 | *p++ = MICROMIPS_LABEL_CHAR; | |
7072 | do | |
7073 | { | |
7074 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7075 | l /= 10; | |
7076 | } | |
7077 | while (l != 0); | |
7078 | while (i > 0) | |
7079 | *p++ = symbol_name_temporary[--i]; | |
7080 | *p = '\0'; | |
7081 | ||
7082 | return micromips_target_name; | |
7083 | } | |
7084 | ||
7085 | static void | |
7086 | micromips_label_expr (expressionS *label_expr) | |
7087 | { | |
7088 | label_expr->X_op = O_symbol; | |
7089 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7090 | label_expr->X_add_number = 0; | |
7091 | } | |
7092 | ||
7093 | static void | |
7094 | micromips_label_inc (void) | |
7095 | { | |
7096 | micromips_target_label++; | |
7097 | *micromips_target_name = '\0'; | |
7098 | } | |
7099 | ||
7100 | static void | |
7101 | micromips_add_label (void) | |
7102 | { | |
7103 | symbolS *s; | |
7104 | ||
7105 | s = colon (micromips_label_name ()); | |
7106 | micromips_label_inc (); | |
f3ded42a | 7107 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7108 | } |
7109 | ||
7110 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7111 | corresponding to the requested one if any. Otherwise return | |
7112 | the reloc unchanged. */ | |
7113 | ||
7114 | static bfd_reloc_code_real_type | |
7115 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7116 | { | |
7117 | static const bfd_reloc_code_real_type relocs[][2] = | |
7118 | { | |
7119 | /* Keep sorted incrementally by the left-hand key. */ | |
7120 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7121 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7122 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7123 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7124 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7125 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7126 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7127 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7128 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7129 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7130 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7131 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7132 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7133 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7134 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7135 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7136 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7137 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7138 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7139 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7140 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7141 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7142 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7143 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7144 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7145 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7146 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7147 | }; | |
7148 | bfd_reloc_code_real_type r; | |
7149 | size_t i; | |
7150 | ||
7151 | if (!mips_opts.micromips) | |
7152 | return reloc; | |
7153 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7154 | { | |
7155 | r = relocs[i][0]; | |
7156 | if (r > reloc) | |
7157 | return reloc; | |
7158 | if (r == reloc) | |
7159 | return relocs[i][1]; | |
7160 | } | |
7161 | return reloc; | |
7162 | } | |
7163 | ||
b886a2ab RS |
7164 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7165 | Return true on success, storing the resolved value in RESULT. */ | |
7166 | ||
7167 | static bfd_boolean | |
7168 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7169 | offsetT *result) | |
7170 | { | |
7171 | switch (reloc) | |
7172 | { | |
7173 | case BFD_RELOC_MIPS_HIGHEST: | |
7174 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7175 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7176 | return TRUE; | |
7177 | ||
7178 | case BFD_RELOC_MIPS_HIGHER: | |
7179 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7180 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7181 | return TRUE; | |
7182 | ||
7183 | case BFD_RELOC_HI16_S: | |
41947d9e | 7184 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7185 | case BFD_RELOC_MICROMIPS_HI16_S: |
7186 | case BFD_RELOC_MIPS16_HI16_S: | |
7187 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7188 | return TRUE; | |
7189 | ||
7190 | case BFD_RELOC_HI16: | |
7191 | case BFD_RELOC_MICROMIPS_HI16: | |
7192 | case BFD_RELOC_MIPS16_HI16: | |
7193 | *result = (operand >> 16) & 0xffff; | |
7194 | return TRUE; | |
7195 | ||
7196 | case BFD_RELOC_LO16: | |
41947d9e | 7197 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7198 | case BFD_RELOC_MICROMIPS_LO16: |
7199 | case BFD_RELOC_MIPS16_LO16: | |
7200 | *result = operand & 0xffff; | |
7201 | return TRUE; | |
7202 | ||
7203 | case BFD_RELOC_UNUSED: | |
7204 | *result = operand; | |
7205 | return TRUE; | |
7206 | ||
7207 | default: | |
7208 | return FALSE; | |
7209 | } | |
7210 | } | |
7211 | ||
71400594 RS |
7212 | /* Output an instruction. IP is the instruction information. |
7213 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7214 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7215 | a macro expansion. */ | |
71400594 RS |
7216 | |
7217 | static void | |
7218 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7219 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7220 | { |
14fe068b | 7221 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7222 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7223 | enum append_method method; |
2309ddf2 | 7224 | bfd_boolean relax32; |
2b0c8b40 | 7225 | int branch_disp; |
71400594 | 7226 | |
2309ddf2 | 7227 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7228 | fix_loongson2f (ip); |
7229 | ||
738f4d98 | 7230 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7231 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7232 | |
df58fc94 | 7233 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7234 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7235 | |
7bd374a4 MR |
7236 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7237 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7238 | if (mips_opts.micromips |
7239 | && !expansionp | |
7bd374a4 MR |
7240 | && !(history[0].frag |
7241 | && history[0].frag->fr_type == rs_machine_dependent | |
7242 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7243 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7244 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7245 | && micromips_insn_length (ip->insn_mo) != 2) | |
7246 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7247 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7248 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7249 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7250 | |
15be625d CM |
7251 | if (address_expr == NULL) |
7252 | ip->complete_p = 1; | |
b886a2ab RS |
7253 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7254 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7255 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7256 | && address_expr->X_op == O_constant) |
7257 | { | |
15be625d CM |
7258 | switch (*reloc_type) |
7259 | { | |
15be625d | 7260 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7261 | { |
7262 | int shift; | |
7263 | ||
17c6c9d9 MR |
7264 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7265 | shift = (mips_opts.micromips | |
7266 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7267 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7268 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7269 | (unsigned long) address_expr->X_add_number); | |
7270 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7271 | & 0x3ffffff); | |
335574df | 7272 | ip->complete_p = 1; |
df58fc94 | 7273 | } |
15be625d CM |
7274 | break; |
7275 | ||
7276 | case BFD_RELOC_MIPS16_JMP: | |
7277 | if ((address_expr->X_add_number & 3) != 0) | |
7278 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7279 | (unsigned long) address_expr->X_add_number); | |
7280 | ip->insn_opcode |= | |
7281 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7282 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7283 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7284 | ip->complete_p = 1; |
15be625d CM |
7285 | break; |
7286 | ||
7287 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7288 | { |
7289 | int shift; | |
7290 | ||
7291 | shift = mips_opts.micromips ? 1 : 2; | |
7292 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7293 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7294 | (unsigned long) address_expr->X_add_number); | |
7295 | if (!mips_relax_branch) | |
7296 | { | |
7297 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7298 | & ~((1 << (shift + 16)) - 1)) | |
7299 | as_bad (_("branch address range overflow (0x%lx)"), | |
7300 | (unsigned long) address_expr->X_add_number); | |
7301 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7302 | & 0xffff); | |
7303 | } | |
df58fc94 | 7304 | } |
15be625d CM |
7305 | break; |
7306 | ||
7361da2c AB |
7307 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7308 | { | |
7309 | int shift; | |
7310 | ||
7311 | shift = 2; | |
7312 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7313 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7314 | (unsigned long) address_expr->X_add_number); | |
7315 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7316 | & ~((1 << (shift + 21)) - 1)) | |
7317 | as_bad (_("branch address range overflow (0x%lx)"), | |
7318 | (unsigned long) address_expr->X_add_number); | |
7319 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7320 | & 0x1fffff); | |
7321 | } | |
7322 | break; | |
7323 | ||
7324 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7325 | { | |
7326 | int shift; | |
7327 | ||
7328 | shift = 2; | |
7329 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7330 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7331 | (unsigned long) address_expr->X_add_number); | |
7332 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7333 | & ~((1 << (shift + 26)) - 1)) | |
7334 | as_bad (_("branch address range overflow (0x%lx)"), | |
7335 | (unsigned long) address_expr->X_add_number); | |
7336 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7337 | & 0x3ffffff); | |
7338 | } | |
7339 | break; | |
7340 | ||
15be625d | 7341 | default: |
b886a2ab RS |
7342 | { |
7343 | offsetT value; | |
7344 | ||
7345 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7346 | &value)) | |
7347 | { | |
7348 | ip->insn_opcode |= value & 0xffff; | |
7349 | ip->complete_p = 1; | |
7350 | } | |
7351 | } | |
7352 | break; | |
7353 | } | |
15be625d CM |
7354 | } |
7355 | ||
71400594 RS |
7356 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7357 | { | |
7358 | /* There are a lot of optimizations we could do that we don't. | |
7359 | In particular, we do not, in general, reorder instructions. | |
7360 | If you use gcc with optimization, it will reorder | |
7361 | instructions and generally do much more optimization then we | |
7362 | do here; repeating all that work in the assembler would only | |
7363 | benefit hand written assembly code, and does not seem worth | |
7364 | it. */ | |
7365 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7366 | ? nops_for_insn (0, history, NULL) |
7367 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7368 | if (nops > 0) |
252b5132 RH |
7369 | { |
7370 | fragS *old_frag; | |
7371 | unsigned long old_frag_offset; | |
7372 | int i; | |
252b5132 RH |
7373 | |
7374 | old_frag = frag_now; | |
7375 | old_frag_offset = frag_now_fix (); | |
7376 | ||
7377 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7378 | add_fixed_insn (NOP_INSN); |
7379 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7380 | |
7381 | if (listing) | |
7382 | { | |
7383 | listing_prev_line (); | |
7384 | /* We may be at the start of a variant frag. In case we | |
7385 | are, make sure there is enough space for the frag | |
7386 | after the frags created by listing_prev_line. The | |
7387 | argument to frag_grow here must be at least as large | |
7388 | as the argument to all other calls to frag_grow in | |
7389 | this file. We don't have to worry about being in the | |
7390 | middle of a variant frag, because the variants insert | |
7391 | all needed nop instructions themselves. */ | |
7392 | frag_grow (40); | |
7393 | } | |
7394 | ||
462427c4 | 7395 | mips_move_text_labels (); |
252b5132 RH |
7396 | |
7397 | #ifndef NO_ECOFF_DEBUGGING | |
7398 | if (ECOFF_DEBUGGING) | |
7399 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7400 | #endif | |
7401 | } | |
71400594 RS |
7402 | } |
7403 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7404 | { | |
932d1a1b RS |
7405 | int nops; |
7406 | ||
7407 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7408 | ignoring hazards generated by the first prev_nop_frag_since | |
7409 | instructions. */ | |
7410 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7411 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7412 | |
71400594 RS |
7413 | /* Enforce NOPS as a minimum. */ |
7414 | if (nops > prev_nop_frag_required) | |
7415 | prev_nop_frag_required = nops; | |
252b5132 | 7416 | |
71400594 RS |
7417 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7418 | { | |
7419 | /* Settle for the current number of nops. Update the history | |
7420 | accordingly (for the benefit of any future .set reorder code). */ | |
7421 | prev_nop_frag = NULL; | |
7422 | insert_into_history (prev_nop_frag_since, | |
7423 | prev_nop_frag_holds, NOP_INSN); | |
7424 | } | |
7425 | else | |
7426 | { | |
7427 | /* Allow this instruction to replace one of the nops that was | |
7428 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7429 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7430 | prev_nop_frag_holds--; |
7431 | prev_nop_frag_since++; | |
252b5132 RH |
7432 | } |
7433 | } | |
7434 | ||
e407c74b | 7435 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7436 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7437 | |
e410add4 RS |
7438 | dwarf2_emit_insn (0); |
7439 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7440 | so "move" the instruction address accordingly. | |
7441 | ||
7442 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7443 | entries. If this instruction is a branch that we are going to swap | |
7444 | with the previous instruction, the two instructions should be | |
7445 | treated as a unit, and the debug information for both instructions | |
7446 | should refer to the start of the branch sequence. Using the | |
7447 | current position is certainly wrong when swapping a 32-bit branch | |
7448 | and a 16-bit delay slot, since the current position would then be | |
7449 | in the middle of a branch. */ | |
7450 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7451 | |
df58fc94 RS |
7452 | relax32 = (mips_relax_branch |
7453 | /* Don't try branch relaxation within .set nomacro, or within | |
7454 | .set noat if we use $at for PIC computations. If it turns | |
7455 | out that the branch was out-of-range, we'll get an error. */ | |
7456 | && !mips_opts.warn_about_macros | |
7457 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7458 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7459 | as they have no complementing branches. */ | |
7460 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7461 | |
7462 | if (!HAVE_CODE_COMPRESSION | |
7463 | && address_expr | |
7464 | && relax32 | |
0b25d3e6 | 7465 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7466 | && delayed_branch_p (ip)) |
4a6a3df4 | 7467 | { |
895921c9 | 7468 | relaxed_branch = TRUE; |
1e915849 RS |
7469 | add_relaxed_insn (ip, (relaxed_branch_length |
7470 | (NULL, NULL, | |
11625dd8 RS |
7471 | uncond_branch_p (ip) ? -1 |
7472 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7473 | : 0)), 4, |
7474 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7475 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7476 | uncond_branch_p (ip), |
7477 | branch_likely_p (ip), | |
1e915849 RS |
7478 | pinfo & INSN_WRITE_GPR_31, |
7479 | 0), | |
7480 | address_expr->X_add_symbol, | |
7481 | address_expr->X_add_number); | |
4a6a3df4 AO |
7482 | *reloc_type = BFD_RELOC_UNUSED; |
7483 | } | |
df58fc94 RS |
7484 | else if (mips_opts.micromips |
7485 | && address_expr | |
7486 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7487 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7488 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7489 | /* Don't try branch relaxation when users specify | |
7490 | 16-bit/32-bit instructions. */ | |
7491 | && !forced_insn_length) | |
df58fc94 | 7492 | { |
7bd374a4 MR |
7493 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7494 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7495 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7496 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7497 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7498 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7499 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7500 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7501 | |
7502 | gas_assert (address_expr != NULL); | |
7503 | gas_assert (!mips_relax.sequence); | |
7504 | ||
2b0c8b40 | 7505 | relaxed_branch = TRUE; |
7bd374a4 MR |
7506 | if (nods) |
7507 | method = APPEND_ADD; | |
7508 | if (relax32) | |
7509 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7510 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7511 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7512 | mips_pic != NO_PIC, |
7bd374a4 | 7513 | uncond, compact, al, nods, |
40209cad | 7514 | relax32, 0, 0), |
df58fc94 RS |
7515 | address_expr->X_add_symbol, |
7516 | address_expr->X_add_number); | |
7517 | *reloc_type = BFD_RELOC_UNUSED; | |
7518 | } | |
7519 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7520 | { |
7fd53920 MR |
7521 | bfd_boolean require_unextended; |
7522 | bfd_boolean require_extended; | |
88a7ef16 MR |
7523 | symbolS *symbol; |
7524 | offsetT offset; | |
7525 | ||
7fd53920 MR |
7526 | if (forced_insn_length != 0) |
7527 | { | |
7528 | require_unextended = forced_insn_length == 2; | |
7529 | require_extended = forced_insn_length == 4; | |
7530 | } | |
7531 | else | |
7532 | { | |
7533 | require_unextended = (mips_opts.noautoextend | |
7534 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7535 | require_extended = 0; | |
7536 | } | |
7537 | ||
252b5132 | 7538 | /* We need to set up a variant frag. */ |
df58fc94 | 7539 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7540 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7541 | symbol created by `make_expr_symbol' may not get a necessary | |
7542 | external relocation produced. */ | |
7543 | if (address_expr->X_op == O_symbol) | |
7544 | { | |
7545 | symbol = address_expr->X_add_symbol; | |
7546 | offset = address_expr->X_add_number; | |
7547 | } | |
7548 | else | |
7549 | { | |
7550 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7551 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7552 | offset = 0; |
7553 | } | |
8507b6e7 | 7554 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7555 | RELAX_MIPS16_ENCODE |
7556 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7557 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7558 | mips_pic != NO_PIC, |
7559 | HAVE_32BIT_SYMBOLS, | |
7560 | mips_opts.warn_about_macros, | |
7fd53920 | 7561 | require_unextended, require_extended, |
11625dd8 | 7562 | delayed_branch_p (&history[0]), |
1e915849 | 7563 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7564 | symbol, offset); |
252b5132 | 7565 | } |
5c04167a | 7566 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7567 | { |
11625dd8 | 7568 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7569 | /* Make sure there is enough room to swap this instruction with |
7570 | a following jump instruction. */ | |
7571 | frag_grow (6); | |
1e915849 | 7572 | add_fixed_insn (ip); |
252b5132 RH |
7573 | } |
7574 | else | |
7575 | { | |
7576 | if (mips_opts.mips16 | |
7577 | && mips_opts.noreorder | |
11625dd8 | 7578 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7579 | as_warn (_("extended instruction in delay slot")); |
7580 | ||
4d7206a2 RS |
7581 | if (mips_relax.sequence) |
7582 | { | |
7583 | /* If we've reached the end of this frag, turn it into a variant | |
7584 | frag and record the information for the instructions we've | |
7585 | written so far. */ | |
7586 | if (frag_room () < 4) | |
7587 | relax_close_frag (); | |
df58fc94 | 7588 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7589 | } |
7590 | ||
584892a6 | 7591 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7592 | { |
7593 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7594 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7595 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7596 | mips_macro_warning.insns[0]++; | |
7597 | } | |
584892a6 | 7598 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7599 | { |
7600 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7601 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7602 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7603 | mips_macro_warning.insns[1]++; | |
7604 | } | |
584892a6 | 7605 | |
1e915849 RS |
7606 | if (mips_opts.mips16) |
7607 | { | |
7608 | ip->fixed_p = 1; | |
7609 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7610 | } | |
7611 | add_fixed_insn (ip); | |
252b5132 RH |
7612 | } |
7613 | ||
9fe77896 | 7614 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7615 | { |
df58fc94 | 7616 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7617 | reloc_howto_type *howto0; |
9fe77896 RS |
7618 | reloc_howto_type *howto; |
7619 | int i; | |
34ce925e | 7620 | |
df58fc94 RS |
7621 | /* Perform any necessary conversion to microMIPS relocations |
7622 | and find out how many relocations there actually are. */ | |
7623 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7624 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7625 | ||
9fe77896 RS |
7626 | /* In a compound relocation, it is the final (outermost) |
7627 | operator that determines the relocated field. */ | |
2309ddf2 | 7628 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7629 | if (!howto) |
7630 | abort (); | |
2309ddf2 MR |
7631 | |
7632 | if (i > 1) | |
7633 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7634 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7635 | bfd_get_reloc_size (howto), | |
7636 | address_expr, | |
2309ddf2 MR |
7637 | howto0 && howto0->pc_relative, |
7638 | final_type[0]); | |
ce8ad872 MR |
7639 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7640 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7641 | |
7642 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7643 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7644 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7645 | ||
7646 | /* These relocations can have an addend that won't fit in | |
7647 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7648 | if (GPR_SIZE == 64 |
9fe77896 RS |
7649 | && ! howto->partial_inplace |
7650 | && (reloc_type[0] == BFD_RELOC_16 | |
7651 | || reloc_type[0] == BFD_RELOC_32 | |
7652 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7653 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7654 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7655 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7656 | || reloc_type[0] == BFD_RELOC_64 | |
7657 | || reloc_type[0] == BFD_RELOC_CTOR | |
7658 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7659 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7660 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7661 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7662 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7663 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7664 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7665 | || hi16_reloc_p (reloc_type[0]) | |
7666 | || lo16_reloc_p (reloc_type[0]))) | |
7667 | ip->fixp[0]->fx_no_overflow = 1; | |
7668 | ||
ddaf2c41 MR |
7669 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7670 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7671 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7672 | ip->fixp[0]->fx_no_overflow = 1; | |
7673 | ||
9fe77896 RS |
7674 | if (mips_relax.sequence) |
7675 | { | |
7676 | if (mips_relax.first_fixup == 0) | |
7677 | mips_relax.first_fixup = ip->fixp[0]; | |
7678 | } | |
7679 | else if (reloc_needs_lo_p (*reloc_type)) | |
7680 | { | |
7681 | struct mips_hi_fixup *hi_fixup; | |
7682 | ||
7683 | /* Reuse the last entry if it already has a matching %lo. */ | |
7684 | hi_fixup = mips_hi_fixup_list; | |
7685 | if (hi_fixup == 0 | |
7686 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7687 | { |
325801bd | 7688 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7689 | hi_fixup->next = mips_hi_fixup_list; |
7690 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7691 | } |
9fe77896 RS |
7692 | hi_fixup->fixp = ip->fixp[0]; |
7693 | hi_fixup->seg = now_seg; | |
7694 | } | |
252b5132 | 7695 | |
9fe77896 RS |
7696 | /* Add fixups for the second and third relocations, if given. |
7697 | Note that the ABI allows the second relocation to be | |
7698 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7699 | moment we only use RSS_UNDEF, but we could add support | |
7700 | for the others if it ever becomes necessary. */ | |
7701 | for (i = 1; i < 3; i++) | |
7702 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7703 | { | |
7704 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7705 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7706 | FALSE, final_type[i]); |
f6688943 | 7707 | |
9fe77896 RS |
7708 | /* Use fx_tcbit to mark compound relocs. */ |
7709 | ip->fixp[0]->fx_tcbit = 1; | |
7710 | ip->fixp[i]->fx_tcbit = 1; | |
7711 | } | |
252b5132 | 7712 | } |
252b5132 RH |
7713 | |
7714 | /* Update the register mask information. */ | |
4c260379 RS |
7715 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7716 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7717 | |
a4e06468 | 7718 | switch (method) |
252b5132 | 7719 | { |
a4e06468 RS |
7720 | case APPEND_ADD: |
7721 | insert_into_history (0, 1, ip); | |
7722 | break; | |
7723 | ||
7724 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7725 | { |
7726 | struct mips_cl_insn *nop; | |
7727 | ||
7728 | insert_into_history (0, 1, ip); | |
7729 | nop = get_delay_slot_nop (ip); | |
7730 | add_fixed_insn (nop); | |
7731 | insert_into_history (0, 1, nop); | |
7732 | if (mips_relax.sequence) | |
7733 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7734 | } | |
a4e06468 RS |
7735 | break; |
7736 | ||
7737 | case APPEND_ADD_COMPACT: | |
7738 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7739 | if (mips_opts.mips16) |
7740 | { | |
7741 | ip->insn_opcode |= 0x0080; | |
7742 | find_altered_mips16_opcode (ip); | |
7743 | } | |
7744 | /* Convert microMIPS instructions. */ | |
7745 | else if (mips_opts.micromips) | |
7746 | { | |
7747 | /* jr16->jrc */ | |
7748 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7749 | ip->insn_opcode |= 0x0020; | |
7750 | /* b16->bc */ | |
7751 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7752 | ip->insn_opcode = 0x40e00000; | |
7753 | /* beqz16->beqzc, bnez16->bnezc */ | |
7754 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7755 | { | |
7756 | unsigned long regno; | |
7757 | ||
7758 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7759 | regno &= MICROMIPSOP_MASK_MD; | |
7760 | regno = micromips_to_32_reg_d_map[regno]; | |
7761 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7762 | | (regno << MICROMIPSOP_SH_RS) | |
7763 | | 0x40a00000) ^ 0x00400000; | |
7764 | } | |
7765 | /* beqz->beqzc, bnez->bnezc */ | |
7766 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7767 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7768 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7769 | | 0x40a00000) ^ 0x00400000; | |
7770 | /* beq $0->beqzc, bne $0->bnezc */ | |
7771 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7772 | ip->insn_opcode = (((ip->insn_opcode >> | |
7773 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7774 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7775 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7776 | | 0x40a00000) ^ 0x00400000; | |
7777 | else | |
7778 | abort (); | |
7779 | find_altered_micromips_opcode (ip); | |
7780 | } | |
7781 | else | |
7782 | abort (); | |
a4e06468 RS |
7783 | install_insn (ip); |
7784 | insert_into_history (0, 1, ip); | |
7785 | break; | |
7786 | ||
7787 | case APPEND_SWAP: | |
7788 | { | |
7789 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7790 | |
7791 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7792 | { |
7793 | /* Add the delay slot instruction to the end of the | |
7794 | current frag and shrink the fixed part of the | |
7795 | original frag. If the branch occupies the tail of | |
7796 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7797 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7798 | if (delay.frag == ip->frag) |
2b0c8b40 | 7799 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7800 | add_fixed_insn (&delay); |
7801 | } | |
7802 | else | |
7803 | { | |
5e35670b MR |
7804 | /* If this is not a relaxed branch and we are in the |
7805 | same frag, then just swap the instructions. */ | |
7806 | move_insn (ip, delay.frag, delay.where); | |
7807 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7808 | } |
7809 | history[0] = *ip; | |
7810 | delay.fixed_p = 1; | |
7811 | insert_into_history (0, 1, &delay); | |
7812 | } | |
7813 | break; | |
252b5132 RH |
7814 | } |
7815 | ||
13408f1e | 7816 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7817 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7818 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7819 | { |
7820 | unsigned int i; | |
7821 | ||
79850f26 | 7822 | mips_no_prev_insn (); |
13408f1e | 7823 | |
e407c74b | 7824 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7825 | history[i].cleared_p = 1; |
e407c74b NC |
7826 | } |
7827 | ||
df58fc94 RS |
7828 | /* We need to emit a label at the end of branch-likely macros. */ |
7829 | if (emit_branch_likely_macro) | |
7830 | { | |
7831 | emit_branch_likely_macro = FALSE; | |
7832 | micromips_add_label (); | |
7833 | } | |
7834 | ||
252b5132 RH |
7835 | /* We just output an insn, so the next one doesn't have a label. */ |
7836 | mips_clear_insn_labels (); | |
252b5132 RH |
7837 | } |
7838 | ||
e407c74b NC |
7839 | /* Forget that there was any previous instruction or label. |
7840 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7841 | |
7842 | static void | |
7d10b47d | 7843 | mips_no_prev_insn (void) |
252b5132 | 7844 | { |
7d10b47d RS |
7845 | prev_nop_frag = NULL; |
7846 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7847 | mips_clear_insn_labels (); |
7848 | } | |
7849 | ||
7d10b47d RS |
7850 | /* This function must be called before we emit something other than |
7851 | instructions. It is like mips_no_prev_insn except that it inserts | |
7852 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7853 | |
7d10b47d RS |
7854 | void |
7855 | mips_emit_delays (void) | |
252b5132 RH |
7856 | { |
7857 | if (! mips_opts.noreorder) | |
7858 | { | |
932d1a1b | 7859 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7860 | if (nops > 0) |
7861 | { | |
7d10b47d RS |
7862 | while (nops-- > 0) |
7863 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7864 | mips_move_text_labels (); |
7d10b47d RS |
7865 | } |
7866 | } | |
7867 | mips_no_prev_insn (); | |
7868 | } | |
7869 | ||
7870 | /* Start a (possibly nested) noreorder block. */ | |
7871 | ||
7872 | static void | |
7873 | start_noreorder (void) | |
7874 | { | |
7875 | if (mips_opts.noreorder == 0) | |
7876 | { | |
7877 | unsigned int i; | |
7878 | int nops; | |
7879 | ||
7880 | /* None of the instructions before the .set noreorder can be moved. */ | |
7881 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7882 | history[i].fixed_p = 1; | |
7883 | ||
7884 | /* Insert any nops that might be needed between the .set noreorder | |
7885 | block and the previous instructions. We will later remove any | |
7886 | nops that turn out not to be needed. */ | |
932d1a1b | 7887 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7888 | if (nops > 0) |
7889 | { | |
7890 | if (mips_optimize != 0) | |
252b5132 RH |
7891 | { |
7892 | /* Record the frag which holds the nop instructions, so | |
7893 | that we can remove them if we don't need them. */ | |
df58fc94 | 7894 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7895 | prev_nop_frag = frag_now; |
7896 | prev_nop_frag_holds = nops; | |
7897 | prev_nop_frag_required = 0; | |
7898 | prev_nop_frag_since = 0; | |
7899 | } | |
7900 | ||
7901 | for (; nops > 0; --nops) | |
1e915849 | 7902 | add_fixed_insn (NOP_INSN); |
252b5132 | 7903 | |
7d10b47d RS |
7904 | /* Move on to a new frag, so that it is safe to simply |
7905 | decrease the size of prev_nop_frag. */ | |
7906 | frag_wane (frag_now); | |
7907 | frag_new (0); | |
462427c4 | 7908 | mips_move_text_labels (); |
252b5132 | 7909 | } |
df58fc94 | 7910 | mips_mark_labels (); |
7d10b47d | 7911 | mips_clear_insn_labels (); |
252b5132 | 7912 | } |
7d10b47d RS |
7913 | mips_opts.noreorder++; |
7914 | mips_any_noreorder = 1; | |
7915 | } | |
252b5132 | 7916 | |
7d10b47d | 7917 | /* End a nested noreorder block. */ |
252b5132 | 7918 | |
7d10b47d RS |
7919 | static void |
7920 | end_noreorder (void) | |
7921 | { | |
7922 | mips_opts.noreorder--; | |
7923 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7924 | { | |
7925 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7926 | handling nop insertion the .set reorder way. */ | |
7927 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7928 | * NOP_INSN_SIZE); |
7d10b47d RS |
7929 | insert_into_history (prev_nop_frag_since, |
7930 | prev_nop_frag_required, NOP_INSN); | |
7931 | prev_nop_frag = NULL; | |
7932 | } | |
252b5132 RH |
7933 | } |
7934 | ||
97d87491 RS |
7935 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7936 | higher bits unset. */ | |
7937 | ||
7938 | static void | |
7939 | normalize_constant_expr (expressionS *ex) | |
7940 | { | |
7941 | if (ex->X_op == O_constant | |
7942 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7943 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7944 | - 0x80000000); | |
7945 | } | |
7946 | ||
7947 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7948 | all higher bits unset. */ | |
7949 | ||
7950 | static void | |
7951 | normalize_address_expr (expressionS *ex) | |
7952 | { | |
7953 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7954 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7955 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7956 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7957 | - 0x80000000); | |
7958 | } | |
7959 | ||
7960 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7961 | Return true if the match was successful. | |
7962 | ||
7963 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7964 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7965 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7966 | as for mips_arg_info. */ | |
7967 | ||
7968 | static bfd_boolean | |
7969 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7970 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7971 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7972 | { |
7973 | const char *args; | |
7974 | struct mips_arg_info arg; | |
7975 | const struct mips_operand *operand; | |
7976 | char c; | |
7977 | ||
7978 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7979 | offset_expr.X_op = O_absent; |
7980 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7981 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7982 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7983 | ||
7984 | create_insn (insn, opcode); | |
60f20e8b RS |
7985 | /* When no opcode suffix is specified, assume ".xyzw". */ |
7986 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
7987 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
7988 | else | |
7989 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
7990 | memset (&arg, 0, sizeof (arg)); |
7991 | arg.insn = insn; | |
7992 | arg.token = tokens; | |
7993 | arg.argnum = 1; | |
7994 | arg.last_regno = ILLEGAL_REG; | |
7995 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 7996 | arg.lax_match = lax_match; |
97d87491 RS |
7997 | for (args = opcode->args;; ++args) |
7998 | { | |
7999 | if (arg.token->type == OT_END) | |
8000 | { | |
8001 | /* Handle unary instructions in which only one operand is given. | |
8002 | The source is then the same as the destination. */ | |
8003 | if (arg.opnum == 1 && *args == ',') | |
8004 | { | |
8005 | operand = (mips_opts.micromips | |
8006 | ? decode_micromips_operand (args + 1) | |
8007 | : decode_mips_operand (args + 1)); | |
8008 | if (operand && mips_optional_operand_p (operand)) | |
8009 | { | |
8010 | arg.token = tokens; | |
8011 | arg.argnum = 1; | |
8012 | continue; | |
8013 | } | |
8014 | } | |
8015 | ||
8016 | /* Treat elided base registers as $0. */ | |
8017 | if (strcmp (args, "(b)") == 0) | |
8018 | args += 3; | |
8019 | ||
8020 | if (args[0] == '+') | |
8021 | switch (args[1]) | |
8022 | { | |
8023 | case 'K': | |
8024 | case 'N': | |
8025 | /* The register suffix is optional. */ | |
8026 | args += 2; | |
8027 | break; | |
8028 | } | |
8029 | ||
8030 | /* Fail the match if there were too few operands. */ | |
8031 | if (*args) | |
8032 | return FALSE; | |
8033 | ||
8034 | /* Successful match. */ | |
60f20e8b RS |
8035 | if (!complete_p) |
8036 | return TRUE; | |
e3de51ce | 8037 | clear_insn_error (); |
97d87491 RS |
8038 | if (arg.dest_regno == arg.last_regno |
8039 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8040 | { | |
8041 | if (arg.opnum == 2) | |
e3de51ce | 8042 | set_insn_error |
1661c76c | 8043 | (0, _("source and destination must be different")); |
97d87491 | 8044 | else if (arg.last_regno == 31) |
e3de51ce | 8045 | set_insn_error |
1661c76c | 8046 | (0, _("a destination register must be supplied")); |
97d87491 | 8047 | } |
173d3447 CF |
8048 | else if (arg.last_regno == 31 |
8049 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8050 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8051 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8052 | check_completed_insn (&arg); |
8053 | return TRUE; | |
8054 | } | |
8055 | ||
8056 | /* Fail the match if the line has too many operands. */ | |
8057 | if (*args == 0) | |
8058 | return FALSE; | |
8059 | ||
8060 | /* Handle characters that need to match exactly. */ | |
8061 | if (*args == '(' || *args == ')' || *args == ',') | |
8062 | { | |
8063 | if (match_char (&arg, *args)) | |
8064 | continue; | |
8065 | return FALSE; | |
8066 | } | |
8067 | if (*args == '#') | |
8068 | { | |
8069 | ++args; | |
8070 | if (arg.token->type == OT_DOUBLE_CHAR | |
8071 | && arg.token->u.ch == *args) | |
8072 | { | |
8073 | ++arg.token; | |
8074 | continue; | |
8075 | } | |
8076 | return FALSE; | |
8077 | } | |
8078 | ||
8079 | /* Handle special macro operands. Work out the properties of | |
8080 | other operands. */ | |
8081 | arg.opnum += 1; | |
97d87491 RS |
8082 | switch (*args) |
8083 | { | |
7361da2c AB |
8084 | case '-': |
8085 | switch (args[1]) | |
8086 | { | |
8087 | case 'A': | |
8088 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8089 | break; | |
8090 | ||
8091 | case 'B': | |
8092 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8093 | break; | |
8094 | } | |
8095 | break; | |
8096 | ||
97d87491 RS |
8097 | case '+': |
8098 | switch (args[1]) | |
8099 | { | |
97d87491 RS |
8100 | case 'i': |
8101 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8102 | break; | |
7361da2c AB |
8103 | |
8104 | case '\'': | |
8105 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8106 | break; | |
8107 | ||
8108 | case '\"': | |
8109 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8110 | break; | |
97d87491 RS |
8111 | } |
8112 | break; | |
8113 | ||
97d87491 | 8114 | case 'I': |
1a00e612 RS |
8115 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8116 | return FALSE; | |
8117 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8118 | if (GPR_SIZE == 32) |
97d87491 RS |
8119 | normalize_constant_expr (&imm_expr); |
8120 | continue; | |
8121 | ||
8122 | case 'A': | |
8123 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8124 | { | |
8125 | /* Assume that the offset has been elided and that what | |
8126 | we saw was a base register. The match will fail later | |
8127 | if that assumption turns out to be wrong. */ | |
8128 | offset_expr.X_op = O_constant; | |
8129 | offset_expr.X_add_number = 0; | |
8130 | } | |
97d87491 | 8131 | else |
1a00e612 RS |
8132 | { |
8133 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8134 | return FALSE; | |
8135 | normalize_address_expr (&offset_expr); | |
8136 | } | |
97d87491 RS |
8137 | continue; |
8138 | ||
8139 | case 'F': | |
8140 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8141 | 8, TRUE)) | |
1a00e612 | 8142 | return FALSE; |
97d87491 RS |
8143 | continue; |
8144 | ||
8145 | case 'L': | |
8146 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8147 | 8, FALSE)) | |
1a00e612 | 8148 | return FALSE; |
97d87491 RS |
8149 | continue; |
8150 | ||
8151 | case 'f': | |
8152 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8153 | 4, TRUE)) | |
1a00e612 | 8154 | return FALSE; |
97d87491 RS |
8155 | continue; |
8156 | ||
8157 | case 'l': | |
8158 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8159 | 4, FALSE)) | |
1a00e612 | 8160 | return FALSE; |
97d87491 RS |
8161 | continue; |
8162 | ||
97d87491 RS |
8163 | case 'p': |
8164 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8165 | break; | |
8166 | ||
8167 | case 'a': | |
8168 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8169 | break; | |
8170 | ||
8171 | case 'm': | |
8172 | gas_assert (mips_opts.micromips); | |
8173 | c = args[1]; | |
8174 | switch (c) | |
8175 | { | |
8176 | case 'D': | |
8177 | case 'E': | |
8178 | if (!forced_insn_length) | |
8179 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8180 | else if (c == 'D') | |
8181 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8182 | else | |
8183 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8184 | break; | |
8185 | } | |
8186 | break; | |
8187 | } | |
8188 | ||
8189 | operand = (mips_opts.micromips | |
8190 | ? decode_micromips_operand (args) | |
8191 | : decode_mips_operand (args)); | |
8192 | if (!operand) | |
8193 | abort (); | |
8194 | ||
8195 | /* Skip prefixes. */ | |
7361da2c | 8196 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8197 | args++; |
8198 | ||
8199 | if (mips_optional_operand_p (operand) | |
8200 | && args[1] == ',' | |
8201 | && (arg.token[0].type != OT_REG | |
8202 | || arg.token[1].type == OT_END)) | |
8203 | { | |
8204 | /* Assume that the register has been elided and is the | |
8205 | same as the first operand. */ | |
8206 | arg.token = tokens; | |
8207 | arg.argnum = 1; | |
8208 | } | |
8209 | ||
8210 | if (!match_operand (&arg, operand)) | |
8211 | return FALSE; | |
8212 | } | |
8213 | } | |
8214 | ||
8215 | /* Like match_insn, but for MIPS16. */ | |
8216 | ||
8217 | static bfd_boolean | |
8218 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8219 | struct mips_operand_token *tokens) |
97d87491 RS |
8220 | { |
8221 | const char *args; | |
8222 | const struct mips_operand *operand; | |
8223 | const struct mips_operand *ext_operand; | |
82d808ed | 8224 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8225 | int required_insn_length; |
97d87491 RS |
8226 | struct mips_arg_info arg; |
8227 | int relax_char; | |
8228 | ||
7fd53920 MR |
8229 | if (forced_insn_length) |
8230 | required_insn_length = forced_insn_length; | |
8231 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8232 | required_insn_length = 2; | |
8233 | else | |
8234 | required_insn_length = 0; | |
8235 | ||
97d87491 RS |
8236 | create_insn (insn, opcode); |
8237 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8238 | offset_expr.X_op = O_absent; |
8239 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8240 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8241 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8242 | relax_char = 0; | |
8243 | ||
8244 | memset (&arg, 0, sizeof (arg)); | |
8245 | arg.insn = insn; | |
8246 | arg.token = tokens; | |
8247 | arg.argnum = 1; | |
8248 | arg.last_regno = ILLEGAL_REG; | |
8249 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8250 | relax_char = 0; |
8251 | for (args = opcode->args;; ++args) | |
8252 | { | |
8253 | int c; | |
8254 | ||
8255 | if (arg.token->type == OT_END) | |
8256 | { | |
8257 | offsetT value; | |
8258 | ||
8259 | /* Handle unary instructions in which only one operand is given. | |
8260 | The source is then the same as the destination. */ | |
8261 | if (arg.opnum == 1 && *args == ',') | |
8262 | { | |
8263 | operand = decode_mips16_operand (args[1], FALSE); | |
8264 | if (operand && mips_optional_operand_p (operand)) | |
8265 | { | |
8266 | arg.token = tokens; | |
8267 | arg.argnum = 1; | |
8268 | continue; | |
8269 | } | |
8270 | } | |
8271 | ||
8272 | /* Fail the match if there were too few operands. */ | |
8273 | if (*args) | |
8274 | return FALSE; | |
8275 | ||
8276 | /* Successful match. Stuff the immediate value in now, if | |
8277 | we can. */ | |
e3de51ce | 8278 | clear_insn_error (); |
97d87491 RS |
8279 | if (opcode->pinfo == INSN_MACRO) |
8280 | { | |
8281 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8282 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8283 | } | |
8284 | else if (relax_char | |
8285 | && offset_expr.X_op == O_constant | |
82d808ed | 8286 | && !pcrel |
97d87491 RS |
8287 | && calculate_reloc (*offset_reloc, |
8288 | offset_expr.X_add_number, | |
8289 | &value)) | |
8290 | { | |
8291 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8292 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8293 | offset_expr.X_op = O_absent; |
8294 | *offset_reloc = BFD_RELOC_UNUSED; | |
8295 | } | |
8296 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8297 | { | |
7fd53920 | 8298 | if (required_insn_length == 2) |
e3de51ce | 8299 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8300 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8301 | { |
8302 | forced_insn_length = 4; | |
8303 | insn->insn_opcode |= MIPS16_EXTEND; | |
8304 | } | |
97d87491 RS |
8305 | } |
8306 | else if (relax_char) | |
8307 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8308 | ||
8309 | check_completed_insn (&arg); | |
8310 | return TRUE; | |
8311 | } | |
8312 | ||
8313 | /* Fail the match if the line has too many operands. */ | |
8314 | if (*args == 0) | |
8315 | return FALSE; | |
8316 | ||
8317 | /* Handle characters that need to match exactly. */ | |
8318 | if (*args == '(' || *args == ')' || *args == ',') | |
8319 | { | |
8320 | if (match_char (&arg, *args)) | |
8321 | continue; | |
8322 | return FALSE; | |
8323 | } | |
8324 | ||
8325 | arg.opnum += 1; | |
8326 | c = *args; | |
8327 | switch (c) | |
8328 | { | |
8329 | case 'p': | |
8330 | case 'q': | |
8331 | case 'A': | |
8332 | case 'B': | |
8333 | case 'E': | |
25499ac7 MR |
8334 | case 'V': |
8335 | case 'u': | |
97d87491 RS |
8336 | relax_char = c; |
8337 | break; | |
8338 | ||
8339 | case 'I': | |
1a00e612 RS |
8340 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8341 | return FALSE; | |
8342 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8343 | if (GPR_SIZE == 32) |
97d87491 RS |
8344 | normalize_constant_expr (&imm_expr); |
8345 | continue; | |
8346 | ||
8347 | case 'a': | |
8348 | case 'i': | |
8349 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8350 | break; |
8351 | } | |
8352 | ||
7fd53920 | 8353 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8354 | if (!operand) |
8355 | abort (); | |
8356 | ||
82d808ed MR |
8357 | if (operand->type == OP_PCREL) |
8358 | pcrel = TRUE; | |
8359 | else | |
97d87491 RS |
8360 | { |
8361 | ext_operand = decode_mips16_operand (c, TRUE); | |
8362 | if (operand != ext_operand) | |
8363 | { | |
8364 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8365 | { | |
8366 | offset_expr.X_op = O_constant; | |
8367 | offset_expr.X_add_number = 0; | |
8368 | relax_char = c; | |
8369 | continue; | |
8370 | } | |
8371 | ||
1a7bf198 | 8372 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8373 | return FALSE; |
8374 | ||
8375 | /* '8' is used for SLTI(U) and has traditionally not | |
8376 | been allowed to take relocation operators. */ | |
8377 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8378 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8379 | { |
8380 | match_not_constant (&arg); | |
8381 | return FALSE; | |
8382 | } | |
97d87491 | 8383 | |
c96425c5 MR |
8384 | if (offset_expr.X_op == O_big) |
8385 | { | |
8386 | match_out_of_range (&arg); | |
8387 | return FALSE; | |
8388 | } | |
8389 | ||
97d87491 RS |
8390 | relax_char = c; |
8391 | continue; | |
8392 | } | |
8393 | } | |
8394 | ||
8395 | if (mips_optional_operand_p (operand) | |
8396 | && args[1] == ',' | |
8397 | && (arg.token[0].type != OT_REG | |
8398 | || arg.token[1].type == OT_END)) | |
8399 | { | |
8400 | /* Assume that the register has been elided and is the | |
8401 | same as the first operand. */ | |
8402 | arg.token = tokens; | |
8403 | arg.argnum = 1; | |
8404 | } | |
8405 | ||
8406 | if (!match_operand (&arg, operand)) | |
8407 | return FALSE; | |
8408 | } | |
8409 | } | |
8410 | ||
60f20e8b RS |
8411 | /* Record that the current instruction is invalid for the current ISA. */ |
8412 | ||
8413 | static void | |
8414 | match_invalid_for_isa (void) | |
8415 | { | |
8416 | set_insn_error_ss | |
1661c76c | 8417 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8418 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8419 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8420 | } | |
8421 | ||
8422 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8423 | Return true if a definite match or failure was found, storing any match | |
8424 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8425 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8426 | tried and failed to match under normal conditions and now want to try a | |
8427 | more relaxed match. */ | |
8428 | ||
8429 | static bfd_boolean | |
8430 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8431 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8432 | int opcode_extra, bfd_boolean lax_match) | |
8433 | { | |
8434 | const struct mips_opcode *opcode; | |
8435 | const struct mips_opcode *invalid_delay_slot; | |
8436 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8437 | ||
8438 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8439 | current ISA or forced_length. */ | |
8440 | invalid_delay_slot = 0; | |
8441 | seen_valid_for_isa = FALSE; | |
8442 | seen_valid_for_size = FALSE; | |
8443 | opcode = first; | |
8444 | do | |
8445 | { | |
8446 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8447 | if (is_opcode_valid (opcode)) | |
8448 | { | |
8449 | seen_valid_for_isa = TRUE; | |
8450 | if (is_size_valid (opcode)) | |
8451 | { | |
8452 | bfd_boolean delay_slot_ok; | |
8453 | ||
8454 | seen_valid_for_size = TRUE; | |
8455 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8456 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8457 | lax_match, delay_slot_ok)) | |
8458 | { | |
8459 | if (!delay_slot_ok) | |
8460 | { | |
8461 | if (!invalid_delay_slot) | |
8462 | invalid_delay_slot = opcode; | |
8463 | } | |
8464 | else | |
8465 | return TRUE; | |
8466 | } | |
8467 | } | |
8468 | } | |
8469 | ++opcode; | |
8470 | } | |
8471 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8472 | ||
8473 | /* If the only matches we found had the wrong length for the delay slot, | |
8474 | pick the first such match. We'll issue an appropriate warning later. */ | |
8475 | if (invalid_delay_slot) | |
8476 | { | |
8477 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8478 | lax_match, TRUE)) | |
8479 | return TRUE; | |
8480 | abort (); | |
8481 | } | |
8482 | ||
8483 | /* Handle the case where we didn't try to match an instruction because | |
8484 | all the alternatives were incompatible with the current ISA. */ | |
8485 | if (!seen_valid_for_isa) | |
8486 | { | |
8487 | match_invalid_for_isa (); | |
8488 | return TRUE; | |
8489 | } | |
8490 | ||
8491 | /* Handle the case where we didn't try to match an instruction because | |
8492 | all the alternatives were of the wrong size. */ | |
8493 | if (!seen_valid_for_size) | |
8494 | { | |
8495 | if (mips_opts.insn32) | |
1661c76c | 8496 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8497 | else |
8498 | set_insn_error_i | |
1661c76c | 8499 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8500 | 8 * forced_insn_length); |
8501 | return TRUE; | |
8502 | } | |
8503 | ||
8504 | return FALSE; | |
8505 | } | |
8506 | ||
8507 | /* Like match_insns, but for MIPS16. */ | |
8508 | ||
8509 | static bfd_boolean | |
8510 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8511 | struct mips_operand_token *tokens) | |
8512 | { | |
8513 | const struct mips_opcode *opcode; | |
8514 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8515 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8516 | |
8517 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8518 | current ISA. There are no separate entries for extended forms so | |
8519 | we deal with forced_length later. */ | |
8520 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8521 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8522 | opcode = first; |
8523 | do | |
8524 | { | |
8525 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8526 | if (is_opcode_valid_16 (opcode)) | |
8527 | { | |
8528 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8529 | if (is_size_valid_16 (opcode)) |
8530 | { | |
8531 | seen_valid_for_size = TRUE; | |
8532 | if (match_mips16_insn (insn, opcode, tokens)) | |
8533 | return TRUE; | |
8534 | } | |
60f20e8b RS |
8535 | } |
8536 | ++opcode; | |
8537 | } | |
8538 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8539 | && strcmp (opcode->name, first->name) == 0); | |
8540 | ||
8541 | /* Handle the case where we didn't try to match an instruction because | |
8542 | all the alternatives were incompatible with the current ISA. */ | |
8543 | if (!seen_valid_for_isa) | |
8544 | { | |
8545 | match_invalid_for_isa (); | |
8546 | return TRUE; | |
8547 | } | |
8548 | ||
7fd53920 MR |
8549 | /* Handle the case where we didn't try to match an instruction because |
8550 | all the alternatives were of the wrong size. */ | |
8551 | if (!seen_valid_for_size) | |
8552 | { | |
8553 | if (forced_insn_length == 2) | |
8554 | set_insn_error | |
8555 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8556 | else | |
8557 | set_insn_error | |
8558 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8559 | return TRUE; | |
8560 | } | |
8561 | ||
60f20e8b RS |
8562 | return FALSE; |
8563 | } | |
8564 | ||
584892a6 RS |
8565 | /* Set up global variables for the start of a new macro. */ |
8566 | ||
8567 | static void | |
8568 | macro_start (void) | |
8569 | { | |
8570 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8571 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8572 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8573 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8574 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8575 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8576 | if (history[0].frag |
8577 | && history[0].frag->fr_type == rs_machine_dependent | |
8578 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8579 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8580 | mips_macro_warning.delay_slot_length = 0; | |
8581 | else | |
8582 | switch (history[0].insn_mo->pinfo2 | |
8583 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8584 | { | |
8585 | case INSN2_BRANCH_DELAY_32BIT: | |
8586 | mips_macro_warning.delay_slot_length = 4; | |
8587 | break; | |
8588 | case INSN2_BRANCH_DELAY_16BIT: | |
8589 | mips_macro_warning.delay_slot_length = 2; | |
8590 | break; | |
8591 | default: | |
8592 | mips_macro_warning.delay_slot_length = 0; | |
8593 | break; | |
8594 | } | |
df58fc94 | 8595 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8596 | } |
8597 | ||
df58fc94 RS |
8598 | /* Given that a macro is longer than one instruction or of the wrong size, |
8599 | return the appropriate warning for it. Return null if no warning is | |
8600 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8601 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8602 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8603 | |
8604 | static const char * | |
8605 | macro_warning (relax_substateT subtype) | |
8606 | { | |
8607 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8608 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8609 | " in a branch delay slot"); |
8610 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8611 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8612 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8613 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8614 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8615 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8616 | " in a 16-bit branch delay slot") |
1661c76c | 8617 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8618 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8619 | else |
8620 | return 0; | |
8621 | } | |
8622 | ||
8623 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8624 | ||
8625 | static void | |
8626 | macro_end (void) | |
8627 | { | |
df58fc94 RS |
8628 | /* Relaxation warning flags. */ |
8629 | relax_substateT subtype = 0; | |
8630 | ||
8631 | /* Check delay slot size requirements. */ | |
8632 | if (mips_macro_warning.delay_slot_length == 2) | |
8633 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8634 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8635 | { |
df58fc94 RS |
8636 | if (mips_macro_warning.delay_slot_length |
8637 | != mips_macro_warning.first_insn_sizes[0]) | |
8638 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8639 | if (mips_macro_warning.delay_slot_length | |
8640 | != mips_macro_warning.first_insn_sizes[1]) | |
8641 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8642 | } | |
584892a6 | 8643 | |
df58fc94 RS |
8644 | /* Check instruction count requirements. */ |
8645 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8646 | { | |
8647 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8648 | subtype |= RELAX_SECOND_LONGER; |
8649 | if (mips_opts.warn_about_macros) | |
8650 | subtype |= RELAX_NOMACRO; | |
8651 | if (mips_macro_warning.delay_slot_p) | |
8652 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8653 | } |
584892a6 | 8654 | |
df58fc94 RS |
8655 | /* If both alternatives fail to fill a delay slot correctly, |
8656 | emit the warning now. */ | |
8657 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8658 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8659 | { | |
8660 | relax_substateT s; | |
8661 | const char *msg; | |
8662 | ||
8663 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8664 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8665 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8666 | msg = macro_warning (s); | |
8667 | if (msg != NULL) | |
8668 | as_warn ("%s", msg); | |
8669 | subtype &= ~s; | |
8670 | } | |
8671 | ||
8672 | /* If both implementations are longer than 1 instruction, then emit the | |
8673 | warning now. */ | |
8674 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8675 | { | |
8676 | relax_substateT s; | |
8677 | const char *msg; | |
8678 | ||
8679 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8680 | msg = macro_warning (s); | |
8681 | if (msg != NULL) | |
8682 | as_warn ("%s", msg); | |
8683 | subtype &= ~s; | |
584892a6 | 8684 | } |
df58fc94 RS |
8685 | |
8686 | /* If any flags still set, then one implementation might need a warning | |
8687 | and the other either will need one of a different kind or none at all. | |
8688 | Pass any remaining flags over to relaxation. */ | |
8689 | if (mips_macro_warning.first_frag != NULL) | |
8690 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8691 | } |
8692 | ||
df58fc94 RS |
8693 | /* Instruction operand formats used in macros that vary between |
8694 | standard MIPS and microMIPS code. */ | |
8695 | ||
833794fc | 8696 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8697 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8698 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8699 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8700 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8701 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8702 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8703 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8704 | ||
833794fc | 8705 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8706 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8707 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8708 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8709 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8710 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8711 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8712 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8713 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8714 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8715 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8716 | ||
6e1304d8 RS |
8717 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8718 | The first argument in *ARGS will be either the code for a single | |
8719 | relocation or -1 followed by the three codes that make up a | |
8720 | composite relocation. */ | |
8721 | ||
8722 | static void | |
8723 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8724 | { | |
8725 | int i, next; | |
8726 | ||
8727 | next = va_arg (*args, int); | |
8728 | if (next >= 0) | |
8729 | r[0] = (bfd_reloc_code_real_type) next; | |
8730 | else | |
f2ae14a1 RS |
8731 | { |
8732 | for (i = 0; i < 3; i++) | |
8733 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8734 | /* This function is only used for 16-bit relocation fields. | |
8735 | To make the macro code simpler, treat an unrelocated value | |
8736 | in the same way as BFD_RELOC_LO16. */ | |
8737 | if (r[0] == BFD_RELOC_UNUSED) | |
8738 | r[0] = BFD_RELOC_LO16; | |
8739 | } | |
6e1304d8 RS |
8740 | } |
8741 | ||
252b5132 RH |
8742 | /* Build an instruction created by a macro expansion. This is passed |
8743 | a pointer to the count of instructions created so far, an | |
8744 | expression, the name of the instruction to build, an operand format | |
8745 | string, and corresponding arguments. */ | |
8746 | ||
252b5132 | 8747 | static void |
67c0d1eb | 8748 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8749 | { |
df58fc94 | 8750 | const struct mips_opcode *mo = NULL; |
f6688943 | 8751 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8752 | const struct mips_opcode *amo; |
e077a1c8 | 8753 | const struct mips_operand *operand; |
df58fc94 RS |
8754 | struct hash_control *hash; |
8755 | struct mips_cl_insn insn; | |
252b5132 | 8756 | va_list args; |
e077a1c8 | 8757 | unsigned int uval; |
252b5132 | 8758 | |
252b5132 | 8759 | va_start (args, fmt); |
252b5132 | 8760 | |
252b5132 RH |
8761 | if (mips_opts.mips16) |
8762 | { | |
03ea81db | 8763 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8764 | va_end (args); |
8765 | return; | |
8766 | } | |
8767 | ||
f6688943 TS |
8768 | r[0] = BFD_RELOC_UNUSED; |
8769 | r[1] = BFD_RELOC_UNUSED; | |
8770 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8771 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8772 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8773 | gas_assert (amo); | |
8774 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8775 | |
df58fc94 | 8776 | do |
8b082fb1 TS |
8777 | { |
8778 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8779 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8780 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8781 | slot instruction length requirement (if any) of the previous |
8782 | instruction. While doing this we record the first instruction | |
8783 | seen that matches all the other conditions and use it anyway | |
8784 | if the requirement cannot be met; we will issue an appropriate | |
8785 | warning later on. */ | |
8786 | if (strcmp (fmt, amo->args) == 0 | |
8787 | && amo->pinfo != INSN_MACRO | |
8788 | && is_opcode_valid (amo) | |
8789 | && is_size_valid (amo)) | |
8790 | { | |
8791 | if (is_delay_slot_valid (amo)) | |
8792 | { | |
8793 | mo = amo; | |
8794 | break; | |
8795 | } | |
8796 | else if (!mo) | |
8797 | mo = amo; | |
8798 | } | |
8b082fb1 | 8799 | |
df58fc94 RS |
8800 | ++amo; |
8801 | gas_assert (amo->name); | |
252b5132 | 8802 | } |
df58fc94 | 8803 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8804 | |
df58fc94 | 8805 | gas_assert (mo); |
1e915849 | 8806 | create_insn (&insn, mo); |
e077a1c8 | 8807 | for (; *fmt; ++fmt) |
252b5132 | 8808 | { |
e077a1c8 | 8809 | switch (*fmt) |
252b5132 | 8810 | { |
252b5132 RH |
8811 | case ',': |
8812 | case '(': | |
8813 | case ')': | |
252b5132 | 8814 | case 'z': |
e077a1c8 | 8815 | break; |
252b5132 RH |
8816 | |
8817 | case 'i': | |
8818 | case 'j': | |
6e1304d8 | 8819 | macro_read_relocs (&args, r); |
9c2799c2 | 8820 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8821 | || *r == BFD_RELOC_MIPS_HIGHER |
8822 | || *r == BFD_RELOC_HI16_S | |
8823 | || *r == BFD_RELOC_LO16 | |
8824 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 8825 | break; |
e391c024 RS |
8826 | |
8827 | case 'o': | |
8828 | macro_read_relocs (&args, r); | |
e077a1c8 | 8829 | break; |
252b5132 RH |
8830 | |
8831 | case 'u': | |
6e1304d8 | 8832 | macro_read_relocs (&args, r); |
9c2799c2 | 8833 | gas_assert (ep != NULL |
90ecf173 MR |
8834 | && (ep->X_op == O_constant |
8835 | || (ep->X_op == O_symbol | |
8836 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8837 | || *r == BFD_RELOC_HI16_S | |
8838 | || *r == BFD_RELOC_HI16 | |
8839 | || *r == BFD_RELOC_GPREL16 | |
8840 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8841 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8842 | break; |
252b5132 RH |
8843 | |
8844 | case 'p': | |
9c2799c2 | 8845 | gas_assert (ep != NULL); |
bad36eac | 8846 | |
252b5132 RH |
8847 | /* |
8848 | * This allows macro() to pass an immediate expression for | |
8849 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8850 | * |
8851 | * We don't allow branch relaxation for these branches, as | |
8852 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8853 | */ |
8854 | if (ep->X_op == O_constant) | |
8855 | { | |
df58fc94 RS |
8856 | /* For microMIPS we always use relocations for branches. |
8857 | So we should not resolve immediate values. */ | |
8858 | gas_assert (!mips_opts.micromips); | |
8859 | ||
bad36eac DJ |
8860 | if ((ep->X_add_number & 3) != 0) |
8861 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8862 | (unsigned long) ep->X_add_number); | |
8863 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8864 | as_bad (_("branch address range overflow (0x%lx)"), | |
8865 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8866 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8867 | ep = NULL; | |
8868 | } | |
8869 | else | |
0b25d3e6 | 8870 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8871 | break; |
252b5132 RH |
8872 | |
8873 | case 'a': | |
9c2799c2 | 8874 | gas_assert (ep != NULL); |
f6688943 | 8875 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8876 | break; |
d43b4baf | 8877 | |
252b5132 | 8878 | default: |
e077a1c8 RS |
8879 | operand = (mips_opts.micromips |
8880 | ? decode_micromips_operand (fmt) | |
8881 | : decode_mips_operand (fmt)); | |
8882 | if (!operand) | |
8883 | abort (); | |
8884 | ||
8885 | uval = va_arg (args, int); | |
8886 | if (operand->type == OP_CLO_CLZ_DEST) | |
8887 | uval |= (uval << 5); | |
8888 | insn_insert_operand (&insn, operand, uval); | |
8889 | ||
7361da2c | 8890 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8891 | ++fmt; |
8892 | break; | |
252b5132 | 8893 | } |
252b5132 RH |
8894 | } |
8895 | va_end (args); | |
9c2799c2 | 8896 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8897 | |
df58fc94 | 8898 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8899 | } |
8900 | ||
8901 | static void | |
67c0d1eb | 8902 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8903 | va_list *args) |
252b5132 | 8904 | { |
1e915849 | 8905 | struct mips_opcode *mo; |
252b5132 | 8906 | struct mips_cl_insn insn; |
e077a1c8 | 8907 | const struct mips_operand *operand; |
f6688943 TS |
8908 | bfd_reloc_code_real_type r[3] |
8909 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8910 | |
1e915849 | 8911 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8912 | gas_assert (mo); |
8913 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8914 | |
1e915849 | 8915 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8916 | { |
1e915849 | 8917 | ++mo; |
9c2799c2 NC |
8918 | gas_assert (mo->name); |
8919 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8920 | } |
8921 | ||
1e915849 | 8922 | create_insn (&insn, mo); |
e077a1c8 | 8923 | for (; *fmt; ++fmt) |
252b5132 RH |
8924 | { |
8925 | int c; | |
8926 | ||
e077a1c8 | 8927 | c = *fmt; |
252b5132 RH |
8928 | switch (c) |
8929 | { | |
252b5132 RH |
8930 | case ',': |
8931 | case '(': | |
8932 | case ')': | |
e077a1c8 | 8933 | break; |
252b5132 | 8934 | |
d8722d76 | 8935 | case '.': |
252b5132 RH |
8936 | case 'S': |
8937 | case 'P': | |
8938 | case 'R': | |
e077a1c8 | 8939 | break; |
252b5132 RH |
8940 | |
8941 | case '<': | |
252b5132 | 8942 | case '5': |
d8722d76 | 8943 | case 'F': |
252b5132 RH |
8944 | case 'H': |
8945 | case 'W': | |
8946 | case 'D': | |
8947 | case 'j': | |
8948 | case '8': | |
8949 | case 'V': | |
8950 | case 'C': | |
8951 | case 'U': | |
8952 | case 'k': | |
8953 | case 'K': | |
8954 | case 'p': | |
8955 | case 'q': | |
8956 | { | |
b886a2ab RS |
8957 | offsetT value; |
8958 | ||
9c2799c2 | 8959 | gas_assert (ep != NULL); |
252b5132 RH |
8960 | |
8961 | if (ep->X_op != O_constant) | |
874e8986 | 8962 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8963 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8964 | { |
b886a2ab | 8965 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8966 | ep = NULL; |
f6688943 | 8967 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8968 | } |
8969 | } | |
e077a1c8 | 8970 | break; |
252b5132 | 8971 | |
e077a1c8 RS |
8972 | default: |
8973 | operand = decode_mips16_operand (c, FALSE); | |
8974 | if (!operand) | |
8975 | abort (); | |
252b5132 | 8976 | |
4a06e5a2 | 8977 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8978 | break; |
8979 | } | |
252b5132 RH |
8980 | } |
8981 | ||
9c2799c2 | 8982 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8983 | |
df58fc94 | 8984 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8985 | } |
8986 | ||
438c16b8 TS |
8987 | /* |
8988 | * Generate a "jalr" instruction with a relocation hint to the called | |
8989 | * function. This occurs in NewABI PIC code. | |
8990 | */ | |
8991 | static void | |
df58fc94 | 8992 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 8993 | { |
df58fc94 RS |
8994 | static const bfd_reloc_code_real_type jalr_relocs[2] |
8995 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
8996 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
8997 | const char *jalr; | |
685736be | 8998 | char *f = NULL; |
b34976b6 | 8999 | |
1180b5a4 | 9000 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9001 | { |
cc3d92a5 | 9002 | frag_grow (8); |
f21f8242 AO |
9003 | f = frag_more (0); |
9004 | } | |
2906b037 | 9005 | if (mips_opts.micromips) |
df58fc94 | 9006 | { |
833794fc MR |
9007 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9008 | ? "jalr" : "jalrs"); | |
e64af278 | 9009 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9010 | || mips_opts.insn32 |
e64af278 | 9011 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9012 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9013 | else | |
9014 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9015 | } | |
2906b037 MR |
9016 | else |
9017 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9018 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9019 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9020 | } |
9021 | ||
252b5132 RH |
9022 | /* |
9023 | * Generate a "lui" instruction. | |
9024 | */ | |
9025 | static void | |
67c0d1eb | 9026 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9027 | { |
9c2799c2 | 9028 | gas_assert (! mips_opts.mips16); |
252b5132 | 9029 | |
df58fc94 | 9030 | if (ep->X_op != O_constant) |
252b5132 | 9031 | { |
9c2799c2 | 9032 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9033 | /* _gp_disp is a special case, used from s_cpload. |
9034 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9035 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9036 | || (! HAVE_NEWABI |
aa6975fb ILT |
9037 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9038 | || (! mips_in_shared | |
bbe506e8 TS |
9039 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9040 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9041 | } |
9042 | ||
df58fc94 | 9043 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9044 | } |
9045 | ||
885add95 CD |
9046 | /* Generate a sequence of instructions to do a load or store from a constant |
9047 | offset off of a base register (breg) into/from a target register (treg), | |
9048 | using AT if necessary. */ | |
9049 | static void | |
67c0d1eb RS |
9050 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9051 | int treg, int breg, int dbl) | |
885add95 | 9052 | { |
9c2799c2 | 9053 | gas_assert (ep->X_op == O_constant); |
885add95 | 9054 | |
256ab948 | 9055 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9056 | if (!dbl) |
9057 | normalize_constant_expr (ep); | |
256ab948 | 9058 | |
67c1ffbe | 9059 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9060 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9061 | as_warn (_("operand overflow")); |
9062 | ||
9063 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9064 | { | |
9065 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9066 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9067 | } |
9068 | else | |
9069 | { | |
9070 | /* 32-bit offset, need multiple instructions and AT, like: | |
9071 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9072 | addu $tempreg,$tempreg,$breg | |
9073 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9074 | to handle the complete offset. */ | |
67c0d1eb RS |
9075 | macro_build_lui (ep, AT); |
9076 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9077 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9078 | |
741fe287 | 9079 | if (!mips_opts.at) |
1661c76c | 9080 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9081 | } |
9082 | } | |
9083 | ||
252b5132 RH |
9084 | /* set_at() |
9085 | * Generates code to set the $at register to true (one) | |
9086 | * if reg is less than the immediate expression. | |
9087 | */ | |
9088 | static void | |
67c0d1eb | 9089 | set_at (int reg, int unsignedp) |
252b5132 | 9090 | { |
b0e6f033 | 9091 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9092 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9093 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9094 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9095 | else |
9096 | { | |
bad1aba3 | 9097 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9098 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9099 | } |
9100 | } | |
9101 | ||
252b5132 RH |
9102 | /* Count the leading zeroes by performing a binary chop. This is a |
9103 | bulky bit of source, but performance is a LOT better for the | |
9104 | majority of values than a simple loop to count the bits: | |
9105 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9106 | if ((v) & (1 << (31 - lcnt))) | |
9107 | break; | |
9108 | However it is not code size friendly, and the gain will drop a bit | |
9109 | on certain cached systems. | |
9110 | */ | |
9111 | #define COUNT_TOP_ZEROES(v) \ | |
9112 | (((v) & ~0xffff) == 0 \ | |
9113 | ? ((v) & ~0xff) == 0 \ | |
9114 | ? ((v) & ~0xf) == 0 \ | |
9115 | ? ((v) & ~0x3) == 0 \ | |
9116 | ? ((v) & ~0x1) == 0 \ | |
9117 | ? !(v) \ | |
9118 | ? 32 \ | |
9119 | : 31 \ | |
9120 | : 30 \ | |
9121 | : ((v) & ~0x7) == 0 \ | |
9122 | ? 29 \ | |
9123 | : 28 \ | |
9124 | : ((v) & ~0x3f) == 0 \ | |
9125 | ? ((v) & ~0x1f) == 0 \ | |
9126 | ? 27 \ | |
9127 | : 26 \ | |
9128 | : ((v) & ~0x7f) == 0 \ | |
9129 | ? 25 \ | |
9130 | : 24 \ | |
9131 | : ((v) & ~0xfff) == 0 \ | |
9132 | ? ((v) & ~0x3ff) == 0 \ | |
9133 | ? ((v) & ~0x1ff) == 0 \ | |
9134 | ? 23 \ | |
9135 | : 22 \ | |
9136 | : ((v) & ~0x7ff) == 0 \ | |
9137 | ? 21 \ | |
9138 | : 20 \ | |
9139 | : ((v) & ~0x3fff) == 0 \ | |
9140 | ? ((v) & ~0x1fff) == 0 \ | |
9141 | ? 19 \ | |
9142 | : 18 \ | |
9143 | : ((v) & ~0x7fff) == 0 \ | |
9144 | ? 17 \ | |
9145 | : 16 \ | |
9146 | : ((v) & ~0xffffff) == 0 \ | |
9147 | ? ((v) & ~0xfffff) == 0 \ | |
9148 | ? ((v) & ~0x3ffff) == 0 \ | |
9149 | ? ((v) & ~0x1ffff) == 0 \ | |
9150 | ? 15 \ | |
9151 | : 14 \ | |
9152 | : ((v) & ~0x7ffff) == 0 \ | |
9153 | ? 13 \ | |
9154 | : 12 \ | |
9155 | : ((v) & ~0x3fffff) == 0 \ | |
9156 | ? ((v) & ~0x1fffff) == 0 \ | |
9157 | ? 11 \ | |
9158 | : 10 \ | |
9159 | : ((v) & ~0x7fffff) == 0 \ | |
9160 | ? 9 \ | |
9161 | : 8 \ | |
9162 | : ((v) & ~0xfffffff) == 0 \ | |
9163 | ? ((v) & ~0x3ffffff) == 0 \ | |
9164 | ? ((v) & ~0x1ffffff) == 0 \ | |
9165 | ? 7 \ | |
9166 | : 6 \ | |
9167 | : ((v) & ~0x7ffffff) == 0 \ | |
9168 | ? 5 \ | |
9169 | : 4 \ | |
9170 | : ((v) & ~0x3fffffff) == 0 \ | |
9171 | ? ((v) & ~0x1fffffff) == 0 \ | |
9172 | ? 3 \ | |
9173 | : 2 \ | |
9174 | : ((v) & ~0x7fffffff) == 0 \ | |
9175 | ? 1 \ | |
9176 | : 0) | |
9177 | ||
9178 | /* load_register() | |
67c1ffbe | 9179 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9180 | * an absolute expression value into a register. |
9181 | */ | |
9182 | static void | |
67c0d1eb | 9183 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9184 | { |
9185 | int freg; | |
9186 | expressionS hi32, lo32; | |
9187 | ||
9188 | if (ep->X_op != O_big) | |
9189 | { | |
9c2799c2 | 9190 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9191 | |
9192 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9193 | if (!dbl) |
9194 | normalize_constant_expr (ep); | |
256ab948 TS |
9195 | |
9196 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9197 | { |
9198 | /* We can handle 16 bit signed values with an addiu to | |
9199 | $zero. No need to ever use daddiu here, since $zero and | |
9200 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9201 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9202 | return; |
9203 | } | |
9204 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9205 | { | |
9206 | /* We can handle 16 bit unsigned values with an ori to | |
9207 | $zero. */ | |
67c0d1eb | 9208 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9209 | return; |
9210 | } | |
256ab948 | 9211 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9212 | { |
9213 | /* 32 bit values require an lui. */ | |
df58fc94 | 9214 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9215 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9216 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9217 | return; |
9218 | } | |
9219 | } | |
9220 | ||
9221 | /* The value is larger than 32 bits. */ | |
9222 | ||
bad1aba3 | 9223 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9224 | { |
55e08f71 NC |
9225 | char value[32]; |
9226 | ||
9227 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9228 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9229 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9230 | return; |
9231 | } | |
9232 | ||
9233 | if (ep->X_op != O_big) | |
9234 | { | |
9235 | hi32 = *ep; | |
9236 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9237 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9238 | hi32.X_add_number &= 0xffffffff; | |
9239 | lo32 = *ep; | |
9240 | lo32.X_add_number &= 0xffffffff; | |
9241 | } | |
9242 | else | |
9243 | { | |
9c2799c2 | 9244 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9245 | if (ep->X_add_number == 3) |
9246 | generic_bignum[3] = 0; | |
9247 | else if (ep->X_add_number > 4) | |
1661c76c | 9248 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9249 | lo32.X_op = O_constant; |
9250 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9251 | hi32.X_op = O_constant; | |
9252 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9253 | } | |
9254 | ||
9255 | if (hi32.X_add_number == 0) | |
9256 | freg = 0; | |
9257 | else | |
9258 | { | |
9259 | int shift, bit; | |
9260 | unsigned long hi, lo; | |
9261 | ||
956cd1d6 | 9262 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9263 | { |
9264 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9265 | { | |
67c0d1eb | 9266 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9267 | return; |
9268 | } | |
9269 | if (lo32.X_add_number & 0x80000000) | |
9270 | { | |
df58fc94 | 9271 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9272 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9273 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9274 | return; |
9275 | } | |
9276 | } | |
252b5132 RH |
9277 | |
9278 | /* Check for 16bit shifted constant. We know that hi32 is | |
9279 | non-zero, so start the mask on the first bit of the hi32 | |
9280 | value. */ | |
9281 | shift = 17; | |
9282 | do | |
beae10d5 KH |
9283 | { |
9284 | unsigned long himask, lomask; | |
9285 | ||
9286 | if (shift < 32) | |
9287 | { | |
9288 | himask = 0xffff >> (32 - shift); | |
9289 | lomask = (0xffff << shift) & 0xffffffff; | |
9290 | } | |
9291 | else | |
9292 | { | |
9293 | himask = 0xffff << (shift - 32); | |
9294 | lomask = 0; | |
9295 | } | |
9296 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9297 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9298 | { | |
9299 | expressionS tmp; | |
9300 | ||
9301 | tmp.X_op = O_constant; | |
9302 | if (shift < 32) | |
9303 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9304 | | (lo32.X_add_number >> shift)); | |
9305 | else | |
9306 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9307 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9308 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9309 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9310 | return; |
9311 | } | |
f9419b05 | 9312 | ++shift; |
beae10d5 KH |
9313 | } |
9314 | while (shift <= (64 - 16)); | |
252b5132 RH |
9315 | |
9316 | /* Find the bit number of the lowest one bit, and store the | |
9317 | shifted value in hi/lo. */ | |
9318 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9319 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9320 | if (lo != 0) | |
9321 | { | |
9322 | bit = 0; | |
9323 | while ((lo & 1) == 0) | |
9324 | { | |
9325 | lo >>= 1; | |
9326 | ++bit; | |
9327 | } | |
9328 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9329 | hi >>= bit; | |
9330 | } | |
9331 | else | |
9332 | { | |
9333 | bit = 32; | |
9334 | while ((hi & 1) == 0) | |
9335 | { | |
9336 | hi >>= 1; | |
9337 | ++bit; | |
9338 | } | |
9339 | lo = hi; | |
9340 | hi = 0; | |
9341 | } | |
9342 | ||
9343 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9344 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9345 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9346 | { |
9347 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9348 | if (shift != 0) |
beae10d5 | 9349 | { |
252b5132 RH |
9350 | expressionS tmp; |
9351 | ||
9352 | /* This instruction will set the register to be all | |
9353 | ones. */ | |
beae10d5 KH |
9354 | tmp.X_op = O_constant; |
9355 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9356 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9357 | if (bit != 0) |
9358 | { | |
9359 | bit += shift; | |
df58fc94 | 9360 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9361 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9362 | } |
df58fc94 | 9363 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9364 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9365 | return; |
9366 | } | |
9367 | } | |
252b5132 RH |
9368 | |
9369 | /* Sign extend hi32 before calling load_register, because we can | |
9370 | generally get better code when we load a sign extended value. */ | |
9371 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9372 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9373 | load_register (reg, &hi32, 0); |
252b5132 RH |
9374 | freg = reg; |
9375 | } | |
9376 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9377 | { | |
9378 | if (freg != 0) | |
9379 | { | |
df58fc94 | 9380 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9381 | freg = reg; |
9382 | } | |
9383 | } | |
9384 | else | |
9385 | { | |
9386 | expressionS mid16; | |
9387 | ||
956cd1d6 | 9388 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9389 | { |
df58fc94 RS |
9390 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9391 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9392 | return; |
9393 | } | |
252b5132 RH |
9394 | |
9395 | if (freg != 0) | |
9396 | { | |
df58fc94 | 9397 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9398 | freg = reg; |
9399 | } | |
9400 | mid16 = lo32; | |
9401 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9402 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9403 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9404 | freg = reg; |
9405 | } | |
9406 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9407 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9408 | } |
9409 | ||
269137b2 TS |
9410 | static inline void |
9411 | load_delay_nop (void) | |
9412 | { | |
9413 | if (!gpr_interlocks) | |
9414 | macro_build (NULL, "nop", ""); | |
9415 | } | |
9416 | ||
252b5132 RH |
9417 | /* Load an address into a register. */ |
9418 | ||
9419 | static void | |
67c0d1eb | 9420 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9421 | { |
252b5132 RH |
9422 | if (ep->X_op != O_constant |
9423 | && ep->X_op != O_symbol) | |
9424 | { | |
9425 | as_bad (_("expression too complex")); | |
9426 | ep->X_op = O_constant; | |
9427 | } | |
9428 | ||
9429 | if (ep->X_op == O_constant) | |
9430 | { | |
67c0d1eb | 9431 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9432 | return; |
9433 | } | |
9434 | ||
9435 | if (mips_pic == NO_PIC) | |
9436 | { | |
9437 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9438 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9439 | Otherwise we want |
9440 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9441 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9442 | If we have an addend, we always use the latter form. |
76b3015f | 9443 | |
d6bc6245 TS |
9444 | With 64bit address space and a usable $at we want |
9445 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9446 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9447 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9448 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9449 | dsll32 $reg,0 | |
3a482fd5 | 9450 | daddu $reg,$reg,$at |
76b3015f | 9451 | |
c03099e6 | 9452 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9453 | on superscalar processors. |
9454 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9455 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9456 | dsll $reg,16 | |
9457 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9458 | dsll $reg,16 | |
9459 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9460 | |
9461 | For GP relative symbols in 64bit address space we can use | |
9462 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9463 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9464 | { |
6caf9ef4 TS |
9465 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9466 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9467 | { | |
9468 | relax_start (ep->X_add_symbol); | |
9469 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9470 | mips_gp_register, BFD_RELOC_GPREL16); | |
9471 | relax_switch (); | |
9472 | } | |
d6bc6245 | 9473 | |
741fe287 | 9474 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9475 | { |
df58fc94 RS |
9476 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9477 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9478 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9479 | BFD_RELOC_MIPS_HIGHER); | |
9480 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9481 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9482 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9483 | *used_at = 1; |
9484 | } | |
9485 | else | |
9486 | { | |
df58fc94 | 9487 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9488 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9489 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9490 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9491 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9492 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9493 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9494 | } |
6caf9ef4 TS |
9495 | |
9496 | if (mips_relax.sequence) | |
9497 | relax_end (); | |
d6bc6245 | 9498 | } |
252b5132 RH |
9499 | else |
9500 | { | |
d6bc6245 | 9501 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9502 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9503 | { |
4d7206a2 | 9504 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9505 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9506 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9507 | relax_switch (); |
d6bc6245 | 9508 | } |
67c0d1eb RS |
9509 | macro_build_lui (ep, reg); |
9510 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9511 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9512 | if (mips_relax.sequence) |
9513 | relax_end (); | |
d6bc6245 | 9514 | } |
252b5132 | 9515 | } |
0a44bf69 | 9516 | else if (!mips_big_got) |
252b5132 RH |
9517 | { |
9518 | expressionS ex; | |
9519 | ||
9520 | /* If this is a reference to an external symbol, we want | |
9521 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9522 | Otherwise we want | |
9523 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9524 | nop | |
9525 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9526 | If there is a constant, it must be added in after. |
9527 | ||
ed6fb7bd | 9528 | If we have NewABI, we want |
f5040a92 AO |
9529 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9530 | unless we're referencing a global symbol with a non-zero | |
9531 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9532 | if (HAVE_NEWABI) |
9533 | { | |
f5040a92 AO |
9534 | if (ep->X_add_number) |
9535 | { | |
4d7206a2 | 9536 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9537 | ep->X_add_number = 0; |
4d7206a2 | 9538 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9539 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9540 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9541 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9542 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9543 | ex.X_op = O_constant; | |
67c0d1eb | 9544 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9545 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9546 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9547 | relax_switch (); |
f5040a92 | 9548 | } |
67c0d1eb | 9549 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9550 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9551 | if (mips_relax.sequence) |
9552 | relax_end (); | |
ed6fb7bd SC |
9553 | } |
9554 | else | |
9555 | { | |
f5040a92 AO |
9556 | ex.X_add_number = ep->X_add_number; |
9557 | ep->X_add_number = 0; | |
67c0d1eb RS |
9558 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9559 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9560 | load_delay_nop (); |
4d7206a2 RS |
9561 | relax_start (ep->X_add_symbol); |
9562 | relax_switch (); | |
67c0d1eb | 9563 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9564 | BFD_RELOC_LO16); |
4d7206a2 | 9565 | relax_end (); |
ed6fb7bd | 9566 | |
f5040a92 AO |
9567 | if (ex.X_add_number != 0) |
9568 | { | |
9569 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9570 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9571 | ex.X_op = O_constant; | |
67c0d1eb | 9572 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9573 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9574 | } |
252b5132 RH |
9575 | } |
9576 | } | |
0a44bf69 | 9577 | else if (mips_big_got) |
252b5132 RH |
9578 | { |
9579 | expressionS ex; | |
252b5132 RH |
9580 | |
9581 | /* This is the large GOT case. If this is a reference to an | |
9582 | external symbol, we want | |
9583 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9584 | addu $reg,$reg,$gp | |
9585 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9586 | |
9587 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9588 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9589 | nop | |
9590 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9591 | If there is a constant, it must be added in after. |
f5040a92 AO |
9592 | |
9593 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9594 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9595 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9596 | */ |
438c16b8 TS |
9597 | if (HAVE_NEWABI) |
9598 | { | |
4d7206a2 | 9599 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9600 | ep->X_add_number = 0; |
4d7206a2 | 9601 | relax_start (ep->X_add_symbol); |
df58fc94 | 9602 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9603 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9604 | reg, reg, mips_gp_register); | |
9605 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9606 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9607 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9608 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9609 | else if (ex.X_add_number) | |
9610 | { | |
9611 | ex.X_op = O_constant; | |
67c0d1eb RS |
9612 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9613 | BFD_RELOC_LO16); | |
f5040a92 AO |
9614 | } |
9615 | ||
9616 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9617 | relax_switch (); |
67c0d1eb | 9618 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9619 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9620 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9621 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9622 | relax_end (); |
438c16b8 | 9623 | } |
252b5132 | 9624 | else |
438c16b8 | 9625 | { |
f5040a92 AO |
9626 | ex.X_add_number = ep->X_add_number; |
9627 | ep->X_add_number = 0; | |
4d7206a2 | 9628 | relax_start (ep->X_add_symbol); |
df58fc94 | 9629 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9630 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9631 | reg, reg, mips_gp_register); | |
9632 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9633 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9634 | relax_switch (); |
9635 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9636 | { |
9637 | /* We need a nop before loading from $gp. This special | |
9638 | check is required because the lui which starts the main | |
9639 | instruction stream does not refer to $gp, and so will not | |
9640 | insert the nop which may be required. */ | |
67c0d1eb | 9641 | macro_build (NULL, "nop", ""); |
438c16b8 | 9642 | } |
67c0d1eb | 9643 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9644 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9645 | load_delay_nop (); |
67c0d1eb | 9646 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9647 | BFD_RELOC_LO16); |
4d7206a2 | 9648 | relax_end (); |
438c16b8 | 9649 | |
f5040a92 AO |
9650 | if (ex.X_add_number != 0) |
9651 | { | |
9652 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9653 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9654 | ex.X_op = O_constant; | |
67c0d1eb RS |
9655 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9656 | BFD_RELOC_LO16); | |
f5040a92 | 9657 | } |
252b5132 RH |
9658 | } |
9659 | } | |
252b5132 RH |
9660 | else |
9661 | abort (); | |
8fc2e39e | 9662 | |
741fe287 | 9663 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9664 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9665 | } |
9666 | ||
ea1fb5dc RS |
9667 | /* Move the contents of register SOURCE into register DEST. */ |
9668 | ||
9669 | static void | |
67c0d1eb | 9670 | move_register (int dest, int source) |
ea1fb5dc | 9671 | { |
df58fc94 RS |
9672 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9673 | instruction specifically requires a 32-bit one. */ | |
9674 | if (mips_opts.micromips | |
833794fc | 9675 | && !mips_opts.insn32 |
df58fc94 | 9676 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9677 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9678 | else |
40fc1451 | 9679 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9680 | } |
9681 | ||
4d7206a2 | 9682 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9683 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9684 | The two alternatives are: | |
4d7206a2 | 9685 | |
33eaf5de | 9686 | Global symbol Local symbol |
4d7206a2 RS |
9687 | ------------- ------------ |
9688 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9689 | ... ... | |
9690 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9691 | ||
9692 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9693 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9694 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9695 | |
9696 | static void | |
67c0d1eb | 9697 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9698 | { |
9699 | expressionS global; | |
9700 | ||
9701 | global = *local; | |
9702 | global.X_add_number = 0; | |
9703 | ||
9704 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9705 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9706 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9707 | relax_switch (); |
67c0d1eb RS |
9708 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9709 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9710 | relax_end (); |
9711 | } | |
9712 | ||
9713 | static void | |
67c0d1eb | 9714 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9715 | { |
9716 | expressionS global; | |
9717 | ||
9718 | global.X_op = O_constant; | |
9719 | global.X_op_symbol = NULL; | |
9720 | global.X_add_symbol = NULL; | |
9721 | global.X_add_number = local->X_add_number; | |
9722 | ||
9723 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9724 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9725 | dest, dest, BFD_RELOC_LO16); |
9726 | relax_switch (); | |
67c0d1eb | 9727 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9728 | relax_end (); |
9729 | } | |
9730 | ||
f6a22291 MR |
9731 | static void |
9732 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9733 | { | |
9734 | expressionS global; | |
9735 | int hold_mips_optimize; | |
9736 | ||
9737 | global.X_op = O_constant; | |
9738 | global.X_op_symbol = NULL; | |
9739 | global.X_add_symbol = NULL; | |
9740 | global.X_add_number = local->X_add_number; | |
9741 | ||
9742 | relax_start (local->X_add_symbol); | |
9743 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9744 | relax_switch (); | |
9745 | /* Set mips_optimize around the lui instruction to avoid | |
9746 | inserting an unnecessary nop after the lw. */ | |
9747 | hold_mips_optimize = mips_optimize; | |
9748 | mips_optimize = 2; | |
9749 | macro_build_lui (&global, tmp); | |
9750 | mips_optimize = hold_mips_optimize; | |
9751 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9752 | relax_end (); | |
9753 | ||
9754 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9755 | } | |
9756 | ||
df58fc94 RS |
9757 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9758 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9759 | is its complementing branch with the original condition negated. | |
9760 | CALL is set if the original branch specified the link operation. | |
9761 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9762 | ||
9763 | Code like this is produced in the noreorder mode: | |
9764 | ||
9765 | BRNEG <args>, 1f | |
9766 | nop | |
9767 | b <sym> | |
9768 | delay slot (executed only if branch taken) | |
9769 | 1: | |
9770 | ||
9771 | or, if CALL is set: | |
9772 | ||
9773 | BRNEG <args>, 1f | |
9774 | nop | |
9775 | bal <sym> | |
9776 | delay slot (executed only if branch taken) | |
9777 | 1: | |
9778 | ||
9779 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9780 | so code produced is simply: | |
9781 | ||
9782 | BR <args>, <sym> | |
9783 | nop | |
9784 | ||
9785 | This function is used when producing code for the microMIPS ASE that | |
9786 | does not implement branch likely instructions in hardware. */ | |
9787 | ||
9788 | static void | |
9789 | macro_build_branch_likely (const char *br, const char *brneg, | |
9790 | int call, expressionS *ep, const char *fmt, | |
9791 | unsigned int sreg, unsigned int treg) | |
9792 | { | |
9793 | int noreorder = mips_opts.noreorder; | |
9794 | expressionS expr1; | |
9795 | ||
9796 | gas_assert (mips_opts.micromips); | |
9797 | start_noreorder (); | |
9798 | if (noreorder) | |
9799 | { | |
9800 | micromips_label_expr (&expr1); | |
9801 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9802 | macro_build (NULL, "nop", ""); | |
9803 | macro_build (ep, call ? "bal" : "b", "p"); | |
9804 | ||
9805 | /* Set to true so that append_insn adds a label. */ | |
9806 | emit_branch_likely_macro = TRUE; | |
9807 | } | |
9808 | else | |
9809 | { | |
9810 | macro_build (ep, br, fmt, sreg, treg); | |
9811 | macro_build (NULL, "nop", ""); | |
9812 | } | |
9813 | end_noreorder (); | |
9814 | } | |
9815 | ||
9816 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9817 | the condition code tested. EP specifies the branch target. */ | |
9818 | ||
9819 | static void | |
9820 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9821 | { | |
9822 | const int call = 0; | |
9823 | const char *brneg; | |
9824 | const char *br; | |
9825 | ||
9826 | switch (type) | |
9827 | { | |
9828 | case M_BC1FL: | |
9829 | br = "bc1f"; | |
9830 | brneg = "bc1t"; | |
9831 | break; | |
9832 | case M_BC1TL: | |
9833 | br = "bc1t"; | |
9834 | brneg = "bc1f"; | |
9835 | break; | |
9836 | case M_BC2FL: | |
9837 | br = "bc2f"; | |
9838 | brneg = "bc2t"; | |
9839 | break; | |
9840 | case M_BC2TL: | |
9841 | br = "bc2t"; | |
9842 | brneg = "bc2f"; | |
9843 | break; | |
9844 | default: | |
9845 | abort (); | |
9846 | } | |
9847 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9848 | } | |
9849 | ||
9850 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9851 | the register tested. EP specifies the branch target. */ | |
9852 | ||
9853 | static void | |
9854 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9855 | { | |
9856 | const char *brneg = NULL; | |
9857 | const char *br; | |
9858 | int call = 0; | |
9859 | ||
9860 | switch (type) | |
9861 | { | |
9862 | case M_BGEZ: | |
9863 | br = "bgez"; | |
9864 | break; | |
9865 | case M_BGEZL: | |
9866 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9867 | brneg = "bltz"; | |
9868 | break; | |
9869 | case M_BGEZALL: | |
9870 | gas_assert (mips_opts.micromips); | |
833794fc | 9871 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9872 | brneg = "bltz"; |
9873 | call = 1; | |
9874 | break; | |
9875 | case M_BGTZ: | |
9876 | br = "bgtz"; | |
9877 | break; | |
9878 | case M_BGTZL: | |
9879 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9880 | brneg = "blez"; | |
9881 | break; | |
9882 | case M_BLEZ: | |
9883 | br = "blez"; | |
9884 | break; | |
9885 | case M_BLEZL: | |
9886 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9887 | brneg = "bgtz"; | |
9888 | break; | |
9889 | case M_BLTZ: | |
9890 | br = "bltz"; | |
9891 | break; | |
9892 | case M_BLTZL: | |
9893 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9894 | brneg = "bgez"; | |
9895 | break; | |
9896 | case M_BLTZALL: | |
9897 | gas_assert (mips_opts.micromips); | |
833794fc | 9898 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9899 | brneg = "bgez"; |
9900 | call = 1; | |
9901 | break; | |
9902 | default: | |
9903 | abort (); | |
9904 | } | |
9905 | if (mips_opts.micromips && brneg) | |
9906 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9907 | else | |
9908 | macro_build (ep, br, "s,p", sreg); | |
9909 | } | |
9910 | ||
9911 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9912 | TREG as the registers tested. EP specifies the branch target. */ | |
9913 | ||
9914 | static void | |
9915 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9916 | unsigned int sreg, unsigned int treg) | |
9917 | { | |
9918 | const char *brneg = NULL; | |
9919 | const int call = 0; | |
9920 | const char *br; | |
9921 | ||
9922 | switch (type) | |
9923 | { | |
9924 | case M_BEQ: | |
9925 | case M_BEQ_I: | |
9926 | br = "beq"; | |
9927 | break; | |
9928 | case M_BEQL: | |
9929 | case M_BEQL_I: | |
9930 | br = mips_opts.micromips ? "beq" : "beql"; | |
9931 | brneg = "bne"; | |
9932 | break; | |
9933 | case M_BNE: | |
9934 | case M_BNE_I: | |
9935 | br = "bne"; | |
9936 | break; | |
9937 | case M_BNEL: | |
9938 | case M_BNEL_I: | |
9939 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9940 | brneg = "beq"; | |
9941 | break; | |
9942 | default: | |
9943 | abort (); | |
9944 | } | |
9945 | if (mips_opts.micromips && brneg) | |
9946 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9947 | else | |
9948 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9949 | } | |
9950 | ||
f2ae14a1 RS |
9951 | /* Return the high part that should be loaded in order to make the low |
9952 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9953 | ||
9954 | static offsetT | |
9955 | offset_high_part (offsetT value, unsigned int offbits) | |
9956 | { | |
9957 | offsetT bias; | |
9958 | addressT low_mask; | |
9959 | ||
9960 | if (offbits == 0) | |
9961 | return value; | |
9962 | bias = 1 << (offbits - 1); | |
9963 | low_mask = bias * 2 - 1; | |
9964 | return (value + bias) & ~low_mask; | |
9965 | } | |
9966 | ||
9967 | /* Return true if the value stored in offset_expr and offset_reloc | |
9968 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9969 | amount that the caller wants to add without inducing overflow | |
9970 | and ALIGN is the known alignment of the value in bytes. */ | |
9971 | ||
9972 | static bfd_boolean | |
9973 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9974 | { | |
9975 | if (offbits == 16) | |
9976 | { | |
9977 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9978 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
9979 | return TRUE; | |
9980 | ||
9981 | /* These relocations are guaranteed not to overflow in correct links. */ | |
9982 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
9983 | || gprel16_reloc_p (*offset_reloc)) | |
9984 | return TRUE; | |
9985 | } | |
9986 | if (offset_expr.X_op == O_constant | |
9987 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
9988 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
9989 | return TRUE; | |
9990 | return FALSE; | |
9991 | } | |
9992 | ||
252b5132 RH |
9993 | /* |
9994 | * Build macros | |
9995 | * This routine implements the seemingly endless macro or synthesized | |
9996 | * instructions and addressing modes in the mips assembly language. Many | |
9997 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 9998 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
9999 | * this verbose method. Others are not simple macros but are more like |
10000 | * optimizing code generation. | |
10001 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10002 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10003 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10004 | * of global optimization. We currently only optimize within a single macro. |
10005 | * For many of the load and store macros if the address is specified as a | |
10006 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10007 | * first load register 'at' with zero and use it as the base register. The | |
10008 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10009 | * we're missing. | |
10010 | */ | |
10011 | static void | |
833794fc | 10012 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10013 | { |
c0ebe874 RS |
10014 | const struct mips_operand_array *operands; |
10015 | unsigned int breg, i; | |
741fe287 | 10016 | unsigned int tempreg; |
252b5132 | 10017 | int mask; |
43841e91 | 10018 | int used_at = 0; |
df58fc94 | 10019 | expressionS label_expr; |
252b5132 | 10020 | expressionS expr1; |
df58fc94 | 10021 | expressionS *ep; |
252b5132 RH |
10022 | const char *s; |
10023 | const char *s2; | |
10024 | const char *fmt; | |
10025 | int likely = 0; | |
252b5132 | 10026 | int coproc = 0; |
7f3c4072 | 10027 | int offbits = 16; |
1abe91b1 | 10028 | int call = 0; |
df58fc94 RS |
10029 | int jals = 0; |
10030 | int dbl = 0; | |
10031 | int imm = 0; | |
10032 | int ust = 0; | |
10033 | int lp = 0; | |
f2ae14a1 | 10034 | bfd_boolean large_offset; |
252b5132 | 10035 | int off; |
252b5132 | 10036 | int hold_mips_optimize; |
f2ae14a1 | 10037 | unsigned int align; |
c0ebe874 | 10038 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10039 | |
9c2799c2 | 10040 | gas_assert (! mips_opts.mips16); |
252b5132 | 10041 | |
c0ebe874 RS |
10042 | operands = insn_operands (ip); |
10043 | for (i = 0; i < MAX_OPERANDS; i++) | |
10044 | if (operands->operand[i]) | |
10045 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10046 | else | |
10047 | op[i] = -1; | |
10048 | ||
252b5132 RH |
10049 | mask = ip->insn_mo->mask; |
10050 | ||
df58fc94 RS |
10051 | label_expr.X_op = O_constant; |
10052 | label_expr.X_op_symbol = NULL; | |
10053 | label_expr.X_add_symbol = NULL; | |
10054 | label_expr.X_add_number = 0; | |
10055 | ||
252b5132 RH |
10056 | expr1.X_op = O_constant; |
10057 | expr1.X_op_symbol = NULL; | |
10058 | expr1.X_add_symbol = NULL; | |
10059 | expr1.X_add_number = 1; | |
f2ae14a1 | 10060 | align = 1; |
252b5132 RH |
10061 | |
10062 | switch (mask) | |
10063 | { | |
10064 | case M_DABS: | |
10065 | dbl = 1; | |
1a0670f3 | 10066 | /* Fall through. */ |
252b5132 | 10067 | case M_ABS: |
df58fc94 RS |
10068 | /* bgez $a0,1f |
10069 | move v0,$a0 | |
10070 | sub v0,$zero,$a0 | |
10071 | 1: | |
10072 | */ | |
252b5132 | 10073 | |
7d10b47d | 10074 | start_noreorder (); |
252b5132 | 10075 | |
df58fc94 RS |
10076 | if (mips_opts.micromips) |
10077 | micromips_label_expr (&label_expr); | |
10078 | else | |
10079 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10080 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10081 | if (op[0] == op[1]) | |
a605d2b3 | 10082 | macro_build (NULL, "nop", ""); |
252b5132 | 10083 | else |
c0ebe874 RS |
10084 | move_register (op[0], op[1]); |
10085 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10086 | if (mips_opts.micromips) |
10087 | micromips_add_label (); | |
252b5132 | 10088 | |
7d10b47d | 10089 | end_noreorder (); |
8fc2e39e | 10090 | break; |
252b5132 RH |
10091 | |
10092 | case M_ADD_I: | |
10093 | s = "addi"; | |
10094 | s2 = "add"; | |
10095 | goto do_addi; | |
10096 | case M_ADDU_I: | |
10097 | s = "addiu"; | |
10098 | s2 = "addu"; | |
10099 | goto do_addi; | |
10100 | case M_DADD_I: | |
10101 | dbl = 1; | |
10102 | s = "daddi"; | |
10103 | s2 = "dadd"; | |
df58fc94 RS |
10104 | if (!mips_opts.micromips) |
10105 | goto do_addi; | |
b0e6f033 | 10106 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
10107 | && imm_expr.X_add_number < 0x200) |
10108 | { | |
b0e6f033 RS |
10109 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10110 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10111 | break; |
10112 | } | |
10113 | goto do_addi_i; | |
252b5132 RH |
10114 | case M_DADDU_I: |
10115 | dbl = 1; | |
10116 | s = "daddiu"; | |
10117 | s2 = "daddu"; | |
10118 | do_addi: | |
b0e6f033 | 10119 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10120 | && imm_expr.X_add_number < 0x8000) |
10121 | { | |
c0ebe874 | 10122 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10123 | break; |
252b5132 | 10124 | } |
df58fc94 | 10125 | do_addi_i: |
8fc2e39e | 10126 | used_at = 1; |
67c0d1eb | 10127 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10128 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10129 | break; |
10130 | ||
10131 | case M_AND_I: | |
10132 | s = "andi"; | |
10133 | s2 = "and"; | |
10134 | goto do_bit; | |
10135 | case M_OR_I: | |
10136 | s = "ori"; | |
10137 | s2 = "or"; | |
10138 | goto do_bit; | |
10139 | case M_NOR_I: | |
10140 | s = ""; | |
10141 | s2 = "nor"; | |
10142 | goto do_bit; | |
10143 | case M_XOR_I: | |
10144 | s = "xori"; | |
10145 | s2 = "xor"; | |
10146 | do_bit: | |
b0e6f033 | 10147 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10148 | && imm_expr.X_add_number < 0x10000) |
10149 | { | |
10150 | if (mask != M_NOR_I) | |
c0ebe874 | 10151 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10152 | else |
10153 | { | |
67c0d1eb | 10154 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10155 | op[0], op[1], BFD_RELOC_LO16); |
10156 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10157 | } |
8fc2e39e | 10158 | break; |
252b5132 RH |
10159 | } |
10160 | ||
8fc2e39e | 10161 | used_at = 1; |
bad1aba3 | 10162 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10163 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10164 | break; |
10165 | ||
8b082fb1 TS |
10166 | case M_BALIGN: |
10167 | switch (imm_expr.X_add_number) | |
10168 | { | |
10169 | case 0: | |
10170 | macro_build (NULL, "nop", ""); | |
10171 | break; | |
10172 | case 2: | |
c0ebe874 | 10173 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10174 | break; |
03f66e8a MR |
10175 | case 1: |
10176 | case 3: | |
c0ebe874 | 10177 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10178 | (int) imm_expr.X_add_number); |
8b082fb1 | 10179 | break; |
03f66e8a MR |
10180 | default: |
10181 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10182 | (unsigned long) imm_expr.X_add_number); | |
10183 | break; | |
8b082fb1 TS |
10184 | } |
10185 | break; | |
10186 | ||
df58fc94 RS |
10187 | case M_BC1FL: |
10188 | case M_BC1TL: | |
10189 | case M_BC2FL: | |
10190 | case M_BC2TL: | |
10191 | gas_assert (mips_opts.micromips); | |
10192 | macro_build_branch_ccl (mask, &offset_expr, | |
10193 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10194 | break; | |
10195 | ||
252b5132 | 10196 | case M_BEQ_I: |
252b5132 | 10197 | case M_BEQL_I: |
252b5132 | 10198 | case M_BNE_I: |
252b5132 | 10199 | case M_BNEL_I: |
b0e6f033 | 10200 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10201 | op[1] = 0; |
df58fc94 | 10202 | else |
252b5132 | 10203 | { |
c0ebe874 | 10204 | op[1] = AT; |
df58fc94 | 10205 | used_at = 1; |
bad1aba3 | 10206 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10207 | } |
df58fc94 RS |
10208 | /* Fall through. */ |
10209 | case M_BEQL: | |
10210 | case M_BNEL: | |
c0ebe874 | 10211 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10212 | break; |
10213 | ||
10214 | case M_BGEL: | |
10215 | likely = 1; | |
1a0670f3 | 10216 | /* Fall through. */ |
252b5132 | 10217 | case M_BGE: |
c0ebe874 RS |
10218 | if (op[1] == 0) |
10219 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10220 | else if (op[0] == 0) | |
10221 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10222 | else |
252b5132 | 10223 | { |
df58fc94 | 10224 | used_at = 1; |
c0ebe874 | 10225 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10226 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10227 | &offset_expr, AT, ZERO); | |
252b5132 | 10228 | } |
df58fc94 RS |
10229 | break; |
10230 | ||
10231 | case M_BGEZL: | |
10232 | case M_BGEZALL: | |
10233 | case M_BGTZL: | |
10234 | case M_BLEZL: | |
10235 | case M_BLTZL: | |
10236 | case M_BLTZALL: | |
c0ebe874 | 10237 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10238 | break; |
10239 | ||
10240 | case M_BGTL_I: | |
10241 | likely = 1; | |
1a0670f3 | 10242 | /* Fall through. */ |
252b5132 | 10243 | case M_BGT_I: |
90ecf173 | 10244 | /* Check for > max integer. */ |
b0e6f033 | 10245 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10246 | { |
10247 | do_false: | |
90ecf173 | 10248 | /* Result is always false. */ |
252b5132 | 10249 | if (! likely) |
a605d2b3 | 10250 | macro_build (NULL, "nop", ""); |
252b5132 | 10251 | else |
df58fc94 | 10252 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10253 | break; |
252b5132 | 10254 | } |
f9419b05 | 10255 | ++imm_expr.X_add_number; |
252b5132 RH |
10256 | /* FALLTHROUGH */ |
10257 | case M_BGE_I: | |
10258 | case M_BGEL_I: | |
10259 | if (mask == M_BGEL_I) | |
10260 | likely = 1; | |
b0e6f033 | 10261 | if (imm_expr.X_add_number == 0) |
252b5132 | 10262 | { |
df58fc94 | 10263 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10264 | &offset_expr, op[0]); |
8fc2e39e | 10265 | break; |
252b5132 | 10266 | } |
b0e6f033 | 10267 | if (imm_expr.X_add_number == 1) |
252b5132 | 10268 | { |
df58fc94 | 10269 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10270 | &offset_expr, op[0]); |
8fc2e39e | 10271 | break; |
252b5132 | 10272 | } |
b0e6f033 | 10273 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10274 | { |
10275 | do_true: | |
10276 | /* result is always true */ | |
1661c76c | 10277 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10278 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10279 | break; |
252b5132 | 10280 | } |
8fc2e39e | 10281 | used_at = 1; |
c0ebe874 | 10282 | set_at (op[0], 0); |
df58fc94 RS |
10283 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10284 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10285 | break; |
10286 | ||
10287 | case M_BGEUL: | |
10288 | likely = 1; | |
1a0670f3 | 10289 | /* Fall through. */ |
252b5132 | 10290 | case M_BGEU: |
c0ebe874 | 10291 | if (op[1] == 0) |
252b5132 | 10292 | goto do_true; |
c0ebe874 | 10293 | else if (op[0] == 0) |
df58fc94 | 10294 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10295 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10296 | else |
252b5132 | 10297 | { |
df58fc94 | 10298 | used_at = 1; |
c0ebe874 | 10299 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10300 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10301 | &offset_expr, AT, ZERO); | |
252b5132 | 10302 | } |
252b5132 RH |
10303 | break; |
10304 | ||
10305 | case M_BGTUL_I: | |
10306 | likely = 1; | |
1a0670f3 | 10307 | /* Fall through. */ |
252b5132 | 10308 | case M_BGTU_I: |
c0ebe874 | 10309 | if (op[0] == 0 |
bad1aba3 | 10310 | || (GPR_SIZE == 32 |
f01dc953 | 10311 | && imm_expr.X_add_number == -1)) |
252b5132 | 10312 | goto do_false; |
f9419b05 | 10313 | ++imm_expr.X_add_number; |
252b5132 RH |
10314 | /* FALLTHROUGH */ |
10315 | case M_BGEU_I: | |
10316 | case M_BGEUL_I: | |
10317 | if (mask == M_BGEUL_I) | |
10318 | likely = 1; | |
b0e6f033 | 10319 | if (imm_expr.X_add_number == 0) |
252b5132 | 10320 | goto do_true; |
b0e6f033 | 10321 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10322 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10323 | &offset_expr, op[0], ZERO); |
df58fc94 | 10324 | else |
252b5132 | 10325 | { |
df58fc94 | 10326 | used_at = 1; |
c0ebe874 | 10327 | set_at (op[0], 1); |
df58fc94 RS |
10328 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10329 | &offset_expr, AT, ZERO); | |
252b5132 | 10330 | } |
252b5132 RH |
10331 | break; |
10332 | ||
10333 | case M_BGTL: | |
10334 | likely = 1; | |
1a0670f3 | 10335 | /* Fall through. */ |
252b5132 | 10336 | case M_BGT: |
c0ebe874 RS |
10337 | if (op[1] == 0) |
10338 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10339 | else if (op[0] == 0) | |
10340 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10341 | else |
252b5132 | 10342 | { |
df58fc94 | 10343 | used_at = 1; |
c0ebe874 | 10344 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10345 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10346 | &offset_expr, AT, ZERO); | |
252b5132 | 10347 | } |
252b5132 RH |
10348 | break; |
10349 | ||
10350 | case M_BGTUL: | |
10351 | likely = 1; | |
1a0670f3 | 10352 | /* Fall through. */ |
252b5132 | 10353 | case M_BGTU: |
c0ebe874 | 10354 | if (op[1] == 0) |
df58fc94 | 10355 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10356 | &offset_expr, op[0], ZERO); |
10357 | else if (op[0] == 0) | |
df58fc94 RS |
10358 | goto do_false; |
10359 | else | |
252b5132 | 10360 | { |
df58fc94 | 10361 | used_at = 1; |
c0ebe874 | 10362 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10363 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10364 | &offset_expr, AT, ZERO); | |
252b5132 | 10365 | } |
252b5132 RH |
10366 | break; |
10367 | ||
10368 | case M_BLEL: | |
10369 | likely = 1; | |
1a0670f3 | 10370 | /* Fall through. */ |
252b5132 | 10371 | case M_BLE: |
c0ebe874 RS |
10372 | if (op[1] == 0) |
10373 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10374 | else if (op[0] == 0) | |
10375 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10376 | else |
252b5132 | 10377 | { |
df58fc94 | 10378 | used_at = 1; |
c0ebe874 | 10379 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10380 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10381 | &offset_expr, AT, ZERO); | |
252b5132 | 10382 | } |
252b5132 RH |
10383 | break; |
10384 | ||
10385 | case M_BLEL_I: | |
10386 | likely = 1; | |
1a0670f3 | 10387 | /* Fall through. */ |
252b5132 | 10388 | case M_BLE_I: |
b0e6f033 | 10389 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10390 | goto do_true; |
f9419b05 | 10391 | ++imm_expr.X_add_number; |
252b5132 RH |
10392 | /* FALLTHROUGH */ |
10393 | case M_BLT_I: | |
10394 | case M_BLTL_I: | |
10395 | if (mask == M_BLTL_I) | |
10396 | likely = 1; | |
b0e6f033 | 10397 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10398 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10399 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10400 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10401 | else |
252b5132 | 10402 | { |
df58fc94 | 10403 | used_at = 1; |
c0ebe874 | 10404 | set_at (op[0], 0); |
df58fc94 RS |
10405 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10406 | &offset_expr, AT, ZERO); | |
252b5132 | 10407 | } |
252b5132 RH |
10408 | break; |
10409 | ||
10410 | case M_BLEUL: | |
10411 | likely = 1; | |
1a0670f3 | 10412 | /* Fall through. */ |
252b5132 | 10413 | case M_BLEU: |
c0ebe874 | 10414 | if (op[1] == 0) |
df58fc94 | 10415 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10416 | &offset_expr, op[0], ZERO); |
10417 | else if (op[0] == 0) | |
df58fc94 RS |
10418 | goto do_true; |
10419 | else | |
252b5132 | 10420 | { |
df58fc94 | 10421 | used_at = 1; |
c0ebe874 | 10422 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10423 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10424 | &offset_expr, AT, ZERO); | |
252b5132 | 10425 | } |
252b5132 RH |
10426 | break; |
10427 | ||
10428 | case M_BLEUL_I: | |
10429 | likely = 1; | |
1a0670f3 | 10430 | /* Fall through. */ |
252b5132 | 10431 | case M_BLEU_I: |
c0ebe874 | 10432 | if (op[0] == 0 |
bad1aba3 | 10433 | || (GPR_SIZE == 32 |
f01dc953 | 10434 | && imm_expr.X_add_number == -1)) |
252b5132 | 10435 | goto do_true; |
f9419b05 | 10436 | ++imm_expr.X_add_number; |
252b5132 RH |
10437 | /* FALLTHROUGH */ |
10438 | case M_BLTU_I: | |
10439 | case M_BLTUL_I: | |
10440 | if (mask == M_BLTUL_I) | |
10441 | likely = 1; | |
b0e6f033 | 10442 | if (imm_expr.X_add_number == 0) |
252b5132 | 10443 | goto do_false; |
b0e6f033 | 10444 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10445 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10446 | &offset_expr, op[0], ZERO); |
df58fc94 | 10447 | else |
252b5132 | 10448 | { |
df58fc94 | 10449 | used_at = 1; |
c0ebe874 | 10450 | set_at (op[0], 1); |
df58fc94 RS |
10451 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10452 | &offset_expr, AT, ZERO); | |
252b5132 | 10453 | } |
252b5132 RH |
10454 | break; |
10455 | ||
10456 | case M_BLTL: | |
10457 | likely = 1; | |
1a0670f3 | 10458 | /* Fall through. */ |
252b5132 | 10459 | case M_BLT: |
c0ebe874 RS |
10460 | if (op[1] == 0) |
10461 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10462 | else if (op[0] == 0) | |
10463 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10464 | else |
252b5132 | 10465 | { |
df58fc94 | 10466 | used_at = 1; |
c0ebe874 | 10467 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10468 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10469 | &offset_expr, AT, ZERO); | |
252b5132 | 10470 | } |
252b5132 RH |
10471 | break; |
10472 | ||
10473 | case M_BLTUL: | |
10474 | likely = 1; | |
1a0670f3 | 10475 | /* Fall through. */ |
252b5132 | 10476 | case M_BLTU: |
c0ebe874 | 10477 | if (op[1] == 0) |
252b5132 | 10478 | goto do_false; |
c0ebe874 | 10479 | else if (op[0] == 0) |
df58fc94 | 10480 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10481 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10482 | else |
252b5132 | 10483 | { |
df58fc94 | 10484 | used_at = 1; |
c0ebe874 | 10485 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10486 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10487 | &offset_expr, AT, ZERO); | |
252b5132 | 10488 | } |
252b5132 RH |
10489 | break; |
10490 | ||
10491 | case M_DDIV_3: | |
10492 | dbl = 1; | |
1a0670f3 | 10493 | /* Fall through. */ |
252b5132 RH |
10494 | case M_DIV_3: |
10495 | s = "mflo"; | |
10496 | goto do_div3; | |
10497 | case M_DREM_3: | |
10498 | dbl = 1; | |
1a0670f3 | 10499 | /* Fall through. */ |
252b5132 RH |
10500 | case M_REM_3: |
10501 | s = "mfhi"; | |
10502 | do_div3: | |
c0ebe874 | 10503 | if (op[2] == 0) |
252b5132 | 10504 | { |
1661c76c | 10505 | as_warn (_("divide by zero")); |
252b5132 | 10506 | if (mips_trap) |
df58fc94 | 10507 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10508 | else |
df58fc94 | 10509 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10510 | break; |
252b5132 RH |
10511 | } |
10512 | ||
7d10b47d | 10513 | start_noreorder (); |
252b5132 RH |
10514 | if (mips_trap) |
10515 | { | |
c0ebe874 RS |
10516 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10517 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10518 | } |
10519 | else | |
10520 | { | |
df58fc94 RS |
10521 | if (mips_opts.micromips) |
10522 | micromips_label_expr (&label_expr); | |
10523 | else | |
10524 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10525 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10526 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10527 | macro_build (NULL, "break", BRK_FMT, 7); |
10528 | if (mips_opts.micromips) | |
10529 | micromips_add_label (); | |
252b5132 RH |
10530 | } |
10531 | expr1.X_add_number = -1; | |
8fc2e39e | 10532 | used_at = 1; |
f6a22291 | 10533 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10534 | if (mips_opts.micromips) |
10535 | micromips_label_expr (&label_expr); | |
10536 | else | |
10537 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10538 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10539 | if (dbl) |
10540 | { | |
10541 | expr1.X_add_number = 1; | |
f6a22291 | 10542 | load_register (AT, &expr1, dbl); |
df58fc94 | 10543 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10544 | } |
10545 | else | |
10546 | { | |
10547 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10548 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10549 | } |
10550 | if (mips_trap) | |
10551 | { | |
c0ebe874 | 10552 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10553 | /* We want to close the noreorder block as soon as possible, so |
10554 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10555 | end_noreorder (); |
252b5132 RH |
10556 | } |
10557 | else | |
10558 | { | |
df58fc94 RS |
10559 | if (mips_opts.micromips) |
10560 | micromips_label_expr (&label_expr); | |
10561 | else | |
10562 | label_expr.X_add_number = 8; | |
c0ebe874 | 10563 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10564 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10565 | |
10566 | /* We want to close the noreorder block as soon as possible, so | |
10567 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10568 | end_noreorder (); |
252b5132 | 10569 | |
df58fc94 | 10570 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10571 | } |
df58fc94 RS |
10572 | if (mips_opts.micromips) |
10573 | micromips_add_label (); | |
c0ebe874 | 10574 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10575 | break; |
10576 | ||
10577 | case M_DIV_3I: | |
10578 | s = "div"; | |
10579 | s2 = "mflo"; | |
10580 | goto do_divi; | |
10581 | case M_DIVU_3I: | |
10582 | s = "divu"; | |
10583 | s2 = "mflo"; | |
10584 | goto do_divi; | |
10585 | case M_REM_3I: | |
10586 | s = "div"; | |
10587 | s2 = "mfhi"; | |
10588 | goto do_divi; | |
10589 | case M_REMU_3I: | |
10590 | s = "divu"; | |
10591 | s2 = "mfhi"; | |
10592 | goto do_divi; | |
10593 | case M_DDIV_3I: | |
10594 | dbl = 1; | |
10595 | s = "ddiv"; | |
10596 | s2 = "mflo"; | |
10597 | goto do_divi; | |
10598 | case M_DDIVU_3I: | |
10599 | dbl = 1; | |
10600 | s = "ddivu"; | |
10601 | s2 = "mflo"; | |
10602 | goto do_divi; | |
10603 | case M_DREM_3I: | |
10604 | dbl = 1; | |
10605 | s = "ddiv"; | |
10606 | s2 = "mfhi"; | |
10607 | goto do_divi; | |
10608 | case M_DREMU_3I: | |
10609 | dbl = 1; | |
10610 | s = "ddivu"; | |
10611 | s2 = "mfhi"; | |
10612 | do_divi: | |
b0e6f033 | 10613 | if (imm_expr.X_add_number == 0) |
252b5132 | 10614 | { |
1661c76c | 10615 | as_warn (_("divide by zero")); |
252b5132 | 10616 | if (mips_trap) |
df58fc94 | 10617 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10618 | else |
df58fc94 | 10619 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10620 | break; |
252b5132 | 10621 | } |
b0e6f033 | 10622 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10623 | { |
10624 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10625 | move_register (op[0], op[1]); |
252b5132 | 10626 | else |
c0ebe874 | 10627 | move_register (op[0], ZERO); |
8fc2e39e | 10628 | break; |
252b5132 | 10629 | } |
b0e6f033 | 10630 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10631 | { |
10632 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10633 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10634 | else |
c0ebe874 | 10635 | move_register (op[0], ZERO); |
8fc2e39e | 10636 | break; |
252b5132 RH |
10637 | } |
10638 | ||
8fc2e39e | 10639 | used_at = 1; |
67c0d1eb | 10640 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10641 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10642 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10643 | break; |
10644 | ||
10645 | case M_DIVU_3: | |
10646 | s = "divu"; | |
10647 | s2 = "mflo"; | |
10648 | goto do_divu3; | |
10649 | case M_REMU_3: | |
10650 | s = "divu"; | |
10651 | s2 = "mfhi"; | |
10652 | goto do_divu3; | |
10653 | case M_DDIVU_3: | |
10654 | s = "ddivu"; | |
10655 | s2 = "mflo"; | |
10656 | goto do_divu3; | |
10657 | case M_DREMU_3: | |
10658 | s = "ddivu"; | |
10659 | s2 = "mfhi"; | |
10660 | do_divu3: | |
7d10b47d | 10661 | start_noreorder (); |
252b5132 RH |
10662 | if (mips_trap) |
10663 | { | |
c0ebe874 RS |
10664 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10665 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10666 | /* We want to close the noreorder block as soon as possible, so |
10667 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10668 | end_noreorder (); |
252b5132 RH |
10669 | } |
10670 | else | |
10671 | { | |
df58fc94 RS |
10672 | if (mips_opts.micromips) |
10673 | micromips_label_expr (&label_expr); | |
10674 | else | |
10675 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10676 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10677 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10678 | |
10679 | /* We want to close the noreorder block as soon as possible, so | |
10680 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10681 | end_noreorder (); |
df58fc94 RS |
10682 | macro_build (NULL, "break", BRK_FMT, 7); |
10683 | if (mips_opts.micromips) | |
10684 | micromips_add_label (); | |
252b5132 | 10685 | } |
c0ebe874 | 10686 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10687 | break; |
252b5132 | 10688 | |
1abe91b1 MR |
10689 | case M_DLCA_AB: |
10690 | dbl = 1; | |
1a0670f3 | 10691 | /* Fall through. */ |
1abe91b1 MR |
10692 | case M_LCA_AB: |
10693 | call = 1; | |
10694 | goto do_la; | |
252b5132 RH |
10695 | case M_DLA_AB: |
10696 | dbl = 1; | |
1a0670f3 | 10697 | /* Fall through. */ |
252b5132 | 10698 | case M_LA_AB: |
1abe91b1 | 10699 | do_la: |
252b5132 RH |
10700 | /* Load the address of a symbol into a register. If breg is not |
10701 | zero, we then add a base register to it. */ | |
10702 | ||
c0ebe874 | 10703 | breg = op[2]; |
bad1aba3 | 10704 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10705 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10706 | "instead")); | |
3bec30a8 | 10707 | |
90ecf173 | 10708 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10709 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10710 | "instead")); | |
3bec30a8 | 10711 | |
f2ae14a1 | 10712 | if (small_offset_p (0, align, 16)) |
0c11417f | 10713 | { |
c0ebe874 | 10714 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10715 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10716 | break; |
0c11417f MR |
10717 | } |
10718 | ||
c0ebe874 | 10719 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10720 | { |
10721 | tempreg = AT; | |
10722 | used_at = 1; | |
10723 | } | |
10724 | else | |
c0ebe874 | 10725 | tempreg = op[0]; |
afdbd6d0 | 10726 | |
252b5132 RH |
10727 | if (offset_expr.X_op != O_symbol |
10728 | && offset_expr.X_op != O_constant) | |
10729 | { | |
1661c76c | 10730 | as_bad (_("expression too complex")); |
252b5132 RH |
10731 | offset_expr.X_op = O_constant; |
10732 | } | |
10733 | ||
252b5132 | 10734 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10735 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10736 | else if (mips_pic == NO_PIC) |
10737 | { | |
d6bc6245 | 10738 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10739 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10740 | Otherwise we want |
10741 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10742 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10743 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10744 | so we may as well always use the latter form. |
76b3015f | 10745 | |
6caf9ef4 TS |
10746 | With 64bit address space and a usable $at we want |
10747 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10748 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10749 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10750 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10751 | dsll32 $tempreg,0 | |
10752 | daddu $tempreg,$tempreg,$at | |
10753 | ||
10754 | If $at is already in use, we use a path which is suboptimal | |
10755 | on superscalar processors. | |
10756 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10757 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10758 | dsll $tempreg,16 | |
10759 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10760 | dsll $tempreg,16 | |
10761 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10762 | ||
10763 | For GP relative symbols in 64bit address space we can use | |
10764 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10765 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10766 | { |
6caf9ef4 TS |
10767 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10768 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10769 | { | |
10770 | relax_start (offset_expr.X_add_symbol); | |
10771 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10772 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10773 | relax_switch (); | |
10774 | } | |
d6bc6245 | 10775 | |
741fe287 | 10776 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10777 | { |
df58fc94 | 10778 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10779 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10780 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10781 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10782 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10783 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10784 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10785 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10786 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10787 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10788 | used_at = 1; |
10789 | } | |
10790 | else | |
10791 | { | |
df58fc94 | 10792 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10793 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10794 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10795 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10796 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10797 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10798 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10799 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10800 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10801 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10802 | } |
6caf9ef4 TS |
10803 | |
10804 | if (mips_relax.sequence) | |
10805 | relax_end (); | |
98d3f06f KH |
10806 | } |
10807 | else | |
10808 | { | |
10809 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10810 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10811 | { |
4d7206a2 | 10812 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10813 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10814 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10815 | relax_switch (); |
98d3f06f | 10816 | } |
6943caf0 | 10817 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10818 | as_bad (_("offset too large")); |
67c0d1eb RS |
10819 | macro_build_lui (&offset_expr, tempreg); |
10820 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10821 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10822 | if (mips_relax.sequence) |
10823 | relax_end (); | |
98d3f06f | 10824 | } |
252b5132 | 10825 | } |
0a44bf69 | 10826 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10827 | { |
9117d219 NC |
10828 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10829 | ||
252b5132 RH |
10830 | /* If this is a reference to an external symbol, and there |
10831 | is no constant, we want | |
10832 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10833 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10834 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10835 | For a local symbol, we want |
10836 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10837 | nop | |
10838 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10839 | ||
10840 | If we have a small constant, and this is a reference to | |
10841 | an external symbol, we want | |
10842 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10843 | nop | |
10844 | addiu $tempreg,$tempreg,<constant> | |
10845 | For a local symbol, we want the same instruction | |
10846 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10847 | addiu instruction. | |
10848 | ||
10849 | If we have a large constant, and this is a reference to | |
10850 | an external symbol, we want | |
10851 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10852 | lui $at,<hiconstant> | |
10853 | addiu $at,$at,<loconstant> | |
10854 | addu $tempreg,$tempreg,$at | |
10855 | For a local symbol, we want the same instruction | |
10856 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10857 | addiu instruction. |
ed6fb7bd SC |
10858 | */ |
10859 | ||
4d7206a2 | 10860 | if (offset_expr.X_add_number == 0) |
252b5132 | 10861 | { |
0a44bf69 RS |
10862 | if (mips_pic == SVR4_PIC |
10863 | && breg == 0 | |
10864 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10865 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10866 | ||
10867 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10868 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10869 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10870 | if (breg != 0) |
252b5132 RH |
10871 | { |
10872 | /* We're going to put in an addu instruction using | |
10873 | tempreg, so we may as well insert the nop right | |
10874 | now. */ | |
269137b2 | 10875 | load_delay_nop (); |
252b5132 | 10876 | } |
4d7206a2 | 10877 | relax_switch (); |
67c0d1eb RS |
10878 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10879 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10880 | load_delay_nop (); |
67c0d1eb RS |
10881 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10882 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10883 | relax_end (); |
252b5132 RH |
10884 | /* FIXME: If breg == 0, and the next instruction uses |
10885 | $tempreg, then if this variant case is used an extra | |
10886 | nop will be generated. */ | |
10887 | } | |
4d7206a2 RS |
10888 | else if (offset_expr.X_add_number >= -0x8000 |
10889 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10890 | { |
67c0d1eb | 10891 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10892 | load_delay_nop (); |
67c0d1eb | 10893 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10894 | } |
10895 | else | |
10896 | { | |
4d7206a2 RS |
10897 | expr1.X_add_number = offset_expr.X_add_number; |
10898 | offset_expr.X_add_number = | |
43c0598f | 10899 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10900 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10901 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10902 | /* If we are going to add in a base register, and the |
10903 | target register and the base register are the same, | |
10904 | then we are using AT as a temporary register. Since | |
10905 | we want to load the constant into AT, we add our | |
10906 | current AT (from the global offset table) and the | |
10907 | register into the register now, and pretend we were | |
10908 | not using a base register. */ | |
c0ebe874 | 10909 | if (breg == op[0]) |
252b5132 | 10910 | { |
269137b2 | 10911 | load_delay_nop (); |
67c0d1eb | 10912 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10913 | op[0], AT, breg); |
252b5132 | 10914 | breg = 0; |
c0ebe874 | 10915 | tempreg = op[0]; |
252b5132 | 10916 | } |
f6a22291 | 10917 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10918 | used_at = 1; |
10919 | } | |
10920 | } | |
0a44bf69 | 10921 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10922 | { |
67c0d1eb | 10923 | int add_breg_early = 0; |
f5040a92 AO |
10924 | |
10925 | /* If this is a reference to an external, and there is no | |
10926 | constant, or local symbol (*), with or without a | |
10927 | constant, we want | |
10928 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10929 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10930 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10931 | ||
10932 | If we have a small constant, and this is a reference to | |
10933 | an external symbol, we want | |
10934 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10935 | addiu $tempreg,$tempreg,<constant> | |
10936 | ||
10937 | If we have a large constant, and this is a reference to | |
10938 | an external symbol, we want | |
10939 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10940 | lui $at,<hiconstant> | |
10941 | addiu $at,$at,<loconstant> | |
10942 | addu $tempreg,$tempreg,$at | |
10943 | ||
10944 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10945 | local symbols, even though it introduces an additional | |
10946 | instruction. */ | |
10947 | ||
f5040a92 AO |
10948 | if (offset_expr.X_add_number) |
10949 | { | |
4d7206a2 | 10950 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10951 | offset_expr.X_add_number = 0; |
10952 | ||
4d7206a2 | 10953 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10954 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10955 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10956 | |
10957 | if (expr1.X_add_number >= -0x8000 | |
10958 | && expr1.X_add_number < 0x8000) | |
10959 | { | |
67c0d1eb RS |
10960 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10961 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10962 | } |
ecd13cd3 | 10963 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10964 | { |
c0ebe874 RS |
10965 | unsigned int dreg; |
10966 | ||
f5040a92 AO |
10967 | /* If we are going to add in a base register, and the |
10968 | target register and the base register are the same, | |
10969 | then we are using AT as a temporary register. Since | |
10970 | we want to load the constant into AT, we add our | |
10971 | current AT (from the global offset table) and the | |
10972 | register into the register now, and pretend we were | |
10973 | not using a base register. */ | |
c0ebe874 | 10974 | if (breg != op[0]) |
f5040a92 AO |
10975 | dreg = tempreg; |
10976 | else | |
10977 | { | |
9c2799c2 | 10978 | gas_assert (tempreg == AT); |
67c0d1eb | 10979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10980 | op[0], AT, breg); |
10981 | dreg = op[0]; | |
67c0d1eb | 10982 | add_breg_early = 1; |
f5040a92 AO |
10983 | } |
10984 | ||
f6a22291 | 10985 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10986 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10987 | dreg, dreg, AT); |
f5040a92 | 10988 | |
f5040a92 AO |
10989 | used_at = 1; |
10990 | } | |
10991 | else | |
10992 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10993 | ||
4d7206a2 | 10994 | relax_switch (); |
f5040a92 AO |
10995 | offset_expr.X_add_number = expr1.X_add_number; |
10996 | ||
67c0d1eb RS |
10997 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10998 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
10999 | if (add_breg_early) | |
f5040a92 | 11000 | { |
67c0d1eb | 11001 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11002 | op[0], tempreg, breg); |
f5040a92 | 11003 | breg = 0; |
c0ebe874 | 11004 | tempreg = op[0]; |
f5040a92 | 11005 | } |
4d7206a2 | 11006 | relax_end (); |
f5040a92 | 11007 | } |
4d7206a2 | 11008 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11009 | { |
4d7206a2 | 11010 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11012 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11013 | relax_switch (); |
67c0d1eb RS |
11014 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11015 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11016 | relax_end (); |
f5040a92 | 11017 | } |
4d7206a2 | 11018 | else |
f5040a92 | 11019 | { |
67c0d1eb RS |
11020 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11021 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11022 | } |
11023 | } | |
0a44bf69 | 11024 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11025 | { |
67c0d1eb | 11026 | int gpdelay; |
9117d219 NC |
11027 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11028 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11029 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11030 | |
11031 | /* This is the large GOT case. If this is a reference to an | |
11032 | external symbol, and there is no constant, we want | |
11033 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11034 | addu $tempreg,$tempreg,$gp | |
11035 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11036 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11037 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11038 | addu $tempreg,$tempreg,$gp | |
11039 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11040 | For a local symbol, we want |
11041 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11042 | nop | |
11043 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11044 | ||
11045 | If we have a small constant, and this is a reference to | |
11046 | an external symbol, we want | |
11047 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11048 | addu $tempreg,$tempreg,$gp | |
11049 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11050 | nop | |
11051 | addiu $tempreg,$tempreg,<constant> | |
11052 | For a local symbol, we want | |
11053 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11054 | nop | |
11055 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11056 | ||
11057 | If we have a large constant, and this is a reference to | |
11058 | an external symbol, we want | |
11059 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11060 | addu $tempreg,$tempreg,$gp | |
11061 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11062 | lui $at,<hiconstant> | |
11063 | addiu $at,$at,<loconstant> | |
11064 | addu $tempreg,$tempreg,$at | |
11065 | For a local symbol, we want | |
11066 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11067 | lui $at,<hiconstant> | |
11068 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11069 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11070 | */ |
438c16b8 | 11071 | |
252b5132 RH |
11072 | expr1.X_add_number = offset_expr.X_add_number; |
11073 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11074 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11075 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11076 | if (expr1.X_add_number == 0 && breg == 0 |
11077 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11078 | { |
11079 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11080 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11081 | } | |
df58fc94 | 11082 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11083 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11084 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11085 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11086 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11087 | if (expr1.X_add_number == 0) |
11088 | { | |
67c0d1eb | 11089 | if (breg != 0) |
252b5132 RH |
11090 | { |
11091 | /* We're going to put in an addu instruction using | |
11092 | tempreg, so we may as well insert the nop right | |
11093 | now. */ | |
269137b2 | 11094 | load_delay_nop (); |
252b5132 | 11095 | } |
252b5132 RH |
11096 | } |
11097 | else if (expr1.X_add_number >= -0x8000 | |
11098 | && expr1.X_add_number < 0x8000) | |
11099 | { | |
269137b2 | 11100 | load_delay_nop (); |
67c0d1eb | 11101 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11102 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11103 | } |
11104 | else | |
11105 | { | |
c0ebe874 RS |
11106 | unsigned int dreg; |
11107 | ||
252b5132 RH |
11108 | /* If we are going to add in a base register, and the |
11109 | target register and the base register are the same, | |
11110 | then we are using AT as a temporary register. Since | |
11111 | we want to load the constant into AT, we add our | |
11112 | current AT (from the global offset table) and the | |
11113 | register into the register now, and pretend we were | |
11114 | not using a base register. */ | |
c0ebe874 | 11115 | if (breg != op[0]) |
67c0d1eb | 11116 | dreg = tempreg; |
252b5132 RH |
11117 | else |
11118 | { | |
9c2799c2 | 11119 | gas_assert (tempreg == AT); |
269137b2 | 11120 | load_delay_nop (); |
67c0d1eb | 11121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11122 | op[0], AT, breg); |
11123 | dreg = op[0]; | |
252b5132 RH |
11124 | } |
11125 | ||
f6a22291 | 11126 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11127 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11128 | |
252b5132 RH |
11129 | used_at = 1; |
11130 | } | |
43c0598f | 11131 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11132 | relax_switch (); |
252b5132 | 11133 | |
67c0d1eb | 11134 | if (gpdelay) |
252b5132 RH |
11135 | { |
11136 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11137 | the first instruction on the main stream does not. */ |
67c0d1eb | 11138 | macro_build (NULL, "nop", ""); |
252b5132 | 11139 | } |
ed6fb7bd | 11140 | |
67c0d1eb RS |
11141 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11142 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11143 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11144 | && expr1.X_add_number < 0x8000) |
11145 | { | |
269137b2 | 11146 | load_delay_nop (); |
67c0d1eb RS |
11147 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11148 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11149 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11150 | register, the external symbol case ended with a load, |
11151 | so if the symbol turns out to not be external, and | |
11152 | the next instruction uses tempreg, an unnecessary nop | |
11153 | will be inserted. */ | |
252b5132 RH |
11154 | } |
11155 | else | |
11156 | { | |
c0ebe874 | 11157 | if (breg == op[0]) |
252b5132 RH |
11158 | { |
11159 | /* We must add in the base register now, as in the | |
f5040a92 | 11160 | external symbol case. */ |
9c2799c2 | 11161 | gas_assert (tempreg == AT); |
269137b2 | 11162 | load_delay_nop (); |
67c0d1eb | 11163 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11164 | op[0], AT, breg); |
11165 | tempreg = op[0]; | |
252b5132 | 11166 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11167 | it in in both cases. */ |
252b5132 RH |
11168 | breg = 0; |
11169 | } | |
11170 | ||
67c0d1eb RS |
11171 | macro_build_lui (&expr1, AT); |
11172 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11173 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11175 | tempreg, tempreg, AT); |
8fc2e39e | 11176 | used_at = 1; |
252b5132 | 11177 | } |
4d7206a2 | 11178 | relax_end (); |
252b5132 | 11179 | } |
0a44bf69 | 11180 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11181 | { |
f5040a92 AO |
11182 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11183 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11184 | int add_breg_early = 0; |
f5040a92 AO |
11185 | |
11186 | /* This is the large GOT case. If this is a reference to an | |
11187 | external symbol, and there is no constant, we want | |
11188 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11189 | add $tempreg,$tempreg,$gp | |
11190 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11191 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11192 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11193 | add $tempreg,$tempreg,$gp | |
11194 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11195 | ||
11196 | If we have a small constant, and this is a reference to | |
11197 | an external symbol, we want | |
11198 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11199 | add $tempreg,$tempreg,$gp | |
11200 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11201 | addi $tempreg,$tempreg,<constant> | |
11202 | ||
11203 | If we have a large constant, and this is a reference to | |
11204 | an external symbol, we want | |
11205 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11206 | addu $tempreg,$tempreg,$gp | |
11207 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11208 | lui $at,<hiconstant> | |
11209 | addi $at,$at,<loconstant> | |
11210 | add $tempreg,$tempreg,$at | |
11211 | ||
11212 | If we have NewABI, and we know it's a local symbol, we want | |
11213 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11214 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11215 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11216 | ||
4d7206a2 | 11217 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11218 | |
4d7206a2 | 11219 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11220 | offset_expr.X_add_number = 0; |
11221 | ||
1abe91b1 MR |
11222 | if (expr1.X_add_number == 0 && breg == 0 |
11223 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11224 | { |
11225 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11226 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11227 | } | |
df58fc94 | 11228 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11229 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11230 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11231 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11232 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11233 | |
11234 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11235 | ; |
f5040a92 AO |
11236 | else if (expr1.X_add_number >= -0x8000 |
11237 | && expr1.X_add_number < 0x8000) | |
11238 | { | |
67c0d1eb | 11239 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11240 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11241 | } |
ecd13cd3 | 11242 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11243 | { |
c0ebe874 RS |
11244 | unsigned int dreg; |
11245 | ||
f5040a92 AO |
11246 | /* If we are going to add in a base register, and the |
11247 | target register and the base register are the same, | |
11248 | then we are using AT as a temporary register. Since | |
11249 | we want to load the constant into AT, we add our | |
11250 | current AT (from the global offset table) and the | |
11251 | register into the register now, and pretend we were | |
11252 | not using a base register. */ | |
c0ebe874 | 11253 | if (breg != op[0]) |
f5040a92 AO |
11254 | dreg = tempreg; |
11255 | else | |
11256 | { | |
9c2799c2 | 11257 | gas_assert (tempreg == AT); |
67c0d1eb | 11258 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11259 | op[0], AT, breg); |
11260 | dreg = op[0]; | |
67c0d1eb | 11261 | add_breg_early = 1; |
f5040a92 AO |
11262 | } |
11263 | ||
f6a22291 | 11264 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11265 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11266 | |
f5040a92 AO |
11267 | used_at = 1; |
11268 | } | |
11269 | else | |
11270 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11271 | ||
4d7206a2 | 11272 | relax_switch (); |
f5040a92 | 11273 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11274 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11275 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11276 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11277 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11278 | if (add_breg_early) | |
f5040a92 | 11279 | { |
67c0d1eb | 11280 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11281 | op[0], tempreg, breg); |
f5040a92 | 11282 | breg = 0; |
c0ebe874 | 11283 | tempreg = op[0]; |
f5040a92 | 11284 | } |
4d7206a2 | 11285 | relax_end (); |
f5040a92 | 11286 | } |
252b5132 RH |
11287 | else |
11288 | abort (); | |
11289 | ||
11290 | if (breg != 0) | |
c0ebe874 | 11291 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11292 | break; |
11293 | ||
52b6b6b9 | 11294 | case M_MSGSND: |
df58fc94 | 11295 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11296 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11297 | break; |
52b6b6b9 JM |
11298 | |
11299 | case M_MSGLD: | |
df58fc94 | 11300 | gas_assert (!mips_opts.micromips); |
c8276761 | 11301 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11302 | break; |
52b6b6b9 JM |
11303 | |
11304 | case M_MSGLD_T: | |
df58fc94 | 11305 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11306 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11307 | break; |
52b6b6b9 JM |
11308 | |
11309 | case M_MSGWAIT: | |
df58fc94 | 11310 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11311 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11312 | break; |
52b6b6b9 JM |
11313 | |
11314 | case M_MSGWAIT_T: | |
df58fc94 | 11315 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11316 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11317 | break; |
52b6b6b9 | 11318 | |
252b5132 RH |
11319 | case M_J_A: |
11320 | /* The j instruction may not be used in PIC code, since it | |
11321 | requires an absolute address. We convert it to a b | |
11322 | instruction. */ | |
11323 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11324 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11325 | else |
67c0d1eb | 11326 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11327 | break; |
252b5132 RH |
11328 | |
11329 | /* The jal instructions must be handled as macros because when | |
11330 | generating PIC code they expand to multi-instruction | |
11331 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11332 | case M_JALS_1: |
c0ebe874 RS |
11333 | op[1] = op[0]; |
11334 | op[0] = RA; | |
df58fc94 RS |
11335 | /* Fall through. */ |
11336 | case M_JALS_2: | |
11337 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11338 | if (mips_opts.insn32) |
11339 | { | |
1661c76c | 11340 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11341 | break; |
11342 | } | |
df58fc94 RS |
11343 | jals = 1; |
11344 | goto jal; | |
252b5132 | 11345 | case M_JAL_1: |
c0ebe874 RS |
11346 | op[1] = op[0]; |
11347 | op[0] = RA; | |
252b5132 RH |
11348 | /* Fall through. */ |
11349 | case M_JAL_2: | |
df58fc94 | 11350 | jal: |
3e722fb5 | 11351 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11352 | { |
11353 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11354 | if (mips_opts.micromips |
833794fc | 11355 | && !mips_opts.insn32 |
c0ebe874 | 11356 | && op[0] == RA |
e64af278 | 11357 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11358 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11359 | else |
c0ebe874 | 11360 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11361 | } |
0a44bf69 | 11362 | else |
252b5132 | 11363 | { |
df58fc94 RS |
11364 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11365 | && mips_cprestore_offset >= 0); | |
11366 | ||
c0ebe874 | 11367 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11368 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11369 | |
833794fc MR |
11370 | s = ((mips_opts.micromips |
11371 | && !mips_opts.insn32 | |
11372 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11373 | ? "jalrs" : "jalr"); |
e64af278 | 11374 | if (mips_opts.micromips |
833794fc | 11375 | && !mips_opts.insn32 |
c0ebe874 | 11376 | && op[0] == RA |
e64af278 | 11377 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11378 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11379 | else |
c0ebe874 | 11380 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11381 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11382 | { |
6478892d | 11383 | if (mips_cprestore_offset < 0) |
1661c76c | 11384 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11385 | else |
11386 | { | |
90ecf173 | 11387 | if (!mips_frame_reg_valid) |
7a621144 | 11388 | { |
1661c76c | 11389 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11390 | /* Quiet this warning. */ |
11391 | mips_frame_reg_valid = 1; | |
11392 | } | |
90ecf173 | 11393 | if (!mips_cprestore_valid) |
7a621144 | 11394 | { |
1661c76c | 11395 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11396 | /* Quiet this warning. */ |
11397 | mips_cprestore_valid = 1; | |
11398 | } | |
d3fca0b5 MR |
11399 | if (mips_opts.noreorder) |
11400 | macro_build (NULL, "nop", ""); | |
6478892d | 11401 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11402 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11403 | mips_gp_register, |
256ab948 TS |
11404 | mips_frame_reg, |
11405 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11406 | } |
252b5132 RH |
11407 | } |
11408 | } | |
252b5132 | 11409 | |
8fc2e39e | 11410 | break; |
252b5132 | 11411 | |
df58fc94 RS |
11412 | case M_JALS_A: |
11413 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11414 | if (mips_opts.insn32) |
11415 | { | |
1661c76c | 11416 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11417 | break; |
11418 | } | |
df58fc94 RS |
11419 | jals = 1; |
11420 | /* Fall through. */ | |
252b5132 RH |
11421 | case M_JAL_A: |
11422 | if (mips_pic == NO_PIC) | |
df58fc94 | 11423 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11424 | else if (mips_pic == SVR4_PIC) |
11425 | { | |
11426 | /* If this is a reference to an external symbol, and we are | |
11427 | using a small GOT, we want | |
11428 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11429 | nop | |
f9419b05 | 11430 | jalr $ra,$25 |
252b5132 RH |
11431 | nop |
11432 | lw $gp,cprestore($sp) | |
11433 | The cprestore value is set using the .cprestore | |
11434 | pseudo-op. If we are using a big GOT, we want | |
11435 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11436 | addu $25,$25,$gp | |
11437 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11438 | nop | |
f9419b05 | 11439 | jalr $ra,$25 |
252b5132 RH |
11440 | nop |
11441 | lw $gp,cprestore($sp) | |
11442 | If the symbol is not external, we want | |
11443 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11444 | nop | |
11445 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11446 | jalr $ra,$25 |
252b5132 | 11447 | nop |
438c16b8 | 11448 | lw $gp,cprestore($sp) |
f5040a92 AO |
11449 | |
11450 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11451 | sequences above, minus nops, unless the symbol is local, | |
11452 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11453 | GOT_DISP. */ | |
438c16b8 | 11454 | if (HAVE_NEWABI) |
252b5132 | 11455 | { |
90ecf173 | 11456 | if (!mips_big_got) |
f5040a92 | 11457 | { |
4d7206a2 | 11458 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11459 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11460 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11461 | mips_gp_register); |
4d7206a2 | 11462 | relax_switch (); |
67c0d1eb RS |
11463 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11464 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11465 | mips_gp_register); |
11466 | relax_end (); | |
f5040a92 AO |
11467 | } |
11468 | else | |
11469 | { | |
4d7206a2 | 11470 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11471 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11472 | BFD_RELOC_MIPS_CALL_HI16); |
11473 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11474 | PIC_CALL_REG, mips_gp_register); | |
11475 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11476 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11477 | PIC_CALL_REG); | |
4d7206a2 | 11478 | relax_switch (); |
67c0d1eb RS |
11479 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11480 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11481 | mips_gp_register); | |
11482 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11483 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11484 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11485 | relax_end (); |
f5040a92 | 11486 | } |
684022ea | 11487 | |
df58fc94 | 11488 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11489 | } |
11490 | else | |
11491 | { | |
4d7206a2 | 11492 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11493 | if (!mips_big_got) |
438c16b8 | 11494 | { |
67c0d1eb RS |
11495 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11496 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11497 | mips_gp_register); |
269137b2 | 11498 | load_delay_nop (); |
4d7206a2 | 11499 | relax_switch (); |
438c16b8 | 11500 | } |
252b5132 | 11501 | else |
252b5132 | 11502 | { |
67c0d1eb RS |
11503 | int gpdelay; |
11504 | ||
11505 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11506 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11507 | BFD_RELOC_MIPS_CALL_HI16); |
11508 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11509 | PIC_CALL_REG, mips_gp_register); | |
11510 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11511 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11512 | PIC_CALL_REG); | |
269137b2 | 11513 | load_delay_nop (); |
4d7206a2 | 11514 | relax_switch (); |
67c0d1eb RS |
11515 | if (gpdelay) |
11516 | macro_build (NULL, "nop", ""); | |
252b5132 | 11517 | } |
67c0d1eb RS |
11518 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11519 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11520 | mips_gp_register); |
269137b2 | 11521 | load_delay_nop (); |
67c0d1eb RS |
11522 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11523 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11524 | relax_end (); |
df58fc94 | 11525 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11526 | |
6478892d | 11527 | if (mips_cprestore_offset < 0) |
1661c76c | 11528 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11529 | else |
11530 | { | |
90ecf173 | 11531 | if (!mips_frame_reg_valid) |
7a621144 | 11532 | { |
1661c76c | 11533 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11534 | /* Quiet this warning. */ |
11535 | mips_frame_reg_valid = 1; | |
11536 | } | |
90ecf173 | 11537 | if (!mips_cprestore_valid) |
7a621144 | 11538 | { |
1661c76c | 11539 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11540 | /* Quiet this warning. */ |
11541 | mips_cprestore_valid = 1; | |
11542 | } | |
6478892d | 11543 | if (mips_opts.noreorder) |
67c0d1eb | 11544 | macro_build (NULL, "nop", ""); |
6478892d | 11545 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11546 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11547 | mips_gp_register, |
256ab948 TS |
11548 | mips_frame_reg, |
11549 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11550 | } |
252b5132 RH |
11551 | } |
11552 | } | |
0a44bf69 | 11553 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11554 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11555 | else |
11556 | abort (); | |
11557 | ||
8fc2e39e | 11558 | break; |
252b5132 | 11559 | |
7f3c4072 | 11560 | case M_LBUE_AB: |
7f3c4072 CM |
11561 | s = "lbue"; |
11562 | fmt = "t,+j(b)"; | |
11563 | offbits = 9; | |
11564 | goto ld_st; | |
11565 | case M_LHUE_AB: | |
7f3c4072 CM |
11566 | s = "lhue"; |
11567 | fmt = "t,+j(b)"; | |
11568 | offbits = 9; | |
11569 | goto ld_st; | |
11570 | case M_LBE_AB: | |
7f3c4072 CM |
11571 | s = "lbe"; |
11572 | fmt = "t,+j(b)"; | |
11573 | offbits = 9; | |
11574 | goto ld_st; | |
11575 | case M_LHE_AB: | |
7f3c4072 CM |
11576 | s = "lhe"; |
11577 | fmt = "t,+j(b)"; | |
11578 | offbits = 9; | |
11579 | goto ld_st; | |
11580 | case M_LLE_AB: | |
7f3c4072 CM |
11581 | s = "lle"; |
11582 | fmt = "t,+j(b)"; | |
11583 | offbits = 9; | |
11584 | goto ld_st; | |
11585 | case M_LWE_AB: | |
7f3c4072 CM |
11586 | s = "lwe"; |
11587 | fmt = "t,+j(b)"; | |
11588 | offbits = 9; | |
11589 | goto ld_st; | |
11590 | case M_LWLE_AB: | |
7f3c4072 CM |
11591 | s = "lwle"; |
11592 | fmt = "t,+j(b)"; | |
11593 | offbits = 9; | |
11594 | goto ld_st; | |
11595 | case M_LWRE_AB: | |
7f3c4072 CM |
11596 | s = "lwre"; |
11597 | fmt = "t,+j(b)"; | |
11598 | offbits = 9; | |
11599 | goto ld_st; | |
11600 | case M_SBE_AB: | |
7f3c4072 CM |
11601 | s = "sbe"; |
11602 | fmt = "t,+j(b)"; | |
11603 | offbits = 9; | |
11604 | goto ld_st; | |
11605 | case M_SCE_AB: | |
7f3c4072 CM |
11606 | s = "sce"; |
11607 | fmt = "t,+j(b)"; | |
11608 | offbits = 9; | |
11609 | goto ld_st; | |
11610 | case M_SHE_AB: | |
7f3c4072 CM |
11611 | s = "she"; |
11612 | fmt = "t,+j(b)"; | |
11613 | offbits = 9; | |
11614 | goto ld_st; | |
11615 | case M_SWE_AB: | |
7f3c4072 CM |
11616 | s = "swe"; |
11617 | fmt = "t,+j(b)"; | |
11618 | offbits = 9; | |
11619 | goto ld_st; | |
11620 | case M_SWLE_AB: | |
7f3c4072 CM |
11621 | s = "swle"; |
11622 | fmt = "t,+j(b)"; | |
11623 | offbits = 9; | |
11624 | goto ld_st; | |
11625 | case M_SWRE_AB: | |
7f3c4072 CM |
11626 | s = "swre"; |
11627 | fmt = "t,+j(b)"; | |
11628 | offbits = 9; | |
11629 | goto ld_st; | |
dec0624d | 11630 | case M_ACLR_AB: |
dec0624d | 11631 | s = "aclr"; |
dec0624d | 11632 | fmt = "\\,~(b)"; |
7f3c4072 | 11633 | offbits = 12; |
dec0624d MR |
11634 | goto ld_st; |
11635 | case M_ASET_AB: | |
dec0624d | 11636 | s = "aset"; |
dec0624d | 11637 | fmt = "\\,~(b)"; |
7f3c4072 | 11638 | offbits = 12; |
dec0624d | 11639 | goto ld_st; |
252b5132 RH |
11640 | case M_LB_AB: |
11641 | s = "lb"; | |
df58fc94 | 11642 | fmt = "t,o(b)"; |
252b5132 RH |
11643 | goto ld; |
11644 | case M_LBU_AB: | |
11645 | s = "lbu"; | |
df58fc94 | 11646 | fmt = "t,o(b)"; |
252b5132 RH |
11647 | goto ld; |
11648 | case M_LH_AB: | |
11649 | s = "lh"; | |
df58fc94 | 11650 | fmt = "t,o(b)"; |
252b5132 RH |
11651 | goto ld; |
11652 | case M_LHU_AB: | |
11653 | s = "lhu"; | |
df58fc94 | 11654 | fmt = "t,o(b)"; |
252b5132 RH |
11655 | goto ld; |
11656 | case M_LW_AB: | |
11657 | s = "lw"; | |
df58fc94 | 11658 | fmt = "t,o(b)"; |
252b5132 RH |
11659 | goto ld; |
11660 | case M_LWC0_AB: | |
df58fc94 | 11661 | gas_assert (!mips_opts.micromips); |
252b5132 | 11662 | s = "lwc0"; |
df58fc94 | 11663 | fmt = "E,o(b)"; |
bdaaa2e1 | 11664 | /* Itbl support may require additional care here. */ |
252b5132 | 11665 | coproc = 1; |
df58fc94 | 11666 | goto ld_st; |
252b5132 RH |
11667 | case M_LWC1_AB: |
11668 | s = "lwc1"; | |
df58fc94 | 11669 | fmt = "T,o(b)"; |
bdaaa2e1 | 11670 | /* Itbl support may require additional care here. */ |
252b5132 | 11671 | coproc = 1; |
df58fc94 | 11672 | goto ld_st; |
252b5132 RH |
11673 | case M_LWC2_AB: |
11674 | s = "lwc2"; | |
df58fc94 | 11675 | fmt = COP12_FMT; |
7361da2c AB |
11676 | offbits = (mips_opts.micromips ? 12 |
11677 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11678 | : 16); | |
bdaaa2e1 | 11679 | /* Itbl support may require additional care here. */ |
252b5132 | 11680 | coproc = 1; |
df58fc94 | 11681 | goto ld_st; |
252b5132 | 11682 | case M_LWC3_AB: |
df58fc94 | 11683 | gas_assert (!mips_opts.micromips); |
252b5132 | 11684 | s = "lwc3"; |
df58fc94 | 11685 | fmt = "E,o(b)"; |
bdaaa2e1 | 11686 | /* Itbl support may require additional care here. */ |
252b5132 | 11687 | coproc = 1; |
df58fc94 | 11688 | goto ld_st; |
252b5132 RH |
11689 | case M_LWL_AB: |
11690 | s = "lwl"; | |
df58fc94 | 11691 | fmt = MEM12_FMT; |
7f3c4072 | 11692 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11693 | goto ld_st; |
252b5132 RH |
11694 | case M_LWR_AB: |
11695 | s = "lwr"; | |
df58fc94 | 11696 | fmt = MEM12_FMT; |
7f3c4072 | 11697 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11698 | goto ld_st; |
252b5132 | 11699 | case M_LDC1_AB: |
252b5132 | 11700 | s = "ldc1"; |
df58fc94 | 11701 | fmt = "T,o(b)"; |
bdaaa2e1 | 11702 | /* Itbl support may require additional care here. */ |
252b5132 | 11703 | coproc = 1; |
df58fc94 | 11704 | goto ld_st; |
252b5132 RH |
11705 | case M_LDC2_AB: |
11706 | s = "ldc2"; | |
df58fc94 | 11707 | fmt = COP12_FMT; |
7361da2c AB |
11708 | offbits = (mips_opts.micromips ? 12 |
11709 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11710 | : 16); | |
bdaaa2e1 | 11711 | /* Itbl support may require additional care here. */ |
252b5132 | 11712 | coproc = 1; |
df58fc94 | 11713 | goto ld_st; |
c77c0862 | 11714 | case M_LQC2_AB: |
c77c0862 | 11715 | s = "lqc2"; |
14daeee3 | 11716 | fmt = "+7,o(b)"; |
c77c0862 RS |
11717 | /* Itbl support may require additional care here. */ |
11718 | coproc = 1; | |
11719 | goto ld_st; | |
252b5132 RH |
11720 | case M_LDC3_AB: |
11721 | s = "ldc3"; | |
df58fc94 | 11722 | fmt = "E,o(b)"; |
bdaaa2e1 | 11723 | /* Itbl support may require additional care here. */ |
252b5132 | 11724 | coproc = 1; |
df58fc94 | 11725 | goto ld_st; |
252b5132 RH |
11726 | case M_LDL_AB: |
11727 | s = "ldl"; | |
df58fc94 | 11728 | fmt = MEM12_FMT; |
7f3c4072 | 11729 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11730 | goto ld_st; |
252b5132 RH |
11731 | case M_LDR_AB: |
11732 | s = "ldr"; | |
df58fc94 | 11733 | fmt = MEM12_FMT; |
7f3c4072 | 11734 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11735 | goto ld_st; |
252b5132 RH |
11736 | case M_LL_AB: |
11737 | s = "ll"; | |
7361da2c AB |
11738 | fmt = LL_SC_FMT; |
11739 | offbits = (mips_opts.micromips ? 12 | |
11740 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11741 | : 16); | |
252b5132 RH |
11742 | goto ld; |
11743 | case M_LLD_AB: | |
11744 | s = "lld"; | |
7361da2c AB |
11745 | fmt = LL_SC_FMT; |
11746 | offbits = (mips_opts.micromips ? 12 | |
11747 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11748 | : 16); | |
252b5132 RH |
11749 | goto ld; |
11750 | case M_LWU_AB: | |
11751 | s = "lwu"; | |
df58fc94 | 11752 | fmt = MEM12_FMT; |
7f3c4072 | 11753 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11754 | goto ld; |
11755 | case M_LWP_AB: | |
df58fc94 RS |
11756 | gas_assert (mips_opts.micromips); |
11757 | s = "lwp"; | |
11758 | fmt = "t,~(b)"; | |
7f3c4072 | 11759 | offbits = 12; |
df58fc94 RS |
11760 | lp = 1; |
11761 | goto ld; | |
11762 | case M_LDP_AB: | |
df58fc94 RS |
11763 | gas_assert (mips_opts.micromips); |
11764 | s = "ldp"; | |
11765 | fmt = "t,~(b)"; | |
7f3c4072 | 11766 | offbits = 12; |
df58fc94 RS |
11767 | lp = 1; |
11768 | goto ld; | |
11769 | case M_LWM_AB: | |
df58fc94 RS |
11770 | gas_assert (mips_opts.micromips); |
11771 | s = "lwm"; | |
11772 | fmt = "n,~(b)"; | |
7f3c4072 | 11773 | offbits = 12; |
df58fc94 RS |
11774 | goto ld_st; |
11775 | case M_LDM_AB: | |
df58fc94 RS |
11776 | gas_assert (mips_opts.micromips); |
11777 | s = "ldm"; | |
11778 | fmt = "n,~(b)"; | |
7f3c4072 | 11779 | offbits = 12; |
df58fc94 RS |
11780 | goto ld_st; |
11781 | ||
252b5132 | 11782 | ld: |
f19ccbda | 11783 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11784 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11785 | goto ld_st; |
252b5132 | 11786 | else |
c0ebe874 | 11787 | tempreg = op[0] + lp; |
df58fc94 RS |
11788 | goto ld_noat; |
11789 | ||
252b5132 RH |
11790 | case M_SB_AB: |
11791 | s = "sb"; | |
df58fc94 RS |
11792 | fmt = "t,o(b)"; |
11793 | goto ld_st; | |
252b5132 RH |
11794 | case M_SH_AB: |
11795 | s = "sh"; | |
df58fc94 RS |
11796 | fmt = "t,o(b)"; |
11797 | goto ld_st; | |
252b5132 RH |
11798 | case M_SW_AB: |
11799 | s = "sw"; | |
df58fc94 RS |
11800 | fmt = "t,o(b)"; |
11801 | goto ld_st; | |
252b5132 | 11802 | case M_SWC0_AB: |
df58fc94 | 11803 | gas_assert (!mips_opts.micromips); |
252b5132 | 11804 | s = "swc0"; |
df58fc94 | 11805 | fmt = "E,o(b)"; |
bdaaa2e1 | 11806 | /* Itbl support may require additional care here. */ |
252b5132 | 11807 | coproc = 1; |
df58fc94 | 11808 | goto ld_st; |
252b5132 RH |
11809 | case M_SWC1_AB: |
11810 | s = "swc1"; | |
df58fc94 | 11811 | fmt = "T,o(b)"; |
bdaaa2e1 | 11812 | /* Itbl support may require additional care here. */ |
252b5132 | 11813 | coproc = 1; |
df58fc94 | 11814 | goto ld_st; |
252b5132 RH |
11815 | case M_SWC2_AB: |
11816 | s = "swc2"; | |
df58fc94 | 11817 | fmt = COP12_FMT; |
7361da2c AB |
11818 | offbits = (mips_opts.micromips ? 12 |
11819 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11820 | : 16); | |
bdaaa2e1 | 11821 | /* Itbl support may require additional care here. */ |
252b5132 | 11822 | coproc = 1; |
df58fc94 | 11823 | goto ld_st; |
252b5132 | 11824 | case M_SWC3_AB: |
df58fc94 | 11825 | gas_assert (!mips_opts.micromips); |
252b5132 | 11826 | s = "swc3"; |
df58fc94 | 11827 | fmt = "E,o(b)"; |
bdaaa2e1 | 11828 | /* Itbl support may require additional care here. */ |
252b5132 | 11829 | coproc = 1; |
df58fc94 | 11830 | goto ld_st; |
252b5132 RH |
11831 | case M_SWL_AB: |
11832 | s = "swl"; | |
df58fc94 | 11833 | fmt = MEM12_FMT; |
7f3c4072 | 11834 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11835 | goto ld_st; |
252b5132 RH |
11836 | case M_SWR_AB: |
11837 | s = "swr"; | |
df58fc94 | 11838 | fmt = MEM12_FMT; |
7f3c4072 | 11839 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11840 | goto ld_st; |
252b5132 RH |
11841 | case M_SC_AB: |
11842 | s = "sc"; | |
7361da2c AB |
11843 | fmt = LL_SC_FMT; |
11844 | offbits = (mips_opts.micromips ? 12 | |
11845 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11846 | : 16); | |
df58fc94 | 11847 | goto ld_st; |
252b5132 RH |
11848 | case M_SCD_AB: |
11849 | s = "scd"; | |
7361da2c AB |
11850 | fmt = LL_SC_FMT; |
11851 | offbits = (mips_opts.micromips ? 12 | |
11852 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11853 | : 16); | |
df58fc94 | 11854 | goto ld_st; |
d43b4baf TS |
11855 | case M_CACHE_AB: |
11856 | s = "cache"; | |
7361da2c AB |
11857 | fmt = (mips_opts.micromips ? "k,~(b)" |
11858 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11859 | : "k,o(b)"); | |
11860 | offbits = (mips_opts.micromips ? 12 | |
11861 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11862 | : 16); | |
7f3c4072 CM |
11863 | goto ld_st; |
11864 | case M_CACHEE_AB: | |
7f3c4072 CM |
11865 | s = "cachee"; |
11866 | fmt = "k,+j(b)"; | |
11867 | offbits = 9; | |
df58fc94 | 11868 | goto ld_st; |
3eebd5eb MR |
11869 | case M_PREF_AB: |
11870 | s = "pref"; | |
7361da2c AB |
11871 | fmt = (mips_opts.micromips ? "k,~(b)" |
11872 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11873 | : "k,o(b)"); | |
11874 | offbits = (mips_opts.micromips ? 12 | |
11875 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11876 | : 16); | |
7f3c4072 CM |
11877 | goto ld_st; |
11878 | case M_PREFE_AB: | |
7f3c4072 CM |
11879 | s = "prefe"; |
11880 | fmt = "k,+j(b)"; | |
11881 | offbits = 9; | |
df58fc94 | 11882 | goto ld_st; |
252b5132 | 11883 | case M_SDC1_AB: |
252b5132 | 11884 | s = "sdc1"; |
df58fc94 | 11885 | fmt = "T,o(b)"; |
252b5132 | 11886 | coproc = 1; |
bdaaa2e1 | 11887 | /* Itbl support may require additional care here. */ |
df58fc94 | 11888 | goto ld_st; |
252b5132 RH |
11889 | case M_SDC2_AB: |
11890 | s = "sdc2"; | |
df58fc94 | 11891 | fmt = COP12_FMT; |
7361da2c AB |
11892 | offbits = (mips_opts.micromips ? 12 |
11893 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11894 | : 16); | |
c77c0862 RS |
11895 | /* Itbl support may require additional care here. */ |
11896 | coproc = 1; | |
11897 | goto ld_st; | |
11898 | case M_SQC2_AB: | |
c77c0862 | 11899 | s = "sqc2"; |
14daeee3 | 11900 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11901 | /* Itbl support may require additional care here. */ |
252b5132 | 11902 | coproc = 1; |
df58fc94 | 11903 | goto ld_st; |
252b5132 | 11904 | case M_SDC3_AB: |
df58fc94 | 11905 | gas_assert (!mips_opts.micromips); |
252b5132 | 11906 | s = "sdc3"; |
df58fc94 | 11907 | fmt = "E,o(b)"; |
bdaaa2e1 | 11908 | /* Itbl support may require additional care here. */ |
252b5132 | 11909 | coproc = 1; |
df58fc94 | 11910 | goto ld_st; |
252b5132 RH |
11911 | case M_SDL_AB: |
11912 | s = "sdl"; | |
df58fc94 | 11913 | fmt = MEM12_FMT; |
7f3c4072 | 11914 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11915 | goto ld_st; |
252b5132 RH |
11916 | case M_SDR_AB: |
11917 | s = "sdr"; | |
df58fc94 | 11918 | fmt = MEM12_FMT; |
7f3c4072 | 11919 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11920 | goto ld_st; |
11921 | case M_SWP_AB: | |
df58fc94 RS |
11922 | gas_assert (mips_opts.micromips); |
11923 | s = "swp"; | |
11924 | fmt = "t,~(b)"; | |
7f3c4072 | 11925 | offbits = 12; |
df58fc94 RS |
11926 | goto ld_st; |
11927 | case M_SDP_AB: | |
df58fc94 RS |
11928 | gas_assert (mips_opts.micromips); |
11929 | s = "sdp"; | |
11930 | fmt = "t,~(b)"; | |
7f3c4072 | 11931 | offbits = 12; |
df58fc94 RS |
11932 | goto ld_st; |
11933 | case M_SWM_AB: | |
df58fc94 RS |
11934 | gas_assert (mips_opts.micromips); |
11935 | s = "swm"; | |
11936 | fmt = "n,~(b)"; | |
7f3c4072 | 11937 | offbits = 12; |
df58fc94 RS |
11938 | goto ld_st; |
11939 | case M_SDM_AB: | |
df58fc94 RS |
11940 | gas_assert (mips_opts.micromips); |
11941 | s = "sdm"; | |
11942 | fmt = "n,~(b)"; | |
7f3c4072 | 11943 | offbits = 12; |
df58fc94 RS |
11944 | |
11945 | ld_st: | |
8fc2e39e | 11946 | tempreg = AT; |
df58fc94 | 11947 | ld_noat: |
c0ebe874 | 11948 | breg = op[2]; |
f2ae14a1 RS |
11949 | if (small_offset_p (0, align, 16)) |
11950 | { | |
11951 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11952 | macros for o32 but which should act like normal instructions | |
11953 | otherwise. */ | |
11954 | if (offbits == 16) | |
c0ebe874 | 11955 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11956 | offset_reloc[1], offset_reloc[2], breg); |
11957 | else if (small_offset_p (0, align, offbits)) | |
11958 | { | |
11959 | if (offbits == 0) | |
c0ebe874 | 11960 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11961 | else |
c0ebe874 | 11962 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11963 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11964 | } |
11965 | else | |
11966 | { | |
11967 | if (tempreg == AT) | |
11968 | used_at = 1; | |
11969 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11970 | tempreg, breg, -1, offset_reloc[0], | |
11971 | offset_reloc[1], offset_reloc[2]); | |
11972 | if (offbits == 0) | |
c0ebe874 | 11973 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11974 | else |
c0ebe874 | 11975 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11976 | } |
11977 | break; | |
11978 | } | |
11979 | ||
11980 | if (tempreg == AT) | |
11981 | used_at = 1; | |
11982 | ||
252b5132 RH |
11983 | if (offset_expr.X_op != O_constant |
11984 | && offset_expr.X_op != O_symbol) | |
11985 | { | |
1661c76c | 11986 | as_bad (_("expression too complex")); |
252b5132 RH |
11987 | offset_expr.X_op = O_constant; |
11988 | } | |
11989 | ||
2051e8c4 MR |
11990 | if (HAVE_32BIT_ADDRESSES |
11991 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11992 | { |
11993 | char value [32]; | |
11994 | ||
11995 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11996 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11997 | } |
2051e8c4 | 11998 | |
252b5132 RH |
11999 | /* A constant expression in PIC code can be handled just as it |
12000 | is in non PIC code. */ | |
aed1a261 RS |
12001 | if (offset_expr.X_op == O_constant) |
12002 | { | |
f2ae14a1 RS |
12003 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12004 | offbits == 0 ? 16 : offbits); | |
12005 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12006 | |
f2ae14a1 RS |
12007 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12008 | if (breg != 0) | |
12009 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12010 | tempreg, tempreg, breg); | |
7f3c4072 | 12011 | if (offbits == 0) |
dd6a37e7 | 12012 | { |
f2ae14a1 | 12013 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12014 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12015 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 12016 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12017 | } |
7f3c4072 | 12018 | else if (offbits == 16) |
c0ebe874 | 12019 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12020 | else |
c0ebe874 | 12021 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12022 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12023 | } |
7f3c4072 | 12024 | else if (offbits != 16) |
df58fc94 | 12025 | { |
7f3c4072 | 12026 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12027 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12028 | register. */ |
12029 | load_address (tempreg, &offset_expr, &used_at); | |
12030 | if (breg != 0) | |
12031 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12032 | tempreg, tempreg, breg); | |
7f3c4072 | 12033 | if (offbits == 0) |
c0ebe874 | 12034 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12035 | else |
c0ebe874 | 12036 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12037 | } |
12038 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12039 | { |
12040 | /* If this is a reference to a GP relative symbol, and there | |
12041 | is no base register, we want | |
c0ebe874 | 12042 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12043 | Otherwise, if there is no base register, we want |
12044 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12045 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12046 | If we have a constant, we need two instructions anyhow, |
12047 | so we always use the latter form. | |
12048 | ||
12049 | If we have a base register, and this is a reference to a | |
12050 | GP relative symbol, we want | |
12051 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12052 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12053 | Otherwise we want |
12054 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12055 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12056 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12057 | With a constant we always use the latter case. |
76b3015f | 12058 | |
d6bc6245 TS |
12059 | With 64bit address space and no base register and $at usable, |
12060 | we want | |
12061 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12062 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12063 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12064 | dsll32 $tempreg,0 | |
12065 | daddu $tempreg,$at | |
c0ebe874 | 12066 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12067 | If we have a base register, we want |
12068 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12069 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12070 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12071 | daddu $at,$breg | |
12072 | dsll32 $tempreg,0 | |
12073 | daddu $tempreg,$at | |
c0ebe874 | 12074 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12075 | |
12076 | Without $at we can't generate the optimal path for superscalar | |
12077 | processors here since this would require two temporary registers. | |
12078 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12079 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12080 | dsll $tempreg,16 | |
12081 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12082 | dsll $tempreg,16 | |
c0ebe874 | 12083 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12084 | If we have a base register, we want |
12085 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12086 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12087 | dsll $tempreg,16 | |
12088 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12089 | dsll $tempreg,16 | |
12090 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12091 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12092 | |
6caf9ef4 | 12093 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12094 | the same sequence as in 32bit address space. */ |
12095 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12096 | { |
aed1a261 | 12097 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12098 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12099 | { | |
12100 | relax_start (offset_expr.X_add_symbol); | |
12101 | if (breg == 0) | |
12102 | { | |
c0ebe874 | 12103 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12104 | BFD_RELOC_GPREL16, mips_gp_register); |
12105 | } | |
12106 | else | |
12107 | { | |
12108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12109 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12110 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12111 | BFD_RELOC_GPREL16, tempreg); |
12112 | } | |
12113 | relax_switch (); | |
12114 | } | |
d6bc6245 | 12115 | |
741fe287 | 12116 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12117 | { |
df58fc94 | 12118 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12119 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12120 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12121 | BFD_RELOC_HI16_S); |
12122 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12123 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12124 | if (breg != 0) |
67c0d1eb | 12125 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12126 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12127 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12128 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12129 | tempreg); |
d6bc6245 TS |
12130 | used_at = 1; |
12131 | } | |
12132 | else | |
12133 | { | |
df58fc94 | 12134 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12135 | BFD_RELOC_MIPS_HIGHEST); |
12136 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12137 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12138 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12139 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12140 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12141 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12142 | if (breg != 0) |
67c0d1eb | 12143 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12144 | tempreg, tempreg, breg); |
c0ebe874 | 12145 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12146 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12147 | } |
6caf9ef4 TS |
12148 | |
12149 | if (mips_relax.sequence) | |
12150 | relax_end (); | |
8fc2e39e | 12151 | break; |
d6bc6245 | 12152 | } |
256ab948 | 12153 | |
252b5132 RH |
12154 | if (breg == 0) |
12155 | { | |
67c0d1eb | 12156 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12157 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12158 | { |
4d7206a2 | 12159 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12160 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12161 | mips_gp_register); |
4d7206a2 | 12162 | relax_switch (); |
252b5132 | 12163 | } |
67c0d1eb | 12164 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12165 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12166 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12167 | if (mips_relax.sequence) |
12168 | relax_end (); | |
252b5132 RH |
12169 | } |
12170 | else | |
12171 | { | |
67c0d1eb | 12172 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12173 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12174 | { |
4d7206a2 | 12175 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12176 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12177 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12178 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12179 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12180 | relax_switch (); |
252b5132 | 12181 | } |
67c0d1eb RS |
12182 | macro_build_lui (&offset_expr, tempreg); |
12183 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12184 | tempreg, tempreg, breg); |
c0ebe874 | 12185 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12186 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12187 | if (mips_relax.sequence) |
12188 | relax_end (); | |
252b5132 RH |
12189 | } |
12190 | } | |
0a44bf69 | 12191 | else if (!mips_big_got) |
252b5132 | 12192 | { |
ed6fb7bd | 12193 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12194 | |
252b5132 RH |
12195 | /* If this is a reference to an external symbol, we want |
12196 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12197 | nop | |
c0ebe874 | 12198 | <op> op[0],0($tempreg) |
252b5132 RH |
12199 | Otherwise we want |
12200 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12201 | nop | |
12202 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12203 | <op> op[0],0($tempreg) |
f5040a92 AO |
12204 | |
12205 | For NewABI, we want | |
12206 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12207 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12208 | |
252b5132 RH |
12209 | If there is a base register, we add it to $tempreg before |
12210 | the <op>. If there is a constant, we stick it in the | |
12211 | <op> instruction. We don't handle constants larger than | |
12212 | 16 bits, because we have no way to load the upper 16 bits | |
12213 | (actually, we could handle them for the subset of cases | |
12214 | in which we are not using $at). */ | |
9c2799c2 | 12215 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12216 | if (HAVE_NEWABI) |
12217 | { | |
67c0d1eb RS |
12218 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12219 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12220 | if (breg != 0) |
67c0d1eb | 12221 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12222 | tempreg, tempreg, breg); |
c0ebe874 | 12223 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12224 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12225 | break; |
12226 | } | |
252b5132 RH |
12227 | expr1.X_add_number = offset_expr.X_add_number; |
12228 | offset_expr.X_add_number = 0; | |
12229 | if (expr1.X_add_number < -0x8000 | |
12230 | || expr1.X_add_number >= 0x8000) | |
12231 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12233 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12234 | load_delay_nop (); |
4d7206a2 RS |
12235 | relax_start (offset_expr.X_add_symbol); |
12236 | relax_switch (); | |
67c0d1eb RS |
12237 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12238 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12239 | relax_end (); |
252b5132 | 12240 | if (breg != 0) |
67c0d1eb | 12241 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12242 | tempreg, tempreg, breg); |
c0ebe874 | 12243 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12244 | } |
0a44bf69 | 12245 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12246 | { |
67c0d1eb | 12247 | int gpdelay; |
252b5132 RH |
12248 | |
12249 | /* If this is a reference to an external symbol, we want | |
12250 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12251 | addu $tempreg,$tempreg,$gp | |
12252 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12253 | <op> op[0],0($tempreg) |
252b5132 RH |
12254 | Otherwise we want |
12255 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12256 | nop | |
12257 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12258 | <op> op[0],0($tempreg) |
252b5132 RH |
12259 | If there is a base register, we add it to $tempreg before |
12260 | the <op>. If there is a constant, we stick it in the | |
12261 | <op> instruction. We don't handle constants larger than | |
12262 | 16 bits, because we have no way to load the upper 16 bits | |
12263 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12264 | in which we are not using $at). */ |
9c2799c2 | 12265 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12266 | expr1.X_add_number = offset_expr.X_add_number; |
12267 | offset_expr.X_add_number = 0; | |
12268 | if (expr1.X_add_number < -0x8000 | |
12269 | || expr1.X_add_number >= 0x8000) | |
12270 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12271 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12272 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12273 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12274 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12275 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12276 | mips_gp_register); | |
12277 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12278 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12279 | relax_switch (); |
67c0d1eb RS |
12280 | if (gpdelay) |
12281 | macro_build (NULL, "nop", ""); | |
12282 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12283 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12284 | load_delay_nop (); |
67c0d1eb RS |
12285 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12286 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12287 | relax_end (); |
12288 | ||
252b5132 | 12289 | if (breg != 0) |
67c0d1eb | 12290 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12291 | tempreg, tempreg, breg); |
c0ebe874 | 12292 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12293 | } |
0a44bf69 | 12294 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12295 | { |
f5040a92 AO |
12296 | /* If this is a reference to an external symbol, we want |
12297 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12298 | add $tempreg,$tempreg,$gp | |
12299 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12300 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12301 | Otherwise, for local symbols, we want: |
12302 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12303 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12304 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12305 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12306 | offset_expr.X_add_number = 0; |
12307 | if (expr1.X_add_number < -0x8000 | |
12308 | || expr1.X_add_number >= 0x8000) | |
12309 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12310 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12311 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12312 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12313 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12314 | mips_gp_register); | |
12315 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12316 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12317 | if (breg != 0) |
67c0d1eb | 12318 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12319 | tempreg, tempreg, breg); |
c0ebe874 | 12320 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12321 | |
4d7206a2 | 12322 | relax_switch (); |
f5040a92 | 12323 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12324 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12325 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12326 | if (breg != 0) |
67c0d1eb | 12327 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12328 | tempreg, tempreg, breg); |
c0ebe874 | 12329 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12330 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12331 | relax_end (); |
f5040a92 | 12332 | } |
252b5132 RH |
12333 | else |
12334 | abort (); | |
12335 | ||
252b5132 RH |
12336 | break; |
12337 | ||
833794fc MR |
12338 | case M_JRADDIUSP: |
12339 | gas_assert (mips_opts.micromips); | |
12340 | gas_assert (mips_opts.insn32); | |
12341 | start_noreorder (); | |
12342 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12343 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12344 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12345 | end_noreorder (); | |
12346 | break; | |
12347 | ||
12348 | case M_JRC: | |
12349 | gas_assert (mips_opts.micromips); | |
12350 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12351 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12352 | if (mips_opts.noreorder) |
12353 | macro_build (NULL, "nop", ""); | |
12354 | break; | |
12355 | ||
252b5132 RH |
12356 | case M_LI: |
12357 | case M_LI_S: | |
c0ebe874 | 12358 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12359 | break; |
252b5132 RH |
12360 | |
12361 | case M_DLI: | |
c0ebe874 | 12362 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12363 | break; |
252b5132 RH |
12364 | |
12365 | case M_LI_SS: | |
12366 | if (imm_expr.X_op == O_constant) | |
12367 | { | |
8fc2e39e | 12368 | used_at = 1; |
67c0d1eb | 12369 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12370 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12371 | break; |
12372 | } | |
12373 | else | |
12374 | { | |
b0e6f033 RS |
12375 | gas_assert (imm_expr.X_op == O_absent |
12376 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12377 | && strcmp (segment_name (S_GET_SEGMENT |
12378 | (offset_expr.X_add_symbol)), | |
12379 | ".lit4") == 0 | |
12380 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12381 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12382 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12383 | break; |
252b5132 RH |
12384 | } |
12385 | ||
12386 | case M_LI_D: | |
ca4e0257 RS |
12387 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12388 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12389 | order 32 bits of the value and the low order 32 bits are either | |
12390 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12391 | if (imm_expr.X_op == O_constant) |
252b5132 | 12392 | { |
bad1aba3 | 12393 | if (GPR_SIZE == 64) |
c0ebe874 | 12394 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12395 | else |
12396 | { | |
12397 | int hreg, lreg; | |
12398 | ||
12399 | if (target_big_endian) | |
12400 | { | |
c0ebe874 RS |
12401 | hreg = op[0]; |
12402 | lreg = op[0] + 1; | |
252b5132 RH |
12403 | } |
12404 | else | |
12405 | { | |
c0ebe874 RS |
12406 | hreg = op[0] + 1; |
12407 | lreg = op[0]; | |
252b5132 RH |
12408 | } |
12409 | ||
12410 | if (hreg <= 31) | |
67c0d1eb | 12411 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12412 | if (lreg <= 31) |
12413 | { | |
12414 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12415 | move_register (lreg, 0); |
252b5132 RH |
12416 | else |
12417 | { | |
9c2799c2 | 12418 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12419 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12420 | } |
12421 | } | |
12422 | } | |
8fc2e39e | 12423 | break; |
252b5132 | 12424 | } |
b0e6f033 | 12425 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12426 | |
12427 | /* We know that sym is in the .rdata section. First we get the | |
12428 | upper 16 bits of the address. */ | |
12429 | if (mips_pic == NO_PIC) | |
12430 | { | |
67c0d1eb | 12431 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12432 | used_at = 1; |
252b5132 | 12433 | } |
0a44bf69 | 12434 | else |
252b5132 | 12435 | { |
67c0d1eb RS |
12436 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12437 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12438 | used_at = 1; |
252b5132 | 12439 | } |
bdaaa2e1 | 12440 | |
252b5132 | 12441 | /* Now we load the register(s). */ |
bad1aba3 | 12442 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12443 | { |
12444 | used_at = 1; | |
c0ebe874 RS |
12445 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12446 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12447 | } |
252b5132 RH |
12448 | else |
12449 | { | |
8fc2e39e | 12450 | used_at = 1; |
c0ebe874 RS |
12451 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12452 | BFD_RELOC_LO16, AT); | |
12453 | if (op[0] != RA) | |
252b5132 RH |
12454 | { |
12455 | /* FIXME: How in the world do we deal with the possible | |
12456 | overflow here? */ | |
12457 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12458 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12459 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12460 | } |
12461 | } | |
252b5132 RH |
12462 | break; |
12463 | ||
12464 | case M_LI_DD: | |
ca4e0257 RS |
12465 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12466 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12467 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12468 | the value and the low order 32 bits are either zero or in | |
12469 | OFFSET_EXPR. */ | |
b0e6f033 | 12470 | if (imm_expr.X_op == O_constant) |
252b5132 | 12471 | { |
8fc2e39e | 12472 | used_at = 1; |
bad1aba3 | 12473 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12474 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12475 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12476 | else |
12477 | { | |
351cdf24 MF |
12478 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12479 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12480 | else if (FPR_SIZE != 32) | |
12481 | as_bad (_("Unable to generate `%s' compliant code " | |
12482 | "without mthc1"), | |
12483 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12484 | else | |
12485 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12486 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12487 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12488 | else |
12489 | { | |
9c2799c2 | 12490 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12491 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12492 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12493 | } |
12494 | } | |
12495 | break; | |
12496 | } | |
12497 | ||
b0e6f033 RS |
12498 | gas_assert (imm_expr.X_op == O_absent |
12499 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12500 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12501 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12502 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12503 | { |
12504 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12505 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12506 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12507 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12508 | } |
12509 | else | |
12510 | { | |
9c2799c2 | 12511 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12512 | used_at = 1; |
0a44bf69 | 12513 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12514 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12515 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12516 | else |
12517 | { | |
12518 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12519 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12520 | } |
bdaaa2e1 | 12521 | |
c0ebe874 | 12522 | op[2] = AT; |
f2ae14a1 RS |
12523 | offset_reloc[0] = BFD_RELOC_LO16; |
12524 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12525 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12526 | } |
f2ae14a1 RS |
12527 | align = 8; |
12528 | /* Fall through */ | |
c4a68bea | 12529 | |
252b5132 RH |
12530 | case M_L_DAB: |
12531 | /* | |
12532 | * The MIPS assembler seems to check for X_add_number not | |
12533 | * being double aligned and generating: | |
12534 | * lui at,%hi(foo+1) | |
12535 | * addu at,at,v1 | |
12536 | * addiu at,at,%lo(foo+1) | |
12537 | * lwc1 f2,0(at) | |
12538 | * lwc1 f3,4(at) | |
12539 | * But, the resulting address is the same after relocation so why | |
12540 | * generate the extra instruction? | |
12541 | */ | |
bdaaa2e1 | 12542 | /* Itbl support may require additional care here. */ |
252b5132 | 12543 | coproc = 1; |
df58fc94 | 12544 | fmt = "T,o(b)"; |
0aa27725 | 12545 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12546 | { |
12547 | s = "ldc1"; | |
df58fc94 | 12548 | goto ld_st; |
252b5132 | 12549 | } |
252b5132 | 12550 | s = "lwc1"; |
252b5132 RH |
12551 | goto ldd_std; |
12552 | ||
12553 | case M_S_DAB: | |
df58fc94 RS |
12554 | gas_assert (!mips_opts.micromips); |
12555 | /* Itbl support may require additional care here. */ | |
12556 | coproc = 1; | |
12557 | fmt = "T,o(b)"; | |
0aa27725 | 12558 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12559 | { |
12560 | s = "sdc1"; | |
df58fc94 | 12561 | goto ld_st; |
252b5132 | 12562 | } |
252b5132 | 12563 | s = "swc1"; |
252b5132 RH |
12564 | goto ldd_std; |
12565 | ||
e407c74b NC |
12566 | case M_LQ_AB: |
12567 | fmt = "t,o(b)"; | |
12568 | s = "lq"; | |
12569 | goto ld; | |
12570 | ||
12571 | case M_SQ_AB: | |
12572 | fmt = "t,o(b)"; | |
12573 | s = "sq"; | |
12574 | goto ld_st; | |
12575 | ||
252b5132 | 12576 | case M_LD_AB: |
df58fc94 | 12577 | fmt = "t,o(b)"; |
bad1aba3 | 12578 | if (GPR_SIZE == 64) |
252b5132 RH |
12579 | { |
12580 | s = "ld"; | |
12581 | goto ld; | |
12582 | } | |
252b5132 | 12583 | s = "lw"; |
252b5132 RH |
12584 | goto ldd_std; |
12585 | ||
12586 | case M_SD_AB: | |
df58fc94 | 12587 | fmt = "t,o(b)"; |
bad1aba3 | 12588 | if (GPR_SIZE == 64) |
252b5132 RH |
12589 | { |
12590 | s = "sd"; | |
df58fc94 | 12591 | goto ld_st; |
252b5132 | 12592 | } |
252b5132 | 12593 | s = "sw"; |
252b5132 RH |
12594 | |
12595 | ldd_std: | |
f2ae14a1 RS |
12596 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12597 | to adjust when loading from memory. We set coproc if we must | |
12598 | load $fn+1 first. */ | |
12599 | /* Itbl support may require additional care here. */ | |
12600 | if (!target_big_endian) | |
12601 | coproc = 0; | |
12602 | ||
c0ebe874 | 12603 | breg = op[2]; |
f2ae14a1 RS |
12604 | if (small_offset_p (0, align, 16)) |
12605 | { | |
12606 | ep = &offset_expr; | |
12607 | if (!small_offset_p (4, align, 16)) | |
12608 | { | |
12609 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12610 | -1, offset_reloc[0], offset_reloc[1], | |
12611 | offset_reloc[2]); | |
12612 | expr1.X_add_number = 0; | |
12613 | ep = &expr1; | |
12614 | breg = AT; | |
12615 | used_at = 1; | |
12616 | offset_reloc[0] = BFD_RELOC_LO16; | |
12617 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12618 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12619 | } | |
c0ebe874 | 12620 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12621 | { |
12622 | ep->X_add_number += 4; | |
c0ebe874 | 12623 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12624 | offset_reloc[1], offset_reloc[2], breg); |
12625 | ep->X_add_number -= 4; | |
c0ebe874 | 12626 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12627 | offset_reloc[1], offset_reloc[2], breg); |
12628 | } | |
12629 | else | |
12630 | { | |
c0ebe874 | 12631 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12632 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12633 | breg); | |
12634 | ep->X_add_number += 4; | |
c0ebe874 | 12635 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12636 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12637 | breg); | |
12638 | } | |
12639 | break; | |
12640 | } | |
12641 | ||
252b5132 RH |
12642 | if (offset_expr.X_op != O_symbol |
12643 | && offset_expr.X_op != O_constant) | |
12644 | { | |
1661c76c | 12645 | as_bad (_("expression too complex")); |
252b5132 RH |
12646 | offset_expr.X_op = O_constant; |
12647 | } | |
12648 | ||
2051e8c4 MR |
12649 | if (HAVE_32BIT_ADDRESSES |
12650 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12651 | { |
12652 | char value [32]; | |
12653 | ||
12654 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12655 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12656 | } |
2051e8c4 | 12657 | |
90ecf173 | 12658 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12659 | { |
12660 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12661 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12662 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12663 | If we have a base register, we use this |
12664 | addu $at,$breg,$gp | |
c0ebe874 RS |
12665 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12666 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12667 | If this is not a GP relative symbol, we want |
12668 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12669 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12670 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12671 | If there is a base register, we add it to $at after the |
12672 | lui instruction. If there is a constant, we always use | |
12673 | the last case. */ | |
39a59cf8 MR |
12674 | if (offset_expr.X_op == O_symbol |
12675 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12676 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12677 | { |
4d7206a2 | 12678 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12679 | if (breg == 0) |
12680 | { | |
c9914766 | 12681 | tempreg = mips_gp_register; |
252b5132 RH |
12682 | } |
12683 | else | |
12684 | { | |
67c0d1eb | 12685 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12686 | AT, breg, mips_gp_register); |
252b5132 | 12687 | tempreg = AT; |
252b5132 RH |
12688 | used_at = 1; |
12689 | } | |
12690 | ||
beae10d5 | 12691 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12692 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12693 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12694 | offset_expr.X_add_number += 4; |
12695 | ||
12696 | /* Set mips_optimize to 2 to avoid inserting an | |
12697 | undesired nop. */ | |
12698 | hold_mips_optimize = mips_optimize; | |
12699 | mips_optimize = 2; | |
beae10d5 | 12700 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12701 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12702 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12703 | mips_optimize = hold_mips_optimize; |
12704 | ||
4d7206a2 | 12705 | relax_switch (); |
252b5132 | 12706 | |
0970e49e | 12707 | offset_expr.X_add_number -= 4; |
252b5132 | 12708 | } |
8fc2e39e | 12709 | used_at = 1; |
f2ae14a1 RS |
12710 | if (offset_high_part (offset_expr.X_add_number, 16) |
12711 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12712 | { | |
12713 | load_address (AT, &offset_expr, &used_at); | |
12714 | offset_expr.X_op = O_constant; | |
12715 | offset_expr.X_add_number = 0; | |
12716 | } | |
12717 | else | |
12718 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12719 | if (breg != 0) |
67c0d1eb | 12720 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12721 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12722 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12723 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12724 | /* FIXME: How do we handle overflow here? */ |
12725 | offset_expr.X_add_number += 4; | |
beae10d5 | 12726 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12727 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12728 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12729 | if (mips_relax.sequence) |
12730 | relax_end (); | |
bdaaa2e1 | 12731 | } |
0a44bf69 | 12732 | else if (!mips_big_got) |
252b5132 | 12733 | { |
252b5132 RH |
12734 | /* If this is a reference to an external symbol, we want |
12735 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12736 | nop | |
c0ebe874 RS |
12737 | <op> op[0],0($at) |
12738 | <op> op[0]+1,4($at) | |
252b5132 RH |
12739 | Otherwise we want |
12740 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12741 | nop | |
c0ebe874 RS |
12742 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12743 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12744 | If there is a base register we add it to $at before the |
12745 | lwc1 instructions. If there is a constant we include it | |
12746 | in the lwc1 instructions. */ | |
12747 | used_at = 1; | |
12748 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12749 | if (expr1.X_add_number < -0x8000 |
12750 | || expr1.X_add_number >= 0x8000 - 4) | |
12751 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12752 | load_got_offset (AT, &offset_expr); |
269137b2 | 12753 | load_delay_nop (); |
252b5132 | 12754 | if (breg != 0) |
67c0d1eb | 12755 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12756 | |
12757 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12758 | nop. */ | |
12759 | hold_mips_optimize = mips_optimize; | |
12760 | mips_optimize = 2; | |
4d7206a2 | 12761 | |
beae10d5 | 12762 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12763 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12764 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12765 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12766 | expr1.X_add_number += 4; |
c0ebe874 | 12767 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12768 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12769 | relax_switch (); |
c0ebe874 | 12770 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12771 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12772 | offset_expr.X_add_number += 4; |
c0ebe874 | 12773 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12774 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12775 | relax_end (); |
252b5132 | 12776 | |
4d7206a2 | 12777 | mips_optimize = hold_mips_optimize; |
252b5132 | 12778 | } |
0a44bf69 | 12779 | else if (mips_big_got) |
252b5132 | 12780 | { |
67c0d1eb | 12781 | int gpdelay; |
252b5132 RH |
12782 | |
12783 | /* If this is a reference to an external symbol, we want | |
12784 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12785 | addu $at,$at,$gp | |
12786 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12787 | nop | |
c0ebe874 RS |
12788 | <op> op[0],0($at) |
12789 | <op> op[0]+1,4($at) | |
252b5132 RH |
12790 | Otherwise we want |
12791 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12792 | nop | |
c0ebe874 RS |
12793 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12794 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12795 | If there is a base register we add it to $at before the |
12796 | lwc1 instructions. If there is a constant we include it | |
12797 | in the lwc1 instructions. */ | |
12798 | used_at = 1; | |
12799 | expr1.X_add_number = offset_expr.X_add_number; | |
12800 | offset_expr.X_add_number = 0; | |
12801 | if (expr1.X_add_number < -0x8000 | |
12802 | || expr1.X_add_number >= 0x8000 - 4) | |
12803 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12804 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12805 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12806 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12807 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12808 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12809 | AT, AT, mips_gp_register); |
67c0d1eb | 12810 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12811 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12812 | load_delay_nop (); |
252b5132 | 12813 | if (breg != 0) |
67c0d1eb | 12814 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12815 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12816 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12817 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12818 | expr1.X_add_number += 4; |
12819 | ||
12820 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12821 | nop. */ | |
12822 | hold_mips_optimize = mips_optimize; | |
12823 | mips_optimize = 2; | |
beae10d5 | 12824 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12825 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12826 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12827 | mips_optimize = hold_mips_optimize; |
12828 | expr1.X_add_number -= 4; | |
12829 | ||
4d7206a2 RS |
12830 | relax_switch (); |
12831 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12832 | if (gpdelay) |
12833 | macro_build (NULL, "nop", ""); | |
12834 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12835 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12836 | load_delay_nop (); |
252b5132 | 12837 | if (breg != 0) |
67c0d1eb | 12838 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12839 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12840 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12841 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12842 | offset_expr.X_add_number += 4; |
252b5132 RH |
12843 | |
12844 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12845 | nop. */ | |
12846 | hold_mips_optimize = mips_optimize; | |
12847 | mips_optimize = 2; | |
beae10d5 | 12848 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12849 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12850 | BFD_RELOC_LO16, AT); |
252b5132 | 12851 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12852 | relax_end (); |
252b5132 | 12853 | } |
252b5132 RH |
12854 | else |
12855 | abort (); | |
12856 | ||
252b5132 | 12857 | break; |
3739860c | 12858 | |
dd6a37e7 | 12859 | case M_SAA_AB: |
dd6a37e7 | 12860 | s = "saa"; |
0db377d0 | 12861 | goto saa_saad; |
dd6a37e7 | 12862 | case M_SAAD_AB: |
dd6a37e7 | 12863 | s = "saad"; |
0db377d0 MR |
12864 | saa_saad: |
12865 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12866 | offbits = 0; |
dd6a37e7 AP |
12867 | fmt = "t,(b)"; |
12868 | goto ld_st; | |
12869 | ||
252b5132 RH |
12870 | /* New code added to support COPZ instructions. |
12871 | This code builds table entries out of the macros in mip_opcodes. | |
12872 | R4000 uses interlocks to handle coproc delays. | |
12873 | Other chips (like the R3000) require nops to be inserted for delays. | |
12874 | ||
f72c8c98 | 12875 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12876 | In order to fill delay slots for non-interlocked chips, |
12877 | we must have a way to specify delays based on the coprocessor. | |
12878 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12879 | What are the side-effects of the cop instruction? | |
12880 | What cache support might we have and what are its effects? | |
12881 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12882 | What registers are read/set/modified? |
252b5132 RH |
12883 | |
12884 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12885 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12886 | |
12887 | case M_COP0: | |
12888 | s = "c0"; | |
12889 | goto copz; | |
12890 | case M_COP1: | |
12891 | s = "c1"; | |
12892 | goto copz; | |
12893 | case M_COP2: | |
12894 | s = "c2"; | |
12895 | goto copz; | |
12896 | case M_COP3: | |
12897 | s = "c3"; | |
12898 | copz: | |
df58fc94 | 12899 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12900 | /* For now we just do C (same as Cz). The parameter will be |
12901 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12902 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12903 | break; |
252b5132 | 12904 | |
ea1fb5dc | 12905 | case M_MOVE: |
c0ebe874 | 12906 | move_register (op[0], op[1]); |
8fc2e39e | 12907 | break; |
ea1fb5dc | 12908 | |
833794fc MR |
12909 | case M_MOVEP: |
12910 | gas_assert (mips_opts.micromips); | |
12911 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12912 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12913 | micromips_to_32_reg_m_map[op[1]]); | |
12914 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12915 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12916 | break; |
12917 | ||
252b5132 RH |
12918 | case M_DMUL: |
12919 | dbl = 1; | |
1a0670f3 | 12920 | /* Fall through. */ |
252b5132 | 12921 | case M_MUL: |
e407c74b | 12922 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12923 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12924 | op[2]); | |
e407c74b NC |
12925 | else |
12926 | { | |
c0ebe874 RS |
12927 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12928 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12929 | } |
8fc2e39e | 12930 | break; |
252b5132 RH |
12931 | |
12932 | case M_DMUL_I: | |
12933 | dbl = 1; | |
1a0670f3 | 12934 | /* Fall through. */ |
252b5132 RH |
12935 | case M_MUL_I: |
12936 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12937 | not trying to be that fancy. GCC should do this for us | |
12938 | anyway. */ | |
8fc2e39e | 12939 | used_at = 1; |
67c0d1eb | 12940 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12941 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12942 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12943 | break; |
12944 | ||
12945 | case M_DMULO_I: | |
12946 | dbl = 1; | |
1a0670f3 | 12947 | /* Fall through. */ |
252b5132 RH |
12948 | case M_MULO_I: |
12949 | imm = 1; | |
12950 | goto do_mulo; | |
12951 | ||
12952 | case M_DMULO: | |
12953 | dbl = 1; | |
1a0670f3 | 12954 | /* Fall through. */ |
252b5132 RH |
12955 | case M_MULO: |
12956 | do_mulo: | |
7d10b47d | 12957 | start_noreorder (); |
8fc2e39e | 12958 | used_at = 1; |
252b5132 | 12959 | if (imm) |
67c0d1eb | 12960 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12961 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12962 | op[1], imm ? AT : op[2]); | |
12963 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12964 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12965 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12966 | if (mips_trap) |
c0ebe874 | 12967 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12968 | else |
12969 | { | |
df58fc94 RS |
12970 | if (mips_opts.micromips) |
12971 | micromips_label_expr (&label_expr); | |
12972 | else | |
12973 | label_expr.X_add_number = 8; | |
c0ebe874 | 12974 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12975 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12976 | macro_build (NULL, "break", BRK_FMT, 6); |
12977 | if (mips_opts.micromips) | |
12978 | micromips_add_label (); | |
252b5132 | 12979 | } |
7d10b47d | 12980 | end_noreorder (); |
c0ebe874 | 12981 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
12982 | break; |
12983 | ||
12984 | case M_DMULOU_I: | |
12985 | dbl = 1; | |
1a0670f3 | 12986 | /* Fall through. */ |
252b5132 RH |
12987 | case M_MULOU_I: |
12988 | imm = 1; | |
12989 | goto do_mulou; | |
12990 | ||
12991 | case M_DMULOU: | |
12992 | dbl = 1; | |
1a0670f3 | 12993 | /* Fall through. */ |
252b5132 RH |
12994 | case M_MULOU: |
12995 | do_mulou: | |
7d10b47d | 12996 | start_noreorder (); |
8fc2e39e | 12997 | used_at = 1; |
252b5132 | 12998 | if (imm) |
67c0d1eb RS |
12999 | load_register (AT, &imm_expr, dbl); |
13000 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13001 | op[1], imm ? AT : op[2]); |
df58fc94 | 13002 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13003 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13004 | if (mips_trap) |
df58fc94 | 13005 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13006 | else |
13007 | { | |
df58fc94 RS |
13008 | if (mips_opts.micromips) |
13009 | micromips_label_expr (&label_expr); | |
13010 | else | |
13011 | label_expr.X_add_number = 8; | |
13012 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13013 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13014 | macro_build (NULL, "break", BRK_FMT, 6); |
13015 | if (mips_opts.micromips) | |
13016 | micromips_add_label (); | |
252b5132 | 13017 | } |
7d10b47d | 13018 | end_noreorder (); |
252b5132 RH |
13019 | break; |
13020 | ||
771c7ce4 | 13021 | case M_DROL: |
fef14a42 | 13022 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13023 | { |
c0ebe874 | 13024 | if (op[0] == op[1]) |
82dd0097 CD |
13025 | { |
13026 | tempreg = AT; | |
13027 | used_at = 1; | |
13028 | } | |
13029 | else | |
c0ebe874 RS |
13030 | tempreg = op[0]; |
13031 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13032 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13033 | break; |
82dd0097 | 13034 | } |
8fc2e39e | 13035 | used_at = 1; |
c0ebe874 RS |
13036 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13037 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13038 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13039 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13040 | break; |
13041 | ||
252b5132 | 13042 | case M_ROL: |
fef14a42 | 13043 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13044 | { |
c0ebe874 | 13045 | if (op[0] == op[1]) |
82dd0097 CD |
13046 | { |
13047 | tempreg = AT; | |
13048 | used_at = 1; | |
13049 | } | |
13050 | else | |
c0ebe874 RS |
13051 | tempreg = op[0]; |
13052 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13053 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13054 | break; |
82dd0097 | 13055 | } |
8fc2e39e | 13056 | used_at = 1; |
c0ebe874 RS |
13057 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13058 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13059 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13060 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13061 | break; |
13062 | ||
771c7ce4 TS |
13063 | case M_DROL_I: |
13064 | { | |
13065 | unsigned int rot; | |
e0471c16 TS |
13066 | const char *l; |
13067 | const char *rr; | |
771c7ce4 | 13068 | |
771c7ce4 | 13069 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13070 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13071 | { |
13072 | rot = (64 - rot) & 0x3f; | |
13073 | if (rot >= 32) | |
c0ebe874 | 13074 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13075 | else |
c0ebe874 | 13076 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13077 | break; |
60b63b72 | 13078 | } |
483fc7cd | 13079 | if (rot == 0) |
483fc7cd | 13080 | { |
c0ebe874 | 13081 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13082 | break; |
483fc7cd | 13083 | } |
82dd0097 | 13084 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13085 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13086 | rot &= 0x1f; |
8fc2e39e | 13087 | used_at = 1; |
c0ebe874 RS |
13088 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13089 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13090 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13091 | } |
13092 | break; | |
13093 | ||
252b5132 | 13094 | case M_ROL_I: |
771c7ce4 TS |
13095 | { |
13096 | unsigned int rot; | |
13097 | ||
771c7ce4 | 13098 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13099 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13100 | { |
c0ebe874 RS |
13101 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13102 | (32 - rot) & 0x1f); | |
8fc2e39e | 13103 | break; |
60b63b72 | 13104 | } |
483fc7cd | 13105 | if (rot == 0) |
483fc7cd | 13106 | { |
c0ebe874 | 13107 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13108 | break; |
483fc7cd | 13109 | } |
8fc2e39e | 13110 | used_at = 1; |
c0ebe874 RS |
13111 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13112 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13113 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13114 | } |
13115 | break; | |
13116 | ||
13117 | case M_DROR: | |
fef14a42 | 13118 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13119 | { |
c0ebe874 | 13120 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13121 | break; |
82dd0097 | 13122 | } |
8fc2e39e | 13123 | used_at = 1; |
c0ebe874 RS |
13124 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13125 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13126 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13127 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13128 | break; |
13129 | ||
13130 | case M_ROR: | |
fef14a42 | 13131 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13132 | { |
c0ebe874 | 13133 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13134 | break; |
82dd0097 | 13135 | } |
8fc2e39e | 13136 | used_at = 1; |
c0ebe874 RS |
13137 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13138 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13139 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13140 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13141 | break; |
13142 | ||
771c7ce4 TS |
13143 | case M_DROR_I: |
13144 | { | |
13145 | unsigned int rot; | |
e0471c16 TS |
13146 | const char *l; |
13147 | const char *rr; | |
771c7ce4 | 13148 | |
771c7ce4 | 13149 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13150 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13151 | { |
13152 | if (rot >= 32) | |
c0ebe874 | 13153 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13154 | else |
c0ebe874 | 13155 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13156 | break; |
82dd0097 | 13157 | } |
483fc7cd | 13158 | if (rot == 0) |
483fc7cd | 13159 | { |
c0ebe874 | 13160 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13161 | break; |
483fc7cd | 13162 | } |
91d6fa6a | 13163 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13164 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13165 | rot &= 0x1f; | |
8fc2e39e | 13166 | used_at = 1; |
c0ebe874 RS |
13167 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13168 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13169 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13170 | } |
13171 | break; | |
13172 | ||
252b5132 | 13173 | case M_ROR_I: |
771c7ce4 TS |
13174 | { |
13175 | unsigned int rot; | |
13176 | ||
771c7ce4 | 13177 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13178 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13179 | { |
c0ebe874 | 13180 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13181 | break; |
82dd0097 | 13182 | } |
483fc7cd | 13183 | if (rot == 0) |
483fc7cd | 13184 | { |
c0ebe874 | 13185 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13186 | break; |
483fc7cd | 13187 | } |
8fc2e39e | 13188 | used_at = 1; |
c0ebe874 RS |
13189 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13190 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13191 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13192 | } |
252b5132 RH |
13193 | break; |
13194 | ||
252b5132 | 13195 | case M_SEQ: |
c0ebe874 RS |
13196 | if (op[1] == 0) |
13197 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13198 | else if (op[2] == 0) | |
13199 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13200 | else |
13201 | { | |
c0ebe874 RS |
13202 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13203 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13204 | } |
8fc2e39e | 13205 | break; |
252b5132 RH |
13206 | |
13207 | case M_SEQ_I: | |
b0e6f033 | 13208 | if (imm_expr.X_add_number == 0) |
252b5132 | 13209 | { |
c0ebe874 | 13210 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13211 | break; |
252b5132 | 13212 | } |
c0ebe874 | 13213 | if (op[1] == 0) |
252b5132 | 13214 | { |
1661c76c | 13215 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13216 | ip->insn_mo->name); |
c0ebe874 | 13217 | move_register (op[0], 0); |
8fc2e39e | 13218 | break; |
252b5132 | 13219 | } |
dd3cbb7e NC |
13220 | if (CPU_HAS_SEQ (mips_opts.arch) |
13221 | && -512 <= imm_expr.X_add_number | |
13222 | && imm_expr.X_add_number < 512) | |
13223 | { | |
c0ebe874 | 13224 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13225 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13226 | break; |
13227 | } | |
b0e6f033 | 13228 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13229 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13230 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13231 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13232 | && imm_expr.X_add_number < 0) |
13233 | { | |
13234 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13235 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13236 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13237 | } |
dd3cbb7e NC |
13238 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13239 | { | |
13240 | used_at = 1; | |
bad1aba3 | 13241 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13242 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13243 | break; |
13244 | } | |
252b5132 RH |
13245 | else |
13246 | { | |
bad1aba3 | 13247 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13248 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13249 | used_at = 1; |
13250 | } | |
c0ebe874 | 13251 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13252 | break; |
252b5132 | 13253 | |
c0ebe874 | 13254 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13255 | s = "slt"; |
13256 | goto sge; | |
13257 | case M_SGEU: | |
13258 | s = "sltu"; | |
13259 | sge: | |
c0ebe874 RS |
13260 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13261 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13262 | break; |
252b5132 | 13263 | |
c0ebe874 | 13264 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13265 | case M_SGEU_I: |
b0e6f033 | 13266 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13267 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13268 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13269 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13270 | else |
13271 | { | |
bad1aba3 | 13272 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13273 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13274 | op[0], op[1], AT); |
252b5132 RH |
13275 | used_at = 1; |
13276 | } | |
c0ebe874 | 13277 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13278 | break; |
252b5132 | 13279 | |
c0ebe874 | 13280 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13281 | s = "slt"; |
13282 | goto sgt; | |
13283 | case M_SGTU: | |
13284 | s = "sltu"; | |
13285 | sgt: | |
c0ebe874 | 13286 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13287 | break; |
252b5132 | 13288 | |
c0ebe874 | 13289 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13290 | s = "slt"; |
13291 | goto sgti; | |
13292 | case M_SGTU_I: | |
13293 | s = "sltu"; | |
13294 | sgti: | |
8fc2e39e | 13295 | used_at = 1; |
bad1aba3 | 13296 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13297 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13298 | break; |
13299 | ||
c0ebe874 | 13300 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13301 | s = "slt"; |
13302 | goto sle; | |
13303 | case M_SLEU: | |
13304 | s = "sltu"; | |
13305 | sle: | |
c0ebe874 RS |
13306 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13307 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13308 | break; |
252b5132 | 13309 | |
c0ebe874 | 13310 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13311 | s = "slt"; |
13312 | goto slei; | |
13313 | case M_SLEU_I: | |
13314 | s = "sltu"; | |
13315 | slei: | |
8fc2e39e | 13316 | used_at = 1; |
bad1aba3 | 13317 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13318 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13319 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13320 | break; |
13321 | ||
13322 | case M_SLT_I: | |
b0e6f033 | 13323 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13324 | && imm_expr.X_add_number < 0x8000) |
13325 | { | |
c0ebe874 RS |
13326 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13327 | BFD_RELOC_LO16); | |
8fc2e39e | 13328 | break; |
252b5132 | 13329 | } |
8fc2e39e | 13330 | used_at = 1; |
bad1aba3 | 13331 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13332 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13333 | break; |
13334 | ||
13335 | case M_SLTU_I: | |
b0e6f033 | 13336 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13337 | && imm_expr.X_add_number < 0x8000) |
13338 | { | |
c0ebe874 | 13339 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13340 | BFD_RELOC_LO16); |
8fc2e39e | 13341 | break; |
252b5132 | 13342 | } |
8fc2e39e | 13343 | used_at = 1; |
bad1aba3 | 13344 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13345 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13346 | break; |
13347 | ||
13348 | case M_SNE: | |
c0ebe874 RS |
13349 | if (op[1] == 0) |
13350 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13351 | else if (op[2] == 0) | |
13352 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13353 | else |
13354 | { | |
c0ebe874 RS |
13355 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13356 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13357 | } |
8fc2e39e | 13358 | break; |
252b5132 RH |
13359 | |
13360 | case M_SNE_I: | |
b0e6f033 | 13361 | if (imm_expr.X_add_number == 0) |
252b5132 | 13362 | { |
c0ebe874 | 13363 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13364 | break; |
252b5132 | 13365 | } |
c0ebe874 | 13366 | if (op[1] == 0) |
252b5132 | 13367 | { |
1661c76c | 13368 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13369 | ip->insn_mo->name); |
bad1aba3 | 13370 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13371 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13372 | break; |
252b5132 | 13373 | } |
dd3cbb7e NC |
13374 | if (CPU_HAS_SEQ (mips_opts.arch) |
13375 | && -512 <= imm_expr.X_add_number | |
13376 | && imm_expr.X_add_number < 512) | |
13377 | { | |
c0ebe874 | 13378 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13379 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13380 | break; |
13381 | } | |
b0e6f033 | 13382 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13383 | && imm_expr.X_add_number < 0x10000) |
13384 | { | |
c0ebe874 RS |
13385 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13386 | BFD_RELOC_LO16); | |
252b5132 | 13387 | } |
b0e6f033 | 13388 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13389 | && imm_expr.X_add_number < 0) |
13390 | { | |
13391 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13392 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13393 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13394 | } |
dd3cbb7e NC |
13395 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13396 | { | |
13397 | used_at = 1; | |
bad1aba3 | 13398 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13399 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13400 | break; |
13401 | } | |
252b5132 RH |
13402 | else |
13403 | { | |
bad1aba3 | 13404 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13405 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13406 | used_at = 1; |
13407 | } | |
c0ebe874 | 13408 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13409 | break; |
252b5132 | 13410 | |
df58fc94 RS |
13411 | case M_SUB_I: |
13412 | s = "addi"; | |
13413 | s2 = "sub"; | |
13414 | goto do_subi; | |
13415 | case M_SUBU_I: | |
13416 | s = "addiu"; | |
13417 | s2 = "subu"; | |
13418 | goto do_subi; | |
252b5132 RH |
13419 | case M_DSUB_I: |
13420 | dbl = 1; | |
df58fc94 RS |
13421 | s = "daddi"; |
13422 | s2 = "dsub"; | |
13423 | if (!mips_opts.micromips) | |
13424 | goto do_subi; | |
b0e6f033 | 13425 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13426 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13427 | { |
b0e6f033 RS |
13428 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13429 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13430 | break; |
252b5132 | 13431 | } |
df58fc94 | 13432 | goto do_subi_i; |
252b5132 RH |
13433 | case M_DSUBU_I: |
13434 | dbl = 1; | |
df58fc94 RS |
13435 | s = "daddiu"; |
13436 | s2 = "dsubu"; | |
13437 | do_subi: | |
b0e6f033 | 13438 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13439 | && imm_expr.X_add_number <= 0x8000) |
13440 | { | |
13441 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13442 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13443 | break; |
252b5132 | 13444 | } |
df58fc94 | 13445 | do_subi_i: |
8fc2e39e | 13446 | used_at = 1; |
67c0d1eb | 13447 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13448 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13449 | break; |
13450 | ||
13451 | case M_TEQ_I: | |
13452 | s = "teq"; | |
13453 | goto trap; | |
13454 | case M_TGE_I: | |
13455 | s = "tge"; | |
13456 | goto trap; | |
13457 | case M_TGEU_I: | |
13458 | s = "tgeu"; | |
13459 | goto trap; | |
13460 | case M_TLT_I: | |
13461 | s = "tlt"; | |
13462 | goto trap; | |
13463 | case M_TLTU_I: | |
13464 | s = "tltu"; | |
13465 | goto trap; | |
13466 | case M_TNE_I: | |
13467 | s = "tne"; | |
13468 | trap: | |
8fc2e39e | 13469 | used_at = 1; |
bad1aba3 | 13470 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13471 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13472 | break; |
13473 | ||
252b5132 | 13474 | case M_TRUNCWS: |
43841e91 | 13475 | case M_TRUNCWD: |
df58fc94 | 13476 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13477 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13478 | used_at = 1; |
252b5132 RH |
13479 | |
13480 | /* | |
13481 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13482 | * or is there a reason for it? | |
13483 | */ | |
7d10b47d | 13484 | start_noreorder (); |
c0ebe874 RS |
13485 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13486 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13487 | macro_build (NULL, "nop", ""); |
252b5132 | 13488 | expr1.X_add_number = 3; |
c0ebe874 | 13489 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13490 | expr1.X_add_number = 2; |
67c0d1eb RS |
13491 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13492 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13493 | macro_build (NULL, "nop", ""); | |
13494 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13495 | op[0], op[1]); |
13496 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13497 | macro_build (NULL, "nop", ""); |
7d10b47d | 13498 | end_noreorder (); |
252b5132 RH |
13499 | break; |
13500 | ||
f2ae14a1 | 13501 | case M_ULH_AB: |
252b5132 | 13502 | s = "lb"; |
df58fc94 RS |
13503 | s2 = "lbu"; |
13504 | off = 1; | |
13505 | goto uld_st; | |
f2ae14a1 | 13506 | case M_ULHU_AB: |
252b5132 | 13507 | s = "lbu"; |
df58fc94 RS |
13508 | s2 = "lbu"; |
13509 | off = 1; | |
13510 | goto uld_st; | |
f2ae14a1 | 13511 | case M_ULW_AB: |
df58fc94 RS |
13512 | s = "lwl"; |
13513 | s2 = "lwr"; | |
7f3c4072 | 13514 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13515 | off = 3; |
13516 | goto uld_st; | |
f2ae14a1 | 13517 | case M_ULD_AB: |
252b5132 RH |
13518 | s = "ldl"; |
13519 | s2 = "ldr"; | |
7f3c4072 | 13520 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13521 | off = 7; |
df58fc94 | 13522 | goto uld_st; |
f2ae14a1 | 13523 | case M_USH_AB: |
df58fc94 RS |
13524 | s = "sb"; |
13525 | s2 = "sb"; | |
13526 | off = 1; | |
13527 | ust = 1; | |
13528 | goto uld_st; | |
f2ae14a1 | 13529 | case M_USW_AB: |
df58fc94 RS |
13530 | s = "swl"; |
13531 | s2 = "swr"; | |
7f3c4072 | 13532 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13533 | off = 3; |
df58fc94 RS |
13534 | ust = 1; |
13535 | goto uld_st; | |
f2ae14a1 | 13536 | case M_USD_AB: |
df58fc94 RS |
13537 | s = "sdl"; |
13538 | s2 = "sdr"; | |
7f3c4072 | 13539 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13540 | off = 7; |
13541 | ust = 1; | |
13542 | ||
13543 | uld_st: | |
c0ebe874 | 13544 | breg = op[2]; |
f2ae14a1 | 13545 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13546 | ep = &offset_expr; |
13547 | expr1.X_add_number = 0; | |
f2ae14a1 | 13548 | if (large_offset) |
df58fc94 RS |
13549 | { |
13550 | used_at = 1; | |
13551 | tempreg = AT; | |
f2ae14a1 RS |
13552 | if (small_offset_p (0, align, 16)) |
13553 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13554 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13555 | else | |
13556 | { | |
13557 | load_address (tempreg, ep, &used_at); | |
13558 | if (breg != 0) | |
13559 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13560 | tempreg, tempreg, breg); | |
13561 | } | |
13562 | offset_reloc[0] = BFD_RELOC_LO16; | |
13563 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13564 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13565 | breg = tempreg; |
c0ebe874 | 13566 | tempreg = op[0]; |
df58fc94 RS |
13567 | ep = &expr1; |
13568 | } | |
c0ebe874 | 13569 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13570 | { |
13571 | used_at = 1; | |
13572 | tempreg = AT; | |
13573 | } | |
252b5132 | 13574 | else |
c0ebe874 | 13575 | tempreg = op[0]; |
af22f5b2 | 13576 | |
df58fc94 RS |
13577 | if (off == 1) |
13578 | goto ulh_sh; | |
252b5132 | 13579 | |
90ecf173 | 13580 | if (!target_big_endian) |
df58fc94 | 13581 | ep->X_add_number += off; |
f2ae14a1 | 13582 | if (offbits == 12) |
c8276761 | 13583 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13584 | else |
13585 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13586 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13587 | |
90ecf173 | 13588 | if (!target_big_endian) |
df58fc94 | 13589 | ep->X_add_number -= off; |
252b5132 | 13590 | else |
df58fc94 | 13591 | ep->X_add_number += off; |
f2ae14a1 | 13592 | if (offbits == 12) |
df58fc94 | 13593 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13594 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13595 | else |
13596 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13597 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13598 | |
df58fc94 | 13599 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13600 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13601 | { |
13602 | /* Protect second load's delay slot. */ | |
13603 | load_delay_nop (); | |
c0ebe874 | 13604 | move_register (op[0], tempreg); |
df58fc94 | 13605 | } |
8fc2e39e | 13606 | break; |
252b5132 | 13607 | |
df58fc94 | 13608 | ulh_sh: |
d6bc6245 | 13609 | used_at = 1; |
df58fc94 RS |
13610 | if (target_big_endian == ust) |
13611 | ep->X_add_number += off; | |
c0ebe874 | 13612 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13613 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13614 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13615 | |
13616 | /* For halfword transfers we need a temporary register to shuffle | |
13617 | bytes. Unfortunately for M_USH_A we have none available before | |
13618 | the next store as AT holds the base address. We deal with this | |
13619 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13620 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13621 | if (ust) |
c0ebe874 | 13622 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13623 | |
13624 | if (target_big_endian == ust) | |
13625 | ep->X_add_number -= off; | |
252b5132 | 13626 | else |
df58fc94 | 13627 | ep->X_add_number += off; |
f2ae14a1 RS |
13628 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13629 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13630 | |
df58fc94 | 13631 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13632 | if (ust && large_offset) |
df58fc94 RS |
13633 | { |
13634 | if (target_big_endian) | |
13635 | ep->X_add_number += off; | |
13636 | else | |
13637 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13638 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13639 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13640 | } |
13641 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13642 | if (!ust || large_offset) |
df58fc94 | 13643 | { |
c0ebe874 | 13644 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13645 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13646 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13647 | } |
252b5132 RH |
13648 | break; |
13649 | ||
13650 | default: | |
13651 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13652 | are added dynamically. */ |
1661c76c | 13653 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13654 | break; |
13655 | } | |
741fe287 | 13656 | if (!mips_opts.at && used_at) |
1661c76c | 13657 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13658 | } |
13659 | ||
13660 | /* Implement macros in mips16 mode. */ | |
13661 | ||
13662 | static void | |
17a2f251 | 13663 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13664 | { |
c0ebe874 | 13665 | const struct mips_operand_array *operands; |
252b5132 | 13666 | int mask; |
c0ebe874 | 13667 | int tmp; |
252b5132 RH |
13668 | expressionS expr1; |
13669 | int dbl; | |
13670 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13671 | unsigned int op[MAX_OPERANDS]; |
13672 | unsigned int i; | |
252b5132 RH |
13673 | |
13674 | mask = ip->insn_mo->mask; | |
13675 | ||
c0ebe874 RS |
13676 | operands = insn_operands (ip); |
13677 | for (i = 0; i < MAX_OPERANDS; i++) | |
13678 | if (operands->operand[i]) | |
13679 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13680 | else | |
13681 | op[i] = -1; | |
252b5132 | 13682 | |
252b5132 RH |
13683 | expr1.X_op = O_constant; |
13684 | expr1.X_op_symbol = NULL; | |
13685 | expr1.X_add_symbol = NULL; | |
13686 | expr1.X_add_number = 1; | |
13687 | ||
13688 | dbl = 0; | |
13689 | ||
13690 | switch (mask) | |
13691 | { | |
13692 | default: | |
b37df7c4 | 13693 | abort (); |
252b5132 RH |
13694 | |
13695 | case M_DDIV_3: | |
13696 | dbl = 1; | |
1a0670f3 | 13697 | /* Fall through. */ |
252b5132 RH |
13698 | case M_DIV_3: |
13699 | s = "mflo"; | |
13700 | goto do_div3; | |
13701 | case M_DREM_3: | |
13702 | dbl = 1; | |
1a0670f3 | 13703 | /* Fall through. */ |
252b5132 RH |
13704 | case M_REM_3: |
13705 | s = "mfhi"; | |
13706 | do_div3: | |
7d10b47d | 13707 | start_noreorder (); |
d8722d76 | 13708 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13709 | expr1.X_add_number = 2; |
c0ebe874 | 13710 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13711 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13712 | |
252b5132 RH |
13713 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13714 | since that causes an overflow. We should do that as well, | |
13715 | but I don't see how to do the comparisons without a temporary | |
13716 | register. */ | |
7d10b47d | 13717 | end_noreorder (); |
c0ebe874 | 13718 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13719 | break; |
13720 | ||
13721 | case M_DIVU_3: | |
13722 | s = "divu"; | |
13723 | s2 = "mflo"; | |
13724 | goto do_divu3; | |
13725 | case M_REMU_3: | |
13726 | s = "divu"; | |
13727 | s2 = "mfhi"; | |
13728 | goto do_divu3; | |
13729 | case M_DDIVU_3: | |
13730 | s = "ddivu"; | |
13731 | s2 = "mflo"; | |
13732 | goto do_divu3; | |
13733 | case M_DREMU_3: | |
13734 | s = "ddivu"; | |
13735 | s2 = "mfhi"; | |
13736 | do_divu3: | |
7d10b47d | 13737 | start_noreorder (); |
d8722d76 | 13738 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13739 | expr1.X_add_number = 2; |
c0ebe874 | 13740 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13741 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13742 | end_noreorder (); |
c0ebe874 | 13743 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13744 | break; |
13745 | ||
13746 | case M_DMUL: | |
13747 | dbl = 1; | |
1a0670f3 | 13748 | /* Fall through. */ |
252b5132 | 13749 | case M_MUL: |
c0ebe874 RS |
13750 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13751 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13752 | break; |
252b5132 RH |
13753 | |
13754 | case M_DSUBU_I: | |
13755 | dbl = 1; | |
13756 | goto do_subu; | |
13757 | case M_SUBU_I: | |
13758 | do_subu: | |
252b5132 | 13759 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13760 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13761 | break; |
13762 | ||
13763 | case M_SUBU_I_2: | |
252b5132 | 13764 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13765 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13766 | break; |
13767 | ||
13768 | case M_DSUBU_I_2: | |
252b5132 | 13769 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13770 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13771 | break; |
13772 | ||
13773 | case M_BEQ: | |
13774 | s = "cmp"; | |
13775 | s2 = "bteqz"; | |
13776 | goto do_branch; | |
13777 | case M_BNE: | |
13778 | s = "cmp"; | |
13779 | s2 = "btnez"; | |
13780 | goto do_branch; | |
13781 | case M_BLT: | |
13782 | s = "slt"; | |
13783 | s2 = "btnez"; | |
13784 | goto do_branch; | |
13785 | case M_BLTU: | |
13786 | s = "sltu"; | |
13787 | s2 = "btnez"; | |
13788 | goto do_branch; | |
13789 | case M_BLE: | |
13790 | s = "slt"; | |
13791 | s2 = "bteqz"; | |
13792 | goto do_reverse_branch; | |
13793 | case M_BLEU: | |
13794 | s = "sltu"; | |
13795 | s2 = "bteqz"; | |
13796 | goto do_reverse_branch; | |
13797 | case M_BGE: | |
13798 | s = "slt"; | |
13799 | s2 = "bteqz"; | |
13800 | goto do_branch; | |
13801 | case M_BGEU: | |
13802 | s = "sltu"; | |
13803 | s2 = "bteqz"; | |
13804 | goto do_branch; | |
13805 | case M_BGT: | |
13806 | s = "slt"; | |
13807 | s2 = "btnez"; | |
13808 | goto do_reverse_branch; | |
13809 | case M_BGTU: | |
13810 | s = "sltu"; | |
13811 | s2 = "btnez"; | |
13812 | ||
13813 | do_reverse_branch: | |
c0ebe874 RS |
13814 | tmp = op[1]; |
13815 | op[1] = op[0]; | |
13816 | op[0] = tmp; | |
252b5132 RH |
13817 | |
13818 | do_branch: | |
c0ebe874 | 13819 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13820 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13821 | break; |
13822 | ||
13823 | case M_BEQ_I: | |
13824 | s = "cmpi"; | |
13825 | s2 = "bteqz"; | |
13826 | s3 = "x,U"; | |
13827 | goto do_branch_i; | |
13828 | case M_BNE_I: | |
13829 | s = "cmpi"; | |
13830 | s2 = "btnez"; | |
13831 | s3 = "x,U"; | |
13832 | goto do_branch_i; | |
13833 | case M_BLT_I: | |
13834 | s = "slti"; | |
13835 | s2 = "btnez"; | |
13836 | s3 = "x,8"; | |
13837 | goto do_branch_i; | |
13838 | case M_BLTU_I: | |
13839 | s = "sltiu"; | |
13840 | s2 = "btnez"; | |
13841 | s3 = "x,8"; | |
13842 | goto do_branch_i; | |
13843 | case M_BLE_I: | |
13844 | s = "slti"; | |
13845 | s2 = "btnez"; | |
13846 | s3 = "x,8"; | |
13847 | goto do_addone_branch_i; | |
13848 | case M_BLEU_I: | |
13849 | s = "sltiu"; | |
13850 | s2 = "btnez"; | |
13851 | s3 = "x,8"; | |
13852 | goto do_addone_branch_i; | |
13853 | case M_BGE_I: | |
13854 | s = "slti"; | |
13855 | s2 = "bteqz"; | |
13856 | s3 = "x,8"; | |
13857 | goto do_branch_i; | |
13858 | case M_BGEU_I: | |
13859 | s = "sltiu"; | |
13860 | s2 = "bteqz"; | |
13861 | s3 = "x,8"; | |
13862 | goto do_branch_i; | |
13863 | case M_BGT_I: | |
13864 | s = "slti"; | |
13865 | s2 = "bteqz"; | |
13866 | s3 = "x,8"; | |
13867 | goto do_addone_branch_i; | |
13868 | case M_BGTU_I: | |
13869 | s = "sltiu"; | |
13870 | s2 = "bteqz"; | |
13871 | s3 = "x,8"; | |
13872 | ||
13873 | do_addone_branch_i: | |
252b5132 RH |
13874 | ++imm_expr.X_add_number; |
13875 | ||
13876 | do_branch_i: | |
c0ebe874 | 13877 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13878 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13879 | break; |
13880 | ||
13881 | case M_ABS: | |
13882 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13883 | macro_build (&expr1, "slti", "x,8", op[1]); |
13884 | if (op[0] != op[1]) | |
13885 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13886 | expr1.X_add_number = 2; |
67c0d1eb | 13887 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13888 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13889 | break; |
252b5132 RH |
13890 | } |
13891 | } | |
13892 | ||
14daeee3 RS |
13893 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13894 | opcode bits in *OPCODE_EXTRA. */ | |
13895 | ||
13896 | static struct mips_opcode * | |
13897 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13898 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13899 | { |
13900 | char *name, *dot, *p; | |
13901 | unsigned int mask, suffix; | |
da8bca91 | 13902 | ssize_t opend; |
14daeee3 RS |
13903 | struct mips_opcode *insn; |
13904 | ||
13905 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 13906 | name = xstrndup (start, length); |
14daeee3 RS |
13907 | |
13908 | /* Look up the instruction as-is. */ | |
13909 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13910 | if (insn) |
e1fa0163 | 13911 | goto end; |
14daeee3 RS |
13912 | |
13913 | dot = strchr (name, '.'); | |
13914 | if (dot && dot[1]) | |
13915 | { | |
13916 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13917 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13918 | if (*p == 0 && mask != 0) | |
13919 | { | |
13920 | *dot = 0; | |
13921 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13922 | *dot = '.'; | |
13923 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13924 | { | |
13925 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 13926 | goto end; |
14daeee3 RS |
13927 | } |
13928 | } | |
13929 | } | |
13930 | ||
13931 | if (mips_opts.micromips) | |
13932 | { | |
13933 | /* See if there's an instruction size override suffix, | |
13934 | either `16' or `32', at the end of the mnemonic proper, | |
13935 | that defines the operation, i.e. before the first `.' | |
13936 | character if any. Strip it and retry. */ | |
13937 | opend = dot != NULL ? dot - name : length; | |
13938 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13939 | suffix = 2; | |
13940 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13941 | suffix = 4; | |
13942 | else | |
13943 | suffix = 0; | |
13944 | if (suffix) | |
13945 | { | |
13946 | memcpy (name + opend - 2, name + opend, length - opend + 1); | |
13947 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13948 | if (insn) |
14daeee3 RS |
13949 | { |
13950 | forced_insn_length = suffix; | |
e1fa0163 | 13951 | goto end; |
14daeee3 RS |
13952 | } |
13953 | } | |
13954 | } | |
13955 | ||
e1fa0163 NC |
13956 | insn = NULL; |
13957 | end: | |
13958 | free (name); | |
13959 | return insn; | |
14daeee3 RS |
13960 | } |
13961 | ||
77bd4346 | 13962 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13963 | is a macro, set imm_expr and offset_expr to the values associated |
13964 | with "I" and "A" operands respectively. Otherwise store the value | |
13965 | of the relocatable field (if any) in offset_expr. In both cases | |
13966 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13967 | |
13968 | static void | |
60f20e8b | 13969 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13970 | { |
60f20e8b | 13971 | const struct mips_opcode *first, *past; |
df58fc94 | 13972 | struct hash_control *hash; |
a92713e6 | 13973 | char format; |
14daeee3 | 13974 | size_t end; |
a92713e6 | 13975 | struct mips_operand_token *tokens; |
14daeee3 | 13976 | unsigned int opcode_extra; |
252b5132 | 13977 | |
df58fc94 RS |
13978 | if (mips_opts.micromips) |
13979 | { | |
13980 | hash = micromips_op_hash; | |
13981 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
13982 | } | |
13983 | else | |
13984 | { | |
13985 | hash = op_hash; | |
13986 | past = &mips_opcodes[NUMOPCODES]; | |
13987 | } | |
13988 | forced_insn_length = 0; | |
14daeee3 | 13989 | opcode_extra = 0; |
252b5132 | 13990 | |
df58fc94 | 13991 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
13992 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
13993 | continue; | |
bdaaa2e1 | 13994 | |
60f20e8b RS |
13995 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
13996 | if (first == NULL) | |
252b5132 | 13997 | { |
1661c76c | 13998 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 13999 | return; |
252b5132 RH |
14000 | } |
14001 | ||
60f20e8b | 14002 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14003 | format = 'f'; |
60f20e8b | 14004 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14005 | format = 'd'; |
14006 | else | |
14007 | format = 0; | |
14008 | tokens = mips_parse_arguments (str + end, format); | |
14009 | if (!tokens) | |
14010 | return; | |
14011 | ||
60f20e8b RS |
14012 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14013 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14014 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14015 | |
e3de51ce | 14016 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14017 | } |
14018 | ||
77bd4346 RS |
14019 | /* As for mips_ip, but used when assembling MIPS16 code. |
14020 | Also set forced_insn_length to the resulting instruction size in | |
14021 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14022 | |
14023 | static void | |
60f20e8b | 14024 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14025 | { |
1a00e612 | 14026 | char *end, *s, c; |
60f20e8b | 14027 | struct mips_opcode *first; |
a92713e6 | 14028 | struct mips_operand_token *tokens; |
3fb49709 | 14029 | unsigned int l; |
252b5132 | 14030 | |
25499ac7 | 14031 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14032 | ; |
1a00e612 RS |
14033 | end = s; |
14034 | c = *end; | |
3fb49709 MR |
14035 | |
14036 | l = 0; | |
1a00e612 | 14037 | switch (c) |
252b5132 RH |
14038 | { |
14039 | case '\0': | |
14040 | break; | |
14041 | ||
14042 | case ' ': | |
1a00e612 | 14043 | s++; |
252b5132 RH |
14044 | break; |
14045 | ||
14046 | case '.': | |
3fb49709 MR |
14047 | s++; |
14048 | if (*s == 't') | |
252b5132 | 14049 | { |
3fb49709 MR |
14050 | l = 2; |
14051 | s++; | |
252b5132 | 14052 | } |
3fb49709 | 14053 | else if (*s == 'e') |
252b5132 | 14054 | { |
3fb49709 MR |
14055 | l = 4; |
14056 | s++; | |
252b5132 | 14057 | } |
3fb49709 MR |
14058 | if (*s == '\0') |
14059 | break; | |
14060 | else if (*s++ == ' ') | |
14061 | break; | |
1661c76c | 14062 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14063 | return; |
14064 | } | |
3fb49709 | 14065 | forced_insn_length = l; |
252b5132 | 14066 | |
1a00e612 | 14067 | *end = 0; |
60f20e8b | 14068 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14069 | *end = c; |
14070 | ||
60f20e8b | 14071 | if (!first) |
252b5132 | 14072 | { |
1661c76c | 14073 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14074 | return; |
14075 | } | |
14076 | ||
a92713e6 RS |
14077 | tokens = mips_parse_arguments (s, 0); |
14078 | if (!tokens) | |
14079 | return; | |
14080 | ||
60f20e8b | 14081 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14082 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14083 | |
e3de51ce | 14084 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14085 | } |
14086 | ||
b886a2ab RS |
14087 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14088 | NBITS is the number of significant bits in VAL. */ | |
14089 | ||
14090 | static unsigned long | |
14091 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14092 | { | |
14093 | int extval; | |
25499ac7 MR |
14094 | |
14095 | extval = 0; | |
14096 | val &= (1U << nbits) - 1; | |
14097 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14098 | { |
14099 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14100 | val &= 0x1f; | |
14101 | } | |
14102 | else if (nbits == 15) | |
14103 | { | |
14104 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14105 | val &= 0xf; | |
14106 | } | |
25499ac7 | 14107 | else if (nbits == 6) |
b886a2ab RS |
14108 | { |
14109 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14110 | val = 0; | |
14111 | } | |
14112 | return (extval << 16) | val; | |
14113 | } | |
14114 | ||
3ccad066 RS |
14115 | /* Like decode_mips16_operand, but require the operand to be defined and |
14116 | require it to be an integer. */ | |
14117 | ||
14118 | static const struct mips_int_operand * | |
14119 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14120 | { | |
14121 | const struct mips_operand *operand; | |
14122 | ||
14123 | operand = decode_mips16_operand (type, extended_p); | |
14124 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14125 | abort (); | |
14126 | return (const struct mips_int_operand *) operand; | |
14127 | } | |
14128 | ||
14129 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14130 | ||
14131 | static bfd_boolean | |
14132 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14133 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14134 | { | |
14135 | int min_val, max_val; | |
14136 | ||
14137 | min_val = mips_int_operand_min (operand); | |
14138 | max_val = mips_int_operand_max (operand); | |
14139 | if (reloc != BFD_RELOC_UNUSED) | |
14140 | { | |
14141 | if (min_val < 0) | |
14142 | sval = SEXT_16BIT (sval); | |
14143 | else | |
14144 | sval &= 0xffff; | |
14145 | } | |
14146 | ||
14147 | return (sval >= min_val | |
14148 | && sval <= max_val | |
14149 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14150 | } | |
14151 | ||
5c04167a RS |
14152 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14153 | extending it if necessary. The instruction in *INSN may | |
14154 | already be extended. | |
14155 | ||
43c0598f RS |
14156 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14157 | if none. In the former case, VAL is a 16-bit number with no | |
14158 | defined signedness. | |
14159 | ||
14160 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14161 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14162 | |
14163 | static void | |
3b4dbbbf | 14164 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14165 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14166 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14167 | { |
3ccad066 RS |
14168 | const struct mips_int_operand *operand; |
14169 | unsigned int uval, length; | |
252b5132 | 14170 | |
3ccad066 RS |
14171 | operand = mips16_immed_operand (type, FALSE); |
14172 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14173 | { |
14174 | /* We need an extended instruction. */ | |
14175 | if (user_insn_length == 2) | |
14176 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14177 | else | |
14178 | *insn |= MIPS16_EXTEND; | |
14179 | } | |
14180 | else if (user_insn_length == 4) | |
14181 | { | |
14182 | /* The operand doesn't force an unextended instruction to be extended. | |
14183 | Warn if the user wanted an extended instruction anyway. */ | |
14184 | *insn |= MIPS16_EXTEND; | |
14185 | as_warn_where (file, line, | |
14186 | _("extended operand requested but not required")); | |
14187 | } | |
252b5132 | 14188 | |
3ccad066 RS |
14189 | length = mips16_opcode_length (*insn); |
14190 | if (length == 4) | |
252b5132 | 14191 | { |
3ccad066 RS |
14192 | operand = mips16_immed_operand (type, TRUE); |
14193 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14194 | as_bad_where (file, line, | |
14195 | _("operand value out of range for instruction")); | |
252b5132 | 14196 | } |
3ccad066 | 14197 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14198 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14199 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14200 | else |
3ccad066 | 14201 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14202 | } |
14203 | \f | |
d6f16593 | 14204 | struct percent_op_match |
ad8d3bb3 | 14205 | { |
5e0116d5 RS |
14206 | const char *str; |
14207 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14208 | }; |
14209 | ||
14210 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14211 | { |
5e0116d5 | 14212 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14213 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14214 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14215 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14216 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14217 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14218 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14219 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14220 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14221 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14222 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14223 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14224 | {"%half", BFD_RELOC_16}, |
14225 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14226 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14227 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14228 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14229 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14230 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14231 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14232 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14233 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14234 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14235 | {"%hi", BFD_RELOC_HI16_S}, |
14236 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14237 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14238 | }; |
14239 | ||
d6f16593 MR |
14240 | static const struct percent_op_match mips16_percent_op[] = |
14241 | { | |
14242 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14243 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14244 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14245 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14246 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14247 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14248 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14249 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14250 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14251 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14252 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14253 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14254 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14255 | }; |
14256 | ||
252b5132 | 14257 | |
5e0116d5 RS |
14258 | /* Return true if *STR points to a relocation operator. When returning true, |
14259 | move *STR over the operator and store its relocation code in *RELOC. | |
14260 | Leave both *STR and *RELOC alone when returning false. */ | |
14261 | ||
14262 | static bfd_boolean | |
17a2f251 | 14263 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14264 | { |
d6f16593 MR |
14265 | const struct percent_op_match *percent_op; |
14266 | size_t limit, i; | |
14267 | ||
14268 | if (mips_opts.mips16) | |
14269 | { | |
14270 | percent_op = mips16_percent_op; | |
14271 | limit = ARRAY_SIZE (mips16_percent_op); | |
14272 | } | |
14273 | else | |
14274 | { | |
14275 | percent_op = mips_percent_op; | |
14276 | limit = ARRAY_SIZE (mips_percent_op); | |
14277 | } | |
76b3015f | 14278 | |
d6f16593 | 14279 | for (i = 0; i < limit; i++) |
5e0116d5 | 14280 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14281 | { |
3f98094e DJ |
14282 | int len = strlen (percent_op[i].str); |
14283 | ||
14284 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14285 | continue; | |
14286 | ||
5e0116d5 RS |
14287 | *str += strlen (percent_op[i].str); |
14288 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14289 | |
5e0116d5 RS |
14290 | /* Check whether the output BFD supports this relocation. |
14291 | If not, issue an error and fall back on something safe. */ | |
14292 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14293 | { |
20203fb9 | 14294 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14295 | percent_op[i].str); |
01a3f561 | 14296 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14297 | } |
5e0116d5 | 14298 | return TRUE; |
394f9b3a | 14299 | } |
5e0116d5 | 14300 | return FALSE; |
394f9b3a | 14301 | } |
ad8d3bb3 | 14302 | |
ad8d3bb3 | 14303 | |
5e0116d5 RS |
14304 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14305 | expression in *EP and the relocations in the array starting | |
14306 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14307 | |
01a3f561 | 14308 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14309 | |
5e0116d5 | 14310 | static size_t |
17a2f251 TS |
14311 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14312 | char *str) | |
ad8d3bb3 | 14313 | { |
5e0116d5 RS |
14314 | bfd_reloc_code_real_type reversed_reloc[3]; |
14315 | size_t reloc_index, i; | |
09b8f35a RS |
14316 | int crux_depth, str_depth; |
14317 | char *crux; | |
5e0116d5 RS |
14318 | |
14319 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14320 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14321 | of the main expression and with CRUX_DEPTH containing the number | |
14322 | of open brackets at that point. */ | |
14323 | reloc_index = -1; | |
14324 | str_depth = 0; | |
14325 | do | |
fb1b3232 | 14326 | { |
09b8f35a RS |
14327 | reloc_index++; |
14328 | crux = str; | |
14329 | crux_depth = str_depth; | |
14330 | ||
14331 | /* Skip over whitespace and brackets, keeping count of the number | |
14332 | of brackets. */ | |
14333 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14334 | if (*str++ == '(') | |
14335 | str_depth++; | |
5e0116d5 | 14336 | } |
09b8f35a RS |
14337 | while (*str == '%' |
14338 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14339 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14340 | |
09b8f35a | 14341 | my_getExpression (ep, crux); |
5e0116d5 | 14342 | str = expr_end; |
394f9b3a | 14343 | |
5e0116d5 | 14344 | /* Match every open bracket. */ |
09b8f35a | 14345 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14346 | if (*str++ == ')') |
09b8f35a | 14347 | crux_depth--; |
394f9b3a | 14348 | |
09b8f35a | 14349 | if (crux_depth > 0) |
20203fb9 | 14350 | as_bad (_("unclosed '('")); |
394f9b3a | 14351 | |
5e0116d5 | 14352 | expr_end = str; |
252b5132 | 14353 | |
01a3f561 | 14354 | if (reloc_index != 0) |
64bdfcaf RS |
14355 | { |
14356 | prev_reloc_op_frag = frag_now; | |
14357 | for (i = 0; i < reloc_index; i++) | |
14358 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14359 | } | |
fb1b3232 | 14360 | |
5e0116d5 | 14361 | return reloc_index; |
252b5132 RH |
14362 | } |
14363 | ||
14364 | static void | |
17a2f251 | 14365 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14366 | { |
14367 | char *save_in; | |
14368 | ||
14369 | save_in = input_line_pointer; | |
14370 | input_line_pointer = str; | |
14371 | expression (ep); | |
14372 | expr_end = input_line_pointer; | |
14373 | input_line_pointer = save_in; | |
252b5132 RH |
14374 | } |
14375 | ||
6d4af3c2 | 14376 | const char * |
17a2f251 | 14377 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14378 | { |
499ac353 | 14379 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14380 | } |
14381 | ||
14382 | void | |
17a2f251 | 14383 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14384 | { |
14385 | if (target_big_endian) | |
14386 | number_to_chars_bigendian (buf, val, n); | |
14387 | else | |
14388 | number_to_chars_littleendian (buf, val, n); | |
14389 | } | |
14390 | \f | |
e013f690 TS |
14391 | static int support_64bit_objects(void) |
14392 | { | |
14393 | const char **list, **l; | |
aa3d8fdf | 14394 | int yes; |
e013f690 TS |
14395 | |
14396 | list = bfd_target_list (); | |
14397 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14398 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14399 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14400 | break; |
aa3d8fdf | 14401 | yes = (*l != NULL); |
e013f690 | 14402 | free (list); |
aa3d8fdf | 14403 | return yes; |
e013f690 TS |
14404 | } |
14405 | ||
316f5878 RS |
14406 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14407 | NEW_VALUE. Warn if another value was already specified. Note: | |
14408 | we have to defer parsing the -march and -mtune arguments in order | |
14409 | to handle 'from-abi' correctly, since the ABI might be specified | |
14410 | in a later argument. */ | |
14411 | ||
14412 | static void | |
17a2f251 | 14413 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14414 | { |
14415 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14416 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14417 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14418 | new_value); | |
14419 | ||
14420 | *string_ptr = new_value; | |
14421 | } | |
14422 | ||
252b5132 | 14423 | int |
17b9d67d | 14424 | md_parse_option (int c, const char *arg) |
252b5132 | 14425 | { |
c6278170 RS |
14426 | unsigned int i; |
14427 | ||
14428 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14429 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14430 | { | |
919731af | 14431 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14432 | c == mips_ases[i].option_on); |
14433 | return 1; | |
14434 | } | |
14435 | ||
252b5132 RH |
14436 | switch (c) |
14437 | { | |
119d663a NC |
14438 | case OPTION_CONSTRUCT_FLOATS: |
14439 | mips_disable_float_construction = 0; | |
14440 | break; | |
bdaaa2e1 | 14441 | |
119d663a NC |
14442 | case OPTION_NO_CONSTRUCT_FLOATS: |
14443 | mips_disable_float_construction = 1; | |
14444 | break; | |
bdaaa2e1 | 14445 | |
252b5132 RH |
14446 | case OPTION_TRAP: |
14447 | mips_trap = 1; | |
14448 | break; | |
14449 | ||
14450 | case OPTION_BREAK: | |
14451 | mips_trap = 0; | |
14452 | break; | |
14453 | ||
14454 | case OPTION_EB: | |
14455 | target_big_endian = 1; | |
14456 | break; | |
14457 | ||
14458 | case OPTION_EL: | |
14459 | target_big_endian = 0; | |
14460 | break; | |
14461 | ||
14462 | case 'O': | |
4ffff32f TS |
14463 | if (arg == NULL) |
14464 | mips_optimize = 1; | |
14465 | else if (arg[0] == '0') | |
14466 | mips_optimize = 0; | |
14467 | else if (arg[0] == '1') | |
252b5132 RH |
14468 | mips_optimize = 1; |
14469 | else | |
14470 | mips_optimize = 2; | |
14471 | break; | |
14472 | ||
14473 | case 'g': | |
14474 | if (arg == NULL) | |
14475 | mips_debug = 2; | |
14476 | else | |
14477 | mips_debug = atoi (arg); | |
252b5132 RH |
14478 | break; |
14479 | ||
14480 | case OPTION_MIPS1: | |
0b35dfee | 14481 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14482 | break; |
14483 | ||
14484 | case OPTION_MIPS2: | |
0b35dfee | 14485 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14486 | break; |
14487 | ||
14488 | case OPTION_MIPS3: | |
0b35dfee | 14489 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14490 | break; |
14491 | ||
14492 | case OPTION_MIPS4: | |
0b35dfee | 14493 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14494 | break; |
14495 | ||
84ea6cf2 | 14496 | case OPTION_MIPS5: |
0b35dfee | 14497 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14498 | break; |
14499 | ||
e7af610e | 14500 | case OPTION_MIPS32: |
0b35dfee | 14501 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14502 | break; |
14503 | ||
af7ee8bf | 14504 | case OPTION_MIPS32R2: |
0b35dfee | 14505 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14506 | break; |
14507 | ||
ae52f483 | 14508 | case OPTION_MIPS32R3: |
0ae19f05 | 14509 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14510 | break; |
14511 | ||
14512 | case OPTION_MIPS32R5: | |
0ae19f05 | 14513 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14514 | break; |
14515 | ||
7361da2c AB |
14516 | case OPTION_MIPS32R6: |
14517 | file_mips_opts.isa = ISA_MIPS32R6; | |
14518 | break; | |
14519 | ||
5f74bc13 | 14520 | case OPTION_MIPS64R2: |
0b35dfee | 14521 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14522 | break; |
14523 | ||
ae52f483 | 14524 | case OPTION_MIPS64R3: |
0ae19f05 | 14525 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14526 | break; |
14527 | ||
14528 | case OPTION_MIPS64R5: | |
0ae19f05 | 14529 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14530 | break; |
14531 | ||
7361da2c AB |
14532 | case OPTION_MIPS64R6: |
14533 | file_mips_opts.isa = ISA_MIPS64R6; | |
14534 | break; | |
14535 | ||
84ea6cf2 | 14536 | case OPTION_MIPS64: |
0b35dfee | 14537 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14538 | break; |
14539 | ||
ec68c924 | 14540 | case OPTION_MTUNE: |
316f5878 RS |
14541 | mips_set_option_string (&mips_tune_string, arg); |
14542 | break; | |
ec68c924 | 14543 | |
316f5878 RS |
14544 | case OPTION_MARCH: |
14545 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14546 | break; |
14547 | ||
14548 | case OPTION_M4650: | |
316f5878 RS |
14549 | mips_set_option_string (&mips_arch_string, "4650"); |
14550 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14551 | break; |
14552 | ||
14553 | case OPTION_NO_M4650: | |
14554 | break; | |
14555 | ||
14556 | case OPTION_M4010: | |
316f5878 RS |
14557 | mips_set_option_string (&mips_arch_string, "4010"); |
14558 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14559 | break; |
14560 | ||
14561 | case OPTION_NO_M4010: | |
14562 | break; | |
14563 | ||
14564 | case OPTION_M4100: | |
316f5878 RS |
14565 | mips_set_option_string (&mips_arch_string, "4100"); |
14566 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14567 | break; |
14568 | ||
14569 | case OPTION_NO_M4100: | |
14570 | break; | |
14571 | ||
252b5132 | 14572 | case OPTION_M3900: |
316f5878 RS |
14573 | mips_set_option_string (&mips_arch_string, "3900"); |
14574 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14575 | break; |
bdaaa2e1 | 14576 | |
252b5132 RH |
14577 | case OPTION_NO_M3900: |
14578 | break; | |
14579 | ||
df58fc94 | 14580 | case OPTION_MICROMIPS: |
919731af | 14581 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14582 | { |
14583 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14584 | return 0; | |
14585 | } | |
919731af | 14586 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14587 | mips_no_prev_insn (); |
14588 | break; | |
14589 | ||
14590 | case OPTION_NO_MICROMIPS: | |
919731af | 14591 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14592 | mips_no_prev_insn (); |
14593 | break; | |
14594 | ||
252b5132 | 14595 | case OPTION_MIPS16: |
919731af | 14596 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14597 | { |
14598 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14599 | return 0; | |
14600 | } | |
919731af | 14601 | file_mips_opts.mips16 = 1; |
7d10b47d | 14602 | mips_no_prev_insn (); |
252b5132 RH |
14603 | break; |
14604 | ||
14605 | case OPTION_NO_MIPS16: | |
919731af | 14606 | file_mips_opts.mips16 = 0; |
7d10b47d | 14607 | mips_no_prev_insn (); |
252b5132 RH |
14608 | break; |
14609 | ||
6a32d874 CM |
14610 | case OPTION_FIX_24K: |
14611 | mips_fix_24k = 1; | |
14612 | break; | |
14613 | ||
14614 | case OPTION_NO_FIX_24K: | |
14615 | mips_fix_24k = 0; | |
14616 | break; | |
14617 | ||
a8d14a88 CM |
14618 | case OPTION_FIX_RM7000: |
14619 | mips_fix_rm7000 = 1; | |
14620 | break; | |
14621 | ||
14622 | case OPTION_NO_FIX_RM7000: | |
14623 | mips_fix_rm7000 = 0; | |
14624 | break; | |
14625 | ||
c67a084a NC |
14626 | case OPTION_FIX_LOONGSON2F_JUMP: |
14627 | mips_fix_loongson2f_jump = TRUE; | |
14628 | break; | |
14629 | ||
14630 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14631 | mips_fix_loongson2f_jump = FALSE; | |
14632 | break; | |
14633 | ||
14634 | case OPTION_FIX_LOONGSON2F_NOP: | |
14635 | mips_fix_loongson2f_nop = TRUE; | |
14636 | break; | |
14637 | ||
14638 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14639 | mips_fix_loongson2f_nop = FALSE; | |
14640 | break; | |
14641 | ||
d766e8ec RS |
14642 | case OPTION_FIX_VR4120: |
14643 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14644 | break; |
14645 | ||
d766e8ec RS |
14646 | case OPTION_NO_FIX_VR4120: |
14647 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14648 | break; |
14649 | ||
7d8e00cf RS |
14650 | case OPTION_FIX_VR4130: |
14651 | mips_fix_vr4130 = 1; | |
14652 | break; | |
14653 | ||
14654 | case OPTION_NO_FIX_VR4130: | |
14655 | mips_fix_vr4130 = 0; | |
14656 | break; | |
14657 | ||
d954098f DD |
14658 | case OPTION_FIX_CN63XXP1: |
14659 | mips_fix_cn63xxp1 = TRUE; | |
14660 | break; | |
14661 | ||
14662 | case OPTION_NO_FIX_CN63XXP1: | |
14663 | mips_fix_cn63xxp1 = FALSE; | |
14664 | break; | |
14665 | ||
4a6a3df4 AO |
14666 | case OPTION_RELAX_BRANCH: |
14667 | mips_relax_branch = 1; | |
14668 | break; | |
14669 | ||
14670 | case OPTION_NO_RELAX_BRANCH: | |
14671 | mips_relax_branch = 0; | |
14672 | break; | |
14673 | ||
8b10b0b3 MR |
14674 | case OPTION_IGNORE_BRANCH_ISA: |
14675 | mips_ignore_branch_isa = TRUE; | |
14676 | break; | |
14677 | ||
14678 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14679 | mips_ignore_branch_isa = FALSE; | |
14680 | break; | |
14681 | ||
833794fc | 14682 | case OPTION_INSN32: |
919731af | 14683 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14684 | break; |
14685 | ||
14686 | case OPTION_NO_INSN32: | |
919731af | 14687 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14688 | break; |
14689 | ||
aa6975fb ILT |
14690 | case OPTION_MSHARED: |
14691 | mips_in_shared = TRUE; | |
14692 | break; | |
14693 | ||
14694 | case OPTION_MNO_SHARED: | |
14695 | mips_in_shared = FALSE; | |
14696 | break; | |
14697 | ||
aed1a261 | 14698 | case OPTION_MSYM32: |
919731af | 14699 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14700 | break; |
14701 | ||
14702 | case OPTION_MNO_SYM32: | |
919731af | 14703 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14704 | break; |
14705 | ||
252b5132 RH |
14706 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14707 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14708 | intended to be compatible with Irix 5. */ | |
14709 | case OPTION_CALL_SHARED: | |
252b5132 | 14710 | mips_pic = SVR4_PIC; |
143d77c5 | 14711 | mips_abicalls = TRUE; |
252b5132 RH |
14712 | break; |
14713 | ||
861fb55a | 14714 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14715 | mips_pic = NO_PIC; |
14716 | mips_abicalls = TRUE; | |
14717 | break; | |
14718 | ||
252b5132 | 14719 | case OPTION_NON_SHARED: |
252b5132 | 14720 | mips_pic = NO_PIC; |
143d77c5 | 14721 | mips_abicalls = FALSE; |
252b5132 RH |
14722 | break; |
14723 | ||
44075ae2 TS |
14724 | /* The -xgot option tells the assembler to use 32 bit offsets |
14725 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14726 | compatibility. */ |
14727 | case OPTION_XGOT: | |
14728 | mips_big_got = 1; | |
14729 | break; | |
14730 | ||
14731 | case 'G': | |
6caf9ef4 TS |
14732 | g_switch_value = atoi (arg); |
14733 | g_switch_seen = 1; | |
252b5132 RH |
14734 | break; |
14735 | ||
34ba82a8 TS |
14736 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14737 | and -mabi=64. */ | |
252b5132 | 14738 | case OPTION_32: |
f3ded42a | 14739 | mips_abi = O32_ABI; |
252b5132 RH |
14740 | break; |
14741 | ||
e013f690 | 14742 | case OPTION_N32: |
316f5878 | 14743 | mips_abi = N32_ABI; |
e013f690 | 14744 | break; |
252b5132 | 14745 | |
e013f690 | 14746 | case OPTION_64: |
316f5878 | 14747 | mips_abi = N64_ABI; |
f43abd2b | 14748 | if (!support_64bit_objects()) |
1661c76c | 14749 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14750 | break; |
14751 | ||
c97ef257 | 14752 | case OPTION_GP32: |
bad1aba3 | 14753 | file_mips_opts.gp = 32; |
c97ef257 AH |
14754 | break; |
14755 | ||
14756 | case OPTION_GP64: | |
bad1aba3 | 14757 | file_mips_opts.gp = 64; |
c97ef257 | 14758 | break; |
252b5132 | 14759 | |
ca4e0257 | 14760 | case OPTION_FP32: |
0b35dfee | 14761 | file_mips_opts.fp = 32; |
316f5878 RS |
14762 | break; |
14763 | ||
351cdf24 MF |
14764 | case OPTION_FPXX: |
14765 | file_mips_opts.fp = 0; | |
14766 | break; | |
14767 | ||
316f5878 | 14768 | case OPTION_FP64: |
0b35dfee | 14769 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14770 | break; |
14771 | ||
351cdf24 MF |
14772 | case OPTION_ODD_SPREG: |
14773 | file_mips_opts.oddspreg = 1; | |
14774 | break; | |
14775 | ||
14776 | case OPTION_NO_ODD_SPREG: | |
14777 | file_mips_opts.oddspreg = 0; | |
14778 | break; | |
14779 | ||
037b32b9 | 14780 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14781 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14782 | break; |
14783 | ||
14784 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14785 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14786 | break; |
14787 | ||
14788 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14789 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14790 | break; |
14791 | ||
14792 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14793 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14794 | break; |
14795 | ||
252b5132 | 14796 | case OPTION_MABI: |
e013f690 | 14797 | if (strcmp (arg, "32") == 0) |
316f5878 | 14798 | mips_abi = O32_ABI; |
e013f690 | 14799 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14800 | mips_abi = O64_ABI; |
e013f690 | 14801 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14802 | mips_abi = N32_ABI; |
e013f690 TS |
14803 | else if (strcmp (arg, "64") == 0) |
14804 | { | |
316f5878 | 14805 | mips_abi = N64_ABI; |
e013f690 | 14806 | if (! support_64bit_objects()) |
1661c76c | 14807 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14808 | "format")); |
14809 | } | |
14810 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14811 | mips_abi = EABI_ABI; |
e013f690 | 14812 | else |
da0e507f TS |
14813 | { |
14814 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14815 | return 0; | |
14816 | } | |
252b5132 RH |
14817 | break; |
14818 | ||
6b76fefe | 14819 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14820 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14821 | break; |
14822 | ||
9ee72ff1 | 14823 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14824 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14825 | break; |
14826 | ||
ecb4347a | 14827 | case OPTION_MDEBUG: |
b34976b6 | 14828 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14829 | break; |
14830 | ||
14831 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14832 | mips_flag_mdebug = FALSE; |
ecb4347a | 14833 | break; |
dcd410fe RO |
14834 | |
14835 | case OPTION_PDR: | |
14836 | mips_flag_pdr = TRUE; | |
14837 | break; | |
14838 | ||
14839 | case OPTION_NO_PDR: | |
14840 | mips_flag_pdr = FALSE; | |
14841 | break; | |
0a44bf69 RS |
14842 | |
14843 | case OPTION_MVXWORKS_PIC: | |
14844 | mips_pic = VXWORKS_PIC; | |
14845 | break; | |
ecb4347a | 14846 | |
ba92f887 MR |
14847 | case OPTION_NAN: |
14848 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14849 | mips_nan2008 = 1; |
ba92f887 | 14850 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14851 | mips_nan2008 = 0; |
ba92f887 MR |
14852 | else |
14853 | { | |
1661c76c | 14854 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14855 | return 0; |
14856 | } | |
14857 | break; | |
14858 | ||
252b5132 RH |
14859 | default: |
14860 | return 0; | |
14861 | } | |
14862 | ||
c67a084a NC |
14863 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14864 | ||
252b5132 RH |
14865 | return 1; |
14866 | } | |
316f5878 | 14867 | \f |
919731af | 14868 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14869 | |
316f5878 | 14870 | static void |
17a2f251 | 14871 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14872 | { |
14873 | if (info != 0) | |
fef14a42 | 14874 | mips_tune = info->cpu; |
316f5878 | 14875 | } |
80cc45a5 | 14876 | |
34ba82a8 | 14877 | |
252b5132 | 14878 | void |
17a2f251 | 14879 | mips_after_parse_args (void) |
e9670677 | 14880 | { |
fef14a42 TS |
14881 | const struct mips_cpu_info *arch_info = 0; |
14882 | const struct mips_cpu_info *tune_info = 0; | |
14883 | ||
e9670677 | 14884 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14885 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14886 | { |
6caf9ef4 | 14887 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14888 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14889 | g_switch_value = 0; |
14890 | } | |
14891 | ||
cac012d6 AO |
14892 | if (mips_abi == NO_ABI) |
14893 | mips_abi = MIPS_DEFAULT_ABI; | |
14894 | ||
919731af | 14895 | /* The following code determines the architecture. |
22923709 RS |
14896 | Similar code was added to GCC 3.3 (see override_options() in |
14897 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14898 | as much as possible. */ | |
e9670677 | 14899 | |
316f5878 | 14900 | if (mips_arch_string != 0) |
fef14a42 | 14901 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14902 | |
0b35dfee | 14903 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14904 | { |
0b35dfee | 14905 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14906 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14907 | the -march selection (if any). */ |
fef14a42 | 14908 | if (arch_info != 0) |
e9670677 | 14909 | { |
316f5878 RS |
14910 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14911 | There's no harm in specifying both as long as the ISA levels | |
14912 | are the same. */ | |
0b35dfee | 14913 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14914 | as_bad (_("-%s conflicts with the other architecture options," |
14915 | " which imply -%s"), | |
0b35dfee | 14916 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14917 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14918 | } |
316f5878 | 14919 | else |
0b35dfee | 14920 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14921 | } |
14922 | ||
fef14a42 | 14923 | if (arch_info == 0) |
95bfe26e MF |
14924 | { |
14925 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14926 | gas_assert (arch_info); | |
14927 | } | |
e9670677 | 14928 | |
fef14a42 | 14929 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14930 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14931 | arch_info->name); |
14932 | ||
919731af | 14933 | file_mips_opts.arch = arch_info->cpu; |
14934 | file_mips_opts.isa = arch_info->isa; | |
14935 | ||
14936 | /* Set up initial mips_opts state. */ | |
14937 | mips_opts = file_mips_opts; | |
14938 | ||
14939 | /* The register size inference code is now placed in | |
14940 | file_mips_check_options. */ | |
fef14a42 | 14941 | |
0b35dfee | 14942 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
14943 | processor. */ | |
fef14a42 TS |
14944 | if (mips_tune_string != 0) |
14945 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14946 | |
fef14a42 TS |
14947 | if (tune_info == 0) |
14948 | mips_set_tune (arch_info); | |
14949 | else | |
14950 | mips_set_tune (tune_info); | |
e9670677 | 14951 | |
ecb4347a | 14952 | if (mips_flag_mdebug < 0) |
e8044f35 | 14953 | mips_flag_mdebug = 0; |
e9670677 MR |
14954 | } |
14955 | \f | |
14956 | void | |
17a2f251 | 14957 | mips_init_after_args (void) |
252b5132 RH |
14958 | { |
14959 | /* initialize opcodes */ | |
14960 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14961 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14962 | } |
14963 | ||
14964 | long | |
17a2f251 | 14965 | md_pcrel_from (fixS *fixP) |
252b5132 | 14966 | { |
a7ebbfdf TS |
14967 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14968 | switch (fixP->fx_r_type) | |
14969 | { | |
df58fc94 RS |
14970 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14971 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14972 | /* Return the address of the delay slot. */ | |
14973 | return addr + 2; | |
14974 | ||
14975 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14976 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 14977 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 14978 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
14979 | case BFD_RELOC_MIPS_21_PCREL_S2: |
14980 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
14981 | case BFD_RELOC_MIPS_JMP: |
14982 | /* Return the address of the delay slot. */ | |
14983 | return addr + 4; | |
df58fc94 | 14984 | |
51f6035b MR |
14985 | case BFD_RELOC_MIPS_18_PCREL_S3: |
14986 | /* Return the aligned address of the doubleword containing | |
14987 | the instruction. */ | |
14988 | return addr & ~7; | |
14989 | ||
a7ebbfdf TS |
14990 | default: |
14991 | return addr; | |
14992 | } | |
252b5132 RH |
14993 | } |
14994 | ||
252b5132 RH |
14995 | /* This is called before the symbol table is processed. In order to |
14996 | work with gcc when using mips-tfile, we must keep all local labels. | |
14997 | However, in other cases, we want to discard them. If we were | |
14998 | called with -g, but we didn't see any debugging information, it may | |
14999 | mean that gcc is smuggling debugging information through to | |
15000 | mips-tfile, in which case we must generate all local labels. */ | |
15001 | ||
15002 | void | |
17a2f251 | 15003 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15004 | { |
15005 | #ifndef NO_ECOFF_DEBUGGING | |
15006 | if (ECOFF_DEBUGGING | |
15007 | && mips_debug != 0 | |
15008 | && ! ecoff_debugging_seen) | |
15009 | flag_keep_locals = 1; | |
15010 | #endif | |
15011 | } | |
15012 | ||
3b91255e | 15013 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15014 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15015 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15016 | relocation operators. | |
15017 | ||
15018 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15019 | expression if: | |
15020 | ||
15021 | (a) it refers to the same symbol; and | |
15022 | (b) the offset applied in the %lo() expression is no lower than | |
15023 | the offset applied in the %got() or %hi(). | |
15024 | ||
15025 | (b) allows us to cope with code like: | |
15026 | ||
15027 | lui $4,%hi(foo) | |
15028 | lh $4,%lo(foo+2)($4) | |
15029 | ||
15030 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15031 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15032 | the high 16 bits. | |
15033 | ||
15034 | When several %lo()s match a particular %got() or %hi(), we use the | |
15035 | following rules to distinguish them: | |
15036 | ||
15037 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15038 | higher offsets. | |
15039 | ||
15040 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15041 | that already have a matching %got() or %hi(). | |
15042 | ||
15043 | (3) later %lo()s are better than earlier %lo()s. | |
15044 | ||
15045 | These rules are applied in order. | |
15046 | ||
15047 | (1) means, among other things, that %lo()s with identical offsets are | |
15048 | chosen if they exist. | |
15049 | ||
15050 | (2) means that we won't associate several high-part relocations with | |
15051 | the same low-part relocation unless there's no alternative. Having | |
15052 | several high parts for the same low part is a GNU extension; this rule | |
15053 | allows careful users to avoid it. | |
15054 | ||
15055 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15056 | with the last high-part relocation being at the front of the list. | |
15057 | It therefore makes sense to choose the last matching low-part | |
15058 | relocation, all other things being equal. It's also easier | |
15059 | to code that way. */ | |
252b5132 RH |
15060 | |
15061 | void | |
17a2f251 | 15062 | mips_frob_file (void) |
252b5132 RH |
15063 | { |
15064 | struct mips_hi_fixup *l; | |
35903be0 | 15065 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15066 | |
15067 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15068 | { | |
15069 | segment_info_type *seginfo; | |
3b91255e RS |
15070 | bfd_boolean matched_lo_p; |
15071 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15072 | |
9c2799c2 | 15073 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15074 | |
5919d012 | 15075 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15076 | there isn't supposed to be a matching LO. Ignore %gots against |
15077 | constants; we'll report an error for those later. */ | |
738e5348 | 15078 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15079 | && !(l->fixp->fx_addsy |
9e009953 | 15080 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15081 | continue; |
15082 | ||
15083 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15084 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15085 | continue; |
15086 | ||
252b5132 | 15087 | seginfo = seg_info (l->seg); |
252b5132 | 15088 | |
3b91255e RS |
15089 | /* Set HI_POS to the position of this relocation in the chain. |
15090 | Set LO_POS to the position of the chosen low-part relocation. | |
15091 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15092 | relocation that matches an immediately-preceding high-part | |
15093 | relocation. */ | |
15094 | hi_pos = NULL; | |
15095 | lo_pos = NULL; | |
15096 | matched_lo_p = FALSE; | |
738e5348 | 15097 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15098 | |
3b91255e RS |
15099 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15100 | { | |
15101 | if (*pos == l->fixp) | |
15102 | hi_pos = pos; | |
15103 | ||
35903be0 | 15104 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15105 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15106 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15107 | && (lo_pos == NULL | |
15108 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15109 | || (!matched_lo_p | |
15110 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15111 | lo_pos = pos; | |
15112 | ||
15113 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15114 | && fixup_has_matching_lo_p (*pos)); | |
15115 | } | |
15116 | ||
15117 | /* If we found a match, remove the high-part relocation from its | |
15118 | current position and insert it before the low-part relocation. | |
15119 | Make the offsets match so that fixup_has_matching_lo_p() | |
15120 | will return true. | |
15121 | ||
15122 | We don't warn about unmatched high-part relocations since some | |
15123 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15124 | instructions. */ | |
15125 | if (lo_pos != NULL) | |
15126 | { | |
15127 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15128 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15129 | { |
3b91255e RS |
15130 | *hi_pos = l->fixp->fx_next; |
15131 | l->fixp->fx_next = *lo_pos; | |
15132 | *lo_pos = l->fixp; | |
252b5132 | 15133 | } |
252b5132 RH |
15134 | } |
15135 | } | |
15136 | } | |
15137 | ||
252b5132 | 15138 | int |
17a2f251 | 15139 | mips_force_relocation (fixS *fixp) |
252b5132 | 15140 | { |
ae6063d4 | 15141 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15142 | return 1; |
15143 | ||
df58fc94 RS |
15144 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15145 | so that the linker relaxation can update targets. */ | |
15146 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15147 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15148 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15149 | return 1; | |
15150 | ||
5caa2b07 MR |
15151 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15152 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15153 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15154 | and BAL to JALX conversion by the linker. */ | |
15155 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15156 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15157 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15158 | && fixp->fx_addsy | |
15159 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15160 | return 1; | |
15161 | ||
7361da2c | 15162 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15163 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15164 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15165 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15166 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15167 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15168 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15169 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15170 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15171 | return 1; | |
15172 | ||
3e722fb5 | 15173 | return 0; |
252b5132 RH |
15174 | } |
15175 | ||
b416ba9b MR |
15176 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15177 | ||
15178 | bfd_boolean | |
15179 | mips_force_relocation_abs (fixS *fixp) | |
15180 | { | |
15181 | if (generic_force_reloc (fixp)) | |
15182 | return TRUE; | |
15183 | ||
15184 | /* These relocations do not have enough bits in the in-place addend | |
15185 | to hold an arbitrary absolute section's offset. */ | |
15186 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15187 | return TRUE; | |
15188 | ||
15189 | return FALSE; | |
15190 | } | |
15191 | ||
b886a2ab RS |
15192 | /* Read the instruction associated with RELOC from BUF. */ |
15193 | ||
15194 | static unsigned int | |
15195 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15196 | { | |
15197 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15198 | return read_compressed_insn (buf, 4); | |
15199 | else | |
15200 | return read_insn (buf); | |
15201 | } | |
15202 | ||
15203 | /* Write instruction INSN to BUF, given that it has been relocated | |
15204 | by RELOC. */ | |
15205 | ||
15206 | static void | |
15207 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15208 | unsigned long insn) | |
15209 | { | |
15210 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15211 | write_compressed_insn (buf, insn, 4); | |
15212 | else | |
15213 | write_insn (buf, insn); | |
15214 | } | |
15215 | ||
9d862524 MR |
15216 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15217 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15218 | ||
15219 | static bfd_boolean | |
15220 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15221 | { | |
15222 | unsigned long opcode; | |
15223 | int other; | |
15224 | char *buf; | |
15225 | ||
15226 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15227 | return FALSE; | |
15228 | ||
15229 | other = S_GET_OTHER (fixP->fx_addsy); | |
15230 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15231 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15232 | switch (fixP->fx_r_type) | |
15233 | { | |
15234 | case BFD_RELOC_MIPS_JMP: | |
15235 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15236 | case BFD_RELOC_MICROMIPS_JMP: | |
15237 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15238 | default: | |
15239 | return FALSE; | |
15240 | } | |
15241 | } | |
15242 | ||
15243 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15244 | jump to a symbol in the same ISA mode. */ | |
15245 | ||
15246 | static bfd_boolean | |
15247 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15248 | { | |
15249 | unsigned long opcode; | |
15250 | int other; | |
15251 | char *buf; | |
15252 | ||
15253 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15254 | return FALSE; | |
15255 | ||
15256 | other = S_GET_OTHER (fixP->fx_addsy); | |
15257 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15258 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15259 | switch (fixP->fx_r_type) | |
15260 | { | |
15261 | case BFD_RELOC_MIPS_JMP: | |
15262 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15263 | case BFD_RELOC_MIPS16_JMP: | |
15264 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15265 | case BFD_RELOC_MICROMIPS_JMP: | |
15266 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15267 | default: | |
15268 | return FALSE; | |
15269 | } | |
15270 | } | |
15271 | ||
15272 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15273 | to a symbol whose value plus addend is not aligned according to the | |
15274 | ultimate (after linker relaxation) jump instruction's immediate field | |
15275 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15276 | regular MIPS code, to (1 << 2). */ | |
15277 | ||
15278 | static bfd_boolean | |
15279 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15280 | { | |
15281 | bfd_boolean micro_to_mips_p; | |
15282 | valueT val; | |
15283 | int other; | |
15284 | ||
15285 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15286 | return FALSE; | |
15287 | ||
15288 | other = S_GET_OTHER (fixP->fx_addsy); | |
15289 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15290 | val += fixP->fx_offset; | |
15291 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15292 | && !ELF_ST_IS_MICROMIPS (other)); | |
15293 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15294 | != ELF_ST_IS_COMPRESSED (other)); | |
15295 | } | |
15296 | ||
15297 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15298 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15299 | symbols check the ISA bit instead. |
15300 | ||
15301 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15302 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15303 | MIPS symbols and associated with BAL instructions as these instructions | |
15304 | may be be converted to JALX by the linker. */ | |
9d862524 MR |
15305 | |
15306 | static bfd_boolean | |
15307 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15308 | { | |
15309 | bfd_boolean absolute_p; | |
15310 | unsigned long opcode; | |
15311 | asection *symsec; | |
15312 | valueT val; | |
15313 | int other; | |
15314 | char *buf; | |
15315 | ||
8b10b0b3 MR |
15316 | if (mips_ignore_branch_isa) |
15317 | return FALSE; | |
15318 | ||
9d862524 MR |
15319 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15320 | return FALSE; | |
15321 | ||
15322 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15323 | absolute_p = bfd_is_abs_section (symsec); | |
15324 | ||
15325 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15326 | other = S_GET_OTHER (fixP->fx_addsy); | |
15327 | ||
15328 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15329 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15330 | switch (fixP->fx_r_type) | |
15331 | { | |
15332 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15333 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15334 | && opcode != 0x0411); | |
15335 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15336 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15337 | && opcode != 0x4060); | |
9d862524 MR |
15338 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15339 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15340 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15341 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15342 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15343 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15344 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15345 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15346 | default: | |
15347 | abort (); | |
15348 | } | |
15349 | } | |
15350 | ||
15351 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15352 | branch instruction pointed to by FIXP is not aligned according to the | |
15353 | branch instruction's immediate field requirement. We need the addend | |
15354 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15355 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15356 | won't be set in the symbol's value then. */ | |
15357 | ||
15358 | static bfd_boolean | |
15359 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15360 | { | |
15361 | bfd_boolean absolute_p; | |
15362 | asection *symsec; | |
15363 | valueT isa_bit; | |
15364 | valueT val; | |
15365 | valueT off; | |
15366 | int other; | |
15367 | ||
15368 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15369 | return FALSE; | |
15370 | ||
15371 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15372 | absolute_p = bfd_is_abs_section (symsec); | |
15373 | ||
15374 | val = S_GET_VALUE (fixP->fx_addsy); | |
15375 | other = S_GET_OTHER (fixP->fx_addsy); | |
15376 | off = fixP->fx_offset; | |
15377 | ||
15378 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15379 | val |= ELF_ST_IS_COMPRESSED (other); | |
15380 | val += off; | |
15381 | return (val & 0x3) != isa_bit; | |
15382 | } | |
15383 | ||
15384 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15385 | and its calculated value VAL. */ | |
15386 | ||
15387 | static void | |
15388 | fix_validate_branch (fixS *fixP, valueT val) | |
15389 | { | |
15390 | if (fixP->fx_done && (val & 0x3) != 0) | |
15391 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15392 | _("branch to misaligned address (0x%lx)"), | |
15393 | (long) (val + md_pcrel_from (fixP))); | |
15394 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15395 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15396 | _("branch to a symbol in another ISA mode")); | |
15397 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15398 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15399 | _("branch to misaligned address (0x%lx)"), | |
15400 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15401 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15402 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15403 | _("cannot encode misaligned addend " | |
15404 | "in the relocatable field (0x%lx)"), | |
15405 | (long) fixP->fx_offset); | |
15406 | } | |
15407 | ||
252b5132 RH |
15408 | /* Apply a fixup to the object file. */ |
15409 | ||
94f592af | 15410 | void |
55cf6793 | 15411 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15412 | { |
4d68580a | 15413 | char *buf; |
b886a2ab | 15414 | unsigned long insn; |
a7ebbfdf | 15415 | reloc_howto_type *howto; |
252b5132 | 15416 | |
d56a8dda RS |
15417 | if (fixP->fx_pcrel) |
15418 | switch (fixP->fx_r_type) | |
15419 | { | |
15420 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15421 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15422 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15423 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15424 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15425 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15426 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15427 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15428 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15429 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15430 | case BFD_RELOC_HI16_S_PCREL: | |
15431 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15432 | break; |
15433 | ||
15434 | case BFD_RELOC_32: | |
15435 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15436 | break; | |
15437 | ||
15438 | default: | |
15439 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15440 | _("PC-relative reference to a different section")); | |
15441 | break; | |
15442 | } | |
15443 | ||
15444 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15445 | that have no MIPS ELF equivalent. */ | |
15446 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15447 | { | |
15448 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15449 | if (!howto) | |
15450 | return; | |
15451 | } | |
65551fa4 | 15452 | |
df58fc94 RS |
15453 | gas_assert (fixP->fx_size == 2 |
15454 | || fixP->fx_size == 4 | |
d56a8dda | 15455 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15456 | || fixP->fx_r_type == BFD_RELOC_16 |
15457 | || fixP->fx_r_type == BFD_RELOC_64 | |
15458 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15459 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15460 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15461 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15462 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15463 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15464 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15465 | |
4d68580a | 15466 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15467 | |
b1dca8ee RS |
15468 | /* Don't treat parts of a composite relocation as done. There are two |
15469 | reasons for this: | |
15470 | ||
15471 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15472 | should nevertheless be emitted if the first part is. | |
15473 | ||
15474 | (2) In normal usage, composite relocations are never assembly-time | |
15475 | constants. The easiest way of dealing with the pathological | |
15476 | exceptions is to generate a relocation against STN_UNDEF and | |
15477 | leave everything up to the linker. */ | |
3994f87e | 15478 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15479 | fixP->fx_done = 1; |
15480 | ||
15481 | switch (fixP->fx_r_type) | |
15482 | { | |
3f98094e DJ |
15483 | case BFD_RELOC_MIPS_TLS_GD: |
15484 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15485 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15486 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15487 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15488 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15489 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15490 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15491 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15492 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15493 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15494 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15495 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15496 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15497 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15498 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15499 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15500 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15501 | case BFD_RELOC_MIPS16_TLS_GD: |
15502 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15503 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15504 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15505 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15506 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15507 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15508 | if (fixP->fx_addsy) |
15509 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15510 | else | |
15511 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15512 | _("TLS relocation against a constant")); | |
15513 | break; | |
3f98094e | 15514 | |
252b5132 | 15515 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15516 | case BFD_RELOC_MIPS16_JMP: |
15517 | case BFD_RELOC_MICROMIPS_JMP: | |
15518 | { | |
15519 | int shift; | |
15520 | ||
15521 | gas_assert (!fixP->fx_done); | |
15522 | ||
15523 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15524 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15525 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15526 | shift = 1; | |
15527 | else | |
15528 | shift = 2; | |
15529 | ||
15530 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15531 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15532 | _("jump to a symbol in another ISA mode")); | |
15533 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15534 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15535 | _("JALX to a symbol in the same ISA mode")); | |
15536 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15537 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15538 | _("jump to misaligned address (0x%lx)"), | |
15539 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15540 | + fixP->fx_offset)); | |
15541 | else if (HAVE_IN_PLACE_ADDENDS | |
15542 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15543 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15544 | _("cannot encode misaligned addend " | |
15545 | "in the relocatable field (0x%lx)"), | |
15546 | (long) fixP->fx_offset); | |
15547 | } | |
15548 | /* Fall through. */ | |
15549 | ||
e369bcce TS |
15550 | case BFD_RELOC_MIPS_SHIFT5: |
15551 | case BFD_RELOC_MIPS_SHIFT6: | |
15552 | case BFD_RELOC_MIPS_GOT_DISP: | |
15553 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15554 | case BFD_RELOC_MIPS_GOT_OFST: | |
15555 | case BFD_RELOC_MIPS_SUB: | |
15556 | case BFD_RELOC_MIPS_INSERT_A: | |
15557 | case BFD_RELOC_MIPS_INSERT_B: | |
15558 | case BFD_RELOC_MIPS_DELETE: | |
15559 | case BFD_RELOC_MIPS_HIGHEST: | |
15560 | case BFD_RELOC_MIPS_HIGHER: | |
15561 | case BFD_RELOC_MIPS_SCN_DISP: | |
15562 | case BFD_RELOC_MIPS_REL16: | |
15563 | case BFD_RELOC_MIPS_RELGOT: | |
15564 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15565 | case BFD_RELOC_HI16: |
15566 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15567 | case BFD_RELOC_LO16: |
cdf6fd85 | 15568 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15569 | case BFD_RELOC_MIPS_LITERAL: |
15570 | case BFD_RELOC_MIPS_CALL16: | |
15571 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15572 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15573 | case BFD_RELOC_MIPS_GOT_HI16: |
15574 | case BFD_RELOC_MIPS_GOT_LO16: | |
15575 | case BFD_RELOC_MIPS_CALL_HI16: | |
15576 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15577 | case BFD_RELOC_HI16_S_PCREL: |
15578 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15579 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15580 | case BFD_RELOC_MIPS16_GOT16: |
15581 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15582 | case BFD_RELOC_MIPS16_HI16: |
15583 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15584 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15585 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15586 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15587 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15588 | case BFD_RELOC_MICROMIPS_SUB: | |
15589 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15590 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15591 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15592 | case BFD_RELOC_MICROMIPS_JALR: | |
15593 | case BFD_RELOC_MICROMIPS_HI16: | |
15594 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15595 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15596 | case BFD_RELOC_MICROMIPS_GPREL16: |
15597 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15598 | case BFD_RELOC_MICROMIPS_CALL16: | |
15599 | case BFD_RELOC_MICROMIPS_GOT16: | |
15600 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15601 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15602 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15603 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15604 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15605 | if (fixP->fx_done) |
15606 | { | |
15607 | offsetT value; | |
15608 | ||
15609 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15610 | { | |
15611 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15612 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15613 | insn |= mips16_immed_extend (value, 16); | |
15614 | else | |
15615 | insn |= (value & 0xffff); | |
15616 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15617 | } | |
15618 | else | |
15619 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15620 | _("unsupported constant in relocation")); |
b886a2ab | 15621 | } |
252b5132 RH |
15622 | break; |
15623 | ||
252b5132 RH |
15624 | case BFD_RELOC_64: |
15625 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15626 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15627 | if (fixP->fx_done) |
252b5132 RH |
15628 | { |
15629 | if (8 <= sizeof (valueT)) | |
4d68580a | 15630 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15631 | else |
15632 | { | |
a7ebbfdf | 15633 | valueT hiv; |
252b5132 | 15634 | |
a7ebbfdf | 15635 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15636 | hiv = 0xffffffff; |
15637 | else | |
15638 | hiv = 0; | |
4d68580a RS |
15639 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15640 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15641 | } |
15642 | } | |
15643 | break; | |
15644 | ||
056350c6 | 15645 | case BFD_RELOC_RVA: |
252b5132 | 15646 | case BFD_RELOC_32: |
b47468a6 | 15647 | case BFD_RELOC_32_PCREL: |
252b5132 | 15648 | case BFD_RELOC_16: |
d56a8dda | 15649 | case BFD_RELOC_8: |
252b5132 | 15650 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15651 | value now. This can happen if we have a .word which is not |
15652 | resolved when it appears but is later defined. */ | |
252b5132 | 15653 | if (fixP->fx_done) |
4d68580a | 15654 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15655 | break; |
15656 | ||
7361da2c | 15657 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15658 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15659 | if (!fixP->fx_done) |
15660 | break; | |
15661 | ||
15662 | if (*valP + 0x400000 <= 0x7fffff) | |
15663 | { | |
15664 | insn = read_insn (buf); | |
15665 | insn |= (*valP >> 2) & 0x1fffff; | |
15666 | write_insn (buf, insn); | |
15667 | } | |
15668 | else | |
15669 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15670 | _("branch out of range")); | |
15671 | break; | |
15672 | ||
7361da2c | 15673 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15674 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15675 | if (!fixP->fx_done) |
15676 | break; | |
7361da2c | 15677 | |
41947d9e MR |
15678 | if (*valP + 0x8000000 <= 0xfffffff) |
15679 | { | |
15680 | insn = read_insn (buf); | |
15681 | insn |= (*valP >> 2) & 0x3ffffff; | |
15682 | write_insn (buf, insn); | |
15683 | } | |
15684 | else | |
15685 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15686 | _("branch out of range")); | |
7361da2c AB |
15687 | break; |
15688 | ||
15689 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15690 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15691 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15692 | _("PC-relative access using misaligned symbol (%lx)"), |
15693 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15694 | if ((fixP->fx_offset & 0x7) != 0) | |
15695 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15696 | _("PC-relative access using misaligned offset (%lx)"), | |
15697 | (long) fixP->fx_offset); | |
41947d9e MR |
15698 | if (!fixP->fx_done) |
15699 | break; | |
7361da2c | 15700 | |
41947d9e MR |
15701 | if (*valP + 0x100000 <= 0x1fffff) |
15702 | { | |
15703 | insn = read_insn (buf); | |
15704 | insn |= (*valP >> 3) & 0x3ffff; | |
15705 | write_insn (buf, insn); | |
15706 | } | |
15707 | else | |
15708 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15709 | _("PC-relative access out of range")); | |
7361da2c AB |
15710 | break; |
15711 | ||
15712 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15713 | if ((*valP & 0x3) != 0) | |
15714 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15715 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15716 | (long) *valP); |
41947d9e MR |
15717 | if (!fixP->fx_done) |
15718 | break; | |
7361da2c | 15719 | |
41947d9e MR |
15720 | if (*valP + 0x100000 <= 0x1fffff) |
15721 | { | |
15722 | insn = read_insn (buf); | |
15723 | insn |= (*valP >> 2) & 0x7ffff; | |
15724 | write_insn (buf, insn); | |
15725 | } | |
15726 | else | |
15727 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15728 | _("PC-relative access out of range")); | |
7361da2c AB |
15729 | break; |
15730 | ||
252b5132 | 15731 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15732 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15733 | |
54f4ddb3 TS |
15734 | /* We need to save the bits in the instruction since fixup_segment() |
15735 | might be deleting the relocation entry (i.e., a branch within | |
15736 | the current segment). */ | |
a7ebbfdf | 15737 | if (! fixP->fx_done) |
bb2d6cd7 | 15738 | break; |
252b5132 | 15739 | |
54f4ddb3 | 15740 | /* Update old instruction data. */ |
4d68580a | 15741 | insn = read_insn (buf); |
252b5132 | 15742 | |
a7ebbfdf TS |
15743 | if (*valP + 0x20000 <= 0x3ffff) |
15744 | { | |
15745 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15746 | write_insn (buf, insn); |
a7ebbfdf | 15747 | } |
ce8ad872 | 15748 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15749 | && fixP->fx_done |
15750 | && fixP->fx_frag->fr_address >= text_section->vma | |
15751 | && (fixP->fx_frag->fr_address | |
587aac4e | 15752 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15753 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15754 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15755 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15756 | { |
15757 | /* The branch offset is too large. If this is an | |
15758 | unconditional branch, and we are not generating PIC code, | |
15759 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15760 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15761 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15762 | else |
a7ebbfdf TS |
15763 | insn = 0x08000000; /* j */ |
15764 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15765 | fixP->fx_done = 0; | |
15766 | fixP->fx_addsy = section_symbol (text_section); | |
15767 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15768 | write_insn (buf, insn); |
a7ebbfdf TS |
15769 | } |
15770 | else | |
15771 | { | |
15772 | /* If we got here, we have branch-relaxation disabled, | |
15773 | and there's nothing we can do to fix this instruction | |
15774 | without turning it into a longer sequence. */ | |
15775 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15776 | _("branch out of range")); |
252b5132 | 15777 | } |
252b5132 RH |
15778 | break; |
15779 | ||
c9775dde | 15780 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15781 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15782 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15783 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15784 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15785 | if (fix_bad_cross_mode_branch_p (fixP)) |
15786 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15787 | _("branch to a symbol in another ISA mode")); | |
15788 | else if (fixP->fx_addsy | |
15789 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15790 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15791 | && (fixP->fx_offset & 0x1) != 0) | |
15792 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15793 | _("branch to misaligned address (0x%lx)"), | |
15794 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15795 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15797 | _("cannot encode misaligned addend " | |
15798 | "in the relocatable field (0x%lx)"), | |
15799 | (long) fixP->fx_offset); | |
df58fc94 RS |
15800 | break; |
15801 | ||
252b5132 RH |
15802 | case BFD_RELOC_VTABLE_INHERIT: |
15803 | fixP->fx_done = 0; | |
15804 | if (fixP->fx_addsy | |
15805 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15806 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15807 | S_SET_WEAK (fixP->fx_addsy); | |
15808 | break; | |
15809 | ||
2f0c68f2 | 15810 | case BFD_RELOC_NONE: |
252b5132 RH |
15811 | case BFD_RELOC_VTABLE_ENTRY: |
15812 | fixP->fx_done = 0; | |
15813 | break; | |
15814 | ||
15815 | default: | |
b37df7c4 | 15816 | abort (); |
252b5132 | 15817 | } |
a7ebbfdf TS |
15818 | |
15819 | /* Remember value for tc_gen_reloc. */ | |
15820 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15821 | } |
15822 | ||
252b5132 | 15823 | static symbolS * |
17a2f251 | 15824 | get_symbol (void) |
252b5132 RH |
15825 | { |
15826 | int c; | |
15827 | char *name; | |
15828 | symbolS *p; | |
15829 | ||
d02603dc | 15830 | c = get_symbol_name (&name); |
252b5132 | 15831 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15832 | (void) restore_line_pointer (c); |
252b5132 RH |
15833 | return p; |
15834 | } | |
15835 | ||
742a56fe RS |
15836 | /* Align the current frag to a given power of two. If a particular |
15837 | fill byte should be used, FILL points to an integer that contains | |
15838 | that byte, otherwise FILL is null. | |
15839 | ||
462427c4 RS |
15840 | This function used to have the comment: |
15841 | ||
15842 | The MIPS assembler also automatically adjusts any preceding label. | |
15843 | ||
15844 | The implementation therefore applied the adjustment to a maximum of | |
15845 | one label. However, other label adjustments are applied to batches | |
15846 | of labels, and adjusting just one caused problems when new labels | |
15847 | were added for the sake of debugging or unwind information. | |
15848 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15849 | |
15850 | static void | |
462427c4 | 15851 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15852 | { |
7d10b47d | 15853 | mips_emit_delays (); |
df58fc94 | 15854 | mips_record_compressed_mode (); |
742a56fe RS |
15855 | if (fill == NULL && subseg_text_p (now_seg)) |
15856 | frag_align_code (to, 0); | |
15857 | else | |
15858 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15859 | record_alignment (now_seg, to); |
462427c4 | 15860 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15861 | } |
15862 | ||
15863 | /* Align to a given power of two. .align 0 turns off the automatic | |
15864 | alignment used by the data creating pseudo-ops. */ | |
15865 | ||
15866 | static void | |
17a2f251 | 15867 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15868 | { |
742a56fe | 15869 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15870 | long max_alignment = 28; |
252b5132 | 15871 | |
54f4ddb3 | 15872 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15873 | to the aligned address. |
54f4ddb3 | 15874 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15875 | a .align pseudo instruction. |
54f4ddb3 | 15876 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15877 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15878 | We don't. */ |
252b5132 RH |
15879 | |
15880 | temp = get_absolute_expression (); | |
15881 | if (temp > max_alignment) | |
1661c76c | 15882 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15883 | else if (temp < 0) |
15884 | { | |
1661c76c | 15885 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15886 | temp = 0; |
15887 | } | |
15888 | if (*input_line_pointer == ',') | |
15889 | { | |
f9419b05 | 15890 | ++input_line_pointer; |
742a56fe RS |
15891 | fill_value = get_absolute_expression (); |
15892 | fill_ptr = &fill_value; | |
252b5132 RH |
15893 | } |
15894 | else | |
742a56fe | 15895 | fill_ptr = 0; |
252b5132 RH |
15896 | if (temp) |
15897 | { | |
a8dbcb85 TS |
15898 | segment_info_type *si = seg_info (now_seg); |
15899 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15900 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15901 | auto_align = 1; |
462427c4 | 15902 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15903 | } |
15904 | else | |
15905 | { | |
15906 | auto_align = 0; | |
15907 | } | |
15908 | ||
15909 | demand_empty_rest_of_line (); | |
15910 | } | |
15911 | ||
252b5132 | 15912 | static void |
17a2f251 | 15913 | s_change_sec (int sec) |
252b5132 RH |
15914 | { |
15915 | segT seg; | |
15916 | ||
252b5132 RH |
15917 | /* The ELF backend needs to know that we are changing sections, so |
15918 | that .previous works correctly. We could do something like check | |
b6ff326e | 15919 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15920 | as it would not be appropriate to use it in the section changing |
15921 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15922 | This should be cleaner, somehow. */ | |
f3ded42a | 15923 | obj_elf_section_change_hook (); |
252b5132 | 15924 | |
7d10b47d | 15925 | mips_emit_delays (); |
6a32d874 | 15926 | |
252b5132 RH |
15927 | switch (sec) |
15928 | { | |
15929 | case 't': | |
15930 | s_text (0); | |
15931 | break; | |
15932 | case 'd': | |
15933 | s_data (0); | |
15934 | break; | |
15935 | case 'b': | |
15936 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15937 | demand_empty_rest_of_line (); | |
15938 | break; | |
15939 | ||
15940 | case 'r': | |
4d0d148d TS |
15941 | seg = subseg_new (RDATA_SECTION_NAME, |
15942 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15943 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15944 | | SEC_READONLY | SEC_RELOC | |
15945 | | SEC_DATA)); | |
15946 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15947 | record_alignment (seg, 4); | |
4d0d148d | 15948 | demand_empty_rest_of_line (); |
252b5132 RH |
15949 | break; |
15950 | ||
15951 | case 's': | |
4d0d148d | 15952 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
15953 | bfd_set_section_flags (stdoutput, seg, |
15954 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
15955 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15956 | record_alignment (seg, 4); | |
4d0d148d TS |
15957 | demand_empty_rest_of_line (); |
15958 | break; | |
998b3c36 MR |
15959 | |
15960 | case 'B': | |
15961 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15962 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
15963 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15964 | record_alignment (seg, 4); | |
998b3c36 MR |
15965 | demand_empty_rest_of_line (); |
15966 | break; | |
252b5132 RH |
15967 | } |
15968 | ||
15969 | auto_align = 1; | |
15970 | } | |
b34976b6 | 15971 | |
cca86cc8 | 15972 | void |
17a2f251 | 15973 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15974 | { |
d02603dc | 15975 | char *saved_ilp; |
cca86cc8 | 15976 | char *section_name; |
d02603dc | 15977 | char c, endc; |
684022ea | 15978 | char next_c = 0; |
cca86cc8 SC |
15979 | int section_type; |
15980 | int section_flag; | |
15981 | int section_entry_size; | |
15982 | int section_alignment; | |
b34976b6 | 15983 | |
d02603dc NC |
15984 | saved_ilp = input_line_pointer; |
15985 | endc = get_symbol_name (§ion_name); | |
15986 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 15987 | if (c) |
d02603dc | 15988 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 15989 | |
4cf0dd0d TS |
15990 | /* Do we have .section Name<,"flags">? */ |
15991 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15992 | { |
d02603dc NC |
15993 | /* Just after name is now '\0'. */ |
15994 | (void) restore_line_pointer (endc); | |
15995 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
15996 | obj_elf_section (ignore); |
15997 | return; | |
15998 | } | |
d02603dc NC |
15999 | |
16000 | section_name = xstrdup (section_name); | |
16001 | c = restore_line_pointer (endc); | |
16002 | ||
cca86cc8 SC |
16003 | input_line_pointer++; |
16004 | ||
16005 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16006 | if (c == ',') | |
16007 | section_type = get_absolute_expression (); | |
16008 | else | |
16009 | section_type = 0; | |
d02603dc | 16010 | |
cca86cc8 SC |
16011 | if (*input_line_pointer++ == ',') |
16012 | section_flag = get_absolute_expression (); | |
16013 | else | |
16014 | section_flag = 0; | |
d02603dc | 16015 | |
cca86cc8 SC |
16016 | if (*input_line_pointer++ == ',') |
16017 | section_entry_size = get_absolute_expression (); | |
16018 | else | |
16019 | section_entry_size = 0; | |
d02603dc | 16020 | |
cca86cc8 SC |
16021 | if (*input_line_pointer++ == ',') |
16022 | section_alignment = get_absolute_expression (); | |
16023 | else | |
16024 | section_alignment = 0; | |
d02603dc | 16025 | |
87975d2a AM |
16026 | /* FIXME: really ignore? */ |
16027 | (void) section_alignment; | |
cca86cc8 | 16028 | |
8ab8a5c8 RS |
16029 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16030 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16031 | traditionally had to fall back on the more common @progbits instead. | |
16032 | ||
16033 | There's nothing really harmful in this, since bfd will correct | |
16034 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16035 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16036 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16037 | ||
16038 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16039 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16040 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16041 | generic type-checking code. */ | |
16042 | if (section_type == SHT_MIPS_DWARF) | |
16043 | section_type = SHT_PROGBITS; | |
16044 | ||
a91e1603 | 16045 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16046 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16047 | |
16048 | if (now_seg->name != section_name) | |
16049 | free (section_name); | |
cca86cc8 | 16050 | } |
252b5132 RH |
16051 | |
16052 | void | |
17a2f251 | 16053 | mips_enable_auto_align (void) |
252b5132 RH |
16054 | { |
16055 | auto_align = 1; | |
16056 | } | |
16057 | ||
16058 | static void | |
17a2f251 | 16059 | s_cons (int log_size) |
252b5132 | 16060 | { |
a8dbcb85 TS |
16061 | segment_info_type *si = seg_info (now_seg); |
16062 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16063 | |
7d10b47d | 16064 | mips_emit_delays (); |
252b5132 | 16065 | if (log_size > 0 && auto_align) |
462427c4 | 16066 | mips_align (log_size, 0, l); |
252b5132 | 16067 | cons (1 << log_size); |
a1facbec | 16068 | mips_clear_insn_labels (); |
252b5132 RH |
16069 | } |
16070 | ||
16071 | static void | |
17a2f251 | 16072 | s_float_cons (int type) |
252b5132 | 16073 | { |
a8dbcb85 TS |
16074 | segment_info_type *si = seg_info (now_seg); |
16075 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16076 | |
7d10b47d | 16077 | mips_emit_delays (); |
252b5132 RH |
16078 | |
16079 | if (auto_align) | |
49309057 ILT |
16080 | { |
16081 | if (type == 'd') | |
462427c4 | 16082 | mips_align (3, 0, l); |
49309057 | 16083 | else |
462427c4 | 16084 | mips_align (2, 0, l); |
49309057 | 16085 | } |
252b5132 | 16086 | |
252b5132 | 16087 | float_cons (type); |
a1facbec | 16088 | mips_clear_insn_labels (); |
252b5132 RH |
16089 | } |
16090 | ||
16091 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16092 | permitted to say | |
16093 | .globl foo .text | |
16094 | where foo is an undefined symbol, to mean that foo should be | |
16095 | considered to be the address of a function. */ | |
16096 | ||
16097 | static void | |
17a2f251 | 16098 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16099 | { |
16100 | char *name; | |
16101 | int c; | |
16102 | symbolS *symbolP; | |
16103 | flagword flag; | |
16104 | ||
8a06b769 | 16105 | do |
252b5132 | 16106 | { |
d02603dc | 16107 | c = get_symbol_name (&name); |
8a06b769 TS |
16108 | symbolP = symbol_find_or_make (name); |
16109 | S_SET_EXTERNAL (symbolP); | |
16110 | ||
252b5132 | 16111 | *input_line_pointer = c; |
d02603dc | 16112 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16113 | |
8a06b769 TS |
16114 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16115 | being a function is apparently labelled as being an object. */ | |
16116 | flag = BSF_OBJECT; | |
252b5132 | 16117 | |
8a06b769 TS |
16118 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16119 | && (*input_line_pointer != ',')) | |
16120 | { | |
16121 | char *secname; | |
16122 | asection *sec; | |
16123 | ||
d02603dc | 16124 | c = get_symbol_name (&secname); |
8a06b769 TS |
16125 | sec = bfd_get_section_by_name (stdoutput, secname); |
16126 | if (sec == NULL) | |
16127 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16128 | (void) restore_line_pointer (c); |
8a06b769 TS |
16129 | |
16130 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16131 | flag = BSF_FUNCTION; | |
16132 | } | |
16133 | ||
16134 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16135 | ||
16136 | c = *input_line_pointer; | |
16137 | if (c == ',') | |
16138 | { | |
16139 | input_line_pointer++; | |
16140 | SKIP_WHITESPACE (); | |
16141 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16142 | c = '\n'; | |
16143 | } | |
16144 | } | |
16145 | while (c == ','); | |
252b5132 | 16146 | |
252b5132 RH |
16147 | demand_empty_rest_of_line (); |
16148 | } | |
16149 | ||
16150 | static void | |
17a2f251 | 16151 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16152 | { |
16153 | char *opt; | |
16154 | char c; | |
16155 | ||
d02603dc | 16156 | c = get_symbol_name (&opt); |
252b5132 RH |
16157 | |
16158 | if (*opt == 'O') | |
16159 | { | |
16160 | /* FIXME: What does this mean? */ | |
16161 | } | |
41a1578e | 16162 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16163 | { |
16164 | int i; | |
16165 | ||
16166 | i = atoi (opt + 3); | |
668c5ebc MR |
16167 | if (i != 0 && i != 2) |
16168 | as_bad (_(".option pic%d not supported"), i); | |
16169 | else if (mips_pic == VXWORKS_PIC) | |
16170 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16171 | else if (i == 0) | |
252b5132 RH |
16172 | mips_pic = NO_PIC; |
16173 | else if (i == 2) | |
143d77c5 | 16174 | { |
8b828383 | 16175 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16176 | mips_abicalls = TRUE; |
16177 | } | |
252b5132 | 16178 | |
4d0d148d | 16179 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16180 | { |
16181 | if (g_switch_seen && g_switch_value != 0) | |
16182 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16183 | g_switch_value = 0; | |
16184 | bfd_set_gp_size (stdoutput, 0); | |
16185 | } | |
16186 | } | |
16187 | else | |
1661c76c | 16188 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16189 | |
d02603dc | 16190 | (void) restore_line_pointer (c); |
252b5132 RH |
16191 | demand_empty_rest_of_line (); |
16192 | } | |
16193 | ||
16194 | /* This structure is used to hold a stack of .set values. */ | |
16195 | ||
e972090a NC |
16196 | struct mips_option_stack |
16197 | { | |
252b5132 RH |
16198 | struct mips_option_stack *next; |
16199 | struct mips_set_options options; | |
16200 | }; | |
16201 | ||
16202 | static struct mips_option_stack *mips_opts_stack; | |
16203 | ||
22522f88 MR |
16204 | /* Return status for .set/.module option handling. */ |
16205 | ||
16206 | enum code_option_type | |
16207 | { | |
16208 | /* Unrecognized option. */ | |
16209 | OPTION_TYPE_BAD = -1, | |
16210 | ||
16211 | /* Ordinary option. */ | |
16212 | OPTION_TYPE_NORMAL, | |
16213 | ||
16214 | /* ISA changing option. */ | |
16215 | OPTION_TYPE_ISA | |
16216 | }; | |
16217 | ||
16218 | /* Handle common .set/.module options. Return status indicating option | |
16219 | type. */ | |
16220 | ||
16221 | static enum code_option_type | |
919731af | 16222 | parse_code_option (char * name) |
252b5132 | 16223 | { |
22522f88 | 16224 | bfd_boolean isa_set = FALSE; |
c6278170 | 16225 | const struct mips_ase *ase; |
22522f88 | 16226 | |
919731af | 16227 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16228 | { |
16229 | char *s = name + 3; | |
16230 | ||
16231 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16232 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16233 | } |
252b5132 | 16234 | else if (strcmp (name, "at") == 0) |
919731af | 16235 | mips_opts.at = ATREG; |
252b5132 | 16236 | else if (strcmp (name, "noat") == 0) |
919731af | 16237 | mips_opts.at = ZERO; |
252b5132 | 16238 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16239 | mips_opts.nomove = 0; |
252b5132 | 16240 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16241 | mips_opts.nomove = 1; |
252b5132 | 16242 | else if (strcmp (name, "bopt") == 0) |
919731af | 16243 | mips_opts.nobopt = 0; |
252b5132 | 16244 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16245 | mips_opts.nobopt = 1; |
ad3fea08 | 16246 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16247 | mips_opts.gp = 32; |
ad3fea08 | 16248 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16249 | mips_opts.gp = 64; |
ad3fea08 | 16250 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16251 | mips_opts.fp = 32; |
351cdf24 MF |
16252 | else if (strcmp (name, "fp=xx") == 0) |
16253 | mips_opts.fp = 0; | |
ad3fea08 | 16254 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16255 | mips_opts.fp = 64; |
037b32b9 AN |
16256 | else if (strcmp (name, "softfloat") == 0) |
16257 | mips_opts.soft_float = 1; | |
16258 | else if (strcmp (name, "hardfloat") == 0) | |
16259 | mips_opts.soft_float = 0; | |
16260 | else if (strcmp (name, "singlefloat") == 0) | |
16261 | mips_opts.single_float = 1; | |
16262 | else if (strcmp (name, "doublefloat") == 0) | |
16263 | mips_opts.single_float = 0; | |
351cdf24 MF |
16264 | else if (strcmp (name, "nooddspreg") == 0) |
16265 | mips_opts.oddspreg = 0; | |
16266 | else if (strcmp (name, "oddspreg") == 0) | |
16267 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16268 | else if (strcmp (name, "mips16") == 0 |
16269 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16270 | mips_opts.mips16 = 1; |
252b5132 RH |
16271 | else if (strcmp (name, "nomips16") == 0 |
16272 | || strcmp (name, "noMIPS-16") == 0) | |
16273 | mips_opts.mips16 = 0; | |
df58fc94 | 16274 | else if (strcmp (name, "micromips") == 0) |
919731af | 16275 | mips_opts.micromips = 1; |
df58fc94 RS |
16276 | else if (strcmp (name, "nomicromips") == 0) |
16277 | mips_opts.micromips = 0; | |
c6278170 RS |
16278 | else if (name[0] == 'n' |
16279 | && name[1] == 'o' | |
16280 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16281 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16282 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16283 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16284 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16285 | { |
1a2c1fad CD |
16286 | /* Permit the user to change the ISA and architecture on the fly. |
16287 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16288 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16289 | { |
16290 | const struct mips_cpu_info *p; | |
16291 | ||
919731af | 16292 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16293 | if (!p) |
16294 | as_bad (_("unknown architecture %s"), name + 5); | |
16295 | else | |
16296 | { | |
16297 | mips_opts.arch = p->cpu; | |
16298 | mips_opts.isa = p->isa; | |
22522f88 | 16299 | isa_set = TRUE; |
1a2c1fad CD |
16300 | } |
16301 | } | |
81a21e38 TS |
16302 | else if (strncmp (name, "mips", 4) == 0) |
16303 | { | |
16304 | const struct mips_cpu_info *p; | |
16305 | ||
919731af | 16306 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16307 | if (!p) |
16308 | as_bad (_("unknown ISA level %s"), name + 4); | |
16309 | else | |
16310 | { | |
16311 | mips_opts.arch = p->cpu; | |
16312 | mips_opts.isa = p->isa; | |
22522f88 | 16313 | isa_set = TRUE; |
81a21e38 TS |
16314 | } |
16315 | } | |
af7ee8bf | 16316 | else |
81a21e38 | 16317 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16318 | } |
16319 | else if (strcmp (name, "autoextend") == 0) | |
16320 | mips_opts.noautoextend = 0; | |
16321 | else if (strcmp (name, "noautoextend") == 0) | |
16322 | mips_opts.noautoextend = 1; | |
833794fc MR |
16323 | else if (strcmp (name, "insn32") == 0) |
16324 | mips_opts.insn32 = TRUE; | |
16325 | else if (strcmp (name, "noinsn32") == 0) | |
16326 | mips_opts.insn32 = FALSE; | |
919731af | 16327 | else if (strcmp (name, "sym32") == 0) |
16328 | mips_opts.sym32 = TRUE; | |
16329 | else if (strcmp (name, "nosym32") == 0) | |
16330 | mips_opts.sym32 = FALSE; | |
16331 | else | |
22522f88 MR |
16332 | return OPTION_TYPE_BAD; |
16333 | ||
16334 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16335 | } |
16336 | ||
16337 | /* Handle the .set pseudo-op. */ | |
16338 | ||
16339 | static void | |
16340 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16341 | { | |
22522f88 | 16342 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16343 | char *name = input_line_pointer, ch; |
919731af | 16344 | |
16345 | file_mips_check_options (); | |
16346 | ||
16347 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16348 | ++input_line_pointer; | |
16349 | ch = *input_line_pointer; | |
16350 | *input_line_pointer = '\0'; | |
16351 | ||
16352 | if (strchr (name, ',')) | |
16353 | { | |
16354 | /* Generic ".set" directive; use the generic handler. */ | |
16355 | *input_line_pointer = ch; | |
16356 | input_line_pointer = name; | |
16357 | s_set (0); | |
16358 | return; | |
16359 | } | |
16360 | ||
16361 | if (strcmp (name, "reorder") == 0) | |
16362 | { | |
16363 | if (mips_opts.noreorder) | |
16364 | end_noreorder (); | |
16365 | } | |
16366 | else if (strcmp (name, "noreorder") == 0) | |
16367 | { | |
16368 | if (!mips_opts.noreorder) | |
16369 | start_noreorder (); | |
16370 | } | |
16371 | else if (strcmp (name, "macro") == 0) | |
16372 | mips_opts.warn_about_macros = 0; | |
16373 | else if (strcmp (name, "nomacro") == 0) | |
16374 | { | |
16375 | if (mips_opts.noreorder == 0) | |
16376 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16377 | mips_opts.warn_about_macros = 1; | |
16378 | } | |
16379 | else if (strcmp (name, "gp=default") == 0) | |
16380 | mips_opts.gp = file_mips_opts.gp; | |
16381 | else if (strcmp (name, "fp=default") == 0) | |
16382 | mips_opts.fp = file_mips_opts.fp; | |
16383 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16384 | { | |
16385 | mips_opts.isa = file_mips_opts.isa; | |
16386 | mips_opts.arch = file_mips_opts.arch; | |
16387 | mips_opts.gp = file_mips_opts.gp; | |
16388 | mips_opts.fp = file_mips_opts.fp; | |
16389 | } | |
252b5132 RH |
16390 | else if (strcmp (name, "push") == 0) |
16391 | { | |
16392 | struct mips_option_stack *s; | |
16393 | ||
325801bd | 16394 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16395 | s->next = mips_opts_stack; |
16396 | s->options = mips_opts; | |
16397 | mips_opts_stack = s; | |
16398 | } | |
16399 | else if (strcmp (name, "pop") == 0) | |
16400 | { | |
16401 | struct mips_option_stack *s; | |
16402 | ||
16403 | s = mips_opts_stack; | |
16404 | if (s == NULL) | |
16405 | as_bad (_(".set pop with no .set push")); | |
16406 | else | |
16407 | { | |
16408 | /* If we're changing the reorder mode we need to handle | |
16409 | delay slots correctly. */ | |
16410 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16411 | start_noreorder (); |
252b5132 | 16412 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16413 | end_noreorder (); |
252b5132 RH |
16414 | |
16415 | mips_opts = s->options; | |
16416 | mips_opts_stack = s->next; | |
16417 | free (s); | |
16418 | } | |
16419 | } | |
22522f88 MR |
16420 | else |
16421 | { | |
16422 | type = parse_code_option (name); | |
16423 | if (type == OPTION_TYPE_BAD) | |
16424 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16425 | } | |
919731af | 16426 | |
16427 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16428 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16429 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16430 | { |
919731af | 16431 | switch (mips_opts.isa) |
16432 | { | |
16433 | case 0: | |
16434 | break; | |
16435 | case ISA_MIPS1: | |
351cdf24 MF |
16436 | /* MIPS I cannot support FPXX. */ |
16437 | mips_opts.fp = 32; | |
16438 | /* fall-through. */ | |
919731af | 16439 | case ISA_MIPS2: |
16440 | case ISA_MIPS32: | |
16441 | case ISA_MIPS32R2: | |
16442 | case ISA_MIPS32R3: | |
16443 | case ISA_MIPS32R5: | |
16444 | mips_opts.gp = 32; | |
351cdf24 MF |
16445 | if (mips_opts.fp != 0) |
16446 | mips_opts.fp = 32; | |
919731af | 16447 | break; |
7361da2c AB |
16448 | case ISA_MIPS32R6: |
16449 | mips_opts.gp = 32; | |
16450 | mips_opts.fp = 64; | |
16451 | break; | |
919731af | 16452 | case ISA_MIPS3: |
16453 | case ISA_MIPS4: | |
16454 | case ISA_MIPS5: | |
16455 | case ISA_MIPS64: | |
16456 | case ISA_MIPS64R2: | |
16457 | case ISA_MIPS64R3: | |
16458 | case ISA_MIPS64R5: | |
7361da2c | 16459 | case ISA_MIPS64R6: |
919731af | 16460 | mips_opts.gp = 64; |
351cdf24 MF |
16461 | if (mips_opts.fp != 0) |
16462 | { | |
16463 | if (mips_opts.arch == CPU_R5900) | |
16464 | mips_opts.fp = 32; | |
16465 | else | |
16466 | mips_opts.fp = 64; | |
16467 | } | |
919731af | 16468 | break; |
16469 | default: | |
16470 | as_bad (_("unknown ISA level %s"), name + 4); | |
16471 | break; | |
16472 | } | |
e6559e01 | 16473 | } |
919731af | 16474 | |
16475 | mips_check_options (&mips_opts, FALSE); | |
16476 | ||
16477 | mips_check_isa_supports_ases (); | |
16478 | *input_line_pointer = ch; | |
16479 | demand_empty_rest_of_line (); | |
16480 | } | |
16481 | ||
16482 | /* Handle the .module pseudo-op. */ | |
16483 | ||
16484 | static void | |
16485 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16486 | { | |
16487 | char *name = input_line_pointer, ch; | |
16488 | ||
16489 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16490 | ++input_line_pointer; | |
16491 | ch = *input_line_pointer; | |
16492 | *input_line_pointer = '\0'; | |
16493 | ||
16494 | if (!file_mips_opts_checked) | |
252b5132 | 16495 | { |
22522f88 | 16496 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16497 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16498 | ||
16499 | /* Update module level settings from mips_opts. */ | |
16500 | file_mips_opts = mips_opts; | |
252b5132 | 16501 | } |
919731af | 16502 | else |
16503 | as_bad (_(".module is not permitted after generating code")); | |
16504 | ||
252b5132 RH |
16505 | *input_line_pointer = ch; |
16506 | demand_empty_rest_of_line (); | |
16507 | } | |
16508 | ||
16509 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16510 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16511 | ||
16512 | static void | |
17a2f251 | 16513 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16514 | { |
16515 | mips_pic = SVR4_PIC; | |
143d77c5 | 16516 | mips_abicalls = TRUE; |
4d0d148d TS |
16517 | |
16518 | if (g_switch_seen && g_switch_value != 0) | |
16519 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16520 | g_switch_value = 0; | |
16521 | ||
252b5132 RH |
16522 | bfd_set_gp_size (stdoutput, 0); |
16523 | demand_empty_rest_of_line (); | |
16524 | } | |
16525 | ||
16526 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16527 | PIC code. It sets the $gp register for the function based on the | |
16528 | function address, which is in the register named in the argument. | |
16529 | This uses a relocation against _gp_disp, which is handled specially | |
16530 | by the linker. The result is: | |
16531 | lui $gp,%hi(_gp_disp) | |
16532 | addiu $gp,$gp,%lo(_gp_disp) | |
16533 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16534 | The .cpload argument is normally $25 == $t9. |
16535 | ||
16536 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16537 | lui $gp,%hi(__gnu_local_gp) |
16538 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16539 | and the argument is ignored. This saves an instruction, but the |
16540 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16541 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16542 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16543 | |
16544 | static void | |
17a2f251 | 16545 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16546 | { |
16547 | expressionS ex; | |
aa6975fb ILT |
16548 | int reg; |
16549 | int in_shared; | |
252b5132 | 16550 | |
919731af | 16551 | file_mips_check_options (); |
16552 | ||
6478892d TS |
16553 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16554 | .cpload is ignored. */ | |
16555 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16556 | { |
16557 | s_ignore (0); | |
16558 | return; | |
16559 | } | |
16560 | ||
a276b80c MR |
16561 | if (mips_opts.mips16) |
16562 | { | |
16563 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16564 | ignore_rest_of_line (); | |
16565 | return; | |
16566 | } | |
16567 | ||
d3ecfc59 | 16568 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16569 | if (mips_opts.noreorder == 0) |
16570 | as_warn (_(".cpload not in noreorder section")); | |
16571 | ||
aa6975fb ILT |
16572 | reg = tc_get_register (0); |
16573 | ||
16574 | /* If we need to produce a 64-bit address, we are better off using | |
16575 | the default instruction sequence. */ | |
aed1a261 | 16576 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16577 | |
252b5132 | 16578 | ex.X_op = O_symbol; |
bbe506e8 TS |
16579 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16580 | "__gnu_local_gp"); | |
252b5132 RH |
16581 | ex.X_op_symbol = NULL; |
16582 | ex.X_add_number = 0; | |
16583 | ||
16584 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16585 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16586 | |
8a75745d MR |
16587 | mips_mark_labels (); |
16588 | mips_assembling_insn = TRUE; | |
16589 | ||
584892a6 | 16590 | macro_start (); |
67c0d1eb RS |
16591 | macro_build_lui (&ex, mips_gp_register); |
16592 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16593 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16594 | if (in_shared) |
16595 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16596 | mips_gp_register, reg); | |
584892a6 | 16597 | macro_end (); |
252b5132 | 16598 | |
8a75745d | 16599 | mips_assembling_insn = FALSE; |
252b5132 RH |
16600 | demand_empty_rest_of_line (); |
16601 | } | |
16602 | ||
6478892d TS |
16603 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16604 | .cpsetup $reg1, offset|$reg2, label | |
16605 | ||
16606 | If offset is given, this results in: | |
16607 | sd $gp, offset($sp) | |
956cd1d6 | 16608 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16609 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16610 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16611 | |
16612 | If $reg2 is given, this results in: | |
40fc1451 | 16613 | or $reg2, $gp, $0 |
956cd1d6 | 16614 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16615 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16616 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16617 | $reg1 is normally $25 == $t9. |
16618 | ||
16619 | The -mno-shared option replaces the last three instructions with | |
16620 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16621 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16622 | |
6478892d | 16623 | static void |
17a2f251 | 16624 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16625 | { |
16626 | expressionS ex_off; | |
16627 | expressionS ex_sym; | |
16628 | int reg1; | |
6478892d | 16629 | |
919731af | 16630 | file_mips_check_options (); |
16631 | ||
8586fc66 | 16632 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16633 | We also need NewABI support. */ |
16634 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16635 | { | |
16636 | s_ignore (0); | |
16637 | return; | |
16638 | } | |
16639 | ||
a276b80c MR |
16640 | if (mips_opts.mips16) |
16641 | { | |
16642 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16643 | ignore_rest_of_line (); | |
16644 | return; | |
16645 | } | |
16646 | ||
6478892d TS |
16647 | reg1 = tc_get_register (0); |
16648 | SKIP_WHITESPACE (); | |
16649 | if (*input_line_pointer != ',') | |
16650 | { | |
16651 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16652 | return; | |
16653 | } | |
16654 | else | |
80245285 | 16655 | ++input_line_pointer; |
6478892d TS |
16656 | SKIP_WHITESPACE (); |
16657 | if (*input_line_pointer == '$') | |
80245285 TS |
16658 | { |
16659 | mips_cpreturn_register = tc_get_register (0); | |
16660 | mips_cpreturn_offset = -1; | |
16661 | } | |
6478892d | 16662 | else |
80245285 TS |
16663 | { |
16664 | mips_cpreturn_offset = get_absolute_expression (); | |
16665 | mips_cpreturn_register = -1; | |
16666 | } | |
6478892d TS |
16667 | SKIP_WHITESPACE (); |
16668 | if (*input_line_pointer != ',') | |
16669 | { | |
16670 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16671 | return; | |
16672 | } | |
16673 | else | |
f9419b05 | 16674 | ++input_line_pointer; |
6478892d | 16675 | SKIP_WHITESPACE (); |
f21f8242 | 16676 | expression (&ex_sym); |
6478892d | 16677 | |
8a75745d MR |
16678 | mips_mark_labels (); |
16679 | mips_assembling_insn = TRUE; | |
16680 | ||
584892a6 | 16681 | macro_start (); |
6478892d TS |
16682 | if (mips_cpreturn_register == -1) |
16683 | { | |
16684 | ex_off.X_op = O_constant; | |
16685 | ex_off.X_add_symbol = NULL; | |
16686 | ex_off.X_op_symbol = NULL; | |
16687 | ex_off.X_add_number = mips_cpreturn_offset; | |
16688 | ||
67c0d1eb | 16689 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16690 | BFD_RELOC_LO16, SP); |
6478892d TS |
16691 | } |
16692 | else | |
40fc1451 | 16693 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16694 | |
aed1a261 | 16695 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16696 | { |
df58fc94 | 16697 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16698 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16699 | BFD_RELOC_HI16_S); | |
16700 | ||
16701 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16702 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16703 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16704 | ||
16705 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16706 | mips_gp_register, reg1); | |
16707 | } | |
16708 | else | |
16709 | { | |
16710 | expressionS ex; | |
16711 | ||
16712 | ex.X_op = O_symbol; | |
4184909a | 16713 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16714 | ex.X_op_symbol = NULL; |
16715 | ex.X_add_number = 0; | |
6e1304d8 | 16716 | |
aa6975fb ILT |
16717 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16718 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16719 | ||
16720 | macro_build_lui (&ex, mips_gp_register); | |
16721 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16722 | mips_gp_register, BFD_RELOC_LO16); | |
16723 | } | |
f21f8242 | 16724 | |
584892a6 | 16725 | macro_end (); |
6478892d | 16726 | |
8a75745d | 16727 | mips_assembling_insn = FALSE; |
6478892d TS |
16728 | demand_empty_rest_of_line (); |
16729 | } | |
16730 | ||
16731 | static void | |
17a2f251 | 16732 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16733 | { |
919731af | 16734 | file_mips_check_options (); |
16735 | ||
6478892d | 16736 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16737 | .cplocal is ignored. */ |
6478892d TS |
16738 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16739 | { | |
16740 | s_ignore (0); | |
16741 | return; | |
16742 | } | |
16743 | ||
a276b80c MR |
16744 | if (mips_opts.mips16) |
16745 | { | |
16746 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16747 | ignore_rest_of_line (); | |
16748 | return; | |
16749 | } | |
16750 | ||
6478892d | 16751 | mips_gp_register = tc_get_register (0); |
85b51719 | 16752 | demand_empty_rest_of_line (); |
6478892d TS |
16753 | } |
16754 | ||
252b5132 RH |
16755 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16756 | offset from $sp. The offset is remembered, and after making a PIC | |
16757 | call $gp is restored from that location. */ | |
16758 | ||
16759 | static void | |
17a2f251 | 16760 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16761 | { |
16762 | expressionS ex; | |
252b5132 | 16763 | |
919731af | 16764 | file_mips_check_options (); |
16765 | ||
6478892d | 16766 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16767 | .cprestore is ignored. */ |
6478892d | 16768 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16769 | { |
16770 | s_ignore (0); | |
16771 | return; | |
16772 | } | |
16773 | ||
a276b80c MR |
16774 | if (mips_opts.mips16) |
16775 | { | |
16776 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16777 | ignore_rest_of_line (); | |
16778 | return; | |
16779 | } | |
16780 | ||
252b5132 | 16781 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16782 | mips_cprestore_valid = 1; |
252b5132 RH |
16783 | |
16784 | ex.X_op = O_constant; | |
16785 | ex.X_add_symbol = NULL; | |
16786 | ex.X_op_symbol = NULL; | |
16787 | ex.X_add_number = mips_cprestore_offset; | |
16788 | ||
8a75745d MR |
16789 | mips_mark_labels (); |
16790 | mips_assembling_insn = TRUE; | |
16791 | ||
584892a6 | 16792 | macro_start (); |
67c0d1eb RS |
16793 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16794 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16795 | macro_end (); |
252b5132 | 16796 | |
8a75745d | 16797 | mips_assembling_insn = FALSE; |
252b5132 RH |
16798 | demand_empty_rest_of_line (); |
16799 | } | |
16800 | ||
6478892d | 16801 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16802 | was given in the preceding .cpsetup, it results in: |
6478892d | 16803 | ld $gp, offset($sp) |
76b3015f | 16804 | |
6478892d | 16805 | If a register $reg2 was given there, it results in: |
40fc1451 | 16806 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16807 | |
6478892d | 16808 | static void |
17a2f251 | 16809 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16810 | { |
16811 | expressionS ex; | |
6478892d | 16812 | |
919731af | 16813 | file_mips_check_options (); |
16814 | ||
6478892d TS |
16815 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16816 | We also need NewABI support. */ | |
16817 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16818 | { | |
16819 | s_ignore (0); | |
16820 | return; | |
16821 | } | |
16822 | ||
a276b80c MR |
16823 | if (mips_opts.mips16) |
16824 | { | |
16825 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16826 | ignore_rest_of_line (); | |
16827 | return; | |
16828 | } | |
16829 | ||
8a75745d MR |
16830 | mips_mark_labels (); |
16831 | mips_assembling_insn = TRUE; | |
16832 | ||
584892a6 | 16833 | macro_start (); |
6478892d TS |
16834 | if (mips_cpreturn_register == -1) |
16835 | { | |
16836 | ex.X_op = O_constant; | |
16837 | ex.X_add_symbol = NULL; | |
16838 | ex.X_op_symbol = NULL; | |
16839 | ex.X_add_number = mips_cpreturn_offset; | |
16840 | ||
67c0d1eb | 16841 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16842 | } |
16843 | else | |
40fc1451 SD |
16844 | move_register (mips_gp_register, mips_cpreturn_register); |
16845 | ||
584892a6 | 16846 | macro_end (); |
6478892d | 16847 | |
8a75745d | 16848 | mips_assembling_insn = FALSE; |
6478892d TS |
16849 | demand_empty_rest_of_line (); |
16850 | } | |
16851 | ||
d0f13682 CLT |
16852 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16853 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16854 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16855 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16856 | |
16857 | static void | |
d0f13682 CLT |
16858 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16859 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16860 | { |
16861 | expressionS ex; | |
16862 | char *p; | |
16863 | ||
16864 | expression (&ex); | |
16865 | ||
16866 | if (ex.X_op != O_symbol) | |
16867 | { | |
1661c76c | 16868 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16869 | ignore_rest_of_line (); |
16870 | } | |
16871 | ||
16872 | p = frag_more (bytes); | |
16873 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16874 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16875 | demand_empty_rest_of_line (); |
de64cffd | 16876 | mips_clear_insn_labels (); |
741d6ea8 JM |
16877 | } |
16878 | ||
16879 | /* Handle .dtprelword. */ | |
16880 | ||
16881 | static void | |
16882 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16883 | { | |
d0f13682 | 16884 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16885 | } |
16886 | ||
16887 | /* Handle .dtpreldword. */ | |
16888 | ||
16889 | static void | |
16890 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16891 | { | |
d0f13682 CLT |
16892 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16893 | } | |
16894 | ||
16895 | /* Handle .tprelword. */ | |
16896 | ||
16897 | static void | |
16898 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16899 | { | |
16900 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16901 | } | |
16902 | ||
16903 | /* Handle .tpreldword. */ | |
16904 | ||
16905 | static void | |
16906 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16907 | { | |
16908 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16909 | } |
16910 | ||
6478892d TS |
16911 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16912 | code. It sets the offset to use in gp_rel relocations. */ | |
16913 | ||
16914 | static void | |
17a2f251 | 16915 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16916 | { |
16917 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16918 | We also need NewABI support. */ | |
16919 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16920 | { | |
16921 | s_ignore (0); | |
16922 | return; | |
16923 | } | |
16924 | ||
def2e0dd | 16925 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16926 | |
16927 | demand_empty_rest_of_line (); | |
16928 | } | |
16929 | ||
252b5132 RH |
16930 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16931 | code. It generates a 32 bit GP relative reloc. */ | |
16932 | ||
16933 | static void | |
17a2f251 | 16934 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16935 | { |
a8dbcb85 TS |
16936 | segment_info_type *si; |
16937 | struct insn_label_list *l; | |
252b5132 RH |
16938 | expressionS ex; |
16939 | char *p; | |
16940 | ||
16941 | /* When not generating PIC code, this is treated as .word. */ | |
16942 | if (mips_pic != SVR4_PIC) | |
16943 | { | |
16944 | s_cons (2); | |
16945 | return; | |
16946 | } | |
16947 | ||
a8dbcb85 TS |
16948 | si = seg_info (now_seg); |
16949 | l = si->label_list; | |
7d10b47d | 16950 | mips_emit_delays (); |
252b5132 | 16951 | if (auto_align) |
462427c4 | 16952 | mips_align (2, 0, l); |
252b5132 RH |
16953 | |
16954 | expression (&ex); | |
a1facbec | 16955 | mips_clear_insn_labels (); |
252b5132 RH |
16956 | |
16957 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16958 | { | |
1661c76c | 16959 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
16960 | ignore_rest_of_line (); |
16961 | } | |
16962 | ||
16963 | p = frag_more (4); | |
17a2f251 | 16964 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16965 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16966 | BFD_RELOC_GPREL32); |
252b5132 RH |
16967 | |
16968 | demand_empty_rest_of_line (); | |
16969 | } | |
16970 | ||
10181a0d | 16971 | static void |
17a2f251 | 16972 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16973 | { |
a8dbcb85 TS |
16974 | segment_info_type *si; |
16975 | struct insn_label_list *l; | |
10181a0d AO |
16976 | expressionS ex; |
16977 | char *p; | |
16978 | ||
16979 | /* When not generating PIC code, this is treated as .dword. */ | |
16980 | if (mips_pic != SVR4_PIC) | |
16981 | { | |
16982 | s_cons (3); | |
16983 | return; | |
16984 | } | |
16985 | ||
a8dbcb85 TS |
16986 | si = seg_info (now_seg); |
16987 | l = si->label_list; | |
7d10b47d | 16988 | mips_emit_delays (); |
10181a0d | 16989 | if (auto_align) |
462427c4 | 16990 | mips_align (3, 0, l); |
10181a0d AO |
16991 | |
16992 | expression (&ex); | |
a1facbec | 16993 | mips_clear_insn_labels (); |
10181a0d AO |
16994 | |
16995 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16996 | { | |
1661c76c | 16997 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
16998 | ignore_rest_of_line (); |
16999 | } | |
17000 | ||
17001 | p = frag_more (8); | |
17a2f251 | 17002 | md_number_to_chars (p, 0, 8); |
a105a300 | 17003 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17004 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17005 | |
17006 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17007 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17008 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17009 | |
17010 | demand_empty_rest_of_line (); | |
17011 | } | |
17012 | ||
a3f278e2 CM |
17013 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17014 | tables. It generates a R_MIPS_EH reloc. */ | |
17015 | ||
17016 | static void | |
17017 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17018 | { | |
17019 | expressionS ex; | |
17020 | char *p; | |
17021 | ||
17022 | mips_emit_delays (); | |
17023 | ||
17024 | expression (&ex); | |
17025 | mips_clear_insn_labels (); | |
17026 | ||
17027 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17028 | { | |
1661c76c | 17029 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17030 | ignore_rest_of_line (); |
17031 | } | |
17032 | ||
17033 | p = frag_more (4); | |
17034 | md_number_to_chars (p, 0, 4); | |
17035 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17036 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17037 | |
17038 | demand_empty_rest_of_line (); | |
17039 | } | |
17040 | ||
252b5132 RH |
17041 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17042 | tables in SVR4 PIC code. */ | |
17043 | ||
17044 | static void | |
17a2f251 | 17045 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17046 | { |
252b5132 RH |
17047 | int reg; |
17048 | ||
919731af | 17049 | file_mips_check_options (); |
17050 | ||
10181a0d AO |
17051 | /* This is ignored when not generating SVR4 PIC code. */ |
17052 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17053 | { |
17054 | s_ignore (0); | |
17055 | return; | |
17056 | } | |
17057 | ||
8a75745d MR |
17058 | mips_mark_labels (); |
17059 | mips_assembling_insn = TRUE; | |
17060 | ||
252b5132 | 17061 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17062 | macro_start (); |
252b5132 | 17063 | reg = tc_get_register (0); |
67c0d1eb | 17064 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17065 | macro_end (); |
252b5132 | 17066 | |
8a75745d | 17067 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17068 | demand_empty_rest_of_line (); |
252b5132 RH |
17069 | } |
17070 | ||
17071 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17072 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17073 | such as generating jalx instructions when needed. We also make |
17074 | them odd for the duration of the assembly, in order to generate the | |
17075 | right sort of code. We will make them even in the adjust_symtab | |
17076 | routine, while leaving them marked. This is convenient for the | |
17077 | debugger and the disassembler. The linker knows to make them odd | |
17078 | again. */ | |
17079 | ||
17080 | static void | |
17a2f251 | 17081 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17082 | { |
7bb01e2d MR |
17083 | file_mips_check_options (); |
17084 | file_ase_mips16 |= mips_opts.mips16; | |
17085 | file_ase_micromips |= mips_opts.micromips; | |
17086 | ||
df58fc94 | 17087 | mips_mark_labels (); |
252b5132 RH |
17088 | |
17089 | demand_empty_rest_of_line (); | |
17090 | } | |
17091 | ||
ba92f887 MR |
17092 | /* Handle the .nan pseudo-op. */ |
17093 | ||
17094 | static void | |
17095 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17096 | { | |
17097 | static const char str_legacy[] = "legacy"; | |
17098 | static const char str_2008[] = "2008"; | |
17099 | size_t i; | |
17100 | ||
17101 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17102 | ||
17103 | if (i == sizeof (str_2008) - 1 | |
17104 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17105 | mips_nan2008 = 1; |
ba92f887 MR |
17106 | else if (i == sizeof (str_legacy) - 1 |
17107 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17108 | { |
17109 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17110 | mips_nan2008 = 0; | |
17111 | else | |
17112 | as_bad (_("`%s' does not support legacy NaN"), | |
17113 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17114 | } | |
ba92f887 | 17115 | else |
1661c76c | 17116 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17117 | |
17118 | input_line_pointer += i; | |
17119 | demand_empty_rest_of_line (); | |
17120 | } | |
17121 | ||
754e2bb9 RS |
17122 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17123 | implemented in a transparent way, so that removing them would not | |
17124 | have any effect on the generated instructions. However, s_stab | |
17125 | internally changes the section, so in practice we need to decide | |
17126 | now whether the preceding label marks compressed code. We do not | |
17127 | support changing the compression mode of a label after a .stab* | |
17128 | directive, such as in: | |
17129 | ||
17130 | foo: | |
134c0c8b | 17131 | .stabs ... |
754e2bb9 RS |
17132 | .set mips16 |
17133 | ||
17134 | so the current mode wins. */ | |
252b5132 RH |
17135 | |
17136 | static void | |
17a2f251 | 17137 | s_mips_stab (int type) |
252b5132 | 17138 | { |
754e2bb9 | 17139 | mips_mark_labels (); |
252b5132 RH |
17140 | s_stab (type); |
17141 | } | |
17142 | ||
54f4ddb3 | 17143 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17144 | |
17145 | static void | |
17a2f251 | 17146 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17147 | { |
17148 | char *name; | |
17149 | int c; | |
17150 | symbolS *symbolP; | |
17151 | expressionS exp; | |
17152 | ||
d02603dc | 17153 | c = get_symbol_name (&name); |
252b5132 RH |
17154 | symbolP = symbol_find_or_make (name); |
17155 | S_SET_WEAK (symbolP); | |
17156 | *input_line_pointer = c; | |
17157 | ||
d02603dc | 17158 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17159 | |
17160 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17161 | { | |
17162 | if (S_IS_DEFINED (symbolP)) | |
17163 | { | |
20203fb9 | 17164 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17165 | S_GET_NAME (symbolP)); |
17166 | ignore_rest_of_line (); | |
17167 | return; | |
17168 | } | |
bdaaa2e1 | 17169 | |
252b5132 RH |
17170 | if (*input_line_pointer == ',') |
17171 | { | |
17172 | ++input_line_pointer; | |
17173 | SKIP_WHITESPACE (); | |
17174 | } | |
bdaaa2e1 | 17175 | |
252b5132 RH |
17176 | expression (&exp); |
17177 | if (exp.X_op != O_symbol) | |
17178 | { | |
20203fb9 | 17179 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17180 | ignore_rest_of_line (); |
252b5132 RH |
17181 | return; |
17182 | } | |
49309057 | 17183 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17184 | } |
17185 | ||
17186 | demand_empty_rest_of_line (); | |
17187 | } | |
17188 | ||
17189 | /* Parse a register string into a number. Called from the ECOFF code | |
17190 | to parse .frame. The argument is non-zero if this is the frame | |
17191 | register, so that we can record it in mips_frame_reg. */ | |
17192 | ||
17193 | int | |
17a2f251 | 17194 | tc_get_register (int frame) |
252b5132 | 17195 | { |
707bfff6 | 17196 | unsigned int reg; |
252b5132 RH |
17197 | |
17198 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17199 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17200 | reg = 0; | |
252b5132 | 17201 | if (frame) |
7a621144 DJ |
17202 | { |
17203 | mips_frame_reg = reg != 0 ? reg : SP; | |
17204 | mips_frame_reg_valid = 1; | |
17205 | mips_cprestore_valid = 0; | |
17206 | } | |
252b5132 RH |
17207 | return reg; |
17208 | } | |
17209 | ||
17210 | valueT | |
17a2f251 | 17211 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17212 | { |
17213 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17214 | ||
f3ded42a RS |
17215 | /* We don't need to align ELF sections to the full alignment. |
17216 | However, Irix 5 may prefer that we align them at least to a 16 | |
17217 | byte boundary. We don't bother to align the sections if we | |
17218 | are targeted for an embedded system. */ | |
17219 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17220 | return addr; | |
17221 | if (align > 4) | |
17222 | align = 4; | |
252b5132 | 17223 | |
8d3842cd | 17224 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17225 | } |
17226 | ||
17227 | /* Utility routine, called from above as well. If called while the | |
17228 | input file is still being read, it's only an approximation. (For | |
17229 | example, a symbol may later become defined which appeared to be | |
17230 | undefined earlier.) */ | |
17231 | ||
17232 | static int | |
17a2f251 | 17233 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17234 | { |
17235 | if (sym == 0) | |
17236 | return 0; | |
17237 | ||
4d0d148d | 17238 | if (g_switch_value > 0) |
252b5132 RH |
17239 | { |
17240 | const char *symname; | |
17241 | int change; | |
17242 | ||
c9914766 | 17243 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17244 | register. It can be if it is smaller than the -G size or if |
17245 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17246 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17247 | they can. */ |
17248 | symname = S_GET_NAME (sym); | |
17249 | if (symname != (const char *) NULL | |
17250 | && (strcmp (symname, "eprol") == 0 | |
17251 | || strcmp (symname, "etext") == 0 | |
17252 | || strcmp (symname, "_gp") == 0 | |
17253 | || strcmp (symname, "edata") == 0 | |
17254 | || strcmp (symname, "_fbss") == 0 | |
17255 | || strcmp (symname, "_fdata") == 0 | |
17256 | || strcmp (symname, "_ftext") == 0 | |
17257 | || strcmp (symname, "end") == 0 | |
17258 | || strcmp (symname, "_gp_disp") == 0)) | |
17259 | change = 1; | |
17260 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17261 | && (0 | |
17262 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17263 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17264 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17265 | <= g_switch_value)) | |
252b5132 RH |
17266 | #endif |
17267 | /* We must defer this decision until after the whole | |
17268 | file has been read, since there might be a .extern | |
17269 | after the first use of this symbol. */ | |
17270 | || (before_relaxing | |
17271 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17272 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17273 | #endif |
17274 | && S_GET_VALUE (sym) == 0) | |
17275 | || (S_GET_VALUE (sym) != 0 | |
17276 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17277 | change = 0; | |
17278 | else | |
17279 | { | |
17280 | const char *segname; | |
17281 | ||
17282 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17283 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17284 | && strcmp (segname, ".lit4") != 0); |
17285 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17286 | && strcmp (segname, ".sbss") != 0 |
17287 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17288 | && strncmp (segname, ".sbss.", 6) != 0 |
17289 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17290 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17291 | } |
17292 | return change; | |
17293 | } | |
17294 | else | |
c9914766 | 17295 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17296 | return 1; |
17297 | } | |
17298 | ||
5919d012 RS |
17299 | |
17300 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17301 | ||
17302 | static bfd_boolean | |
9e009953 | 17303 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17304 | { |
17305 | asection *symsec; | |
5919d012 RS |
17306 | |
17307 | /* Handle the case of a symbol equated to another symbol. */ | |
17308 | while (symbol_equated_reloc_p (sym)) | |
17309 | { | |
17310 | symbolS *n; | |
17311 | ||
5f0fe04b | 17312 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17313 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17314 | if (n == sym) | |
17315 | break; | |
17316 | sym = n; | |
17317 | } | |
17318 | ||
df1f3cda DD |
17319 | if (symbol_section_p (sym)) |
17320 | return TRUE; | |
17321 | ||
5919d012 RS |
17322 | symsec = S_GET_SEGMENT (sym); |
17323 | ||
5919d012 | 17324 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17325 | return (!bfd_is_und_section (symsec) |
17326 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17327 | && !bfd_is_com_section (symsec) |
5919d012 | 17328 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17329 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17330 | } |
14f72d45 MR |
17331 | \f |
17332 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17333 | convert a section-relative value VAL to the equivalent PC-relative | |
17334 | value. */ | |
17335 | ||
17336 | static offsetT | |
17337 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17338 | offsetT val, long stretch) | |
17339 | { | |
17340 | fragS *sym_frag; | |
17341 | addressT addr; | |
17342 | ||
17343 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17344 | ||
17345 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17346 | ||
17347 | /* If the relax_marker of the symbol fragment differs from the | |
17348 | relax_marker of this fragment, we have not yet adjusted the | |
17349 | symbol fragment fr_address. We want to add in STRETCH in | |
17350 | order to get a better estimate of the address. This | |
17351 | particularly matters because of the shift bits. */ | |
17352 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17353 | { | |
17354 | fragS *f; | |
17355 | ||
17356 | /* Adjust stretch for any alignment frag. Note that if have | |
17357 | been expanding the earlier code, the symbol may be | |
17358 | defined in what appears to be an earlier frag. FIXME: | |
17359 | This doesn't handle the fr_subtype field, which specifies | |
17360 | a maximum number of bytes to skip when doing an | |
17361 | alignment. */ | |
17362 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17363 | { | |
17364 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17365 | { | |
17366 | if (stretch < 0) | |
17367 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17368 | else | |
17369 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17370 | if (stretch == 0) | |
17371 | break; | |
17372 | } | |
17373 | } | |
17374 | if (f != NULL) | |
17375 | val += stretch; | |
17376 | } | |
17377 | ||
17378 | addr = fragp->fr_address + fragp->fr_fix; | |
17379 | ||
17380 | /* The base address rules are complicated. The base address of | |
17381 | a branch is the following instruction. The base address of a | |
17382 | PC relative load or add is the instruction itself, but if it | |
17383 | is in a delay slot (in which case it can not be extended) use | |
17384 | the address of the instruction whose delay slot it is in. */ | |
17385 | if (pcrel_op->include_isa_bit) | |
17386 | { | |
17387 | addr += 2; | |
17388 | ||
17389 | /* If we are currently assuming that this frag should be | |
17390 | extended, then the current address is two bytes higher. */ | |
17391 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17392 | addr += 2; | |
17393 | ||
17394 | /* Ignore the low bit in the target, since it will be set | |
17395 | for a text label. */ | |
17396 | val &= -2; | |
17397 | } | |
17398 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17399 | addr -= 4; | |
17400 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17401 | addr -= 2; | |
5919d012 | 17402 | |
14f72d45 MR |
17403 | val -= addr & -(1 << pcrel_op->align_log2); |
17404 | ||
17405 | return val; | |
17406 | } | |
5919d012 | 17407 | |
252b5132 RH |
17408 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17409 | extended opcode. SEC is the section the frag is in. */ | |
17410 | ||
17411 | static int | |
17a2f251 | 17412 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17413 | { |
3ccad066 | 17414 | const struct mips_int_operand *operand; |
252b5132 | 17415 | offsetT val; |
252b5132 | 17416 | segT symsec; |
14f72d45 | 17417 | int type; |
252b5132 RH |
17418 | |
17419 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17420 | return 0; | |
17421 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17422 | return 1; | |
17423 | ||
88a7ef16 | 17424 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17425 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17426 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17427 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17428 | || (operand->root.type == OP_PCREL | |
17429 | ? sec != symsec | |
17430 | : !bfd_is_abs_section (symsec))) | |
17431 | return 1; | |
252b5132 | 17432 | |
88a7ef16 | 17433 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17434 | |
3ccad066 | 17435 | if (operand->root.type == OP_PCREL) |
252b5132 | 17436 | { |
3ccad066 | 17437 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17438 | offsetT maxtiny; |
252b5132 | 17439 | |
1425c41d | 17440 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17441 | return 1; |
252b5132 | 17442 | |
88a7ef16 | 17443 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17444 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17445 | |
17446 | /* If any of the shifted bits are set, we must use an extended | |
17447 | opcode. If the address depends on the size of this | |
17448 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17449 | use an extended opcode. */ |
17450 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17451 | { |
17452 | fragp->fr_subtype = | |
1425c41d | 17453 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17454 | return 1; |
17455 | } | |
17456 | ||
17457 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17458 | is precisely the next value above maxtiny, then there is a |
17459 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17460 | la $4,foo |
17461 | .skip 1020 | |
17462 | .align 2 | |
17463 | foo: | |
17464 | In this case when the la is extended, foo is 0x3fc bytes | |
17465 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17466 | the la must be extended. To avoid this loop, we mark the | |
17467 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17468 | extended with the next value above maxtiny. */ |
17469 | maxtiny = mips_int_operand_max (operand); | |
17470 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17471 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17472 | { |
17473 | fragp->fr_subtype = | |
1425c41d | 17474 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17475 | return 1; |
17476 | } | |
17477 | } | |
252b5132 | 17478 | |
3ccad066 | 17479 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17480 | } |
17481 | ||
8507b6e7 MR |
17482 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17483 | macro expansion. SEC is the section the frag is in. We only | |
17484 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17485 | non-PIC code using 32-bit addressing. */ | |
17486 | ||
17487 | static int | |
17488 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17489 | { | |
17490 | const struct mips_pcrel_operand *pcrel_op; | |
17491 | const struct mips_int_operand *operand; | |
17492 | offsetT val; | |
17493 | segT symsec; | |
17494 | int type; | |
17495 | ||
17496 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17497 | ||
17498 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17499 | return 0; | |
17500 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17501 | return 0; | |
17502 | ||
17503 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17504 | switch (type) | |
17505 | { | |
17506 | case 'A': | |
17507 | case 'B': | |
17508 | case 'E': | |
17509 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17510 | if (bfd_is_abs_section (symsec)) | |
17511 | return 1; | |
17512 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17513 | return 0; | |
17514 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17515 | return 1; | |
17516 | ||
17517 | operand = mips16_immed_operand (type, TRUE); | |
17518 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17519 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17520 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17521 | ||
17522 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17523 | ||
17524 | default: | |
17525 | return 0; | |
17526 | } | |
17527 | } | |
17528 | ||
4a6a3df4 AO |
17529 | /* Compute the length of a branch sequence, and adjust the |
17530 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17531 | worst-case length is computed, with UPDATE being used to indicate | |
17532 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17533 | branch is to be computed. */ | |
17534 | static int | |
17a2f251 | 17535 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17536 | { |
b34976b6 | 17537 | bfd_boolean toofar; |
4a6a3df4 AO |
17538 | int length; |
17539 | ||
17540 | if (fragp | |
17541 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17542 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17543 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17544 | { | |
17545 | addressT addr; | |
17546 | offsetT val; | |
17547 | ||
17548 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17549 | ||
17550 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17551 | ||
17552 | val -= addr; | |
17553 | ||
17554 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17555 | } | |
4a6a3df4 | 17556 | else |
c1f61bd2 MR |
17557 | /* If the symbol is not defined or it's in a different segment, |
17558 | we emit the long sequence. */ | |
b34976b6 | 17559 | toofar = TRUE; |
4a6a3df4 AO |
17560 | |
17561 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17562 | fragp->fr_subtype | |
66b3e8da | 17563 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17564 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17565 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17566 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17567 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17568 | toofar); | |
17569 | ||
17570 | length = 4; | |
17571 | if (toofar) | |
17572 | { | |
17573 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17574 | length += 8; | |
17575 | ||
ce8ad872 | 17576 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17577 | { |
17578 | /* Additional space for PIC loading of target address. */ | |
17579 | length += 8; | |
17580 | if (mips_opts.isa == ISA_MIPS1) | |
17581 | /* Additional space for $at-stabilizing nop. */ | |
17582 | length += 4; | |
17583 | } | |
17584 | ||
17585 | /* If branch is conditional. */ | |
17586 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17587 | length += 8; | |
17588 | } | |
b34976b6 | 17589 | |
4a6a3df4 AO |
17590 | return length; |
17591 | } | |
17592 | ||
7bd374a4 MR |
17593 | /* Get a FRAG's branch instruction delay slot size, either from the |
17594 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17595 | or SHORT_INSN_SIZE otherwise. */ | |
17596 | ||
17597 | static int | |
17598 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17599 | { | |
17600 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17601 | ||
17602 | if (al) | |
17603 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17604 | else | |
17605 | return short_insn_size; | |
17606 | } | |
17607 | ||
df58fc94 RS |
17608 | /* Compute the length of a branch sequence, and adjust the |
17609 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17610 | worst-case length is computed, with UPDATE being used to indicate | |
17611 | whether an unconditional (-1), or regular (0) branch is to be | |
17612 | computed. */ | |
17613 | ||
17614 | static int | |
17615 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17616 | { | |
7bd374a4 MR |
17617 | bfd_boolean insn32 = TRUE; |
17618 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17619 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17620 | bfd_boolean al = TRUE; |
17621 | int short_insn_size; | |
df58fc94 RS |
17622 | bfd_boolean toofar; |
17623 | int length; | |
17624 | ||
7bd374a4 MR |
17625 | if (fragp) |
17626 | { | |
17627 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17628 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17629 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17630 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17631 | } | |
17632 | short_insn_size = insn32 ? 4 : 2; | |
17633 | ||
df58fc94 RS |
17634 | if (fragp |
17635 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17636 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17637 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17638 | { | |
17639 | addressT addr; | |
17640 | offsetT val; | |
17641 | ||
17642 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17643 | /* Ignore the low bit in the target, since it will be set | |
17644 | for a text label. */ | |
17645 | if ((val & 1) != 0) | |
17646 | --val; | |
17647 | ||
17648 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17649 | ||
17650 | val -= addr; | |
17651 | ||
17652 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17653 | } | |
df58fc94 | 17654 | else |
c1f61bd2 MR |
17655 | /* If the symbol is not defined or it's in a different segment, |
17656 | we emit the long sequence. */ | |
df58fc94 RS |
17657 | toofar = TRUE; |
17658 | ||
17659 | if (fragp && update | |
17660 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17661 | fragp->fr_subtype = (toofar | |
17662 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17663 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17664 | ||
17665 | length = 4; | |
17666 | if (toofar) | |
17667 | { | |
17668 | bfd_boolean compact_known = fragp != NULL; | |
17669 | bfd_boolean compact = FALSE; | |
17670 | bfd_boolean uncond; | |
17671 | ||
df58fc94 | 17672 | if (fragp) |
8484fb75 MR |
17673 | { |
17674 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17675 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17676 | } |
df58fc94 RS |
17677 | else |
17678 | uncond = update < 0; | |
17679 | ||
17680 | /* If label is out of range, we turn branch <br>: | |
17681 | ||
17682 | <br> label # 4 bytes | |
17683 | 0: | |
17684 | ||
17685 | into: | |
17686 | ||
17687 | j label # 4 bytes | |
8484fb75 MR |
17688 | nop # 2/4 bytes if |
17689 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17690 | 0: |
17691 | */ | |
ce8ad872 | 17692 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17693 | length += short_insn_size; |
df58fc94 RS |
17694 | |
17695 | /* If assembling PIC code, we further turn: | |
17696 | ||
17697 | j label # 4 bytes | |
17698 | ||
17699 | into: | |
17700 | ||
17701 | lw/ld at, %got(label)(gp) # 4 bytes | |
17702 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17703 | jr/c at # 2/4 bytes |
df58fc94 | 17704 | */ |
ce8ad872 | 17705 | if (pic) |
8484fb75 | 17706 | length += 4 + short_insn_size; |
df58fc94 | 17707 | |
7bd374a4 MR |
17708 | /* Add an extra nop if the jump has no compact form and we need |
17709 | to fill the delay slot. */ | |
ce8ad872 | 17710 | if ((!pic || al) && nods) |
7bd374a4 MR |
17711 | length += (fragp |
17712 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17713 | : short_insn_size); | |
17714 | ||
df58fc94 RS |
17715 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17716 | ||
17717 | <brneg> 0f # 4 bytes | |
8484fb75 | 17718 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17719 | */ |
17720 | if (!uncond) | |
8484fb75 | 17721 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17722 | } |
7bd374a4 MR |
17723 | else if (nods) |
17724 | { | |
17725 | /* Add an extra nop to fill the delay slot. */ | |
17726 | gas_assert (fragp); | |
17727 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17728 | } | |
df58fc94 RS |
17729 | |
17730 | return length; | |
17731 | } | |
17732 | ||
17733 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17734 | bit accordingly. */ | |
17735 | ||
17736 | static int | |
17737 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17738 | { | |
17739 | bfd_boolean toofar; | |
17740 | ||
df58fc94 RS |
17741 | if (fragp |
17742 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17743 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17744 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17745 | { | |
17746 | addressT addr; | |
17747 | offsetT val; | |
17748 | int type; | |
17749 | ||
17750 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17751 | /* Ignore the low bit in the target, since it will be set | |
17752 | for a text label. */ | |
17753 | if ((val & 1) != 0) | |
17754 | --val; | |
17755 | ||
17756 | /* Assume this is a 2-byte branch. */ | |
17757 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17758 | ||
17759 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17760 | long branches. */ | |
17761 | ||
17762 | val -= addr; | |
17763 | ||
17764 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17765 | if (type == 'D') | |
17766 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17767 | else if (type == 'E') | |
17768 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17769 | else | |
17770 | abort (); | |
17771 | } | |
17772 | else | |
17773 | /* If the symbol is not defined or it's in a different segment, | |
17774 | we emit a normal 32-bit branch. */ | |
17775 | toofar = TRUE; | |
17776 | ||
17777 | if (fragp && update | |
17778 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17779 | fragp->fr_subtype | |
17780 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17781 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17782 | ||
17783 | if (toofar) | |
17784 | return 4; | |
17785 | ||
17786 | return 2; | |
17787 | } | |
17788 | ||
252b5132 RH |
17789 | /* Estimate the size of a frag before relaxing. Unless this is the |
17790 | mips16, we are not really relaxing here, and the final size is | |
17791 | encoded in the subtype information. For the mips16, we have to | |
17792 | decide whether we are using an extended opcode or not. */ | |
17793 | ||
252b5132 | 17794 | int |
17a2f251 | 17795 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17796 | { |
5919d012 | 17797 | int change; |
252b5132 | 17798 | |
4a6a3df4 AO |
17799 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17800 | { | |
17801 | ||
b34976b6 AM |
17802 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17803 | ||
4a6a3df4 AO |
17804 | return fragp->fr_var; |
17805 | } | |
17806 | ||
252b5132 | 17807 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17808 | { |
17809 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17810 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17811 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 17812 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
17813 | else |
17814 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17815 | } | |
252b5132 | 17816 | |
df58fc94 RS |
17817 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17818 | { | |
17819 | int length = 4; | |
17820 | ||
17821 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17822 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17823 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17824 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17825 | fragp->fr_var = length; | |
17826 | ||
17827 | return length; | |
17828 | } | |
17829 | ||
ce8ad872 | 17830 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17831 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17832 | change = 0; | |
ce8ad872 MR |
17833 | else if (RELAX_PIC (fragp->fr_subtype)) |
17834 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17835 | else |
ce8ad872 | 17836 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17837 | |
17838 | if (change) | |
17839 | { | |
4d7206a2 | 17840 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17841 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17842 | } |
4d7206a2 RS |
17843 | else |
17844 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17845 | } |
17846 | ||
17847 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17848 | should be converted into a reloc against a section. */ |
252b5132 RH |
17849 | |
17850 | int | |
17a2f251 | 17851 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17852 | { |
252b5132 RH |
17853 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17854 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17855 | return 0; | |
a161fe53 | 17856 | |
252b5132 RH |
17857 | if (fixp->fx_addsy == NULL) |
17858 | return 1; | |
a161fe53 | 17859 | |
2f0c68f2 CM |
17860 | /* Allow relocs used for EH tables. */ |
17861 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17862 | return 1; | |
17863 | ||
de7e6852 RS |
17864 | /* If symbol SYM is in a mergeable section, relocations of the form |
17865 | SYM + 0 can usually be made section-relative. The mergeable data | |
17866 | is then identified by the section offset rather than by the symbol. | |
17867 | ||
17868 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17869 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17870 | need to recalculate the complete offset in order to correctly identify |
17871 | the merge data. | |
17872 | ||
33eaf5de | 17873 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17874 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17875 | placed anywhere. Rather than break backwards compatibility by changing | |
17876 | this, it seems better not to force the issue, and instead keep the | |
17877 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17878 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17879 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17880 | && HAVE_IN_PLACE_ADDENDS |
17881 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17882 | return 0; | |
17883 | ||
97f50151 MR |
17884 | /* There is no place to store an in-place offset for JALR relocations. */ |
17885 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
17886 | return 0; | |
17887 | ||
17888 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 17889 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
17890 | start address of the symbol's containing section. |
17891 | ||
17892 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17893 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 17894 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 17895 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
17896 | return 0; |
17897 | ||
b314ec0e RS |
17898 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17899 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17900 | relocations against MIPS16 functions; in this case, the stub becomes | |
17901 | the function's canonical address. | |
17902 | ||
17903 | Floating-point stubs are stored in unique .mips16.call.* or | |
17904 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17905 | the first relocation in section S must be against F; this is how the | |
17906 | linker determines the target function. All relocations that might | |
17907 | resolve to T must also be against F. We therefore have the following | |
17908 | restrictions, which are given in an intentionally-redundant way: | |
17909 | ||
17910 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17911 | symbols. | |
17912 | ||
17913 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17914 | if that stub might be used. | |
17915 | ||
17916 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17917 | symbols. | |
17918 | ||
17919 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17920 | that stub might be used. | |
17921 | ||
17922 | There is a further restriction: | |
17923 | ||
df58fc94 | 17924 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 17925 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
17926 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
17927 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
17928 | against MIPS16 or microMIPS symbols because we need to keep the | |
17929 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
17930 | detection and JAL or BAL to JALX instruction conversion in the |
17931 | linker. | |
b314ec0e | 17932 | |
df58fc94 | 17933 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 17934 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 17935 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
17936 | |
17937 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17938 | relocation against some symbol R, no relocation against R may be | |
17939 | reduced. (Note that this deals with (2) as well as (1) because | |
17940 | relocations against global symbols will never be reduced on ELF | |
17941 | targets.) This approach is a little simpler than trying to detect | |
17942 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17943 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17944 | if (fixp->fx_subsy == NULL |
30c09090 | 17945 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 17946 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
17947 | && (jmp_reloc_p (fixp->fx_r_type) |
17948 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 17949 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 17950 | return 0; |
a161fe53 | 17951 | |
252b5132 RH |
17952 | return 1; |
17953 | } | |
17954 | ||
17955 | /* Translate internal representation of relocation info to BFD target | |
17956 | format. */ | |
17957 | ||
17958 | arelent ** | |
17a2f251 | 17959 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17960 | { |
17961 | static arelent *retval[4]; | |
17962 | arelent *reloc; | |
17963 | bfd_reloc_code_real_type code; | |
17964 | ||
4b0cff4e | 17965 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
17966 | reloc = retval[0] = XCNEW (arelent); |
17967 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17968 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17969 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17970 | ||
bad36eac DJ |
17971 | if (fixp->fx_pcrel) |
17972 | { | |
df58fc94 | 17973 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 17974 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
17975 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
17976 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 17977 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
17978 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
17979 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
17980 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
17981 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
17982 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
17983 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
17984 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
17985 | |
17986 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17987 | Relocations want only the symbol offset. */ | |
51f6035b MR |
17988 | switch (fixp->fx_r_type) |
17989 | { | |
17990 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
17991 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
17992 | break; | |
17993 | default: | |
17994 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
17995 | break; | |
17996 | } | |
bad36eac | 17997 | } |
17c6c9d9 MR |
17998 | else if (HAVE_IN_PLACE_ADDENDS |
17999 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18000 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18001 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18002 | { | |
18003 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18004 | addend accordingly. */ | |
18005 | reloc->addend = fixp->fx_addnumber >> 1; | |
18006 | } | |
bad36eac DJ |
18007 | else |
18008 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18009 | |
438c16b8 TS |
18010 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18011 | entry to be used in the relocation's section offset. */ | |
18012 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18013 | { |
18014 | reloc->address = reloc->addend; | |
18015 | reloc->addend = 0; | |
18016 | } | |
18017 | ||
252b5132 | 18018 | code = fixp->fx_r_type; |
252b5132 | 18019 | |
bad36eac | 18020 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18021 | if (reloc->howto == NULL) |
18022 | { | |
18023 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18024 | _("cannot represent %s relocation in this object file" |
18025 | " format"), | |
252b5132 RH |
18026 | bfd_get_reloc_code_name (code)); |
18027 | retval[0] = NULL; | |
18028 | } | |
18029 | ||
18030 | return retval; | |
18031 | } | |
18032 | ||
18033 | /* Relax a machine dependent frag. This returns the amount by which | |
18034 | the current size of the frag should change. */ | |
18035 | ||
18036 | int | |
17a2f251 | 18037 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18038 | { |
4a6a3df4 AO |
18039 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18040 | { | |
18041 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18042 | |
18043 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18044 | |
18045 | return fragp->fr_var - old_var; | |
18046 | } | |
18047 | ||
df58fc94 RS |
18048 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18049 | { | |
18050 | offsetT old_var = fragp->fr_var; | |
18051 | offsetT new_var = 4; | |
18052 | ||
18053 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18054 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18055 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18056 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18057 | fragp->fr_var = new_var; | |
18058 | ||
18059 | return new_var - old_var; | |
18060 | } | |
18061 | ||
252b5132 RH |
18062 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18063 | return 0; | |
18064 | ||
8507b6e7 | 18065 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18066 | { |
8507b6e7 MR |
18067 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18068 | { | |
18069 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18070 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18071 | } |
18072 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18073 | { | |
18074 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18075 | return -2; | |
18076 | } | |
18077 | else | |
18078 | return 0; | |
18079 | } | |
18080 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18081 | { | |
18082 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18083 | { | |
18084 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18085 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18086 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18087 | } |
18088 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18089 | { | |
18090 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18091 | return 2; | |
18092 | } | |
18093 | else | |
252b5132 | 18094 | return 0; |
252b5132 RH |
18095 | } |
18096 | else | |
18097 | { | |
8507b6e7 | 18098 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18099 | return 0; |
8507b6e7 MR |
18100 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18101 | { | |
18102 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18103 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18104 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18105 | } |
18106 | else | |
18107 | { | |
18108 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18109 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18110 | } |
252b5132 RH |
18111 | } |
18112 | ||
18113 | return 0; | |
18114 | } | |
18115 | ||
18116 | /* Convert a machine dependent frag. */ | |
18117 | ||
18118 | void | |
17a2f251 | 18119 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18120 | { |
4a6a3df4 AO |
18121 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18122 | { | |
4d68580a | 18123 | char *buf; |
4a6a3df4 AO |
18124 | unsigned long insn; |
18125 | expressionS exp; | |
18126 | fixS *fixp; | |
b34976b6 | 18127 | |
4d68580a RS |
18128 | buf = fragp->fr_literal + fragp->fr_fix; |
18129 | insn = read_insn (buf); | |
b34976b6 | 18130 | |
4a6a3df4 AO |
18131 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18132 | { | |
18133 | /* We generate a fixup instead of applying it right now | |
18134 | because, if there are linker relaxations, we're going to | |
18135 | need the relocations. */ | |
18136 | exp.X_op = O_symbol; | |
18137 | exp.X_add_symbol = fragp->fr_symbol; | |
18138 | exp.X_add_number = fragp->fr_offset; | |
18139 | ||
4d68580a RS |
18140 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18141 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18142 | fixp->fx_file = fragp->fr_file; |
18143 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18144 | |
4d68580a | 18145 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18146 | } |
18147 | else | |
18148 | { | |
18149 | int i; | |
18150 | ||
18151 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18152 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18153 | |
18154 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18155 | goto uncond; | |
18156 | ||
18157 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18158 | { | |
18159 | /* Reverse the branch. */ | |
18160 | switch ((insn >> 28) & 0xf) | |
18161 | { | |
18162 | case 4: | |
56d438b1 CF |
18163 | if ((insn & 0xff000000) == 0x47000000 |
18164 | || (insn & 0xff600000) == 0x45600000) | |
18165 | { | |
18166 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18167 | reversed by tweaking bit 23. */ | |
18168 | insn ^= 0x00800000; | |
18169 | } | |
18170 | else | |
18171 | { | |
18172 | /* bc[0-3][tf]l? instructions can have the condition | |
18173 | reversed by tweaking a single TF bit, and their | |
18174 | opcodes all have 0x4???????. */ | |
18175 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18176 | insn ^= 0x00010000; | |
18177 | } | |
4a6a3df4 AO |
18178 | break; |
18179 | ||
18180 | case 0: | |
18181 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18182 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18183 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18184 | insn ^= 0x00010000; |
18185 | break; | |
b34976b6 | 18186 | |
4a6a3df4 AO |
18187 | case 1: |
18188 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18189 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18190 | insn ^= 0x04000000; |
18191 | break; | |
18192 | ||
18193 | default: | |
18194 | abort (); | |
18195 | } | |
18196 | } | |
18197 | ||
18198 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18199 | { | |
18200 | /* Clear the and-link bit. */ | |
9c2799c2 | 18201 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18202 | |
54f4ddb3 TS |
18203 | /* bltzal 0x04100000 bgezal 0x04110000 |
18204 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18205 | insn &= ~0x00100000; |
18206 | } | |
18207 | ||
18208 | /* Branch over the branch (if the branch was likely) or the | |
18209 | full jump (not likely case). Compute the offset from the | |
18210 | current instruction to branch to. */ | |
18211 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18212 | i = 16; | |
18213 | else | |
18214 | { | |
18215 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18216 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18217 | /* How many bytes in instructions from here to the end? */ |
18218 | i = fragp->fr_var - i; | |
18219 | } | |
18220 | /* Convert to instruction count. */ | |
18221 | i >>= 2; | |
18222 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18223 | i--; |
4a6a3df4 AO |
18224 | insn |= i; |
18225 | /* Branch over the jump. */ | |
4d68580a | 18226 | buf = write_insn (buf, insn); |
4a6a3df4 | 18227 | |
54f4ddb3 | 18228 | /* nop */ |
4d68580a | 18229 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18230 | |
18231 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18232 | { | |
18233 | /* beql $0, $0, 2f */ | |
18234 | insn = 0x50000000; | |
18235 | /* Compute the PC offset from the current instruction to | |
18236 | the end of the variable frag. */ | |
18237 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18238 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18239 | /* How many bytes in instructions from here to the end? */ |
18240 | i = fragp->fr_var - i; | |
18241 | /* Convert to instruction count. */ | |
18242 | i >>= 2; | |
18243 | /* Don't decrement i, because we want to branch over the | |
18244 | delay slot. */ | |
4a6a3df4 | 18245 | insn |= i; |
4a6a3df4 | 18246 | |
4d68580a RS |
18247 | buf = write_insn (buf, insn); |
18248 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18249 | } |
18250 | ||
18251 | uncond: | |
ce8ad872 | 18252 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18253 | { |
18254 | /* j or jal. */ | |
18255 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18256 | ? 0x0c000000 : 0x08000000); | |
18257 | exp.X_op = O_symbol; | |
18258 | exp.X_add_symbol = fragp->fr_symbol; | |
18259 | exp.X_add_number = fragp->fr_offset; | |
18260 | ||
4d68580a RS |
18261 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18262 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18263 | fixp->fx_file = fragp->fr_file; |
18264 | fixp->fx_line = fragp->fr_line; | |
18265 | ||
4d68580a | 18266 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18267 | } |
18268 | else | |
18269 | { | |
66b3e8da MR |
18270 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18271 | ||
4a6a3df4 | 18272 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18273 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18274 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18275 | exp.X_op = O_symbol; |
18276 | exp.X_add_symbol = fragp->fr_symbol; | |
18277 | exp.X_add_number = fragp->fr_offset; | |
18278 | ||
18279 | if (fragp->fr_offset) | |
18280 | { | |
18281 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18282 | exp.X_add_number = 0; | |
18283 | } | |
18284 | ||
4d68580a RS |
18285 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18286 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18287 | fixp->fx_file = fragp->fr_file; |
18288 | fixp->fx_line = fragp->fr_line; | |
18289 | ||
4d68580a | 18290 | buf = write_insn (buf, insn); |
b34976b6 | 18291 | |
4a6a3df4 | 18292 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18293 | /* nop */ |
18294 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18295 | |
18296 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18297 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18298 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18299 | |
4d68580a RS |
18300 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18301 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18302 | fixp->fx_file = fragp->fr_file; |
18303 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18304 | |
4d68580a | 18305 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18306 | |
18307 | /* j(al)r $at. */ | |
18308 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18309 | insn = 0x0000f809; |
4a6a3df4 | 18310 | else |
66b3e8da MR |
18311 | insn = 0x00000008; |
18312 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18313 | |
4d68580a | 18314 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18315 | } |
18316 | } | |
18317 | ||
4a6a3df4 | 18318 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18319 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18320 | return; |
18321 | } | |
18322 | ||
df58fc94 RS |
18323 | /* Relax microMIPS branches. */ |
18324 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18325 | { | |
4d68580a | 18326 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18327 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18328 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18329 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18330 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18331 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18332 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18333 | bfd_boolean short_ds; |
df58fc94 RS |
18334 | unsigned long insn; |
18335 | expressionS exp; | |
18336 | fixS *fixp; | |
18337 | ||
18338 | exp.X_op = O_symbol; | |
18339 | exp.X_add_symbol = fragp->fr_symbol; | |
18340 | exp.X_add_number = fragp->fr_offset; | |
18341 | ||
18342 | fragp->fr_fix += fragp->fr_var; | |
18343 | ||
18344 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18345 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18346 | { | |
18347 | /* We generate a fixup instead of applying it right now, | |
18348 | because if there is linker relaxation, we're going to | |
18349 | need the relocations. */ | |
18350 | if (type == 'D') | |
4d68580a | 18351 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18352 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18353 | else if (type == 'E') | |
4d68580a | 18354 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18355 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18356 | else | |
18357 | abort (); | |
18358 | ||
18359 | fixp->fx_file = fragp->fr_file; | |
18360 | fixp->fx_line = fragp->fr_line; | |
18361 | ||
18362 | /* These relocations can have an addend that won't fit in | |
18363 | 2 octets. */ | |
18364 | fixp->fx_no_overflow = 1; | |
18365 | ||
18366 | return; | |
18367 | } | |
18368 | ||
2309ddf2 | 18369 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18370 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18371 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18372 | { | |
18373 | /* We generate a fixup instead of applying it right now, | |
18374 | because if there is linker relaxation, we're going to | |
18375 | need the relocations. */ | |
4d68580a RS |
18376 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18377 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18378 | fixp->fx_file = fragp->fr_file; |
18379 | fixp->fx_line = fragp->fr_line; | |
18380 | ||
18381 | if (type == 0) | |
7bd374a4 MR |
18382 | { |
18383 | insn = read_compressed_insn (buf, 4); | |
18384 | buf += 4; | |
18385 | ||
18386 | if (nods) | |
18387 | { | |
18388 | /* Check the short-delay-slot bit. */ | |
18389 | if (!al || (insn & 0x02000000) != 0) | |
18390 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18391 | else | |
18392 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18393 | } | |
18394 | ||
18395 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18396 | return; | |
18397 | } | |
df58fc94 RS |
18398 | } |
18399 | ||
18400 | /* Relax 16-bit branches to 32-bit branches. */ | |
18401 | if (type != 0) | |
18402 | { | |
4d68580a | 18403 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18404 | |
18405 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18406 | insn = 0x94000000; /* beq */ | |
18407 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18408 | { | |
18409 | unsigned long regno; | |
18410 | ||
18411 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18412 | regno = micromips_to_32_reg_d_map [regno]; | |
18413 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18414 | insn |= regno << MICROMIPSOP_SH_RS; | |
18415 | } | |
18416 | else | |
18417 | abort (); | |
18418 | ||
18419 | /* Nothing else to do, just write it out. */ | |
18420 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18421 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18422 | { | |
4d68580a | 18423 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18424 | if (nods) |
18425 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18426 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18427 | return; |
18428 | } | |
18429 | } | |
18430 | else | |
4d68580a | 18431 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18432 | |
18433 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18434 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18435 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18436 | |
2309ddf2 | 18437 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18438 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18439 | |
18440 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18441 | { | |
18442 | symbolS *l; | |
18443 | ||
18444 | /* Reverse the branch. */ | |
18445 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18446 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18447 | insn ^= 0x20000000; | |
18448 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18449 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18450 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18451 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18452 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18453 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18454 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18455 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18456 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18457 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18458 | insn ^= 0x00400000; | |
18459 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18460 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18461 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18462 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18463 | insn ^= 0x00200000; | |
56d438b1 CF |
18464 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18465 | BNZ.df */ | |
18466 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18467 | BNZ.V */ | |
18468 | insn ^= 0x00800000; | |
df58fc94 RS |
18469 | else |
18470 | abort (); | |
18471 | ||
18472 | if (al) | |
18473 | { | |
18474 | /* Clear the and-link and short-delay-slot bits. */ | |
18475 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18476 | ||
18477 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18478 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18479 | insn &= ~0x02200000; | |
18480 | } | |
18481 | ||
18482 | /* Make a label at the end for use with the branch. */ | |
18483 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18484 | micromips_label_inc (); | |
f3ded42a | 18485 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18486 | |
18487 | /* Refer to it. */ | |
4d68580a RS |
18488 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18489 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18490 | fixp->fx_file = fragp->fr_file; |
18491 | fixp->fx_line = fragp->fr_line; | |
18492 | ||
18493 | /* Branch over the jump. */ | |
4d68580a | 18494 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18495 | |
df58fc94 | 18496 | if (!compact) |
8484fb75 MR |
18497 | { |
18498 | /* nop */ | |
18499 | if (insn32) | |
18500 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18501 | else | |
18502 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18503 | } | |
df58fc94 RS |
18504 | } |
18505 | ||
ce8ad872 | 18506 | if (!pic) |
df58fc94 | 18507 | { |
7bd374a4 MR |
18508 | unsigned long jal = (short_ds || nods |
18509 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18510 | |
df58fc94 RS |
18511 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18512 | insn = al ? jal : 0xd4000000; | |
18513 | ||
4d68580a RS |
18514 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18515 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18516 | fixp->fx_file = fragp->fr_file; |
18517 | fixp->fx_line = fragp->fr_line; | |
18518 | ||
4d68580a | 18519 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18520 | |
7bd374a4 | 18521 | if (compact || nods) |
8484fb75 MR |
18522 | { |
18523 | /* nop */ | |
18524 | if (insn32) | |
18525 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18526 | else | |
18527 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18528 | } | |
df58fc94 RS |
18529 | } |
18530 | else | |
18531 | { | |
18532 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18533 | ||
18534 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18535 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18536 | insn |= at << MICROMIPSOP_SH_RT; | |
18537 | ||
18538 | if (exp.X_add_number) | |
18539 | { | |
18540 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18541 | exp.X_add_number = 0; | |
18542 | } | |
18543 | ||
4d68580a RS |
18544 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18545 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18546 | fixp->fx_file = fragp->fr_file; |
18547 | fixp->fx_line = fragp->fr_line; | |
18548 | ||
4d68580a | 18549 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18550 | |
18551 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18552 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18553 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18554 | ||
4d68580a RS |
18555 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18556 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18557 | fixp->fx_file = fragp->fr_file; |
18558 | fixp->fx_line = fragp->fr_line; | |
18559 | ||
4d68580a | 18560 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18561 | |
8484fb75 MR |
18562 | if (insn32) |
18563 | { | |
18564 | /* jr/jalr $at */ | |
18565 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18566 | insn |= at << MICROMIPSOP_SH_RS; | |
18567 | ||
18568 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18569 | |
7bd374a4 | 18570 | if (compact || nods) |
8484fb75 MR |
18571 | /* nop */ |
18572 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18573 | } | |
18574 | else | |
18575 | { | |
18576 | /* jr/jrc/jalr/jalrs $at */ | |
18577 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18578 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18579 | |
18580 | insn = al ? jalr : jr; | |
18581 | insn |= at << MICROMIPSOP_SH_MJ; | |
18582 | ||
18583 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18584 | if (al && nods) |
18585 | { | |
18586 | /* nop */ | |
18587 | if (short_ds) | |
18588 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18589 | else | |
18590 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18591 | } | |
8484fb75 | 18592 | } |
df58fc94 RS |
18593 | } |
18594 | ||
4d68580a | 18595 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18596 | return; |
18597 | } | |
18598 | ||
252b5132 RH |
18599 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18600 | { | |
18601 | int type; | |
3ccad066 | 18602 | const struct mips_int_operand *operand; |
252b5132 | 18603 | offsetT val; |
5c04167a | 18604 | char *buf; |
8507b6e7 | 18605 | unsigned int user_length; |
9d862524 | 18606 | bfd_boolean need_reloc; |
252b5132 | 18607 | unsigned long insn; |
8507b6e7 | 18608 | bfd_boolean mac; |
5c04167a | 18609 | bfd_boolean ext; |
88a7ef16 | 18610 | segT symsec; |
252b5132 RH |
18611 | |
18612 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18613 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18614 | |
8507b6e7 | 18615 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18616 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18617 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18618 | |
18619 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18620 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18621 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18622 | ? asec != symsec |
18623 | : !bfd_is_abs_section (symsec))); | |
18624 | ||
8507b6e7 | 18625 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18626 | { |
3ccad066 | 18627 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18628 | |
3ccad066 | 18629 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18630 | |
14f72d45 | 18631 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18632 | { |
14f72d45 MR |
18633 | if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) |
18634 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18635 | _("branch to a symbol in another ISA mode")); | |
18636 | else if ((fragp->fr_offset & 0x1) != 0) | |
18637 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18638 | _("branch to misaligned address (0x%lx)"), | |
18639 | (long) val); | |
252b5132 | 18640 | } |
252b5132 | 18641 | |
14f72d45 | 18642 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18643 | |
18644 | /* Make sure the section winds up with the alignment we have | |
18645 | assumed. */ | |
3ccad066 RS |
18646 | if (operand->shift > 0) |
18647 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18648 | } |
18649 | ||
8507b6e7 MR |
18650 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18651 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18652 | { | |
18653 | if (mac) | |
18654 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18655 | _("macro instruction expanded into multiple " | |
18656 | "instructions in a branch delay slot")); | |
18657 | else if (ext) | |
18658 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18659 | _("extended instruction in a branch delay slot")); | |
18660 | } | |
18661 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18662 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18663 | _("macro instruction expanded into multiple " |
18664 | "instructions")); | |
252b5132 | 18665 | |
5c04167a | 18666 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18667 | |
4d68580a | 18668 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18669 | if (ext) |
18670 | insn |= MIPS16_EXTEND; | |
252b5132 | 18671 | |
5c04167a RS |
18672 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18673 | user_length = 4; | |
18674 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18675 | user_length = 2; | |
18676 | else | |
18677 | user_length = 0; | |
18678 | ||
8507b6e7 | 18679 | if (mac) |
c9775dde | 18680 | { |
8507b6e7 MR |
18681 | unsigned long reg; |
18682 | unsigned long new; | |
18683 | unsigned long op; | |
25499ac7 | 18684 | bfd_boolean e2; |
8507b6e7 MR |
18685 | |
18686 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18687 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18688 | |
25499ac7 MR |
18689 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
18690 | ||
8507b6e7 | 18691 | if (need_reloc) |
c9775dde | 18692 | { |
8507b6e7 MR |
18693 | fixS *fixp; |
18694 | ||
18695 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18696 | ||
18697 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18698 | fragp->fr_symbol, fragp->fr_offset, | |
18699 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18700 | fixp->fx_file = fragp->fr_file; | |
18701 | fixp->fx_line = fragp->fr_line; | |
18702 | ||
25499ac7 | 18703 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
18704 | fragp->fr_symbol, fragp->fr_offset, |
18705 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18706 | fixp->fx_file = fragp->fr_file; | |
18707 | fixp->fx_line = fragp->fr_line; | |
18708 | ||
18709 | val = 0; | |
18710 | } | |
18711 | ||
18712 | switch (insn & 0xf800) | |
18713 | { | |
18714 | case 0x0800: /* ADDIU */ | |
18715 | reg = (insn >> 8) & 0x7; | |
18716 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18717 | break; |
8507b6e7 MR |
18718 | case 0xb000: /* LW */ |
18719 | reg = (insn >> 8) & 0x7; | |
18720 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18721 | break; |
8507b6e7 MR |
18722 | case 0xf800: /* I64 */ |
18723 | reg = (insn >> 5) & 0x7; | |
18724 | switch (insn & 0x0700) | |
18725 | { | |
18726 | case 0x0400: /* LD */ | |
18727 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18728 | break; | |
18729 | case 0x0600: /* DADDIU */ | |
18730 | op = 0xf000fd00 | (reg << 5); | |
18731 | break; | |
18732 | default: | |
18733 | abort (); | |
18734 | } | |
18735 | break; | |
18736 | default: | |
18737 | abort (); | |
c9775dde | 18738 | } |
8507b6e7 | 18739 | |
25499ac7 | 18740 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
18741 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
18742 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
18743 | if (!e2) |
18744 | { | |
18745 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18746 | buf = write_compressed_insn (buf, new, 4); | |
18747 | } | |
8507b6e7 MR |
18748 | op |= mips16_immed_extend (val, 16); |
18749 | buf = write_compressed_insn (buf, op, 4); | |
18750 | ||
25499ac7 | 18751 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
18752 | } |
18753 | else | |
18754 | { | |
18755 | unsigned int length = ext ? 4 : 2; | |
18756 | ||
18757 | if (need_reloc) | |
c9775dde | 18758 | { |
8507b6e7 MR |
18759 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
18760 | expressionS exp; | |
18761 | fixS *fixp; | |
c9775dde | 18762 | |
8507b6e7 MR |
18763 | switch (type) |
18764 | { | |
18765 | case 'p': | |
18766 | case 'q': | |
18767 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18768 | break; | |
18769 | default: | |
18770 | break; | |
18771 | } | |
18772 | if (mac || reloc == BFD_RELOC_NONE) | |
18773 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18774 | _("unsupported relocation")); | |
18775 | else if (ext) | |
18776 | { | |
18777 | exp.X_op = O_symbol; | |
18778 | exp.X_add_symbol = fragp->fr_symbol; | |
18779 | exp.X_add_number = fragp->fr_offset; | |
c9775dde | 18780 | |
8507b6e7 MR |
18781 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18782 | TRUE, reloc); | |
18783 | ||
18784 | fixp->fx_file = fragp->fr_file; | |
18785 | fixp->fx_line = fragp->fr_line; | |
18786 | } | |
18787 | else | |
18788 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18789 | _("invalid unextended operand value")); | |
c9775dde | 18790 | } |
eefc3365 | 18791 | else |
8507b6e7 MR |
18792 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18793 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18794 | |
8507b6e7 MR |
18795 | gas_assert (mips16_opcode_length (insn) == length); |
18796 | write_compressed_insn (buf, insn, length); | |
18797 | fragp->fr_fix += length; | |
18798 | } | |
252b5132 RH |
18799 | } |
18800 | else | |
18801 | { | |
df58fc94 RS |
18802 | relax_substateT subtype = fragp->fr_subtype; |
18803 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18804 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18805 | int first, second; |
18806 | fixS *fixp; | |
252b5132 | 18807 | |
df58fc94 RS |
18808 | first = RELAX_FIRST (subtype); |
18809 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18810 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18811 | |
df58fc94 RS |
18812 | /* If the delay slot chosen does not match the size of the instruction, |
18813 | then emit a warning. */ | |
18814 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18815 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18816 | { | |
18817 | relax_substateT s; | |
18818 | const char *msg; | |
18819 | ||
18820 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18821 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18822 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18823 | msg = macro_warning (s); | |
18824 | if (msg != NULL) | |
db9b2be4 | 18825 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18826 | subtype &= ~s; |
18827 | } | |
18828 | ||
584892a6 | 18829 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18830 | if (use_second == second_longer) |
584892a6 | 18831 | { |
df58fc94 RS |
18832 | relax_substateT s; |
18833 | const char *msg; | |
18834 | ||
18835 | s = (subtype | |
18836 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18837 | msg = macro_warning (s); | |
18838 | if (msg != NULL) | |
db9b2be4 | 18839 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18840 | subtype &= ~s; |
584892a6 RS |
18841 | } |
18842 | ||
4d7206a2 RS |
18843 | /* Go through all the fixups for the first sequence. Disable them |
18844 | (by marking them as done) if we're going to use the second | |
18845 | sequence instead. */ | |
18846 | while (fixp | |
18847 | && fixp->fx_frag == fragp | |
18848 | && fixp->fx_where < fragp->fr_fix - second) | |
18849 | { | |
df58fc94 | 18850 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18851 | fixp->fx_done = 1; |
18852 | fixp = fixp->fx_next; | |
18853 | } | |
252b5132 | 18854 | |
4d7206a2 RS |
18855 | /* Go through the fixups for the second sequence. Disable them if |
18856 | we're going to use the first sequence, otherwise adjust their | |
18857 | addresses to account for the relaxation. */ | |
18858 | while (fixp && fixp->fx_frag == fragp) | |
18859 | { | |
df58fc94 | 18860 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18861 | fixp->fx_where -= first; |
18862 | else | |
18863 | fixp->fx_done = 1; | |
18864 | fixp = fixp->fx_next; | |
18865 | } | |
18866 | ||
18867 | /* Now modify the frag contents. */ | |
df58fc94 | 18868 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18869 | { |
18870 | char *start; | |
18871 | ||
18872 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18873 | memmove (start, start + first, second); | |
18874 | fragp->fr_fix -= first; | |
18875 | } | |
18876 | else | |
18877 | fragp->fr_fix -= second; | |
252b5132 RH |
18878 | } |
18879 | } | |
18880 | ||
252b5132 RH |
18881 | /* This function is called after the relocs have been generated. |
18882 | We've been storing mips16 text labels as odd. Here we convert them | |
18883 | back to even for the convenience of the debugger. */ | |
18884 | ||
18885 | void | |
17a2f251 | 18886 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18887 | { |
18888 | asymbol **syms; | |
18889 | unsigned int count, i; | |
18890 | ||
252b5132 RH |
18891 | syms = bfd_get_outsymbols (stdoutput); |
18892 | count = bfd_get_symcount (stdoutput); | |
18893 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18894 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18895 | && ((*syms)->value & 1) != 0) | |
18896 | { | |
18897 | (*syms)->value &= ~1; | |
18898 | /* If the symbol has an odd size, it was probably computed | |
18899 | incorrectly, so adjust that as well. */ | |
18900 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18901 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18902 | } | |
252b5132 RH |
18903 | } |
18904 | ||
a1facbec MR |
18905 | /* This function is called whenever a label is defined, including fake |
18906 | labels instantiated off the dot special symbol. It is used when | |
18907 | handling branch delays; if a branch has a label, we assume we cannot | |
18908 | move it. This also bumps the value of the symbol by 1 in compressed | |
18909 | code. */ | |
252b5132 | 18910 | |
e1b47bd5 | 18911 | static void |
a1facbec | 18912 | mips_record_label (symbolS *sym) |
252b5132 | 18913 | { |
a8dbcb85 | 18914 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18915 | struct insn_label_list *l; |
18916 | ||
18917 | if (free_insn_labels == NULL) | |
325801bd | 18918 | l = XNEW (struct insn_label_list); |
252b5132 RH |
18919 | else |
18920 | { | |
18921 | l = free_insn_labels; | |
18922 | free_insn_labels = l->next; | |
18923 | } | |
18924 | ||
18925 | l->label = sym; | |
a8dbcb85 TS |
18926 | l->next = si->label_list; |
18927 | si->label_list = l; | |
a1facbec | 18928 | } |
07a53e5c | 18929 | |
a1facbec MR |
18930 | /* This function is called as tc_frob_label() whenever a label is defined |
18931 | and adds a DWARF-2 record we only want for true labels. */ | |
18932 | ||
18933 | void | |
18934 | mips_define_label (symbolS *sym) | |
18935 | { | |
18936 | mips_record_label (sym); | |
07a53e5c | 18937 | dwarf2_emit_label (sym); |
252b5132 | 18938 | } |
e1b47bd5 RS |
18939 | |
18940 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18941 | is defined. */ | |
18942 | ||
18943 | void | |
18944 | mips_add_dot_label (symbolS *sym) | |
18945 | { | |
18946 | mips_record_label (sym); | |
18947 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18948 | mips_compressed_mark_label (sym); | |
18949 | } | |
252b5132 | 18950 | \f |
351cdf24 MF |
18951 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
18952 | static unsigned int | |
18953 | mips_convert_ase_flags (int ase) | |
18954 | { | |
18955 | unsigned int ext_ases = 0; | |
18956 | ||
18957 | if (ase & ASE_DSP) | |
18958 | ext_ases |= AFL_ASE_DSP; | |
18959 | if (ase & ASE_DSPR2) | |
18960 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
18961 | if (ase & ASE_DSPR3) |
18962 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
18963 | if (ase & ASE_EVA) |
18964 | ext_ases |= AFL_ASE_EVA; | |
18965 | if (ase & ASE_MCU) | |
18966 | ext_ases |= AFL_ASE_MCU; | |
18967 | if (ase & ASE_MDMX) | |
18968 | ext_ases |= AFL_ASE_MDMX; | |
18969 | if (ase & ASE_MIPS3D) | |
18970 | ext_ases |= AFL_ASE_MIPS3D; | |
18971 | if (ase & ASE_MT) | |
18972 | ext_ases |= AFL_ASE_MT; | |
18973 | if (ase & ASE_SMARTMIPS) | |
18974 | ext_ases |= AFL_ASE_SMARTMIPS; | |
18975 | if (ase & ASE_VIRT) | |
18976 | ext_ases |= AFL_ASE_VIRT; | |
18977 | if (ase & ASE_MSA) | |
18978 | ext_ases |= AFL_ASE_MSA; | |
18979 | if (ase & ASE_XPA) | |
18980 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
18981 | if (ase & ASE_MIPS16E2) |
18982 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
351cdf24 MF |
18983 | |
18984 | return ext_ases; | |
18985 | } | |
252b5132 RH |
18986 | /* Some special processing for a MIPS ELF file. */ |
18987 | ||
18988 | void | |
17a2f251 | 18989 | mips_elf_final_processing (void) |
252b5132 | 18990 | { |
351cdf24 MF |
18991 | int fpabi; |
18992 | Elf_Internal_ABIFlags_v0 flags; | |
18993 | ||
18994 | flags.version = 0; | |
18995 | flags.isa_rev = 0; | |
18996 | switch (file_mips_opts.isa) | |
18997 | { | |
18998 | case INSN_ISA1: | |
18999 | flags.isa_level = 1; | |
19000 | break; | |
19001 | case INSN_ISA2: | |
19002 | flags.isa_level = 2; | |
19003 | break; | |
19004 | case INSN_ISA3: | |
19005 | flags.isa_level = 3; | |
19006 | break; | |
19007 | case INSN_ISA4: | |
19008 | flags.isa_level = 4; | |
19009 | break; | |
19010 | case INSN_ISA5: | |
19011 | flags.isa_level = 5; | |
19012 | break; | |
19013 | case INSN_ISA32: | |
19014 | flags.isa_level = 32; | |
19015 | flags.isa_rev = 1; | |
19016 | break; | |
19017 | case INSN_ISA32R2: | |
19018 | flags.isa_level = 32; | |
19019 | flags.isa_rev = 2; | |
19020 | break; | |
19021 | case INSN_ISA32R3: | |
19022 | flags.isa_level = 32; | |
19023 | flags.isa_rev = 3; | |
19024 | break; | |
19025 | case INSN_ISA32R5: | |
19026 | flags.isa_level = 32; | |
19027 | flags.isa_rev = 5; | |
19028 | break; | |
09c14161 MF |
19029 | case INSN_ISA32R6: |
19030 | flags.isa_level = 32; | |
19031 | flags.isa_rev = 6; | |
19032 | break; | |
351cdf24 MF |
19033 | case INSN_ISA64: |
19034 | flags.isa_level = 64; | |
19035 | flags.isa_rev = 1; | |
19036 | break; | |
19037 | case INSN_ISA64R2: | |
19038 | flags.isa_level = 64; | |
19039 | flags.isa_rev = 2; | |
19040 | break; | |
19041 | case INSN_ISA64R3: | |
19042 | flags.isa_level = 64; | |
19043 | flags.isa_rev = 3; | |
19044 | break; | |
19045 | case INSN_ISA64R5: | |
19046 | flags.isa_level = 64; | |
19047 | flags.isa_rev = 5; | |
19048 | break; | |
09c14161 MF |
19049 | case INSN_ISA64R6: |
19050 | flags.isa_level = 64; | |
19051 | flags.isa_rev = 6; | |
19052 | break; | |
351cdf24 MF |
19053 | } |
19054 | ||
19055 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19056 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19057 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19058 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19059 | : AFL_REG_32; | |
19060 | flags.cpr2_size = AFL_REG_NONE; | |
19061 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19062 | Tag_GNU_MIPS_ABI_FP); | |
19063 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19064 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19065 | if (file_ase_mips16) | |
19066 | flags.ases |= AFL_ASE_MIPS16; | |
19067 | if (file_ase_micromips) | |
19068 | flags.ases |= AFL_ASE_MICROMIPS; | |
19069 | flags.flags1 = 0; | |
19070 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19071 | || file_mips_opts.fp == 64) | |
19072 | && file_mips_opts.oddspreg) | |
19073 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19074 | flags.flags2 = 0; | |
19075 | ||
19076 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19077 | ((Elf_External_ABIFlags_v0 *) | |
19078 | mips_flags_frag)); | |
19079 | ||
252b5132 | 19080 | /* Write out the register information. */ |
316f5878 | 19081 | if (mips_abi != N64_ABI) |
252b5132 RH |
19082 | { |
19083 | Elf32_RegInfo s; | |
19084 | ||
19085 | s.ri_gprmask = mips_gprmask; | |
19086 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19087 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19088 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19089 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19090 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19091 | ||
19092 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19093 | ((Elf32_External_RegInfo *) | |
19094 | mips_regmask_frag)); | |
19095 | } | |
19096 | else | |
19097 | { | |
19098 | Elf64_Internal_RegInfo s; | |
19099 | ||
19100 | s.ri_gprmask = mips_gprmask; | |
19101 | s.ri_pad = 0; | |
19102 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19103 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19104 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19105 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19106 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19107 | ||
19108 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19109 | ((Elf64_External_RegInfo *) | |
19110 | mips_regmask_frag)); | |
19111 | } | |
19112 | ||
19113 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19114 | sort of BFD interface for this. */ | |
19115 | if (mips_any_noreorder) | |
19116 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19117 | if (mips_pic != NO_PIC) | |
143d77c5 | 19118 | { |
8b828383 | 19119 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19120 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19121 | } | |
19122 | if (mips_abicalls) | |
19123 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19124 | |
b015e599 AP |
19125 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19126 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19127 | if (file_ase_mips16) |
19128 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19129 | if (file_ase_micromips) |
19130 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19131 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19132 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19133 | |
bdaaa2e1 | 19134 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19135 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19136 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19137 | else if (mips_abi == O64_ABI) |
252b5132 | 19138 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19139 | else if (mips_abi == EABI_ABI) |
252b5132 | 19140 | { |
bad1aba3 | 19141 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19142 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19143 | else | |
19144 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19145 | } | |
316f5878 | 19146 | else if (mips_abi == N32_ABI) |
be00bddd TS |
19147 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
19148 | ||
c9914766 | 19149 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
19150 | |
19151 | if (mips_32bitmode) | |
19152 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19153 | |
7361da2c | 19154 | if (mips_nan2008 == 1) |
ba92f887 MR |
19155 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19156 | ||
ad3fea08 | 19157 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19158 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19159 | Tag_GNU_MIPS_ABI_FP); | |
19160 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19161 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19162 | } |
252b5132 | 19163 | \f |
beae10d5 | 19164 | typedef struct proc { |
9b2f1d35 EC |
19165 | symbolS *func_sym; |
19166 | symbolS *func_end_sym; | |
beae10d5 KH |
19167 | unsigned long reg_mask; |
19168 | unsigned long reg_offset; | |
19169 | unsigned long fpreg_mask; | |
19170 | unsigned long fpreg_offset; | |
19171 | unsigned long frame_offset; | |
19172 | unsigned long frame_reg; | |
19173 | unsigned long pc_reg; | |
19174 | } procS; | |
252b5132 RH |
19175 | |
19176 | static procS cur_proc; | |
19177 | static procS *cur_proc_ptr; | |
19178 | static int numprocs; | |
19179 | ||
df58fc94 RS |
19180 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19181 | as "2", and a normal nop as "0". */ | |
19182 | ||
19183 | #define NOP_OPCODE_MIPS 0 | |
19184 | #define NOP_OPCODE_MIPS16 1 | |
19185 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19186 | |
19187 | char | |
19188 | mips_nop_opcode (void) | |
19189 | { | |
df58fc94 RS |
19190 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19191 | return NOP_OPCODE_MICROMIPS; | |
19192 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19193 | return NOP_OPCODE_MIPS16; | |
19194 | else | |
19195 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19196 | } |
19197 | ||
df58fc94 RS |
19198 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19199 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19200 | |
0a9ef439 | 19201 | void |
17a2f251 | 19202 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19203 | { |
df58fc94 | 19204 | char nop_opcode; |
742a56fe | 19205 | char *p; |
c67a084a NC |
19206 | int bytes, size, excess; |
19207 | valueT opcode; | |
742a56fe | 19208 | |
0a9ef439 RH |
19209 | if (fragp->fr_type != rs_align_code) |
19210 | return; | |
19211 | ||
742a56fe | 19212 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19213 | nop_opcode = *p; |
19214 | switch (nop_opcode) | |
a19d8eb0 | 19215 | { |
df58fc94 RS |
19216 | case NOP_OPCODE_MICROMIPS: |
19217 | opcode = micromips_nop32_insn.insn_opcode; | |
19218 | size = 4; | |
19219 | break; | |
19220 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19221 | opcode = mips16_nop_insn.insn_opcode; |
19222 | size = 2; | |
df58fc94 RS |
19223 | break; |
19224 | case NOP_OPCODE_MIPS: | |
19225 | default: | |
c67a084a NC |
19226 | opcode = nop_insn.insn_opcode; |
19227 | size = 4; | |
df58fc94 | 19228 | break; |
c67a084a | 19229 | } |
a19d8eb0 | 19230 | |
c67a084a NC |
19231 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19232 | excess = bytes % size; | |
df58fc94 RS |
19233 | |
19234 | /* Handle the leading part if we're not inserting a whole number of | |
19235 | instructions, and make it the end of the fixed part of the frag. | |
19236 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19237 | and use zeroes otherwise. */ | |
19238 | gas_assert (excess < 4); | |
19239 | fragp->fr_fix += excess; | |
19240 | switch (excess) | |
c67a084a | 19241 | { |
df58fc94 RS |
19242 | case 3: |
19243 | *p++ = '\0'; | |
19244 | /* Fall through. */ | |
19245 | case 2: | |
833794fc | 19246 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19247 | { |
4d68580a | 19248 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19249 | break; |
19250 | } | |
19251 | *p++ = '\0'; | |
19252 | /* Fall through. */ | |
19253 | case 1: | |
19254 | *p++ = '\0'; | |
19255 | /* Fall through. */ | |
19256 | case 0: | |
19257 | break; | |
a19d8eb0 | 19258 | } |
c67a084a NC |
19259 | |
19260 | md_number_to_chars (p, opcode, size); | |
19261 | fragp->fr_var = size; | |
a19d8eb0 CP |
19262 | } |
19263 | ||
252b5132 | 19264 | static long |
17a2f251 | 19265 | get_number (void) |
252b5132 RH |
19266 | { |
19267 | int negative = 0; | |
19268 | long val = 0; | |
19269 | ||
19270 | if (*input_line_pointer == '-') | |
19271 | { | |
19272 | ++input_line_pointer; | |
19273 | negative = 1; | |
19274 | } | |
3882b010 | 19275 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19276 | as_bad (_("expected simple number")); |
252b5132 RH |
19277 | if (input_line_pointer[0] == '0') |
19278 | { | |
19279 | if (input_line_pointer[1] == 'x') | |
19280 | { | |
19281 | input_line_pointer += 2; | |
3882b010 | 19282 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19283 | { |
19284 | val <<= 4; | |
19285 | val |= hex_value (*input_line_pointer++); | |
19286 | } | |
19287 | return negative ? -val : val; | |
19288 | } | |
19289 | else | |
19290 | { | |
19291 | ++input_line_pointer; | |
3882b010 | 19292 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19293 | { |
19294 | val <<= 3; | |
19295 | val |= *input_line_pointer++ - '0'; | |
19296 | } | |
19297 | return negative ? -val : val; | |
19298 | } | |
19299 | } | |
3882b010 | 19300 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19301 | { |
19302 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19303 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19304 | as_warn (_("invalid number")); |
252b5132 RH |
19305 | return -1; |
19306 | } | |
3882b010 | 19307 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19308 | { |
19309 | val *= 10; | |
19310 | val += *input_line_pointer++ - '0'; | |
19311 | } | |
19312 | return negative ? -val : val; | |
19313 | } | |
19314 | ||
19315 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19316 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19317 | case .file implies DWARF-2. */ | |
19318 | ||
19319 | static void | |
17a2f251 | 19320 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19321 | { |
ecb4347a DJ |
19322 | static int first_file_directive = 0; |
19323 | ||
c5dd6aab DJ |
19324 | if (ECOFF_DEBUGGING) |
19325 | { | |
19326 | get_number (); | |
19327 | s_app_file (0); | |
19328 | } | |
19329 | else | |
ecb4347a DJ |
19330 | { |
19331 | char *filename; | |
19332 | ||
19333 | filename = dwarf2_directive_file (0); | |
19334 | ||
19335 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19336 | directive even for stabs output. Make sure that this | |
19337 | ".file" is handled. Note that you need a version of GCC | |
19338 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19339 | if (filename != NULL && ! first_file_directive) | |
19340 | { | |
19341 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19342 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19343 | } |
19344 | first_file_directive = 1; | |
19345 | } | |
c5dd6aab DJ |
19346 | } |
19347 | ||
19348 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19349 | |
19350 | static void | |
17a2f251 | 19351 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19352 | { |
c5dd6aab DJ |
19353 | if (!ECOFF_DEBUGGING) |
19354 | dwarf2_directive_loc (0); | |
252b5132 RH |
19355 | } |
19356 | ||
252b5132 RH |
19357 | /* The .end directive. */ |
19358 | ||
19359 | static void | |
17a2f251 | 19360 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19361 | { |
19362 | symbolS *p; | |
252b5132 | 19363 | |
7a621144 DJ |
19364 | /* Following functions need their own .frame and .cprestore directives. */ |
19365 | mips_frame_reg_valid = 0; | |
19366 | mips_cprestore_valid = 0; | |
19367 | ||
252b5132 RH |
19368 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19369 | { | |
19370 | p = get_symbol (); | |
19371 | demand_empty_rest_of_line (); | |
19372 | } | |
19373 | else | |
19374 | p = NULL; | |
19375 | ||
14949570 | 19376 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19377 | as_warn (_(".end not in text section")); |
19378 | ||
19379 | if (!cur_proc_ptr) | |
19380 | { | |
1661c76c | 19381 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19382 | demand_empty_rest_of_line (); |
19383 | return; | |
19384 | } | |
19385 | ||
19386 | if (p != NULL) | |
19387 | { | |
9c2799c2 | 19388 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19389 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19390 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19391 | |
19392 | if (debug_type == DEBUG_STABS) | |
19393 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19394 | S_GET_NAME (p)); | |
252b5132 RH |
19395 | } |
19396 | else | |
19397 | as_warn (_(".end directive missing or unknown symbol")); | |
19398 | ||
9b2f1d35 EC |
19399 | /* Create an expression to calculate the size of the function. */ |
19400 | if (p && cur_proc_ptr) | |
19401 | { | |
19402 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19403 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19404 | |
19405 | obj->size = exp; | |
19406 | exp->X_op = O_subtract; | |
19407 | exp->X_add_symbol = symbol_temp_new_now (); | |
19408 | exp->X_op_symbol = p; | |
19409 | exp->X_add_number = 0; | |
19410 | ||
19411 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19412 | } | |
19413 | ||
5ff6a06c MR |
19414 | #ifdef md_flush_pending_output |
19415 | md_flush_pending_output (); | |
19416 | #endif | |
19417 | ||
ecb4347a | 19418 | /* Generate a .pdr section. */ |
f3ded42a | 19419 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19420 | { |
19421 | segT saved_seg = now_seg; | |
19422 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19423 | expressionS exp; |
19424 | char *fragp; | |
252b5132 | 19425 | |
9c2799c2 | 19426 | gas_assert (pdr_seg); |
ecb4347a | 19427 | subseg_set (pdr_seg, 0); |
252b5132 | 19428 | |
ecb4347a DJ |
19429 | /* Write the symbol. */ |
19430 | exp.X_op = O_symbol; | |
19431 | exp.X_add_symbol = p; | |
19432 | exp.X_add_number = 0; | |
19433 | emit_expr (&exp, 4); | |
252b5132 | 19434 | |
ecb4347a | 19435 | fragp = frag_more (7 * 4); |
252b5132 | 19436 | |
17a2f251 TS |
19437 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19438 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19439 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19440 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19441 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19442 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19443 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19444 | |
ecb4347a DJ |
19445 | subseg_set (saved_seg, saved_subseg); |
19446 | } | |
252b5132 RH |
19447 | |
19448 | cur_proc_ptr = NULL; | |
19449 | } | |
19450 | ||
19451 | /* The .aent and .ent directives. */ | |
19452 | ||
19453 | static void | |
17a2f251 | 19454 | s_mips_ent (int aent) |
252b5132 | 19455 | { |
252b5132 | 19456 | symbolS *symbolP; |
252b5132 RH |
19457 | |
19458 | symbolP = get_symbol (); | |
19459 | if (*input_line_pointer == ',') | |
f9419b05 | 19460 | ++input_line_pointer; |
252b5132 | 19461 | SKIP_WHITESPACE (); |
3882b010 | 19462 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19463 | || *input_line_pointer == '-') |
874e8986 | 19464 | get_number (); |
252b5132 | 19465 | |
14949570 | 19466 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19467 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19468 | |
19469 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19470 | as_warn (_("missing .end")); |
252b5132 RH |
19471 | |
19472 | if (!aent) | |
19473 | { | |
7a621144 DJ |
19474 | /* This function needs its own .frame and .cprestore directives. */ |
19475 | mips_frame_reg_valid = 0; | |
19476 | mips_cprestore_valid = 0; | |
19477 | ||
252b5132 RH |
19478 | cur_proc_ptr = &cur_proc; |
19479 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19480 | ||
9b2f1d35 | 19481 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19482 | |
f9419b05 | 19483 | ++numprocs; |
ecb4347a DJ |
19484 | |
19485 | if (debug_type == DEBUG_STABS) | |
19486 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19487 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19488 | } |
19489 | ||
7c0fc524 MR |
19490 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19491 | ||
252b5132 RH |
19492 | demand_empty_rest_of_line (); |
19493 | } | |
19494 | ||
19495 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19496 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19497 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19498 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19499 | symbol table (in the mdebug section). */ |
19500 | ||
19501 | static void | |
17a2f251 | 19502 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19503 | { |
f3ded42a RS |
19504 | if (ECOFF_DEBUGGING) |
19505 | s_ignore (ignore); | |
19506 | else | |
ecb4347a DJ |
19507 | { |
19508 | long val; | |
252b5132 | 19509 | |
ecb4347a DJ |
19510 | if (cur_proc_ptr == (procS *) NULL) |
19511 | { | |
19512 | as_warn (_(".frame outside of .ent")); | |
19513 | demand_empty_rest_of_line (); | |
19514 | return; | |
19515 | } | |
252b5132 | 19516 | |
ecb4347a DJ |
19517 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19518 | ||
19519 | SKIP_WHITESPACE (); | |
19520 | if (*input_line_pointer++ != ',' | |
19521 | || get_absolute_expression_and_terminator (&val) != ',') | |
19522 | { | |
1661c76c | 19523 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19524 | --input_line_pointer; |
19525 | demand_empty_rest_of_line (); | |
19526 | return; | |
19527 | } | |
252b5132 | 19528 | |
ecb4347a DJ |
19529 | cur_proc_ptr->frame_offset = val; |
19530 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19531 | |
252b5132 | 19532 | demand_empty_rest_of_line (); |
252b5132 | 19533 | } |
252b5132 RH |
19534 | } |
19535 | ||
bdaaa2e1 KH |
19536 | /* The .fmask and .mask directives. If the mdebug section is present |
19537 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19538 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19539 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19540 | make reference to the ecoff symbol table (in the mdebug section). */ |
19541 | ||
19542 | static void | |
17a2f251 | 19543 | s_mips_mask (int reg_type) |
252b5132 | 19544 | { |
f3ded42a RS |
19545 | if (ECOFF_DEBUGGING) |
19546 | s_ignore (reg_type); | |
19547 | else | |
252b5132 | 19548 | { |
ecb4347a | 19549 | long mask, off; |
252b5132 | 19550 | |
ecb4347a DJ |
19551 | if (cur_proc_ptr == (procS *) NULL) |
19552 | { | |
19553 | as_warn (_(".mask/.fmask outside of .ent")); | |
19554 | demand_empty_rest_of_line (); | |
19555 | return; | |
19556 | } | |
252b5132 | 19557 | |
ecb4347a DJ |
19558 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19559 | { | |
1661c76c | 19560 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19561 | --input_line_pointer; |
19562 | demand_empty_rest_of_line (); | |
19563 | return; | |
19564 | } | |
252b5132 | 19565 | |
ecb4347a DJ |
19566 | off = get_absolute_expression (); |
19567 | ||
19568 | if (reg_type == 'F') | |
19569 | { | |
19570 | cur_proc_ptr->fpreg_mask = mask; | |
19571 | cur_proc_ptr->fpreg_offset = off; | |
19572 | } | |
19573 | else | |
19574 | { | |
19575 | cur_proc_ptr->reg_mask = mask; | |
19576 | cur_proc_ptr->reg_offset = off; | |
19577 | } | |
19578 | ||
19579 | demand_empty_rest_of_line (); | |
252b5132 | 19580 | } |
252b5132 RH |
19581 | } |
19582 | ||
316f5878 RS |
19583 | /* A table describing all the processors gas knows about. Names are |
19584 | matched in the order listed. | |
e7af610e | 19585 | |
316f5878 RS |
19586 | To ease comparison, please keep this table in the same order as |
19587 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19588 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19589 | { | |
316f5878 | 19590 | /* Entries for generic ISAs */ |
d16afab6 RS |
19591 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19592 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19593 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19594 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19595 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19596 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19597 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19598 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19599 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19600 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19601 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19602 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19603 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19604 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19605 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19606 | |
19607 | /* MIPS I */ | |
d16afab6 RS |
19608 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19609 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19610 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19611 | |
19612 | /* MIPS II */ | |
d16afab6 | 19613 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19614 | |
19615 | /* MIPS III */ | |
d16afab6 RS |
19616 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19617 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19618 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19619 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19620 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19621 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19622 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19623 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19624 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19625 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19626 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19627 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19628 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19629 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19630 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19631 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19632 | |
19633 | /* MIPS IV */ | |
d16afab6 RS |
19634 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19635 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19636 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19637 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19638 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19639 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19640 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19641 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19642 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19643 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19644 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19645 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19646 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19647 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19648 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19649 | |
19650 | /* MIPS 32 */ | |
d16afab6 RS |
19651 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19652 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19653 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19654 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19655 | |
19656 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19657 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19658 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19659 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19660 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19661 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19662 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19663 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19664 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19665 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19666 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19667 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19668 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19669 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19670 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19671 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19672 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19673 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19674 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19675 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19676 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19677 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19678 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19679 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19680 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19681 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19682 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19683 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19684 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19685 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19686 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19687 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19688 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19689 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19690 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19691 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19692 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19693 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19694 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19695 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19696 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19697 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19698 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19699 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19700 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19701 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19702 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19703 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19704 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19705 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19706 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19707 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19708 | /* interaptiv is the new name for 1004kf */ |
19709 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
38bf472a MR |
19710 | { "interaptiv-mr2", 0, |
19711 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
19712 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
c6e5c03a RS |
19713 | /* M5100 family */ |
19714 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19715 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19716 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19717 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19718 | |
316f5878 | 19719 | /* MIPS 64 */ |
d16afab6 RS |
19720 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19721 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19722 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19723 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19724 | |
c7a23324 | 19725 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19726 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19727 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19728 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19729 | |
4ba154f5 | 19730 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 19731 | |
ed163775 MR |
19732 | /* MIPS 64 Release 2 */ |
19733 | ||
967344c6 | 19734 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19735 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19736 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19737 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19738 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19739 | |
52b6b6b9 | 19740 | /* RMI Xlr */ |
d16afab6 | 19741 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19742 | |
55a36193 MK |
19743 | /* Broadcom XLP. |
19744 | XLP is mostly like XLR, with the prominent exception that it is | |
19745 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19746 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19747 | |
a4968f42 | 19748 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19749 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19750 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19751 | |
316f5878 | 19752 | /* End marker */ |
d16afab6 | 19753 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19754 | }; |
e7af610e | 19755 | |
84ea6cf2 | 19756 | |
316f5878 RS |
19757 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19758 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19759 | |
316f5878 | 19760 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19761 | |
b34976b6 | 19762 | static bfd_boolean |
17a2f251 | 19763 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19764 | { |
19765 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19766 | given++, canonical++; | |
19767 | ||
19768 | return ((*given == 0 && *canonical == 0) | |
19769 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19770 | } | |
19771 | ||
19772 | ||
19773 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19774 | CPU name. We've traditionally allowed a lot of variation here. | |
19775 | ||
19776 | Note: this function is shared between GCC and GAS. */ | |
19777 | ||
b34976b6 | 19778 | static bfd_boolean |
17a2f251 | 19779 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19780 | { |
19781 | /* First see if the name matches exactly, or with a final "000" | |
19782 | turned into "k". */ | |
19783 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19784 | return TRUE; |
316f5878 RS |
19785 | |
19786 | /* If not, try comparing based on numerical designation alone. | |
19787 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19788 | if (TOLOWER (*given) == 'r') | |
19789 | given++; | |
19790 | if (!ISDIGIT (*given)) | |
b34976b6 | 19791 | return FALSE; |
316f5878 RS |
19792 | |
19793 | /* Skip over some well-known prefixes in the canonical name, | |
19794 | hoping to find a number there too. */ | |
19795 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19796 | canonical += 2; | |
19797 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19798 | canonical += 2; | |
19799 | else if (TOLOWER (canonical[0]) == 'r') | |
19800 | canonical += 1; | |
19801 | ||
19802 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19803 | } | |
19804 | ||
19805 | ||
19806 | /* Parse an option that takes the name of a processor as its argument. | |
19807 | OPTION is the name of the option and CPU_STRING is the argument. | |
19808 | Return the corresponding processor enumeration if the CPU_STRING is | |
19809 | recognized, otherwise report an error and return null. | |
19810 | ||
19811 | A similar function exists in GCC. */ | |
e7af610e NC |
19812 | |
19813 | static const struct mips_cpu_info * | |
17a2f251 | 19814 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19815 | { |
316f5878 | 19816 | const struct mips_cpu_info *p; |
e7af610e | 19817 | |
316f5878 RS |
19818 | /* 'from-abi' selects the most compatible architecture for the given |
19819 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19820 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19821 | version. Look first at the -mgp options, if given, otherwise base | |
19822 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19823 | |
316f5878 RS |
19824 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19825 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19826 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19827 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19828 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19829 | { | |
19830 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19831 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19832 | ||
19833 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19834 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19835 | ||
bad1aba3 | 19836 | if (file_mips_opts.gp >= 0) |
19837 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19838 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19839 | |
19840 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19841 | ? ISA_MIPS3 | |
19842 | : ISA_MIPS1); | |
19843 | } | |
19844 | ||
19845 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19846 | if (strcasecmp (cpu_string, "default") == 0) | |
19847 | return 0; | |
19848 | ||
19849 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19850 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19851 | return p; | |
19852 | ||
1661c76c | 19853 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19854 | return 0; |
e7af610e NC |
19855 | } |
19856 | ||
316f5878 RS |
19857 | /* Return the canonical processor information for ISA (a member of the |
19858 | ISA_MIPS* enumeration). */ | |
19859 | ||
e7af610e | 19860 | static const struct mips_cpu_info * |
17a2f251 | 19861 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19862 | { |
19863 | int i; | |
19864 | ||
19865 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19866 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19867 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19868 | return (&mips_cpu_info_table[i]); |
19869 | ||
e972090a | 19870 | return NULL; |
e7af610e | 19871 | } |
fef14a42 TS |
19872 | |
19873 | static const struct mips_cpu_info * | |
17a2f251 | 19874 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19875 | { |
19876 | int i; | |
19877 | ||
19878 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19879 | if (arch == mips_cpu_info_table[i].cpu) | |
19880 | return (&mips_cpu_info_table[i]); | |
19881 | ||
19882 | return NULL; | |
19883 | } | |
316f5878 RS |
19884 | \f |
19885 | static void | |
17a2f251 | 19886 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19887 | { |
19888 | if (*first_p) | |
19889 | { | |
19890 | fprintf (stream, "%24s", ""); | |
19891 | *col_p = 24; | |
19892 | } | |
19893 | else | |
19894 | { | |
19895 | fprintf (stream, ", "); | |
19896 | *col_p += 2; | |
19897 | } | |
e7af610e | 19898 | |
316f5878 RS |
19899 | if (*col_p + strlen (string) > 72) |
19900 | { | |
19901 | fprintf (stream, "\n%24s", ""); | |
19902 | *col_p = 24; | |
19903 | } | |
19904 | ||
19905 | fprintf (stream, "%s", string); | |
19906 | *col_p += strlen (string); | |
19907 | ||
19908 | *first_p = 0; | |
19909 | } | |
19910 | ||
19911 | void | |
17a2f251 | 19912 | md_show_usage (FILE *stream) |
e7af610e | 19913 | { |
316f5878 RS |
19914 | int column, first; |
19915 | size_t i; | |
19916 | ||
19917 | fprintf (stream, _("\ | |
19918 | MIPS options:\n\ | |
316f5878 RS |
19919 | -EB generate big endian output\n\ |
19920 | -EL generate little endian output\n\ | |
19921 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19922 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19923 | implicitly with the gp register [default 8]\n")); | |
19924 | fprintf (stream, _("\ | |
19925 | -mips1 generate MIPS ISA I instructions\n\ | |
19926 | -mips2 generate MIPS ISA II instructions\n\ | |
19927 | -mips3 generate MIPS ISA III instructions\n\ | |
19928 | -mips4 generate MIPS ISA IV instructions\n\ | |
19929 | -mips5 generate MIPS ISA V instructions\n\ | |
19930 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19931 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
19932 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
19933 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 19934 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 19935 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19936 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
19937 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
19938 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 19939 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
19940 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19941 | ||
19942 | first = 1; | |
e7af610e NC |
19943 | |
19944 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19945 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19946 | show (stream, "from-abi", &column, &first); | |
19947 | fputc ('\n', stream); | |
e7af610e | 19948 | |
316f5878 RS |
19949 | fprintf (stream, _("\ |
19950 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19951 | -no-mCPU don't generate code specific to CPU.\n\ | |
19952 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19953 | ||
19954 | first = 1; | |
19955 | ||
19956 | show (stream, "3900", &column, &first); | |
19957 | show (stream, "4010", &column, &first); | |
19958 | show (stream, "4100", &column, &first); | |
19959 | show (stream, "4650", &column, &first); | |
19960 | fputc ('\n', stream); | |
19961 | ||
19962 | fprintf (stream, _("\ | |
19963 | -mips16 generate mips16 instructions\n\ | |
19964 | -no-mips16 do not generate mips16 instructions\n")); | |
19965 | fprintf (stream, _("\ | |
df58fc94 RS |
19966 | -mmicromips generate microMIPS instructions\n\ |
19967 | -mno-micromips do not generate microMIPS instructions\n")); | |
19968 | fprintf (stream, _("\ | |
e16bfa71 | 19969 | -msmartmips generate smartmips instructions\n\ |
3739860c | 19970 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 19971 | fprintf (stream, _("\ |
74cd071d CF |
19972 | -mdsp generate DSP instructions\n\ |
19973 | -mno-dsp do not generate DSP instructions\n")); | |
19974 | fprintf (stream, _("\ | |
8b082fb1 TS |
19975 | -mdspr2 generate DSP R2 instructions\n\ |
19976 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19977 | fprintf (stream, _("\ | |
8f4f9071 MF |
19978 | -mdspr3 generate DSP R3 instructions\n\ |
19979 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
19980 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19981 | -mmt generate MT instructions\n\ |
19982 | -mno-mt do not generate MT instructions\n")); | |
19983 | fprintf (stream, _("\ | |
dec0624d MR |
19984 | -mmcu generate MCU instructions\n\ |
19985 | -mno-mcu do not generate MCU instructions\n")); | |
19986 | fprintf (stream, _("\ | |
56d438b1 CF |
19987 | -mmsa generate MSA instructions\n\ |
19988 | -mno-msa do not generate MSA instructions\n")); | |
19989 | fprintf (stream, _("\ | |
7d64c587 AB |
19990 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
19991 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
19992 | fprintf (stream, _("\ | |
b015e599 AP |
19993 | -mvirt generate Virtualization instructions\n\ |
19994 | -mno-virt do not generate Virtualization instructions\n")); | |
19995 | fprintf (stream, _("\ | |
833794fc MR |
19996 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
19997 | -mno-insn32 generate all microMIPS instructions\n")); | |
19998 | fprintf (stream, _("\ | |
c67a084a NC |
19999 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20000 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 20001 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20002 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20003 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20004 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
20005 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20006 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20007 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
20008 | -O0 remove unneeded NOPs, do not swap branches\n\ |
20009 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20010 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20011 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20012 | fprintf (stream, _("\ |
20013 | -mhard-float allow floating-point instructions\n\ | |
20014 | -msoft-float do not allow floating-point instructions\n\ | |
20015 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20016 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20017 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20018 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20019 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20020 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20021 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20022 | ||
20023 | first = 1; | |
20024 | ||
20025 | show (stream, "legacy", &column, &first); | |
20026 | show (stream, "2008", &column, &first); | |
20027 | ||
20028 | fputc ('\n', stream); | |
20029 | ||
316f5878 RS |
20030 | fprintf (stream, _("\ |
20031 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20032 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20033 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20034 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20035 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20036 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20037 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20038 | position dependent (non shared) code\n\ |
316f5878 RS |
20039 | -mabi=ABI create ABI conformant object file for:\n")); |
20040 | ||
20041 | first = 1; | |
20042 | ||
20043 | show (stream, "32", &column, &first); | |
20044 | show (stream, "o64", &column, &first); | |
20045 | show (stream, "n32", &column, &first); | |
20046 | show (stream, "64", &column, &first); | |
20047 | show (stream, "eabi", &column, &first); | |
20048 | ||
20049 | fputc ('\n', stream); | |
20050 | ||
20051 | fprintf (stream, _("\ | |
20052 | -32 create o32 ABI object file (default)\n\ | |
20053 | -n32 create n32 ABI object file\n\ | |
20054 | -64 create 64 ABI object file\n")); | |
e7af610e | 20055 | } |
14e777e0 | 20056 | |
1575952e | 20057 | #ifdef TE_IRIX |
14e777e0 | 20058 | enum dwarf2_format |
413a266c | 20059 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20060 | { |
369943fe | 20061 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20062 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20063 | else |
20064 | return dwarf2_format_32bit; | |
20065 | } | |
1575952e | 20066 | #endif |
73369e65 EC |
20067 | |
20068 | int | |
20069 | mips_dwarf2_addr_size (void) | |
20070 | { | |
6b6b3450 | 20071 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20072 | return 8; |
73369e65 EC |
20073 | else |
20074 | return 4; | |
20075 | } | |
5862107c EC |
20076 | |
20077 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20078 | void | |
20079 | mips_cfi_frame_initial_instructions (void) | |
20080 | { | |
20081 | cfi_add_CFA_def_cfa_register (SP); | |
20082 | } | |
20083 | ||
707bfff6 TS |
20084 | int |
20085 | tc_mips_regname_to_dw2regnum (char *regname) | |
20086 | { | |
20087 | unsigned int regnum = -1; | |
20088 | unsigned int reg; | |
20089 | ||
20090 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20091 | regnum = reg; | |
20092 | ||
20093 | return regnum; | |
20094 | } | |
263b2574 | 20095 | |
20096 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20097 | Given a symbolic attribute NAME, return the proper integer value. | |
20098 | Returns -1 if the attribute is not known. */ | |
20099 | ||
20100 | int | |
20101 | mips_convert_symbolic_attribute (const char *name) | |
20102 | { | |
20103 | static const struct | |
20104 | { | |
20105 | const char * name; | |
20106 | const int tag; | |
20107 | } | |
20108 | attribute_table[] = | |
20109 | { | |
20110 | #define T(tag) {#tag, tag} | |
20111 | T (Tag_GNU_MIPS_ABI_FP), | |
20112 | T (Tag_GNU_MIPS_ABI_MSA), | |
20113 | #undef T | |
20114 | }; | |
20115 | unsigned int i; | |
20116 | ||
20117 | if (name == NULL) | |
20118 | return -1; | |
20119 | ||
20120 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20121 | if (streq (name, attribute_table[i].name)) | |
20122 | return attribute_table[i].tag; | |
20123 | ||
20124 | return -1; | |
20125 | } | |
fd5c94ab RS |
20126 | |
20127 | void | |
20128 | md_mips_end (void) | |
20129 | { | |
351cdf24 MF |
20130 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20131 | ||
fd5c94ab RS |
20132 | mips_emit_delays (); |
20133 | if (cur_proc_ptr) | |
20134 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20135 | |
20136 | /* Just in case no code was emitted, do the consistency check. */ | |
20137 | file_mips_check_options (); | |
351cdf24 MF |
20138 | |
20139 | /* Set a floating-point ABI if the user did not. */ | |
20140 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20141 | { | |
20142 | /* Perform consistency checks on the floating-point ABI. */ | |
20143 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20144 | Tag_GNU_MIPS_ABI_FP); | |
20145 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20146 | check_fpabi (fpabi); | |
20147 | } | |
20148 | else | |
20149 | { | |
20150 | /* Soft-float gets precedence over single-float, the two options should | |
20151 | not be used together so this should not matter. */ | |
20152 | if (file_mips_opts.soft_float == 1) | |
20153 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20154 | /* Single-float gets precedence over all double_float cases. */ | |
20155 | else if (file_mips_opts.single_float == 1) | |
20156 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20157 | else | |
20158 | { | |
20159 | switch (file_mips_opts.fp) | |
20160 | { | |
20161 | case 32: | |
20162 | if (file_mips_opts.gp == 32) | |
20163 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20164 | break; | |
20165 | case 0: | |
20166 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20167 | break; | |
20168 | case 64: | |
20169 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20170 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20171 | else if (file_mips_opts.gp == 32) | |
20172 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20173 | else | |
20174 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20175 | break; | |
20176 | } | |
20177 | } | |
20178 | ||
20179 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20180 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20181 | } | |
fd5c94ab | 20182 | } |
2f0c68f2 CM |
20183 | |
20184 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20185 | ||
20186 | bfd_reloc_code_real_type | |
20187 | mips_cfi_reloc_for_encoding (int encoding) | |
20188 | { | |
20189 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20190 | return BFD_RELOC_32_PCREL; | |
20191 | else return BFD_RELOC_NONE; | |
20192 | } |