Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
23fce1e3 | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
741fe287 | 92 | #define ATREG 1 |
252b5132 RH |
93 | #define TREG 24 |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
741fe287 MR |
104 | #define AT mips_opts.at |
105 | ||
252b5132 RH |
106 | /* Allow override of standard little-endian ECOFF format. */ |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
8b082fb1 | 198 | int ase_dspr2; |
ef2e4d86 | 199 | int ase_mt; |
252b5132 RH |
200 | /* Whether we are assembling for the mips16 processor. 0 if we are |
201 | not, 1 if we are, and -1 if the value has not been initialized. | |
202 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
203 | -nomips16 command line options, and the default CPU. */ | |
204 | int mips16; | |
205 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
206 | reorder' and `.set noreorder'. */ | |
207 | int noreorder; | |
741fe287 MR |
208 | /* Non-zero if we should not permit the register designated "assembler |
209 | temporary" to be used in instructions. The value is the register | |
210 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
211 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
212 | unsigned int at; | |
252b5132 RH |
213 | /* Non-zero if we should warn when a macro instruction expands into |
214 | more than one machine instruction. Changed by `.set nomacro' and | |
215 | `.set macro'. */ | |
216 | int warn_about_macros; | |
217 | /* Non-zero if we should not move instructions. Changed by `.set | |
218 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
219 | int nomove; | |
220 | /* Non-zero if we should not optimize branches by moving the target | |
221 | of the branch into the delay slot. Actually, we don't perform | |
222 | this optimization anyhow. Changed by `.set bopt' and `.set | |
223 | nobopt'. */ | |
224 | int nobopt; | |
225 | /* Non-zero if we should not autoextend mips16 instructions. | |
226 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
227 | int noautoextend; | |
a325df1d TS |
228 | /* Restrict general purpose registers and floating point registers |
229 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
230 | is passed but can changed if the assembler code uses .set mipsN. */ | |
231 | int gp32; | |
232 | int fp32; | |
fef14a42 TS |
233 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
234 | command line option, and the default CPU. */ | |
235 | int arch; | |
aed1a261 RS |
236 | /* True if ".set sym32" is in effect. */ |
237 | bfd_boolean sym32; | |
037b32b9 AN |
238 | /* True if floating-point operations are not allowed. Changed by .set |
239 | softfloat or .set hardfloat, by command line options -msoft-float or | |
240 | -mhard-float. The default is false. */ | |
241 | bfd_boolean soft_float; | |
242 | ||
243 | /* True if only single-precision floating-point operations are allowed. | |
244 | Changed by .set singlefloat or .set doublefloat, command-line options | |
245 | -msingle-float or -mdouble-float. The default is false. */ | |
246 | bfd_boolean single_float; | |
252b5132 RH |
247 | }; |
248 | ||
037b32b9 AN |
249 | /* This is the struct we use to hold the current set of options. Note |
250 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
251 | -1 to indicate that they have not been initialized. */ | |
252 | ||
a325df1d | 253 | /* True if -mgp32 was passed. */ |
a8e8e863 | 254 | static int file_mips_gp32 = -1; |
a325df1d TS |
255 | |
256 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 257 | static int file_mips_fp32 = -1; |
a325df1d | 258 | |
037b32b9 AN |
259 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
260 | static int file_mips_soft_float = 0; | |
261 | ||
262 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
263 | static int file_mips_single_float = 0; | |
252b5132 | 264 | |
e972090a NC |
265 | static struct mips_set_options mips_opts = |
266 | { | |
037b32b9 AN |
267 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
268 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
269 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
270 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
271 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
272 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 273 | }; |
252b5132 RH |
274 | |
275 | /* These variables are filled in with the masks of registers used. | |
276 | The object format code reads them and puts them in the appropriate | |
277 | place. */ | |
278 | unsigned long mips_gprmask; | |
279 | unsigned long mips_cprmask[4]; | |
280 | ||
281 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 282 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 283 | |
a4672219 TS |
284 | /* True if -mips16 was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_mips16; | |
287 | ||
3994f87e TS |
288 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
289 | || mips_opts.isa == ISA_MIPS32R2 \ | |
290 | || mips_opts.isa == ISA_MIPS64 \ | |
291 | || mips_opts.isa == ISA_MIPS64R2) | |
292 | ||
b12dd2e4 CF |
293 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
294 | #ifdef TE_IRIX | |
295 | #define MIPS_JALR_HINT_P HAVE_NEWABI | |
296 | #else | |
297 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. */ | |
298 | #define MIPS_JALR_HINT_P 1 | |
299 | #endif | |
300 | ||
1f25f5d3 CD |
301 | /* True if -mips3d was passed or implied by arguments passed on the |
302 | command line (e.g., by -march). */ | |
303 | static int file_ase_mips3d; | |
304 | ||
deec1734 CD |
305 | /* True if -mdmx was passed or implied by arguments passed on the |
306 | command line (e.g., by -march). */ | |
307 | static int file_ase_mdmx; | |
308 | ||
e16bfa71 TS |
309 | /* True if -msmartmips was passed or implied by arguments passed on the |
310 | command line (e.g., by -march). */ | |
311 | static int file_ase_smartmips; | |
312 | ||
ad3fea08 TS |
313 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 315 | |
74cd071d CF |
316 | /* True if -mdsp was passed or implied by arguments passed on the |
317 | command line (e.g., by -march). */ | |
318 | static int file_ase_dsp; | |
319 | ||
ad3fea08 TS |
320 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
321 | || mips_opts.isa == ISA_MIPS64R2) | |
322 | ||
65263ce3 TS |
323 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
324 | ||
8b082fb1 TS |
325 | /* True if -mdspr2 was passed or implied by arguments passed on the |
326 | command line (e.g., by -march). */ | |
327 | static int file_ase_dspr2; | |
328 | ||
329 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
330 | || mips_opts.isa == ISA_MIPS64R2) | |
331 | ||
ef2e4d86 CF |
332 | /* True if -mmt was passed or implied by arguments passed on the |
333 | command line (e.g., by -march). */ | |
334 | static int file_ase_mt; | |
335 | ||
ad3fea08 TS |
336 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
337 | || mips_opts.isa == ISA_MIPS64R2) | |
338 | ||
ec68c924 | 339 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 340 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 341 | static const char *mips_arch_string; |
ec68c924 EC |
342 | |
343 | /* The argument of the -mtune= flag. The architecture for which we | |
344 | are optimizing. */ | |
345 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 346 | static const char *mips_tune_string; |
ec68c924 | 347 | |
316f5878 | 348 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
349 | static int mips_32bitmode = 0; |
350 | ||
316f5878 RS |
351 | /* True if the given ABI requires 32-bit registers. */ |
352 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
353 | ||
354 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
355 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
356 | ((ABI) == N32_ABI \ | |
357 | || (ABI) == N64_ABI \ | |
316f5878 RS |
358 | || (ABI) == O64_ABI) |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
366 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 367 | |
ad3fea08 TS |
368 | /* Return true if ISA supports 64 bit wide float registers. */ |
369 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
370 | ((ISA) == ISA_MIPS3 \ | |
371 | || (ISA) == ISA_MIPS4 \ | |
372 | || (ISA) == ISA_MIPS5 \ | |
373 | || (ISA) == ISA_MIPS32R2 \ | |
374 | || (ISA) == ISA_MIPS64 \ | |
375 | || (ISA) == ISA_MIPS64R2) | |
376 | ||
af7ee8bf CD |
377 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
378 | instructions. */ | |
707bfff6 TS |
379 | #define ISA_HAS_DROR(ISA) \ |
380 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
381 | |
382 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
383 | instructions. */ | |
707bfff6 TS |
384 | #define ISA_HAS_ROR(ISA) \ |
385 | ((ISA) == ISA_MIPS32R2 \ | |
386 | || (ISA) == ISA_MIPS64R2 \ | |
387 | || mips_opts.ase_smartmips) | |
388 | ||
7455baf8 TS |
389 | /* Return true if ISA supports single-precision floats in odd registers. */ |
390 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
391 | ((ISA) == ISA_MIPS32 \ | |
392 | || (ISA) == ISA_MIPS32R2 \ | |
393 | || (ISA) == ISA_MIPS64 \ | |
394 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 395 | |
ad3fea08 TS |
396 | /* Return true if ISA supports move to/from high part of a 64-bit |
397 | floating-point register. */ | |
398 | #define ISA_HAS_MXHC1(ISA) \ | |
399 | ((ISA) == ISA_MIPS32R2 \ | |
400 | || (ISA) == ISA_MIPS64R2) | |
401 | ||
e013f690 | 402 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 403 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 404 | |
e013f690 | 405 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 406 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 407 | |
ad3fea08 TS |
408 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
409 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 410 | |
316f5878 | 411 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 412 | |
316f5878 | 413 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 414 | |
3b91255e RS |
415 | /* True if relocations are stored in-place. */ |
416 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
417 | ||
aed1a261 RS |
418 | /* The ABI-derived address size. */ |
419 | #define HAVE_64BIT_ADDRESSES \ | |
420 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
421 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 422 | |
aed1a261 RS |
423 | /* The size of symbolic constants (i.e., expressions of the form |
424 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
425 | #define HAVE_32BIT_SYMBOLS \ | |
426 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
427 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 428 | |
b7c7d6c1 TS |
429 | /* Addresses are loaded in different ways, depending on the address size |
430 | in use. The n32 ABI Documentation also mandates the use of additions | |
431 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 432 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 433 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
434 | |
435 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 436 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
437 | |
438 | #define ADDRESS_LOAD_INSN \ | |
439 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
440 | ||
441 | #define ADDRESS_STORE_INSN \ | |
442 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
443 | ||
a4672219 | 444 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
445 | #define CPU_HAS_MIPS16(cpu) \ |
446 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
447 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 448 | |
60b63b72 RS |
449 | /* True if CPU has a dror instruction. */ |
450 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
451 | ||
452 | /* True if CPU has a ror instruction. */ | |
453 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
454 | ||
dd3cbb7e NC |
455 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
456 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
457 | ||
b19e8a9b AN |
458 | /* True if CPU does not implement the all the coprocessor insns. For these |
459 | CPUs only those COP insns are accepted that are explicitly marked to be | |
460 | available on the CPU. ISA membership for COP insns is ignored. */ | |
461 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
462 | ||
c8978940 CD |
463 | /* True if mflo and mfhi can be immediately followed by instructions |
464 | which write to the HI and LO registers. | |
465 | ||
466 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
467 | (at least) two instructions between the reads of HI/LO and | |
468 | instructions which write them, and later ISAs do not. Contradicting | |
469 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
470 | the UM for the NEC Vr5000) document needing the instructions between | |
471 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
472 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
473 | earlier-ISA CPUs for which CPU documentation declares that the | |
474 | instructions are really interlocked. */ | |
475 | #define hilo_interlocks \ | |
476 | (mips_opts.isa == ISA_MIPS32 \ | |
477 | || mips_opts.isa == ISA_MIPS32R2 \ | |
478 | || mips_opts.isa == ISA_MIPS64 \ | |
479 | || mips_opts.isa == ISA_MIPS64R2 \ | |
480 | || mips_opts.arch == CPU_R4010 \ | |
481 | || mips_opts.arch == CPU_R10000 \ | |
482 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
483 | || mips_opts.arch == CPU_R14000 \ |
484 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 485 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
486 | || mips_opts.arch == CPU_VR5500 \ |
487 | ) | |
252b5132 RH |
488 | |
489 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
490 | from the GPRs after they are loaded from memory, and thus does not |
491 | require nops to be inserted. This applies to instructions marked | |
492 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
493 | level I. */ | |
252b5132 | 494 | #define gpr_interlocks \ |
e7af610e | 495 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 496 | || mips_opts.arch == CPU_R3900) |
252b5132 | 497 | |
81912461 ILT |
498 | /* Whether the processor uses hardware interlocks to avoid delays |
499 | required by coprocessor instructions, and thus does not require | |
500 | nops to be inserted. This applies to instructions marked | |
501 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
502 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
503 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
504 | levels I, II, and III. */ | |
bdaaa2e1 | 505 | /* Itbl support may require additional care here. */ |
81912461 ILT |
506 | #define cop_interlocks \ |
507 | ((mips_opts.isa != ISA_MIPS1 \ | |
508 | && mips_opts.isa != ISA_MIPS2 \ | |
509 | && mips_opts.isa != ISA_MIPS3) \ | |
510 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
511 | ) |
512 | ||
513 | /* Whether the processor uses hardware interlocks to protect reads | |
514 | from coprocessor registers after they are loaded from memory, and | |
515 | thus does not require nops to be inserted. This applies to | |
516 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
517 | requires at MIPS ISA level I. */ | |
518 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 519 | |
6b76fefe CM |
520 | /* Is this a mfhi or mflo instruction? */ |
521 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
522 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
523 | ||
524 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
525 | or writing the condition code is only possible on the coprocessors and | |
526 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 527 | condition-code flags. */ |
b19e8a9b AN |
528 | #define COP_INSN(PINFO) \ |
529 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
530 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
531 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 532 | |
252b5132 RH |
533 | /* MIPS PIC level. */ |
534 | ||
a161fe53 | 535 | enum mips_pic_level mips_pic; |
252b5132 | 536 | |
c9914766 | 537 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 538 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 539 | static int mips_big_got = 0; |
252b5132 RH |
540 | |
541 | /* 1 if trap instructions should used for overflow rather than break | |
542 | instructions. */ | |
c9914766 | 543 | static int mips_trap = 0; |
252b5132 | 544 | |
119d663a | 545 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 546 | by assembling two single width halves into two single width floating |
119d663a NC |
547 | point registers which just happen to alias the double width destination |
548 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 549 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
550 | automatically at assemble time. */ |
551 | static int mips_disable_float_construction; | |
552 | ||
252b5132 RH |
553 | /* Non-zero if any .set noreorder directives were used. */ |
554 | ||
555 | static int mips_any_noreorder; | |
556 | ||
6b76fefe CM |
557 | /* Non-zero if nops should be inserted when the register referenced in |
558 | an mfhi/mflo instruction is read in the next two instructions. */ | |
559 | static int mips_7000_hilo_fix; | |
560 | ||
02ffd3e4 | 561 | /* The size of objects in the small data section. */ |
156c2f8b | 562 | static unsigned int g_switch_value = 8; |
252b5132 RH |
563 | /* Whether the -G option was used. */ |
564 | static int g_switch_seen = 0; | |
565 | ||
566 | #define N_RMASK 0xc4 | |
567 | #define N_VFP 0xd4 | |
568 | ||
569 | /* If we can determine in advance that GP optimization won't be | |
570 | possible, we can skip the relaxation stuff that tries to produce | |
571 | GP-relative references. This makes delay slot optimization work | |
572 | better. | |
573 | ||
574 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
575 | gcc output. It needs to guess right for gcc, otherwise gcc |
576 | will put what it thinks is a GP-relative instruction in a branch | |
577 | delay slot. | |
252b5132 RH |
578 | |
579 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
580 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 581 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
582 | |
583 | /* handle of the OPCODE hash table */ | |
584 | static struct hash_control *op_hash = NULL; | |
585 | ||
586 | /* The opcode hash table we use for the mips16. */ | |
587 | static struct hash_control *mips16_op_hash = NULL; | |
588 | ||
589 | /* This array holds the chars that always start a comment. If the | |
590 | pre-processor is disabled, these aren't very useful */ | |
591 | const char comment_chars[] = "#"; | |
592 | ||
593 | /* This array holds the chars that only start a comment at the beginning of | |
594 | a line. If the line seems to have the form '# 123 filename' | |
595 | .line and .file directives will appear in the pre-processed output */ | |
596 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
597 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 598 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
599 | /* Also note that C style comments are always supported. */ |
600 | const char line_comment_chars[] = "#"; | |
601 | ||
bdaaa2e1 | 602 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 603 | const char line_separator_chars[] = ";"; |
252b5132 RH |
604 | |
605 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
606 | const char EXP_CHARS[] = "eE"; | |
607 | ||
608 | /* Chars that mean this number is a floating point constant */ | |
609 | /* As in 0f12.456 */ | |
610 | /* or 0d1.2345e12 */ | |
611 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
612 | ||
613 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
614 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
615 | but nothing is ideal around here. | |
616 | */ | |
617 | ||
618 | static char *insn_error; | |
619 | ||
620 | static int auto_align = 1; | |
621 | ||
622 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
623 | offset in the stack frame from which to restore the $gp register. | |
624 | This is set by the .cprestore pseudo-op, and saved in this | |
625 | variable. */ | |
626 | static offsetT mips_cprestore_offset = -1; | |
627 | ||
67c1ffbe | 628 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 629 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 630 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
631 | static offsetT mips_cpreturn_offset = -1; |
632 | static int mips_cpreturn_register = -1; | |
633 | static int mips_gp_register = GP; | |
def2e0dd | 634 | static int mips_gprel_offset = 0; |
6478892d | 635 | |
7a621144 DJ |
636 | /* Whether mips_cprestore_offset has been set in the current function |
637 | (or whether it has already been warned about, if not). */ | |
638 | static int mips_cprestore_valid = 0; | |
639 | ||
252b5132 RH |
640 | /* This is the register which holds the stack frame, as set by the |
641 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
642 | static int mips_frame_reg = SP; | |
643 | ||
7a621144 DJ |
644 | /* Whether mips_frame_reg has been set in the current function |
645 | (or whether it has already been warned about, if not). */ | |
646 | static int mips_frame_reg_valid = 0; | |
647 | ||
252b5132 RH |
648 | /* To output NOP instructions correctly, we need to keep information |
649 | about the previous two instructions. */ | |
650 | ||
651 | /* Whether we are optimizing. The default value of 2 means to remove | |
652 | unneeded NOPs and swap branch instructions when possible. A value | |
653 | of 1 means to not swap branches. A value of 0 means to always | |
654 | insert NOPs. */ | |
655 | static int mips_optimize = 2; | |
656 | ||
657 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
658 | equivalent to seeing no -g option at all. */ | |
659 | static int mips_debug = 0; | |
660 | ||
7d8e00cf RS |
661 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
662 | #define MAX_VR4130_NOPS 4 | |
663 | ||
664 | /* The maximum number of NOPs needed to fill delay slots. */ | |
665 | #define MAX_DELAY_NOPS 2 | |
666 | ||
667 | /* The maximum number of NOPs needed for any purpose. */ | |
668 | #define MAX_NOPS 4 | |
71400594 RS |
669 | |
670 | /* A list of previous instructions, with index 0 being the most recent. | |
671 | We need to look back MAX_NOPS instructions when filling delay slots | |
672 | or working around processor errata. We need to look back one | |
673 | instruction further if we're thinking about using history[0] to | |
674 | fill a branch delay slot. */ | |
675 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 676 | |
1e915849 RS |
677 | /* Nop instructions used by emit_nop. */ |
678 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
679 | ||
680 | /* The appropriate nop for the current mode. */ | |
681 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 682 | |
252b5132 RH |
683 | /* If this is set, it points to a frag holding nop instructions which |
684 | were inserted before the start of a noreorder section. If those | |
685 | nops turn out to be unnecessary, the size of the frag can be | |
686 | decreased. */ | |
687 | static fragS *prev_nop_frag; | |
688 | ||
689 | /* The number of nop instructions we created in prev_nop_frag. */ | |
690 | static int prev_nop_frag_holds; | |
691 | ||
692 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 693 | prev_nop_frag. */ |
252b5132 RH |
694 | static int prev_nop_frag_required; |
695 | ||
696 | /* The number of instructions we've seen since prev_nop_frag. */ | |
697 | static int prev_nop_frag_since; | |
698 | ||
699 | /* For ECOFF and ELF, relocations against symbols are done in two | |
700 | parts, with a HI relocation and a LO relocation. Each relocation | |
701 | has only 16 bits of space to store an addend. This means that in | |
702 | order for the linker to handle carries correctly, it must be able | |
703 | to locate both the HI and the LO relocation. This means that the | |
704 | relocations must appear in order in the relocation table. | |
705 | ||
706 | In order to implement this, we keep track of each unmatched HI | |
707 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 708 | corresponding LO relocation. */ |
252b5132 | 709 | |
e972090a NC |
710 | struct mips_hi_fixup |
711 | { | |
252b5132 RH |
712 | /* Next HI fixup. */ |
713 | struct mips_hi_fixup *next; | |
714 | /* This fixup. */ | |
715 | fixS *fixp; | |
716 | /* The section this fixup is in. */ | |
717 | segT seg; | |
718 | }; | |
719 | ||
720 | /* The list of unmatched HI relocs. */ | |
721 | ||
722 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
723 | ||
64bdfcaf RS |
724 | /* The frag containing the last explicit relocation operator. |
725 | Null if explicit relocations have not been used. */ | |
726 | ||
727 | static fragS *prev_reloc_op_frag; | |
728 | ||
252b5132 RH |
729 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
730 | ||
731 | #define X ILLEGAL_REG | |
e972090a NC |
732 | static const int mips32_to_16_reg_map[] = |
733 | { | |
252b5132 RH |
734 | X, X, 2, 3, 4, 5, 6, 7, |
735 | X, X, X, X, X, X, X, X, | |
736 | 0, 1, X, X, X, X, X, X, | |
737 | X, X, X, X, X, X, X, X | |
738 | }; | |
739 | #undef X | |
740 | ||
741 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
742 | ||
e972090a NC |
743 | static const unsigned int mips16_to_32_reg_map[] = |
744 | { | |
252b5132 RH |
745 | 16, 17, 2, 3, 4, 5, 6, 7 |
746 | }; | |
60b63b72 | 747 | |
71400594 RS |
748 | /* Classifies the kind of instructions we're interested in when |
749 | implementing -mfix-vr4120. */ | |
750 | enum fix_vr4120_class { | |
751 | FIX_VR4120_MACC, | |
752 | FIX_VR4120_DMACC, | |
753 | FIX_VR4120_MULT, | |
754 | FIX_VR4120_DMULT, | |
755 | FIX_VR4120_DIV, | |
756 | FIX_VR4120_MTHILO, | |
757 | NUM_FIX_VR4120_CLASSES | |
758 | }; | |
759 | ||
760 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
761 | there must be at least one other instruction between an instruction | |
762 | of type X and an instruction of type Y. */ | |
763 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
764 | ||
765 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 766 | static int mips_fix_vr4120; |
4a6a3df4 | 767 | |
7d8e00cf RS |
768 | /* ...likewise -mfix-vr4130. */ |
769 | static int mips_fix_vr4130; | |
770 | ||
6a32d874 CM |
771 | /* ...likewise -mfix-24k. */ |
772 | static int mips_fix_24k; | |
773 | ||
4a6a3df4 AO |
774 | /* We don't relax branches by default, since this causes us to expand |
775 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
776 | fail to compute the offset before expanding the macro to the most | |
777 | efficient expansion. */ | |
778 | ||
779 | static int mips_relax_branch; | |
252b5132 | 780 | \f |
4d7206a2 RS |
781 | /* The expansion of many macros depends on the type of symbol that |
782 | they refer to. For example, when generating position-dependent code, | |
783 | a macro that refers to a symbol may have two different expansions, | |
784 | one which uses GP-relative addresses and one which uses absolute | |
785 | addresses. When generating SVR4-style PIC, a macro may have | |
786 | different expansions for local and global symbols. | |
787 | ||
788 | We handle these situations by generating both sequences and putting | |
789 | them in variant frags. In position-dependent code, the first sequence | |
790 | will be the GP-relative one and the second sequence will be the | |
791 | absolute one. In SVR4 PIC, the first sequence will be for global | |
792 | symbols and the second will be for local symbols. | |
793 | ||
584892a6 RS |
794 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
795 | SECOND are the lengths of the two sequences in bytes. These fields | |
796 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
797 | the subtype has the following flags: | |
4d7206a2 | 798 | |
584892a6 RS |
799 | RELAX_USE_SECOND |
800 | Set if it has been decided that we should use the second | |
801 | sequence instead of the first. | |
802 | ||
803 | RELAX_SECOND_LONGER | |
804 | Set in the first variant frag if the macro's second implementation | |
805 | is longer than its first. This refers to the macro as a whole, | |
806 | not an individual relaxation. | |
807 | ||
808 | RELAX_NOMACRO | |
809 | Set in the first variant frag if the macro appeared in a .set nomacro | |
810 | block and if one alternative requires a warning but the other does not. | |
811 | ||
812 | RELAX_DELAY_SLOT | |
813 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
814 | delay slot. | |
4d7206a2 RS |
815 | |
816 | The frag's "opcode" points to the first fixup for relaxable code. | |
817 | ||
818 | Relaxable macros are generated using a sequence such as: | |
819 | ||
820 | relax_start (SYMBOL); | |
821 | ... generate first expansion ... | |
822 | relax_switch (); | |
823 | ... generate second expansion ... | |
824 | relax_end (); | |
825 | ||
826 | The code and fixups for the unwanted alternative are discarded | |
827 | by md_convert_frag. */ | |
584892a6 | 828 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 829 | |
584892a6 RS |
830 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
831 | #define RELAX_SECOND(X) ((X) & 0xff) | |
832 | #define RELAX_USE_SECOND 0x10000 | |
833 | #define RELAX_SECOND_LONGER 0x20000 | |
834 | #define RELAX_NOMACRO 0x40000 | |
835 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 836 | |
4a6a3df4 AO |
837 | /* Branch without likely bit. If label is out of range, we turn: |
838 | ||
839 | beq reg1, reg2, label | |
840 | delay slot | |
841 | ||
842 | into | |
843 | ||
844 | bne reg1, reg2, 0f | |
845 | nop | |
846 | j label | |
847 | 0: delay slot | |
848 | ||
849 | with the following opcode replacements: | |
850 | ||
851 | beq <-> bne | |
852 | blez <-> bgtz | |
853 | bltz <-> bgez | |
854 | bc1f <-> bc1t | |
855 | ||
856 | bltzal <-> bgezal (with jal label instead of j label) | |
857 | ||
858 | Even though keeping the delay slot instruction in the delay slot of | |
859 | the branch would be more efficient, it would be very tricky to do | |
860 | correctly, because we'd have to introduce a variable frag *after* | |
861 | the delay slot instruction, and expand that instead. Let's do it | |
862 | the easy way for now, even if the branch-not-taken case now costs | |
863 | one additional instruction. Out-of-range branches are not supposed | |
864 | to be common, anyway. | |
865 | ||
866 | Branch likely. If label is out of range, we turn: | |
867 | ||
868 | beql reg1, reg2, label | |
869 | delay slot (annulled if branch not taken) | |
870 | ||
871 | into | |
872 | ||
873 | beql reg1, reg2, 1f | |
874 | nop | |
875 | beql $0, $0, 2f | |
876 | nop | |
877 | 1: j[al] label | |
878 | delay slot (executed only if branch taken) | |
879 | 2: | |
880 | ||
881 | It would be possible to generate a shorter sequence by losing the | |
882 | likely bit, generating something like: | |
b34976b6 | 883 | |
4a6a3df4 AO |
884 | bne reg1, reg2, 0f |
885 | nop | |
886 | j[al] label | |
887 | delay slot (executed only if branch taken) | |
888 | 0: | |
889 | ||
890 | beql -> bne | |
891 | bnel -> beq | |
892 | blezl -> bgtz | |
893 | bgtzl -> blez | |
894 | bltzl -> bgez | |
895 | bgezl -> bltz | |
896 | bc1fl -> bc1t | |
897 | bc1tl -> bc1f | |
898 | ||
899 | bltzall -> bgezal (with jal label instead of j label) | |
900 | bgezall -> bltzal (ditto) | |
901 | ||
902 | ||
903 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 904 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
905 | ((relax_substateT) \ |
906 | (0xc0000000 \ | |
907 | | ((toofar) ? 1 : 0) \ | |
908 | | ((link) ? 2 : 0) \ | |
909 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 910 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 911 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
912 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
913 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
914 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 915 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 916 | |
252b5132 RH |
917 | /* For mips16 code, we use an entirely different form of relaxation. |
918 | mips16 supports two versions of most instructions which take | |
919 | immediate values: a small one which takes some small value, and a | |
920 | larger one which takes a 16 bit value. Since branches also follow | |
921 | this pattern, relaxing these values is required. | |
922 | ||
923 | We can assemble both mips16 and normal MIPS code in a single | |
924 | object. Therefore, we need to support this type of relaxation at | |
925 | the same time that we support the relaxation described above. We | |
926 | use the high bit of the subtype field to distinguish these cases. | |
927 | ||
928 | The information we store for this type of relaxation is the | |
929 | argument code found in the opcode file for this relocation, whether | |
930 | the user explicitly requested a small or extended form, and whether | |
931 | the relocation is in a jump or jal delay slot. That tells us the | |
932 | size of the value, and how it should be stored. We also store | |
933 | whether the fragment is considered to be extended or not. We also | |
934 | store whether this is known to be a branch to a different section, | |
935 | whether we have tried to relax this frag yet, and whether we have | |
936 | ever extended a PC relative fragment because of a shift count. */ | |
937 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
938 | (0x80000000 \ | |
939 | | ((type) & 0xff) \ | |
940 | | ((small) ? 0x100 : 0) \ | |
941 | | ((ext) ? 0x200 : 0) \ | |
942 | | ((dslot) ? 0x400 : 0) \ | |
943 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 944 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
945 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
946 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
947 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
948 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
949 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
950 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
951 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
952 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
953 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
954 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
955 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
956 | |
957 | /* Is the given value a sign-extended 32-bit value? */ | |
958 | #define IS_SEXT_32BIT_NUM(x) \ | |
959 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
960 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
961 | ||
962 | /* Is the given value a sign-extended 16-bit value? */ | |
963 | #define IS_SEXT_16BIT_NUM(x) \ | |
964 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
965 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
966 | ||
2051e8c4 MR |
967 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
968 | #define IS_ZEXT_32BIT_NUM(x) \ | |
969 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
970 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
971 | ||
bf12938e RS |
972 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
973 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
974 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
975 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
976 | | (((VALUE) & (MASK)) << (SHIFT))) | |
977 | ||
978 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
979 | SHIFT places. */ | |
980 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
981 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
982 | ||
983 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
984 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
985 | ||
986 | include/opcode/mips.h specifies operand fields using the macros | |
987 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
988 | with "MIPS16OP" instead of "OP". */ | |
989 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
990 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
991 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
992 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
993 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
994 | ||
995 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
996 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
997 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
998 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
999 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1000 | MIPS16OP_MASK_##FIELD, \ | |
1001 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1002 | \f |
1003 | /* Global variables used when generating relaxable macros. See the | |
1004 | comment above RELAX_ENCODE for more details about how relaxation | |
1005 | is used. */ | |
1006 | static struct { | |
1007 | /* 0 if we're not emitting a relaxable macro. | |
1008 | 1 if we're emitting the first of the two relaxation alternatives. | |
1009 | 2 if we're emitting the second alternative. */ | |
1010 | int sequence; | |
1011 | ||
1012 | /* The first relaxable fixup in the current frag. (In other words, | |
1013 | the first fixup that refers to relaxable code.) */ | |
1014 | fixS *first_fixup; | |
1015 | ||
1016 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1017 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1018 | unsigned int sizes[2]; | |
1019 | ||
1020 | /* The symbol on which the choice of sequence depends. */ | |
1021 | symbolS *symbol; | |
1022 | } mips_relax; | |
252b5132 | 1023 | \f |
584892a6 RS |
1024 | /* Global variables used to decide whether a macro needs a warning. */ |
1025 | static struct { | |
1026 | /* True if the macro is in a branch delay slot. */ | |
1027 | bfd_boolean delay_slot_p; | |
1028 | ||
1029 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1030 | in bytes and sizes[1] is the length of the second alternative. | |
1031 | For non-relaxable macros, both elements give the length of the | |
1032 | macro in bytes. */ | |
1033 | unsigned int sizes[2]; | |
1034 | ||
1035 | /* The first variant frag for this macro. */ | |
1036 | fragS *first_frag; | |
1037 | } mips_macro_warning; | |
1038 | \f | |
252b5132 RH |
1039 | /* Prototypes for static functions. */ |
1040 | ||
17a2f251 | 1041 | #define internalError() \ |
252b5132 | 1042 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1043 | |
1044 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1045 | ||
b34976b6 | 1046 | static void append_insn |
4d7206a2 | 1047 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 1048 | static void mips_no_prev_insn (void); |
b34976b6 | 1049 | static void mips16_macro_build |
67c0d1eb RS |
1050 | (expressionS *, const char *, const char *, va_list); |
1051 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
1052 | static void macro_start (void); |
1053 | static void macro_end (void); | |
17a2f251 TS |
1054 | static void macro (struct mips_cl_insn * ip); |
1055 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1056 | #ifdef LOSING_COMPILER |
17a2f251 | 1057 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1058 | #endif |
17a2f251 TS |
1059 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1060 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1061 | static void mips16_immed |
17a2f251 TS |
1062 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1063 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1064 | static size_t my_getSmallExpression |
17a2f251 TS |
1065 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1066 | static void my_getExpression (expressionS *, char *); | |
1067 | static void s_align (int); | |
1068 | static void s_change_sec (int); | |
1069 | static void s_change_section (int); | |
1070 | static void s_cons (int); | |
1071 | static void s_float_cons (int); | |
1072 | static void s_mips_globl (int); | |
1073 | static void s_option (int); | |
1074 | static void s_mipsset (int); | |
1075 | static void s_abicalls (int); | |
1076 | static void s_cpload (int); | |
1077 | static void s_cpsetup (int); | |
1078 | static void s_cplocal (int); | |
1079 | static void s_cprestore (int); | |
1080 | static void s_cpreturn (int); | |
741d6ea8 JM |
1081 | static void s_dtprelword (int); |
1082 | static void s_dtpreldword (int); | |
17a2f251 TS |
1083 | static void s_gpvalue (int); |
1084 | static void s_gpword (int); | |
1085 | static void s_gpdword (int); | |
1086 | static void s_cpadd (int); | |
1087 | static void s_insn (int); | |
1088 | static void md_obj_begin (void); | |
1089 | static void md_obj_end (void); | |
1090 | static void s_mips_ent (int); | |
1091 | static void s_mips_end (int); | |
1092 | static void s_mips_frame (int); | |
1093 | static void s_mips_mask (int reg_type); | |
1094 | static void s_mips_stab (int); | |
1095 | static void s_mips_weakext (int); | |
1096 | static void s_mips_file (int); | |
1097 | static void s_mips_loc (int); | |
1098 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1099 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1100 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1101 | |
1102 | /* Table and functions used to map between CPU/ISA names, and | |
1103 | ISA levels, and CPU numbers. */ | |
1104 | ||
e972090a NC |
1105 | struct mips_cpu_info |
1106 | { | |
e7af610e | 1107 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1108 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1109 | int isa; /* ISA level. */ |
1110 | int cpu; /* CPU number (default CPU if ISA). */ | |
1111 | }; | |
1112 | ||
ad3fea08 TS |
1113 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1114 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1115 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1116 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1117 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1118 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1119 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1120 | |
17a2f251 TS |
1121 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1122 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1123 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1124 | \f |
1125 | /* Pseudo-op table. | |
1126 | ||
1127 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1128 | should be defined here, but are currently unsupported: .alias, | |
1129 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1130 | ||
1131 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1132 | specific to the type of debugging information being generated, and | |
1133 | should be defined by the object format: .aent, .begin, .bend, | |
1134 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1135 | .vreg. | |
1136 | ||
1137 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1138 | not MIPS CPU specific, but are also not specific to the object file | |
1139 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1140 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1141 | |
e972090a NC |
1142 | static const pseudo_typeS mips_pseudo_table[] = |
1143 | { | |
beae10d5 | 1144 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1145 | {"option", s_option, 0}, |
1146 | {"set", s_mipsset, 0}, | |
1147 | {"rdata", s_change_sec, 'r'}, | |
1148 | {"sdata", s_change_sec, 's'}, | |
1149 | {"livereg", s_ignore, 0}, | |
1150 | {"abicalls", s_abicalls, 0}, | |
1151 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1152 | {"cpsetup", s_cpsetup, 0}, |
1153 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1154 | {"cprestore", s_cprestore, 0}, |
6478892d | 1155 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1156 | {"dtprelword", s_dtprelword, 0}, |
1157 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1158 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1159 | {"gpword", s_gpword, 0}, |
10181a0d | 1160 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1161 | {"cpadd", s_cpadd, 0}, |
1162 | {"insn", s_insn, 0}, | |
1163 | ||
beae10d5 | 1164 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1165 | chips. */ |
38a57ae7 | 1166 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1167 | {"bss", s_change_sec, 'b'}, |
1168 | {"err", s_err, 0}, | |
1169 | {"half", s_cons, 1}, | |
1170 | {"dword", s_cons, 3}, | |
1171 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1172 | {"origin", s_org, 0}, |
1173 | {"repeat", s_rept, 0}, | |
252b5132 | 1174 | |
beae10d5 | 1175 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1176 | here for one reason or another. */ |
1177 | {"align", s_align, 0}, | |
1178 | {"byte", s_cons, 0}, | |
1179 | {"data", s_change_sec, 'd'}, | |
1180 | {"double", s_float_cons, 'd'}, | |
1181 | {"float", s_float_cons, 'f'}, | |
1182 | {"globl", s_mips_globl, 0}, | |
1183 | {"global", s_mips_globl, 0}, | |
1184 | {"hword", s_cons, 1}, | |
1185 | {"int", s_cons, 2}, | |
1186 | {"long", s_cons, 2}, | |
1187 | {"octa", s_cons, 4}, | |
1188 | {"quad", s_cons, 3}, | |
cca86cc8 | 1189 | {"section", s_change_section, 0}, |
252b5132 RH |
1190 | {"short", s_cons, 1}, |
1191 | {"single", s_float_cons, 'f'}, | |
1192 | {"stabn", s_mips_stab, 'n'}, | |
1193 | {"text", s_change_sec, 't'}, | |
1194 | {"word", s_cons, 2}, | |
add56521 | 1195 | |
add56521 | 1196 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1197 | |
43841e91 | 1198 | { NULL, NULL, 0 }, |
252b5132 RH |
1199 | }; |
1200 | ||
e972090a NC |
1201 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1202 | { | |
beae10d5 KH |
1203 | /* These pseudo-ops should be defined by the object file format. |
1204 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1205 | {"aent", s_mips_ent, 1}, |
1206 | {"bgnb", s_ignore, 0}, | |
1207 | {"end", s_mips_end, 0}, | |
1208 | {"endb", s_ignore, 0}, | |
1209 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1210 | {"file", s_mips_file, 0}, |
252b5132 RH |
1211 | {"fmask", s_mips_mask, 'F'}, |
1212 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1213 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1214 | {"mask", s_mips_mask, 'R'}, |
1215 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1216 | { NULL, NULL, 0 }, |
252b5132 RH |
1217 | }; |
1218 | ||
17a2f251 | 1219 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1220 | |
1221 | void | |
17a2f251 | 1222 | mips_pop_insert (void) |
252b5132 RH |
1223 | { |
1224 | pop_insert (mips_pseudo_table); | |
1225 | if (! ECOFF_DEBUGGING) | |
1226 | pop_insert (mips_nonecoff_pseudo_table); | |
1227 | } | |
1228 | \f | |
1229 | /* Symbols labelling the current insn. */ | |
1230 | ||
e972090a NC |
1231 | struct insn_label_list |
1232 | { | |
252b5132 RH |
1233 | struct insn_label_list *next; |
1234 | symbolS *label; | |
1235 | }; | |
1236 | ||
252b5132 | 1237 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1238 | #define label_list tc_segment_info_data.labels |
252b5132 | 1239 | |
17a2f251 | 1240 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1241 | |
1242 | static inline void | |
17a2f251 | 1243 | mips_clear_insn_labels (void) |
252b5132 RH |
1244 | { |
1245 | register struct insn_label_list **pl; | |
a8dbcb85 | 1246 | segment_info_type *si; |
252b5132 | 1247 | |
a8dbcb85 TS |
1248 | if (now_seg) |
1249 | { | |
1250 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1251 | ; | |
1252 | ||
1253 | si = seg_info (now_seg); | |
1254 | *pl = si->label_list; | |
1255 | si->label_list = NULL; | |
1256 | } | |
252b5132 | 1257 | } |
a8dbcb85 | 1258 | |
252b5132 RH |
1259 | \f |
1260 | static char *expr_end; | |
1261 | ||
1262 | /* Expressions which appear in instructions. These are set by | |
1263 | mips_ip. */ | |
1264 | ||
1265 | static expressionS imm_expr; | |
5f74bc13 | 1266 | static expressionS imm2_expr; |
252b5132 RH |
1267 | static expressionS offset_expr; |
1268 | ||
1269 | /* Relocs associated with imm_expr and offset_expr. */ | |
1270 | ||
f6688943 TS |
1271 | static bfd_reloc_code_real_type imm_reloc[3] |
1272 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1273 | static bfd_reloc_code_real_type offset_reloc[3] | |
1274 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1275 | |
252b5132 RH |
1276 | /* These are set by mips16_ip if an explicit extension is used. */ |
1277 | ||
b34976b6 | 1278 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1279 | |
7ed4a06a | 1280 | #ifdef OBJ_ELF |
ecb4347a DJ |
1281 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1282 | ECOFF debugging. */ | |
252b5132 RH |
1283 | |
1284 | static segT pdr_seg; | |
7ed4a06a | 1285 | #endif |
252b5132 | 1286 | |
e013f690 TS |
1287 | /* The default target format to use. */ |
1288 | ||
1289 | const char * | |
17a2f251 | 1290 | mips_target_format (void) |
e013f690 TS |
1291 | { |
1292 | switch (OUTPUT_FLAVOR) | |
1293 | { | |
e013f690 TS |
1294 | case bfd_target_ecoff_flavour: |
1295 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1296 | case bfd_target_coff_flavour: | |
1297 | return "pe-mips"; | |
1298 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1299 | #ifdef TE_VXWORKS |
1300 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1301 | return (target_big_endian | |
1302 | ? "elf32-bigmips-vxworks" | |
1303 | : "elf32-littlemips-vxworks"); | |
1304 | #endif | |
e013f690 | 1305 | #ifdef TE_TMIPS |
cfe86eaa | 1306 | /* This is traditional mips. */ |
e013f690 | 1307 | return (target_big_endian |
cfe86eaa TS |
1308 | ? (HAVE_64BIT_OBJECTS |
1309 | ? "elf64-tradbigmips" | |
1310 | : (HAVE_NEWABI | |
1311 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1312 | : (HAVE_64BIT_OBJECTS | |
1313 | ? "elf64-tradlittlemips" | |
1314 | : (HAVE_NEWABI | |
1315 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1316 | #else |
1317 | return (target_big_endian | |
cfe86eaa TS |
1318 | ? (HAVE_64BIT_OBJECTS |
1319 | ? "elf64-bigmips" | |
1320 | : (HAVE_NEWABI | |
1321 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1322 | : (HAVE_64BIT_OBJECTS | |
1323 | ? "elf64-littlemips" | |
1324 | : (HAVE_NEWABI | |
1325 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1326 | #endif |
1327 | default: | |
1328 | abort (); | |
1329 | return NULL; | |
1330 | } | |
1331 | } | |
1332 | ||
1e915849 RS |
1333 | /* Return the length of instruction INSN. */ |
1334 | ||
1335 | static inline unsigned int | |
1336 | insn_length (const struct mips_cl_insn *insn) | |
1337 | { | |
1338 | if (!mips_opts.mips16) | |
1339 | return 4; | |
1340 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1341 | } | |
1342 | ||
1343 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1344 | ||
1345 | static void | |
1346 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1347 | { | |
1348 | size_t i; | |
1349 | ||
1350 | insn->insn_mo = mo; | |
1351 | insn->use_extend = FALSE; | |
1352 | insn->extend = 0; | |
1353 | insn->insn_opcode = mo->match; | |
1354 | insn->frag = NULL; | |
1355 | insn->where = 0; | |
1356 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1357 | insn->fixp[i] = NULL; | |
1358 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1359 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1360 | insn->mips16_absolute_jump_p = 0; | |
1361 | } | |
1362 | ||
742a56fe RS |
1363 | /* Record the current MIPS16 mode in now_seg. */ |
1364 | ||
1365 | static void | |
1366 | mips_record_mips16_mode (void) | |
1367 | { | |
1368 | segment_info_type *si; | |
1369 | ||
1370 | si = seg_info (now_seg); | |
1371 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1372 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1373 | } | |
1374 | ||
1e915849 RS |
1375 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1376 | ||
1377 | static void | |
1378 | install_insn (const struct mips_cl_insn *insn) | |
1379 | { | |
1380 | char *f = insn->frag->fr_literal + insn->where; | |
1381 | if (!mips_opts.mips16) | |
1382 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1383 | else if (insn->mips16_absolute_jump_p) | |
1384 | { | |
1385 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1386 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1387 | } | |
1388 | else | |
1389 | { | |
1390 | if (insn->use_extend) | |
1391 | { | |
1392 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1393 | f += 2; | |
1394 | } | |
1395 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1396 | } | |
742a56fe | 1397 | mips_record_mips16_mode (); |
1e915849 RS |
1398 | } |
1399 | ||
1400 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1401 | and install the opcode in the new location. */ | |
1402 | ||
1403 | static void | |
1404 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1405 | { | |
1406 | size_t i; | |
1407 | ||
1408 | insn->frag = frag; | |
1409 | insn->where = where; | |
1410 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1411 | if (insn->fixp[i] != NULL) | |
1412 | { | |
1413 | insn->fixp[i]->fx_frag = frag; | |
1414 | insn->fixp[i]->fx_where = where; | |
1415 | } | |
1416 | install_insn (insn); | |
1417 | } | |
1418 | ||
1419 | /* Add INSN to the end of the output. */ | |
1420 | ||
1421 | static void | |
1422 | add_fixed_insn (struct mips_cl_insn *insn) | |
1423 | { | |
1424 | char *f = frag_more (insn_length (insn)); | |
1425 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1426 | } | |
1427 | ||
1428 | /* Start a variant frag and move INSN to the start of the variant part, | |
1429 | marking it as fixed. The other arguments are as for frag_var. */ | |
1430 | ||
1431 | static void | |
1432 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1433 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1434 | { | |
1435 | frag_grow (max_chars); | |
1436 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1437 | insn->fixed_p = 1; | |
1438 | frag_var (rs_machine_dependent, max_chars, var, | |
1439 | subtype, symbol, offset, NULL); | |
1440 | } | |
1441 | ||
1442 | /* Insert N copies of INSN into the history buffer, starting at | |
1443 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1444 | ||
1445 | static void | |
1446 | insert_into_history (unsigned int first, unsigned int n, | |
1447 | const struct mips_cl_insn *insn) | |
1448 | { | |
1449 | if (mips_relax.sequence != 2) | |
1450 | { | |
1451 | unsigned int i; | |
1452 | ||
1453 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1454 | if (i >= first + n) | |
1455 | history[i] = history[i - n]; | |
1456 | else | |
1457 | history[i] = *insn; | |
1458 | } | |
1459 | } | |
1460 | ||
1461 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1462 | ||
1463 | static void | |
1464 | emit_nop (void) | |
1465 | { | |
1466 | add_fixed_insn (NOP_INSN); | |
1467 | insert_into_history (0, 1, NOP_INSN); | |
1468 | } | |
1469 | ||
71400594 RS |
1470 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1471 | the idea is to make it obvious at a glance that each errata is | |
1472 | included. */ | |
1473 | ||
1474 | static void | |
1475 | init_vr4120_conflicts (void) | |
1476 | { | |
1477 | #define CONFLICT(FIRST, SECOND) \ | |
1478 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1479 | ||
1480 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1481 | CONFLICT (MACC, DIV); | |
1482 | CONFLICT (DMACC, DIV); | |
1483 | ||
1484 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1485 | CONFLICT (DMULT, DMULT); | |
1486 | CONFLICT (DMULT, DMACC); | |
1487 | CONFLICT (DMACC, DMULT); | |
1488 | CONFLICT (DMACC, DMACC); | |
1489 | ||
1490 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1491 | CONFLICT (MACC, MTHILO); | |
1492 | CONFLICT (DMACC, MTHILO); | |
1493 | ||
1494 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1495 | instruction is executed immediately after a MACC or DMACC | |
1496 | instruction, the result of [either instruction] is incorrect." */ | |
1497 | CONFLICT (MACC, MULT); | |
1498 | CONFLICT (MACC, DMULT); | |
1499 | CONFLICT (DMACC, MULT); | |
1500 | CONFLICT (DMACC, DMULT); | |
1501 | ||
1502 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1503 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1504 | DDIV or DDIVU instruction, the result of the MACC or | |
1505 | DMACC instruction is incorrect.". */ | |
1506 | CONFLICT (DMULT, MACC); | |
1507 | CONFLICT (DMULT, DMACC); | |
1508 | CONFLICT (DIV, MACC); | |
1509 | CONFLICT (DIV, DMACC); | |
1510 | ||
1511 | #undef CONFLICT | |
1512 | } | |
1513 | ||
707bfff6 TS |
1514 | struct regname { |
1515 | const char *name; | |
1516 | unsigned int num; | |
1517 | }; | |
1518 | ||
1519 | #define RTYPE_MASK 0x1ff00 | |
1520 | #define RTYPE_NUM 0x00100 | |
1521 | #define RTYPE_FPU 0x00200 | |
1522 | #define RTYPE_FCC 0x00400 | |
1523 | #define RTYPE_VEC 0x00800 | |
1524 | #define RTYPE_GP 0x01000 | |
1525 | #define RTYPE_CP0 0x02000 | |
1526 | #define RTYPE_PC 0x04000 | |
1527 | #define RTYPE_ACC 0x08000 | |
1528 | #define RTYPE_CCC 0x10000 | |
1529 | #define RNUM_MASK 0x000ff | |
1530 | #define RWARN 0x80000 | |
1531 | ||
1532 | #define GENERIC_REGISTER_NUMBERS \ | |
1533 | {"$0", RTYPE_NUM | 0}, \ | |
1534 | {"$1", RTYPE_NUM | 1}, \ | |
1535 | {"$2", RTYPE_NUM | 2}, \ | |
1536 | {"$3", RTYPE_NUM | 3}, \ | |
1537 | {"$4", RTYPE_NUM | 4}, \ | |
1538 | {"$5", RTYPE_NUM | 5}, \ | |
1539 | {"$6", RTYPE_NUM | 6}, \ | |
1540 | {"$7", RTYPE_NUM | 7}, \ | |
1541 | {"$8", RTYPE_NUM | 8}, \ | |
1542 | {"$9", RTYPE_NUM | 9}, \ | |
1543 | {"$10", RTYPE_NUM | 10}, \ | |
1544 | {"$11", RTYPE_NUM | 11}, \ | |
1545 | {"$12", RTYPE_NUM | 12}, \ | |
1546 | {"$13", RTYPE_NUM | 13}, \ | |
1547 | {"$14", RTYPE_NUM | 14}, \ | |
1548 | {"$15", RTYPE_NUM | 15}, \ | |
1549 | {"$16", RTYPE_NUM | 16}, \ | |
1550 | {"$17", RTYPE_NUM | 17}, \ | |
1551 | {"$18", RTYPE_NUM | 18}, \ | |
1552 | {"$19", RTYPE_NUM | 19}, \ | |
1553 | {"$20", RTYPE_NUM | 20}, \ | |
1554 | {"$21", RTYPE_NUM | 21}, \ | |
1555 | {"$22", RTYPE_NUM | 22}, \ | |
1556 | {"$23", RTYPE_NUM | 23}, \ | |
1557 | {"$24", RTYPE_NUM | 24}, \ | |
1558 | {"$25", RTYPE_NUM | 25}, \ | |
1559 | {"$26", RTYPE_NUM | 26}, \ | |
1560 | {"$27", RTYPE_NUM | 27}, \ | |
1561 | {"$28", RTYPE_NUM | 28}, \ | |
1562 | {"$29", RTYPE_NUM | 29}, \ | |
1563 | {"$30", RTYPE_NUM | 30}, \ | |
1564 | {"$31", RTYPE_NUM | 31} | |
1565 | ||
1566 | #define FPU_REGISTER_NAMES \ | |
1567 | {"$f0", RTYPE_FPU | 0}, \ | |
1568 | {"$f1", RTYPE_FPU | 1}, \ | |
1569 | {"$f2", RTYPE_FPU | 2}, \ | |
1570 | {"$f3", RTYPE_FPU | 3}, \ | |
1571 | {"$f4", RTYPE_FPU | 4}, \ | |
1572 | {"$f5", RTYPE_FPU | 5}, \ | |
1573 | {"$f6", RTYPE_FPU | 6}, \ | |
1574 | {"$f7", RTYPE_FPU | 7}, \ | |
1575 | {"$f8", RTYPE_FPU | 8}, \ | |
1576 | {"$f9", RTYPE_FPU | 9}, \ | |
1577 | {"$f10", RTYPE_FPU | 10}, \ | |
1578 | {"$f11", RTYPE_FPU | 11}, \ | |
1579 | {"$f12", RTYPE_FPU | 12}, \ | |
1580 | {"$f13", RTYPE_FPU | 13}, \ | |
1581 | {"$f14", RTYPE_FPU | 14}, \ | |
1582 | {"$f15", RTYPE_FPU | 15}, \ | |
1583 | {"$f16", RTYPE_FPU | 16}, \ | |
1584 | {"$f17", RTYPE_FPU | 17}, \ | |
1585 | {"$f18", RTYPE_FPU | 18}, \ | |
1586 | {"$f19", RTYPE_FPU | 19}, \ | |
1587 | {"$f20", RTYPE_FPU | 20}, \ | |
1588 | {"$f21", RTYPE_FPU | 21}, \ | |
1589 | {"$f22", RTYPE_FPU | 22}, \ | |
1590 | {"$f23", RTYPE_FPU | 23}, \ | |
1591 | {"$f24", RTYPE_FPU | 24}, \ | |
1592 | {"$f25", RTYPE_FPU | 25}, \ | |
1593 | {"$f26", RTYPE_FPU | 26}, \ | |
1594 | {"$f27", RTYPE_FPU | 27}, \ | |
1595 | {"$f28", RTYPE_FPU | 28}, \ | |
1596 | {"$f29", RTYPE_FPU | 29}, \ | |
1597 | {"$f30", RTYPE_FPU | 30}, \ | |
1598 | {"$f31", RTYPE_FPU | 31} | |
1599 | ||
1600 | #define FPU_CONDITION_CODE_NAMES \ | |
1601 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1602 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1603 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1604 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1605 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1606 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1607 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1608 | {"$fcc7", RTYPE_FCC | 7} | |
1609 | ||
1610 | #define COPROC_CONDITION_CODE_NAMES \ | |
1611 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1612 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1613 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1614 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1615 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1616 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1617 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1618 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1619 | ||
1620 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1621 | {"$a4", RTYPE_GP | 8}, \ | |
1622 | {"$a5", RTYPE_GP | 9}, \ | |
1623 | {"$a6", RTYPE_GP | 10}, \ | |
1624 | {"$a7", RTYPE_GP | 11}, \ | |
1625 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1626 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1627 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1628 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1629 | {"$t0", RTYPE_GP | 12}, \ | |
1630 | {"$t1", RTYPE_GP | 13}, \ | |
1631 | {"$t2", RTYPE_GP | 14}, \ | |
1632 | {"$t3", RTYPE_GP | 15} | |
1633 | ||
1634 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1635 | {"$t0", RTYPE_GP | 8}, \ | |
1636 | {"$t1", RTYPE_GP | 9}, \ | |
1637 | {"$t2", RTYPE_GP | 10}, \ | |
1638 | {"$t3", RTYPE_GP | 11}, \ | |
1639 | {"$t4", RTYPE_GP | 12}, \ | |
1640 | {"$t5", RTYPE_GP | 13}, \ | |
1641 | {"$t6", RTYPE_GP | 14}, \ | |
1642 | {"$t7", RTYPE_GP | 15}, \ | |
1643 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1644 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1645 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1646 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1647 | ||
1648 | /* Remaining symbolic register names */ | |
1649 | #define SYMBOLIC_REGISTER_NAMES \ | |
1650 | {"$zero", RTYPE_GP | 0}, \ | |
1651 | {"$at", RTYPE_GP | 1}, \ | |
1652 | {"$AT", RTYPE_GP | 1}, \ | |
1653 | {"$v0", RTYPE_GP | 2}, \ | |
1654 | {"$v1", RTYPE_GP | 3}, \ | |
1655 | {"$a0", RTYPE_GP | 4}, \ | |
1656 | {"$a1", RTYPE_GP | 5}, \ | |
1657 | {"$a2", RTYPE_GP | 6}, \ | |
1658 | {"$a3", RTYPE_GP | 7}, \ | |
1659 | {"$s0", RTYPE_GP | 16}, \ | |
1660 | {"$s1", RTYPE_GP | 17}, \ | |
1661 | {"$s2", RTYPE_GP | 18}, \ | |
1662 | {"$s3", RTYPE_GP | 19}, \ | |
1663 | {"$s4", RTYPE_GP | 20}, \ | |
1664 | {"$s5", RTYPE_GP | 21}, \ | |
1665 | {"$s6", RTYPE_GP | 22}, \ | |
1666 | {"$s7", RTYPE_GP | 23}, \ | |
1667 | {"$t8", RTYPE_GP | 24}, \ | |
1668 | {"$t9", RTYPE_GP | 25}, \ | |
1669 | {"$k0", RTYPE_GP | 26}, \ | |
1670 | {"$kt0", RTYPE_GP | 26}, \ | |
1671 | {"$k1", RTYPE_GP | 27}, \ | |
1672 | {"$kt1", RTYPE_GP | 27}, \ | |
1673 | {"$gp", RTYPE_GP | 28}, \ | |
1674 | {"$sp", RTYPE_GP | 29}, \ | |
1675 | {"$s8", RTYPE_GP | 30}, \ | |
1676 | {"$fp", RTYPE_GP | 30}, \ | |
1677 | {"$ra", RTYPE_GP | 31} | |
1678 | ||
1679 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1680 | {"$pc", RTYPE_PC | 0} | |
1681 | ||
1682 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1683 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1684 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1685 | {"$v2", RTYPE_VEC | 2}, \ | |
1686 | {"$v3", RTYPE_VEC | 3}, \ | |
1687 | {"$v4", RTYPE_VEC | 4}, \ | |
1688 | {"$v5", RTYPE_VEC | 5}, \ | |
1689 | {"$v6", RTYPE_VEC | 6}, \ | |
1690 | {"$v7", RTYPE_VEC | 7}, \ | |
1691 | {"$v8", RTYPE_VEC | 8}, \ | |
1692 | {"$v9", RTYPE_VEC | 9}, \ | |
1693 | {"$v10", RTYPE_VEC | 10}, \ | |
1694 | {"$v11", RTYPE_VEC | 11}, \ | |
1695 | {"$v12", RTYPE_VEC | 12}, \ | |
1696 | {"$v13", RTYPE_VEC | 13}, \ | |
1697 | {"$v14", RTYPE_VEC | 14}, \ | |
1698 | {"$v15", RTYPE_VEC | 15}, \ | |
1699 | {"$v16", RTYPE_VEC | 16}, \ | |
1700 | {"$v17", RTYPE_VEC | 17}, \ | |
1701 | {"$v18", RTYPE_VEC | 18}, \ | |
1702 | {"$v19", RTYPE_VEC | 19}, \ | |
1703 | {"$v20", RTYPE_VEC | 20}, \ | |
1704 | {"$v21", RTYPE_VEC | 21}, \ | |
1705 | {"$v22", RTYPE_VEC | 22}, \ | |
1706 | {"$v23", RTYPE_VEC | 23}, \ | |
1707 | {"$v24", RTYPE_VEC | 24}, \ | |
1708 | {"$v25", RTYPE_VEC | 25}, \ | |
1709 | {"$v26", RTYPE_VEC | 26}, \ | |
1710 | {"$v27", RTYPE_VEC | 27}, \ | |
1711 | {"$v28", RTYPE_VEC | 28}, \ | |
1712 | {"$v29", RTYPE_VEC | 29}, \ | |
1713 | {"$v30", RTYPE_VEC | 30}, \ | |
1714 | {"$v31", RTYPE_VEC | 31} | |
1715 | ||
1716 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1717 | {"$ac0", RTYPE_ACC | 0}, \ | |
1718 | {"$ac1", RTYPE_ACC | 1}, \ | |
1719 | {"$ac2", RTYPE_ACC | 2}, \ | |
1720 | {"$ac3", RTYPE_ACC | 3} | |
1721 | ||
1722 | static const struct regname reg_names[] = { | |
1723 | GENERIC_REGISTER_NUMBERS, | |
1724 | FPU_REGISTER_NAMES, | |
1725 | FPU_CONDITION_CODE_NAMES, | |
1726 | COPROC_CONDITION_CODE_NAMES, | |
1727 | ||
1728 | /* The $txx registers depends on the abi, | |
1729 | these will be added later into the symbol table from | |
1730 | one of the tables below once mips_abi is set after | |
1731 | parsing of arguments from the command line. */ | |
1732 | SYMBOLIC_REGISTER_NAMES, | |
1733 | ||
1734 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1735 | MDMX_VECTOR_REGISTER_NAMES, | |
1736 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1737 | {0, 0} | |
1738 | }; | |
1739 | ||
1740 | static const struct regname reg_names_o32[] = { | |
1741 | O32_SYMBOLIC_REGISTER_NAMES, | |
1742 | {0, 0} | |
1743 | }; | |
1744 | ||
1745 | static const struct regname reg_names_n32n64[] = { | |
1746 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1747 | {0, 0} | |
1748 | }; | |
1749 | ||
1750 | static int | |
1751 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1752 | { | |
1753 | symbolS *symbolP; | |
1754 | char *e; | |
1755 | char save_c; | |
1756 | int reg = -1; | |
1757 | ||
1758 | /* Find end of name. */ | |
1759 | e = *s; | |
1760 | if (is_name_beginner (*e)) | |
1761 | ++e; | |
1762 | while (is_part_of_name (*e)) | |
1763 | ++e; | |
1764 | ||
1765 | /* Terminate name. */ | |
1766 | save_c = *e; | |
1767 | *e = '\0'; | |
1768 | ||
1769 | /* Look for a register symbol. */ | |
1770 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1771 | { | |
1772 | int r = S_GET_VALUE (symbolP); | |
1773 | if (r & types) | |
1774 | reg = r & RNUM_MASK; | |
1775 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1776 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1777 | reg = (r & RNUM_MASK) - 2; | |
1778 | } | |
1779 | /* Else see if this is a register defined in an itbl entry. */ | |
1780 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1781 | { | |
1782 | char *n = *s; | |
1783 | unsigned long r; | |
1784 | ||
1785 | if (*n == '$') | |
1786 | ++n; | |
1787 | if (itbl_get_reg_val (n, &r)) | |
1788 | reg = r & RNUM_MASK; | |
1789 | } | |
1790 | ||
1791 | /* Advance to next token if a register was recognised. */ | |
1792 | if (reg >= 0) | |
1793 | *s = e; | |
1794 | else if (types & RWARN) | |
20203fb9 | 1795 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1796 | |
1797 | *e = save_c; | |
1798 | if (regnop) | |
1799 | *regnop = reg; | |
1800 | return reg >= 0; | |
1801 | } | |
1802 | ||
037b32b9 AN |
1803 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
1804 | architecture. If EXPANSIONP is TRUE then this check is done while | |
1805 | expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
1806 | ||
1807 | static bfd_boolean | |
1808 | is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp) | |
1809 | { | |
1810 | int isa = mips_opts.isa; | |
1811 | int fp_s, fp_d; | |
1812 | ||
1813 | if (mips_opts.ase_mdmx) | |
1814 | isa |= INSN_MDMX; | |
1815 | if (mips_opts.ase_dsp) | |
1816 | isa |= INSN_DSP; | |
1817 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1818 | isa |= INSN_DSP64; | |
1819 | if (mips_opts.ase_dspr2) | |
1820 | isa |= INSN_DSPR2; | |
1821 | if (mips_opts.ase_mt) | |
1822 | isa |= INSN_MT; | |
1823 | if (mips_opts.ase_mips3d) | |
1824 | isa |= INSN_MIPS3D; | |
1825 | if (mips_opts.ase_smartmips) | |
1826 | isa |= INSN_SMARTMIPS; | |
1827 | ||
1828 | /* For user code we don't check for mips_opts.mips16 since we want | |
1829 | to allow jalx if -mips16 was specified on the command line. */ | |
1830 | if (expansionp ? mips_opts.mips16 : file_ase_mips16) | |
1831 | isa |= INSN_MIPS16; | |
1832 | ||
b19e8a9b AN |
1833 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1834 | all the coprocessor insns. */ | |
1835 | if (NO_ISA_COP (mips_opts.arch) | |
1836 | && COP_INSN (mo->pinfo)) | |
1837 | isa = 0; | |
1838 | ||
037b32b9 AN |
1839 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1840 | return FALSE; | |
1841 | ||
1842 | /* Check whether the instruction or macro requires single-precision or | |
1843 | double-precision floating-point support. Note that this information is | |
1844 | stored differently in the opcode table for insns and macros. */ | |
1845 | if (mo->pinfo == INSN_MACRO) | |
1846 | { | |
1847 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1848 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1849 | } | |
1850 | else | |
1851 | { | |
1852 | fp_s = mo->pinfo & FP_S; | |
1853 | fp_d = mo->pinfo & FP_D; | |
1854 | } | |
1855 | ||
1856 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1857 | return FALSE; | |
1858 | ||
1859 | if (fp_s && mips_opts.soft_float) | |
1860 | return FALSE; | |
1861 | ||
1862 | return TRUE; | |
1863 | } | |
1864 | ||
1865 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1866 | selected ISA and architecture. */ | |
1867 | ||
1868 | static bfd_boolean | |
1869 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1870 | { | |
1871 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1872 | } | |
1873 | ||
707bfff6 TS |
1874 | /* This function is called once, at assembler startup time. It should set up |
1875 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1876 | |
252b5132 | 1877 | void |
17a2f251 | 1878 | md_begin (void) |
252b5132 | 1879 | { |
3994f87e | 1880 | const char *retval = NULL; |
156c2f8b | 1881 | int i = 0; |
252b5132 | 1882 | int broken = 0; |
1f25f5d3 | 1883 | |
0a44bf69 RS |
1884 | if (mips_pic != NO_PIC) |
1885 | { | |
1886 | if (g_switch_seen && g_switch_value != 0) | |
1887 | as_bad (_("-G may not be used in position-independent code")); | |
1888 | g_switch_value = 0; | |
1889 | } | |
1890 | ||
fef14a42 | 1891 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1892 | as_warn (_("Could not set architecture and machine")); |
1893 | ||
252b5132 RH |
1894 | op_hash = hash_new (); |
1895 | ||
1896 | for (i = 0; i < NUMOPCODES;) | |
1897 | { | |
1898 | const char *name = mips_opcodes[i].name; | |
1899 | ||
17a2f251 | 1900 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1901 | if (retval != NULL) |
1902 | { | |
1903 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1904 | mips_opcodes[i].name, retval); | |
1905 | /* Probably a memory allocation problem? Give up now. */ | |
1906 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1907 | } | |
1908 | do | |
1909 | { | |
1910 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1911 | { | |
1912 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1913 | broken = 1; | |
1e915849 RS |
1914 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1915 | { | |
1916 | create_insn (&nop_insn, mips_opcodes + i); | |
1917 | nop_insn.fixed_p = 1; | |
1918 | } | |
252b5132 RH |
1919 | } |
1920 | ++i; | |
1921 | } | |
1922 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1923 | } | |
1924 | ||
1925 | mips16_op_hash = hash_new (); | |
1926 | ||
1927 | i = 0; | |
1928 | while (i < bfd_mips16_num_opcodes) | |
1929 | { | |
1930 | const char *name = mips16_opcodes[i].name; | |
1931 | ||
17a2f251 | 1932 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1933 | if (retval != NULL) |
1934 | as_fatal (_("internal: can't hash `%s': %s"), | |
1935 | mips16_opcodes[i].name, retval); | |
1936 | do | |
1937 | { | |
1938 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1939 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1940 | != mips16_opcodes[i].match)) | |
1941 | { | |
1942 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1943 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1944 | broken = 1; | |
1945 | } | |
1e915849 RS |
1946 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1947 | { | |
1948 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1949 | mips16_nop_insn.fixed_p = 1; | |
1950 | } | |
252b5132 RH |
1951 | ++i; |
1952 | } | |
1953 | while (i < bfd_mips16_num_opcodes | |
1954 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1955 | } | |
1956 | ||
1957 | if (broken) | |
1958 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1959 | ||
1960 | /* We add all the general register names to the symbol table. This | |
1961 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1962 | for (i = 0; reg_names[i].name; i++) |
1963 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1964 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1965 | &zero_address_frag)); |
1966 | if (HAVE_NEWABI) | |
1967 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1968 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1969 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1970 | &zero_address_frag)); |
707bfff6 TS |
1971 | else |
1972 | for (i = 0; reg_names_o32[i].name; i++) | |
1973 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1974 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1975 | &zero_address_frag)); |
6047c971 | 1976 | |
7d10b47d | 1977 | mips_no_prev_insn (); |
252b5132 RH |
1978 | |
1979 | mips_gprmask = 0; | |
1980 | mips_cprmask[0] = 0; | |
1981 | mips_cprmask[1] = 0; | |
1982 | mips_cprmask[2] = 0; | |
1983 | mips_cprmask[3] = 0; | |
1984 | ||
1985 | /* set the default alignment for the text section (2**2) */ | |
1986 | record_alignment (text_section, 2); | |
1987 | ||
4d0d148d | 1988 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1989 | |
707bfff6 | 1990 | #ifdef OBJ_ELF |
f43abd2b | 1991 | if (IS_ELF) |
252b5132 | 1992 | { |
0a44bf69 RS |
1993 | /* On a native system other than VxWorks, sections must be aligned |
1994 | to 16 byte boundaries. When configured for an embedded ELF | |
1995 | target, we don't bother. */ | |
c41e87e3 CF |
1996 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
1997 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
1998 | { |
1999 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2000 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2001 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2002 | } | |
2003 | ||
2004 | /* Create a .reginfo section for register masks and a .mdebug | |
2005 | section for debugging information. */ | |
2006 | { | |
2007 | segT seg; | |
2008 | subsegT subseg; | |
2009 | flagword flags; | |
2010 | segT sec; | |
2011 | ||
2012 | seg = now_seg; | |
2013 | subseg = now_subseg; | |
2014 | ||
2015 | /* The ABI says this section should be loaded so that the | |
2016 | running program can access it. However, we don't load it | |
2017 | if we are configured for an embedded target */ | |
2018 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2019 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2020 | flags |= SEC_ALLOC | SEC_LOAD; |
2021 | ||
316f5878 | 2022 | if (mips_abi != N64_ABI) |
252b5132 RH |
2023 | { |
2024 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2025 | ||
195325d2 TS |
2026 | bfd_set_section_flags (stdoutput, sec, flags); |
2027 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2028 | |
252b5132 | 2029 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2030 | } |
2031 | else | |
2032 | { | |
2033 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2034 | .reginfo section. */ | |
2035 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2036 | bfd_set_section_flags (stdoutput, sec, flags); |
2037 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2038 | |
252b5132 RH |
2039 | /* Set up the option header. */ |
2040 | { | |
2041 | Elf_Internal_Options opthdr; | |
2042 | char *f; | |
2043 | ||
2044 | opthdr.kind = ODK_REGINFO; | |
2045 | opthdr.size = (sizeof (Elf_External_Options) | |
2046 | + sizeof (Elf64_External_RegInfo)); | |
2047 | opthdr.section = 0; | |
2048 | opthdr.info = 0; | |
2049 | f = frag_more (sizeof (Elf_External_Options)); | |
2050 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2051 | (Elf_External_Options *) f); | |
2052 | ||
2053 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2054 | } | |
252b5132 RH |
2055 | } |
2056 | ||
2057 | if (ECOFF_DEBUGGING) | |
2058 | { | |
2059 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2060 | (void) bfd_set_section_flags (stdoutput, sec, | |
2061 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2062 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2063 | } | |
f43abd2b | 2064 | else if (mips_flag_pdr) |
ecb4347a DJ |
2065 | { |
2066 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2067 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2068 | SEC_READONLY | SEC_RELOC | |
2069 | | SEC_DEBUGGING); | |
2070 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2071 | } | |
252b5132 RH |
2072 | |
2073 | subseg_set (seg, subseg); | |
2074 | } | |
2075 | } | |
707bfff6 | 2076 | #endif /* OBJ_ELF */ |
252b5132 RH |
2077 | |
2078 | if (! ECOFF_DEBUGGING) | |
2079 | md_obj_begin (); | |
71400594 RS |
2080 | |
2081 | if (mips_fix_vr4120) | |
2082 | init_vr4120_conflicts (); | |
252b5132 RH |
2083 | } |
2084 | ||
2085 | void | |
17a2f251 | 2086 | md_mips_end (void) |
252b5132 RH |
2087 | { |
2088 | if (! ECOFF_DEBUGGING) | |
2089 | md_obj_end (); | |
2090 | } | |
2091 | ||
2092 | void | |
17a2f251 | 2093 | md_assemble (char *str) |
252b5132 RH |
2094 | { |
2095 | struct mips_cl_insn insn; | |
f6688943 TS |
2096 | bfd_reloc_code_real_type unused_reloc[3] |
2097 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2098 | |
2099 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2100 | imm2_expr.X_op = O_absent; |
252b5132 | 2101 | offset_expr.X_op = O_absent; |
f6688943 TS |
2102 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2103 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2104 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2105 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2106 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2107 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2108 | |
2109 | if (mips_opts.mips16) | |
2110 | mips16_ip (str, &insn); | |
2111 | else | |
2112 | { | |
2113 | mips_ip (str, &insn); | |
beae10d5 KH |
2114 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2115 | str, insn.insn_opcode)); | |
252b5132 RH |
2116 | } |
2117 | ||
2118 | if (insn_error) | |
2119 | { | |
2120 | as_bad ("%s `%s'", insn_error, str); | |
2121 | return; | |
2122 | } | |
2123 | ||
2124 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2125 | { | |
584892a6 | 2126 | macro_start (); |
252b5132 RH |
2127 | if (mips_opts.mips16) |
2128 | mips16_macro (&insn); | |
2129 | else | |
2130 | macro (&insn); | |
584892a6 | 2131 | macro_end (); |
252b5132 RH |
2132 | } |
2133 | else | |
2134 | { | |
2135 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2136 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2137 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2138 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2139 | else |
4d7206a2 | 2140 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2141 | } |
2142 | } | |
2143 | ||
738e5348 RS |
2144 | /* Convenience functions for abstracting away the differences between |
2145 | MIPS16 and non-MIPS16 relocations. */ | |
2146 | ||
2147 | static inline bfd_boolean | |
2148 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2149 | { | |
2150 | switch (reloc) | |
2151 | { | |
2152 | case BFD_RELOC_MIPS16_JMP: | |
2153 | case BFD_RELOC_MIPS16_GPREL: | |
2154 | case BFD_RELOC_MIPS16_GOT16: | |
2155 | case BFD_RELOC_MIPS16_CALL16: | |
2156 | case BFD_RELOC_MIPS16_HI16_S: | |
2157 | case BFD_RELOC_MIPS16_HI16: | |
2158 | case BFD_RELOC_MIPS16_LO16: | |
2159 | return TRUE; | |
2160 | ||
2161 | default: | |
2162 | return FALSE; | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | static inline bfd_boolean | |
2167 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2168 | { | |
2169 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2170 | } | |
2171 | ||
2172 | static inline bfd_boolean | |
2173 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2174 | { | |
2175 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2176 | } | |
2177 | ||
2178 | static inline bfd_boolean | |
2179 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2180 | { | |
2181 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2182 | } | |
2183 | ||
5919d012 | 2184 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2185 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2186 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2187 | |
2188 | static inline bfd_boolean | |
17a2f251 | 2189 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2190 | { |
3b91255e | 2191 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2192 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2193 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2194 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2195 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2196 | } | |
2197 | ||
2198 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2199 | reloc_needs_lo_p. */ | |
2200 | ||
2201 | static inline bfd_reloc_code_real_type | |
2202 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2203 | { | |
2204 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2205 | } |
2206 | ||
2207 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2208 | relocation. */ | |
2209 | ||
2210 | static inline bfd_boolean | |
17a2f251 | 2211 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2212 | { |
2213 | return (fixp->fx_next != NULL | |
738e5348 | 2214 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2215 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2216 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2217 | } | |
2218 | ||
252b5132 RH |
2219 | /* See whether instruction IP reads register REG. CLASS is the type |
2220 | of register. */ | |
2221 | ||
2222 | static int | |
71400594 | 2223 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2224 | enum mips_regclass regclass) |
252b5132 | 2225 | { |
96d56e9f | 2226 | if (regclass == MIPS16_REG) |
252b5132 | 2227 | { |
9c2799c2 | 2228 | gas_assert (mips_opts.mips16); |
252b5132 | 2229 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2230 | regclass = MIPS_GR_REG; |
252b5132 RH |
2231 | } |
2232 | ||
85b51719 | 2233 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2234 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2235 | return 0; |
2236 | ||
96d56e9f | 2237 | if (regclass == MIPS_FP_REG) |
252b5132 | 2238 | { |
9c2799c2 | 2239 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2240 | /* If we are called with either $f0 or $f1, we must check $f0. |
2241 | This is not optimal, because it will introduce an unnecessary | |
2242 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2243 | need to distinguish reading both $f0 and $f1 or just one of | |
2244 | them. Note that we don't have to check the other way, | |
2245 | because there is no instruction that sets both $f0 and $f1 | |
2246 | and requires a delay. */ | |
2247 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2248 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2249 | == (reg &~ (unsigned) 1))) |
2250 | return 1; | |
2251 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2252 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2253 | == (reg &~ (unsigned) 1))) |
2254 | return 1; | |
2255 | } | |
2256 | else if (! mips_opts.mips16) | |
2257 | { | |
2258 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2259 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2260 | return 1; |
2261 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2262 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2263 | return 1; |
2264 | } | |
2265 | else | |
2266 | { | |
2267 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2268 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2269 | return 1; |
2270 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2271 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2272 | return 1; |
2273 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2274 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2275 | == reg)) |
2276 | return 1; | |
2277 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2278 | return 1; | |
2279 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2280 | return 1; | |
2281 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2282 | return 1; | |
2283 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2284 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2285 | return 1; |
2286 | } | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
2291 | /* This function returns true if modifying a register requires a | |
2292 | delay. */ | |
2293 | ||
2294 | static int | |
17a2f251 | 2295 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2296 | { |
2297 | unsigned long prev_pinfo; | |
2298 | ||
47e39b9d | 2299 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2300 | if (! mips_opts.noreorder |
81912461 ILT |
2301 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2302 | && ! gpr_interlocks) | |
2303 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2304 | && ! cop_interlocks))) | |
252b5132 | 2305 | { |
81912461 ILT |
2306 | /* A load from a coprocessor or from memory. All load delays |
2307 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2308 | /* Itbl support may require additional care here. */ |
252b5132 | 2309 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2310 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2311 | return 1; |
2312 | } | |
2313 | ||
2314 | return 0; | |
2315 | } | |
2316 | ||
404a8071 RS |
2317 | /* Move all labels in insn_labels to the current insertion point. */ |
2318 | ||
2319 | static void | |
2320 | mips_move_labels (void) | |
2321 | { | |
a8dbcb85 | 2322 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2323 | struct insn_label_list *l; |
2324 | valueT val; | |
2325 | ||
a8dbcb85 | 2326 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2327 | { |
9c2799c2 | 2328 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2329 | symbol_set_frag (l->label, frag_now); |
2330 | val = (valueT) frag_now_fix (); | |
2331 | /* mips16 text labels are stored as odd. */ | |
2332 | if (mips_opts.mips16) | |
2333 | ++val; | |
2334 | S_SET_VALUE (l->label, val); | |
2335 | } | |
2336 | } | |
2337 | ||
5f0fe04b TS |
2338 | static bfd_boolean |
2339 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2340 | { | |
2341 | bfd_boolean linkonce = FALSE; | |
2342 | segT symseg = S_GET_SEGMENT (sym); | |
2343 | ||
2344 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2345 | { | |
2346 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2347 | linkonce = TRUE; | |
2348 | #ifdef OBJ_ELF | |
2349 | /* The GNU toolchain uses an extension for ELF: a section | |
2350 | beginning with the magic string .gnu.linkonce is a | |
2351 | linkonce section. */ | |
2352 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2353 | sizeof ".gnu.linkonce" - 1) == 0) | |
2354 | linkonce = TRUE; | |
2355 | #endif | |
2356 | } | |
2357 | return linkonce; | |
2358 | } | |
2359 | ||
252b5132 RH |
2360 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2361 | handle them specially, such as generating jalx instructions when | |
2362 | needed. We also make them odd for the duration of the assembly, in | |
2363 | order to generate the right sort of code. We will make them even | |
2364 | in the adjust_symtab routine, while leaving them marked. This is | |
2365 | convenient for the debugger and the disassembler. The linker knows | |
2366 | to make them odd again. */ | |
2367 | ||
2368 | static void | |
17a2f251 | 2369 | mips16_mark_labels (void) |
252b5132 | 2370 | { |
a8dbcb85 TS |
2371 | segment_info_type *si = seg_info (now_seg); |
2372 | struct insn_label_list *l; | |
252b5132 | 2373 | |
a8dbcb85 TS |
2374 | if (!mips_opts.mips16) |
2375 | return; | |
2376 | ||
2377 | for (l = si->label_list; l != NULL; l = l->next) | |
2378 | { | |
2379 | symbolS *label = l->label; | |
2380 | ||
2381 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2382 | if (IS_ELF) |
30c09090 | 2383 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2384 | #endif |
5f0fe04b TS |
2385 | if ((S_GET_VALUE (label) & 1) == 0 |
2386 | /* Don't adjust the address if the label is global or weak, or | |
2387 | in a link-once section, since we'll be emitting symbol reloc | |
2388 | references to it which will be patched up by the linker, and | |
2389 | the final value of the symbol may or may not be MIPS16. */ | |
2390 | && ! S_IS_WEAK (label) | |
2391 | && ! S_IS_EXTERNAL (label) | |
2392 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2393 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2394 | } |
2395 | } | |
2396 | ||
4d7206a2 RS |
2397 | /* End the current frag. Make it a variant frag and record the |
2398 | relaxation info. */ | |
2399 | ||
2400 | static void | |
2401 | relax_close_frag (void) | |
2402 | { | |
584892a6 | 2403 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2404 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2405 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2406 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2407 | ||
2408 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2409 | mips_relax.first_fixup = 0; | |
2410 | } | |
2411 | ||
2412 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2413 | See the comment above RELAX_ENCODE for more details. */ | |
2414 | ||
2415 | static void | |
2416 | relax_start (symbolS *symbol) | |
2417 | { | |
9c2799c2 | 2418 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2419 | mips_relax.sequence = 1; |
2420 | mips_relax.symbol = symbol; | |
2421 | } | |
2422 | ||
2423 | /* Start generating the second version of a relaxable sequence. | |
2424 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2425 | |
2426 | static void | |
4d7206a2 RS |
2427 | relax_switch (void) |
2428 | { | |
9c2799c2 | 2429 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2430 | mips_relax.sequence = 2; |
2431 | } | |
2432 | ||
2433 | /* End the current relaxable sequence. */ | |
2434 | ||
2435 | static void | |
2436 | relax_end (void) | |
2437 | { | |
9c2799c2 | 2438 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2439 | relax_close_frag (); |
2440 | mips_relax.sequence = 0; | |
2441 | } | |
2442 | ||
71400594 RS |
2443 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2444 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2445 | by VR4120 errata. */ | |
4d7206a2 | 2446 | |
71400594 RS |
2447 | static unsigned int |
2448 | classify_vr4120_insn (const char *name) | |
252b5132 | 2449 | { |
71400594 RS |
2450 | if (strncmp (name, "macc", 4) == 0) |
2451 | return FIX_VR4120_MACC; | |
2452 | if (strncmp (name, "dmacc", 5) == 0) | |
2453 | return FIX_VR4120_DMACC; | |
2454 | if (strncmp (name, "mult", 4) == 0) | |
2455 | return FIX_VR4120_MULT; | |
2456 | if (strncmp (name, "dmult", 5) == 0) | |
2457 | return FIX_VR4120_DMULT; | |
2458 | if (strstr (name, "div")) | |
2459 | return FIX_VR4120_DIV; | |
2460 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2461 | return FIX_VR4120_MTHILO; | |
2462 | return NUM_FIX_VR4120_CLASSES; | |
2463 | } | |
252b5132 | 2464 | |
ff239038 CM |
2465 | #define INSN_ERET 0x42000018 |
2466 | #define INSN_DERET 0x4200001f | |
2467 | ||
71400594 RS |
2468 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2469 | where INSN1 is the earlier instruction. Return the worst-case value | |
2470 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2471 | |
71400594 RS |
2472 | static unsigned int |
2473 | insns_between (const struct mips_cl_insn *insn1, | |
2474 | const struct mips_cl_insn *insn2) | |
2475 | { | |
2476 | unsigned long pinfo1, pinfo2; | |
2477 | ||
2478 | /* This function needs to know which pinfo flags are set for INSN2 | |
2479 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2480 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2481 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2482 | pinfo1 = insn1->insn_mo->pinfo; | |
2483 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2484 | |
71400594 RS |
2485 | #define INSN2_USES_REG(REG, CLASS) \ |
2486 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2487 | ||
2488 | /* For most targets, write-after-read dependencies on the HI and LO | |
2489 | registers must be separated by at least two instructions. */ | |
2490 | if (!hilo_interlocks) | |
252b5132 | 2491 | { |
71400594 RS |
2492 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2493 | return 2; | |
2494 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2495 | return 2; | |
2496 | } | |
2497 | ||
2498 | /* If we're working around r7000 errata, there must be two instructions | |
2499 | between an mfhi or mflo and any instruction that uses the result. */ | |
2500 | if (mips_7000_hilo_fix | |
2501 | && MF_HILO_INSN (pinfo1) | |
2502 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2503 | return 2; | |
2504 | ||
ff239038 CM |
2505 | /* If we're working around 24K errata, one instruction is required |
2506 | if an ERET or DERET is followed by a branch instruction. */ | |
2507 | if (mips_fix_24k) | |
2508 | { | |
2509 | if (insn1->insn_opcode == INSN_ERET | |
2510 | || insn1->insn_opcode == INSN_DERET) | |
2511 | { | |
2512 | if (insn2 == NULL | |
2513 | || insn2->insn_opcode == INSN_ERET | |
2514 | || insn2->insn_opcode == INSN_DERET | |
2515 | || (insn2->insn_mo->pinfo | |
2516 | & (INSN_UNCOND_BRANCH_DELAY | |
2517 | | INSN_COND_BRANCH_DELAY | |
2518 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2519 | return 1; | |
2520 | } | |
2521 | } | |
2522 | ||
71400594 RS |
2523 | /* If working around VR4120 errata, check for combinations that need |
2524 | a single intervening instruction. */ | |
2525 | if (mips_fix_vr4120) | |
2526 | { | |
2527 | unsigned int class1, class2; | |
252b5132 | 2528 | |
71400594 RS |
2529 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2530 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2531 | { |
71400594 RS |
2532 | if (insn2 == NULL) |
2533 | return 1; | |
2534 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2535 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2536 | return 1; | |
252b5132 | 2537 | } |
71400594 RS |
2538 | } |
2539 | ||
2540 | if (!mips_opts.mips16) | |
2541 | { | |
2542 | /* Check for GPR or coprocessor load delays. All such delays | |
2543 | are on the RT register. */ | |
2544 | /* Itbl support may require additional care here. */ | |
2545 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2546 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2547 | { |
71400594 RS |
2548 | know (pinfo1 & INSN_WRITE_GPR_T); |
2549 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2550 | return 1; | |
2551 | } | |
2552 | ||
2553 | /* Check for generic coprocessor hazards. | |
2554 | ||
2555 | This case is not handled very well. There is no special | |
2556 | knowledge of CP0 handling, and the coprocessors other than | |
2557 | the floating point unit are not distinguished at all. */ | |
2558 | /* Itbl support may require additional care here. FIXME! | |
2559 | Need to modify this to include knowledge about | |
2560 | user specified delays! */ | |
2561 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2562 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2563 | { | |
2564 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2565 | register. There must be a one instruction delay before INSN2 | |
2566 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2567 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2568 | { |
71400594 RS |
2569 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2570 | return 1; | |
252b5132 | 2571 | } |
71400594 | 2572 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2573 | { |
71400594 RS |
2574 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2575 | return 1; | |
252b5132 RH |
2576 | } |
2577 | else | |
2578 | { | |
71400594 RS |
2579 | /* Read-after-write dependencies on the control registers |
2580 | require a two-instruction gap. */ | |
2581 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2582 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2583 | return 2; | |
2584 | ||
2585 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2586 | also a coprocessor instruction, assume there must be | |
2587 | a one instruction gap. */ | |
2588 | if (pinfo2 & INSN_COP) | |
2589 | return 1; | |
252b5132 RH |
2590 | } |
2591 | } | |
6b76fefe | 2592 | |
71400594 RS |
2593 | /* Check for read-after-write dependencies on the coprocessor |
2594 | control registers in cases where INSN1 does not need a general | |
2595 | coprocessor delay. This means that INSN1 is a floating point | |
2596 | comparison instruction. */ | |
2597 | /* Itbl support may require additional care here. */ | |
2598 | else if (!cop_interlocks | |
2599 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2600 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2601 | return 1; | |
2602 | } | |
6b76fefe | 2603 | |
71400594 | 2604 | #undef INSN2_USES_REG |
6b76fefe | 2605 | |
71400594 RS |
2606 | return 0; |
2607 | } | |
6b76fefe | 2608 | |
7d8e00cf RS |
2609 | /* Return the number of nops that would be needed to work around the |
2610 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2611 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2612 | ||
2613 | static int | |
2614 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2615 | const struct mips_cl_insn *insn) | |
2616 | { | |
2617 | int i, j, reg; | |
2618 | ||
2619 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2620 | are not affected by the errata. */ | |
2621 | if (insn != 0 | |
2622 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2623 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2624 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2625 | return 0; | |
2626 | ||
2627 | /* Search for the first MFLO or MFHI. */ | |
2628 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
65b02341 | 2629 | if (MF_HILO_INSN (history[i].insn_mo->pinfo)) |
7d8e00cf RS |
2630 | { |
2631 | /* Extract the destination register. */ | |
2632 | if (mips_opts.mips16) | |
2633 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2634 | else | |
2635 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2636 | ||
2637 | /* No nops are needed if INSN reads that register. */ | |
2638 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2639 | return 0; | |
2640 | ||
2641 | /* ...or if any of the intervening instructions do. */ | |
2642 | for (j = 0; j < i; j++) | |
2643 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2644 | return 0; | |
2645 | ||
2646 | return MAX_VR4130_NOPS - i; | |
2647 | } | |
2648 | return 0; | |
2649 | } | |
2650 | ||
71400594 RS |
2651 | /* Return the number of nops that would be needed if instruction INSN |
2652 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2653 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2654 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2655 | |
71400594 RS |
2656 | static int |
2657 | nops_for_insn (const struct mips_cl_insn *history, | |
2658 | const struct mips_cl_insn *insn) | |
2659 | { | |
2660 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2661 | |
71400594 | 2662 | nops = 0; |
7d8e00cf | 2663 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 RS |
2664 | { |
2665 | tmp_nops = insns_between (history + i, insn) - i; | |
2666 | if (tmp_nops > nops) | |
2667 | nops = tmp_nops; | |
2668 | } | |
7d8e00cf RS |
2669 | |
2670 | if (mips_fix_vr4130) | |
2671 | { | |
2672 | tmp_nops = nops_for_vr4130 (history, insn); | |
2673 | if (tmp_nops > nops) | |
2674 | nops = tmp_nops; | |
2675 | } | |
2676 | ||
71400594 RS |
2677 | return nops; |
2678 | } | |
252b5132 | 2679 | |
71400594 RS |
2680 | /* The variable arguments provide NUM_INSNS extra instructions that |
2681 | might be added to HISTORY. Return the largest number of nops that | |
2682 | would be needed after the extended sequence. */ | |
252b5132 | 2683 | |
71400594 RS |
2684 | static int |
2685 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2686 | { | |
2687 | va_list args; | |
2688 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2689 | struct mips_cl_insn *cursor; | |
2690 | int nops; | |
2691 | ||
2692 | va_start (args, history); | |
2693 | cursor = buffer + num_insns; | |
2694 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2695 | while (cursor > buffer) | |
2696 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2697 | ||
2698 | nops = nops_for_insn (buffer, NULL); | |
2699 | va_end (args); | |
2700 | return nops; | |
2701 | } | |
252b5132 | 2702 | |
71400594 RS |
2703 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2704 | worst-case delay for the branch target. */ | |
252b5132 | 2705 | |
71400594 RS |
2706 | static int |
2707 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2708 | const struct mips_cl_insn *insn) | |
2709 | { | |
2710 | int nops, tmp_nops; | |
60b63b72 | 2711 | |
71400594 RS |
2712 | nops = nops_for_insn (history, insn); |
2713 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2714 | | INSN_COND_BRANCH_DELAY | |
2715 | | INSN_COND_BRANCH_LIKELY)) | |
2716 | { | |
2717 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2718 | if (tmp_nops > nops) | |
2719 | nops = tmp_nops; | |
2720 | } | |
2721 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2722 | { | |
2723 | tmp_nops = nops_for_sequence (1, history, insn); | |
2724 | if (tmp_nops > nops) | |
2725 | nops = tmp_nops; | |
2726 | } | |
2727 | return nops; | |
2728 | } | |
2729 | ||
2730 | /* Output an instruction. IP is the instruction information. | |
2731 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2732 | RELOC_TYPE. */ | |
2733 | ||
2734 | static void | |
2735 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2736 | bfd_reloc_code_real_type *reloc_type) | |
2737 | { | |
3994f87e | 2738 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2739 | relax_stateT prev_insn_frag_type = 0; |
2740 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2741 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2742 | |
2743 | /* Mark instruction labels in mips16 mode. */ | |
2744 | mips16_mark_labels (); | |
2745 | ||
2746 | prev_pinfo = history[0].insn_mo->pinfo; | |
2747 | pinfo = ip->insn_mo->pinfo; | |
2748 | ||
2749 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2750 | { | |
2751 | /* There are a lot of optimizations we could do that we don't. | |
2752 | In particular, we do not, in general, reorder instructions. | |
2753 | If you use gcc with optimization, it will reorder | |
2754 | instructions and generally do much more optimization then we | |
2755 | do here; repeating all that work in the assembler would only | |
2756 | benefit hand written assembly code, and does not seem worth | |
2757 | it. */ | |
2758 | int nops = (mips_optimize == 0 | |
2759 | ? nops_for_insn (history, NULL) | |
2760 | : nops_for_insn_or_target (history, ip)); | |
2761 | if (nops > 0) | |
252b5132 RH |
2762 | { |
2763 | fragS *old_frag; | |
2764 | unsigned long old_frag_offset; | |
2765 | int i; | |
252b5132 RH |
2766 | |
2767 | old_frag = frag_now; | |
2768 | old_frag_offset = frag_now_fix (); | |
2769 | ||
2770 | for (i = 0; i < nops; i++) | |
2771 | emit_nop (); | |
2772 | ||
2773 | if (listing) | |
2774 | { | |
2775 | listing_prev_line (); | |
2776 | /* We may be at the start of a variant frag. In case we | |
2777 | are, make sure there is enough space for the frag | |
2778 | after the frags created by listing_prev_line. The | |
2779 | argument to frag_grow here must be at least as large | |
2780 | as the argument to all other calls to frag_grow in | |
2781 | this file. We don't have to worry about being in the | |
2782 | middle of a variant frag, because the variants insert | |
2783 | all needed nop instructions themselves. */ | |
2784 | frag_grow (40); | |
2785 | } | |
2786 | ||
404a8071 | 2787 | mips_move_labels (); |
252b5132 RH |
2788 | |
2789 | #ifndef NO_ECOFF_DEBUGGING | |
2790 | if (ECOFF_DEBUGGING) | |
2791 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2792 | #endif | |
2793 | } | |
71400594 RS |
2794 | } |
2795 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2796 | { | |
2797 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2798 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2799 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2800 | |
71400594 RS |
2801 | /* Enforce NOPS as a minimum. */ |
2802 | if (nops > prev_nop_frag_required) | |
2803 | prev_nop_frag_required = nops; | |
252b5132 | 2804 | |
71400594 RS |
2805 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2806 | { | |
2807 | /* Settle for the current number of nops. Update the history | |
2808 | accordingly (for the benefit of any future .set reorder code). */ | |
2809 | prev_nop_frag = NULL; | |
2810 | insert_into_history (prev_nop_frag_since, | |
2811 | prev_nop_frag_holds, NOP_INSN); | |
2812 | } | |
2813 | else | |
2814 | { | |
2815 | /* Allow this instruction to replace one of the nops that was | |
2816 | tentatively added to prev_nop_frag. */ | |
2817 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2818 | prev_nop_frag_holds--; | |
2819 | prev_nop_frag_since++; | |
252b5132 RH |
2820 | } |
2821 | } | |
2822 | ||
58e2ea4d MR |
2823 | #ifdef OBJ_ELF |
2824 | /* The value passed to dwarf2_emit_insn is the distance between | |
2825 | the beginning of the current instruction and the address that | |
2826 | should be recorded in the debug tables. For MIPS16 debug info | |
2827 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2828 | address higher by one than the current. */ | |
2829 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2830 | #endif | |
2831 | ||
895921c9 | 2832 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2833 | if (history[0].frag) |
2834 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2835 | |
4d7206a2 | 2836 | if (address_expr |
0b25d3e6 | 2837 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2838 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2839 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2840 | && mips_relax_branch | |
2841 | /* Don't try branch relaxation within .set nomacro, or within | |
2842 | .set noat if we use $at for PIC computations. If it turns | |
2843 | out that the branch was out-of-range, we'll get an error. */ | |
2844 | && !mips_opts.warn_about_macros | |
741fe287 | 2845 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2846 | && !mips_opts.mips16) |
2847 | { | |
895921c9 | 2848 | relaxed_branch = TRUE; |
1e915849 RS |
2849 | add_relaxed_insn (ip, (relaxed_branch_length |
2850 | (NULL, NULL, | |
2851 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2852 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2853 | : 0)), 4, | |
2854 | RELAX_BRANCH_ENCODE | |
2855 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2856 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2857 | pinfo & INSN_WRITE_GPR_31, | |
2858 | 0), | |
2859 | address_expr->X_add_symbol, | |
2860 | address_expr->X_add_number); | |
4a6a3df4 AO |
2861 | *reloc_type = BFD_RELOC_UNUSED; |
2862 | } | |
2863 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2864 | { |
2865 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2866 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2867 | add_relaxed_insn (ip, 4, 0, |
2868 | RELAX_MIPS16_ENCODE | |
2869 | (*reloc_type - BFD_RELOC_UNUSED, | |
2870 | mips16_small, mips16_ext, | |
2871 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2872 | history[0].mips16_absolute_jump_p), | |
2873 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2874 | } |
252b5132 RH |
2875 | else if (mips_opts.mips16 |
2876 | && ! ip->use_extend | |
f6688943 | 2877 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2878 | { |
b8ee1a6e DU |
2879 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2880 | /* Make sure there is enough room to swap this instruction with | |
2881 | a following jump instruction. */ | |
2882 | frag_grow (6); | |
1e915849 | 2883 | add_fixed_insn (ip); |
252b5132 RH |
2884 | } |
2885 | else | |
2886 | { | |
2887 | if (mips_opts.mips16 | |
2888 | && mips_opts.noreorder | |
2889 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2890 | as_warn (_("extended instruction in delay slot")); | |
2891 | ||
4d7206a2 RS |
2892 | if (mips_relax.sequence) |
2893 | { | |
2894 | /* If we've reached the end of this frag, turn it into a variant | |
2895 | frag and record the information for the instructions we've | |
2896 | written so far. */ | |
2897 | if (frag_room () < 4) | |
2898 | relax_close_frag (); | |
2899 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2900 | } | |
2901 | ||
584892a6 RS |
2902 | if (mips_relax.sequence != 2) |
2903 | mips_macro_warning.sizes[0] += 4; | |
2904 | if (mips_relax.sequence != 1) | |
2905 | mips_macro_warning.sizes[1] += 4; | |
2906 | ||
1e915849 RS |
2907 | if (mips_opts.mips16) |
2908 | { | |
2909 | ip->fixed_p = 1; | |
2910 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2911 | } | |
2912 | add_fixed_insn (ip); | |
252b5132 RH |
2913 | } |
2914 | ||
01a3f561 | 2915 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2916 | { |
2917 | if (address_expr->X_op == O_constant) | |
2918 | { | |
f17c130b | 2919 | unsigned int tmp; |
f6688943 TS |
2920 | |
2921 | switch (*reloc_type) | |
252b5132 RH |
2922 | { |
2923 | case BFD_RELOC_32: | |
2924 | ip->insn_opcode |= address_expr->X_add_number; | |
2925 | break; | |
2926 | ||
f6688943 | 2927 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2928 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2929 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2930 | break; |
2931 | ||
2932 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2933 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2934 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2935 | break; |
2936 | ||
2937 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2938 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2939 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2940 | break; |
2941 | ||
2942 | case BFD_RELOC_HI16: | |
2943 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2944 | break; | |
2945 | ||
01a3f561 | 2946 | case BFD_RELOC_UNUSED: |
252b5132 | 2947 | case BFD_RELOC_LO16: |
ed6fb7bd | 2948 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2949 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2950 | break; | |
2951 | ||
2952 | case BFD_RELOC_MIPS_JMP: | |
2953 | if ((address_expr->X_add_number & 3) != 0) | |
2954 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2955 | (unsigned long) address_expr->X_add_number); | |
2956 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2957 | break; | |
2958 | ||
2959 | case BFD_RELOC_MIPS16_JMP: | |
2960 | if ((address_expr->X_add_number & 3) != 0) | |
2961 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2962 | (unsigned long) address_expr->X_add_number); | |
2963 | ip->insn_opcode |= | |
2964 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2965 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2966 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2967 | break; | |
2968 | ||
252b5132 | 2969 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2970 | if ((address_expr->X_add_number & 3) != 0) |
2971 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2972 | (unsigned long) address_expr->X_add_number); | |
2973 | if (mips_relax_branch) | |
2974 | goto need_reloc; | |
2975 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2976 | as_bad (_("branch address range overflow (0x%lx)"), | |
2977 | (unsigned long) address_expr->X_add_number); | |
2978 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2979 | break; | |
252b5132 RH |
2980 | |
2981 | default: | |
2982 | internalError (); | |
2983 | } | |
2984 | } | |
01a3f561 | 2985 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2986 | need_reloc: |
4d7206a2 RS |
2987 | { |
2988 | reloc_howto_type *howto; | |
2989 | int i; | |
34ce925e | 2990 | |
4d7206a2 RS |
2991 | /* In a compound relocation, it is the final (outermost) |
2992 | operator that determines the relocated field. */ | |
2993 | for (i = 1; i < 3; i++) | |
2994 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2995 | break; | |
34ce925e | 2996 | |
4d7206a2 | 2997 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
2998 | if (howto == NULL) |
2999 | { | |
3000 | /* To reproduce this failure try assembling gas/testsuites/ | |
3001 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3002 | assembler. */ | |
3003 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3004 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3005 | } | |
3006 | ||
1e915849 RS |
3007 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3008 | bfd_get_reloc_size (howto), | |
3009 | address_expr, | |
3010 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3011 | reloc_type[0]); | |
4d7206a2 | 3012 | |
b314ec0e RS |
3013 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3014 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3015 | && ip->fixp[0]->fx_addsy) | |
3016 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3017 | ||
4d7206a2 RS |
3018 | /* These relocations can have an addend that won't fit in |
3019 | 4 octets for 64bit assembly. */ | |
3020 | if (HAVE_64BIT_GPRS | |
3021 | && ! howto->partial_inplace | |
3022 | && (reloc_type[0] == BFD_RELOC_16 | |
3023 | || reloc_type[0] == BFD_RELOC_32 | |
3024 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3025 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3026 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3027 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3028 | || reloc_type[0] == BFD_RELOC_64 | |
3029 | || reloc_type[0] == BFD_RELOC_CTOR | |
3030 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3031 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3032 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3033 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3034 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3035 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3036 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3037 | || hi16_reloc_p (reloc_type[0]) |
3038 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3039 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3040 | |
3041 | if (mips_relax.sequence) | |
3042 | { | |
3043 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3044 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3045 | } |
3046 | else if (reloc_needs_lo_p (*reloc_type)) | |
3047 | { | |
3048 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3049 | |
4d7206a2 RS |
3050 | /* Reuse the last entry if it already has a matching %lo. */ |
3051 | hi_fixup = mips_hi_fixup_list; | |
3052 | if (hi_fixup == 0 | |
3053 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3054 | { | |
3055 | hi_fixup = ((struct mips_hi_fixup *) | |
3056 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3057 | hi_fixup->next = mips_hi_fixup_list; | |
3058 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3059 | } |
1e915849 | 3060 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3061 | hi_fixup->seg = now_seg; |
3062 | } | |
f6688943 | 3063 | |
4d7206a2 RS |
3064 | /* Add fixups for the second and third relocations, if given. |
3065 | Note that the ABI allows the second relocation to be | |
3066 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3067 | moment we only use RSS_UNDEF, but we could add support | |
3068 | for the others if it ever becomes necessary. */ | |
3069 | for (i = 1; i < 3; i++) | |
3070 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3071 | { | |
1e915849 RS |
3072 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3073 | ip->fixp[0]->fx_size, NULL, 0, | |
3074 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3075 | |
3076 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3077 | ip->fixp[0]->fx_tcbit = 1; |
3078 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3079 | } |
252b5132 RH |
3080 | } |
3081 | } | |
1e915849 | 3082 | install_insn (ip); |
252b5132 RH |
3083 | |
3084 | /* Update the register mask information. */ | |
3085 | if (! mips_opts.mips16) | |
3086 | { | |
3087 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3088 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3089 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3090 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3091 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3092 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3093 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3094 | mips_gprmask |= 1 << RA; |
252b5132 | 3095 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3096 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3097 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3098 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3099 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3100 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3101 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3102 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
3103 | if (pinfo & INSN_COP) |
3104 | { | |
bdaaa2e1 KH |
3105 | /* We don't keep enough information to sort these cases out. |
3106 | The itbl support does keep this information however, although | |
3107 | we currently don't support itbl fprmats as part of the cop | |
3108 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3109 | } |
3110 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3111 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3112 | } |
3113 | else | |
3114 | { | |
3115 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3116 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3117 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3118 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3119 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3120 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3121 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3122 | mips_gprmask |= 1 << TREG; | |
3123 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3124 | mips_gprmask |= 1 << SP; | |
3125 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3126 | mips_gprmask |= 1 << RA; | |
3127 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3128 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3129 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3130 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3131 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3132 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3133 | } |
3134 | ||
4d7206a2 | 3135 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3136 | { |
3137 | /* Filling the branch delay slot is more complex. We try to | |
3138 | switch the branch with the previous instruction, which we can | |
3139 | do if the previous instruction does not set up a condition | |
3140 | that the branch tests and if the branch is not itself the | |
3141 | target of any branch. */ | |
3142 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3143 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3144 | { | |
3145 | if (mips_optimize < 2 | |
3146 | /* If we have seen .set volatile or .set nomove, don't | |
3147 | optimize. */ | |
3148 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3149 | /* We can't swap if the previous instruction's position |
3150 | is fixed. */ | |
3151 | || history[0].fixed_p | |
252b5132 RH |
3152 | /* If the previous previous insn was in a .set |
3153 | noreorder, we can't swap. Actually, the MIPS | |
3154 | assembler will swap in this situation. However, gcc | |
3155 | configured -with-gnu-as will generate code like | |
3156 | .set noreorder | |
3157 | lw $4,XXX | |
3158 | .set reorder | |
3159 | INSN | |
3160 | bne $4,$0,foo | |
3161 | in which we can not swap the bne and INSN. If gcc is | |
3162 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3163 | .set pseudo-ops. */ |
47e39b9d | 3164 | || history[1].noreorder_p |
252b5132 RH |
3165 | /* If the branch is itself the target of a branch, we |
3166 | can not swap. We cheat on this; all we check for is | |
3167 | whether there is a label on this instruction. If | |
3168 | there are any branches to anything other than a | |
3169 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3170 | || si->label_list != NULL |
895921c9 MR |
3171 | /* If the previous instruction is in a variant frag |
3172 | other than this branch's one, we cannot do the swap. | |
3173 | This does not apply to the mips16, which uses variant | |
3174 | frags for different purposes. */ | |
252b5132 | 3175 | || (! mips_opts.mips16 |
895921c9 | 3176 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3177 | /* Check for conflicts between the branch and the instructions |
3178 | before the candidate delay slot. */ | |
3179 | || nops_for_insn (history + 1, ip) > 0 | |
3180 | /* Check for conflicts between the swapped sequence and the | |
3181 | target of the branch. */ | |
3182 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3183 | /* We do not swap with a trap instruction, since it |
3184 | complicates trap handlers to have the trap | |
3185 | instruction be in a delay slot. */ | |
3186 | || (prev_pinfo & INSN_TRAP) | |
3187 | /* If the branch reads a register that the previous | |
3188 | instruction sets, we can not swap. */ | |
3189 | || (! mips_opts.mips16 | |
3190 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3191 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3192 | MIPS_GR_REG)) |
3193 | || (! mips_opts.mips16 | |
3194 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3195 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3196 | MIPS_GR_REG)) |
3197 | || (mips_opts.mips16 | |
3198 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3199 | && (insn_uses_reg |
3200 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3201 | MIPS16_REG))) | |
252b5132 | 3202 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3203 | && (insn_uses_reg |
3204 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3205 | MIPS16_REG))) | |
252b5132 | 3206 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3207 | && (insn_uses_reg |
3208 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3209 | MIPS16_REG))) | |
252b5132 RH |
3210 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3211 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3212 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3213 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3214 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3215 | && insn_uses_reg (ip, | |
47e39b9d RS |
3216 | MIPS16OP_EXTRACT_REG32R |
3217 | (history[0].insn_opcode), | |
252b5132 RH |
3218 | MIPS_GR_REG)))) |
3219 | /* If the branch writes a register that the previous | |
3220 | instruction sets, we can not swap (we know that | |
3221 | branches write only to RD or to $31). */ | |
3222 | || (! mips_opts.mips16 | |
3223 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3224 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3225 | && (EXTRACT_OPERAND (RT, history[0]) |
3226 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3227 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3228 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3229 | || (! mips_opts.mips16 |
3230 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3231 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3232 | && (EXTRACT_OPERAND (RD, history[0]) |
3233 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3234 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3235 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3236 | || (mips_opts.mips16 |
3237 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3238 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3239 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3240 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3241 | == RA)))) |
3242 | /* If the branch writes a register that the previous | |
3243 | instruction reads, we can not swap (we know that | |
3244 | branches only write to RD or to $31). */ | |
3245 | || (! mips_opts.mips16 | |
3246 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3247 | && insn_uses_reg (&history[0], |
bf12938e | 3248 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3249 | MIPS_GR_REG)) |
3250 | || (! mips_opts.mips16 | |
3251 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3252 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3253 | || (mips_opts.mips16 |
3254 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3255 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3256 | /* If one instruction sets a condition code and the |
3257 | other one uses a condition code, we can not swap. */ | |
3258 | || ((pinfo & INSN_READ_COND_CODE) | |
3259 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3260 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3261 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3262 | /* If the previous instruction uses the PC, we can not | |
3263 | swap. */ | |
3264 | || (mips_opts.mips16 | |
3265 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3266 | /* If the previous instruction had a fixup in mips16 |
3267 | mode, we can not swap. This normally means that the | |
3268 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3269 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3270 | /* If the previous instruction is a sync, sync.l, or |
3271 | sync.p, we can not swap. */ | |
6a32d874 CM |
3272 | || (prev_pinfo & INSN_SYNC) |
3273 | /* If the previous instruction is an ERET or | |
3274 | DERET, avoid the swap. */ | |
3275 | || (history[0].insn_opcode == INSN_ERET) | |
3276 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3277 | { |
29024861 DU |
3278 | if (mips_opts.mips16 |
3279 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3280 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3281 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3282 | { |
3283 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3284 | ip->insn_opcode |= 0x0080; | |
3285 | install_insn (ip); | |
3286 | insert_into_history (0, 1, ip); | |
3287 | } | |
3288 | else | |
3289 | { | |
3290 | /* We could do even better for unconditional branches to | |
3291 | portions of this object file; we could pick up the | |
3292 | instruction at the destination, put it in the delay | |
3293 | slot, and bump the destination address. */ | |
3294 | insert_into_history (0, 1, ip); | |
3295 | emit_nop (); | |
3296 | } | |
3297 | ||
dd22970f ILT |
3298 | if (mips_relax.sequence) |
3299 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3300 | } |
3301 | else | |
3302 | { | |
3303 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3304 | struct mips_cl_insn delay = history[0]; |
3305 | if (mips_opts.mips16) | |
252b5132 | 3306 | { |
b8ee1a6e DU |
3307 | know (delay.frag == ip->frag); |
3308 | move_insn (ip, delay.frag, delay.where); | |
3309 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3310 | } |
3311 | else if (relaxed_branch) | |
3312 | { | |
3313 | /* Add the delay slot instruction to the end of the | |
3314 | current frag and shrink the fixed part of the | |
3315 | original frag. If the branch occupies the tail of | |
3316 | the latter, move it backwards to cover the gap. */ | |
3317 | delay.frag->fr_fix -= 4; | |
3318 | if (delay.frag == ip->frag) | |
3319 | move_insn (ip, ip->frag, ip->where - 4); | |
3320 | add_fixed_insn (&delay); | |
252b5132 RH |
3321 | } |
3322 | else | |
3323 | { | |
1e915849 RS |
3324 | move_insn (&delay, ip->frag, ip->where); |
3325 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3326 | } |
1e915849 RS |
3327 | history[0] = *ip; |
3328 | delay.fixed_p = 1; | |
3329 | insert_into_history (0, 1, &delay); | |
252b5132 | 3330 | } |
252b5132 RH |
3331 | |
3332 | /* If that was an unconditional branch, forget the previous | |
3333 | insn information. */ | |
3334 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3335 | { |
6a32d874 CM |
3336 | mips_no_prev_insn (); |
3337 | } | |
252b5132 RH |
3338 | } |
3339 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3340 | { | |
3341 | /* We don't yet optimize a branch likely. What we should do | |
3342 | is look at the target, copy the instruction found there | |
3343 | into the delay slot, and increment the branch to jump to | |
3344 | the next instruction. */ | |
1e915849 | 3345 | insert_into_history (0, 1, ip); |
252b5132 | 3346 | emit_nop (); |
252b5132 RH |
3347 | } |
3348 | else | |
1e915849 | 3349 | insert_into_history (0, 1, ip); |
252b5132 | 3350 | } |
1e915849 RS |
3351 | else |
3352 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3353 | |
3354 | /* We just output an insn, so the next one doesn't have a label. */ | |
3355 | mips_clear_insn_labels (); | |
252b5132 RH |
3356 | } |
3357 | ||
7d10b47d | 3358 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3359 | |
3360 | static void | |
7d10b47d | 3361 | mips_no_prev_insn (void) |
252b5132 | 3362 | { |
7d10b47d RS |
3363 | prev_nop_frag = NULL; |
3364 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3365 | mips_clear_insn_labels (); |
3366 | } | |
3367 | ||
7d10b47d RS |
3368 | /* This function must be called before we emit something other than |
3369 | instructions. It is like mips_no_prev_insn except that it inserts | |
3370 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3371 | |
7d10b47d RS |
3372 | void |
3373 | mips_emit_delays (void) | |
252b5132 RH |
3374 | { |
3375 | if (! mips_opts.noreorder) | |
3376 | { | |
71400594 | 3377 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3378 | if (nops > 0) |
3379 | { | |
7d10b47d RS |
3380 | while (nops-- > 0) |
3381 | add_fixed_insn (NOP_INSN); | |
3382 | mips_move_labels (); | |
3383 | } | |
3384 | } | |
3385 | mips_no_prev_insn (); | |
3386 | } | |
3387 | ||
3388 | /* Start a (possibly nested) noreorder block. */ | |
3389 | ||
3390 | static void | |
3391 | start_noreorder (void) | |
3392 | { | |
3393 | if (mips_opts.noreorder == 0) | |
3394 | { | |
3395 | unsigned int i; | |
3396 | int nops; | |
3397 | ||
3398 | /* None of the instructions before the .set noreorder can be moved. */ | |
3399 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3400 | history[i].fixed_p = 1; | |
3401 | ||
3402 | /* Insert any nops that might be needed between the .set noreorder | |
3403 | block and the previous instructions. We will later remove any | |
3404 | nops that turn out not to be needed. */ | |
3405 | nops = nops_for_insn (history, NULL); | |
3406 | if (nops > 0) | |
3407 | { | |
3408 | if (mips_optimize != 0) | |
252b5132 RH |
3409 | { |
3410 | /* Record the frag which holds the nop instructions, so | |
3411 | that we can remove them if we don't need them. */ | |
3412 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3413 | prev_nop_frag = frag_now; | |
3414 | prev_nop_frag_holds = nops; | |
3415 | prev_nop_frag_required = 0; | |
3416 | prev_nop_frag_since = 0; | |
3417 | } | |
3418 | ||
3419 | for (; nops > 0; --nops) | |
1e915849 | 3420 | add_fixed_insn (NOP_INSN); |
252b5132 | 3421 | |
7d10b47d RS |
3422 | /* Move on to a new frag, so that it is safe to simply |
3423 | decrease the size of prev_nop_frag. */ | |
3424 | frag_wane (frag_now); | |
3425 | frag_new (0); | |
404a8071 | 3426 | mips_move_labels (); |
252b5132 | 3427 | } |
7d10b47d RS |
3428 | mips16_mark_labels (); |
3429 | mips_clear_insn_labels (); | |
252b5132 | 3430 | } |
7d10b47d RS |
3431 | mips_opts.noreorder++; |
3432 | mips_any_noreorder = 1; | |
3433 | } | |
252b5132 | 3434 | |
7d10b47d | 3435 | /* End a nested noreorder block. */ |
252b5132 | 3436 | |
7d10b47d RS |
3437 | static void |
3438 | end_noreorder (void) | |
3439 | { | |
6a32d874 | 3440 | |
7d10b47d RS |
3441 | mips_opts.noreorder--; |
3442 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3443 | { | |
3444 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3445 | handling nop insertion the .set reorder way. */ | |
3446 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3447 | * (mips_opts.mips16 ? 2 : 4)); | |
3448 | insert_into_history (prev_nop_frag_since, | |
3449 | prev_nop_frag_required, NOP_INSN); | |
3450 | prev_nop_frag = NULL; | |
3451 | } | |
252b5132 RH |
3452 | } |
3453 | ||
584892a6 RS |
3454 | /* Set up global variables for the start of a new macro. */ |
3455 | ||
3456 | static void | |
3457 | macro_start (void) | |
3458 | { | |
3459 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3460 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3461 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3462 | & (INSN_UNCOND_BRANCH_DELAY |
3463 | | INSN_COND_BRANCH_DELAY | |
3464 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3465 | } | |
3466 | ||
3467 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3468 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3469 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3470 | ||
3471 | static const char * | |
3472 | macro_warning (relax_substateT subtype) | |
3473 | { | |
3474 | if (subtype & RELAX_DELAY_SLOT) | |
3475 | return _("Macro instruction expanded into multiple instructions" | |
3476 | " in a branch delay slot"); | |
3477 | else if (subtype & RELAX_NOMACRO) | |
3478 | return _("Macro instruction expanded into multiple instructions"); | |
3479 | else | |
3480 | return 0; | |
3481 | } | |
3482 | ||
3483 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3484 | ||
3485 | static void | |
3486 | macro_end (void) | |
3487 | { | |
3488 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3489 | { | |
3490 | relax_substateT subtype; | |
3491 | ||
3492 | /* Set up the relaxation warning flags. */ | |
3493 | subtype = 0; | |
3494 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3495 | subtype |= RELAX_SECOND_LONGER; | |
3496 | if (mips_opts.warn_about_macros) | |
3497 | subtype |= RELAX_NOMACRO; | |
3498 | if (mips_macro_warning.delay_slot_p) | |
3499 | subtype |= RELAX_DELAY_SLOT; | |
3500 | ||
3501 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3502 | { | |
3503 | /* Either the macro has a single implementation or both | |
3504 | implementations are longer than 4 bytes. Emit the | |
3505 | warning now. */ | |
3506 | const char *msg = macro_warning (subtype); | |
3507 | if (msg != 0) | |
520725ea | 3508 | as_warn ("%s", msg); |
584892a6 RS |
3509 | } |
3510 | else | |
3511 | { | |
3512 | /* One implementation might need a warning but the other | |
3513 | definitely doesn't. */ | |
3514 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3515 | } | |
3516 | } | |
3517 | } | |
3518 | ||
6e1304d8 RS |
3519 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3520 | The first argument in *ARGS will be either the code for a single | |
3521 | relocation or -1 followed by the three codes that make up a | |
3522 | composite relocation. */ | |
3523 | ||
3524 | static void | |
3525 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3526 | { | |
3527 | int i, next; | |
3528 | ||
3529 | next = va_arg (*args, int); | |
3530 | if (next >= 0) | |
3531 | r[0] = (bfd_reloc_code_real_type) next; | |
3532 | else | |
3533 | for (i = 0; i < 3; i++) | |
3534 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3535 | } | |
3536 | ||
252b5132 RH |
3537 | /* Build an instruction created by a macro expansion. This is passed |
3538 | a pointer to the count of instructions created so far, an | |
3539 | expression, the name of the instruction to build, an operand format | |
3540 | string, and corresponding arguments. */ | |
3541 | ||
252b5132 | 3542 | static void |
67c0d1eb | 3543 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3544 | { |
1e915849 | 3545 | const struct mips_opcode *mo; |
252b5132 | 3546 | struct mips_cl_insn insn; |
f6688943 | 3547 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3548 | va_list args; |
252b5132 | 3549 | |
252b5132 | 3550 | va_start (args, fmt); |
252b5132 | 3551 | |
252b5132 RH |
3552 | if (mips_opts.mips16) |
3553 | { | |
67c0d1eb | 3554 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3555 | va_end (args); |
3556 | return; | |
3557 | } | |
3558 | ||
f6688943 TS |
3559 | r[0] = BFD_RELOC_UNUSED; |
3560 | r[1] = BFD_RELOC_UNUSED; | |
3561 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3562 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3563 | gas_assert (mo); |
3564 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3565 | |
8b082fb1 TS |
3566 | while (1) |
3567 | { | |
3568 | /* Search until we get a match for NAME. It is assumed here that | |
3569 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3570 | if (strcmp (fmt, mo->args) == 0 | |
3571 | && mo->pinfo != INSN_MACRO | |
037b32b9 | 3572 | && is_opcode_valid (mo, TRUE)) |
8b082fb1 TS |
3573 | break; |
3574 | ||
1e915849 | 3575 | ++mo; |
9c2799c2 NC |
3576 | gas_assert (mo->name); |
3577 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3578 | } |
3579 | ||
1e915849 | 3580 | create_insn (&insn, mo); |
252b5132 RH |
3581 | for (;;) |
3582 | { | |
3583 | switch (*fmt++) | |
3584 | { | |
3585 | case '\0': | |
3586 | break; | |
3587 | ||
3588 | case ',': | |
3589 | case '(': | |
3590 | case ')': | |
3591 | continue; | |
3592 | ||
5f74bc13 CD |
3593 | case '+': |
3594 | switch (*fmt++) | |
3595 | { | |
3596 | case 'A': | |
3597 | case 'E': | |
bf12938e | 3598 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3599 | continue; |
3600 | ||
3601 | case 'B': | |
3602 | case 'F': | |
3603 | /* Note that in the macro case, these arguments are already | |
3604 | in MSB form. (When handling the instruction in the | |
3605 | non-macro case, these arguments are sizes from which | |
3606 | MSB values must be calculated.) */ | |
bf12938e | 3607 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3608 | continue; |
3609 | ||
3610 | case 'C': | |
3611 | case 'G': | |
3612 | case 'H': | |
3613 | /* Note that in the macro case, these arguments are already | |
3614 | in MSBD form. (When handling the instruction in the | |
3615 | non-macro case, these arguments are sizes from which | |
3616 | MSBD values must be calculated.) */ | |
bf12938e | 3617 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3618 | continue; |
3619 | ||
dd3cbb7e NC |
3620 | case 'Q': |
3621 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3622 | continue; | |
3623 | ||
5f74bc13 CD |
3624 | default: |
3625 | internalError (); | |
3626 | } | |
3627 | continue; | |
3628 | ||
8b082fb1 TS |
3629 | case '2': |
3630 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3631 | continue; | |
3632 | ||
252b5132 RH |
3633 | case 't': |
3634 | case 'w': | |
3635 | case 'E': | |
bf12938e | 3636 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3637 | continue; |
3638 | ||
3639 | case 'c': | |
bf12938e | 3640 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3641 | continue; |
3642 | ||
252b5132 RH |
3643 | case 'T': |
3644 | case 'W': | |
bf12938e | 3645 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3646 | continue; |
3647 | ||
3648 | case 'd': | |
3649 | case 'G': | |
af7ee8bf | 3650 | case 'K': |
bf12938e | 3651 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3652 | continue; |
3653 | ||
4372b673 NC |
3654 | case 'U': |
3655 | { | |
3656 | int tmp = va_arg (args, int); | |
3657 | ||
bf12938e RS |
3658 | INSERT_OPERAND (RT, insn, tmp); |
3659 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3660 | continue; |
4372b673 NC |
3661 | } |
3662 | ||
252b5132 RH |
3663 | case 'V': |
3664 | case 'S': | |
bf12938e | 3665 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3666 | continue; |
3667 | ||
3668 | case 'z': | |
3669 | continue; | |
3670 | ||
3671 | case '<': | |
bf12938e | 3672 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3673 | continue; |
3674 | ||
3675 | case 'D': | |
bf12938e | 3676 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3677 | continue; |
3678 | ||
3679 | case 'B': | |
bf12938e | 3680 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3681 | continue; |
3682 | ||
4372b673 | 3683 | case 'J': |
bf12938e | 3684 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3685 | continue; |
3686 | ||
252b5132 | 3687 | case 'q': |
bf12938e | 3688 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3689 | continue; |
3690 | ||
3691 | case 'b': | |
3692 | case 's': | |
3693 | case 'r': | |
3694 | case 'v': | |
bf12938e | 3695 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3696 | continue; |
3697 | ||
3698 | case 'i': | |
3699 | case 'j': | |
3700 | case 'o': | |
6e1304d8 | 3701 | macro_read_relocs (&args, r); |
9c2799c2 | 3702 | gas_assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3703 | || *r == BFD_RELOC_MIPS_LITERAL |
3704 | || *r == BFD_RELOC_MIPS_HIGHER | |
3705 | || *r == BFD_RELOC_HI16_S | |
3706 | || *r == BFD_RELOC_LO16 | |
3707 | || *r == BFD_RELOC_MIPS_GOT16 | |
3708 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3709 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3710 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3711 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3712 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3713 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3714 | continue; |
3715 | ||
3716 | case 'u': | |
6e1304d8 | 3717 | macro_read_relocs (&args, r); |
9c2799c2 | 3718 | gas_assert (ep != NULL |
252b5132 RH |
3719 | && (ep->X_op == O_constant |
3720 | || (ep->X_op == O_symbol | |
f6688943 TS |
3721 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3722 | || *r == BFD_RELOC_HI16_S | |
3723 | || *r == BFD_RELOC_HI16 | |
3724 | || *r == BFD_RELOC_GPREL16 | |
3725 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3726 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3727 | continue; |
3728 | ||
3729 | case 'p': | |
9c2799c2 | 3730 | gas_assert (ep != NULL); |
bad36eac | 3731 | |
252b5132 RH |
3732 | /* |
3733 | * This allows macro() to pass an immediate expression for | |
3734 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3735 | * |
3736 | * We don't allow branch relaxation for these branches, as | |
3737 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3738 | */ |
3739 | if (ep->X_op == O_constant) | |
3740 | { | |
bad36eac DJ |
3741 | if ((ep->X_add_number & 3) != 0) |
3742 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3743 | (unsigned long) ep->X_add_number); | |
3744 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3745 | as_bad (_("branch address range overflow (0x%lx)"), | |
3746 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3747 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3748 | ep = NULL; | |
3749 | } | |
3750 | else | |
0b25d3e6 | 3751 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3752 | continue; |
3753 | ||
3754 | case 'a': | |
9c2799c2 | 3755 | gas_assert (ep != NULL); |
f6688943 | 3756 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3757 | continue; |
3758 | ||
3759 | case 'C': | |
a9e24354 | 3760 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3761 | continue; |
3762 | ||
d43b4baf | 3763 | case 'k': |
a9e24354 | 3764 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3765 | continue; |
3766 | ||
252b5132 RH |
3767 | default: |
3768 | internalError (); | |
3769 | } | |
3770 | break; | |
3771 | } | |
3772 | va_end (args); | |
9c2799c2 | 3773 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3774 | |
4d7206a2 | 3775 | append_insn (&insn, ep, r); |
252b5132 RH |
3776 | } |
3777 | ||
3778 | static void | |
67c0d1eb | 3779 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3780 | va_list args) |
252b5132 | 3781 | { |
1e915849 | 3782 | struct mips_opcode *mo; |
252b5132 | 3783 | struct mips_cl_insn insn; |
f6688943 TS |
3784 | bfd_reloc_code_real_type r[3] |
3785 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3786 | |
1e915849 | 3787 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3788 | gas_assert (mo); |
3789 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3790 | |
1e915849 | 3791 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3792 | { |
1e915849 | 3793 | ++mo; |
9c2799c2 NC |
3794 | gas_assert (mo->name); |
3795 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3796 | } |
3797 | ||
1e915849 | 3798 | create_insn (&insn, mo); |
252b5132 RH |
3799 | for (;;) |
3800 | { | |
3801 | int c; | |
3802 | ||
3803 | c = *fmt++; | |
3804 | switch (c) | |
3805 | { | |
3806 | case '\0': | |
3807 | break; | |
3808 | ||
3809 | case ',': | |
3810 | case '(': | |
3811 | case ')': | |
3812 | continue; | |
3813 | ||
3814 | case 'y': | |
3815 | case 'w': | |
bf12938e | 3816 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3817 | continue; |
3818 | ||
3819 | case 'x': | |
3820 | case 'v': | |
bf12938e | 3821 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3822 | continue; |
3823 | ||
3824 | case 'z': | |
bf12938e | 3825 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3826 | continue; |
3827 | ||
3828 | case 'Z': | |
bf12938e | 3829 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3830 | continue; |
3831 | ||
3832 | case '0': | |
3833 | case 'S': | |
3834 | case 'P': | |
3835 | case 'R': | |
3836 | continue; | |
3837 | ||
3838 | case 'X': | |
bf12938e | 3839 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3840 | continue; |
3841 | ||
3842 | case 'Y': | |
3843 | { | |
3844 | int regno; | |
3845 | ||
3846 | regno = va_arg (args, int); | |
3847 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3848 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3849 | } |
3850 | continue; | |
3851 | ||
3852 | case '<': | |
3853 | case '>': | |
3854 | case '4': | |
3855 | case '5': | |
3856 | case 'H': | |
3857 | case 'W': | |
3858 | case 'D': | |
3859 | case 'j': | |
3860 | case '8': | |
3861 | case 'V': | |
3862 | case 'C': | |
3863 | case 'U': | |
3864 | case 'k': | |
3865 | case 'K': | |
3866 | case 'p': | |
3867 | case 'q': | |
3868 | { | |
9c2799c2 | 3869 | gas_assert (ep != NULL); |
252b5132 RH |
3870 | |
3871 | if (ep->X_op != O_constant) | |
874e8986 | 3872 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3873 | else |
3874 | { | |
b34976b6 AM |
3875 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3876 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3877 | &insn.extend); |
252b5132 | 3878 | ep = NULL; |
f6688943 | 3879 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3880 | } |
3881 | } | |
3882 | continue; | |
3883 | ||
3884 | case '6': | |
bf12938e | 3885 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3886 | continue; |
3887 | } | |
3888 | ||
3889 | break; | |
3890 | } | |
3891 | ||
9c2799c2 | 3892 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3893 | |
4d7206a2 | 3894 | append_insn (&insn, ep, r); |
252b5132 RH |
3895 | } |
3896 | ||
2051e8c4 MR |
3897 | /* |
3898 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3899 | * higher bits unset. | |
3900 | */ | |
9f872bbe | 3901 | static void |
2051e8c4 MR |
3902 | normalize_constant_expr (expressionS *ex) |
3903 | { | |
9ee2a2d4 | 3904 | if (ex->X_op == O_constant |
2051e8c4 MR |
3905 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3906 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3907 | - 0x80000000); | |
3908 | } | |
3909 | ||
3910 | /* | |
3911 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3912 | * all higher bits unset. | |
3913 | */ | |
3914 | static void | |
3915 | normalize_address_expr (expressionS *ex) | |
3916 | { | |
3917 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3918 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3919 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3920 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3921 | - 0x80000000); | |
3922 | } | |
3923 | ||
438c16b8 TS |
3924 | /* |
3925 | * Generate a "jalr" instruction with a relocation hint to the called | |
3926 | * function. This occurs in NewABI PIC code. | |
3927 | */ | |
3928 | static void | |
67c0d1eb | 3929 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3930 | { |
685736be | 3931 | char *f = NULL; |
b34976b6 | 3932 | |
b12dd2e4 | 3933 | if (MIPS_JALR_HINT_P) |
f21f8242 | 3934 | { |
cc3d92a5 | 3935 | frag_grow (8); |
f21f8242 AO |
3936 | f = frag_more (0); |
3937 | } | |
67c0d1eb | 3938 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
b12dd2e4 | 3939 | if (MIPS_JALR_HINT_P) |
f21f8242 | 3940 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3941 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3942 | } |
3943 | ||
252b5132 RH |
3944 | /* |
3945 | * Generate a "lui" instruction. | |
3946 | */ | |
3947 | static void | |
67c0d1eb | 3948 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3949 | { |
3950 | expressionS high_expr; | |
1e915849 | 3951 | const struct mips_opcode *mo; |
252b5132 | 3952 | struct mips_cl_insn insn; |
f6688943 TS |
3953 | bfd_reloc_code_real_type r[3] |
3954 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3955 | const char *name = "lui"; |
3956 | const char *fmt = "t,u"; | |
252b5132 | 3957 | |
9c2799c2 | 3958 | gas_assert (! mips_opts.mips16); |
252b5132 | 3959 | |
4d7206a2 | 3960 | high_expr = *ep; |
252b5132 RH |
3961 | |
3962 | if (high_expr.X_op == O_constant) | |
3963 | { | |
54f4ddb3 | 3964 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3965 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3966 | >> 16) & 0xffff; | |
f6688943 | 3967 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3968 | } |
78e1bb40 | 3969 | else |
252b5132 | 3970 | { |
9c2799c2 | 3971 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
3972 | /* _gp_disp is a special case, used from s_cpload. |
3973 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 3974 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 3975 | || (! HAVE_NEWABI |
aa6975fb ILT |
3976 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3977 | || (! mips_in_shared | |
bbe506e8 TS |
3978 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3979 | "__gnu_local_gp") == 0)); | |
f6688943 | 3980 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3981 | } |
3982 | ||
1e915849 | 3983 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
3984 | gas_assert (strcmp (name, mo->name) == 0); |
3985 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 3986 | create_insn (&insn, mo); |
252b5132 | 3987 | |
bf12938e RS |
3988 | insn.insn_opcode = insn.insn_mo->match; |
3989 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3990 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3991 | { |
3992 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3993 | append_insn (&insn, NULL, r); |
252b5132 RH |
3994 | } |
3995 | else | |
4d7206a2 | 3996 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3997 | } |
3998 | ||
885add95 CD |
3999 | /* Generate a sequence of instructions to do a load or store from a constant |
4000 | offset off of a base register (breg) into/from a target register (treg), | |
4001 | using AT if necessary. */ | |
4002 | static void | |
67c0d1eb RS |
4003 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4004 | int treg, int breg, int dbl) | |
885add95 | 4005 | { |
9c2799c2 | 4006 | gas_assert (ep->X_op == O_constant); |
885add95 | 4007 | |
256ab948 | 4008 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4009 | if (!dbl) |
4010 | normalize_constant_expr (ep); | |
256ab948 | 4011 | |
67c1ffbe | 4012 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4013 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4014 | as_warn (_("operand overflow")); |
4015 | ||
4016 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4017 | { | |
4018 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4019 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4020 | } |
4021 | else | |
4022 | { | |
4023 | /* 32-bit offset, need multiple instructions and AT, like: | |
4024 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4025 | addu $tempreg,$tempreg,$breg | |
4026 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4027 | to handle the complete offset. */ | |
67c0d1eb RS |
4028 | macro_build_lui (ep, AT); |
4029 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4030 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4031 | |
741fe287 | 4032 | if (!mips_opts.at) |
8fc2e39e | 4033 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4034 | } |
4035 | } | |
4036 | ||
252b5132 RH |
4037 | /* set_at() |
4038 | * Generates code to set the $at register to true (one) | |
4039 | * if reg is less than the immediate expression. | |
4040 | */ | |
4041 | static void | |
67c0d1eb | 4042 | set_at (int reg, int unsignedp) |
252b5132 RH |
4043 | { |
4044 | if (imm_expr.X_op == O_constant | |
4045 | && imm_expr.X_add_number >= -0x8000 | |
4046 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4047 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4048 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4049 | else |
4050 | { | |
67c0d1eb RS |
4051 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4052 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4053 | } |
4054 | } | |
4055 | ||
4056 | /* Warn if an expression is not a constant. */ | |
4057 | ||
4058 | static void | |
17a2f251 | 4059 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4060 | { |
4061 | if (ex->X_op == O_big) | |
4062 | as_bad (_("unsupported large constant")); | |
4063 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4064 | as_bad (_("Instruction %s requires absolute expression"), |
4065 | ip->insn_mo->name); | |
13757d0c | 4066 | |
9ee2a2d4 MR |
4067 | if (HAVE_32BIT_GPRS) |
4068 | normalize_constant_expr (ex); | |
252b5132 RH |
4069 | } |
4070 | ||
4071 | /* Count the leading zeroes by performing a binary chop. This is a | |
4072 | bulky bit of source, but performance is a LOT better for the | |
4073 | majority of values than a simple loop to count the bits: | |
4074 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4075 | if ((v) & (1 << (31 - lcnt))) | |
4076 | break; | |
4077 | However it is not code size friendly, and the gain will drop a bit | |
4078 | on certain cached systems. | |
4079 | */ | |
4080 | #define COUNT_TOP_ZEROES(v) \ | |
4081 | (((v) & ~0xffff) == 0 \ | |
4082 | ? ((v) & ~0xff) == 0 \ | |
4083 | ? ((v) & ~0xf) == 0 \ | |
4084 | ? ((v) & ~0x3) == 0 \ | |
4085 | ? ((v) & ~0x1) == 0 \ | |
4086 | ? !(v) \ | |
4087 | ? 32 \ | |
4088 | : 31 \ | |
4089 | : 30 \ | |
4090 | : ((v) & ~0x7) == 0 \ | |
4091 | ? 29 \ | |
4092 | : 28 \ | |
4093 | : ((v) & ~0x3f) == 0 \ | |
4094 | ? ((v) & ~0x1f) == 0 \ | |
4095 | ? 27 \ | |
4096 | : 26 \ | |
4097 | : ((v) & ~0x7f) == 0 \ | |
4098 | ? 25 \ | |
4099 | : 24 \ | |
4100 | : ((v) & ~0xfff) == 0 \ | |
4101 | ? ((v) & ~0x3ff) == 0 \ | |
4102 | ? ((v) & ~0x1ff) == 0 \ | |
4103 | ? 23 \ | |
4104 | : 22 \ | |
4105 | : ((v) & ~0x7ff) == 0 \ | |
4106 | ? 21 \ | |
4107 | : 20 \ | |
4108 | : ((v) & ~0x3fff) == 0 \ | |
4109 | ? ((v) & ~0x1fff) == 0 \ | |
4110 | ? 19 \ | |
4111 | : 18 \ | |
4112 | : ((v) & ~0x7fff) == 0 \ | |
4113 | ? 17 \ | |
4114 | : 16 \ | |
4115 | : ((v) & ~0xffffff) == 0 \ | |
4116 | ? ((v) & ~0xfffff) == 0 \ | |
4117 | ? ((v) & ~0x3ffff) == 0 \ | |
4118 | ? ((v) & ~0x1ffff) == 0 \ | |
4119 | ? 15 \ | |
4120 | : 14 \ | |
4121 | : ((v) & ~0x7ffff) == 0 \ | |
4122 | ? 13 \ | |
4123 | : 12 \ | |
4124 | : ((v) & ~0x3fffff) == 0 \ | |
4125 | ? ((v) & ~0x1fffff) == 0 \ | |
4126 | ? 11 \ | |
4127 | : 10 \ | |
4128 | : ((v) & ~0x7fffff) == 0 \ | |
4129 | ? 9 \ | |
4130 | : 8 \ | |
4131 | : ((v) & ~0xfffffff) == 0 \ | |
4132 | ? ((v) & ~0x3ffffff) == 0 \ | |
4133 | ? ((v) & ~0x1ffffff) == 0 \ | |
4134 | ? 7 \ | |
4135 | : 6 \ | |
4136 | : ((v) & ~0x7ffffff) == 0 \ | |
4137 | ? 5 \ | |
4138 | : 4 \ | |
4139 | : ((v) & ~0x3fffffff) == 0 \ | |
4140 | ? ((v) & ~0x1fffffff) == 0 \ | |
4141 | ? 3 \ | |
4142 | : 2 \ | |
4143 | : ((v) & ~0x7fffffff) == 0 \ | |
4144 | ? 1 \ | |
4145 | : 0) | |
4146 | ||
4147 | /* load_register() | |
67c1ffbe | 4148 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4149 | * an absolute expression value into a register. |
4150 | */ | |
4151 | static void | |
67c0d1eb | 4152 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4153 | { |
4154 | int freg; | |
4155 | expressionS hi32, lo32; | |
4156 | ||
4157 | if (ep->X_op != O_big) | |
4158 | { | |
9c2799c2 | 4159 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4160 | |
4161 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4162 | if (!dbl) |
4163 | normalize_constant_expr (ep); | |
256ab948 TS |
4164 | |
4165 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4166 | { |
4167 | /* We can handle 16 bit signed values with an addiu to | |
4168 | $zero. No need to ever use daddiu here, since $zero and | |
4169 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4170 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4171 | return; |
4172 | } | |
4173 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4174 | { | |
4175 | /* We can handle 16 bit unsigned values with an ori to | |
4176 | $zero. */ | |
67c0d1eb | 4177 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4178 | return; |
4179 | } | |
256ab948 | 4180 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4181 | { |
4182 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4183 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4184 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4185 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4186 | return; |
4187 | } | |
4188 | } | |
4189 | ||
4190 | /* The value is larger than 32 bits. */ | |
4191 | ||
2051e8c4 | 4192 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4193 | { |
55e08f71 NC |
4194 | char value[32]; |
4195 | ||
4196 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4197 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4198 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4199 | return; |
4200 | } | |
4201 | ||
4202 | if (ep->X_op != O_big) | |
4203 | { | |
4204 | hi32 = *ep; | |
4205 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4206 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4207 | hi32.X_add_number &= 0xffffffff; | |
4208 | lo32 = *ep; | |
4209 | lo32.X_add_number &= 0xffffffff; | |
4210 | } | |
4211 | else | |
4212 | { | |
9c2799c2 | 4213 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4214 | if (ep->X_add_number == 3) |
4215 | generic_bignum[3] = 0; | |
4216 | else if (ep->X_add_number > 4) | |
4217 | as_bad (_("Number larger than 64 bits")); | |
4218 | lo32.X_op = O_constant; | |
4219 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4220 | hi32.X_op = O_constant; | |
4221 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4222 | } | |
4223 | ||
4224 | if (hi32.X_add_number == 0) | |
4225 | freg = 0; | |
4226 | else | |
4227 | { | |
4228 | int shift, bit; | |
4229 | unsigned long hi, lo; | |
4230 | ||
956cd1d6 | 4231 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4232 | { |
4233 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4234 | { | |
67c0d1eb | 4235 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4236 | return; |
4237 | } | |
4238 | if (lo32.X_add_number & 0x80000000) | |
4239 | { | |
67c0d1eb | 4240 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4241 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4242 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4243 | return; |
4244 | } | |
4245 | } | |
252b5132 RH |
4246 | |
4247 | /* Check for 16bit shifted constant. We know that hi32 is | |
4248 | non-zero, so start the mask on the first bit of the hi32 | |
4249 | value. */ | |
4250 | shift = 17; | |
4251 | do | |
beae10d5 KH |
4252 | { |
4253 | unsigned long himask, lomask; | |
4254 | ||
4255 | if (shift < 32) | |
4256 | { | |
4257 | himask = 0xffff >> (32 - shift); | |
4258 | lomask = (0xffff << shift) & 0xffffffff; | |
4259 | } | |
4260 | else | |
4261 | { | |
4262 | himask = 0xffff << (shift - 32); | |
4263 | lomask = 0; | |
4264 | } | |
4265 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4266 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4267 | { | |
4268 | expressionS tmp; | |
4269 | ||
4270 | tmp.X_op = O_constant; | |
4271 | if (shift < 32) | |
4272 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4273 | | (lo32.X_add_number >> shift)); | |
4274 | else | |
4275 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4276 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4277 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4278 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4279 | return; |
4280 | } | |
f9419b05 | 4281 | ++shift; |
beae10d5 KH |
4282 | } |
4283 | while (shift <= (64 - 16)); | |
252b5132 RH |
4284 | |
4285 | /* Find the bit number of the lowest one bit, and store the | |
4286 | shifted value in hi/lo. */ | |
4287 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4288 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4289 | if (lo != 0) | |
4290 | { | |
4291 | bit = 0; | |
4292 | while ((lo & 1) == 0) | |
4293 | { | |
4294 | lo >>= 1; | |
4295 | ++bit; | |
4296 | } | |
4297 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4298 | hi >>= bit; | |
4299 | } | |
4300 | else | |
4301 | { | |
4302 | bit = 32; | |
4303 | while ((hi & 1) == 0) | |
4304 | { | |
4305 | hi >>= 1; | |
4306 | ++bit; | |
4307 | } | |
4308 | lo = hi; | |
4309 | hi = 0; | |
4310 | } | |
4311 | ||
4312 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4313 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4314 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4315 | { |
4316 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4317 | if (shift != 0) |
beae10d5 | 4318 | { |
252b5132 RH |
4319 | expressionS tmp; |
4320 | ||
4321 | /* This instruction will set the register to be all | |
4322 | ones. */ | |
beae10d5 KH |
4323 | tmp.X_op = O_constant; |
4324 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4325 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4326 | if (bit != 0) |
4327 | { | |
4328 | bit += shift; | |
67c0d1eb RS |
4329 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4330 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4331 | } |
67c0d1eb RS |
4332 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4333 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4334 | return; |
4335 | } | |
4336 | } | |
252b5132 RH |
4337 | |
4338 | /* Sign extend hi32 before calling load_register, because we can | |
4339 | generally get better code when we load a sign extended value. */ | |
4340 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4341 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4342 | load_register (reg, &hi32, 0); |
252b5132 RH |
4343 | freg = reg; |
4344 | } | |
4345 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4346 | { | |
4347 | if (freg != 0) | |
4348 | { | |
67c0d1eb | 4349 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4350 | freg = reg; |
4351 | } | |
4352 | } | |
4353 | else | |
4354 | { | |
4355 | expressionS mid16; | |
4356 | ||
956cd1d6 | 4357 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4358 | { |
67c0d1eb RS |
4359 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4360 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4361 | return; |
4362 | } | |
252b5132 RH |
4363 | |
4364 | if (freg != 0) | |
4365 | { | |
67c0d1eb | 4366 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4367 | freg = reg; |
4368 | } | |
4369 | mid16 = lo32; | |
4370 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4371 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4372 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4373 | freg = reg; |
4374 | } | |
4375 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4376 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4377 | } |
4378 | ||
269137b2 TS |
4379 | static inline void |
4380 | load_delay_nop (void) | |
4381 | { | |
4382 | if (!gpr_interlocks) | |
4383 | macro_build (NULL, "nop", ""); | |
4384 | } | |
4385 | ||
252b5132 RH |
4386 | /* Load an address into a register. */ |
4387 | ||
4388 | static void | |
67c0d1eb | 4389 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4390 | { |
252b5132 RH |
4391 | if (ep->X_op != O_constant |
4392 | && ep->X_op != O_symbol) | |
4393 | { | |
4394 | as_bad (_("expression too complex")); | |
4395 | ep->X_op = O_constant; | |
4396 | } | |
4397 | ||
4398 | if (ep->X_op == O_constant) | |
4399 | { | |
67c0d1eb | 4400 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4401 | return; |
4402 | } | |
4403 | ||
4404 | if (mips_pic == NO_PIC) | |
4405 | { | |
4406 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4407 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4408 | Otherwise we want |
4409 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4410 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4411 | If we have an addend, we always use the latter form. |
76b3015f | 4412 | |
d6bc6245 TS |
4413 | With 64bit address space and a usable $at we want |
4414 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4415 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4416 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4417 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4418 | dsll32 $reg,0 | |
3a482fd5 | 4419 | daddu $reg,$reg,$at |
76b3015f | 4420 | |
c03099e6 | 4421 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4422 | on superscalar processors. |
4423 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4424 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4425 | dsll $reg,16 | |
4426 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4427 | dsll $reg,16 | |
4428 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4429 | |
4430 | For GP relative symbols in 64bit address space we can use | |
4431 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4432 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4433 | { |
6caf9ef4 TS |
4434 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4435 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4436 | { | |
4437 | relax_start (ep->X_add_symbol); | |
4438 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4439 | mips_gp_register, BFD_RELOC_GPREL16); | |
4440 | relax_switch (); | |
4441 | } | |
d6bc6245 | 4442 | |
741fe287 | 4443 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4444 | { |
67c0d1eb RS |
4445 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4446 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4447 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4448 | BFD_RELOC_MIPS_HIGHER); | |
4449 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4450 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4451 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4452 | *used_at = 1; |
4453 | } | |
4454 | else | |
4455 | { | |
67c0d1eb RS |
4456 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4457 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4458 | BFD_RELOC_MIPS_HIGHER); | |
4459 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4460 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4461 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4462 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4463 | } |
6caf9ef4 TS |
4464 | |
4465 | if (mips_relax.sequence) | |
4466 | relax_end (); | |
d6bc6245 | 4467 | } |
252b5132 RH |
4468 | else |
4469 | { | |
d6bc6245 | 4470 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4471 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4472 | { |
4d7206a2 | 4473 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4474 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4475 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4476 | relax_switch (); |
d6bc6245 | 4477 | } |
67c0d1eb RS |
4478 | macro_build_lui (ep, reg); |
4479 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4480 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4481 | if (mips_relax.sequence) |
4482 | relax_end (); | |
d6bc6245 | 4483 | } |
252b5132 | 4484 | } |
0a44bf69 | 4485 | else if (!mips_big_got) |
252b5132 RH |
4486 | { |
4487 | expressionS ex; | |
4488 | ||
4489 | /* If this is a reference to an external symbol, we want | |
4490 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4491 | Otherwise we want | |
4492 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4493 | nop | |
4494 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4495 | If there is a constant, it must be added in after. |
4496 | ||
ed6fb7bd | 4497 | If we have NewABI, we want |
f5040a92 AO |
4498 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4499 | unless we're referencing a global symbol with a non-zero | |
4500 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4501 | if (HAVE_NEWABI) |
4502 | { | |
f5040a92 AO |
4503 | if (ep->X_add_number) |
4504 | { | |
4d7206a2 | 4505 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4506 | ep->X_add_number = 0; |
4d7206a2 | 4507 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4508 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4509 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4510 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4511 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4512 | ex.X_op = O_constant; | |
67c0d1eb | 4513 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4514 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4515 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4516 | relax_switch (); |
f5040a92 | 4517 | } |
67c0d1eb | 4518 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4519 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4520 | if (mips_relax.sequence) |
4521 | relax_end (); | |
ed6fb7bd SC |
4522 | } |
4523 | else | |
4524 | { | |
f5040a92 AO |
4525 | ex.X_add_number = ep->X_add_number; |
4526 | ep->X_add_number = 0; | |
67c0d1eb RS |
4527 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4528 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4529 | load_delay_nop (); |
4d7206a2 RS |
4530 | relax_start (ep->X_add_symbol); |
4531 | relax_switch (); | |
67c0d1eb | 4532 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4533 | BFD_RELOC_LO16); |
4d7206a2 | 4534 | relax_end (); |
ed6fb7bd | 4535 | |
f5040a92 AO |
4536 | if (ex.X_add_number != 0) |
4537 | { | |
4538 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4539 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4540 | ex.X_op = O_constant; | |
67c0d1eb | 4541 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4542 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4543 | } |
252b5132 RH |
4544 | } |
4545 | } | |
0a44bf69 | 4546 | else if (mips_big_got) |
252b5132 RH |
4547 | { |
4548 | expressionS ex; | |
252b5132 RH |
4549 | |
4550 | /* This is the large GOT case. If this is a reference to an | |
4551 | external symbol, we want | |
4552 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4553 | addu $reg,$reg,$gp | |
4554 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4555 | |
4556 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4557 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4558 | nop | |
4559 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4560 | If there is a constant, it must be added in after. |
f5040a92 AO |
4561 | |
4562 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4563 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4564 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4565 | */ |
438c16b8 TS |
4566 | if (HAVE_NEWABI) |
4567 | { | |
4d7206a2 | 4568 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4569 | ep->X_add_number = 0; |
4d7206a2 | 4570 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4571 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4572 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4573 | reg, reg, mips_gp_register); | |
4574 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4575 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4576 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4577 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4578 | else if (ex.X_add_number) | |
4579 | { | |
4580 | ex.X_op = O_constant; | |
67c0d1eb RS |
4581 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4582 | BFD_RELOC_LO16); | |
f5040a92 AO |
4583 | } |
4584 | ||
4585 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4586 | relax_switch (); |
67c0d1eb | 4587 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4588 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4589 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4590 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4591 | relax_end (); |
438c16b8 | 4592 | } |
252b5132 | 4593 | else |
438c16b8 | 4594 | { |
f5040a92 AO |
4595 | ex.X_add_number = ep->X_add_number; |
4596 | ep->X_add_number = 0; | |
4d7206a2 | 4597 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4598 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4599 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4600 | reg, reg, mips_gp_register); | |
4601 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4602 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4603 | relax_switch (); |
4604 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4605 | { |
4606 | /* We need a nop before loading from $gp. This special | |
4607 | check is required because the lui which starts the main | |
4608 | instruction stream does not refer to $gp, and so will not | |
4609 | insert the nop which may be required. */ | |
67c0d1eb | 4610 | macro_build (NULL, "nop", ""); |
438c16b8 | 4611 | } |
67c0d1eb | 4612 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4613 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4614 | load_delay_nop (); |
67c0d1eb | 4615 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4616 | BFD_RELOC_LO16); |
4d7206a2 | 4617 | relax_end (); |
438c16b8 | 4618 | |
f5040a92 AO |
4619 | if (ex.X_add_number != 0) |
4620 | { | |
4621 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4622 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4623 | ex.X_op = O_constant; | |
67c0d1eb RS |
4624 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4625 | BFD_RELOC_LO16); | |
f5040a92 | 4626 | } |
252b5132 RH |
4627 | } |
4628 | } | |
252b5132 RH |
4629 | else |
4630 | abort (); | |
8fc2e39e | 4631 | |
741fe287 | 4632 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4633 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4634 | } |
4635 | ||
ea1fb5dc RS |
4636 | /* Move the contents of register SOURCE into register DEST. */ |
4637 | ||
4638 | static void | |
67c0d1eb | 4639 | move_register (int dest, int source) |
ea1fb5dc | 4640 | { |
67c0d1eb RS |
4641 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4642 | dest, source, 0); | |
ea1fb5dc RS |
4643 | } |
4644 | ||
4d7206a2 | 4645 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4646 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4647 | The two alternatives are: | |
4d7206a2 RS |
4648 | |
4649 | Global symbol Local sybmol | |
4650 | ------------- ------------ | |
4651 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4652 | ... ... | |
4653 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4654 | ||
4655 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4656 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4657 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4658 | |
4659 | static void | |
67c0d1eb | 4660 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4661 | { |
4662 | expressionS global; | |
4663 | ||
4664 | global = *local; | |
4665 | global.X_add_number = 0; | |
4666 | ||
4667 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4668 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4669 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4670 | relax_switch (); |
67c0d1eb RS |
4671 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4672 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4673 | relax_end (); |
4674 | } | |
4675 | ||
4676 | static void | |
67c0d1eb | 4677 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4678 | { |
4679 | expressionS global; | |
4680 | ||
4681 | global.X_op = O_constant; | |
4682 | global.X_op_symbol = NULL; | |
4683 | global.X_add_symbol = NULL; | |
4684 | global.X_add_number = local->X_add_number; | |
4685 | ||
4686 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4687 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4688 | dest, dest, BFD_RELOC_LO16); |
4689 | relax_switch (); | |
67c0d1eb | 4690 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4691 | relax_end (); |
4692 | } | |
4693 | ||
f6a22291 MR |
4694 | static void |
4695 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4696 | { | |
4697 | expressionS global; | |
4698 | int hold_mips_optimize; | |
4699 | ||
4700 | global.X_op = O_constant; | |
4701 | global.X_op_symbol = NULL; | |
4702 | global.X_add_symbol = NULL; | |
4703 | global.X_add_number = local->X_add_number; | |
4704 | ||
4705 | relax_start (local->X_add_symbol); | |
4706 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4707 | relax_switch (); | |
4708 | /* Set mips_optimize around the lui instruction to avoid | |
4709 | inserting an unnecessary nop after the lw. */ | |
4710 | hold_mips_optimize = mips_optimize; | |
4711 | mips_optimize = 2; | |
4712 | macro_build_lui (&global, tmp); | |
4713 | mips_optimize = hold_mips_optimize; | |
4714 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4715 | relax_end (); | |
4716 | ||
4717 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4718 | } | |
4719 | ||
252b5132 RH |
4720 | /* |
4721 | * Build macros | |
4722 | * This routine implements the seemingly endless macro or synthesized | |
4723 | * instructions and addressing modes in the mips assembly language. Many | |
4724 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4725 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4726 | * this verbose method. Others are not simple macros but are more like |
4727 | * optimizing code generation. | |
4728 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4729 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4730 | * The ensuing load upper instructions are ommited. This implies some kind |
4731 | * of global optimization. We currently only optimize within a single macro. | |
4732 | * For many of the load and store macros if the address is specified as a | |
4733 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4734 | * first load register 'at' with zero and use it as the base register. The | |
4735 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4736 | * we're missing. | |
4737 | */ | |
4738 | static void | |
17a2f251 | 4739 | macro (struct mips_cl_insn *ip) |
252b5132 | 4740 | { |
741fe287 MR |
4741 | unsigned int treg, sreg, dreg, breg; |
4742 | unsigned int tempreg; | |
252b5132 | 4743 | int mask; |
43841e91 | 4744 | int used_at = 0; |
252b5132 RH |
4745 | expressionS expr1; |
4746 | const char *s; | |
4747 | const char *s2; | |
4748 | const char *fmt; | |
4749 | int likely = 0; | |
4750 | int dbl = 0; | |
4751 | int coproc = 0; | |
4752 | int lr = 0; | |
4753 | int imm = 0; | |
1abe91b1 | 4754 | int call = 0; |
252b5132 | 4755 | int off; |
67c0d1eb | 4756 | offsetT maxnum; |
252b5132 | 4757 | bfd_reloc_code_real_type r; |
252b5132 RH |
4758 | int hold_mips_optimize; |
4759 | ||
9c2799c2 | 4760 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
4761 | |
4762 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4763 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4764 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4765 | mask = ip->insn_mo->mask; | |
4766 | ||
4767 | expr1.X_op = O_constant; | |
4768 | expr1.X_op_symbol = NULL; | |
4769 | expr1.X_add_symbol = NULL; | |
4770 | expr1.X_add_number = 1; | |
4771 | ||
4772 | switch (mask) | |
4773 | { | |
4774 | case M_DABS: | |
4775 | dbl = 1; | |
4776 | case M_ABS: | |
4777 | /* bgez $a0,.+12 | |
4778 | move v0,$a0 | |
4779 | sub v0,$zero,$a0 | |
4780 | */ | |
4781 | ||
7d10b47d | 4782 | start_noreorder (); |
252b5132 RH |
4783 | |
4784 | expr1.X_add_number = 8; | |
67c0d1eb | 4785 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4786 | if (dreg == sreg) |
67c0d1eb | 4787 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4788 | else |
67c0d1eb RS |
4789 | move_register (dreg, sreg); |
4790 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4791 | |
7d10b47d | 4792 | end_noreorder (); |
8fc2e39e | 4793 | break; |
252b5132 RH |
4794 | |
4795 | case M_ADD_I: | |
4796 | s = "addi"; | |
4797 | s2 = "add"; | |
4798 | goto do_addi; | |
4799 | case M_ADDU_I: | |
4800 | s = "addiu"; | |
4801 | s2 = "addu"; | |
4802 | goto do_addi; | |
4803 | case M_DADD_I: | |
4804 | dbl = 1; | |
4805 | s = "daddi"; | |
4806 | s2 = "dadd"; | |
4807 | goto do_addi; | |
4808 | case M_DADDU_I: | |
4809 | dbl = 1; | |
4810 | s = "daddiu"; | |
4811 | s2 = "daddu"; | |
4812 | do_addi: | |
4813 | if (imm_expr.X_op == O_constant | |
4814 | && imm_expr.X_add_number >= -0x8000 | |
4815 | && imm_expr.X_add_number < 0x8000) | |
4816 | { | |
67c0d1eb | 4817 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4818 | break; |
252b5132 | 4819 | } |
8fc2e39e | 4820 | used_at = 1; |
67c0d1eb RS |
4821 | load_register (AT, &imm_expr, dbl); |
4822 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4823 | break; |
4824 | ||
4825 | case M_AND_I: | |
4826 | s = "andi"; | |
4827 | s2 = "and"; | |
4828 | goto do_bit; | |
4829 | case M_OR_I: | |
4830 | s = "ori"; | |
4831 | s2 = "or"; | |
4832 | goto do_bit; | |
4833 | case M_NOR_I: | |
4834 | s = ""; | |
4835 | s2 = "nor"; | |
4836 | goto do_bit; | |
4837 | case M_XOR_I: | |
4838 | s = "xori"; | |
4839 | s2 = "xor"; | |
4840 | do_bit: | |
4841 | if (imm_expr.X_op == O_constant | |
4842 | && imm_expr.X_add_number >= 0 | |
4843 | && imm_expr.X_add_number < 0x10000) | |
4844 | { | |
4845 | if (mask != M_NOR_I) | |
67c0d1eb | 4846 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4847 | else |
4848 | { | |
67c0d1eb RS |
4849 | macro_build (&imm_expr, "ori", "t,r,i", |
4850 | treg, sreg, BFD_RELOC_LO16); | |
4851 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4852 | } |
8fc2e39e | 4853 | break; |
252b5132 RH |
4854 | } |
4855 | ||
8fc2e39e | 4856 | used_at = 1; |
67c0d1eb RS |
4857 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4858 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4859 | break; |
4860 | ||
8b082fb1 TS |
4861 | case M_BALIGN: |
4862 | switch (imm_expr.X_add_number) | |
4863 | { | |
4864 | case 0: | |
4865 | macro_build (NULL, "nop", ""); | |
4866 | break; | |
4867 | case 2: | |
4868 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4869 | break; | |
4870 | default: | |
4871 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4872 | (int)imm_expr.X_add_number); | |
4873 | break; | |
4874 | } | |
4875 | break; | |
4876 | ||
252b5132 RH |
4877 | case M_BEQ_I: |
4878 | s = "beq"; | |
4879 | goto beq_i; | |
4880 | case M_BEQL_I: | |
4881 | s = "beql"; | |
4882 | likely = 1; | |
4883 | goto beq_i; | |
4884 | case M_BNE_I: | |
4885 | s = "bne"; | |
4886 | goto beq_i; | |
4887 | case M_BNEL_I: | |
4888 | s = "bnel"; | |
4889 | likely = 1; | |
4890 | beq_i: | |
4891 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4892 | { | |
67c0d1eb | 4893 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4894 | break; |
252b5132 | 4895 | } |
8fc2e39e | 4896 | used_at = 1; |
67c0d1eb RS |
4897 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4898 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4899 | break; |
4900 | ||
4901 | case M_BGEL: | |
4902 | likely = 1; | |
4903 | case M_BGE: | |
4904 | if (treg == 0) | |
4905 | { | |
67c0d1eb | 4906 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4907 | break; |
252b5132 RH |
4908 | } |
4909 | if (sreg == 0) | |
4910 | { | |
67c0d1eb | 4911 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4912 | break; |
252b5132 | 4913 | } |
8fc2e39e | 4914 | used_at = 1; |
67c0d1eb RS |
4915 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4916 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4917 | break; |
4918 | ||
4919 | case M_BGTL_I: | |
4920 | likely = 1; | |
4921 | case M_BGT_I: | |
4922 | /* check for > max integer */ | |
4923 | maxnum = 0x7fffffff; | |
ca4e0257 | 4924 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4925 | { |
4926 | maxnum <<= 16; | |
4927 | maxnum |= 0xffff; | |
4928 | maxnum <<= 16; | |
4929 | maxnum |= 0xffff; | |
4930 | } | |
4931 | if (imm_expr.X_op == O_constant | |
4932 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4933 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4934 | { |
4935 | do_false: | |
4936 | /* result is always false */ | |
4937 | if (! likely) | |
67c0d1eb | 4938 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4939 | else |
67c0d1eb | 4940 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4941 | break; |
252b5132 RH |
4942 | } |
4943 | if (imm_expr.X_op != O_constant) | |
4944 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4945 | ++imm_expr.X_add_number; |
252b5132 RH |
4946 | /* FALLTHROUGH */ |
4947 | case M_BGE_I: | |
4948 | case M_BGEL_I: | |
4949 | if (mask == M_BGEL_I) | |
4950 | likely = 1; | |
4951 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4952 | { | |
67c0d1eb | 4953 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4954 | break; |
252b5132 RH |
4955 | } |
4956 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4957 | { | |
67c0d1eb | 4958 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4959 | break; |
252b5132 RH |
4960 | } |
4961 | maxnum = 0x7fffffff; | |
ca4e0257 | 4962 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4963 | { |
4964 | maxnum <<= 16; | |
4965 | maxnum |= 0xffff; | |
4966 | maxnum <<= 16; | |
4967 | maxnum |= 0xffff; | |
4968 | } | |
4969 | maxnum = - maxnum - 1; | |
4970 | if (imm_expr.X_op == O_constant | |
4971 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4972 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4973 | { |
4974 | do_true: | |
4975 | /* result is always true */ | |
4976 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4977 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4978 | break; |
252b5132 | 4979 | } |
8fc2e39e | 4980 | used_at = 1; |
67c0d1eb RS |
4981 | set_at (sreg, 0); |
4982 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4983 | break; |
4984 | ||
4985 | case M_BGEUL: | |
4986 | likely = 1; | |
4987 | case M_BGEU: | |
4988 | if (treg == 0) | |
4989 | goto do_true; | |
4990 | if (sreg == 0) | |
4991 | { | |
67c0d1eb | 4992 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4993 | "s,t,p", 0, treg); |
8fc2e39e | 4994 | break; |
252b5132 | 4995 | } |
8fc2e39e | 4996 | used_at = 1; |
67c0d1eb RS |
4997 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4998 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4999 | break; |
5000 | ||
5001 | case M_BGTUL_I: | |
5002 | likely = 1; | |
5003 | case M_BGTU_I: | |
5004 | if (sreg == 0 | |
ca4e0257 | 5005 | || (HAVE_32BIT_GPRS |
252b5132 | 5006 | && imm_expr.X_op == O_constant |
956cd1d6 | 5007 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5008 | goto do_false; |
5009 | if (imm_expr.X_op != O_constant) | |
5010 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5011 | ++imm_expr.X_add_number; |
252b5132 RH |
5012 | /* FALLTHROUGH */ |
5013 | case M_BGEU_I: | |
5014 | case M_BGEUL_I: | |
5015 | if (mask == M_BGEUL_I) | |
5016 | likely = 1; | |
5017 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5018 | goto do_true; | |
5019 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5020 | { | |
67c0d1eb | 5021 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5022 | "s,t,p", sreg, 0); |
8fc2e39e | 5023 | break; |
252b5132 | 5024 | } |
8fc2e39e | 5025 | used_at = 1; |
67c0d1eb RS |
5026 | set_at (sreg, 1); |
5027 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5028 | break; |
5029 | ||
5030 | case M_BGTL: | |
5031 | likely = 1; | |
5032 | case M_BGT: | |
5033 | if (treg == 0) | |
5034 | { | |
67c0d1eb | 5035 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5036 | break; |
252b5132 RH |
5037 | } |
5038 | if (sreg == 0) | |
5039 | { | |
67c0d1eb | 5040 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5041 | break; |
252b5132 | 5042 | } |
8fc2e39e | 5043 | used_at = 1; |
67c0d1eb RS |
5044 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5045 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5046 | break; |
5047 | ||
5048 | case M_BGTUL: | |
5049 | likely = 1; | |
5050 | case M_BGTU: | |
5051 | if (treg == 0) | |
5052 | { | |
67c0d1eb | 5053 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5054 | "s,t,p", sreg, 0); |
8fc2e39e | 5055 | break; |
252b5132 RH |
5056 | } |
5057 | if (sreg == 0) | |
5058 | goto do_false; | |
8fc2e39e | 5059 | used_at = 1; |
67c0d1eb RS |
5060 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5061 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5062 | break; |
5063 | ||
5064 | case M_BLEL: | |
5065 | likely = 1; | |
5066 | case M_BLE: | |
5067 | if (treg == 0) | |
5068 | { | |
67c0d1eb | 5069 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5070 | break; |
252b5132 RH |
5071 | } |
5072 | if (sreg == 0) | |
5073 | { | |
67c0d1eb | 5074 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5075 | break; |
252b5132 | 5076 | } |
8fc2e39e | 5077 | used_at = 1; |
67c0d1eb RS |
5078 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5079 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5080 | break; |
5081 | ||
5082 | case M_BLEL_I: | |
5083 | likely = 1; | |
5084 | case M_BLE_I: | |
5085 | maxnum = 0x7fffffff; | |
ca4e0257 | 5086 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5087 | { |
5088 | maxnum <<= 16; | |
5089 | maxnum |= 0xffff; | |
5090 | maxnum <<= 16; | |
5091 | maxnum |= 0xffff; | |
5092 | } | |
5093 | if (imm_expr.X_op == O_constant | |
5094 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5095 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5096 | goto do_true; |
5097 | if (imm_expr.X_op != O_constant) | |
5098 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5099 | ++imm_expr.X_add_number; |
252b5132 RH |
5100 | /* FALLTHROUGH */ |
5101 | case M_BLT_I: | |
5102 | case M_BLTL_I: | |
5103 | if (mask == M_BLTL_I) | |
5104 | likely = 1; | |
5105 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5106 | { | |
67c0d1eb | 5107 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5108 | break; |
252b5132 RH |
5109 | } |
5110 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5111 | { | |
67c0d1eb | 5112 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5113 | break; |
252b5132 | 5114 | } |
8fc2e39e | 5115 | used_at = 1; |
67c0d1eb RS |
5116 | set_at (sreg, 0); |
5117 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5118 | break; |
5119 | ||
5120 | case M_BLEUL: | |
5121 | likely = 1; | |
5122 | case M_BLEU: | |
5123 | if (treg == 0) | |
5124 | { | |
67c0d1eb | 5125 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5126 | "s,t,p", sreg, 0); |
8fc2e39e | 5127 | break; |
252b5132 RH |
5128 | } |
5129 | if (sreg == 0) | |
5130 | goto do_true; | |
8fc2e39e | 5131 | used_at = 1; |
67c0d1eb RS |
5132 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5133 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5134 | break; |
5135 | ||
5136 | case M_BLEUL_I: | |
5137 | likely = 1; | |
5138 | case M_BLEU_I: | |
5139 | if (sreg == 0 | |
ca4e0257 | 5140 | || (HAVE_32BIT_GPRS |
252b5132 | 5141 | && imm_expr.X_op == O_constant |
956cd1d6 | 5142 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5143 | goto do_true; |
5144 | if (imm_expr.X_op != O_constant) | |
5145 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5146 | ++imm_expr.X_add_number; |
252b5132 RH |
5147 | /* FALLTHROUGH */ |
5148 | case M_BLTU_I: | |
5149 | case M_BLTUL_I: | |
5150 | if (mask == M_BLTUL_I) | |
5151 | likely = 1; | |
5152 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5153 | goto do_false; | |
5154 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5155 | { | |
67c0d1eb | 5156 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 5157 | "s,t,p", sreg, 0); |
8fc2e39e | 5158 | break; |
252b5132 | 5159 | } |
8fc2e39e | 5160 | used_at = 1; |
67c0d1eb RS |
5161 | set_at (sreg, 1); |
5162 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5163 | break; |
5164 | ||
5165 | case M_BLTL: | |
5166 | likely = 1; | |
5167 | case M_BLT: | |
5168 | if (treg == 0) | |
5169 | { | |
67c0d1eb | 5170 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5171 | break; |
252b5132 RH |
5172 | } |
5173 | if (sreg == 0) | |
5174 | { | |
67c0d1eb | 5175 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5176 | break; |
252b5132 | 5177 | } |
8fc2e39e | 5178 | used_at = 1; |
67c0d1eb RS |
5179 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
5180 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5181 | break; |
5182 | ||
5183 | case M_BLTUL: | |
5184 | likely = 1; | |
5185 | case M_BLTU: | |
5186 | if (treg == 0) | |
5187 | goto do_false; | |
5188 | if (sreg == 0) | |
5189 | { | |
67c0d1eb | 5190 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5191 | "s,t,p", 0, treg); |
8fc2e39e | 5192 | break; |
252b5132 | 5193 | } |
8fc2e39e | 5194 | used_at = 1; |
67c0d1eb RS |
5195 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5196 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5197 | break; |
5198 | ||
5f74bc13 CD |
5199 | case M_DEXT: |
5200 | { | |
5201 | unsigned long pos; | |
5202 | unsigned long size; | |
5203 | ||
5204 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5205 | { | |
5206 | as_bad (_("Unsupported large constant")); | |
5207 | pos = size = 1; | |
5208 | } | |
5209 | else | |
5210 | { | |
5211 | pos = (unsigned long) imm_expr.X_add_number; | |
5212 | size = (unsigned long) imm2_expr.X_add_number; | |
5213 | } | |
5214 | ||
5215 | if (pos > 63) | |
5216 | { | |
5217 | as_bad (_("Improper position (%lu)"), pos); | |
5218 | pos = 1; | |
5219 | } | |
5220 | if (size == 0 || size > 64 | |
5221 | || (pos + size - 1) > 63) | |
5222 | { | |
5223 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5224 | size, pos); | |
5225 | size = 1; | |
5226 | } | |
5227 | ||
5228 | if (size <= 32 && pos < 32) | |
5229 | { | |
5230 | s = "dext"; | |
5231 | fmt = "t,r,+A,+C"; | |
5232 | } | |
5233 | else if (size <= 32) | |
5234 | { | |
5235 | s = "dextu"; | |
5236 | fmt = "t,r,+E,+H"; | |
5237 | } | |
5238 | else | |
5239 | { | |
5240 | s = "dextm"; | |
5241 | fmt = "t,r,+A,+G"; | |
5242 | } | |
67c0d1eb | 5243 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5244 | } |
8fc2e39e | 5245 | break; |
5f74bc13 CD |
5246 | |
5247 | case M_DINS: | |
5248 | { | |
5249 | unsigned long pos; | |
5250 | unsigned long size; | |
5251 | ||
5252 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5253 | { | |
5254 | as_bad (_("Unsupported large constant")); | |
5255 | pos = size = 1; | |
5256 | } | |
5257 | else | |
5258 | { | |
5259 | pos = (unsigned long) imm_expr.X_add_number; | |
5260 | size = (unsigned long) imm2_expr.X_add_number; | |
5261 | } | |
5262 | ||
5263 | if (pos > 63) | |
5264 | { | |
5265 | as_bad (_("Improper position (%lu)"), pos); | |
5266 | pos = 1; | |
5267 | } | |
5268 | if (size == 0 || size > 64 | |
5269 | || (pos + size - 1) > 63) | |
5270 | { | |
5271 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5272 | size, pos); | |
5273 | size = 1; | |
5274 | } | |
5275 | ||
5276 | if (pos < 32 && (pos + size - 1) < 32) | |
5277 | { | |
5278 | s = "dins"; | |
5279 | fmt = "t,r,+A,+B"; | |
5280 | } | |
5281 | else if (pos >= 32) | |
5282 | { | |
5283 | s = "dinsu"; | |
5284 | fmt = "t,r,+E,+F"; | |
5285 | } | |
5286 | else | |
5287 | { | |
5288 | s = "dinsm"; | |
5289 | fmt = "t,r,+A,+F"; | |
5290 | } | |
750bdd57 AS |
5291 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5292 | (int) (pos + size - 1)); | |
5f74bc13 | 5293 | } |
8fc2e39e | 5294 | break; |
5f74bc13 | 5295 | |
252b5132 RH |
5296 | case M_DDIV_3: |
5297 | dbl = 1; | |
5298 | case M_DIV_3: | |
5299 | s = "mflo"; | |
5300 | goto do_div3; | |
5301 | case M_DREM_3: | |
5302 | dbl = 1; | |
5303 | case M_REM_3: | |
5304 | s = "mfhi"; | |
5305 | do_div3: | |
5306 | if (treg == 0) | |
5307 | { | |
5308 | as_warn (_("Divide by zero.")); | |
5309 | if (mips_trap) | |
67c0d1eb | 5310 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5311 | else |
67c0d1eb | 5312 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5313 | break; |
252b5132 RH |
5314 | } |
5315 | ||
7d10b47d | 5316 | start_noreorder (); |
252b5132 RH |
5317 | if (mips_trap) |
5318 | { | |
67c0d1eb RS |
5319 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5320 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5321 | } |
5322 | else | |
5323 | { | |
5324 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5325 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5326 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5327 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5328 | } |
5329 | expr1.X_add_number = -1; | |
8fc2e39e | 5330 | used_at = 1; |
f6a22291 | 5331 | load_register (AT, &expr1, dbl); |
252b5132 | 5332 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5333 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5334 | if (dbl) |
5335 | { | |
5336 | expr1.X_add_number = 1; | |
f6a22291 | 5337 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5338 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5339 | } |
5340 | else | |
5341 | { | |
5342 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5343 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5344 | } |
5345 | if (mips_trap) | |
5346 | { | |
67c0d1eb | 5347 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5348 | /* We want to close the noreorder block as soon as possible, so |
5349 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5350 | end_noreorder (); |
252b5132 RH |
5351 | } |
5352 | else | |
5353 | { | |
5354 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5355 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5356 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5357 | |
5358 | /* We want to close the noreorder block as soon as possible, so | |
5359 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5360 | end_noreorder (); |
252b5132 | 5361 | |
67c0d1eb | 5362 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5363 | } |
67c0d1eb | 5364 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5365 | break; |
5366 | ||
5367 | case M_DIV_3I: | |
5368 | s = "div"; | |
5369 | s2 = "mflo"; | |
5370 | goto do_divi; | |
5371 | case M_DIVU_3I: | |
5372 | s = "divu"; | |
5373 | s2 = "mflo"; | |
5374 | goto do_divi; | |
5375 | case M_REM_3I: | |
5376 | s = "div"; | |
5377 | s2 = "mfhi"; | |
5378 | goto do_divi; | |
5379 | case M_REMU_3I: | |
5380 | s = "divu"; | |
5381 | s2 = "mfhi"; | |
5382 | goto do_divi; | |
5383 | case M_DDIV_3I: | |
5384 | dbl = 1; | |
5385 | s = "ddiv"; | |
5386 | s2 = "mflo"; | |
5387 | goto do_divi; | |
5388 | case M_DDIVU_3I: | |
5389 | dbl = 1; | |
5390 | s = "ddivu"; | |
5391 | s2 = "mflo"; | |
5392 | goto do_divi; | |
5393 | case M_DREM_3I: | |
5394 | dbl = 1; | |
5395 | s = "ddiv"; | |
5396 | s2 = "mfhi"; | |
5397 | goto do_divi; | |
5398 | case M_DREMU_3I: | |
5399 | dbl = 1; | |
5400 | s = "ddivu"; | |
5401 | s2 = "mfhi"; | |
5402 | do_divi: | |
5403 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5404 | { | |
5405 | as_warn (_("Divide by zero.")); | |
5406 | if (mips_trap) | |
67c0d1eb | 5407 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5408 | else |
67c0d1eb | 5409 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5410 | break; |
252b5132 RH |
5411 | } |
5412 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5413 | { | |
5414 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5415 | move_register (dreg, sreg); |
252b5132 | 5416 | else |
67c0d1eb | 5417 | move_register (dreg, 0); |
8fc2e39e | 5418 | break; |
252b5132 RH |
5419 | } |
5420 | if (imm_expr.X_op == O_constant | |
5421 | && imm_expr.X_add_number == -1 | |
5422 | && s[strlen (s) - 1] != 'u') | |
5423 | { | |
5424 | if (strcmp (s2, "mflo") == 0) | |
5425 | { | |
67c0d1eb | 5426 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5427 | } |
5428 | else | |
67c0d1eb | 5429 | move_register (dreg, 0); |
8fc2e39e | 5430 | break; |
252b5132 RH |
5431 | } |
5432 | ||
8fc2e39e | 5433 | used_at = 1; |
67c0d1eb RS |
5434 | load_register (AT, &imm_expr, dbl); |
5435 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5436 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5437 | break; |
5438 | ||
5439 | case M_DIVU_3: | |
5440 | s = "divu"; | |
5441 | s2 = "mflo"; | |
5442 | goto do_divu3; | |
5443 | case M_REMU_3: | |
5444 | s = "divu"; | |
5445 | s2 = "mfhi"; | |
5446 | goto do_divu3; | |
5447 | case M_DDIVU_3: | |
5448 | s = "ddivu"; | |
5449 | s2 = "mflo"; | |
5450 | goto do_divu3; | |
5451 | case M_DREMU_3: | |
5452 | s = "ddivu"; | |
5453 | s2 = "mfhi"; | |
5454 | do_divu3: | |
7d10b47d | 5455 | start_noreorder (); |
252b5132 RH |
5456 | if (mips_trap) |
5457 | { | |
67c0d1eb RS |
5458 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5459 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5460 | /* We want to close the noreorder block as soon as possible, so |
5461 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5462 | end_noreorder (); |
252b5132 RH |
5463 | } |
5464 | else | |
5465 | { | |
5466 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5467 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5468 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5469 | |
5470 | /* We want to close the noreorder block as soon as possible, so | |
5471 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5472 | end_noreorder (); |
67c0d1eb | 5473 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5474 | } |
67c0d1eb | 5475 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5476 | break; |
252b5132 | 5477 | |
1abe91b1 MR |
5478 | case M_DLCA_AB: |
5479 | dbl = 1; | |
5480 | case M_LCA_AB: | |
5481 | call = 1; | |
5482 | goto do_la; | |
252b5132 RH |
5483 | case M_DLA_AB: |
5484 | dbl = 1; | |
5485 | case M_LA_AB: | |
1abe91b1 | 5486 | do_la: |
252b5132 RH |
5487 | /* Load the address of a symbol into a register. If breg is not |
5488 | zero, we then add a base register to it. */ | |
5489 | ||
3bec30a8 TS |
5490 | if (dbl && HAVE_32BIT_GPRS) |
5491 | as_warn (_("dla used to load 32-bit register")); | |
5492 | ||
c90bbe5b | 5493 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5494 | as_warn (_("la used to load 64-bit address")); |
5495 | ||
0c11417f MR |
5496 | if (offset_expr.X_op == O_constant |
5497 | && offset_expr.X_add_number >= -0x8000 | |
5498 | && offset_expr.X_add_number < 0x8000) | |
5499 | { | |
aed1a261 | 5500 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5501 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5502 | break; |
0c11417f MR |
5503 | } |
5504 | ||
741fe287 | 5505 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5506 | { |
5507 | tempreg = AT; | |
5508 | used_at = 1; | |
5509 | } | |
5510 | else | |
5511 | { | |
5512 | tempreg = treg; | |
afdbd6d0 CD |
5513 | } |
5514 | ||
252b5132 RH |
5515 | if (offset_expr.X_op != O_symbol |
5516 | && offset_expr.X_op != O_constant) | |
5517 | { | |
5518 | as_bad (_("expression too complex")); | |
5519 | offset_expr.X_op = O_constant; | |
5520 | } | |
5521 | ||
252b5132 | 5522 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5523 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5524 | else if (mips_pic == NO_PIC) |
5525 | { | |
d6bc6245 | 5526 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5527 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5528 | Otherwise we want |
5529 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5530 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5531 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5532 | so we may as well always use the latter form. |
76b3015f | 5533 | |
6caf9ef4 TS |
5534 | With 64bit address space and a usable $at we want |
5535 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5536 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5537 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5538 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5539 | dsll32 $tempreg,0 | |
5540 | daddu $tempreg,$tempreg,$at | |
5541 | ||
5542 | If $at is already in use, we use a path which is suboptimal | |
5543 | on superscalar processors. | |
5544 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5545 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5546 | dsll $tempreg,16 | |
5547 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5548 | dsll $tempreg,16 | |
5549 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5550 | ||
5551 | For GP relative symbols in 64bit address space we can use | |
5552 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5553 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5554 | { |
6caf9ef4 TS |
5555 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5556 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5557 | { | |
5558 | relax_start (offset_expr.X_add_symbol); | |
5559 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5560 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5561 | relax_switch (); | |
5562 | } | |
d6bc6245 | 5563 | |
741fe287 | 5564 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5565 | { |
67c0d1eb | 5566 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5567 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5568 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5569 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5570 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5571 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5572 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5573 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5574 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5575 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5576 | used_at = 1; |
5577 | } | |
5578 | else | |
5579 | { | |
67c0d1eb | 5580 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5581 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5582 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5583 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5584 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5585 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5586 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5587 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5588 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5589 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5590 | } |
6caf9ef4 TS |
5591 | |
5592 | if (mips_relax.sequence) | |
5593 | relax_end (); | |
98d3f06f KH |
5594 | } |
5595 | else | |
5596 | { | |
5597 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5598 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5599 | { |
4d7206a2 | 5600 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5601 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5602 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5603 | relax_switch (); |
98d3f06f | 5604 | } |
6943caf0 ILT |
5605 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5606 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5607 | macro_build_lui (&offset_expr, tempreg); |
5608 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5609 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5610 | if (mips_relax.sequence) |
5611 | relax_end (); | |
98d3f06f | 5612 | } |
252b5132 | 5613 | } |
0a44bf69 | 5614 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5615 | { |
9117d219 NC |
5616 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5617 | ||
252b5132 RH |
5618 | /* If this is a reference to an external symbol, and there |
5619 | is no constant, we want | |
5620 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5621 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5622 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5623 | For a local symbol, we want |
5624 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5625 | nop | |
5626 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5627 | ||
5628 | If we have a small constant, and this is a reference to | |
5629 | an external symbol, we want | |
5630 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5631 | nop | |
5632 | addiu $tempreg,$tempreg,<constant> | |
5633 | For a local symbol, we want the same instruction | |
5634 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5635 | addiu instruction. | |
5636 | ||
5637 | If we have a large constant, and this is a reference to | |
5638 | an external symbol, we want | |
5639 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5640 | lui $at,<hiconstant> | |
5641 | addiu $at,$at,<loconstant> | |
5642 | addu $tempreg,$tempreg,$at | |
5643 | For a local symbol, we want the same instruction | |
5644 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5645 | addiu instruction. |
ed6fb7bd SC |
5646 | */ |
5647 | ||
4d7206a2 | 5648 | if (offset_expr.X_add_number == 0) |
252b5132 | 5649 | { |
0a44bf69 RS |
5650 | if (mips_pic == SVR4_PIC |
5651 | && breg == 0 | |
5652 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5653 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5654 | ||
5655 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5656 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5657 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5658 | if (breg != 0) |
252b5132 RH |
5659 | { |
5660 | /* We're going to put in an addu instruction using | |
5661 | tempreg, so we may as well insert the nop right | |
5662 | now. */ | |
269137b2 | 5663 | load_delay_nop (); |
252b5132 | 5664 | } |
4d7206a2 | 5665 | relax_switch (); |
67c0d1eb RS |
5666 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5667 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5668 | load_delay_nop (); |
67c0d1eb RS |
5669 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5670 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5671 | relax_end (); |
252b5132 RH |
5672 | /* FIXME: If breg == 0, and the next instruction uses |
5673 | $tempreg, then if this variant case is used an extra | |
5674 | nop will be generated. */ | |
5675 | } | |
4d7206a2 RS |
5676 | else if (offset_expr.X_add_number >= -0x8000 |
5677 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5678 | { |
67c0d1eb | 5679 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5680 | load_delay_nop (); |
67c0d1eb | 5681 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5682 | } |
5683 | else | |
5684 | { | |
4d7206a2 RS |
5685 | expr1.X_add_number = offset_expr.X_add_number; |
5686 | offset_expr.X_add_number = | |
5687 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5688 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5689 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5690 | /* If we are going to add in a base register, and the |
5691 | target register and the base register are the same, | |
5692 | then we are using AT as a temporary register. Since | |
5693 | we want to load the constant into AT, we add our | |
5694 | current AT (from the global offset table) and the | |
5695 | register into the register now, and pretend we were | |
5696 | not using a base register. */ | |
67c0d1eb | 5697 | if (breg == treg) |
252b5132 | 5698 | { |
269137b2 | 5699 | load_delay_nop (); |
67c0d1eb | 5700 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5701 | treg, AT, breg); |
252b5132 RH |
5702 | breg = 0; |
5703 | tempreg = treg; | |
252b5132 | 5704 | } |
f6a22291 | 5705 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5706 | used_at = 1; |
5707 | } | |
5708 | } | |
0a44bf69 | 5709 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5710 | { |
67c0d1eb | 5711 | int add_breg_early = 0; |
f5040a92 AO |
5712 | |
5713 | /* If this is a reference to an external, and there is no | |
5714 | constant, or local symbol (*), with or without a | |
5715 | constant, we want | |
5716 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5717 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5718 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5719 | ||
5720 | If we have a small constant, and this is a reference to | |
5721 | an external symbol, we want | |
5722 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5723 | addiu $tempreg,$tempreg,<constant> | |
5724 | ||
5725 | If we have a large constant, and this is a reference to | |
5726 | an external symbol, we want | |
5727 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5728 | lui $at,<hiconstant> | |
5729 | addiu $at,$at,<loconstant> | |
5730 | addu $tempreg,$tempreg,$at | |
5731 | ||
5732 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5733 | local symbols, even though it introduces an additional | |
5734 | instruction. */ | |
5735 | ||
f5040a92 AO |
5736 | if (offset_expr.X_add_number) |
5737 | { | |
4d7206a2 | 5738 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5739 | offset_expr.X_add_number = 0; |
5740 | ||
4d7206a2 | 5741 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5742 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5743 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5744 | |
5745 | if (expr1.X_add_number >= -0x8000 | |
5746 | && expr1.X_add_number < 0x8000) | |
5747 | { | |
67c0d1eb RS |
5748 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5749 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5750 | } |
ecd13cd3 | 5751 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5752 | { |
5753 | int dreg; | |
5754 | ||
5755 | /* If we are going to add in a base register, and the | |
5756 | target register and the base register are the same, | |
5757 | then we are using AT as a temporary register. Since | |
5758 | we want to load the constant into AT, we add our | |
5759 | current AT (from the global offset table) and the | |
5760 | register into the register now, and pretend we were | |
5761 | not using a base register. */ | |
5762 | if (breg != treg) | |
5763 | dreg = tempreg; | |
5764 | else | |
5765 | { | |
9c2799c2 | 5766 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5767 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5768 | treg, AT, breg); | |
f5040a92 | 5769 | dreg = treg; |
67c0d1eb | 5770 | add_breg_early = 1; |
f5040a92 AO |
5771 | } |
5772 | ||
f6a22291 | 5773 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5774 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5775 | dreg, dreg, AT); |
f5040a92 | 5776 | |
f5040a92 AO |
5777 | used_at = 1; |
5778 | } | |
5779 | else | |
5780 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5781 | ||
4d7206a2 | 5782 | relax_switch (); |
f5040a92 AO |
5783 | offset_expr.X_add_number = expr1.X_add_number; |
5784 | ||
67c0d1eb RS |
5785 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5786 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5787 | if (add_breg_early) | |
f5040a92 | 5788 | { |
67c0d1eb | 5789 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5790 | treg, tempreg, breg); |
f5040a92 AO |
5791 | breg = 0; |
5792 | tempreg = treg; | |
5793 | } | |
4d7206a2 | 5794 | relax_end (); |
f5040a92 | 5795 | } |
4d7206a2 | 5796 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5797 | { |
4d7206a2 | 5798 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5799 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5800 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5801 | relax_switch (); |
67c0d1eb RS |
5802 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5803 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5804 | relax_end (); |
f5040a92 | 5805 | } |
4d7206a2 | 5806 | else |
f5040a92 | 5807 | { |
67c0d1eb RS |
5808 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5809 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5810 | } |
5811 | } | |
0a44bf69 | 5812 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5813 | { |
67c0d1eb | 5814 | int gpdelay; |
9117d219 NC |
5815 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5816 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5817 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5818 | |
5819 | /* This is the large GOT case. If this is a reference to an | |
5820 | external symbol, and there is no constant, we want | |
5821 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5822 | addu $tempreg,$tempreg,$gp | |
5823 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5824 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5825 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5826 | addu $tempreg,$tempreg,$gp | |
5827 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5828 | For a local symbol, we want |
5829 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5830 | nop | |
5831 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5832 | ||
5833 | If we have a small constant, and this is a reference to | |
5834 | an external symbol, we want | |
5835 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5836 | addu $tempreg,$tempreg,$gp | |
5837 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5838 | nop | |
5839 | addiu $tempreg,$tempreg,<constant> | |
5840 | For a local symbol, we want | |
5841 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5842 | nop | |
5843 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5844 | ||
5845 | If we have a large constant, and this is a reference to | |
5846 | an external symbol, we want | |
5847 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5848 | addu $tempreg,$tempreg,$gp | |
5849 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5850 | lui $at,<hiconstant> | |
5851 | addiu $at,$at,<loconstant> | |
5852 | addu $tempreg,$tempreg,$at | |
5853 | For a local symbol, we want | |
5854 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5855 | lui $at,<hiconstant> | |
5856 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5857 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5858 | */ |
438c16b8 | 5859 | |
252b5132 RH |
5860 | expr1.X_add_number = offset_expr.X_add_number; |
5861 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5862 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5863 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5864 | if (expr1.X_add_number == 0 && breg == 0 |
5865 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5866 | { |
5867 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5868 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5869 | } | |
67c0d1eb RS |
5870 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5871 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5872 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5873 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5874 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5875 | if (expr1.X_add_number == 0) |
5876 | { | |
67c0d1eb | 5877 | if (breg != 0) |
252b5132 RH |
5878 | { |
5879 | /* We're going to put in an addu instruction using | |
5880 | tempreg, so we may as well insert the nop right | |
5881 | now. */ | |
269137b2 | 5882 | load_delay_nop (); |
252b5132 | 5883 | } |
252b5132 RH |
5884 | } |
5885 | else if (expr1.X_add_number >= -0x8000 | |
5886 | && expr1.X_add_number < 0x8000) | |
5887 | { | |
269137b2 | 5888 | load_delay_nop (); |
67c0d1eb | 5889 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5890 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5891 | } |
5892 | else | |
5893 | { | |
67c0d1eb | 5894 | int dreg; |
252b5132 RH |
5895 | |
5896 | /* If we are going to add in a base register, and the | |
5897 | target register and the base register are the same, | |
5898 | then we are using AT as a temporary register. Since | |
5899 | we want to load the constant into AT, we add our | |
5900 | current AT (from the global offset table) and the | |
5901 | register into the register now, and pretend we were | |
5902 | not using a base register. */ | |
5903 | if (breg != treg) | |
67c0d1eb | 5904 | dreg = tempreg; |
252b5132 RH |
5905 | else |
5906 | { | |
9c2799c2 | 5907 | gas_assert (tempreg == AT); |
269137b2 | 5908 | load_delay_nop (); |
67c0d1eb | 5909 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5910 | treg, AT, breg); |
252b5132 | 5911 | dreg = treg; |
252b5132 RH |
5912 | } |
5913 | ||
f6a22291 | 5914 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5915 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5916 | |
252b5132 RH |
5917 | used_at = 1; |
5918 | } | |
4d7206a2 RS |
5919 | offset_expr.X_add_number = |
5920 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5921 | relax_switch (); | |
252b5132 | 5922 | |
67c0d1eb | 5923 | if (gpdelay) |
252b5132 RH |
5924 | { |
5925 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5926 | the first instruction on the main stream does not. */ |
67c0d1eb | 5927 | macro_build (NULL, "nop", ""); |
252b5132 | 5928 | } |
ed6fb7bd | 5929 | |
67c0d1eb RS |
5930 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5931 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5932 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5933 | && expr1.X_add_number < 0x8000) |
5934 | { | |
269137b2 | 5935 | load_delay_nop (); |
67c0d1eb RS |
5936 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5937 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5938 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5939 | register, the external symbol case ended with a load, |
5940 | so if the symbol turns out to not be external, and | |
5941 | the next instruction uses tempreg, an unnecessary nop | |
5942 | will be inserted. */ | |
252b5132 RH |
5943 | } |
5944 | else | |
5945 | { | |
5946 | if (breg == treg) | |
5947 | { | |
5948 | /* We must add in the base register now, as in the | |
f5040a92 | 5949 | external symbol case. */ |
9c2799c2 | 5950 | gas_assert (tempreg == AT); |
269137b2 | 5951 | load_delay_nop (); |
67c0d1eb | 5952 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5953 | treg, AT, breg); |
252b5132 RH |
5954 | tempreg = treg; |
5955 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5956 | it in in both cases. */ |
252b5132 RH |
5957 | breg = 0; |
5958 | } | |
5959 | ||
67c0d1eb RS |
5960 | macro_build_lui (&expr1, AT); |
5961 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5962 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5963 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5964 | tempreg, tempreg, AT); |
8fc2e39e | 5965 | used_at = 1; |
252b5132 | 5966 | } |
4d7206a2 | 5967 | relax_end (); |
252b5132 | 5968 | } |
0a44bf69 | 5969 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5970 | { |
f5040a92 AO |
5971 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5972 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5973 | int add_breg_early = 0; |
f5040a92 AO |
5974 | |
5975 | /* This is the large GOT case. If this is a reference to an | |
5976 | external symbol, and there is no constant, we want | |
5977 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5978 | add $tempreg,$tempreg,$gp | |
5979 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5980 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5981 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5982 | add $tempreg,$tempreg,$gp | |
5983 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5984 | ||
5985 | If we have a small constant, and this is a reference to | |
5986 | an external symbol, we want | |
5987 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5988 | add $tempreg,$tempreg,$gp | |
5989 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5990 | addi $tempreg,$tempreg,<constant> | |
5991 | ||
5992 | If we have a large constant, and this is a reference to | |
5993 | an external symbol, we want | |
5994 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5995 | addu $tempreg,$tempreg,$gp | |
5996 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5997 | lui $at,<hiconstant> | |
5998 | addi $at,$at,<loconstant> | |
5999 | add $tempreg,$tempreg,$at | |
6000 | ||
6001 | If we have NewABI, and we know it's a local symbol, we want | |
6002 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6003 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6004 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6005 | ||
4d7206a2 | 6006 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6007 | |
4d7206a2 | 6008 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6009 | offset_expr.X_add_number = 0; |
6010 | ||
1abe91b1 MR |
6011 | if (expr1.X_add_number == 0 && breg == 0 |
6012 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6013 | { |
6014 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6015 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6016 | } | |
67c0d1eb RS |
6017 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6018 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6019 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6020 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6021 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6022 | |
6023 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6024 | ; |
f5040a92 AO |
6025 | else if (expr1.X_add_number >= -0x8000 |
6026 | && expr1.X_add_number < 0x8000) | |
6027 | { | |
67c0d1eb | 6028 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6029 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6030 | } |
ecd13cd3 | 6031 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
6032 | { |
6033 | int dreg; | |
6034 | ||
6035 | /* If we are going to add in a base register, and the | |
6036 | target register and the base register are the same, | |
6037 | then we are using AT as a temporary register. Since | |
6038 | we want to load the constant into AT, we add our | |
6039 | current AT (from the global offset table) and the | |
6040 | register into the register now, and pretend we were | |
6041 | not using a base register. */ | |
6042 | if (breg != treg) | |
6043 | dreg = tempreg; | |
6044 | else | |
6045 | { | |
9c2799c2 | 6046 | gas_assert (tempreg == AT); |
67c0d1eb | 6047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6048 | treg, AT, breg); |
f5040a92 | 6049 | dreg = treg; |
67c0d1eb | 6050 | add_breg_early = 1; |
f5040a92 AO |
6051 | } |
6052 | ||
f6a22291 | 6053 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6054 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6055 | |
f5040a92 AO |
6056 | used_at = 1; |
6057 | } | |
6058 | else | |
6059 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6060 | ||
4d7206a2 | 6061 | relax_switch (); |
f5040a92 | 6062 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6063 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6064 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6065 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6066 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6067 | if (add_breg_early) | |
f5040a92 | 6068 | { |
67c0d1eb | 6069 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6070 | treg, tempreg, breg); |
f5040a92 AO |
6071 | breg = 0; |
6072 | tempreg = treg; | |
6073 | } | |
4d7206a2 | 6074 | relax_end (); |
f5040a92 | 6075 | } |
252b5132 RH |
6076 | else |
6077 | abort (); | |
6078 | ||
6079 | if (breg != 0) | |
aed1a261 | 6080 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6081 | break; |
6082 | ||
52b6b6b9 JM |
6083 | case M_MSGSND: |
6084 | { | |
6085 | unsigned long temp = (treg << 16) | (0x01); | |
6086 | macro_build (NULL, "c2", "C", temp); | |
6087 | } | |
6088 | /* AT is not used, just return */ | |
6089 | return; | |
6090 | ||
6091 | case M_MSGLD: | |
6092 | { | |
6093 | unsigned long temp = (0x02); | |
6094 | macro_build (NULL, "c2", "C", temp); | |
6095 | } | |
6096 | /* AT is not used, just return */ | |
6097 | return; | |
6098 | ||
6099 | case M_MSGLD_T: | |
6100 | { | |
6101 | unsigned long temp = (treg << 16) | (0x02); | |
6102 | macro_build (NULL, "c2", "C", temp); | |
6103 | } | |
6104 | /* AT is not used, just return */ | |
6105 | return; | |
6106 | ||
6107 | case M_MSGWAIT: | |
6108 | macro_build (NULL, "c2", "C", 3); | |
6109 | /* AT is not used, just return */ | |
6110 | return; | |
6111 | ||
6112 | case M_MSGWAIT_T: | |
6113 | { | |
6114 | unsigned long temp = (treg << 16) | 0x03; | |
6115 | macro_build (NULL, "c2", "C", temp); | |
6116 | } | |
6117 | /* AT is not used, just return */ | |
6118 | return; | |
6119 | ||
252b5132 RH |
6120 | case M_J_A: |
6121 | /* The j instruction may not be used in PIC code, since it | |
6122 | requires an absolute address. We convert it to a b | |
6123 | instruction. */ | |
6124 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6125 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6126 | else |
67c0d1eb | 6127 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6128 | break; |
252b5132 RH |
6129 | |
6130 | /* The jal instructions must be handled as macros because when | |
6131 | generating PIC code they expand to multi-instruction | |
6132 | sequences. Normally they are simple instructions. */ | |
6133 | case M_JAL_1: | |
6134 | dreg = RA; | |
6135 | /* Fall through. */ | |
6136 | case M_JAL_2: | |
3e722fb5 | 6137 | if (mips_pic == NO_PIC) |
67c0d1eb | 6138 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6139 | else |
252b5132 RH |
6140 | { |
6141 | if (sreg != PIC_CALL_REG) | |
6142 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6143 | |
67c0d1eb | 6144 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6145 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6146 | { |
6478892d TS |
6147 | if (mips_cprestore_offset < 0) |
6148 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6149 | else | |
6150 | { | |
7a621144 DJ |
6151 | if (! mips_frame_reg_valid) |
6152 | { | |
6153 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6154 | /* Quiet this warning. */ | |
6155 | mips_frame_reg_valid = 1; | |
6156 | } | |
6157 | if (! mips_cprestore_valid) | |
6158 | { | |
6159 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6160 | /* Quiet this warning. */ | |
6161 | mips_cprestore_valid = 1; | |
6162 | } | |
6478892d | 6163 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6164 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6165 | mips_gp_register, |
256ab948 TS |
6166 | mips_frame_reg, |
6167 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6168 | } |
252b5132 RH |
6169 | } |
6170 | } | |
252b5132 | 6171 | |
8fc2e39e | 6172 | break; |
252b5132 RH |
6173 | |
6174 | case M_JAL_A: | |
6175 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6176 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6177 | else if (mips_pic == SVR4_PIC) |
6178 | { | |
6179 | /* If this is a reference to an external symbol, and we are | |
6180 | using a small GOT, we want | |
6181 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6182 | nop | |
f9419b05 | 6183 | jalr $ra,$25 |
252b5132 RH |
6184 | nop |
6185 | lw $gp,cprestore($sp) | |
6186 | The cprestore value is set using the .cprestore | |
6187 | pseudo-op. If we are using a big GOT, we want | |
6188 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6189 | addu $25,$25,$gp | |
6190 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6191 | nop | |
f9419b05 | 6192 | jalr $ra,$25 |
252b5132 RH |
6193 | nop |
6194 | lw $gp,cprestore($sp) | |
6195 | If the symbol is not external, we want | |
6196 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6197 | nop | |
6198 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6199 | jalr $ra,$25 |
252b5132 | 6200 | nop |
438c16b8 | 6201 | lw $gp,cprestore($sp) |
f5040a92 AO |
6202 | |
6203 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6204 | sequences above, minus nops, unless the symbol is local, | |
6205 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6206 | GOT_DISP. */ | |
438c16b8 | 6207 | if (HAVE_NEWABI) |
252b5132 | 6208 | { |
f5040a92 AO |
6209 | if (! mips_big_got) |
6210 | { | |
4d7206a2 | 6211 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6212 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6213 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6214 | mips_gp_register); |
4d7206a2 | 6215 | relax_switch (); |
67c0d1eb RS |
6216 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6217 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6218 | mips_gp_register); |
6219 | relax_end (); | |
f5040a92 AO |
6220 | } |
6221 | else | |
6222 | { | |
4d7206a2 | 6223 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6224 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6225 | BFD_RELOC_MIPS_CALL_HI16); | |
6226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6227 | PIC_CALL_REG, mips_gp_register); | |
6228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6229 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6230 | PIC_CALL_REG); | |
4d7206a2 | 6231 | relax_switch (); |
67c0d1eb RS |
6232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6233 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6234 | mips_gp_register); | |
6235 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6236 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6237 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6238 | relax_end (); |
f5040a92 | 6239 | } |
684022ea | 6240 | |
67c0d1eb | 6241 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6242 | } |
6243 | else | |
6244 | { | |
4d7206a2 | 6245 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6246 | if (! mips_big_got) |
6247 | { | |
67c0d1eb RS |
6248 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6249 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6250 | mips_gp_register); |
269137b2 | 6251 | load_delay_nop (); |
4d7206a2 | 6252 | relax_switch (); |
438c16b8 | 6253 | } |
252b5132 | 6254 | else |
252b5132 | 6255 | { |
67c0d1eb RS |
6256 | int gpdelay; |
6257 | ||
6258 | gpdelay = reg_needs_delay (mips_gp_register); | |
6259 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6260 | BFD_RELOC_MIPS_CALL_HI16); | |
6261 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6262 | PIC_CALL_REG, mips_gp_register); | |
6263 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6264 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6265 | PIC_CALL_REG); | |
269137b2 | 6266 | load_delay_nop (); |
4d7206a2 | 6267 | relax_switch (); |
67c0d1eb RS |
6268 | if (gpdelay) |
6269 | macro_build (NULL, "nop", ""); | |
252b5132 | 6270 | } |
67c0d1eb RS |
6271 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6272 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6273 | mips_gp_register); |
269137b2 | 6274 | load_delay_nop (); |
67c0d1eb RS |
6275 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6276 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6277 | relax_end (); |
67c0d1eb | 6278 | macro_build_jalr (&offset_expr); |
438c16b8 | 6279 | |
6478892d TS |
6280 | if (mips_cprestore_offset < 0) |
6281 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6282 | else | |
6283 | { | |
7a621144 DJ |
6284 | if (! mips_frame_reg_valid) |
6285 | { | |
6286 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6287 | /* Quiet this warning. */ | |
6288 | mips_frame_reg_valid = 1; | |
6289 | } | |
6290 | if (! mips_cprestore_valid) | |
6291 | { | |
6292 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6293 | /* Quiet this warning. */ | |
6294 | mips_cprestore_valid = 1; | |
6295 | } | |
6478892d | 6296 | if (mips_opts.noreorder) |
67c0d1eb | 6297 | macro_build (NULL, "nop", ""); |
6478892d | 6298 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6299 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6300 | mips_gp_register, |
256ab948 TS |
6301 | mips_frame_reg, |
6302 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6303 | } |
252b5132 RH |
6304 | } |
6305 | } | |
0a44bf69 RS |
6306 | else if (mips_pic == VXWORKS_PIC) |
6307 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6308 | else |
6309 | abort (); | |
6310 | ||
8fc2e39e | 6311 | break; |
252b5132 RH |
6312 | |
6313 | case M_LB_AB: | |
6314 | s = "lb"; | |
6315 | goto ld; | |
6316 | case M_LBU_AB: | |
6317 | s = "lbu"; | |
6318 | goto ld; | |
6319 | case M_LH_AB: | |
6320 | s = "lh"; | |
6321 | goto ld; | |
6322 | case M_LHU_AB: | |
6323 | s = "lhu"; | |
6324 | goto ld; | |
6325 | case M_LW_AB: | |
6326 | s = "lw"; | |
6327 | goto ld; | |
6328 | case M_LWC0_AB: | |
6329 | s = "lwc0"; | |
bdaaa2e1 | 6330 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6331 | coproc = 1; |
6332 | goto ld; | |
6333 | case M_LWC1_AB: | |
6334 | s = "lwc1"; | |
bdaaa2e1 | 6335 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6336 | coproc = 1; |
6337 | goto ld; | |
6338 | case M_LWC2_AB: | |
6339 | s = "lwc2"; | |
bdaaa2e1 | 6340 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6341 | coproc = 1; |
6342 | goto ld; | |
6343 | case M_LWC3_AB: | |
6344 | s = "lwc3"; | |
bdaaa2e1 | 6345 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6346 | coproc = 1; |
6347 | goto ld; | |
6348 | case M_LWL_AB: | |
6349 | s = "lwl"; | |
6350 | lr = 1; | |
6351 | goto ld; | |
6352 | case M_LWR_AB: | |
6353 | s = "lwr"; | |
6354 | lr = 1; | |
6355 | goto ld; | |
6356 | case M_LDC1_AB: | |
252b5132 | 6357 | s = "ldc1"; |
bdaaa2e1 | 6358 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6359 | coproc = 1; |
6360 | goto ld; | |
6361 | case M_LDC2_AB: | |
6362 | s = "ldc2"; | |
bdaaa2e1 | 6363 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6364 | coproc = 1; |
6365 | goto ld; | |
6366 | case M_LDC3_AB: | |
6367 | s = "ldc3"; | |
bdaaa2e1 | 6368 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6369 | coproc = 1; |
6370 | goto ld; | |
6371 | case M_LDL_AB: | |
6372 | s = "ldl"; | |
6373 | lr = 1; | |
6374 | goto ld; | |
6375 | case M_LDR_AB: | |
6376 | s = "ldr"; | |
6377 | lr = 1; | |
6378 | goto ld; | |
6379 | case M_LL_AB: | |
6380 | s = "ll"; | |
6381 | goto ld; | |
6382 | case M_LLD_AB: | |
6383 | s = "lld"; | |
6384 | goto ld; | |
6385 | case M_LWU_AB: | |
6386 | s = "lwu"; | |
6387 | ld: | |
8fc2e39e | 6388 | if (breg == treg || coproc || lr) |
252b5132 RH |
6389 | { |
6390 | tempreg = AT; | |
6391 | used_at = 1; | |
6392 | } | |
6393 | else | |
6394 | { | |
6395 | tempreg = treg; | |
252b5132 RH |
6396 | } |
6397 | goto ld_st; | |
6398 | case M_SB_AB: | |
6399 | s = "sb"; | |
6400 | goto st; | |
6401 | case M_SH_AB: | |
6402 | s = "sh"; | |
6403 | goto st; | |
6404 | case M_SW_AB: | |
6405 | s = "sw"; | |
6406 | goto st; | |
6407 | case M_SWC0_AB: | |
6408 | s = "swc0"; | |
bdaaa2e1 | 6409 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6410 | coproc = 1; |
6411 | goto st; | |
6412 | case M_SWC1_AB: | |
6413 | s = "swc1"; | |
bdaaa2e1 | 6414 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6415 | coproc = 1; |
6416 | goto st; | |
6417 | case M_SWC2_AB: | |
6418 | s = "swc2"; | |
bdaaa2e1 | 6419 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6420 | coproc = 1; |
6421 | goto st; | |
6422 | case M_SWC3_AB: | |
6423 | s = "swc3"; | |
bdaaa2e1 | 6424 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6425 | coproc = 1; |
6426 | goto st; | |
6427 | case M_SWL_AB: | |
6428 | s = "swl"; | |
6429 | goto st; | |
6430 | case M_SWR_AB: | |
6431 | s = "swr"; | |
6432 | goto st; | |
6433 | case M_SC_AB: | |
6434 | s = "sc"; | |
6435 | goto st; | |
6436 | case M_SCD_AB: | |
6437 | s = "scd"; | |
6438 | goto st; | |
d43b4baf TS |
6439 | case M_CACHE_AB: |
6440 | s = "cache"; | |
6441 | goto st; | |
252b5132 | 6442 | case M_SDC1_AB: |
252b5132 RH |
6443 | s = "sdc1"; |
6444 | coproc = 1; | |
bdaaa2e1 | 6445 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6446 | goto st; |
6447 | case M_SDC2_AB: | |
6448 | s = "sdc2"; | |
bdaaa2e1 | 6449 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6450 | coproc = 1; |
6451 | goto st; | |
6452 | case M_SDC3_AB: | |
6453 | s = "sdc3"; | |
bdaaa2e1 | 6454 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6455 | coproc = 1; |
6456 | goto st; | |
6457 | case M_SDL_AB: | |
6458 | s = "sdl"; | |
6459 | goto st; | |
6460 | case M_SDR_AB: | |
6461 | s = "sdr"; | |
6462 | st: | |
8fc2e39e TS |
6463 | tempreg = AT; |
6464 | used_at = 1; | |
252b5132 | 6465 | ld_st: |
b19e8a9b AN |
6466 | if (coproc |
6467 | && NO_ISA_COP (mips_opts.arch) | |
6468 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6469 | { | |
6470 | as_bad (_("opcode not supported on this processor: %s"), | |
6471 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
6472 | break; | |
6473 | } | |
6474 | ||
bdaaa2e1 | 6475 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6476 | if (mask == M_LWC1_AB |
6477 | || mask == M_SWC1_AB | |
6478 | || mask == M_LDC1_AB | |
6479 | || mask == M_SDC1_AB | |
6480 | || mask == M_L_DAB | |
6481 | || mask == M_S_DAB) | |
6482 | fmt = "T,o(b)"; | |
d43b4baf TS |
6483 | else if (mask == M_CACHE_AB) |
6484 | fmt = "k,o(b)"; | |
252b5132 RH |
6485 | else if (coproc) |
6486 | fmt = "E,o(b)"; | |
6487 | else | |
6488 | fmt = "t,o(b)"; | |
6489 | ||
6490 | if (offset_expr.X_op != O_constant | |
6491 | && offset_expr.X_op != O_symbol) | |
6492 | { | |
6493 | as_bad (_("expression too complex")); | |
6494 | offset_expr.X_op = O_constant; | |
6495 | } | |
6496 | ||
2051e8c4 MR |
6497 | if (HAVE_32BIT_ADDRESSES |
6498 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6499 | { |
6500 | char value [32]; | |
6501 | ||
6502 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6503 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6504 | } |
2051e8c4 | 6505 | |
252b5132 RH |
6506 | /* A constant expression in PIC code can be handled just as it |
6507 | is in non PIC code. */ | |
aed1a261 RS |
6508 | if (offset_expr.X_op == O_constant) |
6509 | { | |
aed1a261 RS |
6510 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6511 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6512 | normalize_address_expr (&expr1); |
aed1a261 RS |
6513 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6514 | if (breg != 0) | |
6515 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6516 | tempreg, tempreg, breg); | |
6517 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6518 | } | |
6519 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6520 | { |
6521 | /* If this is a reference to a GP relative symbol, and there | |
6522 | is no base register, we want | |
cdf6fd85 | 6523 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6524 | Otherwise, if there is no base register, we want |
6525 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6526 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6527 | If we have a constant, we need two instructions anyhow, | |
6528 | so we always use the latter form. | |
6529 | ||
6530 | If we have a base register, and this is a reference to a | |
6531 | GP relative symbol, we want | |
6532 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6533 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6534 | Otherwise we want |
6535 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6536 | addu $tempreg,$tempreg,$breg | |
6537 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6538 | With a constant we always use the latter case. |
76b3015f | 6539 | |
d6bc6245 TS |
6540 | With 64bit address space and no base register and $at usable, |
6541 | we want | |
6542 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6543 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6544 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6545 | dsll32 $tempreg,0 | |
6546 | daddu $tempreg,$at | |
6547 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6548 | If we have a base register, we want | |
6549 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6550 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6551 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6552 | daddu $at,$breg | |
6553 | dsll32 $tempreg,0 | |
6554 | daddu $tempreg,$at | |
6555 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6556 | ||
6557 | Without $at we can't generate the optimal path for superscalar | |
6558 | processors here since this would require two temporary registers. | |
6559 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6560 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6561 | dsll $tempreg,16 | |
6562 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6563 | dsll $tempreg,16 | |
6564 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6565 | If we have a base register, we want | |
6566 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6567 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6568 | dsll $tempreg,16 | |
6569 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6570 | dsll $tempreg,16 | |
6571 | daddu $tempreg,$tempreg,$breg | |
6572 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6573 | |
6caf9ef4 | 6574 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6575 | the same sequence as in 32bit address space. */ |
6576 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6577 | { |
aed1a261 | 6578 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6579 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6580 | { | |
6581 | relax_start (offset_expr.X_add_symbol); | |
6582 | if (breg == 0) | |
6583 | { | |
6584 | macro_build (&offset_expr, s, fmt, treg, | |
6585 | BFD_RELOC_GPREL16, mips_gp_register); | |
6586 | } | |
6587 | else | |
6588 | { | |
6589 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6590 | tempreg, breg, mips_gp_register); | |
6591 | macro_build (&offset_expr, s, fmt, treg, | |
6592 | BFD_RELOC_GPREL16, tempreg); | |
6593 | } | |
6594 | relax_switch (); | |
6595 | } | |
d6bc6245 | 6596 | |
741fe287 | 6597 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6598 | { |
67c0d1eb RS |
6599 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6600 | BFD_RELOC_MIPS_HIGHEST); | |
6601 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6602 | BFD_RELOC_HI16_S); | |
6603 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6604 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6605 | if (breg != 0) |
67c0d1eb RS |
6606 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6607 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6608 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6609 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6610 | tempreg); | |
d6bc6245 TS |
6611 | used_at = 1; |
6612 | } | |
6613 | else | |
6614 | { | |
67c0d1eb RS |
6615 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6616 | BFD_RELOC_MIPS_HIGHEST); | |
6617 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6618 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6619 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6620 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6621 | tempreg, BFD_RELOC_HI16_S); | |
6622 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6623 | if (breg != 0) |
67c0d1eb | 6624 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6625 | tempreg, tempreg, breg); |
67c0d1eb | 6626 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6627 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6628 | } |
6caf9ef4 TS |
6629 | |
6630 | if (mips_relax.sequence) | |
6631 | relax_end (); | |
8fc2e39e | 6632 | break; |
d6bc6245 | 6633 | } |
256ab948 | 6634 | |
252b5132 RH |
6635 | if (breg == 0) |
6636 | { | |
67c0d1eb | 6637 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6638 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6639 | { |
4d7206a2 | 6640 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6641 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6642 | mips_gp_register); | |
4d7206a2 | 6643 | relax_switch (); |
252b5132 | 6644 | } |
67c0d1eb RS |
6645 | macro_build_lui (&offset_expr, tempreg); |
6646 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6647 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6648 | if (mips_relax.sequence) |
6649 | relax_end (); | |
252b5132 RH |
6650 | } |
6651 | else | |
6652 | { | |
67c0d1eb | 6653 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6654 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6655 | { |
4d7206a2 | 6656 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6658 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6659 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6660 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6661 | relax_switch (); |
252b5132 | 6662 | } |
67c0d1eb RS |
6663 | macro_build_lui (&offset_expr, tempreg); |
6664 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6665 | tempreg, tempreg, breg); |
67c0d1eb | 6666 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6667 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6668 | if (mips_relax.sequence) |
6669 | relax_end (); | |
252b5132 RH |
6670 | } |
6671 | } | |
0a44bf69 | 6672 | else if (!mips_big_got) |
252b5132 | 6673 | { |
ed6fb7bd | 6674 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6675 | |
252b5132 RH |
6676 | /* If this is a reference to an external symbol, we want |
6677 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6678 | nop | |
6679 | <op> $treg,0($tempreg) | |
6680 | Otherwise we want | |
6681 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6682 | nop | |
6683 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6684 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6685 | |
6686 | For NewABI, we want | |
6687 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6688 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6689 | ||
252b5132 RH |
6690 | If there is a base register, we add it to $tempreg before |
6691 | the <op>. If there is a constant, we stick it in the | |
6692 | <op> instruction. We don't handle constants larger than | |
6693 | 16 bits, because we have no way to load the upper 16 bits | |
6694 | (actually, we could handle them for the subset of cases | |
6695 | in which we are not using $at). */ | |
9c2799c2 | 6696 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6697 | if (HAVE_NEWABI) |
6698 | { | |
67c0d1eb RS |
6699 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6700 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6701 | if (breg != 0) |
67c0d1eb | 6702 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6703 | tempreg, tempreg, breg); |
67c0d1eb | 6704 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6705 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6706 | break; |
6707 | } | |
252b5132 RH |
6708 | expr1.X_add_number = offset_expr.X_add_number; |
6709 | offset_expr.X_add_number = 0; | |
6710 | if (expr1.X_add_number < -0x8000 | |
6711 | || expr1.X_add_number >= 0x8000) | |
6712 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6713 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6714 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6715 | load_delay_nop (); |
4d7206a2 RS |
6716 | relax_start (offset_expr.X_add_symbol); |
6717 | relax_switch (); | |
67c0d1eb RS |
6718 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6719 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6720 | relax_end (); |
252b5132 | 6721 | if (breg != 0) |
67c0d1eb | 6722 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6723 | tempreg, tempreg, breg); |
67c0d1eb | 6724 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6725 | } |
0a44bf69 | 6726 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6727 | { |
67c0d1eb | 6728 | int gpdelay; |
252b5132 RH |
6729 | |
6730 | /* If this is a reference to an external symbol, we want | |
6731 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6732 | addu $tempreg,$tempreg,$gp | |
6733 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6734 | <op> $treg,0($tempreg) | |
6735 | Otherwise we want | |
6736 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6737 | nop | |
6738 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6739 | <op> $treg,0($tempreg) | |
6740 | If there is a base register, we add it to $tempreg before | |
6741 | the <op>. If there is a constant, we stick it in the | |
6742 | <op> instruction. We don't handle constants larger than | |
6743 | 16 bits, because we have no way to load the upper 16 bits | |
6744 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6745 | in which we are not using $at). */ |
9c2799c2 | 6746 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6747 | expr1.X_add_number = offset_expr.X_add_number; |
6748 | offset_expr.X_add_number = 0; | |
6749 | if (expr1.X_add_number < -0x8000 | |
6750 | || expr1.X_add_number >= 0x8000) | |
6751 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6752 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6753 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6754 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6755 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6756 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6757 | mips_gp_register); | |
6758 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6759 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6760 | relax_switch (); |
67c0d1eb RS |
6761 | if (gpdelay) |
6762 | macro_build (NULL, "nop", ""); | |
6763 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6764 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6765 | load_delay_nop (); |
67c0d1eb RS |
6766 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6767 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6768 | relax_end (); |
6769 | ||
252b5132 | 6770 | if (breg != 0) |
67c0d1eb | 6771 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6772 | tempreg, tempreg, breg); |
67c0d1eb | 6773 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6774 | } |
0a44bf69 | 6775 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6776 | { |
f5040a92 AO |
6777 | /* If this is a reference to an external symbol, we want |
6778 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6779 | add $tempreg,$tempreg,$gp | |
6780 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6781 | <op> $treg,<ofst>($tempreg) | |
6782 | Otherwise, for local symbols, we want: | |
6783 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6784 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6785 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6786 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6787 | offset_expr.X_add_number = 0; |
6788 | if (expr1.X_add_number < -0x8000 | |
6789 | || expr1.X_add_number >= 0x8000) | |
6790 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6791 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6792 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6793 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6794 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6795 | mips_gp_register); | |
6796 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6797 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6798 | if (breg != 0) |
67c0d1eb | 6799 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6800 | tempreg, tempreg, breg); |
67c0d1eb | 6801 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6802 | |
4d7206a2 | 6803 | relax_switch (); |
f5040a92 | 6804 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6805 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6806 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6807 | if (breg != 0) |
67c0d1eb | 6808 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6809 | tempreg, tempreg, breg); |
67c0d1eb | 6810 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6811 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6812 | relax_end (); |
f5040a92 | 6813 | } |
252b5132 RH |
6814 | else |
6815 | abort (); | |
6816 | ||
252b5132 RH |
6817 | break; |
6818 | ||
6819 | case M_LI: | |
6820 | case M_LI_S: | |
67c0d1eb | 6821 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6822 | break; |
252b5132 RH |
6823 | |
6824 | case M_DLI: | |
67c0d1eb | 6825 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6826 | break; |
252b5132 RH |
6827 | |
6828 | case M_LI_SS: | |
6829 | if (imm_expr.X_op == O_constant) | |
6830 | { | |
8fc2e39e | 6831 | used_at = 1; |
67c0d1eb RS |
6832 | load_register (AT, &imm_expr, 0); |
6833 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6834 | break; |
6835 | } | |
6836 | else | |
6837 | { | |
9c2799c2 | 6838 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
6839 | && strcmp (segment_name (S_GET_SEGMENT |
6840 | (offset_expr.X_add_symbol)), | |
6841 | ".lit4") == 0 | |
6842 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6843 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6844 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6845 | break; |
252b5132 RH |
6846 | } |
6847 | ||
6848 | case M_LI_D: | |
ca4e0257 RS |
6849 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6850 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6851 | order 32 bits of the value and the low order 32 bits are either | |
6852 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6853 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6854 | { | |
ca4e0257 | 6855 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6856 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6857 | else |
6858 | { | |
6859 | int hreg, lreg; | |
6860 | ||
6861 | if (target_big_endian) | |
6862 | { | |
6863 | hreg = treg; | |
6864 | lreg = treg + 1; | |
6865 | } | |
6866 | else | |
6867 | { | |
6868 | hreg = treg + 1; | |
6869 | lreg = treg; | |
6870 | } | |
6871 | ||
6872 | if (hreg <= 31) | |
67c0d1eb | 6873 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6874 | if (lreg <= 31) |
6875 | { | |
6876 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6877 | move_register (lreg, 0); |
252b5132 RH |
6878 | else |
6879 | { | |
9c2799c2 | 6880 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6881 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6882 | } |
6883 | } | |
6884 | } | |
8fc2e39e | 6885 | break; |
252b5132 RH |
6886 | } |
6887 | ||
6888 | /* We know that sym is in the .rdata section. First we get the | |
6889 | upper 16 bits of the address. */ | |
6890 | if (mips_pic == NO_PIC) | |
6891 | { | |
67c0d1eb | 6892 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6893 | used_at = 1; |
252b5132 | 6894 | } |
0a44bf69 | 6895 | else |
252b5132 | 6896 | { |
67c0d1eb RS |
6897 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6898 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6899 | used_at = 1; |
252b5132 | 6900 | } |
bdaaa2e1 | 6901 | |
252b5132 | 6902 | /* Now we load the register(s). */ |
ca4e0257 | 6903 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6904 | { |
6905 | used_at = 1; | |
6906 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6907 | } | |
252b5132 RH |
6908 | else |
6909 | { | |
8fc2e39e | 6910 | used_at = 1; |
67c0d1eb | 6911 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6912 | if (treg != RA) |
252b5132 RH |
6913 | { |
6914 | /* FIXME: How in the world do we deal with the possible | |
6915 | overflow here? */ | |
6916 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6917 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6918 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6919 | } |
6920 | } | |
252b5132 RH |
6921 | break; |
6922 | ||
6923 | case M_LI_DD: | |
ca4e0257 RS |
6924 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6925 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6926 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6927 | the value and the low order 32 bits are either zero or in | |
6928 | OFFSET_EXPR. */ | |
252b5132 RH |
6929 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6930 | { | |
8fc2e39e | 6931 | used_at = 1; |
67c0d1eb | 6932 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6933 | if (HAVE_64BIT_FPRS) |
6934 | { | |
9c2799c2 | 6935 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 6936 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6937 | } |
252b5132 RH |
6938 | else |
6939 | { | |
67c0d1eb | 6940 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6941 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6942 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6943 | else |
6944 | { | |
9c2799c2 | 6945 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
6946 | load_register (AT, &offset_expr, 0); |
6947 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6948 | } |
6949 | } | |
6950 | break; | |
6951 | } | |
6952 | ||
9c2799c2 | 6953 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
6954 | && offset_expr.X_add_number == 0); |
6955 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6956 | if (strcmp (s, ".lit8") == 0) | |
6957 | { | |
e7af610e | 6958 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6959 | { |
67c0d1eb | 6960 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6961 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6962 | break; |
252b5132 | 6963 | } |
c9914766 | 6964 | breg = mips_gp_register; |
252b5132 RH |
6965 | r = BFD_RELOC_MIPS_LITERAL; |
6966 | goto dob; | |
6967 | } | |
6968 | else | |
6969 | { | |
9c2799c2 | 6970 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 6971 | used_at = 1; |
0a44bf69 | 6972 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6973 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6974 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6975 | else |
6976 | { | |
6977 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6978 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6979 | } |
bdaaa2e1 | 6980 | |
e7af610e | 6981 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6982 | { |
67c0d1eb RS |
6983 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6984 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6985 | break; |
6986 | } | |
6987 | breg = AT; | |
6988 | r = BFD_RELOC_LO16; | |
6989 | goto dob; | |
6990 | } | |
6991 | ||
6992 | case M_L_DOB: | |
252b5132 RH |
6993 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6994 | to adjust when loading from memory. */ | |
6995 | r = BFD_RELOC_LO16; | |
6996 | dob: | |
9c2799c2 | 6997 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6998 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6999 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7000 | /* FIXME: A possible overflow which I don't know how to deal |
7001 | with. */ | |
7002 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7003 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7004 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7005 | break; |
7006 | ||
7007 | case M_L_DAB: | |
7008 | /* | |
7009 | * The MIPS assembler seems to check for X_add_number not | |
7010 | * being double aligned and generating: | |
7011 | * lui at,%hi(foo+1) | |
7012 | * addu at,at,v1 | |
7013 | * addiu at,at,%lo(foo+1) | |
7014 | * lwc1 f2,0(at) | |
7015 | * lwc1 f3,4(at) | |
7016 | * But, the resulting address is the same after relocation so why | |
7017 | * generate the extra instruction? | |
7018 | */ | |
bdaaa2e1 | 7019 | /* Itbl support may require additional care here. */ |
252b5132 | 7020 | coproc = 1; |
e7af610e | 7021 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7022 | { |
7023 | s = "ldc1"; | |
7024 | goto ld; | |
7025 | } | |
7026 | ||
7027 | s = "lwc1"; | |
7028 | fmt = "T,o(b)"; | |
7029 | goto ldd_std; | |
7030 | ||
7031 | case M_S_DAB: | |
e7af610e | 7032 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7033 | { |
7034 | s = "sdc1"; | |
7035 | goto st; | |
7036 | } | |
7037 | ||
7038 | s = "swc1"; | |
7039 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7040 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7041 | coproc = 1; |
7042 | goto ldd_std; | |
7043 | ||
7044 | case M_LD_AB: | |
ca4e0257 | 7045 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7046 | { |
7047 | s = "ld"; | |
7048 | goto ld; | |
7049 | } | |
7050 | ||
7051 | s = "lw"; | |
7052 | fmt = "t,o(b)"; | |
7053 | goto ldd_std; | |
7054 | ||
7055 | case M_SD_AB: | |
ca4e0257 | 7056 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7057 | { |
7058 | s = "sd"; | |
7059 | goto st; | |
7060 | } | |
7061 | ||
7062 | s = "sw"; | |
7063 | fmt = "t,o(b)"; | |
7064 | ||
7065 | ldd_std: | |
7066 | if (offset_expr.X_op != O_symbol | |
7067 | && offset_expr.X_op != O_constant) | |
7068 | { | |
7069 | as_bad (_("expression too complex")); | |
7070 | offset_expr.X_op = O_constant; | |
7071 | } | |
7072 | ||
2051e8c4 MR |
7073 | if (HAVE_32BIT_ADDRESSES |
7074 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7075 | { |
7076 | char value [32]; | |
7077 | ||
7078 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7079 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7080 | } |
2051e8c4 | 7081 | |
252b5132 RH |
7082 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7083 | to adjust when loading from memory. We set coproc if we must | |
7084 | load $fn+1 first. */ | |
bdaaa2e1 | 7085 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7086 | if (! target_big_endian) |
7087 | coproc = 0; | |
7088 | ||
7089 | if (mips_pic == NO_PIC | |
7090 | || offset_expr.X_op == O_constant) | |
7091 | { | |
7092 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7093 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7094 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7095 | If we have a base register, we use this |
7096 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7097 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7098 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7099 | If this is not a GP relative symbol, we want |
7100 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7101 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7102 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7103 | If there is a base register, we add it to $at after the | |
7104 | lui instruction. If there is a constant, we always use | |
7105 | the last case. */ | |
39a59cf8 MR |
7106 | if (offset_expr.X_op == O_symbol |
7107 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7108 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7109 | { |
4d7206a2 | 7110 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7111 | if (breg == 0) |
7112 | { | |
c9914766 | 7113 | tempreg = mips_gp_register; |
252b5132 RH |
7114 | } |
7115 | else | |
7116 | { | |
67c0d1eb | 7117 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7118 | AT, breg, mips_gp_register); |
252b5132 | 7119 | tempreg = AT; |
252b5132 RH |
7120 | used_at = 1; |
7121 | } | |
7122 | ||
beae10d5 | 7123 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7124 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7125 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7126 | offset_expr.X_add_number += 4; |
7127 | ||
7128 | /* Set mips_optimize to 2 to avoid inserting an | |
7129 | undesired nop. */ | |
7130 | hold_mips_optimize = mips_optimize; | |
7131 | mips_optimize = 2; | |
beae10d5 | 7132 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7133 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7134 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7135 | mips_optimize = hold_mips_optimize; |
7136 | ||
4d7206a2 | 7137 | relax_switch (); |
252b5132 RH |
7138 | |
7139 | /* We just generated two relocs. When tc_gen_reloc | |
7140 | handles this case, it will skip the first reloc and | |
7141 | handle the second. The second reloc already has an | |
7142 | extra addend of 4, which we added above. We must | |
7143 | subtract it out, and then subtract another 4 to make | |
7144 | the first reloc come out right. The second reloc | |
7145 | will come out right because we are going to add 4 to | |
7146 | offset_expr when we build its instruction below. | |
7147 | ||
7148 | If we have a symbol, then we don't want to include | |
7149 | the offset, because it will wind up being included | |
7150 | when we generate the reloc. */ | |
7151 | ||
7152 | if (offset_expr.X_op == O_constant) | |
7153 | offset_expr.X_add_number -= 8; | |
7154 | else | |
7155 | { | |
7156 | offset_expr.X_add_number = -4; | |
7157 | offset_expr.X_op = O_constant; | |
7158 | } | |
7159 | } | |
8fc2e39e | 7160 | used_at = 1; |
67c0d1eb | 7161 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7162 | if (breg != 0) |
67c0d1eb | 7163 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7164 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7165 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7166 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7167 | /* FIXME: How do we handle overflow here? */ |
7168 | offset_expr.X_add_number += 4; | |
beae10d5 | 7169 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7170 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7171 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7172 | if (mips_relax.sequence) |
7173 | relax_end (); | |
bdaaa2e1 | 7174 | } |
0a44bf69 | 7175 | else if (!mips_big_got) |
252b5132 | 7176 | { |
252b5132 RH |
7177 | /* If this is a reference to an external symbol, we want |
7178 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7179 | nop | |
7180 | <op> $treg,0($at) | |
7181 | <op> $treg+1,4($at) | |
7182 | Otherwise we want | |
7183 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7184 | nop | |
7185 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7186 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7187 | If there is a base register we add it to $at before the | |
7188 | lwc1 instructions. If there is a constant we include it | |
7189 | in the lwc1 instructions. */ | |
7190 | used_at = 1; | |
7191 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7192 | if (expr1.X_add_number < -0x8000 |
7193 | || expr1.X_add_number >= 0x8000 - 4) | |
7194 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7195 | load_got_offset (AT, &offset_expr); |
269137b2 | 7196 | load_delay_nop (); |
252b5132 | 7197 | if (breg != 0) |
67c0d1eb | 7198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7199 | |
7200 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7201 | nop. */ | |
7202 | hold_mips_optimize = mips_optimize; | |
7203 | mips_optimize = 2; | |
4d7206a2 | 7204 | |
beae10d5 | 7205 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7206 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7207 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7208 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7209 | expr1.X_add_number += 4; |
67c0d1eb RS |
7210 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7211 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7212 | relax_switch (); |
67c0d1eb RS |
7213 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7214 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7215 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7216 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7217 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7218 | relax_end (); |
252b5132 | 7219 | |
4d7206a2 | 7220 | mips_optimize = hold_mips_optimize; |
252b5132 | 7221 | } |
0a44bf69 | 7222 | else if (mips_big_got) |
252b5132 | 7223 | { |
67c0d1eb | 7224 | int gpdelay; |
252b5132 RH |
7225 | |
7226 | /* If this is a reference to an external symbol, we want | |
7227 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7228 | addu $at,$at,$gp | |
7229 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7230 | nop | |
7231 | <op> $treg,0($at) | |
7232 | <op> $treg+1,4($at) | |
7233 | Otherwise we want | |
7234 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7235 | nop | |
7236 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7237 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7238 | If there is a base register we add it to $at before the | |
7239 | lwc1 instructions. If there is a constant we include it | |
7240 | in the lwc1 instructions. */ | |
7241 | used_at = 1; | |
7242 | expr1.X_add_number = offset_expr.X_add_number; | |
7243 | offset_expr.X_add_number = 0; | |
7244 | if (expr1.X_add_number < -0x8000 | |
7245 | || expr1.X_add_number >= 0x8000 - 4) | |
7246 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7247 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7248 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7249 | macro_build (&offset_expr, "lui", "t,u", |
7250 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7251 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7252 | AT, AT, mips_gp_register); |
67c0d1eb | 7253 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7254 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7255 | load_delay_nop (); |
252b5132 | 7256 | if (breg != 0) |
67c0d1eb | 7257 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7258 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7259 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7260 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7261 | expr1.X_add_number += 4; |
7262 | ||
7263 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7264 | nop. */ | |
7265 | hold_mips_optimize = mips_optimize; | |
7266 | mips_optimize = 2; | |
beae10d5 | 7267 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7268 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7269 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7270 | mips_optimize = hold_mips_optimize; |
7271 | expr1.X_add_number -= 4; | |
7272 | ||
4d7206a2 RS |
7273 | relax_switch (); |
7274 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7275 | if (gpdelay) |
7276 | macro_build (NULL, "nop", ""); | |
7277 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7278 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7279 | load_delay_nop (); |
252b5132 | 7280 | if (breg != 0) |
67c0d1eb | 7281 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7282 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7283 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7284 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7285 | offset_expr.X_add_number += 4; |
252b5132 RH |
7286 | |
7287 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7288 | nop. */ | |
7289 | hold_mips_optimize = mips_optimize; | |
7290 | mips_optimize = 2; | |
beae10d5 | 7291 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7292 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7293 | BFD_RELOC_LO16, AT); | |
252b5132 | 7294 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7295 | relax_end (); |
252b5132 | 7296 | } |
252b5132 RH |
7297 | else |
7298 | abort (); | |
7299 | ||
252b5132 RH |
7300 | break; |
7301 | ||
7302 | case M_LD_OB: | |
7303 | s = "lw"; | |
7304 | goto sd_ob; | |
7305 | case M_SD_OB: | |
7306 | s = "sw"; | |
7307 | sd_ob: | |
9c2799c2 | 7308 | gas_assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7309 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7310 | offset_expr.X_add_number += 4; |
67c0d1eb | 7311 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7312 | break; |
252b5132 RH |
7313 | |
7314 | /* New code added to support COPZ instructions. | |
7315 | This code builds table entries out of the macros in mip_opcodes. | |
7316 | R4000 uses interlocks to handle coproc delays. | |
7317 | Other chips (like the R3000) require nops to be inserted for delays. | |
7318 | ||
f72c8c98 | 7319 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7320 | In order to fill delay slots for non-interlocked chips, |
7321 | we must have a way to specify delays based on the coprocessor. | |
7322 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7323 | What are the side-effects of the cop instruction? | |
7324 | What cache support might we have and what are its effects? | |
7325 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7326 | What registers are read/set/modified? |
252b5132 RH |
7327 | |
7328 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7329 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7330 | |
7331 | case M_COP0: | |
7332 | s = "c0"; | |
7333 | goto copz; | |
7334 | case M_COP1: | |
7335 | s = "c1"; | |
7336 | goto copz; | |
7337 | case M_COP2: | |
7338 | s = "c2"; | |
7339 | goto copz; | |
7340 | case M_COP3: | |
7341 | s = "c3"; | |
7342 | copz: | |
b19e8a9b AN |
7343 | if (NO_ISA_COP (mips_opts.arch) |
7344 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7345 | { | |
7346 | as_bad (_("opcode not supported on this processor: %s"), | |
7347 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7348 | break; | |
7349 | } | |
7350 | ||
252b5132 RH |
7351 | /* For now we just do C (same as Cz). The parameter will be |
7352 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7353 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7354 | break; |
252b5132 | 7355 | |
ea1fb5dc | 7356 | case M_MOVE: |
67c0d1eb | 7357 | move_register (dreg, sreg); |
8fc2e39e | 7358 | break; |
ea1fb5dc | 7359 | |
252b5132 RH |
7360 | #ifdef LOSING_COMPILER |
7361 | default: | |
7362 | /* Try and see if this is a new itbl instruction. | |
7363 | This code builds table entries out of the macros in mip_opcodes. | |
7364 | FIXME: For now we just assemble the expression and pass it's | |
7365 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7366 | We may want to have the assembler assemble this value, |
252b5132 RH |
7367 | so that we gain the assembler's knowledge of delay slots, |
7368 | symbols, etc. | |
7369 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7370 | if (itbl_have_entries |
252b5132 | 7371 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7372 | { |
252b5132 RH |
7373 | s = ip->insn_mo->name; |
7374 | s2 = "cop3"; | |
7375 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7376 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7377 | break; |
beae10d5 | 7378 | } |
252b5132 | 7379 | macro2 (ip); |
8fc2e39e | 7380 | break; |
252b5132 | 7381 | } |
741fe287 | 7382 | if (!mips_opts.at && used_at) |
8fc2e39e | 7383 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7384 | } |
bdaaa2e1 | 7385 | |
252b5132 | 7386 | static void |
17a2f251 | 7387 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7388 | { |
741fe287 MR |
7389 | unsigned int treg, sreg, dreg, breg; |
7390 | unsigned int tempreg; | |
252b5132 | 7391 | int mask; |
252b5132 RH |
7392 | int used_at; |
7393 | expressionS expr1; | |
7394 | const char *s; | |
7395 | const char *s2; | |
7396 | const char *fmt; | |
7397 | int likely = 0; | |
7398 | int dbl = 0; | |
7399 | int coproc = 0; | |
7400 | int lr = 0; | |
7401 | int imm = 0; | |
7402 | int off; | |
7403 | offsetT maxnum; | |
7404 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7405 | |
252b5132 RH |
7406 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7407 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7408 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7409 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7410 | |
252b5132 RH |
7411 | expr1.X_op = O_constant; |
7412 | expr1.X_op_symbol = NULL; | |
7413 | expr1.X_add_symbol = NULL; | |
7414 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7415 | |
252b5132 RH |
7416 | switch (mask) |
7417 | { | |
7418 | #endif /* LOSING_COMPILER */ | |
7419 | ||
7420 | case M_DMUL: | |
7421 | dbl = 1; | |
7422 | case M_MUL: | |
67c0d1eb RS |
7423 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7424 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7425 | break; |
252b5132 RH |
7426 | |
7427 | case M_DMUL_I: | |
7428 | dbl = 1; | |
7429 | case M_MUL_I: | |
7430 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7431 | not trying to be that fancy. GCC should do this for us | |
7432 | anyway. */ | |
8fc2e39e | 7433 | used_at = 1; |
67c0d1eb RS |
7434 | load_register (AT, &imm_expr, dbl); |
7435 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7436 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7437 | break; |
7438 | ||
7439 | case M_DMULO_I: | |
7440 | dbl = 1; | |
7441 | case M_MULO_I: | |
7442 | imm = 1; | |
7443 | goto do_mulo; | |
7444 | ||
7445 | case M_DMULO: | |
7446 | dbl = 1; | |
7447 | case M_MULO: | |
7448 | do_mulo: | |
7d10b47d | 7449 | start_noreorder (); |
8fc2e39e | 7450 | used_at = 1; |
252b5132 | 7451 | if (imm) |
67c0d1eb RS |
7452 | load_register (AT, &imm_expr, dbl); |
7453 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7454 | macro_build (NULL, "mflo", "d", dreg); | |
7455 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7456 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7457 | if (mips_trap) |
67c0d1eb | 7458 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7459 | else |
7460 | { | |
7461 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7462 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7463 | macro_build (NULL, "nop", "", 0); | |
7464 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7465 | } |
7d10b47d | 7466 | end_noreorder (); |
67c0d1eb | 7467 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7468 | break; |
7469 | ||
7470 | case M_DMULOU_I: | |
7471 | dbl = 1; | |
7472 | case M_MULOU_I: | |
7473 | imm = 1; | |
7474 | goto do_mulou; | |
7475 | ||
7476 | case M_DMULOU: | |
7477 | dbl = 1; | |
7478 | case M_MULOU: | |
7479 | do_mulou: | |
7d10b47d | 7480 | start_noreorder (); |
8fc2e39e | 7481 | used_at = 1; |
252b5132 | 7482 | if (imm) |
67c0d1eb RS |
7483 | load_register (AT, &imm_expr, dbl); |
7484 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7485 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7486 | macro_build (NULL, "mfhi", "d", AT); |
7487 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7488 | if (mips_trap) |
67c0d1eb | 7489 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7490 | else |
7491 | { | |
7492 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7493 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7494 | macro_build (NULL, "nop", "", 0); | |
7495 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7496 | } |
7d10b47d | 7497 | end_noreorder (); |
252b5132 RH |
7498 | break; |
7499 | ||
771c7ce4 | 7500 | case M_DROL: |
fef14a42 | 7501 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7502 | { |
7503 | if (dreg == sreg) | |
7504 | { | |
7505 | tempreg = AT; | |
7506 | used_at = 1; | |
7507 | } | |
7508 | else | |
7509 | { | |
7510 | tempreg = dreg; | |
82dd0097 | 7511 | } |
67c0d1eb RS |
7512 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7513 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7514 | break; |
82dd0097 | 7515 | } |
8fc2e39e | 7516 | used_at = 1; |
67c0d1eb RS |
7517 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7518 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7519 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7520 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7521 | break; |
7522 | ||
252b5132 | 7523 | case M_ROL: |
fef14a42 | 7524 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7525 | { |
7526 | if (dreg == sreg) | |
7527 | { | |
7528 | tempreg = AT; | |
7529 | used_at = 1; | |
7530 | } | |
7531 | else | |
7532 | { | |
7533 | tempreg = dreg; | |
82dd0097 | 7534 | } |
67c0d1eb RS |
7535 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7536 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7537 | break; |
82dd0097 | 7538 | } |
8fc2e39e | 7539 | used_at = 1; |
67c0d1eb RS |
7540 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7541 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7542 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7543 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7544 | break; |
7545 | ||
771c7ce4 TS |
7546 | case M_DROL_I: |
7547 | { | |
7548 | unsigned int rot; | |
82dd0097 | 7549 | char *l, *r; |
771c7ce4 TS |
7550 | |
7551 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7552 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7553 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7554 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7555 | { |
7556 | rot = (64 - rot) & 0x3f; | |
7557 | if (rot >= 32) | |
67c0d1eb | 7558 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7559 | else |
67c0d1eb | 7560 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7561 | break; |
60b63b72 | 7562 | } |
483fc7cd | 7563 | if (rot == 0) |
483fc7cd | 7564 | { |
67c0d1eb | 7565 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7566 | break; |
483fc7cd | 7567 | } |
82dd0097 CD |
7568 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7569 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7570 | rot &= 0x1f; | |
8fc2e39e | 7571 | used_at = 1; |
67c0d1eb RS |
7572 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7573 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7574 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7575 | } |
7576 | break; | |
7577 | ||
252b5132 | 7578 | case M_ROL_I: |
771c7ce4 TS |
7579 | { |
7580 | unsigned int rot; | |
7581 | ||
7582 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7583 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7584 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7585 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7586 | { |
67c0d1eb | 7587 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7588 | break; |
60b63b72 | 7589 | } |
483fc7cd | 7590 | if (rot == 0) |
483fc7cd | 7591 | { |
67c0d1eb | 7592 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7593 | break; |
483fc7cd | 7594 | } |
8fc2e39e | 7595 | used_at = 1; |
67c0d1eb RS |
7596 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7597 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7598 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7599 | } |
7600 | break; | |
7601 | ||
7602 | case M_DROR: | |
fef14a42 | 7603 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7604 | { |
67c0d1eb | 7605 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7606 | break; |
82dd0097 | 7607 | } |
8fc2e39e | 7608 | used_at = 1; |
67c0d1eb RS |
7609 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7610 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7611 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7612 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7613 | break; |
7614 | ||
7615 | case M_ROR: | |
fef14a42 | 7616 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7617 | { |
67c0d1eb | 7618 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7619 | break; |
82dd0097 | 7620 | } |
8fc2e39e | 7621 | used_at = 1; |
67c0d1eb RS |
7622 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7623 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7624 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7625 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7626 | break; |
7627 | ||
771c7ce4 TS |
7628 | case M_DROR_I: |
7629 | { | |
7630 | unsigned int rot; | |
82dd0097 | 7631 | char *l, *r; |
771c7ce4 TS |
7632 | |
7633 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7634 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7635 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7636 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7637 | { |
7638 | if (rot >= 32) | |
67c0d1eb | 7639 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7640 | else |
67c0d1eb | 7641 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7642 | break; |
82dd0097 | 7643 | } |
483fc7cd | 7644 | if (rot == 0) |
483fc7cd | 7645 | { |
67c0d1eb | 7646 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7647 | break; |
483fc7cd | 7648 | } |
82dd0097 CD |
7649 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7650 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7651 | rot &= 0x1f; | |
8fc2e39e | 7652 | used_at = 1; |
67c0d1eb RS |
7653 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7654 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7655 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7656 | } |
7657 | break; | |
7658 | ||
252b5132 | 7659 | case M_ROR_I: |
771c7ce4 TS |
7660 | { |
7661 | unsigned int rot; | |
7662 | ||
7663 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7664 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7665 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7666 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7667 | { |
67c0d1eb | 7668 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7669 | break; |
82dd0097 | 7670 | } |
483fc7cd | 7671 | if (rot == 0) |
483fc7cd | 7672 | { |
67c0d1eb | 7673 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7674 | break; |
483fc7cd | 7675 | } |
8fc2e39e | 7676 | used_at = 1; |
67c0d1eb RS |
7677 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7678 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7679 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7680 | } |
252b5132 RH |
7681 | break; |
7682 | ||
7683 | case M_S_DOB: | |
9c2799c2 | 7684 | gas_assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7685 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7686 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7687 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7688 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7689 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7690 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7691 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7692 | break; |
252b5132 RH |
7693 | |
7694 | case M_SEQ: | |
7695 | if (sreg == 0) | |
67c0d1eb | 7696 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7697 | else if (treg == 0) |
67c0d1eb | 7698 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7699 | else |
7700 | { | |
67c0d1eb RS |
7701 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7702 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7703 | } |
8fc2e39e | 7704 | break; |
252b5132 RH |
7705 | |
7706 | case M_SEQ_I: | |
7707 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7708 | { | |
67c0d1eb | 7709 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7710 | break; |
252b5132 RH |
7711 | } |
7712 | if (sreg == 0) | |
7713 | { | |
7714 | as_warn (_("Instruction %s: result is always false"), | |
7715 | ip->insn_mo->name); | |
67c0d1eb | 7716 | move_register (dreg, 0); |
8fc2e39e | 7717 | break; |
252b5132 | 7718 | } |
dd3cbb7e NC |
7719 | if (CPU_HAS_SEQ (mips_opts.arch) |
7720 | && -512 <= imm_expr.X_add_number | |
7721 | && imm_expr.X_add_number < 512) | |
7722 | { | |
7723 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7724 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7725 | break; |
7726 | } | |
252b5132 RH |
7727 | if (imm_expr.X_op == O_constant |
7728 | && imm_expr.X_add_number >= 0 | |
7729 | && imm_expr.X_add_number < 0x10000) | |
7730 | { | |
67c0d1eb | 7731 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7732 | } |
7733 | else if (imm_expr.X_op == O_constant | |
7734 | && imm_expr.X_add_number > -0x8000 | |
7735 | && imm_expr.X_add_number < 0) | |
7736 | { | |
7737 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7738 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7739 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7740 | } |
dd3cbb7e NC |
7741 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7742 | { | |
7743 | used_at = 1; | |
7744 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7745 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7746 | break; | |
7747 | } | |
252b5132 RH |
7748 | else |
7749 | { | |
67c0d1eb RS |
7750 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7751 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7752 | used_at = 1; |
7753 | } | |
67c0d1eb | 7754 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7755 | break; |
252b5132 RH |
7756 | |
7757 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7758 | s = "slt"; | |
7759 | goto sge; | |
7760 | case M_SGEU: | |
7761 | s = "sltu"; | |
7762 | sge: | |
67c0d1eb RS |
7763 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7764 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7765 | break; |
252b5132 RH |
7766 | |
7767 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7768 | case M_SGEU_I: | |
7769 | if (imm_expr.X_op == O_constant | |
7770 | && imm_expr.X_add_number >= -0x8000 | |
7771 | && imm_expr.X_add_number < 0x8000) | |
7772 | { | |
67c0d1eb RS |
7773 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7774 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7775 | } |
7776 | else | |
7777 | { | |
67c0d1eb RS |
7778 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7779 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7780 | dreg, sreg, AT); | |
252b5132 RH |
7781 | used_at = 1; |
7782 | } | |
67c0d1eb | 7783 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7784 | break; |
252b5132 RH |
7785 | |
7786 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7787 | s = "slt"; | |
7788 | goto sgt; | |
7789 | case M_SGTU: | |
7790 | s = "sltu"; | |
7791 | sgt: | |
67c0d1eb | 7792 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7793 | break; |
252b5132 RH |
7794 | |
7795 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7796 | s = "slt"; | |
7797 | goto sgti; | |
7798 | case M_SGTU_I: | |
7799 | s = "sltu"; | |
7800 | sgti: | |
8fc2e39e | 7801 | used_at = 1; |
67c0d1eb RS |
7802 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7803 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7804 | break; |
7805 | ||
2396cfb9 | 7806 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7807 | s = "slt"; |
7808 | goto sle; | |
7809 | case M_SLEU: | |
7810 | s = "sltu"; | |
7811 | sle: | |
67c0d1eb RS |
7812 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7813 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7814 | break; |
252b5132 | 7815 | |
2396cfb9 | 7816 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7817 | s = "slt"; |
7818 | goto slei; | |
7819 | case M_SLEU_I: | |
7820 | s = "sltu"; | |
7821 | slei: | |
8fc2e39e | 7822 | used_at = 1; |
67c0d1eb RS |
7823 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7824 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7825 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7826 | break; |
7827 | ||
7828 | case M_SLT_I: | |
7829 | if (imm_expr.X_op == O_constant | |
7830 | && imm_expr.X_add_number >= -0x8000 | |
7831 | && imm_expr.X_add_number < 0x8000) | |
7832 | { | |
67c0d1eb | 7833 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7834 | break; |
252b5132 | 7835 | } |
8fc2e39e | 7836 | used_at = 1; |
67c0d1eb RS |
7837 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7838 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7839 | break; |
7840 | ||
7841 | case M_SLTU_I: | |
7842 | if (imm_expr.X_op == O_constant | |
7843 | && imm_expr.X_add_number >= -0x8000 | |
7844 | && imm_expr.X_add_number < 0x8000) | |
7845 | { | |
67c0d1eb | 7846 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7847 | BFD_RELOC_LO16); |
8fc2e39e | 7848 | break; |
252b5132 | 7849 | } |
8fc2e39e | 7850 | used_at = 1; |
67c0d1eb RS |
7851 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7852 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7853 | break; |
7854 | ||
7855 | case M_SNE: | |
7856 | if (sreg == 0) | |
67c0d1eb | 7857 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7858 | else if (treg == 0) |
67c0d1eb | 7859 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7860 | else |
7861 | { | |
67c0d1eb RS |
7862 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7863 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7864 | } |
8fc2e39e | 7865 | break; |
252b5132 RH |
7866 | |
7867 | case M_SNE_I: | |
7868 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7869 | { | |
67c0d1eb | 7870 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7871 | break; |
252b5132 RH |
7872 | } |
7873 | if (sreg == 0) | |
7874 | { | |
7875 | as_warn (_("Instruction %s: result is always true"), | |
7876 | ip->insn_mo->name); | |
67c0d1eb RS |
7877 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7878 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7879 | break; |
252b5132 | 7880 | } |
dd3cbb7e NC |
7881 | if (CPU_HAS_SEQ (mips_opts.arch) |
7882 | && -512 <= imm_expr.X_add_number | |
7883 | && imm_expr.X_add_number < 512) | |
7884 | { | |
7885 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7886 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7887 | break; |
7888 | } | |
252b5132 RH |
7889 | if (imm_expr.X_op == O_constant |
7890 | && imm_expr.X_add_number >= 0 | |
7891 | && imm_expr.X_add_number < 0x10000) | |
7892 | { | |
67c0d1eb | 7893 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7894 | } |
7895 | else if (imm_expr.X_op == O_constant | |
7896 | && imm_expr.X_add_number > -0x8000 | |
7897 | && imm_expr.X_add_number < 0) | |
7898 | { | |
7899 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7900 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7901 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7902 | } |
dd3cbb7e NC |
7903 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7904 | { | |
7905 | used_at = 1; | |
7906 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7907 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7908 | break; | |
7909 | } | |
252b5132 RH |
7910 | else |
7911 | { | |
67c0d1eb RS |
7912 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7913 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7914 | used_at = 1; |
7915 | } | |
67c0d1eb | 7916 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7917 | break; |
252b5132 RH |
7918 | |
7919 | case M_DSUB_I: | |
7920 | dbl = 1; | |
7921 | case M_SUB_I: | |
7922 | if (imm_expr.X_op == O_constant | |
7923 | && imm_expr.X_add_number > -0x8000 | |
7924 | && imm_expr.X_add_number <= 0x8000) | |
7925 | { | |
7926 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7927 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7928 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7929 | break; |
252b5132 | 7930 | } |
8fc2e39e | 7931 | used_at = 1; |
67c0d1eb RS |
7932 | load_register (AT, &imm_expr, dbl); |
7933 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7934 | break; |
7935 | ||
7936 | case M_DSUBU_I: | |
7937 | dbl = 1; | |
7938 | case M_SUBU_I: | |
7939 | if (imm_expr.X_op == O_constant | |
7940 | && imm_expr.X_add_number > -0x8000 | |
7941 | && imm_expr.X_add_number <= 0x8000) | |
7942 | { | |
7943 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7944 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7945 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7946 | break; |
252b5132 | 7947 | } |
8fc2e39e | 7948 | used_at = 1; |
67c0d1eb RS |
7949 | load_register (AT, &imm_expr, dbl); |
7950 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7951 | break; |
7952 | ||
7953 | case M_TEQ_I: | |
7954 | s = "teq"; | |
7955 | goto trap; | |
7956 | case M_TGE_I: | |
7957 | s = "tge"; | |
7958 | goto trap; | |
7959 | case M_TGEU_I: | |
7960 | s = "tgeu"; | |
7961 | goto trap; | |
7962 | case M_TLT_I: | |
7963 | s = "tlt"; | |
7964 | goto trap; | |
7965 | case M_TLTU_I: | |
7966 | s = "tltu"; | |
7967 | goto trap; | |
7968 | case M_TNE_I: | |
7969 | s = "tne"; | |
7970 | trap: | |
8fc2e39e | 7971 | used_at = 1; |
67c0d1eb RS |
7972 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7973 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7974 | break; |
7975 | ||
252b5132 | 7976 | case M_TRUNCWS: |
43841e91 | 7977 | case M_TRUNCWD: |
9c2799c2 | 7978 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7979 | used_at = 1; |
252b5132 RH |
7980 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7981 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7982 | ||
7983 | /* | |
7984 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7985 | * or is there a reason for it? | |
7986 | */ | |
7d10b47d | 7987 | start_noreorder (); |
67c0d1eb RS |
7988 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7989 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7990 | macro_build (NULL, "nop", ""); | |
252b5132 | 7991 | expr1.X_add_number = 3; |
67c0d1eb | 7992 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7993 | expr1.X_add_number = 2; |
67c0d1eb RS |
7994 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7995 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7996 | macro_build (NULL, "nop", ""); | |
7997 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7998 | dreg, sreg); | |
7999 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8000 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8001 | end_noreorder (); |
252b5132 RH |
8002 | break; |
8003 | ||
8004 | case M_ULH: | |
8005 | s = "lb"; | |
8006 | goto ulh; | |
8007 | case M_ULHU: | |
8008 | s = "lbu"; | |
8009 | ulh: | |
8fc2e39e | 8010 | used_at = 1; |
252b5132 RH |
8011 | if (offset_expr.X_add_number >= 0x7fff) |
8012 | as_bad (_("operand overflow")); | |
252b5132 | 8013 | if (! target_big_endian) |
f9419b05 | 8014 | ++offset_expr.X_add_number; |
67c0d1eb | 8015 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 8016 | if (! target_big_endian) |
f9419b05 | 8017 | --offset_expr.X_add_number; |
252b5132 | 8018 | else |
f9419b05 | 8019 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8020 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8021 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8022 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8023 | break; |
8024 | ||
8025 | case M_ULD: | |
8026 | s = "ldl"; | |
8027 | s2 = "ldr"; | |
8028 | off = 7; | |
8029 | goto ulw; | |
8030 | case M_ULW: | |
8031 | s = "lwl"; | |
8032 | s2 = "lwr"; | |
8033 | off = 3; | |
8034 | ulw: | |
8035 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8036 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
8037 | if (treg != breg) |
8038 | tempreg = treg; | |
8039 | else | |
8fc2e39e TS |
8040 | { |
8041 | used_at = 1; | |
8042 | tempreg = AT; | |
8043 | } | |
252b5132 RH |
8044 | if (! target_big_endian) |
8045 | offset_expr.X_add_number += off; | |
67c0d1eb | 8046 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8047 | if (! target_big_endian) |
8048 | offset_expr.X_add_number -= off; | |
8049 | else | |
8050 | offset_expr.X_add_number += off; | |
67c0d1eb | 8051 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
8052 | |
8053 | /* If necessary, move the result in tempreg the final destination. */ | |
8054 | if (treg == tempreg) | |
8fc2e39e | 8055 | break; |
af22f5b2 | 8056 | /* Protect second load's delay slot. */ |
017315e4 | 8057 | load_delay_nop (); |
67c0d1eb | 8058 | move_register (treg, tempreg); |
af22f5b2 | 8059 | break; |
252b5132 RH |
8060 | |
8061 | case M_ULD_A: | |
8062 | s = "ldl"; | |
8063 | s2 = "ldr"; | |
8064 | off = 7; | |
8065 | goto ulwa; | |
8066 | case M_ULW_A: | |
8067 | s = "lwl"; | |
8068 | s2 = "lwr"; | |
8069 | off = 3; | |
8070 | ulwa: | |
d6bc6245 | 8071 | used_at = 1; |
67c0d1eb | 8072 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8073 | if (breg != 0) |
67c0d1eb | 8074 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8075 | if (! target_big_endian) |
8076 | expr1.X_add_number = off; | |
8077 | else | |
8078 | expr1.X_add_number = 0; | |
67c0d1eb | 8079 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8080 | if (! target_big_endian) |
8081 | expr1.X_add_number = 0; | |
8082 | else | |
8083 | expr1.X_add_number = off; | |
67c0d1eb | 8084 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8085 | break; |
8086 | ||
8087 | case M_ULH_A: | |
8088 | case M_ULHU_A: | |
d6bc6245 | 8089 | used_at = 1; |
67c0d1eb | 8090 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8091 | if (breg != 0) |
67c0d1eb | 8092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8093 | if (target_big_endian) |
8094 | expr1.X_add_number = 0; | |
67c0d1eb | 8095 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8096 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8097 | if (target_big_endian) |
8098 | expr1.X_add_number = 1; | |
8099 | else | |
8100 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8101 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8102 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8103 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8104 | break; |
8105 | ||
8106 | case M_USH: | |
8fc2e39e | 8107 | used_at = 1; |
252b5132 RH |
8108 | if (offset_expr.X_add_number >= 0x7fff) |
8109 | as_bad (_("operand overflow")); | |
8110 | if (target_big_endian) | |
f9419b05 | 8111 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8112 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8113 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8114 | if (target_big_endian) |
f9419b05 | 8115 | --offset_expr.X_add_number; |
252b5132 | 8116 | else |
f9419b05 | 8117 | ++offset_expr.X_add_number; |
67c0d1eb | 8118 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8119 | break; |
8120 | ||
8121 | case M_USD: | |
8122 | s = "sdl"; | |
8123 | s2 = "sdr"; | |
8124 | off = 7; | |
8125 | goto usw; | |
8126 | case M_USW: | |
8127 | s = "swl"; | |
8128 | s2 = "swr"; | |
8129 | off = 3; | |
8130 | usw: | |
8131 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8132 | as_bad (_("operand overflow")); | |
8133 | if (! target_big_endian) | |
8134 | offset_expr.X_add_number += off; | |
67c0d1eb | 8135 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8136 | if (! target_big_endian) |
8137 | offset_expr.X_add_number -= off; | |
8138 | else | |
8139 | offset_expr.X_add_number += off; | |
67c0d1eb | 8140 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8141 | break; |
252b5132 RH |
8142 | |
8143 | case M_USD_A: | |
8144 | s = "sdl"; | |
8145 | s2 = "sdr"; | |
8146 | off = 7; | |
8147 | goto uswa; | |
8148 | case M_USW_A: | |
8149 | s = "swl"; | |
8150 | s2 = "swr"; | |
8151 | off = 3; | |
8152 | uswa: | |
d6bc6245 | 8153 | used_at = 1; |
67c0d1eb | 8154 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8155 | if (breg != 0) |
67c0d1eb | 8156 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8157 | if (! target_big_endian) |
8158 | expr1.X_add_number = off; | |
8159 | else | |
8160 | expr1.X_add_number = 0; | |
67c0d1eb | 8161 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8162 | if (! target_big_endian) |
8163 | expr1.X_add_number = 0; | |
8164 | else | |
8165 | expr1.X_add_number = off; | |
67c0d1eb | 8166 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8167 | break; |
8168 | ||
8169 | case M_USH_A: | |
d6bc6245 | 8170 | used_at = 1; |
67c0d1eb | 8171 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8172 | if (breg != 0) |
67c0d1eb | 8173 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8174 | if (! target_big_endian) |
8175 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8176 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8177 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
8178 | if (! target_big_endian) |
8179 | expr1.X_add_number = 1; | |
8180 | else | |
8181 | expr1.X_add_number = 0; | |
67c0d1eb | 8182 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8183 | if (! target_big_endian) |
8184 | expr1.X_add_number = 0; | |
8185 | else | |
8186 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8187 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8188 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8189 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8190 | break; |
8191 | ||
8192 | default: | |
8193 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8194 | are added dynamically. */ |
252b5132 RH |
8195 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8196 | break; | |
8197 | } | |
741fe287 | 8198 | if (!mips_opts.at && used_at) |
8fc2e39e | 8199 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8200 | } |
8201 | ||
8202 | /* Implement macros in mips16 mode. */ | |
8203 | ||
8204 | static void | |
17a2f251 | 8205 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8206 | { |
8207 | int mask; | |
8208 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8209 | expressionS expr1; |
8210 | int dbl; | |
8211 | const char *s, *s2, *s3; | |
8212 | ||
8213 | mask = ip->insn_mo->mask; | |
8214 | ||
bf12938e RS |
8215 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8216 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8217 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8218 | |
252b5132 RH |
8219 | expr1.X_op = O_constant; |
8220 | expr1.X_op_symbol = NULL; | |
8221 | expr1.X_add_symbol = NULL; | |
8222 | expr1.X_add_number = 1; | |
8223 | ||
8224 | dbl = 0; | |
8225 | ||
8226 | switch (mask) | |
8227 | { | |
8228 | default: | |
8229 | internalError (); | |
8230 | ||
8231 | case M_DDIV_3: | |
8232 | dbl = 1; | |
8233 | case M_DIV_3: | |
8234 | s = "mflo"; | |
8235 | goto do_div3; | |
8236 | case M_DREM_3: | |
8237 | dbl = 1; | |
8238 | case M_REM_3: | |
8239 | s = "mfhi"; | |
8240 | do_div3: | |
7d10b47d | 8241 | start_noreorder (); |
67c0d1eb | 8242 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8243 | expr1.X_add_number = 2; |
67c0d1eb RS |
8244 | macro_build (&expr1, "bnez", "x,p", yreg); |
8245 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8246 | |
252b5132 RH |
8247 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8248 | since that causes an overflow. We should do that as well, | |
8249 | but I don't see how to do the comparisons without a temporary | |
8250 | register. */ | |
7d10b47d | 8251 | end_noreorder (); |
67c0d1eb | 8252 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8253 | break; |
8254 | ||
8255 | case M_DIVU_3: | |
8256 | s = "divu"; | |
8257 | s2 = "mflo"; | |
8258 | goto do_divu3; | |
8259 | case M_REMU_3: | |
8260 | s = "divu"; | |
8261 | s2 = "mfhi"; | |
8262 | goto do_divu3; | |
8263 | case M_DDIVU_3: | |
8264 | s = "ddivu"; | |
8265 | s2 = "mflo"; | |
8266 | goto do_divu3; | |
8267 | case M_DREMU_3: | |
8268 | s = "ddivu"; | |
8269 | s2 = "mfhi"; | |
8270 | do_divu3: | |
7d10b47d | 8271 | start_noreorder (); |
67c0d1eb | 8272 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8273 | expr1.X_add_number = 2; |
67c0d1eb RS |
8274 | macro_build (&expr1, "bnez", "x,p", yreg); |
8275 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8276 | end_noreorder (); |
67c0d1eb | 8277 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8278 | break; |
8279 | ||
8280 | case M_DMUL: | |
8281 | dbl = 1; | |
8282 | case M_MUL: | |
67c0d1eb RS |
8283 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8284 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8285 | break; |
252b5132 RH |
8286 | |
8287 | case M_DSUBU_I: | |
8288 | dbl = 1; | |
8289 | goto do_subu; | |
8290 | case M_SUBU_I: | |
8291 | do_subu: | |
8292 | if (imm_expr.X_op != O_constant) | |
8293 | as_bad (_("Unsupported large constant")); | |
8294 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8295 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8296 | break; |
8297 | ||
8298 | case M_SUBU_I_2: | |
8299 | if (imm_expr.X_op != O_constant) | |
8300 | as_bad (_("Unsupported large constant")); | |
8301 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8302 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8303 | break; |
8304 | ||
8305 | case M_DSUBU_I_2: | |
8306 | if (imm_expr.X_op != O_constant) | |
8307 | as_bad (_("Unsupported large constant")); | |
8308 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8309 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8310 | break; |
8311 | ||
8312 | case M_BEQ: | |
8313 | s = "cmp"; | |
8314 | s2 = "bteqz"; | |
8315 | goto do_branch; | |
8316 | case M_BNE: | |
8317 | s = "cmp"; | |
8318 | s2 = "btnez"; | |
8319 | goto do_branch; | |
8320 | case M_BLT: | |
8321 | s = "slt"; | |
8322 | s2 = "btnez"; | |
8323 | goto do_branch; | |
8324 | case M_BLTU: | |
8325 | s = "sltu"; | |
8326 | s2 = "btnez"; | |
8327 | goto do_branch; | |
8328 | case M_BLE: | |
8329 | s = "slt"; | |
8330 | s2 = "bteqz"; | |
8331 | goto do_reverse_branch; | |
8332 | case M_BLEU: | |
8333 | s = "sltu"; | |
8334 | s2 = "bteqz"; | |
8335 | goto do_reverse_branch; | |
8336 | case M_BGE: | |
8337 | s = "slt"; | |
8338 | s2 = "bteqz"; | |
8339 | goto do_branch; | |
8340 | case M_BGEU: | |
8341 | s = "sltu"; | |
8342 | s2 = "bteqz"; | |
8343 | goto do_branch; | |
8344 | case M_BGT: | |
8345 | s = "slt"; | |
8346 | s2 = "btnez"; | |
8347 | goto do_reverse_branch; | |
8348 | case M_BGTU: | |
8349 | s = "sltu"; | |
8350 | s2 = "btnez"; | |
8351 | ||
8352 | do_reverse_branch: | |
8353 | tmp = xreg; | |
8354 | xreg = yreg; | |
8355 | yreg = tmp; | |
8356 | ||
8357 | do_branch: | |
67c0d1eb RS |
8358 | macro_build (NULL, s, "x,y", xreg, yreg); |
8359 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8360 | break; |
8361 | ||
8362 | case M_BEQ_I: | |
8363 | s = "cmpi"; | |
8364 | s2 = "bteqz"; | |
8365 | s3 = "x,U"; | |
8366 | goto do_branch_i; | |
8367 | case M_BNE_I: | |
8368 | s = "cmpi"; | |
8369 | s2 = "btnez"; | |
8370 | s3 = "x,U"; | |
8371 | goto do_branch_i; | |
8372 | case M_BLT_I: | |
8373 | s = "slti"; | |
8374 | s2 = "btnez"; | |
8375 | s3 = "x,8"; | |
8376 | goto do_branch_i; | |
8377 | case M_BLTU_I: | |
8378 | s = "sltiu"; | |
8379 | s2 = "btnez"; | |
8380 | s3 = "x,8"; | |
8381 | goto do_branch_i; | |
8382 | case M_BLE_I: | |
8383 | s = "slti"; | |
8384 | s2 = "btnez"; | |
8385 | s3 = "x,8"; | |
8386 | goto do_addone_branch_i; | |
8387 | case M_BLEU_I: | |
8388 | s = "sltiu"; | |
8389 | s2 = "btnez"; | |
8390 | s3 = "x,8"; | |
8391 | goto do_addone_branch_i; | |
8392 | case M_BGE_I: | |
8393 | s = "slti"; | |
8394 | s2 = "bteqz"; | |
8395 | s3 = "x,8"; | |
8396 | goto do_branch_i; | |
8397 | case M_BGEU_I: | |
8398 | s = "sltiu"; | |
8399 | s2 = "bteqz"; | |
8400 | s3 = "x,8"; | |
8401 | goto do_branch_i; | |
8402 | case M_BGT_I: | |
8403 | s = "slti"; | |
8404 | s2 = "bteqz"; | |
8405 | s3 = "x,8"; | |
8406 | goto do_addone_branch_i; | |
8407 | case M_BGTU_I: | |
8408 | s = "sltiu"; | |
8409 | s2 = "bteqz"; | |
8410 | s3 = "x,8"; | |
8411 | ||
8412 | do_addone_branch_i: | |
8413 | if (imm_expr.X_op != O_constant) | |
8414 | as_bad (_("Unsupported large constant")); | |
8415 | ++imm_expr.X_add_number; | |
8416 | ||
8417 | do_branch_i: | |
67c0d1eb RS |
8418 | macro_build (&imm_expr, s, s3, xreg); |
8419 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8420 | break; |
8421 | ||
8422 | case M_ABS: | |
8423 | expr1.X_add_number = 0; | |
67c0d1eb | 8424 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8425 | if (xreg != yreg) |
67c0d1eb | 8426 | move_register (xreg, yreg); |
252b5132 | 8427 | expr1.X_add_number = 2; |
67c0d1eb RS |
8428 | macro_build (&expr1, "bteqz", "p"); |
8429 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8430 | } |
8431 | } | |
8432 | ||
8433 | /* For consistency checking, verify that all bits are specified either | |
8434 | by the match/mask part of the instruction definition, or by the | |
8435 | operand list. */ | |
8436 | static int | |
17a2f251 | 8437 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8438 | { |
8439 | const char *p = opc->args; | |
8440 | char c; | |
8441 | unsigned long used_bits = opc->mask; | |
8442 | ||
8443 | if ((used_bits & opc->match) != opc->match) | |
8444 | { | |
8445 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8446 | opc->name, opc->args); | |
8447 | return 0; | |
8448 | } | |
8449 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8450 | while (*p) | |
8451 | switch (c = *p++) | |
8452 | { | |
8453 | case ',': break; | |
8454 | case '(': break; | |
8455 | case ')': break; | |
af7ee8bf CD |
8456 | case '+': |
8457 | switch (c = *p++) | |
8458 | { | |
9bcd4f99 TS |
8459 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8460 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8461 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8462 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8463 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8464 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8465 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8466 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8467 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8468 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8469 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8470 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8471 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8472 | case 'I': break; | |
ef2e4d86 CF |
8473 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8474 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8475 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8476 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8477 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8478 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8479 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8480 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8481 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8482 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
8483 | ||
af7ee8bf CD |
8484 | default: |
8485 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8486 | c, opc->name, opc->args); | |
8487 | return 0; | |
8488 | } | |
8489 | break; | |
252b5132 RH |
8490 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8491 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8492 | case 'A': break; | |
4372b673 | 8493 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8494 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8495 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8496 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8497 | case 'F': break; | |
8498 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8499 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8500 | case 'I': break; |
e972090a | 8501 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8502 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8503 | case 'L': break; |
8504 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8505 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8506 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8507 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8508 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8509 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8510 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8511 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8512 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8513 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8514 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8515 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8516 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8517 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8518 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8519 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8520 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8521 | case 'f': break; | |
8522 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8523 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8524 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8525 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8526 | case 'l': break; | |
8527 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8528 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8529 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8530 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8531 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8532 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8533 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8534 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8535 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8536 | case 'x': break; | |
8537 | case 'z': break; | |
8538 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8539 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8540 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8541 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8542 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8543 | case '[': break; | |
8544 | case ']': break; | |
620edafd | 8545 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8546 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8547 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8548 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8549 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8550 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8551 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8552 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8553 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8554 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8555 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8556 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8557 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8558 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8559 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8560 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8561 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8562 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8563 | default: |
8564 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8565 | c, opc->name, opc->args); | |
8566 | return 0; | |
8567 | } | |
8568 | #undef USE_BITS | |
8569 | if (used_bits != 0xffffffff) | |
8570 | { | |
8571 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8572 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8573 | return 0; | |
8574 | } | |
8575 | return 1; | |
8576 | } | |
8577 | ||
9bcd4f99 TS |
8578 | /* UDI immediates. */ |
8579 | struct mips_immed { | |
8580 | char type; | |
8581 | unsigned int shift; | |
8582 | unsigned long mask; | |
8583 | const char * desc; | |
8584 | }; | |
8585 | ||
8586 | static const struct mips_immed mips_immed[] = { | |
8587 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8588 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8589 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8590 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8591 | { 0,0,0,0 } | |
8592 | }; | |
8593 | ||
7455baf8 TS |
8594 | /* Check whether an odd floating-point register is allowed. */ |
8595 | static int | |
8596 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8597 | { | |
8598 | const char *s = insn->name; | |
8599 | ||
8600 | if (insn->pinfo == INSN_MACRO) | |
8601 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8602 | return 1; | |
8603 | ||
8604 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8605 | { | |
8606 | /* Allow odd registers for single-precision ops. */ | |
8607 | switch (insn->pinfo & (FP_S | FP_D)) | |
8608 | { | |
8609 | case FP_S: | |
8610 | case 0: | |
8611 | return 1; /* both single precision - ok */ | |
8612 | case FP_D: | |
8613 | return 0; /* both double precision - fail */ | |
8614 | default: | |
8615 | break; | |
8616 | } | |
8617 | ||
8618 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8619 | s = strchr (insn->name, '.'); | |
8620 | if (argnum == 2) | |
8621 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8622 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8623 | } | |
8624 | ||
8625 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8626 | if ((insn->pinfo & FP_S) | |
8627 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8628 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8629 | return 1; | |
8630 | ||
8631 | return 0; | |
8632 | } | |
8633 | ||
252b5132 RH |
8634 | /* This routine assembles an instruction into its binary format. As a |
8635 | side effect, it sets one of the global variables imm_reloc or | |
8636 | offset_reloc to the type of relocation to do if one of the operands | |
8637 | is an address expression. */ | |
8638 | ||
8639 | static void | |
17a2f251 | 8640 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8641 | { |
8642 | char *s; | |
8643 | const char *args; | |
43841e91 | 8644 | char c = 0; |
252b5132 RH |
8645 | struct mips_opcode *insn; |
8646 | char *argsStart; | |
8647 | unsigned int regno; | |
8648 | unsigned int lastregno = 0; | |
af7ee8bf | 8649 | unsigned int lastpos = 0; |
071742cf | 8650 | unsigned int limlo, limhi; |
252b5132 RH |
8651 | char *s_reset; |
8652 | char save_c = 0; | |
74cd071d | 8653 | offsetT min_range, max_range; |
707bfff6 TS |
8654 | int argnum; |
8655 | unsigned int rtype; | |
252b5132 RH |
8656 | |
8657 | insn_error = NULL; | |
8658 | ||
8659 | /* If the instruction contains a '.', we first try to match an instruction | |
8660 | including the '.'. Then we try again without the '.'. */ | |
8661 | insn = NULL; | |
3882b010 | 8662 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8663 | continue; |
8664 | ||
8665 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8666 | the call to hash_find. Save the character we replaced just in case we | |
8667 | have to re-parse the instruction. */ | |
3882b010 | 8668 | if (ISSPACE (*s)) |
252b5132 RH |
8669 | { |
8670 | save_c = *s; | |
8671 | *s++ = '\0'; | |
8672 | } | |
bdaaa2e1 | 8673 | |
252b5132 RH |
8674 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8675 | ||
8676 | /* If we didn't find the instruction in the opcode table, try again, but | |
8677 | this time with just the instruction up to, but not including the | |
8678 | first '.'. */ | |
8679 | if (insn == NULL) | |
8680 | { | |
bdaaa2e1 | 8681 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8682 | if (save_c) |
8683 | *(--s) = save_c; | |
8684 | ||
8685 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8686 | for (s = str; |
8687 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8688 | ++s) | |
252b5132 RH |
8689 | continue; |
8690 | ||
8691 | /* If we did not find a '.', then we can quit now. */ | |
8692 | if (*s != '.') | |
8693 | { | |
20203fb9 | 8694 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8695 | return; |
8696 | } | |
8697 | ||
8698 | /* Lookup the instruction in the hash table. */ | |
8699 | *s++ = '\0'; | |
8700 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8701 | { | |
20203fb9 | 8702 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8703 | return; |
8704 | } | |
252b5132 RH |
8705 | } |
8706 | ||
8707 | argsStart = s; | |
8708 | for (;;) | |
8709 | { | |
b34976b6 | 8710 | bfd_boolean ok; |
252b5132 | 8711 | |
9c2799c2 | 8712 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8713 | |
037b32b9 | 8714 | ok = is_opcode_valid (insn, FALSE); |
252b5132 RH |
8715 | if (! ok) |
8716 | { | |
8717 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8718 | && strcmp (insn->name, insn[1].name) == 0) | |
8719 | { | |
8720 | ++insn; | |
8721 | continue; | |
8722 | } | |
252b5132 | 8723 | else |
beae10d5 | 8724 | { |
268f6bed L |
8725 | if (!insn_error) |
8726 | { | |
8727 | static char buf[100]; | |
fef14a42 TS |
8728 | sprintf (buf, |
8729 | _("opcode not supported on this processor: %s (%s)"), | |
8730 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8731 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8732 | insn_error = buf; |
8733 | } | |
8734 | if (save_c) | |
8735 | *(--s) = save_c; | |
2bd7f1f3 | 8736 | return; |
252b5132 | 8737 | } |
252b5132 RH |
8738 | } |
8739 | ||
1e915849 | 8740 | create_insn (ip, insn); |
268f6bed | 8741 | insn_error = NULL; |
707bfff6 | 8742 | argnum = 1; |
24864476 | 8743 | lastregno = 0xffffffff; |
252b5132 RH |
8744 | for (args = insn->args;; ++args) |
8745 | { | |
deec1734 CD |
8746 | int is_mdmx; |
8747 | ||
ad8d3bb3 | 8748 | s += strspn (s, " \t"); |
deec1734 | 8749 | is_mdmx = 0; |
252b5132 RH |
8750 | switch (*args) |
8751 | { | |
8752 | case '\0': /* end of args */ | |
8753 | if (*s == '\0') | |
8754 | return; | |
8755 | break; | |
8756 | ||
8b082fb1 TS |
8757 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8758 | my_getExpression (&imm_expr, s); | |
8759 | check_absolute_expr (ip, &imm_expr); | |
8760 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8761 | && (unsigned long) imm_expr.X_add_number != 3) | |
8762 | { | |
8763 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8764 | (unsigned long) imm_expr.X_add_number); | |
8765 | } | |
8766 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8767 | imm_expr.X_op = O_absent; | |
8768 | s = expr_end; | |
8769 | continue; | |
8770 | ||
74cd071d CF |
8771 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8772 | my_getExpression (&imm_expr, s); | |
8773 | check_absolute_expr (ip, &imm_expr); | |
8774 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8775 | { | |
a9e24354 TS |
8776 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8777 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8778 | } |
a9e24354 | 8779 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8780 | imm_expr.X_op = O_absent; |
8781 | s = expr_end; | |
8782 | continue; | |
8783 | ||
8784 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8785 | my_getExpression (&imm_expr, s); | |
8786 | check_absolute_expr (ip, &imm_expr); | |
8787 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8788 | { | |
a9e24354 TS |
8789 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8790 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8791 | } |
a9e24354 | 8792 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8793 | imm_expr.X_op = O_absent; |
8794 | s = expr_end; | |
8795 | continue; | |
8796 | ||
8797 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8798 | my_getExpression (&imm_expr, s); | |
8799 | check_absolute_expr (ip, &imm_expr); | |
8800 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8801 | { | |
a9e24354 TS |
8802 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8803 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8804 | } |
a9e24354 | 8805 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8806 | imm_expr.X_op = O_absent; |
8807 | s = expr_end; | |
8808 | continue; | |
8809 | ||
8810 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8811 | my_getExpression (&imm_expr, s); | |
8812 | check_absolute_expr (ip, &imm_expr); | |
8813 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8814 | { | |
a9e24354 TS |
8815 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8816 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8817 | } |
a9e24354 | 8818 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8819 | imm_expr.X_op = O_absent; |
8820 | s = expr_end; | |
8821 | continue; | |
8822 | ||
8823 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8824 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8825 | s[3] >= '0' && s[3] <= '3') | |
8826 | { | |
8827 | regno = s[3] - '0'; | |
8828 | s += 4; | |
a9e24354 | 8829 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8830 | continue; |
8831 | } | |
8832 | else | |
8833 | as_bad (_("Invalid dsp acc register")); | |
8834 | break; | |
8835 | ||
8836 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8837 | my_getExpression (&imm_expr, s); | |
8838 | check_absolute_expr (ip, &imm_expr); | |
8839 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8840 | { | |
a9e24354 TS |
8841 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8842 | OP_MASK_WRDSP, | |
8843 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8844 | } |
a9e24354 | 8845 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8846 | imm_expr.X_op = O_absent; |
8847 | s = expr_end; | |
8848 | continue; | |
8849 | ||
8850 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8851 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8852 | s[3] >= '0' && s[3] <= '3') | |
8853 | { | |
8854 | regno = s[3] - '0'; | |
8855 | s += 4; | |
a9e24354 | 8856 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8857 | continue; |
8858 | } | |
8859 | else | |
8860 | as_bad (_("Invalid dsp acc register")); | |
8861 | break; | |
8862 | ||
8863 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8864 | my_getExpression (&imm_expr, s); | |
8865 | check_absolute_expr (ip, &imm_expr); | |
8866 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8867 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8868 | if (imm_expr.X_add_number < min_range || | |
8869 | imm_expr.X_add_number > max_range) | |
8870 | { | |
a9e24354 TS |
8871 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8872 | (long) min_range, (long) max_range, | |
8873 | (long) imm_expr.X_add_number); | |
74cd071d | 8874 | } |
a9e24354 | 8875 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8876 | imm_expr.X_op = O_absent; |
8877 | s = expr_end; | |
8878 | continue; | |
8879 | ||
8880 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8881 | my_getExpression (&imm_expr, s); | |
8882 | check_absolute_expr (ip, &imm_expr); | |
8883 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8884 | { | |
a9e24354 TS |
8885 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8886 | OP_MASK_RDDSP, | |
8887 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8888 | } |
a9e24354 | 8889 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8890 | imm_expr.X_op = O_absent; |
8891 | s = expr_end; | |
8892 | continue; | |
8893 | ||
8894 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8895 | my_getExpression (&imm_expr, s); | |
8896 | check_absolute_expr (ip, &imm_expr); | |
8897 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8898 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8899 | if (imm_expr.X_add_number < min_range || | |
8900 | imm_expr.X_add_number > max_range) | |
8901 | { | |
a9e24354 TS |
8902 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8903 | (long) min_range, (long) max_range, | |
8904 | (long) imm_expr.X_add_number); | |
74cd071d | 8905 | } |
a9e24354 | 8906 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8907 | imm_expr.X_op = O_absent; |
8908 | s = expr_end; | |
8909 | continue; | |
8910 | ||
8911 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8912 | my_getExpression (&imm_expr, s); | |
8913 | check_absolute_expr (ip, &imm_expr); | |
8914 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8915 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8916 | if (imm_expr.X_add_number < min_range || | |
8917 | imm_expr.X_add_number > max_range) | |
8918 | { | |
a9e24354 TS |
8919 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8920 | (long) min_range, (long) max_range, | |
8921 | (long) imm_expr.X_add_number); | |
74cd071d | 8922 | } |
a9e24354 | 8923 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8924 | imm_expr.X_op = O_absent; |
8925 | s = expr_end; | |
8926 | continue; | |
8927 | ||
a9e24354 | 8928 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8929 | my_getExpression (&imm_expr, s); |
8930 | check_absolute_expr (ip, &imm_expr); | |
8931 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8932 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8933 | (unsigned long) imm_expr.X_add_number); | |
8934 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8935 | imm_expr.X_op = O_absent; |
8936 | s = expr_end; | |
8937 | continue; | |
8938 | ||
a9e24354 | 8939 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8940 | my_getExpression (&imm_expr, s); |
8941 | check_absolute_expr (ip, &imm_expr); | |
8942 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8943 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8944 | (unsigned long) imm_expr.X_add_number); | |
8945 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8946 | imm_expr.X_op = O_absent; |
8947 | s = expr_end; | |
8948 | continue; | |
8949 | ||
8950 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8951 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8952 | s[3] >= '0' && s[3] <= '3') | |
8953 | { | |
8954 | regno = s[3] - '0'; | |
8955 | s += 4; | |
a9e24354 | 8956 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8957 | continue; |
8958 | } | |
8959 | else | |
8960 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8961 | break; | |
8962 | ||
8963 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8964 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8965 | s[3] >= '0' && s[3] <= '3') | |
8966 | { | |
8967 | regno = s[3] - '0'; | |
8968 | s += 4; | |
a9e24354 | 8969 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8970 | continue; |
8971 | } | |
8972 | else | |
8973 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8974 | break; | |
8975 | ||
252b5132 | 8976 | case ',': |
a339155f | 8977 | ++argnum; |
252b5132 RH |
8978 | if (*s++ == *args) |
8979 | continue; | |
8980 | s--; | |
8981 | switch (*++args) | |
8982 | { | |
8983 | case 'r': | |
8984 | case 'v': | |
bf12938e | 8985 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8986 | continue; |
8987 | ||
8988 | case 'w': | |
bf12938e | 8989 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8990 | continue; |
8991 | ||
252b5132 | 8992 | case 'W': |
bf12938e | 8993 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8994 | continue; |
8995 | ||
8996 | case 'V': | |
bf12938e | 8997 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8998 | continue; |
8999 | } | |
9000 | break; | |
9001 | ||
9002 | case '(': | |
9003 | /* Handle optional base register. | |
9004 | Either the base register is omitted or | |
bdaaa2e1 | 9005 | we must have a left paren. */ |
252b5132 RH |
9006 | /* This is dependent on the next operand specifier |
9007 | is a base register specification. */ | |
9c2799c2 | 9008 | gas_assert (args[1] == 'b' || args[1] == '5' |
252b5132 RH |
9009 | || args[1] == '-' || args[1] == '4'); |
9010 | if (*s == '\0') | |
9011 | return; | |
9012 | ||
9013 | case ')': /* these must match exactly */ | |
60b63b72 RS |
9014 | case '[': |
9015 | case ']': | |
252b5132 RH |
9016 | if (*s++ == *args) |
9017 | continue; | |
9018 | break; | |
9019 | ||
af7ee8bf CD |
9020 | case '+': /* Opcode extension character. */ |
9021 | switch (*++args) | |
9022 | { | |
9bcd4f99 TS |
9023 | case '1': /* UDI immediates. */ |
9024 | case '2': | |
9025 | case '3': | |
9026 | case '4': | |
9027 | { | |
9028 | const struct mips_immed *imm = mips_immed; | |
9029 | ||
9030 | while (imm->type && imm->type != *args) | |
9031 | ++imm; | |
9032 | if (! imm->type) | |
9033 | internalError (); | |
9034 | my_getExpression (&imm_expr, s); | |
9035 | check_absolute_expr (ip, &imm_expr); | |
9036 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9037 | { | |
9038 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9039 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9040 | (unsigned long) imm_expr.X_add_number, | |
9041 | (unsigned long) imm_expr.X_add_number); | |
9042 | imm_expr.X_add_number &= imm->mask; | |
9043 | } | |
9044 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9045 | << imm->shift); | |
9046 | imm_expr.X_op = O_absent; | |
9047 | s = expr_end; | |
9048 | } | |
9049 | continue; | |
9050 | ||
071742cf CD |
9051 | case 'A': /* ins/ext position, becomes LSB. */ |
9052 | limlo = 0; | |
9053 | limhi = 31; | |
5f74bc13 CD |
9054 | goto do_lsb; |
9055 | case 'E': | |
9056 | limlo = 32; | |
9057 | limhi = 63; | |
9058 | goto do_lsb; | |
9059 | do_lsb: | |
071742cf CD |
9060 | my_getExpression (&imm_expr, s); |
9061 | check_absolute_expr (ip, &imm_expr); | |
9062 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9063 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9064 | { | |
9065 | as_bad (_("Improper position (%lu)"), | |
9066 | (unsigned long) imm_expr.X_add_number); | |
9067 | imm_expr.X_add_number = limlo; | |
9068 | } | |
9069 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9070 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9071 | imm_expr.X_op = O_absent; |
9072 | s = expr_end; | |
9073 | continue; | |
9074 | ||
9075 | case 'B': /* ins size, becomes MSB. */ | |
9076 | limlo = 1; | |
9077 | limhi = 32; | |
5f74bc13 CD |
9078 | goto do_msb; |
9079 | case 'F': | |
9080 | limlo = 33; | |
9081 | limhi = 64; | |
9082 | goto do_msb; | |
9083 | do_msb: | |
071742cf CD |
9084 | my_getExpression (&imm_expr, s); |
9085 | check_absolute_expr (ip, &imm_expr); | |
9086 | /* Check for negative input so that small negative numbers | |
9087 | will not succeed incorrectly. The checks against | |
9088 | (pos+size) transitively check "size" itself, | |
9089 | assuming that "pos" is reasonable. */ | |
9090 | if ((long) imm_expr.X_add_number < 0 | |
9091 | || ((unsigned long) imm_expr.X_add_number | |
9092 | + lastpos) < limlo | |
9093 | || ((unsigned long) imm_expr.X_add_number | |
9094 | + lastpos) > limhi) | |
9095 | { | |
9096 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9097 | (unsigned long) imm_expr.X_add_number, | |
9098 | (unsigned long) lastpos); | |
9099 | imm_expr.X_add_number = limlo - lastpos; | |
9100 | } | |
bf12938e RS |
9101 | INSERT_OPERAND (INSMSB, *ip, |
9102 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9103 | imm_expr.X_op = O_absent; |
9104 | s = expr_end; | |
9105 | continue; | |
9106 | ||
9107 | case 'C': /* ext size, becomes MSBD. */ | |
9108 | limlo = 1; | |
9109 | limhi = 32; | |
5f74bc13 CD |
9110 | goto do_msbd; |
9111 | case 'G': | |
9112 | limlo = 33; | |
9113 | limhi = 64; | |
9114 | goto do_msbd; | |
9115 | case 'H': | |
9116 | limlo = 33; | |
9117 | limhi = 64; | |
9118 | goto do_msbd; | |
9119 | do_msbd: | |
071742cf CD |
9120 | my_getExpression (&imm_expr, s); |
9121 | check_absolute_expr (ip, &imm_expr); | |
9122 | /* Check for negative input so that small negative numbers | |
9123 | will not succeed incorrectly. The checks against | |
9124 | (pos+size) transitively check "size" itself, | |
9125 | assuming that "pos" is reasonable. */ | |
9126 | if ((long) imm_expr.X_add_number < 0 | |
9127 | || ((unsigned long) imm_expr.X_add_number | |
9128 | + lastpos) < limlo | |
9129 | || ((unsigned long) imm_expr.X_add_number | |
9130 | + lastpos) > limhi) | |
9131 | { | |
9132 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9133 | (unsigned long) imm_expr.X_add_number, | |
9134 | (unsigned long) lastpos); | |
9135 | imm_expr.X_add_number = limlo - lastpos; | |
9136 | } | |
bf12938e | 9137 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9138 | imm_expr.X_op = O_absent; |
9139 | s = expr_end; | |
9140 | continue; | |
af7ee8bf | 9141 | |
bbcc0807 CD |
9142 | case 'D': |
9143 | /* +D is for disassembly only; never match. */ | |
9144 | break; | |
9145 | ||
5f74bc13 CD |
9146 | case 'I': |
9147 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9148 | my_getExpression (&imm2_expr, s); | |
9149 | if (imm2_expr.X_op != O_big | |
9150 | && imm2_expr.X_op != O_constant) | |
9151 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9152 | if (HAVE_32BIT_GPRS) |
9153 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9154 | s = expr_end; |
9155 | continue; | |
9156 | ||
707bfff6 | 9157 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9158 | /* +T is for disassembly only; never match. */ |
9159 | break; | |
9160 | ||
707bfff6 | 9161 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9162 | if (s[0] == '$' && ISDIGIT (s[1])) |
9163 | { | |
9164 | ++s; | |
9165 | regno = 0; | |
9166 | do | |
9167 | { | |
9168 | regno *= 10; | |
9169 | regno += *s - '0'; | |
9170 | ++s; | |
9171 | } | |
9172 | while (ISDIGIT (*s)); | |
9173 | if (regno > 31) | |
9174 | as_bad (_("Invalid register number (%d)"), regno); | |
9175 | else | |
9176 | { | |
a9e24354 | 9177 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9178 | continue; |
9179 | } | |
9180 | } | |
9181 | else | |
9182 | as_bad (_("Invalid coprocessor 0 register number")); | |
9183 | break; | |
9184 | ||
bb35fb24 NC |
9185 | case 'x': |
9186 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9187 | is not in the valid range. */ | |
9188 | my_getExpression (&imm_expr, s); | |
9189 | check_absolute_expr (ip, &imm_expr); | |
9190 | if ((unsigned) imm_expr.X_add_number > 31) | |
9191 | { | |
9192 | as_bad (_("Improper bit index (%lu)"), | |
9193 | (unsigned long) imm_expr.X_add_number); | |
9194 | imm_expr.X_add_number = 0; | |
9195 | } | |
9196 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9197 | imm_expr.X_op = O_absent; | |
9198 | s = expr_end; | |
9199 | continue; | |
9200 | ||
9201 | case 'X': | |
9202 | /* bbit[01] bit index when bbit is used but we generate | |
9203 | bbit[01]32 because the index is over 32. Move to the | |
9204 | next candidate if index is not in the valid range. */ | |
9205 | my_getExpression (&imm_expr, s); | |
9206 | check_absolute_expr (ip, &imm_expr); | |
9207 | if ((unsigned) imm_expr.X_add_number < 32 | |
9208 | || (unsigned) imm_expr.X_add_number > 63) | |
9209 | break; | |
9210 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9211 | imm_expr.X_op = O_absent; | |
9212 | s = expr_end; | |
9213 | continue; | |
9214 | ||
9215 | case 'p': | |
9216 | /* cins, cins32, exts and exts32 position field. Give error | |
9217 | if it's not in the valid range. */ | |
9218 | my_getExpression (&imm_expr, s); | |
9219 | check_absolute_expr (ip, &imm_expr); | |
9220 | if ((unsigned) imm_expr.X_add_number > 31) | |
9221 | { | |
9222 | as_bad (_("Improper position (%lu)"), | |
9223 | (unsigned long) imm_expr.X_add_number); | |
9224 | imm_expr.X_add_number = 0; | |
9225 | } | |
9226 | /* Make the pos explicit to simplify +S. */ | |
9227 | lastpos = imm_expr.X_add_number + 32; | |
9228 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9229 | imm_expr.X_op = O_absent; | |
9230 | s = expr_end; | |
9231 | continue; | |
9232 | ||
9233 | case 'P': | |
9234 | /* cins, cins32, exts and exts32 position field. Move to | |
9235 | the next candidate if it's not in the valid range. */ | |
9236 | my_getExpression (&imm_expr, s); | |
9237 | check_absolute_expr (ip, &imm_expr); | |
9238 | if ((unsigned) imm_expr.X_add_number < 32 | |
9239 | || (unsigned) imm_expr.X_add_number > 63) | |
9240 | break; | |
9241 | lastpos = imm_expr.X_add_number; | |
9242 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9243 | imm_expr.X_op = O_absent; | |
9244 | s = expr_end; | |
9245 | continue; | |
9246 | ||
9247 | case 's': | |
9248 | /* cins and exts length-minus-one field. */ | |
9249 | my_getExpression (&imm_expr, s); | |
9250 | check_absolute_expr (ip, &imm_expr); | |
9251 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9252 | { | |
9253 | as_bad (_("Improper size (%lu)"), | |
9254 | (unsigned long) imm_expr.X_add_number); | |
9255 | imm_expr.X_add_number = 0; | |
9256 | } | |
9257 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9258 | imm_expr.X_op = O_absent; | |
9259 | s = expr_end; | |
9260 | continue; | |
9261 | ||
9262 | case 'S': | |
9263 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9264 | length-minus-one field. */ | |
9265 | my_getExpression (&imm_expr, s); | |
9266 | check_absolute_expr (ip, &imm_expr); | |
9267 | if ((long) imm_expr.X_add_number < 0 | |
9268 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9269 | { | |
9270 | as_bad (_("Improper size (%lu)"), | |
9271 | (unsigned long) imm_expr.X_add_number); | |
9272 | imm_expr.X_add_number = 0; | |
9273 | } | |
9274 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9275 | imm_expr.X_op = O_absent; | |
9276 | s = expr_end; | |
9277 | continue; | |
9278 | ||
dd3cbb7e NC |
9279 | case 'Q': |
9280 | /* seqi/snei immediate field. */ | |
9281 | my_getExpression (&imm_expr, s); | |
9282 | check_absolute_expr (ip, &imm_expr); | |
9283 | if ((long) imm_expr.X_add_number < -512 | |
9284 | || (long) imm_expr.X_add_number >= 512) | |
9285 | { | |
9286 | as_bad (_("Improper immediate (%ld)"), | |
9287 | (long) imm_expr.X_add_number); | |
9288 | imm_expr.X_add_number = 0; | |
9289 | } | |
9290 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9291 | imm_expr.X_op = O_absent; | |
9292 | s = expr_end; | |
9293 | continue; | |
9294 | ||
af7ee8bf CD |
9295 | default: |
9296 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
9297 | *args, insn->name, insn->args); | |
9298 | /* Further processing is fruitless. */ | |
9299 | return; | |
9300 | } | |
9301 | break; | |
9302 | ||
252b5132 RH |
9303 | case '<': /* must be at least one digit */ |
9304 | /* | |
9305 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9306 | * than 31 or less than 0, then the shift amount should be |
9307 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9308 | * We issue a warning and mask out all but the low 5 bits. |
9309 | */ | |
9310 | my_getExpression (&imm_expr, s); | |
9311 | check_absolute_expr (ip, &imm_expr); | |
9312 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9313 | as_warn (_("Improper shift amount (%lu)"), |
9314 | (unsigned long) imm_expr.X_add_number); | |
9315 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9316 | imm_expr.X_op = O_absent; |
9317 | s = expr_end; | |
9318 | continue; | |
9319 | ||
9320 | case '>': /* shift amount minus 32 */ | |
9321 | my_getExpression (&imm_expr, s); | |
9322 | check_absolute_expr (ip, &imm_expr); | |
9323 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9324 | || (unsigned long) imm_expr.X_add_number > 63) | |
9325 | break; | |
bf12938e | 9326 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9327 | imm_expr.X_op = O_absent; |
9328 | s = expr_end; | |
9329 | continue; | |
9330 | ||
252b5132 RH |
9331 | case 'k': /* cache code */ |
9332 | case 'h': /* prefx code */ | |
620edafd | 9333 | case '1': /* sync type */ |
252b5132 RH |
9334 | my_getExpression (&imm_expr, s); |
9335 | check_absolute_expr (ip, &imm_expr); | |
9336 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9337 | as_warn (_("Invalid value for `%s' (%lu)"), |
9338 | ip->insn_mo->name, | |
9339 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9340 | if (*args == 'k') |
bf12938e | 9341 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
620edafd | 9342 | else if (*args == 'h') |
bf12938e | 9343 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9344 | else |
9345 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9346 | imm_expr.X_op = O_absent; |
9347 | s = expr_end; | |
9348 | continue; | |
9349 | ||
9350 | case 'c': /* break code */ | |
9351 | my_getExpression (&imm_expr, s); | |
9352 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9353 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9354 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9355 | ip->insn_mo->name, | |
bf12938e RS |
9356 | (unsigned long) imm_expr.X_add_number); |
9357 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9358 | imm_expr.X_op = O_absent; |
9359 | s = expr_end; | |
9360 | continue; | |
9361 | ||
9362 | case 'q': /* lower break code */ | |
9363 | my_getExpression (&imm_expr, s); | |
9364 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9365 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9366 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9367 | ip->insn_mo->name, | |
bf12938e RS |
9368 | (unsigned long) imm_expr.X_add_number); |
9369 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9370 | imm_expr.X_op = O_absent; |
9371 | s = expr_end; | |
9372 | continue; | |
9373 | ||
4372b673 | 9374 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9375 | my_getExpression (&imm_expr, s); |
156c2f8b | 9376 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9377 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9378 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9379 | ip->insn_mo->name, | |
793b27f4 | 9380 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9381 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9382 | imm_expr.X_op = O_absent; |
9383 | s = expr_end; | |
9384 | continue; | |
9385 | ||
98d3f06f | 9386 | case 'C': /* Coprocessor code */ |
beae10d5 | 9387 | my_getExpression (&imm_expr, s); |
252b5132 | 9388 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9389 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9390 | { |
793b27f4 TS |
9391 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9392 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9393 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9394 | } |
a9e24354 | 9395 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9396 | imm_expr.X_op = O_absent; |
9397 | s = expr_end; | |
9398 | continue; | |
252b5132 | 9399 | |
4372b673 NC |
9400 | case 'J': /* 19-bit wait code. */ |
9401 | my_getExpression (&imm_expr, s); | |
9402 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9403 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9404 | { |
9405 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9406 | (unsigned long) imm_expr.X_add_number); | |
9407 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9408 | } | |
bf12938e | 9409 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9410 | imm_expr.X_op = O_absent; |
9411 | s = expr_end; | |
9412 | continue; | |
9413 | ||
707bfff6 | 9414 | case 'P': /* Performance register. */ |
beae10d5 | 9415 | my_getExpression (&imm_expr, s); |
252b5132 | 9416 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9417 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9418 | as_warn (_("Invalid performance register (%lu)"), |
9419 | (unsigned long) imm_expr.X_add_number); | |
9420 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9421 | imm_expr.X_op = O_absent; |
9422 | s = expr_end; | |
9423 | continue; | |
252b5132 | 9424 | |
707bfff6 TS |
9425 | case 'G': /* Coprocessor destination register. */ |
9426 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9427 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9428 | else | |
9429 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9430 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9431 | if (ok) |
9432 | { | |
9433 | lastregno = regno; | |
9434 | continue; | |
9435 | } | |
9436 | else | |
9437 | break; | |
9438 | ||
252b5132 RH |
9439 | case 'b': /* base register */ |
9440 | case 'd': /* destination register */ | |
9441 | case 's': /* source register */ | |
9442 | case 't': /* target register */ | |
9443 | case 'r': /* both target and source */ | |
9444 | case 'v': /* both dest and source */ | |
9445 | case 'w': /* both dest and target */ | |
9446 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9447 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9448 | case 'x': /* ignore register name */ |
9449 | case 'z': /* must be zero register */ | |
4372b673 | 9450 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9451 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9452 | s_reset = s; |
9453 | if (*args == 'E' || *args == 'K') | |
9454 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9455 | else | |
9456 | { | |
9457 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9458 | if (regno == AT && mips_opts.at) |
9459 | { | |
9460 | if (mips_opts.at == ATREG) | |
9461 | as_warn (_("used $at without \".set noat\"")); | |
9462 | else | |
9463 | as_warn (_("used $%u with \".set at=$%u\""), | |
9464 | regno, mips_opts.at); | |
9465 | } | |
707bfff6 TS |
9466 | } |
9467 | if (ok) | |
252b5132 | 9468 | { |
252b5132 RH |
9469 | c = *args; |
9470 | if (*s == ' ') | |
f9419b05 | 9471 | ++s; |
252b5132 RH |
9472 | if (args[1] != *s) |
9473 | { | |
9474 | if (c == 'r' || c == 'v' || c == 'w') | |
9475 | { | |
9476 | regno = lastregno; | |
9477 | s = s_reset; | |
f9419b05 | 9478 | ++args; |
252b5132 RH |
9479 | } |
9480 | } | |
9481 | /* 'z' only matches $0. */ | |
9482 | if (c == 'z' && regno != 0) | |
9483 | break; | |
9484 | ||
24864476 | 9485 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9486 | { |
9487 | if (regno == lastregno) | |
9488 | { | |
24864476 | 9489 | insn_error = _("source and destination must be different"); |
e7c604dd CM |
9490 | continue; |
9491 | } | |
24864476 | 9492 | if (regno == 31 && lastregno == 0xffffffff) |
e7c604dd CM |
9493 | { |
9494 | insn_error = _("a destination register must be supplied"); | |
9495 | continue; | |
9496 | } | |
9497 | } | |
bdaaa2e1 KH |
9498 | /* Now that we have assembled one operand, we use the args string |
9499 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9500 | switch (c) |
9501 | { | |
9502 | case 'r': | |
9503 | case 's': | |
9504 | case 'v': | |
9505 | case 'b': | |
bf12938e | 9506 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9507 | break; |
9508 | case 'd': | |
9509 | case 'G': | |
af7ee8bf | 9510 | case 'K': |
ef2e4d86 | 9511 | case 'g': |
bf12938e | 9512 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9513 | break; |
4372b673 | 9514 | case 'U': |
bf12938e RS |
9515 | INSERT_OPERAND (RD, *ip, regno); |
9516 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9517 | break; |
252b5132 RH |
9518 | case 'w': |
9519 | case 't': | |
9520 | case 'E': | |
bf12938e | 9521 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9522 | break; |
9523 | case 'x': | |
9524 | /* This case exists because on the r3000 trunc | |
9525 | expands into a macro which requires a gp | |
9526 | register. On the r6000 or r4000 it is | |
9527 | assembled into a single instruction which | |
9528 | ignores the register. Thus the insn version | |
9529 | is MIPS_ISA2 and uses 'x', and the macro | |
9530 | version is MIPS_ISA1 and uses 't'. */ | |
9531 | break; | |
9532 | case 'z': | |
9533 | /* This case is for the div instruction, which | |
9534 | acts differently if the destination argument | |
9535 | is $0. This only matches $0, and is checked | |
9536 | outside the switch. */ | |
9537 | break; | |
9538 | case 'D': | |
9539 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9540 | break; | |
9541 | /* What about all other operands like 'i', which | |
9542 | can be specified in the opcode table? */ | |
9543 | } | |
9544 | lastregno = regno; | |
9545 | continue; | |
9546 | } | |
252b5132 RH |
9547 | switch (*args++) |
9548 | { | |
9549 | case 'r': | |
9550 | case 'v': | |
bf12938e | 9551 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9552 | continue; |
9553 | case 'w': | |
bf12938e | 9554 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9555 | continue; |
9556 | } | |
9557 | break; | |
9558 | ||
deec1734 CD |
9559 | case 'O': /* MDMX alignment immediate constant. */ |
9560 | my_getExpression (&imm_expr, s); | |
9561 | check_absolute_expr (ip, &imm_expr); | |
9562 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9563 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9564 | (long) imm_expr.X_add_number); |
9565 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9566 | imm_expr.X_op = O_absent; |
9567 | s = expr_end; | |
9568 | continue; | |
9569 | ||
9570 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9571 | if (s[0] != '$') | |
9572 | { | |
9573 | /* MDMX Immediate. */ | |
9574 | my_getExpression (&imm_expr, s); | |
9575 | check_absolute_expr (ip, &imm_expr); | |
9576 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9577 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9578 | (long) imm_expr.X_add_number); | |
9579 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9580 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9581 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9582 | else | |
9583 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9584 | imm_expr.X_op = O_absent; |
9585 | s = expr_end; | |
9586 | continue; | |
9587 | } | |
9588 | /* Not MDMX Immediate. Fall through. */ | |
9589 | case 'X': /* MDMX destination register. */ | |
9590 | case 'Y': /* MDMX source register. */ | |
9591 | case 'Z': /* MDMX target register. */ | |
9592 | is_mdmx = 1; | |
252b5132 RH |
9593 | case 'D': /* floating point destination register */ |
9594 | case 'S': /* floating point source register */ | |
9595 | case 'T': /* floating point target register */ | |
9596 | case 'R': /* floating point source register */ | |
9597 | case 'V': | |
9598 | case 'W': | |
707bfff6 TS |
9599 | rtype = RTYPE_FPU; |
9600 | if (is_mdmx | |
9601 | || (mips_opts.ase_mdmx | |
9602 | && (ip->insn_mo->pinfo & FP_D) | |
9603 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9604 | | INSN_COPROC_MEMORY_DELAY | |
9605 | | INSN_LOAD_COPROC_DELAY | |
9606 | | INSN_LOAD_MEMORY_DELAY | |
9607 | | INSN_STORE_MEMORY)))) | |
9608 | rtype |= RTYPE_VEC; | |
252b5132 | 9609 | s_reset = s; |
707bfff6 | 9610 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9611 | { |
252b5132 | 9612 | if ((regno & 1) != 0 |
ca4e0257 | 9613 | && HAVE_32BIT_FPRS |
7455baf8 | 9614 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9615 | as_warn (_("Float register should be even, was %d"), |
9616 | regno); | |
9617 | ||
9618 | c = *args; | |
9619 | if (*s == ' ') | |
f9419b05 | 9620 | ++s; |
252b5132 RH |
9621 | if (args[1] != *s) |
9622 | { | |
9623 | if (c == 'V' || c == 'W') | |
9624 | { | |
9625 | regno = lastregno; | |
9626 | s = s_reset; | |
f9419b05 | 9627 | ++args; |
252b5132 RH |
9628 | } |
9629 | } | |
9630 | switch (c) | |
9631 | { | |
9632 | case 'D': | |
deec1734 | 9633 | case 'X': |
bf12938e | 9634 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9635 | break; |
9636 | case 'V': | |
9637 | case 'S': | |
deec1734 | 9638 | case 'Y': |
bf12938e | 9639 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9640 | break; |
deec1734 CD |
9641 | case 'Q': |
9642 | /* This is like 'Z', but also needs to fix the MDMX | |
9643 | vector/scalar select bits. Note that the | |
9644 | scalar immediate case is handled above. */ | |
9645 | if (*s == '[') | |
9646 | { | |
9647 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9648 | int max_el = (is_qh ? 3 : 7); | |
9649 | s++; | |
9650 | my_getExpression(&imm_expr, s); | |
9651 | check_absolute_expr (ip, &imm_expr); | |
9652 | s = expr_end; | |
9653 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9654 | as_bad (_("Bad element selector %ld"), |
9655 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9656 | imm_expr.X_add_number &= max_el; |
9657 | ip->insn_opcode |= (imm_expr.X_add_number | |
9658 | << (OP_SH_VSEL + | |
9659 | (is_qh ? 2 : 1))); | |
01a3f561 | 9660 | imm_expr.X_op = O_absent; |
deec1734 | 9661 | if (*s != ']') |
20203fb9 | 9662 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9663 | else |
9664 | s++; | |
9665 | } | |
9666 | else | |
9667 | { | |
9668 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9669 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9670 | << OP_SH_VSEL); | |
9671 | else | |
9672 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9673 | OP_SH_VSEL); | |
9674 | } | |
9675 | /* Fall through */ | |
252b5132 RH |
9676 | case 'W': |
9677 | case 'T': | |
deec1734 | 9678 | case 'Z': |
bf12938e | 9679 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9680 | break; |
9681 | case 'R': | |
bf12938e | 9682 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9683 | break; |
9684 | } | |
9685 | lastregno = regno; | |
9686 | continue; | |
9687 | } | |
9688 | ||
252b5132 RH |
9689 | switch (*args++) |
9690 | { | |
9691 | case 'V': | |
bf12938e | 9692 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9693 | continue; |
9694 | case 'W': | |
bf12938e | 9695 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9696 | continue; |
9697 | } | |
9698 | break; | |
9699 | ||
9700 | case 'I': | |
9701 | my_getExpression (&imm_expr, s); | |
9702 | if (imm_expr.X_op != O_big | |
9703 | && imm_expr.X_op != O_constant) | |
9704 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9705 | if (HAVE_32BIT_GPRS) |
9706 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9707 | s = expr_end; |
9708 | continue; | |
9709 | ||
9710 | case 'A': | |
9711 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9712 | normalize_address_expr (&offset_expr); |
f6688943 | 9713 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9714 | s = expr_end; |
9715 | continue; | |
9716 | ||
9717 | case 'F': | |
9718 | case 'L': | |
9719 | case 'f': | |
9720 | case 'l': | |
9721 | { | |
9722 | int f64; | |
ca4e0257 | 9723 | int using_gprs; |
252b5132 RH |
9724 | char *save_in; |
9725 | char *err; | |
9726 | unsigned char temp[8]; | |
9727 | int len; | |
9728 | unsigned int length; | |
9729 | segT seg; | |
9730 | subsegT subseg; | |
9731 | char *p; | |
9732 | ||
9733 | /* These only appear as the last operand in an | |
9734 | instruction, and every instruction that accepts | |
9735 | them in any variant accepts them in all variants. | |
9736 | This means we don't have to worry about backing out | |
9737 | any changes if the instruction does not match. | |
9738 | ||
9739 | The difference between them is the size of the | |
9740 | floating point constant and where it goes. For 'F' | |
9741 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9742 | is 32 bits. Where the constant is placed is based | |
9743 | on how the MIPS assembler does things: | |
9744 | F -- .rdata | |
9745 | L -- .lit8 | |
9746 | f -- immediate value | |
9747 | l -- .lit4 | |
9748 | ||
9749 | The .lit4 and .lit8 sections are only used if | |
9750 | permitted by the -G argument. | |
9751 | ||
ca4e0257 RS |
9752 | The code below needs to know whether the target register |
9753 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9754 | 'F' are used with GPR-based instructions and 'l' and | |
9755 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9756 | |
9757 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9758 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9759 | |
9760 | save_in = input_line_pointer; | |
9761 | input_line_pointer = s; | |
9762 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9763 | length = len; | |
9764 | s = input_line_pointer; | |
9765 | input_line_pointer = save_in; | |
9766 | if (err != NULL && *err != '\0') | |
9767 | { | |
9768 | as_bad (_("Bad floating point constant: %s"), err); | |
9769 | memset (temp, '\0', sizeof temp); | |
9770 | length = f64 ? 8 : 4; | |
9771 | } | |
9772 | ||
9c2799c2 | 9773 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9774 | |
9775 | if (*args == 'f' | |
9776 | || (*args == 'l' | |
3e722fb5 | 9777 | && (g_switch_value < 4 |
252b5132 RH |
9778 | || (temp[0] == 0 && temp[1] == 0) |
9779 | || (temp[2] == 0 && temp[3] == 0)))) | |
9780 | { | |
9781 | imm_expr.X_op = O_constant; | |
9782 | if (! target_big_endian) | |
9783 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9784 | else | |
9785 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9786 | } | |
9787 | else if (length > 4 | |
119d663a | 9788 | && ! mips_disable_float_construction |
ca4e0257 RS |
9789 | /* Constants can only be constructed in GPRs and |
9790 | copied to FPRs if the GPRs are at least as wide | |
9791 | as the FPRs. Force the constant into memory if | |
9792 | we are using 64-bit FPRs but the GPRs are only | |
9793 | 32 bits wide. */ | |
9794 | && (using_gprs | |
9795 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9796 | && ((temp[0] == 0 && temp[1] == 0) |
9797 | || (temp[2] == 0 && temp[3] == 0)) | |
9798 | && ((temp[4] == 0 && temp[5] == 0) | |
9799 | || (temp[6] == 0 && temp[7] == 0))) | |
9800 | { | |
ca4e0257 RS |
9801 | /* The value is simple enough to load with a couple of |
9802 | instructions. If using 32-bit registers, set | |
9803 | imm_expr to the high order 32 bits and offset_expr to | |
9804 | the low order 32 bits. Otherwise, set imm_expr to | |
9805 | the entire 64 bit constant. */ | |
9806 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9807 | { |
9808 | imm_expr.X_op = O_constant; | |
9809 | offset_expr.X_op = O_constant; | |
9810 | if (! target_big_endian) | |
9811 | { | |
9812 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9813 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9814 | } | |
9815 | else | |
9816 | { | |
9817 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9818 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9819 | } | |
9820 | if (offset_expr.X_add_number == 0) | |
9821 | offset_expr.X_op = O_absent; | |
9822 | } | |
9823 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9824 | { | |
9825 | imm_expr.X_op = O_constant; | |
9826 | if (! target_big_endian) | |
9827 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9828 | else | |
9829 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9830 | } | |
9831 | else | |
9832 | { | |
9833 | imm_expr.X_op = O_big; | |
9834 | imm_expr.X_add_number = 4; | |
9835 | if (! target_big_endian) | |
9836 | { | |
9837 | generic_bignum[0] = bfd_getl16 (temp); | |
9838 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9839 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9840 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9841 | } | |
9842 | else | |
9843 | { | |
9844 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9845 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9846 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9847 | generic_bignum[3] = bfd_getb16 (temp); | |
9848 | } | |
9849 | } | |
9850 | } | |
9851 | else | |
9852 | { | |
9853 | const char *newname; | |
9854 | segT new_seg; | |
9855 | ||
9856 | /* Switch to the right section. */ | |
9857 | seg = now_seg; | |
9858 | subseg = now_subseg; | |
9859 | switch (*args) | |
9860 | { | |
9861 | default: /* unused default case avoids warnings. */ | |
9862 | case 'L': | |
9863 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9864 | if (g_switch_value >= 8) |
252b5132 RH |
9865 | newname = ".lit8"; |
9866 | break; | |
9867 | case 'F': | |
3e722fb5 | 9868 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9869 | break; |
9870 | case 'l': | |
9c2799c2 | 9871 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9872 | newname = ".lit4"; |
9873 | break; | |
9874 | } | |
9875 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9876 | if (IS_ELF) |
252b5132 RH |
9877 | bfd_set_section_flags (stdoutput, new_seg, |
9878 | (SEC_ALLOC | |
9879 | | SEC_LOAD | |
9880 | | SEC_READONLY | |
9881 | | SEC_DATA)); | |
9882 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9883 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9884 | record_alignment (new_seg, 4); |
9885 | else | |
9886 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9887 | if (seg == now_seg) | |
9888 | as_bad (_("Can't use floating point insn in this section")); | |
9889 | ||
9890 | /* Set the argument to the current address in the | |
9891 | section. */ | |
9892 | offset_expr.X_op = O_symbol; | |
9893 | offset_expr.X_add_symbol = | |
9894 | symbol_new ("L0\001", now_seg, | |
9895 | (valueT) frag_now_fix (), frag_now); | |
9896 | offset_expr.X_add_number = 0; | |
9897 | ||
9898 | /* Put the floating point number into the section. */ | |
9899 | p = frag_more ((int) length); | |
9900 | memcpy (p, temp, length); | |
9901 | ||
9902 | /* Switch back to the original section. */ | |
9903 | subseg_set (seg, subseg); | |
9904 | } | |
9905 | } | |
9906 | continue; | |
9907 | ||
9908 | case 'i': /* 16 bit unsigned immediate */ | |
9909 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9910 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9911 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9912 | { |
9913 | int more; | |
5e0116d5 RS |
9914 | offsetT minval, maxval; |
9915 | ||
9916 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9917 | && strcmp (insn->name, insn[1].name) == 0); | |
9918 | ||
9919 | /* If the expression was written as an unsigned number, | |
9920 | only treat it as signed if there are no more | |
9921 | alternatives. */ | |
9922 | if (more | |
9923 | && *args == 'j' | |
9924 | && sizeof (imm_expr.X_add_number) <= 4 | |
9925 | && imm_expr.X_op == O_constant | |
9926 | && imm_expr.X_add_number < 0 | |
9927 | && imm_expr.X_unsigned | |
9928 | && HAVE_64BIT_GPRS) | |
9929 | break; | |
9930 | ||
9931 | /* For compatibility with older assemblers, we accept | |
9932 | 0x8000-0xffff as signed 16-bit numbers when only | |
9933 | signed numbers are allowed. */ | |
9934 | if (*args == 'i') | |
9935 | minval = 0, maxval = 0xffff; | |
9936 | else if (more) | |
9937 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9938 | else |
5e0116d5 RS |
9939 | minval = -0x8000, maxval = 0xffff; |
9940 | ||
9941 | if (imm_expr.X_op != O_constant | |
9942 | || imm_expr.X_add_number < minval | |
9943 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9944 | { |
9945 | if (more) | |
9946 | break; | |
2ae7e77b AH |
9947 | if (imm_expr.X_op == O_constant |
9948 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9949 | as_bad (_("expression out of range")); |
252b5132 RH |
9950 | } |
9951 | } | |
9952 | s = expr_end; | |
9953 | continue; | |
9954 | ||
9955 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9956 | /* Check whether there is only a single bracketed expression |
9957 | left. If so, it must be the base register and the | |
9958 | constant must be zero. */ | |
9959 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9960 | { | |
9961 | offset_expr.X_op = O_constant; | |
9962 | offset_expr.X_add_number = 0; | |
9963 | continue; | |
9964 | } | |
252b5132 RH |
9965 | |
9966 | /* If this value won't fit into a 16 bit offset, then go | |
9967 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9968 | code pattern. */ |
5e0116d5 | 9969 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9970 | && (offset_expr.X_op != O_constant |
9971 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9972 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9973 | break; |
9974 | ||
252b5132 RH |
9975 | s = expr_end; |
9976 | continue; | |
9977 | ||
9978 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9979 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9980 | my_getExpression (&offset_expr, s); |
9981 | s = expr_end; | |
9982 | continue; | |
9983 | ||
9984 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9985 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9986 | && imm_expr.X_op == O_constant | |
9987 | && (imm_expr.X_add_number < 0 | |
9988 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9989 | as_bad (_("lui expression not in range 0..65535")); |
9990 | s = expr_end; | |
9991 | continue; | |
9992 | ||
9993 | case 'a': /* 26 bit address */ | |
9994 | my_getExpression (&offset_expr, s); | |
9995 | s = expr_end; | |
f6688943 | 9996 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9997 | continue; |
9998 | ||
9999 | case 'N': /* 3 bit branch condition code */ | |
10000 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
10001 | rtype = RTYPE_CCC; |
10002 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
10003 | rtype |= RTYPE_FCC; | |
10004 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10005 | break; |
30c378fd CD |
10006 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
10007 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
10008 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
10009 | && (regno & 1) != 0) | |
20203fb9 NC |
10010 | as_warn (_("Condition code register should be even for %s, was %d"), |
10011 | str, regno); | |
30c378fd CD |
10012 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 |
10013 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
10014 | && (regno & 3) != 0) | |
20203fb9 NC |
10015 | as_warn (_("Condition code register should be 0 or 4 for %s, was %d"), |
10016 | str, regno); | |
252b5132 | 10017 | if (*args == 'N') |
bf12938e | 10018 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10019 | else |
bf12938e | 10020 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10021 | continue; |
252b5132 | 10022 | |
156c2f8b NC |
10023 | case 'H': |
10024 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10025 | s += 2; | |
3882b010 | 10026 | if (ISDIGIT (*s)) |
156c2f8b NC |
10027 | { |
10028 | c = 0; | |
10029 | do | |
10030 | { | |
10031 | c *= 10; | |
10032 | c += *s - '0'; | |
10033 | ++s; | |
10034 | } | |
3882b010 | 10035 | while (ISDIGIT (*s)); |
156c2f8b NC |
10036 | } |
10037 | else | |
10038 | c = 8; /* Invalid sel value. */ | |
10039 | ||
10040 | if (c > 7) | |
10041 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
10042 | ip->insn_opcode |= c; | |
10043 | continue; | |
10044 | ||
60b63b72 RS |
10045 | case 'e': |
10046 | /* Must be at least one digit. */ | |
10047 | my_getExpression (&imm_expr, s); | |
10048 | check_absolute_expr (ip, &imm_expr); | |
10049 | ||
10050 | if ((unsigned long) imm_expr.X_add_number | |
10051 | > (unsigned long) OP_MASK_VECBYTE) | |
10052 | { | |
10053 | as_bad (_("bad byte vector index (%ld)"), | |
10054 | (long) imm_expr.X_add_number); | |
10055 | imm_expr.X_add_number = 0; | |
10056 | } | |
10057 | ||
bf12938e | 10058 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10059 | imm_expr.X_op = O_absent; |
10060 | s = expr_end; | |
10061 | continue; | |
10062 | ||
10063 | case '%': | |
10064 | my_getExpression (&imm_expr, s); | |
10065 | check_absolute_expr (ip, &imm_expr); | |
10066 | ||
10067 | if ((unsigned long) imm_expr.X_add_number | |
10068 | > (unsigned long) OP_MASK_VECALIGN) | |
10069 | { | |
10070 | as_bad (_("bad byte vector index (%ld)"), | |
10071 | (long) imm_expr.X_add_number); | |
10072 | imm_expr.X_add_number = 0; | |
10073 | } | |
10074 | ||
bf12938e | 10075 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10076 | imm_expr.X_op = O_absent; |
10077 | s = expr_end; | |
10078 | continue; | |
10079 | ||
252b5132 RH |
10080 | default: |
10081 | as_bad (_("bad char = '%c'\n"), *args); | |
10082 | internalError (); | |
10083 | } | |
10084 | break; | |
10085 | } | |
10086 | /* Args don't match. */ | |
10087 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10088 | !strcmp (insn->name, insn[1].name)) | |
10089 | { | |
10090 | ++insn; | |
10091 | s = argsStart; | |
268f6bed | 10092 | insn_error = _("illegal operands"); |
252b5132 RH |
10093 | continue; |
10094 | } | |
268f6bed | 10095 | if (save_c) |
570de991 | 10096 | *(--argsStart) = save_c; |
252b5132 RH |
10097 | insn_error = _("illegal operands"); |
10098 | return; | |
10099 | } | |
10100 | } | |
10101 | ||
0499d65b TS |
10102 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10103 | ||
252b5132 RH |
10104 | /* This routine assembles an instruction into its binary format when |
10105 | assembling for the mips16. As a side effect, it sets one of the | |
10106 | global variables imm_reloc or offset_reloc to the type of | |
10107 | relocation to do if one of the operands is an address expression. | |
10108 | It also sets mips16_small and mips16_ext if the user explicitly | |
10109 | requested a small or extended instruction. */ | |
10110 | ||
10111 | static void | |
17a2f251 | 10112 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10113 | { |
10114 | char *s; | |
10115 | const char *args; | |
10116 | struct mips_opcode *insn; | |
10117 | char *argsstart; | |
10118 | unsigned int regno; | |
10119 | unsigned int lastregno = 0; | |
10120 | char *s_reset; | |
d6f16593 | 10121 | size_t i; |
252b5132 RH |
10122 | |
10123 | insn_error = NULL; | |
10124 | ||
b34976b6 AM |
10125 | mips16_small = FALSE; |
10126 | mips16_ext = FALSE; | |
252b5132 | 10127 | |
3882b010 | 10128 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10129 | ; |
10130 | switch (*s) | |
10131 | { | |
10132 | case '\0': | |
10133 | break; | |
10134 | ||
10135 | case ' ': | |
10136 | *s++ = '\0'; | |
10137 | break; | |
10138 | ||
10139 | case '.': | |
10140 | if (s[1] == 't' && s[2] == ' ') | |
10141 | { | |
10142 | *s = '\0'; | |
b34976b6 | 10143 | mips16_small = TRUE; |
252b5132 RH |
10144 | s += 3; |
10145 | break; | |
10146 | } | |
10147 | else if (s[1] == 'e' && s[2] == ' ') | |
10148 | { | |
10149 | *s = '\0'; | |
b34976b6 | 10150 | mips16_ext = TRUE; |
252b5132 RH |
10151 | s += 3; |
10152 | break; | |
10153 | } | |
10154 | /* Fall through. */ | |
10155 | default: | |
10156 | insn_error = _("unknown opcode"); | |
10157 | return; | |
10158 | } | |
10159 | ||
10160 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10161 | mips16_small = TRUE; |
252b5132 RH |
10162 | |
10163 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10164 | { | |
10165 | insn_error = _("unrecognized opcode"); | |
10166 | return; | |
10167 | } | |
10168 | ||
10169 | argsstart = s; | |
10170 | for (;;) | |
10171 | { | |
9b3f89ee TS |
10172 | bfd_boolean ok; |
10173 | ||
9c2799c2 | 10174 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10175 | |
037b32b9 | 10176 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10177 | if (! ok) |
10178 | { | |
10179 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10180 | && strcmp (insn->name, insn[1].name) == 0) | |
10181 | { | |
10182 | ++insn; | |
10183 | continue; | |
10184 | } | |
10185 | else | |
10186 | { | |
10187 | if (!insn_error) | |
10188 | { | |
10189 | static char buf[100]; | |
10190 | sprintf (buf, | |
10191 | _("opcode not supported on this processor: %s (%s)"), | |
10192 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10193 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10194 | insn_error = buf; | |
10195 | } | |
10196 | return; | |
10197 | } | |
10198 | } | |
10199 | ||
1e915849 | 10200 | create_insn (ip, insn); |
252b5132 | 10201 | imm_expr.X_op = O_absent; |
f6688943 TS |
10202 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10203 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10204 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10205 | imm2_expr.X_op = O_absent; |
252b5132 | 10206 | offset_expr.X_op = O_absent; |
f6688943 TS |
10207 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10208 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10209 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10210 | for (args = insn->args; 1; ++args) |
10211 | { | |
10212 | int c; | |
10213 | ||
10214 | if (*s == ' ') | |
10215 | ++s; | |
10216 | ||
10217 | /* In this switch statement we call break if we did not find | |
10218 | a match, continue if we did find a match, or return if we | |
10219 | are done. */ | |
10220 | ||
10221 | c = *args; | |
10222 | switch (c) | |
10223 | { | |
10224 | case '\0': | |
10225 | if (*s == '\0') | |
10226 | { | |
10227 | /* Stuff the immediate value in now, if we can. */ | |
10228 | if (imm_expr.X_op == O_constant | |
f6688943 | 10229 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10230 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10231 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10232 | && insn->pinfo != INSN_MACRO) |
10233 | { | |
d6f16593 MR |
10234 | valueT tmp; |
10235 | ||
10236 | switch (*offset_reloc) | |
10237 | { | |
10238 | case BFD_RELOC_MIPS16_HI16_S: | |
10239 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10240 | break; | |
10241 | ||
10242 | case BFD_RELOC_MIPS16_HI16: | |
10243 | tmp = imm_expr.X_add_number >> 16; | |
10244 | break; | |
10245 | ||
10246 | case BFD_RELOC_MIPS16_LO16: | |
10247 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10248 | - 0x8000; | |
10249 | break; | |
10250 | ||
10251 | case BFD_RELOC_UNUSED: | |
10252 | tmp = imm_expr.X_add_number; | |
10253 | break; | |
10254 | ||
10255 | default: | |
10256 | internalError (); | |
10257 | } | |
10258 | *offset_reloc = BFD_RELOC_UNUSED; | |
10259 | ||
c4e7957c | 10260 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10261 | tmp, TRUE, mips16_small, |
252b5132 RH |
10262 | mips16_ext, &ip->insn_opcode, |
10263 | &ip->use_extend, &ip->extend); | |
10264 | imm_expr.X_op = O_absent; | |
f6688943 | 10265 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10266 | } |
10267 | ||
10268 | return; | |
10269 | } | |
10270 | break; | |
10271 | ||
10272 | case ',': | |
10273 | if (*s++ == c) | |
10274 | continue; | |
10275 | s--; | |
10276 | switch (*++args) | |
10277 | { | |
10278 | case 'v': | |
bf12938e | 10279 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10280 | continue; |
10281 | case 'w': | |
bf12938e | 10282 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10283 | continue; |
10284 | } | |
10285 | break; | |
10286 | ||
10287 | case '(': | |
10288 | case ')': | |
10289 | if (*s++ == c) | |
10290 | continue; | |
10291 | break; | |
10292 | ||
10293 | case 'v': | |
10294 | case 'w': | |
10295 | if (s[0] != '$') | |
10296 | { | |
10297 | if (c == 'v') | |
bf12938e | 10298 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10299 | else |
bf12938e | 10300 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10301 | ++args; |
10302 | continue; | |
10303 | } | |
10304 | /* Fall through. */ | |
10305 | case 'x': | |
10306 | case 'y': | |
10307 | case 'z': | |
10308 | case 'Z': | |
10309 | case '0': | |
10310 | case 'S': | |
10311 | case 'R': | |
10312 | case 'X': | |
10313 | case 'Y': | |
707bfff6 TS |
10314 | s_reset = s; |
10315 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10316 | { |
707bfff6 | 10317 | if (c == 'v' || c == 'w') |
85b51719 | 10318 | { |
707bfff6 | 10319 | if (c == 'v') |
a9e24354 | 10320 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10321 | else |
a9e24354 | 10322 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10323 | ++args; |
10324 | continue; | |
85b51719 | 10325 | } |
707bfff6 | 10326 | break; |
252b5132 RH |
10327 | } |
10328 | ||
10329 | if (*s == ' ') | |
10330 | ++s; | |
10331 | if (args[1] != *s) | |
10332 | { | |
10333 | if (c == 'v' || c == 'w') | |
10334 | { | |
10335 | regno = mips16_to_32_reg_map[lastregno]; | |
10336 | s = s_reset; | |
f9419b05 | 10337 | ++args; |
252b5132 RH |
10338 | } |
10339 | } | |
10340 | ||
10341 | switch (c) | |
10342 | { | |
10343 | case 'x': | |
10344 | case 'y': | |
10345 | case 'z': | |
10346 | case 'v': | |
10347 | case 'w': | |
10348 | case 'Z': | |
10349 | regno = mips32_to_16_reg_map[regno]; | |
10350 | break; | |
10351 | ||
10352 | case '0': | |
10353 | if (regno != 0) | |
10354 | regno = ILLEGAL_REG; | |
10355 | break; | |
10356 | ||
10357 | case 'S': | |
10358 | if (regno != SP) | |
10359 | regno = ILLEGAL_REG; | |
10360 | break; | |
10361 | ||
10362 | case 'R': | |
10363 | if (regno != RA) | |
10364 | regno = ILLEGAL_REG; | |
10365 | break; | |
10366 | ||
10367 | case 'X': | |
10368 | case 'Y': | |
741fe287 MR |
10369 | if (regno == AT && mips_opts.at) |
10370 | { | |
10371 | if (mips_opts.at == ATREG) | |
10372 | as_warn (_("used $at without \".set noat\"")); | |
10373 | else | |
10374 | as_warn (_("used $%u with \".set at=$%u\""), | |
10375 | regno, mips_opts.at); | |
10376 | } | |
252b5132 RH |
10377 | break; |
10378 | ||
10379 | default: | |
10380 | internalError (); | |
10381 | } | |
10382 | ||
10383 | if (regno == ILLEGAL_REG) | |
10384 | break; | |
10385 | ||
10386 | switch (c) | |
10387 | { | |
10388 | case 'x': | |
10389 | case 'v': | |
bf12938e | 10390 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10391 | break; |
10392 | case 'y': | |
10393 | case 'w': | |
bf12938e | 10394 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10395 | break; |
10396 | case 'z': | |
bf12938e | 10397 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10398 | break; |
10399 | case 'Z': | |
bf12938e | 10400 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10401 | case '0': |
10402 | case 'S': | |
10403 | case 'R': | |
10404 | break; | |
10405 | case 'X': | |
bf12938e | 10406 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10407 | break; |
10408 | case 'Y': | |
10409 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10410 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10411 | break; |
10412 | default: | |
10413 | internalError (); | |
10414 | } | |
10415 | ||
10416 | lastregno = regno; | |
10417 | continue; | |
10418 | ||
10419 | case 'P': | |
10420 | if (strncmp (s, "$pc", 3) == 0) | |
10421 | { | |
10422 | s += 3; | |
10423 | continue; | |
10424 | } | |
10425 | break; | |
10426 | ||
252b5132 RH |
10427 | case '5': |
10428 | case 'H': | |
10429 | case 'W': | |
10430 | case 'D': | |
10431 | case 'j': | |
252b5132 RH |
10432 | case 'V': |
10433 | case 'C': | |
10434 | case 'U': | |
10435 | case 'k': | |
10436 | case 'K': | |
d6f16593 MR |
10437 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10438 | if (i > 0) | |
252b5132 | 10439 | { |
d6f16593 | 10440 | if (imm_expr.X_op != O_constant) |
252b5132 | 10441 | { |
b34976b6 | 10442 | mips16_ext = TRUE; |
b34976b6 | 10443 | ip->use_extend = TRUE; |
252b5132 | 10444 | ip->extend = 0; |
252b5132 | 10445 | } |
d6f16593 MR |
10446 | else |
10447 | { | |
10448 | /* We need to relax this instruction. */ | |
10449 | *offset_reloc = *imm_reloc; | |
10450 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10451 | } | |
10452 | s = expr_end; | |
10453 | continue; | |
252b5132 | 10454 | } |
d6f16593 MR |
10455 | *imm_reloc = BFD_RELOC_UNUSED; |
10456 | /* Fall through. */ | |
10457 | case '<': | |
10458 | case '>': | |
10459 | case '[': | |
10460 | case ']': | |
10461 | case '4': | |
10462 | case '8': | |
10463 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10464 | if (imm_expr.X_op == O_register) |
10465 | { | |
10466 | /* What we thought was an expression turned out to | |
10467 | be a register. */ | |
10468 | ||
10469 | if (s[0] == '(' && args[1] == '(') | |
10470 | { | |
10471 | /* It looks like the expression was omitted | |
10472 | before a register indirection, which means | |
10473 | that the expression is implicitly zero. We | |
10474 | still set up imm_expr, so that we handle | |
10475 | explicit extensions correctly. */ | |
10476 | imm_expr.X_op = O_constant; | |
10477 | imm_expr.X_add_number = 0; | |
f6688943 | 10478 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10479 | continue; |
10480 | } | |
10481 | ||
10482 | break; | |
10483 | } | |
10484 | ||
10485 | /* We need to relax this instruction. */ | |
f6688943 | 10486 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10487 | s = expr_end; |
10488 | continue; | |
10489 | ||
10490 | case 'p': | |
10491 | case 'q': | |
10492 | case 'A': | |
10493 | case 'B': | |
10494 | case 'E': | |
10495 | /* We use offset_reloc rather than imm_reloc for the PC | |
10496 | relative operands. This lets macros with both | |
10497 | immediate and address operands work correctly. */ | |
10498 | my_getExpression (&offset_expr, s); | |
10499 | ||
10500 | if (offset_expr.X_op == O_register) | |
10501 | break; | |
10502 | ||
10503 | /* We need to relax this instruction. */ | |
f6688943 | 10504 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10505 | s = expr_end; |
10506 | continue; | |
10507 | ||
10508 | case '6': /* break code */ | |
10509 | my_getExpression (&imm_expr, s); | |
10510 | check_absolute_expr (ip, &imm_expr); | |
10511 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10512 | as_warn (_("Invalid value for `%s' (%lu)"), |
10513 | ip->insn_mo->name, | |
10514 | (unsigned long) imm_expr.X_add_number); | |
10515 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10516 | imm_expr.X_op = O_absent; |
10517 | s = expr_end; | |
10518 | continue; | |
10519 | ||
10520 | case 'a': /* 26 bit address */ | |
10521 | my_getExpression (&offset_expr, s); | |
10522 | s = expr_end; | |
f6688943 | 10523 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10524 | ip->insn_opcode <<= 16; |
10525 | continue; | |
10526 | ||
10527 | case 'l': /* register list for entry macro */ | |
10528 | case 'L': /* register list for exit macro */ | |
10529 | { | |
10530 | int mask; | |
10531 | ||
10532 | if (c == 'l') | |
10533 | mask = 0; | |
10534 | else | |
10535 | mask = 7 << 3; | |
10536 | while (*s != '\0') | |
10537 | { | |
707bfff6 | 10538 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10539 | |
10540 | while (*s == ' ' || *s == ',') | |
10541 | ++s; | |
707bfff6 | 10542 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10543 | freg = 0; |
707bfff6 TS |
10544 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10545 | freg = 1; | |
252b5132 RH |
10546 | else |
10547 | { | |
707bfff6 TS |
10548 | as_bad (_("can't parse register list")); |
10549 | break; | |
252b5132 RH |
10550 | } |
10551 | if (*s == ' ') | |
10552 | ++s; | |
10553 | if (*s != '-') | |
10554 | reg2 = reg1; | |
10555 | else | |
10556 | { | |
10557 | ++s; | |
707bfff6 TS |
10558 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10559 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10560 | { |
707bfff6 TS |
10561 | as_bad (_("invalid register list")); |
10562 | break; | |
252b5132 RH |
10563 | } |
10564 | } | |
10565 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10566 | { | |
10567 | mask &= ~ (7 << 3); | |
10568 | mask |= 5 << 3; | |
10569 | } | |
10570 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10571 | { | |
10572 | mask &= ~ (7 << 3); | |
10573 | mask |= 6 << 3; | |
10574 | } | |
10575 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10576 | mask |= (reg2 - 3) << 3; | |
10577 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10578 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10579 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10580 | mask |= 1; |
10581 | else | |
10582 | { | |
10583 | as_bad (_("invalid register list")); | |
10584 | break; | |
10585 | } | |
10586 | } | |
10587 | /* The mask is filled in in the opcode table for the | |
10588 | benefit of the disassembler. We remove it before | |
10589 | applying the actual mask. */ | |
10590 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10591 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10592 | } | |
10593 | continue; | |
10594 | ||
0499d65b TS |
10595 | case 'm': /* Register list for save insn. */ |
10596 | case 'M': /* Register list for restore insn. */ | |
10597 | { | |
10598 | int opcode = 0; | |
10599 | int framesz = 0, seen_framesz = 0; | |
10600 | int args = 0, statics = 0, sregs = 0; | |
10601 | ||
10602 | while (*s != '\0') | |
10603 | { | |
10604 | unsigned int reg1, reg2; | |
10605 | ||
10606 | SKIP_SPACE_TABS (s); | |
10607 | while (*s == ',') | |
10608 | ++s; | |
10609 | SKIP_SPACE_TABS (s); | |
10610 | ||
10611 | my_getExpression (&imm_expr, s); | |
10612 | if (imm_expr.X_op == O_constant) | |
10613 | { | |
10614 | /* Handle the frame size. */ | |
10615 | if (seen_framesz) | |
10616 | { | |
10617 | as_bad (_("more than one frame size in list")); | |
10618 | break; | |
10619 | } | |
10620 | seen_framesz = 1; | |
10621 | framesz = imm_expr.X_add_number; | |
10622 | imm_expr.X_op = O_absent; | |
10623 | s = expr_end; | |
10624 | continue; | |
10625 | } | |
10626 | ||
707bfff6 | 10627 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10628 | { |
10629 | as_bad (_("can't parse register list")); | |
10630 | break; | |
10631 | } | |
0499d65b | 10632 | |
707bfff6 TS |
10633 | while (*s == ' ') |
10634 | ++s; | |
10635 | ||
0499d65b TS |
10636 | if (*s != '-') |
10637 | reg2 = reg1; | |
10638 | else | |
10639 | { | |
10640 | ++s; | |
707bfff6 TS |
10641 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10642 | || reg2 < reg1) | |
0499d65b TS |
10643 | { |
10644 | as_bad (_("can't parse register list")); | |
10645 | break; | |
10646 | } | |
0499d65b TS |
10647 | } |
10648 | ||
10649 | while (reg1 <= reg2) | |
10650 | { | |
10651 | if (reg1 >= 4 && reg1 <= 7) | |
10652 | { | |
3a93f742 | 10653 | if (!seen_framesz) |
0499d65b TS |
10654 | /* args $a0-$a3 */ |
10655 | args |= 1 << (reg1 - 4); | |
10656 | else | |
10657 | /* statics $a0-$a3 */ | |
10658 | statics |= 1 << (reg1 - 4); | |
10659 | } | |
10660 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10661 | { | |
10662 | /* $s0-$s8 */ | |
10663 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10664 | } | |
10665 | else if (reg1 == 31) | |
10666 | { | |
10667 | /* Add $ra to insn. */ | |
10668 | opcode |= 0x40; | |
10669 | } | |
10670 | else | |
10671 | { | |
10672 | as_bad (_("unexpected register in list")); | |
10673 | break; | |
10674 | } | |
10675 | if (++reg1 == 24) | |
10676 | reg1 = 30; | |
10677 | } | |
10678 | } | |
10679 | ||
10680 | /* Encode args/statics combination. */ | |
10681 | if (args & statics) | |
10682 | as_bad (_("arg/static registers overlap")); | |
10683 | else if (args == 0xf) | |
10684 | /* All $a0-$a3 are args. */ | |
10685 | opcode |= MIPS16_ALL_ARGS << 16; | |
10686 | else if (statics == 0xf) | |
10687 | /* All $a0-$a3 are statics. */ | |
10688 | opcode |= MIPS16_ALL_STATICS << 16; | |
10689 | else | |
10690 | { | |
10691 | int narg = 0, nstat = 0; | |
10692 | ||
10693 | /* Count arg registers. */ | |
10694 | while (args & 0x1) | |
10695 | { | |
10696 | args >>= 1; | |
10697 | narg++; | |
10698 | } | |
10699 | if (args != 0) | |
10700 | as_bad (_("invalid arg register list")); | |
10701 | ||
10702 | /* Count static registers. */ | |
10703 | while (statics & 0x8) | |
10704 | { | |
10705 | statics = (statics << 1) & 0xf; | |
10706 | nstat++; | |
10707 | } | |
10708 | if (statics != 0) | |
10709 | as_bad (_("invalid static register list")); | |
10710 | ||
10711 | /* Encode args/statics. */ | |
10712 | opcode |= ((narg << 2) | nstat) << 16; | |
10713 | } | |
10714 | ||
10715 | /* Encode $s0/$s1. */ | |
10716 | if (sregs & (1 << 0)) /* $s0 */ | |
10717 | opcode |= 0x20; | |
10718 | if (sregs & (1 << 1)) /* $s1 */ | |
10719 | opcode |= 0x10; | |
10720 | sregs >>= 2; | |
10721 | ||
10722 | if (sregs != 0) | |
10723 | { | |
10724 | /* Count regs $s2-$s8. */ | |
10725 | int nsreg = 0; | |
10726 | while (sregs & 1) | |
10727 | { | |
10728 | sregs >>= 1; | |
10729 | nsreg++; | |
10730 | } | |
10731 | if (sregs != 0) | |
10732 | as_bad (_("invalid static register list")); | |
10733 | /* Encode $s2-$s8. */ | |
10734 | opcode |= nsreg << 24; | |
10735 | } | |
10736 | ||
10737 | /* Encode frame size. */ | |
10738 | if (!seen_framesz) | |
10739 | as_bad (_("missing frame size")); | |
10740 | else if ((framesz & 7) != 0 || framesz < 0 | |
10741 | || framesz > 0xff * 8) | |
10742 | as_bad (_("invalid frame size")); | |
10743 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10744 | { | |
10745 | framesz /= 8; | |
10746 | opcode |= (((framesz & 0xf0) << 16) | |
10747 | | (framesz & 0x0f)); | |
10748 | } | |
10749 | ||
10750 | /* Finally build the instruction. */ | |
10751 | if ((opcode >> 16) != 0 || framesz == 0) | |
10752 | { | |
10753 | ip->use_extend = TRUE; | |
10754 | ip->extend = opcode >> 16; | |
10755 | } | |
10756 | ip->insn_opcode |= opcode & 0x7f; | |
10757 | } | |
10758 | continue; | |
10759 | ||
252b5132 RH |
10760 | case 'e': /* extend code */ |
10761 | my_getExpression (&imm_expr, s); | |
10762 | check_absolute_expr (ip, &imm_expr); | |
10763 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10764 | { | |
10765 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10766 | ip->insn_mo->name, | |
10767 | (unsigned long) imm_expr.X_add_number); | |
10768 | imm_expr.X_add_number &= 0x7ff; | |
10769 | } | |
10770 | ip->insn_opcode |= imm_expr.X_add_number; | |
10771 | imm_expr.X_op = O_absent; | |
10772 | s = expr_end; | |
10773 | continue; | |
10774 | ||
10775 | default: | |
10776 | internalError (); | |
10777 | } | |
10778 | break; | |
10779 | } | |
10780 | ||
10781 | /* Args don't match. */ | |
10782 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10783 | strcmp (insn->name, insn[1].name) == 0) | |
10784 | { | |
10785 | ++insn; | |
10786 | s = argsstart; | |
10787 | continue; | |
10788 | } | |
10789 | ||
10790 | insn_error = _("illegal operands"); | |
10791 | ||
10792 | return; | |
10793 | } | |
10794 | } | |
10795 | ||
10796 | /* This structure holds information we know about a mips16 immediate | |
10797 | argument type. */ | |
10798 | ||
e972090a NC |
10799 | struct mips16_immed_operand |
10800 | { | |
252b5132 RH |
10801 | /* The type code used in the argument string in the opcode table. */ |
10802 | int type; | |
10803 | /* The number of bits in the short form of the opcode. */ | |
10804 | int nbits; | |
10805 | /* The number of bits in the extended form of the opcode. */ | |
10806 | int extbits; | |
10807 | /* The amount by which the short form is shifted when it is used; | |
10808 | for example, the sw instruction has a shift count of 2. */ | |
10809 | int shift; | |
10810 | /* The amount by which the short form is shifted when it is stored | |
10811 | into the instruction code. */ | |
10812 | int op_shift; | |
10813 | /* Non-zero if the short form is unsigned. */ | |
10814 | int unsp; | |
10815 | /* Non-zero if the extended form is unsigned. */ | |
10816 | int extu; | |
10817 | /* Non-zero if the value is PC relative. */ | |
10818 | int pcrel; | |
10819 | }; | |
10820 | ||
10821 | /* The mips16 immediate operand types. */ | |
10822 | ||
10823 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10824 | { | |
10825 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10826 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10827 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10828 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10829 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10830 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10831 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10832 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10833 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10834 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10835 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10836 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10837 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10838 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10839 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10840 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10841 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10842 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10843 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10844 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10845 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10846 | }; | |
10847 | ||
10848 | #define MIPS16_NUM_IMMED \ | |
10849 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10850 | ||
10851 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10852 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10853 | whether an extended value is needed; if one is needed, it sets | |
10854 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10855 | If SMALL is true, an unextended opcode was explicitly requested. | |
10856 | If EXT is true, an extended opcode was explicitly requested. If | |
10857 | WARN is true, warn if EXT does not match reality. */ | |
10858 | ||
10859 | static void | |
17a2f251 TS |
10860 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10861 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10862 | unsigned long *insn, bfd_boolean *use_extend, | |
10863 | unsigned short *extend) | |
252b5132 | 10864 | { |
3994f87e | 10865 | const struct mips16_immed_operand *op; |
252b5132 | 10866 | int mintiny, maxtiny; |
b34976b6 | 10867 | bfd_boolean needext; |
252b5132 RH |
10868 | |
10869 | op = mips16_immed_operands; | |
10870 | while (op->type != type) | |
10871 | { | |
10872 | ++op; | |
9c2799c2 | 10873 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
10874 | } |
10875 | ||
10876 | if (op->unsp) | |
10877 | { | |
10878 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10879 | { | |
10880 | mintiny = 1; | |
10881 | maxtiny = 1 << op->nbits; | |
10882 | } | |
10883 | else | |
10884 | { | |
10885 | mintiny = 0; | |
10886 | maxtiny = (1 << op->nbits) - 1; | |
10887 | } | |
10888 | } | |
10889 | else | |
10890 | { | |
10891 | mintiny = - (1 << (op->nbits - 1)); | |
10892 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10893 | } | |
10894 | ||
10895 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10896 | if (type == 'p' || type == 'q') | |
10897 | val /= 2; | |
10898 | ||
10899 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10900 | || val < (mintiny << op->shift) | |
10901 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10902 | needext = TRUE; |
252b5132 | 10903 | else |
b34976b6 | 10904 | needext = FALSE; |
252b5132 RH |
10905 | |
10906 | if (warn && ext && ! needext) | |
beae10d5 KH |
10907 | as_warn_where (file, line, |
10908 | _("extended operand requested but not required")); | |
252b5132 RH |
10909 | if (small && needext) |
10910 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10911 | ||
10912 | if (small || (! ext && ! needext)) | |
10913 | { | |
10914 | int insnval; | |
10915 | ||
b34976b6 | 10916 | *use_extend = FALSE; |
252b5132 RH |
10917 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10918 | insnval <<= op->op_shift; | |
10919 | *insn |= insnval; | |
10920 | } | |
10921 | else | |
10922 | { | |
10923 | long minext, maxext; | |
10924 | int extval; | |
10925 | ||
10926 | if (op->extu) | |
10927 | { | |
10928 | minext = 0; | |
10929 | maxext = (1 << op->extbits) - 1; | |
10930 | } | |
10931 | else | |
10932 | { | |
10933 | minext = - (1 << (op->extbits - 1)); | |
10934 | maxext = (1 << (op->extbits - 1)) - 1; | |
10935 | } | |
10936 | if (val < minext || val > maxext) | |
10937 | as_bad_where (file, line, | |
10938 | _("operand value out of range for instruction")); | |
10939 | ||
b34976b6 | 10940 | *use_extend = TRUE; |
252b5132 RH |
10941 | if (op->extbits == 16) |
10942 | { | |
10943 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10944 | val &= 0x1f; | |
10945 | } | |
10946 | else if (op->extbits == 15) | |
10947 | { | |
10948 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10949 | val &= 0xf; | |
10950 | } | |
10951 | else | |
10952 | { | |
10953 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10954 | val = 0; | |
10955 | } | |
10956 | ||
10957 | *extend = (unsigned short) extval; | |
10958 | *insn |= val; | |
10959 | } | |
10960 | } | |
10961 | \f | |
d6f16593 | 10962 | struct percent_op_match |
ad8d3bb3 | 10963 | { |
5e0116d5 RS |
10964 | const char *str; |
10965 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10966 | }; |
10967 | ||
10968 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10969 | { |
5e0116d5 | 10970 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10971 | #ifdef OBJ_ELF |
5e0116d5 RS |
10972 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10973 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10974 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10975 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10976 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10977 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10978 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10979 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10980 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10981 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10982 | {"%half", BFD_RELOC_16}, | |
10983 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10984 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10985 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10986 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10987 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10988 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10989 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10990 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10991 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10992 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10993 | #endif |
5e0116d5 | 10994 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10995 | }; |
10996 | ||
d6f16593 MR |
10997 | static const struct percent_op_match mips16_percent_op[] = |
10998 | { | |
10999 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11000 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11001 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11002 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11003 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11004 | }; | |
11005 | ||
252b5132 | 11006 | |
5e0116d5 RS |
11007 | /* Return true if *STR points to a relocation operator. When returning true, |
11008 | move *STR over the operator and store its relocation code in *RELOC. | |
11009 | Leave both *STR and *RELOC alone when returning false. */ | |
11010 | ||
11011 | static bfd_boolean | |
17a2f251 | 11012 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11013 | { |
d6f16593 MR |
11014 | const struct percent_op_match *percent_op; |
11015 | size_t limit, i; | |
11016 | ||
11017 | if (mips_opts.mips16) | |
11018 | { | |
11019 | percent_op = mips16_percent_op; | |
11020 | limit = ARRAY_SIZE (mips16_percent_op); | |
11021 | } | |
11022 | else | |
11023 | { | |
11024 | percent_op = mips_percent_op; | |
11025 | limit = ARRAY_SIZE (mips_percent_op); | |
11026 | } | |
76b3015f | 11027 | |
d6f16593 | 11028 | for (i = 0; i < limit; i++) |
5e0116d5 | 11029 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11030 | { |
3f98094e DJ |
11031 | int len = strlen (percent_op[i].str); |
11032 | ||
11033 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11034 | continue; | |
11035 | ||
5e0116d5 RS |
11036 | *str += strlen (percent_op[i].str); |
11037 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11038 | |
5e0116d5 RS |
11039 | /* Check whether the output BFD supports this relocation. |
11040 | If not, issue an error and fall back on something safe. */ | |
11041 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11042 | { |
20203fb9 | 11043 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11044 | percent_op[i].str); |
01a3f561 | 11045 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11046 | } |
5e0116d5 | 11047 | return TRUE; |
394f9b3a | 11048 | } |
5e0116d5 | 11049 | return FALSE; |
394f9b3a | 11050 | } |
ad8d3bb3 | 11051 | |
ad8d3bb3 | 11052 | |
5e0116d5 RS |
11053 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11054 | expression in *EP and the relocations in the array starting | |
11055 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11056 | |
01a3f561 | 11057 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11058 | |
5e0116d5 | 11059 | static size_t |
17a2f251 TS |
11060 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11061 | char *str) | |
ad8d3bb3 | 11062 | { |
5e0116d5 RS |
11063 | bfd_reloc_code_real_type reversed_reloc[3]; |
11064 | size_t reloc_index, i; | |
09b8f35a RS |
11065 | int crux_depth, str_depth; |
11066 | char *crux; | |
5e0116d5 RS |
11067 | |
11068 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11069 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11070 | of the main expression and with CRUX_DEPTH containing the number | |
11071 | of open brackets at that point. */ | |
11072 | reloc_index = -1; | |
11073 | str_depth = 0; | |
11074 | do | |
fb1b3232 | 11075 | { |
09b8f35a RS |
11076 | reloc_index++; |
11077 | crux = str; | |
11078 | crux_depth = str_depth; | |
11079 | ||
11080 | /* Skip over whitespace and brackets, keeping count of the number | |
11081 | of brackets. */ | |
11082 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11083 | if (*str++ == '(') | |
11084 | str_depth++; | |
5e0116d5 | 11085 | } |
09b8f35a RS |
11086 | while (*str == '%' |
11087 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11088 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11089 | |
09b8f35a | 11090 | my_getExpression (ep, crux); |
5e0116d5 | 11091 | str = expr_end; |
394f9b3a | 11092 | |
5e0116d5 | 11093 | /* Match every open bracket. */ |
09b8f35a | 11094 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11095 | if (*str++ == ')') |
09b8f35a | 11096 | crux_depth--; |
394f9b3a | 11097 | |
09b8f35a | 11098 | if (crux_depth > 0) |
20203fb9 | 11099 | as_bad (_("unclosed '('")); |
394f9b3a | 11100 | |
5e0116d5 | 11101 | expr_end = str; |
252b5132 | 11102 | |
01a3f561 | 11103 | if (reloc_index != 0) |
64bdfcaf RS |
11104 | { |
11105 | prev_reloc_op_frag = frag_now; | |
11106 | for (i = 0; i < reloc_index; i++) | |
11107 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11108 | } | |
fb1b3232 | 11109 | |
5e0116d5 | 11110 | return reloc_index; |
252b5132 RH |
11111 | } |
11112 | ||
11113 | static void | |
17a2f251 | 11114 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11115 | { |
11116 | char *save_in; | |
98aa84af | 11117 | valueT val; |
252b5132 RH |
11118 | |
11119 | save_in = input_line_pointer; | |
11120 | input_line_pointer = str; | |
11121 | expression (ep); | |
11122 | expr_end = input_line_pointer; | |
11123 | input_line_pointer = save_in; | |
11124 | ||
11125 | /* If we are in mips16 mode, and this is an expression based on `.', | |
11126 | then we bump the value of the symbol by 1 since that is how other | |
11127 | text symbols are handled. We don't bother to handle complex | |
11128 | expressions, just `.' plus or minus a constant. */ | |
11129 | if (mips_opts.mips16 | |
11130 | && ep->X_op == O_symbol | |
11131 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
11132 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
11133 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
11134 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
11135 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
11136 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
11137 | } |
11138 | ||
252b5132 | 11139 | char * |
17a2f251 | 11140 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11141 | { |
499ac353 | 11142 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11143 | } |
11144 | ||
11145 | void | |
17a2f251 | 11146 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11147 | { |
11148 | if (target_big_endian) | |
11149 | number_to_chars_bigendian (buf, val, n); | |
11150 | else | |
11151 | number_to_chars_littleendian (buf, val, n); | |
11152 | } | |
11153 | \f | |
ae948b86 | 11154 | #ifdef OBJ_ELF |
e013f690 TS |
11155 | static int support_64bit_objects(void) |
11156 | { | |
11157 | const char **list, **l; | |
aa3d8fdf | 11158 | int yes; |
e013f690 TS |
11159 | |
11160 | list = bfd_target_list (); | |
11161 | for (l = list; *l != NULL; l++) | |
11162 | #ifdef TE_TMIPS | |
11163 | /* This is traditional mips */ | |
11164 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
11165 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
11166 | #else | |
11167 | if (strcmp (*l, "elf64-bigmips") == 0 | |
11168 | || strcmp (*l, "elf64-littlemips") == 0) | |
11169 | #endif | |
11170 | break; | |
aa3d8fdf | 11171 | yes = (*l != NULL); |
e013f690 | 11172 | free (list); |
aa3d8fdf | 11173 | return yes; |
e013f690 | 11174 | } |
ae948b86 | 11175 | #endif /* OBJ_ELF */ |
e013f690 | 11176 | |
78849248 | 11177 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11178 | |
23fce1e3 NC |
11179 | enum options |
11180 | { | |
11181 | OPTION_MARCH = OPTION_MD_BASE, | |
11182 | OPTION_MTUNE, | |
11183 | OPTION_MIPS1, | |
11184 | OPTION_MIPS2, | |
11185 | OPTION_MIPS3, | |
11186 | OPTION_MIPS4, | |
11187 | OPTION_MIPS5, | |
11188 | OPTION_MIPS32, | |
11189 | OPTION_MIPS64, | |
11190 | OPTION_MIPS32R2, | |
11191 | OPTION_MIPS64R2, | |
11192 | OPTION_MIPS16, | |
11193 | OPTION_NO_MIPS16, | |
11194 | OPTION_MIPS3D, | |
11195 | OPTION_NO_MIPS3D, | |
11196 | OPTION_MDMX, | |
11197 | OPTION_NO_MDMX, | |
11198 | OPTION_DSP, | |
11199 | OPTION_NO_DSP, | |
11200 | OPTION_MT, | |
11201 | OPTION_NO_MT, | |
11202 | OPTION_SMARTMIPS, | |
11203 | OPTION_NO_SMARTMIPS, | |
11204 | OPTION_DSPR2, | |
11205 | OPTION_NO_DSPR2, | |
11206 | OPTION_COMPAT_ARCH_BASE, | |
11207 | OPTION_M4650, | |
11208 | OPTION_NO_M4650, | |
11209 | OPTION_M4010, | |
11210 | OPTION_NO_M4010, | |
11211 | OPTION_M4100, | |
11212 | OPTION_NO_M4100, | |
11213 | OPTION_M3900, | |
11214 | OPTION_NO_M3900, | |
11215 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11216 | OPTION_MNO_7000_HILO_FIX, |
11217 | OPTION_FIX_24K, | |
11218 | OPTION_NO_FIX_24K, | |
23fce1e3 NC |
11219 | OPTION_FIX_VR4120, |
11220 | OPTION_NO_FIX_VR4120, | |
11221 | OPTION_FIX_VR4130, | |
11222 | OPTION_NO_FIX_VR4130, | |
11223 | OPTION_TRAP, | |
11224 | OPTION_BREAK, | |
11225 | OPTION_EB, | |
11226 | OPTION_EL, | |
11227 | OPTION_FP32, | |
11228 | OPTION_GP32, | |
11229 | OPTION_CONSTRUCT_FLOATS, | |
11230 | OPTION_NO_CONSTRUCT_FLOATS, | |
11231 | OPTION_FP64, | |
11232 | OPTION_GP64, | |
11233 | OPTION_RELAX_BRANCH, | |
11234 | OPTION_NO_RELAX_BRANCH, | |
11235 | OPTION_MSHARED, | |
11236 | OPTION_MNO_SHARED, | |
11237 | OPTION_MSYM32, | |
11238 | OPTION_MNO_SYM32, | |
11239 | OPTION_SOFT_FLOAT, | |
11240 | OPTION_HARD_FLOAT, | |
11241 | OPTION_SINGLE_FLOAT, | |
11242 | OPTION_DOUBLE_FLOAT, | |
11243 | OPTION_32, | |
11244 | #ifdef OBJ_ELF | |
11245 | OPTION_CALL_SHARED, | |
11246 | OPTION_CALL_NONPIC, | |
11247 | OPTION_NON_SHARED, | |
11248 | OPTION_XGOT, | |
11249 | OPTION_MABI, | |
11250 | OPTION_N32, | |
11251 | OPTION_64, | |
11252 | OPTION_MDEBUG, | |
11253 | OPTION_NO_MDEBUG, | |
11254 | OPTION_PDR, | |
11255 | OPTION_NO_PDR, | |
11256 | OPTION_MVXWORKS_PIC, | |
11257 | #endif /* OBJ_ELF */ | |
11258 | OPTION_END_OF_ENUM | |
11259 | }; | |
11260 | ||
e972090a NC |
11261 | struct option md_longopts[] = |
11262 | { | |
f9b4148d | 11263 | /* Options which specify architecture. */ |
f9b4148d | 11264 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11265 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11266 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11267 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11268 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11269 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11270 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11271 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11272 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11273 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11274 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11275 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11276 | |
11277 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11278 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11279 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11280 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11281 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11282 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11283 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11284 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11285 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11286 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11287 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11288 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11289 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11290 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11291 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11292 | |
11293 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11294 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11295 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11296 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11297 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11298 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11299 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11300 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11301 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11302 | ||
11303 | /* Options which enable bug fixes. */ | |
f9b4148d | 11304 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11305 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11306 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
11307 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11308 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11309 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11310 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11311 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11312 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
f9b4148d CD |
11313 | |
11314 | /* Miscellaneous options. */ | |
252b5132 RH |
11315 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11316 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11317 | {"break", no_argument, NULL, OPTION_BREAK}, |
11318 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11319 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11320 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11321 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11322 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11323 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11324 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11325 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11326 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11327 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11328 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11329 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11330 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11331 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11332 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11333 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11334 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11335 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11336 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11337 | |
11338 | /* Strictly speaking this next option is ELF specific, | |
11339 | but we allow it for other ports as well in order to | |
11340 | make testing easier. */ | |
11341 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11342 | |
f9b4148d | 11343 | /* ELF-specific options. */ |
156c2f8b | 11344 | #ifdef OBJ_ELF |
156c2f8b NC |
11345 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11346 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11347 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11348 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11349 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11350 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11351 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11352 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11353 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11354 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11355 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11356 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11357 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11358 | #endif /* OBJ_ELF */ |
f9b4148d | 11359 | |
252b5132 RH |
11360 | {NULL, no_argument, NULL, 0} |
11361 | }; | |
156c2f8b | 11362 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11363 | |
316f5878 RS |
11364 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11365 | NEW_VALUE. Warn if another value was already specified. Note: | |
11366 | we have to defer parsing the -march and -mtune arguments in order | |
11367 | to handle 'from-abi' correctly, since the ABI might be specified | |
11368 | in a later argument. */ | |
11369 | ||
11370 | static void | |
17a2f251 | 11371 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11372 | { |
11373 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11374 | as_warn (_("A different %s was already specified, is now %s"), | |
11375 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11376 | new_value); | |
11377 | ||
11378 | *string_ptr = new_value; | |
11379 | } | |
11380 | ||
252b5132 | 11381 | int |
17a2f251 | 11382 | md_parse_option (int c, char *arg) |
252b5132 RH |
11383 | { |
11384 | switch (c) | |
11385 | { | |
119d663a NC |
11386 | case OPTION_CONSTRUCT_FLOATS: |
11387 | mips_disable_float_construction = 0; | |
11388 | break; | |
bdaaa2e1 | 11389 | |
119d663a NC |
11390 | case OPTION_NO_CONSTRUCT_FLOATS: |
11391 | mips_disable_float_construction = 1; | |
11392 | break; | |
bdaaa2e1 | 11393 | |
252b5132 RH |
11394 | case OPTION_TRAP: |
11395 | mips_trap = 1; | |
11396 | break; | |
11397 | ||
11398 | case OPTION_BREAK: | |
11399 | mips_trap = 0; | |
11400 | break; | |
11401 | ||
11402 | case OPTION_EB: | |
11403 | target_big_endian = 1; | |
11404 | break; | |
11405 | ||
11406 | case OPTION_EL: | |
11407 | target_big_endian = 0; | |
11408 | break; | |
11409 | ||
11410 | case 'O': | |
4ffff32f TS |
11411 | if (arg == NULL) |
11412 | mips_optimize = 1; | |
11413 | else if (arg[0] == '0') | |
11414 | mips_optimize = 0; | |
11415 | else if (arg[0] == '1') | |
252b5132 RH |
11416 | mips_optimize = 1; |
11417 | else | |
11418 | mips_optimize = 2; | |
11419 | break; | |
11420 | ||
11421 | case 'g': | |
11422 | if (arg == NULL) | |
11423 | mips_debug = 2; | |
11424 | else | |
11425 | mips_debug = atoi (arg); | |
252b5132 RH |
11426 | break; |
11427 | ||
11428 | case OPTION_MIPS1: | |
316f5878 | 11429 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11430 | break; |
11431 | ||
11432 | case OPTION_MIPS2: | |
316f5878 | 11433 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11434 | break; |
11435 | ||
11436 | case OPTION_MIPS3: | |
316f5878 | 11437 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11438 | break; |
11439 | ||
11440 | case OPTION_MIPS4: | |
316f5878 | 11441 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11442 | break; |
11443 | ||
84ea6cf2 | 11444 | case OPTION_MIPS5: |
316f5878 | 11445 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11446 | break; |
11447 | ||
e7af610e | 11448 | case OPTION_MIPS32: |
316f5878 | 11449 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11450 | break; |
11451 | ||
af7ee8bf CD |
11452 | case OPTION_MIPS32R2: |
11453 | file_mips_isa = ISA_MIPS32R2; | |
11454 | break; | |
11455 | ||
5f74bc13 CD |
11456 | case OPTION_MIPS64R2: |
11457 | file_mips_isa = ISA_MIPS64R2; | |
11458 | break; | |
11459 | ||
84ea6cf2 | 11460 | case OPTION_MIPS64: |
316f5878 | 11461 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11462 | break; |
11463 | ||
ec68c924 | 11464 | case OPTION_MTUNE: |
316f5878 RS |
11465 | mips_set_option_string (&mips_tune_string, arg); |
11466 | break; | |
ec68c924 | 11467 | |
316f5878 RS |
11468 | case OPTION_MARCH: |
11469 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11470 | break; |
11471 | ||
11472 | case OPTION_M4650: | |
316f5878 RS |
11473 | mips_set_option_string (&mips_arch_string, "4650"); |
11474 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11475 | break; |
11476 | ||
11477 | case OPTION_NO_M4650: | |
11478 | break; | |
11479 | ||
11480 | case OPTION_M4010: | |
316f5878 RS |
11481 | mips_set_option_string (&mips_arch_string, "4010"); |
11482 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11483 | break; |
11484 | ||
11485 | case OPTION_NO_M4010: | |
11486 | break; | |
11487 | ||
11488 | case OPTION_M4100: | |
316f5878 RS |
11489 | mips_set_option_string (&mips_arch_string, "4100"); |
11490 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11491 | break; |
11492 | ||
11493 | case OPTION_NO_M4100: | |
11494 | break; | |
11495 | ||
252b5132 | 11496 | case OPTION_M3900: |
316f5878 RS |
11497 | mips_set_option_string (&mips_arch_string, "3900"); |
11498 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11499 | break; |
bdaaa2e1 | 11500 | |
252b5132 RH |
11501 | case OPTION_NO_M3900: |
11502 | break; | |
11503 | ||
deec1734 CD |
11504 | case OPTION_MDMX: |
11505 | mips_opts.ase_mdmx = 1; | |
11506 | break; | |
11507 | ||
11508 | case OPTION_NO_MDMX: | |
11509 | mips_opts.ase_mdmx = 0; | |
11510 | break; | |
11511 | ||
74cd071d CF |
11512 | case OPTION_DSP: |
11513 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11514 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11515 | break; |
11516 | ||
11517 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11518 | mips_opts.ase_dsp = 0; |
11519 | mips_opts.ase_dspr2 = 0; | |
11520 | break; | |
11521 | ||
11522 | case OPTION_DSPR2: | |
11523 | mips_opts.ase_dspr2 = 1; | |
11524 | mips_opts.ase_dsp = 1; | |
11525 | break; | |
11526 | ||
11527 | case OPTION_NO_DSPR2: | |
11528 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11529 | mips_opts.ase_dsp = 0; |
11530 | break; | |
11531 | ||
ef2e4d86 CF |
11532 | case OPTION_MT: |
11533 | mips_opts.ase_mt = 1; | |
11534 | break; | |
11535 | ||
11536 | case OPTION_NO_MT: | |
11537 | mips_opts.ase_mt = 0; | |
11538 | break; | |
11539 | ||
252b5132 RH |
11540 | case OPTION_MIPS16: |
11541 | mips_opts.mips16 = 1; | |
7d10b47d | 11542 | mips_no_prev_insn (); |
252b5132 RH |
11543 | break; |
11544 | ||
11545 | case OPTION_NO_MIPS16: | |
11546 | mips_opts.mips16 = 0; | |
7d10b47d | 11547 | mips_no_prev_insn (); |
252b5132 RH |
11548 | break; |
11549 | ||
1f25f5d3 CD |
11550 | case OPTION_MIPS3D: |
11551 | mips_opts.ase_mips3d = 1; | |
11552 | break; | |
11553 | ||
11554 | case OPTION_NO_MIPS3D: | |
11555 | mips_opts.ase_mips3d = 0; | |
11556 | break; | |
11557 | ||
e16bfa71 TS |
11558 | case OPTION_SMARTMIPS: |
11559 | mips_opts.ase_smartmips = 1; | |
11560 | break; | |
11561 | ||
11562 | case OPTION_NO_SMARTMIPS: | |
11563 | mips_opts.ase_smartmips = 0; | |
11564 | break; | |
11565 | ||
6a32d874 CM |
11566 | case OPTION_FIX_24K: |
11567 | mips_fix_24k = 1; | |
11568 | break; | |
11569 | ||
11570 | case OPTION_NO_FIX_24K: | |
11571 | mips_fix_24k = 0; | |
11572 | break; | |
11573 | ||
d766e8ec RS |
11574 | case OPTION_FIX_VR4120: |
11575 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11576 | break; |
11577 | ||
d766e8ec RS |
11578 | case OPTION_NO_FIX_VR4120: |
11579 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11580 | break; |
11581 | ||
7d8e00cf RS |
11582 | case OPTION_FIX_VR4130: |
11583 | mips_fix_vr4130 = 1; | |
11584 | break; | |
11585 | ||
11586 | case OPTION_NO_FIX_VR4130: | |
11587 | mips_fix_vr4130 = 0; | |
11588 | break; | |
11589 | ||
4a6a3df4 AO |
11590 | case OPTION_RELAX_BRANCH: |
11591 | mips_relax_branch = 1; | |
11592 | break; | |
11593 | ||
11594 | case OPTION_NO_RELAX_BRANCH: | |
11595 | mips_relax_branch = 0; | |
11596 | break; | |
11597 | ||
aa6975fb ILT |
11598 | case OPTION_MSHARED: |
11599 | mips_in_shared = TRUE; | |
11600 | break; | |
11601 | ||
11602 | case OPTION_MNO_SHARED: | |
11603 | mips_in_shared = FALSE; | |
11604 | break; | |
11605 | ||
aed1a261 RS |
11606 | case OPTION_MSYM32: |
11607 | mips_opts.sym32 = TRUE; | |
11608 | break; | |
11609 | ||
11610 | case OPTION_MNO_SYM32: | |
11611 | mips_opts.sym32 = FALSE; | |
11612 | break; | |
11613 | ||
0f074f60 | 11614 | #ifdef OBJ_ELF |
252b5132 RH |
11615 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11616 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11617 | intended to be compatible with Irix 5. */ | |
11618 | case OPTION_CALL_SHARED: | |
f43abd2b | 11619 | if (!IS_ELF) |
252b5132 RH |
11620 | { |
11621 | as_bad (_("-call_shared is supported only for ELF format")); | |
11622 | return 0; | |
11623 | } | |
11624 | mips_pic = SVR4_PIC; | |
143d77c5 | 11625 | mips_abicalls = TRUE; |
252b5132 RH |
11626 | break; |
11627 | ||
861fb55a DJ |
11628 | case OPTION_CALL_NONPIC: |
11629 | if (!IS_ELF) | |
11630 | { | |
11631 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11632 | return 0; | |
11633 | } | |
11634 | mips_pic = NO_PIC; | |
11635 | mips_abicalls = TRUE; | |
11636 | break; | |
11637 | ||
252b5132 | 11638 | case OPTION_NON_SHARED: |
f43abd2b | 11639 | if (!IS_ELF) |
252b5132 RH |
11640 | { |
11641 | as_bad (_("-non_shared is supported only for ELF format")); | |
11642 | return 0; | |
11643 | } | |
11644 | mips_pic = NO_PIC; | |
143d77c5 | 11645 | mips_abicalls = FALSE; |
252b5132 RH |
11646 | break; |
11647 | ||
44075ae2 TS |
11648 | /* The -xgot option tells the assembler to use 32 bit offsets |
11649 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11650 | compatibility. */ |
11651 | case OPTION_XGOT: | |
11652 | mips_big_got = 1; | |
11653 | break; | |
0f074f60 | 11654 | #endif /* OBJ_ELF */ |
252b5132 RH |
11655 | |
11656 | case 'G': | |
6caf9ef4 TS |
11657 | g_switch_value = atoi (arg); |
11658 | g_switch_seen = 1; | |
252b5132 RH |
11659 | break; |
11660 | ||
34ba82a8 TS |
11661 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11662 | and -mabi=64. */ | |
252b5132 | 11663 | case OPTION_32: |
23fce1e3 NC |
11664 | if (IS_ELF) |
11665 | mips_abi = O32_ABI; | |
11666 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11667 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11668 | break; |
11669 | ||
23fce1e3 | 11670 | #ifdef OBJ_ELF |
e013f690 | 11671 | case OPTION_N32: |
f43abd2b | 11672 | if (!IS_ELF) |
34ba82a8 TS |
11673 | { |
11674 | as_bad (_("-n32 is supported for ELF format only")); | |
11675 | return 0; | |
11676 | } | |
316f5878 | 11677 | mips_abi = N32_ABI; |
e013f690 | 11678 | break; |
252b5132 | 11679 | |
e013f690 | 11680 | case OPTION_64: |
f43abd2b | 11681 | if (!IS_ELF) |
34ba82a8 TS |
11682 | { |
11683 | as_bad (_("-64 is supported for ELF format only")); | |
11684 | return 0; | |
11685 | } | |
316f5878 | 11686 | mips_abi = N64_ABI; |
f43abd2b | 11687 | if (!support_64bit_objects()) |
e013f690 | 11688 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11689 | break; |
ae948b86 | 11690 | #endif /* OBJ_ELF */ |
252b5132 | 11691 | |
c97ef257 | 11692 | case OPTION_GP32: |
a325df1d | 11693 | file_mips_gp32 = 1; |
c97ef257 AH |
11694 | break; |
11695 | ||
11696 | case OPTION_GP64: | |
a325df1d | 11697 | file_mips_gp32 = 0; |
c97ef257 | 11698 | break; |
252b5132 | 11699 | |
ca4e0257 | 11700 | case OPTION_FP32: |
a325df1d | 11701 | file_mips_fp32 = 1; |
316f5878 RS |
11702 | break; |
11703 | ||
11704 | case OPTION_FP64: | |
11705 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11706 | break; |
11707 | ||
037b32b9 AN |
11708 | case OPTION_SINGLE_FLOAT: |
11709 | file_mips_single_float = 1; | |
11710 | break; | |
11711 | ||
11712 | case OPTION_DOUBLE_FLOAT: | |
11713 | file_mips_single_float = 0; | |
11714 | break; | |
11715 | ||
11716 | case OPTION_SOFT_FLOAT: | |
11717 | file_mips_soft_float = 1; | |
11718 | break; | |
11719 | ||
11720 | case OPTION_HARD_FLOAT: | |
11721 | file_mips_soft_float = 0; | |
11722 | break; | |
11723 | ||
ae948b86 | 11724 | #ifdef OBJ_ELF |
252b5132 | 11725 | case OPTION_MABI: |
f43abd2b | 11726 | if (!IS_ELF) |
34ba82a8 TS |
11727 | { |
11728 | as_bad (_("-mabi is supported for ELF format only")); | |
11729 | return 0; | |
11730 | } | |
e013f690 | 11731 | if (strcmp (arg, "32") == 0) |
316f5878 | 11732 | mips_abi = O32_ABI; |
e013f690 | 11733 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11734 | mips_abi = O64_ABI; |
e013f690 | 11735 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11736 | mips_abi = N32_ABI; |
e013f690 TS |
11737 | else if (strcmp (arg, "64") == 0) |
11738 | { | |
316f5878 | 11739 | mips_abi = N64_ABI; |
e013f690 TS |
11740 | if (! support_64bit_objects()) |
11741 | as_fatal (_("No compiled in support for 64 bit object file " | |
11742 | "format")); | |
11743 | } | |
11744 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11745 | mips_abi = EABI_ABI; |
e013f690 | 11746 | else |
da0e507f TS |
11747 | { |
11748 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11749 | return 0; | |
11750 | } | |
252b5132 | 11751 | break; |
e013f690 | 11752 | #endif /* OBJ_ELF */ |
252b5132 | 11753 | |
6b76fefe | 11754 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11755 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11756 | break; |
11757 | ||
9ee72ff1 | 11758 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11759 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11760 | break; |
11761 | ||
ecb4347a DJ |
11762 | #ifdef OBJ_ELF |
11763 | case OPTION_MDEBUG: | |
b34976b6 | 11764 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11765 | break; |
11766 | ||
11767 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11768 | mips_flag_mdebug = FALSE; |
ecb4347a | 11769 | break; |
dcd410fe RO |
11770 | |
11771 | case OPTION_PDR: | |
11772 | mips_flag_pdr = TRUE; | |
11773 | break; | |
11774 | ||
11775 | case OPTION_NO_PDR: | |
11776 | mips_flag_pdr = FALSE; | |
11777 | break; | |
0a44bf69 RS |
11778 | |
11779 | case OPTION_MVXWORKS_PIC: | |
11780 | mips_pic = VXWORKS_PIC; | |
11781 | break; | |
ecb4347a DJ |
11782 | #endif /* OBJ_ELF */ |
11783 | ||
252b5132 RH |
11784 | default: |
11785 | return 0; | |
11786 | } | |
11787 | ||
11788 | return 1; | |
11789 | } | |
316f5878 RS |
11790 | \f |
11791 | /* Set up globals to generate code for the ISA or processor | |
11792 | described by INFO. */ | |
252b5132 | 11793 | |
252b5132 | 11794 | static void |
17a2f251 | 11795 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11796 | { |
316f5878 | 11797 | if (info != 0) |
252b5132 | 11798 | { |
fef14a42 TS |
11799 | file_mips_arch = info->cpu; |
11800 | mips_opts.arch = info->cpu; | |
316f5878 | 11801 | mips_opts.isa = info->isa; |
252b5132 | 11802 | } |
252b5132 RH |
11803 | } |
11804 | ||
252b5132 | 11805 | |
316f5878 | 11806 | /* Likewise for tuning. */ |
252b5132 | 11807 | |
316f5878 | 11808 | static void |
17a2f251 | 11809 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11810 | { |
11811 | if (info != 0) | |
fef14a42 | 11812 | mips_tune = info->cpu; |
316f5878 | 11813 | } |
80cc45a5 | 11814 | |
34ba82a8 | 11815 | |
252b5132 | 11816 | void |
17a2f251 | 11817 | mips_after_parse_args (void) |
e9670677 | 11818 | { |
fef14a42 TS |
11819 | const struct mips_cpu_info *arch_info = 0; |
11820 | const struct mips_cpu_info *tune_info = 0; | |
11821 | ||
e9670677 | 11822 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11823 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11824 | { |
6caf9ef4 | 11825 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11826 | as_bad (_("-G not supported in this configuration.")); |
11827 | g_switch_value = 0; | |
11828 | } | |
11829 | ||
cac012d6 AO |
11830 | if (mips_abi == NO_ABI) |
11831 | mips_abi = MIPS_DEFAULT_ABI; | |
11832 | ||
22923709 RS |
11833 | /* The following code determines the architecture and register size. |
11834 | Similar code was added to GCC 3.3 (see override_options() in | |
11835 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11836 | as much as possible. */ | |
e9670677 | 11837 | |
316f5878 | 11838 | if (mips_arch_string != 0) |
fef14a42 | 11839 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11840 | |
316f5878 | 11841 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11842 | { |
316f5878 | 11843 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11844 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11845 | the -march selection (if any). */ |
fef14a42 | 11846 | if (arch_info != 0) |
e9670677 | 11847 | { |
316f5878 RS |
11848 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11849 | There's no harm in specifying both as long as the ISA levels | |
11850 | are the same. */ | |
fef14a42 | 11851 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11852 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11853 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11854 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11855 | } |
316f5878 | 11856 | else |
fef14a42 | 11857 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11858 | } |
11859 | ||
fef14a42 TS |
11860 | if (arch_info == 0) |
11861 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11862 | |
fef14a42 | 11863 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 11864 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
11865 | arch_info->name); |
11866 | ||
11867 | mips_set_architecture (arch_info); | |
11868 | ||
11869 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11870 | if (mips_tune_string != 0) | |
11871 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11872 | |
fef14a42 TS |
11873 | if (tune_info == 0) |
11874 | mips_set_tune (arch_info); | |
11875 | else | |
11876 | mips_set_tune (tune_info); | |
e9670677 | 11877 | |
316f5878 | 11878 | if (file_mips_gp32 >= 0) |
e9670677 | 11879 | { |
316f5878 RS |
11880 | /* The user specified the size of the integer registers. Make sure |
11881 | it agrees with the ABI and ISA. */ | |
11882 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11883 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11884 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11885 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11886 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11887 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11888 | } |
11889 | else | |
11890 | { | |
316f5878 RS |
11891 | /* Infer the integer register size from the ABI and processor. |
11892 | Restrict ourselves to 32-bit registers if that's all the | |
11893 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11894 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11895 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11896 | } |
11897 | ||
ad3fea08 TS |
11898 | switch (file_mips_fp32) |
11899 | { | |
11900 | default: | |
11901 | case -1: | |
11902 | /* No user specified float register size. | |
11903 | ??? GAS treats single-float processors as though they had 64-bit | |
11904 | float registers (although it complains when double-precision | |
11905 | instructions are used). As things stand, saying they have 32-bit | |
11906 | registers would lead to spurious "register must be even" messages. | |
11907 | So here we assume float registers are never smaller than the | |
11908 | integer ones. */ | |
11909 | if (file_mips_gp32 == 0) | |
11910 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11911 | file_mips_fp32 = 0; | |
11912 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11913 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11914 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11915 | file_mips_fp32 = 0; | |
11916 | else | |
11917 | /* 32-bit float registers. */ | |
11918 | file_mips_fp32 = 1; | |
11919 | break; | |
11920 | ||
11921 | /* The user specified the size of the float registers. Check if it | |
11922 | agrees with the ABI and ISA. */ | |
11923 | case 0: | |
11924 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11925 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11926 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11927 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11928 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11929 | break; | |
11930 | case 1: | |
11931 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11932 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11933 | break; | |
11934 | } | |
e9670677 | 11935 | |
316f5878 | 11936 | /* End of GCC-shared inference code. */ |
e9670677 | 11937 | |
17a2f251 TS |
11938 | /* This flag is set when we have a 64-bit capable CPU but use only |
11939 | 32-bit wide registers. Note that EABI does not use it. */ | |
11940 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11941 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11942 | || mips_abi == O32_ABI)) | |
316f5878 | 11943 | mips_32bitmode = 1; |
e9670677 MR |
11944 | |
11945 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11946 | as_bad (_("trap exception not supported at ISA 1")); | |
11947 | ||
e9670677 MR |
11948 | /* If the selected architecture includes support for ASEs, enable |
11949 | generation of code for them. */ | |
a4672219 | 11950 | if (mips_opts.mips16 == -1) |
fef14a42 | 11951 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11952 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11953 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11954 | && file_mips_fp32 == 0) ? 1 : 0; |
11955 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11956 | as_bad (_("-mfp32 used with -mips3d")); | |
11957 | ||
ffdefa66 | 11958 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11959 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11960 | && file_mips_fp32 == 0) ? 1 : 0; |
11961 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11962 | as_bad (_("-mfp32 used with -mdmx")); | |
11963 | ||
11964 | if (mips_opts.ase_smartmips == -1) | |
11965 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11966 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
11967 | as_warn (_("%s ISA does not support SmartMIPS"), |
11968 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 11969 | |
74cd071d | 11970 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11971 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11972 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
11973 | as_warn (_("%s ISA does not support DSP ASE"), |
11974 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 11975 | |
8b082fb1 TS |
11976 | if (mips_opts.ase_dspr2 == -1) |
11977 | { | |
11978 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11979 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11980 | } | |
11981 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
11982 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
11983 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 11984 | |
ef2e4d86 | 11985 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11986 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11987 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
11988 | as_warn (_("%s ISA does not support MT ASE"), |
11989 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11990 | |
e9670677 | 11991 | file_mips_isa = mips_opts.isa; |
a4672219 | 11992 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11993 | file_ase_mips3d = mips_opts.ase_mips3d; |
11994 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11995 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11996 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11997 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11998 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11999 | mips_opts.gp32 = file_mips_gp32; |
12000 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12001 | mips_opts.soft_float = file_mips_soft_float; |
12002 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12003 | |
ecb4347a DJ |
12004 | if (mips_flag_mdebug < 0) |
12005 | { | |
12006 | #ifdef OBJ_MAYBE_ECOFF | |
12007 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12008 | mips_flag_mdebug = 1; | |
12009 | else | |
12010 | #endif /* OBJ_MAYBE_ECOFF */ | |
12011 | mips_flag_mdebug = 0; | |
12012 | } | |
e9670677 MR |
12013 | } |
12014 | \f | |
12015 | void | |
17a2f251 | 12016 | mips_init_after_args (void) |
252b5132 RH |
12017 | { |
12018 | /* initialize opcodes */ | |
12019 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12020 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12021 | } |
12022 | ||
12023 | long | |
17a2f251 | 12024 | md_pcrel_from (fixS *fixP) |
252b5132 | 12025 | { |
a7ebbfdf TS |
12026 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12027 | switch (fixP->fx_r_type) | |
12028 | { | |
12029 | case BFD_RELOC_16_PCREL_S2: | |
12030 | case BFD_RELOC_MIPS_JMP: | |
12031 | /* Return the address of the delay slot. */ | |
12032 | return addr + 4; | |
12033 | default: | |
58ea3d6a | 12034 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12035 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12036 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12037 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12038 | return addr; |
12039 | } | |
252b5132 RH |
12040 | } |
12041 | ||
252b5132 RH |
12042 | /* This is called before the symbol table is processed. In order to |
12043 | work with gcc when using mips-tfile, we must keep all local labels. | |
12044 | However, in other cases, we want to discard them. If we were | |
12045 | called with -g, but we didn't see any debugging information, it may | |
12046 | mean that gcc is smuggling debugging information through to | |
12047 | mips-tfile, in which case we must generate all local labels. */ | |
12048 | ||
12049 | void | |
17a2f251 | 12050 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12051 | { |
12052 | #ifndef NO_ECOFF_DEBUGGING | |
12053 | if (ECOFF_DEBUGGING | |
12054 | && mips_debug != 0 | |
12055 | && ! ecoff_debugging_seen) | |
12056 | flag_keep_locals = 1; | |
12057 | #endif | |
12058 | } | |
12059 | ||
3b91255e | 12060 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12061 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12062 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12063 | relocation operators. | |
12064 | ||
12065 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12066 | expression if: | |
12067 | ||
12068 | (a) it refers to the same symbol; and | |
12069 | (b) the offset applied in the %lo() expression is no lower than | |
12070 | the offset applied in the %got() or %hi(). | |
12071 | ||
12072 | (b) allows us to cope with code like: | |
12073 | ||
12074 | lui $4,%hi(foo) | |
12075 | lh $4,%lo(foo+2)($4) | |
12076 | ||
12077 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12078 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12079 | the high 16 bits. | |
12080 | ||
12081 | When several %lo()s match a particular %got() or %hi(), we use the | |
12082 | following rules to distinguish them: | |
12083 | ||
12084 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12085 | higher offsets. | |
12086 | ||
12087 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12088 | that already have a matching %got() or %hi(). | |
12089 | ||
12090 | (3) later %lo()s are better than earlier %lo()s. | |
12091 | ||
12092 | These rules are applied in order. | |
12093 | ||
12094 | (1) means, among other things, that %lo()s with identical offsets are | |
12095 | chosen if they exist. | |
12096 | ||
12097 | (2) means that we won't associate several high-part relocations with | |
12098 | the same low-part relocation unless there's no alternative. Having | |
12099 | several high parts for the same low part is a GNU extension; this rule | |
12100 | allows careful users to avoid it. | |
12101 | ||
12102 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12103 | with the last high-part relocation being at the front of the list. | |
12104 | It therefore makes sense to choose the last matching low-part | |
12105 | relocation, all other things being equal. It's also easier | |
12106 | to code that way. */ | |
252b5132 RH |
12107 | |
12108 | void | |
17a2f251 | 12109 | mips_frob_file (void) |
252b5132 RH |
12110 | { |
12111 | struct mips_hi_fixup *l; | |
35903be0 | 12112 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12113 | |
12114 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12115 | { | |
12116 | segment_info_type *seginfo; | |
3b91255e RS |
12117 | bfd_boolean matched_lo_p; |
12118 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12119 | |
9c2799c2 | 12120 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12121 | |
5919d012 RS |
12122 | /* If a GOT16 relocation turns out to be against a global symbol, |
12123 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12124 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12125 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12126 | continue; | |
12127 | ||
12128 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12129 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12130 | continue; |
12131 | ||
252b5132 | 12132 | seginfo = seg_info (l->seg); |
252b5132 | 12133 | |
3b91255e RS |
12134 | /* Set HI_POS to the position of this relocation in the chain. |
12135 | Set LO_POS to the position of the chosen low-part relocation. | |
12136 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12137 | relocation that matches an immediately-preceding high-part | |
12138 | relocation. */ | |
12139 | hi_pos = NULL; | |
12140 | lo_pos = NULL; | |
12141 | matched_lo_p = FALSE; | |
738e5348 | 12142 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12143 | |
3b91255e RS |
12144 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12145 | { | |
12146 | if (*pos == l->fixp) | |
12147 | hi_pos = pos; | |
12148 | ||
35903be0 | 12149 | if ((*pos)->fx_r_type == looking_for_rtype |
3b91255e RS |
12150 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
12151 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
12152 | && (lo_pos == NULL | |
12153 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12154 | || (!matched_lo_p | |
12155 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12156 | lo_pos = pos; | |
12157 | ||
12158 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12159 | && fixup_has_matching_lo_p (*pos)); | |
12160 | } | |
12161 | ||
12162 | /* If we found a match, remove the high-part relocation from its | |
12163 | current position and insert it before the low-part relocation. | |
12164 | Make the offsets match so that fixup_has_matching_lo_p() | |
12165 | will return true. | |
12166 | ||
12167 | We don't warn about unmatched high-part relocations since some | |
12168 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12169 | instructions. */ | |
12170 | if (lo_pos != NULL) | |
12171 | { | |
12172 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12173 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12174 | { |
3b91255e RS |
12175 | *hi_pos = l->fixp->fx_next; |
12176 | l->fixp->fx_next = *lo_pos; | |
12177 | *lo_pos = l->fixp; | |
252b5132 | 12178 | } |
252b5132 RH |
12179 | } |
12180 | } | |
12181 | } | |
12182 | ||
3e722fb5 | 12183 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12184 | We have to prevent gas from dropping them. */ |
252b5132 | 12185 | |
252b5132 | 12186 | int |
17a2f251 | 12187 | mips_force_relocation (fixS *fixp) |
252b5132 | 12188 | { |
ae6063d4 | 12189 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12190 | return 1; |
12191 | ||
f6688943 TS |
12192 | if (HAVE_NEWABI |
12193 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12194 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12195 | || hi16_reloc_p (fixp->fx_r_type) |
12196 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12197 | return 1; |
12198 | ||
3e722fb5 | 12199 | return 0; |
252b5132 RH |
12200 | } |
12201 | ||
12202 | /* Apply a fixup to the object file. */ | |
12203 | ||
94f592af | 12204 | void |
55cf6793 | 12205 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12206 | { |
874e8986 | 12207 | bfd_byte *buf; |
98aa84af | 12208 | long insn; |
a7ebbfdf | 12209 | reloc_howto_type *howto; |
252b5132 | 12210 | |
a7ebbfdf TS |
12211 | /* We ignore generic BFD relocations we don't know about. */ |
12212 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12213 | if (! howto) | |
12214 | return; | |
65551fa4 | 12215 | |
9c2799c2 | 12216 | gas_assert (fixP->fx_size == 4 |
252b5132 RH |
12217 | || fixP->fx_r_type == BFD_RELOC_16 |
12218 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
12219 | || fixP->fx_r_type == BFD_RELOC_CTOR |
12220 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 12221 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
12222 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
12223 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12224 | |
a7ebbfdf | 12225 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12226 | |
9c2799c2 | 12227 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12228 | |
12229 | /* Don't treat parts of a composite relocation as done. There are two | |
12230 | reasons for this: | |
12231 | ||
12232 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12233 | should nevertheless be emitted if the first part is. | |
12234 | ||
12235 | (2) In normal usage, composite relocations are never assembly-time | |
12236 | constants. The easiest way of dealing with the pathological | |
12237 | exceptions is to generate a relocation against STN_UNDEF and | |
12238 | leave everything up to the linker. */ | |
3994f87e | 12239 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12240 | fixP->fx_done = 1; |
12241 | ||
12242 | switch (fixP->fx_r_type) | |
12243 | { | |
3f98094e DJ |
12244 | case BFD_RELOC_MIPS_TLS_GD: |
12245 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12246 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12247 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12248 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12249 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12250 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12251 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12252 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12253 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12254 | /* fall through */ | |
12255 | ||
252b5132 | 12256 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12257 | case BFD_RELOC_MIPS_SHIFT5: |
12258 | case BFD_RELOC_MIPS_SHIFT6: | |
12259 | case BFD_RELOC_MIPS_GOT_DISP: | |
12260 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12261 | case BFD_RELOC_MIPS_GOT_OFST: | |
12262 | case BFD_RELOC_MIPS_SUB: | |
12263 | case BFD_RELOC_MIPS_INSERT_A: | |
12264 | case BFD_RELOC_MIPS_INSERT_B: | |
12265 | case BFD_RELOC_MIPS_DELETE: | |
12266 | case BFD_RELOC_MIPS_HIGHEST: | |
12267 | case BFD_RELOC_MIPS_HIGHER: | |
12268 | case BFD_RELOC_MIPS_SCN_DISP: | |
12269 | case BFD_RELOC_MIPS_REL16: | |
12270 | case BFD_RELOC_MIPS_RELGOT: | |
12271 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12272 | case BFD_RELOC_HI16: |
12273 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12274 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12275 | case BFD_RELOC_MIPS_LITERAL: |
12276 | case BFD_RELOC_MIPS_CALL16: | |
12277 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12278 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12279 | case BFD_RELOC_MIPS_GOT_HI16: |
12280 | case BFD_RELOC_MIPS_GOT_LO16: | |
12281 | case BFD_RELOC_MIPS_CALL_HI16: | |
12282 | case BFD_RELOC_MIPS_CALL_LO16: | |
12283 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12284 | case BFD_RELOC_MIPS16_GOT16: |
12285 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12286 | case BFD_RELOC_MIPS16_HI16: |
12287 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12288 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12289 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12290 | break; |
12291 | ||
252b5132 RH |
12292 | case BFD_RELOC_64: |
12293 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12294 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12295 | if (fixP->fx_done) |
252b5132 RH |
12296 | { |
12297 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12298 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12299 | else |
12300 | { | |
a7ebbfdf | 12301 | valueT hiv; |
252b5132 | 12302 | |
a7ebbfdf | 12303 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12304 | hiv = 0xffffffff; |
12305 | else | |
12306 | hiv = 0; | |
b215186b | 12307 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12308 | *valP, 4); |
b215186b | 12309 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12310 | hiv, 4); |
252b5132 RH |
12311 | } |
12312 | } | |
12313 | break; | |
12314 | ||
056350c6 | 12315 | case BFD_RELOC_RVA: |
252b5132 | 12316 | case BFD_RELOC_32: |
252b5132 RH |
12317 | case BFD_RELOC_16: |
12318 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12319 | value now. This can happen if we have a .word which is not |
12320 | resolved when it appears but is later defined. */ | |
252b5132 | 12321 | if (fixP->fx_done) |
54f4ddb3 | 12322 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12323 | break; |
12324 | ||
12325 | case BFD_RELOC_LO16: | |
d6f16593 | 12326 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12327 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12328 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12329 | /* When handling an embedded PIC switch statement, we can wind |
12330 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12331 | if (fixP->fx_done) | |
12332 | { | |
a7ebbfdf | 12333 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12334 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12335 | _("relocation overflow")); | |
252b5132 RH |
12336 | if (target_big_endian) |
12337 | buf += 2; | |
2132e3a3 | 12338 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12339 | } |
12340 | break; | |
12341 | ||
12342 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12343 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12344 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12345 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12346 | |
54f4ddb3 TS |
12347 | /* We need to save the bits in the instruction since fixup_segment() |
12348 | might be deleting the relocation entry (i.e., a branch within | |
12349 | the current segment). */ | |
a7ebbfdf | 12350 | if (! fixP->fx_done) |
bb2d6cd7 | 12351 | break; |
252b5132 | 12352 | |
54f4ddb3 | 12353 | /* Update old instruction data. */ |
252b5132 RH |
12354 | if (target_big_endian) |
12355 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12356 | else | |
12357 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12358 | ||
a7ebbfdf TS |
12359 | if (*valP + 0x20000 <= 0x3ffff) |
12360 | { | |
12361 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12362 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12363 | } |
12364 | else if (mips_pic == NO_PIC | |
12365 | && fixP->fx_done | |
12366 | && fixP->fx_frag->fr_address >= text_section->vma | |
12367 | && (fixP->fx_frag->fr_address | |
587aac4e | 12368 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12369 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12370 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12371 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12372 | { |
12373 | /* The branch offset is too large. If this is an | |
12374 | unconditional branch, and we are not generating PIC code, | |
12375 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12376 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12377 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12378 | else |
a7ebbfdf TS |
12379 | insn = 0x08000000; /* j */ |
12380 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12381 | fixP->fx_done = 0; | |
12382 | fixP->fx_addsy = section_symbol (text_section); | |
12383 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12384 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12385 | } |
12386 | else | |
12387 | { | |
12388 | /* If we got here, we have branch-relaxation disabled, | |
12389 | and there's nothing we can do to fix this instruction | |
12390 | without turning it into a longer sequence. */ | |
12391 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12392 | _("Branch out of range")); | |
252b5132 | 12393 | } |
252b5132 RH |
12394 | break; |
12395 | ||
12396 | case BFD_RELOC_VTABLE_INHERIT: | |
12397 | fixP->fx_done = 0; | |
12398 | if (fixP->fx_addsy | |
12399 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12400 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12401 | S_SET_WEAK (fixP->fx_addsy); | |
12402 | break; | |
12403 | ||
12404 | case BFD_RELOC_VTABLE_ENTRY: | |
12405 | fixP->fx_done = 0; | |
12406 | break; | |
12407 | ||
12408 | default: | |
12409 | internalError (); | |
12410 | } | |
a7ebbfdf TS |
12411 | |
12412 | /* Remember value for tc_gen_reloc. */ | |
12413 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12414 | } |
12415 | ||
252b5132 | 12416 | static symbolS * |
17a2f251 | 12417 | get_symbol (void) |
252b5132 RH |
12418 | { |
12419 | int c; | |
12420 | char *name; | |
12421 | symbolS *p; | |
12422 | ||
12423 | name = input_line_pointer; | |
12424 | c = get_symbol_end (); | |
12425 | p = (symbolS *) symbol_find_or_make (name); | |
12426 | *input_line_pointer = c; | |
12427 | return p; | |
12428 | } | |
12429 | ||
742a56fe RS |
12430 | /* Align the current frag to a given power of two. If a particular |
12431 | fill byte should be used, FILL points to an integer that contains | |
12432 | that byte, otherwise FILL is null. | |
12433 | ||
12434 | The MIPS assembler also automatically adjusts any preceding | |
12435 | label. */ | |
252b5132 RH |
12436 | |
12437 | static void | |
742a56fe | 12438 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12439 | { |
7d10b47d | 12440 | mips_emit_delays (); |
742a56fe RS |
12441 | mips_record_mips16_mode (); |
12442 | if (fill == NULL && subseg_text_p (now_seg)) | |
12443 | frag_align_code (to, 0); | |
12444 | else | |
12445 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12446 | record_alignment (now_seg, to); |
12447 | if (label != NULL) | |
12448 | { | |
9c2799c2 | 12449 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12450 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12451 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12452 | } | |
12453 | } | |
12454 | ||
12455 | /* Align to a given power of two. .align 0 turns off the automatic | |
12456 | alignment used by the data creating pseudo-ops. */ | |
12457 | ||
12458 | static void | |
17a2f251 | 12459 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12460 | { |
742a56fe | 12461 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12462 | long max_alignment = 28; |
252b5132 | 12463 | |
54f4ddb3 | 12464 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12465 | to the aligned address. |
54f4ddb3 | 12466 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12467 | a .align pseudo instruction. |
54f4ddb3 | 12468 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12469 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12470 | We don't. */ |
252b5132 RH |
12471 | |
12472 | temp = get_absolute_expression (); | |
12473 | if (temp > max_alignment) | |
12474 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12475 | else if (temp < 0) | |
12476 | { | |
12477 | as_warn (_("Alignment negative: 0 assumed.")); | |
12478 | temp = 0; | |
12479 | } | |
12480 | if (*input_line_pointer == ',') | |
12481 | { | |
f9419b05 | 12482 | ++input_line_pointer; |
742a56fe RS |
12483 | fill_value = get_absolute_expression (); |
12484 | fill_ptr = &fill_value; | |
252b5132 RH |
12485 | } |
12486 | else | |
742a56fe | 12487 | fill_ptr = 0; |
252b5132 RH |
12488 | if (temp) |
12489 | { | |
a8dbcb85 TS |
12490 | segment_info_type *si = seg_info (now_seg); |
12491 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12492 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12493 | auto_align = 1; |
742a56fe | 12494 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12495 | } |
12496 | else | |
12497 | { | |
12498 | auto_align = 0; | |
12499 | } | |
12500 | ||
12501 | demand_empty_rest_of_line (); | |
12502 | } | |
12503 | ||
252b5132 | 12504 | static void |
17a2f251 | 12505 | s_change_sec (int sec) |
252b5132 RH |
12506 | { |
12507 | segT seg; | |
12508 | ||
252b5132 RH |
12509 | #ifdef OBJ_ELF |
12510 | /* The ELF backend needs to know that we are changing sections, so | |
12511 | that .previous works correctly. We could do something like check | |
b6ff326e | 12512 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12513 | as it would not be appropriate to use it in the section changing |
12514 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12515 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12516 | if (IS_ELF) |
12517 | obj_elf_section_change_hook (); | |
252b5132 RH |
12518 | #endif |
12519 | ||
7d10b47d | 12520 | mips_emit_delays (); |
6a32d874 | 12521 | |
252b5132 RH |
12522 | switch (sec) |
12523 | { | |
12524 | case 't': | |
12525 | s_text (0); | |
12526 | break; | |
12527 | case 'd': | |
12528 | s_data (0); | |
12529 | break; | |
12530 | case 'b': | |
12531 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12532 | demand_empty_rest_of_line (); | |
12533 | break; | |
12534 | ||
12535 | case 'r': | |
4d0d148d TS |
12536 | seg = subseg_new (RDATA_SECTION_NAME, |
12537 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12538 | if (IS_ELF) |
252b5132 | 12539 | { |
4d0d148d TS |
12540 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12541 | | SEC_READONLY | SEC_RELOC | |
12542 | | SEC_DATA)); | |
c41e87e3 | 12543 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12544 | record_alignment (seg, 4); |
252b5132 | 12545 | } |
4d0d148d | 12546 | demand_empty_rest_of_line (); |
252b5132 RH |
12547 | break; |
12548 | ||
12549 | case 's': | |
4d0d148d | 12550 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12551 | if (IS_ELF) |
252b5132 | 12552 | { |
4d0d148d TS |
12553 | bfd_set_section_flags (stdoutput, seg, |
12554 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12555 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12556 | record_alignment (seg, 4); |
252b5132 | 12557 | } |
4d0d148d TS |
12558 | demand_empty_rest_of_line (); |
12559 | break; | |
252b5132 RH |
12560 | } |
12561 | ||
12562 | auto_align = 1; | |
12563 | } | |
b34976b6 | 12564 | |
cca86cc8 | 12565 | void |
17a2f251 | 12566 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12567 | { |
7ed4a06a | 12568 | #ifdef OBJ_ELF |
cca86cc8 SC |
12569 | char *section_name; |
12570 | char c; | |
684022ea | 12571 | char next_c = 0; |
cca86cc8 SC |
12572 | int section_type; |
12573 | int section_flag; | |
12574 | int section_entry_size; | |
12575 | int section_alignment; | |
b34976b6 | 12576 | |
f43abd2b | 12577 | if (!IS_ELF) |
7ed4a06a TS |
12578 | return; |
12579 | ||
cca86cc8 SC |
12580 | section_name = input_line_pointer; |
12581 | c = get_symbol_end (); | |
a816d1ed AO |
12582 | if (c) |
12583 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12584 | |
4cf0dd0d TS |
12585 | /* Do we have .section Name<,"flags">? */ |
12586 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12587 | { |
4cf0dd0d TS |
12588 | /* just after name is now '\0'. */ |
12589 | *input_line_pointer = c; | |
cca86cc8 SC |
12590 | input_line_pointer = section_name; |
12591 | obj_elf_section (ignore); | |
12592 | return; | |
12593 | } | |
12594 | input_line_pointer++; | |
12595 | ||
12596 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12597 | if (c == ',') | |
12598 | section_type = get_absolute_expression (); | |
12599 | else | |
12600 | section_type = 0; | |
12601 | if (*input_line_pointer++ == ',') | |
12602 | section_flag = get_absolute_expression (); | |
12603 | else | |
12604 | section_flag = 0; | |
12605 | if (*input_line_pointer++ == ',') | |
12606 | section_entry_size = get_absolute_expression (); | |
12607 | else | |
12608 | section_entry_size = 0; | |
12609 | if (*input_line_pointer++ == ',') | |
12610 | section_alignment = get_absolute_expression (); | |
12611 | else | |
12612 | section_alignment = 0; | |
12613 | ||
a816d1ed AO |
12614 | section_name = xstrdup (section_name); |
12615 | ||
8ab8a5c8 RS |
12616 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12617 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12618 | traditionally had to fall back on the more common @progbits instead. | |
12619 | ||
12620 | There's nothing really harmful in this, since bfd will correct | |
12621 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12622 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12623 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12624 | ||
12625 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12626 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12627 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12628 | generic type-checking code. */ | |
12629 | if (section_type == SHT_MIPS_DWARF) | |
12630 | section_type = SHT_PROGBITS; | |
12631 | ||
cca86cc8 SC |
12632 | obj_elf_change_section (section_name, section_type, section_flag, |
12633 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12634 | |
12635 | if (now_seg->name != section_name) | |
12636 | free (section_name); | |
7ed4a06a | 12637 | #endif /* OBJ_ELF */ |
cca86cc8 | 12638 | } |
252b5132 RH |
12639 | |
12640 | void | |
17a2f251 | 12641 | mips_enable_auto_align (void) |
252b5132 RH |
12642 | { |
12643 | auto_align = 1; | |
12644 | } | |
12645 | ||
12646 | static void | |
17a2f251 | 12647 | s_cons (int log_size) |
252b5132 | 12648 | { |
a8dbcb85 TS |
12649 | segment_info_type *si = seg_info (now_seg); |
12650 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12651 | symbolS *label; |
12652 | ||
a8dbcb85 | 12653 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12654 | mips_emit_delays (); |
252b5132 RH |
12655 | if (log_size > 0 && auto_align) |
12656 | mips_align (log_size, 0, label); | |
12657 | mips_clear_insn_labels (); | |
12658 | cons (1 << log_size); | |
12659 | } | |
12660 | ||
12661 | static void | |
17a2f251 | 12662 | s_float_cons (int type) |
252b5132 | 12663 | { |
a8dbcb85 TS |
12664 | segment_info_type *si = seg_info (now_seg); |
12665 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12666 | symbolS *label; |
12667 | ||
a8dbcb85 | 12668 | label = l != NULL ? l->label : NULL; |
252b5132 | 12669 | |
7d10b47d | 12670 | mips_emit_delays (); |
252b5132 RH |
12671 | |
12672 | if (auto_align) | |
49309057 ILT |
12673 | { |
12674 | if (type == 'd') | |
12675 | mips_align (3, 0, label); | |
12676 | else | |
12677 | mips_align (2, 0, label); | |
12678 | } | |
252b5132 RH |
12679 | |
12680 | mips_clear_insn_labels (); | |
12681 | ||
12682 | float_cons (type); | |
12683 | } | |
12684 | ||
12685 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12686 | permitted to say | |
12687 | .globl foo .text | |
12688 | where foo is an undefined symbol, to mean that foo should be | |
12689 | considered to be the address of a function. */ | |
12690 | ||
12691 | static void | |
17a2f251 | 12692 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12693 | { |
12694 | char *name; | |
12695 | int c; | |
12696 | symbolS *symbolP; | |
12697 | flagword flag; | |
12698 | ||
8a06b769 | 12699 | do |
252b5132 | 12700 | { |
8a06b769 | 12701 | name = input_line_pointer; |
252b5132 | 12702 | c = get_symbol_end (); |
8a06b769 TS |
12703 | symbolP = symbol_find_or_make (name); |
12704 | S_SET_EXTERNAL (symbolP); | |
12705 | ||
252b5132 | 12706 | *input_line_pointer = c; |
8a06b769 | 12707 | SKIP_WHITESPACE (); |
252b5132 | 12708 | |
8a06b769 TS |
12709 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12710 | being a function is apparently labelled as being an object. */ | |
12711 | flag = BSF_OBJECT; | |
252b5132 | 12712 | |
8a06b769 TS |
12713 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12714 | && (*input_line_pointer != ',')) | |
12715 | { | |
12716 | char *secname; | |
12717 | asection *sec; | |
12718 | ||
12719 | secname = input_line_pointer; | |
12720 | c = get_symbol_end (); | |
12721 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12722 | if (sec == NULL) | |
12723 | as_bad (_("%s: no such section"), secname); | |
12724 | *input_line_pointer = c; | |
12725 | ||
12726 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12727 | flag = BSF_FUNCTION; | |
12728 | } | |
12729 | ||
12730 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12731 | ||
12732 | c = *input_line_pointer; | |
12733 | if (c == ',') | |
12734 | { | |
12735 | input_line_pointer++; | |
12736 | SKIP_WHITESPACE (); | |
12737 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12738 | c = '\n'; | |
12739 | } | |
12740 | } | |
12741 | while (c == ','); | |
252b5132 | 12742 | |
252b5132 RH |
12743 | demand_empty_rest_of_line (); |
12744 | } | |
12745 | ||
12746 | static void | |
17a2f251 | 12747 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12748 | { |
12749 | char *opt; | |
12750 | char c; | |
12751 | ||
12752 | opt = input_line_pointer; | |
12753 | c = get_symbol_end (); | |
12754 | ||
12755 | if (*opt == 'O') | |
12756 | { | |
12757 | /* FIXME: What does this mean? */ | |
12758 | } | |
12759 | else if (strncmp (opt, "pic", 3) == 0) | |
12760 | { | |
12761 | int i; | |
12762 | ||
12763 | i = atoi (opt + 3); | |
12764 | if (i == 0) | |
12765 | mips_pic = NO_PIC; | |
12766 | else if (i == 2) | |
143d77c5 | 12767 | { |
252b5132 | 12768 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12769 | mips_abicalls = TRUE; |
12770 | } | |
252b5132 RH |
12771 | else |
12772 | as_bad (_(".option pic%d not supported"), i); | |
12773 | ||
4d0d148d | 12774 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12775 | { |
12776 | if (g_switch_seen && g_switch_value != 0) | |
12777 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12778 | g_switch_value = 0; | |
12779 | bfd_set_gp_size (stdoutput, 0); | |
12780 | } | |
12781 | } | |
12782 | else | |
12783 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12784 | ||
12785 | *input_line_pointer = c; | |
12786 | demand_empty_rest_of_line (); | |
12787 | } | |
12788 | ||
12789 | /* This structure is used to hold a stack of .set values. */ | |
12790 | ||
e972090a NC |
12791 | struct mips_option_stack |
12792 | { | |
252b5132 RH |
12793 | struct mips_option_stack *next; |
12794 | struct mips_set_options options; | |
12795 | }; | |
12796 | ||
12797 | static struct mips_option_stack *mips_opts_stack; | |
12798 | ||
12799 | /* Handle the .set pseudo-op. */ | |
12800 | ||
12801 | static void | |
17a2f251 | 12802 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12803 | { |
12804 | char *name = input_line_pointer, ch; | |
12805 | ||
12806 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12807 | ++input_line_pointer; |
252b5132 RH |
12808 | ch = *input_line_pointer; |
12809 | *input_line_pointer = '\0'; | |
12810 | ||
12811 | if (strcmp (name, "reorder") == 0) | |
12812 | { | |
7d10b47d RS |
12813 | if (mips_opts.noreorder) |
12814 | end_noreorder (); | |
252b5132 RH |
12815 | } |
12816 | else if (strcmp (name, "noreorder") == 0) | |
12817 | { | |
7d10b47d RS |
12818 | if (!mips_opts.noreorder) |
12819 | start_noreorder (); | |
252b5132 | 12820 | } |
741fe287 MR |
12821 | else if (strncmp (name, "at=", 3) == 0) |
12822 | { | |
12823 | char *s = name + 3; | |
12824 | ||
12825 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12826 | as_bad (_("Unrecognized register name `%s'"), s); | |
12827 | } | |
252b5132 RH |
12828 | else if (strcmp (name, "at") == 0) |
12829 | { | |
741fe287 | 12830 | mips_opts.at = ATREG; |
252b5132 RH |
12831 | } |
12832 | else if (strcmp (name, "noat") == 0) | |
12833 | { | |
741fe287 | 12834 | mips_opts.at = ZERO; |
252b5132 RH |
12835 | } |
12836 | else if (strcmp (name, "macro") == 0) | |
12837 | { | |
12838 | mips_opts.warn_about_macros = 0; | |
12839 | } | |
12840 | else if (strcmp (name, "nomacro") == 0) | |
12841 | { | |
12842 | if (mips_opts.noreorder == 0) | |
12843 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12844 | mips_opts.warn_about_macros = 1; | |
12845 | } | |
12846 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12847 | { | |
12848 | mips_opts.nomove = 0; | |
12849 | } | |
12850 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12851 | { | |
12852 | mips_opts.nomove = 1; | |
12853 | } | |
12854 | else if (strcmp (name, "bopt") == 0) | |
12855 | { | |
12856 | mips_opts.nobopt = 0; | |
12857 | } | |
12858 | else if (strcmp (name, "nobopt") == 0) | |
12859 | { | |
12860 | mips_opts.nobopt = 1; | |
12861 | } | |
ad3fea08 TS |
12862 | else if (strcmp (name, "gp=default") == 0) |
12863 | mips_opts.gp32 = file_mips_gp32; | |
12864 | else if (strcmp (name, "gp=32") == 0) | |
12865 | mips_opts.gp32 = 1; | |
12866 | else if (strcmp (name, "gp=64") == 0) | |
12867 | { | |
12868 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 12869 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
12870 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12871 | mips_opts.gp32 = 0; | |
12872 | } | |
12873 | else if (strcmp (name, "fp=default") == 0) | |
12874 | mips_opts.fp32 = file_mips_fp32; | |
12875 | else if (strcmp (name, "fp=32") == 0) | |
12876 | mips_opts.fp32 = 1; | |
12877 | else if (strcmp (name, "fp=64") == 0) | |
12878 | { | |
12879 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 12880 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
12881 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12882 | mips_opts.fp32 = 0; | |
12883 | } | |
037b32b9 AN |
12884 | else if (strcmp (name, "softfloat") == 0) |
12885 | mips_opts.soft_float = 1; | |
12886 | else if (strcmp (name, "hardfloat") == 0) | |
12887 | mips_opts.soft_float = 0; | |
12888 | else if (strcmp (name, "singlefloat") == 0) | |
12889 | mips_opts.single_float = 1; | |
12890 | else if (strcmp (name, "doublefloat") == 0) | |
12891 | mips_opts.single_float = 0; | |
252b5132 RH |
12892 | else if (strcmp (name, "mips16") == 0 |
12893 | || strcmp (name, "MIPS-16") == 0) | |
12894 | mips_opts.mips16 = 1; | |
12895 | else if (strcmp (name, "nomips16") == 0 | |
12896 | || strcmp (name, "noMIPS-16") == 0) | |
12897 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12898 | else if (strcmp (name, "smartmips") == 0) |
12899 | { | |
ad3fea08 | 12900 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 12901 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
12902 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12903 | mips_opts.ase_smartmips = 1; | |
12904 | } | |
12905 | else if (strcmp (name, "nosmartmips") == 0) | |
12906 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12907 | else if (strcmp (name, "mips3d") == 0) |
12908 | mips_opts.ase_mips3d = 1; | |
12909 | else if (strcmp (name, "nomips3d") == 0) | |
12910 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12911 | else if (strcmp (name, "mdmx") == 0) |
12912 | mips_opts.ase_mdmx = 1; | |
12913 | else if (strcmp (name, "nomdmx") == 0) | |
12914 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12915 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12916 | { |
12917 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 12918 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
12919 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12920 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12921 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12922 | } |
74cd071d | 12923 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12924 | { |
12925 | mips_opts.ase_dsp = 0; | |
12926 | mips_opts.ase_dspr2 = 0; | |
12927 | } | |
12928 | else if (strcmp (name, "dspr2") == 0) | |
12929 | { | |
12930 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 12931 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
12932 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12933 | mips_opts.ase_dspr2 = 1; | |
12934 | mips_opts.ase_dsp = 1; | |
12935 | } | |
12936 | else if (strcmp (name, "nodspr2") == 0) | |
12937 | { | |
12938 | mips_opts.ase_dspr2 = 0; | |
12939 | mips_opts.ase_dsp = 0; | |
12940 | } | |
ef2e4d86 | 12941 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12942 | { |
12943 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 12944 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
12945 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12946 | mips_opts.ase_mt = 1; | |
12947 | } | |
ef2e4d86 CF |
12948 | else if (strcmp (name, "nomt") == 0) |
12949 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12950 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12951 | { |
af7ee8bf | 12952 | int reset = 0; |
252b5132 | 12953 | |
1a2c1fad CD |
12954 | /* Permit the user to change the ISA and architecture on the fly. |
12955 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12956 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12957 | { |
12958 | reset = 1; | |
12959 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12960 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12961 | } |
12962 | else if (strncmp (name, "arch=", 5) == 0) | |
12963 | { | |
12964 | const struct mips_cpu_info *p; | |
12965 | ||
12966 | p = mips_parse_cpu("internal use", name + 5); | |
12967 | if (!p) | |
12968 | as_bad (_("unknown architecture %s"), name + 5); | |
12969 | else | |
12970 | { | |
12971 | mips_opts.arch = p->cpu; | |
12972 | mips_opts.isa = p->isa; | |
12973 | } | |
12974 | } | |
81a21e38 TS |
12975 | else if (strncmp (name, "mips", 4) == 0) |
12976 | { | |
12977 | const struct mips_cpu_info *p; | |
12978 | ||
12979 | p = mips_parse_cpu("internal use", name); | |
12980 | if (!p) | |
12981 | as_bad (_("unknown ISA level %s"), name + 4); | |
12982 | else | |
12983 | { | |
12984 | mips_opts.arch = p->cpu; | |
12985 | mips_opts.isa = p->isa; | |
12986 | } | |
12987 | } | |
af7ee8bf | 12988 | else |
81a21e38 | 12989 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12990 | |
12991 | switch (mips_opts.isa) | |
98d3f06f KH |
12992 | { |
12993 | case 0: | |
98d3f06f | 12994 | break; |
af7ee8bf CD |
12995 | case ISA_MIPS1: |
12996 | case ISA_MIPS2: | |
12997 | case ISA_MIPS32: | |
12998 | case ISA_MIPS32R2: | |
98d3f06f KH |
12999 | mips_opts.gp32 = 1; |
13000 | mips_opts.fp32 = 1; | |
13001 | break; | |
af7ee8bf CD |
13002 | case ISA_MIPS3: |
13003 | case ISA_MIPS4: | |
13004 | case ISA_MIPS5: | |
13005 | case ISA_MIPS64: | |
5f74bc13 | 13006 | case ISA_MIPS64R2: |
98d3f06f KH |
13007 | mips_opts.gp32 = 0; |
13008 | mips_opts.fp32 = 0; | |
13009 | break; | |
13010 | default: | |
13011 | as_bad (_("unknown ISA level %s"), name + 4); | |
13012 | break; | |
13013 | } | |
af7ee8bf | 13014 | if (reset) |
98d3f06f | 13015 | { |
af7ee8bf CD |
13016 | mips_opts.gp32 = file_mips_gp32; |
13017 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13018 | } |
252b5132 RH |
13019 | } |
13020 | else if (strcmp (name, "autoextend") == 0) | |
13021 | mips_opts.noautoextend = 0; | |
13022 | else if (strcmp (name, "noautoextend") == 0) | |
13023 | mips_opts.noautoextend = 1; | |
13024 | else if (strcmp (name, "push") == 0) | |
13025 | { | |
13026 | struct mips_option_stack *s; | |
13027 | ||
13028 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13029 | s->next = mips_opts_stack; | |
13030 | s->options = mips_opts; | |
13031 | mips_opts_stack = s; | |
13032 | } | |
13033 | else if (strcmp (name, "pop") == 0) | |
13034 | { | |
13035 | struct mips_option_stack *s; | |
13036 | ||
13037 | s = mips_opts_stack; | |
13038 | if (s == NULL) | |
13039 | as_bad (_(".set pop with no .set push")); | |
13040 | else | |
13041 | { | |
13042 | /* If we're changing the reorder mode we need to handle | |
13043 | delay slots correctly. */ | |
13044 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13045 | start_noreorder (); |
252b5132 | 13046 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13047 | end_noreorder (); |
252b5132 RH |
13048 | |
13049 | mips_opts = s->options; | |
13050 | mips_opts_stack = s->next; | |
13051 | free (s); | |
13052 | } | |
13053 | } | |
aed1a261 RS |
13054 | else if (strcmp (name, "sym32") == 0) |
13055 | mips_opts.sym32 = TRUE; | |
13056 | else if (strcmp (name, "nosym32") == 0) | |
13057 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13058 | else if (strchr (name, ',')) |
13059 | { | |
13060 | /* Generic ".set" directive; use the generic handler. */ | |
13061 | *input_line_pointer = ch; | |
13062 | input_line_pointer = name; | |
13063 | s_set (0); | |
13064 | return; | |
13065 | } | |
252b5132 RH |
13066 | else |
13067 | { | |
13068 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13069 | } | |
13070 | *input_line_pointer = ch; | |
13071 | demand_empty_rest_of_line (); | |
13072 | } | |
13073 | ||
13074 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13075 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13076 | ||
13077 | static void | |
17a2f251 | 13078 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13079 | { |
13080 | mips_pic = SVR4_PIC; | |
143d77c5 | 13081 | mips_abicalls = TRUE; |
4d0d148d TS |
13082 | |
13083 | if (g_switch_seen && g_switch_value != 0) | |
13084 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13085 | g_switch_value = 0; | |
13086 | ||
252b5132 RH |
13087 | bfd_set_gp_size (stdoutput, 0); |
13088 | demand_empty_rest_of_line (); | |
13089 | } | |
13090 | ||
13091 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13092 | PIC code. It sets the $gp register for the function based on the | |
13093 | function address, which is in the register named in the argument. | |
13094 | This uses a relocation against _gp_disp, which is handled specially | |
13095 | by the linker. The result is: | |
13096 | lui $gp,%hi(_gp_disp) | |
13097 | addiu $gp,$gp,%lo(_gp_disp) | |
13098 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13099 | The .cpload argument is normally $25 == $t9. |
13100 | ||
13101 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13102 | lui $gp,%hi(__gnu_local_gp) |
13103 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13104 | and the argument is ignored. This saves an instruction, but the |
13105 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13106 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13107 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13108 | |
13109 | static void | |
17a2f251 | 13110 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13111 | { |
13112 | expressionS ex; | |
aa6975fb ILT |
13113 | int reg; |
13114 | int in_shared; | |
252b5132 | 13115 | |
6478892d TS |
13116 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13117 | .cpload is ignored. */ | |
13118 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13119 | { |
13120 | s_ignore (0); | |
13121 | return; | |
13122 | } | |
13123 | ||
d3ecfc59 | 13124 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13125 | if (mips_opts.noreorder == 0) |
13126 | as_warn (_(".cpload not in noreorder section")); | |
13127 | ||
aa6975fb ILT |
13128 | reg = tc_get_register (0); |
13129 | ||
13130 | /* If we need to produce a 64-bit address, we are better off using | |
13131 | the default instruction sequence. */ | |
aed1a261 | 13132 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13133 | |
252b5132 | 13134 | ex.X_op = O_symbol; |
bbe506e8 TS |
13135 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13136 | "__gnu_local_gp"); | |
252b5132 RH |
13137 | ex.X_op_symbol = NULL; |
13138 | ex.X_add_number = 0; | |
13139 | ||
13140 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13141 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13142 | |
584892a6 | 13143 | macro_start (); |
67c0d1eb RS |
13144 | macro_build_lui (&ex, mips_gp_register); |
13145 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13146 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13147 | if (in_shared) |
13148 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13149 | mips_gp_register, reg); | |
584892a6 | 13150 | macro_end (); |
252b5132 RH |
13151 | |
13152 | demand_empty_rest_of_line (); | |
13153 | } | |
13154 | ||
6478892d TS |
13155 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13156 | .cpsetup $reg1, offset|$reg2, label | |
13157 | ||
13158 | If offset is given, this results in: | |
13159 | sd $gp, offset($sp) | |
956cd1d6 | 13160 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13161 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13162 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13163 | |
13164 | If $reg2 is given, this results in: | |
13165 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13166 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13167 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13168 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13169 | $reg1 is normally $25 == $t9. |
13170 | ||
13171 | The -mno-shared option replaces the last three instructions with | |
13172 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13173 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13174 | |
6478892d | 13175 | static void |
17a2f251 | 13176 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13177 | { |
13178 | expressionS ex_off; | |
13179 | expressionS ex_sym; | |
13180 | int reg1; | |
6478892d | 13181 | |
8586fc66 | 13182 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13183 | We also need NewABI support. */ |
13184 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13185 | { | |
13186 | s_ignore (0); | |
13187 | return; | |
13188 | } | |
13189 | ||
13190 | reg1 = tc_get_register (0); | |
13191 | SKIP_WHITESPACE (); | |
13192 | if (*input_line_pointer != ',') | |
13193 | { | |
13194 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13195 | return; | |
13196 | } | |
13197 | else | |
80245285 | 13198 | ++input_line_pointer; |
6478892d TS |
13199 | SKIP_WHITESPACE (); |
13200 | if (*input_line_pointer == '$') | |
80245285 TS |
13201 | { |
13202 | mips_cpreturn_register = tc_get_register (0); | |
13203 | mips_cpreturn_offset = -1; | |
13204 | } | |
6478892d | 13205 | else |
80245285 TS |
13206 | { |
13207 | mips_cpreturn_offset = get_absolute_expression (); | |
13208 | mips_cpreturn_register = -1; | |
13209 | } | |
6478892d TS |
13210 | SKIP_WHITESPACE (); |
13211 | if (*input_line_pointer != ',') | |
13212 | { | |
13213 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13214 | return; | |
13215 | } | |
13216 | else | |
f9419b05 | 13217 | ++input_line_pointer; |
6478892d | 13218 | SKIP_WHITESPACE (); |
f21f8242 | 13219 | expression (&ex_sym); |
6478892d | 13220 | |
584892a6 | 13221 | macro_start (); |
6478892d TS |
13222 | if (mips_cpreturn_register == -1) |
13223 | { | |
13224 | ex_off.X_op = O_constant; | |
13225 | ex_off.X_add_symbol = NULL; | |
13226 | ex_off.X_op_symbol = NULL; | |
13227 | ex_off.X_add_number = mips_cpreturn_offset; | |
13228 | ||
67c0d1eb | 13229 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13230 | BFD_RELOC_LO16, SP); |
6478892d TS |
13231 | } |
13232 | else | |
67c0d1eb | 13233 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13234 | mips_gp_register, 0); |
6478892d | 13235 | |
aed1a261 | 13236 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13237 | { |
13238 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13239 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13240 | BFD_RELOC_HI16_S); | |
13241 | ||
13242 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13243 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13244 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13245 | ||
13246 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13247 | mips_gp_register, reg1); | |
13248 | } | |
13249 | else | |
13250 | { | |
13251 | expressionS ex; | |
13252 | ||
13253 | ex.X_op = O_symbol; | |
4184909a | 13254 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13255 | ex.X_op_symbol = NULL; |
13256 | ex.X_add_number = 0; | |
6e1304d8 | 13257 | |
aa6975fb ILT |
13258 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13259 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13260 | ||
13261 | macro_build_lui (&ex, mips_gp_register); | |
13262 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13263 | mips_gp_register, BFD_RELOC_LO16); | |
13264 | } | |
f21f8242 | 13265 | |
584892a6 | 13266 | macro_end (); |
6478892d TS |
13267 | |
13268 | demand_empty_rest_of_line (); | |
13269 | } | |
13270 | ||
13271 | static void | |
17a2f251 | 13272 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13273 | { |
13274 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13275 | .cplocal is ignored. */ |
6478892d TS |
13276 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13277 | { | |
13278 | s_ignore (0); | |
13279 | return; | |
13280 | } | |
13281 | ||
13282 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13283 | demand_empty_rest_of_line (); |
6478892d TS |
13284 | } |
13285 | ||
252b5132 RH |
13286 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13287 | offset from $sp. The offset is remembered, and after making a PIC | |
13288 | call $gp is restored from that location. */ | |
13289 | ||
13290 | static void | |
17a2f251 | 13291 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13292 | { |
13293 | expressionS ex; | |
252b5132 | 13294 | |
6478892d | 13295 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13296 | .cprestore is ignored. */ |
6478892d | 13297 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13298 | { |
13299 | s_ignore (0); | |
13300 | return; | |
13301 | } | |
13302 | ||
13303 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13304 | mips_cprestore_valid = 1; |
252b5132 RH |
13305 | |
13306 | ex.X_op = O_constant; | |
13307 | ex.X_add_symbol = NULL; | |
13308 | ex.X_op_symbol = NULL; | |
13309 | ex.X_add_number = mips_cprestore_offset; | |
13310 | ||
584892a6 | 13311 | macro_start (); |
67c0d1eb RS |
13312 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13313 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13314 | macro_end (); |
252b5132 RH |
13315 | |
13316 | demand_empty_rest_of_line (); | |
13317 | } | |
13318 | ||
6478892d | 13319 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13320 | was given in the preceding .cpsetup, it results in: |
6478892d | 13321 | ld $gp, offset($sp) |
76b3015f | 13322 | |
6478892d | 13323 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13324 | daddu $gp, $reg2, $0 */ |
13325 | ||
6478892d | 13326 | static void |
17a2f251 | 13327 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13328 | { |
13329 | expressionS ex; | |
6478892d TS |
13330 | |
13331 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13332 | We also need NewABI support. */ | |
13333 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13334 | { | |
13335 | s_ignore (0); | |
13336 | return; | |
13337 | } | |
13338 | ||
584892a6 | 13339 | macro_start (); |
6478892d TS |
13340 | if (mips_cpreturn_register == -1) |
13341 | { | |
13342 | ex.X_op = O_constant; | |
13343 | ex.X_add_symbol = NULL; | |
13344 | ex.X_op_symbol = NULL; | |
13345 | ex.X_add_number = mips_cpreturn_offset; | |
13346 | ||
67c0d1eb | 13347 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13348 | } |
13349 | else | |
67c0d1eb | 13350 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13351 | mips_cpreturn_register, 0); |
584892a6 | 13352 | macro_end (); |
6478892d TS |
13353 | |
13354 | demand_empty_rest_of_line (); | |
13355 | } | |
13356 | ||
741d6ea8 JM |
13357 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13358 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13359 | use in DWARF debug information. */ | |
13360 | ||
13361 | static void | |
13362 | s_dtprel_internal (size_t bytes) | |
13363 | { | |
13364 | expressionS ex; | |
13365 | char *p; | |
13366 | ||
13367 | expression (&ex); | |
13368 | ||
13369 | if (ex.X_op != O_symbol) | |
13370 | { | |
13371 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13372 | ? ".dtpreldword" | |
13373 | : ".dtprelword")); | |
13374 | ignore_rest_of_line (); | |
13375 | } | |
13376 | ||
13377 | p = frag_more (bytes); | |
13378 | md_number_to_chars (p, 0, bytes); | |
13379 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13380 | (bytes == 8 | |
13381 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13382 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13383 | ||
13384 | demand_empty_rest_of_line (); | |
13385 | } | |
13386 | ||
13387 | /* Handle .dtprelword. */ | |
13388 | ||
13389 | static void | |
13390 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13391 | { | |
13392 | s_dtprel_internal (4); | |
13393 | } | |
13394 | ||
13395 | /* Handle .dtpreldword. */ | |
13396 | ||
13397 | static void | |
13398 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13399 | { | |
13400 | s_dtprel_internal (8); | |
13401 | } | |
13402 | ||
6478892d TS |
13403 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13404 | code. It sets the offset to use in gp_rel relocations. */ | |
13405 | ||
13406 | static void | |
17a2f251 | 13407 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13408 | { |
13409 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13410 | We also need NewABI support. */ | |
13411 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13412 | { | |
13413 | s_ignore (0); | |
13414 | return; | |
13415 | } | |
13416 | ||
def2e0dd | 13417 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13418 | |
13419 | demand_empty_rest_of_line (); | |
13420 | } | |
13421 | ||
252b5132 RH |
13422 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13423 | code. It generates a 32 bit GP relative reloc. */ | |
13424 | ||
13425 | static void | |
17a2f251 | 13426 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13427 | { |
a8dbcb85 TS |
13428 | segment_info_type *si; |
13429 | struct insn_label_list *l; | |
252b5132 RH |
13430 | symbolS *label; |
13431 | expressionS ex; | |
13432 | char *p; | |
13433 | ||
13434 | /* When not generating PIC code, this is treated as .word. */ | |
13435 | if (mips_pic != SVR4_PIC) | |
13436 | { | |
13437 | s_cons (2); | |
13438 | return; | |
13439 | } | |
13440 | ||
a8dbcb85 TS |
13441 | si = seg_info (now_seg); |
13442 | l = si->label_list; | |
13443 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13444 | mips_emit_delays (); |
252b5132 RH |
13445 | if (auto_align) |
13446 | mips_align (2, 0, label); | |
13447 | mips_clear_insn_labels (); | |
13448 | ||
13449 | expression (&ex); | |
13450 | ||
13451 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13452 | { | |
13453 | as_bad (_("Unsupported use of .gpword")); | |
13454 | ignore_rest_of_line (); | |
13455 | } | |
13456 | ||
13457 | p = frag_more (4); | |
17a2f251 | 13458 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13459 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13460 | BFD_RELOC_GPREL32); |
252b5132 RH |
13461 | |
13462 | demand_empty_rest_of_line (); | |
13463 | } | |
13464 | ||
10181a0d | 13465 | static void |
17a2f251 | 13466 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13467 | { |
a8dbcb85 TS |
13468 | segment_info_type *si; |
13469 | struct insn_label_list *l; | |
10181a0d AO |
13470 | symbolS *label; |
13471 | expressionS ex; | |
13472 | char *p; | |
13473 | ||
13474 | /* When not generating PIC code, this is treated as .dword. */ | |
13475 | if (mips_pic != SVR4_PIC) | |
13476 | { | |
13477 | s_cons (3); | |
13478 | return; | |
13479 | } | |
13480 | ||
a8dbcb85 TS |
13481 | si = seg_info (now_seg); |
13482 | l = si->label_list; | |
13483 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13484 | mips_emit_delays (); |
10181a0d AO |
13485 | if (auto_align) |
13486 | mips_align (3, 0, label); | |
13487 | mips_clear_insn_labels (); | |
13488 | ||
13489 | expression (&ex); | |
13490 | ||
13491 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13492 | { | |
13493 | as_bad (_("Unsupported use of .gpdword")); | |
13494 | ignore_rest_of_line (); | |
13495 | } | |
13496 | ||
13497 | p = frag_more (8); | |
17a2f251 | 13498 | md_number_to_chars (p, 0, 8); |
a105a300 | 13499 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13500 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13501 | |
13502 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13503 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13504 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13505 | |
13506 | demand_empty_rest_of_line (); | |
13507 | } | |
13508 | ||
252b5132 RH |
13509 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13510 | tables in SVR4 PIC code. */ | |
13511 | ||
13512 | static void | |
17a2f251 | 13513 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13514 | { |
252b5132 RH |
13515 | int reg; |
13516 | ||
10181a0d AO |
13517 | /* This is ignored when not generating SVR4 PIC code. */ |
13518 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13519 | { |
13520 | s_ignore (0); | |
13521 | return; | |
13522 | } | |
13523 | ||
13524 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13525 | macro_start (); |
252b5132 | 13526 | reg = tc_get_register (0); |
67c0d1eb | 13527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13528 | macro_end (); |
252b5132 | 13529 | |
bdaaa2e1 | 13530 | demand_empty_rest_of_line (); |
252b5132 RH |
13531 | } |
13532 | ||
13533 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13534 | mips16 mode. This permits the linker to handle them specially, | |
13535 | such as generating jalx instructions when needed. We also make | |
13536 | them odd for the duration of the assembly, in order to generate the | |
13537 | right sort of code. We will make them even in the adjust_symtab | |
13538 | routine, while leaving them marked. This is convenient for the | |
13539 | debugger and the disassembler. The linker knows to make them odd | |
13540 | again. */ | |
13541 | ||
13542 | static void | |
17a2f251 | 13543 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13544 | { |
f9419b05 | 13545 | mips16_mark_labels (); |
252b5132 RH |
13546 | |
13547 | demand_empty_rest_of_line (); | |
13548 | } | |
13549 | ||
13550 | /* Handle a .stabn directive. We need these in order to mark a label | |
13551 | as being a mips16 text label correctly. Sometimes the compiler | |
13552 | will emit a label, followed by a .stabn, and then switch sections. | |
13553 | If the label and .stabn are in mips16 mode, then the label is | |
13554 | really a mips16 text label. */ | |
13555 | ||
13556 | static void | |
17a2f251 | 13557 | s_mips_stab (int type) |
252b5132 | 13558 | { |
f9419b05 | 13559 | if (type == 'n') |
252b5132 RH |
13560 | mips16_mark_labels (); |
13561 | ||
13562 | s_stab (type); | |
13563 | } | |
13564 | ||
54f4ddb3 | 13565 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13566 | |
13567 | static void | |
17a2f251 | 13568 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13569 | { |
13570 | char *name; | |
13571 | int c; | |
13572 | symbolS *symbolP; | |
13573 | expressionS exp; | |
13574 | ||
13575 | name = input_line_pointer; | |
13576 | c = get_symbol_end (); | |
13577 | symbolP = symbol_find_or_make (name); | |
13578 | S_SET_WEAK (symbolP); | |
13579 | *input_line_pointer = c; | |
13580 | ||
13581 | SKIP_WHITESPACE (); | |
13582 | ||
13583 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13584 | { | |
13585 | if (S_IS_DEFINED (symbolP)) | |
13586 | { | |
20203fb9 | 13587 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13588 | S_GET_NAME (symbolP)); |
13589 | ignore_rest_of_line (); | |
13590 | return; | |
13591 | } | |
bdaaa2e1 | 13592 | |
252b5132 RH |
13593 | if (*input_line_pointer == ',') |
13594 | { | |
13595 | ++input_line_pointer; | |
13596 | SKIP_WHITESPACE (); | |
13597 | } | |
bdaaa2e1 | 13598 | |
252b5132 RH |
13599 | expression (&exp); |
13600 | if (exp.X_op != O_symbol) | |
13601 | { | |
20203fb9 | 13602 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13603 | ignore_rest_of_line (); |
252b5132 RH |
13604 | return; |
13605 | } | |
49309057 | 13606 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13607 | } |
13608 | ||
13609 | demand_empty_rest_of_line (); | |
13610 | } | |
13611 | ||
13612 | /* Parse a register string into a number. Called from the ECOFF code | |
13613 | to parse .frame. The argument is non-zero if this is the frame | |
13614 | register, so that we can record it in mips_frame_reg. */ | |
13615 | ||
13616 | int | |
17a2f251 | 13617 | tc_get_register (int frame) |
252b5132 | 13618 | { |
707bfff6 | 13619 | unsigned int reg; |
252b5132 RH |
13620 | |
13621 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13622 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13623 | reg = 0; | |
252b5132 | 13624 | if (frame) |
7a621144 DJ |
13625 | { |
13626 | mips_frame_reg = reg != 0 ? reg : SP; | |
13627 | mips_frame_reg_valid = 1; | |
13628 | mips_cprestore_valid = 0; | |
13629 | } | |
252b5132 RH |
13630 | return reg; |
13631 | } | |
13632 | ||
13633 | valueT | |
17a2f251 | 13634 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13635 | { |
13636 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13637 | ||
b4c71f56 TS |
13638 | if (IS_ELF) |
13639 | { | |
13640 | /* We don't need to align ELF sections to the full alignment. | |
13641 | However, Irix 5 may prefer that we align them at least to a 16 | |
13642 | byte boundary. We don't bother to align the sections if we | |
13643 | are targeted for an embedded system. */ | |
c41e87e3 | 13644 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13645 | return addr; |
13646 | if (align > 4) | |
13647 | align = 4; | |
13648 | } | |
252b5132 RH |
13649 | |
13650 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13651 | } | |
13652 | ||
13653 | /* Utility routine, called from above as well. If called while the | |
13654 | input file is still being read, it's only an approximation. (For | |
13655 | example, a symbol may later become defined which appeared to be | |
13656 | undefined earlier.) */ | |
13657 | ||
13658 | static int | |
17a2f251 | 13659 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13660 | { |
13661 | if (sym == 0) | |
13662 | return 0; | |
13663 | ||
4d0d148d | 13664 | if (g_switch_value > 0) |
252b5132 RH |
13665 | { |
13666 | const char *symname; | |
13667 | int change; | |
13668 | ||
c9914766 | 13669 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13670 | register. It can be if it is smaller than the -G size or if |
13671 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13672 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13673 | they can. */ |
13674 | symname = S_GET_NAME (sym); | |
13675 | if (symname != (const char *) NULL | |
13676 | && (strcmp (symname, "eprol") == 0 | |
13677 | || strcmp (symname, "etext") == 0 | |
13678 | || strcmp (symname, "_gp") == 0 | |
13679 | || strcmp (symname, "edata") == 0 | |
13680 | || strcmp (symname, "_fbss") == 0 | |
13681 | || strcmp (symname, "_fdata") == 0 | |
13682 | || strcmp (symname, "_ftext") == 0 | |
13683 | || strcmp (symname, "end") == 0 | |
13684 | || strcmp (symname, "_gp_disp") == 0)) | |
13685 | change = 1; | |
13686 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13687 | && (0 | |
13688 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13689 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13690 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13691 | <= g_switch_value)) | |
252b5132 RH |
13692 | #endif |
13693 | /* We must defer this decision until after the whole | |
13694 | file has been read, since there might be a .extern | |
13695 | after the first use of this symbol. */ | |
13696 | || (before_relaxing | |
13697 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13698 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13699 | #endif |
13700 | && S_GET_VALUE (sym) == 0) | |
13701 | || (S_GET_VALUE (sym) != 0 | |
13702 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13703 | change = 0; | |
13704 | else | |
13705 | { | |
13706 | const char *segname; | |
13707 | ||
13708 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13709 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13710 | && strcmp (segname, ".lit4") != 0); |
13711 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13712 | && strcmp (segname, ".sbss") != 0 |
13713 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13714 | && strncmp (segname, ".sbss.", 6) != 0 |
13715 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13716 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13717 | } |
13718 | return change; | |
13719 | } | |
13720 | else | |
c9914766 | 13721 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13722 | return 1; |
13723 | } | |
13724 | ||
5919d012 RS |
13725 | |
13726 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13727 | ||
13728 | static bfd_boolean | |
17a2f251 | 13729 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13730 | { |
13731 | asection *symsec; | |
5919d012 RS |
13732 | |
13733 | /* Handle the case of a symbol equated to another symbol. */ | |
13734 | while (symbol_equated_reloc_p (sym)) | |
13735 | { | |
13736 | symbolS *n; | |
13737 | ||
5f0fe04b | 13738 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13739 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13740 | if (n == sym) | |
13741 | break; | |
13742 | sym = n; | |
13743 | } | |
13744 | ||
df1f3cda DD |
13745 | if (symbol_section_p (sym)) |
13746 | return TRUE; | |
13747 | ||
5919d012 RS |
13748 | symsec = S_GET_SEGMENT (sym); |
13749 | ||
5919d012 RS |
13750 | /* This must duplicate the test in adjust_reloc_syms. */ |
13751 | return (symsec != &bfd_und_section | |
13752 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13753 | && !bfd_is_com_section (symsec) |
13754 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13755 | #ifdef OBJ_ELF |
13756 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13757 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13758 | #endif |
13759 | ); | |
13760 | } | |
13761 | ||
13762 | ||
252b5132 RH |
13763 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13764 | extended opcode. SEC is the section the frag is in. */ | |
13765 | ||
13766 | static int | |
17a2f251 | 13767 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13768 | { |
13769 | int type; | |
3994f87e | 13770 | const struct mips16_immed_operand *op; |
252b5132 RH |
13771 | offsetT val; |
13772 | int mintiny, maxtiny; | |
13773 | segT symsec; | |
98aa84af | 13774 | fragS *sym_frag; |
252b5132 RH |
13775 | |
13776 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13777 | return 0; | |
13778 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13779 | return 1; | |
13780 | ||
13781 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13782 | op = mips16_immed_operands; | |
13783 | while (op->type != type) | |
13784 | { | |
13785 | ++op; | |
9c2799c2 | 13786 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13787 | } |
13788 | ||
13789 | if (op->unsp) | |
13790 | { | |
13791 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13792 | { | |
13793 | mintiny = 1; | |
13794 | maxtiny = 1 << op->nbits; | |
13795 | } | |
13796 | else | |
13797 | { | |
13798 | mintiny = 0; | |
13799 | maxtiny = (1 << op->nbits) - 1; | |
13800 | } | |
13801 | } | |
13802 | else | |
13803 | { | |
13804 | mintiny = - (1 << (op->nbits - 1)); | |
13805 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13806 | } | |
13807 | ||
98aa84af | 13808 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13809 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13810 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13811 | |
13812 | if (op->pcrel) | |
13813 | { | |
13814 | addressT addr; | |
13815 | ||
13816 | /* We won't have the section when we are called from | |
13817 | mips_relax_frag. However, we will always have been called | |
13818 | from md_estimate_size_before_relax first. If this is a | |
13819 | branch to a different section, we mark it as such. If SEC is | |
13820 | NULL, and the frag is not marked, then it must be a branch to | |
13821 | the same section. */ | |
13822 | if (sec == NULL) | |
13823 | { | |
13824 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13825 | return 1; | |
13826 | } | |
13827 | else | |
13828 | { | |
98aa84af | 13829 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13830 | if (symsec != sec) |
13831 | { | |
13832 | fragp->fr_subtype = | |
13833 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13834 | ||
13835 | /* FIXME: We should support this, and let the linker | |
13836 | catch branches and loads that are out of range. */ | |
13837 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13838 | _("unsupported PC relative reference to different section")); | |
13839 | ||
13840 | return 1; | |
13841 | } | |
98aa84af AM |
13842 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13843 | /* Assume non-extended on the first relaxation pass. | |
13844 | The address we have calculated will be bogus if this is | |
13845 | a forward branch to another frag, as the forward frag | |
13846 | will have fr_address == 0. */ | |
13847 | return 0; | |
252b5132 RH |
13848 | } |
13849 | ||
13850 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13851 | the same section. If the relax_marker of the symbol fragment |
13852 | differs from the relax_marker of this fragment, we have not | |
13853 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13854 | in STRETCH in order to get a better estimate of the address. |
13855 | This particularly matters because of the shift bits. */ | |
13856 | if (stretch != 0 | |
98aa84af | 13857 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13858 | { |
13859 | fragS *f; | |
13860 | ||
13861 | /* Adjust stretch for any alignment frag. Note that if have | |
13862 | been expanding the earlier code, the symbol may be | |
13863 | defined in what appears to be an earlier frag. FIXME: | |
13864 | This doesn't handle the fr_subtype field, which specifies | |
13865 | a maximum number of bytes to skip when doing an | |
13866 | alignment. */ | |
98aa84af | 13867 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13868 | { |
13869 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13870 | { | |
13871 | if (stretch < 0) | |
13872 | stretch = - ((- stretch) | |
13873 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13874 | else | |
13875 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13876 | if (stretch == 0) | |
13877 | break; | |
13878 | } | |
13879 | } | |
13880 | if (f != NULL) | |
13881 | val += stretch; | |
13882 | } | |
13883 | ||
13884 | addr = fragp->fr_address + fragp->fr_fix; | |
13885 | ||
13886 | /* The base address rules are complicated. The base address of | |
13887 | a branch is the following instruction. The base address of a | |
13888 | PC relative load or add is the instruction itself, but if it | |
13889 | is in a delay slot (in which case it can not be extended) use | |
13890 | the address of the instruction whose delay slot it is in. */ | |
13891 | if (type == 'p' || type == 'q') | |
13892 | { | |
13893 | addr += 2; | |
13894 | ||
13895 | /* If we are currently assuming that this frag should be | |
13896 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13897 | higher. */ |
252b5132 RH |
13898 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13899 | addr += 2; | |
13900 | ||
13901 | /* Ignore the low bit in the target, since it will be set | |
13902 | for a text label. */ | |
13903 | if ((val & 1) != 0) | |
13904 | --val; | |
13905 | } | |
13906 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13907 | addr -= 4; | |
13908 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13909 | addr -= 2; | |
13910 | ||
13911 | val -= addr & ~ ((1 << op->shift) - 1); | |
13912 | ||
13913 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13914 | if (type == 'p' || type == 'q') | |
13915 | val /= 2; | |
13916 | ||
13917 | /* If any of the shifted bits are set, we must use an extended | |
13918 | opcode. If the address depends on the size of this | |
13919 | instruction, this can lead to a loop, so we arrange to always | |
13920 | use an extended opcode. We only check this when we are in | |
13921 | the main relaxation loop, when SEC is NULL. */ | |
13922 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13923 | { | |
13924 | fragp->fr_subtype = | |
13925 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13926 | return 1; | |
13927 | } | |
13928 | ||
13929 | /* If we are about to mark a frag as extended because the value | |
13930 | is precisely maxtiny + 1, then there is a chance of an | |
13931 | infinite loop as in the following code: | |
13932 | la $4,foo | |
13933 | .skip 1020 | |
13934 | .align 2 | |
13935 | foo: | |
13936 | In this case when the la is extended, foo is 0x3fc bytes | |
13937 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13938 | the la must be extended. To avoid this loop, we mark the | |
13939 | frag as extended if it was small, and is about to become | |
13940 | extended with a value of maxtiny + 1. */ | |
13941 | if (val == ((maxtiny + 1) << op->shift) | |
13942 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13943 | && sec == NULL) | |
13944 | { | |
13945 | fragp->fr_subtype = | |
13946 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13947 | return 1; | |
13948 | } | |
13949 | } | |
13950 | else if (symsec != absolute_section && sec != NULL) | |
13951 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13952 | ||
13953 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13954 | || val < (mintiny << op->shift) | |
13955 | || val > (maxtiny << op->shift)) | |
13956 | return 1; | |
13957 | else | |
13958 | return 0; | |
13959 | } | |
13960 | ||
4a6a3df4 AO |
13961 | /* Compute the length of a branch sequence, and adjust the |
13962 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13963 | worst-case length is computed, with UPDATE being used to indicate | |
13964 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13965 | branch is to be computed. */ | |
13966 | static int | |
17a2f251 | 13967 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13968 | { |
b34976b6 | 13969 | bfd_boolean toofar; |
4a6a3df4 AO |
13970 | int length; |
13971 | ||
13972 | if (fragp | |
13973 | && S_IS_DEFINED (fragp->fr_symbol) | |
13974 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13975 | { | |
13976 | addressT addr; | |
13977 | offsetT val; | |
13978 | ||
13979 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13980 | ||
13981 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13982 | ||
13983 | val -= addr; | |
13984 | ||
13985 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13986 | } | |
13987 | else if (fragp) | |
13988 | /* If the symbol is not defined or it's in a different segment, | |
13989 | assume the user knows what's going on and emit a short | |
13990 | branch. */ | |
b34976b6 | 13991 | toofar = FALSE; |
4a6a3df4 | 13992 | else |
b34976b6 | 13993 | toofar = TRUE; |
4a6a3df4 AO |
13994 | |
13995 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13996 | fragp->fr_subtype | |
af6ae2ad | 13997 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13998 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13999 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14000 | toofar); | |
14001 | ||
14002 | length = 4; | |
14003 | if (toofar) | |
14004 | { | |
14005 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14006 | length += 8; | |
14007 | ||
14008 | if (mips_pic != NO_PIC) | |
14009 | { | |
14010 | /* Additional space for PIC loading of target address. */ | |
14011 | length += 8; | |
14012 | if (mips_opts.isa == ISA_MIPS1) | |
14013 | /* Additional space for $at-stabilizing nop. */ | |
14014 | length += 4; | |
14015 | } | |
14016 | ||
14017 | /* If branch is conditional. */ | |
14018 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14019 | length += 8; | |
14020 | } | |
b34976b6 | 14021 | |
4a6a3df4 AO |
14022 | return length; |
14023 | } | |
14024 | ||
252b5132 RH |
14025 | /* Estimate the size of a frag before relaxing. Unless this is the |
14026 | mips16, we are not really relaxing here, and the final size is | |
14027 | encoded in the subtype information. For the mips16, we have to | |
14028 | decide whether we are using an extended opcode or not. */ | |
14029 | ||
252b5132 | 14030 | int |
17a2f251 | 14031 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14032 | { |
5919d012 | 14033 | int change; |
252b5132 | 14034 | |
4a6a3df4 AO |
14035 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14036 | { | |
14037 | ||
b34976b6 AM |
14038 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14039 | ||
4a6a3df4 AO |
14040 | return fragp->fr_var; |
14041 | } | |
14042 | ||
252b5132 | 14043 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14044 | /* We don't want to modify the EXTENDED bit here; it might get us |
14045 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14046 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14047 | |
14048 | if (mips_pic == NO_PIC) | |
5919d012 | 14049 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14050 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14051 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14052 | else if (mips_pic == VXWORKS_PIC) |
14053 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14054 | change = 0; | |
252b5132 RH |
14055 | else |
14056 | abort (); | |
14057 | ||
14058 | if (change) | |
14059 | { | |
4d7206a2 | 14060 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14061 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14062 | } |
4d7206a2 RS |
14063 | else |
14064 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14065 | } |
14066 | ||
14067 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14068 | should be converted into a reloc against a section. */ |
252b5132 RH |
14069 | |
14070 | int | |
17a2f251 | 14071 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14072 | { |
252b5132 RH |
14073 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14074 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14075 | return 0; | |
a161fe53 | 14076 | |
252b5132 RH |
14077 | if (fixp->fx_addsy == NULL) |
14078 | return 1; | |
a161fe53 | 14079 | |
de7e6852 RS |
14080 | /* If symbol SYM is in a mergeable section, relocations of the form |
14081 | SYM + 0 can usually be made section-relative. The mergeable data | |
14082 | is then identified by the section offset rather than by the symbol. | |
14083 | ||
14084 | However, if we're generating REL LO16 relocations, the offset is split | |
14085 | between the LO16 and parterning high part relocation. The linker will | |
14086 | need to recalculate the complete offset in order to correctly identify | |
14087 | the merge data. | |
14088 | ||
14089 | The linker has traditionally not looked for the parterning high part | |
14090 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14091 | placed anywhere. Rather than break backwards compatibility by changing | |
14092 | this, it seems better not to force the issue, and instead keep the | |
14093 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14094 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14095 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14096 | && HAVE_IN_PLACE_ADDENDS |
14097 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14098 | return 0; | |
14099 | ||
252b5132 | 14100 | #ifdef OBJ_ELF |
b314ec0e RS |
14101 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14102 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14103 | relocations against MIPS16 functions; in this case, the stub becomes | |
14104 | the function's canonical address. | |
14105 | ||
14106 | Floating-point stubs are stored in unique .mips16.call.* or | |
14107 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14108 | the first relocation in section S must be against F; this is how the | |
14109 | linker determines the target function. All relocations that might | |
14110 | resolve to T must also be against F. We therefore have the following | |
14111 | restrictions, which are given in an intentionally-redundant way: | |
14112 | ||
14113 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14114 | symbols. | |
14115 | ||
14116 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14117 | if that stub might be used. | |
14118 | ||
14119 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14120 | symbols. | |
14121 | ||
14122 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14123 | that stub might be used. | |
14124 | ||
14125 | There is a further restriction: | |
14126 | ||
14127 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14128 | on targets with in-place addends; the relocation field cannot | |
14129 | encode the low bit. | |
14130 | ||
14131 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14132 | against a MIPS16 symbol. | |
14133 | ||
14134 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14135 | relocation against some symbol R, no relocation against R may be | |
14136 | reduced. (Note that this deals with (2) as well as (1) because | |
14137 | relocations against global symbols will never be reduced on ELF | |
14138 | targets.) This approach is a little simpler than trying to detect | |
14139 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14140 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14141 | if (IS_ELF |
b314ec0e | 14142 | && fixp->fx_subsy == NULL |
30c09090 | 14143 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14144 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14145 | return 0; |
14146 | #endif | |
a161fe53 | 14147 | |
252b5132 RH |
14148 | return 1; |
14149 | } | |
14150 | ||
14151 | /* Translate internal representation of relocation info to BFD target | |
14152 | format. */ | |
14153 | ||
14154 | arelent ** | |
17a2f251 | 14155 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14156 | { |
14157 | static arelent *retval[4]; | |
14158 | arelent *reloc; | |
14159 | bfd_reloc_code_real_type code; | |
14160 | ||
4b0cff4e TS |
14161 | memset (retval, 0, sizeof(retval)); |
14162 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14163 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14164 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14165 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14166 | ||
bad36eac DJ |
14167 | if (fixp->fx_pcrel) |
14168 | { | |
9c2799c2 | 14169 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14170 | |
14171 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14172 | Relocations want only the symbol offset. */ | |
14173 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14174 | if (!IS_ELF) |
bad36eac DJ |
14175 | { |
14176 | /* A gruesome hack which is a result of the gruesome gas | |
14177 | reloc handling. What's worse, for COFF (as opposed to | |
14178 | ECOFF), we might need yet another copy of reloc->address. | |
14179 | See bfd_install_relocation. */ | |
14180 | reloc->addend += reloc->address; | |
14181 | } | |
14182 | } | |
14183 | else | |
14184 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14185 | |
438c16b8 TS |
14186 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14187 | entry to be used in the relocation's section offset. */ | |
14188 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14189 | { |
14190 | reloc->address = reloc->addend; | |
14191 | reloc->addend = 0; | |
14192 | } | |
14193 | ||
252b5132 | 14194 | code = fixp->fx_r_type; |
252b5132 | 14195 | |
bad36eac | 14196 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14197 | if (reloc->howto == NULL) |
14198 | { | |
14199 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14200 | _("Can not represent %s relocation in this object file format"), | |
14201 | bfd_get_reloc_code_name (code)); | |
14202 | retval[0] = NULL; | |
14203 | } | |
14204 | ||
14205 | return retval; | |
14206 | } | |
14207 | ||
14208 | /* Relax a machine dependent frag. This returns the amount by which | |
14209 | the current size of the frag should change. */ | |
14210 | ||
14211 | int | |
17a2f251 | 14212 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14213 | { |
4a6a3df4 AO |
14214 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14215 | { | |
14216 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14217 | |
14218 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14219 | |
14220 | return fragp->fr_var - old_var; | |
14221 | } | |
14222 | ||
252b5132 RH |
14223 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14224 | return 0; | |
14225 | ||
c4e7957c | 14226 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14227 | { |
14228 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14229 | return 0; | |
14230 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14231 | return 2; | |
14232 | } | |
14233 | else | |
14234 | { | |
14235 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14236 | return 0; | |
14237 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14238 | return -2; | |
14239 | } | |
14240 | ||
14241 | return 0; | |
14242 | } | |
14243 | ||
14244 | /* Convert a machine dependent frag. */ | |
14245 | ||
14246 | void | |
17a2f251 | 14247 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14248 | { |
4a6a3df4 AO |
14249 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14250 | { | |
14251 | bfd_byte *buf; | |
14252 | unsigned long insn; | |
14253 | expressionS exp; | |
14254 | fixS *fixp; | |
b34976b6 | 14255 | |
4a6a3df4 AO |
14256 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14257 | ||
14258 | if (target_big_endian) | |
14259 | insn = bfd_getb32 (buf); | |
14260 | else | |
14261 | insn = bfd_getl32 (buf); | |
b34976b6 | 14262 | |
4a6a3df4 AO |
14263 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14264 | { | |
14265 | /* We generate a fixup instead of applying it right now | |
14266 | because, if there are linker relaxations, we're going to | |
14267 | need the relocations. */ | |
14268 | exp.X_op = O_symbol; | |
14269 | exp.X_add_symbol = fragp->fr_symbol; | |
14270 | exp.X_add_number = fragp->fr_offset; | |
14271 | ||
14272 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14273 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14274 | fixp->fx_file = fragp->fr_file; |
14275 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14276 | |
2132e3a3 | 14277 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14278 | buf += 4; |
14279 | } | |
14280 | else | |
14281 | { | |
14282 | int i; | |
14283 | ||
14284 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14285 | _("relaxed out-of-range branch into a jump")); | |
14286 | ||
14287 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14288 | goto uncond; | |
14289 | ||
14290 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14291 | { | |
14292 | /* Reverse the branch. */ | |
14293 | switch ((insn >> 28) & 0xf) | |
14294 | { | |
14295 | case 4: | |
14296 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14297 | have the condition reversed by tweaking a single | |
14298 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14299 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14300 | insn ^= 0x00010000; |
14301 | break; | |
14302 | ||
14303 | case 0: | |
14304 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14305 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14306 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14307 | insn ^= 0x00010000; |
14308 | break; | |
b34976b6 | 14309 | |
4a6a3df4 AO |
14310 | case 1: |
14311 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14312 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14313 | insn ^= 0x04000000; |
14314 | break; | |
14315 | ||
14316 | default: | |
14317 | abort (); | |
14318 | } | |
14319 | } | |
14320 | ||
14321 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14322 | { | |
14323 | /* Clear the and-link bit. */ | |
9c2799c2 | 14324 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14325 | |
54f4ddb3 TS |
14326 | /* bltzal 0x04100000 bgezal 0x04110000 |
14327 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14328 | insn &= ~0x00100000; |
14329 | } | |
14330 | ||
14331 | /* Branch over the branch (if the branch was likely) or the | |
14332 | full jump (not likely case). Compute the offset from the | |
14333 | current instruction to branch to. */ | |
14334 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14335 | i = 16; | |
14336 | else | |
14337 | { | |
14338 | /* How many bytes in instructions we've already emitted? */ | |
14339 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14340 | /* How many bytes in instructions from here to the end? */ | |
14341 | i = fragp->fr_var - i; | |
14342 | } | |
14343 | /* Convert to instruction count. */ | |
14344 | i >>= 2; | |
14345 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14346 | i--; |
4a6a3df4 AO |
14347 | insn |= i; |
14348 | /* Branch over the jump. */ | |
2132e3a3 | 14349 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14350 | buf += 4; |
14351 | ||
54f4ddb3 | 14352 | /* nop */ |
2132e3a3 | 14353 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14354 | buf += 4; |
14355 | ||
14356 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14357 | { | |
14358 | /* beql $0, $0, 2f */ | |
14359 | insn = 0x50000000; | |
14360 | /* Compute the PC offset from the current instruction to | |
14361 | the end of the variable frag. */ | |
14362 | /* How many bytes in instructions we've already emitted? */ | |
14363 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14364 | /* How many bytes in instructions from here to the end? */ | |
14365 | i = fragp->fr_var - i; | |
14366 | /* Convert to instruction count. */ | |
14367 | i >>= 2; | |
14368 | /* Don't decrement i, because we want to branch over the | |
14369 | delay slot. */ | |
14370 | ||
14371 | insn |= i; | |
2132e3a3 | 14372 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14373 | buf += 4; |
14374 | ||
2132e3a3 | 14375 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14376 | buf += 4; |
14377 | } | |
14378 | ||
14379 | uncond: | |
14380 | if (mips_pic == NO_PIC) | |
14381 | { | |
14382 | /* j or jal. */ | |
14383 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14384 | ? 0x0c000000 : 0x08000000); | |
14385 | exp.X_op = O_symbol; | |
14386 | exp.X_add_symbol = fragp->fr_symbol; | |
14387 | exp.X_add_number = fragp->fr_offset; | |
14388 | ||
14389 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14390 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14391 | fixp->fx_file = fragp->fr_file; |
14392 | fixp->fx_line = fragp->fr_line; | |
14393 | ||
2132e3a3 | 14394 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14395 | buf += 4; |
14396 | } | |
14397 | else | |
14398 | { | |
14399 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14400 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14401 | exp.X_op = O_symbol; | |
14402 | exp.X_add_symbol = fragp->fr_symbol; | |
14403 | exp.X_add_number = fragp->fr_offset; | |
14404 | ||
14405 | if (fragp->fr_offset) | |
14406 | { | |
14407 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14408 | exp.X_add_number = 0; | |
14409 | } | |
14410 | ||
14411 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14412 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14413 | fixp->fx_file = fragp->fr_file; |
14414 | fixp->fx_line = fragp->fr_line; | |
14415 | ||
2132e3a3 | 14416 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14417 | buf += 4; |
b34976b6 | 14418 | |
4a6a3df4 AO |
14419 | if (mips_opts.isa == ISA_MIPS1) |
14420 | { | |
14421 | /* nop */ | |
2132e3a3 | 14422 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14423 | buf += 4; |
14424 | } | |
14425 | ||
14426 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14427 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14428 | ||
14429 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14430 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14431 | fixp->fx_file = fragp->fr_file; |
14432 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14433 | |
2132e3a3 | 14434 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14435 | buf += 4; |
14436 | ||
14437 | /* j(al)r $at. */ | |
14438 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14439 | insn = 0x0020f809; | |
14440 | else | |
14441 | insn = 0x00200008; | |
14442 | ||
2132e3a3 | 14443 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14444 | buf += 4; |
14445 | } | |
14446 | } | |
14447 | ||
9c2799c2 | 14448 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14449 | + fragp->fr_fix + fragp->fr_var); |
14450 | ||
14451 | fragp->fr_fix += fragp->fr_var; | |
14452 | ||
14453 | return; | |
14454 | } | |
14455 | ||
252b5132 RH |
14456 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14457 | { | |
14458 | int type; | |
3994f87e | 14459 | const struct mips16_immed_operand *op; |
b34976b6 | 14460 | bfd_boolean small, ext; |
252b5132 RH |
14461 | offsetT val; |
14462 | bfd_byte *buf; | |
14463 | unsigned long insn; | |
b34976b6 | 14464 | bfd_boolean use_extend; |
252b5132 RH |
14465 | unsigned short extend; |
14466 | ||
14467 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14468 | op = mips16_immed_operands; | |
14469 | while (op->type != type) | |
14470 | ++op; | |
14471 | ||
14472 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14473 | { | |
b34976b6 AM |
14474 | small = FALSE; |
14475 | ext = TRUE; | |
252b5132 RH |
14476 | } |
14477 | else | |
14478 | { | |
b34976b6 AM |
14479 | small = TRUE; |
14480 | ext = FALSE; | |
252b5132 RH |
14481 | } |
14482 | ||
6386f3a7 | 14483 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14484 | val = S_GET_VALUE (fragp->fr_symbol); |
14485 | if (op->pcrel) | |
14486 | { | |
14487 | addressT addr; | |
14488 | ||
14489 | addr = fragp->fr_address + fragp->fr_fix; | |
14490 | ||
14491 | /* The rules for the base address of a PC relative reloc are | |
14492 | complicated; see mips16_extended_frag. */ | |
14493 | if (type == 'p' || type == 'q') | |
14494 | { | |
14495 | addr += 2; | |
14496 | if (ext) | |
14497 | addr += 2; | |
14498 | /* Ignore the low bit in the target, since it will be | |
14499 | set for a text label. */ | |
14500 | if ((val & 1) != 0) | |
14501 | --val; | |
14502 | } | |
14503 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14504 | addr -= 4; | |
14505 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14506 | addr -= 2; | |
14507 | ||
14508 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14509 | val -= addr; | |
14510 | ||
14511 | /* Make sure the section winds up with the alignment we have | |
14512 | assumed. */ | |
14513 | if (op->shift > 0) | |
14514 | record_alignment (asec, op->shift); | |
14515 | } | |
14516 | ||
14517 | if (ext | |
14518 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14519 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14520 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14521 | _("extended instruction in delay slot")); | |
14522 | ||
14523 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14524 | ||
14525 | if (target_big_endian) | |
14526 | insn = bfd_getb16 (buf); | |
14527 | else | |
14528 | insn = bfd_getl16 (buf); | |
14529 | ||
14530 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14531 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14532 | small, ext, &insn, &use_extend, &extend); | |
14533 | ||
14534 | if (use_extend) | |
14535 | { | |
2132e3a3 | 14536 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14537 | fragp->fr_fix += 2; |
14538 | buf += 2; | |
14539 | } | |
14540 | ||
2132e3a3 | 14541 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14542 | fragp->fr_fix += 2; |
14543 | buf += 2; | |
14544 | } | |
14545 | else | |
14546 | { | |
4d7206a2 RS |
14547 | int first, second; |
14548 | fixS *fixp; | |
252b5132 | 14549 | |
4d7206a2 RS |
14550 | first = RELAX_FIRST (fragp->fr_subtype); |
14551 | second = RELAX_SECOND (fragp->fr_subtype); | |
14552 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14553 | |
584892a6 RS |
14554 | /* Possibly emit a warning if we've chosen the longer option. */ |
14555 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14556 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14557 | { | |
14558 | const char *msg = macro_warning (fragp->fr_subtype); | |
14559 | if (msg != 0) | |
520725ea | 14560 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14561 | } |
14562 | ||
4d7206a2 RS |
14563 | /* Go through all the fixups for the first sequence. Disable them |
14564 | (by marking them as done) if we're going to use the second | |
14565 | sequence instead. */ | |
14566 | while (fixp | |
14567 | && fixp->fx_frag == fragp | |
14568 | && fixp->fx_where < fragp->fr_fix - second) | |
14569 | { | |
14570 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14571 | fixp->fx_done = 1; | |
14572 | fixp = fixp->fx_next; | |
14573 | } | |
252b5132 | 14574 | |
4d7206a2 RS |
14575 | /* Go through the fixups for the second sequence. Disable them if |
14576 | we're going to use the first sequence, otherwise adjust their | |
14577 | addresses to account for the relaxation. */ | |
14578 | while (fixp && fixp->fx_frag == fragp) | |
14579 | { | |
14580 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14581 | fixp->fx_where -= first; | |
14582 | else | |
14583 | fixp->fx_done = 1; | |
14584 | fixp = fixp->fx_next; | |
14585 | } | |
14586 | ||
14587 | /* Now modify the frag contents. */ | |
14588 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14589 | { | |
14590 | char *start; | |
14591 | ||
14592 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14593 | memmove (start, start + first, second); | |
14594 | fragp->fr_fix -= first; | |
14595 | } | |
14596 | else | |
14597 | fragp->fr_fix -= second; | |
252b5132 RH |
14598 | } |
14599 | } | |
14600 | ||
14601 | #ifdef OBJ_ELF | |
14602 | ||
14603 | /* This function is called after the relocs have been generated. | |
14604 | We've been storing mips16 text labels as odd. Here we convert them | |
14605 | back to even for the convenience of the debugger. */ | |
14606 | ||
14607 | void | |
17a2f251 | 14608 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14609 | { |
14610 | asymbol **syms; | |
14611 | unsigned int count, i; | |
14612 | ||
f43abd2b | 14613 | if (!IS_ELF) |
252b5132 RH |
14614 | return; |
14615 | ||
14616 | syms = bfd_get_outsymbols (stdoutput); | |
14617 | count = bfd_get_symcount (stdoutput); | |
14618 | for (i = 0; i < count; i++, syms++) | |
14619 | { | |
30c09090 | 14620 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14621 | && ((*syms)->value & 1) != 0) |
14622 | { | |
14623 | (*syms)->value &= ~1; | |
14624 | /* If the symbol has an odd size, it was probably computed | |
14625 | incorrectly, so adjust that as well. */ | |
14626 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14627 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14628 | } | |
14629 | } | |
14630 | } | |
14631 | ||
14632 | #endif | |
14633 | ||
14634 | /* This function is called whenever a label is defined. It is used | |
14635 | when handling branch delays; if a branch has a label, we assume we | |
14636 | can not move it. */ | |
14637 | ||
14638 | void | |
17a2f251 | 14639 | mips_define_label (symbolS *sym) |
252b5132 | 14640 | { |
a8dbcb85 | 14641 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14642 | struct insn_label_list *l; |
14643 | ||
14644 | if (free_insn_labels == NULL) | |
14645 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14646 | else | |
14647 | { | |
14648 | l = free_insn_labels; | |
14649 | free_insn_labels = l->next; | |
14650 | } | |
14651 | ||
14652 | l->label = sym; | |
a8dbcb85 TS |
14653 | l->next = si->label_list; |
14654 | si->label_list = l; | |
07a53e5c RH |
14655 | |
14656 | #ifdef OBJ_ELF | |
14657 | dwarf2_emit_label (sym); | |
14658 | #endif | |
252b5132 RH |
14659 | } |
14660 | \f | |
14661 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14662 | ||
14663 | /* Some special processing for a MIPS ELF file. */ | |
14664 | ||
14665 | void | |
17a2f251 | 14666 | mips_elf_final_processing (void) |
252b5132 RH |
14667 | { |
14668 | /* Write out the register information. */ | |
316f5878 | 14669 | if (mips_abi != N64_ABI) |
252b5132 RH |
14670 | { |
14671 | Elf32_RegInfo s; | |
14672 | ||
14673 | s.ri_gprmask = mips_gprmask; | |
14674 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14675 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14676 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14677 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14678 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14679 | ||
14680 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14681 | ((Elf32_External_RegInfo *) | |
14682 | mips_regmask_frag)); | |
14683 | } | |
14684 | else | |
14685 | { | |
14686 | Elf64_Internal_RegInfo s; | |
14687 | ||
14688 | s.ri_gprmask = mips_gprmask; | |
14689 | s.ri_pad = 0; | |
14690 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14691 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14692 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14693 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14694 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14695 | ||
14696 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14697 | ((Elf64_External_RegInfo *) | |
14698 | mips_regmask_frag)); | |
14699 | } | |
14700 | ||
14701 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14702 | sort of BFD interface for this. */ | |
14703 | if (mips_any_noreorder) | |
14704 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14705 | if (mips_pic != NO_PIC) | |
143d77c5 | 14706 | { |
252b5132 | 14707 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14708 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14709 | } | |
14710 | if (mips_abicalls) | |
14711 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14712 | |
98d3f06f | 14713 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14714 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14715 | file_ase_dsp is true. */ | |
8b082fb1 | 14716 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14717 | /* We may need to define a new flag for MT ASE, and set this flag when |
14718 | file_ase_mt is true. */ | |
a4672219 TS |
14719 | if (file_ase_mips16) |
14720 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14721 | #if 0 /* XXX FIXME */ |
14722 | if (file_ase_mips3d) | |
14723 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14724 | #endif | |
deec1734 CD |
14725 | if (file_ase_mdmx) |
14726 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14727 | |
bdaaa2e1 | 14728 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14729 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14730 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14731 | else if (mips_abi == O64_ABI) |
252b5132 | 14732 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14733 | else if (mips_abi == EABI_ABI) |
252b5132 | 14734 | { |
316f5878 | 14735 | if (!file_mips_gp32) |
252b5132 RH |
14736 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14737 | else | |
14738 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14739 | } | |
316f5878 | 14740 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14741 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14742 | ||
c9914766 | 14743 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14744 | |
14745 | if (mips_32bitmode) | |
14746 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14747 | |
14748 | #if 0 /* XXX FIXME */ | |
14749 | /* 32 bit code with 64 bit FP registers. */ | |
14750 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14751 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14752 | #endif | |
252b5132 RH |
14753 | } |
14754 | ||
14755 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14756 | \f | |
beae10d5 | 14757 | typedef struct proc { |
9b2f1d35 EC |
14758 | symbolS *func_sym; |
14759 | symbolS *func_end_sym; | |
beae10d5 KH |
14760 | unsigned long reg_mask; |
14761 | unsigned long reg_offset; | |
14762 | unsigned long fpreg_mask; | |
14763 | unsigned long fpreg_offset; | |
14764 | unsigned long frame_offset; | |
14765 | unsigned long frame_reg; | |
14766 | unsigned long pc_reg; | |
14767 | } procS; | |
252b5132 RH |
14768 | |
14769 | static procS cur_proc; | |
14770 | static procS *cur_proc_ptr; | |
14771 | static int numprocs; | |
14772 | ||
742a56fe RS |
14773 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14774 | nop as "0". */ | |
14775 | ||
14776 | char | |
14777 | mips_nop_opcode (void) | |
14778 | { | |
14779 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14780 | } | |
14781 | ||
14782 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14783 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14784 | |
0a9ef439 | 14785 | void |
17a2f251 | 14786 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14787 | { |
742a56fe RS |
14788 | char *p; |
14789 | ||
0a9ef439 RH |
14790 | if (fragp->fr_type != rs_align_code) |
14791 | return; | |
14792 | ||
742a56fe RS |
14793 | p = fragp->fr_literal + fragp->fr_fix; |
14794 | if (*p) | |
a19d8eb0 | 14795 | { |
0a9ef439 | 14796 | int bytes; |
a19d8eb0 | 14797 | |
0a9ef439 | 14798 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
0a9ef439 RH |
14799 | if (bytes & 1) |
14800 | { | |
14801 | *p++ = 0; | |
f9419b05 | 14802 | fragp->fr_fix++; |
0a9ef439 | 14803 | } |
742a56fe | 14804 | md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2); |
0a9ef439 | 14805 | fragp->fr_var = 2; |
a19d8eb0 | 14806 | } |
a19d8eb0 CP |
14807 | } |
14808 | ||
252b5132 | 14809 | static void |
17a2f251 | 14810 | md_obj_begin (void) |
252b5132 RH |
14811 | { |
14812 | } | |
14813 | ||
14814 | static void | |
17a2f251 | 14815 | md_obj_end (void) |
252b5132 | 14816 | { |
54f4ddb3 | 14817 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14818 | if (cur_proc_ptr) |
9a41af64 | 14819 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14820 | } |
14821 | ||
14822 | static long | |
17a2f251 | 14823 | get_number (void) |
252b5132 RH |
14824 | { |
14825 | int negative = 0; | |
14826 | long val = 0; | |
14827 | ||
14828 | if (*input_line_pointer == '-') | |
14829 | { | |
14830 | ++input_line_pointer; | |
14831 | negative = 1; | |
14832 | } | |
3882b010 | 14833 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14834 | as_bad (_("expected simple number")); |
252b5132 RH |
14835 | if (input_line_pointer[0] == '0') |
14836 | { | |
14837 | if (input_line_pointer[1] == 'x') | |
14838 | { | |
14839 | input_line_pointer += 2; | |
3882b010 | 14840 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14841 | { |
14842 | val <<= 4; | |
14843 | val |= hex_value (*input_line_pointer++); | |
14844 | } | |
14845 | return negative ? -val : val; | |
14846 | } | |
14847 | else | |
14848 | { | |
14849 | ++input_line_pointer; | |
3882b010 | 14850 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14851 | { |
14852 | val <<= 3; | |
14853 | val |= *input_line_pointer++ - '0'; | |
14854 | } | |
14855 | return negative ? -val : val; | |
14856 | } | |
14857 | } | |
3882b010 | 14858 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14859 | { |
14860 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14861 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14862 | as_warn (_("invalid number")); |
252b5132 RH |
14863 | return -1; |
14864 | } | |
3882b010 | 14865 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14866 | { |
14867 | val *= 10; | |
14868 | val += *input_line_pointer++ - '0'; | |
14869 | } | |
14870 | return negative ? -val : val; | |
14871 | } | |
14872 | ||
14873 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14874 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14875 | case .file implies DWARF-2. */ | |
14876 | ||
14877 | static void | |
17a2f251 | 14878 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14879 | { |
ecb4347a DJ |
14880 | static int first_file_directive = 0; |
14881 | ||
c5dd6aab DJ |
14882 | if (ECOFF_DEBUGGING) |
14883 | { | |
14884 | get_number (); | |
14885 | s_app_file (0); | |
14886 | } | |
14887 | else | |
ecb4347a DJ |
14888 | { |
14889 | char *filename; | |
14890 | ||
14891 | filename = dwarf2_directive_file (0); | |
14892 | ||
14893 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14894 | directive even for stabs output. Make sure that this | |
14895 | ".file" is handled. Note that you need a version of GCC | |
14896 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14897 | if (filename != NULL && ! first_file_directive) | |
14898 | { | |
14899 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14900 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14901 | } |
14902 | first_file_directive = 1; | |
14903 | } | |
c5dd6aab DJ |
14904 | } |
14905 | ||
14906 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14907 | |
14908 | static void | |
17a2f251 | 14909 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14910 | { |
c5dd6aab DJ |
14911 | if (!ECOFF_DEBUGGING) |
14912 | dwarf2_directive_loc (0); | |
252b5132 RH |
14913 | } |
14914 | ||
252b5132 RH |
14915 | /* The .end directive. */ |
14916 | ||
14917 | static void | |
17a2f251 | 14918 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14919 | { |
14920 | symbolS *p; | |
252b5132 | 14921 | |
7a621144 DJ |
14922 | /* Following functions need their own .frame and .cprestore directives. */ |
14923 | mips_frame_reg_valid = 0; | |
14924 | mips_cprestore_valid = 0; | |
14925 | ||
252b5132 RH |
14926 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14927 | { | |
14928 | p = get_symbol (); | |
14929 | demand_empty_rest_of_line (); | |
14930 | } | |
14931 | else | |
14932 | p = NULL; | |
14933 | ||
14949570 | 14934 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14935 | as_warn (_(".end not in text section")); |
14936 | ||
14937 | if (!cur_proc_ptr) | |
14938 | { | |
14939 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14940 | demand_empty_rest_of_line (); | |
14941 | return; | |
14942 | } | |
14943 | ||
14944 | if (p != NULL) | |
14945 | { | |
9c2799c2 | 14946 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 14947 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14948 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14949 | |
14950 | if (debug_type == DEBUG_STABS) | |
14951 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14952 | S_GET_NAME (p)); | |
252b5132 RH |
14953 | } |
14954 | else | |
14955 | as_warn (_(".end directive missing or unknown symbol")); | |
14956 | ||
2132e3a3 | 14957 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14958 | /* Create an expression to calculate the size of the function. */ |
14959 | if (p && cur_proc_ptr) | |
14960 | { | |
14961 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14962 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14963 | ||
14964 | obj->size = exp; | |
14965 | exp->X_op = O_subtract; | |
14966 | exp->X_add_symbol = symbol_temp_new_now (); | |
14967 | exp->X_op_symbol = p; | |
14968 | exp->X_add_number = 0; | |
14969 | ||
14970 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14971 | } | |
14972 | ||
ecb4347a | 14973 | /* Generate a .pdr section. */ |
f43abd2b | 14974 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14975 | { |
14976 | segT saved_seg = now_seg; | |
14977 | subsegT saved_subseg = now_subseg; | |
14978 | valueT dot; | |
14979 | expressionS exp; | |
14980 | char *fragp; | |
252b5132 | 14981 | |
ecb4347a | 14982 | dot = frag_now_fix (); |
252b5132 RH |
14983 | |
14984 | #ifdef md_flush_pending_output | |
ecb4347a | 14985 | md_flush_pending_output (); |
252b5132 RH |
14986 | #endif |
14987 | ||
9c2799c2 | 14988 | gas_assert (pdr_seg); |
ecb4347a | 14989 | subseg_set (pdr_seg, 0); |
252b5132 | 14990 | |
ecb4347a DJ |
14991 | /* Write the symbol. */ |
14992 | exp.X_op = O_symbol; | |
14993 | exp.X_add_symbol = p; | |
14994 | exp.X_add_number = 0; | |
14995 | emit_expr (&exp, 4); | |
252b5132 | 14996 | |
ecb4347a | 14997 | fragp = frag_more (7 * 4); |
252b5132 | 14998 | |
17a2f251 TS |
14999 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15000 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15001 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15002 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15003 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15004 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15005 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15006 | |
ecb4347a DJ |
15007 | subseg_set (saved_seg, saved_subseg); |
15008 | } | |
15009 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15010 | |
15011 | cur_proc_ptr = NULL; | |
15012 | } | |
15013 | ||
15014 | /* The .aent and .ent directives. */ | |
15015 | ||
15016 | static void | |
17a2f251 | 15017 | s_mips_ent (int aent) |
252b5132 | 15018 | { |
252b5132 | 15019 | symbolS *symbolP; |
252b5132 RH |
15020 | |
15021 | symbolP = get_symbol (); | |
15022 | if (*input_line_pointer == ',') | |
f9419b05 | 15023 | ++input_line_pointer; |
252b5132 | 15024 | SKIP_WHITESPACE (); |
3882b010 | 15025 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15026 | || *input_line_pointer == '-') |
874e8986 | 15027 | get_number (); |
252b5132 | 15028 | |
14949570 | 15029 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15030 | as_warn (_(".ent or .aent not in text section.")); |
15031 | ||
15032 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15033 | as_warn (_("missing .end")); |
252b5132 RH |
15034 | |
15035 | if (!aent) | |
15036 | { | |
7a621144 DJ |
15037 | /* This function needs its own .frame and .cprestore directives. */ |
15038 | mips_frame_reg_valid = 0; | |
15039 | mips_cprestore_valid = 0; | |
15040 | ||
252b5132 RH |
15041 | cur_proc_ptr = &cur_proc; |
15042 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15043 | ||
9b2f1d35 | 15044 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15045 | |
49309057 | 15046 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 15047 | |
f9419b05 | 15048 | ++numprocs; |
ecb4347a DJ |
15049 | |
15050 | if (debug_type == DEBUG_STABS) | |
15051 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15052 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15053 | } |
15054 | ||
15055 | demand_empty_rest_of_line (); | |
15056 | } | |
15057 | ||
15058 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15059 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15060 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15061 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15062 | symbol table (in the mdebug section). */ |
15063 | ||
15064 | static void | |
17a2f251 | 15065 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15066 | { |
ecb4347a | 15067 | #ifdef OBJ_ELF |
f43abd2b | 15068 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15069 | { |
15070 | long val; | |
252b5132 | 15071 | |
ecb4347a DJ |
15072 | if (cur_proc_ptr == (procS *) NULL) |
15073 | { | |
15074 | as_warn (_(".frame outside of .ent")); | |
15075 | demand_empty_rest_of_line (); | |
15076 | return; | |
15077 | } | |
252b5132 | 15078 | |
ecb4347a DJ |
15079 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15080 | ||
15081 | SKIP_WHITESPACE (); | |
15082 | if (*input_line_pointer++ != ',' | |
15083 | || get_absolute_expression_and_terminator (&val) != ',') | |
15084 | { | |
15085 | as_warn (_("Bad .frame directive")); | |
15086 | --input_line_pointer; | |
15087 | demand_empty_rest_of_line (); | |
15088 | return; | |
15089 | } | |
252b5132 | 15090 | |
ecb4347a DJ |
15091 | cur_proc_ptr->frame_offset = val; |
15092 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15093 | |
252b5132 | 15094 | demand_empty_rest_of_line (); |
252b5132 | 15095 | } |
ecb4347a DJ |
15096 | else |
15097 | #endif /* OBJ_ELF */ | |
15098 | s_ignore (ignore); | |
252b5132 RH |
15099 | } |
15100 | ||
bdaaa2e1 KH |
15101 | /* The .fmask and .mask directives. If the mdebug section is present |
15102 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15103 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15104 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15105 | make reference to the ecoff symbol table (in the mdebug section). */ |
15106 | ||
15107 | static void | |
17a2f251 | 15108 | s_mips_mask (int reg_type) |
252b5132 | 15109 | { |
ecb4347a | 15110 | #ifdef OBJ_ELF |
f43abd2b | 15111 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15112 | { |
ecb4347a | 15113 | long mask, off; |
252b5132 | 15114 | |
ecb4347a DJ |
15115 | if (cur_proc_ptr == (procS *) NULL) |
15116 | { | |
15117 | as_warn (_(".mask/.fmask outside of .ent")); | |
15118 | demand_empty_rest_of_line (); | |
15119 | return; | |
15120 | } | |
252b5132 | 15121 | |
ecb4347a DJ |
15122 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15123 | { | |
15124 | as_warn (_("Bad .mask/.fmask directive")); | |
15125 | --input_line_pointer; | |
15126 | demand_empty_rest_of_line (); | |
15127 | return; | |
15128 | } | |
252b5132 | 15129 | |
ecb4347a DJ |
15130 | off = get_absolute_expression (); |
15131 | ||
15132 | if (reg_type == 'F') | |
15133 | { | |
15134 | cur_proc_ptr->fpreg_mask = mask; | |
15135 | cur_proc_ptr->fpreg_offset = off; | |
15136 | } | |
15137 | else | |
15138 | { | |
15139 | cur_proc_ptr->reg_mask = mask; | |
15140 | cur_proc_ptr->reg_offset = off; | |
15141 | } | |
15142 | ||
15143 | demand_empty_rest_of_line (); | |
252b5132 RH |
15144 | } |
15145 | else | |
ecb4347a DJ |
15146 | #endif /* OBJ_ELF */ |
15147 | s_ignore (reg_type); | |
252b5132 RH |
15148 | } |
15149 | ||
316f5878 RS |
15150 | /* A table describing all the processors gas knows about. Names are |
15151 | matched in the order listed. | |
e7af610e | 15152 | |
316f5878 RS |
15153 | To ease comparison, please keep this table in the same order as |
15154 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15155 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15156 | { | |
316f5878 | 15157 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15158 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15159 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15160 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15161 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15162 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15163 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15164 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15165 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15166 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15167 | |
15168 | /* MIPS I */ | |
ad3fea08 TS |
15169 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15170 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15171 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15172 | |
15173 | /* MIPS II */ | |
ad3fea08 | 15174 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15175 | |
15176 | /* MIPS III */ | |
ad3fea08 TS |
15177 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15178 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15179 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15180 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15181 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15182 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15183 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15184 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15185 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15186 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15187 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15188 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15189 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15190 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15191 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15192 | |
15193 | /* MIPS IV */ | |
ad3fea08 TS |
15194 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15195 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15196 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15197 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15198 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15199 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15200 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15201 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15202 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15203 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15204 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15205 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15206 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15207 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15208 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15209 | |
15210 | /* MIPS 32 */ | |
ad3fea08 TS |
15211 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15212 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15213 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15214 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15215 | ||
15216 | /* MIPS 32 Release 2 */ | |
15217 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15218 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15219 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15220 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15221 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15222 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15223 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15224 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15225 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15226 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15227 | /* Deprecated forms of the above. */ | |
15228 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15229 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15230 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15231 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15232 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15233 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15234 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15235 | /* Deprecated forms of the above. */ | |
15236 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15237 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15238 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15239 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15240 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15241 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15242 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15243 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15244 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15245 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15246 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15247 | /* Deprecated forms of the above. */ | |
15248 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15249 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15250 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15251 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15252 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15253 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15254 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15255 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15256 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15257 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15258 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15259 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15260 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15261 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15262 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15263 | /* Deprecated forms of the above. */ | |
15264 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15265 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15266 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15267 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15268 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15269 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15270 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15271 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15272 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15273 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15274 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15275 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15276 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15277 | |
316f5878 | 15278 | /* MIPS 64 */ |
ad3fea08 TS |
15279 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15280 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15281 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15282 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15283 | |
c7a23324 | 15284 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15285 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15286 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15287 | /* Broadcom SB-1A CPU core */ |
15288 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15289 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 15290 | |
ed163775 MR |
15291 | /* MIPS 64 Release 2 */ |
15292 | ||
967344c6 AN |
15293 | /* Cavium Networks Octeon CPU core */ |
15294 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15295 | ||
52b6b6b9 JM |
15296 | /* RMI Xlr */ |
15297 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15298 | ||
316f5878 RS |
15299 | /* End marker */ |
15300 | { NULL, 0, 0, 0 } | |
15301 | }; | |
e7af610e | 15302 | |
84ea6cf2 | 15303 | |
316f5878 RS |
15304 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15305 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15306 | |
316f5878 | 15307 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15308 | |
b34976b6 | 15309 | static bfd_boolean |
17a2f251 | 15310 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15311 | { |
15312 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15313 | given++, canonical++; | |
15314 | ||
15315 | return ((*given == 0 && *canonical == 0) | |
15316 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15317 | } | |
15318 | ||
15319 | ||
15320 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15321 | CPU name. We've traditionally allowed a lot of variation here. | |
15322 | ||
15323 | Note: this function is shared between GCC and GAS. */ | |
15324 | ||
b34976b6 | 15325 | static bfd_boolean |
17a2f251 | 15326 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15327 | { |
15328 | /* First see if the name matches exactly, or with a final "000" | |
15329 | turned into "k". */ | |
15330 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15331 | return TRUE; |
316f5878 RS |
15332 | |
15333 | /* If not, try comparing based on numerical designation alone. | |
15334 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15335 | if (TOLOWER (*given) == 'r') | |
15336 | given++; | |
15337 | if (!ISDIGIT (*given)) | |
b34976b6 | 15338 | return FALSE; |
316f5878 RS |
15339 | |
15340 | /* Skip over some well-known prefixes in the canonical name, | |
15341 | hoping to find a number there too. */ | |
15342 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15343 | canonical += 2; | |
15344 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15345 | canonical += 2; | |
15346 | else if (TOLOWER (canonical[0]) == 'r') | |
15347 | canonical += 1; | |
15348 | ||
15349 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15350 | } | |
15351 | ||
15352 | ||
15353 | /* Parse an option that takes the name of a processor as its argument. | |
15354 | OPTION is the name of the option and CPU_STRING is the argument. | |
15355 | Return the corresponding processor enumeration if the CPU_STRING is | |
15356 | recognized, otherwise report an error and return null. | |
15357 | ||
15358 | A similar function exists in GCC. */ | |
e7af610e NC |
15359 | |
15360 | static const struct mips_cpu_info * | |
17a2f251 | 15361 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15362 | { |
316f5878 | 15363 | const struct mips_cpu_info *p; |
e7af610e | 15364 | |
316f5878 RS |
15365 | /* 'from-abi' selects the most compatible architecture for the given |
15366 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15367 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15368 | version. Look first at the -mgp options, if given, otherwise base | |
15369 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15370 | |
316f5878 RS |
15371 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15372 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15373 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15374 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15375 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15376 | { | |
15377 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15378 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15379 | ||
15380 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15381 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15382 | ||
15383 | if (file_mips_gp32 >= 0) | |
15384 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15385 | ||
15386 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15387 | ? ISA_MIPS3 | |
15388 | : ISA_MIPS1); | |
15389 | } | |
15390 | ||
15391 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15392 | if (strcasecmp (cpu_string, "default") == 0) | |
15393 | return 0; | |
15394 | ||
15395 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15396 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15397 | return p; | |
15398 | ||
20203fb9 | 15399 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15400 | return 0; |
e7af610e NC |
15401 | } |
15402 | ||
316f5878 RS |
15403 | /* Return the canonical processor information for ISA (a member of the |
15404 | ISA_MIPS* enumeration). */ | |
15405 | ||
e7af610e | 15406 | static const struct mips_cpu_info * |
17a2f251 | 15407 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15408 | { |
15409 | int i; | |
15410 | ||
15411 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15412 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15413 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15414 | return (&mips_cpu_info_table[i]); |
15415 | ||
e972090a | 15416 | return NULL; |
e7af610e | 15417 | } |
fef14a42 TS |
15418 | |
15419 | static const struct mips_cpu_info * | |
17a2f251 | 15420 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15421 | { |
15422 | int i; | |
15423 | ||
15424 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15425 | if (arch == mips_cpu_info_table[i].cpu) | |
15426 | return (&mips_cpu_info_table[i]); | |
15427 | ||
15428 | return NULL; | |
15429 | } | |
316f5878 RS |
15430 | \f |
15431 | static void | |
17a2f251 | 15432 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15433 | { |
15434 | if (*first_p) | |
15435 | { | |
15436 | fprintf (stream, "%24s", ""); | |
15437 | *col_p = 24; | |
15438 | } | |
15439 | else | |
15440 | { | |
15441 | fprintf (stream, ", "); | |
15442 | *col_p += 2; | |
15443 | } | |
e7af610e | 15444 | |
316f5878 RS |
15445 | if (*col_p + strlen (string) > 72) |
15446 | { | |
15447 | fprintf (stream, "\n%24s", ""); | |
15448 | *col_p = 24; | |
15449 | } | |
15450 | ||
15451 | fprintf (stream, "%s", string); | |
15452 | *col_p += strlen (string); | |
15453 | ||
15454 | *first_p = 0; | |
15455 | } | |
15456 | ||
15457 | void | |
17a2f251 | 15458 | md_show_usage (FILE *stream) |
e7af610e | 15459 | { |
316f5878 RS |
15460 | int column, first; |
15461 | size_t i; | |
15462 | ||
15463 | fprintf (stream, _("\ | |
15464 | MIPS options:\n\ | |
316f5878 RS |
15465 | -EB generate big endian output\n\ |
15466 | -EL generate little endian output\n\ | |
15467 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15468 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15469 | implicitly with the gp register [default 8]\n")); | |
15470 | fprintf (stream, _("\ | |
15471 | -mips1 generate MIPS ISA I instructions\n\ | |
15472 | -mips2 generate MIPS ISA II instructions\n\ | |
15473 | -mips3 generate MIPS ISA III instructions\n\ | |
15474 | -mips4 generate MIPS ISA IV instructions\n\ | |
15475 | -mips5 generate MIPS ISA V instructions\n\ | |
15476 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15477 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15478 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15479 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15480 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15481 | ||
15482 | first = 1; | |
e7af610e NC |
15483 | |
15484 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15485 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15486 | show (stream, "from-abi", &column, &first); | |
15487 | fputc ('\n', stream); | |
e7af610e | 15488 | |
316f5878 RS |
15489 | fprintf (stream, _("\ |
15490 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15491 | -no-mCPU don't generate code specific to CPU.\n\ | |
15492 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15493 | ||
15494 | first = 1; | |
15495 | ||
15496 | show (stream, "3900", &column, &first); | |
15497 | show (stream, "4010", &column, &first); | |
15498 | show (stream, "4100", &column, &first); | |
15499 | show (stream, "4650", &column, &first); | |
15500 | fputc ('\n', stream); | |
15501 | ||
15502 | fprintf (stream, _("\ | |
15503 | -mips16 generate mips16 instructions\n\ | |
15504 | -no-mips16 do not generate mips16 instructions\n")); | |
15505 | fprintf (stream, _("\ | |
e16bfa71 TS |
15506 | -msmartmips generate smartmips instructions\n\ |
15507 | -mno-smartmips do not generate smartmips instructions\n")); | |
15508 | fprintf (stream, _("\ | |
74cd071d CF |
15509 | -mdsp generate DSP instructions\n\ |
15510 | -mno-dsp do not generate DSP instructions\n")); | |
15511 | fprintf (stream, _("\ | |
8b082fb1 TS |
15512 | -mdspr2 generate DSP R2 instructions\n\ |
15513 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15514 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15515 | -mmt generate MT instructions\n\ |
15516 | -mno-mt do not generate MT instructions\n")); | |
15517 | fprintf (stream, _("\ | |
d766e8ec | 15518 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15519 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15520 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
316f5878 RS |
15521 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15522 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15523 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15524 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15525 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15526 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15527 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15528 | fprintf (stream, _("\ |
15529 | -mhard-float allow floating-point instructions\n\ | |
15530 | -msoft-float do not allow floating-point instructions\n\ | |
15531 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15532 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15533 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15534 | )); | |
316f5878 RS |
15535 | #ifdef OBJ_ELF |
15536 | fprintf (stream, _("\ | |
15537 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15538 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15539 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15540 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15541 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15542 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15543 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15544 | position dependent (non shared) code\n\ |
316f5878 RS |
15545 | -mabi=ABI create ABI conformant object file for:\n")); |
15546 | ||
15547 | first = 1; | |
15548 | ||
15549 | show (stream, "32", &column, &first); | |
15550 | show (stream, "o64", &column, &first); | |
15551 | show (stream, "n32", &column, &first); | |
15552 | show (stream, "64", &column, &first); | |
15553 | show (stream, "eabi", &column, &first); | |
15554 | ||
15555 | fputc ('\n', stream); | |
15556 | ||
15557 | fprintf (stream, _("\ | |
15558 | -32 create o32 ABI object file (default)\n\ | |
15559 | -n32 create n32 ABI object file\n\ | |
15560 | -64 create 64 ABI object file\n")); | |
15561 | #endif | |
e7af610e | 15562 | } |
14e777e0 KB |
15563 | |
15564 | enum dwarf2_format | |
413a266c | 15565 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15566 | { |
369943fe | 15567 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15568 | { |
15569 | #ifdef TE_IRIX | |
15570 | return dwarf2_format_64bit_irix; | |
15571 | #else | |
15572 | return dwarf2_format_64bit; | |
15573 | #endif | |
15574 | } | |
14e777e0 KB |
15575 | else |
15576 | return dwarf2_format_32bit; | |
15577 | } | |
73369e65 EC |
15578 | |
15579 | int | |
15580 | mips_dwarf2_addr_size (void) | |
15581 | { | |
6b6b3450 | 15582 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15583 | return 8; |
73369e65 EC |
15584 | else |
15585 | return 4; | |
15586 | } | |
5862107c EC |
15587 | |
15588 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15589 | void | |
15590 | mips_cfi_frame_initial_instructions (void) | |
15591 | { | |
15592 | cfi_add_CFA_def_cfa_register (SP); | |
15593 | } | |
15594 | ||
707bfff6 TS |
15595 | int |
15596 | tc_mips_regname_to_dw2regnum (char *regname) | |
15597 | { | |
15598 | unsigned int regnum = -1; | |
15599 | unsigned int reg; | |
15600 | ||
15601 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15602 | regnum = reg; | |
15603 | ||
15604 | return regnum; | |
15605 | } |