Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 | 36 | |
42429eac RS |
37 | /* Check assumptions made in this file. */ |
38 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
39 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
40 | ||
252b5132 RH |
41 | #ifdef DEBUG |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
252b5132 | 47 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
48 | static int mips_output_flavor (void); |
49 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
50 | #undef OBJ_PROCESS_STAB |
51 | #undef OUTPUT_FLAVOR | |
52 | #undef S_GET_ALIGN | |
53 | #undef S_GET_SIZE | |
54 | #undef S_SET_ALIGN | |
55 | #undef S_SET_SIZE | |
252b5132 RH |
56 | #undef obj_frob_file |
57 | #undef obj_frob_file_after_relocs | |
58 | #undef obj_frob_symbol | |
59 | #undef obj_pop_insert | |
60 | #undef obj_sec_sym_ok_for_reloc | |
61 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
62 | ||
63 | #include "obj-elf.h" | |
64 | /* Fix any of them that we actually care about. */ | |
65 | #undef OUTPUT_FLAVOR | |
66 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 67 | |
252b5132 | 68 | #include "elf/mips.h" |
252b5132 RH |
69 | |
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
252b5132 | 88 | static char *mips_regmask_frag; |
252b5132 | 89 | |
85b51719 | 90 | #define ZERO 0 |
741fe287 | 91 | #define ATREG 1 |
df58fc94 RS |
92 | #define S0 16 |
93 | #define S7 23 | |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | extern int target_big_endian; |
108 | ||
252b5132 | 109 | /* The name of the readonly data section. */ |
e8044f35 | 110 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 111 | |
a4e06468 RS |
112 | /* Ways in which an instruction can be "appended" to the output. */ |
113 | enum append_method { | |
114 | /* Just add it normally. */ | |
115 | APPEND_ADD, | |
116 | ||
117 | /* Add it normally and then add a nop. */ | |
118 | APPEND_ADD_WITH_NOP, | |
119 | ||
120 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
121 | APPEND_ADD_COMPACT, | |
122 | ||
123 | /* Insert the instruction before the last one. */ | |
124 | APPEND_SWAP | |
125 | }; | |
126 | ||
47e39b9d RS |
127 | /* Information about an instruction, including its format, operands |
128 | and fixups. */ | |
129 | struct mips_cl_insn | |
130 | { | |
131 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
132 | const struct mips_opcode *insn_mo; | |
133 | ||
47e39b9d | 134 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
135 | a copy of INSN_MO->match with the operands filled in. If we have |
136 | decided to use an extended MIPS16 instruction, this includes the | |
137 | extension. */ | |
47e39b9d RS |
138 | unsigned long insn_opcode; |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d | 151 | |
708587a4 | 152 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
153 | unsigned int noreorder_p : 1; |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
157 | |
158 | /* True if this instruction is complete. */ | |
159 | unsigned int complete_p : 1; | |
e407c74b NC |
160 | |
161 | /* True if this instruction is cleared from history by unconditional | |
162 | branch. */ | |
163 | unsigned int cleared_p : 1; | |
47e39b9d RS |
164 | }; |
165 | ||
a325df1d TS |
166 | /* The ABI to use. */ |
167 | enum mips_abi_level | |
168 | { | |
169 | NO_ABI = 0, | |
170 | O32_ABI, | |
171 | O64_ABI, | |
172 | N32_ABI, | |
173 | N64_ABI, | |
174 | EABI_ABI | |
175 | }; | |
176 | ||
177 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 178 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 179 | |
143d77c5 EC |
180 | /* Whether or not we have code that can call pic code. */ |
181 | int mips_abicalls = FALSE; | |
182 | ||
aa6975fb ILT |
183 | /* Whether or not we have code which can be put into a shared |
184 | library. */ | |
185 | static bfd_boolean mips_in_shared = TRUE; | |
186 | ||
252b5132 RH |
187 | /* This is the set of options which may be modified by the .set |
188 | pseudo-op. We use a struct so that .set push and .set pop are more | |
189 | reliable. */ | |
190 | ||
e972090a NC |
191 | struct mips_set_options |
192 | { | |
252b5132 RH |
193 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
194 | if it has not been initialized. Changed by `.set mipsN', and the | |
195 | -mipsN command line option, and the default CPU. */ | |
196 | int isa; | |
846ef2d0 RS |
197 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
198 | <asename>', by command line options, and based on the default | |
199 | architecture. */ | |
200 | int ase; | |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
df58fc94 RS |
206 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
207 | 1 if we are, and -1 if the value has not been initialized. Changed | |
208 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
209 | and -mno-micromips command line options, and the default CPU. */ | |
210 | int micromips; | |
252b5132 RH |
211 | /* Non-zero if we should not reorder instructions. Changed by `.set |
212 | reorder' and `.set noreorder'. */ | |
213 | int noreorder; | |
741fe287 MR |
214 | /* Non-zero if we should not permit the register designated "assembler |
215 | temporary" to be used in instructions. The value is the register | |
216 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
217 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
218 | unsigned int at; | |
252b5132 RH |
219 | /* Non-zero if we should warn when a macro instruction expands into |
220 | more than one machine instruction. Changed by `.set nomacro' and | |
221 | `.set macro'. */ | |
222 | int warn_about_macros; | |
223 | /* Non-zero if we should not move instructions. Changed by `.set | |
224 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
225 | int nomove; | |
226 | /* Non-zero if we should not optimize branches by moving the target | |
227 | of the branch into the delay slot. Actually, we don't perform | |
228 | this optimization anyhow. Changed by `.set bopt' and `.set | |
229 | nobopt'. */ | |
230 | int nobopt; | |
231 | /* Non-zero if we should not autoextend mips16 instructions. | |
232 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
233 | int noautoextend; | |
a325df1d TS |
234 | /* Restrict general purpose registers and floating point registers |
235 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
236 | is passed but can changed if the assembler code uses .set mipsN. */ | |
237 | int gp32; | |
238 | int fp32; | |
fef14a42 TS |
239 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
240 | command line option, and the default CPU. */ | |
241 | int arch; | |
aed1a261 RS |
242 | /* True if ".set sym32" is in effect. */ |
243 | bfd_boolean sym32; | |
037b32b9 AN |
244 | /* True if floating-point operations are not allowed. Changed by .set |
245 | softfloat or .set hardfloat, by command line options -msoft-float or | |
246 | -mhard-float. The default is false. */ | |
247 | bfd_boolean soft_float; | |
248 | ||
249 | /* True if only single-precision floating-point operations are allowed. | |
250 | Changed by .set singlefloat or .set doublefloat, command-line options | |
251 | -msingle-float or -mdouble-float. The default is false. */ | |
252 | bfd_boolean single_float; | |
252b5132 RH |
253 | }; |
254 | ||
037b32b9 AN |
255 | /* This is the struct we use to hold the current set of options. Note |
256 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
257 | -1 to indicate that they have not been initialized. */ | |
258 | ||
a325df1d | 259 | /* True if -mgp32 was passed. */ |
a8e8e863 | 260 | static int file_mips_gp32 = -1; |
a325df1d TS |
261 | |
262 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 263 | static int file_mips_fp32 = -1; |
a325df1d | 264 | |
037b32b9 AN |
265 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
266 | static int file_mips_soft_float = 0; | |
267 | ||
268 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
269 | static int file_mips_single_float = 0; | |
252b5132 | 270 | |
e972090a NC |
271 | static struct mips_set_options mips_opts = |
272 | { | |
846ef2d0 | 273 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 AP |
274 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
275 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
276 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
277 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 278 | }; |
252b5132 | 279 | |
846ef2d0 RS |
280 | /* The set of ASEs that were selected on the command line, either |
281 | explicitly via ASE options or implicitly through things like -march. */ | |
282 | static unsigned int file_ase; | |
283 | ||
284 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
285 | static unsigned int file_ase_explicit; | |
286 | ||
252b5132 RH |
287 | /* These variables are filled in with the masks of registers used. |
288 | The object format code reads them and puts them in the appropriate | |
289 | place. */ | |
290 | unsigned long mips_gprmask; | |
291 | unsigned long mips_cprmask[4]; | |
292 | ||
293 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 294 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 295 | |
738f4d98 | 296 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
297 | static int file_ase_mips16; |
298 | ||
3994f87e TS |
299 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
300 | || mips_opts.isa == ISA_MIPS32R2 \ | |
301 | || mips_opts.isa == ISA_MIPS64 \ | |
302 | || mips_opts.isa == ISA_MIPS64R2) | |
303 | ||
df58fc94 RS |
304 | /* True if any microMIPS code was produced. */ |
305 | static int file_ase_micromips; | |
306 | ||
b12dd2e4 CF |
307 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
308 | #ifdef TE_IRIX | |
1180b5a4 | 309 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 310 | #else |
1180b5a4 RS |
311 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
312 | because there's no place for any addend, the only acceptable | |
313 | expression is a bare symbol. */ | |
314 | #define MIPS_JALR_HINT_P(EXPR) \ | |
315 | (!HAVE_IN_PLACE_ADDENDS \ | |
316 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
317 | #endif |
318 | ||
ec68c924 | 319 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 320 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 321 | static const char *mips_arch_string; |
ec68c924 EC |
322 | |
323 | /* The argument of the -mtune= flag. The architecture for which we | |
324 | are optimizing. */ | |
325 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 326 | static const char *mips_tune_string; |
ec68c924 | 327 | |
316f5878 | 328 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
329 | static int mips_32bitmode = 0; |
330 | ||
316f5878 RS |
331 | /* True if the given ABI requires 32-bit registers. */ |
332 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
333 | ||
334 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
335 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
336 | ((ABI) == N32_ABI \ | |
337 | || (ABI) == N64_ABI \ | |
316f5878 RS |
338 | || (ABI) == O64_ABI) |
339 | ||
ad3fea08 | 340 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
341 | #define ISA_HAS_64BIT_REGS(ISA) \ |
342 | ((ISA) == ISA_MIPS3 \ | |
343 | || (ISA) == ISA_MIPS4 \ | |
344 | || (ISA) == ISA_MIPS5 \ | |
345 | || (ISA) == ISA_MIPS64 \ | |
346 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 347 | |
ad3fea08 TS |
348 | /* Return true if ISA supports 64 bit wide float registers. */ |
349 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
350 | ((ISA) == ISA_MIPS3 \ | |
351 | || (ISA) == ISA_MIPS4 \ | |
352 | || (ISA) == ISA_MIPS5 \ | |
353 | || (ISA) == ISA_MIPS32R2 \ | |
354 | || (ISA) == ISA_MIPS64 \ | |
355 | || (ISA) == ISA_MIPS64R2) | |
356 | ||
af7ee8bf CD |
357 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
358 | instructions. */ | |
707bfff6 | 359 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
360 | ((ISA) == ISA_MIPS64R2 \ |
361 | || (mips_opts.micromips \ | |
362 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
363 | ) | |
af7ee8bf CD |
364 | |
365 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
366 | instructions. */ | |
707bfff6 TS |
367 | #define ISA_HAS_ROR(ISA) \ |
368 | ((ISA) == ISA_MIPS32R2 \ | |
369 | || (ISA) == ISA_MIPS64R2 \ | |
846ef2d0 | 370 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
371 | || mips_opts.micromips \ |
372 | ) | |
707bfff6 | 373 | |
7455baf8 TS |
374 | /* Return true if ISA supports single-precision floats in odd registers. */ |
375 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
376 | ((ISA) == ISA_MIPS32 \ | |
377 | || (ISA) == ISA_MIPS32R2 \ | |
378 | || (ISA) == ISA_MIPS64 \ | |
379 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 380 | |
ad3fea08 TS |
381 | /* Return true if ISA supports move to/from high part of a 64-bit |
382 | floating-point register. */ | |
383 | #define ISA_HAS_MXHC1(ISA) \ | |
384 | ((ISA) == ISA_MIPS32R2 \ | |
385 | || (ISA) == ISA_MIPS64R2) | |
386 | ||
e013f690 | 387 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 388 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 389 | |
e013f690 | 390 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 391 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 392 | |
ad3fea08 TS |
393 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
394 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 395 | |
316f5878 | 396 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 397 | |
316f5878 | 398 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 399 | |
3b91255e RS |
400 | /* True if relocations are stored in-place. */ |
401 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
402 | ||
aed1a261 RS |
403 | /* The ABI-derived address size. */ |
404 | #define HAVE_64BIT_ADDRESSES \ | |
405 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
406 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 407 | |
aed1a261 RS |
408 | /* The size of symbolic constants (i.e., expressions of the form |
409 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
410 | #define HAVE_32BIT_SYMBOLS \ | |
411 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
412 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 413 | |
b7c7d6c1 TS |
414 | /* Addresses are loaded in different ways, depending on the address size |
415 | in use. The n32 ABI Documentation also mandates the use of additions | |
416 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 417 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 418 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
419 | |
420 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 421 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
422 | |
423 | #define ADDRESS_LOAD_INSN \ | |
424 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
425 | ||
426 | #define ADDRESS_STORE_INSN \ | |
427 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
428 | ||
a4672219 | 429 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
430 | #define CPU_HAS_MIPS16(cpu) \ |
431 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
432 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 433 | |
2309ddf2 | 434 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
435 | #define CPU_HAS_MICROMIPS(cpu) 0 |
436 | ||
60b63b72 RS |
437 | /* True if CPU has a dror instruction. */ |
438 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
439 | ||
440 | /* True if CPU has a ror instruction. */ | |
441 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
442 | ||
dd6a37e7 | 443 | /* True if CPU is in the Octeon family */ |
432233b3 | 444 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 445 | |
dd3cbb7e | 446 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 447 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 448 | |
0aa27725 RS |
449 | /* True, if CPU has support for ldc1 and sdc1. */ |
450 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
451 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
452 | ||
c8978940 CD |
453 | /* True if mflo and mfhi can be immediately followed by instructions |
454 | which write to the HI and LO registers. | |
455 | ||
456 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
457 | (at least) two instructions between the reads of HI/LO and | |
458 | instructions which write them, and later ISAs do not. Contradicting | |
459 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
460 | the UM for the NEC Vr5000) document needing the instructions between | |
461 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
462 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
463 | earlier-ISA CPUs for which CPU documentation declares that the | |
464 | instructions are really interlocked. */ | |
465 | #define hilo_interlocks \ | |
466 | (mips_opts.isa == ISA_MIPS32 \ | |
467 | || mips_opts.isa == ISA_MIPS32R2 \ | |
468 | || mips_opts.isa == ISA_MIPS64 \ | |
469 | || mips_opts.isa == ISA_MIPS64R2 \ | |
470 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 471 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
472 | || mips_opts.arch == CPU_R10000 \ |
473 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
474 | || mips_opts.arch == CPU_R14000 \ |
475 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 476 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 477 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 478 | || mips_opts.micromips \ |
c8978940 | 479 | ) |
252b5132 RH |
480 | |
481 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
482 | from the GPRs after they are loaded from memory, and thus does not |
483 | require nops to be inserted. This applies to instructions marked | |
484 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
485 | level I and microMIPS mode instructions are always interlocked. */ |
486 | #define gpr_interlocks \ | |
487 | (mips_opts.isa != ISA_MIPS1 \ | |
488 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 489 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
490 | || mips_opts.micromips \ |
491 | ) | |
252b5132 | 492 | |
81912461 ILT |
493 | /* Whether the processor uses hardware interlocks to avoid delays |
494 | required by coprocessor instructions, and thus does not require | |
495 | nops to be inserted. This applies to instructions marked | |
496 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
497 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
498 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
499 | levels I, II, and III and microMIPS mode instructions are always |
500 | interlocked. */ | |
bdaaa2e1 | 501 | /* Itbl support may require additional care here. */ |
81912461 ILT |
502 | #define cop_interlocks \ |
503 | ((mips_opts.isa != ISA_MIPS1 \ | |
504 | && mips_opts.isa != ISA_MIPS2 \ | |
505 | && mips_opts.isa != ISA_MIPS3) \ | |
506 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 507 | || mips_opts.micromips \ |
81912461 ILT |
508 | ) |
509 | ||
510 | /* Whether the processor uses hardware interlocks to protect reads | |
511 | from coprocessor registers after they are loaded from memory, and | |
512 | thus does not require nops to be inserted. This applies to | |
513 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
514 | requires at MIPS ISA level I and microMIPS mode instructions are |
515 | always interlocked. */ | |
516 | #define cop_mem_interlocks \ | |
517 | (mips_opts.isa != ISA_MIPS1 \ | |
518 | || mips_opts.micromips \ | |
519 | ) | |
252b5132 | 520 | |
6b76fefe CM |
521 | /* Is this a mfhi or mflo instruction? */ |
522 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
523 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
524 | ||
df58fc94 RS |
525 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
526 | has been selected. This implies, in particular, that addresses of text | |
527 | labels have their LSB set. */ | |
528 | #define HAVE_CODE_COMPRESSION \ | |
529 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
530 | ||
42429eac RS |
531 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
532 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1)) | |
533 | #define GPR_SMIN (-GPR_SMAX - 1) | |
534 | ||
252b5132 RH |
535 | /* MIPS PIC level. */ |
536 | ||
a161fe53 | 537 | enum mips_pic_level mips_pic; |
252b5132 | 538 | |
c9914766 | 539 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 540 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 541 | static int mips_big_got = 0; |
252b5132 RH |
542 | |
543 | /* 1 if trap instructions should used for overflow rather than break | |
544 | instructions. */ | |
c9914766 | 545 | static int mips_trap = 0; |
252b5132 | 546 | |
119d663a | 547 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 548 | by assembling two single width halves into two single width floating |
119d663a NC |
549 | point registers which just happen to alias the double width destination |
550 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 551 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
552 | automatically at assemble time. */ |
553 | static int mips_disable_float_construction; | |
554 | ||
252b5132 RH |
555 | /* Non-zero if any .set noreorder directives were used. */ |
556 | ||
557 | static int mips_any_noreorder; | |
558 | ||
6b76fefe CM |
559 | /* Non-zero if nops should be inserted when the register referenced in |
560 | an mfhi/mflo instruction is read in the next two instructions. */ | |
561 | static int mips_7000_hilo_fix; | |
562 | ||
02ffd3e4 | 563 | /* The size of objects in the small data section. */ |
156c2f8b | 564 | static unsigned int g_switch_value = 8; |
252b5132 RH |
565 | /* Whether the -G option was used. */ |
566 | static int g_switch_seen = 0; | |
567 | ||
568 | #define N_RMASK 0xc4 | |
569 | #define N_VFP 0xd4 | |
570 | ||
571 | /* If we can determine in advance that GP optimization won't be | |
572 | possible, we can skip the relaxation stuff that tries to produce | |
573 | GP-relative references. This makes delay slot optimization work | |
574 | better. | |
575 | ||
576 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
577 | gcc output. It needs to guess right for gcc, otherwise gcc |
578 | will put what it thinks is a GP-relative instruction in a branch | |
579 | delay slot. | |
252b5132 RH |
580 | |
581 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
582 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 583 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
584 | |
585 | /* handle of the OPCODE hash table */ | |
586 | static struct hash_control *op_hash = NULL; | |
587 | ||
588 | /* The opcode hash table we use for the mips16. */ | |
589 | static struct hash_control *mips16_op_hash = NULL; | |
590 | ||
df58fc94 RS |
591 | /* The opcode hash table we use for the microMIPS ASE. */ |
592 | static struct hash_control *micromips_op_hash = NULL; | |
593 | ||
252b5132 RH |
594 | /* This array holds the chars that always start a comment. If the |
595 | pre-processor is disabled, these aren't very useful */ | |
596 | const char comment_chars[] = "#"; | |
597 | ||
598 | /* This array holds the chars that only start a comment at the beginning of | |
599 | a line. If the line seems to have the form '# 123 filename' | |
600 | .line and .file directives will appear in the pre-processed output */ | |
601 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
602 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 603 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
604 | /* Also note that C style comments are always supported. */ |
605 | const char line_comment_chars[] = "#"; | |
606 | ||
bdaaa2e1 | 607 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 608 | const char line_separator_chars[] = ";"; |
252b5132 RH |
609 | |
610 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
611 | const char EXP_CHARS[] = "eE"; | |
612 | ||
613 | /* Chars that mean this number is a floating point constant */ | |
614 | /* As in 0f12.456 */ | |
615 | /* or 0d1.2345e12 */ | |
616 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
617 | ||
618 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
619 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
620 | but nothing is ideal around here. | |
621 | */ | |
622 | ||
623 | static char *insn_error; | |
624 | ||
625 | static int auto_align = 1; | |
626 | ||
627 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
628 | offset in the stack frame from which to restore the $gp register. | |
629 | This is set by the .cprestore pseudo-op, and saved in this | |
630 | variable. */ | |
631 | static offsetT mips_cprestore_offset = -1; | |
632 | ||
67c1ffbe | 633 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 634 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 635 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
636 | static offsetT mips_cpreturn_offset = -1; |
637 | static int mips_cpreturn_register = -1; | |
638 | static int mips_gp_register = GP; | |
def2e0dd | 639 | static int mips_gprel_offset = 0; |
6478892d | 640 | |
7a621144 DJ |
641 | /* Whether mips_cprestore_offset has been set in the current function |
642 | (or whether it has already been warned about, if not). */ | |
643 | static int mips_cprestore_valid = 0; | |
644 | ||
252b5132 RH |
645 | /* This is the register which holds the stack frame, as set by the |
646 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
647 | static int mips_frame_reg = SP; | |
648 | ||
7a621144 DJ |
649 | /* Whether mips_frame_reg has been set in the current function |
650 | (or whether it has already been warned about, if not). */ | |
651 | static int mips_frame_reg_valid = 0; | |
652 | ||
252b5132 RH |
653 | /* To output NOP instructions correctly, we need to keep information |
654 | about the previous two instructions. */ | |
655 | ||
656 | /* Whether we are optimizing. The default value of 2 means to remove | |
657 | unneeded NOPs and swap branch instructions when possible. A value | |
658 | of 1 means to not swap branches. A value of 0 means to always | |
659 | insert NOPs. */ | |
660 | static int mips_optimize = 2; | |
661 | ||
662 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
663 | equivalent to seeing no -g option at all. */ | |
664 | static int mips_debug = 0; | |
665 | ||
7d8e00cf RS |
666 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
667 | #define MAX_VR4130_NOPS 4 | |
668 | ||
669 | /* The maximum number of NOPs needed to fill delay slots. */ | |
670 | #define MAX_DELAY_NOPS 2 | |
671 | ||
672 | /* The maximum number of NOPs needed for any purpose. */ | |
673 | #define MAX_NOPS 4 | |
71400594 RS |
674 | |
675 | /* A list of previous instructions, with index 0 being the most recent. | |
676 | We need to look back MAX_NOPS instructions when filling delay slots | |
677 | or working around processor errata. We need to look back one | |
678 | instruction further if we're thinking about using history[0] to | |
679 | fill a branch delay slot. */ | |
680 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 681 | |
1e915849 | 682 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
683 | static struct mips_cl_insn nop_insn; |
684 | static struct mips_cl_insn mips16_nop_insn; | |
685 | static struct mips_cl_insn micromips_nop16_insn; | |
686 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
687 | |
688 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
689 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
690 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
691 | ||
692 | /* The size of NOP_INSN in bytes. */ | |
693 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 694 | |
252b5132 RH |
695 | /* If this is set, it points to a frag holding nop instructions which |
696 | were inserted before the start of a noreorder section. If those | |
697 | nops turn out to be unnecessary, the size of the frag can be | |
698 | decreased. */ | |
699 | static fragS *prev_nop_frag; | |
700 | ||
701 | /* The number of nop instructions we created in prev_nop_frag. */ | |
702 | static int prev_nop_frag_holds; | |
703 | ||
704 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 705 | prev_nop_frag. */ |
252b5132 RH |
706 | static int prev_nop_frag_required; |
707 | ||
708 | /* The number of instructions we've seen since prev_nop_frag. */ | |
709 | static int prev_nop_frag_since; | |
710 | ||
e8044f35 RS |
711 | /* Relocations against symbols are sometimes done in two parts, with a HI |
712 | relocation and a LO relocation. Each relocation has only 16 bits of | |
713 | space to store an addend. This means that in order for the linker to | |
714 | handle carries correctly, it must be able to locate both the HI and | |
715 | the LO relocation. This means that the relocations must appear in | |
716 | order in the relocation table. | |
252b5132 RH |
717 | |
718 | In order to implement this, we keep track of each unmatched HI | |
719 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 720 | corresponding LO relocation. */ |
252b5132 | 721 | |
e972090a NC |
722 | struct mips_hi_fixup |
723 | { | |
252b5132 RH |
724 | /* Next HI fixup. */ |
725 | struct mips_hi_fixup *next; | |
726 | /* This fixup. */ | |
727 | fixS *fixp; | |
728 | /* The section this fixup is in. */ | |
729 | segT seg; | |
730 | }; | |
731 | ||
732 | /* The list of unmatched HI relocs. */ | |
733 | ||
734 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
735 | ||
64bdfcaf RS |
736 | /* The frag containing the last explicit relocation operator. |
737 | Null if explicit relocations have not been used. */ | |
738 | ||
739 | static fragS *prev_reloc_op_frag; | |
740 | ||
252b5132 RH |
741 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
742 | ||
743 | #define X ILLEGAL_REG | |
e972090a NC |
744 | static const int mips32_to_16_reg_map[] = |
745 | { | |
252b5132 RH |
746 | X, X, 2, 3, 4, 5, 6, 7, |
747 | X, X, X, X, X, X, X, X, | |
748 | 0, 1, X, X, X, X, X, X, | |
749 | X, X, X, X, X, X, X, X | |
750 | }; | |
751 | #undef X | |
752 | ||
753 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
754 | ||
e972090a NC |
755 | static const unsigned int mips16_to_32_reg_map[] = |
756 | { | |
252b5132 RH |
757 | 16, 17, 2, 3, 4, 5, 6, 7 |
758 | }; | |
60b63b72 | 759 | |
df58fc94 RS |
760 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
761 | ||
762 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
763 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
764 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
765 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
766 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
767 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
768 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
769 | ||
770 | #define X ILLEGAL_REG | |
771 | /* reg type h: 4, 5, 6. */ | |
772 | static const int mips32_to_micromips_reg_h_map[] = | |
773 | { | |
774 | X, X, X, X, 4, 5, 6, X, | |
775 | X, X, X, X, X, X, X, X, | |
776 | X, X, X, X, X, X, X, X, | |
777 | X, X, X, X, X, X, X, X | |
778 | }; | |
779 | ||
780 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
781 | static const int mips32_to_micromips_reg_m_map[] = | |
782 | { | |
783 | 0, X, 2, 3, X, X, X, X, | |
784 | X, X, X, X, X, X, X, X, | |
785 | 4, 1, 5, 6, 7, X, X, X, | |
786 | X, X, X, X, X, X, X, X | |
787 | }; | |
788 | ||
789 | /* reg type q: 0, 2-7. 17. */ | |
790 | static const int mips32_to_micromips_reg_q_map[] = | |
791 | { | |
792 | 0, X, 2, 3, 4, 5, 6, 7, | |
793 | X, X, X, X, X, X, X, X, | |
794 | X, 1, X, X, X, X, X, X, | |
795 | X, X, X, X, X, X, X, X | |
796 | }; | |
797 | ||
798 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
799 | #undef X | |
800 | ||
801 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
802 | ||
803 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
804 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
805 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
806 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
807 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
808 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
809 | ||
810 | /* The microMIPS registers with type h. */ | |
811 | static const unsigned int micromips_to_32_reg_h_map[] = | |
812 | { | |
813 | 5, 5, 6, 4, 4, 4, 4, 4 | |
814 | }; | |
815 | ||
816 | /* The microMIPS registers with type i. */ | |
817 | static const unsigned int micromips_to_32_reg_i_map[] = | |
818 | { | |
819 | 6, 7, 7, 21, 22, 5, 6, 7 | |
820 | }; | |
821 | ||
822 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
823 | ||
824 | /* The microMIPS registers with type m. */ | |
825 | static const unsigned int micromips_to_32_reg_m_map[] = | |
826 | { | |
827 | 0, 17, 2, 3, 16, 18, 19, 20 | |
828 | }; | |
829 | ||
830 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
831 | ||
832 | /* The microMIPS registers with type q. */ | |
833 | static const unsigned int micromips_to_32_reg_q_map[] = | |
834 | { | |
835 | 0, 17, 2, 3, 4, 5, 6, 7 | |
836 | }; | |
837 | ||
838 | /* microMIPS imm type B. */ | |
839 | static const int micromips_imm_b_map[] = | |
840 | { | |
841 | 1, 4, 8, 12, 16, 20, 24, -1 | |
842 | }; | |
843 | ||
844 | /* microMIPS imm type C. */ | |
845 | static const int micromips_imm_c_map[] = | |
846 | { | |
847 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
848 | }; | |
849 | ||
71400594 RS |
850 | /* Classifies the kind of instructions we're interested in when |
851 | implementing -mfix-vr4120. */ | |
c67a084a NC |
852 | enum fix_vr4120_class |
853 | { | |
71400594 RS |
854 | FIX_VR4120_MACC, |
855 | FIX_VR4120_DMACC, | |
856 | FIX_VR4120_MULT, | |
857 | FIX_VR4120_DMULT, | |
858 | FIX_VR4120_DIV, | |
859 | FIX_VR4120_MTHILO, | |
860 | NUM_FIX_VR4120_CLASSES | |
861 | }; | |
862 | ||
c67a084a NC |
863 | /* ...likewise -mfix-loongson2f-jump. */ |
864 | static bfd_boolean mips_fix_loongson2f_jump; | |
865 | ||
866 | /* ...likewise -mfix-loongson2f-nop. */ | |
867 | static bfd_boolean mips_fix_loongson2f_nop; | |
868 | ||
869 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
870 | static bfd_boolean mips_fix_loongson2f; | |
871 | ||
71400594 RS |
872 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
873 | there must be at least one other instruction between an instruction | |
874 | of type X and an instruction of type Y. */ | |
875 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
876 | ||
877 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 878 | static int mips_fix_vr4120; |
4a6a3df4 | 879 | |
7d8e00cf RS |
880 | /* ...likewise -mfix-vr4130. */ |
881 | static int mips_fix_vr4130; | |
882 | ||
6a32d874 CM |
883 | /* ...likewise -mfix-24k. */ |
884 | static int mips_fix_24k; | |
885 | ||
d954098f DD |
886 | /* ...likewise -mfix-cn63xxp1 */ |
887 | static bfd_boolean mips_fix_cn63xxp1; | |
888 | ||
4a6a3df4 AO |
889 | /* We don't relax branches by default, since this causes us to expand |
890 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
891 | fail to compute the offset before expanding the macro to the most | |
892 | efficient expansion. */ | |
893 | ||
894 | static int mips_relax_branch; | |
252b5132 | 895 | \f |
4d7206a2 RS |
896 | /* The expansion of many macros depends on the type of symbol that |
897 | they refer to. For example, when generating position-dependent code, | |
898 | a macro that refers to a symbol may have two different expansions, | |
899 | one which uses GP-relative addresses and one which uses absolute | |
900 | addresses. When generating SVR4-style PIC, a macro may have | |
901 | different expansions for local and global symbols. | |
902 | ||
903 | We handle these situations by generating both sequences and putting | |
904 | them in variant frags. In position-dependent code, the first sequence | |
905 | will be the GP-relative one and the second sequence will be the | |
906 | absolute one. In SVR4 PIC, the first sequence will be for global | |
907 | symbols and the second will be for local symbols. | |
908 | ||
584892a6 RS |
909 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
910 | SECOND are the lengths of the two sequences in bytes. These fields | |
911 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
912 | the subtype has the following flags: | |
4d7206a2 | 913 | |
584892a6 RS |
914 | RELAX_USE_SECOND |
915 | Set if it has been decided that we should use the second | |
916 | sequence instead of the first. | |
917 | ||
918 | RELAX_SECOND_LONGER | |
919 | Set in the first variant frag if the macro's second implementation | |
920 | is longer than its first. This refers to the macro as a whole, | |
921 | not an individual relaxation. | |
922 | ||
923 | RELAX_NOMACRO | |
924 | Set in the first variant frag if the macro appeared in a .set nomacro | |
925 | block and if one alternative requires a warning but the other does not. | |
926 | ||
927 | RELAX_DELAY_SLOT | |
928 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
929 | delay slot. | |
4d7206a2 | 930 | |
df58fc94 RS |
931 | RELAX_DELAY_SLOT_16BIT |
932 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
933 | 16-bit instruction. | |
934 | ||
935 | RELAX_DELAY_SLOT_SIZE_FIRST | |
936 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
937 | the macro is of the wrong size for the branch delay slot. | |
938 | ||
939 | RELAX_DELAY_SLOT_SIZE_SECOND | |
940 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
941 | the macro is of the wrong size for the branch delay slot. | |
942 | ||
4d7206a2 RS |
943 | The frag's "opcode" points to the first fixup for relaxable code. |
944 | ||
945 | Relaxable macros are generated using a sequence such as: | |
946 | ||
947 | relax_start (SYMBOL); | |
948 | ... generate first expansion ... | |
949 | relax_switch (); | |
950 | ... generate second expansion ... | |
951 | relax_end (); | |
952 | ||
953 | The code and fixups for the unwanted alternative are discarded | |
954 | by md_convert_frag. */ | |
584892a6 | 955 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 956 | |
584892a6 RS |
957 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
958 | #define RELAX_SECOND(X) ((X) & 0xff) | |
959 | #define RELAX_USE_SECOND 0x10000 | |
960 | #define RELAX_SECOND_LONGER 0x20000 | |
961 | #define RELAX_NOMACRO 0x40000 | |
962 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
963 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
964 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
965 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 966 | |
4a6a3df4 AO |
967 | /* Branch without likely bit. If label is out of range, we turn: |
968 | ||
969 | beq reg1, reg2, label | |
970 | delay slot | |
971 | ||
972 | into | |
973 | ||
974 | bne reg1, reg2, 0f | |
975 | nop | |
976 | j label | |
977 | 0: delay slot | |
978 | ||
979 | with the following opcode replacements: | |
980 | ||
981 | beq <-> bne | |
982 | blez <-> bgtz | |
983 | bltz <-> bgez | |
984 | bc1f <-> bc1t | |
985 | ||
986 | bltzal <-> bgezal (with jal label instead of j label) | |
987 | ||
988 | Even though keeping the delay slot instruction in the delay slot of | |
989 | the branch would be more efficient, it would be very tricky to do | |
990 | correctly, because we'd have to introduce a variable frag *after* | |
991 | the delay slot instruction, and expand that instead. Let's do it | |
992 | the easy way for now, even if the branch-not-taken case now costs | |
993 | one additional instruction. Out-of-range branches are not supposed | |
994 | to be common, anyway. | |
995 | ||
996 | Branch likely. If label is out of range, we turn: | |
997 | ||
998 | beql reg1, reg2, label | |
999 | delay slot (annulled if branch not taken) | |
1000 | ||
1001 | into | |
1002 | ||
1003 | beql reg1, reg2, 1f | |
1004 | nop | |
1005 | beql $0, $0, 2f | |
1006 | nop | |
1007 | 1: j[al] label | |
1008 | delay slot (executed only if branch taken) | |
1009 | 2: | |
1010 | ||
1011 | It would be possible to generate a shorter sequence by losing the | |
1012 | likely bit, generating something like: | |
b34976b6 | 1013 | |
4a6a3df4 AO |
1014 | bne reg1, reg2, 0f |
1015 | nop | |
1016 | j[al] label | |
1017 | delay slot (executed only if branch taken) | |
1018 | 0: | |
1019 | ||
1020 | beql -> bne | |
1021 | bnel -> beq | |
1022 | blezl -> bgtz | |
1023 | bgtzl -> blez | |
1024 | bltzl -> bgez | |
1025 | bgezl -> bltz | |
1026 | bc1fl -> bc1t | |
1027 | bc1tl -> bc1f | |
1028 | ||
1029 | bltzall -> bgezal (with jal label instead of j label) | |
1030 | bgezall -> bltzal (ditto) | |
1031 | ||
1032 | ||
1033 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1034 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1035 | ((relax_substateT) \ | |
1036 | (0xc0000000 \ | |
1037 | | ((at) & 0x1f) \ | |
1038 | | ((toofar) ? 0x20 : 0) \ | |
1039 | | ((link) ? 0x40 : 0) \ | |
1040 | | ((likely) ? 0x80 : 0) \ | |
1041 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1042 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1043 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1044 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1045 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1046 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1047 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1048 | |
252b5132 RH |
1049 | /* For mips16 code, we use an entirely different form of relaxation. |
1050 | mips16 supports two versions of most instructions which take | |
1051 | immediate values: a small one which takes some small value, and a | |
1052 | larger one which takes a 16 bit value. Since branches also follow | |
1053 | this pattern, relaxing these values is required. | |
1054 | ||
1055 | We can assemble both mips16 and normal MIPS code in a single | |
1056 | object. Therefore, we need to support this type of relaxation at | |
1057 | the same time that we support the relaxation described above. We | |
1058 | use the high bit of the subtype field to distinguish these cases. | |
1059 | ||
1060 | The information we store for this type of relaxation is the | |
1061 | argument code found in the opcode file for this relocation, whether | |
1062 | the user explicitly requested a small or extended form, and whether | |
1063 | the relocation is in a jump or jal delay slot. That tells us the | |
1064 | size of the value, and how it should be stored. We also store | |
1065 | whether the fragment is considered to be extended or not. We also | |
1066 | store whether this is known to be a branch to a different section, | |
1067 | whether we have tried to relax this frag yet, and whether we have | |
1068 | ever extended a PC relative fragment because of a shift count. */ | |
1069 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1070 | (0x80000000 \ | |
1071 | | ((type) & 0xff) \ | |
1072 | | ((small) ? 0x100 : 0) \ | |
1073 | | ((ext) ? 0x200 : 0) \ | |
1074 | | ((dslot) ? 0x400 : 0) \ | |
1075 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1076 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1077 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1078 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1079 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1080 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1081 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1082 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1083 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1084 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1085 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1086 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1087 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1088 | |
df58fc94 RS |
1089 | /* For microMIPS code, we use relaxation similar to one we use for |
1090 | MIPS16 code. Some instructions that take immediate values support | |
1091 | two encodings: a small one which takes some small value, and a | |
1092 | larger one which takes a 16 bit value. As some branches also follow | |
1093 | this pattern, relaxing these values is required. | |
1094 | ||
1095 | We can assemble both microMIPS and normal MIPS code in a single | |
1096 | object. Therefore, we need to support this type of relaxation at | |
1097 | the same time that we support the relaxation described above. We | |
1098 | use one of the high bits of the subtype field to distinguish these | |
1099 | cases. | |
1100 | ||
1101 | The information we store for this type of relaxation is the argument | |
1102 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1103 | selected as the assembler temporary, whether the branch is |
1104 | unconditional, whether it is compact, whether it stores the link | |
1105 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1106 | branches to a sequence of instructions is enabled, and whether the | |
1107 | displacement of a branch is too large to fit as an immediate argument | |
1108 | of a 16-bit and a 32-bit branch, respectively. */ | |
1109 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1110 | relax32, toofar16, toofar32) \ | |
1111 | (0x40000000 \ | |
1112 | | ((type) & 0xff) \ | |
1113 | | (((at) & 0x1f) << 8) \ | |
1114 | | ((uncond) ? 0x2000 : 0) \ | |
1115 | | ((compact) ? 0x4000 : 0) \ | |
1116 | | ((link) ? 0x8000 : 0) \ | |
1117 | | ((relax32) ? 0x10000 : 0) \ | |
1118 | | ((toofar16) ? 0x20000 : 0) \ | |
1119 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1120 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1121 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1122 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1123 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1124 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1125 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1126 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1127 | ||
1128 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1129 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1130 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1131 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1132 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1133 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1134 | |
43c0598f RS |
1135 | /* Sign-extend 16-bit value X. */ |
1136 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1137 | ||
885add95 CD |
1138 | /* Is the given value a sign-extended 32-bit value? */ |
1139 | #define IS_SEXT_32BIT_NUM(x) \ | |
1140 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1141 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1142 | ||
1143 | /* Is the given value a sign-extended 16-bit value? */ | |
1144 | #define IS_SEXT_16BIT_NUM(x) \ | |
1145 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1146 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1147 | ||
df58fc94 RS |
1148 | /* Is the given value a sign-extended 12-bit value? */ |
1149 | #define IS_SEXT_12BIT_NUM(x) \ | |
1150 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1151 | ||
7f3c4072 CM |
1152 | /* Is the given value a sign-extended 9-bit value? */ |
1153 | #define IS_SEXT_9BIT_NUM(x) \ | |
1154 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1155 | ||
2051e8c4 MR |
1156 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1157 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1158 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1159 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1160 | ||
bf12938e RS |
1161 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1162 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1163 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1164 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1165 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1166 | ||
1167 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1168 | SHIFT places. */ | |
1169 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1170 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1171 | ||
1172 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1173 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1174 | ||
1175 | include/opcode/mips.h specifies operand fields using the macros | |
1176 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1177 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1178 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1179 | do \ | |
1180 | if (!(MICROMIPS)) \ | |
1181 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1182 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1183 | else \ | |
1184 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1185 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1186 | while (0) | |
bf12938e RS |
1187 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1188 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1189 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1190 | ||
1191 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1192 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1193 | (!(MICROMIPS) \ | |
1194 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1195 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1196 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1197 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1198 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1199 | MIPS16OP_MASK_##FIELD, \ | |
1200 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1201 | |
1202 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1203 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1204 | \f |
df58fc94 RS |
1205 | /* Whether or not we are emitting a branch-likely macro. */ |
1206 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1207 | ||
4d7206a2 RS |
1208 | /* Global variables used when generating relaxable macros. See the |
1209 | comment above RELAX_ENCODE for more details about how relaxation | |
1210 | is used. */ | |
1211 | static struct { | |
1212 | /* 0 if we're not emitting a relaxable macro. | |
1213 | 1 if we're emitting the first of the two relaxation alternatives. | |
1214 | 2 if we're emitting the second alternative. */ | |
1215 | int sequence; | |
1216 | ||
1217 | /* The first relaxable fixup in the current frag. (In other words, | |
1218 | the first fixup that refers to relaxable code.) */ | |
1219 | fixS *first_fixup; | |
1220 | ||
1221 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1222 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1223 | unsigned int sizes[2]; | |
1224 | ||
1225 | /* The symbol on which the choice of sequence depends. */ | |
1226 | symbolS *symbol; | |
1227 | } mips_relax; | |
252b5132 | 1228 | \f |
584892a6 RS |
1229 | /* Global variables used to decide whether a macro needs a warning. */ |
1230 | static struct { | |
1231 | /* True if the macro is in a branch delay slot. */ | |
1232 | bfd_boolean delay_slot_p; | |
1233 | ||
df58fc94 RS |
1234 | /* Set to the length in bytes required if the macro is in a delay slot |
1235 | that requires a specific length of instruction, otherwise zero. */ | |
1236 | unsigned int delay_slot_length; | |
1237 | ||
584892a6 RS |
1238 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1239 | in bytes and sizes[1] is the length of the second alternative. | |
1240 | For non-relaxable macros, both elements give the length of the | |
1241 | macro in bytes. */ | |
1242 | unsigned int sizes[2]; | |
1243 | ||
df58fc94 RS |
1244 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1245 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1246 | is the length of the first instruction of the second alternative. | |
1247 | For non-relaxable macros, both elements give the length of the first | |
1248 | instruction in bytes. | |
1249 | ||
1250 | Set to zero if we haven't yet seen the first instruction. */ | |
1251 | unsigned int first_insn_sizes[2]; | |
1252 | ||
1253 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1254 | first alternative and insns[1] is the number of instructions for the | |
1255 | second alternative. | |
1256 | ||
1257 | For non-relaxable macros, both elements give the number of | |
1258 | instructions for the macro. */ | |
1259 | unsigned int insns[2]; | |
1260 | ||
584892a6 RS |
1261 | /* The first variant frag for this macro. */ |
1262 | fragS *first_frag; | |
1263 | } mips_macro_warning; | |
1264 | \f | |
252b5132 RH |
1265 | /* Prototypes for static functions. */ |
1266 | ||
252b5132 RH |
1267 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1268 | ||
b34976b6 | 1269 | static void append_insn |
df58fc94 RS |
1270 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1271 | bfd_boolean expansionp); | |
7d10b47d | 1272 | static void mips_no_prev_insn (void); |
c67a084a | 1273 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1274 | static void mips16_macro_build |
03ea81db | 1275 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1276 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1277 | static void macro_start (void); |
1278 | static void macro_end (void); | |
17a2f251 TS |
1279 | static void macro (struct mips_cl_insn * ip); |
1280 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1281 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1282 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1283 | static void mips16_immed |
43c0598f RS |
1284 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1285 | unsigned int, unsigned long *); | |
5e0116d5 | 1286 | static size_t my_getSmallExpression |
17a2f251 TS |
1287 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1288 | static void my_getExpression (expressionS *, char *); | |
1289 | static void s_align (int); | |
1290 | static void s_change_sec (int); | |
1291 | static void s_change_section (int); | |
1292 | static void s_cons (int); | |
1293 | static void s_float_cons (int); | |
1294 | static void s_mips_globl (int); | |
1295 | static void s_option (int); | |
1296 | static void s_mipsset (int); | |
1297 | static void s_abicalls (int); | |
1298 | static void s_cpload (int); | |
1299 | static void s_cpsetup (int); | |
1300 | static void s_cplocal (int); | |
1301 | static void s_cprestore (int); | |
1302 | static void s_cpreturn (int); | |
741d6ea8 JM |
1303 | static void s_dtprelword (int); |
1304 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1305 | static void s_tprelword (int); |
1306 | static void s_tpreldword (int); | |
17a2f251 TS |
1307 | static void s_gpvalue (int); |
1308 | static void s_gpword (int); | |
1309 | static void s_gpdword (int); | |
a3f278e2 | 1310 | static void s_ehword (int); |
17a2f251 TS |
1311 | static void s_cpadd (int); |
1312 | static void s_insn (int); | |
1313 | static void md_obj_begin (void); | |
1314 | static void md_obj_end (void); | |
1315 | static void s_mips_ent (int); | |
1316 | static void s_mips_end (int); | |
1317 | static void s_mips_frame (int); | |
1318 | static void s_mips_mask (int reg_type); | |
1319 | static void s_mips_stab (int); | |
1320 | static void s_mips_weakext (int); | |
1321 | static void s_mips_file (int); | |
1322 | static void s_mips_loc (int); | |
1323 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1324 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1325 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1326 | static int validate_micromips_insn (const struct mips_opcode *); |
1327 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1328 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1329 | |
1330 | /* Table and functions used to map between CPU/ISA names, and | |
1331 | ISA levels, and CPU numbers. */ | |
1332 | ||
e972090a NC |
1333 | struct mips_cpu_info |
1334 | { | |
e7af610e | 1335 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1336 | int flags; /* MIPS_CPU_* flags. */ |
1337 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1338 | int isa; /* ISA level. */ |
1339 | int cpu; /* CPU number (default CPU if ISA). */ | |
1340 | }; | |
1341 | ||
ad3fea08 | 1342 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1343 | |
17a2f251 TS |
1344 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1345 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1346 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1347 | \f |
c31f3936 RS |
1348 | /* Command-line options. */ |
1349 | const char *md_shortopts = "O::g::G:"; | |
1350 | ||
1351 | enum options | |
1352 | { | |
1353 | OPTION_MARCH = OPTION_MD_BASE, | |
1354 | OPTION_MTUNE, | |
1355 | OPTION_MIPS1, | |
1356 | OPTION_MIPS2, | |
1357 | OPTION_MIPS3, | |
1358 | OPTION_MIPS4, | |
1359 | OPTION_MIPS5, | |
1360 | OPTION_MIPS32, | |
1361 | OPTION_MIPS64, | |
1362 | OPTION_MIPS32R2, | |
1363 | OPTION_MIPS64R2, | |
1364 | OPTION_MIPS16, | |
1365 | OPTION_NO_MIPS16, | |
1366 | OPTION_MIPS3D, | |
1367 | OPTION_NO_MIPS3D, | |
1368 | OPTION_MDMX, | |
1369 | OPTION_NO_MDMX, | |
1370 | OPTION_DSP, | |
1371 | OPTION_NO_DSP, | |
1372 | OPTION_MT, | |
1373 | OPTION_NO_MT, | |
1374 | OPTION_VIRT, | |
1375 | OPTION_NO_VIRT, | |
1376 | OPTION_SMARTMIPS, | |
1377 | OPTION_NO_SMARTMIPS, | |
1378 | OPTION_DSPR2, | |
1379 | OPTION_NO_DSPR2, | |
1380 | OPTION_EVA, | |
1381 | OPTION_NO_EVA, | |
1382 | OPTION_MICROMIPS, | |
1383 | OPTION_NO_MICROMIPS, | |
1384 | OPTION_MCU, | |
1385 | OPTION_NO_MCU, | |
1386 | OPTION_COMPAT_ARCH_BASE, | |
1387 | OPTION_M4650, | |
1388 | OPTION_NO_M4650, | |
1389 | OPTION_M4010, | |
1390 | OPTION_NO_M4010, | |
1391 | OPTION_M4100, | |
1392 | OPTION_NO_M4100, | |
1393 | OPTION_M3900, | |
1394 | OPTION_NO_M3900, | |
1395 | OPTION_M7000_HILO_FIX, | |
1396 | OPTION_MNO_7000_HILO_FIX, | |
1397 | OPTION_FIX_24K, | |
1398 | OPTION_NO_FIX_24K, | |
1399 | OPTION_FIX_LOONGSON2F_JUMP, | |
1400 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1401 | OPTION_FIX_LOONGSON2F_NOP, | |
1402 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1403 | OPTION_FIX_VR4120, | |
1404 | OPTION_NO_FIX_VR4120, | |
1405 | OPTION_FIX_VR4130, | |
1406 | OPTION_NO_FIX_VR4130, | |
1407 | OPTION_FIX_CN63XXP1, | |
1408 | OPTION_NO_FIX_CN63XXP1, | |
1409 | OPTION_TRAP, | |
1410 | OPTION_BREAK, | |
1411 | OPTION_EB, | |
1412 | OPTION_EL, | |
1413 | OPTION_FP32, | |
1414 | OPTION_GP32, | |
1415 | OPTION_CONSTRUCT_FLOATS, | |
1416 | OPTION_NO_CONSTRUCT_FLOATS, | |
1417 | OPTION_FP64, | |
1418 | OPTION_GP64, | |
1419 | OPTION_RELAX_BRANCH, | |
1420 | OPTION_NO_RELAX_BRANCH, | |
1421 | OPTION_MSHARED, | |
1422 | OPTION_MNO_SHARED, | |
1423 | OPTION_MSYM32, | |
1424 | OPTION_MNO_SYM32, | |
1425 | OPTION_SOFT_FLOAT, | |
1426 | OPTION_HARD_FLOAT, | |
1427 | OPTION_SINGLE_FLOAT, | |
1428 | OPTION_DOUBLE_FLOAT, | |
1429 | OPTION_32, | |
c31f3936 RS |
1430 | OPTION_CALL_SHARED, |
1431 | OPTION_CALL_NONPIC, | |
1432 | OPTION_NON_SHARED, | |
1433 | OPTION_XGOT, | |
1434 | OPTION_MABI, | |
1435 | OPTION_N32, | |
1436 | OPTION_64, | |
1437 | OPTION_MDEBUG, | |
1438 | OPTION_NO_MDEBUG, | |
1439 | OPTION_PDR, | |
1440 | OPTION_NO_PDR, | |
1441 | OPTION_MVXWORKS_PIC, | |
c31f3936 RS |
1442 | OPTION_END_OF_ENUM |
1443 | }; | |
1444 | ||
1445 | struct option md_longopts[] = | |
1446 | { | |
1447 | /* Options which specify architecture. */ | |
1448 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1449 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1450 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1451 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1452 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1453 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1454 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1455 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1456 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1457 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1458 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
1459 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
1460 | ||
1461 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1462 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1463 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1464 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1465 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1466 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1467 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1468 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1469 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1470 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1471 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1472 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1473 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1474 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1475 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1476 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1477 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1478 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1479 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1480 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1481 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1482 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1483 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
1484 | ||
1485 | /* Old-style architecture options. Don't add more of these. */ | |
1486 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1487 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1488 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1489 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1490 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1491 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1492 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1493 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1494 | ||
1495 | /* Options which enable bug fixes. */ | |
1496 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1497 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1498 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1499 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1500 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1501 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1502 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1503 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1504 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1505 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1506 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1507 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1508 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
1509 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, | |
1510 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1511 | ||
1512 | /* Miscellaneous options. */ | |
1513 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1514 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1515 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1516 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1517 | {"EB", no_argument, NULL, OPTION_EB}, | |
1518 | {"EL", no_argument, NULL, OPTION_EL}, | |
1519 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1520 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1521 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1522 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1523 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1524 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1525 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1526 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
1527 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
1528 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1529 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1530 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1531 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1532 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1533 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1534 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1535 | ||
1536 | /* Strictly speaking this next option is ELF specific, | |
1537 | but we allow it for other ports as well in order to | |
1538 | make testing easier. */ | |
1539 | {"32", no_argument, NULL, OPTION_32}, | |
1540 | ||
1541 | /* ELF-specific options. */ | |
c31f3936 RS |
1542 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1543 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1544 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1545 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1546 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1547 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1548 | {"n32", no_argument, NULL, OPTION_N32}, | |
1549 | {"64", no_argument, NULL, OPTION_64}, | |
1550 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1551 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1552 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1553 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1554 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
c31f3936 RS |
1555 | |
1556 | {NULL, no_argument, NULL, 0} | |
1557 | }; | |
1558 | size_t md_longopts_size = sizeof (md_longopts); | |
1559 | \f | |
c6278170 RS |
1560 | /* Information about either an Application Specific Extension or an |
1561 | optional architecture feature that, for simplicity, we treat in the | |
1562 | same way as an ASE. */ | |
1563 | struct mips_ase | |
1564 | { | |
1565 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1566 | const char *name; | |
1567 | ||
1568 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1569 | and 64-bit architectures, the flags here refer to the subset that | |
1570 | is available on both. */ | |
1571 | unsigned int flags; | |
1572 | ||
1573 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1574 | architectures but that are not included in FLAGS. */ | |
1575 | unsigned int flags64; | |
1576 | ||
1577 | /* The command-line options that turn the ASE on and off. */ | |
1578 | int option_on; | |
1579 | int option_off; | |
1580 | ||
1581 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1582 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1583 | int mips32_rev; | |
1584 | int mips64_rev; | |
1585 | int micromips32_rev; | |
1586 | int micromips64_rev; | |
1587 | }; | |
1588 | ||
1589 | /* A table of all supported ASEs. */ | |
1590 | static const struct mips_ase mips_ases[] = { | |
1591 | { "dsp", ASE_DSP, ASE_DSP64, | |
1592 | OPTION_DSP, OPTION_NO_DSP, | |
1593 | 2, 2, 2, 2 }, | |
1594 | ||
1595 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1596 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
1597 | 2, 2, 2, 2 }, | |
1598 | ||
1599 | { "eva", ASE_EVA, 0, | |
1600 | OPTION_EVA, OPTION_NO_EVA, | |
1601 | 2, 2, 2, 2 }, | |
1602 | ||
1603 | { "mcu", ASE_MCU, 0, | |
1604 | OPTION_MCU, OPTION_NO_MCU, | |
1605 | 2, 2, 2, 2 }, | |
1606 | ||
1607 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1608 | { "mdmx", ASE_MDMX, 0, | |
1609 | OPTION_MDMX, OPTION_NO_MDMX, | |
1610 | -1, 1, -1, -1 }, | |
1611 | ||
1612 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1613 | { "mips3d", ASE_MIPS3D, 0, | |
1614 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
1615 | 2, 1, -1, -1 }, | |
1616 | ||
1617 | { "mt", ASE_MT, 0, | |
1618 | OPTION_MT, OPTION_NO_MT, | |
1619 | 2, 2, -1, -1 }, | |
1620 | ||
1621 | { "smartmips", ASE_SMARTMIPS, 0, | |
1622 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
1623 | 1, -1, -1, -1 }, | |
1624 | ||
1625 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1626 | OPTION_VIRT, OPTION_NO_VIRT, | |
1627 | 2, 2, 2, 2 } | |
1628 | }; | |
1629 | ||
1630 | /* The set of ASEs that require -mfp64. */ | |
1631 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX) | |
1632 | ||
1633 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1634 | static const unsigned int mips_ase_groups[] = { | |
1635 | ASE_DSP | ASE_DSPR2 | |
1636 | }; | |
1637 | \f | |
252b5132 RH |
1638 | /* Pseudo-op table. |
1639 | ||
1640 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1641 | should be defined here, but are currently unsupported: .alias, | |
1642 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1643 | ||
1644 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1645 | specific to the type of debugging information being generated, and | |
1646 | should be defined by the object format: .aent, .begin, .bend, | |
1647 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1648 | .vreg. | |
1649 | ||
1650 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1651 | not MIPS CPU specific, but are also not specific to the object file | |
1652 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1653 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1654 | |
e972090a NC |
1655 | static const pseudo_typeS mips_pseudo_table[] = |
1656 | { | |
beae10d5 | 1657 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1658 | {"option", s_option, 0}, |
1659 | {"set", s_mipsset, 0}, | |
1660 | {"rdata", s_change_sec, 'r'}, | |
1661 | {"sdata", s_change_sec, 's'}, | |
1662 | {"livereg", s_ignore, 0}, | |
1663 | {"abicalls", s_abicalls, 0}, | |
1664 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1665 | {"cpsetup", s_cpsetup, 0}, |
1666 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1667 | {"cprestore", s_cprestore, 0}, |
6478892d | 1668 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1669 | {"dtprelword", s_dtprelword, 0}, |
1670 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1671 | {"tprelword", s_tprelword, 0}, |
1672 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1673 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1674 | {"gpword", s_gpword, 0}, |
10181a0d | 1675 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1676 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1677 | {"cpadd", s_cpadd, 0}, |
1678 | {"insn", s_insn, 0}, | |
1679 | ||
beae10d5 | 1680 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1681 | chips. */ |
38a57ae7 | 1682 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1683 | {"bss", s_change_sec, 'b'}, |
1684 | {"err", s_err, 0}, | |
1685 | {"half", s_cons, 1}, | |
1686 | {"dword", s_cons, 3}, | |
1687 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1688 | {"origin", s_org, 0}, |
1689 | {"repeat", s_rept, 0}, | |
252b5132 | 1690 | |
998b3c36 MR |
1691 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1692 | {"sbss", s_change_sec, 'B'}, | |
1693 | ||
beae10d5 | 1694 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1695 | here for one reason or another. */ |
1696 | {"align", s_align, 0}, | |
1697 | {"byte", s_cons, 0}, | |
1698 | {"data", s_change_sec, 'd'}, | |
1699 | {"double", s_float_cons, 'd'}, | |
1700 | {"float", s_float_cons, 'f'}, | |
1701 | {"globl", s_mips_globl, 0}, | |
1702 | {"global", s_mips_globl, 0}, | |
1703 | {"hword", s_cons, 1}, | |
1704 | {"int", s_cons, 2}, | |
1705 | {"long", s_cons, 2}, | |
1706 | {"octa", s_cons, 4}, | |
1707 | {"quad", s_cons, 3}, | |
cca86cc8 | 1708 | {"section", s_change_section, 0}, |
252b5132 RH |
1709 | {"short", s_cons, 1}, |
1710 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1711 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1712 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1713 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1714 | {"text", s_change_sec, 't'}, |
1715 | {"word", s_cons, 2}, | |
add56521 | 1716 | |
add56521 | 1717 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1718 | |
43841e91 | 1719 | { NULL, NULL, 0 }, |
252b5132 RH |
1720 | }; |
1721 | ||
e972090a NC |
1722 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1723 | { | |
beae10d5 KH |
1724 | /* These pseudo-ops should be defined by the object file format. |
1725 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1726 | {"aent", s_mips_ent, 1}, |
1727 | {"bgnb", s_ignore, 0}, | |
1728 | {"end", s_mips_end, 0}, | |
1729 | {"endb", s_ignore, 0}, | |
1730 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1731 | {"file", s_mips_file, 0}, |
252b5132 RH |
1732 | {"fmask", s_mips_mask, 'F'}, |
1733 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1734 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1735 | {"mask", s_mips_mask, 'R'}, |
1736 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1737 | { NULL, NULL, 0 }, |
252b5132 RH |
1738 | }; |
1739 | ||
3ae8dd8d MR |
1740 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1741 | purpose of the `.dc.a' internal pseudo-op. */ | |
1742 | ||
1743 | int | |
1744 | mips_address_bytes (void) | |
1745 | { | |
1746 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1747 | } | |
1748 | ||
17a2f251 | 1749 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1750 | |
1751 | void | |
17a2f251 | 1752 | mips_pop_insert (void) |
252b5132 RH |
1753 | { |
1754 | pop_insert (mips_pseudo_table); | |
1755 | if (! ECOFF_DEBUGGING) | |
1756 | pop_insert (mips_nonecoff_pseudo_table); | |
1757 | } | |
1758 | \f | |
1759 | /* Symbols labelling the current insn. */ | |
1760 | ||
e972090a NC |
1761 | struct insn_label_list |
1762 | { | |
252b5132 RH |
1763 | struct insn_label_list *next; |
1764 | symbolS *label; | |
1765 | }; | |
1766 | ||
252b5132 | 1767 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1768 | #define label_list tc_segment_info_data.labels |
252b5132 | 1769 | |
17a2f251 | 1770 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1771 | static void mips_mark_labels (void); |
1772 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1773 | |
1774 | static inline void | |
17a2f251 | 1775 | mips_clear_insn_labels (void) |
252b5132 RH |
1776 | { |
1777 | register struct insn_label_list **pl; | |
a8dbcb85 | 1778 | segment_info_type *si; |
252b5132 | 1779 | |
a8dbcb85 TS |
1780 | if (now_seg) |
1781 | { | |
1782 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1783 | ; | |
1784 | ||
1785 | si = seg_info (now_seg); | |
1786 | *pl = si->label_list; | |
1787 | si->label_list = NULL; | |
1788 | } | |
252b5132 | 1789 | } |
a8dbcb85 | 1790 | |
df58fc94 RS |
1791 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1792 | ||
1793 | static inline void | |
1794 | mips_mark_labels (void) | |
1795 | { | |
1796 | if (HAVE_CODE_COMPRESSION) | |
1797 | mips_compressed_mark_labels (); | |
1798 | } | |
252b5132 RH |
1799 | \f |
1800 | static char *expr_end; | |
1801 | ||
1802 | /* Expressions which appear in instructions. These are set by | |
1803 | mips_ip. */ | |
1804 | ||
1805 | static expressionS imm_expr; | |
5f74bc13 | 1806 | static expressionS imm2_expr; |
252b5132 RH |
1807 | static expressionS offset_expr; |
1808 | ||
1809 | /* Relocs associated with imm_expr and offset_expr. */ | |
1810 | ||
f6688943 TS |
1811 | static bfd_reloc_code_real_type imm_reloc[3] |
1812 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1813 | static bfd_reloc_code_real_type offset_reloc[3] | |
1814 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1815 | |
df58fc94 RS |
1816 | /* This is set to the resulting size of the instruction to be produced |
1817 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1818 | explicit size is supplied. */ | |
252b5132 | 1819 | |
df58fc94 | 1820 | static unsigned int forced_insn_length; |
252b5132 | 1821 | |
e1b47bd5 RS |
1822 | /* True if we are assembling an instruction. All dot symbols defined during |
1823 | this time should be treated as code labels. */ | |
1824 | ||
1825 | static bfd_boolean mips_assembling_insn; | |
1826 | ||
ecb4347a DJ |
1827 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1828 | ECOFF debugging. */ | |
252b5132 RH |
1829 | |
1830 | static segT pdr_seg; | |
252b5132 | 1831 | |
e013f690 TS |
1832 | /* The default target format to use. */ |
1833 | ||
aeffff67 RS |
1834 | #if defined (TE_FreeBSD) |
1835 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1836 | #elif defined (TE_TMIPS) | |
1837 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1838 | #else | |
1839 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1840 | #endif | |
1841 | ||
e013f690 | 1842 | const char * |
17a2f251 | 1843 | mips_target_format (void) |
e013f690 TS |
1844 | { |
1845 | switch (OUTPUT_FLAVOR) | |
1846 | { | |
e013f690 | 1847 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1848 | #ifdef TE_VXWORKS |
1849 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1850 | return (target_big_endian | |
1851 | ? "elf32-bigmips-vxworks" | |
1852 | : "elf32-littlemips-vxworks"); | |
1853 | #endif | |
e013f690 | 1854 | return (target_big_endian |
cfe86eaa | 1855 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1856 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1857 | : (HAVE_NEWABI |
aeffff67 RS |
1858 | ? ELF_TARGET ("elf32-n", "big") |
1859 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1860 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1861 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1862 | : (HAVE_NEWABI |
aeffff67 RS |
1863 | ? ELF_TARGET ("elf32-n", "little") |
1864 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1865 | default: |
1866 | abort (); | |
1867 | return NULL; | |
1868 | } | |
1869 | } | |
1870 | ||
c6278170 RS |
1871 | /* Return the ISA revision that is currently in use, or 0 if we are |
1872 | generating code for MIPS V or below. */ | |
1873 | ||
1874 | static int | |
1875 | mips_isa_rev (void) | |
1876 | { | |
1877 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1878 | return 2; | |
1879 | ||
1880 | /* microMIPS implies revision 2 or above. */ | |
1881 | if (mips_opts.micromips) | |
1882 | return 2; | |
1883 | ||
1884 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1885 | return 1; | |
1886 | ||
1887 | return 0; | |
1888 | } | |
1889 | ||
1890 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1891 | ||
1892 | static unsigned int | |
1893 | mips_ase_mask (unsigned int flags) | |
1894 | { | |
1895 | unsigned int i; | |
1896 | ||
1897 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1898 | if (flags & mips_ase_groups[i]) | |
1899 | flags |= mips_ase_groups[i]; | |
1900 | return flags; | |
1901 | } | |
1902 | ||
1903 | /* Check whether the current ISA supports ASE. Issue a warning if | |
1904 | appropriate. */ | |
1905 | ||
1906 | static void | |
1907 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
1908 | { | |
1909 | const char *base; | |
1910 | int min_rev, size; | |
1911 | static unsigned int warned_isa; | |
1912 | static unsigned int warned_fp32; | |
1913 | ||
1914 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1915 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
1916 | else | |
1917 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
1918 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
1919 | && (warned_isa & ase->flags) != ase->flags) | |
1920 | { | |
1921 | warned_isa |= ase->flags; | |
1922 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
1923 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
1924 | if (min_rev < 0) | |
1925 | as_warn (_("The %d-bit %s architecture does not support the" | |
1926 | " `%s' extension"), size, base, ase->name); | |
1927 | else | |
1928 | as_warn (_("The `%s' extension requires %s%d revision %d or greater"), | |
1929 | ase->name, base, size, min_rev); | |
1930 | } | |
1931 | if ((ase->flags & FP64_ASES) | |
1932 | && mips_opts.fp32 | |
1933 | && (warned_fp32 & ase->flags) != ase->flags) | |
1934 | { | |
1935 | warned_fp32 |= ase->flags; | |
1936 | as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name); | |
1937 | } | |
1938 | } | |
1939 | ||
1940 | /* Check all enabled ASEs to see whether they are supported by the | |
1941 | chosen architecture. */ | |
1942 | ||
1943 | static void | |
1944 | mips_check_isa_supports_ases (void) | |
1945 | { | |
1946 | unsigned int i, mask; | |
1947 | ||
1948 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1949 | { | |
1950 | mask = mips_ase_mask (mips_ases[i].flags); | |
1951 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
1952 | mips_check_isa_supports_ase (&mips_ases[i]); | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
1957 | that were affected. */ | |
1958 | ||
1959 | static unsigned int | |
1960 | mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) | |
1961 | { | |
1962 | unsigned int mask; | |
1963 | ||
1964 | mask = mips_ase_mask (ase->flags); | |
1965 | mips_opts.ase &= ~mask; | |
1966 | if (enabled_p) | |
1967 | mips_opts.ase |= ase->flags; | |
1968 | return mask; | |
1969 | } | |
1970 | ||
1971 | /* Return the ASE called NAME, or null if none. */ | |
1972 | ||
1973 | static const struct mips_ase * | |
1974 | mips_lookup_ase (const char *name) | |
1975 | { | |
1976 | unsigned int i; | |
1977 | ||
1978 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1979 | if (strcmp (name, mips_ases[i].name) == 0) | |
1980 | return &mips_ases[i]; | |
1981 | return NULL; | |
1982 | } | |
1983 | ||
df58fc94 RS |
1984 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1985 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1986 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1987 | major opcode) will require further modifications to the opcode | |
1988 | table. */ | |
1989 | ||
1990 | static inline unsigned int | |
1991 | micromips_insn_length (const struct mips_opcode *mo) | |
1992 | { | |
1993 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1994 | } | |
1995 | ||
5c04167a RS |
1996 | /* Return the length of MIPS16 instruction OPCODE. */ |
1997 | ||
1998 | static inline unsigned int | |
1999 | mips16_opcode_length (unsigned long opcode) | |
2000 | { | |
2001 | return (opcode >> 16) == 0 ? 2 : 4; | |
2002 | } | |
2003 | ||
1e915849 RS |
2004 | /* Return the length of instruction INSN. */ |
2005 | ||
2006 | static inline unsigned int | |
2007 | insn_length (const struct mips_cl_insn *insn) | |
2008 | { | |
df58fc94 RS |
2009 | if (mips_opts.micromips) |
2010 | return micromips_insn_length (insn->insn_mo); | |
2011 | else if (mips_opts.mips16) | |
5c04167a | 2012 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2013 | else |
1e915849 | 2014 | return 4; |
1e915849 RS |
2015 | } |
2016 | ||
2017 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2018 | ||
2019 | static void | |
2020 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2021 | { | |
2022 | size_t i; | |
2023 | ||
2024 | insn->insn_mo = mo; | |
1e915849 RS |
2025 | insn->insn_opcode = mo->match; |
2026 | insn->frag = NULL; | |
2027 | insn->where = 0; | |
2028 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2029 | insn->fixp[i] = NULL; | |
2030 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2031 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2032 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2033 | insn->complete_p = 0; |
e407c74b | 2034 | insn->cleared_p = 0; |
1e915849 RS |
2035 | } |
2036 | ||
df58fc94 | 2037 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2038 | |
2039 | static void | |
df58fc94 | 2040 | mips_record_compressed_mode (void) |
742a56fe RS |
2041 | { |
2042 | segment_info_type *si; | |
2043 | ||
2044 | si = seg_info (now_seg); | |
2045 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2046 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2047 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2048 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2049 | } |
2050 | ||
4d68580a RS |
2051 | /* Read a standard MIPS instruction from BUF. */ |
2052 | ||
2053 | static unsigned long | |
2054 | read_insn (char *buf) | |
2055 | { | |
2056 | if (target_big_endian) | |
2057 | return bfd_getb32 ((bfd_byte *) buf); | |
2058 | else | |
2059 | return bfd_getl32 ((bfd_byte *) buf); | |
2060 | } | |
2061 | ||
2062 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2063 | the next byte. */ | |
2064 | ||
2065 | static char * | |
2066 | write_insn (char *buf, unsigned int insn) | |
2067 | { | |
2068 | md_number_to_chars (buf, insn, 4); | |
2069 | return buf + 4; | |
2070 | } | |
2071 | ||
2072 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2073 | has length LENGTH. */ | |
2074 | ||
2075 | static unsigned long | |
2076 | read_compressed_insn (char *buf, unsigned int length) | |
2077 | { | |
2078 | unsigned long insn; | |
2079 | unsigned int i; | |
2080 | ||
2081 | insn = 0; | |
2082 | for (i = 0; i < length; i += 2) | |
2083 | { | |
2084 | insn <<= 16; | |
2085 | if (target_big_endian) | |
2086 | insn |= bfd_getb16 ((char *) buf); | |
2087 | else | |
2088 | insn |= bfd_getl16 ((char *) buf); | |
2089 | buf += 2; | |
2090 | } | |
2091 | return insn; | |
2092 | } | |
2093 | ||
5c04167a RS |
2094 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2095 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2096 | ||
2097 | static char * | |
2098 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2099 | { | |
2100 | unsigned int i; | |
2101 | ||
2102 | for (i = 0; i < length; i += 2) | |
2103 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2104 | return buf + length; | |
2105 | } | |
2106 | ||
1e915849 RS |
2107 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2108 | ||
2109 | static void | |
2110 | install_insn (const struct mips_cl_insn *insn) | |
2111 | { | |
2112 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2113 | if (HAVE_CODE_COMPRESSION) |
2114 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2115 | else |
4d68580a | 2116 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2117 | mips_record_compressed_mode (); |
1e915849 RS |
2118 | } |
2119 | ||
2120 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2121 | and install the opcode in the new location. */ | |
2122 | ||
2123 | static void | |
2124 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2125 | { | |
2126 | size_t i; | |
2127 | ||
2128 | insn->frag = frag; | |
2129 | insn->where = where; | |
2130 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2131 | if (insn->fixp[i] != NULL) | |
2132 | { | |
2133 | insn->fixp[i]->fx_frag = frag; | |
2134 | insn->fixp[i]->fx_where = where; | |
2135 | } | |
2136 | install_insn (insn); | |
2137 | } | |
2138 | ||
2139 | /* Add INSN to the end of the output. */ | |
2140 | ||
2141 | static void | |
2142 | add_fixed_insn (struct mips_cl_insn *insn) | |
2143 | { | |
2144 | char *f = frag_more (insn_length (insn)); | |
2145 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2146 | } | |
2147 | ||
2148 | /* Start a variant frag and move INSN to the start of the variant part, | |
2149 | marking it as fixed. The other arguments are as for frag_var. */ | |
2150 | ||
2151 | static void | |
2152 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2153 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2154 | { | |
2155 | frag_grow (max_chars); | |
2156 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2157 | insn->fixed_p = 1; | |
2158 | frag_var (rs_machine_dependent, max_chars, var, | |
2159 | subtype, symbol, offset, NULL); | |
2160 | } | |
2161 | ||
2162 | /* Insert N copies of INSN into the history buffer, starting at | |
2163 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2164 | ||
2165 | static void | |
2166 | insert_into_history (unsigned int first, unsigned int n, | |
2167 | const struct mips_cl_insn *insn) | |
2168 | { | |
2169 | if (mips_relax.sequence != 2) | |
2170 | { | |
2171 | unsigned int i; | |
2172 | ||
2173 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2174 | if (i >= first + n) | |
2175 | history[i] = history[i - n]; | |
2176 | else | |
2177 | history[i] = *insn; | |
2178 | } | |
2179 | } | |
2180 | ||
71400594 RS |
2181 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2182 | the idea is to make it obvious at a glance that each errata is | |
2183 | included. */ | |
2184 | ||
2185 | static void | |
2186 | init_vr4120_conflicts (void) | |
2187 | { | |
2188 | #define CONFLICT(FIRST, SECOND) \ | |
2189 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2190 | ||
2191 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2192 | CONFLICT (MACC, DIV); | |
2193 | CONFLICT (DMACC, DIV); | |
2194 | ||
2195 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2196 | CONFLICT (DMULT, DMULT); | |
2197 | CONFLICT (DMULT, DMACC); | |
2198 | CONFLICT (DMACC, DMULT); | |
2199 | CONFLICT (DMACC, DMACC); | |
2200 | ||
2201 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2202 | CONFLICT (MACC, MTHILO); | |
2203 | CONFLICT (DMACC, MTHILO); | |
2204 | ||
2205 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2206 | instruction is executed immediately after a MACC or DMACC | |
2207 | instruction, the result of [either instruction] is incorrect." */ | |
2208 | CONFLICT (MACC, MULT); | |
2209 | CONFLICT (MACC, DMULT); | |
2210 | CONFLICT (DMACC, MULT); | |
2211 | CONFLICT (DMACC, DMULT); | |
2212 | ||
2213 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2214 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2215 | DDIV or DDIVU instruction, the result of the MACC or | |
2216 | DMACC instruction is incorrect.". */ | |
2217 | CONFLICT (DMULT, MACC); | |
2218 | CONFLICT (DMULT, DMACC); | |
2219 | CONFLICT (DIV, MACC); | |
2220 | CONFLICT (DIV, DMACC); | |
2221 | ||
2222 | #undef CONFLICT | |
2223 | } | |
2224 | ||
707bfff6 TS |
2225 | struct regname { |
2226 | const char *name; | |
2227 | unsigned int num; | |
2228 | }; | |
2229 | ||
2230 | #define RTYPE_MASK 0x1ff00 | |
2231 | #define RTYPE_NUM 0x00100 | |
2232 | #define RTYPE_FPU 0x00200 | |
2233 | #define RTYPE_FCC 0x00400 | |
2234 | #define RTYPE_VEC 0x00800 | |
2235 | #define RTYPE_GP 0x01000 | |
2236 | #define RTYPE_CP0 0x02000 | |
2237 | #define RTYPE_PC 0x04000 | |
2238 | #define RTYPE_ACC 0x08000 | |
2239 | #define RTYPE_CCC 0x10000 | |
2240 | #define RNUM_MASK 0x000ff | |
2241 | #define RWARN 0x80000 | |
2242 | ||
2243 | #define GENERIC_REGISTER_NUMBERS \ | |
2244 | {"$0", RTYPE_NUM | 0}, \ | |
2245 | {"$1", RTYPE_NUM | 1}, \ | |
2246 | {"$2", RTYPE_NUM | 2}, \ | |
2247 | {"$3", RTYPE_NUM | 3}, \ | |
2248 | {"$4", RTYPE_NUM | 4}, \ | |
2249 | {"$5", RTYPE_NUM | 5}, \ | |
2250 | {"$6", RTYPE_NUM | 6}, \ | |
2251 | {"$7", RTYPE_NUM | 7}, \ | |
2252 | {"$8", RTYPE_NUM | 8}, \ | |
2253 | {"$9", RTYPE_NUM | 9}, \ | |
2254 | {"$10", RTYPE_NUM | 10}, \ | |
2255 | {"$11", RTYPE_NUM | 11}, \ | |
2256 | {"$12", RTYPE_NUM | 12}, \ | |
2257 | {"$13", RTYPE_NUM | 13}, \ | |
2258 | {"$14", RTYPE_NUM | 14}, \ | |
2259 | {"$15", RTYPE_NUM | 15}, \ | |
2260 | {"$16", RTYPE_NUM | 16}, \ | |
2261 | {"$17", RTYPE_NUM | 17}, \ | |
2262 | {"$18", RTYPE_NUM | 18}, \ | |
2263 | {"$19", RTYPE_NUM | 19}, \ | |
2264 | {"$20", RTYPE_NUM | 20}, \ | |
2265 | {"$21", RTYPE_NUM | 21}, \ | |
2266 | {"$22", RTYPE_NUM | 22}, \ | |
2267 | {"$23", RTYPE_NUM | 23}, \ | |
2268 | {"$24", RTYPE_NUM | 24}, \ | |
2269 | {"$25", RTYPE_NUM | 25}, \ | |
2270 | {"$26", RTYPE_NUM | 26}, \ | |
2271 | {"$27", RTYPE_NUM | 27}, \ | |
2272 | {"$28", RTYPE_NUM | 28}, \ | |
2273 | {"$29", RTYPE_NUM | 29}, \ | |
2274 | {"$30", RTYPE_NUM | 30}, \ | |
2275 | {"$31", RTYPE_NUM | 31} | |
2276 | ||
2277 | #define FPU_REGISTER_NAMES \ | |
2278 | {"$f0", RTYPE_FPU | 0}, \ | |
2279 | {"$f1", RTYPE_FPU | 1}, \ | |
2280 | {"$f2", RTYPE_FPU | 2}, \ | |
2281 | {"$f3", RTYPE_FPU | 3}, \ | |
2282 | {"$f4", RTYPE_FPU | 4}, \ | |
2283 | {"$f5", RTYPE_FPU | 5}, \ | |
2284 | {"$f6", RTYPE_FPU | 6}, \ | |
2285 | {"$f7", RTYPE_FPU | 7}, \ | |
2286 | {"$f8", RTYPE_FPU | 8}, \ | |
2287 | {"$f9", RTYPE_FPU | 9}, \ | |
2288 | {"$f10", RTYPE_FPU | 10}, \ | |
2289 | {"$f11", RTYPE_FPU | 11}, \ | |
2290 | {"$f12", RTYPE_FPU | 12}, \ | |
2291 | {"$f13", RTYPE_FPU | 13}, \ | |
2292 | {"$f14", RTYPE_FPU | 14}, \ | |
2293 | {"$f15", RTYPE_FPU | 15}, \ | |
2294 | {"$f16", RTYPE_FPU | 16}, \ | |
2295 | {"$f17", RTYPE_FPU | 17}, \ | |
2296 | {"$f18", RTYPE_FPU | 18}, \ | |
2297 | {"$f19", RTYPE_FPU | 19}, \ | |
2298 | {"$f20", RTYPE_FPU | 20}, \ | |
2299 | {"$f21", RTYPE_FPU | 21}, \ | |
2300 | {"$f22", RTYPE_FPU | 22}, \ | |
2301 | {"$f23", RTYPE_FPU | 23}, \ | |
2302 | {"$f24", RTYPE_FPU | 24}, \ | |
2303 | {"$f25", RTYPE_FPU | 25}, \ | |
2304 | {"$f26", RTYPE_FPU | 26}, \ | |
2305 | {"$f27", RTYPE_FPU | 27}, \ | |
2306 | {"$f28", RTYPE_FPU | 28}, \ | |
2307 | {"$f29", RTYPE_FPU | 29}, \ | |
2308 | {"$f30", RTYPE_FPU | 30}, \ | |
2309 | {"$f31", RTYPE_FPU | 31} | |
2310 | ||
2311 | #define FPU_CONDITION_CODE_NAMES \ | |
2312 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2313 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2314 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2315 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2316 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2317 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2318 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2319 | {"$fcc7", RTYPE_FCC | 7} | |
2320 | ||
2321 | #define COPROC_CONDITION_CODE_NAMES \ | |
2322 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2323 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2324 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2325 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2326 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2327 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2328 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2329 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2330 | ||
2331 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2332 | {"$a4", RTYPE_GP | 8}, \ | |
2333 | {"$a5", RTYPE_GP | 9}, \ | |
2334 | {"$a6", RTYPE_GP | 10}, \ | |
2335 | {"$a7", RTYPE_GP | 11}, \ | |
2336 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2337 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2338 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2339 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2340 | {"$t0", RTYPE_GP | 12}, \ | |
2341 | {"$t1", RTYPE_GP | 13}, \ | |
2342 | {"$t2", RTYPE_GP | 14}, \ | |
2343 | {"$t3", RTYPE_GP | 15} | |
2344 | ||
2345 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2346 | {"$t0", RTYPE_GP | 8}, \ | |
2347 | {"$t1", RTYPE_GP | 9}, \ | |
2348 | {"$t2", RTYPE_GP | 10}, \ | |
2349 | {"$t3", RTYPE_GP | 11}, \ | |
2350 | {"$t4", RTYPE_GP | 12}, \ | |
2351 | {"$t5", RTYPE_GP | 13}, \ | |
2352 | {"$t6", RTYPE_GP | 14}, \ | |
2353 | {"$t7", RTYPE_GP | 15}, \ | |
2354 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2355 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2356 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2357 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2358 | ||
2359 | /* Remaining symbolic register names */ | |
2360 | #define SYMBOLIC_REGISTER_NAMES \ | |
2361 | {"$zero", RTYPE_GP | 0}, \ | |
2362 | {"$at", RTYPE_GP | 1}, \ | |
2363 | {"$AT", RTYPE_GP | 1}, \ | |
2364 | {"$v0", RTYPE_GP | 2}, \ | |
2365 | {"$v1", RTYPE_GP | 3}, \ | |
2366 | {"$a0", RTYPE_GP | 4}, \ | |
2367 | {"$a1", RTYPE_GP | 5}, \ | |
2368 | {"$a2", RTYPE_GP | 6}, \ | |
2369 | {"$a3", RTYPE_GP | 7}, \ | |
2370 | {"$s0", RTYPE_GP | 16}, \ | |
2371 | {"$s1", RTYPE_GP | 17}, \ | |
2372 | {"$s2", RTYPE_GP | 18}, \ | |
2373 | {"$s3", RTYPE_GP | 19}, \ | |
2374 | {"$s4", RTYPE_GP | 20}, \ | |
2375 | {"$s5", RTYPE_GP | 21}, \ | |
2376 | {"$s6", RTYPE_GP | 22}, \ | |
2377 | {"$s7", RTYPE_GP | 23}, \ | |
2378 | {"$t8", RTYPE_GP | 24}, \ | |
2379 | {"$t9", RTYPE_GP | 25}, \ | |
2380 | {"$k0", RTYPE_GP | 26}, \ | |
2381 | {"$kt0", RTYPE_GP | 26}, \ | |
2382 | {"$k1", RTYPE_GP | 27}, \ | |
2383 | {"$kt1", RTYPE_GP | 27}, \ | |
2384 | {"$gp", RTYPE_GP | 28}, \ | |
2385 | {"$sp", RTYPE_GP | 29}, \ | |
2386 | {"$s8", RTYPE_GP | 30}, \ | |
2387 | {"$fp", RTYPE_GP | 30}, \ | |
2388 | {"$ra", RTYPE_GP | 31} | |
2389 | ||
2390 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2391 | {"$pc", RTYPE_PC | 0} | |
2392 | ||
2393 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2394 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2395 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2396 | {"$v2", RTYPE_VEC | 2}, \ | |
2397 | {"$v3", RTYPE_VEC | 3}, \ | |
2398 | {"$v4", RTYPE_VEC | 4}, \ | |
2399 | {"$v5", RTYPE_VEC | 5}, \ | |
2400 | {"$v6", RTYPE_VEC | 6}, \ | |
2401 | {"$v7", RTYPE_VEC | 7}, \ | |
2402 | {"$v8", RTYPE_VEC | 8}, \ | |
2403 | {"$v9", RTYPE_VEC | 9}, \ | |
2404 | {"$v10", RTYPE_VEC | 10}, \ | |
2405 | {"$v11", RTYPE_VEC | 11}, \ | |
2406 | {"$v12", RTYPE_VEC | 12}, \ | |
2407 | {"$v13", RTYPE_VEC | 13}, \ | |
2408 | {"$v14", RTYPE_VEC | 14}, \ | |
2409 | {"$v15", RTYPE_VEC | 15}, \ | |
2410 | {"$v16", RTYPE_VEC | 16}, \ | |
2411 | {"$v17", RTYPE_VEC | 17}, \ | |
2412 | {"$v18", RTYPE_VEC | 18}, \ | |
2413 | {"$v19", RTYPE_VEC | 19}, \ | |
2414 | {"$v20", RTYPE_VEC | 20}, \ | |
2415 | {"$v21", RTYPE_VEC | 21}, \ | |
2416 | {"$v22", RTYPE_VEC | 22}, \ | |
2417 | {"$v23", RTYPE_VEC | 23}, \ | |
2418 | {"$v24", RTYPE_VEC | 24}, \ | |
2419 | {"$v25", RTYPE_VEC | 25}, \ | |
2420 | {"$v26", RTYPE_VEC | 26}, \ | |
2421 | {"$v27", RTYPE_VEC | 27}, \ | |
2422 | {"$v28", RTYPE_VEC | 28}, \ | |
2423 | {"$v29", RTYPE_VEC | 29}, \ | |
2424 | {"$v30", RTYPE_VEC | 30}, \ | |
2425 | {"$v31", RTYPE_VEC | 31} | |
2426 | ||
2427 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2428 | {"$ac0", RTYPE_ACC | 0}, \ | |
2429 | {"$ac1", RTYPE_ACC | 1}, \ | |
2430 | {"$ac2", RTYPE_ACC | 2}, \ | |
2431 | {"$ac3", RTYPE_ACC | 3} | |
2432 | ||
2433 | static const struct regname reg_names[] = { | |
2434 | GENERIC_REGISTER_NUMBERS, | |
2435 | FPU_REGISTER_NAMES, | |
2436 | FPU_CONDITION_CODE_NAMES, | |
2437 | COPROC_CONDITION_CODE_NAMES, | |
2438 | ||
2439 | /* The $txx registers depends on the abi, | |
2440 | these will be added later into the symbol table from | |
2441 | one of the tables below once mips_abi is set after | |
2442 | parsing of arguments from the command line. */ | |
2443 | SYMBOLIC_REGISTER_NAMES, | |
2444 | ||
2445 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2446 | MDMX_VECTOR_REGISTER_NAMES, | |
2447 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2448 | {0, 0} | |
2449 | }; | |
2450 | ||
2451 | static const struct regname reg_names_o32[] = { | |
2452 | O32_SYMBOLIC_REGISTER_NAMES, | |
2453 | {0, 0} | |
2454 | }; | |
2455 | ||
2456 | static const struct regname reg_names_n32n64[] = { | |
2457 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2458 | {0, 0} | |
2459 | }; | |
2460 | ||
df58fc94 RS |
2461 | /* Check if S points at a valid register specifier according to TYPES. |
2462 | If so, then return 1, advance S to consume the specifier and store | |
2463 | the register's number in REGNOP, otherwise return 0. */ | |
2464 | ||
707bfff6 TS |
2465 | static int |
2466 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2467 | { | |
2468 | symbolS *symbolP; | |
2469 | char *e; | |
2470 | char save_c; | |
2471 | int reg = -1; | |
2472 | ||
2473 | /* Find end of name. */ | |
2474 | e = *s; | |
2475 | if (is_name_beginner (*e)) | |
2476 | ++e; | |
2477 | while (is_part_of_name (*e)) | |
2478 | ++e; | |
2479 | ||
2480 | /* Terminate name. */ | |
2481 | save_c = *e; | |
2482 | *e = '\0'; | |
2483 | ||
2484 | /* Look for a register symbol. */ | |
2485 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2486 | { | |
2487 | int r = S_GET_VALUE (symbolP); | |
2488 | if (r & types) | |
2489 | reg = r & RNUM_MASK; | |
2490 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2491 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2492 | reg = (r & RNUM_MASK) - 2; | |
2493 | } | |
2494 | /* Else see if this is a register defined in an itbl entry. */ | |
2495 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2496 | { | |
2497 | char *n = *s; | |
2498 | unsigned long r; | |
2499 | ||
2500 | if (*n == '$') | |
2501 | ++n; | |
2502 | if (itbl_get_reg_val (n, &r)) | |
2503 | reg = r & RNUM_MASK; | |
2504 | } | |
2505 | ||
2506 | /* Advance to next token if a register was recognised. */ | |
2507 | if (reg >= 0) | |
2508 | *s = e; | |
2509 | else if (types & RWARN) | |
20203fb9 | 2510 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2511 | |
2512 | *e = save_c; | |
2513 | if (regnop) | |
2514 | *regnop = reg; | |
2515 | return reg >= 0; | |
2516 | } | |
2517 | ||
df58fc94 RS |
2518 | /* Check if S points at a valid register list according to TYPES. |
2519 | If so, then return 1, advance S to consume the list and store | |
2520 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2521 | otherwise return 0. A valid list comprises a comma-separated | |
2522 | enumeration of valid single registers and/or dash-separated | |
2523 | contiguous register ranges as determined by their numbers. | |
2524 | ||
2525 | As a special exception if one of s0-s7 registers is specified as | |
2526 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2527 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2528 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2529 | |
2530 | static int | |
2531 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2532 | { | |
2533 | unsigned int reglist = 0; | |
2534 | unsigned int lastregno; | |
2535 | bfd_boolean ok = TRUE; | |
2536 | unsigned int regmask; | |
2309ddf2 | 2537 | char *s_endlist = *s; |
df58fc94 | 2538 | char *s_reset = *s; |
2309ddf2 | 2539 | unsigned int regno; |
df58fc94 RS |
2540 | |
2541 | while (reg_lookup (s, types, ®no)) | |
2542 | { | |
2543 | lastregno = regno; | |
2544 | if (**s == '-') | |
2545 | { | |
2546 | (*s)++; | |
2547 | ok = reg_lookup (s, types, &lastregno); | |
2548 | if (ok && lastregno < regno) | |
2549 | ok = FALSE; | |
2550 | if (!ok) | |
2551 | break; | |
2552 | } | |
2553 | ||
2554 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2555 | { | |
2556 | lastregno = S7; | |
2557 | reglist |= 1 << FP; | |
2558 | } | |
2559 | regmask = 1 << lastregno; | |
2560 | regmask = (regmask << 1) - 1; | |
2561 | regmask ^= (1 << regno) - 1; | |
2562 | reglist |= regmask; | |
2563 | ||
2309ddf2 | 2564 | s_endlist = *s; |
df58fc94 RS |
2565 | if (**s != ',') |
2566 | break; | |
2567 | (*s)++; | |
2568 | } | |
2569 | ||
2570 | if (ok) | |
2309ddf2 | 2571 | *s = s_endlist; |
df58fc94 RS |
2572 | else |
2573 | *s = s_reset; | |
2574 | if (reglistp) | |
2575 | *reglistp = reglist; | |
2576 | return ok && reglist != 0; | |
2577 | } | |
2578 | ||
d301a56b RS |
2579 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2580 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2581 | |
2582 | static bfd_boolean | |
f79e2745 | 2583 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2584 | { |
2585 | int isa = mips_opts.isa; | |
846ef2d0 | 2586 | int ase = mips_opts.ase; |
037b32b9 | 2587 | int fp_s, fp_d; |
c6278170 | 2588 | unsigned int i; |
037b32b9 | 2589 | |
c6278170 RS |
2590 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
2591 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2592 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
2593 | ase |= mips_ases[i].flags64; | |
037b32b9 | 2594 | |
d301a56b | 2595 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2596 | return FALSE; |
2597 | ||
2598 | /* Check whether the instruction or macro requires single-precision or | |
2599 | double-precision floating-point support. Note that this information is | |
2600 | stored differently in the opcode table for insns and macros. */ | |
2601 | if (mo->pinfo == INSN_MACRO) | |
2602 | { | |
2603 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2604 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2605 | } | |
2606 | else | |
2607 | { | |
2608 | fp_s = mo->pinfo & FP_S; | |
2609 | fp_d = mo->pinfo & FP_D; | |
2610 | } | |
2611 | ||
2612 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2613 | return FALSE; | |
2614 | ||
2615 | if (fp_s && mips_opts.soft_float) | |
2616 | return FALSE; | |
2617 | ||
2618 | return TRUE; | |
2619 | } | |
2620 | ||
2621 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2622 | selected ISA and architecture. */ | |
2623 | ||
2624 | static bfd_boolean | |
2625 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2626 | { | |
d301a56b | 2627 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2628 | } |
2629 | ||
df58fc94 RS |
2630 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2631 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2632 | ||
2633 | static bfd_boolean | |
2634 | is_size_valid (const struct mips_opcode *mo) | |
2635 | { | |
2636 | if (!mips_opts.micromips) | |
2637 | return TRUE; | |
2638 | ||
2639 | if (!forced_insn_length) | |
2640 | return TRUE; | |
2641 | if (mo->pinfo == INSN_MACRO) | |
2642 | return FALSE; | |
2643 | return forced_insn_length == micromips_insn_length (mo); | |
2644 | } | |
2645 | ||
2646 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2647 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2648 | ||
2649 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2650 | a macro expansion fails because it relies on a preceding 32-bit real | |
2651 | instruction to have matched and does not handle the operands correctly. | |
2652 | The only macros that may expand to 16-bit instructions are JAL that | |
2653 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2654 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2655 | a NOP. In all these cases the macros precede any corresponding real | |
2656 | instruction definitions in the opcode table, so they will match in the | |
2657 | second pass where the size of the delay slot is ignored and therefore | |
2658 | produce correct code. */ | |
df58fc94 RS |
2659 | |
2660 | static bfd_boolean | |
2661 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2662 | { | |
2663 | if (!mips_opts.micromips) | |
2664 | return TRUE; | |
2665 | ||
2666 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2667 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2668 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2669 | && micromips_insn_length (mo) != 4) | |
2670 | return FALSE; | |
2671 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2672 | && micromips_insn_length (mo) != 2) | |
2673 | return FALSE; | |
2674 | ||
2675 | return TRUE; | |
2676 | } | |
2677 | ||
707bfff6 TS |
2678 | /* This function is called once, at assembler startup time. It should set up |
2679 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2680 | |
252b5132 | 2681 | void |
17a2f251 | 2682 | md_begin (void) |
252b5132 | 2683 | { |
3994f87e | 2684 | const char *retval = NULL; |
156c2f8b | 2685 | int i = 0; |
252b5132 | 2686 | int broken = 0; |
1f25f5d3 | 2687 | |
0a44bf69 RS |
2688 | if (mips_pic != NO_PIC) |
2689 | { | |
2690 | if (g_switch_seen && g_switch_value != 0) | |
2691 | as_bad (_("-G may not be used in position-independent code")); | |
2692 | g_switch_value = 0; | |
2693 | } | |
2694 | ||
fef14a42 | 2695 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2696 | as_warn (_("Could not set architecture and machine")); |
2697 | ||
252b5132 RH |
2698 | op_hash = hash_new (); |
2699 | ||
2700 | for (i = 0; i < NUMOPCODES;) | |
2701 | { | |
2702 | const char *name = mips_opcodes[i].name; | |
2703 | ||
17a2f251 | 2704 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2705 | if (retval != NULL) |
2706 | { | |
2707 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2708 | mips_opcodes[i].name, retval); | |
2709 | /* Probably a memory allocation problem? Give up now. */ | |
2710 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2711 | } | |
2712 | do | |
2713 | { | |
2714 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2715 | { | |
2716 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2717 | broken = 1; | |
1e915849 RS |
2718 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2719 | { | |
2720 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2721 | if (mips_fix_loongson2f_nop) |
2722 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2723 | nop_insn.fixed_p = 1; |
2724 | } | |
252b5132 RH |
2725 | } |
2726 | ++i; | |
2727 | } | |
2728 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2729 | } | |
2730 | ||
2731 | mips16_op_hash = hash_new (); | |
2732 | ||
2733 | i = 0; | |
2734 | while (i < bfd_mips16_num_opcodes) | |
2735 | { | |
2736 | const char *name = mips16_opcodes[i].name; | |
2737 | ||
17a2f251 | 2738 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2739 | if (retval != NULL) |
2740 | as_fatal (_("internal: can't hash `%s': %s"), | |
2741 | mips16_opcodes[i].name, retval); | |
2742 | do | |
2743 | { | |
2744 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2745 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2746 | != mips16_opcodes[i].match)) | |
2747 | { | |
2748 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2749 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2750 | broken = 1; | |
2751 | } | |
1e915849 RS |
2752 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2753 | { | |
2754 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2755 | mips16_nop_insn.fixed_p = 1; | |
2756 | } | |
252b5132 RH |
2757 | ++i; |
2758 | } | |
2759 | while (i < bfd_mips16_num_opcodes | |
2760 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2761 | } | |
2762 | ||
df58fc94 RS |
2763 | micromips_op_hash = hash_new (); |
2764 | ||
2765 | i = 0; | |
2766 | while (i < bfd_micromips_num_opcodes) | |
2767 | { | |
2768 | const char *name = micromips_opcodes[i].name; | |
2769 | ||
2770 | retval = hash_insert (micromips_op_hash, name, | |
2771 | (void *) µmips_opcodes[i]); | |
2772 | if (retval != NULL) | |
2773 | as_fatal (_("internal: can't hash `%s': %s"), | |
2774 | micromips_opcodes[i].name, retval); | |
2775 | do | |
2776 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2777 | { | |
2778 | struct mips_cl_insn *micromips_nop_insn; | |
2779 | ||
2780 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2781 | broken = 1; | |
2782 | ||
2783 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2784 | micromips_nop_insn = µmips_nop16_insn; | |
2785 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2786 | micromips_nop_insn = µmips_nop32_insn; | |
2787 | else | |
2788 | continue; | |
2789 | ||
2790 | if (micromips_nop_insn->insn_mo == NULL | |
2791 | && strcmp (name, "nop") == 0) | |
2792 | { | |
2793 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2794 | micromips_nop_insn->fixed_p = 1; | |
2795 | } | |
2796 | } | |
2797 | while (++i < bfd_micromips_num_opcodes | |
2798 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2799 | } | |
2800 | ||
252b5132 RH |
2801 | if (broken) |
2802 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2803 | ||
2804 | /* We add all the general register names to the symbol table. This | |
2805 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2806 | for (i = 0; reg_names[i].name; i++) |
2807 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2808 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2809 | &zero_address_frag)); |
2810 | if (HAVE_NEWABI) | |
2811 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2812 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2813 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2814 | &zero_address_frag)); |
707bfff6 TS |
2815 | else |
2816 | for (i = 0; reg_names_o32[i].name; i++) | |
2817 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2818 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2819 | &zero_address_frag)); |
6047c971 | 2820 | |
7d10b47d | 2821 | mips_no_prev_insn (); |
252b5132 RH |
2822 | |
2823 | mips_gprmask = 0; | |
2824 | mips_cprmask[0] = 0; | |
2825 | mips_cprmask[1] = 0; | |
2826 | mips_cprmask[2] = 0; | |
2827 | mips_cprmask[3] = 0; | |
2828 | ||
2829 | /* set the default alignment for the text section (2**2) */ | |
2830 | record_alignment (text_section, 2); | |
2831 | ||
4d0d148d | 2832 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2833 | |
f3ded42a RS |
2834 | /* On a native system other than VxWorks, sections must be aligned |
2835 | to 16 byte boundaries. When configured for an embedded ELF | |
2836 | target, we don't bother. */ | |
2837 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
2838 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 2839 | { |
f3ded42a RS |
2840 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
2841 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2842 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2843 | } | |
252b5132 | 2844 | |
f3ded42a RS |
2845 | /* Create a .reginfo section for register masks and a .mdebug |
2846 | section for debugging information. */ | |
2847 | { | |
2848 | segT seg; | |
2849 | subsegT subseg; | |
2850 | flagword flags; | |
2851 | segT sec; | |
2852 | ||
2853 | seg = now_seg; | |
2854 | subseg = now_subseg; | |
2855 | ||
2856 | /* The ABI says this section should be loaded so that the | |
2857 | running program can access it. However, we don't load it | |
2858 | if we are configured for an embedded target */ | |
2859 | flags = SEC_READONLY | SEC_DATA; | |
2860 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
2861 | flags |= SEC_ALLOC | SEC_LOAD; | |
2862 | ||
2863 | if (mips_abi != N64_ABI) | |
252b5132 | 2864 | { |
f3ded42a | 2865 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 2866 | |
f3ded42a RS |
2867 | bfd_set_section_flags (stdoutput, sec, flags); |
2868 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 2869 | |
f3ded42a RS |
2870 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
2871 | } | |
2872 | else | |
2873 | { | |
2874 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2875 | .reginfo section. */ | |
2876 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
2877 | bfd_set_section_flags (stdoutput, sec, flags); | |
2878 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2879 | |
f3ded42a RS |
2880 | /* Set up the option header. */ |
2881 | { | |
2882 | Elf_Internal_Options opthdr; | |
2883 | char *f; | |
2884 | ||
2885 | opthdr.kind = ODK_REGINFO; | |
2886 | opthdr.size = (sizeof (Elf_External_Options) | |
2887 | + sizeof (Elf64_External_RegInfo)); | |
2888 | opthdr.section = 0; | |
2889 | opthdr.info = 0; | |
2890 | f = frag_more (sizeof (Elf_External_Options)); | |
2891 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2892 | (Elf_External_Options *) f); | |
2893 | ||
2894 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2895 | } | |
2896 | } | |
252b5132 | 2897 | |
f3ded42a RS |
2898 | if (ECOFF_DEBUGGING) |
2899 | { | |
2900 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2901 | (void) bfd_set_section_flags (stdoutput, sec, | |
2902 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2903 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 2904 | } |
f3ded42a RS |
2905 | else if (mips_flag_pdr) |
2906 | { | |
2907 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2908 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2909 | SEC_READONLY | SEC_RELOC | |
2910 | | SEC_DEBUGGING); | |
2911 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2912 | } | |
2913 | ||
2914 | subseg_set (seg, subseg); | |
2915 | } | |
252b5132 RH |
2916 | |
2917 | if (! ECOFF_DEBUGGING) | |
2918 | md_obj_begin (); | |
71400594 RS |
2919 | |
2920 | if (mips_fix_vr4120) | |
2921 | init_vr4120_conflicts (); | |
252b5132 RH |
2922 | } |
2923 | ||
2924 | void | |
17a2f251 | 2925 | md_mips_end (void) |
252b5132 | 2926 | { |
02b1ab82 | 2927 | mips_emit_delays (); |
252b5132 RH |
2928 | if (! ECOFF_DEBUGGING) |
2929 | md_obj_end (); | |
2930 | } | |
2931 | ||
2932 | void | |
17a2f251 | 2933 | md_assemble (char *str) |
252b5132 RH |
2934 | { |
2935 | struct mips_cl_insn insn; | |
f6688943 TS |
2936 | bfd_reloc_code_real_type unused_reloc[3] |
2937 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2938 | |
2939 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2940 | imm2_expr.X_op = O_absent; |
252b5132 | 2941 | offset_expr.X_op = O_absent; |
f6688943 TS |
2942 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2943 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2944 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2945 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2946 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2947 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2948 | |
e1b47bd5 RS |
2949 | mips_mark_labels (); |
2950 | mips_assembling_insn = TRUE; | |
2951 | ||
252b5132 RH |
2952 | if (mips_opts.mips16) |
2953 | mips16_ip (str, &insn); | |
2954 | else | |
2955 | { | |
2956 | mips_ip (str, &insn); | |
beae10d5 KH |
2957 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2958 | str, insn.insn_opcode)); | |
252b5132 RH |
2959 | } |
2960 | ||
2961 | if (insn_error) | |
e1b47bd5 RS |
2962 | as_bad ("%s `%s'", insn_error, str); |
2963 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2964 | { |
584892a6 | 2965 | macro_start (); |
252b5132 RH |
2966 | if (mips_opts.mips16) |
2967 | mips16_macro (&insn); | |
2968 | else | |
2969 | macro (&insn); | |
584892a6 | 2970 | macro_end (); |
252b5132 RH |
2971 | } |
2972 | else | |
2973 | { | |
2974 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2975 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2976 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2977 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2978 | else |
df58fc94 | 2979 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2980 | } |
e1b47bd5 RS |
2981 | |
2982 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2983 | } |
2984 | ||
738e5348 RS |
2985 | /* Convenience functions for abstracting away the differences between |
2986 | MIPS16 and non-MIPS16 relocations. */ | |
2987 | ||
2988 | static inline bfd_boolean | |
2989 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2990 | { | |
2991 | switch (reloc) | |
2992 | { | |
2993 | case BFD_RELOC_MIPS16_JMP: | |
2994 | case BFD_RELOC_MIPS16_GPREL: | |
2995 | case BFD_RELOC_MIPS16_GOT16: | |
2996 | case BFD_RELOC_MIPS16_CALL16: | |
2997 | case BFD_RELOC_MIPS16_HI16_S: | |
2998 | case BFD_RELOC_MIPS16_HI16: | |
2999 | case BFD_RELOC_MIPS16_LO16: | |
3000 | return TRUE; | |
3001 | ||
3002 | default: | |
3003 | return FALSE; | |
3004 | } | |
3005 | } | |
3006 | ||
df58fc94 RS |
3007 | static inline bfd_boolean |
3008 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
3009 | { | |
3010 | switch (reloc) | |
3011 | { | |
3012 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3013 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3014 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3015 | case BFD_RELOC_MICROMIPS_GPREL16: | |
3016 | case BFD_RELOC_MICROMIPS_JMP: | |
3017 | case BFD_RELOC_MICROMIPS_HI16: | |
3018 | case BFD_RELOC_MICROMIPS_HI16_S: | |
3019 | case BFD_RELOC_MICROMIPS_LO16: | |
3020 | case BFD_RELOC_MICROMIPS_LITERAL: | |
3021 | case BFD_RELOC_MICROMIPS_GOT16: | |
3022 | case BFD_RELOC_MICROMIPS_CALL16: | |
3023 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
3024 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
3025 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
3026 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
3027 | case BFD_RELOC_MICROMIPS_SUB: | |
3028 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
3029 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
3030 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
3031 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
3032 | case BFD_RELOC_MICROMIPS_HIGHER: | |
3033 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
3034 | case BFD_RELOC_MICROMIPS_JALR: | |
3035 | return TRUE; | |
3036 | ||
3037 | default: | |
3038 | return FALSE; | |
3039 | } | |
3040 | } | |
3041 | ||
2309ddf2 MR |
3042 | static inline bfd_boolean |
3043 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
3044 | { | |
3045 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
3046 | } | |
3047 | ||
738e5348 RS |
3048 | static inline bfd_boolean |
3049 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
3050 | { | |
2309ddf2 | 3051 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 3052 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
3053 | } |
3054 | ||
3055 | static inline bfd_boolean | |
3056 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
3057 | { | |
2309ddf2 | 3058 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 3059 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
3060 | } |
3061 | ||
3062 | static inline bfd_boolean | |
3063 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
3064 | { | |
2309ddf2 | 3065 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
3066 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
3067 | } | |
3068 | ||
df58fc94 RS |
3069 | static inline bfd_boolean |
3070 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
3071 | { | |
2309ddf2 | 3072 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
3073 | } |
3074 | ||
2de39019 CM |
3075 | /* Return true if RELOC is a PC-relative relocation that does not have |
3076 | full address range. */ | |
3077 | ||
3078 | static inline bfd_boolean | |
3079 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
3080 | { | |
3081 | switch (reloc) | |
3082 | { | |
3083 | case BFD_RELOC_16_PCREL_S2: | |
3084 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3085 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3086 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3087 | return TRUE; | |
3088 | ||
b47468a6 CM |
3089 | case BFD_RELOC_32_PCREL: |
3090 | return HAVE_64BIT_ADDRESSES; | |
3091 | ||
2de39019 CM |
3092 | default: |
3093 | return FALSE; | |
3094 | } | |
3095 | } | |
b47468a6 | 3096 | |
5919d012 | 3097 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
3098 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
3099 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
3100 | |
3101 | static inline bfd_boolean | |
17a2f251 | 3102 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 3103 | { |
3b91255e | 3104 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 3105 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
3106 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
3107 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
3108 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
3109 | } | |
3110 | ||
3111 | /* Return the type of %lo() reloc needed by RELOC, given that | |
3112 | reloc_needs_lo_p. */ | |
3113 | ||
3114 | static inline bfd_reloc_code_real_type | |
3115 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
3116 | { | |
df58fc94 RS |
3117 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
3118 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
3119 | : BFD_RELOC_LO16)); | |
5919d012 RS |
3120 | } |
3121 | ||
3122 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
3123 | relocation. */ | |
3124 | ||
3125 | static inline bfd_boolean | |
17a2f251 | 3126 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
3127 | { |
3128 | return (fixp->fx_next != NULL | |
738e5348 | 3129 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
3130 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
3131 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
3132 | } | |
3133 | ||
252b5132 RH |
3134 | /* This function returns true if modifying a register requires a |
3135 | delay. */ | |
3136 | ||
3137 | static int | |
17a2f251 | 3138 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
3139 | { |
3140 | unsigned long prev_pinfo; | |
3141 | ||
47e39b9d | 3142 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 3143 | if (! mips_opts.noreorder |
81912461 ILT |
3144 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
3145 | && ! gpr_interlocks) | |
3146 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
3147 | && ! cop_interlocks))) | |
252b5132 | 3148 | { |
81912461 ILT |
3149 | /* A load from a coprocessor or from memory. All load delays |
3150 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 3151 | /* Itbl support may require additional care here. */ |
252b5132 | 3152 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 3153 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
3154 | return 1; |
3155 | } | |
3156 | ||
3157 | return 0; | |
3158 | } | |
3159 | ||
462427c4 RS |
3160 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3161 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3162 | |
3163 | static void | |
462427c4 | 3164 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3165 | { |
3166 | struct insn_label_list *l; | |
3167 | valueT val; | |
3168 | ||
462427c4 | 3169 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3170 | { |
9c2799c2 | 3171 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3172 | symbol_set_frag (l->label, frag_now); |
3173 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3174 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3175 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3176 | ++val; |
3177 | S_SET_VALUE (l->label, val); | |
3178 | } | |
3179 | } | |
3180 | ||
462427c4 RS |
3181 | /* Move all labels in insn_labels to the current insertion point |
3182 | and treat them as text labels. */ | |
3183 | ||
3184 | static void | |
3185 | mips_move_text_labels (void) | |
3186 | { | |
3187 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3188 | } | |
3189 | ||
5f0fe04b TS |
3190 | static bfd_boolean |
3191 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3192 | { | |
3193 | bfd_boolean linkonce = FALSE; | |
3194 | segT symseg = S_GET_SEGMENT (sym); | |
3195 | ||
3196 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3197 | { | |
3198 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3199 | linkonce = TRUE; | |
5f0fe04b TS |
3200 | /* The GNU toolchain uses an extension for ELF: a section |
3201 | beginning with the magic string .gnu.linkonce is a | |
3202 | linkonce section. */ | |
3203 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3204 | sizeof ".gnu.linkonce" - 1) == 0) | |
3205 | linkonce = TRUE; | |
5f0fe04b TS |
3206 | } |
3207 | return linkonce; | |
3208 | } | |
3209 | ||
e1b47bd5 | 3210 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3211 | linker to handle them specially, such as generating jalx instructions |
3212 | when needed. We also make them odd for the duration of the assembly, | |
3213 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3214 | in the adjust_symtab routine, while leaving them marked. This is |
3215 | convenient for the debugger and the disassembler. The linker knows | |
3216 | to make them odd again. */ | |
3217 | ||
3218 | static void | |
e1b47bd5 | 3219 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3220 | { |
df58fc94 | 3221 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3222 | |
f3ded42a RS |
3223 | if (mips_opts.mips16) |
3224 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3225 | else | |
3226 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
3227 | if ((S_GET_VALUE (label) & 1) == 0 |
3228 | /* Don't adjust the address if the label is global or weak, or | |
3229 | in a link-once section, since we'll be emitting symbol reloc | |
3230 | references to it which will be patched up by the linker, and | |
3231 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3232 | && !S_IS_WEAK (label) | |
3233 | && !S_IS_EXTERNAL (label) | |
3234 | && !s_is_linkonce (label, now_seg)) | |
3235 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3236 | } | |
3237 | ||
3238 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3239 | ||
3240 | static void | |
3241 | mips_compressed_mark_labels (void) | |
3242 | { | |
3243 | struct insn_label_list *l; | |
3244 | ||
3245 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3246 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3247 | } |
3248 | ||
4d7206a2 RS |
3249 | /* End the current frag. Make it a variant frag and record the |
3250 | relaxation info. */ | |
3251 | ||
3252 | static void | |
3253 | relax_close_frag (void) | |
3254 | { | |
584892a6 | 3255 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3256 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3257 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3258 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3259 | ||
3260 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3261 | mips_relax.first_fixup = 0; | |
3262 | } | |
3263 | ||
3264 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3265 | See the comment above RELAX_ENCODE for more details. */ | |
3266 | ||
3267 | static void | |
3268 | relax_start (symbolS *symbol) | |
3269 | { | |
9c2799c2 | 3270 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3271 | mips_relax.sequence = 1; |
3272 | mips_relax.symbol = symbol; | |
3273 | } | |
3274 | ||
3275 | /* Start generating the second version of a relaxable sequence. | |
3276 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3277 | |
3278 | static void | |
4d7206a2 RS |
3279 | relax_switch (void) |
3280 | { | |
9c2799c2 | 3281 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3282 | mips_relax.sequence = 2; |
3283 | } | |
3284 | ||
3285 | /* End the current relaxable sequence. */ | |
3286 | ||
3287 | static void | |
3288 | relax_end (void) | |
3289 | { | |
9c2799c2 | 3290 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3291 | relax_close_frag (); |
3292 | mips_relax.sequence = 0; | |
3293 | } | |
3294 | ||
11625dd8 RS |
3295 | /* Return true if IP is a delayed branch or jump. */ |
3296 | ||
3297 | static inline bfd_boolean | |
3298 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3299 | { | |
3300 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3301 | | INSN_COND_BRANCH_DELAY | |
3302 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3303 | } | |
3304 | ||
3305 | /* Return true if IP is a compact branch or jump. */ | |
3306 | ||
3307 | static inline bfd_boolean | |
3308 | compact_branch_p (const struct mips_cl_insn *ip) | |
3309 | { | |
3310 | if (mips_opts.mips16) | |
3311 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3312 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3313 | else | |
3314 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3315 | | INSN2_COND_BRANCH)) != 0; | |
3316 | } | |
3317 | ||
3318 | /* Return true if IP is an unconditional branch or jump. */ | |
3319 | ||
3320 | static inline bfd_boolean | |
3321 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3322 | { | |
3323 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3324 | || (mips_opts.mips16 | |
3325 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3326 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3327 | } | |
3328 | ||
3329 | /* Return true if IP is a branch-likely instruction. */ | |
3330 | ||
3331 | static inline bfd_boolean | |
3332 | branch_likely_p (const struct mips_cl_insn *ip) | |
3333 | { | |
3334 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3335 | } | |
3336 | ||
14fe068b RS |
3337 | /* Return the type of nop that should be used to fill the delay slot |
3338 | of delayed branch IP. */ | |
3339 | ||
3340 | static struct mips_cl_insn * | |
3341 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3342 | { | |
3343 | if (mips_opts.micromips | |
3344 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3345 | return µmips_nop32_insn; | |
3346 | return NOP_INSN; | |
3347 | } | |
3348 | ||
2309ddf2 | 3349 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3350 | |
3351 | static unsigned int | |
3352 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3353 | { | |
2309ddf2 | 3354 | unsigned long pinfo2; |
df58fc94 RS |
3355 | unsigned int mask; |
3356 | ||
3357 | mask = 0; | |
df58fc94 RS |
3358 | pinfo2 = ip->insn_mo->pinfo2; |
3359 | if (mips_opts.micromips) | |
3360 | { | |
df58fc94 RS |
3361 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3362 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3363 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3364 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3365 | if (pinfo2 & INSN2_MOD_SP) |
3366 | mask |= 1 << SP; | |
3367 | } | |
3368 | return mask; | |
3369 | } | |
3370 | ||
4c260379 RS |
3371 | /* Return the mask of core registers that IP reads. */ |
3372 | ||
3373 | static unsigned int | |
3374 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3375 | { | |
3376 | unsigned long pinfo, pinfo2; | |
3377 | unsigned int mask; | |
3378 | ||
df58fc94 | 3379 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3380 | pinfo = ip->insn_mo->pinfo; |
3381 | pinfo2 = ip->insn_mo->pinfo2; | |
3382 | if (mips_opts.mips16) | |
3383 | { | |
3384 | if (pinfo & MIPS16_INSN_READ_X) | |
3385 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3386 | if (pinfo & MIPS16_INSN_READ_Y) | |
3387 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3388 | if (pinfo & MIPS16_INSN_READ_T) | |
3389 | mask |= 1 << TREG; | |
3390 | if (pinfo & MIPS16_INSN_READ_SP) | |
3391 | mask |= 1 << SP; | |
3392 | if (pinfo & MIPS16_INSN_READ_31) | |
3393 | mask |= 1 << RA; | |
3394 | if (pinfo & MIPS16_INSN_READ_Z) | |
3395 | mask |= 1 << (mips16_to_32_reg_map | |
3396 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3397 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3398 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3399 | } | |
3400 | else | |
3401 | { | |
3402 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3403 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3404 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3405 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3406 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3407 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3408 | if (pinfo2 & INSN2_READ_GP) | |
3409 | mask |= 1 << GP; | |
3410 | if (pinfo2 & INSN2_READ_GPR_31) | |
3411 | mask |= 1 << RA; | |
4c260379 | 3412 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3413 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3414 | } |
2b0c8b40 MR |
3415 | if (mips_opts.micromips) |
3416 | { | |
3417 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3418 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3419 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3420 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3421 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3422 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3423 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3424 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3425 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3426 | { | |
3427 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3428 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3429 | } | |
3430 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3431 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3432 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3433 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3434 | } | |
fe35f09f RS |
3435 | /* Don't include register 0. */ |
3436 | return mask & ~1; | |
4c260379 RS |
3437 | } |
3438 | ||
3439 | /* Return the mask of core registers that IP writes. */ | |
3440 | ||
3441 | static unsigned int | |
3442 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3443 | { | |
3444 | unsigned long pinfo, pinfo2; | |
3445 | unsigned int mask; | |
3446 | ||
df58fc94 | 3447 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3448 | pinfo = ip->insn_mo->pinfo; |
3449 | pinfo2 = ip->insn_mo->pinfo2; | |
3450 | if (mips_opts.mips16) | |
3451 | { | |
3452 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3453 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3454 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3455 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3456 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3457 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3458 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3459 | mask |= 1 << TREG; | |
3460 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3461 | mask |= 1 << SP; | |
3462 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3463 | mask |= 1 << RA; | |
3464 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3465 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3466 | } | |
3467 | else | |
3468 | { | |
3469 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3470 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3471 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3472 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3473 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3474 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3475 | if (pinfo & INSN_WRITE_GPR_31) |
3476 | mask |= 1 << RA; | |
3477 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3478 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3479 | } |
2b0c8b40 MR |
3480 | if (mips_opts.micromips) |
3481 | { | |
3482 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3483 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3484 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3485 | { | |
3486 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3487 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3488 | } | |
3489 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3490 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3491 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3492 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3493 | } | |
fe35f09f RS |
3494 | /* Don't include register 0. */ |
3495 | return mask & ~1; | |
4c260379 RS |
3496 | } |
3497 | ||
3498 | /* Return the mask of floating-point registers that IP reads. */ | |
3499 | ||
3500 | static unsigned int | |
3501 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3502 | { | |
3503 | unsigned long pinfo, pinfo2; | |
3504 | unsigned int mask; | |
3505 | ||
3506 | mask = 0; | |
3507 | pinfo = ip->insn_mo->pinfo; | |
3508 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3509 | if (!mips_opts.mips16) |
df58fc94 RS |
3510 | { |
3511 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3512 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3513 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3514 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3515 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3516 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3517 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3518 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3519 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3520 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3521 | } |
3522 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3523 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3524 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3525 | mask |= mask << 1; | |
3526 | return mask; | |
3527 | } | |
3528 | ||
3529 | /* Return the mask of floating-point registers that IP writes. */ | |
3530 | ||
3531 | static unsigned int | |
3532 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3533 | { | |
3534 | unsigned long pinfo, pinfo2; | |
3535 | unsigned int mask; | |
3536 | ||
3537 | mask = 0; | |
3538 | pinfo = ip->insn_mo->pinfo; | |
3539 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3540 | if (!mips_opts.mips16) |
4c260379 RS |
3541 | { |
3542 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3543 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3544 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3545 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3546 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3547 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3548 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3549 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3550 | } |
3551 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3552 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3553 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3554 | mask |= mask << 1; | |
3555 | return mask; | |
3556 | } | |
3557 | ||
71400594 RS |
3558 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3559 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3560 | by VR4120 errata. */ | |
4d7206a2 | 3561 | |
71400594 RS |
3562 | static unsigned int |
3563 | classify_vr4120_insn (const char *name) | |
252b5132 | 3564 | { |
71400594 RS |
3565 | if (strncmp (name, "macc", 4) == 0) |
3566 | return FIX_VR4120_MACC; | |
3567 | if (strncmp (name, "dmacc", 5) == 0) | |
3568 | return FIX_VR4120_DMACC; | |
3569 | if (strncmp (name, "mult", 4) == 0) | |
3570 | return FIX_VR4120_MULT; | |
3571 | if (strncmp (name, "dmult", 5) == 0) | |
3572 | return FIX_VR4120_DMULT; | |
3573 | if (strstr (name, "div")) | |
3574 | return FIX_VR4120_DIV; | |
3575 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3576 | return FIX_VR4120_MTHILO; | |
3577 | return NUM_FIX_VR4120_CLASSES; | |
3578 | } | |
252b5132 | 3579 | |
ff239038 CM |
3580 | #define INSN_ERET 0x42000018 |
3581 | #define INSN_DERET 0x4200001f | |
3582 | ||
71400594 RS |
3583 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3584 | where INSN1 is the earlier instruction. Return the worst-case value | |
3585 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3586 | |
71400594 RS |
3587 | static unsigned int |
3588 | insns_between (const struct mips_cl_insn *insn1, | |
3589 | const struct mips_cl_insn *insn2) | |
3590 | { | |
3591 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3592 | unsigned int mask; |
71400594 RS |
3593 | |
3594 | /* This function needs to know which pinfo flags are set for INSN2 | |
3595 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3596 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3597 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3598 | pinfo1 = insn1->insn_mo->pinfo; |
3599 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3600 | |
4c260379 RS |
3601 | #define INSN2_USES_GPR(REG) \ |
3602 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3603 | |
3604 | /* For most targets, write-after-read dependencies on the HI and LO | |
3605 | registers must be separated by at least two instructions. */ | |
3606 | if (!hilo_interlocks) | |
252b5132 | 3607 | { |
71400594 RS |
3608 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3609 | return 2; | |
3610 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3611 | return 2; | |
3612 | } | |
3613 | ||
3614 | /* If we're working around r7000 errata, there must be two instructions | |
3615 | between an mfhi or mflo and any instruction that uses the result. */ | |
3616 | if (mips_7000_hilo_fix | |
df58fc94 | 3617 | && !mips_opts.micromips |
71400594 | 3618 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3619 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3620 | return 2; |
3621 | ||
ff239038 CM |
3622 | /* If we're working around 24K errata, one instruction is required |
3623 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3624 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3625 | { |
3626 | if (insn1->insn_opcode == INSN_ERET | |
3627 | || insn1->insn_opcode == INSN_DERET) | |
3628 | { | |
3629 | if (insn2 == NULL | |
3630 | || insn2->insn_opcode == INSN_ERET | |
3631 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3632 | || delayed_branch_p (insn2)) |
ff239038 CM |
3633 | return 1; |
3634 | } | |
3635 | } | |
3636 | ||
71400594 RS |
3637 | /* If working around VR4120 errata, check for combinations that need |
3638 | a single intervening instruction. */ | |
df58fc94 | 3639 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3640 | { |
3641 | unsigned int class1, class2; | |
252b5132 | 3642 | |
71400594 RS |
3643 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3644 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3645 | { |
71400594 RS |
3646 | if (insn2 == NULL) |
3647 | return 1; | |
3648 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3649 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3650 | return 1; | |
252b5132 | 3651 | } |
71400594 RS |
3652 | } |
3653 | ||
df58fc94 | 3654 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3655 | { |
3656 | /* Check for GPR or coprocessor load delays. All such delays | |
3657 | are on the RT register. */ | |
3658 | /* Itbl support may require additional care here. */ | |
3659 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3660 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3661 | { |
71400594 | 3662 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3663 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3664 | return 1; |
3665 | } | |
3666 | ||
3667 | /* Check for generic coprocessor hazards. | |
3668 | ||
3669 | This case is not handled very well. There is no special | |
3670 | knowledge of CP0 handling, and the coprocessors other than | |
3671 | the floating point unit are not distinguished at all. */ | |
3672 | /* Itbl support may require additional care here. FIXME! | |
3673 | Need to modify this to include knowledge about | |
3674 | user specified delays! */ | |
3675 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3676 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3677 | { | |
3678 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3679 | register. There must be a one instruction delay before INSN2 | |
3680 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3681 | mask = fpr_write_mask (insn1); |
3682 | if (mask != 0) | |
252b5132 | 3683 | { |
4c260379 | 3684 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3685 | return 1; |
252b5132 RH |
3686 | } |
3687 | else | |
3688 | { | |
71400594 RS |
3689 | /* Read-after-write dependencies on the control registers |
3690 | require a two-instruction gap. */ | |
3691 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3692 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3693 | return 2; | |
3694 | ||
3695 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3696 | also a coprocessor instruction, assume there must be | |
3697 | a one instruction gap. */ | |
3698 | if (pinfo2 & INSN_COP) | |
3699 | return 1; | |
252b5132 RH |
3700 | } |
3701 | } | |
6b76fefe | 3702 | |
71400594 RS |
3703 | /* Check for read-after-write dependencies on the coprocessor |
3704 | control registers in cases where INSN1 does not need a general | |
3705 | coprocessor delay. This means that INSN1 is a floating point | |
3706 | comparison instruction. */ | |
3707 | /* Itbl support may require additional care here. */ | |
3708 | else if (!cop_interlocks | |
3709 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3710 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3711 | return 1; | |
3712 | } | |
6b76fefe | 3713 | |
4c260379 | 3714 | #undef INSN2_USES_GPR |
6b76fefe | 3715 | |
71400594 RS |
3716 | return 0; |
3717 | } | |
6b76fefe | 3718 | |
7d8e00cf RS |
3719 | /* Return the number of nops that would be needed to work around the |
3720 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3721 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3722 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3723 | |
3724 | static int | |
932d1a1b | 3725 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3726 | const struct mips_cl_insn *insn) |
3727 | { | |
4c260379 RS |
3728 | int i, j; |
3729 | unsigned int mask; | |
7d8e00cf RS |
3730 | |
3731 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3732 | are not affected by the errata. */ | |
3733 | if (insn != 0 | |
3734 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3735 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3736 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3737 | return 0; | |
3738 | ||
3739 | /* Search for the first MFLO or MFHI. */ | |
3740 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3741 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3742 | { |
3743 | /* Extract the destination register. */ | |
4c260379 | 3744 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3745 | |
3746 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3747 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3748 | return 0; |
3749 | ||
3750 | /* ...or if any of the intervening instructions do. */ | |
3751 | for (j = 0; j < i; j++) | |
4c260379 | 3752 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3753 | return 0; |
3754 | ||
932d1a1b RS |
3755 | if (i >= ignore) |
3756 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3757 | } |
3758 | return 0; | |
3759 | } | |
3760 | ||
15be625d CM |
3761 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3762 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3763 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3764 | ||
3765 | /* Return the minimum alignment for this store instruction. */ | |
3766 | ||
3767 | static int | |
3768 | fix_24k_align_to (const struct mips_opcode *mo) | |
3769 | { | |
3770 | if (strcmp (mo->name, "sh") == 0) | |
3771 | return 2; | |
3772 | ||
3773 | if (strcmp (mo->name, "swc1") == 0 | |
3774 | || strcmp (mo->name, "swc2") == 0 | |
3775 | || strcmp (mo->name, "sw") == 0 | |
3776 | || strcmp (mo->name, "sc") == 0 | |
3777 | || strcmp (mo->name, "s.s") == 0) | |
3778 | return 4; | |
3779 | ||
3780 | if (strcmp (mo->name, "sdc1") == 0 | |
3781 | || strcmp (mo->name, "sdc2") == 0 | |
3782 | || strcmp (mo->name, "s.d") == 0) | |
3783 | return 8; | |
3784 | ||
3785 | /* sb, swl, swr */ | |
3786 | return 1; | |
3787 | } | |
3788 | ||
3789 | struct fix_24k_store_info | |
3790 | { | |
3791 | /* Immediate offset, if any, for this store instruction. */ | |
3792 | short off; | |
3793 | /* Alignment required by this store instruction. */ | |
3794 | int align_to; | |
3795 | /* True for register offsets. */ | |
3796 | int register_offset; | |
3797 | }; | |
3798 | ||
3799 | /* Comparison function used by qsort. */ | |
3800 | ||
3801 | static int | |
3802 | fix_24k_sort (const void *a, const void *b) | |
3803 | { | |
3804 | const struct fix_24k_store_info *pos1 = a; | |
3805 | const struct fix_24k_store_info *pos2 = b; | |
3806 | ||
3807 | return (pos1->off - pos2->off); | |
3808 | } | |
3809 | ||
3810 | /* INSN is a store instruction. Try to record the store information | |
3811 | in STINFO. Return false if the information isn't known. */ | |
3812 | ||
3813 | static bfd_boolean | |
3814 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3815 | const struct mips_cl_insn *insn) |
15be625d CM |
3816 | { |
3817 | /* The instruction must have a known offset. */ | |
3818 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3819 | return FALSE; | |
3820 | ||
3821 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3822 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3823 | return TRUE; | |
3824 | } | |
3825 | ||
932d1a1b RS |
3826 | /* Return the number of nops that would be needed to work around the 24k |
3827 | "lost data on stores during refill" errata if instruction INSN | |
3828 | immediately followed the 2 instructions described by HIST. | |
3829 | Ignore hazards that are contained within the first IGNORE | |
3830 | instructions of HIST. | |
3831 | ||
3832 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3833 | for the data cache refills and store data. The following describes | |
3834 | the scenario where the store data could be lost. | |
3835 | ||
3836 | * A data cache miss, due to either a load or a store, causing fill | |
3837 | data to be supplied by the memory subsystem | |
3838 | * The first three doublewords of fill data are returned and written | |
3839 | into the cache | |
3840 | * A sequence of four stores occurs in consecutive cycles around the | |
3841 | final doubleword of the fill: | |
3842 | * Store A | |
3843 | * Store B | |
3844 | * Store C | |
3845 | * Zero, One or more instructions | |
3846 | * Store D | |
3847 | ||
3848 | The four stores A-D must be to different doublewords of the line that | |
3849 | is being filled. The fourth instruction in the sequence above permits | |
3850 | the fill of the final doubleword to be transferred from the FSB into | |
3851 | the cache. In the sequence above, the stores may be either integer | |
3852 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3853 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3854 | different doublewords on the line. If the floating point unit is | |
3855 | running in 1:2 mode, it is not possible to create the sequence above | |
3856 | using only floating point store instructions. | |
15be625d CM |
3857 | |
3858 | In this case, the cache line being filled is incorrectly marked | |
3859 | invalid, thereby losing the data from any store to the line that | |
3860 | occurs between the original miss and the completion of the five | |
3861 | cycle sequence shown above. | |
3862 | ||
932d1a1b | 3863 | The workarounds are: |
15be625d | 3864 | |
932d1a1b RS |
3865 | * Run the data cache in write-through mode. |
3866 | * Insert a non-store instruction between | |
3867 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3868 | |
3869 | static int | |
932d1a1b | 3870 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3871 | const struct mips_cl_insn *insn) |
3872 | { | |
3873 | struct fix_24k_store_info pos[3]; | |
3874 | int align, i, base_offset; | |
3875 | ||
932d1a1b RS |
3876 | if (ignore >= 2) |
3877 | return 0; | |
3878 | ||
ab9794cf RS |
3879 | /* If the previous instruction wasn't a store, there's nothing to |
3880 | worry about. */ | |
15be625d CM |
3881 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3882 | return 0; | |
3883 | ||
ab9794cf RS |
3884 | /* If the instructions after the previous one are unknown, we have |
3885 | to assume the worst. */ | |
3886 | if (!insn) | |
15be625d CM |
3887 | return 1; |
3888 | ||
ab9794cf RS |
3889 | /* Check whether we are dealing with three consecutive stores. */ |
3890 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3891 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3892 | return 0; |
3893 | ||
3894 | /* If we don't know the relationship between the store addresses, | |
3895 | assume the worst. */ | |
ab9794cf | 3896 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3897 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3898 | return 1; | |
3899 | ||
3900 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3901 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3902 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3903 | return 1; | |
3904 | ||
3905 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3906 | ||
3907 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3908 | X bytes and such that the base register + X is known to be aligned | |
3909 | to align bytes. */ | |
3910 | ||
3911 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3912 | align = 8; | |
3913 | else | |
3914 | { | |
3915 | align = pos[0].align_to; | |
3916 | base_offset = pos[0].off; | |
3917 | for (i = 1; i < 3; i++) | |
3918 | if (align < pos[i].align_to) | |
3919 | { | |
3920 | align = pos[i].align_to; | |
3921 | base_offset = pos[i].off; | |
3922 | } | |
3923 | for (i = 0; i < 3; i++) | |
3924 | pos[i].off -= base_offset; | |
3925 | } | |
3926 | ||
3927 | pos[0].off &= ~align + 1; | |
3928 | pos[1].off &= ~align + 1; | |
3929 | pos[2].off &= ~align + 1; | |
3930 | ||
3931 | /* If any two stores write to the same chunk, they also write to the | |
3932 | same doubleword. The offsets are still sorted at this point. */ | |
3933 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3934 | return 0; | |
3935 | ||
3936 | /* A range of at least 9 bytes is needed for the stores to be in | |
3937 | non-overlapping doublewords. */ | |
3938 | if (pos[2].off - pos[0].off <= 8) | |
3939 | return 0; | |
3940 | ||
3941 | if (pos[2].off - pos[1].off >= 24 | |
3942 | || pos[1].off - pos[0].off >= 24 | |
3943 | || pos[2].off - pos[0].off >= 32) | |
3944 | return 0; | |
3945 | ||
3946 | return 1; | |
3947 | } | |
3948 | ||
71400594 | 3949 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3950 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3951 | where HIST[0] is the most recent instruction. Ignore hazards |
3952 | between INSN and the first IGNORE instructions in HIST. | |
3953 | ||
3954 | If INSN is null, return the worse-case number of nops for any | |
3955 | instruction. */ | |
bdaaa2e1 | 3956 | |
71400594 | 3957 | static int |
932d1a1b | 3958 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3959 | const struct mips_cl_insn *insn) |
3960 | { | |
3961 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3962 | |
71400594 | 3963 | nops = 0; |
932d1a1b | 3964 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3965 | { |
91d6fa6a | 3966 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3967 | if (tmp_nops > nops) |
3968 | nops = tmp_nops; | |
3969 | } | |
7d8e00cf | 3970 | |
df58fc94 | 3971 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3972 | { |
932d1a1b | 3973 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3974 | if (tmp_nops > nops) |
3975 | nops = tmp_nops; | |
3976 | } | |
3977 | ||
df58fc94 | 3978 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3979 | { |
932d1a1b | 3980 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3981 | if (tmp_nops > nops) |
3982 | nops = tmp_nops; | |
3983 | } | |
3984 | ||
71400594 RS |
3985 | return nops; |
3986 | } | |
252b5132 | 3987 | |
71400594 | 3988 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3989 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3990 | would be needed after the extended sequence, ignoring hazards |
3991 | in the first IGNORE instructions. */ | |
252b5132 | 3992 | |
71400594 | 3993 | static int |
932d1a1b RS |
3994 | nops_for_sequence (int num_insns, int ignore, |
3995 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3996 | { |
3997 | va_list args; | |
3998 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3999 | struct mips_cl_insn *cursor; | |
4000 | int nops; | |
4001 | ||
91d6fa6a | 4002 | va_start (args, hist); |
71400594 | 4003 | cursor = buffer + num_insns; |
91d6fa6a | 4004 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
4005 | while (cursor > buffer) |
4006 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
4007 | ||
932d1a1b | 4008 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
4009 | va_end (args); |
4010 | return nops; | |
4011 | } | |
252b5132 | 4012 | |
71400594 RS |
4013 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
4014 | worst-case delay for the branch target. */ | |
252b5132 | 4015 | |
71400594 | 4016 | static int |
932d1a1b | 4017 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
4018 | const struct mips_cl_insn *insn) |
4019 | { | |
4020 | int nops, tmp_nops; | |
60b63b72 | 4021 | |
932d1a1b | 4022 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 4023 | if (delayed_branch_p (insn)) |
71400594 | 4024 | { |
932d1a1b | 4025 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 4026 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
4027 | if (tmp_nops > nops) |
4028 | nops = tmp_nops; | |
4029 | } | |
11625dd8 | 4030 | else if (compact_branch_p (insn)) |
71400594 | 4031 | { |
932d1a1b | 4032 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
4033 | if (tmp_nops > nops) |
4034 | nops = tmp_nops; | |
4035 | } | |
4036 | return nops; | |
4037 | } | |
4038 | ||
c67a084a NC |
4039 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
4040 | ||
4041 | static void | |
4042 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
4043 | { | |
df58fc94 | 4044 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4045 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
4046 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
4047 | } | |
4048 | ||
4049 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
4050 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
4051 | ||
4052 | static void | |
4053 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
4054 | { | |
df58fc94 | 4055 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4056 | if (strcmp (ip->insn_mo->name, "j") == 0 |
4057 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
4058 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
4059 | { | |
4060 | int sreg; | |
4061 | expressionS ep; | |
4062 | ||
4063 | if (! mips_opts.at) | |
4064 | return; | |
4065 | ||
df58fc94 | 4066 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
4067 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
4068 | return; | |
4069 | ||
4070 | ep.X_op = O_constant; | |
4071 | ep.X_add_number = 0xcfff0000; | |
4072 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
4073 | ep.X_add_number = 0xffff; | |
4074 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
4075 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
4076 | } | |
4077 | } | |
4078 | ||
4079 | static void | |
4080 | fix_loongson2f (struct mips_cl_insn * ip) | |
4081 | { | |
4082 | if (mips_fix_loongson2f_nop) | |
4083 | fix_loongson2f_nop (ip); | |
4084 | ||
4085 | if (mips_fix_loongson2f_jump) | |
4086 | fix_loongson2f_jump (ip); | |
4087 | } | |
4088 | ||
a4e06468 RS |
4089 | /* IP is a branch that has a delay slot, and we need to fill it |
4090 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
4091 | with the previous instruction. |
4092 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4093 | RELOC_TYPE. */ | |
a4e06468 RS |
4094 | |
4095 | static bfd_boolean | |
e407c74b NC |
4096 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
4097 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 4098 | { |
2b0c8b40 | 4099 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
4100 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
4101 | ||
4102 | /* -O2 and above is required for this optimization. */ | |
4103 | if (mips_optimize < 2) | |
4104 | return FALSE; | |
4105 | ||
4106 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
4107 | if (mips_opts.nomove) | |
4108 | return FALSE; | |
4109 | ||
4110 | /* We can't swap if the previous instruction's position is fixed. */ | |
4111 | if (history[0].fixed_p) | |
4112 | return FALSE; | |
4113 | ||
4114 | /* If the previous previous insn was in a .set noreorder, we can't | |
4115 | swap. Actually, the MIPS assembler will swap in this situation. | |
4116 | However, gcc configured -with-gnu-as will generate code like | |
4117 | ||
4118 | .set noreorder | |
4119 | lw $4,XXX | |
4120 | .set reorder | |
4121 | INSN | |
4122 | bne $4,$0,foo | |
4123 | ||
4124 | in which we can not swap the bne and INSN. If gcc is not configured | |
4125 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
4126 | if (history[1].noreorder_p) | |
4127 | return FALSE; | |
4128 | ||
87333bb7 MR |
4129 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
4130 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
4131 | if (mips_opts.mips16 && history[0].fixp[0]) |
4132 | return FALSE; | |
4133 | ||
4134 | /* If the branch is itself the target of a branch, we can not swap. | |
4135 | We cheat on this; all we check for is whether there is a label on | |
4136 | this instruction. If there are any branches to anything other than | |
4137 | a label, users must use .set noreorder. */ | |
4138 | if (seg_info (now_seg)->label_list) | |
4139 | return FALSE; | |
4140 | ||
4141 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 4142 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
4143 | MIPS16 code, which uses variant frags for different purposes. */ |
4144 | if (!mips_opts.mips16 | |
a4e06468 RS |
4145 | && history[0].frag |
4146 | && history[0].frag->fr_type == rs_machine_dependent) | |
4147 | return FALSE; | |
4148 | ||
bcd530a7 RS |
4149 | /* We do not swap with instructions that cannot architecturally |
4150 | be placed in a branch delay slot, such as SYNC or ERET. We | |
4151 | also refrain from swapping with a trap instruction, since it | |
4152 | complicates trap handlers to have the trap instruction be in | |
4153 | a delay slot. */ | |
a4e06468 | 4154 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 4155 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
4156 | return FALSE; |
4157 | ||
4158 | /* Check for conflicts between the branch and the instructions | |
4159 | before the candidate delay slot. */ | |
4160 | if (nops_for_insn (0, history + 1, ip) > 0) | |
4161 | return FALSE; | |
4162 | ||
4163 | /* Check for conflicts between the swapped sequence and the | |
4164 | target of the branch. */ | |
4165 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
4166 | return FALSE; | |
4167 | ||
4168 | /* If the branch reads a register that the previous | |
4169 | instruction sets, we can not swap. */ | |
4170 | gpr_read = gpr_read_mask (ip); | |
4171 | prev_gpr_write = gpr_write_mask (&history[0]); | |
4172 | if (gpr_read & prev_gpr_write) | |
4173 | return FALSE; | |
4174 | ||
4175 | /* If the branch writes a register that the previous | |
4176 | instruction sets, we can not swap. */ | |
4177 | gpr_write = gpr_write_mask (ip); | |
4178 | if (gpr_write & prev_gpr_write) | |
4179 | return FALSE; | |
4180 | ||
4181 | /* If the branch writes a register that the previous | |
4182 | instruction reads, we can not swap. */ | |
4183 | prev_gpr_read = gpr_read_mask (&history[0]); | |
4184 | if (gpr_write & prev_gpr_read) | |
4185 | return FALSE; | |
4186 | ||
4187 | /* If one instruction sets a condition code and the | |
4188 | other one uses a condition code, we can not swap. */ | |
4189 | pinfo = ip->insn_mo->pinfo; | |
4190 | if ((pinfo & INSN_READ_COND_CODE) | |
4191 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
4192 | return FALSE; | |
4193 | if ((pinfo & INSN_WRITE_COND_CODE) | |
4194 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
4195 | return FALSE; | |
4196 | ||
4197 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 4198 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
4199 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
4200 | return FALSE; | |
2b0c8b40 MR |
4201 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
4202 | return FALSE; | |
a4e06468 | 4203 | |
df58fc94 RS |
4204 | /* If the previous instruction has an incorrect size for a fixed |
4205 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
4206 | pinfo2 = ip->insn_mo->pinfo2; |
4207 | if (mips_opts.micromips | |
4208 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
4209 | && insn_length (history) != 2) | |
4210 | return FALSE; | |
4211 | if (mips_opts.micromips | |
4212 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
4213 | && insn_length (history) != 4) | |
4214 | return FALSE; | |
4215 | ||
e407c74b NC |
4216 | /* On R5900 short loops need to be fixed by inserting a nop in |
4217 | the branch delay slots. | |
4218 | A short loop can be terminated too early. */ | |
4219 | if (mips_opts.arch == CPU_R5900 | |
4220 | /* Check if instruction has a parameter, ignore "j $31". */ | |
4221 | && (address_expr != NULL) | |
4222 | /* Parameter must be 16 bit. */ | |
4223 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
4224 | /* Branch to same segment. */ | |
4225 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
4226 | /* Branch to same code fragment. */ | |
4227 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
4228 | /* Can only calculate branch offset if value is known. */ | |
4229 | && symbol_constant_p(address_expr->X_add_symbol) | |
4230 | /* Check if branch is really conditional. */ | |
4231 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
4232 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
4233 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
4234 | { | |
4235 | int distance; | |
4236 | /* Check if loop is shorter than 6 instructions including | |
4237 | branch and delay slot. */ | |
4238 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
4239 | if (distance <= 20) | |
4240 | { | |
4241 | int i; | |
4242 | int rv; | |
4243 | ||
4244 | rv = FALSE; | |
4245 | /* When the loop includes branches or jumps, | |
4246 | it is not a short loop. */ | |
4247 | for (i = 0; i < (distance / 4); i++) | |
4248 | { | |
4249 | if ((history[i].cleared_p) | |
4250 | || delayed_branch_p(&history[i])) | |
4251 | { | |
4252 | rv = TRUE; | |
4253 | break; | |
4254 | } | |
4255 | } | |
4256 | if (rv == FALSE) | |
4257 | { | |
4258 | /* Insert nop after branch to fix short loop. */ | |
4259 | return FALSE; | |
4260 | } | |
4261 | } | |
4262 | } | |
4263 | ||
a4e06468 RS |
4264 | return TRUE; |
4265 | } | |
4266 | ||
e407c74b NC |
4267 | /* Decide how we should add IP to the instruction stream. |
4268 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4269 | RELOC_TYPE. */ | |
a4e06468 RS |
4270 | |
4271 | static enum append_method | |
e407c74b NC |
4272 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
4273 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
4274 | { |
4275 | unsigned long pinfo; | |
4276 | ||
4277 | /* The relaxed version of a macro sequence must be inherently | |
4278 | hazard-free. */ | |
4279 | if (mips_relax.sequence == 2) | |
4280 | return APPEND_ADD; | |
4281 | ||
4282 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4283 | if (mips_opts.noreorder) | |
4284 | return APPEND_ADD; | |
4285 | ||
4286 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4287 | if (delayed_branch_p (ip)) |
a4e06468 | 4288 | { |
e407c74b NC |
4289 | if (!branch_likely_p (ip) |
4290 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4291 | return APPEND_SWAP; |
4292 | ||
11625dd8 | 4293 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4294 | if (mips_opts.mips16 |
4295 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4296 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4297 | return APPEND_ADD_COMPACT; | |
4298 | ||
4299 | return APPEND_ADD_WITH_NOP; | |
4300 | } | |
4301 | ||
a4e06468 RS |
4302 | return APPEND_ADD; |
4303 | } | |
4304 | ||
ceb94aa5 RS |
4305 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4306 | Point IP->insn_mo to the new opcode's definition. */ | |
4307 | ||
4308 | static void | |
4309 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4310 | { | |
4311 | const struct mips_opcode *mo, *end; | |
4312 | ||
4313 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4314 | for (mo = ip->insn_mo; mo < end; mo++) | |
4315 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4316 | { | |
4317 | ip->insn_mo = mo; | |
4318 | return; | |
4319 | } | |
4320 | abort (); | |
4321 | } | |
4322 | ||
df58fc94 RS |
4323 | /* For microMIPS macros, we need to generate a local number label |
4324 | as the target of branches. */ | |
4325 | #define MICROMIPS_LABEL_CHAR '\037' | |
4326 | static unsigned long micromips_target_label; | |
4327 | static char micromips_target_name[32]; | |
4328 | ||
4329 | static char * | |
4330 | micromips_label_name (void) | |
4331 | { | |
4332 | char *p = micromips_target_name; | |
4333 | char symbol_name_temporary[24]; | |
4334 | unsigned long l; | |
4335 | int i; | |
4336 | ||
4337 | if (*p) | |
4338 | return p; | |
4339 | ||
4340 | i = 0; | |
4341 | l = micromips_target_label; | |
4342 | #ifdef LOCAL_LABEL_PREFIX | |
4343 | *p++ = LOCAL_LABEL_PREFIX; | |
4344 | #endif | |
4345 | *p++ = 'L'; | |
4346 | *p++ = MICROMIPS_LABEL_CHAR; | |
4347 | do | |
4348 | { | |
4349 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4350 | l /= 10; | |
4351 | } | |
4352 | while (l != 0); | |
4353 | while (i > 0) | |
4354 | *p++ = symbol_name_temporary[--i]; | |
4355 | *p = '\0'; | |
4356 | ||
4357 | return micromips_target_name; | |
4358 | } | |
4359 | ||
4360 | static void | |
4361 | micromips_label_expr (expressionS *label_expr) | |
4362 | { | |
4363 | label_expr->X_op = O_symbol; | |
4364 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4365 | label_expr->X_add_number = 0; | |
4366 | } | |
4367 | ||
4368 | static void | |
4369 | micromips_label_inc (void) | |
4370 | { | |
4371 | micromips_target_label++; | |
4372 | *micromips_target_name = '\0'; | |
4373 | } | |
4374 | ||
4375 | static void | |
4376 | micromips_add_label (void) | |
4377 | { | |
4378 | symbolS *s; | |
4379 | ||
4380 | s = colon (micromips_label_name ()); | |
4381 | micromips_label_inc (); | |
f3ded42a | 4382 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
4383 | } |
4384 | ||
4385 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4386 | corresponding to the requested one if any. Otherwise return | |
4387 | the reloc unchanged. */ | |
4388 | ||
4389 | static bfd_reloc_code_real_type | |
4390 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4391 | { | |
4392 | static const bfd_reloc_code_real_type relocs[][2] = | |
4393 | { | |
4394 | /* Keep sorted incrementally by the left-hand key. */ | |
4395 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4396 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4397 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4398 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4399 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4400 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4401 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4402 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4403 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4404 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4405 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4406 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4407 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4408 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4409 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4410 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4411 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4412 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4413 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4414 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4415 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4416 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4417 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4418 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4419 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4420 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4421 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4422 | }; | |
4423 | bfd_reloc_code_real_type r; | |
4424 | size_t i; | |
4425 | ||
4426 | if (!mips_opts.micromips) | |
4427 | return reloc; | |
4428 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4429 | { | |
4430 | r = relocs[i][0]; | |
4431 | if (r > reloc) | |
4432 | return reloc; | |
4433 | if (r == reloc) | |
4434 | return relocs[i][1]; | |
4435 | } | |
4436 | return reloc; | |
4437 | } | |
4438 | ||
b886a2ab RS |
4439 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4440 | Return true on success, storing the resolved value in RESULT. */ | |
4441 | ||
4442 | static bfd_boolean | |
4443 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4444 | offsetT *result) | |
4445 | { | |
4446 | switch (reloc) | |
4447 | { | |
4448 | case BFD_RELOC_MIPS_HIGHEST: | |
4449 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4450 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4451 | return TRUE; | |
4452 | ||
4453 | case BFD_RELOC_MIPS_HIGHER: | |
4454 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4455 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4456 | return TRUE; | |
4457 | ||
4458 | case BFD_RELOC_HI16_S: | |
4459 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4460 | case BFD_RELOC_MIPS16_HI16_S: | |
4461 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4462 | return TRUE; | |
4463 | ||
4464 | case BFD_RELOC_HI16: | |
4465 | case BFD_RELOC_MICROMIPS_HI16: | |
4466 | case BFD_RELOC_MIPS16_HI16: | |
4467 | *result = (operand >> 16) & 0xffff; | |
4468 | return TRUE; | |
4469 | ||
4470 | case BFD_RELOC_LO16: | |
4471 | case BFD_RELOC_MICROMIPS_LO16: | |
4472 | case BFD_RELOC_MIPS16_LO16: | |
4473 | *result = operand & 0xffff; | |
4474 | return TRUE; | |
4475 | ||
4476 | case BFD_RELOC_UNUSED: | |
4477 | *result = operand; | |
4478 | return TRUE; | |
4479 | ||
4480 | default: | |
4481 | return FALSE; | |
4482 | } | |
4483 | } | |
4484 | ||
71400594 RS |
4485 | /* Output an instruction. IP is the instruction information. |
4486 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4487 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4488 | a macro expansion. */ | |
71400594 RS |
4489 | |
4490 | static void | |
4491 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4492 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4493 | { |
14fe068b | 4494 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4495 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4496 | enum append_method method; |
2309ddf2 | 4497 | bfd_boolean relax32; |
2b0c8b40 | 4498 | int branch_disp; |
71400594 | 4499 | |
2309ddf2 | 4500 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4501 | fix_loongson2f (ip); |
4502 | ||
738f4d98 | 4503 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4504 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4505 | |
df58fc94 | 4506 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4507 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4508 | |
4509 | if (mips_opts.micromips | |
4510 | && !expansionp | |
4511 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4512 | && micromips_insn_length (ip->insn_mo) != 2) | |
4513 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4514 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4515 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4516 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4517 | |
15be625d CM |
4518 | if (address_expr == NULL) |
4519 | ip->complete_p = 1; | |
b886a2ab RS |
4520 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4521 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4522 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4523 | && address_expr->X_op == O_constant) |
4524 | { | |
15be625d CM |
4525 | switch (*reloc_type) |
4526 | { | |
15be625d | 4527 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4528 | { |
4529 | int shift; | |
4530 | ||
4531 | shift = mips_opts.micromips ? 1 : 2; | |
4532 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4533 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4534 | (unsigned long) address_expr->X_add_number); | |
4535 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4536 | & 0x3ffffff); | |
335574df | 4537 | ip->complete_p = 1; |
df58fc94 | 4538 | } |
15be625d CM |
4539 | break; |
4540 | ||
4541 | case BFD_RELOC_MIPS16_JMP: | |
4542 | if ((address_expr->X_add_number & 3) != 0) | |
4543 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4544 | (unsigned long) address_expr->X_add_number); | |
4545 | ip->insn_opcode |= | |
4546 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4547 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4548 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4549 | ip->complete_p = 1; |
15be625d CM |
4550 | break; |
4551 | ||
4552 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4553 | { |
4554 | int shift; | |
4555 | ||
4556 | shift = mips_opts.micromips ? 1 : 2; | |
4557 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4558 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4559 | (unsigned long) address_expr->X_add_number); | |
4560 | if (!mips_relax_branch) | |
4561 | { | |
4562 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4563 | & ~((1 << (shift + 16)) - 1)) | |
4564 | as_bad (_("branch address range overflow (0x%lx)"), | |
4565 | (unsigned long) address_expr->X_add_number); | |
4566 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4567 | & 0xffff); | |
4568 | } | |
df58fc94 | 4569 | } |
15be625d CM |
4570 | break; |
4571 | ||
4572 | default: | |
b886a2ab RS |
4573 | { |
4574 | offsetT value; | |
4575 | ||
4576 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4577 | &value)) | |
4578 | { | |
4579 | ip->insn_opcode |= value & 0xffff; | |
4580 | ip->complete_p = 1; | |
4581 | } | |
4582 | } | |
4583 | break; | |
4584 | } | |
15be625d CM |
4585 | } |
4586 | ||
71400594 RS |
4587 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4588 | { | |
4589 | /* There are a lot of optimizations we could do that we don't. | |
4590 | In particular, we do not, in general, reorder instructions. | |
4591 | If you use gcc with optimization, it will reorder | |
4592 | instructions and generally do much more optimization then we | |
4593 | do here; repeating all that work in the assembler would only | |
4594 | benefit hand written assembly code, and does not seem worth | |
4595 | it. */ | |
4596 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4597 | ? nops_for_insn (0, history, NULL) |
4598 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4599 | if (nops > 0) |
252b5132 RH |
4600 | { |
4601 | fragS *old_frag; | |
4602 | unsigned long old_frag_offset; | |
4603 | int i; | |
252b5132 RH |
4604 | |
4605 | old_frag = frag_now; | |
4606 | old_frag_offset = frag_now_fix (); | |
4607 | ||
4608 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4609 | add_fixed_insn (NOP_INSN); |
4610 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4611 | |
4612 | if (listing) | |
4613 | { | |
4614 | listing_prev_line (); | |
4615 | /* We may be at the start of a variant frag. In case we | |
4616 | are, make sure there is enough space for the frag | |
4617 | after the frags created by listing_prev_line. The | |
4618 | argument to frag_grow here must be at least as large | |
4619 | as the argument to all other calls to frag_grow in | |
4620 | this file. We don't have to worry about being in the | |
4621 | middle of a variant frag, because the variants insert | |
4622 | all needed nop instructions themselves. */ | |
4623 | frag_grow (40); | |
4624 | } | |
4625 | ||
462427c4 | 4626 | mips_move_text_labels (); |
252b5132 RH |
4627 | |
4628 | #ifndef NO_ECOFF_DEBUGGING | |
4629 | if (ECOFF_DEBUGGING) | |
4630 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4631 | #endif | |
4632 | } | |
71400594 RS |
4633 | } |
4634 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4635 | { | |
932d1a1b RS |
4636 | int nops; |
4637 | ||
4638 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4639 | ignoring hazards generated by the first prev_nop_frag_since | |
4640 | instructions. */ | |
4641 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4642 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4643 | |
71400594 RS |
4644 | /* Enforce NOPS as a minimum. */ |
4645 | if (nops > prev_nop_frag_required) | |
4646 | prev_nop_frag_required = nops; | |
252b5132 | 4647 | |
71400594 RS |
4648 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4649 | { | |
4650 | /* Settle for the current number of nops. Update the history | |
4651 | accordingly (for the benefit of any future .set reorder code). */ | |
4652 | prev_nop_frag = NULL; | |
4653 | insert_into_history (prev_nop_frag_since, | |
4654 | prev_nop_frag_holds, NOP_INSN); | |
4655 | } | |
4656 | else | |
4657 | { | |
4658 | /* Allow this instruction to replace one of the nops that was | |
4659 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4660 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4661 | prev_nop_frag_holds--; |
4662 | prev_nop_frag_since++; | |
252b5132 RH |
4663 | } |
4664 | } | |
4665 | ||
e407c74b | 4666 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4667 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4668 | |
e410add4 RS |
4669 | dwarf2_emit_insn (0); |
4670 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4671 | so "move" the instruction address accordingly. | |
4672 | ||
4673 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4674 | entries. If this instruction is a branch that we are going to swap | |
4675 | with the previous instruction, the two instructions should be | |
4676 | treated as a unit, and the debug information for both instructions | |
4677 | should refer to the start of the branch sequence. Using the | |
4678 | current position is certainly wrong when swapping a 32-bit branch | |
4679 | and a 16-bit delay slot, since the current position would then be | |
4680 | in the middle of a branch. */ | |
4681 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 4682 | |
df58fc94 RS |
4683 | relax32 = (mips_relax_branch |
4684 | /* Don't try branch relaxation within .set nomacro, or within | |
4685 | .set noat if we use $at for PIC computations. If it turns | |
4686 | out that the branch was out-of-range, we'll get an error. */ | |
4687 | && !mips_opts.warn_about_macros | |
4688 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4689 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4690 | as they have no complementing branches. */ | |
4691 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4692 | |
4693 | if (!HAVE_CODE_COMPRESSION | |
4694 | && address_expr | |
4695 | && relax32 | |
0b25d3e6 | 4696 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4697 | && delayed_branch_p (ip)) |
4a6a3df4 | 4698 | { |
895921c9 | 4699 | relaxed_branch = TRUE; |
1e915849 RS |
4700 | add_relaxed_insn (ip, (relaxed_branch_length |
4701 | (NULL, NULL, | |
11625dd8 RS |
4702 | uncond_branch_p (ip) ? -1 |
4703 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4704 | : 0)), 4, |
4705 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4706 | (AT, |
11625dd8 RS |
4707 | uncond_branch_p (ip), |
4708 | branch_likely_p (ip), | |
1e915849 RS |
4709 | pinfo & INSN_WRITE_GPR_31, |
4710 | 0), | |
4711 | address_expr->X_add_symbol, | |
4712 | address_expr->X_add_number); | |
4a6a3df4 AO |
4713 | *reloc_type = BFD_RELOC_UNUSED; |
4714 | } | |
df58fc94 RS |
4715 | else if (mips_opts.micromips |
4716 | && address_expr | |
4717 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4718 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4719 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4720 | /* Don't try branch relaxation when users specify | |
4721 | 16-bit/32-bit instructions. */ | |
4722 | && !forced_insn_length) | |
df58fc94 RS |
4723 | { |
4724 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4725 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4726 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4727 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4728 | int al = pinfo & INSN_WRITE_GPR_31; |
4729 | int length32; | |
4730 | ||
4731 | gas_assert (address_expr != NULL); | |
4732 | gas_assert (!mips_relax.sequence); | |
4733 | ||
2b0c8b40 | 4734 | relaxed_branch = TRUE; |
df58fc94 RS |
4735 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4736 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4737 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4738 | relax32, 0, 0), | |
df58fc94 RS |
4739 | address_expr->X_add_symbol, |
4740 | address_expr->X_add_number); | |
4741 | *reloc_type = BFD_RELOC_UNUSED; | |
4742 | } | |
4743 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4744 | { |
4745 | /* We need to set up a variant frag. */ | |
df58fc94 | 4746 | gas_assert (address_expr != NULL); |
1e915849 RS |
4747 | add_relaxed_insn (ip, 4, 0, |
4748 | RELAX_MIPS16_ENCODE | |
4749 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4750 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4751 | delayed_branch_p (&history[0]), |
1e915849 RS |
4752 | history[0].mips16_absolute_jump_p), |
4753 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4754 | } |
5c04167a | 4755 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4756 | { |
11625dd8 | 4757 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4758 | /* Make sure there is enough room to swap this instruction with |
4759 | a following jump instruction. */ | |
4760 | frag_grow (6); | |
1e915849 | 4761 | add_fixed_insn (ip); |
252b5132 RH |
4762 | } |
4763 | else | |
4764 | { | |
4765 | if (mips_opts.mips16 | |
4766 | && mips_opts.noreorder | |
11625dd8 | 4767 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4768 | as_warn (_("extended instruction in delay slot")); |
4769 | ||
4d7206a2 RS |
4770 | if (mips_relax.sequence) |
4771 | { | |
4772 | /* If we've reached the end of this frag, turn it into a variant | |
4773 | frag and record the information for the instructions we've | |
4774 | written so far. */ | |
4775 | if (frag_room () < 4) | |
4776 | relax_close_frag (); | |
df58fc94 | 4777 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4778 | } |
4779 | ||
584892a6 | 4780 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4781 | { |
4782 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4783 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4784 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4785 | mips_macro_warning.insns[0]++; | |
4786 | } | |
584892a6 | 4787 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4788 | { |
4789 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4790 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4791 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4792 | mips_macro_warning.insns[1]++; | |
4793 | } | |
584892a6 | 4794 | |
1e915849 RS |
4795 | if (mips_opts.mips16) |
4796 | { | |
4797 | ip->fixed_p = 1; | |
4798 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4799 | } | |
4800 | add_fixed_insn (ip); | |
252b5132 RH |
4801 | } |
4802 | ||
9fe77896 | 4803 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4804 | { |
df58fc94 | 4805 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4806 | reloc_howto_type *howto0; |
9fe77896 RS |
4807 | reloc_howto_type *howto; |
4808 | int i; | |
34ce925e | 4809 | |
df58fc94 RS |
4810 | /* Perform any necessary conversion to microMIPS relocations |
4811 | and find out how many relocations there actually are. */ | |
4812 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4813 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4814 | ||
9fe77896 RS |
4815 | /* In a compound relocation, it is the final (outermost) |
4816 | operator that determines the relocated field. */ | |
2309ddf2 | 4817 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
4818 | if (!howto) |
4819 | abort (); | |
2309ddf2 MR |
4820 | |
4821 | if (i > 1) | |
4822 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4823 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4824 | bfd_get_reloc_size (howto), | |
4825 | address_expr, | |
2309ddf2 MR |
4826 | howto0 && howto0->pc_relative, |
4827 | final_type[0]); | |
9fe77896 RS |
4828 | |
4829 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4830 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4831 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4832 | ||
4833 | /* These relocations can have an addend that won't fit in | |
4834 | 4 octets for 64bit assembly. */ | |
4835 | if (HAVE_64BIT_GPRS | |
4836 | && ! howto->partial_inplace | |
4837 | && (reloc_type[0] == BFD_RELOC_16 | |
4838 | || reloc_type[0] == BFD_RELOC_32 | |
4839 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4840 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4841 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4842 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4843 | || reloc_type[0] == BFD_RELOC_64 | |
4844 | || reloc_type[0] == BFD_RELOC_CTOR | |
4845 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4846 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4847 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4848 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4849 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4850 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4851 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4852 | || hi16_reloc_p (reloc_type[0]) | |
4853 | || lo16_reloc_p (reloc_type[0]))) | |
4854 | ip->fixp[0]->fx_no_overflow = 1; | |
4855 | ||
ddaf2c41 MR |
4856 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4857 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4858 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4859 | ip->fixp[0]->fx_no_overflow = 1; | |
4860 | ||
9fe77896 RS |
4861 | if (mips_relax.sequence) |
4862 | { | |
4863 | if (mips_relax.first_fixup == 0) | |
4864 | mips_relax.first_fixup = ip->fixp[0]; | |
4865 | } | |
4866 | else if (reloc_needs_lo_p (*reloc_type)) | |
4867 | { | |
4868 | struct mips_hi_fixup *hi_fixup; | |
4869 | ||
4870 | /* Reuse the last entry if it already has a matching %lo. */ | |
4871 | hi_fixup = mips_hi_fixup_list; | |
4872 | if (hi_fixup == 0 | |
4873 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4874 | { |
9fe77896 RS |
4875 | hi_fixup = ((struct mips_hi_fixup *) |
4876 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4877 | hi_fixup->next = mips_hi_fixup_list; | |
4878 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4879 | } |
9fe77896 RS |
4880 | hi_fixup->fixp = ip->fixp[0]; |
4881 | hi_fixup->seg = now_seg; | |
4882 | } | |
252b5132 | 4883 | |
9fe77896 RS |
4884 | /* Add fixups for the second and third relocations, if given. |
4885 | Note that the ABI allows the second relocation to be | |
4886 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4887 | moment we only use RSS_UNDEF, but we could add support | |
4888 | for the others if it ever becomes necessary. */ | |
4889 | for (i = 1; i < 3; i++) | |
4890 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4891 | { | |
4892 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4893 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4894 | FALSE, final_type[i]); |
f6688943 | 4895 | |
9fe77896 RS |
4896 | /* Use fx_tcbit to mark compound relocs. */ |
4897 | ip->fixp[0]->fx_tcbit = 1; | |
4898 | ip->fixp[i]->fx_tcbit = 1; | |
4899 | } | |
252b5132 | 4900 | } |
1e915849 | 4901 | install_insn (ip); |
252b5132 RH |
4902 | |
4903 | /* Update the register mask information. */ | |
4c260379 RS |
4904 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4905 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4906 | |
a4e06468 | 4907 | switch (method) |
252b5132 | 4908 | { |
a4e06468 RS |
4909 | case APPEND_ADD: |
4910 | insert_into_history (0, 1, ip); | |
4911 | break; | |
4912 | ||
4913 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4914 | { |
4915 | struct mips_cl_insn *nop; | |
4916 | ||
4917 | insert_into_history (0, 1, ip); | |
4918 | nop = get_delay_slot_nop (ip); | |
4919 | add_fixed_insn (nop); | |
4920 | insert_into_history (0, 1, nop); | |
4921 | if (mips_relax.sequence) | |
4922 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4923 | } | |
a4e06468 RS |
4924 | break; |
4925 | ||
4926 | case APPEND_ADD_COMPACT: | |
4927 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4928 | gas_assert (mips_opts.mips16); | |
4929 | ip->insn_opcode |= 0x0080; | |
4930 | find_altered_mips16_opcode (ip); | |
4931 | install_insn (ip); | |
4932 | insert_into_history (0, 1, ip); | |
4933 | break; | |
4934 | ||
4935 | case APPEND_SWAP: | |
4936 | { | |
4937 | struct mips_cl_insn delay = history[0]; | |
4938 | if (mips_opts.mips16) | |
4939 | { | |
4940 | know (delay.frag == ip->frag); | |
4941 | move_insn (ip, delay.frag, delay.where); | |
4942 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4943 | } | |
464ab0e5 | 4944 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4945 | { |
4946 | /* Add the delay slot instruction to the end of the | |
4947 | current frag and shrink the fixed part of the | |
4948 | original frag. If the branch occupies the tail of | |
4949 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4950 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4951 | if (delay.frag == ip->frag) |
2b0c8b40 | 4952 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4953 | add_fixed_insn (&delay); |
4954 | } | |
4955 | else | |
4956 | { | |
2b0c8b40 MR |
4957 | move_insn (&delay, ip->frag, |
4958 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4959 | move_insn (ip, history[0].frag, history[0].where); |
4960 | } | |
4961 | history[0] = *ip; | |
4962 | delay.fixed_p = 1; | |
4963 | insert_into_history (0, 1, &delay); | |
4964 | } | |
4965 | break; | |
252b5132 RH |
4966 | } |
4967 | ||
13408f1e | 4968 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4969 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4970 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4971 | { |
4972 | unsigned int i; | |
4973 | ||
79850f26 | 4974 | mips_no_prev_insn (); |
13408f1e | 4975 | |
e407c74b | 4976 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4977 | history[i].cleared_p = 1; |
e407c74b NC |
4978 | } |
4979 | ||
df58fc94 RS |
4980 | /* We need to emit a label at the end of branch-likely macros. */ |
4981 | if (emit_branch_likely_macro) | |
4982 | { | |
4983 | emit_branch_likely_macro = FALSE; | |
4984 | micromips_add_label (); | |
4985 | } | |
4986 | ||
252b5132 RH |
4987 | /* We just output an insn, so the next one doesn't have a label. */ |
4988 | mips_clear_insn_labels (); | |
252b5132 RH |
4989 | } |
4990 | ||
e407c74b NC |
4991 | /* Forget that there was any previous instruction or label. |
4992 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4993 | |
4994 | static void | |
7d10b47d | 4995 | mips_no_prev_insn (void) |
252b5132 | 4996 | { |
7d10b47d RS |
4997 | prev_nop_frag = NULL; |
4998 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4999 | mips_clear_insn_labels (); |
5000 | } | |
5001 | ||
7d10b47d RS |
5002 | /* This function must be called before we emit something other than |
5003 | instructions. It is like mips_no_prev_insn except that it inserts | |
5004 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 5005 | |
7d10b47d RS |
5006 | void |
5007 | mips_emit_delays (void) | |
252b5132 RH |
5008 | { |
5009 | if (! mips_opts.noreorder) | |
5010 | { | |
932d1a1b | 5011 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
5012 | if (nops > 0) |
5013 | { | |
7d10b47d RS |
5014 | while (nops-- > 0) |
5015 | add_fixed_insn (NOP_INSN); | |
462427c4 | 5016 | mips_move_text_labels (); |
7d10b47d RS |
5017 | } |
5018 | } | |
5019 | mips_no_prev_insn (); | |
5020 | } | |
5021 | ||
5022 | /* Start a (possibly nested) noreorder block. */ | |
5023 | ||
5024 | static void | |
5025 | start_noreorder (void) | |
5026 | { | |
5027 | if (mips_opts.noreorder == 0) | |
5028 | { | |
5029 | unsigned int i; | |
5030 | int nops; | |
5031 | ||
5032 | /* None of the instructions before the .set noreorder can be moved. */ | |
5033 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
5034 | history[i].fixed_p = 1; | |
5035 | ||
5036 | /* Insert any nops that might be needed between the .set noreorder | |
5037 | block and the previous instructions. We will later remove any | |
5038 | nops that turn out not to be needed. */ | |
932d1a1b | 5039 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
5040 | if (nops > 0) |
5041 | { | |
5042 | if (mips_optimize != 0) | |
252b5132 RH |
5043 | { |
5044 | /* Record the frag which holds the nop instructions, so | |
5045 | that we can remove them if we don't need them. */ | |
df58fc94 | 5046 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
5047 | prev_nop_frag = frag_now; |
5048 | prev_nop_frag_holds = nops; | |
5049 | prev_nop_frag_required = 0; | |
5050 | prev_nop_frag_since = 0; | |
5051 | } | |
5052 | ||
5053 | for (; nops > 0; --nops) | |
1e915849 | 5054 | add_fixed_insn (NOP_INSN); |
252b5132 | 5055 | |
7d10b47d RS |
5056 | /* Move on to a new frag, so that it is safe to simply |
5057 | decrease the size of prev_nop_frag. */ | |
5058 | frag_wane (frag_now); | |
5059 | frag_new (0); | |
462427c4 | 5060 | mips_move_text_labels (); |
252b5132 | 5061 | } |
df58fc94 | 5062 | mips_mark_labels (); |
7d10b47d | 5063 | mips_clear_insn_labels (); |
252b5132 | 5064 | } |
7d10b47d RS |
5065 | mips_opts.noreorder++; |
5066 | mips_any_noreorder = 1; | |
5067 | } | |
252b5132 | 5068 | |
7d10b47d | 5069 | /* End a nested noreorder block. */ |
252b5132 | 5070 | |
7d10b47d RS |
5071 | static void |
5072 | end_noreorder (void) | |
5073 | { | |
5074 | mips_opts.noreorder--; | |
5075 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
5076 | { | |
5077 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
5078 | handling nop insertion the .set reorder way. */ | |
5079 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 5080 | * NOP_INSN_SIZE); |
7d10b47d RS |
5081 | insert_into_history (prev_nop_frag_since, |
5082 | prev_nop_frag_required, NOP_INSN); | |
5083 | prev_nop_frag = NULL; | |
5084 | } | |
252b5132 RH |
5085 | } |
5086 | ||
584892a6 RS |
5087 | /* Set up global variables for the start of a new macro. */ |
5088 | ||
5089 | static void | |
5090 | macro_start (void) | |
5091 | { | |
5092 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
5093 | memset (&mips_macro_warning.first_insn_sizes, 0, |
5094 | sizeof (mips_macro_warning.first_insn_sizes)); | |
5095 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 5096 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 5097 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
5098 | switch (history[0].insn_mo->pinfo2 |
5099 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
5100 | { | |
5101 | case INSN2_BRANCH_DELAY_32BIT: | |
5102 | mips_macro_warning.delay_slot_length = 4; | |
5103 | break; | |
5104 | case INSN2_BRANCH_DELAY_16BIT: | |
5105 | mips_macro_warning.delay_slot_length = 2; | |
5106 | break; | |
5107 | default: | |
5108 | mips_macro_warning.delay_slot_length = 0; | |
5109 | break; | |
5110 | } | |
5111 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
5112 | } |
5113 | ||
df58fc94 RS |
5114 | /* Given that a macro is longer than one instruction or of the wrong size, |
5115 | return the appropriate warning for it. Return null if no warning is | |
5116 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
5117 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
5118 | and RELAX_NOMACRO. */ | |
584892a6 RS |
5119 | |
5120 | static const char * | |
5121 | macro_warning (relax_substateT subtype) | |
5122 | { | |
5123 | if (subtype & RELAX_DELAY_SLOT) | |
5124 | return _("Macro instruction expanded into multiple instructions" | |
5125 | " in a branch delay slot"); | |
5126 | else if (subtype & RELAX_NOMACRO) | |
5127 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
5128 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
5129 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
5130 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
5131 | ? _("Macro instruction expanded into a wrong size instruction" | |
5132 | " in a 16-bit branch delay slot") | |
5133 | : _("Macro instruction expanded into a wrong size instruction" | |
5134 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
5135 | else |
5136 | return 0; | |
5137 | } | |
5138 | ||
5139 | /* Finish up a macro. Emit warnings as appropriate. */ | |
5140 | ||
5141 | static void | |
5142 | macro_end (void) | |
5143 | { | |
df58fc94 RS |
5144 | /* Relaxation warning flags. */ |
5145 | relax_substateT subtype = 0; | |
5146 | ||
5147 | /* Check delay slot size requirements. */ | |
5148 | if (mips_macro_warning.delay_slot_length == 2) | |
5149 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
5150 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 5151 | { |
df58fc94 RS |
5152 | if (mips_macro_warning.delay_slot_length |
5153 | != mips_macro_warning.first_insn_sizes[0]) | |
5154 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
5155 | if (mips_macro_warning.delay_slot_length | |
5156 | != mips_macro_warning.first_insn_sizes[1]) | |
5157 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
5158 | } | |
584892a6 | 5159 | |
df58fc94 RS |
5160 | /* Check instruction count requirements. */ |
5161 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
5162 | { | |
5163 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
5164 | subtype |= RELAX_SECOND_LONGER; |
5165 | if (mips_opts.warn_about_macros) | |
5166 | subtype |= RELAX_NOMACRO; | |
5167 | if (mips_macro_warning.delay_slot_p) | |
5168 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 5169 | } |
584892a6 | 5170 | |
df58fc94 RS |
5171 | /* If both alternatives fail to fill a delay slot correctly, |
5172 | emit the warning now. */ | |
5173 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
5174 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
5175 | { | |
5176 | relax_substateT s; | |
5177 | const char *msg; | |
5178 | ||
5179 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
5180 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
5181 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
5182 | msg = macro_warning (s); | |
5183 | if (msg != NULL) | |
5184 | as_warn ("%s", msg); | |
5185 | subtype &= ~s; | |
5186 | } | |
5187 | ||
5188 | /* If both implementations are longer than 1 instruction, then emit the | |
5189 | warning now. */ | |
5190 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
5191 | { | |
5192 | relax_substateT s; | |
5193 | const char *msg; | |
5194 | ||
5195 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
5196 | msg = macro_warning (s); | |
5197 | if (msg != NULL) | |
5198 | as_warn ("%s", msg); | |
5199 | subtype &= ~s; | |
584892a6 | 5200 | } |
df58fc94 RS |
5201 | |
5202 | /* If any flags still set, then one implementation might need a warning | |
5203 | and the other either will need one of a different kind or none at all. | |
5204 | Pass any remaining flags over to relaxation. */ | |
5205 | if (mips_macro_warning.first_frag != NULL) | |
5206 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
5207 | } |
5208 | ||
df58fc94 RS |
5209 | /* Instruction operand formats used in macros that vary between |
5210 | standard MIPS and microMIPS code. */ | |
5211 | ||
5212 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
5213 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
5214 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
5215 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
5216 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
5217 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
5218 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
5219 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
5220 | ||
5221 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
5222 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
5223 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
5224 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
5225 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
5226 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
5227 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
5228 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
5229 | ||
6e1304d8 RS |
5230 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
5231 | The first argument in *ARGS will be either the code for a single | |
5232 | relocation or -1 followed by the three codes that make up a | |
5233 | composite relocation. */ | |
5234 | ||
5235 | static void | |
5236 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
5237 | { | |
5238 | int i, next; | |
5239 | ||
5240 | next = va_arg (*args, int); | |
5241 | if (next >= 0) | |
5242 | r[0] = (bfd_reloc_code_real_type) next; | |
5243 | else | |
5244 | for (i = 0; i < 3; i++) | |
5245 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
5246 | } | |
5247 | ||
252b5132 RH |
5248 | /* Build an instruction created by a macro expansion. This is passed |
5249 | a pointer to the count of instructions created so far, an | |
5250 | expression, the name of the instruction to build, an operand format | |
5251 | string, and corresponding arguments. */ | |
5252 | ||
252b5132 | 5253 | static void |
67c0d1eb | 5254 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 5255 | { |
df58fc94 | 5256 | const struct mips_opcode *mo = NULL; |
f6688943 | 5257 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
5258 | const struct mips_opcode *amo; |
5259 | struct hash_control *hash; | |
5260 | struct mips_cl_insn insn; | |
252b5132 | 5261 | va_list args; |
252b5132 | 5262 | |
252b5132 | 5263 | va_start (args, fmt); |
252b5132 | 5264 | |
252b5132 RH |
5265 | if (mips_opts.mips16) |
5266 | { | |
03ea81db | 5267 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5268 | va_end (args); |
5269 | return; | |
5270 | } | |
5271 | ||
f6688943 TS |
5272 | r[0] = BFD_RELOC_UNUSED; |
5273 | r[1] = BFD_RELOC_UNUSED; | |
5274 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5275 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5276 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5277 | gas_assert (amo); | |
5278 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5279 | |
df58fc94 | 5280 | do |
8b082fb1 TS |
5281 | { |
5282 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5283 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5284 | We try to match an instruction that fulfils the branch delay | |
5285 | slot instruction length requirement (if any) of the previous | |
5286 | instruction. While doing this we record the first instruction | |
5287 | seen that matches all the other conditions and use it anyway | |
5288 | if the requirement cannot be met; we will issue an appropriate | |
5289 | warning later on. */ | |
5290 | if (strcmp (fmt, amo->args) == 0 | |
5291 | && amo->pinfo != INSN_MACRO | |
5292 | && is_opcode_valid (amo) | |
5293 | && is_size_valid (amo)) | |
5294 | { | |
5295 | if (is_delay_slot_valid (amo)) | |
5296 | { | |
5297 | mo = amo; | |
5298 | break; | |
5299 | } | |
5300 | else if (!mo) | |
5301 | mo = amo; | |
5302 | } | |
8b082fb1 | 5303 | |
df58fc94 RS |
5304 | ++amo; |
5305 | gas_assert (amo->name); | |
252b5132 | 5306 | } |
df58fc94 | 5307 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5308 | |
df58fc94 | 5309 | gas_assert (mo); |
1e915849 | 5310 | create_insn (&insn, mo); |
252b5132 RH |
5311 | for (;;) |
5312 | { | |
5313 | switch (*fmt++) | |
5314 | { | |
5315 | case '\0': | |
5316 | break; | |
5317 | ||
5318 | case ',': | |
5319 | case '(': | |
5320 | case ')': | |
5321 | continue; | |
5322 | ||
5f74bc13 CD |
5323 | case '+': |
5324 | switch (*fmt++) | |
5325 | { | |
5326 | case 'A': | |
5327 | case 'E': | |
df58fc94 RS |
5328 | INSERT_OPERAND (mips_opts.micromips, |
5329 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5330 | continue; |
5331 | ||
5332 | case 'B': | |
5333 | case 'F': | |
5334 | /* Note that in the macro case, these arguments are already | |
5335 | in MSB form. (When handling the instruction in the | |
5336 | non-macro case, these arguments are sizes from which | |
5337 | MSB values must be calculated.) */ | |
df58fc94 RS |
5338 | INSERT_OPERAND (mips_opts.micromips, |
5339 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5340 | continue; |
5341 | ||
b015e599 AP |
5342 | case 'J': |
5343 | gas_assert (!mips_opts.micromips); | |
5344 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5345 | continue; | |
5346 | ||
5f74bc13 CD |
5347 | case 'C': |
5348 | case 'G': | |
5349 | case 'H': | |
5350 | /* Note that in the macro case, these arguments are already | |
5351 | in MSBD form. (When handling the instruction in the | |
5352 | non-macro case, these arguments are sizes from which | |
5353 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5354 | INSERT_OPERAND (mips_opts.micromips, |
5355 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5356 | continue; |
5357 | ||
dd3cbb7e | 5358 | case 'Q': |
df58fc94 RS |
5359 | gas_assert (!mips_opts.micromips); |
5360 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5361 | continue; |
5362 | ||
7f3c4072 CM |
5363 | case 'j': |
5364 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5365 | continue; | |
5366 | ||
5f74bc13 | 5367 | default: |
b37df7c4 | 5368 | abort (); |
5f74bc13 CD |
5369 | } |
5370 | continue; | |
5371 | ||
8b082fb1 | 5372 | case '2': |
03f66e8a | 5373 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5374 | continue; |
5375 | ||
df58fc94 RS |
5376 | case 'n': |
5377 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5378 | case 't': |
5379 | case 'w': | |
5380 | case 'E': | |
df58fc94 | 5381 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5382 | continue; |
5383 | ||
5384 | case 'c': | |
df58fc94 RS |
5385 | gas_assert (!mips_opts.micromips); |
5386 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5387 | continue; |
5388 | ||
252b5132 | 5389 | case 'W': |
df58fc94 RS |
5390 | gas_assert (!mips_opts.micromips); |
5391 | case 'T': | |
5392 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5393 | continue; |
5394 | ||
252b5132 | 5395 | case 'G': |
df58fc94 RS |
5396 | if (mips_opts.micromips) |
5397 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5398 | else | |
5399 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5400 | continue; | |
5401 | ||
af7ee8bf | 5402 | case 'K': |
df58fc94 RS |
5403 | gas_assert (!mips_opts.micromips); |
5404 | case 'd': | |
5405 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5406 | continue; |
5407 | ||
4372b673 | 5408 | case 'U': |
df58fc94 | 5409 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5410 | { |
5411 | int tmp = va_arg (args, int); | |
5412 | ||
df58fc94 RS |
5413 | INSERT_OPERAND (0, RT, insn, tmp); |
5414 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5415 | } |
df58fc94 | 5416 | continue; |
4372b673 | 5417 | |
252b5132 RH |
5418 | case 'V': |
5419 | case 'S': | |
df58fc94 RS |
5420 | gas_assert (!mips_opts.micromips); |
5421 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5422 | continue; |
5423 | ||
5424 | case 'z': | |
5425 | continue; | |
5426 | ||
5427 | case '<': | |
df58fc94 RS |
5428 | INSERT_OPERAND (mips_opts.micromips, |
5429 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5430 | continue; |
5431 | ||
5432 | case 'D': | |
df58fc94 RS |
5433 | gas_assert (!mips_opts.micromips); |
5434 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5435 | continue; |
5436 | ||
5437 | case 'B': | |
df58fc94 RS |
5438 | gas_assert (!mips_opts.micromips); |
5439 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5440 | continue; |
5441 | ||
4372b673 | 5442 | case 'J': |
df58fc94 RS |
5443 | gas_assert (!mips_opts.micromips); |
5444 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5445 | continue; |
5446 | ||
252b5132 | 5447 | case 'q': |
df58fc94 RS |
5448 | gas_assert (!mips_opts.micromips); |
5449 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5450 | continue; |
5451 | ||
5452 | case 'b': | |
5453 | case 's': | |
5454 | case 'r': | |
5455 | case 'v': | |
df58fc94 | 5456 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5457 | continue; |
5458 | ||
5459 | case 'i': | |
5460 | case 'j': | |
6e1304d8 | 5461 | macro_read_relocs (&args, r); |
9c2799c2 | 5462 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5463 | || *r == BFD_RELOC_MIPS_HIGHER |
5464 | || *r == BFD_RELOC_HI16_S | |
5465 | || *r == BFD_RELOC_LO16 | |
5466 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5467 | continue; | |
5468 | ||
5469 | case 'o': | |
5470 | macro_read_relocs (&args, r); | |
252b5132 RH |
5471 | continue; |
5472 | ||
5473 | case 'u': | |
6e1304d8 | 5474 | macro_read_relocs (&args, r); |
9c2799c2 | 5475 | gas_assert (ep != NULL |
90ecf173 MR |
5476 | && (ep->X_op == O_constant |
5477 | || (ep->X_op == O_symbol | |
5478 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5479 | || *r == BFD_RELOC_HI16_S | |
5480 | || *r == BFD_RELOC_HI16 | |
5481 | || *r == BFD_RELOC_GPREL16 | |
5482 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5483 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5484 | continue; |
5485 | ||
5486 | case 'p': | |
9c2799c2 | 5487 | gas_assert (ep != NULL); |
bad36eac | 5488 | |
252b5132 RH |
5489 | /* |
5490 | * This allows macro() to pass an immediate expression for | |
5491 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5492 | * |
5493 | * We don't allow branch relaxation for these branches, as | |
5494 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5495 | */ |
5496 | if (ep->X_op == O_constant) | |
5497 | { | |
df58fc94 RS |
5498 | /* For microMIPS we always use relocations for branches. |
5499 | So we should not resolve immediate values. */ | |
5500 | gas_assert (!mips_opts.micromips); | |
5501 | ||
bad36eac DJ |
5502 | if ((ep->X_add_number & 3) != 0) |
5503 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5504 | (unsigned long) ep->X_add_number); | |
5505 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5506 | as_bad (_("branch address range overflow (0x%lx)"), | |
5507 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5508 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5509 | ep = NULL; | |
5510 | } | |
5511 | else | |
0b25d3e6 | 5512 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5513 | continue; |
5514 | ||
5515 | case 'a': | |
9c2799c2 | 5516 | gas_assert (ep != NULL); |
f6688943 | 5517 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5518 | continue; |
5519 | ||
5520 | case 'C': | |
df58fc94 RS |
5521 | gas_assert (!mips_opts.micromips); |
5522 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5523 | continue; |
5524 | ||
d43b4baf | 5525 | case 'k': |
df58fc94 RS |
5526 | INSERT_OPERAND (mips_opts.micromips, |
5527 | CACHE, insn, va_arg (args, unsigned long)); | |
5528 | continue; | |
5529 | ||
5530 | case '|': | |
5531 | gas_assert (mips_opts.micromips); | |
5532 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5533 | continue; | |
5534 | ||
5535 | case '.': | |
5536 | gas_assert (mips_opts.micromips); | |
5537 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5538 | continue; | |
5539 | ||
dec0624d MR |
5540 | case '\\': |
5541 | INSERT_OPERAND (mips_opts.micromips, | |
5542 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5543 | continue; | |
5544 | ||
df58fc94 | 5545 | case '~': |
dec0624d MR |
5546 | INSERT_OPERAND (mips_opts.micromips, |
5547 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5548 | continue; |
5549 | ||
5550 | case 'N': | |
5551 | gas_assert (mips_opts.micromips); | |
5552 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5553 | continue; | |
5554 | ||
5555 | case 'm': /* Opcode extension character. */ | |
5556 | gas_assert (mips_opts.micromips); | |
5557 | switch (*fmt++) | |
5558 | { | |
5559 | case 'j': | |
5560 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5561 | break; | |
5562 | ||
5563 | case 'p': | |
5564 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5565 | break; | |
5566 | ||
5567 | case 'F': | |
5568 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5569 | break; | |
5570 | ||
5571 | default: | |
b37df7c4 | 5572 | abort (); |
df58fc94 | 5573 | } |
d43b4baf TS |
5574 | continue; |
5575 | ||
252b5132 | 5576 | default: |
b37df7c4 | 5577 | abort (); |
252b5132 RH |
5578 | } |
5579 | break; | |
5580 | } | |
5581 | va_end (args); | |
9c2799c2 | 5582 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5583 | |
df58fc94 | 5584 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5585 | } |
5586 | ||
5587 | static void | |
67c0d1eb | 5588 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5589 | va_list *args) |
252b5132 | 5590 | { |
1e915849 | 5591 | struct mips_opcode *mo; |
252b5132 | 5592 | struct mips_cl_insn insn; |
f6688943 TS |
5593 | bfd_reloc_code_real_type r[3] |
5594 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5595 | |
1e915849 | 5596 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5597 | gas_assert (mo); |
5598 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5599 | |
1e915849 | 5600 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5601 | { |
1e915849 | 5602 | ++mo; |
9c2799c2 NC |
5603 | gas_assert (mo->name); |
5604 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5605 | } |
5606 | ||
1e915849 | 5607 | create_insn (&insn, mo); |
252b5132 RH |
5608 | for (;;) |
5609 | { | |
5610 | int c; | |
5611 | ||
5612 | c = *fmt++; | |
5613 | switch (c) | |
5614 | { | |
5615 | case '\0': | |
5616 | break; | |
5617 | ||
5618 | case ',': | |
5619 | case '(': | |
5620 | case ')': | |
5621 | continue; | |
5622 | ||
5623 | case 'y': | |
5624 | case 'w': | |
03ea81db | 5625 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5626 | continue; |
5627 | ||
5628 | case 'x': | |
5629 | case 'v': | |
03ea81db | 5630 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5631 | continue; |
5632 | ||
5633 | case 'z': | |
03ea81db | 5634 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5635 | continue; |
5636 | ||
5637 | case 'Z': | |
03ea81db | 5638 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5639 | continue; |
5640 | ||
5641 | case '0': | |
5642 | case 'S': | |
5643 | case 'P': | |
5644 | case 'R': | |
5645 | continue; | |
5646 | ||
5647 | case 'X': | |
03ea81db | 5648 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5649 | continue; |
5650 | ||
5651 | case 'Y': | |
5652 | { | |
5653 | int regno; | |
5654 | ||
03ea81db | 5655 | regno = va_arg (*args, int); |
252b5132 | 5656 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5657 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5658 | } |
5659 | continue; | |
5660 | ||
5661 | case '<': | |
5662 | case '>': | |
5663 | case '4': | |
5664 | case '5': | |
5665 | case 'H': | |
5666 | case 'W': | |
5667 | case 'D': | |
5668 | case 'j': | |
5669 | case '8': | |
5670 | case 'V': | |
5671 | case 'C': | |
5672 | case 'U': | |
5673 | case 'k': | |
5674 | case 'K': | |
5675 | case 'p': | |
5676 | case 'q': | |
5677 | { | |
b886a2ab RS |
5678 | offsetT value; |
5679 | ||
9c2799c2 | 5680 | gas_assert (ep != NULL); |
252b5132 RH |
5681 | |
5682 | if (ep->X_op != O_constant) | |
874e8986 | 5683 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5684 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5685 | { |
b886a2ab | 5686 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5687 | ep = NULL; |
f6688943 | 5688 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5689 | } |
5690 | } | |
5691 | continue; | |
5692 | ||
5693 | case '6': | |
03ea81db | 5694 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5695 | continue; |
5696 | } | |
5697 | ||
5698 | break; | |
5699 | } | |
5700 | ||
9c2799c2 | 5701 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5702 | |
df58fc94 | 5703 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5704 | } |
5705 | ||
2051e8c4 MR |
5706 | /* |
5707 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5708 | * higher bits unset. | |
5709 | */ | |
9f872bbe | 5710 | static void |
2051e8c4 MR |
5711 | normalize_constant_expr (expressionS *ex) |
5712 | { | |
9ee2a2d4 | 5713 | if (ex->X_op == O_constant |
2051e8c4 MR |
5714 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5715 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5716 | - 0x80000000); | |
5717 | } | |
5718 | ||
5719 | /* | |
5720 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5721 | * all higher bits unset. | |
5722 | */ | |
5723 | static void | |
5724 | normalize_address_expr (expressionS *ex) | |
5725 | { | |
5726 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5727 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5728 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5729 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5730 | - 0x80000000); | |
5731 | } | |
5732 | ||
438c16b8 TS |
5733 | /* |
5734 | * Generate a "jalr" instruction with a relocation hint to the called | |
5735 | * function. This occurs in NewABI PIC code. | |
5736 | */ | |
5737 | static void | |
df58fc94 | 5738 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5739 | { |
df58fc94 RS |
5740 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5741 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5742 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5743 | const char *jalr; | |
685736be | 5744 | char *f = NULL; |
b34976b6 | 5745 | |
1180b5a4 | 5746 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5747 | { |
cc3d92a5 | 5748 | frag_grow (8); |
f21f8242 AO |
5749 | f = frag_more (0); |
5750 | } | |
2906b037 | 5751 | if (mips_opts.micromips) |
df58fc94 RS |
5752 | { |
5753 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5754 | if (MIPS_JALR_HINT_P (ep) |
5755 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5756 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5757 | else | |
5758 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5759 | } | |
2906b037 MR |
5760 | else |
5761 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5762 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5763 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5764 | } |
5765 | ||
252b5132 RH |
5766 | /* |
5767 | * Generate a "lui" instruction. | |
5768 | */ | |
5769 | static void | |
67c0d1eb | 5770 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5771 | { |
9c2799c2 | 5772 | gas_assert (! mips_opts.mips16); |
252b5132 | 5773 | |
df58fc94 | 5774 | if (ep->X_op != O_constant) |
252b5132 | 5775 | { |
9c2799c2 | 5776 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5777 | /* _gp_disp is a special case, used from s_cpload. |
5778 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5779 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5780 | || (! HAVE_NEWABI |
aa6975fb ILT |
5781 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5782 | || (! mips_in_shared | |
bbe506e8 TS |
5783 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5784 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5785 | } |
5786 | ||
df58fc94 | 5787 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5788 | } |
5789 | ||
885add95 CD |
5790 | /* Generate a sequence of instructions to do a load or store from a constant |
5791 | offset off of a base register (breg) into/from a target register (treg), | |
5792 | using AT if necessary. */ | |
5793 | static void | |
67c0d1eb RS |
5794 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5795 | int treg, int breg, int dbl) | |
885add95 | 5796 | { |
9c2799c2 | 5797 | gas_assert (ep->X_op == O_constant); |
885add95 | 5798 | |
256ab948 | 5799 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5800 | if (!dbl) |
5801 | normalize_constant_expr (ep); | |
256ab948 | 5802 | |
67c1ffbe | 5803 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5804 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5805 | as_warn (_("operand overflow")); |
5806 | ||
5807 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5808 | { | |
5809 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5810 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5811 | } |
5812 | else | |
5813 | { | |
5814 | /* 32-bit offset, need multiple instructions and AT, like: | |
5815 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5816 | addu $tempreg,$tempreg,$breg | |
5817 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5818 | to handle the complete offset. */ | |
67c0d1eb RS |
5819 | macro_build_lui (ep, AT); |
5820 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5821 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5822 | |
741fe287 | 5823 | if (!mips_opts.at) |
8fc2e39e | 5824 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5825 | } |
5826 | } | |
5827 | ||
252b5132 RH |
5828 | /* set_at() |
5829 | * Generates code to set the $at register to true (one) | |
5830 | * if reg is less than the immediate expression. | |
5831 | */ | |
5832 | static void | |
67c0d1eb | 5833 | set_at (int reg, int unsignedp) |
252b5132 RH |
5834 | { |
5835 | if (imm_expr.X_op == O_constant | |
5836 | && imm_expr.X_add_number >= -0x8000 | |
5837 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5838 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5839 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5840 | else |
5841 | { | |
67c0d1eb RS |
5842 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5843 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5844 | } |
5845 | } | |
5846 | ||
5847 | /* Warn if an expression is not a constant. */ | |
5848 | ||
5849 | static void | |
17a2f251 | 5850 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5851 | { |
5852 | if (ex->X_op == O_big) | |
5853 | as_bad (_("unsupported large constant")); | |
5854 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5855 | as_bad (_("Instruction %s requires absolute expression"), |
5856 | ip->insn_mo->name); | |
13757d0c | 5857 | |
9ee2a2d4 MR |
5858 | if (HAVE_32BIT_GPRS) |
5859 | normalize_constant_expr (ex); | |
252b5132 RH |
5860 | } |
5861 | ||
5862 | /* Count the leading zeroes by performing a binary chop. This is a | |
5863 | bulky bit of source, but performance is a LOT better for the | |
5864 | majority of values than a simple loop to count the bits: | |
5865 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5866 | if ((v) & (1 << (31 - lcnt))) | |
5867 | break; | |
5868 | However it is not code size friendly, and the gain will drop a bit | |
5869 | on certain cached systems. | |
5870 | */ | |
5871 | #define COUNT_TOP_ZEROES(v) \ | |
5872 | (((v) & ~0xffff) == 0 \ | |
5873 | ? ((v) & ~0xff) == 0 \ | |
5874 | ? ((v) & ~0xf) == 0 \ | |
5875 | ? ((v) & ~0x3) == 0 \ | |
5876 | ? ((v) & ~0x1) == 0 \ | |
5877 | ? !(v) \ | |
5878 | ? 32 \ | |
5879 | : 31 \ | |
5880 | : 30 \ | |
5881 | : ((v) & ~0x7) == 0 \ | |
5882 | ? 29 \ | |
5883 | : 28 \ | |
5884 | : ((v) & ~0x3f) == 0 \ | |
5885 | ? ((v) & ~0x1f) == 0 \ | |
5886 | ? 27 \ | |
5887 | : 26 \ | |
5888 | : ((v) & ~0x7f) == 0 \ | |
5889 | ? 25 \ | |
5890 | : 24 \ | |
5891 | : ((v) & ~0xfff) == 0 \ | |
5892 | ? ((v) & ~0x3ff) == 0 \ | |
5893 | ? ((v) & ~0x1ff) == 0 \ | |
5894 | ? 23 \ | |
5895 | : 22 \ | |
5896 | : ((v) & ~0x7ff) == 0 \ | |
5897 | ? 21 \ | |
5898 | : 20 \ | |
5899 | : ((v) & ~0x3fff) == 0 \ | |
5900 | ? ((v) & ~0x1fff) == 0 \ | |
5901 | ? 19 \ | |
5902 | : 18 \ | |
5903 | : ((v) & ~0x7fff) == 0 \ | |
5904 | ? 17 \ | |
5905 | : 16 \ | |
5906 | : ((v) & ~0xffffff) == 0 \ | |
5907 | ? ((v) & ~0xfffff) == 0 \ | |
5908 | ? ((v) & ~0x3ffff) == 0 \ | |
5909 | ? ((v) & ~0x1ffff) == 0 \ | |
5910 | ? 15 \ | |
5911 | : 14 \ | |
5912 | : ((v) & ~0x7ffff) == 0 \ | |
5913 | ? 13 \ | |
5914 | : 12 \ | |
5915 | : ((v) & ~0x3fffff) == 0 \ | |
5916 | ? ((v) & ~0x1fffff) == 0 \ | |
5917 | ? 11 \ | |
5918 | : 10 \ | |
5919 | : ((v) & ~0x7fffff) == 0 \ | |
5920 | ? 9 \ | |
5921 | : 8 \ | |
5922 | : ((v) & ~0xfffffff) == 0 \ | |
5923 | ? ((v) & ~0x3ffffff) == 0 \ | |
5924 | ? ((v) & ~0x1ffffff) == 0 \ | |
5925 | ? 7 \ | |
5926 | : 6 \ | |
5927 | : ((v) & ~0x7ffffff) == 0 \ | |
5928 | ? 5 \ | |
5929 | : 4 \ | |
5930 | : ((v) & ~0x3fffffff) == 0 \ | |
5931 | ? ((v) & ~0x1fffffff) == 0 \ | |
5932 | ? 3 \ | |
5933 | : 2 \ | |
5934 | : ((v) & ~0x7fffffff) == 0 \ | |
5935 | ? 1 \ | |
5936 | : 0) | |
5937 | ||
5938 | /* load_register() | |
67c1ffbe | 5939 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5940 | * an absolute expression value into a register. |
5941 | */ | |
5942 | static void | |
67c0d1eb | 5943 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5944 | { |
5945 | int freg; | |
5946 | expressionS hi32, lo32; | |
5947 | ||
5948 | if (ep->X_op != O_big) | |
5949 | { | |
9c2799c2 | 5950 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5951 | |
5952 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5953 | if (!dbl) |
5954 | normalize_constant_expr (ep); | |
256ab948 TS |
5955 | |
5956 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5957 | { |
5958 | /* We can handle 16 bit signed values with an addiu to | |
5959 | $zero. No need to ever use daddiu here, since $zero and | |
5960 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5961 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5962 | return; |
5963 | } | |
5964 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5965 | { | |
5966 | /* We can handle 16 bit unsigned values with an ori to | |
5967 | $zero. */ | |
67c0d1eb | 5968 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5969 | return; |
5970 | } | |
256ab948 | 5971 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5972 | { |
5973 | /* 32 bit values require an lui. */ | |
df58fc94 | 5974 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5975 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5976 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5977 | return; |
5978 | } | |
5979 | } | |
5980 | ||
5981 | /* The value is larger than 32 bits. */ | |
5982 | ||
2051e8c4 | 5983 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5984 | { |
55e08f71 NC |
5985 | char value[32]; |
5986 | ||
5987 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5988 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5989 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5990 | return; |
5991 | } | |
5992 | ||
5993 | if (ep->X_op != O_big) | |
5994 | { | |
5995 | hi32 = *ep; | |
5996 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5997 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5998 | hi32.X_add_number &= 0xffffffff; | |
5999 | lo32 = *ep; | |
6000 | lo32.X_add_number &= 0xffffffff; | |
6001 | } | |
6002 | else | |
6003 | { | |
9c2799c2 | 6004 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
6005 | if (ep->X_add_number == 3) |
6006 | generic_bignum[3] = 0; | |
6007 | else if (ep->X_add_number > 4) | |
6008 | as_bad (_("Number larger than 64 bits")); | |
6009 | lo32.X_op = O_constant; | |
6010 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
6011 | hi32.X_op = O_constant; | |
6012 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
6013 | } | |
6014 | ||
6015 | if (hi32.X_add_number == 0) | |
6016 | freg = 0; | |
6017 | else | |
6018 | { | |
6019 | int shift, bit; | |
6020 | unsigned long hi, lo; | |
6021 | ||
956cd1d6 | 6022 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
6023 | { |
6024 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
6025 | { | |
67c0d1eb | 6026 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6027 | return; |
6028 | } | |
6029 | if (lo32.X_add_number & 0x80000000) | |
6030 | { | |
df58fc94 | 6031 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6032 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 6033 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
6034 | return; |
6035 | } | |
6036 | } | |
252b5132 RH |
6037 | |
6038 | /* Check for 16bit shifted constant. We know that hi32 is | |
6039 | non-zero, so start the mask on the first bit of the hi32 | |
6040 | value. */ | |
6041 | shift = 17; | |
6042 | do | |
beae10d5 KH |
6043 | { |
6044 | unsigned long himask, lomask; | |
6045 | ||
6046 | if (shift < 32) | |
6047 | { | |
6048 | himask = 0xffff >> (32 - shift); | |
6049 | lomask = (0xffff << shift) & 0xffffffff; | |
6050 | } | |
6051 | else | |
6052 | { | |
6053 | himask = 0xffff << (shift - 32); | |
6054 | lomask = 0; | |
6055 | } | |
6056 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
6057 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
6058 | { | |
6059 | expressionS tmp; | |
6060 | ||
6061 | tmp.X_op = O_constant; | |
6062 | if (shift < 32) | |
6063 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
6064 | | (lo32.X_add_number >> shift)); | |
6065 | else | |
6066 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 6067 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 6068 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6069 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6070 | return; |
6071 | } | |
f9419b05 | 6072 | ++shift; |
beae10d5 KH |
6073 | } |
6074 | while (shift <= (64 - 16)); | |
252b5132 RH |
6075 | |
6076 | /* Find the bit number of the lowest one bit, and store the | |
6077 | shifted value in hi/lo. */ | |
6078 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
6079 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
6080 | if (lo != 0) | |
6081 | { | |
6082 | bit = 0; | |
6083 | while ((lo & 1) == 0) | |
6084 | { | |
6085 | lo >>= 1; | |
6086 | ++bit; | |
6087 | } | |
6088 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
6089 | hi >>= bit; | |
6090 | } | |
6091 | else | |
6092 | { | |
6093 | bit = 32; | |
6094 | while ((hi & 1) == 0) | |
6095 | { | |
6096 | hi >>= 1; | |
6097 | ++bit; | |
6098 | } | |
6099 | lo = hi; | |
6100 | hi = 0; | |
6101 | } | |
6102 | ||
6103 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
6104 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
6105 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
6106 | { |
6107 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 6108 | if (shift != 0) |
beae10d5 | 6109 | { |
252b5132 RH |
6110 | expressionS tmp; |
6111 | ||
6112 | /* This instruction will set the register to be all | |
6113 | ones. */ | |
beae10d5 KH |
6114 | tmp.X_op = O_constant; |
6115 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 6116 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6117 | if (bit != 0) |
6118 | { | |
6119 | bit += shift; | |
df58fc94 | 6120 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6121 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 6122 | } |
df58fc94 | 6123 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 6124 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6125 | return; |
6126 | } | |
6127 | } | |
252b5132 RH |
6128 | |
6129 | /* Sign extend hi32 before calling load_register, because we can | |
6130 | generally get better code when we load a sign extended value. */ | |
6131 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 6132 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 6133 | load_register (reg, &hi32, 0); |
252b5132 RH |
6134 | freg = reg; |
6135 | } | |
6136 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
6137 | { | |
6138 | if (freg != 0) | |
6139 | { | |
df58fc94 | 6140 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
6141 | freg = reg; |
6142 | } | |
6143 | } | |
6144 | else | |
6145 | { | |
6146 | expressionS mid16; | |
6147 | ||
956cd1d6 | 6148 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 6149 | { |
df58fc94 RS |
6150 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
6151 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
6152 | return; |
6153 | } | |
252b5132 RH |
6154 | |
6155 | if (freg != 0) | |
6156 | { | |
df58fc94 | 6157 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
6158 | freg = reg; |
6159 | } | |
6160 | mid16 = lo32; | |
6161 | mid16.X_add_number >>= 16; | |
67c0d1eb | 6162 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 6163 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
6164 | freg = reg; |
6165 | } | |
6166 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 6167 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
6168 | } |
6169 | ||
269137b2 TS |
6170 | static inline void |
6171 | load_delay_nop (void) | |
6172 | { | |
6173 | if (!gpr_interlocks) | |
6174 | macro_build (NULL, "nop", ""); | |
6175 | } | |
6176 | ||
252b5132 RH |
6177 | /* Load an address into a register. */ |
6178 | ||
6179 | static void | |
67c0d1eb | 6180 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 6181 | { |
252b5132 RH |
6182 | if (ep->X_op != O_constant |
6183 | && ep->X_op != O_symbol) | |
6184 | { | |
6185 | as_bad (_("expression too complex")); | |
6186 | ep->X_op = O_constant; | |
6187 | } | |
6188 | ||
6189 | if (ep->X_op == O_constant) | |
6190 | { | |
67c0d1eb | 6191 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
6192 | return; |
6193 | } | |
6194 | ||
6195 | if (mips_pic == NO_PIC) | |
6196 | { | |
6197 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 6198 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
6199 | Otherwise we want |
6200 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
6201 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 6202 | If we have an addend, we always use the latter form. |
76b3015f | 6203 | |
d6bc6245 TS |
6204 | With 64bit address space and a usable $at we want |
6205 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6206 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6207 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6208 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
6209 | dsll32 $reg,0 | |
3a482fd5 | 6210 | daddu $reg,$reg,$at |
76b3015f | 6211 | |
c03099e6 | 6212 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
6213 | on superscalar processors. |
6214 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6215 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6216 | dsll $reg,16 | |
6217 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
6218 | dsll $reg,16 | |
6219 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
6220 | |
6221 | For GP relative symbols in 64bit address space we can use | |
6222 | the same sequence as in 32bit address space. */ | |
aed1a261 | 6223 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 6224 | { |
6caf9ef4 TS |
6225 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6226 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
6227 | { | |
6228 | relax_start (ep->X_add_symbol); | |
6229 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
6230 | mips_gp_register, BFD_RELOC_GPREL16); | |
6231 | relax_switch (); | |
6232 | } | |
d6bc6245 | 6233 | |
741fe287 | 6234 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 6235 | { |
df58fc94 RS |
6236 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
6237 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
6238 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6239 | BFD_RELOC_MIPS_HIGHER); | |
6240 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 6241 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 6242 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
6243 | *used_at = 1; |
6244 | } | |
6245 | else | |
6246 | { | |
df58fc94 | 6247 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
6248 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6249 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 6250 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6251 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 6252 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6253 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 6254 | } |
6caf9ef4 TS |
6255 | |
6256 | if (mips_relax.sequence) | |
6257 | relax_end (); | |
d6bc6245 | 6258 | } |
252b5132 RH |
6259 | else |
6260 | { | |
d6bc6245 | 6261 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6262 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 6263 | { |
4d7206a2 | 6264 | relax_start (ep->X_add_symbol); |
67c0d1eb | 6265 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 6266 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6267 | relax_switch (); |
d6bc6245 | 6268 | } |
67c0d1eb RS |
6269 | macro_build_lui (ep, reg); |
6270 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6271 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6272 | if (mips_relax.sequence) |
6273 | relax_end (); | |
d6bc6245 | 6274 | } |
252b5132 | 6275 | } |
0a44bf69 | 6276 | else if (!mips_big_got) |
252b5132 RH |
6277 | { |
6278 | expressionS ex; | |
6279 | ||
6280 | /* If this is a reference to an external symbol, we want | |
6281 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6282 | Otherwise we want | |
6283 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6284 | nop | |
6285 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6286 | If there is a constant, it must be added in after. |
6287 | ||
ed6fb7bd | 6288 | If we have NewABI, we want |
f5040a92 AO |
6289 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6290 | unless we're referencing a global symbol with a non-zero | |
6291 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6292 | if (HAVE_NEWABI) |
6293 | { | |
f5040a92 AO |
6294 | if (ep->X_add_number) |
6295 | { | |
4d7206a2 | 6296 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6297 | ep->X_add_number = 0; |
4d7206a2 | 6298 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6299 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6300 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6301 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6302 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6303 | ex.X_op = O_constant; | |
67c0d1eb | 6304 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6305 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6306 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6307 | relax_switch (); |
f5040a92 | 6308 | } |
67c0d1eb | 6309 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6310 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6311 | if (mips_relax.sequence) |
6312 | relax_end (); | |
ed6fb7bd SC |
6313 | } |
6314 | else | |
6315 | { | |
f5040a92 AO |
6316 | ex.X_add_number = ep->X_add_number; |
6317 | ep->X_add_number = 0; | |
67c0d1eb RS |
6318 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6319 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6320 | load_delay_nop (); |
4d7206a2 RS |
6321 | relax_start (ep->X_add_symbol); |
6322 | relax_switch (); | |
67c0d1eb | 6323 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6324 | BFD_RELOC_LO16); |
4d7206a2 | 6325 | relax_end (); |
ed6fb7bd | 6326 | |
f5040a92 AO |
6327 | if (ex.X_add_number != 0) |
6328 | { | |
6329 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6330 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6331 | ex.X_op = O_constant; | |
67c0d1eb | 6332 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6333 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6334 | } |
252b5132 RH |
6335 | } |
6336 | } | |
0a44bf69 | 6337 | else if (mips_big_got) |
252b5132 RH |
6338 | { |
6339 | expressionS ex; | |
252b5132 RH |
6340 | |
6341 | /* This is the large GOT case. If this is a reference to an | |
6342 | external symbol, we want | |
6343 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6344 | addu $reg,$reg,$gp | |
6345 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6346 | |
6347 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6348 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6349 | nop | |
6350 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6351 | If there is a constant, it must be added in after. |
f5040a92 AO |
6352 | |
6353 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6354 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6355 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6356 | */ |
438c16b8 TS |
6357 | if (HAVE_NEWABI) |
6358 | { | |
4d7206a2 | 6359 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6360 | ep->X_add_number = 0; |
4d7206a2 | 6361 | relax_start (ep->X_add_symbol); |
df58fc94 | 6362 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6364 | reg, reg, mips_gp_register); | |
6365 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6366 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6367 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6368 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6369 | else if (ex.X_add_number) | |
6370 | { | |
6371 | ex.X_op = O_constant; | |
67c0d1eb RS |
6372 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6373 | BFD_RELOC_LO16); | |
f5040a92 AO |
6374 | } |
6375 | ||
6376 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6377 | relax_switch (); |
67c0d1eb | 6378 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6379 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6380 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6381 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6382 | relax_end (); |
438c16b8 | 6383 | } |
252b5132 | 6384 | else |
438c16b8 | 6385 | { |
f5040a92 AO |
6386 | ex.X_add_number = ep->X_add_number; |
6387 | ep->X_add_number = 0; | |
4d7206a2 | 6388 | relax_start (ep->X_add_symbol); |
df58fc94 | 6389 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6390 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6391 | reg, reg, mips_gp_register); | |
6392 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6393 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6394 | relax_switch (); |
6395 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6396 | { |
6397 | /* We need a nop before loading from $gp. This special | |
6398 | check is required because the lui which starts the main | |
6399 | instruction stream does not refer to $gp, and so will not | |
6400 | insert the nop which may be required. */ | |
67c0d1eb | 6401 | macro_build (NULL, "nop", ""); |
438c16b8 | 6402 | } |
67c0d1eb | 6403 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6404 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6405 | load_delay_nop (); |
67c0d1eb | 6406 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6407 | BFD_RELOC_LO16); |
4d7206a2 | 6408 | relax_end (); |
438c16b8 | 6409 | |
f5040a92 AO |
6410 | if (ex.X_add_number != 0) |
6411 | { | |
6412 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6413 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6414 | ex.X_op = O_constant; | |
67c0d1eb RS |
6415 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6416 | BFD_RELOC_LO16); | |
f5040a92 | 6417 | } |
252b5132 RH |
6418 | } |
6419 | } | |
252b5132 RH |
6420 | else |
6421 | abort (); | |
8fc2e39e | 6422 | |
741fe287 | 6423 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6424 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6425 | } |
6426 | ||
ea1fb5dc RS |
6427 | /* Move the contents of register SOURCE into register DEST. */ |
6428 | ||
6429 | static void | |
67c0d1eb | 6430 | move_register (int dest, int source) |
ea1fb5dc | 6431 | { |
df58fc94 RS |
6432 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6433 | instruction specifically requires a 32-bit one. */ | |
6434 | if (mips_opts.micromips | |
6435 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6436 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6437 | else |
6438 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6439 | dest, source, 0); | |
ea1fb5dc RS |
6440 | } |
6441 | ||
4d7206a2 | 6442 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6443 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6444 | The two alternatives are: | |
4d7206a2 RS |
6445 | |
6446 | Global symbol Local sybmol | |
6447 | ------------- ------------ | |
6448 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6449 | ... ... | |
6450 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6451 | ||
6452 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6453 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6454 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6455 | |
6456 | static void | |
67c0d1eb | 6457 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6458 | { |
6459 | expressionS global; | |
6460 | ||
6461 | global = *local; | |
6462 | global.X_add_number = 0; | |
6463 | ||
6464 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6465 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6466 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6467 | relax_switch (); |
67c0d1eb RS |
6468 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6469 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6470 | relax_end (); |
6471 | } | |
6472 | ||
6473 | static void | |
67c0d1eb | 6474 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6475 | { |
6476 | expressionS global; | |
6477 | ||
6478 | global.X_op = O_constant; | |
6479 | global.X_op_symbol = NULL; | |
6480 | global.X_add_symbol = NULL; | |
6481 | global.X_add_number = local->X_add_number; | |
6482 | ||
6483 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6484 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6485 | dest, dest, BFD_RELOC_LO16); |
6486 | relax_switch (); | |
67c0d1eb | 6487 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6488 | relax_end (); |
6489 | } | |
6490 | ||
f6a22291 MR |
6491 | static void |
6492 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6493 | { | |
6494 | expressionS global; | |
6495 | int hold_mips_optimize; | |
6496 | ||
6497 | global.X_op = O_constant; | |
6498 | global.X_op_symbol = NULL; | |
6499 | global.X_add_symbol = NULL; | |
6500 | global.X_add_number = local->X_add_number; | |
6501 | ||
6502 | relax_start (local->X_add_symbol); | |
6503 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6504 | relax_switch (); | |
6505 | /* Set mips_optimize around the lui instruction to avoid | |
6506 | inserting an unnecessary nop after the lw. */ | |
6507 | hold_mips_optimize = mips_optimize; | |
6508 | mips_optimize = 2; | |
6509 | macro_build_lui (&global, tmp); | |
6510 | mips_optimize = hold_mips_optimize; | |
6511 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6512 | relax_end (); | |
6513 | ||
6514 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6515 | } | |
6516 | ||
df58fc94 RS |
6517 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6518 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6519 | is its complementing branch with the original condition negated. | |
6520 | CALL is set if the original branch specified the link operation. | |
6521 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6522 | ||
6523 | Code like this is produced in the noreorder mode: | |
6524 | ||
6525 | BRNEG <args>, 1f | |
6526 | nop | |
6527 | b <sym> | |
6528 | delay slot (executed only if branch taken) | |
6529 | 1: | |
6530 | ||
6531 | or, if CALL is set: | |
6532 | ||
6533 | BRNEG <args>, 1f | |
6534 | nop | |
6535 | bal <sym> | |
6536 | delay slot (executed only if branch taken) | |
6537 | 1: | |
6538 | ||
6539 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6540 | so code produced is simply: | |
6541 | ||
6542 | BR <args>, <sym> | |
6543 | nop | |
6544 | ||
6545 | This function is used when producing code for the microMIPS ASE that | |
6546 | does not implement branch likely instructions in hardware. */ | |
6547 | ||
6548 | static void | |
6549 | macro_build_branch_likely (const char *br, const char *brneg, | |
6550 | int call, expressionS *ep, const char *fmt, | |
6551 | unsigned int sreg, unsigned int treg) | |
6552 | { | |
6553 | int noreorder = mips_opts.noreorder; | |
6554 | expressionS expr1; | |
6555 | ||
6556 | gas_assert (mips_opts.micromips); | |
6557 | start_noreorder (); | |
6558 | if (noreorder) | |
6559 | { | |
6560 | micromips_label_expr (&expr1); | |
6561 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6562 | macro_build (NULL, "nop", ""); | |
6563 | macro_build (ep, call ? "bal" : "b", "p"); | |
6564 | ||
6565 | /* Set to true so that append_insn adds a label. */ | |
6566 | emit_branch_likely_macro = TRUE; | |
6567 | } | |
6568 | else | |
6569 | { | |
6570 | macro_build (ep, br, fmt, sreg, treg); | |
6571 | macro_build (NULL, "nop", ""); | |
6572 | } | |
6573 | end_noreorder (); | |
6574 | } | |
6575 | ||
6576 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6577 | the condition code tested. EP specifies the branch target. */ | |
6578 | ||
6579 | static void | |
6580 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6581 | { | |
6582 | const int call = 0; | |
6583 | const char *brneg; | |
6584 | const char *br; | |
6585 | ||
6586 | switch (type) | |
6587 | { | |
6588 | case M_BC1FL: | |
6589 | br = "bc1f"; | |
6590 | brneg = "bc1t"; | |
6591 | break; | |
6592 | case M_BC1TL: | |
6593 | br = "bc1t"; | |
6594 | brneg = "bc1f"; | |
6595 | break; | |
6596 | case M_BC2FL: | |
6597 | br = "bc2f"; | |
6598 | brneg = "bc2t"; | |
6599 | break; | |
6600 | case M_BC2TL: | |
6601 | br = "bc2t"; | |
6602 | brneg = "bc2f"; | |
6603 | break; | |
6604 | default: | |
6605 | abort (); | |
6606 | } | |
6607 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6608 | } | |
6609 | ||
6610 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6611 | the register tested. EP specifies the branch target. */ | |
6612 | ||
6613 | static void | |
6614 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6615 | { | |
6616 | const char *brneg = NULL; | |
6617 | const char *br; | |
6618 | int call = 0; | |
6619 | ||
6620 | switch (type) | |
6621 | { | |
6622 | case M_BGEZ: | |
6623 | br = "bgez"; | |
6624 | break; | |
6625 | case M_BGEZL: | |
6626 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6627 | brneg = "bltz"; | |
6628 | break; | |
6629 | case M_BGEZALL: | |
6630 | gas_assert (mips_opts.micromips); | |
6631 | br = "bgezals"; | |
6632 | brneg = "bltz"; | |
6633 | call = 1; | |
6634 | break; | |
6635 | case M_BGTZ: | |
6636 | br = "bgtz"; | |
6637 | break; | |
6638 | case M_BGTZL: | |
6639 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6640 | brneg = "blez"; | |
6641 | break; | |
6642 | case M_BLEZ: | |
6643 | br = "blez"; | |
6644 | break; | |
6645 | case M_BLEZL: | |
6646 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6647 | brneg = "bgtz"; | |
6648 | break; | |
6649 | case M_BLTZ: | |
6650 | br = "bltz"; | |
6651 | break; | |
6652 | case M_BLTZL: | |
6653 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6654 | brneg = "bgez"; | |
6655 | break; | |
6656 | case M_BLTZALL: | |
6657 | gas_assert (mips_opts.micromips); | |
6658 | br = "bltzals"; | |
6659 | brneg = "bgez"; | |
6660 | call = 1; | |
6661 | break; | |
6662 | default: | |
6663 | abort (); | |
6664 | } | |
6665 | if (mips_opts.micromips && brneg) | |
6666 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6667 | else | |
6668 | macro_build (ep, br, "s,p", sreg); | |
6669 | } | |
6670 | ||
6671 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6672 | TREG as the registers tested. EP specifies the branch target. */ | |
6673 | ||
6674 | static void | |
6675 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6676 | unsigned int sreg, unsigned int treg) | |
6677 | { | |
6678 | const char *brneg = NULL; | |
6679 | const int call = 0; | |
6680 | const char *br; | |
6681 | ||
6682 | switch (type) | |
6683 | { | |
6684 | case M_BEQ: | |
6685 | case M_BEQ_I: | |
6686 | br = "beq"; | |
6687 | break; | |
6688 | case M_BEQL: | |
6689 | case M_BEQL_I: | |
6690 | br = mips_opts.micromips ? "beq" : "beql"; | |
6691 | brneg = "bne"; | |
6692 | break; | |
6693 | case M_BNE: | |
6694 | case M_BNE_I: | |
6695 | br = "bne"; | |
6696 | break; | |
6697 | case M_BNEL: | |
6698 | case M_BNEL_I: | |
6699 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6700 | brneg = "beq"; | |
6701 | break; | |
6702 | default: | |
6703 | abort (); | |
6704 | } | |
6705 | if (mips_opts.micromips && brneg) | |
6706 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6707 | else | |
6708 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6709 | } | |
6710 | ||
252b5132 RH |
6711 | /* |
6712 | * Build macros | |
6713 | * This routine implements the seemingly endless macro or synthesized | |
6714 | * instructions and addressing modes in the mips assembly language. Many | |
6715 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6716 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6717 | * this verbose method. Others are not simple macros but are more like |
6718 | * optimizing code generation. | |
6719 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6720 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6721 | * The ensuing load upper instructions are ommited. This implies some kind |
6722 | * of global optimization. We currently only optimize within a single macro. | |
6723 | * For many of the load and store macros if the address is specified as a | |
6724 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6725 | * first load register 'at' with zero and use it as the base register. The | |
6726 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6727 | * we're missing. | |
6728 | */ | |
6729 | static void | |
17a2f251 | 6730 | macro (struct mips_cl_insn *ip) |
252b5132 | 6731 | { |
741fe287 MR |
6732 | unsigned int treg, sreg, dreg, breg; |
6733 | unsigned int tempreg; | |
252b5132 | 6734 | int mask; |
43841e91 | 6735 | int used_at = 0; |
df58fc94 | 6736 | expressionS label_expr; |
252b5132 | 6737 | expressionS expr1; |
df58fc94 | 6738 | expressionS *ep; |
252b5132 RH |
6739 | const char *s; |
6740 | const char *s2; | |
6741 | const char *fmt; | |
6742 | int likely = 0; | |
252b5132 | 6743 | int coproc = 0; |
7f3c4072 | 6744 | int offbits = 16; |
1abe91b1 | 6745 | int call = 0; |
df58fc94 RS |
6746 | int jals = 0; |
6747 | int dbl = 0; | |
6748 | int imm = 0; | |
6749 | int ust = 0; | |
6750 | int lp = 0; | |
6751 | int ab = 0; | |
252b5132 RH |
6752 | int off; |
6753 | bfd_reloc_code_real_type r; | |
252b5132 RH |
6754 | int hold_mips_optimize; |
6755 | ||
9c2799c2 | 6756 | gas_assert (! mips_opts.mips16); |
252b5132 | 6757 | |
df58fc94 RS |
6758 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6759 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6760 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6761 | mask = ip->insn_mo->mask; |
6762 | ||
df58fc94 RS |
6763 | label_expr.X_op = O_constant; |
6764 | label_expr.X_op_symbol = NULL; | |
6765 | label_expr.X_add_symbol = NULL; | |
6766 | label_expr.X_add_number = 0; | |
6767 | ||
252b5132 RH |
6768 | expr1.X_op = O_constant; |
6769 | expr1.X_op_symbol = NULL; | |
6770 | expr1.X_add_symbol = NULL; | |
6771 | expr1.X_add_number = 1; | |
6772 | ||
6773 | switch (mask) | |
6774 | { | |
6775 | case M_DABS: | |
6776 | dbl = 1; | |
6777 | case M_ABS: | |
df58fc94 RS |
6778 | /* bgez $a0,1f |
6779 | move v0,$a0 | |
6780 | sub v0,$zero,$a0 | |
6781 | 1: | |
6782 | */ | |
252b5132 | 6783 | |
7d10b47d | 6784 | start_noreorder (); |
252b5132 | 6785 | |
df58fc94 RS |
6786 | if (mips_opts.micromips) |
6787 | micromips_label_expr (&label_expr); | |
6788 | else | |
6789 | label_expr.X_add_number = 8; | |
6790 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6791 | if (dreg == sreg) |
a605d2b3 | 6792 | macro_build (NULL, "nop", ""); |
252b5132 | 6793 | else |
67c0d1eb RS |
6794 | move_register (dreg, sreg); |
6795 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6796 | if (mips_opts.micromips) |
6797 | micromips_add_label (); | |
252b5132 | 6798 | |
7d10b47d | 6799 | end_noreorder (); |
8fc2e39e | 6800 | break; |
252b5132 RH |
6801 | |
6802 | case M_ADD_I: | |
6803 | s = "addi"; | |
6804 | s2 = "add"; | |
6805 | goto do_addi; | |
6806 | case M_ADDU_I: | |
6807 | s = "addiu"; | |
6808 | s2 = "addu"; | |
6809 | goto do_addi; | |
6810 | case M_DADD_I: | |
6811 | dbl = 1; | |
6812 | s = "daddi"; | |
6813 | s2 = "dadd"; | |
df58fc94 RS |
6814 | if (!mips_opts.micromips) |
6815 | goto do_addi; | |
6816 | if (imm_expr.X_op == O_constant | |
6817 | && imm_expr.X_add_number >= -0x200 | |
6818 | && imm_expr.X_add_number < 0x200) | |
6819 | { | |
6820 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6821 | break; | |
6822 | } | |
6823 | goto do_addi_i; | |
252b5132 RH |
6824 | case M_DADDU_I: |
6825 | dbl = 1; | |
6826 | s = "daddiu"; | |
6827 | s2 = "daddu"; | |
6828 | do_addi: | |
6829 | if (imm_expr.X_op == O_constant | |
6830 | && imm_expr.X_add_number >= -0x8000 | |
6831 | && imm_expr.X_add_number < 0x8000) | |
6832 | { | |
67c0d1eb | 6833 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6834 | break; |
252b5132 | 6835 | } |
df58fc94 | 6836 | do_addi_i: |
8fc2e39e | 6837 | used_at = 1; |
67c0d1eb RS |
6838 | load_register (AT, &imm_expr, dbl); |
6839 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6840 | break; |
6841 | ||
6842 | case M_AND_I: | |
6843 | s = "andi"; | |
6844 | s2 = "and"; | |
6845 | goto do_bit; | |
6846 | case M_OR_I: | |
6847 | s = "ori"; | |
6848 | s2 = "or"; | |
6849 | goto do_bit; | |
6850 | case M_NOR_I: | |
6851 | s = ""; | |
6852 | s2 = "nor"; | |
6853 | goto do_bit; | |
6854 | case M_XOR_I: | |
6855 | s = "xori"; | |
6856 | s2 = "xor"; | |
6857 | do_bit: | |
6858 | if (imm_expr.X_op == O_constant | |
6859 | && imm_expr.X_add_number >= 0 | |
6860 | && imm_expr.X_add_number < 0x10000) | |
6861 | { | |
6862 | if (mask != M_NOR_I) | |
67c0d1eb | 6863 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6864 | else |
6865 | { | |
67c0d1eb RS |
6866 | macro_build (&imm_expr, "ori", "t,r,i", |
6867 | treg, sreg, BFD_RELOC_LO16); | |
6868 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6869 | } |
8fc2e39e | 6870 | break; |
252b5132 RH |
6871 | } |
6872 | ||
8fc2e39e | 6873 | used_at = 1; |
67c0d1eb RS |
6874 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6875 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6876 | break; |
6877 | ||
8b082fb1 TS |
6878 | case M_BALIGN: |
6879 | switch (imm_expr.X_add_number) | |
6880 | { | |
6881 | case 0: | |
6882 | macro_build (NULL, "nop", ""); | |
6883 | break; | |
6884 | case 2: | |
6885 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6886 | break; | |
03f66e8a MR |
6887 | case 1: |
6888 | case 3: | |
8b082fb1 | 6889 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6890 | (int) imm_expr.X_add_number); |
8b082fb1 | 6891 | break; |
03f66e8a MR |
6892 | default: |
6893 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6894 | (unsigned long) imm_expr.X_add_number); | |
6895 | break; | |
8b082fb1 TS |
6896 | } |
6897 | break; | |
6898 | ||
df58fc94 RS |
6899 | case M_BC1FL: |
6900 | case M_BC1TL: | |
6901 | case M_BC2FL: | |
6902 | case M_BC2TL: | |
6903 | gas_assert (mips_opts.micromips); | |
6904 | macro_build_branch_ccl (mask, &offset_expr, | |
6905 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6906 | break; | |
6907 | ||
252b5132 | 6908 | case M_BEQ_I: |
252b5132 | 6909 | case M_BEQL_I: |
252b5132 | 6910 | case M_BNE_I: |
252b5132 | 6911 | case M_BNEL_I: |
252b5132 | 6912 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6913 | treg = 0; |
6914 | else | |
252b5132 | 6915 | { |
df58fc94 RS |
6916 | treg = AT; |
6917 | used_at = 1; | |
6918 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6919 | } |
df58fc94 RS |
6920 | /* Fall through. */ |
6921 | case M_BEQL: | |
6922 | case M_BNEL: | |
6923 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6924 | break; |
6925 | ||
6926 | case M_BGEL: | |
6927 | likely = 1; | |
6928 | case M_BGE: | |
6929 | if (treg == 0) | |
df58fc94 RS |
6930 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6931 | else if (sreg == 0) | |
6932 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6933 | else | |
252b5132 | 6934 | { |
df58fc94 RS |
6935 | used_at = 1; |
6936 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6937 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6938 | &offset_expr, AT, ZERO); | |
252b5132 | 6939 | } |
df58fc94 RS |
6940 | break; |
6941 | ||
6942 | case M_BGEZL: | |
6943 | case M_BGEZALL: | |
6944 | case M_BGTZL: | |
6945 | case M_BLEZL: | |
6946 | case M_BLTZL: | |
6947 | case M_BLTZALL: | |
6948 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6949 | break; |
6950 | ||
6951 | case M_BGTL_I: | |
6952 | likely = 1; | |
6953 | case M_BGT_I: | |
90ecf173 | 6954 | /* Check for > max integer. */ |
42429eac | 6955 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
6956 | { |
6957 | do_false: | |
90ecf173 | 6958 | /* Result is always false. */ |
252b5132 | 6959 | if (! likely) |
a605d2b3 | 6960 | macro_build (NULL, "nop", ""); |
252b5132 | 6961 | else |
df58fc94 | 6962 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6963 | break; |
252b5132 RH |
6964 | } |
6965 | if (imm_expr.X_op != O_constant) | |
6966 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6967 | ++imm_expr.X_add_number; |
252b5132 RH |
6968 | /* FALLTHROUGH */ |
6969 | case M_BGE_I: | |
6970 | case M_BGEL_I: | |
6971 | if (mask == M_BGEL_I) | |
6972 | likely = 1; | |
6973 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6974 | { | |
df58fc94 RS |
6975 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6976 | &offset_expr, sreg); | |
8fc2e39e | 6977 | break; |
252b5132 RH |
6978 | } |
6979 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6980 | { | |
df58fc94 RS |
6981 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6982 | &offset_expr, sreg); | |
8fc2e39e | 6983 | break; |
252b5132 | 6984 | } |
42429eac | 6985 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
6986 | { |
6987 | do_true: | |
6988 | /* result is always true */ | |
6989 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6990 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6991 | break; |
252b5132 | 6992 | } |
8fc2e39e | 6993 | used_at = 1; |
67c0d1eb | 6994 | set_at (sreg, 0); |
df58fc94 RS |
6995 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6996 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6997 | break; |
6998 | ||
6999 | case M_BGEUL: | |
7000 | likely = 1; | |
7001 | case M_BGEU: | |
7002 | if (treg == 0) | |
7003 | goto do_true; | |
df58fc94 RS |
7004 | else if (sreg == 0) |
7005 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7006 | &offset_expr, ZERO, treg); | |
7007 | else | |
252b5132 | 7008 | { |
df58fc94 RS |
7009 | used_at = 1; |
7010 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7011 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7012 | &offset_expr, AT, ZERO); | |
252b5132 | 7013 | } |
252b5132 RH |
7014 | break; |
7015 | ||
7016 | case M_BGTUL_I: | |
7017 | likely = 1; | |
7018 | case M_BGTU_I: | |
7019 | if (sreg == 0 | |
ca4e0257 | 7020 | || (HAVE_32BIT_GPRS |
252b5132 | 7021 | && imm_expr.X_op == O_constant |
f01dc953 | 7022 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7023 | goto do_false; |
7024 | if (imm_expr.X_op != O_constant) | |
7025 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7026 | ++imm_expr.X_add_number; |
252b5132 RH |
7027 | /* FALLTHROUGH */ |
7028 | case M_BGEU_I: | |
7029 | case M_BGEUL_I: | |
7030 | if (mask == M_BGEUL_I) | |
7031 | likely = 1; | |
7032 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7033 | goto do_true; | |
df58fc94 RS |
7034 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7035 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7036 | &offset_expr, sreg, ZERO); | |
7037 | else | |
252b5132 | 7038 | { |
df58fc94 RS |
7039 | used_at = 1; |
7040 | set_at (sreg, 1); | |
7041 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7042 | &offset_expr, AT, ZERO); | |
252b5132 | 7043 | } |
252b5132 RH |
7044 | break; |
7045 | ||
7046 | case M_BGTL: | |
7047 | likely = 1; | |
7048 | case M_BGT: | |
7049 | if (treg == 0) | |
df58fc94 RS |
7050 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
7051 | else if (sreg == 0) | |
7052 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
7053 | else | |
252b5132 | 7054 | { |
df58fc94 RS |
7055 | used_at = 1; |
7056 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7057 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7058 | &offset_expr, AT, ZERO); | |
252b5132 | 7059 | } |
252b5132 RH |
7060 | break; |
7061 | ||
7062 | case M_BGTUL: | |
7063 | likely = 1; | |
7064 | case M_BGTU: | |
7065 | if (treg == 0) | |
df58fc94 RS |
7066 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
7067 | &offset_expr, sreg, ZERO); | |
7068 | else if (sreg == 0) | |
7069 | goto do_false; | |
7070 | else | |
252b5132 | 7071 | { |
df58fc94 RS |
7072 | used_at = 1; |
7073 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7074 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7075 | &offset_expr, AT, ZERO); | |
252b5132 | 7076 | } |
252b5132 RH |
7077 | break; |
7078 | ||
7079 | case M_BLEL: | |
7080 | likely = 1; | |
7081 | case M_BLE: | |
7082 | if (treg == 0) | |
df58fc94 RS |
7083 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
7084 | else if (sreg == 0) | |
7085 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
7086 | else | |
252b5132 | 7087 | { |
df58fc94 RS |
7088 | used_at = 1; |
7089 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7090 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7091 | &offset_expr, AT, ZERO); | |
252b5132 | 7092 | } |
252b5132 RH |
7093 | break; |
7094 | ||
7095 | case M_BLEL_I: | |
7096 | likely = 1; | |
7097 | case M_BLE_I: | |
42429eac | 7098 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
7099 | goto do_true; |
7100 | if (imm_expr.X_op != O_constant) | |
7101 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7102 | ++imm_expr.X_add_number; |
252b5132 RH |
7103 | /* FALLTHROUGH */ |
7104 | case M_BLT_I: | |
7105 | case M_BLTL_I: | |
7106 | if (mask == M_BLTL_I) | |
7107 | likely = 1; | |
7108 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
7109 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7110 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7111 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
7112 | else | |
252b5132 | 7113 | { |
df58fc94 RS |
7114 | used_at = 1; |
7115 | set_at (sreg, 0); | |
7116 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7117 | &offset_expr, AT, ZERO); | |
252b5132 | 7118 | } |
252b5132 RH |
7119 | break; |
7120 | ||
7121 | case M_BLEUL: | |
7122 | likely = 1; | |
7123 | case M_BLEU: | |
7124 | if (treg == 0) | |
df58fc94 RS |
7125 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7126 | &offset_expr, sreg, ZERO); | |
7127 | else if (sreg == 0) | |
7128 | goto do_true; | |
7129 | else | |
252b5132 | 7130 | { |
df58fc94 RS |
7131 | used_at = 1; |
7132 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7133 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7134 | &offset_expr, AT, ZERO); | |
252b5132 | 7135 | } |
252b5132 RH |
7136 | break; |
7137 | ||
7138 | case M_BLEUL_I: | |
7139 | likely = 1; | |
7140 | case M_BLEU_I: | |
7141 | if (sreg == 0 | |
ca4e0257 | 7142 | || (HAVE_32BIT_GPRS |
252b5132 | 7143 | && imm_expr.X_op == O_constant |
f01dc953 | 7144 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7145 | goto do_true; |
7146 | if (imm_expr.X_op != O_constant) | |
7147 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7148 | ++imm_expr.X_add_number; |
252b5132 RH |
7149 | /* FALLTHROUGH */ |
7150 | case M_BLTU_I: | |
7151 | case M_BLTUL_I: | |
7152 | if (mask == M_BLTUL_I) | |
7153 | likely = 1; | |
7154 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7155 | goto do_false; | |
df58fc94 RS |
7156 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7157 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7158 | &offset_expr, sreg, ZERO); | |
7159 | else | |
252b5132 | 7160 | { |
df58fc94 RS |
7161 | used_at = 1; |
7162 | set_at (sreg, 1); | |
7163 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7164 | &offset_expr, AT, ZERO); | |
252b5132 | 7165 | } |
252b5132 RH |
7166 | break; |
7167 | ||
7168 | case M_BLTL: | |
7169 | likely = 1; | |
7170 | case M_BLT: | |
7171 | if (treg == 0) | |
df58fc94 RS |
7172 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7173 | else if (sreg == 0) | |
7174 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
7175 | else | |
252b5132 | 7176 | { |
df58fc94 RS |
7177 | used_at = 1; |
7178 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7179 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7180 | &offset_expr, AT, ZERO); | |
252b5132 | 7181 | } |
252b5132 RH |
7182 | break; |
7183 | ||
7184 | case M_BLTUL: | |
7185 | likely = 1; | |
7186 | case M_BLTU: | |
7187 | if (treg == 0) | |
7188 | goto do_false; | |
df58fc94 RS |
7189 | else if (sreg == 0) |
7190 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7191 | &offset_expr, ZERO, treg); | |
7192 | else | |
252b5132 | 7193 | { |
df58fc94 RS |
7194 | used_at = 1; |
7195 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7196 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7197 | &offset_expr, AT, ZERO); | |
252b5132 | 7198 | } |
252b5132 RH |
7199 | break; |
7200 | ||
5f74bc13 CD |
7201 | case M_DEXT: |
7202 | { | |
d5818fca MR |
7203 | /* Use unsigned arithmetic. */ |
7204 | addressT pos; | |
7205 | addressT size; | |
5f74bc13 | 7206 | |
90ecf173 | 7207 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7208 | { |
7209 | as_bad (_("Unsupported large constant")); | |
7210 | pos = size = 1; | |
7211 | } | |
7212 | else | |
7213 | { | |
d5818fca MR |
7214 | pos = imm_expr.X_add_number; |
7215 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7216 | } |
7217 | ||
7218 | if (pos > 63) | |
7219 | { | |
d5818fca | 7220 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7221 | pos = 1; |
7222 | } | |
90ecf173 | 7223 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7224 | { |
7225 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 7226 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7227 | size = 1; |
7228 | } | |
7229 | ||
7230 | if (size <= 32 && pos < 32) | |
7231 | { | |
7232 | s = "dext"; | |
7233 | fmt = "t,r,+A,+C"; | |
7234 | } | |
7235 | else if (size <= 32) | |
7236 | { | |
7237 | s = "dextu"; | |
7238 | fmt = "t,r,+E,+H"; | |
7239 | } | |
7240 | else | |
7241 | { | |
7242 | s = "dextm"; | |
7243 | fmt = "t,r,+A,+G"; | |
7244 | } | |
d5818fca MR |
7245 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7246 | (int) (size - 1)); | |
5f74bc13 | 7247 | } |
8fc2e39e | 7248 | break; |
5f74bc13 CD |
7249 | |
7250 | case M_DINS: | |
7251 | { | |
d5818fca MR |
7252 | /* Use unsigned arithmetic. */ |
7253 | addressT pos; | |
7254 | addressT size; | |
5f74bc13 | 7255 | |
90ecf173 | 7256 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7257 | { |
7258 | as_bad (_("Unsupported large constant")); | |
7259 | pos = size = 1; | |
7260 | } | |
7261 | else | |
7262 | { | |
d5818fca MR |
7263 | pos = imm_expr.X_add_number; |
7264 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7265 | } |
7266 | ||
7267 | if (pos > 63) | |
7268 | { | |
d5818fca | 7269 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7270 | pos = 1; |
7271 | } | |
90ecf173 | 7272 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7273 | { |
7274 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7275 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7276 | size = 1; |
7277 | } | |
7278 | ||
7279 | if (pos < 32 && (pos + size - 1) < 32) | |
7280 | { | |
7281 | s = "dins"; | |
7282 | fmt = "t,r,+A,+B"; | |
7283 | } | |
7284 | else if (pos >= 32) | |
7285 | { | |
7286 | s = "dinsu"; | |
7287 | fmt = "t,r,+E,+F"; | |
7288 | } | |
7289 | else | |
7290 | { | |
7291 | s = "dinsm"; | |
7292 | fmt = "t,r,+A,+F"; | |
7293 | } | |
750bdd57 AS |
7294 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7295 | (int) (pos + size - 1)); | |
5f74bc13 | 7296 | } |
8fc2e39e | 7297 | break; |
5f74bc13 | 7298 | |
252b5132 RH |
7299 | case M_DDIV_3: |
7300 | dbl = 1; | |
7301 | case M_DIV_3: | |
7302 | s = "mflo"; | |
7303 | goto do_div3; | |
7304 | case M_DREM_3: | |
7305 | dbl = 1; | |
7306 | case M_REM_3: | |
7307 | s = "mfhi"; | |
7308 | do_div3: | |
7309 | if (treg == 0) | |
7310 | { | |
7311 | as_warn (_("Divide by zero.")); | |
7312 | if (mips_trap) | |
df58fc94 | 7313 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7314 | else |
df58fc94 | 7315 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7316 | break; |
252b5132 RH |
7317 | } |
7318 | ||
7d10b47d | 7319 | start_noreorder (); |
252b5132 RH |
7320 | if (mips_trap) |
7321 | { | |
df58fc94 | 7322 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7323 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7324 | } |
7325 | else | |
7326 | { | |
df58fc94 RS |
7327 | if (mips_opts.micromips) |
7328 | micromips_label_expr (&label_expr); | |
7329 | else | |
7330 | label_expr.X_add_number = 8; | |
7331 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7332 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7333 | macro_build (NULL, "break", BRK_FMT, 7); |
7334 | if (mips_opts.micromips) | |
7335 | micromips_add_label (); | |
252b5132 RH |
7336 | } |
7337 | expr1.X_add_number = -1; | |
8fc2e39e | 7338 | used_at = 1; |
f6a22291 | 7339 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7340 | if (mips_opts.micromips) |
7341 | micromips_label_expr (&label_expr); | |
7342 | else | |
7343 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7344 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7345 | if (dbl) |
7346 | { | |
7347 | expr1.X_add_number = 1; | |
f6a22291 | 7348 | load_register (AT, &expr1, dbl); |
df58fc94 | 7349 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7350 | } |
7351 | else | |
7352 | { | |
7353 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7354 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7355 | } |
7356 | if (mips_trap) | |
7357 | { | |
df58fc94 | 7358 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7359 | /* We want to close the noreorder block as soon as possible, so |
7360 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7361 | end_noreorder (); |
252b5132 RH |
7362 | } |
7363 | else | |
7364 | { | |
df58fc94 RS |
7365 | if (mips_opts.micromips) |
7366 | micromips_label_expr (&label_expr); | |
7367 | else | |
7368 | label_expr.X_add_number = 8; | |
7369 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7370 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7371 | |
7372 | /* We want to close the noreorder block as soon as possible, so | |
7373 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7374 | end_noreorder (); |
252b5132 | 7375 | |
df58fc94 | 7376 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7377 | } |
df58fc94 RS |
7378 | if (mips_opts.micromips) |
7379 | micromips_add_label (); | |
7380 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7381 | break; |
7382 | ||
7383 | case M_DIV_3I: | |
7384 | s = "div"; | |
7385 | s2 = "mflo"; | |
7386 | goto do_divi; | |
7387 | case M_DIVU_3I: | |
7388 | s = "divu"; | |
7389 | s2 = "mflo"; | |
7390 | goto do_divi; | |
7391 | case M_REM_3I: | |
7392 | s = "div"; | |
7393 | s2 = "mfhi"; | |
7394 | goto do_divi; | |
7395 | case M_REMU_3I: | |
7396 | s = "divu"; | |
7397 | s2 = "mfhi"; | |
7398 | goto do_divi; | |
7399 | case M_DDIV_3I: | |
7400 | dbl = 1; | |
7401 | s = "ddiv"; | |
7402 | s2 = "mflo"; | |
7403 | goto do_divi; | |
7404 | case M_DDIVU_3I: | |
7405 | dbl = 1; | |
7406 | s = "ddivu"; | |
7407 | s2 = "mflo"; | |
7408 | goto do_divi; | |
7409 | case M_DREM_3I: | |
7410 | dbl = 1; | |
7411 | s = "ddiv"; | |
7412 | s2 = "mfhi"; | |
7413 | goto do_divi; | |
7414 | case M_DREMU_3I: | |
7415 | dbl = 1; | |
7416 | s = "ddivu"; | |
7417 | s2 = "mfhi"; | |
7418 | do_divi: | |
7419 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7420 | { | |
7421 | as_warn (_("Divide by zero.")); | |
7422 | if (mips_trap) | |
df58fc94 | 7423 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7424 | else |
df58fc94 | 7425 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7426 | break; |
252b5132 RH |
7427 | } |
7428 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7429 | { | |
7430 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7431 | move_register (dreg, sreg); |
252b5132 | 7432 | else |
c80c840e | 7433 | move_register (dreg, ZERO); |
8fc2e39e | 7434 | break; |
252b5132 RH |
7435 | } |
7436 | if (imm_expr.X_op == O_constant | |
7437 | && imm_expr.X_add_number == -1 | |
7438 | && s[strlen (s) - 1] != 'u') | |
7439 | { | |
7440 | if (strcmp (s2, "mflo") == 0) | |
7441 | { | |
67c0d1eb | 7442 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7443 | } |
7444 | else | |
c80c840e | 7445 | move_register (dreg, ZERO); |
8fc2e39e | 7446 | break; |
252b5132 RH |
7447 | } |
7448 | ||
8fc2e39e | 7449 | used_at = 1; |
67c0d1eb RS |
7450 | load_register (AT, &imm_expr, dbl); |
7451 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7452 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7453 | break; |
7454 | ||
7455 | case M_DIVU_3: | |
7456 | s = "divu"; | |
7457 | s2 = "mflo"; | |
7458 | goto do_divu3; | |
7459 | case M_REMU_3: | |
7460 | s = "divu"; | |
7461 | s2 = "mfhi"; | |
7462 | goto do_divu3; | |
7463 | case M_DDIVU_3: | |
7464 | s = "ddivu"; | |
7465 | s2 = "mflo"; | |
7466 | goto do_divu3; | |
7467 | case M_DREMU_3: | |
7468 | s = "ddivu"; | |
7469 | s2 = "mfhi"; | |
7470 | do_divu3: | |
7d10b47d | 7471 | start_noreorder (); |
252b5132 RH |
7472 | if (mips_trap) |
7473 | { | |
df58fc94 | 7474 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7475 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7476 | /* We want to close the noreorder block as soon as possible, so |
7477 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7478 | end_noreorder (); |
252b5132 RH |
7479 | } |
7480 | else | |
7481 | { | |
df58fc94 RS |
7482 | if (mips_opts.micromips) |
7483 | micromips_label_expr (&label_expr); | |
7484 | else | |
7485 | label_expr.X_add_number = 8; | |
7486 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7487 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7488 | |
7489 | /* We want to close the noreorder block as soon as possible, so | |
7490 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7491 | end_noreorder (); |
df58fc94 RS |
7492 | macro_build (NULL, "break", BRK_FMT, 7); |
7493 | if (mips_opts.micromips) | |
7494 | micromips_add_label (); | |
252b5132 | 7495 | } |
df58fc94 | 7496 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7497 | break; |
252b5132 | 7498 | |
1abe91b1 MR |
7499 | case M_DLCA_AB: |
7500 | dbl = 1; | |
7501 | case M_LCA_AB: | |
7502 | call = 1; | |
7503 | goto do_la; | |
252b5132 RH |
7504 | case M_DLA_AB: |
7505 | dbl = 1; | |
7506 | case M_LA_AB: | |
1abe91b1 | 7507 | do_la: |
252b5132 RH |
7508 | /* Load the address of a symbol into a register. If breg is not |
7509 | zero, we then add a base register to it. */ | |
7510 | ||
3bec30a8 TS |
7511 | if (dbl && HAVE_32BIT_GPRS) |
7512 | as_warn (_("dla used to load 32-bit register")); | |
7513 | ||
90ecf173 | 7514 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7515 | as_warn (_("la used to load 64-bit address")); |
7516 | ||
0c11417f MR |
7517 | if (offset_expr.X_op == O_constant |
7518 | && offset_expr.X_add_number >= -0x8000 | |
7519 | && offset_expr.X_add_number < 0x8000) | |
7520 | { | |
aed1a261 | 7521 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7522 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7523 | break; |
0c11417f MR |
7524 | } |
7525 | ||
741fe287 | 7526 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7527 | { |
7528 | tempreg = AT; | |
7529 | used_at = 1; | |
7530 | } | |
7531 | else | |
7532 | { | |
7533 | tempreg = treg; | |
afdbd6d0 CD |
7534 | } |
7535 | ||
252b5132 RH |
7536 | if (offset_expr.X_op != O_symbol |
7537 | && offset_expr.X_op != O_constant) | |
7538 | { | |
f71d0d44 | 7539 | as_bad (_("Expression too complex")); |
252b5132 RH |
7540 | offset_expr.X_op = O_constant; |
7541 | } | |
7542 | ||
252b5132 | 7543 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7544 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7545 | else if (mips_pic == NO_PIC) |
7546 | { | |
d6bc6245 | 7547 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7548 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7549 | Otherwise we want |
7550 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7551 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7552 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7553 | so we may as well always use the latter form. |
76b3015f | 7554 | |
6caf9ef4 TS |
7555 | With 64bit address space and a usable $at we want |
7556 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7557 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7558 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7559 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7560 | dsll32 $tempreg,0 | |
7561 | daddu $tempreg,$tempreg,$at | |
7562 | ||
7563 | If $at is already in use, we use a path which is suboptimal | |
7564 | on superscalar processors. | |
7565 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7566 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7567 | dsll $tempreg,16 | |
7568 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7569 | dsll $tempreg,16 | |
7570 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7571 | ||
7572 | For GP relative symbols in 64bit address space we can use | |
7573 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7574 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7575 | { |
6caf9ef4 TS |
7576 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7577 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7578 | { | |
7579 | relax_start (offset_expr.X_add_symbol); | |
7580 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7581 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7582 | relax_switch (); | |
7583 | } | |
d6bc6245 | 7584 | |
741fe287 | 7585 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7586 | { |
df58fc94 | 7587 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7588 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7589 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7590 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7591 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7592 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7593 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7594 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7595 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7596 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7597 | used_at = 1; |
7598 | } | |
7599 | else | |
7600 | { | |
df58fc94 | 7601 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7602 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7603 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7604 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7605 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7606 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7607 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7608 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7609 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7610 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7611 | } |
6caf9ef4 TS |
7612 | |
7613 | if (mips_relax.sequence) | |
7614 | relax_end (); | |
98d3f06f KH |
7615 | } |
7616 | else | |
7617 | { | |
7618 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7619 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7620 | { |
4d7206a2 | 7621 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7622 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7623 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7624 | relax_switch (); |
98d3f06f | 7625 | } |
6943caf0 | 7626 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7627 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7628 | macro_build_lui (&offset_expr, tempreg); |
7629 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7630 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7631 | if (mips_relax.sequence) |
7632 | relax_end (); | |
98d3f06f | 7633 | } |
252b5132 | 7634 | } |
0a44bf69 | 7635 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7636 | { |
9117d219 NC |
7637 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7638 | ||
252b5132 RH |
7639 | /* If this is a reference to an external symbol, and there |
7640 | is no constant, we want | |
7641 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7642 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7643 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7644 | For a local symbol, we want |
7645 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7646 | nop | |
7647 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7648 | ||
7649 | If we have a small constant, and this is a reference to | |
7650 | an external symbol, we want | |
7651 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7652 | nop | |
7653 | addiu $tempreg,$tempreg,<constant> | |
7654 | For a local symbol, we want the same instruction | |
7655 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7656 | addiu instruction. | |
7657 | ||
7658 | If we have a large constant, and this is a reference to | |
7659 | an external symbol, we want | |
7660 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7661 | lui $at,<hiconstant> | |
7662 | addiu $at,$at,<loconstant> | |
7663 | addu $tempreg,$tempreg,$at | |
7664 | For a local symbol, we want the same instruction | |
7665 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7666 | addiu instruction. |
ed6fb7bd SC |
7667 | */ |
7668 | ||
4d7206a2 | 7669 | if (offset_expr.X_add_number == 0) |
252b5132 | 7670 | { |
0a44bf69 RS |
7671 | if (mips_pic == SVR4_PIC |
7672 | && breg == 0 | |
7673 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7674 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7675 | ||
7676 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7677 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7678 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7679 | if (breg != 0) |
252b5132 RH |
7680 | { |
7681 | /* We're going to put in an addu instruction using | |
7682 | tempreg, so we may as well insert the nop right | |
7683 | now. */ | |
269137b2 | 7684 | load_delay_nop (); |
252b5132 | 7685 | } |
4d7206a2 | 7686 | relax_switch (); |
67c0d1eb RS |
7687 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7688 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7689 | load_delay_nop (); |
67c0d1eb RS |
7690 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7691 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7692 | relax_end (); |
252b5132 RH |
7693 | /* FIXME: If breg == 0, and the next instruction uses |
7694 | $tempreg, then if this variant case is used an extra | |
7695 | nop will be generated. */ | |
7696 | } | |
4d7206a2 RS |
7697 | else if (offset_expr.X_add_number >= -0x8000 |
7698 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7699 | { |
67c0d1eb | 7700 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7701 | load_delay_nop (); |
67c0d1eb | 7702 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7703 | } |
7704 | else | |
7705 | { | |
4d7206a2 RS |
7706 | expr1.X_add_number = offset_expr.X_add_number; |
7707 | offset_expr.X_add_number = | |
43c0598f | 7708 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7709 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7710 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7711 | /* If we are going to add in a base register, and the |
7712 | target register and the base register are the same, | |
7713 | then we are using AT as a temporary register. Since | |
7714 | we want to load the constant into AT, we add our | |
7715 | current AT (from the global offset table) and the | |
7716 | register into the register now, and pretend we were | |
7717 | not using a base register. */ | |
67c0d1eb | 7718 | if (breg == treg) |
252b5132 | 7719 | { |
269137b2 | 7720 | load_delay_nop (); |
67c0d1eb | 7721 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7722 | treg, AT, breg); |
252b5132 RH |
7723 | breg = 0; |
7724 | tempreg = treg; | |
252b5132 | 7725 | } |
f6a22291 | 7726 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7727 | used_at = 1; |
7728 | } | |
7729 | } | |
0a44bf69 | 7730 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7731 | { |
67c0d1eb | 7732 | int add_breg_early = 0; |
f5040a92 AO |
7733 | |
7734 | /* If this is a reference to an external, and there is no | |
7735 | constant, or local symbol (*), with or without a | |
7736 | constant, we want | |
7737 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7738 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7739 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7740 | ||
7741 | If we have a small constant, and this is a reference to | |
7742 | an external symbol, we want | |
7743 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7744 | addiu $tempreg,$tempreg,<constant> | |
7745 | ||
7746 | If we have a large constant, and this is a reference to | |
7747 | an external symbol, we want | |
7748 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7749 | lui $at,<hiconstant> | |
7750 | addiu $at,$at,<loconstant> | |
7751 | addu $tempreg,$tempreg,$at | |
7752 | ||
7753 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7754 | local symbols, even though it introduces an additional | |
7755 | instruction. */ | |
7756 | ||
f5040a92 AO |
7757 | if (offset_expr.X_add_number) |
7758 | { | |
4d7206a2 | 7759 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7760 | offset_expr.X_add_number = 0; |
7761 | ||
4d7206a2 | 7762 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7763 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7764 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7765 | |
7766 | if (expr1.X_add_number >= -0x8000 | |
7767 | && expr1.X_add_number < 0x8000) | |
7768 | { | |
67c0d1eb RS |
7769 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7770 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7771 | } |
ecd13cd3 | 7772 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7773 | { |
f5040a92 AO |
7774 | /* If we are going to add in a base register, and the |
7775 | target register and the base register are the same, | |
7776 | then we are using AT as a temporary register. Since | |
7777 | we want to load the constant into AT, we add our | |
7778 | current AT (from the global offset table) and the | |
7779 | register into the register now, and pretend we were | |
7780 | not using a base register. */ | |
7781 | if (breg != treg) | |
7782 | dreg = tempreg; | |
7783 | else | |
7784 | { | |
9c2799c2 | 7785 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7786 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7787 | treg, AT, breg); | |
f5040a92 | 7788 | dreg = treg; |
67c0d1eb | 7789 | add_breg_early = 1; |
f5040a92 AO |
7790 | } |
7791 | ||
f6a22291 | 7792 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7794 | dreg, dreg, AT); |
f5040a92 | 7795 | |
f5040a92 AO |
7796 | used_at = 1; |
7797 | } | |
7798 | else | |
7799 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7800 | ||
4d7206a2 | 7801 | relax_switch (); |
f5040a92 AO |
7802 | offset_expr.X_add_number = expr1.X_add_number; |
7803 | ||
67c0d1eb RS |
7804 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7805 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7806 | if (add_breg_early) | |
f5040a92 | 7807 | { |
67c0d1eb | 7808 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7809 | treg, tempreg, breg); |
f5040a92 AO |
7810 | breg = 0; |
7811 | tempreg = treg; | |
7812 | } | |
4d7206a2 | 7813 | relax_end (); |
f5040a92 | 7814 | } |
4d7206a2 | 7815 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7816 | { |
4d7206a2 | 7817 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7818 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7819 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7820 | relax_switch (); |
67c0d1eb RS |
7821 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7822 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7823 | relax_end (); |
f5040a92 | 7824 | } |
4d7206a2 | 7825 | else |
f5040a92 | 7826 | { |
67c0d1eb RS |
7827 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7828 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7829 | } |
7830 | } | |
0a44bf69 | 7831 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7832 | { |
67c0d1eb | 7833 | int gpdelay; |
9117d219 NC |
7834 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7835 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7836 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7837 | |
7838 | /* This is the large GOT case. If this is a reference to an | |
7839 | external symbol, and there is no constant, we want | |
7840 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7841 | addu $tempreg,$tempreg,$gp | |
7842 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7843 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7844 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7845 | addu $tempreg,$tempreg,$gp | |
7846 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7847 | For a local symbol, we want |
7848 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7849 | nop | |
7850 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7851 | ||
7852 | If we have a small constant, and this is a reference to | |
7853 | an external symbol, we want | |
7854 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7855 | addu $tempreg,$tempreg,$gp | |
7856 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7857 | nop | |
7858 | addiu $tempreg,$tempreg,<constant> | |
7859 | For a local symbol, we want | |
7860 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7861 | nop | |
7862 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7863 | ||
7864 | If we have a large constant, and this is a reference to | |
7865 | an external symbol, we want | |
7866 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7867 | addu $tempreg,$tempreg,$gp | |
7868 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7869 | lui $at,<hiconstant> | |
7870 | addiu $at,$at,<loconstant> | |
7871 | addu $tempreg,$tempreg,$at | |
7872 | For a local symbol, we want | |
7873 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7874 | lui $at,<hiconstant> | |
7875 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7876 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7877 | */ |
438c16b8 | 7878 | |
252b5132 RH |
7879 | expr1.X_add_number = offset_expr.X_add_number; |
7880 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7881 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7882 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7883 | if (expr1.X_add_number == 0 && breg == 0 |
7884 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7885 | { |
7886 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7887 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7888 | } | |
df58fc94 | 7889 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7890 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7891 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7892 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7893 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7894 | if (expr1.X_add_number == 0) |
7895 | { | |
67c0d1eb | 7896 | if (breg != 0) |
252b5132 RH |
7897 | { |
7898 | /* We're going to put in an addu instruction using | |
7899 | tempreg, so we may as well insert the nop right | |
7900 | now. */ | |
269137b2 | 7901 | load_delay_nop (); |
252b5132 | 7902 | } |
252b5132 RH |
7903 | } |
7904 | else if (expr1.X_add_number >= -0x8000 | |
7905 | && expr1.X_add_number < 0x8000) | |
7906 | { | |
269137b2 | 7907 | load_delay_nop (); |
67c0d1eb | 7908 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7909 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7910 | } |
7911 | else | |
7912 | { | |
252b5132 RH |
7913 | /* If we are going to add in a base register, and the |
7914 | target register and the base register are the same, | |
7915 | then we are using AT as a temporary register. Since | |
7916 | we want to load the constant into AT, we add our | |
7917 | current AT (from the global offset table) and the | |
7918 | register into the register now, and pretend we were | |
7919 | not using a base register. */ | |
7920 | if (breg != treg) | |
67c0d1eb | 7921 | dreg = tempreg; |
252b5132 RH |
7922 | else |
7923 | { | |
9c2799c2 | 7924 | gas_assert (tempreg == AT); |
269137b2 | 7925 | load_delay_nop (); |
67c0d1eb | 7926 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7927 | treg, AT, breg); |
252b5132 | 7928 | dreg = treg; |
252b5132 RH |
7929 | } |
7930 | ||
f6a22291 | 7931 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7932 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7933 | |
252b5132 RH |
7934 | used_at = 1; |
7935 | } | |
43c0598f | 7936 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7937 | relax_switch (); |
252b5132 | 7938 | |
67c0d1eb | 7939 | if (gpdelay) |
252b5132 RH |
7940 | { |
7941 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7942 | the first instruction on the main stream does not. */ |
67c0d1eb | 7943 | macro_build (NULL, "nop", ""); |
252b5132 | 7944 | } |
ed6fb7bd | 7945 | |
67c0d1eb RS |
7946 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7947 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7948 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7949 | && expr1.X_add_number < 0x8000) |
7950 | { | |
269137b2 | 7951 | load_delay_nop (); |
67c0d1eb RS |
7952 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7953 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7954 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7955 | register, the external symbol case ended with a load, |
7956 | so if the symbol turns out to not be external, and | |
7957 | the next instruction uses tempreg, an unnecessary nop | |
7958 | will be inserted. */ | |
252b5132 RH |
7959 | } |
7960 | else | |
7961 | { | |
7962 | if (breg == treg) | |
7963 | { | |
7964 | /* We must add in the base register now, as in the | |
f5040a92 | 7965 | external symbol case. */ |
9c2799c2 | 7966 | gas_assert (tempreg == AT); |
269137b2 | 7967 | load_delay_nop (); |
67c0d1eb | 7968 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7969 | treg, AT, breg); |
252b5132 RH |
7970 | tempreg = treg; |
7971 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7972 | it in in both cases. */ |
252b5132 RH |
7973 | breg = 0; |
7974 | } | |
7975 | ||
67c0d1eb RS |
7976 | macro_build_lui (&expr1, AT); |
7977 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7978 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7980 | tempreg, tempreg, AT); |
8fc2e39e | 7981 | used_at = 1; |
252b5132 | 7982 | } |
4d7206a2 | 7983 | relax_end (); |
252b5132 | 7984 | } |
0a44bf69 | 7985 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7986 | { |
f5040a92 AO |
7987 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7988 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7989 | int add_breg_early = 0; |
f5040a92 AO |
7990 | |
7991 | /* This is the large GOT case. If this is a reference to an | |
7992 | external symbol, and there is no constant, we want | |
7993 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7994 | add $tempreg,$tempreg,$gp | |
7995 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7996 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7997 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7998 | add $tempreg,$tempreg,$gp | |
7999 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
8000 | ||
8001 | If we have a small constant, and this is a reference to | |
8002 | an external symbol, we want | |
8003 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8004 | add $tempreg,$tempreg,$gp | |
8005 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8006 | addi $tempreg,$tempreg,<constant> | |
8007 | ||
8008 | If we have a large constant, and this is a reference to | |
8009 | an external symbol, we want | |
8010 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8011 | addu $tempreg,$tempreg,$gp | |
8012 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8013 | lui $at,<hiconstant> | |
8014 | addi $at,$at,<loconstant> | |
8015 | add $tempreg,$tempreg,$at | |
8016 | ||
8017 | If we have NewABI, and we know it's a local symbol, we want | |
8018 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8019 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
8020 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
8021 | ||
4d7206a2 | 8022 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 8023 | |
4d7206a2 | 8024 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8025 | offset_expr.X_add_number = 0; |
8026 | ||
1abe91b1 MR |
8027 | if (expr1.X_add_number == 0 && breg == 0 |
8028 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
8029 | { |
8030 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
8031 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
8032 | } | |
df58fc94 | 8033 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 8034 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8035 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
8036 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8037 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
8038 | |
8039 | if (expr1.X_add_number == 0) | |
4d7206a2 | 8040 | ; |
f5040a92 AO |
8041 | else if (expr1.X_add_number >= -0x8000 |
8042 | && expr1.X_add_number < 0x8000) | |
8043 | { | |
67c0d1eb | 8044 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8045 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 8046 | } |
ecd13cd3 | 8047 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 8048 | { |
f5040a92 AO |
8049 | /* If we are going to add in a base register, and the |
8050 | target register and the base register are the same, | |
8051 | then we are using AT as a temporary register. Since | |
8052 | we want to load the constant into AT, we add our | |
8053 | current AT (from the global offset table) and the | |
8054 | register into the register now, and pretend we were | |
8055 | not using a base register. */ | |
8056 | if (breg != treg) | |
8057 | dreg = tempreg; | |
8058 | else | |
8059 | { | |
9c2799c2 | 8060 | gas_assert (tempreg == AT); |
67c0d1eb | 8061 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8062 | treg, AT, breg); |
f5040a92 | 8063 | dreg = treg; |
67c0d1eb | 8064 | add_breg_early = 1; |
f5040a92 AO |
8065 | } |
8066 | ||
f6a22291 | 8067 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 8069 | |
f5040a92 AO |
8070 | used_at = 1; |
8071 | } | |
8072 | else | |
8073 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
8074 | ||
4d7206a2 | 8075 | relax_switch (); |
f5040a92 | 8076 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8077 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8078 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
8079 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
8080 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
8081 | if (add_breg_early) | |
f5040a92 | 8082 | { |
67c0d1eb | 8083 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8084 | treg, tempreg, breg); |
f5040a92 AO |
8085 | breg = 0; |
8086 | tempreg = treg; | |
8087 | } | |
4d7206a2 | 8088 | relax_end (); |
f5040a92 | 8089 | } |
252b5132 RH |
8090 | else |
8091 | abort (); | |
8092 | ||
8093 | if (breg != 0) | |
aed1a261 | 8094 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
8095 | break; |
8096 | ||
52b6b6b9 | 8097 | case M_MSGSND: |
df58fc94 | 8098 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8099 | { |
8100 | unsigned long temp = (treg << 16) | (0x01); | |
8101 | macro_build (NULL, "c2", "C", temp); | |
8102 | } | |
c7af4273 | 8103 | break; |
52b6b6b9 JM |
8104 | |
8105 | case M_MSGLD: | |
df58fc94 | 8106 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8107 | { |
8108 | unsigned long temp = (0x02); | |
8109 | macro_build (NULL, "c2", "C", temp); | |
8110 | } | |
c7af4273 | 8111 | break; |
52b6b6b9 JM |
8112 | |
8113 | case M_MSGLD_T: | |
df58fc94 | 8114 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8115 | { |
8116 | unsigned long temp = (treg << 16) | (0x02); | |
8117 | macro_build (NULL, "c2", "C", temp); | |
8118 | } | |
c7af4273 | 8119 | break; |
52b6b6b9 JM |
8120 | |
8121 | case M_MSGWAIT: | |
df58fc94 | 8122 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 8123 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 8124 | break; |
52b6b6b9 JM |
8125 | |
8126 | case M_MSGWAIT_T: | |
df58fc94 | 8127 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8128 | { |
8129 | unsigned long temp = (treg << 16) | 0x03; | |
8130 | macro_build (NULL, "c2", "C", temp); | |
8131 | } | |
c7af4273 | 8132 | break; |
52b6b6b9 | 8133 | |
252b5132 RH |
8134 | case M_J_A: |
8135 | /* The j instruction may not be used in PIC code, since it | |
8136 | requires an absolute address. We convert it to a b | |
8137 | instruction. */ | |
8138 | if (mips_pic == NO_PIC) | |
67c0d1eb | 8139 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 8140 | else |
67c0d1eb | 8141 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 8142 | break; |
252b5132 RH |
8143 | |
8144 | /* The jal instructions must be handled as macros because when | |
8145 | generating PIC code they expand to multi-instruction | |
8146 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
8147 | case M_JALS_1: |
8148 | dreg = RA; | |
8149 | /* Fall through. */ | |
8150 | case M_JALS_2: | |
8151 | gas_assert (mips_opts.micromips); | |
8152 | jals = 1; | |
8153 | goto jal; | |
252b5132 RH |
8154 | case M_JAL_1: |
8155 | dreg = RA; | |
8156 | /* Fall through. */ | |
8157 | case M_JAL_2: | |
df58fc94 | 8158 | jal: |
3e722fb5 | 8159 | if (mips_pic == NO_PIC) |
df58fc94 RS |
8160 | { |
8161 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
8162 | if (mips_opts.micromips |
8163 | && dreg == RA | |
8164 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8165 | macro_build (NULL, s, "mj", sreg); |
8166 | else | |
8167 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
8168 | } | |
0a44bf69 | 8169 | else |
252b5132 | 8170 | { |
df58fc94 RS |
8171 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
8172 | && mips_cprestore_offset >= 0); | |
8173 | ||
252b5132 RH |
8174 | if (sreg != PIC_CALL_REG) |
8175 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 8176 | |
df58fc94 RS |
8177 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
8178 | ? "jalrs" : "jalr"); | |
e64af278 MR |
8179 | if (mips_opts.micromips |
8180 | && dreg == RA | |
8181 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8182 | macro_build (NULL, s, "mj", sreg); |
8183 | else | |
8184 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 8185 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 8186 | { |
6478892d TS |
8187 | if (mips_cprestore_offset < 0) |
8188 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8189 | else | |
8190 | { | |
90ecf173 | 8191 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8192 | { |
8193 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8194 | /* Quiet this warning. */ | |
8195 | mips_frame_reg_valid = 1; | |
8196 | } | |
90ecf173 | 8197 | if (!mips_cprestore_valid) |
7a621144 DJ |
8198 | { |
8199 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8200 | /* Quiet this warning. */ | |
8201 | mips_cprestore_valid = 1; | |
8202 | } | |
d3fca0b5 MR |
8203 | if (mips_opts.noreorder) |
8204 | macro_build (NULL, "nop", ""); | |
6478892d | 8205 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8206 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8207 | mips_gp_register, |
256ab948 TS |
8208 | mips_frame_reg, |
8209 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8210 | } |
252b5132 RH |
8211 | } |
8212 | } | |
252b5132 | 8213 | |
8fc2e39e | 8214 | break; |
252b5132 | 8215 | |
df58fc94 RS |
8216 | case M_JALS_A: |
8217 | gas_assert (mips_opts.micromips); | |
8218 | jals = 1; | |
8219 | /* Fall through. */ | |
252b5132 RH |
8220 | case M_JAL_A: |
8221 | if (mips_pic == NO_PIC) | |
df58fc94 | 8222 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
8223 | else if (mips_pic == SVR4_PIC) |
8224 | { | |
8225 | /* If this is a reference to an external symbol, and we are | |
8226 | using a small GOT, we want | |
8227 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
8228 | nop | |
f9419b05 | 8229 | jalr $ra,$25 |
252b5132 RH |
8230 | nop |
8231 | lw $gp,cprestore($sp) | |
8232 | The cprestore value is set using the .cprestore | |
8233 | pseudo-op. If we are using a big GOT, we want | |
8234 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8235 | addu $25,$25,$gp | |
8236 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8237 | nop | |
f9419b05 | 8238 | jalr $ra,$25 |
252b5132 RH |
8239 | nop |
8240 | lw $gp,cprestore($sp) | |
8241 | If the symbol is not external, we want | |
8242 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8243 | nop | |
8244 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8245 | jalr $ra,$25 |
252b5132 | 8246 | nop |
438c16b8 | 8247 | lw $gp,cprestore($sp) |
f5040a92 AO |
8248 | |
8249 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8250 | sequences above, minus nops, unless the symbol is local, | |
8251 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8252 | GOT_DISP. */ | |
438c16b8 | 8253 | if (HAVE_NEWABI) |
252b5132 | 8254 | { |
90ecf173 | 8255 | if (!mips_big_got) |
f5040a92 | 8256 | { |
4d7206a2 | 8257 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8258 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8259 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8260 | mips_gp_register); |
4d7206a2 | 8261 | relax_switch (); |
67c0d1eb RS |
8262 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8263 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8264 | mips_gp_register); |
8265 | relax_end (); | |
f5040a92 AO |
8266 | } |
8267 | else | |
8268 | { | |
4d7206a2 | 8269 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8270 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8271 | BFD_RELOC_MIPS_CALL_HI16); |
8272 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8273 | PIC_CALL_REG, mips_gp_register); | |
8274 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8275 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8276 | PIC_CALL_REG); | |
4d7206a2 | 8277 | relax_switch (); |
67c0d1eb RS |
8278 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8279 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8280 | mips_gp_register); | |
8281 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8282 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8283 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8284 | relax_end (); |
f5040a92 | 8285 | } |
684022ea | 8286 | |
df58fc94 | 8287 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8288 | } |
8289 | else | |
8290 | { | |
4d7206a2 | 8291 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8292 | if (!mips_big_got) |
438c16b8 | 8293 | { |
67c0d1eb RS |
8294 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8295 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8296 | mips_gp_register); |
269137b2 | 8297 | load_delay_nop (); |
4d7206a2 | 8298 | relax_switch (); |
438c16b8 | 8299 | } |
252b5132 | 8300 | else |
252b5132 | 8301 | { |
67c0d1eb RS |
8302 | int gpdelay; |
8303 | ||
8304 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8305 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8306 | BFD_RELOC_MIPS_CALL_HI16); |
8307 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8308 | PIC_CALL_REG, mips_gp_register); | |
8309 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8310 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8311 | PIC_CALL_REG); | |
269137b2 | 8312 | load_delay_nop (); |
4d7206a2 | 8313 | relax_switch (); |
67c0d1eb RS |
8314 | if (gpdelay) |
8315 | macro_build (NULL, "nop", ""); | |
252b5132 | 8316 | } |
67c0d1eb RS |
8317 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8318 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8319 | mips_gp_register); |
269137b2 | 8320 | load_delay_nop (); |
67c0d1eb RS |
8321 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8322 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8323 | relax_end (); |
df58fc94 | 8324 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8325 | |
6478892d TS |
8326 | if (mips_cprestore_offset < 0) |
8327 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8328 | else | |
8329 | { | |
90ecf173 | 8330 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8331 | { |
8332 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8333 | /* Quiet this warning. */ | |
8334 | mips_frame_reg_valid = 1; | |
8335 | } | |
90ecf173 | 8336 | if (!mips_cprestore_valid) |
7a621144 DJ |
8337 | { |
8338 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8339 | /* Quiet this warning. */ | |
8340 | mips_cprestore_valid = 1; | |
8341 | } | |
6478892d | 8342 | if (mips_opts.noreorder) |
67c0d1eb | 8343 | macro_build (NULL, "nop", ""); |
6478892d | 8344 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8345 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8346 | mips_gp_register, |
256ab948 TS |
8347 | mips_frame_reg, |
8348 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8349 | } |
252b5132 RH |
8350 | } |
8351 | } | |
0a44bf69 RS |
8352 | else if (mips_pic == VXWORKS_PIC) |
8353 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8354 | else |
8355 | abort (); | |
8356 | ||
8fc2e39e | 8357 | break; |
252b5132 | 8358 | |
7f3c4072 CM |
8359 | case M_LBUE_AB: |
8360 | ab = 1; | |
8361 | case M_LBUE_OB: | |
8362 | s = "lbue"; | |
8363 | fmt = "t,+j(b)"; | |
8364 | offbits = 9; | |
8365 | goto ld_st; | |
8366 | case M_LHUE_AB: | |
8367 | ab = 1; | |
8368 | case M_LHUE_OB: | |
8369 | s = "lhue"; | |
8370 | fmt = "t,+j(b)"; | |
8371 | offbits = 9; | |
8372 | goto ld_st; | |
8373 | case M_LBE_AB: | |
8374 | ab = 1; | |
8375 | case M_LBE_OB: | |
8376 | s = "lbe"; | |
8377 | fmt = "t,+j(b)"; | |
8378 | offbits = 9; | |
8379 | goto ld_st; | |
8380 | case M_LHE_AB: | |
8381 | ab = 1; | |
8382 | case M_LHE_OB: | |
8383 | s = "lhe"; | |
8384 | fmt = "t,+j(b)"; | |
8385 | offbits = 9; | |
8386 | goto ld_st; | |
8387 | case M_LLE_AB: | |
8388 | ab = 1; | |
8389 | case M_LLE_OB: | |
8390 | s = "lle"; | |
8391 | fmt = "t,+j(b)"; | |
8392 | offbits = 9; | |
8393 | goto ld_st; | |
8394 | case M_LWE_AB: | |
8395 | ab = 1; | |
8396 | case M_LWE_OB: | |
8397 | s = "lwe"; | |
8398 | fmt = "t,+j(b)"; | |
8399 | offbits = 9; | |
8400 | goto ld_st; | |
8401 | case M_LWLE_AB: | |
8402 | ab = 1; | |
8403 | case M_LWLE_OB: | |
8404 | s = "lwle"; | |
8405 | fmt = "t,+j(b)"; | |
8406 | offbits = 9; | |
8407 | goto ld_st; | |
8408 | case M_LWRE_AB: | |
8409 | ab = 1; | |
8410 | case M_LWRE_OB: | |
8411 | s = "lwre"; | |
8412 | fmt = "t,+j(b)"; | |
8413 | offbits = 9; | |
8414 | goto ld_st; | |
8415 | case M_SBE_AB: | |
8416 | ab = 1; | |
8417 | case M_SBE_OB: | |
8418 | s = "sbe"; | |
8419 | fmt = "t,+j(b)"; | |
8420 | offbits = 9; | |
8421 | goto ld_st; | |
8422 | case M_SCE_AB: | |
8423 | ab = 1; | |
8424 | case M_SCE_OB: | |
8425 | s = "sce"; | |
8426 | fmt = "t,+j(b)"; | |
8427 | offbits = 9; | |
8428 | goto ld_st; | |
8429 | case M_SHE_AB: | |
8430 | ab = 1; | |
8431 | case M_SHE_OB: | |
8432 | s = "she"; | |
8433 | fmt = "t,+j(b)"; | |
8434 | offbits = 9; | |
8435 | goto ld_st; | |
8436 | case M_SWE_AB: | |
8437 | ab = 1; | |
8438 | case M_SWE_OB: | |
8439 | s = "swe"; | |
8440 | fmt = "t,+j(b)"; | |
8441 | offbits = 9; | |
8442 | goto ld_st; | |
8443 | case M_SWLE_AB: | |
8444 | ab = 1; | |
8445 | case M_SWLE_OB: | |
8446 | s = "swle"; | |
8447 | fmt = "t,+j(b)"; | |
8448 | offbits = 9; | |
8449 | goto ld_st; | |
8450 | case M_SWRE_AB: | |
8451 | ab = 1; | |
8452 | case M_SWRE_OB: | |
8453 | s = "swre"; | |
8454 | fmt = "t,+j(b)"; | |
8455 | offbits = 9; | |
8456 | goto ld_st; | |
dec0624d MR |
8457 | case M_ACLR_AB: |
8458 | ab = 1; | |
8459 | case M_ACLR_OB: | |
8460 | s = "aclr"; | |
8461 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8462 | fmt = "\\,~(b)"; | |
7f3c4072 | 8463 | offbits = 12; |
dec0624d MR |
8464 | goto ld_st; |
8465 | case M_ASET_AB: | |
8466 | ab = 1; | |
8467 | case M_ASET_OB: | |
8468 | s = "aset"; | |
8469 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8470 | fmt = "\\,~(b)"; | |
7f3c4072 | 8471 | offbits = 12; |
dec0624d | 8472 | goto ld_st; |
252b5132 | 8473 | case M_LB_AB: |
df58fc94 | 8474 | ab = 1; |
252b5132 | 8475 | s = "lb"; |
df58fc94 | 8476 | fmt = "t,o(b)"; |
252b5132 RH |
8477 | goto ld; |
8478 | case M_LBU_AB: | |
df58fc94 | 8479 | ab = 1; |
252b5132 | 8480 | s = "lbu"; |
df58fc94 | 8481 | fmt = "t,o(b)"; |
252b5132 RH |
8482 | goto ld; |
8483 | case M_LH_AB: | |
df58fc94 | 8484 | ab = 1; |
252b5132 | 8485 | s = "lh"; |
df58fc94 | 8486 | fmt = "t,o(b)"; |
252b5132 RH |
8487 | goto ld; |
8488 | case M_LHU_AB: | |
df58fc94 | 8489 | ab = 1; |
252b5132 | 8490 | s = "lhu"; |
df58fc94 | 8491 | fmt = "t,o(b)"; |
252b5132 RH |
8492 | goto ld; |
8493 | case M_LW_AB: | |
df58fc94 | 8494 | ab = 1; |
252b5132 | 8495 | s = "lw"; |
df58fc94 | 8496 | fmt = "t,o(b)"; |
252b5132 RH |
8497 | goto ld; |
8498 | case M_LWC0_AB: | |
df58fc94 RS |
8499 | ab = 1; |
8500 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8501 | s = "lwc0"; |
df58fc94 | 8502 | fmt = "E,o(b)"; |
bdaaa2e1 | 8503 | /* Itbl support may require additional care here. */ |
252b5132 | 8504 | coproc = 1; |
df58fc94 | 8505 | goto ld_st; |
252b5132 | 8506 | case M_LWC1_AB: |
df58fc94 | 8507 | ab = 1; |
252b5132 | 8508 | s = "lwc1"; |
df58fc94 | 8509 | fmt = "T,o(b)"; |
bdaaa2e1 | 8510 | /* Itbl support may require additional care here. */ |
252b5132 | 8511 | coproc = 1; |
df58fc94 | 8512 | goto ld_st; |
252b5132 | 8513 | case M_LWC2_AB: |
df58fc94 RS |
8514 | ab = 1; |
8515 | case M_LWC2_OB: | |
252b5132 | 8516 | s = "lwc2"; |
df58fc94 | 8517 | fmt = COP12_FMT; |
7f3c4072 | 8518 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8519 | /* Itbl support may require additional care here. */ |
252b5132 | 8520 | coproc = 1; |
df58fc94 | 8521 | goto ld_st; |
252b5132 | 8522 | case M_LWC3_AB: |
df58fc94 RS |
8523 | ab = 1; |
8524 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8525 | s = "lwc3"; |
df58fc94 | 8526 | fmt = "E,o(b)"; |
bdaaa2e1 | 8527 | /* Itbl support may require additional care here. */ |
252b5132 | 8528 | coproc = 1; |
df58fc94 | 8529 | goto ld_st; |
252b5132 | 8530 | case M_LWL_AB: |
df58fc94 RS |
8531 | ab = 1; |
8532 | case M_LWL_OB: | |
252b5132 | 8533 | s = "lwl"; |
df58fc94 | 8534 | fmt = MEM12_FMT; |
7f3c4072 | 8535 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8536 | goto ld_st; |
252b5132 | 8537 | case M_LWR_AB: |
df58fc94 RS |
8538 | ab = 1; |
8539 | case M_LWR_OB: | |
252b5132 | 8540 | s = "lwr"; |
df58fc94 | 8541 | fmt = MEM12_FMT; |
7f3c4072 | 8542 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8543 | goto ld_st; |
252b5132 | 8544 | case M_LDC1_AB: |
df58fc94 | 8545 | ab = 1; |
252b5132 | 8546 | s = "ldc1"; |
df58fc94 | 8547 | fmt = "T,o(b)"; |
bdaaa2e1 | 8548 | /* Itbl support may require additional care here. */ |
252b5132 | 8549 | coproc = 1; |
df58fc94 | 8550 | goto ld_st; |
252b5132 | 8551 | case M_LDC2_AB: |
df58fc94 RS |
8552 | ab = 1; |
8553 | case M_LDC2_OB: | |
252b5132 | 8554 | s = "ldc2"; |
df58fc94 | 8555 | fmt = COP12_FMT; |
7f3c4072 | 8556 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8557 | /* Itbl support may require additional care here. */ |
252b5132 | 8558 | coproc = 1; |
df58fc94 | 8559 | goto ld_st; |
c77c0862 RS |
8560 | case M_LQC2_AB: |
8561 | ab = 1; | |
8562 | s = "lqc2"; | |
8563 | fmt = "E,o(b)"; | |
8564 | /* Itbl support may require additional care here. */ | |
8565 | coproc = 1; | |
8566 | goto ld_st; | |
252b5132 | 8567 | case M_LDC3_AB: |
df58fc94 | 8568 | ab = 1; |
252b5132 | 8569 | s = "ldc3"; |
df58fc94 | 8570 | fmt = "E,o(b)"; |
bdaaa2e1 | 8571 | /* Itbl support may require additional care here. */ |
252b5132 | 8572 | coproc = 1; |
df58fc94 | 8573 | goto ld_st; |
252b5132 | 8574 | case M_LDL_AB: |
df58fc94 RS |
8575 | ab = 1; |
8576 | case M_LDL_OB: | |
252b5132 | 8577 | s = "ldl"; |
df58fc94 | 8578 | fmt = MEM12_FMT; |
7f3c4072 | 8579 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8580 | goto ld_st; |
252b5132 | 8581 | case M_LDR_AB: |
df58fc94 RS |
8582 | ab = 1; |
8583 | case M_LDR_OB: | |
252b5132 | 8584 | s = "ldr"; |
df58fc94 | 8585 | fmt = MEM12_FMT; |
7f3c4072 | 8586 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8587 | goto ld_st; |
252b5132 | 8588 | case M_LL_AB: |
df58fc94 RS |
8589 | ab = 1; |
8590 | case M_LL_OB: | |
252b5132 | 8591 | s = "ll"; |
df58fc94 | 8592 | fmt = MEM12_FMT; |
7f3c4072 | 8593 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8594 | goto ld; |
8595 | case M_LLD_AB: | |
df58fc94 RS |
8596 | ab = 1; |
8597 | case M_LLD_OB: | |
252b5132 | 8598 | s = "lld"; |
df58fc94 | 8599 | fmt = MEM12_FMT; |
7f3c4072 | 8600 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8601 | goto ld; |
8602 | case M_LWU_AB: | |
df58fc94 RS |
8603 | ab = 1; |
8604 | case M_LWU_OB: | |
252b5132 | 8605 | s = "lwu"; |
df58fc94 | 8606 | fmt = MEM12_FMT; |
7f3c4072 | 8607 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8608 | goto ld; |
8609 | case M_LWP_AB: | |
8610 | ab = 1; | |
8611 | case M_LWP_OB: | |
8612 | gas_assert (mips_opts.micromips); | |
8613 | s = "lwp"; | |
8614 | fmt = "t,~(b)"; | |
7f3c4072 | 8615 | offbits = 12; |
df58fc94 RS |
8616 | lp = 1; |
8617 | goto ld; | |
8618 | case M_LDP_AB: | |
8619 | ab = 1; | |
8620 | case M_LDP_OB: | |
8621 | gas_assert (mips_opts.micromips); | |
8622 | s = "ldp"; | |
8623 | fmt = "t,~(b)"; | |
7f3c4072 | 8624 | offbits = 12; |
df58fc94 RS |
8625 | lp = 1; |
8626 | goto ld; | |
8627 | case M_LWM_AB: | |
8628 | ab = 1; | |
8629 | case M_LWM_OB: | |
8630 | gas_assert (mips_opts.micromips); | |
8631 | s = "lwm"; | |
8632 | fmt = "n,~(b)"; | |
7f3c4072 | 8633 | offbits = 12; |
df58fc94 RS |
8634 | goto ld_st; |
8635 | case M_LDM_AB: | |
8636 | ab = 1; | |
8637 | case M_LDM_OB: | |
8638 | gas_assert (mips_opts.micromips); | |
8639 | s = "ldm"; | |
8640 | fmt = "n,~(b)"; | |
7f3c4072 | 8641 | offbits = 12; |
df58fc94 RS |
8642 | goto ld_st; |
8643 | ||
252b5132 | 8644 | ld: |
f19ccbda MR |
8645 | /* We don't want to use $0 as tempreg. */ |
8646 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8647 | goto ld_st; |
252b5132 | 8648 | else |
df58fc94 RS |
8649 | tempreg = treg + lp; |
8650 | goto ld_noat; | |
8651 | ||
252b5132 | 8652 | case M_SB_AB: |
df58fc94 | 8653 | ab = 1; |
252b5132 | 8654 | s = "sb"; |
df58fc94 RS |
8655 | fmt = "t,o(b)"; |
8656 | goto ld_st; | |
252b5132 | 8657 | case M_SH_AB: |
df58fc94 | 8658 | ab = 1; |
252b5132 | 8659 | s = "sh"; |
df58fc94 RS |
8660 | fmt = "t,o(b)"; |
8661 | goto ld_st; | |
252b5132 | 8662 | case M_SW_AB: |
df58fc94 | 8663 | ab = 1; |
252b5132 | 8664 | s = "sw"; |
df58fc94 RS |
8665 | fmt = "t,o(b)"; |
8666 | goto ld_st; | |
252b5132 | 8667 | case M_SWC0_AB: |
df58fc94 RS |
8668 | ab = 1; |
8669 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8670 | s = "swc0"; |
df58fc94 | 8671 | fmt = "E,o(b)"; |
bdaaa2e1 | 8672 | /* Itbl support may require additional care here. */ |
252b5132 | 8673 | coproc = 1; |
df58fc94 | 8674 | goto ld_st; |
252b5132 | 8675 | case M_SWC1_AB: |
df58fc94 | 8676 | ab = 1; |
252b5132 | 8677 | s = "swc1"; |
df58fc94 | 8678 | fmt = "T,o(b)"; |
bdaaa2e1 | 8679 | /* Itbl support may require additional care here. */ |
252b5132 | 8680 | coproc = 1; |
df58fc94 | 8681 | goto ld_st; |
252b5132 | 8682 | case M_SWC2_AB: |
df58fc94 RS |
8683 | ab = 1; |
8684 | case M_SWC2_OB: | |
252b5132 | 8685 | s = "swc2"; |
df58fc94 | 8686 | fmt = COP12_FMT; |
7f3c4072 | 8687 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8688 | /* Itbl support may require additional care here. */ |
252b5132 | 8689 | coproc = 1; |
df58fc94 | 8690 | goto ld_st; |
252b5132 | 8691 | case M_SWC3_AB: |
df58fc94 RS |
8692 | ab = 1; |
8693 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8694 | s = "swc3"; |
df58fc94 | 8695 | fmt = "E,o(b)"; |
bdaaa2e1 | 8696 | /* Itbl support may require additional care here. */ |
252b5132 | 8697 | coproc = 1; |
df58fc94 | 8698 | goto ld_st; |
252b5132 | 8699 | case M_SWL_AB: |
df58fc94 RS |
8700 | ab = 1; |
8701 | case M_SWL_OB: | |
252b5132 | 8702 | s = "swl"; |
df58fc94 | 8703 | fmt = MEM12_FMT; |
7f3c4072 | 8704 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8705 | goto ld_st; |
252b5132 | 8706 | case M_SWR_AB: |
df58fc94 RS |
8707 | ab = 1; |
8708 | case M_SWR_OB: | |
252b5132 | 8709 | s = "swr"; |
df58fc94 | 8710 | fmt = MEM12_FMT; |
7f3c4072 | 8711 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8712 | goto ld_st; |
252b5132 | 8713 | case M_SC_AB: |
df58fc94 RS |
8714 | ab = 1; |
8715 | case M_SC_OB: | |
252b5132 | 8716 | s = "sc"; |
df58fc94 | 8717 | fmt = MEM12_FMT; |
7f3c4072 | 8718 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8719 | goto ld_st; |
252b5132 | 8720 | case M_SCD_AB: |
df58fc94 RS |
8721 | ab = 1; |
8722 | case M_SCD_OB: | |
252b5132 | 8723 | s = "scd"; |
df58fc94 | 8724 | fmt = MEM12_FMT; |
7f3c4072 | 8725 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8726 | goto ld_st; |
d43b4baf | 8727 | case M_CACHE_AB: |
df58fc94 RS |
8728 | ab = 1; |
8729 | case M_CACHE_OB: | |
d43b4baf | 8730 | s = "cache"; |
df58fc94 | 8731 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8732 | offbits = (mips_opts.micromips ? 12 : 16); |
8733 | goto ld_st; | |
8734 | case M_CACHEE_AB: | |
8735 | ab = 1; | |
8736 | case M_CACHEE_OB: | |
8737 | s = "cachee"; | |
8738 | fmt = "k,+j(b)"; | |
8739 | offbits = 9; | |
df58fc94 | 8740 | goto ld_st; |
3eebd5eb | 8741 | case M_PREF_AB: |
df58fc94 RS |
8742 | ab = 1; |
8743 | case M_PREF_OB: | |
3eebd5eb | 8744 | s = "pref"; |
df58fc94 | 8745 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8746 | offbits = (mips_opts.micromips ? 12 : 16); |
8747 | goto ld_st; | |
8748 | case M_PREFE_AB: | |
8749 | ab = 1; | |
8750 | case M_PREFE_OB: | |
8751 | s = "prefe"; | |
8752 | fmt = "k,+j(b)"; | |
8753 | offbits = 9; | |
df58fc94 | 8754 | goto ld_st; |
252b5132 | 8755 | case M_SDC1_AB: |
df58fc94 | 8756 | ab = 1; |
252b5132 | 8757 | s = "sdc1"; |
df58fc94 | 8758 | fmt = "T,o(b)"; |
252b5132 | 8759 | coproc = 1; |
bdaaa2e1 | 8760 | /* Itbl support may require additional care here. */ |
df58fc94 | 8761 | goto ld_st; |
252b5132 | 8762 | case M_SDC2_AB: |
df58fc94 RS |
8763 | ab = 1; |
8764 | case M_SDC2_OB: | |
252b5132 | 8765 | s = "sdc2"; |
df58fc94 | 8766 | fmt = COP12_FMT; |
7f3c4072 | 8767 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8768 | /* Itbl support may require additional care here. */ |
8769 | coproc = 1; | |
8770 | goto ld_st; | |
8771 | case M_SQC2_AB: | |
8772 | ab = 1; | |
8773 | s = "sqc2"; | |
8774 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8775 | /* Itbl support may require additional care here. */ |
252b5132 | 8776 | coproc = 1; |
df58fc94 | 8777 | goto ld_st; |
252b5132 | 8778 | case M_SDC3_AB: |
df58fc94 RS |
8779 | ab = 1; |
8780 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8781 | s = "sdc3"; |
df58fc94 | 8782 | fmt = "E,o(b)"; |
bdaaa2e1 | 8783 | /* Itbl support may require additional care here. */ |
252b5132 | 8784 | coproc = 1; |
df58fc94 | 8785 | goto ld_st; |
252b5132 | 8786 | case M_SDL_AB: |
df58fc94 RS |
8787 | ab = 1; |
8788 | case M_SDL_OB: | |
252b5132 | 8789 | s = "sdl"; |
df58fc94 | 8790 | fmt = MEM12_FMT; |
7f3c4072 | 8791 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8792 | goto ld_st; |
252b5132 | 8793 | case M_SDR_AB: |
df58fc94 RS |
8794 | ab = 1; |
8795 | case M_SDR_OB: | |
252b5132 | 8796 | s = "sdr"; |
df58fc94 | 8797 | fmt = MEM12_FMT; |
7f3c4072 | 8798 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8799 | goto ld_st; |
8800 | case M_SWP_AB: | |
8801 | ab = 1; | |
8802 | case M_SWP_OB: | |
8803 | gas_assert (mips_opts.micromips); | |
8804 | s = "swp"; | |
8805 | fmt = "t,~(b)"; | |
7f3c4072 | 8806 | offbits = 12; |
df58fc94 RS |
8807 | goto ld_st; |
8808 | case M_SDP_AB: | |
8809 | ab = 1; | |
8810 | case M_SDP_OB: | |
8811 | gas_assert (mips_opts.micromips); | |
8812 | s = "sdp"; | |
8813 | fmt = "t,~(b)"; | |
7f3c4072 | 8814 | offbits = 12; |
df58fc94 RS |
8815 | goto ld_st; |
8816 | case M_SWM_AB: | |
8817 | ab = 1; | |
8818 | case M_SWM_OB: | |
8819 | gas_assert (mips_opts.micromips); | |
8820 | s = "swm"; | |
8821 | fmt = "n,~(b)"; | |
7f3c4072 | 8822 | offbits = 12; |
df58fc94 RS |
8823 | goto ld_st; |
8824 | case M_SDM_AB: | |
8825 | ab = 1; | |
8826 | case M_SDM_OB: | |
8827 | gas_assert (mips_opts.micromips); | |
8828 | s = "sdm"; | |
8829 | fmt = "n,~(b)"; | |
7f3c4072 | 8830 | offbits = 12; |
df58fc94 RS |
8831 | |
8832 | ld_st: | |
8fc2e39e TS |
8833 | tempreg = AT; |
8834 | used_at = 1; | |
df58fc94 | 8835 | ld_noat: |
252b5132 RH |
8836 | if (offset_expr.X_op != O_constant |
8837 | && offset_expr.X_op != O_symbol) | |
8838 | { | |
f71d0d44 | 8839 | as_bad (_("Expression too complex")); |
252b5132 RH |
8840 | offset_expr.X_op = O_constant; |
8841 | } | |
8842 | ||
2051e8c4 MR |
8843 | if (HAVE_32BIT_ADDRESSES |
8844 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8845 | { |
8846 | char value [32]; | |
8847 | ||
8848 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8849 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8850 | } |
2051e8c4 | 8851 | |
252b5132 RH |
8852 | /* A constant expression in PIC code can be handled just as it |
8853 | is in non PIC code. */ | |
aed1a261 RS |
8854 | if (offset_expr.X_op == O_constant) |
8855 | { | |
df58fc94 RS |
8856 | int hipart = 0; |
8857 | ||
842f8b2a | 8858 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8859 | normalize_address_expr (&expr1); |
7f3c4072 CM |
8860 | if ((offbits == 0 || offbits == 16) |
8861 | && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) | |
842f8b2a MR |
8862 | { |
8863 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8864 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8865 | hipart = 1; |
8866 | } | |
7f3c4072 | 8867 | else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) |
df58fc94 RS |
8868 | { |
8869 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8870 | & ~(bfd_vma) 0xfff); | |
8871 | hipart = 1; | |
8872 | } | |
7f3c4072 CM |
8873 | else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number)) |
8874 | { | |
8875 | expr1.X_add_number = ((expr1.X_add_number + 0x100) | |
8876 | & ~(bfd_vma) 0x1ff); | |
8877 | hipart = 1; | |
8878 | } | |
df58fc94 RS |
8879 | if (hipart) |
8880 | { | |
842f8b2a MR |
8881 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8882 | if (breg != 0) | |
8883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8884 | tempreg, tempreg, breg); | |
8885 | breg = tempreg; | |
8886 | } | |
7f3c4072 | 8887 | if (offbits == 0) |
dd6a37e7 AP |
8888 | { |
8889 | if (offset_expr.X_add_number == 0) | |
8890 | tempreg = breg; | |
8891 | else | |
8892 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8893 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8894 | macro_build (NULL, s, fmt, treg, tempreg); | |
8895 | } | |
7f3c4072 | 8896 | else if (offbits == 16) |
df58fc94 RS |
8897 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8898 | else | |
8899 | macro_build (NULL, s, fmt, | |
8900 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8901 | } | |
7f3c4072 | 8902 | else if (offbits != 16) |
df58fc94 | 8903 | { |
7f3c4072 CM |
8904 | /* The offset field is too narrow to be used for a low-part |
8905 | relocation, so load the whole address into the auxillary | |
8906 | register. In the case of "A(b)" addresses, we first load | |
8907 | absolute address "A" into the register and then add base | |
8908 | register "b". In the case of "o(b)" addresses, we simply | |
8909 | need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8910 | offset_reloc already contains the relocations associated |
8911 | with "o". */ | |
8912 | if (ab) | |
8913 | { | |
8914 | load_address (tempreg, &offset_expr, &used_at); | |
8915 | if (breg != 0) | |
8916 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8917 | tempreg, tempreg, breg); | |
8918 | } | |
8919 | else | |
8920 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8921 | tempreg, breg, -1, | |
8922 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8923 | expr1.X_add_number = 0; | |
7f3c4072 | 8924 | if (offbits == 0) |
dd6a37e7 AP |
8925 | macro_build (NULL, s, fmt, treg, tempreg); |
8926 | else | |
8927 | macro_build (NULL, s, fmt, | |
8928 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8929 | } |
8930 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8931 | { |
8932 | /* If this is a reference to a GP relative symbol, and there | |
8933 | is no base register, we want | |
cdf6fd85 | 8934 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8935 | Otherwise, if there is no base register, we want |
8936 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8937 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8938 | If we have a constant, we need two instructions anyhow, | |
8939 | so we always use the latter form. | |
8940 | ||
8941 | If we have a base register, and this is a reference to a | |
8942 | GP relative symbol, we want | |
8943 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8944 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8945 | Otherwise we want |
8946 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8947 | addu $tempreg,$tempreg,$breg | |
8948 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8949 | With a constant we always use the latter case. |
76b3015f | 8950 | |
d6bc6245 TS |
8951 | With 64bit address space and no base register and $at usable, |
8952 | we want | |
8953 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8954 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8955 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8956 | dsll32 $tempreg,0 | |
8957 | daddu $tempreg,$at | |
8958 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8959 | If we have a base register, we want | |
8960 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8961 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8962 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8963 | daddu $at,$breg | |
8964 | dsll32 $tempreg,0 | |
8965 | daddu $tempreg,$at | |
8966 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8967 | ||
8968 | Without $at we can't generate the optimal path for superscalar | |
8969 | processors here since this would require two temporary registers. | |
8970 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8971 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8972 | dsll $tempreg,16 | |
8973 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8974 | dsll $tempreg,16 | |
8975 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8976 | If we have a base register, we want | |
8977 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8978 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8979 | dsll $tempreg,16 | |
8980 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8981 | dsll $tempreg,16 | |
8982 | daddu $tempreg,$tempreg,$breg | |
8983 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8984 | |
6caf9ef4 | 8985 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8986 | the same sequence as in 32bit address space. */ |
8987 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8988 | { |
aed1a261 | 8989 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8990 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8991 | { | |
8992 | relax_start (offset_expr.X_add_symbol); | |
8993 | if (breg == 0) | |
8994 | { | |
8995 | macro_build (&offset_expr, s, fmt, treg, | |
8996 | BFD_RELOC_GPREL16, mips_gp_register); | |
8997 | } | |
8998 | else | |
8999 | { | |
9000 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9001 | tempreg, breg, mips_gp_register); | |
9002 | macro_build (&offset_expr, s, fmt, treg, | |
9003 | BFD_RELOC_GPREL16, tempreg); | |
9004 | } | |
9005 | relax_switch (); | |
9006 | } | |
d6bc6245 | 9007 | |
741fe287 | 9008 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 9009 | { |
df58fc94 | 9010 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 9011 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 9012 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
9013 | BFD_RELOC_HI16_S); |
9014 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
9015 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 9016 | if (breg != 0) |
67c0d1eb | 9017 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 9018 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
9019 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
9020 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
9021 | tempreg); | |
d6bc6245 TS |
9022 | used_at = 1; |
9023 | } | |
9024 | else | |
9025 | { | |
df58fc94 | 9026 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
9027 | BFD_RELOC_MIPS_HIGHEST); |
9028 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
9029 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9030 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
9031 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
9032 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 9033 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 9034 | if (breg != 0) |
67c0d1eb | 9035 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 9036 | tempreg, tempreg, breg); |
67c0d1eb | 9037 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9038 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 9039 | } |
6caf9ef4 TS |
9040 | |
9041 | if (mips_relax.sequence) | |
9042 | relax_end (); | |
8fc2e39e | 9043 | break; |
d6bc6245 | 9044 | } |
256ab948 | 9045 | |
252b5132 RH |
9046 | if (breg == 0) |
9047 | { | |
67c0d1eb | 9048 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9049 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9050 | { |
4d7206a2 | 9051 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9052 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
9053 | mips_gp_register); | |
4d7206a2 | 9054 | relax_switch (); |
252b5132 | 9055 | } |
67c0d1eb RS |
9056 | macro_build_lui (&offset_expr, tempreg); |
9057 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 9058 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9059 | if (mips_relax.sequence) |
9060 | relax_end (); | |
252b5132 RH |
9061 | } |
9062 | else | |
9063 | { | |
67c0d1eb | 9064 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9065 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9066 | { |
4d7206a2 | 9067 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 9068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9069 | tempreg, breg, mips_gp_register); |
67c0d1eb | 9070 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9071 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 9072 | relax_switch (); |
252b5132 | 9073 | } |
67c0d1eb RS |
9074 | macro_build_lui (&offset_expr, tempreg); |
9075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9076 | tempreg, tempreg, breg); |
67c0d1eb | 9077 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9078 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9079 | if (mips_relax.sequence) |
9080 | relax_end (); | |
252b5132 RH |
9081 | } |
9082 | } | |
0a44bf69 | 9083 | else if (!mips_big_got) |
252b5132 | 9084 | { |
ed6fb7bd | 9085 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 9086 | |
252b5132 RH |
9087 | /* If this is a reference to an external symbol, we want |
9088 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9089 | nop | |
9090 | <op> $treg,0($tempreg) | |
9091 | Otherwise we want | |
9092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9093 | nop | |
9094 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9095 | <op> $treg,0($tempreg) | |
f5040a92 AO |
9096 | |
9097 | For NewABI, we want | |
9098 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9099 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
9100 | ||
252b5132 RH |
9101 | If there is a base register, we add it to $tempreg before |
9102 | the <op>. If there is a constant, we stick it in the | |
9103 | <op> instruction. We don't handle constants larger than | |
9104 | 16 bits, because we have no way to load the upper 16 bits | |
9105 | (actually, we could handle them for the subset of cases | |
9106 | in which we are not using $at). */ | |
9c2799c2 | 9107 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
9108 | if (HAVE_NEWABI) |
9109 | { | |
67c0d1eb RS |
9110 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9111 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9112 | if (breg != 0) |
67c0d1eb | 9113 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9114 | tempreg, tempreg, breg); |
67c0d1eb | 9115 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9116 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
9117 | break; |
9118 | } | |
252b5132 RH |
9119 | expr1.X_add_number = offset_expr.X_add_number; |
9120 | offset_expr.X_add_number = 0; | |
9121 | if (expr1.X_add_number < -0x8000 | |
9122 | || expr1.X_add_number >= 0x8000) | |
9123 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
9124 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9125 | lw_reloc_type, mips_gp_register); | |
269137b2 | 9126 | load_delay_nop (); |
4d7206a2 RS |
9127 | relax_start (offset_expr.X_add_symbol); |
9128 | relax_switch (); | |
67c0d1eb RS |
9129 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9130 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9131 | relax_end (); |
252b5132 | 9132 | if (breg != 0) |
67c0d1eb | 9133 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9134 | tempreg, tempreg, breg); |
67c0d1eb | 9135 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9136 | } |
0a44bf69 | 9137 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 9138 | { |
67c0d1eb | 9139 | int gpdelay; |
252b5132 RH |
9140 | |
9141 | /* If this is a reference to an external symbol, we want | |
9142 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9143 | addu $tempreg,$tempreg,$gp | |
9144 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9145 | <op> $treg,0($tempreg) | |
9146 | Otherwise we want | |
9147 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9148 | nop | |
9149 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9150 | <op> $treg,0($tempreg) | |
9151 | If there is a base register, we add it to $tempreg before | |
9152 | the <op>. If there is a constant, we stick it in the | |
9153 | <op> instruction. We don't handle constants larger than | |
9154 | 16 bits, because we have no way to load the upper 16 bits | |
9155 | (actually, we could handle them for the subset of cases | |
f5040a92 | 9156 | in which we are not using $at). */ |
9c2799c2 | 9157 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
9158 | expr1.X_add_number = offset_expr.X_add_number; |
9159 | offset_expr.X_add_number = 0; | |
9160 | if (expr1.X_add_number < -0x8000 | |
9161 | || expr1.X_add_number >= 0x8000) | |
9162 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9163 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9164 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9165 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9166 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9167 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9168 | mips_gp_register); | |
9169 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9170 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 9171 | relax_switch (); |
67c0d1eb RS |
9172 | if (gpdelay) |
9173 | macro_build (NULL, "nop", ""); | |
9174 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9175 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9176 | load_delay_nop (); |
67c0d1eb RS |
9177 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9178 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9179 | relax_end (); |
9180 | ||
252b5132 | 9181 | if (breg != 0) |
67c0d1eb | 9182 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9183 | tempreg, tempreg, breg); |
67c0d1eb | 9184 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9185 | } |
0a44bf69 | 9186 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 9187 | { |
f5040a92 AO |
9188 | /* If this is a reference to an external symbol, we want |
9189 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9190 | add $tempreg,$tempreg,$gp | |
9191 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9192 | <op> $treg,<ofst>($tempreg) | |
9193 | Otherwise, for local symbols, we want: | |
9194 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9195 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 9196 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 9197 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
9198 | offset_expr.X_add_number = 0; |
9199 | if (expr1.X_add_number < -0x8000 | |
9200 | || expr1.X_add_number >= 0x8000) | |
9201 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 9202 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9203 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9204 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9205 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9206 | mips_gp_register); | |
9207 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9208 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 9209 | if (breg != 0) |
67c0d1eb | 9210 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9211 | tempreg, tempreg, breg); |
67c0d1eb | 9212 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 9213 | |
4d7206a2 | 9214 | relax_switch (); |
f5040a92 | 9215 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
9216 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9217 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9218 | if (breg != 0) |
67c0d1eb | 9219 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9220 | tempreg, tempreg, breg); |
67c0d1eb | 9221 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9222 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 9223 | relax_end (); |
f5040a92 | 9224 | } |
252b5132 RH |
9225 | else |
9226 | abort (); | |
9227 | ||
252b5132 RH |
9228 | break; |
9229 | ||
9230 | case M_LI: | |
9231 | case M_LI_S: | |
67c0d1eb | 9232 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 9233 | break; |
252b5132 RH |
9234 | |
9235 | case M_DLI: | |
67c0d1eb | 9236 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9237 | break; |
252b5132 RH |
9238 | |
9239 | case M_LI_SS: | |
9240 | if (imm_expr.X_op == O_constant) | |
9241 | { | |
8fc2e39e | 9242 | used_at = 1; |
67c0d1eb RS |
9243 | load_register (AT, &imm_expr, 0); |
9244 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9245 | break; |
9246 | } | |
9247 | else | |
9248 | { | |
9c2799c2 | 9249 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9250 | && strcmp (segment_name (S_GET_SEGMENT |
9251 | (offset_expr.X_add_symbol)), | |
9252 | ".lit4") == 0 | |
9253 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9254 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9255 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9256 | break; |
252b5132 RH |
9257 | } |
9258 | ||
9259 | case M_LI_D: | |
ca4e0257 RS |
9260 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9261 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9262 | order 32 bits of the value and the low order 32 bits are either | |
9263 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9264 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9265 | { | |
ca4e0257 | 9266 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9267 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9268 | else |
9269 | { | |
9270 | int hreg, lreg; | |
9271 | ||
9272 | if (target_big_endian) | |
9273 | { | |
9274 | hreg = treg; | |
9275 | lreg = treg + 1; | |
9276 | } | |
9277 | else | |
9278 | { | |
9279 | hreg = treg + 1; | |
9280 | lreg = treg; | |
9281 | } | |
9282 | ||
9283 | if (hreg <= 31) | |
67c0d1eb | 9284 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9285 | if (lreg <= 31) |
9286 | { | |
9287 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9288 | move_register (lreg, 0); |
252b5132 RH |
9289 | else |
9290 | { | |
9c2799c2 | 9291 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9292 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9293 | } |
9294 | } | |
9295 | } | |
8fc2e39e | 9296 | break; |
252b5132 RH |
9297 | } |
9298 | ||
9299 | /* We know that sym is in the .rdata section. First we get the | |
9300 | upper 16 bits of the address. */ | |
9301 | if (mips_pic == NO_PIC) | |
9302 | { | |
67c0d1eb | 9303 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9304 | used_at = 1; |
252b5132 | 9305 | } |
0a44bf69 | 9306 | else |
252b5132 | 9307 | { |
67c0d1eb RS |
9308 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9309 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9310 | used_at = 1; |
252b5132 | 9311 | } |
bdaaa2e1 | 9312 | |
252b5132 | 9313 | /* Now we load the register(s). */ |
ca4e0257 | 9314 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9315 | { |
9316 | used_at = 1; | |
9317 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9318 | } | |
252b5132 RH |
9319 | else |
9320 | { | |
8fc2e39e | 9321 | used_at = 1; |
67c0d1eb | 9322 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9323 | if (treg != RA) |
252b5132 RH |
9324 | { |
9325 | /* FIXME: How in the world do we deal with the possible | |
9326 | overflow here? */ | |
9327 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9328 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9329 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9330 | } |
9331 | } | |
252b5132 RH |
9332 | break; |
9333 | ||
9334 | case M_LI_DD: | |
ca4e0257 RS |
9335 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9336 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9337 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9338 | the value and the low order 32 bits are either zero or in | |
9339 | OFFSET_EXPR. */ | |
252b5132 RH |
9340 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9341 | { | |
8fc2e39e | 9342 | used_at = 1; |
67c0d1eb | 9343 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9344 | if (HAVE_64BIT_FPRS) |
9345 | { | |
9c2799c2 | 9346 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9347 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9348 | } |
252b5132 RH |
9349 | else |
9350 | { | |
67c0d1eb | 9351 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9352 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9353 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9354 | else |
9355 | { | |
9c2799c2 | 9356 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9357 | load_register (AT, &offset_expr, 0); |
9358 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9359 | } |
9360 | } | |
9361 | break; | |
9362 | } | |
9363 | ||
9c2799c2 | 9364 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9365 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9366 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9367 | if (strcmp (s, ".lit8") == 0) | |
9368 | { | |
0aa27725 | 9369 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9370 | { |
67c0d1eb | 9371 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 9372 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9373 | break; |
252b5132 | 9374 | } |
c9914766 | 9375 | breg = mips_gp_register; |
252b5132 RH |
9376 | r = BFD_RELOC_MIPS_LITERAL; |
9377 | goto dob; | |
9378 | } | |
9379 | else | |
9380 | { | |
9c2799c2 | 9381 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9382 | used_at = 1; |
0a44bf69 | 9383 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9384 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9385 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9386 | else |
9387 | { | |
9388 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9389 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9390 | } |
bdaaa2e1 | 9391 | |
0aa27725 | 9392 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9393 | { |
67c0d1eb RS |
9394 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9395 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9396 | break; |
9397 | } | |
9398 | breg = AT; | |
9399 | r = BFD_RELOC_LO16; | |
9400 | goto dob; | |
9401 | } | |
9402 | ||
9403 | case M_L_DOB: | |
252b5132 RH |
9404 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9405 | to adjust when loading from memory. */ | |
9406 | r = BFD_RELOC_LO16; | |
9407 | dob: | |
df58fc94 | 9408 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9409 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9410 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9411 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9412 | /* FIXME: A possible overflow which I don't know how to deal |
9413 | with. */ | |
9414 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9415 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9416 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9417 | break; |
9418 | ||
c4a68bea | 9419 | case M_S_DOB: |
df58fc94 | 9420 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9421 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9422 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9423 | to adjust when storing to memory. */ | |
9424 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9425 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9426 | offset_expr.X_add_number += 4; | |
9427 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9428 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9429 | break; | |
9430 | ||
252b5132 | 9431 | case M_L_DAB: |
df58fc94 | 9432 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9433 | /* |
9434 | * The MIPS assembler seems to check for X_add_number not | |
9435 | * being double aligned and generating: | |
9436 | * lui at,%hi(foo+1) | |
9437 | * addu at,at,v1 | |
9438 | * addiu at,at,%lo(foo+1) | |
9439 | * lwc1 f2,0(at) | |
9440 | * lwc1 f3,4(at) | |
9441 | * But, the resulting address is the same after relocation so why | |
9442 | * generate the extra instruction? | |
9443 | */ | |
bdaaa2e1 | 9444 | /* Itbl support may require additional care here. */ |
252b5132 | 9445 | coproc = 1; |
df58fc94 | 9446 | fmt = "T,o(b)"; |
0aa27725 | 9447 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9448 | { |
9449 | s = "ldc1"; | |
df58fc94 | 9450 | goto ld_st; |
252b5132 | 9451 | } |
252b5132 | 9452 | s = "lwc1"; |
252b5132 RH |
9453 | goto ldd_std; |
9454 | ||
9455 | case M_S_DAB: | |
df58fc94 RS |
9456 | gas_assert (!mips_opts.micromips); |
9457 | /* Itbl support may require additional care here. */ | |
9458 | coproc = 1; | |
9459 | fmt = "T,o(b)"; | |
0aa27725 | 9460 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9461 | { |
9462 | s = "sdc1"; | |
df58fc94 | 9463 | goto ld_st; |
252b5132 | 9464 | } |
252b5132 | 9465 | s = "swc1"; |
252b5132 RH |
9466 | goto ldd_std; |
9467 | ||
e407c74b NC |
9468 | case M_LQ_AB: |
9469 | fmt = "t,o(b)"; | |
9470 | s = "lq"; | |
9471 | goto ld; | |
9472 | ||
9473 | case M_SQ_AB: | |
9474 | fmt = "t,o(b)"; | |
9475 | s = "sq"; | |
9476 | goto ld_st; | |
9477 | ||
252b5132 | 9478 | case M_LD_AB: |
df58fc94 | 9479 | fmt = "t,o(b)"; |
ca4e0257 | 9480 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9481 | { |
9482 | s = "ld"; | |
9483 | goto ld; | |
9484 | } | |
252b5132 | 9485 | s = "lw"; |
252b5132 RH |
9486 | goto ldd_std; |
9487 | ||
9488 | case M_SD_AB: | |
df58fc94 | 9489 | fmt = "t,o(b)"; |
ca4e0257 | 9490 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9491 | { |
9492 | s = "sd"; | |
df58fc94 | 9493 | goto ld_st; |
252b5132 | 9494 | } |
252b5132 | 9495 | s = "sw"; |
252b5132 RH |
9496 | |
9497 | ldd_std: | |
9498 | if (offset_expr.X_op != O_symbol | |
9499 | && offset_expr.X_op != O_constant) | |
9500 | { | |
f71d0d44 | 9501 | as_bad (_("Expression too complex")); |
252b5132 RH |
9502 | offset_expr.X_op = O_constant; |
9503 | } | |
9504 | ||
2051e8c4 MR |
9505 | if (HAVE_32BIT_ADDRESSES |
9506 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9507 | { |
9508 | char value [32]; | |
9509 | ||
9510 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9511 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9512 | } |
2051e8c4 | 9513 | |
252b5132 RH |
9514 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9515 | to adjust when loading from memory. We set coproc if we must | |
9516 | load $fn+1 first. */ | |
bdaaa2e1 | 9517 | /* Itbl support may require additional care here. */ |
90ecf173 | 9518 | if (!target_big_endian) |
252b5132 RH |
9519 | coproc = 0; |
9520 | ||
90ecf173 | 9521 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9522 | { |
9523 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9524 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9525 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9526 | If we have a base register, we use this |
9527 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9528 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9529 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9530 | If this is not a GP relative symbol, we want |
9531 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9532 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9533 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9534 | If there is a base register, we add it to $at after the | |
9535 | lui instruction. If there is a constant, we always use | |
9536 | the last case. */ | |
39a59cf8 MR |
9537 | if (offset_expr.X_op == O_symbol |
9538 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9539 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9540 | { |
4d7206a2 | 9541 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9542 | if (breg == 0) |
9543 | { | |
c9914766 | 9544 | tempreg = mips_gp_register; |
252b5132 RH |
9545 | } |
9546 | else | |
9547 | { | |
67c0d1eb | 9548 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9549 | AT, breg, mips_gp_register); |
252b5132 | 9550 | tempreg = AT; |
252b5132 RH |
9551 | used_at = 1; |
9552 | } | |
9553 | ||
beae10d5 | 9554 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9555 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9556 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9557 | offset_expr.X_add_number += 4; |
9558 | ||
9559 | /* Set mips_optimize to 2 to avoid inserting an | |
9560 | undesired nop. */ | |
9561 | hold_mips_optimize = mips_optimize; | |
9562 | mips_optimize = 2; | |
beae10d5 | 9563 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9564 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9565 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9566 | mips_optimize = hold_mips_optimize; |
9567 | ||
4d7206a2 | 9568 | relax_switch (); |
252b5132 | 9569 | |
0970e49e | 9570 | offset_expr.X_add_number -= 4; |
252b5132 | 9571 | } |
8fc2e39e | 9572 | used_at = 1; |
67c0d1eb | 9573 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9574 | if (breg != 0) |
67c0d1eb | 9575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9576 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9577 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9578 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9579 | /* FIXME: How do we handle overflow here? */ |
9580 | offset_expr.X_add_number += 4; | |
beae10d5 | 9581 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9582 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9583 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9584 | if (mips_relax.sequence) |
9585 | relax_end (); | |
bdaaa2e1 | 9586 | } |
0a44bf69 | 9587 | else if (!mips_big_got) |
252b5132 | 9588 | { |
252b5132 RH |
9589 | /* If this is a reference to an external symbol, we want |
9590 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9591 | nop | |
9592 | <op> $treg,0($at) | |
9593 | <op> $treg+1,4($at) | |
9594 | Otherwise we want | |
9595 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9596 | nop | |
9597 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9598 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9599 | If there is a base register we add it to $at before the | |
9600 | lwc1 instructions. If there is a constant we include it | |
9601 | in the lwc1 instructions. */ | |
9602 | used_at = 1; | |
9603 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9604 | if (expr1.X_add_number < -0x8000 |
9605 | || expr1.X_add_number >= 0x8000 - 4) | |
9606 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9607 | load_got_offset (AT, &offset_expr); |
269137b2 | 9608 | load_delay_nop (); |
252b5132 | 9609 | if (breg != 0) |
67c0d1eb | 9610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9611 | |
9612 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9613 | nop. */ | |
9614 | hold_mips_optimize = mips_optimize; | |
9615 | mips_optimize = 2; | |
4d7206a2 | 9616 | |
beae10d5 | 9617 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9618 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9619 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9620 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9621 | expr1.X_add_number += 4; |
67c0d1eb RS |
9622 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9623 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9624 | relax_switch (); |
67c0d1eb RS |
9625 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9626 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9627 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9628 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9629 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9630 | relax_end (); |
252b5132 | 9631 | |
4d7206a2 | 9632 | mips_optimize = hold_mips_optimize; |
252b5132 | 9633 | } |
0a44bf69 | 9634 | else if (mips_big_got) |
252b5132 | 9635 | { |
67c0d1eb | 9636 | int gpdelay; |
252b5132 RH |
9637 | |
9638 | /* If this is a reference to an external symbol, we want | |
9639 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9640 | addu $at,$at,$gp | |
9641 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9642 | nop | |
9643 | <op> $treg,0($at) | |
9644 | <op> $treg+1,4($at) | |
9645 | Otherwise we want | |
9646 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9647 | nop | |
9648 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9649 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9650 | If there is a base register we add it to $at before the | |
9651 | lwc1 instructions. If there is a constant we include it | |
9652 | in the lwc1 instructions. */ | |
9653 | used_at = 1; | |
9654 | expr1.X_add_number = offset_expr.X_add_number; | |
9655 | offset_expr.X_add_number = 0; | |
9656 | if (expr1.X_add_number < -0x8000 | |
9657 | || expr1.X_add_number >= 0x8000 - 4) | |
9658 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9659 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9660 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9661 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9662 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9663 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9664 | AT, AT, mips_gp_register); |
67c0d1eb | 9665 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9666 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9667 | load_delay_nop (); |
252b5132 | 9668 | if (breg != 0) |
67c0d1eb | 9669 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9670 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9671 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9672 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9673 | expr1.X_add_number += 4; |
9674 | ||
9675 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9676 | nop. */ | |
9677 | hold_mips_optimize = mips_optimize; | |
9678 | mips_optimize = 2; | |
beae10d5 | 9679 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9680 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9681 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9682 | mips_optimize = hold_mips_optimize; |
9683 | expr1.X_add_number -= 4; | |
9684 | ||
4d7206a2 RS |
9685 | relax_switch (); |
9686 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9687 | if (gpdelay) |
9688 | macro_build (NULL, "nop", ""); | |
9689 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9690 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9691 | load_delay_nop (); |
252b5132 | 9692 | if (breg != 0) |
67c0d1eb | 9693 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9694 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9695 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9696 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9697 | offset_expr.X_add_number += 4; |
252b5132 RH |
9698 | |
9699 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9700 | nop. */ | |
9701 | hold_mips_optimize = mips_optimize; | |
9702 | mips_optimize = 2; | |
beae10d5 | 9703 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9704 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9705 | BFD_RELOC_LO16, AT); | |
252b5132 | 9706 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9707 | relax_end (); |
252b5132 | 9708 | } |
252b5132 RH |
9709 | else |
9710 | abort (); | |
9711 | ||
252b5132 RH |
9712 | break; |
9713 | ||
9714 | case M_LD_OB: | |
704897fb | 9715 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9716 | goto sd_ob; |
9717 | case M_SD_OB: | |
704897fb | 9718 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9719 | sd_ob: |
4614d845 MR |
9720 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9721 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9722 | breg); | |
704897fb MR |
9723 | if (!HAVE_64BIT_GPRS) |
9724 | { | |
9725 | offset_expr.X_add_number += 4; | |
9726 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9727 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9728 | breg); | |
704897fb | 9729 | } |
8fc2e39e | 9730 | break; |
252b5132 | 9731 | |
dd6a37e7 AP |
9732 | |
9733 | case M_SAA_AB: | |
9734 | ab = 1; | |
9735 | case M_SAA_OB: | |
9736 | s = "saa"; | |
7f3c4072 | 9737 | offbits = 0; |
dd6a37e7 AP |
9738 | fmt = "t,(b)"; |
9739 | goto ld_st; | |
9740 | case M_SAAD_AB: | |
9741 | ab = 1; | |
9742 | case M_SAAD_OB: | |
9743 | s = "saad"; | |
7f3c4072 | 9744 | offbits = 0; |
dd6a37e7 AP |
9745 | fmt = "t,(b)"; |
9746 | goto ld_st; | |
9747 | ||
252b5132 RH |
9748 | /* New code added to support COPZ instructions. |
9749 | This code builds table entries out of the macros in mip_opcodes. | |
9750 | R4000 uses interlocks to handle coproc delays. | |
9751 | Other chips (like the R3000) require nops to be inserted for delays. | |
9752 | ||
f72c8c98 | 9753 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9754 | In order to fill delay slots for non-interlocked chips, |
9755 | we must have a way to specify delays based on the coprocessor. | |
9756 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9757 | What are the side-effects of the cop instruction? | |
9758 | What cache support might we have and what are its effects? | |
9759 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9760 | What registers are read/set/modified? |
252b5132 RH |
9761 | |
9762 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9763 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9764 | |
9765 | case M_COP0: | |
9766 | s = "c0"; | |
9767 | goto copz; | |
9768 | case M_COP1: | |
9769 | s = "c1"; | |
9770 | goto copz; | |
9771 | case M_COP2: | |
9772 | s = "c2"; | |
9773 | goto copz; | |
9774 | case M_COP3: | |
9775 | s = "c3"; | |
9776 | copz: | |
df58fc94 | 9777 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9778 | /* For now we just do C (same as Cz). The parameter will be |
9779 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9780 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9781 | break; |
252b5132 | 9782 | |
ea1fb5dc | 9783 | case M_MOVE: |
67c0d1eb | 9784 | move_register (dreg, sreg); |
8fc2e39e | 9785 | break; |
ea1fb5dc | 9786 | |
252b5132 RH |
9787 | case M_DMUL: |
9788 | dbl = 1; | |
9789 | case M_MUL: | |
e407c74b NC |
9790 | if (mips_opts.arch == CPU_R5900) |
9791 | { | |
9792 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9793 | } | |
9794 | else | |
9795 | { | |
67c0d1eb | 9796 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9797 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9798 | } |
8fc2e39e | 9799 | break; |
252b5132 RH |
9800 | |
9801 | case M_DMUL_I: | |
9802 | dbl = 1; | |
9803 | case M_MUL_I: | |
9804 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9805 | not trying to be that fancy. GCC should do this for us | |
9806 | anyway. */ | |
8fc2e39e | 9807 | used_at = 1; |
67c0d1eb RS |
9808 | load_register (AT, &imm_expr, dbl); |
9809 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9810 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9811 | break; |
9812 | ||
9813 | case M_DMULO_I: | |
9814 | dbl = 1; | |
9815 | case M_MULO_I: | |
9816 | imm = 1; | |
9817 | goto do_mulo; | |
9818 | ||
9819 | case M_DMULO: | |
9820 | dbl = 1; | |
9821 | case M_MULO: | |
9822 | do_mulo: | |
7d10b47d | 9823 | start_noreorder (); |
8fc2e39e | 9824 | used_at = 1; |
252b5132 | 9825 | if (imm) |
67c0d1eb RS |
9826 | load_register (AT, &imm_expr, dbl); |
9827 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9828 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9829 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9830 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9831 | if (mips_trap) |
df58fc94 | 9832 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9833 | else |
9834 | { | |
df58fc94 RS |
9835 | if (mips_opts.micromips) |
9836 | micromips_label_expr (&label_expr); | |
9837 | else | |
9838 | label_expr.X_add_number = 8; | |
9839 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9840 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9841 | macro_build (NULL, "break", BRK_FMT, 6); |
9842 | if (mips_opts.micromips) | |
9843 | micromips_add_label (); | |
252b5132 | 9844 | } |
7d10b47d | 9845 | end_noreorder (); |
df58fc94 | 9846 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9847 | break; |
9848 | ||
9849 | case M_DMULOU_I: | |
9850 | dbl = 1; | |
9851 | case M_MULOU_I: | |
9852 | imm = 1; | |
9853 | goto do_mulou; | |
9854 | ||
9855 | case M_DMULOU: | |
9856 | dbl = 1; | |
9857 | case M_MULOU: | |
9858 | do_mulou: | |
7d10b47d | 9859 | start_noreorder (); |
8fc2e39e | 9860 | used_at = 1; |
252b5132 | 9861 | if (imm) |
67c0d1eb RS |
9862 | load_register (AT, &imm_expr, dbl); |
9863 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9864 | sreg, imm ? AT : treg); |
df58fc94 RS |
9865 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9866 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9867 | if (mips_trap) |
df58fc94 | 9868 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9869 | else |
9870 | { | |
df58fc94 RS |
9871 | if (mips_opts.micromips) |
9872 | micromips_label_expr (&label_expr); | |
9873 | else | |
9874 | label_expr.X_add_number = 8; | |
9875 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9876 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9877 | macro_build (NULL, "break", BRK_FMT, 6); |
9878 | if (mips_opts.micromips) | |
9879 | micromips_add_label (); | |
252b5132 | 9880 | } |
7d10b47d | 9881 | end_noreorder (); |
252b5132 RH |
9882 | break; |
9883 | ||
771c7ce4 | 9884 | case M_DROL: |
fef14a42 | 9885 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9886 | { |
9887 | if (dreg == sreg) | |
9888 | { | |
9889 | tempreg = AT; | |
9890 | used_at = 1; | |
9891 | } | |
9892 | else | |
9893 | { | |
9894 | tempreg = dreg; | |
82dd0097 | 9895 | } |
67c0d1eb RS |
9896 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9897 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9898 | break; |
82dd0097 | 9899 | } |
8fc2e39e | 9900 | used_at = 1; |
c80c840e | 9901 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9902 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9903 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9904 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9905 | break; |
9906 | ||
252b5132 | 9907 | case M_ROL: |
fef14a42 | 9908 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9909 | { |
9910 | if (dreg == sreg) | |
9911 | { | |
9912 | tempreg = AT; | |
9913 | used_at = 1; | |
9914 | } | |
9915 | else | |
9916 | { | |
9917 | tempreg = dreg; | |
82dd0097 | 9918 | } |
67c0d1eb RS |
9919 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9920 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9921 | break; |
82dd0097 | 9922 | } |
8fc2e39e | 9923 | used_at = 1; |
c80c840e | 9924 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9925 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9926 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9927 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9928 | break; |
9929 | ||
771c7ce4 TS |
9930 | case M_DROL_I: |
9931 | { | |
9932 | unsigned int rot; | |
91d6fa6a NC |
9933 | char *l; |
9934 | char *rr; | |
771c7ce4 TS |
9935 | |
9936 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9937 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9938 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9939 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9940 | { |
9941 | rot = (64 - rot) & 0x3f; | |
9942 | if (rot >= 32) | |
df58fc94 | 9943 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9944 | else |
df58fc94 | 9945 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9946 | break; |
60b63b72 | 9947 | } |
483fc7cd | 9948 | if (rot == 0) |
483fc7cd | 9949 | { |
df58fc94 | 9950 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9951 | break; |
483fc7cd | 9952 | } |
82dd0097 | 9953 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9954 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9955 | rot &= 0x1f; |
8fc2e39e | 9956 | used_at = 1; |
df58fc94 RS |
9957 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9958 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9959 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9960 | } |
9961 | break; | |
9962 | ||
252b5132 | 9963 | case M_ROL_I: |
771c7ce4 TS |
9964 | { |
9965 | unsigned int rot; | |
9966 | ||
9967 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9968 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9969 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9970 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9971 | { |
df58fc94 | 9972 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9973 | break; |
60b63b72 | 9974 | } |
483fc7cd | 9975 | if (rot == 0) |
483fc7cd | 9976 | { |
df58fc94 | 9977 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9978 | break; |
483fc7cd | 9979 | } |
8fc2e39e | 9980 | used_at = 1; |
df58fc94 RS |
9981 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9982 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9983 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9984 | } |
9985 | break; | |
9986 | ||
9987 | case M_DROR: | |
fef14a42 | 9988 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9989 | { |
67c0d1eb | 9990 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9991 | break; |
82dd0097 | 9992 | } |
8fc2e39e | 9993 | used_at = 1; |
c80c840e | 9994 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9995 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9996 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9997 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9998 | break; |
9999 | ||
10000 | case M_ROR: | |
fef14a42 | 10001 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10002 | { |
67c0d1eb | 10003 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 10004 | break; |
82dd0097 | 10005 | } |
8fc2e39e | 10006 | used_at = 1; |
c80c840e | 10007 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
10008 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
10009 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
10010 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
10011 | break; |
10012 | ||
771c7ce4 TS |
10013 | case M_DROR_I: |
10014 | { | |
10015 | unsigned int rot; | |
91d6fa6a NC |
10016 | char *l; |
10017 | char *rr; | |
771c7ce4 TS |
10018 | |
10019 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10020 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10021 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 10022 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
10023 | { |
10024 | if (rot >= 32) | |
df58fc94 | 10025 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 10026 | else |
df58fc94 | 10027 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10028 | break; |
82dd0097 | 10029 | } |
483fc7cd | 10030 | if (rot == 0) |
483fc7cd | 10031 | { |
df58fc94 | 10032 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10033 | break; |
483fc7cd | 10034 | } |
91d6fa6a | 10035 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
10036 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
10037 | rot &= 0x1f; | |
8fc2e39e | 10038 | used_at = 1; |
df58fc94 RS |
10039 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
10040 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10041 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
10042 | } |
10043 | break; | |
10044 | ||
252b5132 | 10045 | case M_ROR_I: |
771c7ce4 TS |
10046 | { |
10047 | unsigned int rot; | |
10048 | ||
10049 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10050 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10051 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 10052 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10053 | { |
df58fc94 | 10054 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10055 | break; |
82dd0097 | 10056 | } |
483fc7cd | 10057 | if (rot == 0) |
483fc7cd | 10058 | { |
df58fc94 | 10059 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10060 | break; |
483fc7cd | 10061 | } |
8fc2e39e | 10062 | used_at = 1; |
df58fc94 RS |
10063 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
10064 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10065 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 10066 | } |
252b5132 RH |
10067 | break; |
10068 | ||
252b5132 RH |
10069 | case M_SEQ: |
10070 | if (sreg == 0) | |
67c0d1eb | 10071 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 10072 | else if (treg == 0) |
67c0d1eb | 10073 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10074 | else |
10075 | { | |
67c0d1eb RS |
10076 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10077 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 10078 | } |
8fc2e39e | 10079 | break; |
252b5132 RH |
10080 | |
10081 | case M_SEQ_I: | |
10082 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10083 | { | |
67c0d1eb | 10084 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10085 | break; |
252b5132 RH |
10086 | } |
10087 | if (sreg == 0) | |
10088 | { | |
10089 | as_warn (_("Instruction %s: result is always false"), | |
10090 | ip->insn_mo->name); | |
67c0d1eb | 10091 | move_register (dreg, 0); |
8fc2e39e | 10092 | break; |
252b5132 | 10093 | } |
dd3cbb7e NC |
10094 | if (CPU_HAS_SEQ (mips_opts.arch) |
10095 | && -512 <= imm_expr.X_add_number | |
10096 | && imm_expr.X_add_number < 512) | |
10097 | { | |
10098 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10099 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10100 | break; |
10101 | } | |
252b5132 RH |
10102 | if (imm_expr.X_op == O_constant |
10103 | && imm_expr.X_add_number >= 0 | |
10104 | && imm_expr.X_add_number < 0x10000) | |
10105 | { | |
67c0d1eb | 10106 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10107 | } |
10108 | else if (imm_expr.X_op == O_constant | |
10109 | && imm_expr.X_add_number > -0x8000 | |
10110 | && imm_expr.X_add_number < 0) | |
10111 | { | |
10112 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10113 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10114 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10115 | } |
dd3cbb7e NC |
10116 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10117 | { | |
10118 | used_at = 1; | |
10119 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10120 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
10121 | break; | |
10122 | } | |
252b5132 RH |
10123 | else |
10124 | { | |
67c0d1eb RS |
10125 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10126 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10127 | used_at = 1; |
10128 | } | |
67c0d1eb | 10129 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10130 | break; |
252b5132 RH |
10131 | |
10132 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
10133 | s = "slt"; | |
10134 | goto sge; | |
10135 | case M_SGEU: | |
10136 | s = "sltu"; | |
10137 | sge: | |
67c0d1eb RS |
10138 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
10139 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10140 | break; |
252b5132 RH |
10141 | |
10142 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
10143 | case M_SGEU_I: | |
10144 | if (imm_expr.X_op == O_constant | |
10145 | && imm_expr.X_add_number >= -0x8000 | |
10146 | && imm_expr.X_add_number < 0x8000) | |
10147 | { | |
67c0d1eb RS |
10148 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
10149 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
10150 | } |
10151 | else | |
10152 | { | |
67c0d1eb RS |
10153 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10154 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
10155 | dreg, sreg, AT); | |
252b5132 RH |
10156 | used_at = 1; |
10157 | } | |
67c0d1eb | 10158 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10159 | break; |
252b5132 RH |
10160 | |
10161 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
10162 | s = "slt"; | |
10163 | goto sgt; | |
10164 | case M_SGTU: | |
10165 | s = "sltu"; | |
10166 | sgt: | |
67c0d1eb | 10167 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 10168 | break; |
252b5132 RH |
10169 | |
10170 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
10171 | s = "slt"; | |
10172 | goto sgti; | |
10173 | case M_SGTU_I: | |
10174 | s = "sltu"; | |
10175 | sgti: | |
8fc2e39e | 10176 | used_at = 1; |
67c0d1eb RS |
10177 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10178 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
10179 | break; |
10180 | ||
2396cfb9 | 10181 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
10182 | s = "slt"; |
10183 | goto sle; | |
10184 | case M_SLEU: | |
10185 | s = "sltu"; | |
10186 | sle: | |
67c0d1eb RS |
10187 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
10188 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10189 | break; |
252b5132 | 10190 | |
2396cfb9 | 10191 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
10192 | s = "slt"; |
10193 | goto slei; | |
10194 | case M_SLEU_I: | |
10195 | s = "sltu"; | |
10196 | slei: | |
8fc2e39e | 10197 | used_at = 1; |
67c0d1eb RS |
10198 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10199 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
10200 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
10201 | break; |
10202 | ||
10203 | case M_SLT_I: | |
10204 | if (imm_expr.X_op == O_constant | |
10205 | && imm_expr.X_add_number >= -0x8000 | |
10206 | && imm_expr.X_add_number < 0x8000) | |
10207 | { | |
67c0d1eb | 10208 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10209 | break; |
252b5132 | 10210 | } |
8fc2e39e | 10211 | used_at = 1; |
67c0d1eb RS |
10212 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10213 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10214 | break; |
10215 | ||
10216 | case M_SLTU_I: | |
10217 | if (imm_expr.X_op == O_constant | |
10218 | && imm_expr.X_add_number >= -0x8000 | |
10219 | && imm_expr.X_add_number < 0x8000) | |
10220 | { | |
67c0d1eb | 10221 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 10222 | BFD_RELOC_LO16); |
8fc2e39e | 10223 | break; |
252b5132 | 10224 | } |
8fc2e39e | 10225 | used_at = 1; |
67c0d1eb RS |
10226 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10227 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10228 | break; |
10229 | ||
10230 | case M_SNE: | |
10231 | if (sreg == 0) | |
67c0d1eb | 10232 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 10233 | else if (treg == 0) |
67c0d1eb | 10234 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10235 | else |
10236 | { | |
67c0d1eb RS |
10237 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10238 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10239 | } |
8fc2e39e | 10240 | break; |
252b5132 RH |
10241 | |
10242 | case M_SNE_I: | |
10243 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10244 | { | |
67c0d1eb | 10245 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10246 | break; |
252b5132 RH |
10247 | } |
10248 | if (sreg == 0) | |
10249 | { | |
10250 | as_warn (_("Instruction %s: result is always true"), | |
10251 | ip->insn_mo->name); | |
67c0d1eb RS |
10252 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10253 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10254 | break; |
252b5132 | 10255 | } |
dd3cbb7e NC |
10256 | if (CPU_HAS_SEQ (mips_opts.arch) |
10257 | && -512 <= imm_expr.X_add_number | |
10258 | && imm_expr.X_add_number < 512) | |
10259 | { | |
10260 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10261 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10262 | break; |
10263 | } | |
252b5132 RH |
10264 | if (imm_expr.X_op == O_constant |
10265 | && imm_expr.X_add_number >= 0 | |
10266 | && imm_expr.X_add_number < 0x10000) | |
10267 | { | |
67c0d1eb | 10268 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10269 | } |
10270 | else if (imm_expr.X_op == O_constant | |
10271 | && imm_expr.X_add_number > -0x8000 | |
10272 | && imm_expr.X_add_number < 0) | |
10273 | { | |
10274 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10275 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10276 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10277 | } |
dd3cbb7e NC |
10278 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10279 | { | |
10280 | used_at = 1; | |
10281 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10282 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10283 | break; | |
10284 | } | |
252b5132 RH |
10285 | else |
10286 | { | |
67c0d1eb RS |
10287 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10288 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10289 | used_at = 1; |
10290 | } | |
67c0d1eb | 10291 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10292 | break; |
252b5132 | 10293 | |
df58fc94 RS |
10294 | case M_SUB_I: |
10295 | s = "addi"; | |
10296 | s2 = "sub"; | |
10297 | goto do_subi; | |
10298 | case M_SUBU_I: | |
10299 | s = "addiu"; | |
10300 | s2 = "subu"; | |
10301 | goto do_subi; | |
252b5132 RH |
10302 | case M_DSUB_I: |
10303 | dbl = 1; | |
df58fc94 RS |
10304 | s = "daddi"; |
10305 | s2 = "dsub"; | |
10306 | if (!mips_opts.micromips) | |
10307 | goto do_subi; | |
252b5132 | 10308 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10309 | && imm_expr.X_add_number > -0x200 |
10310 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10311 | { |
df58fc94 | 10312 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10313 | break; |
252b5132 | 10314 | } |
df58fc94 | 10315 | goto do_subi_i; |
252b5132 RH |
10316 | case M_DSUBU_I: |
10317 | dbl = 1; | |
df58fc94 RS |
10318 | s = "daddiu"; |
10319 | s2 = "dsubu"; | |
10320 | do_subi: | |
252b5132 RH |
10321 | if (imm_expr.X_op == O_constant |
10322 | && imm_expr.X_add_number > -0x8000 | |
10323 | && imm_expr.X_add_number <= 0x8000) | |
10324 | { | |
10325 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10326 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10327 | break; |
252b5132 | 10328 | } |
df58fc94 | 10329 | do_subi_i: |
8fc2e39e | 10330 | used_at = 1; |
67c0d1eb | 10331 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10332 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10333 | break; |
10334 | ||
10335 | case M_TEQ_I: | |
10336 | s = "teq"; | |
10337 | goto trap; | |
10338 | case M_TGE_I: | |
10339 | s = "tge"; | |
10340 | goto trap; | |
10341 | case M_TGEU_I: | |
10342 | s = "tgeu"; | |
10343 | goto trap; | |
10344 | case M_TLT_I: | |
10345 | s = "tlt"; | |
10346 | goto trap; | |
10347 | case M_TLTU_I: | |
10348 | s = "tltu"; | |
10349 | goto trap; | |
10350 | case M_TNE_I: | |
10351 | s = "tne"; | |
10352 | trap: | |
8fc2e39e | 10353 | used_at = 1; |
67c0d1eb RS |
10354 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10355 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10356 | break; |
10357 | ||
252b5132 | 10358 | case M_TRUNCWS: |
43841e91 | 10359 | case M_TRUNCWD: |
df58fc94 | 10360 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10361 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10362 | used_at = 1; |
252b5132 RH |
10363 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10364 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10365 | ||
10366 | /* | |
10367 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10368 | * or is there a reason for it? | |
10369 | */ | |
7d10b47d | 10370 | start_noreorder (); |
67c0d1eb RS |
10371 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10372 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10373 | macro_build (NULL, "nop", ""); | |
252b5132 | 10374 | expr1.X_add_number = 3; |
67c0d1eb | 10375 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10376 | expr1.X_add_number = 2; |
67c0d1eb RS |
10377 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10378 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10379 | macro_build (NULL, "nop", ""); | |
10380 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10381 | dreg, sreg); | |
10382 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10383 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10384 | end_noreorder (); |
252b5132 RH |
10385 | break; |
10386 | ||
df58fc94 RS |
10387 | case M_ULH_A: |
10388 | ab = 1; | |
252b5132 RH |
10389 | case M_ULH: |
10390 | s = "lb"; | |
df58fc94 RS |
10391 | s2 = "lbu"; |
10392 | off = 1; | |
10393 | goto uld_st; | |
10394 | case M_ULHU_A: | |
10395 | ab = 1; | |
252b5132 RH |
10396 | case M_ULHU: |
10397 | s = "lbu"; | |
df58fc94 RS |
10398 | s2 = "lbu"; |
10399 | off = 1; | |
10400 | goto uld_st; | |
10401 | case M_ULW_A: | |
10402 | ab = 1; | |
10403 | case M_ULW: | |
10404 | s = "lwl"; | |
10405 | s2 = "lwr"; | |
7f3c4072 | 10406 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10407 | off = 3; |
10408 | goto uld_st; | |
10409 | case M_ULD_A: | |
10410 | ab = 1; | |
252b5132 RH |
10411 | case M_ULD: |
10412 | s = "ldl"; | |
10413 | s2 = "ldr"; | |
7f3c4072 | 10414 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10415 | off = 7; |
df58fc94 RS |
10416 | goto uld_st; |
10417 | case M_USH_A: | |
10418 | ab = 1; | |
10419 | case M_USH: | |
10420 | s = "sb"; | |
10421 | s2 = "sb"; | |
10422 | off = 1; | |
10423 | ust = 1; | |
10424 | goto uld_st; | |
10425 | case M_USW_A: | |
10426 | ab = 1; | |
10427 | case M_USW: | |
10428 | s = "swl"; | |
10429 | s2 = "swr"; | |
7f3c4072 | 10430 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10431 | off = 3; |
df58fc94 RS |
10432 | ust = 1; |
10433 | goto uld_st; | |
10434 | case M_USD_A: | |
10435 | ab = 1; | |
10436 | case M_USD: | |
10437 | s = "sdl"; | |
10438 | s2 = "sdr"; | |
7f3c4072 | 10439 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10440 | off = 7; |
10441 | ust = 1; | |
10442 | ||
10443 | uld_st: | |
10444 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10445 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10446 | |
10447 | ep = &offset_expr; | |
10448 | expr1.X_add_number = 0; | |
10449 | if (ab) | |
10450 | { | |
10451 | used_at = 1; | |
10452 | tempreg = AT; | |
10453 | load_address (tempreg, ep, &used_at); | |
10454 | if (breg != 0) | |
10455 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10456 | tempreg, tempreg, breg); | |
10457 | breg = tempreg; | |
10458 | tempreg = treg; | |
10459 | ep = &expr1; | |
10460 | } | |
7f3c4072 | 10461 | else if (offbits == 12 |
df58fc94 RS |
10462 | && (offset_expr.X_op != O_constant |
10463 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10464 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10465 | { | |
10466 | used_at = 1; | |
10467 | tempreg = AT; | |
10468 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10469 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10470 | breg = tempreg; | |
10471 | tempreg = treg; | |
10472 | ep = &expr1; | |
10473 | } | |
10474 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10475 | { |
10476 | used_at = 1; | |
10477 | tempreg = AT; | |
10478 | } | |
252b5132 | 10479 | else |
df58fc94 | 10480 | tempreg = treg; |
af22f5b2 | 10481 | |
df58fc94 RS |
10482 | if (off == 1) |
10483 | goto ulh_sh; | |
252b5132 | 10484 | |
90ecf173 | 10485 | if (!target_big_endian) |
df58fc94 | 10486 | ep->X_add_number += off; |
7f3c4072 | 10487 | if (offbits != 12) |
df58fc94 | 10488 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 | 10489 | else |
df58fc94 RS |
10490 | macro_build (NULL, s, "t,~(b)", |
10491 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10492 | ||
90ecf173 | 10493 | if (!target_big_endian) |
df58fc94 | 10494 | ep->X_add_number -= off; |
252b5132 | 10495 | else |
df58fc94 | 10496 | ep->X_add_number += off; |
7f3c4072 | 10497 | if (offbits != 12) |
df58fc94 RS |
10498 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
10499 | else | |
10500 | macro_build (NULL, s2, "t,~(b)", | |
10501 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10502 | |
df58fc94 RS |
10503 | /* If necessary, move the result in tempreg to the final destination. */ |
10504 | if (!ust && treg != tempreg) | |
10505 | { | |
10506 | /* Protect second load's delay slot. */ | |
10507 | load_delay_nop (); | |
10508 | move_register (treg, tempreg); | |
10509 | } | |
8fc2e39e | 10510 | break; |
252b5132 | 10511 | |
df58fc94 | 10512 | ulh_sh: |
d6bc6245 | 10513 | used_at = 1; |
df58fc94 RS |
10514 | if (target_big_endian == ust) |
10515 | ep->X_add_number += off; | |
10516 | tempreg = ust || ab ? treg : AT; | |
10517 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10518 | ||
10519 | /* For halfword transfers we need a temporary register to shuffle | |
10520 | bytes. Unfortunately for M_USH_A we have none available before | |
10521 | the next store as AT holds the base address. We deal with this | |
10522 | case by clobbering TREG and then restoring it as with ULH. */ | |
10523 | tempreg = ust == ab ? treg : AT; | |
10524 | if (ust) | |
10525 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10526 | ||
10527 | if (target_big_endian == ust) | |
10528 | ep->X_add_number -= off; | |
252b5132 | 10529 | else |
df58fc94 RS |
10530 | ep->X_add_number += off; |
10531 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10532 | |
df58fc94 RS |
10533 | /* For M_USH_A re-retrieve the LSB. */ |
10534 | if (ust && ab) | |
10535 | { | |
10536 | if (target_big_endian) | |
10537 | ep->X_add_number += off; | |
10538 | else | |
10539 | ep->X_add_number -= off; | |
10540 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10541 | } | |
10542 | /* For ULH and M_USH_A OR the LSB in. */ | |
10543 | if (!ust || ab) | |
10544 | { | |
10545 | tempreg = !ab ? AT : treg; | |
10546 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10547 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10548 | } | |
252b5132 RH |
10549 | break; |
10550 | ||
10551 | default: | |
10552 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10553 | are added dynamically. */ |
252b5132 RH |
10554 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10555 | break; | |
10556 | } | |
741fe287 | 10557 | if (!mips_opts.at && used_at) |
8fc2e39e | 10558 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10559 | } |
10560 | ||
10561 | /* Implement macros in mips16 mode. */ | |
10562 | ||
10563 | static void | |
17a2f251 | 10564 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10565 | { |
10566 | int mask; | |
10567 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10568 | expressionS expr1; |
10569 | int dbl; | |
10570 | const char *s, *s2, *s3; | |
10571 | ||
10572 | mask = ip->insn_mo->mask; | |
10573 | ||
bf12938e RS |
10574 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10575 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10576 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10577 | |
252b5132 RH |
10578 | expr1.X_op = O_constant; |
10579 | expr1.X_op_symbol = NULL; | |
10580 | expr1.X_add_symbol = NULL; | |
10581 | expr1.X_add_number = 1; | |
10582 | ||
10583 | dbl = 0; | |
10584 | ||
10585 | switch (mask) | |
10586 | { | |
10587 | default: | |
b37df7c4 | 10588 | abort (); |
252b5132 RH |
10589 | |
10590 | case M_DDIV_3: | |
10591 | dbl = 1; | |
10592 | case M_DIV_3: | |
10593 | s = "mflo"; | |
10594 | goto do_div3; | |
10595 | case M_DREM_3: | |
10596 | dbl = 1; | |
10597 | case M_REM_3: | |
10598 | s = "mfhi"; | |
10599 | do_div3: | |
7d10b47d | 10600 | start_noreorder (); |
67c0d1eb | 10601 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10602 | expr1.X_add_number = 2; |
67c0d1eb RS |
10603 | macro_build (&expr1, "bnez", "x,p", yreg); |
10604 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10605 | |
252b5132 RH |
10606 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10607 | since that causes an overflow. We should do that as well, | |
10608 | but I don't see how to do the comparisons without a temporary | |
10609 | register. */ | |
7d10b47d | 10610 | end_noreorder (); |
67c0d1eb | 10611 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10612 | break; |
10613 | ||
10614 | case M_DIVU_3: | |
10615 | s = "divu"; | |
10616 | s2 = "mflo"; | |
10617 | goto do_divu3; | |
10618 | case M_REMU_3: | |
10619 | s = "divu"; | |
10620 | s2 = "mfhi"; | |
10621 | goto do_divu3; | |
10622 | case M_DDIVU_3: | |
10623 | s = "ddivu"; | |
10624 | s2 = "mflo"; | |
10625 | goto do_divu3; | |
10626 | case M_DREMU_3: | |
10627 | s = "ddivu"; | |
10628 | s2 = "mfhi"; | |
10629 | do_divu3: | |
7d10b47d | 10630 | start_noreorder (); |
67c0d1eb | 10631 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10632 | expr1.X_add_number = 2; |
67c0d1eb RS |
10633 | macro_build (&expr1, "bnez", "x,p", yreg); |
10634 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10635 | end_noreorder (); |
67c0d1eb | 10636 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10637 | break; |
10638 | ||
10639 | case M_DMUL: | |
10640 | dbl = 1; | |
10641 | case M_MUL: | |
67c0d1eb RS |
10642 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10643 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10644 | break; |
252b5132 RH |
10645 | |
10646 | case M_DSUBU_I: | |
10647 | dbl = 1; | |
10648 | goto do_subu; | |
10649 | case M_SUBU_I: | |
10650 | do_subu: | |
10651 | if (imm_expr.X_op != O_constant) | |
10652 | as_bad (_("Unsupported large constant")); | |
10653 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10654 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10655 | break; |
10656 | ||
10657 | case M_SUBU_I_2: | |
10658 | if (imm_expr.X_op != O_constant) | |
10659 | as_bad (_("Unsupported large constant")); | |
10660 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10661 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10662 | break; |
10663 | ||
10664 | case M_DSUBU_I_2: | |
10665 | if (imm_expr.X_op != O_constant) | |
10666 | as_bad (_("Unsupported large constant")); | |
10667 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10668 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10669 | break; |
10670 | ||
10671 | case M_BEQ: | |
10672 | s = "cmp"; | |
10673 | s2 = "bteqz"; | |
10674 | goto do_branch; | |
10675 | case M_BNE: | |
10676 | s = "cmp"; | |
10677 | s2 = "btnez"; | |
10678 | goto do_branch; | |
10679 | case M_BLT: | |
10680 | s = "slt"; | |
10681 | s2 = "btnez"; | |
10682 | goto do_branch; | |
10683 | case M_BLTU: | |
10684 | s = "sltu"; | |
10685 | s2 = "btnez"; | |
10686 | goto do_branch; | |
10687 | case M_BLE: | |
10688 | s = "slt"; | |
10689 | s2 = "bteqz"; | |
10690 | goto do_reverse_branch; | |
10691 | case M_BLEU: | |
10692 | s = "sltu"; | |
10693 | s2 = "bteqz"; | |
10694 | goto do_reverse_branch; | |
10695 | case M_BGE: | |
10696 | s = "slt"; | |
10697 | s2 = "bteqz"; | |
10698 | goto do_branch; | |
10699 | case M_BGEU: | |
10700 | s = "sltu"; | |
10701 | s2 = "bteqz"; | |
10702 | goto do_branch; | |
10703 | case M_BGT: | |
10704 | s = "slt"; | |
10705 | s2 = "btnez"; | |
10706 | goto do_reverse_branch; | |
10707 | case M_BGTU: | |
10708 | s = "sltu"; | |
10709 | s2 = "btnez"; | |
10710 | ||
10711 | do_reverse_branch: | |
10712 | tmp = xreg; | |
10713 | xreg = yreg; | |
10714 | yreg = tmp; | |
10715 | ||
10716 | do_branch: | |
67c0d1eb RS |
10717 | macro_build (NULL, s, "x,y", xreg, yreg); |
10718 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10719 | break; |
10720 | ||
10721 | case M_BEQ_I: | |
10722 | s = "cmpi"; | |
10723 | s2 = "bteqz"; | |
10724 | s3 = "x,U"; | |
10725 | goto do_branch_i; | |
10726 | case M_BNE_I: | |
10727 | s = "cmpi"; | |
10728 | s2 = "btnez"; | |
10729 | s3 = "x,U"; | |
10730 | goto do_branch_i; | |
10731 | case M_BLT_I: | |
10732 | s = "slti"; | |
10733 | s2 = "btnez"; | |
10734 | s3 = "x,8"; | |
10735 | goto do_branch_i; | |
10736 | case M_BLTU_I: | |
10737 | s = "sltiu"; | |
10738 | s2 = "btnez"; | |
10739 | s3 = "x,8"; | |
10740 | goto do_branch_i; | |
10741 | case M_BLE_I: | |
10742 | s = "slti"; | |
10743 | s2 = "btnez"; | |
10744 | s3 = "x,8"; | |
10745 | goto do_addone_branch_i; | |
10746 | case M_BLEU_I: | |
10747 | s = "sltiu"; | |
10748 | s2 = "btnez"; | |
10749 | s3 = "x,8"; | |
10750 | goto do_addone_branch_i; | |
10751 | case M_BGE_I: | |
10752 | s = "slti"; | |
10753 | s2 = "bteqz"; | |
10754 | s3 = "x,8"; | |
10755 | goto do_branch_i; | |
10756 | case M_BGEU_I: | |
10757 | s = "sltiu"; | |
10758 | s2 = "bteqz"; | |
10759 | s3 = "x,8"; | |
10760 | goto do_branch_i; | |
10761 | case M_BGT_I: | |
10762 | s = "slti"; | |
10763 | s2 = "bteqz"; | |
10764 | s3 = "x,8"; | |
10765 | goto do_addone_branch_i; | |
10766 | case M_BGTU_I: | |
10767 | s = "sltiu"; | |
10768 | s2 = "bteqz"; | |
10769 | s3 = "x,8"; | |
10770 | ||
10771 | do_addone_branch_i: | |
10772 | if (imm_expr.X_op != O_constant) | |
10773 | as_bad (_("Unsupported large constant")); | |
10774 | ++imm_expr.X_add_number; | |
10775 | ||
10776 | do_branch_i: | |
67c0d1eb RS |
10777 | macro_build (&imm_expr, s, s3, xreg); |
10778 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10779 | break; |
10780 | ||
10781 | case M_ABS: | |
10782 | expr1.X_add_number = 0; | |
67c0d1eb | 10783 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10784 | if (xreg != yreg) |
67c0d1eb | 10785 | move_register (xreg, yreg); |
252b5132 | 10786 | expr1.X_add_number = 2; |
67c0d1eb RS |
10787 | macro_build (&expr1, "bteqz", "p"); |
10788 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10789 | } |
10790 | } | |
10791 | ||
10792 | /* For consistency checking, verify that all bits are specified either | |
10793 | by the match/mask part of the instruction definition, or by the | |
10794 | operand list. */ | |
10795 | static int | |
17a2f251 | 10796 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10797 | { |
10798 | const char *p = opc->args; | |
10799 | char c; | |
10800 | unsigned long used_bits = opc->mask; | |
10801 | ||
10802 | if ((used_bits & opc->match) != opc->match) | |
10803 | { | |
10804 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10805 | opc->name, opc->args); | |
10806 | return 0; | |
10807 | } | |
10808 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10809 | while (*p) | |
10810 | switch (c = *p++) | |
10811 | { | |
10812 | case ',': break; | |
10813 | case '(': break; | |
10814 | case ')': break; | |
af7ee8bf CD |
10815 | case '+': |
10816 | switch (c = *p++) | |
10817 | { | |
9bcd4f99 TS |
10818 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10819 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10820 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10821 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10822 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10823 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10824 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10825 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10826 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10827 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10828 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10829 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10830 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10831 | case 'I': break; | |
b015e599 | 10832 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10833 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10834 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10835 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10836 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10837 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10838 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10839 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10840 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10841 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10842 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10843 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10844 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10845 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10846 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10847 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
7f3c4072 | 10848 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10849 | |
af7ee8bf CD |
10850 | default: |
10851 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10852 | c, opc->name, opc->args); | |
10853 | return 0; | |
10854 | } | |
10855 | break; | |
252b5132 RH |
10856 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10857 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10858 | case 'A': break; | |
4372b673 | 10859 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10860 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10861 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10862 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10863 | case 'F': break; | |
10864 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10865 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10866 | case 'I': break; |
e972090a | 10867 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10868 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10869 | case 'L': break; |
10870 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10871 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10872 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10873 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10874 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10875 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10876 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10877 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10878 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10879 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10880 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10881 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10882 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10883 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10884 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10885 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10886 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10887 | case 'f': break; | |
10888 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10889 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10890 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10891 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10892 | case 'l': break; | |
10893 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10894 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10895 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10896 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10897 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10898 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10899 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10900 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10901 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10902 | case 'x': break; | |
10903 | case 'z': break; | |
10904 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10905 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10906 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10907 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10908 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10909 | case '[': break; | |
10910 | case ']': break; | |
620edafd | 10911 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10912 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10913 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10914 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10915 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10916 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10917 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10918 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10919 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10920 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10921 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10922 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10923 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10924 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10925 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10926 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10927 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10928 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10929 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10930 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10931 | default: |
10932 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10933 | c, opc->name, opc->args); | |
10934 | return 0; | |
10935 | } | |
10936 | #undef USE_BITS | |
10937 | if (used_bits != 0xffffffff) | |
10938 | { | |
10939 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10940 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10941 | return 0; | |
10942 | } | |
10943 | return 1; | |
10944 | } | |
10945 | ||
df58fc94 RS |
10946 | /* For consistency checking, verify that the length implied matches the |
10947 | major opcode and that all bits are specified either by the match/mask | |
10948 | part of the instruction definition, or by the operand list. */ | |
10949 | ||
10950 | static int | |
10951 | validate_micromips_insn (const struct mips_opcode *opc) | |
10952 | { | |
10953 | unsigned long match = opc->match; | |
10954 | unsigned long mask = opc->mask; | |
10955 | const char *p = opc->args; | |
10956 | unsigned long insn_bits; | |
10957 | unsigned long used_bits; | |
10958 | unsigned long major; | |
10959 | unsigned int length; | |
10960 | char e; | |
10961 | char c; | |
10962 | ||
10963 | if ((mask & match) != match) | |
10964 | { | |
10965 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10966 | opc->name, opc->args); | |
10967 | return 0; | |
10968 | } | |
10969 | length = micromips_insn_length (opc); | |
10970 | if (length != 2 && length != 4) | |
10971 | { | |
10972 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10973 | "%s %s"), length, opc->name, opc->args); | |
10974 | return 0; | |
10975 | } | |
10976 | major = match >> (10 + 8 * (length - 2)); | |
10977 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10978 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10979 | { | |
10980 | as_bad (_("Internal error: bad microMIPS opcode " | |
10981 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10982 | return 0; | |
10983 | } | |
10984 | ||
10985 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10986 | insn_bits = 1 << 4 * length; | |
10987 | insn_bits <<= 4 * length; | |
10988 | insn_bits -= 1; | |
10989 | used_bits = mask; | |
10990 | #define USE_BITS(field) \ | |
10991 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10992 | while (*p) | |
10993 | switch (c = *p++) | |
10994 | { | |
10995 | case ',': break; | |
10996 | case '(': break; | |
10997 | case ')': break; | |
10998 | case '+': | |
10999 | e = c; | |
11000 | switch (c = *p++) | |
11001 | { | |
11002 | case 'A': USE_BITS (EXTLSB); break; | |
11003 | case 'B': USE_BITS (INSMSB); break; | |
11004 | case 'C': USE_BITS (EXTMSBD); break; | |
11005 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
11006 | case 'E': USE_BITS (EXTLSB); break; | |
11007 | case 'F': USE_BITS (INSMSB); break; | |
11008 | case 'G': USE_BITS (EXTMSBD); break; | |
11009 | case 'H': USE_BITS (EXTMSBD); break; | |
7f3c4072 | 11010 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
11011 | default: |
11012 | as_bad (_("Internal error: bad mips opcode " | |
11013 | "(unknown extension operand type `%c%c'): %s %s"), | |
11014 | e, c, opc->name, opc->args); | |
11015 | return 0; | |
11016 | } | |
11017 | break; | |
11018 | case 'm': | |
11019 | e = c; | |
11020 | switch (c = *p++) | |
11021 | { | |
11022 | case 'A': USE_BITS (IMMA); break; | |
11023 | case 'B': USE_BITS (IMMB); break; | |
11024 | case 'C': USE_BITS (IMMC); break; | |
11025 | case 'D': USE_BITS (IMMD); break; | |
11026 | case 'E': USE_BITS (IMME); break; | |
11027 | case 'F': USE_BITS (IMMF); break; | |
11028 | case 'G': USE_BITS (IMMG); break; | |
11029 | case 'H': USE_BITS (IMMH); break; | |
11030 | case 'I': USE_BITS (IMMI); break; | |
11031 | case 'J': USE_BITS (IMMJ); break; | |
11032 | case 'L': USE_BITS (IMML); break; | |
11033 | case 'M': USE_BITS (IMMM); break; | |
11034 | case 'N': USE_BITS (IMMN); break; | |
11035 | case 'O': USE_BITS (IMMO); break; | |
11036 | case 'P': USE_BITS (IMMP); break; | |
11037 | case 'Q': USE_BITS (IMMQ); break; | |
11038 | case 'U': USE_BITS (IMMU); break; | |
11039 | case 'W': USE_BITS (IMMW); break; | |
11040 | case 'X': USE_BITS (IMMX); break; | |
11041 | case 'Y': USE_BITS (IMMY); break; | |
11042 | case 'Z': break; | |
11043 | case 'a': break; | |
11044 | case 'b': USE_BITS (MB); break; | |
11045 | case 'c': USE_BITS (MC); break; | |
11046 | case 'd': USE_BITS (MD); break; | |
11047 | case 'e': USE_BITS (ME); break; | |
11048 | case 'f': USE_BITS (MF); break; | |
11049 | case 'g': USE_BITS (MG); break; | |
11050 | case 'h': USE_BITS (MH); break; | |
11051 | case 'i': USE_BITS (MI); break; | |
11052 | case 'j': USE_BITS (MJ); break; | |
11053 | case 'l': USE_BITS (ML); break; | |
11054 | case 'm': USE_BITS (MM); break; | |
11055 | case 'n': USE_BITS (MN); break; | |
11056 | case 'p': USE_BITS (MP); break; | |
11057 | case 'q': USE_BITS (MQ); break; | |
11058 | case 'r': break; | |
11059 | case 's': break; | |
11060 | case 't': break; | |
11061 | case 'x': break; | |
11062 | case 'y': break; | |
11063 | case 'z': break; | |
11064 | default: | |
11065 | as_bad (_("Internal error: bad mips opcode " | |
11066 | "(unknown extension operand type `%c%c'): %s %s"), | |
11067 | e, c, opc->name, opc->args); | |
11068 | return 0; | |
11069 | } | |
11070 | break; | |
11071 | case '.': USE_BITS (OFFSET10); break; | |
11072 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
11073 | case '2': USE_BITS (BP); break; |
11074 | case '3': USE_BITS (SA3); break; | |
11075 | case '4': USE_BITS (SA4); break; | |
11076 | case '5': USE_BITS (IMM8); break; | |
11077 | case '6': USE_BITS (RS); break; | |
11078 | case '7': USE_BITS (DSPACC); break; | |
11079 | case '8': USE_BITS (WRDSP); break; | |
11080 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
11081 | case '<': USE_BITS (SHAMT); break; |
11082 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 11083 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
11084 | case 'B': USE_BITS (CODE10); break; |
11085 | case 'C': USE_BITS (COPZ); break; | |
11086 | case 'D': USE_BITS (FD); break; | |
11087 | case 'E': USE_BITS (RT); break; | |
11088 | case 'G': USE_BITS (RS); break; | |
444d75be | 11089 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
11090 | case 'K': USE_BITS (RS); break; |
11091 | case 'M': USE_BITS (CCC); break; | |
11092 | case 'N': USE_BITS (BCC); break; | |
11093 | case 'R': USE_BITS (FR); break; | |
11094 | case 'S': USE_BITS (FS); break; | |
11095 | case 'T': USE_BITS (FT); break; | |
11096 | case 'V': USE_BITS (FS); break; | |
dec0624d | 11097 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 11098 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
11099 | case 'a': USE_BITS (TARGET); break; |
11100 | case 'b': USE_BITS (RS); break; | |
11101 | case 'c': USE_BITS (CODE); break; | |
11102 | case 'd': USE_BITS (RD); break; | |
11103 | case 'h': USE_BITS (PREFX); break; | |
11104 | case 'i': USE_BITS (IMMEDIATE); break; | |
11105 | case 'j': USE_BITS (DELTA); break; | |
11106 | case 'k': USE_BITS (CACHE); break; | |
11107 | case 'n': USE_BITS (RT); break; | |
11108 | case 'o': USE_BITS (DELTA); break; | |
11109 | case 'p': USE_BITS (DELTA); break; | |
11110 | case 'q': USE_BITS (CODE2); break; | |
11111 | case 'r': USE_BITS (RS); break; | |
11112 | case 's': USE_BITS (RS); break; | |
11113 | case 't': USE_BITS (RT); break; | |
11114 | case 'u': USE_BITS (IMMEDIATE); break; | |
11115 | case 'v': USE_BITS (RS); break; | |
11116 | case 'w': USE_BITS (RT); break; | |
11117 | case 'y': USE_BITS (RS3); break; | |
11118 | case 'z': break; | |
11119 | case '|': USE_BITS (TRAP); break; | |
11120 | case '~': USE_BITS (OFFSET12); break; | |
11121 | default: | |
11122 | as_bad (_("Internal error: bad microMIPS opcode " | |
11123 | "(unknown operand type `%c'): %s %s"), | |
11124 | c, opc->name, opc->args); | |
11125 | return 0; | |
11126 | } | |
11127 | #undef USE_BITS | |
11128 | if (used_bits != insn_bits) | |
11129 | { | |
11130 | if (~used_bits & insn_bits) | |
11131 | as_bad (_("Internal error: bad microMIPS opcode " | |
11132 | "(bits 0x%lx undefined): %s %s"), | |
11133 | ~used_bits & insn_bits, opc->name, opc->args); | |
11134 | if (used_bits & ~insn_bits) | |
11135 | as_bad (_("Internal error: bad microMIPS opcode " | |
11136 | "(bits 0x%lx defined): %s %s"), | |
11137 | used_bits & ~insn_bits, opc->name, opc->args); | |
11138 | return 0; | |
11139 | } | |
11140 | return 1; | |
11141 | } | |
11142 | ||
9bcd4f99 TS |
11143 | /* UDI immediates. */ |
11144 | struct mips_immed { | |
11145 | char type; | |
11146 | unsigned int shift; | |
11147 | unsigned long mask; | |
11148 | const char * desc; | |
11149 | }; | |
11150 | ||
11151 | static const struct mips_immed mips_immed[] = { | |
11152 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
11153 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
11154 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
11155 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
11156 | { 0,0,0,0 } | |
11157 | }; | |
11158 | ||
7455baf8 TS |
11159 | /* Check whether an odd floating-point register is allowed. */ |
11160 | static int | |
11161 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
11162 | { | |
11163 | const char *s = insn->name; | |
11164 | ||
11165 | if (insn->pinfo == INSN_MACRO) | |
11166 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
11167 | return 1; | |
11168 | ||
e407c74b | 11169 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
11170 | { |
11171 | /* Allow odd registers for single-precision ops. */ | |
11172 | switch (insn->pinfo & (FP_S | FP_D)) | |
11173 | { | |
11174 | case FP_S: | |
11175 | case 0: | |
11176 | return 1; /* both single precision - ok */ | |
11177 | case FP_D: | |
11178 | return 0; /* both double precision - fail */ | |
11179 | default: | |
11180 | break; | |
11181 | } | |
11182 | ||
11183 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
11184 | s = strchr (insn->name, '.'); | |
11185 | if (argnum == 2) | |
11186 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
11187 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
11188 | } | |
11189 | ||
11190 | /* Single-precision coprocessor loads and moves are OK too. */ | |
11191 | if ((insn->pinfo & FP_S) | |
11192 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
11193 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
11194 | return 1; | |
11195 | ||
11196 | return 0; | |
11197 | } | |
11198 | ||
df58fc94 RS |
11199 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
11200 | taking bits from BIT up. */ | |
11201 | static int | |
11202 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
11203 | { | |
11204 | return (ep->X_op == O_constant | |
11205 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
11206 | && ep->X_add_number >= min << bit | |
11207 | && ep->X_add_number < max << bit); | |
11208 | } | |
11209 | ||
252b5132 RH |
11210 | /* This routine assembles an instruction into its binary format. As a |
11211 | side effect, it sets one of the global variables imm_reloc or | |
11212 | offset_reloc to the type of relocation to do if one of the operands | |
11213 | is an address expression. */ | |
11214 | ||
11215 | static void | |
17a2f251 | 11216 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 11217 | { |
df58fc94 RS |
11218 | bfd_boolean wrong_delay_slot_insns = FALSE; |
11219 | bfd_boolean need_delay_slot_ok = TRUE; | |
11220 | struct mips_opcode *firstinsn = NULL; | |
11221 | const struct mips_opcode *past; | |
11222 | struct hash_control *hash; | |
252b5132 RH |
11223 | char *s; |
11224 | const char *args; | |
43841e91 | 11225 | char c = 0; |
252b5132 RH |
11226 | struct mips_opcode *insn; |
11227 | char *argsStart; | |
11228 | unsigned int regno; | |
34224acf | 11229 | unsigned int lastregno; |
df58fc94 | 11230 | unsigned int destregno = 0; |
af7ee8bf | 11231 | unsigned int lastpos = 0; |
071742cf | 11232 | unsigned int limlo, limhi; |
f02d8318 | 11233 | int sizelo; |
252b5132 | 11234 | char *s_reset; |
74cd071d | 11235 | offsetT min_range, max_range; |
df58fc94 | 11236 | long opend; |
a40bc9dd | 11237 | char *name; |
707bfff6 TS |
11238 | int argnum; |
11239 | unsigned int rtype; | |
df58fc94 | 11240 | char *dot; |
a40bc9dd | 11241 | long end; |
252b5132 RH |
11242 | |
11243 | insn_error = NULL; | |
11244 | ||
df58fc94 RS |
11245 | if (mips_opts.micromips) |
11246 | { | |
11247 | hash = micromips_op_hash; | |
11248 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11249 | } | |
11250 | else | |
11251 | { | |
11252 | hash = op_hash; | |
11253 | past = &mips_opcodes[NUMOPCODES]; | |
11254 | } | |
11255 | forced_insn_length = 0; | |
252b5132 | 11256 | insn = NULL; |
252b5132 | 11257 | |
df58fc94 | 11258 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11259 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11260 | continue; | |
bdaaa2e1 | 11261 | |
a40bc9dd RS |
11262 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11263 | name = alloca (end + 1); | |
11264 | memcpy (name, str, end); | |
11265 | name[end] = '\0'; | |
252b5132 | 11266 | |
df58fc94 RS |
11267 | for (;;) |
11268 | { | |
11269 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11270 | ||
11271 | if (insn != NULL || !mips_opts.micromips) | |
11272 | break; | |
11273 | if (forced_insn_length) | |
11274 | break; | |
11275 | ||
11276 | /* See if there's an instruction size override suffix, | |
11277 | either `16' or `32', at the end of the mnemonic proper, | |
11278 | that defines the operation, i.e. before the first `.' | |
11279 | character if any. Strip it and retry. */ | |
11280 | dot = strchr (name, '.'); | |
11281 | opend = dot != NULL ? dot - name : end; | |
11282 | if (opend < 3) | |
11283 | break; | |
11284 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11285 | forced_insn_length = 2; | |
11286 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11287 | forced_insn_length = 4; | |
11288 | else | |
11289 | break; | |
11290 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11291 | } | |
252b5132 RH |
11292 | if (insn == NULL) |
11293 | { | |
a40bc9dd RS |
11294 | insn_error = _("Unrecognized opcode"); |
11295 | return; | |
252b5132 RH |
11296 | } |
11297 | ||
df58fc94 RS |
11298 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11299 | we make up to two passes over the relevant fragment of the opcode | |
11300 | table. First we try instructions that meet the delay slot's length | |
11301 | requirement. If none matched, then we retry with the remaining ones | |
11302 | and if one matches, then we use it and then issue an appropriate | |
11303 | warning later on. */ | |
a40bc9dd | 11304 | argsStart = s = str + end; |
252b5132 RH |
11305 | for (;;) |
11306 | { | |
df58fc94 RS |
11307 | bfd_boolean delay_slot_ok; |
11308 | bfd_boolean size_ok; | |
b34976b6 | 11309 | bfd_boolean ok; |
252b5132 | 11310 | |
a40bc9dd | 11311 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11312 | |
f79e2745 | 11313 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11314 | size_ok = is_size_valid (insn); |
11315 | delay_slot_ok = is_delay_slot_valid (insn); | |
11316 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11317 | { |
df58fc94 RS |
11318 | firstinsn = insn; |
11319 | wrong_delay_slot_insns = TRUE; | |
11320 | } | |
11321 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11322 | { | |
11323 | static char buf[256]; | |
11324 | ||
11325 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11326 | { |
11327 | ++insn; | |
11328 | continue; | |
11329 | } | |
df58fc94 | 11330 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11331 | { |
df58fc94 RS |
11332 | gas_assert (firstinsn); |
11333 | need_delay_slot_ok = FALSE; | |
11334 | past = insn + 1; | |
11335 | insn = firstinsn; | |
11336 | continue; | |
252b5132 | 11337 | } |
df58fc94 RS |
11338 | |
11339 | if (insn_error) | |
11340 | return; | |
11341 | ||
11342 | if (!ok) | |
7bd942df | 11343 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11344 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11345 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11346 | else | |
11347 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11348 | 8 * forced_insn_length); | |
11349 | insn_error = buf; | |
11350 | ||
11351 | return; | |
252b5132 RH |
11352 | } |
11353 | ||
1e915849 | 11354 | create_insn (ip, insn); |
268f6bed | 11355 | insn_error = NULL; |
707bfff6 | 11356 | argnum = 1; |
24864476 | 11357 | lastregno = 0xffffffff; |
252b5132 RH |
11358 | for (args = insn->args;; ++args) |
11359 | { | |
deec1734 CD |
11360 | int is_mdmx; |
11361 | ||
ad8d3bb3 | 11362 | s += strspn (s, " \t"); |
deec1734 | 11363 | is_mdmx = 0; |
252b5132 RH |
11364 | switch (*args) |
11365 | { | |
11366 | case '\0': /* end of args */ | |
11367 | if (*s == '\0') | |
11368 | return; | |
11369 | break; | |
11370 | ||
03f66e8a MR |
11371 | case '2': |
11372 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11373 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11374 | my_getExpression (&imm_expr, s); |
11375 | check_absolute_expr (ip, &imm_expr); | |
11376 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11377 | && (unsigned long) imm_expr.X_add_number != 3) | |
11378 | { | |
11379 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11380 | (unsigned long) imm_expr.X_add_number); | |
11381 | } | |
03f66e8a MR |
11382 | INSERT_OPERAND (mips_opts.micromips, |
11383 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11384 | imm_expr.X_op = O_absent; |
11385 | s = expr_end; | |
11386 | continue; | |
11387 | ||
03f66e8a MR |
11388 | case '3': |
11389 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11390 | code) or 21 (for microMIPS code). */ | |
11391 | { | |
11392 | unsigned long mask = (mips_opts.micromips | |
11393 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11394 | ||
11395 | my_getExpression (&imm_expr, s); | |
11396 | check_absolute_expr (ip, &imm_expr); | |
11397 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11398 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11399 | mask, (unsigned long) imm_expr.X_add_number); | |
11400 | INSERT_OPERAND (mips_opts.micromips, | |
11401 | SA3, *ip, imm_expr.X_add_number); | |
11402 | imm_expr.X_op = O_absent; | |
11403 | s = expr_end; | |
11404 | } | |
74cd071d CF |
11405 | continue; |
11406 | ||
03f66e8a MR |
11407 | case '4': |
11408 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11409 | code) or 21 (for microMIPS code). */ | |
11410 | { | |
11411 | unsigned long mask = (mips_opts.micromips | |
11412 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11413 | ||
11414 | my_getExpression (&imm_expr, s); | |
11415 | check_absolute_expr (ip, &imm_expr); | |
11416 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11417 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11418 | mask, (unsigned long) imm_expr.X_add_number); | |
11419 | INSERT_OPERAND (mips_opts.micromips, | |
11420 | SA4, *ip, imm_expr.X_add_number); | |
11421 | imm_expr.X_op = O_absent; | |
11422 | s = expr_end; | |
11423 | } | |
74cd071d CF |
11424 | continue; |
11425 | ||
03f66e8a MR |
11426 | case '5': |
11427 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11428 | code) or 16 (for microMIPS code). */ | |
11429 | { | |
11430 | unsigned long mask = (mips_opts.micromips | |
11431 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11432 | ||
11433 | my_getExpression (&imm_expr, s); | |
11434 | check_absolute_expr (ip, &imm_expr); | |
11435 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11436 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11437 | mask, (unsigned long) imm_expr.X_add_number); | |
11438 | INSERT_OPERAND (mips_opts.micromips, | |
11439 | IMM8, *ip, imm_expr.X_add_number); | |
11440 | imm_expr.X_op = O_absent; | |
11441 | s = expr_end; | |
11442 | } | |
74cd071d CF |
11443 | continue; |
11444 | ||
03f66e8a MR |
11445 | case '6': |
11446 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11447 | code) or 21 (for microMIPS code). */ | |
11448 | { | |
11449 | unsigned long mask = (mips_opts.micromips | |
11450 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11451 | ||
11452 | my_getExpression (&imm_expr, s); | |
11453 | check_absolute_expr (ip, &imm_expr); | |
11454 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11455 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11456 | mask, (unsigned long) imm_expr.X_add_number); | |
11457 | INSERT_OPERAND (mips_opts.micromips, | |
11458 | RS, *ip, imm_expr.X_add_number); | |
11459 | imm_expr.X_op = O_absent; | |
11460 | s = expr_end; | |
11461 | } | |
74cd071d CF |
11462 | continue; |
11463 | ||
90ecf173 | 11464 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11465 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11466 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11467 | { |
11468 | regno = s[3] - '0'; | |
11469 | s += 4; | |
03f66e8a | 11470 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11471 | continue; |
11472 | } | |
11473 | else | |
11474 | as_bad (_("Invalid dsp acc register")); | |
11475 | break; | |
11476 | ||
03f66e8a MR |
11477 | case '8': |
11478 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11479 | code) or 14 (for microMIPS code). */ | |
11480 | { | |
11481 | unsigned long mask = (mips_opts.micromips | |
11482 | ? MICROMIPSOP_MASK_WRDSP | |
11483 | : OP_MASK_WRDSP); | |
11484 | ||
11485 | my_getExpression (&imm_expr, s); | |
11486 | check_absolute_expr (ip, &imm_expr); | |
11487 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11488 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11489 | mask, (unsigned long) imm_expr.X_add_number); | |
11490 | INSERT_OPERAND (mips_opts.micromips, | |
11491 | WRDSP, *ip, imm_expr.X_add_number); | |
11492 | imm_expr.X_op = O_absent; | |
11493 | s = expr_end; | |
11494 | } | |
74cd071d CF |
11495 | continue; |
11496 | ||
90ecf173 | 11497 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11498 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11499 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11500 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11501 | { |
11502 | regno = s[3] - '0'; | |
11503 | s += 4; | |
df58fc94 | 11504 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11505 | continue; |
11506 | } | |
11507 | else | |
11508 | as_bad (_("Invalid dsp acc register")); | |
11509 | break; | |
11510 | ||
03f66e8a MR |
11511 | case '0': |
11512 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11513 | code) or 20 (for microMIPS code). */ | |
11514 | { | |
11515 | long mask = (mips_opts.micromips | |
11516 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11517 | ||
11518 | my_getExpression (&imm_expr, s); | |
11519 | check_absolute_expr (ip, &imm_expr); | |
11520 | min_range = -((mask + 1) >> 1); | |
11521 | max_range = ((mask + 1) >> 1) - 1; | |
11522 | if (imm_expr.X_add_number < min_range | |
11523 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11524 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11525 | (long) min_range, (long) max_range, | |
11526 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11527 | INSERT_OPERAND (mips_opts.micromips, |
11528 | DSPSFT, *ip, imm_expr.X_add_number); | |
11529 | imm_expr.X_op = O_absent; | |
11530 | s = expr_end; | |
11531 | } | |
74cd071d CF |
11532 | continue; |
11533 | ||
90ecf173 | 11534 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11535 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11536 | my_getExpression (&imm_expr, s); |
11537 | check_absolute_expr (ip, &imm_expr); | |
11538 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11539 | { | |
a9e24354 TS |
11540 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11541 | OP_MASK_RDDSP, | |
11542 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11543 | } |
df58fc94 | 11544 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11545 | imm_expr.X_op = O_absent; |
11546 | s = expr_end; | |
11547 | continue; | |
11548 | ||
90ecf173 | 11549 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11550 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11551 | my_getExpression (&imm_expr, s); |
11552 | check_absolute_expr (ip, &imm_expr); | |
11553 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11554 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11555 | if (imm_expr.X_add_number < min_range || | |
11556 | imm_expr.X_add_number > max_range) | |
11557 | { | |
a9e24354 TS |
11558 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11559 | (long) min_range, (long) max_range, | |
11560 | (long) imm_expr.X_add_number); | |
74cd071d | 11561 | } |
df58fc94 | 11562 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11563 | imm_expr.X_op = O_absent; |
11564 | s = expr_end; | |
11565 | continue; | |
11566 | ||
90ecf173 | 11567 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11568 | { |
11569 | long mask = (mips_opts.micromips | |
11570 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11571 | ||
11572 | my_getExpression (&imm_expr, s); | |
11573 | check_absolute_expr (ip, &imm_expr); | |
11574 | min_range = -((mask + 1) >> 1); | |
11575 | max_range = ((mask + 1) >> 1) - 1; | |
11576 | if (imm_expr.X_add_number < min_range | |
11577 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11578 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11579 | (long) min_range, (long) max_range, | |
11580 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11581 | INSERT_OPERAND (mips_opts.micromips, |
11582 | IMM10, *ip, imm_expr.X_add_number); | |
11583 | imm_expr.X_op = O_absent; | |
11584 | s = expr_end; | |
11585 | } | |
11586 | continue; | |
11587 | ||
11588 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11589 | gas_assert (mips_opts.micromips); | |
11590 | my_getExpression (&imm_expr, s); | |
11591 | check_absolute_expr (ip, &imm_expr); | |
11592 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11593 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11594 | MICROMIPSOP_MASK_RD, | |
11595 | (unsigned long) imm_expr.X_add_number); | |
11596 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11597 | imm_expr.X_op = O_absent; |
11598 | s = expr_end; | |
11599 | continue; | |
11600 | ||
a9e24354 | 11601 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11602 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11603 | my_getExpression (&imm_expr, s); |
11604 | check_absolute_expr (ip, &imm_expr); | |
11605 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11606 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11607 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11608 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11609 | imm_expr.X_op = O_absent; |
11610 | s = expr_end; | |
11611 | continue; | |
11612 | ||
a9e24354 | 11613 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11614 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11615 | my_getExpression (&imm_expr, s); |
11616 | check_absolute_expr (ip, &imm_expr); | |
11617 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11618 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11619 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11620 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11621 | imm_expr.X_op = O_absent; |
11622 | s = expr_end; | |
11623 | continue; | |
11624 | ||
90ecf173 | 11625 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11626 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11627 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11628 | s[3] >= '0' && s[3] <= '3') | |
11629 | { | |
11630 | regno = s[3] - '0'; | |
11631 | s += 4; | |
df58fc94 | 11632 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11633 | continue; |
11634 | } | |
11635 | else | |
11636 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11637 | break; | |
11638 | ||
90ecf173 | 11639 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11640 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11641 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11642 | s[3] >= '0' && s[3] <= '3') | |
11643 | { | |
11644 | regno = s[3] - '0'; | |
11645 | s += 4; | |
df58fc94 | 11646 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11647 | continue; |
11648 | } | |
11649 | else | |
11650 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11651 | break; | |
11652 | ||
dec0624d MR |
11653 | case '\\': /* 3-bit bit position. */ |
11654 | { | |
2906b037 MR |
11655 | unsigned long mask = (mips_opts.micromips |
11656 | ? MICROMIPSOP_MASK_3BITPOS | |
11657 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11658 | |
11659 | my_getExpression (&imm_expr, s); | |
11660 | check_absolute_expr (ip, &imm_expr); | |
11661 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11662 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11663 | ip->insn_mo->name, | |
11664 | mask, (unsigned long) imm_expr.X_add_number); | |
11665 | INSERT_OPERAND (mips_opts.micromips, | |
11666 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11667 | imm_expr.X_op = O_absent; | |
11668 | s = expr_end; | |
11669 | } | |
11670 | continue; | |
11671 | ||
252b5132 | 11672 | case ',': |
a339155f | 11673 | ++argnum; |
252b5132 RH |
11674 | if (*s++ == *args) |
11675 | continue; | |
11676 | s--; | |
11677 | switch (*++args) | |
11678 | { | |
11679 | case 'r': | |
11680 | case 'v': | |
df58fc94 | 11681 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11682 | continue; |
11683 | ||
11684 | case 'w': | |
df58fc94 | 11685 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11686 | continue; |
11687 | ||
252b5132 | 11688 | case 'W': |
df58fc94 RS |
11689 | gas_assert (!mips_opts.micromips); |
11690 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11691 | continue; |
11692 | ||
11693 | case 'V': | |
df58fc94 | 11694 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11695 | continue; |
11696 | } | |
11697 | break; | |
11698 | ||
11699 | case '(': | |
11700 | /* Handle optional base register. | |
11701 | Either the base register is omitted or | |
bdaaa2e1 | 11702 | we must have a left paren. */ |
252b5132 RH |
11703 | /* This is dependent on the next operand specifier |
11704 | is a base register specification. */ | |
df58fc94 RS |
11705 | gas_assert (args[1] == 'b' |
11706 | || (mips_opts.micromips | |
11707 | && args[1] == 'm' | |
11708 | && (args[2] == 'l' || args[2] == 'n' | |
11709 | || args[2] == 's' || args[2] == 'a'))); | |
11710 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11711 | return; |
df58fc94 | 11712 | /* Fall through. */ |
252b5132 | 11713 | |
90ecf173 | 11714 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11715 | if (*s++ == *args) |
11716 | continue; | |
11717 | break; | |
11718 | ||
11719 | case '[': /* These must match exactly. */ | |
60b63b72 | 11720 | case ']': |
df58fc94 | 11721 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11722 | if (*s++ == *args) |
11723 | continue; | |
11724 | break; | |
11725 | ||
af7ee8bf CD |
11726 | case '+': /* Opcode extension character. */ |
11727 | switch (*++args) | |
11728 | { | |
9bcd4f99 TS |
11729 | case '1': /* UDI immediates. */ |
11730 | case '2': | |
11731 | case '3': | |
11732 | case '4': | |
df58fc94 | 11733 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11734 | { |
11735 | const struct mips_immed *imm = mips_immed; | |
11736 | ||
11737 | while (imm->type && imm->type != *args) | |
11738 | ++imm; | |
11739 | if (! imm->type) | |
b37df7c4 | 11740 | abort (); |
9bcd4f99 TS |
11741 | my_getExpression (&imm_expr, s); |
11742 | check_absolute_expr (ip, &imm_expr); | |
11743 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11744 | { | |
11745 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11746 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11747 | (unsigned long) imm_expr.X_add_number, | |
11748 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11749 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11750 | } |
11751 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11752 | << imm->shift); | |
11753 | imm_expr.X_op = O_absent; | |
11754 | s = expr_end; | |
11755 | } | |
11756 | continue; | |
90ecf173 | 11757 | |
b015e599 AP |
11758 | case 'J': /* 10-bit hypcall code. */ |
11759 | gas_assert (!mips_opts.micromips); | |
11760 | { | |
11761 | unsigned long mask = OP_MASK_CODE10; | |
11762 | ||
11763 | my_getExpression (&imm_expr, s); | |
11764 | check_absolute_expr (ip, &imm_expr); | |
11765 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11766 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11767 | ip->insn_mo->name, | |
11768 | mask, (unsigned long) imm_expr.X_add_number); | |
11769 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11770 | imm_expr.X_op = O_absent; | |
11771 | s = expr_end; | |
11772 | } | |
11773 | continue; | |
11774 | ||
071742cf CD |
11775 | case 'A': /* ins/ext position, becomes LSB. */ |
11776 | limlo = 0; | |
11777 | limhi = 31; | |
5f74bc13 CD |
11778 | goto do_lsb; |
11779 | case 'E': | |
11780 | limlo = 32; | |
11781 | limhi = 63; | |
11782 | goto do_lsb; | |
90ecf173 | 11783 | do_lsb: |
071742cf CD |
11784 | my_getExpression (&imm_expr, s); |
11785 | check_absolute_expr (ip, &imm_expr); | |
11786 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11787 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11788 | { | |
11789 | as_bad (_("Improper position (%lu)"), | |
11790 | (unsigned long) imm_expr.X_add_number); | |
11791 | imm_expr.X_add_number = limlo; | |
11792 | } | |
11793 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11794 | INSERT_OPERAND (mips_opts.micromips, |
11795 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11796 | imm_expr.X_op = O_absent; |
11797 | s = expr_end; | |
11798 | continue; | |
11799 | ||
11800 | case 'B': /* ins size, becomes MSB. */ | |
11801 | limlo = 1; | |
11802 | limhi = 32; | |
5f74bc13 CD |
11803 | goto do_msb; |
11804 | case 'F': | |
11805 | limlo = 33; | |
11806 | limhi = 64; | |
11807 | goto do_msb; | |
90ecf173 | 11808 | do_msb: |
071742cf CD |
11809 | my_getExpression (&imm_expr, s); |
11810 | check_absolute_expr (ip, &imm_expr); | |
11811 | /* Check for negative input so that small negative numbers | |
11812 | will not succeed incorrectly. The checks against | |
11813 | (pos+size) transitively check "size" itself, | |
11814 | assuming that "pos" is reasonable. */ | |
11815 | if ((long) imm_expr.X_add_number < 0 | |
11816 | || ((unsigned long) imm_expr.X_add_number | |
11817 | + lastpos) < limlo | |
11818 | || ((unsigned long) imm_expr.X_add_number | |
11819 | + lastpos) > limhi) | |
11820 | { | |
11821 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11822 | (unsigned long) imm_expr.X_add_number, | |
11823 | (unsigned long) lastpos); | |
11824 | imm_expr.X_add_number = limlo - lastpos; | |
11825 | } | |
df58fc94 RS |
11826 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11827 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11828 | imm_expr.X_op = O_absent; |
11829 | s = expr_end; | |
11830 | continue; | |
11831 | ||
11832 | case 'C': /* ext size, becomes MSBD. */ | |
11833 | limlo = 1; | |
11834 | limhi = 32; | |
f02d8318 | 11835 | sizelo = 1; |
5f74bc13 CD |
11836 | goto do_msbd; |
11837 | case 'G': | |
11838 | limlo = 33; | |
11839 | limhi = 64; | |
f02d8318 | 11840 | sizelo = 33; |
5f74bc13 CD |
11841 | goto do_msbd; |
11842 | case 'H': | |
11843 | limlo = 33; | |
11844 | limhi = 64; | |
f02d8318 | 11845 | sizelo = 1; |
5f74bc13 | 11846 | goto do_msbd; |
90ecf173 | 11847 | do_msbd: |
071742cf CD |
11848 | my_getExpression (&imm_expr, s); |
11849 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11850 | /* The checks against (pos+size) don't transitively check |
11851 | "size" itself, assuming that "pos" is reasonable. | |
11852 | We also need to check the lower bound of "size". */ | |
11853 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11854 | || ((unsigned long) imm_expr.X_add_number |
11855 | + lastpos) < limlo | |
11856 | || ((unsigned long) imm_expr.X_add_number | |
11857 | + lastpos) > limhi) | |
11858 | { | |
11859 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11860 | (unsigned long) imm_expr.X_add_number, | |
11861 | (unsigned long) lastpos); | |
11862 | imm_expr.X_add_number = limlo - lastpos; | |
11863 | } | |
df58fc94 RS |
11864 | INSERT_OPERAND (mips_opts.micromips, |
11865 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11866 | imm_expr.X_op = O_absent; |
11867 | s = expr_end; | |
11868 | continue; | |
af7ee8bf | 11869 | |
bbcc0807 CD |
11870 | case 'D': |
11871 | /* +D is for disassembly only; never match. */ | |
11872 | break; | |
11873 | ||
5f74bc13 CD |
11874 | case 'I': |
11875 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11876 | my_getExpression (&imm2_expr, s); | |
11877 | if (imm2_expr.X_op != O_big | |
11878 | && imm2_expr.X_op != O_constant) | |
11879 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11880 | if (HAVE_32BIT_GPRS) |
11881 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11882 | s = expr_end; |
11883 | continue; | |
11884 | ||
707bfff6 | 11885 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11886 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11887 | /* +T is for disassembly only; never match. */ |
11888 | break; | |
11889 | ||
707bfff6 | 11890 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11891 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11892 | if (s[0] == '$' && ISDIGIT (s[1])) |
11893 | { | |
11894 | ++s; | |
11895 | regno = 0; | |
11896 | do | |
11897 | { | |
11898 | regno *= 10; | |
11899 | regno += *s - '0'; | |
11900 | ++s; | |
11901 | } | |
11902 | while (ISDIGIT (*s)); | |
11903 | if (regno > 31) | |
11904 | as_bad (_("Invalid register number (%d)"), regno); | |
11905 | else | |
11906 | { | |
df58fc94 | 11907 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11908 | continue; |
11909 | } | |
11910 | } | |
11911 | else | |
11912 | as_bad (_("Invalid coprocessor 0 register number")); | |
11913 | break; | |
11914 | ||
bb35fb24 NC |
11915 | case 'x': |
11916 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11917 | is not in the valid range. */ | |
df58fc94 | 11918 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11919 | my_getExpression (&imm_expr, s); |
11920 | check_absolute_expr (ip, &imm_expr); | |
11921 | if ((unsigned) imm_expr.X_add_number > 31) | |
11922 | { | |
11923 | as_bad (_("Improper bit index (%lu)"), | |
11924 | (unsigned long) imm_expr.X_add_number); | |
11925 | imm_expr.X_add_number = 0; | |
11926 | } | |
df58fc94 | 11927 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11928 | imm_expr.X_op = O_absent; |
11929 | s = expr_end; | |
11930 | continue; | |
11931 | ||
11932 | case 'X': | |
11933 | /* bbit[01] bit index when bbit is used but we generate | |
11934 | bbit[01]32 because the index is over 32. Move to the | |
11935 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11936 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11937 | my_getExpression (&imm_expr, s); |
11938 | check_absolute_expr (ip, &imm_expr); | |
11939 | if ((unsigned) imm_expr.X_add_number < 32 | |
11940 | || (unsigned) imm_expr.X_add_number > 63) | |
11941 | break; | |
df58fc94 | 11942 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11943 | imm_expr.X_op = O_absent; |
11944 | s = expr_end; | |
11945 | continue; | |
11946 | ||
11947 | case 'p': | |
11948 | /* cins, cins32, exts and exts32 position field. Give error | |
11949 | if it's not in the valid range. */ | |
df58fc94 | 11950 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11951 | my_getExpression (&imm_expr, s); |
11952 | check_absolute_expr (ip, &imm_expr); | |
11953 | if ((unsigned) imm_expr.X_add_number > 31) | |
11954 | { | |
11955 | as_bad (_("Improper position (%lu)"), | |
11956 | (unsigned long) imm_expr.X_add_number); | |
11957 | imm_expr.X_add_number = 0; | |
11958 | } | |
11959 | /* Make the pos explicit to simplify +S. */ | |
11960 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11961 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11962 | imm_expr.X_op = O_absent; |
11963 | s = expr_end; | |
11964 | continue; | |
11965 | ||
11966 | case 'P': | |
11967 | /* cins, cins32, exts and exts32 position field. Move to | |
11968 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11969 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11970 | my_getExpression (&imm_expr, s); |
11971 | check_absolute_expr (ip, &imm_expr); | |
11972 | if ((unsigned) imm_expr.X_add_number < 32 | |
11973 | || (unsigned) imm_expr.X_add_number > 63) | |
11974 | break; | |
11975 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11976 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11977 | imm_expr.X_op = O_absent; |
11978 | s = expr_end; | |
11979 | continue; | |
11980 | ||
11981 | case 's': | |
11982 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11983 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11984 | my_getExpression (&imm_expr, s); |
11985 | check_absolute_expr (ip, &imm_expr); | |
11986 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11987 | { | |
11988 | as_bad (_("Improper size (%lu)"), | |
11989 | (unsigned long) imm_expr.X_add_number); | |
11990 | imm_expr.X_add_number = 0; | |
11991 | } | |
df58fc94 | 11992 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11993 | imm_expr.X_op = O_absent; |
11994 | s = expr_end; | |
11995 | continue; | |
11996 | ||
11997 | case 'S': | |
11998 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11999 | length-minus-one field. */ | |
df58fc94 | 12000 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
12001 | my_getExpression (&imm_expr, s); |
12002 | check_absolute_expr (ip, &imm_expr); | |
12003 | if ((long) imm_expr.X_add_number < 0 | |
12004 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
12005 | { | |
12006 | as_bad (_("Improper size (%lu)"), | |
12007 | (unsigned long) imm_expr.X_add_number); | |
12008 | imm_expr.X_add_number = 0; | |
12009 | } | |
df58fc94 | 12010 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
12011 | imm_expr.X_op = O_absent; |
12012 | s = expr_end; | |
12013 | continue; | |
12014 | ||
dd3cbb7e NC |
12015 | case 'Q': |
12016 | /* seqi/snei immediate field. */ | |
df58fc94 | 12017 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
12018 | my_getExpression (&imm_expr, s); |
12019 | check_absolute_expr (ip, &imm_expr); | |
12020 | if ((long) imm_expr.X_add_number < -512 | |
12021 | || (long) imm_expr.X_add_number >= 512) | |
12022 | { | |
12023 | as_bad (_("Improper immediate (%ld)"), | |
12024 | (long) imm_expr.X_add_number); | |
12025 | imm_expr.X_add_number = 0; | |
12026 | } | |
df58fc94 | 12027 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
12028 | imm_expr.X_op = O_absent; |
12029 | s = expr_end; | |
12030 | continue; | |
12031 | ||
98675402 | 12032 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 12033 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12034 | my_getExpression (&imm_expr, s); |
12035 | check_absolute_expr (ip, &imm_expr); | |
12036 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
12037 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
12038 | if (imm_expr.X_add_number < min_range | |
12039 | || imm_expr.X_add_number > max_range) | |
12040 | { | |
c95354ed | 12041 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12042 | (long) min_range, (long) max_range, |
12043 | (long) imm_expr.X_add_number); | |
12044 | } | |
df58fc94 | 12045 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
12046 | imm_expr.X_op = O_absent; |
12047 | s = expr_end; | |
12048 | continue; | |
12049 | ||
12050 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 12051 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12052 | my_getExpression (&imm_expr, s); |
12053 | check_absolute_expr (ip, &imm_expr); | |
12054 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
12055 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
12056 | if (imm_expr.X_add_number < min_range | |
12057 | || imm_expr.X_add_number > max_range) | |
12058 | { | |
c95354ed | 12059 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12060 | (long) min_range, (long) max_range, |
12061 | (long) imm_expr.X_add_number); | |
12062 | } | |
df58fc94 | 12063 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
12064 | imm_expr.X_op = O_absent; |
12065 | s = expr_end; | |
12066 | continue; | |
12067 | ||
12068 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 12069 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12070 | my_getExpression (&imm_expr, s); |
12071 | check_absolute_expr (ip, &imm_expr); | |
12072 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
12073 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
12074 | /* We check the offset range before adjusted. */ |
12075 | min_range <<= 4; | |
12076 | max_range <<= 4; | |
98675402 RS |
12077 | if (imm_expr.X_add_number < min_range |
12078 | || imm_expr.X_add_number > max_range) | |
12079 | { | |
c95354ed | 12080 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12081 | (long) min_range, (long) max_range, |
12082 | (long) imm_expr.X_add_number); | |
12083 | } | |
c95354ed MX |
12084 | if (imm_expr.X_add_number & 0xf) |
12085 | { | |
12086 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
12087 | (long) imm_expr.X_add_number); | |
12088 | } | |
12089 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
12090 | INSERT_OPERAND (0, OFFSET_C, *ip, |
12091 | imm_expr.X_add_number >> 4); | |
98675402 RS |
12092 | imm_expr.X_op = O_absent; |
12093 | s = expr_end; | |
12094 | continue; | |
12095 | ||
12096 | case 'z': | |
df58fc94 | 12097 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12098 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
12099 | break; | |
12100 | if (regno == AT && mips_opts.at) | |
12101 | { | |
12102 | if (mips_opts.at == ATREG) | |
12103 | as_warn (_("used $at without \".set noat\"")); | |
12104 | else | |
12105 | as_warn (_("used $%u with \".set at=$%u\""), | |
12106 | regno, mips_opts.at); | |
12107 | } | |
df58fc94 | 12108 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
12109 | continue; |
12110 | ||
12111 | case 'Z': | |
df58fc94 | 12112 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12113 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
12114 | break; | |
df58fc94 | 12115 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
12116 | continue; |
12117 | ||
7f3c4072 CM |
12118 | case 'j': |
12119 | { | |
12120 | int shift = 8; | |
12121 | size_t i; | |
12122 | /* Check whether there is only a single bracketed expression | |
12123 | left. If so, it must be the base register and the | |
12124 | constant must be zero. */ | |
12125 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12126 | continue; | |
12127 | ||
12128 | /* If this value won't fit into the offset, then go find | |
12129 | a macro that will generate a 16- or 32-bit offset code | |
12130 | pattern. */ | |
12131 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12132 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12133 | || imm_expr.X_add_number >= 1 << shift | |
12134 | || imm_expr.X_add_number < -1 << shift)) | |
12135 | || i > 0) | |
12136 | { | |
12137 | imm_expr.X_op = O_absent; | |
12138 | break; | |
12139 | } | |
12140 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
12141 | imm_expr.X_add_number); | |
12142 | imm_expr.X_op = O_absent; | |
12143 | s = expr_end; | |
12144 | } | |
12145 | continue; | |
12146 | ||
af7ee8bf | 12147 | default: |
df58fc94 | 12148 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 12149 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 12150 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 12151 | *args, insn->name, insn->args); |
af7ee8bf CD |
12152 | /* Further processing is fruitless. */ |
12153 | return; | |
12154 | } | |
12155 | break; | |
12156 | ||
df58fc94 | 12157 | case '.': /* 10-bit offset. */ |
df58fc94 | 12158 | gas_assert (mips_opts.micromips); |
dec0624d | 12159 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
12160 | { |
12161 | int shift = *args == '.' ? 9 : 11; | |
12162 | size_t i; | |
12163 | ||
12164 | /* Check whether there is only a single bracketed expression | |
12165 | left. If so, it must be the base register and the | |
12166 | constant must be zero. */ | |
12167 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12168 | continue; | |
12169 | ||
12170 | /* If this value won't fit into the offset, then go find | |
12171 | a macro that will generate a 16- or 32-bit offset code | |
12172 | pattern. */ | |
12173 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12174 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12175 | || imm_expr.X_add_number >= 1 << shift | |
12176 | || imm_expr.X_add_number < -1 << shift)) | |
12177 | || i > 0) | |
12178 | { | |
12179 | imm_expr.X_op = O_absent; | |
12180 | break; | |
12181 | } | |
12182 | if (shift == 9) | |
12183 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
12184 | else | |
dec0624d MR |
12185 | INSERT_OPERAND (mips_opts.micromips, |
12186 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
12187 | imm_expr.X_op = O_absent; |
12188 | s = expr_end; | |
12189 | } | |
12190 | continue; | |
12191 | ||
252b5132 RH |
12192 | case '<': /* must be at least one digit */ |
12193 | /* | |
12194 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
12195 | * than 31 or less than 0, then the shift amount should be |
12196 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
12197 | * We issue a warning and mask out all but the low 5 bits. |
12198 | */ | |
12199 | my_getExpression (&imm_expr, s); | |
12200 | check_absolute_expr (ip, &imm_expr); | |
12201 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12202 | as_warn (_("Improper shift amount (%lu)"), |
12203 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
12204 | INSERT_OPERAND (mips_opts.micromips, |
12205 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
12206 | imm_expr.X_op = O_absent; |
12207 | s = expr_end; | |
12208 | continue; | |
12209 | ||
12210 | case '>': /* shift amount minus 32 */ | |
12211 | my_getExpression (&imm_expr, s); | |
12212 | check_absolute_expr (ip, &imm_expr); | |
12213 | if ((unsigned long) imm_expr.X_add_number < 32 | |
12214 | || (unsigned long) imm_expr.X_add_number > 63) | |
12215 | break; | |
df58fc94 RS |
12216 | INSERT_OPERAND (mips_opts.micromips, |
12217 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
12218 | imm_expr.X_op = O_absent; |
12219 | s = expr_end; | |
12220 | continue; | |
12221 | ||
90ecf173 MR |
12222 | case 'k': /* CACHE code. */ |
12223 | case 'h': /* PREFX code. */ | |
12224 | case '1': /* SYNC type. */ | |
252b5132 RH |
12225 | my_getExpression (&imm_expr, s); |
12226 | check_absolute_expr (ip, &imm_expr); | |
12227 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12228 | as_warn (_("Invalid value for `%s' (%lu)"), |
12229 | ip->insn_mo->name, | |
12230 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12231 | switch (*args) |
d954098f | 12232 | { |
df58fc94 RS |
12233 | case 'k': |
12234 | if (mips_fix_cn63xxp1 | |
12235 | && !mips_opts.micromips | |
12236 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12237 | switch (imm_expr.X_add_number) |
12238 | { | |
12239 | case 5: | |
12240 | case 25: | |
12241 | case 26: | |
12242 | case 27: | |
12243 | case 28: | |
12244 | case 29: | |
12245 | case 30: | |
12246 | case 31: /* These are ok. */ | |
12247 | break; | |
12248 | ||
12249 | default: /* The rest must be changed to 28. */ | |
12250 | imm_expr.X_add_number = 28; | |
12251 | break; | |
12252 | } | |
df58fc94 RS |
12253 | INSERT_OPERAND (mips_opts.micromips, |
12254 | CACHE, *ip, imm_expr.X_add_number); | |
12255 | break; | |
12256 | case 'h': | |
12257 | INSERT_OPERAND (mips_opts.micromips, | |
12258 | PREFX, *ip, imm_expr.X_add_number); | |
12259 | break; | |
12260 | case '1': | |
12261 | INSERT_OPERAND (mips_opts.micromips, | |
12262 | STYPE, *ip, imm_expr.X_add_number); | |
12263 | break; | |
d954098f | 12264 | } |
252b5132 RH |
12265 | imm_expr.X_op = O_absent; |
12266 | s = expr_end; | |
12267 | continue; | |
12268 | ||
90ecf173 | 12269 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12270 | { |
12271 | unsigned long mask = (mips_opts.micromips | |
12272 | ? MICROMIPSOP_MASK_CODE | |
12273 | : OP_MASK_CODE); | |
12274 | ||
12275 | my_getExpression (&imm_expr, s); | |
12276 | check_absolute_expr (ip, &imm_expr); | |
12277 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12278 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12279 | ip->insn_mo->name, | |
12280 | mask, (unsigned long) imm_expr.X_add_number); | |
12281 | INSERT_OPERAND (mips_opts.micromips, | |
12282 | CODE, *ip, imm_expr.X_add_number); | |
12283 | imm_expr.X_op = O_absent; | |
12284 | s = expr_end; | |
12285 | } | |
252b5132 RH |
12286 | continue; |
12287 | ||
90ecf173 | 12288 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12289 | { |
12290 | unsigned long mask = (mips_opts.micromips | |
12291 | ? MICROMIPSOP_MASK_CODE2 | |
12292 | : OP_MASK_CODE2); | |
12293 | ||
12294 | my_getExpression (&imm_expr, s); | |
12295 | check_absolute_expr (ip, &imm_expr); | |
12296 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12297 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12298 | ip->insn_mo->name, | |
12299 | mask, (unsigned long) imm_expr.X_add_number); | |
12300 | INSERT_OPERAND (mips_opts.micromips, | |
12301 | CODE2, *ip, imm_expr.X_add_number); | |
12302 | imm_expr.X_op = O_absent; | |
12303 | s = expr_end; | |
12304 | } | |
252b5132 RH |
12305 | continue; |
12306 | ||
df58fc94 RS |
12307 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12308 | { | |
12309 | unsigned long mask = (mips_opts.micromips | |
12310 | ? MICROMIPSOP_MASK_CODE10 | |
12311 | : OP_MASK_CODE20); | |
12312 | ||
12313 | my_getExpression (&imm_expr, s); | |
12314 | check_absolute_expr (ip, &imm_expr); | |
12315 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12316 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12317 | ip->insn_mo->name, | |
12318 | mask, (unsigned long) imm_expr.X_add_number); | |
12319 | if (mips_opts.micromips) | |
12320 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12321 | else | |
12322 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12323 | imm_expr.X_op = O_absent; | |
12324 | s = expr_end; | |
12325 | } | |
252b5132 RH |
12326 | continue; |
12327 | ||
df58fc94 RS |
12328 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12329 | { | |
12330 | unsigned long mask = (mips_opts.micromips | |
12331 | ? MICROMIPSOP_MASK_COPZ | |
12332 | : OP_MASK_COPZ); | |
12333 | ||
12334 | my_getExpression (&imm_expr, s); | |
12335 | check_absolute_expr (ip, &imm_expr); | |
12336 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12337 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12338 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12339 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12340 | INSERT_OPERAND (mips_opts.micromips, |
12341 | COPZ, *ip, imm_expr.X_add_number); | |
12342 | imm_expr.X_op = O_absent; | |
12343 | s = expr_end; | |
12344 | } | |
beae10d5 | 12345 | continue; |
252b5132 | 12346 | |
df58fc94 RS |
12347 | case 'J': /* 19-bit WAIT code. */ |
12348 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12349 | my_getExpression (&imm_expr, s); |
12350 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12351 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12352 | { |
12353 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12354 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12355 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12356 | } | |
12357 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12358 | imm_expr.X_op = O_absent; |
12359 | s = expr_end; | |
12360 | continue; | |
12361 | ||
707bfff6 | 12362 | case 'P': /* Performance register. */ |
df58fc94 | 12363 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12364 | my_getExpression (&imm_expr, s); |
252b5132 | 12365 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12366 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12367 | as_warn (_("Invalid performance register (%lu)"), |
12368 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12369 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12370 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12371 | as_warn (_("Invalid performance register (%lu)"), | |
12372 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12373 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12374 | imm_expr.X_op = O_absent; |
12375 | s = expr_end; | |
12376 | continue; | |
252b5132 | 12377 | |
707bfff6 | 12378 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12379 | { |
12380 | unsigned long opcode = ip->insn_opcode; | |
12381 | unsigned long mask; | |
12382 | unsigned int types; | |
12383 | int cop0; | |
12384 | ||
12385 | if (mips_opts.micromips) | |
12386 | { | |
12387 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12388 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12389 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12390 | opcode &= mask; | |
12391 | switch (opcode) | |
12392 | { | |
12393 | case 0x000000fc: /* mfc0 */ | |
12394 | case 0x000002fc: /* mtc0 */ | |
12395 | case 0x580000fc: /* dmfc0 */ | |
12396 | case 0x580002fc: /* dmtc0 */ | |
12397 | cop0 = 1; | |
12398 | break; | |
12399 | default: | |
12400 | cop0 = 0; | |
12401 | break; | |
12402 | } | |
12403 | } | |
12404 | else | |
12405 | { | |
12406 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12407 | cop0 = opcode == OP_OP_COP0; | |
12408 | } | |
12409 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12410 | ok = reg_lookup (&s, types, ®no); | |
12411 | if (mips_opts.micromips) | |
12412 | INSERT_OPERAND (1, RS, *ip, regno); | |
12413 | else | |
12414 | INSERT_OPERAND (0, RD, *ip, regno); | |
12415 | if (ok) | |
12416 | { | |
12417 | lastregno = regno; | |
12418 | continue; | |
12419 | } | |
12420 | } | |
12421 | break; | |
707bfff6 | 12422 | |
df58fc94 RS |
12423 | case 'y': /* ALNV.PS source register. */ |
12424 | gas_assert (mips_opts.micromips); | |
12425 | goto do_reg; | |
12426 | case 'x': /* Ignore register name. */ | |
12427 | case 'U': /* Destination register (CLO/CLZ). */ | |
12428 | case 'g': /* Coprocessor destination register. */ | |
12429 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12430 | case 'b': /* Base register. */ |
12431 | case 'd': /* Destination register. */ | |
12432 | case 's': /* Source register. */ | |
12433 | case 't': /* Target register. */ | |
12434 | case 'r': /* Both target and source. */ | |
12435 | case 'v': /* Both dest and source. */ | |
12436 | case 'w': /* Both dest and target. */ | |
12437 | case 'E': /* Coprocessor target register. */ | |
12438 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12439 | case 'z': /* Must be zero register. */ |
df58fc94 | 12440 | do_reg: |
90ecf173 | 12441 | s_reset = s; |
707bfff6 TS |
12442 | if (*args == 'E' || *args == 'K') |
12443 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12444 | else | |
12445 | { | |
12446 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12447 | if (regno == AT && mips_opts.at) |
12448 | { | |
12449 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12450 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12451 | else |
f71d0d44 | 12452 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12453 | regno, mips_opts.at); |
12454 | } | |
707bfff6 TS |
12455 | } |
12456 | if (ok) | |
252b5132 | 12457 | { |
252b5132 RH |
12458 | c = *args; |
12459 | if (*s == ' ') | |
f9419b05 | 12460 | ++s; |
252b5132 RH |
12461 | if (args[1] != *s) |
12462 | { | |
12463 | if (c == 'r' || c == 'v' || c == 'w') | |
12464 | { | |
12465 | regno = lastregno; | |
12466 | s = s_reset; | |
f9419b05 | 12467 | ++args; |
252b5132 RH |
12468 | } |
12469 | } | |
12470 | /* 'z' only matches $0. */ | |
12471 | if (c == 'z' && regno != 0) | |
12472 | break; | |
12473 | ||
24864476 | 12474 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12475 | { |
12476 | if (regno == lastregno) | |
90ecf173 MR |
12477 | { |
12478 | insn_error | |
f71d0d44 | 12479 | = _("Source and destination must be different"); |
e7c604dd | 12480 | continue; |
90ecf173 | 12481 | } |
24864476 | 12482 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12483 | { |
12484 | insn_error | |
f71d0d44 | 12485 | = _("A destination register must be supplied"); |
e7c604dd | 12486 | continue; |
90ecf173 | 12487 | } |
e7c604dd | 12488 | } |
90ecf173 MR |
12489 | /* Now that we have assembled one operand, we use the args |
12490 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12491 | switch (c) |
12492 | { | |
12493 | case 'r': | |
12494 | case 's': | |
12495 | case 'v': | |
12496 | case 'b': | |
df58fc94 | 12497 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12498 | break; |
df58fc94 | 12499 | |
af7ee8bf | 12500 | case 'K': |
df58fc94 RS |
12501 | if (mips_opts.micromips) |
12502 | INSERT_OPERAND (1, RS, *ip, regno); | |
12503 | else | |
12504 | INSERT_OPERAND (0, RD, *ip, regno); | |
12505 | break; | |
12506 | ||
12507 | case 'd': | |
ef2e4d86 | 12508 | case 'g': |
df58fc94 | 12509 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12510 | break; |
df58fc94 | 12511 | |
4372b673 | 12512 | case 'U': |
df58fc94 RS |
12513 | gas_assert (!mips_opts.micromips); |
12514 | INSERT_OPERAND (0, RD, *ip, regno); | |
12515 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12516 | break; |
df58fc94 | 12517 | |
252b5132 RH |
12518 | case 'w': |
12519 | case 't': | |
12520 | case 'E': | |
df58fc94 RS |
12521 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12522 | break; | |
12523 | ||
12524 | case 'y': | |
12525 | gas_assert (mips_opts.micromips); | |
12526 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12527 | break; |
df58fc94 | 12528 | |
252b5132 RH |
12529 | case 'x': |
12530 | /* This case exists because on the r3000 trunc | |
12531 | expands into a macro which requires a gp | |
12532 | register. On the r6000 or r4000 it is | |
12533 | assembled into a single instruction which | |
12534 | ignores the register. Thus the insn version | |
12535 | is MIPS_ISA2 and uses 'x', and the macro | |
12536 | version is MIPS_ISA1 and uses 't'. */ | |
12537 | break; | |
df58fc94 | 12538 | |
252b5132 RH |
12539 | case 'z': |
12540 | /* This case is for the div instruction, which | |
12541 | acts differently if the destination argument | |
12542 | is $0. This only matches $0, and is checked | |
12543 | outside the switch. */ | |
12544 | break; | |
252b5132 RH |
12545 | } |
12546 | lastregno = regno; | |
12547 | continue; | |
12548 | } | |
252b5132 RH |
12549 | switch (*args++) |
12550 | { | |
12551 | case 'r': | |
12552 | case 'v': | |
df58fc94 | 12553 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12554 | continue; |
df58fc94 | 12555 | |
252b5132 | 12556 | case 'w': |
df58fc94 | 12557 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12558 | continue; |
12559 | } | |
12560 | break; | |
12561 | ||
deec1734 | 12562 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12563 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12564 | my_getExpression (&imm_expr, s); |
12565 | check_absolute_expr (ip, &imm_expr); | |
12566 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12567 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12568 | (long) imm_expr.X_add_number); |
df58fc94 | 12569 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12570 | imm_expr.X_op = O_absent; |
12571 | s = expr_end; | |
12572 | continue; | |
12573 | ||
12574 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12575 | if (s[0] != '$') | |
12576 | { | |
12577 | /* MDMX Immediate. */ | |
df58fc94 | 12578 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12579 | my_getExpression (&imm_expr, s); |
12580 | check_absolute_expr (ip, &imm_expr); | |
12581 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12582 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12583 | (long) imm_expr.X_add_number); | |
df58fc94 | 12584 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12585 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12586 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12587 | else | |
12588 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12589 | imm_expr.X_op = O_absent; |
12590 | s = expr_end; | |
12591 | continue; | |
12592 | } | |
12593 | /* Not MDMX Immediate. Fall through. */ | |
12594 | case 'X': /* MDMX destination register. */ | |
12595 | case 'Y': /* MDMX source register. */ | |
12596 | case 'Z': /* MDMX target register. */ | |
12597 | is_mdmx = 1; | |
df58fc94 RS |
12598 | case 'W': |
12599 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12600 | case 'D': /* Floating point destination register. */ |
12601 | case 'S': /* Floating point source register. */ | |
12602 | case 'T': /* Floating point target register. */ | |
12603 | case 'R': /* Floating point source register. */ | |
252b5132 | 12604 | case 'V': |
707bfff6 TS |
12605 | rtype = RTYPE_FPU; |
12606 | if (is_mdmx | |
846ef2d0 | 12607 | || ((mips_opts.ase & ASE_MDMX) |
707bfff6 TS |
12608 | && (ip->insn_mo->pinfo & FP_D) |
12609 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12610 | | INSN_COPROC_MEMORY_DELAY | |
12611 | | INSN_LOAD_COPROC_DELAY | |
12612 | | INSN_LOAD_MEMORY_DELAY | |
12613 | | INSN_STORE_MEMORY)))) | |
12614 | rtype |= RTYPE_VEC; | |
252b5132 | 12615 | s_reset = s; |
707bfff6 | 12616 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12617 | { |
252b5132 | 12618 | if ((regno & 1) != 0 |
ca4e0257 | 12619 | && HAVE_32BIT_FPRS |
90ecf173 | 12620 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12621 | as_warn (_("Float register should be even, was %d"), |
12622 | regno); | |
12623 | ||
12624 | c = *args; | |
12625 | if (*s == ' ') | |
f9419b05 | 12626 | ++s; |
252b5132 RH |
12627 | if (args[1] != *s) |
12628 | { | |
12629 | if (c == 'V' || c == 'W') | |
12630 | { | |
12631 | regno = lastregno; | |
12632 | s = s_reset; | |
f9419b05 | 12633 | ++args; |
252b5132 RH |
12634 | } |
12635 | } | |
12636 | switch (c) | |
12637 | { | |
12638 | case 'D': | |
deec1734 | 12639 | case 'X': |
df58fc94 | 12640 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12641 | break; |
df58fc94 | 12642 | |
252b5132 RH |
12643 | case 'V': |
12644 | case 'S': | |
deec1734 | 12645 | case 'Y': |
df58fc94 | 12646 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12647 | break; |
df58fc94 | 12648 | |
deec1734 CD |
12649 | case 'Q': |
12650 | /* This is like 'Z', but also needs to fix the MDMX | |
12651 | vector/scalar select bits. Note that the | |
12652 | scalar immediate case is handled above. */ | |
12653 | if (*s == '[') | |
12654 | { | |
12655 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12656 | int max_el = (is_qh ? 3 : 7); | |
12657 | s++; | |
12658 | my_getExpression(&imm_expr, s); | |
12659 | check_absolute_expr (ip, &imm_expr); | |
12660 | s = expr_end; | |
12661 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12662 | as_bad (_("Bad element selector %ld"), |
12663 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12664 | imm_expr.X_add_number &= max_el; |
12665 | ip->insn_opcode |= (imm_expr.X_add_number | |
12666 | << (OP_SH_VSEL + | |
12667 | (is_qh ? 2 : 1))); | |
01a3f561 | 12668 | imm_expr.X_op = O_absent; |
deec1734 | 12669 | if (*s != ']') |
20203fb9 | 12670 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12671 | else |
12672 | s++; | |
12673 | } | |
12674 | else | |
12675 | { | |
12676 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12677 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12678 | << OP_SH_VSEL); | |
12679 | else | |
12680 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12681 | OP_SH_VSEL); | |
12682 | } | |
90ecf173 | 12683 | /* Fall through. */ |
252b5132 RH |
12684 | case 'W': |
12685 | case 'T': | |
deec1734 | 12686 | case 'Z': |
df58fc94 | 12687 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12688 | break; |
df58fc94 | 12689 | |
252b5132 | 12690 | case 'R': |
df58fc94 | 12691 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12692 | break; |
12693 | } | |
12694 | lastregno = regno; | |
12695 | continue; | |
12696 | } | |
12697 | ||
252b5132 RH |
12698 | switch (*args++) |
12699 | { | |
12700 | case 'V': | |
df58fc94 | 12701 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12702 | continue; |
df58fc94 | 12703 | |
252b5132 | 12704 | case 'W': |
df58fc94 | 12705 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12706 | continue; |
12707 | } | |
12708 | break; | |
12709 | ||
12710 | case 'I': | |
12711 | my_getExpression (&imm_expr, s); | |
12712 | if (imm_expr.X_op != O_big | |
12713 | && imm_expr.X_op != O_constant) | |
12714 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12715 | if (HAVE_32BIT_GPRS) |
12716 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12717 | s = expr_end; |
12718 | continue; | |
12719 | ||
12720 | case 'A': | |
12721 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12722 | normalize_address_expr (&offset_expr); |
f6688943 | 12723 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12724 | s = expr_end; |
12725 | continue; | |
12726 | ||
12727 | case 'F': | |
12728 | case 'L': | |
12729 | case 'f': | |
12730 | case 'l': | |
12731 | { | |
12732 | int f64; | |
ca4e0257 | 12733 | int using_gprs; |
252b5132 RH |
12734 | char *save_in; |
12735 | char *err; | |
12736 | unsigned char temp[8]; | |
12737 | int len; | |
12738 | unsigned int length; | |
12739 | segT seg; | |
12740 | subsegT subseg; | |
12741 | char *p; | |
12742 | ||
12743 | /* These only appear as the last operand in an | |
12744 | instruction, and every instruction that accepts | |
12745 | them in any variant accepts them in all variants. | |
12746 | This means we don't have to worry about backing out | |
12747 | any changes if the instruction does not match. | |
12748 | ||
12749 | The difference between them is the size of the | |
12750 | floating point constant and where it goes. For 'F' | |
12751 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12752 | is 32 bits. Where the constant is placed is based | |
12753 | on how the MIPS assembler does things: | |
12754 | F -- .rdata | |
12755 | L -- .lit8 | |
12756 | f -- immediate value | |
12757 | l -- .lit4 | |
12758 | ||
12759 | The .lit4 and .lit8 sections are only used if | |
12760 | permitted by the -G argument. | |
12761 | ||
ca4e0257 RS |
12762 | The code below needs to know whether the target register |
12763 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12764 | 'F' are used with GPR-based instructions and 'l' and | |
12765 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12766 | |
12767 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12768 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12769 | |
12770 | save_in = input_line_pointer; | |
12771 | input_line_pointer = s; | |
12772 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12773 | length = len; | |
12774 | s = input_line_pointer; | |
12775 | input_line_pointer = save_in; | |
12776 | if (err != NULL && *err != '\0') | |
12777 | { | |
12778 | as_bad (_("Bad floating point constant: %s"), err); | |
12779 | memset (temp, '\0', sizeof temp); | |
12780 | length = f64 ? 8 : 4; | |
12781 | } | |
12782 | ||
9c2799c2 | 12783 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12784 | |
12785 | if (*args == 'f' | |
12786 | || (*args == 'l' | |
3e722fb5 | 12787 | && (g_switch_value < 4 |
252b5132 RH |
12788 | || (temp[0] == 0 && temp[1] == 0) |
12789 | || (temp[2] == 0 && temp[3] == 0)))) | |
12790 | { | |
12791 | imm_expr.X_op = O_constant; | |
90ecf173 | 12792 | if (!target_big_endian) |
252b5132 RH |
12793 | imm_expr.X_add_number = bfd_getl32 (temp); |
12794 | else | |
12795 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12796 | } | |
12797 | else if (length > 4 | |
90ecf173 | 12798 | && !mips_disable_float_construction |
ca4e0257 RS |
12799 | /* Constants can only be constructed in GPRs and |
12800 | copied to FPRs if the GPRs are at least as wide | |
12801 | as the FPRs. Force the constant into memory if | |
12802 | we are using 64-bit FPRs but the GPRs are only | |
12803 | 32 bits wide. */ | |
12804 | && (using_gprs | |
90ecf173 | 12805 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12806 | && ((temp[0] == 0 && temp[1] == 0) |
12807 | || (temp[2] == 0 && temp[3] == 0)) | |
12808 | && ((temp[4] == 0 && temp[5] == 0) | |
12809 | || (temp[6] == 0 && temp[7] == 0))) | |
12810 | { | |
ca4e0257 | 12811 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12812 | instructions. If using 32-bit registers, set |
12813 | imm_expr to the high order 32 bits and offset_expr to | |
12814 | the low order 32 bits. Otherwise, set imm_expr to | |
12815 | the entire 64 bit constant. */ | |
ca4e0257 | 12816 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12817 | { |
12818 | imm_expr.X_op = O_constant; | |
12819 | offset_expr.X_op = O_constant; | |
90ecf173 | 12820 | if (!target_big_endian) |
252b5132 RH |
12821 | { |
12822 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12823 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12824 | } | |
12825 | else | |
12826 | { | |
12827 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12828 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12829 | } | |
12830 | if (offset_expr.X_add_number == 0) | |
12831 | offset_expr.X_op = O_absent; | |
12832 | } | |
42429eac | 12833 | else |
252b5132 RH |
12834 | { |
12835 | imm_expr.X_op = O_constant; | |
90ecf173 | 12836 | if (!target_big_endian) |
252b5132 RH |
12837 | imm_expr.X_add_number = bfd_getl64 (temp); |
12838 | else | |
12839 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12840 | } | |
252b5132 RH |
12841 | } |
12842 | else | |
12843 | { | |
12844 | const char *newname; | |
12845 | segT new_seg; | |
12846 | ||
12847 | /* Switch to the right section. */ | |
12848 | seg = now_seg; | |
12849 | subseg = now_subseg; | |
12850 | switch (*args) | |
12851 | { | |
12852 | default: /* unused default case avoids warnings. */ | |
12853 | case 'L': | |
12854 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12855 | if (g_switch_value >= 8) |
252b5132 RH |
12856 | newname = ".lit8"; |
12857 | break; | |
12858 | case 'F': | |
3e722fb5 | 12859 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12860 | break; |
12861 | case 'l': | |
9c2799c2 | 12862 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12863 | newname = ".lit4"; |
12864 | break; | |
12865 | } | |
12866 | new_seg = subseg_new (newname, (subsegT) 0); | |
f3ded42a RS |
12867 | bfd_set_section_flags (stdoutput, new_seg, |
12868 | (SEC_ALLOC | |
12869 | | SEC_LOAD | |
12870 | | SEC_READONLY | |
12871 | | SEC_DATA)); | |
252b5132 | 12872 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
f3ded42a | 12873 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12874 | record_alignment (new_seg, 4); |
12875 | else | |
12876 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12877 | if (seg == now_seg) | |
12878 | as_bad (_("Can't use floating point insn in this section")); | |
12879 | ||
df58fc94 RS |
12880 | /* Set the argument to the current address in the |
12881 | section. */ | |
12882 | offset_expr.X_op = O_symbol; | |
12883 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12884 | offset_expr.X_add_number = 0; | |
12885 | ||
12886 | /* Put the floating point number into the section. */ | |
12887 | p = frag_more ((int) length); | |
12888 | memcpy (p, temp, length); | |
12889 | ||
12890 | /* Switch back to the original section. */ | |
12891 | subseg_set (seg, subseg); | |
12892 | } | |
12893 | } | |
12894 | continue; | |
12895 | ||
12896 | case 'i': /* 16-bit unsigned immediate. */ | |
12897 | case 'j': /* 16-bit signed immediate. */ | |
12898 | *imm_reloc = BFD_RELOC_LO16; | |
12899 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12900 | { | |
12901 | int more; | |
12902 | offsetT minval, maxval; | |
12903 | ||
12904 | more = (insn + 1 < past | |
12905 | && strcmp (insn->name, insn[1].name) == 0); | |
12906 | ||
df58fc94 RS |
12907 | /* For compatibility with older assemblers, we accept |
12908 | 0x8000-0xffff as signed 16-bit numbers when only | |
12909 | signed numbers are allowed. */ | |
12910 | if (*args == 'i') | |
12911 | minval = 0, maxval = 0xffff; | |
12912 | else if (more) | |
12913 | minval = -0x8000, maxval = 0x7fff; | |
12914 | else | |
12915 | minval = -0x8000, maxval = 0xffff; | |
12916 | ||
12917 | if (imm_expr.X_op != O_constant | |
12918 | || imm_expr.X_add_number < minval | |
12919 | || imm_expr.X_add_number > maxval) | |
12920 | { | |
12921 | if (more) | |
12922 | break; | |
12923 | if (imm_expr.X_op == O_constant | |
12924 | || imm_expr.X_op == O_big) | |
12925 | as_bad (_("Expression out of range")); | |
12926 | } | |
12927 | } | |
12928 | s = expr_end; | |
12929 | continue; | |
12930 | ||
12931 | case 'o': /* 16-bit offset. */ | |
12932 | offset_reloc[0] = BFD_RELOC_LO16; | |
12933 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12934 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12935 | ||
12936 | /* Check whether there is only a single bracketed expression | |
12937 | left. If so, it must be the base register and the | |
12938 | constant must be zero. */ | |
12939 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12940 | { | |
12941 | offset_expr.X_op = O_constant; | |
12942 | offset_expr.X_add_number = 0; | |
12943 | continue; | |
12944 | } | |
12945 | ||
12946 | /* If this value won't fit into a 16 bit offset, then go | |
12947 | find a macro that will generate the 32 bit offset | |
12948 | code pattern. */ | |
12949 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12950 | && (offset_expr.X_op != O_constant | |
12951 | || offset_expr.X_add_number >= 0x8000 | |
12952 | || offset_expr.X_add_number < -0x8000)) | |
12953 | break; | |
12954 | ||
12955 | s = expr_end; | |
12956 | continue; | |
12957 | ||
12958 | case 'p': /* PC-relative offset. */ | |
12959 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12960 | my_getExpression (&offset_expr, s); | |
12961 | s = expr_end; | |
12962 | continue; | |
12963 | ||
12964 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12965 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12966 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12967 | && imm_expr.X_op == O_constant | |
12968 | && (imm_expr.X_add_number < 0 | |
12969 | || imm_expr.X_add_number >= 0x10000)) | |
12970 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12971 | (unsigned long) imm_expr.X_add_number); | |
12972 | s = expr_end; | |
12973 | continue; | |
12974 | ||
12975 | case 'a': /* 26-bit address. */ | |
12976 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12977 | my_getExpression (&offset_expr, s); | |
12978 | s = expr_end; | |
12979 | continue; | |
12980 | ||
12981 | case 'N': /* 3-bit branch condition code. */ | |
12982 | case 'M': /* 3-bit compare condition code. */ | |
12983 | rtype = RTYPE_CCC; | |
12984 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12985 | rtype |= RTYPE_FCC; | |
12986 | if (!reg_lookup (&s, rtype, ®no)) | |
12987 | break; | |
12988 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12989 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12990 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12991 | && (regno & 1) != 0) | |
12992 | as_warn (_("Condition code register should be even for %s, " | |
12993 | "was %d"), | |
12994 | str, regno); | |
12995 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12996 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12997 | && (regno & 3) != 0) | |
12998 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12999 | "was %d"), | |
13000 | str, regno); | |
13001 | if (*args == 'N') | |
13002 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
13003 | else | |
13004 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
13005 | continue; | |
13006 | ||
13007 | case 'H': | |
13008 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
13009 | s += 2; | |
13010 | if (ISDIGIT (*s)) | |
13011 | { | |
13012 | c = 0; | |
13013 | do | |
13014 | { | |
13015 | c *= 10; | |
13016 | c += *s - '0'; | |
13017 | ++s; | |
13018 | } | |
13019 | while (ISDIGIT (*s)); | |
13020 | } | |
13021 | else | |
13022 | c = 8; /* Invalid sel value. */ | |
13023 | ||
13024 | if (c > 7) | |
13025 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
13026 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
13027 | continue; | |
13028 | ||
13029 | case 'e': | |
13030 | gas_assert (!mips_opts.micromips); | |
13031 | /* Must be at least one digit. */ | |
13032 | my_getExpression (&imm_expr, s); | |
13033 | check_absolute_expr (ip, &imm_expr); | |
13034 | ||
13035 | if ((unsigned long) imm_expr.X_add_number | |
13036 | > (unsigned long) OP_MASK_VECBYTE) | |
13037 | { | |
13038 | as_bad (_("bad byte vector index (%ld)"), | |
13039 | (long) imm_expr.X_add_number); | |
13040 | imm_expr.X_add_number = 0; | |
13041 | } | |
13042 | ||
13043 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
13044 | imm_expr.X_op = O_absent; | |
13045 | s = expr_end; | |
13046 | continue; | |
13047 | ||
13048 | case '%': | |
13049 | gas_assert (!mips_opts.micromips); | |
13050 | my_getExpression (&imm_expr, s); | |
13051 | check_absolute_expr (ip, &imm_expr); | |
13052 | ||
13053 | if ((unsigned long) imm_expr.X_add_number | |
13054 | > (unsigned long) OP_MASK_VECALIGN) | |
13055 | { | |
13056 | as_bad (_("bad byte vector index (%ld)"), | |
13057 | (long) imm_expr.X_add_number); | |
13058 | imm_expr.X_add_number = 0; | |
13059 | } | |
13060 | ||
13061 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
13062 | imm_expr.X_op = O_absent; | |
13063 | s = expr_end; | |
13064 | continue; | |
13065 | ||
13066 | case 'm': /* Opcode extension character. */ | |
13067 | gas_assert (mips_opts.micromips); | |
13068 | c = *++args; | |
13069 | switch (c) | |
13070 | { | |
13071 | case 'r': | |
13072 | if (strncmp (s, "$pc", 3) == 0) | |
13073 | { | |
13074 | s += 3; | |
13075 | continue; | |
13076 | } | |
13077 | break; | |
13078 | ||
13079 | case 'a': | |
13080 | case 'b': | |
13081 | case 'c': | |
13082 | case 'd': | |
13083 | case 'e': | |
13084 | case 'f': | |
13085 | case 'g': | |
13086 | case 'h': | |
13087 | case 'i': | |
13088 | case 'j': | |
13089 | case 'l': | |
13090 | case 'm': | |
13091 | case 'n': | |
13092 | case 'p': | |
13093 | case 'q': | |
13094 | case 's': | |
13095 | case 't': | |
13096 | case 'x': | |
13097 | case 'y': | |
13098 | case 'z': | |
13099 | s_reset = s; | |
13100 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
13101 | if (regno == AT && mips_opts.at) | |
13102 | { | |
13103 | if (mips_opts.at == ATREG) | |
13104 | as_warn (_("Used $at without \".set noat\"")); | |
13105 | else | |
13106 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13107 | regno, mips_opts.at); | |
13108 | } | |
13109 | if (!ok) | |
13110 | { | |
13111 | if (c == 'c') | |
13112 | { | |
13113 | gas_assert (args[1] == ','); | |
13114 | regno = lastregno; | |
13115 | ++args; | |
13116 | } | |
13117 | else if (c == 't') | |
13118 | { | |
13119 | gas_assert (args[1] == ','); | |
13120 | ++args; | |
13121 | continue; /* Nothing to do. */ | |
13122 | } | |
13123 | else | |
13124 | break; | |
13125 | } | |
13126 | ||
13127 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
13128 | { | |
13129 | if (regno == lastregno) | |
13130 | { | |
13131 | insn_error | |
13132 | = _("Source and destination must be different"); | |
13133 | continue; | |
13134 | } | |
13135 | if (regno == 31 && lastregno == 0xffffffff) | |
13136 | { | |
13137 | insn_error | |
13138 | = _("A destination register must be supplied"); | |
13139 | continue; | |
13140 | } | |
13141 | } | |
13142 | ||
13143 | if (*s == ' ') | |
13144 | ++s; | |
13145 | if (args[1] != *s) | |
13146 | { | |
13147 | if (c == 'e') | |
13148 | { | |
13149 | gas_assert (args[1] == ','); | |
13150 | regno = lastregno; | |
13151 | s = s_reset; | |
13152 | ++args; | |
13153 | } | |
13154 | else if (c == 't') | |
13155 | { | |
13156 | gas_assert (args[1] == ','); | |
13157 | s = s_reset; | |
13158 | ++args; | |
13159 | continue; /* Nothing to do. */ | |
13160 | } | |
13161 | } | |
13162 | ||
13163 | /* Make sure regno is the same as lastregno. */ | |
13164 | if (c == 't' && regno != lastregno) | |
13165 | break; | |
13166 | ||
13167 | /* Make sure regno is the same as destregno. */ | |
13168 | if (c == 'x' && regno != destregno) | |
13169 | break; | |
13170 | ||
13171 | /* We need to save regno, before regno maps to the | |
13172 | microMIPS register encoding. */ | |
13173 | lastregno = regno; | |
13174 | ||
13175 | if (c == 'f') | |
13176 | destregno = regno; | |
13177 | ||
13178 | switch (c) | |
13179 | { | |
13180 | case 'a': | |
13181 | if (regno != GP) | |
13182 | regno = ILLEGAL_REG; | |
13183 | break; | |
13184 | ||
13185 | case 'b': | |
13186 | regno = mips32_to_micromips_reg_b_map[regno]; | |
13187 | break; | |
13188 | ||
13189 | case 'c': | |
13190 | regno = mips32_to_micromips_reg_c_map[regno]; | |
13191 | break; | |
13192 | ||
13193 | case 'd': | |
13194 | regno = mips32_to_micromips_reg_d_map[regno]; | |
13195 | break; | |
13196 | ||
13197 | case 'e': | |
13198 | regno = mips32_to_micromips_reg_e_map[regno]; | |
13199 | break; | |
13200 | ||
13201 | case 'f': | |
13202 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13203 | break; | |
13204 | ||
13205 | case 'g': | |
13206 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13207 | break; | |
13208 | ||
13209 | case 'h': | |
13210 | regno = mips32_to_micromips_reg_h_map[regno]; | |
13211 | break; | |
13212 | ||
13213 | case 'i': | |
13214 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
13215 | { | |
13216 | case 4: | |
13217 | if (regno == 21) | |
13218 | regno = 3; | |
13219 | else if (regno == 22) | |
13220 | regno = 4; | |
13221 | else if (regno == 5) | |
13222 | regno = 5; | |
13223 | else if (regno == 6) | |
13224 | regno = 6; | |
13225 | else if (regno == 7) | |
13226 | regno = 7; | |
13227 | else | |
13228 | regno = ILLEGAL_REG; | |
13229 | break; | |
13230 | ||
13231 | case 5: | |
13232 | if (regno == 6) | |
13233 | regno = 0; | |
13234 | else if (regno == 7) | |
13235 | regno = 1; | |
13236 | else | |
13237 | regno = ILLEGAL_REG; | |
13238 | break; | |
13239 | ||
13240 | case 6: | |
13241 | if (regno == 7) | |
13242 | regno = 2; | |
13243 | else | |
13244 | regno = ILLEGAL_REG; | |
13245 | break; | |
13246 | ||
13247 | default: | |
13248 | regno = ILLEGAL_REG; | |
13249 | break; | |
13250 | } | |
13251 | break; | |
13252 | ||
13253 | case 'l': | |
13254 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13255 | break; | |
13256 | ||
13257 | case 'm': | |
13258 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13259 | break; | |
13260 | ||
13261 | case 'n': | |
13262 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13263 | break; | |
13264 | ||
13265 | case 'q': | |
13266 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13267 | break; | |
13268 | ||
13269 | case 's': | |
13270 | if (regno != SP) | |
13271 | regno = ILLEGAL_REG; | |
13272 | break; | |
13273 | ||
13274 | case 'y': | |
13275 | if (regno != 31) | |
13276 | regno = ILLEGAL_REG; | |
13277 | break; | |
13278 | ||
13279 | case 'z': | |
13280 | if (regno != ZERO) | |
13281 | regno = ILLEGAL_REG; | |
13282 | break; | |
13283 | ||
13284 | case 'j': /* Do nothing. */ | |
13285 | case 'p': | |
13286 | case 't': | |
13287 | case 'x': | |
13288 | break; | |
13289 | ||
13290 | default: | |
b37df7c4 | 13291 | abort (); |
df58fc94 RS |
13292 | } |
13293 | ||
13294 | if (regno == ILLEGAL_REG) | |
13295 | break; | |
13296 | ||
13297 | switch (c) | |
13298 | { | |
13299 | case 'b': | |
13300 | INSERT_OPERAND (1, MB, *ip, regno); | |
13301 | break; | |
13302 | ||
13303 | case 'c': | |
13304 | INSERT_OPERAND (1, MC, *ip, regno); | |
13305 | break; | |
13306 | ||
13307 | case 'd': | |
13308 | INSERT_OPERAND (1, MD, *ip, regno); | |
13309 | break; | |
13310 | ||
13311 | case 'e': | |
13312 | INSERT_OPERAND (1, ME, *ip, regno); | |
13313 | break; | |
13314 | ||
13315 | case 'f': | |
13316 | INSERT_OPERAND (1, MF, *ip, regno); | |
13317 | break; | |
13318 | ||
13319 | case 'g': | |
13320 | INSERT_OPERAND (1, MG, *ip, regno); | |
13321 | break; | |
13322 | ||
13323 | case 'h': | |
13324 | INSERT_OPERAND (1, MH, *ip, regno); | |
13325 | break; | |
13326 | ||
13327 | case 'i': | |
13328 | INSERT_OPERAND (1, MI, *ip, regno); | |
13329 | break; | |
13330 | ||
13331 | case 'j': | |
13332 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13333 | break; | |
13334 | ||
13335 | case 'l': | |
13336 | INSERT_OPERAND (1, ML, *ip, regno); | |
13337 | break; | |
13338 | ||
13339 | case 'm': | |
13340 | INSERT_OPERAND (1, MM, *ip, regno); | |
13341 | break; | |
13342 | ||
13343 | case 'n': | |
13344 | INSERT_OPERAND (1, MN, *ip, regno); | |
13345 | break; | |
13346 | ||
13347 | case 'p': | |
13348 | INSERT_OPERAND (1, MP, *ip, regno); | |
13349 | break; | |
13350 | ||
13351 | case 'q': | |
13352 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13353 | break; | |
13354 | ||
13355 | case 'a': /* Do nothing. */ | |
13356 | case 's': /* Do nothing. */ | |
13357 | case 't': /* Do nothing. */ | |
13358 | case 'x': /* Do nothing. */ | |
13359 | case 'y': /* Do nothing. */ | |
13360 | case 'z': /* Do nothing. */ | |
13361 | break; | |
13362 | ||
13363 | default: | |
b37df7c4 | 13364 | abort (); |
df58fc94 RS |
13365 | } |
13366 | continue; | |
13367 | ||
13368 | case 'A': | |
13369 | { | |
13370 | bfd_reloc_code_real_type r[3]; | |
13371 | expressionS ep; | |
13372 | int imm; | |
13373 | ||
13374 | /* Check whether there is only a single bracketed | |
13375 | expression left. If so, it must be the base register | |
13376 | and the constant must be zero. */ | |
13377 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13378 | { | |
13379 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13380 | continue; | |
13381 | } | |
13382 | ||
13383 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13384 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13385 | break; | |
13386 | ||
13387 | imm = ep.X_add_number >> 2; | |
13388 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13389 | } | |
13390 | s = expr_end; | |
13391 | continue; | |
13392 | ||
13393 | case 'B': | |
13394 | { | |
13395 | bfd_reloc_code_real_type r[3]; | |
13396 | expressionS ep; | |
13397 | int imm; | |
13398 | ||
13399 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13400 | || ep.X_op != O_constant) | |
13401 | break; | |
13402 | ||
13403 | for (imm = 0; imm < 8; imm++) | |
13404 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13405 | break; | |
13406 | if (imm >= 8) | |
13407 | break; | |
13408 | ||
13409 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13410 | } | |
13411 | s = expr_end; | |
13412 | continue; | |
13413 | ||
13414 | case 'C': | |
13415 | { | |
13416 | bfd_reloc_code_real_type r[3]; | |
13417 | expressionS ep; | |
13418 | int imm; | |
13419 | ||
13420 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13421 | || ep.X_op != O_constant) | |
13422 | break; | |
13423 | ||
13424 | for (imm = 0; imm < 16; imm++) | |
13425 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13426 | break; | |
13427 | if (imm >= 16) | |
13428 | break; | |
13429 | ||
13430 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13431 | } | |
13432 | s = expr_end; | |
13433 | continue; | |
13434 | ||
13435 | case 'D': /* pc relative offset */ | |
13436 | case 'E': /* pc relative offset */ | |
13437 | my_getExpression (&offset_expr, s); | |
13438 | if (offset_expr.X_op == O_register) | |
13439 | break; | |
13440 | ||
40209cad MR |
13441 | if (!forced_insn_length) |
13442 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13443 | else if (c == 'D') | |
13444 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13445 | else | |
13446 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13447 | s = expr_end; |
13448 | continue; | |
13449 | ||
13450 | case 'F': | |
13451 | { | |
13452 | bfd_reloc_code_real_type r[3]; | |
13453 | expressionS ep; | |
13454 | int imm; | |
13455 | ||
13456 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13457 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13458 | break; | |
13459 | ||
13460 | imm = ep.X_add_number; | |
13461 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13462 | } | |
13463 | s = expr_end; | |
13464 | continue; | |
13465 | ||
13466 | case 'G': | |
13467 | { | |
13468 | bfd_reloc_code_real_type r[3]; | |
13469 | expressionS ep; | |
13470 | int imm; | |
13471 | ||
13472 | /* Check whether there is only a single bracketed | |
13473 | expression left. If so, it must be the base register | |
13474 | and the constant must be zero. */ | |
13475 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13476 | { | |
13477 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13478 | continue; | |
13479 | } | |
13480 | ||
13481 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13482 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13483 | break; | |
13484 | ||
13485 | imm = ep.X_add_number & 15; | |
13486 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13487 | } | |
13488 | s = expr_end; | |
13489 | continue; | |
13490 | ||
13491 | case 'H': | |
13492 | { | |
13493 | bfd_reloc_code_real_type r[3]; | |
13494 | expressionS ep; | |
13495 | int imm; | |
13496 | ||
13497 | /* Check whether there is only a single bracketed | |
13498 | expression left. If so, it must be the base register | |
13499 | and the constant must be zero. */ | |
13500 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13501 | { | |
13502 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13503 | continue; | |
13504 | } | |
13505 | ||
13506 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13507 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13508 | break; | |
13509 | ||
13510 | imm = ep.X_add_number >> 1; | |
13511 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13512 | } | |
13513 | s = expr_end; | |
13514 | continue; | |
13515 | ||
13516 | case 'I': | |
13517 | { | |
13518 | bfd_reloc_code_real_type r[3]; | |
13519 | expressionS ep; | |
13520 | int imm; | |
13521 | ||
13522 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13523 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13524 | break; | |
13525 | ||
13526 | imm = ep.X_add_number & 127; | |
13527 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13528 | } | |
13529 | s = expr_end; | |
13530 | continue; | |
13531 | ||
13532 | case 'J': | |
13533 | { | |
13534 | bfd_reloc_code_real_type r[3]; | |
13535 | expressionS ep; | |
13536 | int imm; | |
13537 | ||
13538 | /* Check whether there is only a single bracketed | |
13539 | expression left. If so, it must be the base register | |
13540 | and the constant must be zero. */ | |
13541 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13542 | { | |
13543 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13544 | continue; | |
13545 | } | |
13546 | ||
13547 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13548 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13549 | break; | |
13550 | ||
13551 | imm = ep.X_add_number >> 2; | |
13552 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13553 | } | |
13554 | s = expr_end; | |
13555 | continue; | |
13556 | ||
13557 | case 'L': | |
13558 | { | |
13559 | bfd_reloc_code_real_type r[3]; | |
13560 | expressionS ep; | |
13561 | int imm; | |
13562 | ||
13563 | /* Check whether there is only a single bracketed | |
13564 | expression left. If so, it must be the base register | |
13565 | and the constant must be zero. */ | |
13566 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13567 | { | |
13568 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13569 | continue; | |
13570 | } | |
13571 | ||
13572 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13573 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13574 | break; | |
13575 | ||
13576 | imm = ep.X_add_number; | |
13577 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13578 | } | |
13579 | s = expr_end; | |
13580 | continue; | |
13581 | ||
13582 | case 'M': | |
13583 | { | |
13584 | bfd_reloc_code_real_type r[3]; | |
13585 | expressionS ep; | |
13586 | int imm; | |
13587 | ||
13588 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13589 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13590 | break; | |
13591 | ||
13592 | imm = ep.X_add_number & 7; | |
13593 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13594 | } | |
13595 | s = expr_end; | |
13596 | continue; | |
13597 | ||
13598 | case 'N': /* Register list for lwm and swm. */ | |
13599 | { | |
13600 | /* A comma-separated list of registers and/or | |
13601 | dash-separated contiguous ranges including | |
13602 | both ra and a set of one or more registers | |
13603 | starting at s0 up to s3 which have to be | |
13604 | consecutive, e.g.: | |
13605 | ||
13606 | s0, ra | |
13607 | s0, s1, ra, s2, s3 | |
13608 | s0-s2, ra | |
13609 | ||
13610 | and any permutations of these. */ | |
13611 | unsigned int reglist; | |
13612 | int imm; | |
13613 | ||
13614 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13615 | break; | |
13616 | ||
13617 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13618 | break; | |
13619 | ||
13620 | reglist = (reglist >> 17) & 7; | |
13621 | reglist += 1; | |
13622 | if ((reglist & -reglist) != reglist) | |
13623 | break; | |
252b5132 | 13624 | |
df58fc94 RS |
13625 | imm = ffs (reglist) - 1; |
13626 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13627 | } | |
13628 | continue; | |
252b5132 | 13629 | |
df58fc94 RS |
13630 | case 'O': /* sdbbp 4-bit code. */ |
13631 | { | |
13632 | bfd_reloc_code_real_type r[3]; | |
13633 | expressionS ep; | |
13634 | int imm; | |
13635 | ||
13636 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13637 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13638 | break; | |
13639 | ||
13640 | imm = ep.X_add_number; | |
13641 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13642 | } |
df58fc94 RS |
13643 | s = expr_end; |
13644 | continue; | |
252b5132 | 13645 | |
df58fc94 RS |
13646 | case 'P': |
13647 | { | |
13648 | bfd_reloc_code_real_type r[3]; | |
13649 | expressionS ep; | |
13650 | int imm; | |
5e0116d5 | 13651 | |
df58fc94 RS |
13652 | if (my_getSmallExpression (&ep, r, s) > 0 |
13653 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13654 | break; | |
5e0116d5 | 13655 | |
df58fc94 RS |
13656 | imm = ep.X_add_number >> 2; |
13657 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13658 | } | |
13659 | s = expr_end; | |
13660 | continue; | |
5e0116d5 | 13661 | |
df58fc94 RS |
13662 | case 'Q': |
13663 | { | |
13664 | bfd_reloc_code_real_type r[3]; | |
13665 | expressionS ep; | |
13666 | int imm; | |
5e0116d5 | 13667 | |
df58fc94 RS |
13668 | if (my_getSmallExpression (&ep, r, s) > 0 |
13669 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13670 | break; | |
252b5132 | 13671 | |
df58fc94 RS |
13672 | imm = ep.X_add_number >> 2; |
13673 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13674 | } | |
13675 | s = expr_end; | |
13676 | continue; | |
4614d845 | 13677 | |
df58fc94 RS |
13678 | case 'U': |
13679 | { | |
13680 | bfd_reloc_code_real_type r[3]; | |
13681 | expressionS ep; | |
13682 | int imm; | |
13683 | ||
13684 | /* Check whether there is only a single bracketed | |
13685 | expression left. If so, it must be the base register | |
13686 | and the constant must be zero. */ | |
13687 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13688 | { | |
13689 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13690 | continue; | |
13691 | } | |
13692 | ||
13693 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13694 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13695 | break; | |
13696 | ||
13697 | imm = ep.X_add_number >> 2; | |
13698 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13699 | } | |
13700 | s = expr_end; | |
5e0116d5 | 13701 | continue; |
252b5132 | 13702 | |
df58fc94 RS |
13703 | case 'W': |
13704 | { | |
13705 | bfd_reloc_code_real_type r[3]; | |
13706 | expressionS ep; | |
13707 | int imm; | |
252b5132 | 13708 | |
df58fc94 RS |
13709 | if (my_getSmallExpression (&ep, r, s) > 0 |
13710 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13711 | break; | |
252b5132 | 13712 | |
df58fc94 RS |
13713 | imm = ep.X_add_number >> 2; |
13714 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13715 | } | |
13716 | s = expr_end; | |
13717 | continue; | |
252b5132 | 13718 | |
df58fc94 RS |
13719 | case 'X': |
13720 | { | |
13721 | bfd_reloc_code_real_type r[3]; | |
13722 | expressionS ep; | |
13723 | int imm; | |
252b5132 | 13724 | |
df58fc94 RS |
13725 | if (my_getSmallExpression (&ep, r, s) > 0 |
13726 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13727 | break; | |
252b5132 | 13728 | |
df58fc94 RS |
13729 | imm = ep.X_add_number; |
13730 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13731 | } | |
13732 | s = expr_end; | |
13733 | continue; | |
252b5132 | 13734 | |
df58fc94 RS |
13735 | case 'Y': |
13736 | { | |
13737 | bfd_reloc_code_real_type r[3]; | |
13738 | expressionS ep; | |
13739 | int imm; | |
156c2f8b | 13740 | |
df58fc94 RS |
13741 | if (my_getSmallExpression (&ep, r, s) > 0 |
13742 | || expr_const_in_range (&ep, -2, 2, 2) | |
13743 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13744 | break; | |
156c2f8b | 13745 | |
df58fc94 RS |
13746 | imm = ep.X_add_number >> 2; |
13747 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13748 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13749 | } | |
13750 | s = expr_end; | |
13751 | continue; | |
60b63b72 | 13752 | |
df58fc94 RS |
13753 | case 'Z': |
13754 | { | |
13755 | bfd_reloc_code_real_type r[3]; | |
13756 | expressionS ep; | |
13757 | ||
13758 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13759 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13760 | break; | |
13761 | } | |
13762 | s = expr_end; | |
13763 | continue; | |
13764 | ||
13765 | default: | |
13766 | as_bad (_("Internal error: bad microMIPS opcode " | |
13767 | "(unknown extension operand type `m%c'): %s %s"), | |
13768 | *args, insn->name, insn->args); | |
13769 | /* Further processing is fruitless. */ | |
13770 | return; | |
60b63b72 | 13771 | } |
df58fc94 | 13772 | break; |
60b63b72 | 13773 | |
df58fc94 RS |
13774 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13775 | gas_assert (mips_opts.micromips); | |
13776 | { | |
13777 | /* A comma-separated list of registers and/or | |
13778 | dash-separated contiguous ranges including | |
13779 | at least one of ra and a set of one or more | |
13780 | registers starting at s0 up to s7 and then | |
13781 | s8 which have to be consecutive, e.g.: | |
13782 | ||
13783 | ra | |
13784 | s0 | |
13785 | ra, s0, s1, s2 | |
13786 | s0-s8 | |
13787 | s0-s5, ra | |
13788 | ||
13789 | and any permutations of these. */ | |
13790 | unsigned int reglist; | |
13791 | int imm; | |
13792 | int ra; | |
13793 | ||
13794 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13795 | break; | |
13796 | ||
13797 | if ((reglist & 0x3f00ffff) != 0) | |
13798 | break; | |
13799 | ||
13800 | ra = (reglist >> 27) & 0x10; | |
13801 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13802 | reglist += 1; | |
13803 | if ((reglist & -reglist) != reglist) | |
13804 | break; | |
13805 | ||
13806 | imm = (ffs (reglist) - 1) | ra; | |
13807 | INSERT_OPERAND (1, RT, *ip, imm); | |
13808 | imm_expr.X_op = O_absent; | |
13809 | } | |
60b63b72 RS |
13810 | continue; |
13811 | ||
df58fc94 RS |
13812 | case '|': /* 4-bit trap code. */ |
13813 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13814 | my_getExpression (&imm_expr, s); |
13815 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13816 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13817 | > MICROMIPSOP_MASK_TRAP) |
13818 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13819 | (unsigned long) imm_expr.X_add_number, | |
13820 | ip->insn_mo->name); | |
13821 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13822 | imm_expr.X_op = O_absent; |
13823 | s = expr_end; | |
13824 | continue; | |
13825 | ||
252b5132 | 13826 | default: |
f71d0d44 | 13827 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13828 | abort (); |
252b5132 RH |
13829 | } |
13830 | break; | |
13831 | } | |
13832 | /* Args don't match. */ | |
df58fc94 RS |
13833 | s = argsStart; |
13834 | insn_error = _("Illegal operands"); | |
13835 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13836 | { |
13837 | ++insn; | |
252b5132 RH |
13838 | continue; |
13839 | } | |
df58fc94 RS |
13840 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13841 | { | |
13842 | gas_assert (firstinsn); | |
13843 | need_delay_slot_ok = FALSE; | |
13844 | past = insn + 1; | |
13845 | insn = firstinsn; | |
13846 | continue; | |
13847 | } | |
252b5132 RH |
13848 | return; |
13849 | } | |
13850 | } | |
13851 | ||
0499d65b TS |
13852 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13853 | ||
252b5132 RH |
13854 | /* This routine assembles an instruction into its binary format when |
13855 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13856 | global variables imm_reloc or offset_reloc to the type of relocation |
13857 | to do if one of the operands is an address expression. It also sets | |
13858 | forced_insn_length to the resulting instruction size in bytes if the | |
13859 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13860 | |
13861 | static void | |
17a2f251 | 13862 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13863 | { |
13864 | char *s; | |
13865 | const char *args; | |
13866 | struct mips_opcode *insn; | |
13867 | char *argsstart; | |
13868 | unsigned int regno; | |
13869 | unsigned int lastregno = 0; | |
13870 | char *s_reset; | |
d6f16593 | 13871 | size_t i; |
252b5132 RH |
13872 | |
13873 | insn_error = NULL; | |
13874 | ||
df58fc94 | 13875 | forced_insn_length = 0; |
252b5132 | 13876 | |
3882b010 | 13877 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13878 | ; |
13879 | switch (*s) | |
13880 | { | |
13881 | case '\0': | |
13882 | break; | |
13883 | ||
13884 | case ' ': | |
13885 | *s++ = '\0'; | |
13886 | break; | |
13887 | ||
13888 | case '.': | |
13889 | if (s[1] == 't' && s[2] == ' ') | |
13890 | { | |
13891 | *s = '\0'; | |
df58fc94 | 13892 | forced_insn_length = 2; |
252b5132 RH |
13893 | s += 3; |
13894 | break; | |
13895 | } | |
13896 | else if (s[1] == 'e' && s[2] == ' ') | |
13897 | { | |
13898 | *s = '\0'; | |
df58fc94 | 13899 | forced_insn_length = 4; |
252b5132 RH |
13900 | s += 3; |
13901 | break; | |
13902 | } | |
13903 | /* Fall through. */ | |
13904 | default: | |
13905 | insn_error = _("unknown opcode"); | |
13906 | return; | |
13907 | } | |
13908 | ||
df58fc94 RS |
13909 | if (mips_opts.noautoextend && !forced_insn_length) |
13910 | forced_insn_length = 2; | |
252b5132 RH |
13911 | |
13912 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13913 | { | |
13914 | insn_error = _("unrecognized opcode"); | |
13915 | return; | |
13916 | } | |
13917 | ||
13918 | argsstart = s; | |
13919 | for (;;) | |
13920 | { | |
9b3f89ee TS |
13921 | bfd_boolean ok; |
13922 | ||
9c2799c2 | 13923 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13924 | |
037b32b9 | 13925 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13926 | if (! ok) |
13927 | { | |
13928 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13929 | && strcmp (insn->name, insn[1].name) == 0) | |
13930 | { | |
13931 | ++insn; | |
13932 | continue; | |
13933 | } | |
13934 | else | |
13935 | { | |
13936 | if (!insn_error) | |
13937 | { | |
13938 | static char buf[100]; | |
13939 | sprintf (buf, | |
7bd942df | 13940 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13941 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13942 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13943 | insn_error = buf; | |
13944 | } | |
13945 | return; | |
13946 | } | |
13947 | } | |
13948 | ||
1e915849 | 13949 | create_insn (ip, insn); |
252b5132 | 13950 | imm_expr.X_op = O_absent; |
f6688943 TS |
13951 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13952 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13953 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13954 | imm2_expr.X_op = O_absent; |
252b5132 | 13955 | offset_expr.X_op = O_absent; |
f6688943 TS |
13956 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13957 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13958 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13959 | for (args = insn->args; 1; ++args) |
13960 | { | |
13961 | int c; | |
13962 | ||
13963 | if (*s == ' ') | |
13964 | ++s; | |
13965 | ||
13966 | /* In this switch statement we call break if we did not find | |
13967 | a match, continue if we did find a match, or return if we | |
13968 | are done. */ | |
13969 | ||
13970 | c = *args; | |
13971 | switch (c) | |
13972 | { | |
13973 | case '\0': | |
13974 | if (*s == '\0') | |
13975 | { | |
b886a2ab RS |
13976 | offsetT value; |
13977 | ||
252b5132 RH |
13978 | /* Stuff the immediate value in now, if we can. */ |
13979 | if (imm_expr.X_op == O_constant | |
f6688943 | 13980 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13981 | && insn->pinfo != INSN_MACRO |
13982 | && calculate_reloc (*offset_reloc, | |
13983 | imm_expr.X_add_number, &value)) | |
252b5132 | 13984 | { |
c4e7957c | 13985 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13986 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13987 | &ip->insn_opcode); |
252b5132 | 13988 | imm_expr.X_op = O_absent; |
f6688943 | 13989 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13990 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13991 | } |
13992 | ||
13993 | return; | |
13994 | } | |
13995 | break; | |
13996 | ||
13997 | case ',': | |
13998 | if (*s++ == c) | |
13999 | continue; | |
14000 | s--; | |
14001 | switch (*++args) | |
14002 | { | |
14003 | case 'v': | |
bf12938e | 14004 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
14005 | continue; |
14006 | case 'w': | |
bf12938e | 14007 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
14008 | continue; |
14009 | } | |
14010 | break; | |
14011 | ||
14012 | case '(': | |
14013 | case ')': | |
14014 | if (*s++ == c) | |
14015 | continue; | |
14016 | break; | |
14017 | ||
14018 | case 'v': | |
14019 | case 'w': | |
14020 | if (s[0] != '$') | |
14021 | { | |
14022 | if (c == 'v') | |
bf12938e | 14023 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 14024 | else |
bf12938e | 14025 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
14026 | ++args; |
14027 | continue; | |
14028 | } | |
14029 | /* Fall through. */ | |
14030 | case 'x': | |
14031 | case 'y': | |
14032 | case 'z': | |
14033 | case 'Z': | |
14034 | case '0': | |
14035 | case 'S': | |
14036 | case 'R': | |
14037 | case 'X': | |
14038 | case 'Y': | |
707bfff6 TS |
14039 | s_reset = s; |
14040 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 14041 | { |
707bfff6 | 14042 | if (c == 'v' || c == 'w') |
85b51719 | 14043 | { |
707bfff6 | 14044 | if (c == 'v') |
a9e24354 | 14045 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 14046 | else |
a9e24354 | 14047 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
14048 | ++args; |
14049 | continue; | |
85b51719 | 14050 | } |
707bfff6 | 14051 | break; |
252b5132 RH |
14052 | } |
14053 | ||
14054 | if (*s == ' ') | |
14055 | ++s; | |
14056 | if (args[1] != *s) | |
14057 | { | |
14058 | if (c == 'v' || c == 'w') | |
14059 | { | |
14060 | regno = mips16_to_32_reg_map[lastregno]; | |
14061 | s = s_reset; | |
f9419b05 | 14062 | ++args; |
252b5132 RH |
14063 | } |
14064 | } | |
14065 | ||
14066 | switch (c) | |
14067 | { | |
14068 | case 'x': | |
14069 | case 'y': | |
14070 | case 'z': | |
14071 | case 'v': | |
14072 | case 'w': | |
14073 | case 'Z': | |
14074 | regno = mips32_to_16_reg_map[regno]; | |
14075 | break; | |
14076 | ||
14077 | case '0': | |
14078 | if (regno != 0) | |
14079 | regno = ILLEGAL_REG; | |
14080 | break; | |
14081 | ||
14082 | case 'S': | |
14083 | if (regno != SP) | |
14084 | regno = ILLEGAL_REG; | |
14085 | break; | |
14086 | ||
14087 | case 'R': | |
14088 | if (regno != RA) | |
14089 | regno = ILLEGAL_REG; | |
14090 | break; | |
14091 | ||
14092 | case 'X': | |
14093 | case 'Y': | |
741fe287 MR |
14094 | if (regno == AT && mips_opts.at) |
14095 | { | |
14096 | if (mips_opts.at == ATREG) | |
14097 | as_warn (_("used $at without \".set noat\"")); | |
14098 | else | |
14099 | as_warn (_("used $%u with \".set at=$%u\""), | |
14100 | regno, mips_opts.at); | |
14101 | } | |
252b5132 RH |
14102 | break; |
14103 | ||
14104 | default: | |
b37df7c4 | 14105 | abort (); |
252b5132 RH |
14106 | } |
14107 | ||
14108 | if (regno == ILLEGAL_REG) | |
14109 | break; | |
14110 | ||
14111 | switch (c) | |
14112 | { | |
14113 | case 'x': | |
14114 | case 'v': | |
bf12938e | 14115 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
14116 | break; |
14117 | case 'y': | |
14118 | case 'w': | |
bf12938e | 14119 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
14120 | break; |
14121 | case 'z': | |
bf12938e | 14122 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
14123 | break; |
14124 | case 'Z': | |
bf12938e | 14125 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
14126 | case '0': |
14127 | case 'S': | |
14128 | case 'R': | |
14129 | break; | |
14130 | case 'X': | |
bf12938e | 14131 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
14132 | break; |
14133 | case 'Y': | |
14134 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 14135 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
14136 | break; |
14137 | default: | |
b37df7c4 | 14138 | abort (); |
252b5132 RH |
14139 | } |
14140 | ||
14141 | lastregno = regno; | |
14142 | continue; | |
14143 | ||
14144 | case 'P': | |
14145 | if (strncmp (s, "$pc", 3) == 0) | |
14146 | { | |
14147 | s += 3; | |
14148 | continue; | |
14149 | } | |
14150 | break; | |
14151 | ||
252b5132 RH |
14152 | case '5': |
14153 | case 'H': | |
14154 | case 'W': | |
14155 | case 'D': | |
14156 | case 'j': | |
252b5132 RH |
14157 | case 'V': |
14158 | case 'C': | |
14159 | case 'U': | |
14160 | case 'k': | |
14161 | case 'K': | |
d6f16593 MR |
14162 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
14163 | if (i > 0) | |
252b5132 | 14164 | { |
d6f16593 | 14165 | if (imm_expr.X_op != O_constant) |
252b5132 | 14166 | { |
df58fc94 | 14167 | forced_insn_length = 4; |
5c04167a | 14168 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 14169 | } |
d6f16593 MR |
14170 | else |
14171 | { | |
14172 | /* We need to relax this instruction. */ | |
14173 | *offset_reloc = *imm_reloc; | |
14174 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
14175 | } | |
14176 | s = expr_end; | |
14177 | continue; | |
252b5132 | 14178 | } |
d6f16593 MR |
14179 | *imm_reloc = BFD_RELOC_UNUSED; |
14180 | /* Fall through. */ | |
14181 | case '<': | |
14182 | case '>': | |
14183 | case '[': | |
14184 | case ']': | |
14185 | case '4': | |
14186 | case '8': | |
14187 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
14188 | if (imm_expr.X_op == O_register) |
14189 | { | |
14190 | /* What we thought was an expression turned out to | |
14191 | be a register. */ | |
14192 | ||
14193 | if (s[0] == '(' && args[1] == '(') | |
14194 | { | |
14195 | /* It looks like the expression was omitted | |
14196 | before a register indirection, which means | |
14197 | that the expression is implicitly zero. We | |
14198 | still set up imm_expr, so that we handle | |
14199 | explicit extensions correctly. */ | |
14200 | imm_expr.X_op = O_constant; | |
14201 | imm_expr.X_add_number = 0; | |
f6688943 | 14202 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14203 | continue; |
14204 | } | |
14205 | ||
14206 | break; | |
14207 | } | |
14208 | ||
14209 | /* We need to relax this instruction. */ | |
f6688943 | 14210 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14211 | s = expr_end; |
14212 | continue; | |
14213 | ||
14214 | case 'p': | |
14215 | case 'q': | |
14216 | case 'A': | |
14217 | case 'B': | |
14218 | case 'E': | |
14219 | /* We use offset_reloc rather than imm_reloc for the PC | |
14220 | relative operands. This lets macros with both | |
14221 | immediate and address operands work correctly. */ | |
14222 | my_getExpression (&offset_expr, s); | |
14223 | ||
14224 | if (offset_expr.X_op == O_register) | |
14225 | break; | |
14226 | ||
14227 | /* We need to relax this instruction. */ | |
f6688943 | 14228 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14229 | s = expr_end; |
14230 | continue; | |
14231 | ||
14232 | case '6': /* break code */ | |
14233 | my_getExpression (&imm_expr, s); | |
14234 | check_absolute_expr (ip, &imm_expr); | |
14235 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14236 | as_warn (_("Invalid value for `%s' (%lu)"), |
14237 | ip->insn_mo->name, | |
14238 | (unsigned long) imm_expr.X_add_number); | |
14239 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14240 | imm_expr.X_op = O_absent; |
14241 | s = expr_end; | |
14242 | continue; | |
14243 | ||
14244 | case 'a': /* 26 bit address */ | |
14245 | my_getExpression (&offset_expr, s); | |
14246 | s = expr_end; | |
f6688943 | 14247 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14248 | ip->insn_opcode <<= 16; |
14249 | continue; | |
14250 | ||
14251 | case 'l': /* register list for entry macro */ | |
14252 | case 'L': /* register list for exit macro */ | |
14253 | { | |
14254 | int mask; | |
14255 | ||
14256 | if (c == 'l') | |
14257 | mask = 0; | |
14258 | else | |
14259 | mask = 7 << 3; | |
14260 | while (*s != '\0') | |
14261 | { | |
707bfff6 | 14262 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14263 | |
14264 | while (*s == ' ' || *s == ',') | |
14265 | ++s; | |
707bfff6 | 14266 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14267 | freg = 0; |
707bfff6 TS |
14268 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14269 | freg = 1; | |
252b5132 RH |
14270 | else |
14271 | { | |
707bfff6 TS |
14272 | as_bad (_("can't parse register list")); |
14273 | break; | |
252b5132 RH |
14274 | } |
14275 | if (*s == ' ') | |
14276 | ++s; | |
14277 | if (*s != '-') | |
14278 | reg2 = reg1; | |
14279 | else | |
14280 | { | |
14281 | ++s; | |
707bfff6 TS |
14282 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14283 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14284 | { |
707bfff6 TS |
14285 | as_bad (_("invalid register list")); |
14286 | break; | |
252b5132 RH |
14287 | } |
14288 | } | |
14289 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14290 | { | |
14291 | mask &= ~ (7 << 3); | |
14292 | mask |= 5 << 3; | |
14293 | } | |
14294 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14295 | { | |
14296 | mask &= ~ (7 << 3); | |
14297 | mask |= 6 << 3; | |
14298 | } | |
14299 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14300 | mask |= (reg2 - 3) << 3; | |
14301 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14302 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14303 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14304 | mask |= 1; |
14305 | else | |
14306 | { | |
14307 | as_bad (_("invalid register list")); | |
14308 | break; | |
14309 | } | |
14310 | } | |
14311 | /* The mask is filled in in the opcode table for the | |
14312 | benefit of the disassembler. We remove it before | |
14313 | applying the actual mask. */ | |
14314 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14315 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14316 | } | |
14317 | continue; | |
14318 | ||
0499d65b TS |
14319 | case 'm': /* Register list for save insn. */ |
14320 | case 'M': /* Register list for restore insn. */ | |
14321 | { | |
5c04167a | 14322 | int opcode = ip->insn_opcode; |
0499d65b | 14323 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14324 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14325 | |
14326 | while (*s != '\0') | |
14327 | { | |
14328 | unsigned int reg1, reg2; | |
14329 | ||
14330 | SKIP_SPACE_TABS (s); | |
14331 | while (*s == ',') | |
14332 | ++s; | |
14333 | SKIP_SPACE_TABS (s); | |
14334 | ||
14335 | my_getExpression (&imm_expr, s); | |
14336 | if (imm_expr.X_op == O_constant) | |
14337 | { | |
14338 | /* Handle the frame size. */ | |
14339 | if (seen_framesz) | |
14340 | { | |
14341 | as_bad (_("more than one frame size in list")); | |
14342 | break; | |
14343 | } | |
14344 | seen_framesz = 1; | |
14345 | framesz = imm_expr.X_add_number; | |
14346 | imm_expr.X_op = O_absent; | |
14347 | s = expr_end; | |
14348 | continue; | |
14349 | } | |
14350 | ||
707bfff6 | 14351 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14352 | { |
14353 | as_bad (_("can't parse register list")); | |
14354 | break; | |
14355 | } | |
0499d65b | 14356 | |
707bfff6 TS |
14357 | while (*s == ' ') |
14358 | ++s; | |
14359 | ||
0499d65b TS |
14360 | if (*s != '-') |
14361 | reg2 = reg1; | |
14362 | else | |
14363 | { | |
14364 | ++s; | |
707bfff6 TS |
14365 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14366 | || reg2 < reg1) | |
0499d65b TS |
14367 | { |
14368 | as_bad (_("can't parse register list")); | |
14369 | break; | |
14370 | } | |
0499d65b TS |
14371 | } |
14372 | ||
14373 | while (reg1 <= reg2) | |
14374 | { | |
14375 | if (reg1 >= 4 && reg1 <= 7) | |
14376 | { | |
3a93f742 | 14377 | if (!seen_framesz) |
0499d65b | 14378 | /* args $a0-$a3 */ |
91d6fa6a | 14379 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14380 | else |
14381 | /* statics $a0-$a3 */ | |
14382 | statics |= 1 << (reg1 - 4); | |
14383 | } | |
14384 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14385 | { | |
14386 | /* $s0-$s8 */ | |
14387 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14388 | } | |
14389 | else if (reg1 == 31) | |
14390 | { | |
14391 | /* Add $ra to insn. */ | |
14392 | opcode |= 0x40; | |
14393 | } | |
14394 | else | |
14395 | { | |
14396 | as_bad (_("unexpected register in list")); | |
14397 | break; | |
14398 | } | |
14399 | if (++reg1 == 24) | |
14400 | reg1 = 30; | |
14401 | } | |
14402 | } | |
14403 | ||
14404 | /* Encode args/statics combination. */ | |
91d6fa6a | 14405 | if (nargs & statics) |
0499d65b | 14406 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14407 | else if (nargs == 0xf) |
0499d65b TS |
14408 | /* All $a0-$a3 are args. */ |
14409 | opcode |= MIPS16_ALL_ARGS << 16; | |
14410 | else if (statics == 0xf) | |
14411 | /* All $a0-$a3 are statics. */ | |
14412 | opcode |= MIPS16_ALL_STATICS << 16; | |
14413 | else | |
14414 | { | |
14415 | int narg = 0, nstat = 0; | |
14416 | ||
14417 | /* Count arg registers. */ | |
91d6fa6a | 14418 | while (nargs & 0x1) |
0499d65b | 14419 | { |
91d6fa6a | 14420 | nargs >>= 1; |
0499d65b TS |
14421 | narg++; |
14422 | } | |
91d6fa6a | 14423 | if (nargs != 0) |
0499d65b TS |
14424 | as_bad (_("invalid arg register list")); |
14425 | ||
14426 | /* Count static registers. */ | |
14427 | while (statics & 0x8) | |
14428 | { | |
14429 | statics = (statics << 1) & 0xf; | |
14430 | nstat++; | |
14431 | } | |
14432 | if (statics != 0) | |
14433 | as_bad (_("invalid static register list")); | |
14434 | ||
14435 | /* Encode args/statics. */ | |
14436 | opcode |= ((narg << 2) | nstat) << 16; | |
14437 | } | |
14438 | ||
14439 | /* Encode $s0/$s1. */ | |
14440 | if (sregs & (1 << 0)) /* $s0 */ | |
14441 | opcode |= 0x20; | |
14442 | if (sregs & (1 << 1)) /* $s1 */ | |
14443 | opcode |= 0x10; | |
14444 | sregs >>= 2; | |
14445 | ||
14446 | if (sregs != 0) | |
14447 | { | |
14448 | /* Count regs $s2-$s8. */ | |
14449 | int nsreg = 0; | |
14450 | while (sregs & 1) | |
14451 | { | |
14452 | sregs >>= 1; | |
14453 | nsreg++; | |
14454 | } | |
14455 | if (sregs != 0) | |
14456 | as_bad (_("invalid static register list")); | |
14457 | /* Encode $s2-$s8. */ | |
14458 | opcode |= nsreg << 24; | |
14459 | } | |
14460 | ||
14461 | /* Encode frame size. */ | |
14462 | if (!seen_framesz) | |
14463 | as_bad (_("missing frame size")); | |
14464 | else if ((framesz & 7) != 0 || framesz < 0 | |
14465 | || framesz > 0xff * 8) | |
14466 | as_bad (_("invalid frame size")); | |
14467 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14468 | { | |
14469 | framesz /= 8; | |
14470 | opcode |= (((framesz & 0xf0) << 16) | |
14471 | | (framesz & 0x0f)); | |
14472 | } | |
14473 | ||
14474 | /* Finally build the instruction. */ | |
14475 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14476 | opcode |= MIPS16_EXTEND; |
14477 | ip->insn_opcode = opcode; | |
0499d65b TS |
14478 | } |
14479 | continue; | |
14480 | ||
252b5132 RH |
14481 | case 'e': /* extend code */ |
14482 | my_getExpression (&imm_expr, s); | |
14483 | check_absolute_expr (ip, &imm_expr); | |
14484 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14485 | { | |
14486 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14487 | ip->insn_mo->name, | |
14488 | (unsigned long) imm_expr.X_add_number); | |
14489 | imm_expr.X_add_number &= 0x7ff; | |
14490 | } | |
14491 | ip->insn_opcode |= imm_expr.X_add_number; | |
14492 | imm_expr.X_op = O_absent; | |
14493 | s = expr_end; | |
14494 | continue; | |
14495 | ||
14496 | default: | |
b37df7c4 | 14497 | abort (); |
252b5132 RH |
14498 | } |
14499 | break; | |
14500 | } | |
14501 | ||
14502 | /* Args don't match. */ | |
14503 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14504 | strcmp (insn->name, insn[1].name) == 0) | |
14505 | { | |
14506 | ++insn; | |
14507 | s = argsstart; | |
14508 | continue; | |
14509 | } | |
14510 | ||
14511 | insn_error = _("illegal operands"); | |
14512 | ||
14513 | return; | |
14514 | } | |
14515 | } | |
14516 | ||
14517 | /* This structure holds information we know about a mips16 immediate | |
14518 | argument type. */ | |
14519 | ||
e972090a NC |
14520 | struct mips16_immed_operand |
14521 | { | |
252b5132 RH |
14522 | /* The type code used in the argument string in the opcode table. */ |
14523 | int type; | |
14524 | /* The number of bits in the short form of the opcode. */ | |
14525 | int nbits; | |
14526 | /* The number of bits in the extended form of the opcode. */ | |
14527 | int extbits; | |
14528 | /* The amount by which the short form is shifted when it is used; | |
14529 | for example, the sw instruction has a shift count of 2. */ | |
14530 | int shift; | |
14531 | /* The amount by which the short form is shifted when it is stored | |
14532 | into the instruction code. */ | |
14533 | int op_shift; | |
14534 | /* Non-zero if the short form is unsigned. */ | |
14535 | int unsp; | |
14536 | /* Non-zero if the extended form is unsigned. */ | |
14537 | int extu; | |
14538 | /* Non-zero if the value is PC relative. */ | |
14539 | int pcrel; | |
14540 | }; | |
14541 | ||
14542 | /* The mips16 immediate operand types. */ | |
14543 | ||
14544 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14545 | { | |
14546 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14547 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14548 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14549 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14550 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14551 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14552 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14553 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14554 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14555 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14556 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14557 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14558 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14559 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14560 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14561 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14562 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14563 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14564 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14565 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14566 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14567 | }; | |
14568 | ||
14569 | #define MIPS16_NUM_IMMED \ | |
14570 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14571 | ||
b886a2ab RS |
14572 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14573 | NBITS is the number of significant bits in VAL. */ | |
14574 | ||
14575 | static unsigned long | |
14576 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14577 | { | |
14578 | int extval; | |
14579 | if (nbits == 16) | |
14580 | { | |
14581 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14582 | val &= 0x1f; | |
14583 | } | |
14584 | else if (nbits == 15) | |
14585 | { | |
14586 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14587 | val &= 0xf; | |
14588 | } | |
14589 | else | |
14590 | { | |
14591 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14592 | val = 0; | |
14593 | } | |
14594 | return (extval << 16) | val; | |
14595 | } | |
14596 | ||
5c04167a RS |
14597 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14598 | extending it if necessary. The instruction in *INSN may | |
14599 | already be extended. | |
14600 | ||
43c0598f RS |
14601 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14602 | if none. In the former case, VAL is a 16-bit number with no | |
14603 | defined signedness. | |
14604 | ||
14605 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14606 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14607 | |
14608 | static void | |
43c0598f RS |
14609 | mips16_immed (char *file, unsigned int line, int type, |
14610 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14611 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14612 | { |
3994f87e | 14613 | const struct mips16_immed_operand *op; |
252b5132 | 14614 | int mintiny, maxtiny; |
252b5132 RH |
14615 | |
14616 | op = mips16_immed_operands; | |
14617 | while (op->type != type) | |
14618 | { | |
14619 | ++op; | |
9c2799c2 | 14620 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14621 | } |
14622 | ||
14623 | if (op->unsp) | |
14624 | { | |
14625 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14626 | { | |
14627 | mintiny = 1; | |
14628 | maxtiny = 1 << op->nbits; | |
14629 | } | |
14630 | else | |
14631 | { | |
14632 | mintiny = 0; | |
14633 | maxtiny = (1 << op->nbits) - 1; | |
14634 | } | |
43c0598f RS |
14635 | if (reloc != BFD_RELOC_UNUSED) |
14636 | val &= 0xffff; | |
252b5132 RH |
14637 | } |
14638 | else | |
14639 | { | |
14640 | mintiny = - (1 << (op->nbits - 1)); | |
14641 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14642 | if (reloc != BFD_RELOC_UNUSED) |
14643 | val = SEXT_16BIT (val); | |
252b5132 RH |
14644 | } |
14645 | ||
14646 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14647 | if (type == 'p' || type == 'q') | |
14648 | val /= 2; | |
14649 | ||
14650 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14651 | || val < (mintiny << op->shift) | |
14652 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14653 | { |
14654 | /* We need an extended instruction. */ | |
14655 | if (user_insn_length == 2) | |
14656 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14657 | else | |
14658 | *insn |= MIPS16_EXTEND; | |
14659 | } | |
14660 | else if (user_insn_length == 4) | |
14661 | { | |
14662 | /* The operand doesn't force an unextended instruction to be extended. | |
14663 | Warn if the user wanted an extended instruction anyway. */ | |
14664 | *insn |= MIPS16_EXTEND; | |
14665 | as_warn_where (file, line, | |
14666 | _("extended operand requested but not required")); | |
14667 | } | |
252b5132 | 14668 | |
5c04167a | 14669 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14670 | { |
14671 | int insnval; | |
14672 | ||
252b5132 RH |
14673 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14674 | insnval <<= op->op_shift; | |
14675 | *insn |= insnval; | |
14676 | } | |
14677 | else | |
14678 | { | |
14679 | long minext, maxext; | |
252b5132 | 14680 | |
43c0598f | 14681 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14682 | { |
43c0598f RS |
14683 | if (op->extu) |
14684 | { | |
14685 | minext = 0; | |
14686 | maxext = (1 << op->extbits) - 1; | |
14687 | } | |
14688 | else | |
14689 | { | |
14690 | minext = - (1 << (op->extbits - 1)); | |
14691 | maxext = (1 << (op->extbits - 1)) - 1; | |
14692 | } | |
14693 | if (val < minext || val > maxext) | |
14694 | as_bad_where (file, line, | |
14695 | _("operand value out of range for instruction")); | |
252b5132 | 14696 | } |
252b5132 | 14697 | |
b886a2ab | 14698 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14699 | } |
14700 | } | |
14701 | \f | |
d6f16593 | 14702 | struct percent_op_match |
ad8d3bb3 | 14703 | { |
5e0116d5 RS |
14704 | const char *str; |
14705 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14706 | }; |
14707 | ||
14708 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14709 | { |
5e0116d5 | 14710 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14711 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14712 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14713 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14714 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14715 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14716 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14717 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14718 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14719 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14720 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14721 | {"%half", BFD_RELOC_16}, | |
14722 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14723 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14724 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14725 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14726 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14727 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14728 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14729 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14730 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14731 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
5e0116d5 | 14732 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14733 | }; |
14734 | ||
d6f16593 MR |
14735 | static const struct percent_op_match mips16_percent_op[] = |
14736 | { | |
14737 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14738 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14739 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14740 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14741 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14742 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14743 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14744 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14745 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14746 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14747 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14748 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14749 | }; |
14750 | ||
252b5132 | 14751 | |
5e0116d5 RS |
14752 | /* Return true if *STR points to a relocation operator. When returning true, |
14753 | move *STR over the operator and store its relocation code in *RELOC. | |
14754 | Leave both *STR and *RELOC alone when returning false. */ | |
14755 | ||
14756 | static bfd_boolean | |
17a2f251 | 14757 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14758 | { |
d6f16593 MR |
14759 | const struct percent_op_match *percent_op; |
14760 | size_t limit, i; | |
14761 | ||
14762 | if (mips_opts.mips16) | |
14763 | { | |
14764 | percent_op = mips16_percent_op; | |
14765 | limit = ARRAY_SIZE (mips16_percent_op); | |
14766 | } | |
14767 | else | |
14768 | { | |
14769 | percent_op = mips_percent_op; | |
14770 | limit = ARRAY_SIZE (mips_percent_op); | |
14771 | } | |
76b3015f | 14772 | |
d6f16593 | 14773 | for (i = 0; i < limit; i++) |
5e0116d5 | 14774 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14775 | { |
3f98094e DJ |
14776 | int len = strlen (percent_op[i].str); |
14777 | ||
14778 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14779 | continue; | |
14780 | ||
5e0116d5 RS |
14781 | *str += strlen (percent_op[i].str); |
14782 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14783 | |
5e0116d5 RS |
14784 | /* Check whether the output BFD supports this relocation. |
14785 | If not, issue an error and fall back on something safe. */ | |
14786 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14787 | { |
20203fb9 | 14788 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14789 | percent_op[i].str); |
01a3f561 | 14790 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14791 | } |
5e0116d5 | 14792 | return TRUE; |
394f9b3a | 14793 | } |
5e0116d5 | 14794 | return FALSE; |
394f9b3a | 14795 | } |
ad8d3bb3 | 14796 | |
ad8d3bb3 | 14797 | |
5e0116d5 RS |
14798 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14799 | expression in *EP and the relocations in the array starting | |
14800 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14801 | |
01a3f561 | 14802 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14803 | |
5e0116d5 | 14804 | static size_t |
17a2f251 TS |
14805 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14806 | char *str) | |
ad8d3bb3 | 14807 | { |
5e0116d5 RS |
14808 | bfd_reloc_code_real_type reversed_reloc[3]; |
14809 | size_t reloc_index, i; | |
09b8f35a RS |
14810 | int crux_depth, str_depth; |
14811 | char *crux; | |
5e0116d5 RS |
14812 | |
14813 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14814 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14815 | of the main expression and with CRUX_DEPTH containing the number | |
14816 | of open brackets at that point. */ | |
14817 | reloc_index = -1; | |
14818 | str_depth = 0; | |
14819 | do | |
fb1b3232 | 14820 | { |
09b8f35a RS |
14821 | reloc_index++; |
14822 | crux = str; | |
14823 | crux_depth = str_depth; | |
14824 | ||
14825 | /* Skip over whitespace and brackets, keeping count of the number | |
14826 | of brackets. */ | |
14827 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14828 | if (*str++ == '(') | |
14829 | str_depth++; | |
5e0116d5 | 14830 | } |
09b8f35a RS |
14831 | while (*str == '%' |
14832 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14833 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14834 | |
09b8f35a | 14835 | my_getExpression (ep, crux); |
5e0116d5 | 14836 | str = expr_end; |
394f9b3a | 14837 | |
5e0116d5 | 14838 | /* Match every open bracket. */ |
09b8f35a | 14839 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14840 | if (*str++ == ')') |
09b8f35a | 14841 | crux_depth--; |
394f9b3a | 14842 | |
09b8f35a | 14843 | if (crux_depth > 0) |
20203fb9 | 14844 | as_bad (_("unclosed '('")); |
394f9b3a | 14845 | |
5e0116d5 | 14846 | expr_end = str; |
252b5132 | 14847 | |
01a3f561 | 14848 | if (reloc_index != 0) |
64bdfcaf RS |
14849 | { |
14850 | prev_reloc_op_frag = frag_now; | |
14851 | for (i = 0; i < reloc_index; i++) | |
14852 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14853 | } | |
fb1b3232 | 14854 | |
5e0116d5 | 14855 | return reloc_index; |
252b5132 RH |
14856 | } |
14857 | ||
14858 | static void | |
17a2f251 | 14859 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14860 | { |
14861 | char *save_in; | |
14862 | ||
14863 | save_in = input_line_pointer; | |
14864 | input_line_pointer = str; | |
14865 | expression (ep); | |
14866 | expr_end = input_line_pointer; | |
14867 | input_line_pointer = save_in; | |
252b5132 RH |
14868 | } |
14869 | ||
252b5132 | 14870 | char * |
17a2f251 | 14871 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14872 | { |
499ac353 | 14873 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14874 | } |
14875 | ||
14876 | void | |
17a2f251 | 14877 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14878 | { |
14879 | if (target_big_endian) | |
14880 | number_to_chars_bigendian (buf, val, n); | |
14881 | else | |
14882 | number_to_chars_littleendian (buf, val, n); | |
14883 | } | |
14884 | \f | |
e013f690 TS |
14885 | static int support_64bit_objects(void) |
14886 | { | |
14887 | const char **list, **l; | |
aa3d8fdf | 14888 | int yes; |
e013f690 TS |
14889 | |
14890 | list = bfd_target_list (); | |
14891 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14892 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14893 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14894 | break; |
aa3d8fdf | 14895 | yes = (*l != NULL); |
e013f690 | 14896 | free (list); |
aa3d8fdf | 14897 | return yes; |
e013f690 TS |
14898 | } |
14899 | ||
316f5878 RS |
14900 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14901 | NEW_VALUE. Warn if another value was already specified. Note: | |
14902 | we have to defer parsing the -march and -mtune arguments in order | |
14903 | to handle 'from-abi' correctly, since the ABI might be specified | |
14904 | in a later argument. */ | |
14905 | ||
14906 | static void | |
17a2f251 | 14907 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14908 | { |
14909 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14910 | as_warn (_("A different %s was already specified, is now %s"), | |
14911 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14912 | new_value); | |
14913 | ||
14914 | *string_ptr = new_value; | |
14915 | } | |
14916 | ||
252b5132 | 14917 | int |
17a2f251 | 14918 | md_parse_option (int c, char *arg) |
252b5132 | 14919 | { |
c6278170 RS |
14920 | unsigned int i; |
14921 | ||
14922 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14923 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14924 | { | |
14925 | file_ase_explicit |= mips_set_ase (&mips_ases[i], | |
14926 | c == mips_ases[i].option_on); | |
14927 | return 1; | |
14928 | } | |
14929 | ||
252b5132 RH |
14930 | switch (c) |
14931 | { | |
119d663a NC |
14932 | case OPTION_CONSTRUCT_FLOATS: |
14933 | mips_disable_float_construction = 0; | |
14934 | break; | |
bdaaa2e1 | 14935 | |
119d663a NC |
14936 | case OPTION_NO_CONSTRUCT_FLOATS: |
14937 | mips_disable_float_construction = 1; | |
14938 | break; | |
bdaaa2e1 | 14939 | |
252b5132 RH |
14940 | case OPTION_TRAP: |
14941 | mips_trap = 1; | |
14942 | break; | |
14943 | ||
14944 | case OPTION_BREAK: | |
14945 | mips_trap = 0; | |
14946 | break; | |
14947 | ||
14948 | case OPTION_EB: | |
14949 | target_big_endian = 1; | |
14950 | break; | |
14951 | ||
14952 | case OPTION_EL: | |
14953 | target_big_endian = 0; | |
14954 | break; | |
14955 | ||
14956 | case 'O': | |
4ffff32f TS |
14957 | if (arg == NULL) |
14958 | mips_optimize = 1; | |
14959 | else if (arg[0] == '0') | |
14960 | mips_optimize = 0; | |
14961 | else if (arg[0] == '1') | |
252b5132 RH |
14962 | mips_optimize = 1; |
14963 | else | |
14964 | mips_optimize = 2; | |
14965 | break; | |
14966 | ||
14967 | case 'g': | |
14968 | if (arg == NULL) | |
14969 | mips_debug = 2; | |
14970 | else | |
14971 | mips_debug = atoi (arg); | |
252b5132 RH |
14972 | break; |
14973 | ||
14974 | case OPTION_MIPS1: | |
316f5878 | 14975 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14976 | break; |
14977 | ||
14978 | case OPTION_MIPS2: | |
316f5878 | 14979 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14980 | break; |
14981 | ||
14982 | case OPTION_MIPS3: | |
316f5878 | 14983 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14984 | break; |
14985 | ||
14986 | case OPTION_MIPS4: | |
316f5878 | 14987 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14988 | break; |
14989 | ||
84ea6cf2 | 14990 | case OPTION_MIPS5: |
316f5878 | 14991 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14992 | break; |
14993 | ||
e7af610e | 14994 | case OPTION_MIPS32: |
316f5878 | 14995 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14996 | break; |
14997 | ||
af7ee8bf CD |
14998 | case OPTION_MIPS32R2: |
14999 | file_mips_isa = ISA_MIPS32R2; | |
15000 | break; | |
15001 | ||
5f74bc13 CD |
15002 | case OPTION_MIPS64R2: |
15003 | file_mips_isa = ISA_MIPS64R2; | |
15004 | break; | |
15005 | ||
84ea6cf2 | 15006 | case OPTION_MIPS64: |
316f5878 | 15007 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
15008 | break; |
15009 | ||
ec68c924 | 15010 | case OPTION_MTUNE: |
316f5878 RS |
15011 | mips_set_option_string (&mips_tune_string, arg); |
15012 | break; | |
ec68c924 | 15013 | |
316f5878 RS |
15014 | case OPTION_MARCH: |
15015 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
15016 | break; |
15017 | ||
15018 | case OPTION_M4650: | |
316f5878 RS |
15019 | mips_set_option_string (&mips_arch_string, "4650"); |
15020 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
15021 | break; |
15022 | ||
15023 | case OPTION_NO_M4650: | |
15024 | break; | |
15025 | ||
15026 | case OPTION_M4010: | |
316f5878 RS |
15027 | mips_set_option_string (&mips_arch_string, "4010"); |
15028 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
15029 | break; |
15030 | ||
15031 | case OPTION_NO_M4010: | |
15032 | break; | |
15033 | ||
15034 | case OPTION_M4100: | |
316f5878 RS |
15035 | mips_set_option_string (&mips_arch_string, "4100"); |
15036 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
15037 | break; |
15038 | ||
15039 | case OPTION_NO_M4100: | |
15040 | break; | |
15041 | ||
252b5132 | 15042 | case OPTION_M3900: |
316f5878 RS |
15043 | mips_set_option_string (&mips_arch_string, "3900"); |
15044 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 15045 | break; |
bdaaa2e1 | 15046 | |
252b5132 RH |
15047 | case OPTION_NO_M3900: |
15048 | break; | |
15049 | ||
df58fc94 RS |
15050 | case OPTION_MICROMIPS: |
15051 | if (mips_opts.mips16 == 1) | |
15052 | { | |
15053 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15054 | return 0; | |
15055 | } | |
15056 | mips_opts.micromips = 1; | |
15057 | mips_no_prev_insn (); | |
15058 | break; | |
15059 | ||
15060 | case OPTION_NO_MICROMIPS: | |
15061 | mips_opts.micromips = 0; | |
15062 | mips_no_prev_insn (); | |
15063 | break; | |
15064 | ||
252b5132 | 15065 | case OPTION_MIPS16: |
df58fc94 RS |
15066 | if (mips_opts.micromips == 1) |
15067 | { | |
15068 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15069 | return 0; | |
15070 | } | |
252b5132 | 15071 | mips_opts.mips16 = 1; |
7d10b47d | 15072 | mips_no_prev_insn (); |
252b5132 RH |
15073 | break; |
15074 | ||
15075 | case OPTION_NO_MIPS16: | |
15076 | mips_opts.mips16 = 0; | |
7d10b47d | 15077 | mips_no_prev_insn (); |
252b5132 RH |
15078 | break; |
15079 | ||
6a32d874 CM |
15080 | case OPTION_FIX_24K: |
15081 | mips_fix_24k = 1; | |
15082 | break; | |
15083 | ||
15084 | case OPTION_NO_FIX_24K: | |
15085 | mips_fix_24k = 0; | |
15086 | break; | |
15087 | ||
c67a084a NC |
15088 | case OPTION_FIX_LOONGSON2F_JUMP: |
15089 | mips_fix_loongson2f_jump = TRUE; | |
15090 | break; | |
15091 | ||
15092 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15093 | mips_fix_loongson2f_jump = FALSE; | |
15094 | break; | |
15095 | ||
15096 | case OPTION_FIX_LOONGSON2F_NOP: | |
15097 | mips_fix_loongson2f_nop = TRUE; | |
15098 | break; | |
15099 | ||
15100 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15101 | mips_fix_loongson2f_nop = FALSE; | |
15102 | break; | |
15103 | ||
d766e8ec RS |
15104 | case OPTION_FIX_VR4120: |
15105 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15106 | break; |
15107 | ||
d766e8ec RS |
15108 | case OPTION_NO_FIX_VR4120: |
15109 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15110 | break; |
15111 | ||
7d8e00cf RS |
15112 | case OPTION_FIX_VR4130: |
15113 | mips_fix_vr4130 = 1; | |
15114 | break; | |
15115 | ||
15116 | case OPTION_NO_FIX_VR4130: | |
15117 | mips_fix_vr4130 = 0; | |
15118 | break; | |
15119 | ||
d954098f DD |
15120 | case OPTION_FIX_CN63XXP1: |
15121 | mips_fix_cn63xxp1 = TRUE; | |
15122 | break; | |
15123 | ||
15124 | case OPTION_NO_FIX_CN63XXP1: | |
15125 | mips_fix_cn63xxp1 = FALSE; | |
15126 | break; | |
15127 | ||
4a6a3df4 AO |
15128 | case OPTION_RELAX_BRANCH: |
15129 | mips_relax_branch = 1; | |
15130 | break; | |
15131 | ||
15132 | case OPTION_NO_RELAX_BRANCH: | |
15133 | mips_relax_branch = 0; | |
15134 | break; | |
15135 | ||
aa6975fb ILT |
15136 | case OPTION_MSHARED: |
15137 | mips_in_shared = TRUE; | |
15138 | break; | |
15139 | ||
15140 | case OPTION_MNO_SHARED: | |
15141 | mips_in_shared = FALSE; | |
15142 | break; | |
15143 | ||
aed1a261 RS |
15144 | case OPTION_MSYM32: |
15145 | mips_opts.sym32 = TRUE; | |
15146 | break; | |
15147 | ||
15148 | case OPTION_MNO_SYM32: | |
15149 | mips_opts.sym32 = FALSE; | |
15150 | break; | |
15151 | ||
252b5132 RH |
15152 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15153 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15154 | intended to be compatible with Irix 5. */ | |
15155 | case OPTION_CALL_SHARED: | |
252b5132 | 15156 | mips_pic = SVR4_PIC; |
143d77c5 | 15157 | mips_abicalls = TRUE; |
252b5132 RH |
15158 | break; |
15159 | ||
861fb55a | 15160 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15161 | mips_pic = NO_PIC; |
15162 | mips_abicalls = TRUE; | |
15163 | break; | |
15164 | ||
252b5132 | 15165 | case OPTION_NON_SHARED: |
252b5132 | 15166 | mips_pic = NO_PIC; |
143d77c5 | 15167 | mips_abicalls = FALSE; |
252b5132 RH |
15168 | break; |
15169 | ||
44075ae2 TS |
15170 | /* The -xgot option tells the assembler to use 32 bit offsets |
15171 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15172 | compatibility. */ |
15173 | case OPTION_XGOT: | |
15174 | mips_big_got = 1; | |
15175 | break; | |
15176 | ||
15177 | case 'G': | |
6caf9ef4 TS |
15178 | g_switch_value = atoi (arg); |
15179 | g_switch_seen = 1; | |
252b5132 RH |
15180 | break; |
15181 | ||
34ba82a8 TS |
15182 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15183 | and -mabi=64. */ | |
252b5132 | 15184 | case OPTION_32: |
f3ded42a | 15185 | mips_abi = O32_ABI; |
252b5132 RH |
15186 | break; |
15187 | ||
e013f690 | 15188 | case OPTION_N32: |
316f5878 | 15189 | mips_abi = N32_ABI; |
e013f690 | 15190 | break; |
252b5132 | 15191 | |
e013f690 | 15192 | case OPTION_64: |
316f5878 | 15193 | mips_abi = N64_ABI; |
f43abd2b | 15194 | if (!support_64bit_objects()) |
e013f690 | 15195 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 RH |
15196 | break; |
15197 | ||
c97ef257 | 15198 | case OPTION_GP32: |
a325df1d | 15199 | file_mips_gp32 = 1; |
c97ef257 AH |
15200 | break; |
15201 | ||
15202 | case OPTION_GP64: | |
a325df1d | 15203 | file_mips_gp32 = 0; |
c97ef257 | 15204 | break; |
252b5132 | 15205 | |
ca4e0257 | 15206 | case OPTION_FP32: |
a325df1d | 15207 | file_mips_fp32 = 1; |
316f5878 RS |
15208 | break; |
15209 | ||
15210 | case OPTION_FP64: | |
15211 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15212 | break; |
15213 | ||
037b32b9 AN |
15214 | case OPTION_SINGLE_FLOAT: |
15215 | file_mips_single_float = 1; | |
15216 | break; | |
15217 | ||
15218 | case OPTION_DOUBLE_FLOAT: | |
15219 | file_mips_single_float = 0; | |
15220 | break; | |
15221 | ||
15222 | case OPTION_SOFT_FLOAT: | |
15223 | file_mips_soft_float = 1; | |
15224 | break; | |
15225 | ||
15226 | case OPTION_HARD_FLOAT: | |
15227 | file_mips_soft_float = 0; | |
15228 | break; | |
15229 | ||
252b5132 | 15230 | case OPTION_MABI: |
e013f690 | 15231 | if (strcmp (arg, "32") == 0) |
316f5878 | 15232 | mips_abi = O32_ABI; |
e013f690 | 15233 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15234 | mips_abi = O64_ABI; |
e013f690 | 15235 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15236 | mips_abi = N32_ABI; |
e013f690 TS |
15237 | else if (strcmp (arg, "64") == 0) |
15238 | { | |
316f5878 | 15239 | mips_abi = N64_ABI; |
e013f690 TS |
15240 | if (! support_64bit_objects()) |
15241 | as_fatal (_("No compiled in support for 64 bit object file " | |
15242 | "format")); | |
15243 | } | |
15244 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15245 | mips_abi = EABI_ABI; |
e013f690 | 15246 | else |
da0e507f TS |
15247 | { |
15248 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15249 | return 0; | |
15250 | } | |
252b5132 RH |
15251 | break; |
15252 | ||
6b76fefe | 15253 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15254 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15255 | break; |
15256 | ||
9ee72ff1 | 15257 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15258 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15259 | break; |
15260 | ||
ecb4347a | 15261 | case OPTION_MDEBUG: |
b34976b6 | 15262 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15263 | break; |
15264 | ||
15265 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15266 | mips_flag_mdebug = FALSE; |
ecb4347a | 15267 | break; |
dcd410fe RO |
15268 | |
15269 | case OPTION_PDR: | |
15270 | mips_flag_pdr = TRUE; | |
15271 | break; | |
15272 | ||
15273 | case OPTION_NO_PDR: | |
15274 | mips_flag_pdr = FALSE; | |
15275 | break; | |
0a44bf69 RS |
15276 | |
15277 | case OPTION_MVXWORKS_PIC: | |
15278 | mips_pic = VXWORKS_PIC; | |
15279 | break; | |
ecb4347a | 15280 | |
252b5132 RH |
15281 | default: |
15282 | return 0; | |
15283 | } | |
15284 | ||
c67a084a NC |
15285 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15286 | ||
252b5132 RH |
15287 | return 1; |
15288 | } | |
316f5878 RS |
15289 | \f |
15290 | /* Set up globals to generate code for the ISA or processor | |
15291 | described by INFO. */ | |
252b5132 | 15292 | |
252b5132 | 15293 | static void |
17a2f251 | 15294 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15295 | { |
316f5878 | 15296 | if (info != 0) |
252b5132 | 15297 | { |
fef14a42 TS |
15298 | file_mips_arch = info->cpu; |
15299 | mips_opts.arch = info->cpu; | |
316f5878 | 15300 | mips_opts.isa = info->isa; |
252b5132 | 15301 | } |
252b5132 RH |
15302 | } |
15303 | ||
252b5132 | 15304 | |
316f5878 | 15305 | /* Likewise for tuning. */ |
252b5132 | 15306 | |
316f5878 | 15307 | static void |
17a2f251 | 15308 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15309 | { |
15310 | if (info != 0) | |
fef14a42 | 15311 | mips_tune = info->cpu; |
316f5878 | 15312 | } |
80cc45a5 | 15313 | |
34ba82a8 | 15314 | |
252b5132 | 15315 | void |
17a2f251 | 15316 | mips_after_parse_args (void) |
e9670677 | 15317 | { |
fef14a42 TS |
15318 | const struct mips_cpu_info *arch_info = 0; |
15319 | const struct mips_cpu_info *tune_info = 0; | |
15320 | ||
e9670677 | 15321 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15322 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15323 | { |
6caf9ef4 | 15324 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15325 | as_bad (_("-G not supported in this configuration.")); |
15326 | g_switch_value = 0; | |
15327 | } | |
15328 | ||
cac012d6 AO |
15329 | if (mips_abi == NO_ABI) |
15330 | mips_abi = MIPS_DEFAULT_ABI; | |
15331 | ||
22923709 RS |
15332 | /* The following code determines the architecture and register size. |
15333 | Similar code was added to GCC 3.3 (see override_options() in | |
15334 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15335 | as much as possible. */ | |
e9670677 | 15336 | |
316f5878 | 15337 | if (mips_arch_string != 0) |
fef14a42 | 15338 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15339 | |
316f5878 | 15340 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15341 | { |
316f5878 | 15342 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15343 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15344 | the -march selection (if any). */ |
fef14a42 | 15345 | if (arch_info != 0) |
e9670677 | 15346 | { |
316f5878 RS |
15347 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15348 | There's no harm in specifying both as long as the ISA levels | |
15349 | are the same. */ | |
fef14a42 | 15350 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15351 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15352 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15353 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15354 | } |
316f5878 | 15355 | else |
fef14a42 | 15356 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15357 | } |
15358 | ||
fef14a42 | 15359 | if (arch_info == 0) |
95bfe26e MF |
15360 | { |
15361 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15362 | gas_assert (arch_info); | |
15363 | } | |
e9670677 | 15364 | |
fef14a42 | 15365 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15366 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15367 | arch_info->name); |
15368 | ||
15369 | mips_set_architecture (arch_info); | |
15370 | ||
15371 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15372 | if (mips_tune_string != 0) | |
15373 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15374 | |
fef14a42 TS |
15375 | if (tune_info == 0) |
15376 | mips_set_tune (arch_info); | |
15377 | else | |
15378 | mips_set_tune (tune_info); | |
e9670677 | 15379 | |
316f5878 | 15380 | if (file_mips_gp32 >= 0) |
e9670677 | 15381 | { |
316f5878 RS |
15382 | /* The user specified the size of the integer registers. Make sure |
15383 | it agrees with the ABI and ISA. */ | |
15384 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15385 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15386 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15387 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15388 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15389 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15390 | } |
15391 | else | |
15392 | { | |
316f5878 RS |
15393 | /* Infer the integer register size from the ABI and processor. |
15394 | Restrict ourselves to 32-bit registers if that's all the | |
15395 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15396 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15397 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15398 | } |
15399 | ||
ad3fea08 TS |
15400 | switch (file_mips_fp32) |
15401 | { | |
15402 | default: | |
15403 | case -1: | |
15404 | /* No user specified float register size. | |
15405 | ??? GAS treats single-float processors as though they had 64-bit | |
15406 | float registers (although it complains when double-precision | |
15407 | instructions are used). As things stand, saying they have 32-bit | |
15408 | registers would lead to spurious "register must be even" messages. | |
15409 | So here we assume float registers are never smaller than the | |
15410 | integer ones. */ | |
15411 | if (file_mips_gp32 == 0) | |
15412 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15413 | file_mips_fp32 = 0; | |
c6278170 | 15414 | else if ((mips_opts.ase & FP64_ASES) |
ad3fea08 TS |
15415 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
15416 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15417 | file_mips_fp32 = 0; | |
15418 | else | |
15419 | /* 32-bit float registers. */ | |
15420 | file_mips_fp32 = 1; | |
15421 | break; | |
15422 | ||
15423 | /* The user specified the size of the float registers. Check if it | |
15424 | agrees with the ABI and ISA. */ | |
15425 | case 0: | |
15426 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15427 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15428 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15429 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15430 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15431 | break; | |
15432 | case 1: | |
15433 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15434 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15435 | break; | |
15436 | } | |
e9670677 | 15437 | |
316f5878 | 15438 | /* End of GCC-shared inference code. */ |
e9670677 | 15439 | |
17a2f251 TS |
15440 | /* This flag is set when we have a 64-bit capable CPU but use only |
15441 | 32-bit wide registers. Note that EABI does not use it. */ | |
15442 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15443 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15444 | || mips_abi == O32_ABI)) | |
316f5878 | 15445 | mips_32bitmode = 1; |
e9670677 MR |
15446 | |
15447 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15448 | as_bad (_("trap exception not supported at ISA 1")); | |
15449 | ||
e9670677 MR |
15450 | /* If the selected architecture includes support for ASEs, enable |
15451 | generation of code for them. */ | |
a4672219 | 15452 | if (mips_opts.mips16 == -1) |
fef14a42 | 15453 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15454 | if (mips_opts.micromips == -1) |
15455 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
846ef2d0 RS |
15456 | |
15457 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
15458 | ASEs from being selected implicitly. */ | |
15459 | if (file_mips_fp32 == 1) | |
15460 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; | |
15461 | ||
15462 | /* If the user didn't explicitly select or deselect a particular ASE, | |
15463 | use the default setting for the CPU. */ | |
15464 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
15465 | ||
e9670677 | 15466 | file_mips_isa = mips_opts.isa; |
846ef2d0 | 15467 | file_ase = mips_opts.ase; |
e9670677 MR |
15468 | mips_opts.gp32 = file_mips_gp32; |
15469 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15470 | mips_opts.soft_float = file_mips_soft_float; |
15471 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15472 | |
c6278170 RS |
15473 | mips_check_isa_supports_ases (); |
15474 | ||
ecb4347a | 15475 | if (mips_flag_mdebug < 0) |
e8044f35 | 15476 | mips_flag_mdebug = 0; |
e9670677 MR |
15477 | } |
15478 | \f | |
15479 | void | |
17a2f251 | 15480 | mips_init_after_args (void) |
252b5132 RH |
15481 | { |
15482 | /* initialize opcodes */ | |
15483 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15484 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15485 | } |
15486 | ||
15487 | long | |
17a2f251 | 15488 | md_pcrel_from (fixS *fixP) |
252b5132 | 15489 | { |
a7ebbfdf TS |
15490 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15491 | switch (fixP->fx_r_type) | |
15492 | { | |
df58fc94 RS |
15493 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15494 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15495 | /* Return the address of the delay slot. */ | |
15496 | return addr + 2; | |
15497 | ||
15498 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15499 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15500 | case BFD_RELOC_16_PCREL_S2: |
15501 | case BFD_RELOC_MIPS_JMP: | |
15502 | /* Return the address of the delay slot. */ | |
15503 | return addr + 4; | |
df58fc94 | 15504 | |
b47468a6 CM |
15505 | case BFD_RELOC_32_PCREL: |
15506 | return addr; | |
15507 | ||
a7ebbfdf | 15508 | default: |
58ea3d6a | 15509 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15510 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15511 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15512 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15513 | return addr; |
15514 | } | |
252b5132 RH |
15515 | } |
15516 | ||
252b5132 RH |
15517 | /* This is called before the symbol table is processed. In order to |
15518 | work with gcc when using mips-tfile, we must keep all local labels. | |
15519 | However, in other cases, we want to discard them. If we were | |
15520 | called with -g, but we didn't see any debugging information, it may | |
15521 | mean that gcc is smuggling debugging information through to | |
15522 | mips-tfile, in which case we must generate all local labels. */ | |
15523 | ||
15524 | void | |
17a2f251 | 15525 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15526 | { |
15527 | #ifndef NO_ECOFF_DEBUGGING | |
15528 | if (ECOFF_DEBUGGING | |
15529 | && mips_debug != 0 | |
15530 | && ! ecoff_debugging_seen) | |
15531 | flag_keep_locals = 1; | |
15532 | #endif | |
15533 | } | |
15534 | ||
3b91255e | 15535 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15536 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15537 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15538 | relocation operators. | |
15539 | ||
15540 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15541 | expression if: | |
15542 | ||
15543 | (a) it refers to the same symbol; and | |
15544 | (b) the offset applied in the %lo() expression is no lower than | |
15545 | the offset applied in the %got() or %hi(). | |
15546 | ||
15547 | (b) allows us to cope with code like: | |
15548 | ||
15549 | lui $4,%hi(foo) | |
15550 | lh $4,%lo(foo+2)($4) | |
15551 | ||
15552 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15553 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15554 | the high 16 bits. | |
15555 | ||
15556 | When several %lo()s match a particular %got() or %hi(), we use the | |
15557 | following rules to distinguish them: | |
15558 | ||
15559 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15560 | higher offsets. | |
15561 | ||
15562 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15563 | that already have a matching %got() or %hi(). | |
15564 | ||
15565 | (3) later %lo()s are better than earlier %lo()s. | |
15566 | ||
15567 | These rules are applied in order. | |
15568 | ||
15569 | (1) means, among other things, that %lo()s with identical offsets are | |
15570 | chosen if they exist. | |
15571 | ||
15572 | (2) means that we won't associate several high-part relocations with | |
15573 | the same low-part relocation unless there's no alternative. Having | |
15574 | several high parts for the same low part is a GNU extension; this rule | |
15575 | allows careful users to avoid it. | |
15576 | ||
15577 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15578 | with the last high-part relocation being at the front of the list. | |
15579 | It therefore makes sense to choose the last matching low-part | |
15580 | relocation, all other things being equal. It's also easier | |
15581 | to code that way. */ | |
252b5132 RH |
15582 | |
15583 | void | |
17a2f251 | 15584 | mips_frob_file (void) |
252b5132 RH |
15585 | { |
15586 | struct mips_hi_fixup *l; | |
35903be0 | 15587 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15588 | |
15589 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15590 | { | |
15591 | segment_info_type *seginfo; | |
3b91255e RS |
15592 | bfd_boolean matched_lo_p; |
15593 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15594 | |
9c2799c2 | 15595 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15596 | |
5919d012 | 15597 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15598 | there isn't supposed to be a matching LO. Ignore %gots against |
15599 | constants; we'll report an error for those later. */ | |
738e5348 | 15600 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15601 | && !(l->fixp->fx_addsy |
15602 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15603 | continue; |
15604 | ||
15605 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15606 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15607 | continue; |
15608 | ||
252b5132 | 15609 | seginfo = seg_info (l->seg); |
252b5132 | 15610 | |
3b91255e RS |
15611 | /* Set HI_POS to the position of this relocation in the chain. |
15612 | Set LO_POS to the position of the chosen low-part relocation. | |
15613 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15614 | relocation that matches an immediately-preceding high-part | |
15615 | relocation. */ | |
15616 | hi_pos = NULL; | |
15617 | lo_pos = NULL; | |
15618 | matched_lo_p = FALSE; | |
738e5348 | 15619 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15620 | |
3b91255e RS |
15621 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15622 | { | |
15623 | if (*pos == l->fixp) | |
15624 | hi_pos = pos; | |
15625 | ||
35903be0 | 15626 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15627 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15628 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15629 | && (lo_pos == NULL | |
15630 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15631 | || (!matched_lo_p | |
15632 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15633 | lo_pos = pos; | |
15634 | ||
15635 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15636 | && fixup_has_matching_lo_p (*pos)); | |
15637 | } | |
15638 | ||
15639 | /* If we found a match, remove the high-part relocation from its | |
15640 | current position and insert it before the low-part relocation. | |
15641 | Make the offsets match so that fixup_has_matching_lo_p() | |
15642 | will return true. | |
15643 | ||
15644 | We don't warn about unmatched high-part relocations since some | |
15645 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15646 | instructions. */ | |
15647 | if (lo_pos != NULL) | |
15648 | { | |
15649 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15650 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15651 | { |
3b91255e RS |
15652 | *hi_pos = l->fixp->fx_next; |
15653 | l->fixp->fx_next = *lo_pos; | |
15654 | *lo_pos = l->fixp; | |
252b5132 | 15655 | } |
252b5132 RH |
15656 | } |
15657 | } | |
15658 | } | |
15659 | ||
252b5132 | 15660 | int |
17a2f251 | 15661 | mips_force_relocation (fixS *fixp) |
252b5132 | 15662 | { |
ae6063d4 | 15663 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15664 | return 1; |
15665 | ||
df58fc94 RS |
15666 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15667 | so that the linker relaxation can update targets. */ | |
15668 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15669 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15670 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15671 | return 1; | |
15672 | ||
3e722fb5 | 15673 | return 0; |
252b5132 RH |
15674 | } |
15675 | ||
b886a2ab RS |
15676 | /* Read the instruction associated with RELOC from BUF. */ |
15677 | ||
15678 | static unsigned int | |
15679 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15680 | { | |
15681 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15682 | return read_compressed_insn (buf, 4); | |
15683 | else | |
15684 | return read_insn (buf); | |
15685 | } | |
15686 | ||
15687 | /* Write instruction INSN to BUF, given that it has been relocated | |
15688 | by RELOC. */ | |
15689 | ||
15690 | static void | |
15691 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15692 | unsigned long insn) | |
15693 | { | |
15694 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15695 | write_compressed_insn (buf, insn, 4); | |
15696 | else | |
15697 | write_insn (buf, insn); | |
15698 | } | |
15699 | ||
252b5132 RH |
15700 | /* Apply a fixup to the object file. */ |
15701 | ||
94f592af | 15702 | void |
55cf6793 | 15703 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15704 | { |
4d68580a | 15705 | char *buf; |
b886a2ab | 15706 | unsigned long insn; |
a7ebbfdf | 15707 | reloc_howto_type *howto; |
252b5132 | 15708 | |
a7ebbfdf TS |
15709 | /* We ignore generic BFD relocations we don't know about. */ |
15710 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15711 | if (! howto) | |
15712 | return; | |
65551fa4 | 15713 | |
df58fc94 RS |
15714 | gas_assert (fixP->fx_size == 2 |
15715 | || fixP->fx_size == 4 | |
90ecf173 MR |
15716 | || fixP->fx_r_type == BFD_RELOC_16 |
15717 | || fixP->fx_r_type == BFD_RELOC_64 | |
15718 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15719 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15720 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15721 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15722 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15723 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15724 | |
4d68580a | 15725 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15726 | |
df58fc94 RS |
15727 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15728 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15729 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15730 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15731 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15732 | |
15733 | /* Don't treat parts of a composite relocation as done. There are two | |
15734 | reasons for this: | |
15735 | ||
15736 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15737 | should nevertheless be emitted if the first part is. | |
15738 | ||
15739 | (2) In normal usage, composite relocations are never assembly-time | |
15740 | constants. The easiest way of dealing with the pathological | |
15741 | exceptions is to generate a relocation against STN_UNDEF and | |
15742 | leave everything up to the linker. */ | |
3994f87e | 15743 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15744 | fixP->fx_done = 1; |
15745 | ||
15746 | switch (fixP->fx_r_type) | |
15747 | { | |
3f98094e DJ |
15748 | case BFD_RELOC_MIPS_TLS_GD: |
15749 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15750 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15751 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15752 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15753 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15754 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15755 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15756 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15757 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15758 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15759 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15760 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15761 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15762 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15763 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15764 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15765 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15766 | case BFD_RELOC_MIPS16_TLS_GD: |
15767 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15768 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15769 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15770 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15771 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15772 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15773 | if (!fixP->fx_addsy) |
15774 | { | |
15775 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15776 | _("TLS relocation against a constant")); | |
15777 | break; | |
15778 | } | |
3f98094e DJ |
15779 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15780 | /* fall through */ | |
15781 | ||
252b5132 | 15782 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15783 | case BFD_RELOC_MIPS_SHIFT5: |
15784 | case BFD_RELOC_MIPS_SHIFT6: | |
15785 | case BFD_RELOC_MIPS_GOT_DISP: | |
15786 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15787 | case BFD_RELOC_MIPS_GOT_OFST: | |
15788 | case BFD_RELOC_MIPS_SUB: | |
15789 | case BFD_RELOC_MIPS_INSERT_A: | |
15790 | case BFD_RELOC_MIPS_INSERT_B: | |
15791 | case BFD_RELOC_MIPS_DELETE: | |
15792 | case BFD_RELOC_MIPS_HIGHEST: | |
15793 | case BFD_RELOC_MIPS_HIGHER: | |
15794 | case BFD_RELOC_MIPS_SCN_DISP: | |
15795 | case BFD_RELOC_MIPS_REL16: | |
15796 | case BFD_RELOC_MIPS_RELGOT: | |
15797 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15798 | case BFD_RELOC_HI16: |
15799 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15800 | case BFD_RELOC_LO16: |
cdf6fd85 | 15801 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15802 | case BFD_RELOC_MIPS_LITERAL: |
15803 | case BFD_RELOC_MIPS_CALL16: | |
15804 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15805 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15806 | case BFD_RELOC_MIPS_GOT_HI16: |
15807 | case BFD_RELOC_MIPS_GOT_LO16: | |
15808 | case BFD_RELOC_MIPS_CALL_HI16: | |
15809 | case BFD_RELOC_MIPS_CALL_LO16: | |
15810 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15811 | case BFD_RELOC_MIPS16_GOT16: |
15812 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15813 | case BFD_RELOC_MIPS16_HI16: |
15814 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15815 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15816 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15817 | case BFD_RELOC_MICROMIPS_JMP: |
15818 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15819 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15820 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15821 | case BFD_RELOC_MICROMIPS_SUB: | |
15822 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15823 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15824 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15825 | case BFD_RELOC_MICROMIPS_JALR: | |
15826 | case BFD_RELOC_MICROMIPS_HI16: | |
15827 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15828 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15829 | case BFD_RELOC_MICROMIPS_GPREL16: |
15830 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15831 | case BFD_RELOC_MICROMIPS_CALL16: | |
15832 | case BFD_RELOC_MICROMIPS_GOT16: | |
15833 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15834 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15835 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15836 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15837 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15838 | if (fixP->fx_done) |
15839 | { | |
15840 | offsetT value; | |
15841 | ||
15842 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15843 | { | |
15844 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15845 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15846 | insn |= mips16_immed_extend (value, 16); | |
15847 | else | |
15848 | insn |= (value & 0xffff); | |
15849 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15850 | } | |
15851 | else | |
15852 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15853 | _("Unsupported constant in relocation")); | |
15854 | } | |
252b5132 RH |
15855 | break; |
15856 | ||
252b5132 RH |
15857 | case BFD_RELOC_64: |
15858 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15859 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15860 | if (fixP->fx_done) |
252b5132 RH |
15861 | { |
15862 | if (8 <= sizeof (valueT)) | |
4d68580a | 15863 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15864 | else |
15865 | { | |
a7ebbfdf | 15866 | valueT hiv; |
252b5132 | 15867 | |
a7ebbfdf | 15868 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15869 | hiv = 0xffffffff; |
15870 | else | |
15871 | hiv = 0; | |
4d68580a RS |
15872 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15873 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15874 | } |
15875 | } | |
15876 | break; | |
15877 | ||
056350c6 | 15878 | case BFD_RELOC_RVA: |
252b5132 | 15879 | case BFD_RELOC_32: |
b47468a6 | 15880 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15881 | case BFD_RELOC_16: |
15882 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15883 | value now. This can happen if we have a .word which is not |
15884 | resolved when it appears but is later defined. */ | |
252b5132 | 15885 | if (fixP->fx_done) |
4d68580a | 15886 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15887 | break; |
15888 | ||
252b5132 | 15889 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15890 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15891 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15892 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15893 | |
54f4ddb3 TS |
15894 | /* We need to save the bits in the instruction since fixup_segment() |
15895 | might be deleting the relocation entry (i.e., a branch within | |
15896 | the current segment). */ | |
a7ebbfdf | 15897 | if (! fixP->fx_done) |
bb2d6cd7 | 15898 | break; |
252b5132 | 15899 | |
54f4ddb3 | 15900 | /* Update old instruction data. */ |
4d68580a | 15901 | insn = read_insn (buf); |
252b5132 | 15902 | |
a7ebbfdf TS |
15903 | if (*valP + 0x20000 <= 0x3ffff) |
15904 | { | |
15905 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15906 | write_insn (buf, insn); |
a7ebbfdf TS |
15907 | } |
15908 | else if (mips_pic == NO_PIC | |
15909 | && fixP->fx_done | |
15910 | && fixP->fx_frag->fr_address >= text_section->vma | |
15911 | && (fixP->fx_frag->fr_address | |
587aac4e | 15912 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15913 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15914 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15915 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15916 | { |
15917 | /* The branch offset is too large. If this is an | |
15918 | unconditional branch, and we are not generating PIC code, | |
15919 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15920 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15921 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15922 | else |
a7ebbfdf TS |
15923 | insn = 0x08000000; /* j */ |
15924 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15925 | fixP->fx_done = 0; | |
15926 | fixP->fx_addsy = section_symbol (text_section); | |
15927 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15928 | write_insn (buf, insn); |
a7ebbfdf TS |
15929 | } |
15930 | else | |
15931 | { | |
15932 | /* If we got here, we have branch-relaxation disabled, | |
15933 | and there's nothing we can do to fix this instruction | |
15934 | without turning it into a longer sequence. */ | |
15935 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15936 | _("Branch out of range")); | |
252b5132 | 15937 | } |
252b5132 RH |
15938 | break; |
15939 | ||
df58fc94 RS |
15940 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15941 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15942 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15943 | /* We adjust the offset back to even. */ | |
15944 | if ((*valP & 0x1) != 0) | |
15945 | --(*valP); | |
15946 | ||
15947 | if (! fixP->fx_done) | |
15948 | break; | |
15949 | ||
15950 | /* Should never visit here, because we keep the relocation. */ | |
15951 | abort (); | |
15952 | break; | |
15953 | ||
252b5132 RH |
15954 | case BFD_RELOC_VTABLE_INHERIT: |
15955 | fixP->fx_done = 0; | |
15956 | if (fixP->fx_addsy | |
15957 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15958 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15959 | S_SET_WEAK (fixP->fx_addsy); | |
15960 | break; | |
15961 | ||
15962 | case BFD_RELOC_VTABLE_ENTRY: | |
15963 | fixP->fx_done = 0; | |
15964 | break; | |
15965 | ||
15966 | default: | |
b37df7c4 | 15967 | abort (); |
252b5132 | 15968 | } |
a7ebbfdf TS |
15969 | |
15970 | /* Remember value for tc_gen_reloc. */ | |
15971 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15972 | } |
15973 | ||
252b5132 | 15974 | static symbolS * |
17a2f251 | 15975 | get_symbol (void) |
252b5132 RH |
15976 | { |
15977 | int c; | |
15978 | char *name; | |
15979 | symbolS *p; | |
15980 | ||
15981 | name = input_line_pointer; | |
15982 | c = get_symbol_end (); | |
15983 | p = (symbolS *) symbol_find_or_make (name); | |
15984 | *input_line_pointer = c; | |
15985 | return p; | |
15986 | } | |
15987 | ||
742a56fe RS |
15988 | /* Align the current frag to a given power of two. If a particular |
15989 | fill byte should be used, FILL points to an integer that contains | |
15990 | that byte, otherwise FILL is null. | |
15991 | ||
462427c4 RS |
15992 | This function used to have the comment: |
15993 | ||
15994 | The MIPS assembler also automatically adjusts any preceding label. | |
15995 | ||
15996 | The implementation therefore applied the adjustment to a maximum of | |
15997 | one label. However, other label adjustments are applied to batches | |
15998 | of labels, and adjusting just one caused problems when new labels | |
15999 | were added for the sake of debugging or unwind information. | |
16000 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16001 | |
16002 | static void | |
462427c4 | 16003 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16004 | { |
7d10b47d | 16005 | mips_emit_delays (); |
df58fc94 | 16006 | mips_record_compressed_mode (); |
742a56fe RS |
16007 | if (fill == NULL && subseg_text_p (now_seg)) |
16008 | frag_align_code (to, 0); | |
16009 | else | |
16010 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16011 | record_alignment (now_seg, to); |
462427c4 | 16012 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16013 | } |
16014 | ||
16015 | /* Align to a given power of two. .align 0 turns off the automatic | |
16016 | alignment used by the data creating pseudo-ops. */ | |
16017 | ||
16018 | static void | |
17a2f251 | 16019 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16020 | { |
742a56fe | 16021 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16022 | long max_alignment = 28; |
252b5132 | 16023 | |
54f4ddb3 | 16024 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16025 | to the aligned address. |
54f4ddb3 | 16026 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16027 | a .align pseudo instruction. |
54f4ddb3 | 16028 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16029 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16030 | We don't. */ |
252b5132 RH |
16031 | |
16032 | temp = get_absolute_expression (); | |
16033 | if (temp > max_alignment) | |
16034 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16035 | else if (temp < 0) | |
16036 | { | |
16037 | as_warn (_("Alignment negative: 0 assumed.")); | |
16038 | temp = 0; | |
16039 | } | |
16040 | if (*input_line_pointer == ',') | |
16041 | { | |
f9419b05 | 16042 | ++input_line_pointer; |
742a56fe RS |
16043 | fill_value = get_absolute_expression (); |
16044 | fill_ptr = &fill_value; | |
252b5132 RH |
16045 | } |
16046 | else | |
742a56fe | 16047 | fill_ptr = 0; |
252b5132 RH |
16048 | if (temp) |
16049 | { | |
a8dbcb85 TS |
16050 | segment_info_type *si = seg_info (now_seg); |
16051 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16052 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16053 | auto_align = 1; |
462427c4 | 16054 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16055 | } |
16056 | else | |
16057 | { | |
16058 | auto_align = 0; | |
16059 | } | |
16060 | ||
16061 | demand_empty_rest_of_line (); | |
16062 | } | |
16063 | ||
252b5132 | 16064 | static void |
17a2f251 | 16065 | s_change_sec (int sec) |
252b5132 RH |
16066 | { |
16067 | segT seg; | |
16068 | ||
252b5132 RH |
16069 | /* The ELF backend needs to know that we are changing sections, so |
16070 | that .previous works correctly. We could do something like check | |
b6ff326e | 16071 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16072 | as it would not be appropriate to use it in the section changing |
16073 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16074 | This should be cleaner, somehow. */ | |
f3ded42a | 16075 | obj_elf_section_change_hook (); |
252b5132 | 16076 | |
7d10b47d | 16077 | mips_emit_delays (); |
6a32d874 | 16078 | |
252b5132 RH |
16079 | switch (sec) |
16080 | { | |
16081 | case 't': | |
16082 | s_text (0); | |
16083 | break; | |
16084 | case 'd': | |
16085 | s_data (0); | |
16086 | break; | |
16087 | case 'b': | |
16088 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16089 | demand_empty_rest_of_line (); | |
16090 | break; | |
16091 | ||
16092 | case 'r': | |
4d0d148d TS |
16093 | seg = subseg_new (RDATA_SECTION_NAME, |
16094 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16095 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16096 | | SEC_READONLY | SEC_RELOC | |
16097 | | SEC_DATA)); | |
16098 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16099 | record_alignment (seg, 4); | |
4d0d148d | 16100 | demand_empty_rest_of_line (); |
252b5132 RH |
16101 | break; |
16102 | ||
16103 | case 's': | |
4d0d148d | 16104 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16105 | bfd_set_section_flags (stdoutput, seg, |
16106 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16107 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16108 | record_alignment (seg, 4); | |
4d0d148d TS |
16109 | demand_empty_rest_of_line (); |
16110 | break; | |
998b3c36 MR |
16111 | |
16112 | case 'B': | |
16113 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16114 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16115 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16116 | record_alignment (seg, 4); | |
998b3c36 MR |
16117 | demand_empty_rest_of_line (); |
16118 | break; | |
252b5132 RH |
16119 | } |
16120 | ||
16121 | auto_align = 1; | |
16122 | } | |
b34976b6 | 16123 | |
cca86cc8 | 16124 | void |
17a2f251 | 16125 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16126 | { |
cca86cc8 SC |
16127 | char *section_name; |
16128 | char c; | |
684022ea | 16129 | char next_c = 0; |
cca86cc8 SC |
16130 | int section_type; |
16131 | int section_flag; | |
16132 | int section_entry_size; | |
16133 | int section_alignment; | |
b34976b6 | 16134 | |
cca86cc8 SC |
16135 | section_name = input_line_pointer; |
16136 | c = get_symbol_end (); | |
a816d1ed AO |
16137 | if (c) |
16138 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16139 | |
4cf0dd0d TS |
16140 | /* Do we have .section Name<,"flags">? */ |
16141 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16142 | { |
4cf0dd0d TS |
16143 | /* just after name is now '\0'. */ |
16144 | *input_line_pointer = c; | |
cca86cc8 SC |
16145 | input_line_pointer = section_name; |
16146 | obj_elf_section (ignore); | |
16147 | return; | |
16148 | } | |
16149 | input_line_pointer++; | |
16150 | ||
16151 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16152 | if (c == ',') | |
16153 | section_type = get_absolute_expression (); | |
16154 | else | |
16155 | section_type = 0; | |
16156 | if (*input_line_pointer++ == ',') | |
16157 | section_flag = get_absolute_expression (); | |
16158 | else | |
16159 | section_flag = 0; | |
16160 | if (*input_line_pointer++ == ',') | |
16161 | section_entry_size = get_absolute_expression (); | |
16162 | else | |
16163 | section_entry_size = 0; | |
16164 | if (*input_line_pointer++ == ',') | |
16165 | section_alignment = get_absolute_expression (); | |
16166 | else | |
16167 | section_alignment = 0; | |
87975d2a AM |
16168 | /* FIXME: really ignore? */ |
16169 | (void) section_alignment; | |
cca86cc8 | 16170 | |
a816d1ed AO |
16171 | section_name = xstrdup (section_name); |
16172 | ||
8ab8a5c8 RS |
16173 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16174 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16175 | traditionally had to fall back on the more common @progbits instead. | |
16176 | ||
16177 | There's nothing really harmful in this, since bfd will correct | |
16178 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16179 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16180 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16181 | ||
16182 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16183 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16184 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16185 | generic type-checking code. */ | |
16186 | if (section_type == SHT_MIPS_DWARF) | |
16187 | section_type = SHT_PROGBITS; | |
16188 | ||
cca86cc8 SC |
16189 | obj_elf_change_section (section_name, section_type, section_flag, |
16190 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16191 | |
16192 | if (now_seg->name != section_name) | |
16193 | free (section_name); | |
cca86cc8 | 16194 | } |
252b5132 RH |
16195 | |
16196 | void | |
17a2f251 | 16197 | mips_enable_auto_align (void) |
252b5132 RH |
16198 | { |
16199 | auto_align = 1; | |
16200 | } | |
16201 | ||
16202 | static void | |
17a2f251 | 16203 | s_cons (int log_size) |
252b5132 | 16204 | { |
a8dbcb85 TS |
16205 | segment_info_type *si = seg_info (now_seg); |
16206 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16207 | |
7d10b47d | 16208 | mips_emit_delays (); |
252b5132 | 16209 | if (log_size > 0 && auto_align) |
462427c4 | 16210 | mips_align (log_size, 0, l); |
252b5132 | 16211 | cons (1 << log_size); |
a1facbec | 16212 | mips_clear_insn_labels (); |
252b5132 RH |
16213 | } |
16214 | ||
16215 | static void | |
17a2f251 | 16216 | s_float_cons (int type) |
252b5132 | 16217 | { |
a8dbcb85 TS |
16218 | segment_info_type *si = seg_info (now_seg); |
16219 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16220 | |
7d10b47d | 16221 | mips_emit_delays (); |
252b5132 RH |
16222 | |
16223 | if (auto_align) | |
49309057 ILT |
16224 | { |
16225 | if (type == 'd') | |
462427c4 | 16226 | mips_align (3, 0, l); |
49309057 | 16227 | else |
462427c4 | 16228 | mips_align (2, 0, l); |
49309057 | 16229 | } |
252b5132 | 16230 | |
252b5132 | 16231 | float_cons (type); |
a1facbec | 16232 | mips_clear_insn_labels (); |
252b5132 RH |
16233 | } |
16234 | ||
16235 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16236 | permitted to say | |
16237 | .globl foo .text | |
16238 | where foo is an undefined symbol, to mean that foo should be | |
16239 | considered to be the address of a function. */ | |
16240 | ||
16241 | static void | |
17a2f251 | 16242 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16243 | { |
16244 | char *name; | |
16245 | int c; | |
16246 | symbolS *symbolP; | |
16247 | flagword flag; | |
16248 | ||
8a06b769 | 16249 | do |
252b5132 | 16250 | { |
8a06b769 | 16251 | name = input_line_pointer; |
252b5132 | 16252 | c = get_symbol_end (); |
8a06b769 TS |
16253 | symbolP = symbol_find_or_make (name); |
16254 | S_SET_EXTERNAL (symbolP); | |
16255 | ||
252b5132 | 16256 | *input_line_pointer = c; |
8a06b769 | 16257 | SKIP_WHITESPACE (); |
252b5132 | 16258 | |
8a06b769 TS |
16259 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16260 | being a function is apparently labelled as being an object. */ | |
16261 | flag = BSF_OBJECT; | |
252b5132 | 16262 | |
8a06b769 TS |
16263 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16264 | && (*input_line_pointer != ',')) | |
16265 | { | |
16266 | char *secname; | |
16267 | asection *sec; | |
16268 | ||
16269 | secname = input_line_pointer; | |
16270 | c = get_symbol_end (); | |
16271 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16272 | if (sec == NULL) | |
16273 | as_bad (_("%s: no such section"), secname); | |
16274 | *input_line_pointer = c; | |
16275 | ||
16276 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16277 | flag = BSF_FUNCTION; | |
16278 | } | |
16279 | ||
16280 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16281 | ||
16282 | c = *input_line_pointer; | |
16283 | if (c == ',') | |
16284 | { | |
16285 | input_line_pointer++; | |
16286 | SKIP_WHITESPACE (); | |
16287 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16288 | c = '\n'; | |
16289 | } | |
16290 | } | |
16291 | while (c == ','); | |
252b5132 | 16292 | |
252b5132 RH |
16293 | demand_empty_rest_of_line (); |
16294 | } | |
16295 | ||
16296 | static void | |
17a2f251 | 16297 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16298 | { |
16299 | char *opt; | |
16300 | char c; | |
16301 | ||
16302 | opt = input_line_pointer; | |
16303 | c = get_symbol_end (); | |
16304 | ||
16305 | if (*opt == 'O') | |
16306 | { | |
16307 | /* FIXME: What does this mean? */ | |
16308 | } | |
16309 | else if (strncmp (opt, "pic", 3) == 0) | |
16310 | { | |
16311 | int i; | |
16312 | ||
16313 | i = atoi (opt + 3); | |
16314 | if (i == 0) | |
16315 | mips_pic = NO_PIC; | |
16316 | else if (i == 2) | |
143d77c5 | 16317 | { |
8b828383 | 16318 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16319 | mips_abicalls = TRUE; |
16320 | } | |
252b5132 RH |
16321 | else |
16322 | as_bad (_(".option pic%d not supported"), i); | |
16323 | ||
4d0d148d | 16324 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16325 | { |
16326 | if (g_switch_seen && g_switch_value != 0) | |
16327 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16328 | g_switch_value = 0; | |
16329 | bfd_set_gp_size (stdoutput, 0); | |
16330 | } | |
16331 | } | |
16332 | else | |
16333 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16334 | ||
16335 | *input_line_pointer = c; | |
16336 | demand_empty_rest_of_line (); | |
16337 | } | |
16338 | ||
16339 | /* This structure is used to hold a stack of .set values. */ | |
16340 | ||
e972090a NC |
16341 | struct mips_option_stack |
16342 | { | |
252b5132 RH |
16343 | struct mips_option_stack *next; |
16344 | struct mips_set_options options; | |
16345 | }; | |
16346 | ||
16347 | static struct mips_option_stack *mips_opts_stack; | |
16348 | ||
16349 | /* Handle the .set pseudo-op. */ | |
16350 | ||
16351 | static void | |
17a2f251 | 16352 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16353 | { |
16354 | char *name = input_line_pointer, ch; | |
c6278170 | 16355 | const struct mips_ase *ase; |
252b5132 RH |
16356 | |
16357 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16358 | ++input_line_pointer; |
252b5132 RH |
16359 | ch = *input_line_pointer; |
16360 | *input_line_pointer = '\0'; | |
16361 | ||
16362 | if (strcmp (name, "reorder") == 0) | |
16363 | { | |
7d10b47d RS |
16364 | if (mips_opts.noreorder) |
16365 | end_noreorder (); | |
252b5132 RH |
16366 | } |
16367 | else if (strcmp (name, "noreorder") == 0) | |
16368 | { | |
7d10b47d RS |
16369 | if (!mips_opts.noreorder) |
16370 | start_noreorder (); | |
252b5132 | 16371 | } |
741fe287 MR |
16372 | else if (strncmp (name, "at=", 3) == 0) |
16373 | { | |
16374 | char *s = name + 3; | |
16375 | ||
16376 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16377 | as_bad (_("Unrecognized register name `%s'"), s); | |
16378 | } | |
252b5132 RH |
16379 | else if (strcmp (name, "at") == 0) |
16380 | { | |
741fe287 | 16381 | mips_opts.at = ATREG; |
252b5132 RH |
16382 | } |
16383 | else if (strcmp (name, "noat") == 0) | |
16384 | { | |
741fe287 | 16385 | mips_opts.at = ZERO; |
252b5132 RH |
16386 | } |
16387 | else if (strcmp (name, "macro") == 0) | |
16388 | { | |
16389 | mips_opts.warn_about_macros = 0; | |
16390 | } | |
16391 | else if (strcmp (name, "nomacro") == 0) | |
16392 | { | |
16393 | if (mips_opts.noreorder == 0) | |
16394 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16395 | mips_opts.warn_about_macros = 1; | |
16396 | } | |
16397 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16398 | { | |
16399 | mips_opts.nomove = 0; | |
16400 | } | |
16401 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16402 | { | |
16403 | mips_opts.nomove = 1; | |
16404 | } | |
16405 | else if (strcmp (name, "bopt") == 0) | |
16406 | { | |
16407 | mips_opts.nobopt = 0; | |
16408 | } | |
16409 | else if (strcmp (name, "nobopt") == 0) | |
16410 | { | |
16411 | mips_opts.nobopt = 1; | |
16412 | } | |
ad3fea08 TS |
16413 | else if (strcmp (name, "gp=default") == 0) |
16414 | mips_opts.gp32 = file_mips_gp32; | |
16415 | else if (strcmp (name, "gp=32") == 0) | |
16416 | mips_opts.gp32 = 1; | |
16417 | else if (strcmp (name, "gp=64") == 0) | |
16418 | { | |
16419 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16420 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16421 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16422 | mips_opts.gp32 = 0; | |
16423 | } | |
16424 | else if (strcmp (name, "fp=default") == 0) | |
16425 | mips_opts.fp32 = file_mips_fp32; | |
16426 | else if (strcmp (name, "fp=32") == 0) | |
16427 | mips_opts.fp32 = 1; | |
16428 | else if (strcmp (name, "fp=64") == 0) | |
16429 | { | |
16430 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16431 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16432 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16433 | mips_opts.fp32 = 0; | |
16434 | } | |
037b32b9 AN |
16435 | else if (strcmp (name, "softfloat") == 0) |
16436 | mips_opts.soft_float = 1; | |
16437 | else if (strcmp (name, "hardfloat") == 0) | |
16438 | mips_opts.soft_float = 0; | |
16439 | else if (strcmp (name, "singlefloat") == 0) | |
16440 | mips_opts.single_float = 1; | |
16441 | else if (strcmp (name, "doublefloat") == 0) | |
16442 | mips_opts.single_float = 0; | |
252b5132 RH |
16443 | else if (strcmp (name, "mips16") == 0 |
16444 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16445 | { |
16446 | if (mips_opts.micromips == 1) | |
16447 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16448 | mips_opts.mips16 = 1; | |
16449 | } | |
252b5132 RH |
16450 | else if (strcmp (name, "nomips16") == 0 |
16451 | || strcmp (name, "noMIPS-16") == 0) | |
16452 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16453 | else if (strcmp (name, "micromips") == 0) |
16454 | { | |
16455 | if (mips_opts.mips16 == 1) | |
16456 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16457 | mips_opts.micromips = 1; | |
16458 | } | |
16459 | else if (strcmp (name, "nomicromips") == 0) | |
16460 | mips_opts.micromips = 0; | |
c6278170 RS |
16461 | else if (name[0] == 'n' |
16462 | && name[1] == 'o' | |
16463 | && (ase = mips_lookup_ase (name + 2))) | |
16464 | mips_set_ase (ase, FALSE); | |
16465 | else if ((ase = mips_lookup_ase (name))) | |
16466 | mips_set_ase (ase, TRUE); | |
1a2c1fad | 16467 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16468 | { |
af7ee8bf | 16469 | int reset = 0; |
252b5132 | 16470 | |
1a2c1fad CD |
16471 | /* Permit the user to change the ISA and architecture on the fly. |
16472 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16473 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16474 | { |
16475 | reset = 1; | |
16476 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16477 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16478 | } |
16479 | else if (strncmp (name, "arch=", 5) == 0) | |
16480 | { | |
16481 | const struct mips_cpu_info *p; | |
16482 | ||
16483 | p = mips_parse_cpu("internal use", name + 5); | |
16484 | if (!p) | |
16485 | as_bad (_("unknown architecture %s"), name + 5); | |
16486 | else | |
16487 | { | |
16488 | mips_opts.arch = p->cpu; | |
16489 | mips_opts.isa = p->isa; | |
16490 | } | |
16491 | } | |
81a21e38 TS |
16492 | else if (strncmp (name, "mips", 4) == 0) |
16493 | { | |
16494 | const struct mips_cpu_info *p; | |
16495 | ||
16496 | p = mips_parse_cpu("internal use", name); | |
16497 | if (!p) | |
16498 | as_bad (_("unknown ISA level %s"), name + 4); | |
16499 | else | |
16500 | { | |
16501 | mips_opts.arch = p->cpu; | |
16502 | mips_opts.isa = p->isa; | |
16503 | } | |
16504 | } | |
af7ee8bf | 16505 | else |
81a21e38 | 16506 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16507 | |
16508 | switch (mips_opts.isa) | |
98d3f06f KH |
16509 | { |
16510 | case 0: | |
98d3f06f | 16511 | break; |
af7ee8bf CD |
16512 | case ISA_MIPS1: |
16513 | case ISA_MIPS2: | |
16514 | case ISA_MIPS32: | |
16515 | case ISA_MIPS32R2: | |
98d3f06f KH |
16516 | mips_opts.gp32 = 1; |
16517 | mips_opts.fp32 = 1; | |
16518 | break; | |
af7ee8bf CD |
16519 | case ISA_MIPS3: |
16520 | case ISA_MIPS4: | |
16521 | case ISA_MIPS5: | |
16522 | case ISA_MIPS64: | |
5f74bc13 | 16523 | case ISA_MIPS64R2: |
98d3f06f | 16524 | mips_opts.gp32 = 0; |
e407c74b NC |
16525 | if (mips_opts.arch == CPU_R5900) |
16526 | { | |
16527 | mips_opts.fp32 = 1; | |
16528 | } | |
16529 | else | |
16530 | { | |
98d3f06f | 16531 | mips_opts.fp32 = 0; |
e407c74b | 16532 | } |
98d3f06f KH |
16533 | break; |
16534 | default: | |
16535 | as_bad (_("unknown ISA level %s"), name + 4); | |
16536 | break; | |
16537 | } | |
af7ee8bf | 16538 | if (reset) |
98d3f06f | 16539 | { |
af7ee8bf CD |
16540 | mips_opts.gp32 = file_mips_gp32; |
16541 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16542 | } |
252b5132 RH |
16543 | } |
16544 | else if (strcmp (name, "autoextend") == 0) | |
16545 | mips_opts.noautoextend = 0; | |
16546 | else if (strcmp (name, "noautoextend") == 0) | |
16547 | mips_opts.noautoextend = 1; | |
16548 | else if (strcmp (name, "push") == 0) | |
16549 | { | |
16550 | struct mips_option_stack *s; | |
16551 | ||
16552 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16553 | s->next = mips_opts_stack; | |
16554 | s->options = mips_opts; | |
16555 | mips_opts_stack = s; | |
16556 | } | |
16557 | else if (strcmp (name, "pop") == 0) | |
16558 | { | |
16559 | struct mips_option_stack *s; | |
16560 | ||
16561 | s = mips_opts_stack; | |
16562 | if (s == NULL) | |
16563 | as_bad (_(".set pop with no .set push")); | |
16564 | else | |
16565 | { | |
16566 | /* If we're changing the reorder mode we need to handle | |
16567 | delay slots correctly. */ | |
16568 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16569 | start_noreorder (); |
252b5132 | 16570 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16571 | end_noreorder (); |
252b5132 RH |
16572 | |
16573 | mips_opts = s->options; | |
16574 | mips_opts_stack = s->next; | |
16575 | free (s); | |
16576 | } | |
16577 | } | |
aed1a261 RS |
16578 | else if (strcmp (name, "sym32") == 0) |
16579 | mips_opts.sym32 = TRUE; | |
16580 | else if (strcmp (name, "nosym32") == 0) | |
16581 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16582 | else if (strchr (name, ',')) |
16583 | { | |
16584 | /* Generic ".set" directive; use the generic handler. */ | |
16585 | *input_line_pointer = ch; | |
16586 | input_line_pointer = name; | |
16587 | s_set (0); | |
16588 | return; | |
16589 | } | |
252b5132 RH |
16590 | else |
16591 | { | |
16592 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16593 | } | |
c6278170 | 16594 | mips_check_isa_supports_ases (); |
252b5132 RH |
16595 | *input_line_pointer = ch; |
16596 | demand_empty_rest_of_line (); | |
16597 | } | |
16598 | ||
16599 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16600 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16601 | ||
16602 | static void | |
17a2f251 | 16603 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16604 | { |
16605 | mips_pic = SVR4_PIC; | |
143d77c5 | 16606 | mips_abicalls = TRUE; |
4d0d148d TS |
16607 | |
16608 | if (g_switch_seen && g_switch_value != 0) | |
16609 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16610 | g_switch_value = 0; | |
16611 | ||
252b5132 RH |
16612 | bfd_set_gp_size (stdoutput, 0); |
16613 | demand_empty_rest_of_line (); | |
16614 | } | |
16615 | ||
16616 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16617 | PIC code. It sets the $gp register for the function based on the | |
16618 | function address, which is in the register named in the argument. | |
16619 | This uses a relocation against _gp_disp, which is handled specially | |
16620 | by the linker. The result is: | |
16621 | lui $gp,%hi(_gp_disp) | |
16622 | addiu $gp,$gp,%lo(_gp_disp) | |
16623 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16624 | The .cpload argument is normally $25 == $t9. |
16625 | ||
16626 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16627 | lui $gp,%hi(__gnu_local_gp) |
16628 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16629 | and the argument is ignored. This saves an instruction, but the |
16630 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16631 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16632 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16633 | |
16634 | static void | |
17a2f251 | 16635 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16636 | { |
16637 | expressionS ex; | |
aa6975fb ILT |
16638 | int reg; |
16639 | int in_shared; | |
252b5132 | 16640 | |
6478892d TS |
16641 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16642 | .cpload is ignored. */ | |
16643 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16644 | { |
16645 | s_ignore (0); | |
16646 | return; | |
16647 | } | |
16648 | ||
a276b80c MR |
16649 | if (mips_opts.mips16) |
16650 | { | |
16651 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16652 | ignore_rest_of_line (); | |
16653 | return; | |
16654 | } | |
16655 | ||
d3ecfc59 | 16656 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16657 | if (mips_opts.noreorder == 0) |
16658 | as_warn (_(".cpload not in noreorder section")); | |
16659 | ||
aa6975fb ILT |
16660 | reg = tc_get_register (0); |
16661 | ||
16662 | /* If we need to produce a 64-bit address, we are better off using | |
16663 | the default instruction sequence. */ | |
aed1a261 | 16664 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16665 | |
252b5132 | 16666 | ex.X_op = O_symbol; |
bbe506e8 TS |
16667 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16668 | "__gnu_local_gp"); | |
252b5132 RH |
16669 | ex.X_op_symbol = NULL; |
16670 | ex.X_add_number = 0; | |
16671 | ||
16672 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16673 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16674 | |
8a75745d MR |
16675 | mips_mark_labels (); |
16676 | mips_assembling_insn = TRUE; | |
16677 | ||
584892a6 | 16678 | macro_start (); |
67c0d1eb RS |
16679 | macro_build_lui (&ex, mips_gp_register); |
16680 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16681 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16682 | if (in_shared) |
16683 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16684 | mips_gp_register, reg); | |
584892a6 | 16685 | macro_end (); |
252b5132 | 16686 | |
8a75745d | 16687 | mips_assembling_insn = FALSE; |
252b5132 RH |
16688 | demand_empty_rest_of_line (); |
16689 | } | |
16690 | ||
6478892d TS |
16691 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16692 | .cpsetup $reg1, offset|$reg2, label | |
16693 | ||
16694 | If offset is given, this results in: | |
16695 | sd $gp, offset($sp) | |
956cd1d6 | 16696 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16697 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16698 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16699 | |
16700 | If $reg2 is given, this results in: | |
16701 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16702 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16703 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16704 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16705 | $reg1 is normally $25 == $t9. |
16706 | ||
16707 | The -mno-shared option replaces the last three instructions with | |
16708 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16709 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16710 | |
6478892d | 16711 | static void |
17a2f251 | 16712 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16713 | { |
16714 | expressionS ex_off; | |
16715 | expressionS ex_sym; | |
16716 | int reg1; | |
6478892d | 16717 | |
8586fc66 | 16718 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16719 | We also need NewABI support. */ |
16720 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16721 | { | |
16722 | s_ignore (0); | |
16723 | return; | |
16724 | } | |
16725 | ||
a276b80c MR |
16726 | if (mips_opts.mips16) |
16727 | { | |
16728 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16729 | ignore_rest_of_line (); | |
16730 | return; | |
16731 | } | |
16732 | ||
6478892d TS |
16733 | reg1 = tc_get_register (0); |
16734 | SKIP_WHITESPACE (); | |
16735 | if (*input_line_pointer != ',') | |
16736 | { | |
16737 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16738 | return; | |
16739 | } | |
16740 | else | |
80245285 | 16741 | ++input_line_pointer; |
6478892d TS |
16742 | SKIP_WHITESPACE (); |
16743 | if (*input_line_pointer == '$') | |
80245285 TS |
16744 | { |
16745 | mips_cpreturn_register = tc_get_register (0); | |
16746 | mips_cpreturn_offset = -1; | |
16747 | } | |
6478892d | 16748 | else |
80245285 TS |
16749 | { |
16750 | mips_cpreturn_offset = get_absolute_expression (); | |
16751 | mips_cpreturn_register = -1; | |
16752 | } | |
6478892d TS |
16753 | SKIP_WHITESPACE (); |
16754 | if (*input_line_pointer != ',') | |
16755 | { | |
16756 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16757 | return; | |
16758 | } | |
16759 | else | |
f9419b05 | 16760 | ++input_line_pointer; |
6478892d | 16761 | SKIP_WHITESPACE (); |
f21f8242 | 16762 | expression (&ex_sym); |
6478892d | 16763 | |
8a75745d MR |
16764 | mips_mark_labels (); |
16765 | mips_assembling_insn = TRUE; | |
16766 | ||
584892a6 | 16767 | macro_start (); |
6478892d TS |
16768 | if (mips_cpreturn_register == -1) |
16769 | { | |
16770 | ex_off.X_op = O_constant; | |
16771 | ex_off.X_add_symbol = NULL; | |
16772 | ex_off.X_op_symbol = NULL; | |
16773 | ex_off.X_add_number = mips_cpreturn_offset; | |
16774 | ||
67c0d1eb | 16775 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16776 | BFD_RELOC_LO16, SP); |
6478892d TS |
16777 | } |
16778 | else | |
67c0d1eb | 16779 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16780 | mips_gp_register, 0); |
6478892d | 16781 | |
aed1a261 | 16782 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16783 | { |
df58fc94 | 16784 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16785 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16786 | BFD_RELOC_HI16_S); | |
16787 | ||
16788 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16789 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16790 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16791 | ||
16792 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16793 | mips_gp_register, reg1); | |
16794 | } | |
16795 | else | |
16796 | { | |
16797 | expressionS ex; | |
16798 | ||
16799 | ex.X_op = O_symbol; | |
4184909a | 16800 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16801 | ex.X_op_symbol = NULL; |
16802 | ex.X_add_number = 0; | |
6e1304d8 | 16803 | |
aa6975fb ILT |
16804 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16805 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16806 | ||
16807 | macro_build_lui (&ex, mips_gp_register); | |
16808 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16809 | mips_gp_register, BFD_RELOC_LO16); | |
16810 | } | |
f21f8242 | 16811 | |
584892a6 | 16812 | macro_end (); |
6478892d | 16813 | |
8a75745d | 16814 | mips_assembling_insn = FALSE; |
6478892d TS |
16815 | demand_empty_rest_of_line (); |
16816 | } | |
16817 | ||
16818 | static void | |
17a2f251 | 16819 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16820 | { |
16821 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16822 | .cplocal is ignored. */ |
6478892d TS |
16823 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16824 | { | |
16825 | s_ignore (0); | |
16826 | return; | |
16827 | } | |
16828 | ||
a276b80c MR |
16829 | if (mips_opts.mips16) |
16830 | { | |
16831 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16832 | ignore_rest_of_line (); | |
16833 | return; | |
16834 | } | |
16835 | ||
6478892d | 16836 | mips_gp_register = tc_get_register (0); |
85b51719 | 16837 | demand_empty_rest_of_line (); |
6478892d TS |
16838 | } |
16839 | ||
252b5132 RH |
16840 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16841 | offset from $sp. The offset is remembered, and after making a PIC | |
16842 | call $gp is restored from that location. */ | |
16843 | ||
16844 | static void | |
17a2f251 | 16845 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16846 | { |
16847 | expressionS ex; | |
252b5132 | 16848 | |
6478892d | 16849 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16850 | .cprestore is ignored. */ |
6478892d | 16851 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16852 | { |
16853 | s_ignore (0); | |
16854 | return; | |
16855 | } | |
16856 | ||
a276b80c MR |
16857 | if (mips_opts.mips16) |
16858 | { | |
16859 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16860 | ignore_rest_of_line (); | |
16861 | return; | |
16862 | } | |
16863 | ||
252b5132 | 16864 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16865 | mips_cprestore_valid = 1; |
252b5132 RH |
16866 | |
16867 | ex.X_op = O_constant; | |
16868 | ex.X_add_symbol = NULL; | |
16869 | ex.X_op_symbol = NULL; | |
16870 | ex.X_add_number = mips_cprestore_offset; | |
16871 | ||
8a75745d MR |
16872 | mips_mark_labels (); |
16873 | mips_assembling_insn = TRUE; | |
16874 | ||
584892a6 | 16875 | macro_start (); |
67c0d1eb RS |
16876 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16877 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16878 | macro_end (); |
252b5132 | 16879 | |
8a75745d | 16880 | mips_assembling_insn = FALSE; |
252b5132 RH |
16881 | demand_empty_rest_of_line (); |
16882 | } | |
16883 | ||
6478892d | 16884 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16885 | was given in the preceding .cpsetup, it results in: |
6478892d | 16886 | ld $gp, offset($sp) |
76b3015f | 16887 | |
6478892d | 16888 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16889 | daddu $gp, $reg2, $0 */ |
16890 | ||
6478892d | 16891 | static void |
17a2f251 | 16892 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16893 | { |
16894 | expressionS ex; | |
6478892d TS |
16895 | |
16896 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16897 | We also need NewABI support. */ | |
16898 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16899 | { | |
16900 | s_ignore (0); | |
16901 | return; | |
16902 | } | |
16903 | ||
a276b80c MR |
16904 | if (mips_opts.mips16) |
16905 | { | |
16906 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16907 | ignore_rest_of_line (); | |
16908 | return; | |
16909 | } | |
16910 | ||
8a75745d MR |
16911 | mips_mark_labels (); |
16912 | mips_assembling_insn = TRUE; | |
16913 | ||
584892a6 | 16914 | macro_start (); |
6478892d TS |
16915 | if (mips_cpreturn_register == -1) |
16916 | { | |
16917 | ex.X_op = O_constant; | |
16918 | ex.X_add_symbol = NULL; | |
16919 | ex.X_op_symbol = NULL; | |
16920 | ex.X_add_number = mips_cpreturn_offset; | |
16921 | ||
67c0d1eb | 16922 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16923 | } |
16924 | else | |
67c0d1eb | 16925 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16926 | mips_cpreturn_register, 0); |
584892a6 | 16927 | macro_end (); |
6478892d | 16928 | |
8a75745d | 16929 | mips_assembling_insn = FALSE; |
6478892d TS |
16930 | demand_empty_rest_of_line (); |
16931 | } | |
16932 | ||
d0f13682 CLT |
16933 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16934 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16935 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16936 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16937 | |
16938 | static void | |
d0f13682 CLT |
16939 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16940 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16941 | { |
16942 | expressionS ex; | |
16943 | char *p; | |
16944 | ||
16945 | expression (&ex); | |
16946 | ||
16947 | if (ex.X_op != O_symbol) | |
16948 | { | |
d0f13682 | 16949 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16950 | ignore_rest_of_line (); |
16951 | } | |
16952 | ||
16953 | p = frag_more (bytes); | |
16954 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16955 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16956 | demand_empty_rest_of_line (); |
de64cffd | 16957 | mips_clear_insn_labels (); |
741d6ea8 JM |
16958 | } |
16959 | ||
16960 | /* Handle .dtprelword. */ | |
16961 | ||
16962 | static void | |
16963 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16964 | { | |
d0f13682 | 16965 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16966 | } |
16967 | ||
16968 | /* Handle .dtpreldword. */ | |
16969 | ||
16970 | static void | |
16971 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16972 | { | |
d0f13682 CLT |
16973 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16974 | } | |
16975 | ||
16976 | /* Handle .tprelword. */ | |
16977 | ||
16978 | static void | |
16979 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16980 | { | |
16981 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16982 | } | |
16983 | ||
16984 | /* Handle .tpreldword. */ | |
16985 | ||
16986 | static void | |
16987 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16988 | { | |
16989 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16990 | } |
16991 | ||
6478892d TS |
16992 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16993 | code. It sets the offset to use in gp_rel relocations. */ | |
16994 | ||
16995 | static void | |
17a2f251 | 16996 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16997 | { |
16998 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16999 | We also need NewABI support. */ | |
17000 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17001 | { | |
17002 | s_ignore (0); | |
17003 | return; | |
17004 | } | |
17005 | ||
def2e0dd | 17006 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17007 | |
17008 | demand_empty_rest_of_line (); | |
17009 | } | |
17010 | ||
252b5132 RH |
17011 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17012 | code. It generates a 32 bit GP relative reloc. */ | |
17013 | ||
17014 | static void | |
17a2f251 | 17015 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17016 | { |
a8dbcb85 TS |
17017 | segment_info_type *si; |
17018 | struct insn_label_list *l; | |
252b5132 RH |
17019 | expressionS ex; |
17020 | char *p; | |
17021 | ||
17022 | /* When not generating PIC code, this is treated as .word. */ | |
17023 | if (mips_pic != SVR4_PIC) | |
17024 | { | |
17025 | s_cons (2); | |
17026 | return; | |
17027 | } | |
17028 | ||
a8dbcb85 TS |
17029 | si = seg_info (now_seg); |
17030 | l = si->label_list; | |
7d10b47d | 17031 | mips_emit_delays (); |
252b5132 | 17032 | if (auto_align) |
462427c4 | 17033 | mips_align (2, 0, l); |
252b5132 RH |
17034 | |
17035 | expression (&ex); | |
a1facbec | 17036 | mips_clear_insn_labels (); |
252b5132 RH |
17037 | |
17038 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17039 | { | |
17040 | as_bad (_("Unsupported use of .gpword")); | |
17041 | ignore_rest_of_line (); | |
17042 | } | |
17043 | ||
17044 | p = frag_more (4); | |
17a2f251 | 17045 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17046 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17047 | BFD_RELOC_GPREL32); |
252b5132 RH |
17048 | |
17049 | demand_empty_rest_of_line (); | |
17050 | } | |
17051 | ||
10181a0d | 17052 | static void |
17a2f251 | 17053 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17054 | { |
a8dbcb85 TS |
17055 | segment_info_type *si; |
17056 | struct insn_label_list *l; | |
10181a0d AO |
17057 | expressionS ex; |
17058 | char *p; | |
17059 | ||
17060 | /* When not generating PIC code, this is treated as .dword. */ | |
17061 | if (mips_pic != SVR4_PIC) | |
17062 | { | |
17063 | s_cons (3); | |
17064 | return; | |
17065 | } | |
17066 | ||
a8dbcb85 TS |
17067 | si = seg_info (now_seg); |
17068 | l = si->label_list; | |
7d10b47d | 17069 | mips_emit_delays (); |
10181a0d | 17070 | if (auto_align) |
462427c4 | 17071 | mips_align (3, 0, l); |
10181a0d AO |
17072 | |
17073 | expression (&ex); | |
a1facbec | 17074 | mips_clear_insn_labels (); |
10181a0d AO |
17075 | |
17076 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17077 | { | |
17078 | as_bad (_("Unsupported use of .gpdword")); | |
17079 | ignore_rest_of_line (); | |
17080 | } | |
17081 | ||
17082 | p = frag_more (8); | |
17a2f251 | 17083 | md_number_to_chars (p, 0, 8); |
a105a300 | 17084 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17085 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17086 | |
17087 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17088 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17089 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17090 | |
17091 | demand_empty_rest_of_line (); | |
17092 | } | |
17093 | ||
a3f278e2 CM |
17094 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17095 | tables. It generates a R_MIPS_EH reloc. */ | |
17096 | ||
17097 | static void | |
17098 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17099 | { | |
17100 | expressionS ex; | |
17101 | char *p; | |
17102 | ||
17103 | mips_emit_delays (); | |
17104 | ||
17105 | expression (&ex); | |
17106 | mips_clear_insn_labels (); | |
17107 | ||
17108 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17109 | { | |
17110 | as_bad (_("Unsupported use of .ehword")); | |
17111 | ignore_rest_of_line (); | |
17112 | } | |
17113 | ||
17114 | p = frag_more (4); | |
17115 | md_number_to_chars (p, 0, 4); | |
17116 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17117 | BFD_RELOC_MIPS_EH); | |
17118 | ||
17119 | demand_empty_rest_of_line (); | |
17120 | } | |
17121 | ||
252b5132 RH |
17122 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17123 | tables in SVR4 PIC code. */ | |
17124 | ||
17125 | static void | |
17a2f251 | 17126 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17127 | { |
252b5132 RH |
17128 | int reg; |
17129 | ||
10181a0d AO |
17130 | /* This is ignored when not generating SVR4 PIC code. */ |
17131 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17132 | { |
17133 | s_ignore (0); | |
17134 | return; | |
17135 | } | |
17136 | ||
8a75745d MR |
17137 | mips_mark_labels (); |
17138 | mips_assembling_insn = TRUE; | |
17139 | ||
252b5132 | 17140 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17141 | macro_start (); |
252b5132 | 17142 | reg = tc_get_register (0); |
67c0d1eb | 17143 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17144 | macro_end (); |
252b5132 | 17145 | |
8a75745d | 17146 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17147 | demand_empty_rest_of_line (); |
252b5132 RH |
17148 | } |
17149 | ||
17150 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17151 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17152 | such as generating jalx instructions when needed. We also make |
17153 | them odd for the duration of the assembly, in order to generate the | |
17154 | right sort of code. We will make them even in the adjust_symtab | |
17155 | routine, while leaving them marked. This is convenient for the | |
17156 | debugger and the disassembler. The linker knows to make them odd | |
17157 | again. */ | |
17158 | ||
17159 | static void | |
17a2f251 | 17160 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17161 | { |
df58fc94 | 17162 | mips_mark_labels (); |
252b5132 RH |
17163 | |
17164 | demand_empty_rest_of_line (); | |
17165 | } | |
17166 | ||
754e2bb9 RS |
17167 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17168 | implemented in a transparent way, so that removing them would not | |
17169 | have any effect on the generated instructions. However, s_stab | |
17170 | internally changes the section, so in practice we need to decide | |
17171 | now whether the preceding label marks compressed code. We do not | |
17172 | support changing the compression mode of a label after a .stab* | |
17173 | directive, such as in: | |
17174 | ||
17175 | foo: | |
17176 | .stabs ... | |
17177 | .set mips16 | |
17178 | ||
17179 | so the current mode wins. */ | |
252b5132 RH |
17180 | |
17181 | static void | |
17a2f251 | 17182 | s_mips_stab (int type) |
252b5132 | 17183 | { |
754e2bb9 | 17184 | mips_mark_labels (); |
252b5132 RH |
17185 | s_stab (type); |
17186 | } | |
17187 | ||
54f4ddb3 | 17188 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17189 | |
17190 | static void | |
17a2f251 | 17191 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17192 | { |
17193 | char *name; | |
17194 | int c; | |
17195 | symbolS *symbolP; | |
17196 | expressionS exp; | |
17197 | ||
17198 | name = input_line_pointer; | |
17199 | c = get_symbol_end (); | |
17200 | symbolP = symbol_find_or_make (name); | |
17201 | S_SET_WEAK (symbolP); | |
17202 | *input_line_pointer = c; | |
17203 | ||
17204 | SKIP_WHITESPACE (); | |
17205 | ||
17206 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17207 | { | |
17208 | if (S_IS_DEFINED (symbolP)) | |
17209 | { | |
20203fb9 | 17210 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17211 | S_GET_NAME (symbolP)); |
17212 | ignore_rest_of_line (); | |
17213 | return; | |
17214 | } | |
bdaaa2e1 | 17215 | |
252b5132 RH |
17216 | if (*input_line_pointer == ',') |
17217 | { | |
17218 | ++input_line_pointer; | |
17219 | SKIP_WHITESPACE (); | |
17220 | } | |
bdaaa2e1 | 17221 | |
252b5132 RH |
17222 | expression (&exp); |
17223 | if (exp.X_op != O_symbol) | |
17224 | { | |
20203fb9 | 17225 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17226 | ignore_rest_of_line (); |
252b5132 RH |
17227 | return; |
17228 | } | |
49309057 | 17229 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17230 | } |
17231 | ||
17232 | demand_empty_rest_of_line (); | |
17233 | } | |
17234 | ||
17235 | /* Parse a register string into a number. Called from the ECOFF code | |
17236 | to parse .frame. The argument is non-zero if this is the frame | |
17237 | register, so that we can record it in mips_frame_reg. */ | |
17238 | ||
17239 | int | |
17a2f251 | 17240 | tc_get_register (int frame) |
252b5132 | 17241 | { |
707bfff6 | 17242 | unsigned int reg; |
252b5132 RH |
17243 | |
17244 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17245 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17246 | reg = 0; | |
252b5132 | 17247 | if (frame) |
7a621144 DJ |
17248 | { |
17249 | mips_frame_reg = reg != 0 ? reg : SP; | |
17250 | mips_frame_reg_valid = 1; | |
17251 | mips_cprestore_valid = 0; | |
17252 | } | |
252b5132 RH |
17253 | return reg; |
17254 | } | |
17255 | ||
17256 | valueT | |
17a2f251 | 17257 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17258 | { |
17259 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17260 | ||
f3ded42a RS |
17261 | /* We don't need to align ELF sections to the full alignment. |
17262 | However, Irix 5 may prefer that we align them at least to a 16 | |
17263 | byte boundary. We don't bother to align the sections if we | |
17264 | are targeted for an embedded system. */ | |
17265 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17266 | return addr; | |
17267 | if (align > 4) | |
17268 | align = 4; | |
252b5132 RH |
17269 | |
17270 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17271 | } | |
17272 | ||
17273 | /* Utility routine, called from above as well. If called while the | |
17274 | input file is still being read, it's only an approximation. (For | |
17275 | example, a symbol may later become defined which appeared to be | |
17276 | undefined earlier.) */ | |
17277 | ||
17278 | static int | |
17a2f251 | 17279 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17280 | { |
17281 | if (sym == 0) | |
17282 | return 0; | |
17283 | ||
4d0d148d | 17284 | if (g_switch_value > 0) |
252b5132 RH |
17285 | { |
17286 | const char *symname; | |
17287 | int change; | |
17288 | ||
c9914766 | 17289 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17290 | register. It can be if it is smaller than the -G size or if |
17291 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17292 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17293 | they can. */ |
17294 | symname = S_GET_NAME (sym); | |
17295 | if (symname != (const char *) NULL | |
17296 | && (strcmp (symname, "eprol") == 0 | |
17297 | || strcmp (symname, "etext") == 0 | |
17298 | || strcmp (symname, "_gp") == 0 | |
17299 | || strcmp (symname, "edata") == 0 | |
17300 | || strcmp (symname, "_fbss") == 0 | |
17301 | || strcmp (symname, "_fdata") == 0 | |
17302 | || strcmp (symname, "_ftext") == 0 | |
17303 | || strcmp (symname, "end") == 0 | |
17304 | || strcmp (symname, "_gp_disp") == 0)) | |
17305 | change = 1; | |
17306 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17307 | && (0 | |
17308 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17309 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17310 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17311 | <= g_switch_value)) | |
252b5132 RH |
17312 | #endif |
17313 | /* We must defer this decision until after the whole | |
17314 | file has been read, since there might be a .extern | |
17315 | after the first use of this symbol. */ | |
17316 | || (before_relaxing | |
17317 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17318 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17319 | #endif |
17320 | && S_GET_VALUE (sym) == 0) | |
17321 | || (S_GET_VALUE (sym) != 0 | |
17322 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17323 | change = 0; | |
17324 | else | |
17325 | { | |
17326 | const char *segname; | |
17327 | ||
17328 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17329 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17330 | && strcmp (segname, ".lit4") != 0); |
17331 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17332 | && strcmp (segname, ".sbss") != 0 |
17333 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17334 | && strncmp (segname, ".sbss.", 6) != 0 |
17335 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17336 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17337 | } |
17338 | return change; | |
17339 | } | |
17340 | else | |
c9914766 | 17341 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17342 | return 1; |
17343 | } | |
17344 | ||
5919d012 RS |
17345 | |
17346 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17347 | ||
17348 | static bfd_boolean | |
17a2f251 | 17349 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17350 | { |
17351 | asection *symsec; | |
5919d012 RS |
17352 | |
17353 | /* Handle the case of a symbol equated to another symbol. */ | |
17354 | while (symbol_equated_reloc_p (sym)) | |
17355 | { | |
17356 | symbolS *n; | |
17357 | ||
5f0fe04b | 17358 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17359 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17360 | if (n == sym) | |
17361 | break; | |
17362 | sym = n; | |
17363 | } | |
17364 | ||
df1f3cda DD |
17365 | if (symbol_section_p (sym)) |
17366 | return TRUE; | |
17367 | ||
5919d012 RS |
17368 | symsec = S_GET_SEGMENT (sym); |
17369 | ||
5919d012 | 17370 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17371 | return (!bfd_is_und_section (symsec) |
17372 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17373 | && !bfd_is_com_section (symsec) |
17374 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 17375 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17376 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
17377 | } |
17378 | ||
17379 | ||
252b5132 RH |
17380 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17381 | extended opcode. SEC is the section the frag is in. */ | |
17382 | ||
17383 | static int | |
17a2f251 | 17384 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17385 | { |
17386 | int type; | |
3994f87e | 17387 | const struct mips16_immed_operand *op; |
252b5132 RH |
17388 | offsetT val; |
17389 | int mintiny, maxtiny; | |
17390 | segT symsec; | |
98aa84af | 17391 | fragS *sym_frag; |
252b5132 RH |
17392 | |
17393 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17394 | return 0; | |
17395 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17396 | return 1; | |
17397 | ||
17398 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17399 | op = mips16_immed_operands; | |
17400 | while (op->type != type) | |
17401 | { | |
17402 | ++op; | |
9c2799c2 | 17403 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17404 | } |
17405 | ||
17406 | if (op->unsp) | |
17407 | { | |
17408 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17409 | { | |
17410 | mintiny = 1; | |
17411 | maxtiny = 1 << op->nbits; | |
17412 | } | |
17413 | else | |
17414 | { | |
17415 | mintiny = 0; | |
17416 | maxtiny = (1 << op->nbits) - 1; | |
17417 | } | |
17418 | } | |
17419 | else | |
17420 | { | |
17421 | mintiny = - (1 << (op->nbits - 1)); | |
17422 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17423 | } | |
17424 | ||
98aa84af | 17425 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17426 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17427 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17428 | |
17429 | if (op->pcrel) | |
17430 | { | |
17431 | addressT addr; | |
17432 | ||
17433 | /* We won't have the section when we are called from | |
17434 | mips_relax_frag. However, we will always have been called | |
17435 | from md_estimate_size_before_relax first. If this is a | |
17436 | branch to a different section, we mark it as such. If SEC is | |
17437 | NULL, and the frag is not marked, then it must be a branch to | |
17438 | the same section. */ | |
17439 | if (sec == NULL) | |
17440 | { | |
17441 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17442 | return 1; | |
17443 | } | |
17444 | else | |
17445 | { | |
98aa84af | 17446 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17447 | if (symsec != sec) |
17448 | { | |
17449 | fragp->fr_subtype = | |
17450 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17451 | ||
17452 | /* FIXME: We should support this, and let the linker | |
17453 | catch branches and loads that are out of range. */ | |
17454 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17455 | _("unsupported PC relative reference to different section")); | |
17456 | ||
17457 | return 1; | |
17458 | } | |
98aa84af AM |
17459 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17460 | /* Assume non-extended on the first relaxation pass. | |
17461 | The address we have calculated will be bogus if this is | |
17462 | a forward branch to another frag, as the forward frag | |
17463 | will have fr_address == 0. */ | |
17464 | return 0; | |
252b5132 RH |
17465 | } |
17466 | ||
17467 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17468 | the same section. If the relax_marker of the symbol fragment |
17469 | differs from the relax_marker of this fragment, we have not | |
17470 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17471 | in STRETCH in order to get a better estimate of the address. |
17472 | This particularly matters because of the shift bits. */ | |
17473 | if (stretch != 0 | |
98aa84af | 17474 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17475 | { |
17476 | fragS *f; | |
17477 | ||
17478 | /* Adjust stretch for any alignment frag. Note that if have | |
17479 | been expanding the earlier code, the symbol may be | |
17480 | defined in what appears to be an earlier frag. FIXME: | |
17481 | This doesn't handle the fr_subtype field, which specifies | |
17482 | a maximum number of bytes to skip when doing an | |
17483 | alignment. */ | |
98aa84af | 17484 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17485 | { |
17486 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17487 | { | |
17488 | if (stretch < 0) | |
17489 | stretch = - ((- stretch) | |
17490 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17491 | else | |
17492 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17493 | if (stretch == 0) | |
17494 | break; | |
17495 | } | |
17496 | } | |
17497 | if (f != NULL) | |
17498 | val += stretch; | |
17499 | } | |
17500 | ||
17501 | addr = fragp->fr_address + fragp->fr_fix; | |
17502 | ||
17503 | /* The base address rules are complicated. The base address of | |
17504 | a branch is the following instruction. The base address of a | |
17505 | PC relative load or add is the instruction itself, but if it | |
17506 | is in a delay slot (in which case it can not be extended) use | |
17507 | the address of the instruction whose delay slot it is in. */ | |
17508 | if (type == 'p' || type == 'q') | |
17509 | { | |
17510 | addr += 2; | |
17511 | ||
17512 | /* If we are currently assuming that this frag should be | |
17513 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17514 | higher. */ |
252b5132 RH |
17515 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17516 | addr += 2; | |
17517 | ||
17518 | /* Ignore the low bit in the target, since it will be set | |
17519 | for a text label. */ | |
17520 | if ((val & 1) != 0) | |
17521 | --val; | |
17522 | } | |
17523 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17524 | addr -= 4; | |
17525 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17526 | addr -= 2; | |
17527 | ||
17528 | val -= addr & ~ ((1 << op->shift) - 1); | |
17529 | ||
17530 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17531 | if (type == 'p' || type == 'q') | |
17532 | val /= 2; | |
17533 | ||
17534 | /* If any of the shifted bits are set, we must use an extended | |
17535 | opcode. If the address depends on the size of this | |
17536 | instruction, this can lead to a loop, so we arrange to always | |
17537 | use an extended opcode. We only check this when we are in | |
17538 | the main relaxation loop, when SEC is NULL. */ | |
17539 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17540 | { | |
17541 | fragp->fr_subtype = | |
17542 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17543 | return 1; | |
17544 | } | |
17545 | ||
17546 | /* If we are about to mark a frag as extended because the value | |
17547 | is precisely maxtiny + 1, then there is a chance of an | |
17548 | infinite loop as in the following code: | |
17549 | la $4,foo | |
17550 | .skip 1020 | |
17551 | .align 2 | |
17552 | foo: | |
17553 | In this case when the la is extended, foo is 0x3fc bytes | |
17554 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17555 | the la must be extended. To avoid this loop, we mark the | |
17556 | frag as extended if it was small, and is about to become | |
17557 | extended with a value of maxtiny + 1. */ | |
17558 | if (val == ((maxtiny + 1) << op->shift) | |
17559 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17560 | && sec == NULL) | |
17561 | { | |
17562 | fragp->fr_subtype = | |
17563 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17564 | return 1; | |
17565 | } | |
17566 | } | |
17567 | else if (symsec != absolute_section && sec != NULL) | |
17568 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17569 | ||
17570 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17571 | || val < (mintiny << op->shift) | |
17572 | || val > (maxtiny << op->shift)) | |
17573 | return 1; | |
17574 | else | |
17575 | return 0; | |
17576 | } | |
17577 | ||
4a6a3df4 AO |
17578 | /* Compute the length of a branch sequence, and adjust the |
17579 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17580 | worst-case length is computed, with UPDATE being used to indicate | |
17581 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17582 | branch is to be computed. */ | |
17583 | static int | |
17a2f251 | 17584 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17585 | { |
b34976b6 | 17586 | bfd_boolean toofar; |
4a6a3df4 AO |
17587 | int length; |
17588 | ||
17589 | if (fragp | |
17590 | && S_IS_DEFINED (fragp->fr_symbol) | |
17591 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17592 | { | |
17593 | addressT addr; | |
17594 | offsetT val; | |
17595 | ||
17596 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17597 | ||
17598 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17599 | ||
17600 | val -= addr; | |
17601 | ||
17602 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17603 | } | |
17604 | else if (fragp) | |
17605 | /* If the symbol is not defined or it's in a different segment, | |
17606 | assume the user knows what's going on and emit a short | |
17607 | branch. */ | |
b34976b6 | 17608 | toofar = FALSE; |
4a6a3df4 | 17609 | else |
b34976b6 | 17610 | toofar = TRUE; |
4a6a3df4 AO |
17611 | |
17612 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17613 | fragp->fr_subtype | |
66b3e8da MR |
17614 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17615 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17616 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17617 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17618 | toofar); | |
17619 | ||
17620 | length = 4; | |
17621 | if (toofar) | |
17622 | { | |
17623 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17624 | length += 8; | |
17625 | ||
17626 | if (mips_pic != NO_PIC) | |
17627 | { | |
17628 | /* Additional space for PIC loading of target address. */ | |
17629 | length += 8; | |
17630 | if (mips_opts.isa == ISA_MIPS1) | |
17631 | /* Additional space for $at-stabilizing nop. */ | |
17632 | length += 4; | |
17633 | } | |
17634 | ||
17635 | /* If branch is conditional. */ | |
17636 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17637 | length += 8; | |
17638 | } | |
b34976b6 | 17639 | |
4a6a3df4 AO |
17640 | return length; |
17641 | } | |
17642 | ||
df58fc94 RS |
17643 | /* Compute the length of a branch sequence, and adjust the |
17644 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17645 | worst-case length is computed, with UPDATE being used to indicate | |
17646 | whether an unconditional (-1), or regular (0) branch is to be | |
17647 | computed. */ | |
17648 | ||
17649 | static int | |
17650 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17651 | { | |
17652 | bfd_boolean toofar; | |
17653 | int length; | |
17654 | ||
17655 | if (fragp | |
17656 | && S_IS_DEFINED (fragp->fr_symbol) | |
17657 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17658 | { | |
17659 | addressT addr; | |
17660 | offsetT val; | |
17661 | ||
17662 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17663 | /* Ignore the low bit in the target, since it will be set | |
17664 | for a text label. */ | |
17665 | if ((val & 1) != 0) | |
17666 | --val; | |
17667 | ||
17668 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17669 | ||
17670 | val -= addr; | |
17671 | ||
17672 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17673 | } | |
17674 | else if (fragp) | |
17675 | /* If the symbol is not defined or it's in a different segment, | |
17676 | assume the user knows what's going on and emit a short | |
17677 | branch. */ | |
17678 | toofar = FALSE; | |
17679 | else | |
17680 | toofar = TRUE; | |
17681 | ||
17682 | if (fragp && update | |
17683 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17684 | fragp->fr_subtype = (toofar | |
17685 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17686 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17687 | ||
17688 | length = 4; | |
17689 | if (toofar) | |
17690 | { | |
17691 | bfd_boolean compact_known = fragp != NULL; | |
17692 | bfd_boolean compact = FALSE; | |
17693 | bfd_boolean uncond; | |
17694 | ||
17695 | if (compact_known) | |
17696 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17697 | if (fragp) | |
17698 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17699 | else | |
17700 | uncond = update < 0; | |
17701 | ||
17702 | /* If label is out of range, we turn branch <br>: | |
17703 | ||
17704 | <br> label # 4 bytes | |
17705 | 0: | |
17706 | ||
17707 | into: | |
17708 | ||
17709 | j label # 4 bytes | |
17710 | nop # 2 bytes if compact && !PIC | |
17711 | 0: | |
17712 | */ | |
17713 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17714 | length += 2; | |
17715 | ||
17716 | /* If assembling PIC code, we further turn: | |
17717 | ||
17718 | j label # 4 bytes | |
17719 | ||
17720 | into: | |
17721 | ||
17722 | lw/ld at, %got(label)(gp) # 4 bytes | |
17723 | d/addiu at, %lo(label) # 4 bytes | |
17724 | jr/c at # 2 bytes | |
17725 | */ | |
17726 | if (mips_pic != NO_PIC) | |
17727 | length += 6; | |
17728 | ||
17729 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17730 | ||
17731 | <brneg> 0f # 4 bytes | |
17732 | nop # 2 bytes if !compact | |
17733 | */ | |
17734 | if (!uncond) | |
17735 | length += (compact_known && compact) ? 4 : 6; | |
17736 | } | |
17737 | ||
17738 | return length; | |
17739 | } | |
17740 | ||
17741 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17742 | bit accordingly. */ | |
17743 | ||
17744 | static int | |
17745 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17746 | { | |
17747 | bfd_boolean toofar; | |
17748 | ||
df58fc94 RS |
17749 | if (fragp |
17750 | && S_IS_DEFINED (fragp->fr_symbol) | |
17751 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17752 | { | |
17753 | addressT addr; | |
17754 | offsetT val; | |
17755 | int type; | |
17756 | ||
17757 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17758 | /* Ignore the low bit in the target, since it will be set | |
17759 | for a text label. */ | |
17760 | if ((val & 1) != 0) | |
17761 | --val; | |
17762 | ||
17763 | /* Assume this is a 2-byte branch. */ | |
17764 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17765 | ||
17766 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17767 | long branches. */ | |
17768 | ||
17769 | val -= addr; | |
17770 | ||
17771 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17772 | if (type == 'D') | |
17773 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17774 | else if (type == 'E') | |
17775 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17776 | else | |
17777 | abort (); | |
17778 | } | |
17779 | else | |
17780 | /* If the symbol is not defined or it's in a different segment, | |
17781 | we emit a normal 32-bit branch. */ | |
17782 | toofar = TRUE; | |
17783 | ||
17784 | if (fragp && update | |
17785 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17786 | fragp->fr_subtype | |
17787 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17788 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17789 | ||
17790 | if (toofar) | |
17791 | return 4; | |
17792 | ||
17793 | return 2; | |
17794 | } | |
17795 | ||
252b5132 RH |
17796 | /* Estimate the size of a frag before relaxing. Unless this is the |
17797 | mips16, we are not really relaxing here, and the final size is | |
17798 | encoded in the subtype information. For the mips16, we have to | |
17799 | decide whether we are using an extended opcode or not. */ | |
17800 | ||
252b5132 | 17801 | int |
17a2f251 | 17802 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17803 | { |
5919d012 | 17804 | int change; |
252b5132 | 17805 | |
4a6a3df4 AO |
17806 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17807 | { | |
17808 | ||
b34976b6 AM |
17809 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17810 | ||
4a6a3df4 AO |
17811 | return fragp->fr_var; |
17812 | } | |
17813 | ||
252b5132 | 17814 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17815 | /* We don't want to modify the EXTENDED bit here; it might get us |
17816 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17817 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17818 | |
df58fc94 RS |
17819 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17820 | { | |
17821 | int length = 4; | |
17822 | ||
17823 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17824 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17825 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17826 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17827 | fragp->fr_var = length; | |
17828 | ||
17829 | return length; | |
17830 | } | |
17831 | ||
252b5132 | 17832 | if (mips_pic == NO_PIC) |
5919d012 | 17833 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17834 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17835 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17836 | else if (mips_pic == VXWORKS_PIC) |
17837 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17838 | change = 0; | |
252b5132 RH |
17839 | else |
17840 | abort (); | |
17841 | ||
17842 | if (change) | |
17843 | { | |
4d7206a2 | 17844 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17845 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17846 | } |
4d7206a2 RS |
17847 | else |
17848 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17849 | } |
17850 | ||
17851 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17852 | should be converted into a reloc against a section. */ |
252b5132 RH |
17853 | |
17854 | int | |
17a2f251 | 17855 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17856 | { |
252b5132 RH |
17857 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17858 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17859 | return 0; | |
a161fe53 | 17860 | |
252b5132 RH |
17861 | if (fixp->fx_addsy == NULL) |
17862 | return 1; | |
a161fe53 | 17863 | |
de7e6852 RS |
17864 | /* If symbol SYM is in a mergeable section, relocations of the form |
17865 | SYM + 0 can usually be made section-relative. The mergeable data | |
17866 | is then identified by the section offset rather than by the symbol. | |
17867 | ||
17868 | However, if we're generating REL LO16 relocations, the offset is split | |
17869 | between the LO16 and parterning high part relocation. The linker will | |
17870 | need to recalculate the complete offset in order to correctly identify | |
17871 | the merge data. | |
17872 | ||
17873 | The linker has traditionally not looked for the parterning high part | |
17874 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17875 | placed anywhere. Rather than break backwards compatibility by changing | |
17876 | this, it seems better not to force the issue, and instead keep the | |
17877 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17878 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17879 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17880 | && HAVE_IN_PLACE_ADDENDS |
17881 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17882 | return 0; | |
17883 | ||
ce70d90a | 17884 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17885 | Likewise an in-range offset of limited PC-relative relocations may |
17886 | overflow the in-place relocatable field if recalculated against the | |
17887 | start address of the symbol's containing section. */ | |
ce70d90a | 17888 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17889 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17890 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17891 | return 0; |
17892 | ||
b314ec0e RS |
17893 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17894 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17895 | relocations against MIPS16 functions; in this case, the stub becomes | |
17896 | the function's canonical address. | |
17897 | ||
17898 | Floating-point stubs are stored in unique .mips16.call.* or | |
17899 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17900 | the first relocation in section S must be against F; this is how the | |
17901 | linker determines the target function. All relocations that might | |
17902 | resolve to T must also be against F. We therefore have the following | |
17903 | restrictions, which are given in an intentionally-redundant way: | |
17904 | ||
17905 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17906 | symbols. | |
17907 | ||
17908 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17909 | if that stub might be used. | |
17910 | ||
17911 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17912 | symbols. | |
17913 | ||
17914 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17915 | that stub might be used. | |
17916 | ||
17917 | There is a further restriction: | |
17918 | ||
df58fc94 RS |
17919 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17920 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17921 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17922 | encode the low bit. |
17923 | ||
df58fc94 RS |
17924 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17925 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17926 | such relocations on REL targets. | |
b314ec0e RS |
17927 | |
17928 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17929 | relocation against some symbol R, no relocation against R may be | |
17930 | reduced. (Note that this deals with (2) as well as (1) because | |
17931 | relocations against global symbols will never be reduced on ELF | |
17932 | targets.) This approach is a little simpler than trying to detect | |
17933 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17934 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17935 | if (fixp->fx_subsy == NULL |
30c09090 | 17936 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17937 | || *symbol_get_tc (fixp->fx_addsy) |
17938 | || (HAVE_IN_PLACE_ADDENDS | |
17939 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17940 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 17941 | return 0; |
a161fe53 | 17942 | |
252b5132 RH |
17943 | return 1; |
17944 | } | |
17945 | ||
17946 | /* Translate internal representation of relocation info to BFD target | |
17947 | format. */ | |
17948 | ||
17949 | arelent ** | |
17a2f251 | 17950 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17951 | { |
17952 | static arelent *retval[4]; | |
17953 | arelent *reloc; | |
17954 | bfd_reloc_code_real_type code; | |
17955 | ||
4b0cff4e TS |
17956 | memset (retval, 0, sizeof(retval)); |
17957 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17958 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17959 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17960 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17961 | ||
bad36eac DJ |
17962 | if (fixp->fx_pcrel) |
17963 | { | |
df58fc94 RS |
17964 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17965 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17966 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
17967 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
17968 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
17969 | |
17970 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17971 | Relocations want only the symbol offset. */ | |
17972 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
17973 | } |
17974 | else | |
17975 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17976 | |
438c16b8 TS |
17977 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17978 | entry to be used in the relocation's section offset. */ | |
17979 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17980 | { |
17981 | reloc->address = reloc->addend; | |
17982 | reloc->addend = 0; | |
17983 | } | |
17984 | ||
252b5132 | 17985 | code = fixp->fx_r_type; |
252b5132 | 17986 | |
bad36eac | 17987 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17988 | if (reloc->howto == NULL) |
17989 | { | |
17990 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17991 | _("Can not represent %s relocation in this object file format"), | |
17992 | bfd_get_reloc_code_name (code)); | |
17993 | retval[0] = NULL; | |
17994 | } | |
17995 | ||
17996 | return retval; | |
17997 | } | |
17998 | ||
17999 | /* Relax a machine dependent frag. This returns the amount by which | |
18000 | the current size of the frag should change. */ | |
18001 | ||
18002 | int | |
17a2f251 | 18003 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18004 | { |
4a6a3df4 AO |
18005 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18006 | { | |
18007 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18008 | |
18009 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18010 | |
18011 | return fragp->fr_var - old_var; | |
18012 | } | |
18013 | ||
df58fc94 RS |
18014 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18015 | { | |
18016 | offsetT old_var = fragp->fr_var; | |
18017 | offsetT new_var = 4; | |
18018 | ||
18019 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18020 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18021 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18022 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18023 | fragp->fr_var = new_var; | |
18024 | ||
18025 | return new_var - old_var; | |
18026 | } | |
18027 | ||
252b5132 RH |
18028 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18029 | return 0; | |
18030 | ||
c4e7957c | 18031 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18032 | { |
18033 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18034 | return 0; | |
18035 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18036 | return 2; | |
18037 | } | |
18038 | else | |
18039 | { | |
18040 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18041 | return 0; | |
18042 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18043 | return -2; | |
18044 | } | |
18045 | ||
18046 | return 0; | |
18047 | } | |
18048 | ||
18049 | /* Convert a machine dependent frag. */ | |
18050 | ||
18051 | void | |
17a2f251 | 18052 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18053 | { |
4a6a3df4 AO |
18054 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18055 | { | |
4d68580a | 18056 | char *buf; |
4a6a3df4 AO |
18057 | unsigned long insn; |
18058 | expressionS exp; | |
18059 | fixS *fixp; | |
b34976b6 | 18060 | |
4d68580a RS |
18061 | buf = fragp->fr_literal + fragp->fr_fix; |
18062 | insn = read_insn (buf); | |
b34976b6 | 18063 | |
4a6a3df4 AO |
18064 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18065 | { | |
18066 | /* We generate a fixup instead of applying it right now | |
18067 | because, if there are linker relaxations, we're going to | |
18068 | need the relocations. */ | |
18069 | exp.X_op = O_symbol; | |
18070 | exp.X_add_symbol = fragp->fr_symbol; | |
18071 | exp.X_add_number = fragp->fr_offset; | |
18072 | ||
4d68580a RS |
18073 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18074 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18075 | fixp->fx_file = fragp->fr_file; |
18076 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18077 | |
4d68580a | 18078 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18079 | } |
18080 | else | |
18081 | { | |
18082 | int i; | |
18083 | ||
18084 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18085 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18086 | |
18087 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18088 | goto uncond; | |
18089 | ||
18090 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18091 | { | |
18092 | /* Reverse the branch. */ | |
18093 | switch ((insn >> 28) & 0xf) | |
18094 | { | |
18095 | case 4: | |
3bf0dbfb MR |
18096 | /* bc[0-3][tf]l? instructions can have the condition |
18097 | reversed by tweaking a single TF bit, and their | |
18098 | opcodes all have 0x4???????. */ | |
18099 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18100 | insn ^= 0x00010000; |
18101 | break; | |
18102 | ||
18103 | case 0: | |
18104 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18105 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18106 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18107 | insn ^= 0x00010000; |
18108 | break; | |
b34976b6 | 18109 | |
4a6a3df4 AO |
18110 | case 1: |
18111 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18112 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18113 | insn ^= 0x04000000; |
18114 | break; | |
18115 | ||
18116 | default: | |
18117 | abort (); | |
18118 | } | |
18119 | } | |
18120 | ||
18121 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18122 | { | |
18123 | /* Clear the and-link bit. */ | |
9c2799c2 | 18124 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18125 | |
54f4ddb3 TS |
18126 | /* bltzal 0x04100000 bgezal 0x04110000 |
18127 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18128 | insn &= ~0x00100000; |
18129 | } | |
18130 | ||
18131 | /* Branch over the branch (if the branch was likely) or the | |
18132 | full jump (not likely case). Compute the offset from the | |
18133 | current instruction to branch to. */ | |
18134 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18135 | i = 16; | |
18136 | else | |
18137 | { | |
18138 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18139 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18140 | /* How many bytes in instructions from here to the end? */ |
18141 | i = fragp->fr_var - i; | |
18142 | } | |
18143 | /* Convert to instruction count. */ | |
18144 | i >>= 2; | |
18145 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18146 | i--; |
4a6a3df4 AO |
18147 | insn |= i; |
18148 | /* Branch over the jump. */ | |
4d68580a | 18149 | buf = write_insn (buf, insn); |
4a6a3df4 | 18150 | |
54f4ddb3 | 18151 | /* nop */ |
4d68580a | 18152 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18153 | |
18154 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18155 | { | |
18156 | /* beql $0, $0, 2f */ | |
18157 | insn = 0x50000000; | |
18158 | /* Compute the PC offset from the current instruction to | |
18159 | the end of the variable frag. */ | |
18160 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18161 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18162 | /* How many bytes in instructions from here to the end? */ |
18163 | i = fragp->fr_var - i; | |
18164 | /* Convert to instruction count. */ | |
18165 | i >>= 2; | |
18166 | /* Don't decrement i, because we want to branch over the | |
18167 | delay slot. */ | |
4a6a3df4 | 18168 | insn |= i; |
4a6a3df4 | 18169 | |
4d68580a RS |
18170 | buf = write_insn (buf, insn); |
18171 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18172 | } |
18173 | ||
18174 | uncond: | |
18175 | if (mips_pic == NO_PIC) | |
18176 | { | |
18177 | /* j or jal. */ | |
18178 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18179 | ? 0x0c000000 : 0x08000000); | |
18180 | exp.X_op = O_symbol; | |
18181 | exp.X_add_symbol = fragp->fr_symbol; | |
18182 | exp.X_add_number = fragp->fr_offset; | |
18183 | ||
4d68580a RS |
18184 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18185 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18186 | fixp->fx_file = fragp->fr_file; |
18187 | fixp->fx_line = fragp->fr_line; | |
18188 | ||
4d68580a | 18189 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18190 | } |
18191 | else | |
18192 | { | |
66b3e8da MR |
18193 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18194 | ||
4a6a3df4 | 18195 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18196 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18197 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18198 | exp.X_op = O_symbol; |
18199 | exp.X_add_symbol = fragp->fr_symbol; | |
18200 | exp.X_add_number = fragp->fr_offset; | |
18201 | ||
18202 | if (fragp->fr_offset) | |
18203 | { | |
18204 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18205 | exp.X_add_number = 0; | |
18206 | } | |
18207 | ||
4d68580a RS |
18208 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18209 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18210 | fixp->fx_file = fragp->fr_file; |
18211 | fixp->fx_line = fragp->fr_line; | |
18212 | ||
4d68580a | 18213 | buf = write_insn (buf, insn); |
b34976b6 | 18214 | |
4a6a3df4 | 18215 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18216 | /* nop */ |
18217 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18218 | |
18219 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18220 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18221 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18222 | |
4d68580a RS |
18223 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18224 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18225 | fixp->fx_file = fragp->fr_file; |
18226 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18227 | |
4d68580a | 18228 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18229 | |
18230 | /* j(al)r $at. */ | |
18231 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18232 | insn = 0x0000f809; |
4a6a3df4 | 18233 | else |
66b3e8da MR |
18234 | insn = 0x00000008; |
18235 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18236 | |
4d68580a | 18237 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18238 | } |
18239 | } | |
18240 | ||
4a6a3df4 | 18241 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18242 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18243 | return; |
18244 | } | |
18245 | ||
df58fc94 RS |
18246 | /* Relax microMIPS branches. */ |
18247 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18248 | { | |
4d68580a | 18249 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18250 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18251 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18252 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18253 | bfd_boolean short_ds; |
df58fc94 RS |
18254 | unsigned long insn; |
18255 | expressionS exp; | |
18256 | fixS *fixp; | |
18257 | ||
18258 | exp.X_op = O_symbol; | |
18259 | exp.X_add_symbol = fragp->fr_symbol; | |
18260 | exp.X_add_number = fragp->fr_offset; | |
18261 | ||
18262 | fragp->fr_fix += fragp->fr_var; | |
18263 | ||
18264 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18265 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18266 | { | |
18267 | /* We generate a fixup instead of applying it right now, | |
18268 | because if there is linker relaxation, we're going to | |
18269 | need the relocations. */ | |
18270 | if (type == 'D') | |
4d68580a | 18271 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18272 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18273 | else if (type == 'E') | |
4d68580a | 18274 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18275 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18276 | else | |
18277 | abort (); | |
18278 | ||
18279 | fixp->fx_file = fragp->fr_file; | |
18280 | fixp->fx_line = fragp->fr_line; | |
18281 | ||
18282 | /* These relocations can have an addend that won't fit in | |
18283 | 2 octets. */ | |
18284 | fixp->fx_no_overflow = 1; | |
18285 | ||
18286 | return; | |
18287 | } | |
18288 | ||
2309ddf2 | 18289 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18290 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18291 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18292 | { | |
18293 | /* We generate a fixup instead of applying it right now, | |
18294 | because if there is linker relaxation, we're going to | |
18295 | need the relocations. */ | |
4d68580a RS |
18296 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18297 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18298 | fixp->fx_file = fragp->fr_file; |
18299 | fixp->fx_line = fragp->fr_line; | |
18300 | ||
18301 | if (type == 0) | |
18302 | return; | |
18303 | } | |
18304 | ||
18305 | /* Relax 16-bit branches to 32-bit branches. */ | |
18306 | if (type != 0) | |
18307 | { | |
4d68580a | 18308 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18309 | |
18310 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18311 | insn = 0x94000000; /* beq */ | |
18312 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18313 | { | |
18314 | unsigned long regno; | |
18315 | ||
18316 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18317 | regno = micromips_to_32_reg_d_map [regno]; | |
18318 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18319 | insn |= regno << MICROMIPSOP_SH_RS; | |
18320 | } | |
18321 | else | |
18322 | abort (); | |
18323 | ||
18324 | /* Nothing else to do, just write it out. */ | |
18325 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18326 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18327 | { | |
4d68580a RS |
18328 | buf = write_compressed_insn (buf, insn, 4); |
18329 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18330 | return; |
18331 | } | |
18332 | } | |
18333 | else | |
4d68580a | 18334 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18335 | |
18336 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18337 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18338 | _("Relaxed out-of-range branch into a jump")); | |
18339 | ||
2309ddf2 MR |
18340 | /* Set the short-delay-slot bit. */ |
18341 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18342 | |
18343 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18344 | { | |
18345 | symbolS *l; | |
18346 | ||
18347 | /* Reverse the branch. */ | |
18348 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18349 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18350 | insn ^= 0x20000000; | |
18351 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18352 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18353 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18354 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18355 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18356 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18357 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18358 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18359 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18360 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18361 | insn ^= 0x00400000; | |
18362 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18363 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18364 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18365 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18366 | insn ^= 0x00200000; | |
18367 | else | |
18368 | abort (); | |
18369 | ||
18370 | if (al) | |
18371 | { | |
18372 | /* Clear the and-link and short-delay-slot bits. */ | |
18373 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18374 | ||
18375 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18376 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18377 | insn &= ~0x02200000; | |
18378 | } | |
18379 | ||
18380 | /* Make a label at the end for use with the branch. */ | |
18381 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18382 | micromips_label_inc (); | |
f3ded42a | 18383 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18384 | |
18385 | /* Refer to it. */ | |
4d68580a RS |
18386 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18387 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18388 | fixp->fx_file = fragp->fr_file; |
18389 | fixp->fx_line = fragp->fr_line; | |
18390 | ||
18391 | /* Branch over the jump. */ | |
4d68580a | 18392 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18393 | if (!compact) |
4d68580a RS |
18394 | /* nop */ |
18395 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18396 | } |
18397 | ||
18398 | if (mips_pic == NO_PIC) | |
18399 | { | |
2309ddf2 MR |
18400 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18401 | ||
df58fc94 RS |
18402 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18403 | insn = al ? jal : 0xd4000000; | |
18404 | ||
4d68580a RS |
18405 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18406 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18407 | fixp->fx_file = fragp->fr_file; |
18408 | fixp->fx_line = fragp->fr_line; | |
18409 | ||
4d68580a | 18410 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18411 | if (compact) |
4d68580a RS |
18412 | /* nop */ |
18413 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18414 | } |
18415 | else | |
18416 | { | |
18417 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18418 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18419 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18420 | |
18421 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18422 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18423 | insn |= at << MICROMIPSOP_SH_RT; | |
18424 | ||
18425 | if (exp.X_add_number) | |
18426 | { | |
18427 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18428 | exp.X_add_number = 0; | |
18429 | } | |
18430 | ||
4d68580a RS |
18431 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18432 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18433 | fixp->fx_file = fragp->fr_file; |
18434 | fixp->fx_line = fragp->fr_line; | |
18435 | ||
4d68580a | 18436 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18437 | |
18438 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18439 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18440 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18441 | ||
4d68580a RS |
18442 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18443 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18444 | fixp->fx_file = fragp->fr_file; |
18445 | fixp->fx_line = fragp->fr_line; | |
18446 | ||
4d68580a | 18447 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18448 | |
18449 | /* jr/jrc/jalr/jalrs $at */ | |
18450 | insn = al ? jalr : jr; | |
18451 | insn |= at << MICROMIPSOP_SH_MJ; | |
18452 | ||
4d68580a | 18453 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18454 | } |
18455 | ||
4d68580a | 18456 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18457 | return; |
18458 | } | |
18459 | ||
252b5132 RH |
18460 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18461 | { | |
18462 | int type; | |
3994f87e | 18463 | const struct mips16_immed_operand *op; |
252b5132 | 18464 | offsetT val; |
5c04167a RS |
18465 | char *buf; |
18466 | unsigned int user_length, length; | |
252b5132 | 18467 | unsigned long insn; |
5c04167a | 18468 | bfd_boolean ext; |
252b5132 RH |
18469 | |
18470 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18471 | op = mips16_immed_operands; | |
18472 | while (op->type != type) | |
18473 | ++op; | |
18474 | ||
5c04167a | 18475 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18476 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18477 | if (op->pcrel) |
18478 | { | |
18479 | addressT addr; | |
18480 | ||
18481 | addr = fragp->fr_address + fragp->fr_fix; | |
18482 | ||
18483 | /* The rules for the base address of a PC relative reloc are | |
18484 | complicated; see mips16_extended_frag. */ | |
18485 | if (type == 'p' || type == 'q') | |
18486 | { | |
18487 | addr += 2; | |
18488 | if (ext) | |
18489 | addr += 2; | |
18490 | /* Ignore the low bit in the target, since it will be | |
18491 | set for a text label. */ | |
18492 | if ((val & 1) != 0) | |
18493 | --val; | |
18494 | } | |
18495 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18496 | addr -= 4; | |
18497 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18498 | addr -= 2; | |
18499 | ||
18500 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18501 | val -= addr; | |
18502 | ||
18503 | /* Make sure the section winds up with the alignment we have | |
18504 | assumed. */ | |
18505 | if (op->shift > 0) | |
18506 | record_alignment (asec, op->shift); | |
18507 | } | |
18508 | ||
18509 | if (ext | |
18510 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18511 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18512 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18513 | _("extended instruction in delay slot")); | |
18514 | ||
5c04167a | 18515 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18516 | |
4d68580a | 18517 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18518 | if (ext) |
18519 | insn |= MIPS16_EXTEND; | |
252b5132 | 18520 | |
5c04167a RS |
18521 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18522 | user_length = 4; | |
18523 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18524 | user_length = 2; | |
18525 | else | |
18526 | user_length = 0; | |
18527 | ||
43c0598f | 18528 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18529 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18530 | |
5c04167a RS |
18531 | length = (ext ? 4 : 2); |
18532 | gas_assert (mips16_opcode_length (insn) == length); | |
18533 | write_compressed_insn (buf, insn, length); | |
18534 | fragp->fr_fix += length; | |
252b5132 RH |
18535 | } |
18536 | else | |
18537 | { | |
df58fc94 RS |
18538 | relax_substateT subtype = fragp->fr_subtype; |
18539 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18540 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18541 | int first, second; |
18542 | fixS *fixp; | |
252b5132 | 18543 | |
df58fc94 RS |
18544 | first = RELAX_FIRST (subtype); |
18545 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18546 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18547 | |
df58fc94 RS |
18548 | /* If the delay slot chosen does not match the size of the instruction, |
18549 | then emit a warning. */ | |
18550 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18551 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18552 | { | |
18553 | relax_substateT s; | |
18554 | const char *msg; | |
18555 | ||
18556 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18557 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18558 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18559 | msg = macro_warning (s); | |
18560 | if (msg != NULL) | |
db9b2be4 | 18561 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18562 | subtype &= ~s; |
18563 | } | |
18564 | ||
584892a6 | 18565 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18566 | if (use_second == second_longer) |
584892a6 | 18567 | { |
df58fc94 RS |
18568 | relax_substateT s; |
18569 | const char *msg; | |
18570 | ||
18571 | s = (subtype | |
18572 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18573 | msg = macro_warning (s); | |
18574 | if (msg != NULL) | |
db9b2be4 | 18575 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18576 | subtype &= ~s; |
584892a6 RS |
18577 | } |
18578 | ||
4d7206a2 RS |
18579 | /* Go through all the fixups for the first sequence. Disable them |
18580 | (by marking them as done) if we're going to use the second | |
18581 | sequence instead. */ | |
18582 | while (fixp | |
18583 | && fixp->fx_frag == fragp | |
18584 | && fixp->fx_where < fragp->fr_fix - second) | |
18585 | { | |
df58fc94 | 18586 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18587 | fixp->fx_done = 1; |
18588 | fixp = fixp->fx_next; | |
18589 | } | |
252b5132 | 18590 | |
4d7206a2 RS |
18591 | /* Go through the fixups for the second sequence. Disable them if |
18592 | we're going to use the first sequence, otherwise adjust their | |
18593 | addresses to account for the relaxation. */ | |
18594 | while (fixp && fixp->fx_frag == fragp) | |
18595 | { | |
df58fc94 | 18596 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18597 | fixp->fx_where -= first; |
18598 | else | |
18599 | fixp->fx_done = 1; | |
18600 | fixp = fixp->fx_next; | |
18601 | } | |
18602 | ||
18603 | /* Now modify the frag contents. */ | |
df58fc94 | 18604 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18605 | { |
18606 | char *start; | |
18607 | ||
18608 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18609 | memmove (start, start + first, second); | |
18610 | fragp->fr_fix -= first; | |
18611 | } | |
18612 | else | |
18613 | fragp->fr_fix -= second; | |
252b5132 RH |
18614 | } |
18615 | } | |
18616 | ||
252b5132 RH |
18617 | /* This function is called after the relocs have been generated. |
18618 | We've been storing mips16 text labels as odd. Here we convert them | |
18619 | back to even for the convenience of the debugger. */ | |
18620 | ||
18621 | void | |
17a2f251 | 18622 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18623 | { |
18624 | asymbol **syms; | |
18625 | unsigned int count, i; | |
18626 | ||
252b5132 RH |
18627 | syms = bfd_get_outsymbols (stdoutput); |
18628 | count = bfd_get_symcount (stdoutput); | |
18629 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18630 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18631 | && ((*syms)->value & 1) != 0) | |
18632 | { | |
18633 | (*syms)->value &= ~1; | |
18634 | /* If the symbol has an odd size, it was probably computed | |
18635 | incorrectly, so adjust that as well. */ | |
18636 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18637 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18638 | } | |
252b5132 RH |
18639 | } |
18640 | ||
a1facbec MR |
18641 | /* This function is called whenever a label is defined, including fake |
18642 | labels instantiated off the dot special symbol. It is used when | |
18643 | handling branch delays; if a branch has a label, we assume we cannot | |
18644 | move it. This also bumps the value of the symbol by 1 in compressed | |
18645 | code. */ | |
252b5132 | 18646 | |
e1b47bd5 | 18647 | static void |
a1facbec | 18648 | mips_record_label (symbolS *sym) |
252b5132 | 18649 | { |
a8dbcb85 | 18650 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18651 | struct insn_label_list *l; |
18652 | ||
18653 | if (free_insn_labels == NULL) | |
18654 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18655 | else | |
18656 | { | |
18657 | l = free_insn_labels; | |
18658 | free_insn_labels = l->next; | |
18659 | } | |
18660 | ||
18661 | l->label = sym; | |
a8dbcb85 TS |
18662 | l->next = si->label_list; |
18663 | si->label_list = l; | |
a1facbec | 18664 | } |
07a53e5c | 18665 | |
a1facbec MR |
18666 | /* This function is called as tc_frob_label() whenever a label is defined |
18667 | and adds a DWARF-2 record we only want for true labels. */ | |
18668 | ||
18669 | void | |
18670 | mips_define_label (symbolS *sym) | |
18671 | { | |
18672 | mips_record_label (sym); | |
07a53e5c | 18673 | dwarf2_emit_label (sym); |
252b5132 | 18674 | } |
e1b47bd5 RS |
18675 | |
18676 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18677 | is defined. */ | |
18678 | ||
18679 | void | |
18680 | mips_add_dot_label (symbolS *sym) | |
18681 | { | |
18682 | mips_record_label (sym); | |
18683 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18684 | mips_compressed_mark_label (sym); | |
18685 | } | |
252b5132 | 18686 | \f |
252b5132 RH |
18687 | /* Some special processing for a MIPS ELF file. */ |
18688 | ||
18689 | void | |
17a2f251 | 18690 | mips_elf_final_processing (void) |
252b5132 RH |
18691 | { |
18692 | /* Write out the register information. */ | |
316f5878 | 18693 | if (mips_abi != N64_ABI) |
252b5132 RH |
18694 | { |
18695 | Elf32_RegInfo s; | |
18696 | ||
18697 | s.ri_gprmask = mips_gprmask; | |
18698 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18699 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18700 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18701 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18702 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18703 | ||
18704 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18705 | ((Elf32_External_RegInfo *) | |
18706 | mips_regmask_frag)); | |
18707 | } | |
18708 | else | |
18709 | { | |
18710 | Elf64_Internal_RegInfo s; | |
18711 | ||
18712 | s.ri_gprmask = mips_gprmask; | |
18713 | s.ri_pad = 0; | |
18714 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18715 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18716 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18717 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18718 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18719 | ||
18720 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18721 | ((Elf64_External_RegInfo *) | |
18722 | mips_regmask_frag)); | |
18723 | } | |
18724 | ||
18725 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18726 | sort of BFD interface for this. */ | |
18727 | if (mips_any_noreorder) | |
18728 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18729 | if (mips_pic != NO_PIC) | |
143d77c5 | 18730 | { |
8b828383 | 18731 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18732 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18733 | } | |
18734 | if (mips_abicalls) | |
18735 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18736 | |
b015e599 AP |
18737 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18738 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18739 | if (file_ase_mips16) |
18740 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18741 | if (file_ase_micromips) |
18742 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 18743 | if (file_ase & ASE_MDMX) |
deec1734 | 18744 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18745 | |
bdaaa2e1 | 18746 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18747 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18748 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18749 | else if (mips_abi == O64_ABI) |
252b5132 | 18750 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18751 | else if (mips_abi == EABI_ABI) |
252b5132 | 18752 | { |
316f5878 | 18753 | if (!file_mips_gp32) |
252b5132 RH |
18754 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18755 | else | |
18756 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18757 | } | |
316f5878 | 18758 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18759 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18760 | ||
c9914766 | 18761 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18762 | |
18763 | if (mips_32bitmode) | |
18764 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18765 | |
18766 | #if 0 /* XXX FIXME */ | |
18767 | /* 32 bit code with 64 bit FP registers. */ | |
18768 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18769 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18770 | #endif | |
252b5132 | 18771 | } |
252b5132 | 18772 | \f |
beae10d5 | 18773 | typedef struct proc { |
9b2f1d35 EC |
18774 | symbolS *func_sym; |
18775 | symbolS *func_end_sym; | |
beae10d5 KH |
18776 | unsigned long reg_mask; |
18777 | unsigned long reg_offset; | |
18778 | unsigned long fpreg_mask; | |
18779 | unsigned long fpreg_offset; | |
18780 | unsigned long frame_offset; | |
18781 | unsigned long frame_reg; | |
18782 | unsigned long pc_reg; | |
18783 | } procS; | |
252b5132 RH |
18784 | |
18785 | static procS cur_proc; | |
18786 | static procS *cur_proc_ptr; | |
18787 | static int numprocs; | |
18788 | ||
df58fc94 RS |
18789 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18790 | as "2", and a normal nop as "0". */ | |
18791 | ||
18792 | #define NOP_OPCODE_MIPS 0 | |
18793 | #define NOP_OPCODE_MIPS16 1 | |
18794 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18795 | |
18796 | char | |
18797 | mips_nop_opcode (void) | |
18798 | { | |
df58fc94 RS |
18799 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18800 | return NOP_OPCODE_MICROMIPS; | |
18801 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18802 | return NOP_OPCODE_MIPS16; | |
18803 | else | |
18804 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18805 | } |
18806 | ||
df58fc94 RS |
18807 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18808 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18809 | |
0a9ef439 | 18810 | void |
17a2f251 | 18811 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18812 | { |
df58fc94 | 18813 | char nop_opcode; |
742a56fe | 18814 | char *p; |
c67a084a NC |
18815 | int bytes, size, excess; |
18816 | valueT opcode; | |
742a56fe | 18817 | |
0a9ef439 RH |
18818 | if (fragp->fr_type != rs_align_code) |
18819 | return; | |
18820 | ||
742a56fe | 18821 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18822 | nop_opcode = *p; |
18823 | switch (nop_opcode) | |
a19d8eb0 | 18824 | { |
df58fc94 RS |
18825 | case NOP_OPCODE_MICROMIPS: |
18826 | opcode = micromips_nop32_insn.insn_opcode; | |
18827 | size = 4; | |
18828 | break; | |
18829 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18830 | opcode = mips16_nop_insn.insn_opcode; |
18831 | size = 2; | |
df58fc94 RS |
18832 | break; |
18833 | case NOP_OPCODE_MIPS: | |
18834 | default: | |
c67a084a NC |
18835 | opcode = nop_insn.insn_opcode; |
18836 | size = 4; | |
df58fc94 | 18837 | break; |
c67a084a | 18838 | } |
a19d8eb0 | 18839 | |
c67a084a NC |
18840 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18841 | excess = bytes % size; | |
df58fc94 RS |
18842 | |
18843 | /* Handle the leading part if we're not inserting a whole number of | |
18844 | instructions, and make it the end of the fixed part of the frag. | |
18845 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18846 | and use zeroes otherwise. */ | |
18847 | gas_assert (excess < 4); | |
18848 | fragp->fr_fix += excess; | |
18849 | switch (excess) | |
c67a084a | 18850 | { |
df58fc94 RS |
18851 | case 3: |
18852 | *p++ = '\0'; | |
18853 | /* Fall through. */ | |
18854 | case 2: | |
18855 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18856 | { | |
4d68580a | 18857 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18858 | break; |
18859 | } | |
18860 | *p++ = '\0'; | |
18861 | /* Fall through. */ | |
18862 | case 1: | |
18863 | *p++ = '\0'; | |
18864 | /* Fall through. */ | |
18865 | case 0: | |
18866 | break; | |
a19d8eb0 | 18867 | } |
c67a084a NC |
18868 | |
18869 | md_number_to_chars (p, opcode, size); | |
18870 | fragp->fr_var = size; | |
a19d8eb0 CP |
18871 | } |
18872 | ||
252b5132 | 18873 | static void |
17a2f251 | 18874 | md_obj_begin (void) |
252b5132 RH |
18875 | { |
18876 | } | |
18877 | ||
18878 | static void | |
17a2f251 | 18879 | md_obj_end (void) |
252b5132 | 18880 | { |
54f4ddb3 | 18881 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18882 | if (cur_proc_ptr) |
9a41af64 | 18883 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18884 | } |
18885 | ||
18886 | static long | |
17a2f251 | 18887 | get_number (void) |
252b5132 RH |
18888 | { |
18889 | int negative = 0; | |
18890 | long val = 0; | |
18891 | ||
18892 | if (*input_line_pointer == '-') | |
18893 | { | |
18894 | ++input_line_pointer; | |
18895 | negative = 1; | |
18896 | } | |
3882b010 | 18897 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18898 | as_bad (_("expected simple number")); |
252b5132 RH |
18899 | if (input_line_pointer[0] == '0') |
18900 | { | |
18901 | if (input_line_pointer[1] == 'x') | |
18902 | { | |
18903 | input_line_pointer += 2; | |
3882b010 | 18904 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18905 | { |
18906 | val <<= 4; | |
18907 | val |= hex_value (*input_line_pointer++); | |
18908 | } | |
18909 | return negative ? -val : val; | |
18910 | } | |
18911 | else | |
18912 | { | |
18913 | ++input_line_pointer; | |
3882b010 | 18914 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18915 | { |
18916 | val <<= 3; | |
18917 | val |= *input_line_pointer++ - '0'; | |
18918 | } | |
18919 | return negative ? -val : val; | |
18920 | } | |
18921 | } | |
3882b010 | 18922 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18923 | { |
18924 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18925 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18926 | as_warn (_("invalid number")); |
252b5132 RH |
18927 | return -1; |
18928 | } | |
3882b010 | 18929 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18930 | { |
18931 | val *= 10; | |
18932 | val += *input_line_pointer++ - '0'; | |
18933 | } | |
18934 | return negative ? -val : val; | |
18935 | } | |
18936 | ||
18937 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18938 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18939 | case .file implies DWARF-2. */ | |
18940 | ||
18941 | static void | |
17a2f251 | 18942 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18943 | { |
ecb4347a DJ |
18944 | static int first_file_directive = 0; |
18945 | ||
c5dd6aab DJ |
18946 | if (ECOFF_DEBUGGING) |
18947 | { | |
18948 | get_number (); | |
18949 | s_app_file (0); | |
18950 | } | |
18951 | else | |
ecb4347a DJ |
18952 | { |
18953 | char *filename; | |
18954 | ||
18955 | filename = dwarf2_directive_file (0); | |
18956 | ||
18957 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18958 | directive even for stabs output. Make sure that this | |
18959 | ".file" is handled. Note that you need a version of GCC | |
18960 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18961 | if (filename != NULL && ! first_file_directive) | |
18962 | { | |
18963 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18964 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18965 | } |
18966 | first_file_directive = 1; | |
18967 | } | |
c5dd6aab DJ |
18968 | } |
18969 | ||
18970 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18971 | |
18972 | static void | |
17a2f251 | 18973 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18974 | { |
c5dd6aab DJ |
18975 | if (!ECOFF_DEBUGGING) |
18976 | dwarf2_directive_loc (0); | |
252b5132 RH |
18977 | } |
18978 | ||
252b5132 RH |
18979 | /* The .end directive. */ |
18980 | ||
18981 | static void | |
17a2f251 | 18982 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18983 | { |
18984 | symbolS *p; | |
252b5132 | 18985 | |
7a621144 DJ |
18986 | /* Following functions need their own .frame and .cprestore directives. */ |
18987 | mips_frame_reg_valid = 0; | |
18988 | mips_cprestore_valid = 0; | |
18989 | ||
252b5132 RH |
18990 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18991 | { | |
18992 | p = get_symbol (); | |
18993 | demand_empty_rest_of_line (); | |
18994 | } | |
18995 | else | |
18996 | p = NULL; | |
18997 | ||
14949570 | 18998 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18999 | as_warn (_(".end not in text section")); |
19000 | ||
19001 | if (!cur_proc_ptr) | |
19002 | { | |
19003 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19004 | demand_empty_rest_of_line (); | |
19005 | return; | |
19006 | } | |
19007 | ||
19008 | if (p != NULL) | |
19009 | { | |
9c2799c2 | 19010 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19011 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19012 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19013 | |
19014 | if (debug_type == DEBUG_STABS) | |
19015 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19016 | S_GET_NAME (p)); | |
252b5132 RH |
19017 | } |
19018 | else | |
19019 | as_warn (_(".end directive missing or unknown symbol")); | |
19020 | ||
9b2f1d35 EC |
19021 | /* Create an expression to calculate the size of the function. */ |
19022 | if (p && cur_proc_ptr) | |
19023 | { | |
19024 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19025 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19026 | ||
19027 | obj->size = exp; | |
19028 | exp->X_op = O_subtract; | |
19029 | exp->X_add_symbol = symbol_temp_new_now (); | |
19030 | exp->X_op_symbol = p; | |
19031 | exp->X_add_number = 0; | |
19032 | ||
19033 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19034 | } | |
19035 | ||
ecb4347a | 19036 | /* Generate a .pdr section. */ |
f3ded42a | 19037 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19038 | { |
19039 | segT saved_seg = now_seg; | |
19040 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19041 | expressionS exp; |
19042 | char *fragp; | |
252b5132 | 19043 | |
252b5132 | 19044 | #ifdef md_flush_pending_output |
ecb4347a | 19045 | md_flush_pending_output (); |
252b5132 RH |
19046 | #endif |
19047 | ||
9c2799c2 | 19048 | gas_assert (pdr_seg); |
ecb4347a | 19049 | subseg_set (pdr_seg, 0); |
252b5132 | 19050 | |
ecb4347a DJ |
19051 | /* Write the symbol. */ |
19052 | exp.X_op = O_symbol; | |
19053 | exp.X_add_symbol = p; | |
19054 | exp.X_add_number = 0; | |
19055 | emit_expr (&exp, 4); | |
252b5132 | 19056 | |
ecb4347a | 19057 | fragp = frag_more (7 * 4); |
252b5132 | 19058 | |
17a2f251 TS |
19059 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19060 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19061 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19062 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19063 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19064 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19065 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19066 | |
ecb4347a DJ |
19067 | subseg_set (saved_seg, saved_subseg); |
19068 | } | |
252b5132 RH |
19069 | |
19070 | cur_proc_ptr = NULL; | |
19071 | } | |
19072 | ||
19073 | /* The .aent and .ent directives. */ | |
19074 | ||
19075 | static void | |
17a2f251 | 19076 | s_mips_ent (int aent) |
252b5132 | 19077 | { |
252b5132 | 19078 | symbolS *symbolP; |
252b5132 RH |
19079 | |
19080 | symbolP = get_symbol (); | |
19081 | if (*input_line_pointer == ',') | |
f9419b05 | 19082 | ++input_line_pointer; |
252b5132 | 19083 | SKIP_WHITESPACE (); |
3882b010 | 19084 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19085 | || *input_line_pointer == '-') |
874e8986 | 19086 | get_number (); |
252b5132 | 19087 | |
14949570 | 19088 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19089 | as_warn (_(".ent or .aent not in text section.")); |
19090 | ||
19091 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19092 | as_warn (_("missing .end")); |
252b5132 RH |
19093 | |
19094 | if (!aent) | |
19095 | { | |
7a621144 DJ |
19096 | /* This function needs its own .frame and .cprestore directives. */ |
19097 | mips_frame_reg_valid = 0; | |
19098 | mips_cprestore_valid = 0; | |
19099 | ||
252b5132 RH |
19100 | cur_proc_ptr = &cur_proc; |
19101 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19102 | ||
9b2f1d35 | 19103 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19104 | |
f9419b05 | 19105 | ++numprocs; |
ecb4347a DJ |
19106 | |
19107 | if (debug_type == DEBUG_STABS) | |
19108 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19109 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19110 | } |
19111 | ||
7c0fc524 MR |
19112 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19113 | ||
252b5132 RH |
19114 | demand_empty_rest_of_line (); |
19115 | } | |
19116 | ||
19117 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19118 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19119 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19120 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19121 | symbol table (in the mdebug section). */ |
19122 | ||
19123 | static void | |
17a2f251 | 19124 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19125 | { |
f3ded42a RS |
19126 | if (ECOFF_DEBUGGING) |
19127 | s_ignore (ignore); | |
19128 | else | |
ecb4347a DJ |
19129 | { |
19130 | long val; | |
252b5132 | 19131 | |
ecb4347a DJ |
19132 | if (cur_proc_ptr == (procS *) NULL) |
19133 | { | |
19134 | as_warn (_(".frame outside of .ent")); | |
19135 | demand_empty_rest_of_line (); | |
19136 | return; | |
19137 | } | |
252b5132 | 19138 | |
ecb4347a DJ |
19139 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19140 | ||
19141 | SKIP_WHITESPACE (); | |
19142 | if (*input_line_pointer++ != ',' | |
19143 | || get_absolute_expression_and_terminator (&val) != ',') | |
19144 | { | |
19145 | as_warn (_("Bad .frame directive")); | |
19146 | --input_line_pointer; | |
19147 | demand_empty_rest_of_line (); | |
19148 | return; | |
19149 | } | |
252b5132 | 19150 | |
ecb4347a DJ |
19151 | cur_proc_ptr->frame_offset = val; |
19152 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19153 | |
252b5132 | 19154 | demand_empty_rest_of_line (); |
252b5132 | 19155 | } |
252b5132 RH |
19156 | } |
19157 | ||
bdaaa2e1 KH |
19158 | /* The .fmask and .mask directives. If the mdebug section is present |
19159 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19160 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19161 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19162 | make reference to the ecoff symbol table (in the mdebug section). */ |
19163 | ||
19164 | static void | |
17a2f251 | 19165 | s_mips_mask (int reg_type) |
252b5132 | 19166 | { |
f3ded42a RS |
19167 | if (ECOFF_DEBUGGING) |
19168 | s_ignore (reg_type); | |
19169 | else | |
252b5132 | 19170 | { |
ecb4347a | 19171 | long mask, off; |
252b5132 | 19172 | |
ecb4347a DJ |
19173 | if (cur_proc_ptr == (procS *) NULL) |
19174 | { | |
19175 | as_warn (_(".mask/.fmask outside of .ent")); | |
19176 | demand_empty_rest_of_line (); | |
19177 | return; | |
19178 | } | |
252b5132 | 19179 | |
ecb4347a DJ |
19180 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19181 | { | |
19182 | as_warn (_("Bad .mask/.fmask directive")); | |
19183 | --input_line_pointer; | |
19184 | demand_empty_rest_of_line (); | |
19185 | return; | |
19186 | } | |
252b5132 | 19187 | |
ecb4347a DJ |
19188 | off = get_absolute_expression (); |
19189 | ||
19190 | if (reg_type == 'F') | |
19191 | { | |
19192 | cur_proc_ptr->fpreg_mask = mask; | |
19193 | cur_proc_ptr->fpreg_offset = off; | |
19194 | } | |
19195 | else | |
19196 | { | |
19197 | cur_proc_ptr->reg_mask = mask; | |
19198 | cur_proc_ptr->reg_offset = off; | |
19199 | } | |
19200 | ||
19201 | demand_empty_rest_of_line (); | |
252b5132 | 19202 | } |
252b5132 RH |
19203 | } |
19204 | ||
316f5878 RS |
19205 | /* A table describing all the processors gas knows about. Names are |
19206 | matched in the order listed. | |
e7af610e | 19207 | |
316f5878 RS |
19208 | To ease comparison, please keep this table in the same order as |
19209 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19210 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19211 | { | |
316f5878 | 19212 | /* Entries for generic ISAs */ |
d16afab6 RS |
19213 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19214 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19215 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19216 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19217 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19218 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19219 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19220 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19221 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19222 | |
19223 | /* MIPS I */ | |
d16afab6 RS |
19224 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19225 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19226 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19227 | |
19228 | /* MIPS II */ | |
d16afab6 | 19229 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19230 | |
19231 | /* MIPS III */ | |
d16afab6 RS |
19232 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19233 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19234 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19235 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19236 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19237 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19238 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19239 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19240 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19241 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19242 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19243 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19244 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19245 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19246 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19247 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19248 | |
19249 | /* MIPS IV */ | |
d16afab6 RS |
19250 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19251 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19252 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19253 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19254 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19255 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19256 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19257 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19258 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19259 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19260 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19261 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19262 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19263 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19264 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19265 | |
19266 | /* MIPS 32 */ | |
d16afab6 RS |
19267 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19268 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19269 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19270 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19271 | |
19272 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19273 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19274 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19275 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19276 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19277 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19278 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19279 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19280 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19281 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19282 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19283 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19284 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19285 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19286 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19287 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19288 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19289 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19290 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19291 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19292 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19293 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19294 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19295 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19296 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19297 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19298 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19299 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19300 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19301 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19302 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19303 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19304 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19305 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19306 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19307 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19308 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19309 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19310 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19311 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19312 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19313 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19314 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19315 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19316 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19317 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19318 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19319 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19320 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19321 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19322 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19323 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19324 | |
316f5878 | 19325 | /* MIPS 64 */ |
d16afab6 RS |
19326 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19327 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19328 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19329 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19330 | |
c7a23324 | 19331 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19332 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19333 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19334 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 19335 | |
d16afab6 | 19336 | { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, |
e7af610e | 19337 | |
ed163775 MR |
19338 | /* MIPS 64 Release 2 */ |
19339 | ||
967344c6 | 19340 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19341 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19342 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19343 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 19344 | |
52b6b6b9 | 19345 | /* RMI Xlr */ |
d16afab6 | 19346 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19347 | |
55a36193 MK |
19348 | /* Broadcom XLP. |
19349 | XLP is mostly like XLR, with the prominent exception that it is | |
19350 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19351 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19352 | |
316f5878 | 19353 | /* End marker */ |
d16afab6 | 19354 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19355 | }; |
e7af610e | 19356 | |
84ea6cf2 | 19357 | |
316f5878 RS |
19358 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19359 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19360 | |
316f5878 | 19361 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19362 | |
b34976b6 | 19363 | static bfd_boolean |
17a2f251 | 19364 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19365 | { |
19366 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19367 | given++, canonical++; | |
19368 | ||
19369 | return ((*given == 0 && *canonical == 0) | |
19370 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19371 | } | |
19372 | ||
19373 | ||
19374 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19375 | CPU name. We've traditionally allowed a lot of variation here. | |
19376 | ||
19377 | Note: this function is shared between GCC and GAS. */ | |
19378 | ||
b34976b6 | 19379 | static bfd_boolean |
17a2f251 | 19380 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19381 | { |
19382 | /* First see if the name matches exactly, or with a final "000" | |
19383 | turned into "k". */ | |
19384 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19385 | return TRUE; |
316f5878 RS |
19386 | |
19387 | /* If not, try comparing based on numerical designation alone. | |
19388 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19389 | if (TOLOWER (*given) == 'r') | |
19390 | given++; | |
19391 | if (!ISDIGIT (*given)) | |
b34976b6 | 19392 | return FALSE; |
316f5878 RS |
19393 | |
19394 | /* Skip over some well-known prefixes in the canonical name, | |
19395 | hoping to find a number there too. */ | |
19396 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19397 | canonical += 2; | |
19398 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19399 | canonical += 2; | |
19400 | else if (TOLOWER (canonical[0]) == 'r') | |
19401 | canonical += 1; | |
19402 | ||
19403 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19404 | } | |
19405 | ||
19406 | ||
19407 | /* Parse an option that takes the name of a processor as its argument. | |
19408 | OPTION is the name of the option and CPU_STRING is the argument. | |
19409 | Return the corresponding processor enumeration if the CPU_STRING is | |
19410 | recognized, otherwise report an error and return null. | |
19411 | ||
19412 | A similar function exists in GCC. */ | |
e7af610e NC |
19413 | |
19414 | static const struct mips_cpu_info * | |
17a2f251 | 19415 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19416 | { |
316f5878 | 19417 | const struct mips_cpu_info *p; |
e7af610e | 19418 | |
316f5878 RS |
19419 | /* 'from-abi' selects the most compatible architecture for the given |
19420 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19421 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19422 | version. Look first at the -mgp options, if given, otherwise base | |
19423 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19424 | |
316f5878 RS |
19425 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19426 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19427 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19428 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19429 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19430 | { | |
19431 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19432 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19433 | ||
19434 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19435 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19436 | ||
19437 | if (file_mips_gp32 >= 0) | |
19438 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19439 | ||
19440 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19441 | ? ISA_MIPS3 | |
19442 | : ISA_MIPS1); | |
19443 | } | |
19444 | ||
19445 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19446 | if (strcasecmp (cpu_string, "default") == 0) | |
19447 | return 0; | |
19448 | ||
19449 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19450 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19451 | return p; | |
19452 | ||
20203fb9 | 19453 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19454 | return 0; |
e7af610e NC |
19455 | } |
19456 | ||
316f5878 RS |
19457 | /* Return the canonical processor information for ISA (a member of the |
19458 | ISA_MIPS* enumeration). */ | |
19459 | ||
e7af610e | 19460 | static const struct mips_cpu_info * |
17a2f251 | 19461 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19462 | { |
19463 | int i; | |
19464 | ||
19465 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19466 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19467 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19468 | return (&mips_cpu_info_table[i]); |
19469 | ||
e972090a | 19470 | return NULL; |
e7af610e | 19471 | } |
fef14a42 TS |
19472 | |
19473 | static const struct mips_cpu_info * | |
17a2f251 | 19474 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19475 | { |
19476 | int i; | |
19477 | ||
19478 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19479 | if (arch == mips_cpu_info_table[i].cpu) | |
19480 | return (&mips_cpu_info_table[i]); | |
19481 | ||
19482 | return NULL; | |
19483 | } | |
316f5878 RS |
19484 | \f |
19485 | static void | |
17a2f251 | 19486 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19487 | { |
19488 | if (*first_p) | |
19489 | { | |
19490 | fprintf (stream, "%24s", ""); | |
19491 | *col_p = 24; | |
19492 | } | |
19493 | else | |
19494 | { | |
19495 | fprintf (stream, ", "); | |
19496 | *col_p += 2; | |
19497 | } | |
e7af610e | 19498 | |
316f5878 RS |
19499 | if (*col_p + strlen (string) > 72) |
19500 | { | |
19501 | fprintf (stream, "\n%24s", ""); | |
19502 | *col_p = 24; | |
19503 | } | |
19504 | ||
19505 | fprintf (stream, "%s", string); | |
19506 | *col_p += strlen (string); | |
19507 | ||
19508 | *first_p = 0; | |
19509 | } | |
19510 | ||
19511 | void | |
17a2f251 | 19512 | md_show_usage (FILE *stream) |
e7af610e | 19513 | { |
316f5878 RS |
19514 | int column, first; |
19515 | size_t i; | |
19516 | ||
19517 | fprintf (stream, _("\ | |
19518 | MIPS options:\n\ | |
316f5878 RS |
19519 | -EB generate big endian output\n\ |
19520 | -EL generate little endian output\n\ | |
19521 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19522 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19523 | implicitly with the gp register [default 8]\n")); | |
19524 | fprintf (stream, _("\ | |
19525 | -mips1 generate MIPS ISA I instructions\n\ | |
19526 | -mips2 generate MIPS ISA II instructions\n\ | |
19527 | -mips3 generate MIPS ISA III instructions\n\ | |
19528 | -mips4 generate MIPS ISA IV instructions\n\ | |
19529 | -mips5 generate MIPS ISA V instructions\n\ | |
19530 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19531 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19532 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19533 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19534 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19535 | ||
19536 | first = 1; | |
e7af610e NC |
19537 | |
19538 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19539 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19540 | show (stream, "from-abi", &column, &first); | |
19541 | fputc ('\n', stream); | |
e7af610e | 19542 | |
316f5878 RS |
19543 | fprintf (stream, _("\ |
19544 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19545 | -no-mCPU don't generate code specific to CPU.\n\ | |
19546 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19547 | ||
19548 | first = 1; | |
19549 | ||
19550 | show (stream, "3900", &column, &first); | |
19551 | show (stream, "4010", &column, &first); | |
19552 | show (stream, "4100", &column, &first); | |
19553 | show (stream, "4650", &column, &first); | |
19554 | fputc ('\n', stream); | |
19555 | ||
19556 | fprintf (stream, _("\ | |
19557 | -mips16 generate mips16 instructions\n\ | |
19558 | -no-mips16 do not generate mips16 instructions\n")); | |
19559 | fprintf (stream, _("\ | |
df58fc94 RS |
19560 | -mmicromips generate microMIPS instructions\n\ |
19561 | -mno-micromips do not generate microMIPS instructions\n")); | |
19562 | fprintf (stream, _("\ | |
e16bfa71 TS |
19563 | -msmartmips generate smartmips instructions\n\ |
19564 | -mno-smartmips do not generate smartmips instructions\n")); | |
19565 | fprintf (stream, _("\ | |
74cd071d CF |
19566 | -mdsp generate DSP instructions\n\ |
19567 | -mno-dsp do not generate DSP instructions\n")); | |
19568 | fprintf (stream, _("\ | |
8b082fb1 TS |
19569 | -mdspr2 generate DSP R2 instructions\n\ |
19570 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19571 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19572 | -mmt generate MT instructions\n\ |
19573 | -mno-mt do not generate MT instructions\n")); | |
19574 | fprintf (stream, _("\ | |
dec0624d MR |
19575 | -mmcu generate MCU instructions\n\ |
19576 | -mno-mcu do not generate MCU instructions\n")); | |
19577 | fprintf (stream, _("\ | |
b015e599 AP |
19578 | -mvirt generate Virtualization instructions\n\ |
19579 | -mno-virt do not generate Virtualization instructions\n")); | |
19580 | fprintf (stream, _("\ | |
c67a084a NC |
19581 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19582 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19583 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19584 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19585 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19586 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19587 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19588 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19589 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19590 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19591 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19592 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19593 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19594 | fprintf (stream, _("\ |
19595 | -mhard-float allow floating-point instructions\n\ | |
19596 | -msoft-float do not allow floating-point instructions\n\ | |
19597 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19598 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19599 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19600 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19601 | )); |
316f5878 RS |
19602 | fprintf (stream, _("\ |
19603 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19604 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19605 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19606 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19607 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19608 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19609 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19610 | position dependent (non shared) code\n\ |
316f5878 RS |
19611 | -mabi=ABI create ABI conformant object file for:\n")); |
19612 | ||
19613 | first = 1; | |
19614 | ||
19615 | show (stream, "32", &column, &first); | |
19616 | show (stream, "o64", &column, &first); | |
19617 | show (stream, "n32", &column, &first); | |
19618 | show (stream, "64", &column, &first); | |
19619 | show (stream, "eabi", &column, &first); | |
19620 | ||
19621 | fputc ('\n', stream); | |
19622 | ||
19623 | fprintf (stream, _("\ | |
19624 | -32 create o32 ABI object file (default)\n\ | |
19625 | -n32 create n32 ABI object file\n\ | |
19626 | -64 create 64 ABI object file\n")); | |
e7af610e | 19627 | } |
14e777e0 | 19628 | |
1575952e | 19629 | #ifdef TE_IRIX |
14e777e0 | 19630 | enum dwarf2_format |
413a266c | 19631 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19632 | { |
369943fe | 19633 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19634 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19635 | else |
19636 | return dwarf2_format_32bit; | |
19637 | } | |
1575952e | 19638 | #endif |
73369e65 EC |
19639 | |
19640 | int | |
19641 | mips_dwarf2_addr_size (void) | |
19642 | { | |
6b6b3450 | 19643 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19644 | return 8; |
73369e65 EC |
19645 | else |
19646 | return 4; | |
19647 | } | |
5862107c EC |
19648 | |
19649 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19650 | void | |
19651 | mips_cfi_frame_initial_instructions (void) | |
19652 | { | |
19653 | cfi_add_CFA_def_cfa_register (SP); | |
19654 | } | |
19655 | ||
707bfff6 TS |
19656 | int |
19657 | tc_mips_regname_to_dw2regnum (char *regname) | |
19658 | { | |
19659 | unsigned int regnum = -1; | |
19660 | unsigned int reg; | |
19661 | ||
19662 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19663 | regnum = reg; | |
19664 | ||
19665 | return regnum; | |
19666 | } |