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* config/tc-mips.c (load_register): Remove unused variable tmp.
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
3d3c5039 1/* tc-mips.c -- assemble code for a MIPS chip.
fb251650 2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3d3c5039
ILT		 3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
8358c818
ILT		 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
3d3c5039
ILT		 7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
fb251650
ILT		 21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 02111-1307, USA. */
3d3c5039
ILT		 24
25#include "as.h"
8358c818 26#include "config.h"
9da4c5d1 27#include "subsegs.h"
b2b8c24e 28#include "libiberty.h"
3d3c5039
ILT		 29
30#include <ctype.h>
31
1dc1e798 32#ifdef USE_STDARG
3d3c5039 33#include <stdarg.h>
1dc1e798
KR		 34#endif
35#ifdef USE_VARARGS
3d3c5039 36#include <varargs.h>
1dc1e798 37#endif
3d3c5039 38
918692a5 39#include "opcode/mips.h"
3d3c5039 40
739708fa
KR		 41#ifdef OBJ_MAYBE_ELF
42/* Clean up namespace so we can include obj-elf.h too. */
43static int mips_output_flavor () { return OUTPUT_FLAVOR; }
44#undef OBJ_PROCESS_STAB
45#undef OUTPUT_FLAVOR
46#undef S_GET_ALIGN
47#undef S_GET_SIZE
48#undef S_SET_ALIGN
49#undef S_SET_SIZE
50#undef TARGET_SYMBOL_FIELDS
51#undef obj_frob_file
52#undef obj_frob_symbol
53#undef obj_pop_insert
54#undef obj_sec_sym_ok_for_reloc
55
56#include "obj-elf.h"
57/* Fix any of them that we actually care about. */
58#undef OUTPUT_FLAVOR
59#define OUTPUT_FLAVOR mips_output_flavor()
60#endif
61
62#if defined (OBJ_ELF)
f2a663d3 63#include "elf/mips.h"
1dc1e798 64#endif
f2a663d3 65
739708fa 66#ifndef ECOFF_DEBUGGING
c625fc23 67#define NO_ECOFF_DEBUGGING
739708fa
KR		 68#define ECOFF_DEBUGGING 0
69#endif
70
22ba90ce
ILT		 71#include "ecoff.h"
72
a8aed9dd 73#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
f2a663d3 74static char *mips_regmask_frag;
a8aed9dd 75#endif
f2a663d3 76
3d3c5039 77#define AT 1
9226253a 78#define PIC_CALL_REG 25
b2b8c24e
ILT		 79#define KT0 26
80#define KT1 27
670a50eb 81#define GP 28
9226253a
ILT		 82#define SP 29
83#define FP 30
3d3c5039
ILT		 84#define RA 31
85
1dc1e798 86extern int target_big_endian;
88225433 87
7f9880e5
ILT		 88/* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
90static int mips_64;
91
04cb3372 92/* The default target format to use. */
1dc1e798
KR		 93const char *
94mips_target_format ()
95{
96 switch (OUTPUT_FLAVOR)
97 {
98 case bfd_target_aout_flavour:
99 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour:
101 return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour:
7f9880e5
ILT		 103 return (target_big_endian
104 ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64 ? "elf64-littlemips" : "elf32-littlemips"));
1dc1e798
KR		 106 default:
107 abort ();
108 }
109}
04cb3372 110
d2c71068 111/* The name of the readonly data section. */
1dc1e798
KR		 112#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
113 ? ".data" \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 ? ".rdata" \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
117 ? ".rodata" \
118 : (abort (), ""))
d2c71068 119
1aa6938e
ILT		 120/* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
122 place. */
123unsigned long mips_gprmask;
124unsigned long mips_cprmask[4];
125
1051c97f
ILT		 126/* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
8358c818
ILT		 128static int mips_isa = -1;
129
1051c97f
ILT		 130/* MIPS ISA we are using for this output file. */
131static int file_mips_isa;
132
8c63448a 133/* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
4bb0cc41 134static int mips_cpu = -1;
8c63448a 135
b2b8c24e
ILT		 136/* Whether the 4650 instructions (mad/madu) are permitted. */
137static int mips_4650 = -1;
138
e532b44c
ILT		 139/* Whether the 4010 instructions are permitted. */
140static int mips_4010 = -1;
141
c625fc23
JSC		 142/* Whether the 4100 MADD16 and DMADD16 are permitted. */
143static int mips_4100 = -1;
144
e532b44c
ILT		 145/* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147static int interlocks = -1;
148
344a8d61
JSC		 149/* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151static int cop_interlocks = -1;
152
d9aba805
ILT		 153/* MIPS PIC level. */
154
155enum mips_pic_level
156{
157 /* Do not generate PIC code. */
158 NO_PIC,
159
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
162 IRIX4_PIC,
163
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
165 SVR4_PIC,
166
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
171 EMBEDDED_PIC
172};
173
174static enum mips_pic_level mips_pic;
9226253a 175
fb251650
ILT		 176/* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178static int mips_big_got;
179
8ea7f4e8
ILT		 180/* 1 if trap instructions should used for overflow rather than break
181 instructions. */
182static int mips_trap;
183
3d3c5039
ILT		 184static int mips_warn_about_macros;
185static int mips_noreorder;
0dd2d296 186static int mips_any_noreorder;
3d3c5039
ILT		 187static int mips_nomove;
188static int mips_noat;
189static int mips_nobopt;
190
670a50eb
ILT		 191/* The size of the small data section. */
192static int g_switch_value = 8;
42562568
ILT		 193/* Whether the -G option was used. */
194static int g_switch_seen = 0;
670a50eb 195
3d3c5039
ILT		 196#define N_RMASK 0xc4
197#define N_VFP 0xd4
198
d8a1c247
KR		 199/* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
202 better.
203
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
207
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210static int nopic_need_relax PARAMS ((symbolS *));
211
3d3c5039
ILT		 212/* handle of the OPCODE hash table */
213static struct hash_control *op_hash = NULL;
214
215/* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217const char comment_chars[] = "#";
218
219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222/* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225/* Also note that C style comments are always supported. */
226const char line_comment_chars[] = "#";
227
228/* This array holds machine specific line separator characters. */
229const char line_separator_chars[] = "";
230
231/* Chars that can be used to separate mant from exp in floating point nums */
232const char EXP_CHARS[] = "eE";
233
234/* Chars that mean this number is a floating point constant */
235/* As in 0f12.456 */
236/* or 0d1.2345e12 */
237const char FLT_CHARS[] = "rRsSfFdDxXpP";
238
239/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
242 */
243
670a50eb 244static char *insn_error;
3d3c5039 245
22ba90ce 246static int byte_order;
3d3c5039
ILT		 247
248static int auto_align = 1;
becfe05e
ILT		 249
250/* Symbol labelling the current insn. */
251static symbolS *insn_label;
252
9226253a
ILT		 253/* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
256 variable. */
0dd2d296
ILT		 257static offsetT mips_cprestore_offset = -1;
258
259/* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261static int mips_frame_reg = SP;
9226253a 262
becfe05e
ILT		 263/* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
265
0aa07269
ILT		 266/* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
269 insert NOPs. */
270static int mips_optimize = 2;
4e95866e 271
22ba90ce
ILT		 272/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274static int mips_debug = 0;
275
becfe05e
ILT		 276/* The previous instruction. */
277static struct mips_cl_insn prev_insn;
278
279/* The instruction before prev_insn. */
280static struct mips_cl_insn prev_prev_insn;
281
282/* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284static const struct mips_opcode dummy_opcode = { 0 };
285
286/* Non-zero if prev_insn is valid. */
287static int prev_insn_valid;
288
289/* The frag for the previous instruction. */
290static struct frag *prev_insn_frag;
291
292/* The offset into prev_insn_frag for the previous instruction. */
293static long prev_insn_where;
294
295/* The reloc for the previous instruction, if any. */
296static fixS *prev_insn_fixp;
297
298/* Non-zero if the previous instruction was in a delay slot. */
299static int prev_insn_is_delay_slot;
4e95866e
ILT		 300
301/* Non-zero if the previous instruction was in a .set noreorder. */
302static int prev_insn_unreordered;
303
304/* Non-zero if the previous previous instruction was in a .set
305 noreorder. */
306static int prev_prev_insn_unreordered;
867a58b3
ILT		 307
308/* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
314
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
318
319struct mips_hi_fixup
320{
321 /* Next HI fixup. */
322 struct mips_hi_fixup *next;
323 /* This fixup. */
324 fixS *fixp;
325 /* The section this fixup is in. */
326 segT seg;
327};
328
329/* The list of unmatched HI relocs. */
330
331static struct mips_hi_fixup *mips_hi_fixup_list;
3d3c5039 332\f
0dd2d296
ILT		 333/* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
337
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
23dc1ae3 341 a macro instruction like this:
0dd2d296
ILT		 342 lw $4,i
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
346 lw $4,i($gp)
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
349 lui $at,i
350 lw $4,i($at)
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
353 the symbol i.
354
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
23dc1ae3 359 platforms choose the size of a PC relative instruction only at the
0dd2d296
ILT		 360 end of assembly.
361
362 When generating position independent code we do not use GP
23dc1ae3
ILT		 363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
0dd2d296
ILT		 365
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
379
380 Generating two instruction sequences must be handled carefully to
23dc1ae3
ILT		 381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
0dd2d296
ILT		 388
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
393 one if needed. */
394#define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
395 ((relax_substateT) \
396 (((old) << 24) \
397 | ((new) << 16) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
401 | ((warn) ? 1 : 0)))
402#define RELAX_OLD(i) (((i) >> 24) & 0xff)
403#define RELAX_NEW(i) (((i) >> 16) & 0xff)
483971bd
KR		 404#define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405#define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
0dd2d296
ILT		 406#define RELAX_RELOC3(i) (((i) >> 1) & 1)
407#define RELAX_WARN(i) ((i) & 1)
408\f
3d3c5039
ILT		 409/* Prototypes for static functions. */
410
411#ifdef __STDC__
412#define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
414#else
415#define internalError() as_fatal ("MIPS internal Error");
416#endif
417
becfe05e 418static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
604633ae 419 unsigned int reg, int fpr));
fb251650 420static int reg_needs_delay PARAMS ((int));
0dd2d296
ILT		 421static void append_insn PARAMS ((char *place,
422 struct mips_cl_insn * ip,
670a50eb 423 expressionS * p,
867a58b3
ILT		 424 bfd_reloc_code_real_type r,
425 boolean));
becfe05e
ILT		 426static void mips_no_prev_insn PARAMS ((void));
427static void mips_emit_delays PARAMS ((void));
c625fc23 428#ifdef USE_STDARG
0dd2d296 429static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
3d3c5039
ILT		 430 const char *name, const char *fmt,
431 ...));
c625fc23
JSC		 432#else
433static void macro_build ();
434#endif
0dd2d296
ILT		 435static void macro_build_lui PARAMS ((char *place, int *counter,
436 expressionS * ep, int regnum));
6e8dda9c 437static void set_at PARAMS ((int *counter, int reg, int unsignedp));
670a50eb 438static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
19ed8960 439 expressionS *));
d8a1c247 440static void load_register PARAMS ((int *, int, expressionS *, int));
0dd2d296 441static void load_address PARAMS ((int *counter, int reg, expressionS *ep));
670a50eb 442static void macro PARAMS ((struct mips_cl_insn * ip));
917fae09
SS		 443#ifdef LOSING_COMPILER
444static void macro2 PARAMS ((struct mips_cl_insn * ip));
445#endif
670a50eb
ILT		 446static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
447static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
448static void my_getExpression PARAMS ((expressionS * ep, char *str));
3d3c5039 449static symbolS *get_symbol PARAMS ((void));
23dc1ae3 450static void mips_align PARAMS ((int to, int fill, symbolS *label));
3d3c5039
ILT		 451static void s_align PARAMS ((int));
452static void s_change_sec PARAMS ((int));
453static void s_cons PARAMS ((int));
3d3c5039 454static void s_float_cons PARAMS ((int));
c1444ec4 455static void s_mips_globl PARAMS ((int));
3d3c5039
ILT		 456static void s_option PARAMS ((int));
457static void s_mipsset PARAMS ((int));
9226253a
ILT		 458static void s_abicalls PARAMS ((int));
459static void s_cpload PARAMS ((int));
460static void s_cprestore PARAMS ((int));
0dd2d296
ILT		 461static void s_gpword PARAMS ((int));
462static void s_cpadd PARAMS ((int));
3d3c5039
ILT		 463static void md_obj_begin PARAMS ((void));
464static void md_obj_end PARAMS ((void));
465static long get_number PARAMS ((void));
466static void s_ent PARAMS ((int));
467static void s_mipsend PARAMS ((int));
468static void s_file PARAMS ((int));
3d3c5039
ILT		 469\f
470/* Pseudo-op table.
471
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
475
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
480 .vreg.
481
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
487
739708fa 488static const pseudo_typeS mips_pseudo_table[] =
3d3c5039 489{
670a50eb
ILT		 490 /* MIPS specific pseudo-ops. */
491 {"option", s_option, 0},
492 {"set", s_mipsset, 0},
dd3f1f76
ILT		 493 {"rdata", s_change_sec, 'r'},
494 {"sdata", s_change_sec, 's'},
495 {"livereg", s_ignore, 0},
739708fa
KR		 496 {"abicalls", s_abicalls, 0},
497 {"cpload", s_cpload, 0},
498 {"cprestore", s_cprestore, 0},
499 {"gpword", s_gpword, 0},
500 {"cpadd", s_cpadd, 0},
3d3c5039 501
670a50eb 502 /* Relatively generic pseudo-ops that happen to be used on MIPS
3d3c5039 503 chips. */
739708fa 504 {"asciiz", stringer, 1},
670a50eb
ILT		 505 {"bss", s_change_sec, 'b'},
506 {"err", s_err, 0},
507 {"half", s_cons, 1},
52aa70b5 508 {"dword", s_cons, 3},
3d3c5039 509
670a50eb 510 /* These pseudo-ops are defined in read.c, but must be overridden
3d3c5039 511 here for one reason or another. */
670a50eb
ILT		 512 {"align", s_align, 0},
513 {"byte", s_cons, 0},
514 {"data", s_change_sec, 'd'},
becfe05e 515 {"double", s_float_cons, 'd'},
becfe05e 516 {"float", s_float_cons, 'f'},
c1444ec4
ILT		 517 {"globl", s_mips_globl, 0},
518 {"global", s_mips_globl, 0},
eb8fd0e9
ILT		 519 {"hword", s_cons, 1},
520 {"int", s_cons, 2},
521 {"long", s_cons, 2},
522 {"octa", s_cons, 4},
523 {"quad", s_cons, 3},
524 {"short", s_cons, 1},
525 {"single", s_float_cons, 'f'},
670a50eb
ILT		 526 {"text", s_change_sec, 't'},
527 {"word", s_cons, 2},
739708fa
KR		 528 { 0 },
529};
3d3c5039 530
739708fa 531static const pseudo_typeS mips_nonecoff_pseudo_table[] = {
670a50eb 532 /* These pseudo-ops should be defined by the object file format.
0dd2d296 533 However, a.out doesn't support them, so we have versions here. */
670a50eb 534 {"aent", s_ent, 1},
9226253a 535 {"bgnb", s_ignore, 0},
670a50eb 536 {"end", s_mipsend, 0},
9226253a 537 {"endb", s_ignore, 0},
670a50eb
ILT		 538 {"ent", s_ent, 0},
539 {"file", s_file, 0},
540 {"fmask", s_ignore, 'F'},
541 {"frame", s_ignore, 0},
542 {"loc", s_ignore, 0},
543 {"mask", s_ignore, 'R'},
544 {"verstamp", s_ignore, 0},
739708fa
KR		 545 { 0 },
546};
61420a20 547
739708fa
KR		 548extern void pop_insert PARAMS ((const pseudo_typeS *));
549
550void
551mips_pop_insert ()
552{
553 pop_insert (mips_pseudo_table);
554 if (! ECOFF_DEBUGGING)
555 pop_insert (mips_nonecoff_pseudo_table);
739708fa 556}
3d3c5039 557\f
3d3c5039
ILT		 558static char *expr_end;
559
867a58b3
ILT		 560/* Expressions which appear in instructions. These are set by
561 mips_ip. */
562
3d3c5039
ILT		 563static expressionS imm_expr;
564static expressionS offset_expr;
867a58b3
ILT		 565
566/* Relocs associated with imm_expr and offset_expr. */
567
3d3c5039
ILT		 568static bfd_reloc_code_real_type imm_reloc;
569static bfd_reloc_code_real_type offset_reloc;
570
867a58b3
ILT		 571/* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
572
573static boolean imm_unmatched_hi;
574
3d3c5039
ILT		 575/*
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
578 */
579void
670a50eb 580md_begin ()
3d3c5039 581{
0dd2d296 582 boolean ok = false;
604633ae 583 register const char *retval = NULL;
670a50eb 584 register unsigned int i = 0;
3d3c5039 585
8358c818
ILT		 586 if (mips_isa == -1)
587 {
8c63448a
ILT		 588 const char *cpu;
589 char *a = NULL;
590
591 cpu = TARGET_CPU;
592 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
593 {
594 a = xmalloc (sizeof TARGET_CPU);
595 strcpy (a, TARGET_CPU);
596 a[(sizeof TARGET_CPU) - 3] = '\0';
597 cpu = a;
598 }
599
600 if (strcmp (cpu, "mips") == 0)
601 {
602 mips_isa = 1;
4bb0cc41
ILT		 603 if (mips_cpu == -1)
604 mips_cpu = 3000;
8c63448a
ILT		 605 }
606 else if (strcmp (cpu, "r6000") == 0
607 || strcmp (cpu, "mips2") == 0)
608 {
609 mips_isa = 2;
4bb0cc41
ILT		 610 if (mips_cpu == -1)
611 mips_cpu = 6000;
8c63448a
ILT		 612 }
613 else if (strcmp (cpu, "mips64") == 0
614 || strcmp (cpu, "r4000") == 0
615 || strcmp (cpu, "mips3") == 0)
616 {
617 mips_isa = 3;
4bb0cc41
ILT		 618 if (mips_cpu == -1)
619 mips_cpu = 4000;
8c63448a
ILT		 620 }
621 else if (strcmp (cpu, "r4400") == 0)
622 {
623 mips_isa = 3;
4bb0cc41
ILT		 624 if (mips_cpu == -1)
625 mips_cpu = 4400;
8c63448a
ILT		 626 }
627 else if (strcmp (cpu, "mips64orion") == 0
628 || strcmp (cpu, "r4600") == 0)
629 {
630 mips_isa = 3;
4bb0cc41
ILT		 631 if (mips_cpu == -1)
632 mips_cpu = 4600;
8c63448a 633 }
b2b8c24e
ILT		 634 else if (strcmp (cpu, "r4650") == 0)
635 {
636 mips_isa = 3;
637 if (mips_cpu == -1)
638 mips_cpu = 4650;
639 if (mips_4650 == -1)
640 mips_4650 = 1;
641 }
c625fc23
JSC		 642 else if (strcmp (cpu, "mips64vr4300") == 0)
643 {
644 mips_isa = 3;
645 if (mips_cpu == -1)
646 mips_cpu = 4300;
647 }
648 else if (strcmp (cpu, "mips64vr4100") == 0)
649 {
650 mips_isa = 3;
651 if (mips_cpu == -1)
652 mips_cpu = 4100;
653 if (mips_4100 == -1)
654 mips_4100 = 1;
655 }
e532b44c
ILT		 656 else if (strcmp (cpu, "r4010") == 0)
657 {
658 mips_isa = 2;
659 if (mips_cpu == -1)
660 mips_cpu = 4010;
661 if (mips_4010 == -1)
662 mips_4010 = 1;
663 }
d8a1c247
KR		 664 else if (strcmp (cpu, "r8000") == 0
665 || strcmp (cpu, "mips4") == 0)
666 {
667 mips_isa = 4;
668 if (mips_cpu == -1)
669 mips_cpu = 8000;
670 }
671 else if (strcmp (cpu, "r10000") == 0)
672 {
673 mips_isa = 4;
674 if (mips_cpu == -1)
675 mips_cpu = 10000;
676 }
8358c818 677 else
8c63448a
ILT		 678 {
679 mips_isa = 1;
4bb0cc41
ILT		 680 if (mips_cpu == -1)
681 mips_cpu = 3000;
8c63448a
ILT		 682 }
683
684 if (a != NULL)
685 free (a);
8358c818
ILT		 686 }
687
b2b8c24e
ILT		 688 if (mips_4650 < 0)
689 mips_4650 = 0;
690
e532b44c
ILT		 691 if (mips_4010 < 0)
692 mips_4010 = 0;
693
c625fc23
JSC		 694 if (mips_4100 < 0)
695 mips_4100 = 0;
696
344a8d61 697 if (mips_4650 || mips_4010 || mips_4100 || mips_cpu == 4300)
e532b44c
ILT		 698 interlocks = 1;
699 else
700 interlocks = 0;
701
344a8d61
JSC		 702 if (mips_cpu == 4300)
703 cop_interlocks = 1;
704 else
705 cop_interlocks = 0;
706
8ea7f4e8
ILT		 707 if (mips_isa < 2 && mips_trap)
708 as_bad ("trap exception not supported at ISA 1");
709
97f99d11
ILT		 710 switch (mips_isa)
711 {
712 case 1:
713 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000);
714 break;
715 case 2:
716 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000);
717 break;
718 case 3:
719 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000);
720 break;
d8a1c247
KR		 721 case 4:
722 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000);
723 break;
97f99d11
ILT		 724 }
725 if (! ok)
726 as_warn ("Could not set architecture and machine");
727
1051c97f
ILT		 728 file_mips_isa = mips_isa;
729
13fe1379
ILT		 730 op_hash = hash_new ();
731
670a50eb
ILT		 732 for (i = 0; i < NUMOPCODES;)
733 {
734 const char *name = mips_opcodes[i].name;
735
604633ae 736 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
abdad6bc 737 if (retval != NULL)
670a50eb
ILT		 738 {
739 fprintf (stderr, "internal error: can't hash `%s': %s\n",
740 mips_opcodes[i].name, retval);
741 as_fatal ("Broken assembler. No assembly attempted.");
742 }
743 do
744 {
8358c818
ILT		 745 if (mips_opcodes[i].pinfo != INSN_MACRO
746 && ((mips_opcodes[i].match & mips_opcodes[i].mask)
747 != mips_opcodes[i].match))
670a50eb
ILT		 748 {
749 fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n",
750 mips_opcodes[i].name, mips_opcodes[i].args);
751 as_fatal ("Broken assembler. No assembly attempted.");
3d3c5039 752 }
670a50eb
ILT		 753 ++i;
754 }
755 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3d3c5039
ILT		 756 }
757
becfe05e
ILT		 758 mips_no_prev_insn ();
759
1aa6938e
ILT		 760 mips_gprmask = 0;
761 mips_cprmask[0] = 0;
762 mips_cprmask[1] = 0;
763 mips_cprmask[2] = 0;
764 mips_cprmask[3] = 0;
765
8358c818
ILT		 766 /* set the default alignment for the text section (2**2) */
767 record_alignment (text_section, 2);
768
1dc1e798
KR		 769 if (USE_GLOBAL_POINTER_OPT)
770 bfd_set_gp_size (stdoutput, g_switch_value);
abdad6bc 771
1dc1e798
KR		 772 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
773 {
774 /* Sections must be aligned to 16 byte boundaries. */
775 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
776 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
777 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
778
779 /* Create a .reginfo section for register masks and a .mdebug
780 section for debugging information. */
781 {
782 segT seg;
783 subsegT subseg;
784 segT sec;
785
786 seg = now_seg;
787 subseg = now_subseg;
1dc1e798 788
87178180
ILT		 789 if (! mips_64)
790 {
791 sec = subseg_new (".reginfo", (subsegT) 0);
8358c818 792
87178180
ILT		 793 /* The ABI says this section should be loaded so that the
794 running program can access it. */
795 (void) bfd_set_section_flags (stdoutput, sec,
796 (SEC_ALLOC | SEC_LOAD
797 | SEC_READONLY | SEC_DATA));
798 (void) bfd_set_section_alignment (stdoutput, sec, 2);
799
f2a663d3 800#ifdef OBJ_ELF
87178180 801 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1dc1e798 802#endif
87178180
ILT		 803 }
804 else
805 {
806 /* The 64-bit ABI uses a .MIPS.options section rather than
807 .reginfo section. */
808 sec = subseg_new (".MIPS.options", (subsegT) 0);
809 (void) bfd_set_section_flags (stdoutput, sec,
810 (SEC_ALLOC | SEC_LOAD
811 | SEC_READONLY | SEC_DATA));
812 (void) bfd_set_section_alignment (stdoutput, sec, 3);
813
814#ifdef OBJ_ELF
815 /* Set up the option header. */
816 {
817 Elf_Internal_Options opthdr;
818 char *f;
819
820 opthdr.kind = ODK_REGINFO;
821 opthdr.size = (sizeof (Elf_External_Options)
822 + sizeof (Elf64_External_RegInfo));
823 opthdr.section = 0;
824 opthdr.info = 0;
825 f = frag_more (sizeof (Elf_External_Options));
826 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
827 (Elf_External_Options *) f);
828
829 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
830 }
831#endif
832 }
f2a663d3 833
739708fa
KR		 834 if (ECOFF_DEBUGGING)
835 {
836 sec = subseg_new (".mdebug", (subsegT) 0);
837 (void) bfd_set_section_flags (stdoutput, sec,
838 SEC_HAS_CONTENTS | SEC_READONLY);
839 (void) bfd_set_section_alignment (stdoutput, sec, 2);
840 }
0dd2d296 841
1dc1e798
KR		 842 subseg_set (seg, subseg);
843 }
844 }
f2a663d3 845
739708fa
KR		 846 if (! ECOFF_DEBUGGING)
847 md_obj_begin ();
3d3c5039
ILT		 848}
849
850void
13fe1379 851md_mips_end ()
3d3c5039 852{
739708fa
KR		 853 if (! ECOFF_DEBUGGING)
854 md_obj_end ();
3d3c5039
ILT		 855}
856
857void
670a50eb
ILT		 858md_assemble (str)
859 char *str;
3d3c5039 860{
670a50eb 861 struct mips_cl_insn insn;
3d3c5039 862
5ac34ac3 863 imm_expr.X_op = O_absent;
867a58b3
ILT		 864 imm_reloc = BFD_RELOC_UNUSED;
865 imm_unmatched_hi = false;
5ac34ac3 866 offset_expr.X_op = O_absent;
867a58b3 867 offset_reloc = BFD_RELOC_UNUSED;
3d3c5039 868
670a50eb
ILT		 869 mips_ip (str, &insn);
870 if (insn_error)
871 {
872 as_bad ("%s `%s'", insn_error, str);
873 return;
874 }
875 if (insn.insn_mo->pinfo == INSN_MACRO)
876 {
877 macro (&insn);
3d3c5039 878 }
670a50eb
ILT		 879 else
880 {
5ac34ac3 881 if (imm_expr.X_op != O_absent)
867a58b3
ILT		 882 append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc,
883 imm_unmatched_hi);
5ac34ac3 884 else if (offset_expr.X_op != O_absent)
867a58b3 885 append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false);
670a50eb 886 else
867a58b3 887 append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false);
3d3c5039
ILT		 888 }
889}
890
becfe05e
ILT		 891/* See whether instruction IP reads register REG. If FPR is non-zero,
892 REG is a floating point register. */
893
894static int
895insn_uses_reg (ip, reg, fpr)
896 struct mips_cl_insn *ip;
604633ae 897 unsigned int reg;
becfe05e
ILT		 898 int fpr;
899{
900 /* Don't report on general register 0, since it never changes. */
901 if (! fpr && reg == 0)
902 return 0;
903
904 if (fpr)
905 {
906 /* If we are called with either $f0 or $f1, we must check $f0.
907 This is not optimal, because it will introduce an unnecessary
908 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
909 need to distinguish reading both $f0 and $f1 or just one of
910 them. Note that we don't have to check the other way,
911 because there is no instruction that sets both $f0 and $f1
912 and requires a delay. */
913 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
604633ae
ILT		 914 && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS)
915 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 916 return 1;
917 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
604633ae
ILT		 918 && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT)
919 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 920 return 1;
921 }
922 else
923 {
924 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
925 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
926 return 1;
927 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
928 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
929 return 1;
930 }
931
932 return 0;
933}
934
fb251650
ILT		 935/* This function returns true if modifying a register requires a
936 delay. */
937
938static int
939reg_needs_delay (reg)
940 int reg;
941{
942 unsigned long prev_pinfo;
943
944 prev_pinfo = prev_insn.insn_mo->pinfo;
945 if (! mips_noreorder
946 && mips_isa < 4
947 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
948 || (mips_isa < 2
949 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
950 {
951 /* A load from a coprocessor or from memory. All load
952 delays delay the use of general register rt for one
953 instruction on the r3000. The r6000 and r4000 use
954 interlocks. */
955 know (prev_pinfo & INSN_WRITE_GPR_T);
956 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
957 return 1;
958 }
959
960 return 0;
961}
962
0dd2d296
ILT		 963/* Output an instruction. PLACE is where to put the instruction; if
964 it is NULL, this uses frag_more to get room. IP is the instruction
965 information. ADDRESS_EXPR is an operand of the instruction to be
966 used with RELOC_TYPE. */
3d3c5039 967
3d3c5039 968static void
867a58b3 969append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
0dd2d296 970 char *place;
670a50eb
ILT		 971 struct mips_cl_insn *ip;
972 expressionS *address_expr;
973 bfd_reloc_code_real_type reloc_type;
867a58b3 974 boolean unmatched_hi;
3d3c5039 975{
1aa6938e 976 register unsigned long prev_pinfo, pinfo;
670a50eb 977 char *f;
becfe05e
ILT		 978 fixS *fixp;
979 int nops = 0;
3d3c5039 980
1aa6938e
ILT		 981 prev_pinfo = prev_insn.insn_mo->pinfo;
982 pinfo = ip->insn_mo->pinfo;
983
0dd2d296 984 if (place == NULL && ! mips_noreorder)
becfe05e
ILT		 985 {
986 /* If the previous insn required any delay slots, see if we need
8358c818 987 to insert a NOP or two. There are eight kinds of possible
becfe05e 988 hazards, of which an instruction can have at most one type.
8358c818
ILT		 989 (1) a load from memory delay
990 (2) a load from a coprocessor delay
991 (3) an unconditional branch delay
992 (4) a conditional branch delay
993 (5) a move to coprocessor register delay
994 (6) a load coprocessor register from memory delay
995 (7) a coprocessor condition code delay
996 (8) a HI/LO special register delay
becfe05e
ILT		 997
998 There are a lot of optimizations we could do that we don't.
999 In particular, we do not, in general, reorder instructions.
1000 If you use gcc with optimization, it will reorder
1001 instructions and generally do much more optimization then we
1002 do here; repeating all that work in the assembler would only
1003 benefit hand written assembly code, and does not seem worth
1004 it. */
1005
1006 /* This is how a NOP is emitted. */
1007#define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1008
1009 /* The previous insn might require a delay slot, depending upon
1010 the contents of the current insn. */
d8a1c247 1011 if (mips_isa < 4
5af96dce
ILT		 1012 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1013 && ! cop_interlocks)
d8a1c247
KR		 1014 || (mips_isa < 2
1015 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
8358c818
ILT		 1016 {
1017 /* A load from a coprocessor or from memory. All load
1018 delays delay the use of general register rt for one
1019 instruction on the r3000. The r6000 and r4000 use
1020 interlocks. */
1aa6938e 1021 know (prev_pinfo & INSN_WRITE_GPR_T);
0aa07269
ILT		 1022 if (mips_optimize == 0
1023 || insn_uses_reg (ip,
1024 ((prev_insn.insn_opcode >> OP_SH_RT)
1025 & OP_MASK_RT),
1026 0))
becfe05e
ILT		 1027 ++nops;
1028 }
d8a1c247 1029 else if (mips_isa < 4
5af96dce
ILT		 1030 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1031 && ! cop_interlocks)
d8a1c247
KR		 1032 || (mips_isa < 2
1033 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
becfe05e
ILT		 1034 {
1035 /* A generic coprocessor delay. The previous instruction
1036 modified a coprocessor general or control register. If
1037 it modified a control register, we need to avoid any
1038 coprocessor instruction (this is probably not always
1039 required, but it sometimes is). If it modified a general
1040 register, we avoid using that register.
1041
8358c818
ILT		 1042 On the r6000 and r4000 loading a coprocessor register
1043 from memory is interlocked, and does not require a delay.
1044
becfe05e
ILT		 1045 This case is not handled very well. There is no special
1046 knowledge of CP0 handling, and the coprocessors other
1047 than the floating point unit are not distinguished at
1048 all. */
1aa6938e 1049 if (prev_pinfo & INSN_WRITE_FPR_T)
becfe05e 1050 {
0aa07269
ILT		 1051 if (mips_optimize == 0
1052 || insn_uses_reg (ip,
8358c818
ILT		 1053 ((prev_insn.insn_opcode >> OP_SH_FT)
1054 & OP_MASK_FT),
0aa07269 1055 1))
becfe05e
ILT		 1056 ++nops;
1057 }
1aa6938e 1058 else if (prev_pinfo & INSN_WRITE_FPR_S)
becfe05e 1059 {
0aa07269
ILT		 1060 if (mips_optimize == 0
1061 || insn_uses_reg (ip,
8358c818
ILT		 1062 ((prev_insn.insn_opcode >> OP_SH_FS)
1063 & OP_MASK_FS),
0aa07269 1064 1))
becfe05e
ILT		 1065 ++nops;
1066 }
1067 else
1068 {
1069 /* We don't know exactly what the previous instruction
1070 does. If the current instruction uses a coprocessor
1071 register, we must insert a NOP. If previous
1072 instruction may set the condition codes, and the
1073 current instruction uses them, we must insert two
1074 NOPS. */
0aa07269 1075 if (mips_optimize == 0
1aa6938e
ILT		 1076 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1077 && (pinfo & INSN_READ_COND_CODE)))
becfe05e 1078 nops += 2;
1aa6938e 1079 else if (pinfo & INSN_COP)
becfe05e
ILT		 1080 ++nops;
1081 }
1082 }
d8a1c247 1083 else if (mips_isa < 4
344a8d61
JSC		 1084 && (prev_pinfo & INSN_WRITE_COND_CODE)
1085 && ! cop_interlocks)
becfe05e
ILT		 1086 {
1087 /* The previous instruction sets the coprocessor condition
1088 codes, but does not require a general coprocessor delay
1089 (this means it is a floating point comparison
1090 instruction). If this instruction uses the condition
1091 codes, we need to insert a single NOP. */
0aa07269 1092 if (mips_optimize == 0
1aa6938e 1093 || (pinfo & INSN_READ_COND_CODE))
becfe05e
ILT		 1094 ++nops;
1095 }
1aa6938e 1096 else if (prev_pinfo & INSN_READ_LO)
becfe05e
ILT		 1097 {
1098 /* The previous instruction reads the LO register; if the
1099 current instruction writes to the LO register, we must
344a8d61
JSC		 1100 insert two NOPS. The R4650, VR4100 and VR4300 have
1101 interlocks. */
e532b44c 1102 if (! interlocks
b2b8c24e
ILT		 1103 && (mips_optimize == 0
1104 || (pinfo & INSN_WRITE_LO)))
becfe05e
ILT		 1105 nops += 2;
1106 }
1107 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1108 {
1109 /* The previous instruction reads the HI register; if the
1110 current instruction writes to the HI register, we must
344a8d61
JSC		 1111 insert a NOP. The R4650, VR4100 and VR4300 have
1112 interlocks. */
e532b44c 1113 if (! interlocks
b2b8c24e
ILT		 1114 && (mips_optimize == 0
1115 || (pinfo & INSN_WRITE_HI)))
becfe05e
ILT		 1116 nops += 2;
1117 }
1118
1119 /* There are two cases which require two intervening
1120 instructions: 1) setting the condition codes using a move to
1121 coprocessor instruction which requires a general coprocessor
1122 delay and then reading the condition codes 2) reading the HI
b2b8c24e 1123 or LO register and then writing to it (except on the R4650,
344a8d61
JSC		 1124 VR4100, and VR4300 which have interlocks). If we are not
1125 already emitting a NOP instruction, we must check for these
1126 cases compared to the instruction previous to the previous
c625fc23 1127 instruction. */
becfe05e 1128 if (nops == 0
d8a1c247
KR		 1129 && ((mips_isa < 4
1130 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
becfe05e 1131 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
344a8d61
JSC		 1132 && (pinfo & INSN_READ_COND_CODE)
1133 && ! cop_interlocks)
becfe05e 1134 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
b2b8c24e 1135 && (pinfo & INSN_WRITE_LO)
e532b44c 1136 && ! interlocks)
becfe05e 1137 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
b2b8c24e 1138 && (pinfo & INSN_WRITE_HI)
e532b44c 1139 && ! interlocks)))
becfe05e
ILT		 1140 ++nops;
1141
0dd2d296
ILT		 1142 /* If we are being given a nop instruction, don't bother with
1143 one of the nops we would otherwise output. This will only
1144 happen when a nop instruction is used with mips_optimize set
1145 to 0. */
1146 if (nops > 0 && ip->insn_opcode == 0)
1147 --nops;
1148
becfe05e
ILT		 1149 /* Now emit the right number of NOP instructions. */
1150 if (nops > 0)
1151 {
5af96dce
ILT		 1152 fragS *old_frag;
1153 unsigned long old_frag_offset;
8c63448a
ILT		 1154 int i;
1155
5af96dce
ILT		 1156 old_frag = frag_now;
1157 old_frag_offset = frag_now_fix ();
1158
8c63448a 1159 for (i = 0; i < nops; i++)
becfe05e 1160 emit_nop ();
5af96dce 1161
af255ca0 1162 if (listing)
546f5536
ILT		 1163 {
1164 listing_prev_line ();
1165 /* We may be at the start of a variant frag. In case we
1166 are, make sure there is enough space for the frag
1167 after the frags created by listing_prev_line. The
1168 argument to frag_grow here must be at least as large
1169 as the argument to all other calls to frag_grow in
1170 this file. We don't have to worry about being in the
1171 middle of a variant frag, because the variants insert
1172 all needed nop instructions themselves. */
1173 frag_grow (40);
1174 }
5af96dce 1175
becfe05e
ILT		 1176 if (insn_label != NULL)
1177 {
1178 assert (S_GET_SEGMENT (insn_label) == now_seg);
1179 insn_label->sy_frag = frag_now;
604633ae 1180 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e 1181 }
5af96dce
ILT		 1182
1183#ifndef NO_ECOFF_DEBUGGING
1184 if (ECOFF_DEBUGGING)
1185 ecoff_fix_loc (old_frag, old_frag_offset);
1186#endif
becfe05e
ILT		 1187 }
1188 }
1189
0dd2d296
ILT		 1190 if (place == NULL)
1191 f = frag_more (4);
1192 else
1193 f = place;
becfe05e 1194 fixp = NULL;
670a50eb
ILT		 1195 if (address_expr != NULL)
1196 {
5ac34ac3 1197 if (address_expr->X_op == O_constant)
670a50eb
ILT		 1198 {
1199 switch (reloc_type)
1200 {
3d3c5039 1201 case BFD_RELOC_32:
670a50eb
ILT		 1202 ip->insn_opcode |= address_expr->X_add_number;
1203 break;
3d3c5039
ILT		 1204
1205 case BFD_RELOC_LO16:
670a50eb
ILT		 1206 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1207 break;
3d3c5039
ILT		 1208
1209 case BFD_RELOC_MIPS_JMP:
1210 case BFD_RELOC_16_PCREL_S2:
670a50eb 1211 goto need_reloc;
3d3c5039
ILT		 1212
1213 default:
670a50eb 1214 internalError ();
3d3c5039 1215 }
670a50eb
ILT		 1216 }
1217 else
1218 {
1219 assert (reloc_type != BFD_RELOC_UNUSED);
3d3c5039 1220 need_reloc:
0dd2d296
ILT		 1221 /* Don't generate a reloc if we are writing into a variant
1222 frag. */
1223 if (place == NULL)
867a58b3
ILT		 1224 {
1225 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1226 address_expr,
1227 reloc_type == BFD_RELOC_16_PCREL_S2,
1228 reloc_type);
1229 if (unmatched_hi)
1230 {
1231 struct mips_hi_fixup *hi_fixup;
1232
1233 assert (reloc_type == BFD_RELOC_HI16_S);
1234 hi_fixup = ((struct mips_hi_fixup *)
1235 xmalloc (sizeof (struct mips_hi_fixup)));
1236 hi_fixup->fixp = fixp;
1237 hi_fixup->seg = now_seg;
1238 hi_fixup->next = mips_hi_fixup_list;
1239 mips_hi_fixup_list = hi_fixup;
1240 }
1241 }
3d3c5039
ILT		 1242 }
1243 }
becfe05e 1244
670a50eb
ILT		 1245 md_number_to_chars (f, ip->insn_opcode, 4);
1246
1aa6938e
ILT		 1247 /* Update the register mask information. */
1248 if (pinfo & INSN_WRITE_GPR_D)
1249 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
1250 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
1251 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
1252 if (pinfo & INSN_READ_GPR_S)
1253 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
1254 if (pinfo & INSN_WRITE_GPR_31)
1255 mips_gprmask |= 1 << 31;
1256 if (pinfo & INSN_WRITE_FPR_D)
1257 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
1258 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
1259 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
1260 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
1261 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
d8a1c247
KR		 1262 if ((pinfo & INSN_READ_FPR_R) != 0)
1263 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
1aa6938e
ILT		 1264 if (pinfo & INSN_COP)
1265 {
1266 /* We don't keep enough information to sort these cases out. */
1267 }
1268 /* Never set the bit for $0, which is always zero. */
1269 mips_gprmask &=~ 1 << 0;
1270
0dd2d296 1271 if (place == NULL && ! mips_noreorder)
670a50eb 1272 {
becfe05e
ILT		 1273 /* Filling the branch delay slot is more complex. We try to
1274 switch the branch with the previous instruction, which we can
1275 do if the previous instruction does not set up a condition
1276 that the branch tests and if the branch is not itself the
1277 target of any branch. */
1aa6938e
ILT		 1278 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
1279 || (pinfo & INSN_COND_BRANCH_DELAY))
becfe05e 1280 {
0aa07269 1281 if (mips_optimize < 2
19ed8960
ILT		 1282 /* If we have seen .set volatile or .set nomove, don't
1283 optimize. */
1284 || mips_nomove != 0
4e95866e
ILT		 1285 /* If we had to emit any NOP instructions, then we
1286 already know we can not swap. */
1287 || nops != 0
becfe05e
ILT		 1288 /* If we don't even know the previous insn, we can not
1289 swap. */
1290 || ! prev_insn_valid
1291 /* If the previous insn is already in a branch delay
1292 slot, then we can not swap. */
1293 || prev_insn_is_delay_slot
4e95866e
ILT		 1294 /* If the previous previous insn was in a .set
1295 noreorder, we can't swap. Actually, the MIPS
1296 assembler will swap in this situation. However, gcc
1297 configured -with-gnu-as will generate code like
1298 .set noreorder
1299 lw $4,XXX
1300 .set reorder
1301 INSN
1302 bne $4,$0,foo
1303 in which we can not swap the bne and INSN. If gcc is
1304 not configured -with-gnu-as, it does not output the
1305 .set pseudo-ops. We don't have to check
1306 prev_insn_unreordered, because prev_insn_valid will
1307 be 0 in that case. We don't want to use
1308 prev_prev_insn_valid, because we do want to be able
1309 to swap at the start of a function. */
1310 || prev_prev_insn_unreordered
becfe05e
ILT		 1311 /* If the branch is itself the target of a branch, we
1312 can not swap. We cheat on this; all we check for is
1313 whether there is a label on this instruction. If
1314 there are any branches to anything other than a
1315 label, users must use .set noreorder. */
1316 || insn_label != NULL
777ad64d
ILT		 1317 /* If the previous instruction is in a variant frag, we
1318 can not do the swap. */
1319 || prev_insn_frag->fr_type == rs_machine_dependent
becfe05e
ILT		 1320 /* If the branch reads the condition codes, we don't
1321 even try to swap, because in the sequence
1322 ctc1 $X,$31
1323 INSN
1324 INSN
1325 bc1t LABEL
1326 we can not swap, and I don't feel like handling that
1327 case. */
d8a1c247
KR		 1328 || (mips_isa < 4
1329 && (pinfo & INSN_READ_COND_CODE))
becfe05e
ILT		 1330 /* We can not swap with an instruction that requires a
1331 delay slot, becase the target of the branch might
1332 interfere with that instruction. */
d8a1c247
KR		 1333 || (mips_isa < 4
1334 && (prev_pinfo
1335 & (INSN_LOAD_COPROC_DELAY
1336 | INSN_COPROC_MOVE_DELAY
1337 | INSN_WRITE_COND_CODE)))
e532b44c 1338 || (! interlocks
b2b8c24e
ILT		 1339 && (prev_pinfo
1340 & (INSN_READ_LO
1341 | INSN_READ_HI)))
8358c818 1342 || (mips_isa < 2
1aa6938e 1343 && (prev_pinfo
8358c818
ILT		 1344 & (INSN_LOAD_MEMORY_DELAY
1345 | INSN_COPROC_MEMORY_DELAY)))
becfe05e 1346 /* We can not swap with a branch instruction. */
1aa6938e 1347 || (prev_pinfo
6e8dda9c
ILT		 1348 & (INSN_UNCOND_BRANCH_DELAY
1349 | INSN_COND_BRANCH_DELAY
1350 | INSN_COND_BRANCH_LIKELY))
abdad6bc
ILT		 1351 /* We do not swap with a trap instruction, since it
1352 complicates trap handlers to have the trap
1353 instruction be in a delay slot. */
1aa6938e 1354 || (prev_pinfo & INSN_TRAP)
becfe05e
ILT		 1355 /* If the branch reads a register that the previous
1356 instruction sets, we can not swap. */
1aa6938e 1357 || ((prev_pinfo & INSN_WRITE_GPR_T)
becfe05e
ILT		 1358 && insn_uses_reg (ip,
1359 ((prev_insn.insn_opcode >> OP_SH_RT)
1360 & OP_MASK_RT),
1361 0))
1aa6938e 1362 || ((prev_pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 1363 && insn_uses_reg (ip,
1364 ((prev_insn.insn_opcode >> OP_SH_RD)
1365 & OP_MASK_RD),
1366 0))
1849d646
ILT		 1367 /* If the branch writes a register that the previous
1368 instruction sets, we can not swap (we know that
1369 branches write only to RD or to $31). */
1aa6938e
ILT		 1370 || ((prev_pinfo & INSN_WRITE_GPR_T)
1371 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 1372 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
1373 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 1374 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 1375 && (((prev_insn.insn_opcode >> OP_SH_RT)
1376 & OP_MASK_RT)
1377 == 31))))
1aa6938e
ILT		 1378 || ((prev_pinfo & INSN_WRITE_GPR_D)
1379 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 1380 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
1381 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 1382 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 1383 && (((prev_insn.insn_opcode >> OP_SH_RD)
1384 & OP_MASK_RD)
1385 == 31))))
becfe05e
ILT		 1386 /* If the branch writes a register that the previous
1387 instruction reads, we can not swap (we know that
1388 branches only write to RD or to $31). */
1aa6938e 1389 || ((pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 1390 && insn_uses_reg (&prev_insn,
1391 ((ip->insn_opcode >> OP_SH_RD)
1392 & OP_MASK_RD),
1393 0))
1aa6938e 1394 || ((pinfo & INSN_WRITE_GPR_31)
becfe05e 1395 && insn_uses_reg (&prev_insn, 31, 0))
5b63f465
ILT		 1396 /* If we are generating embedded PIC code, the branch
1397 might be expanded into a sequence which uses $at, so
1398 we can't swap with an instruction which reads it. */
1399 || (mips_pic == EMBEDDED_PIC
1400 && insn_uses_reg (&prev_insn, AT, 0))
becfe05e
ILT		 1401 /* If the previous previous instruction has a load
1402 delay, and sets a register that the branch reads, we
1403 can not swap. */
d8a1c247
KR		 1404 || (mips_isa < 4
1405 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
1406 || (mips_isa < 2
1407 && (prev_prev_insn.insn_mo->pinfo
1408 & INSN_LOAD_MEMORY_DELAY)))
becfe05e
ILT		 1409 && insn_uses_reg (ip,
1410 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
1411 & OP_MASK_RT),
1412 0)))
1413 {
1414 /* We could do even better for unconditional branches to
1415 portions of this object file; we could pick up the
1416 instruction at the destination, put it in the delay
1417 slot, and bump the destination address. */
1418 emit_nop ();
1419 /* Update the previous insn information. */
1420 prev_prev_insn = *ip;
1421 prev_insn.insn_mo = &dummy_opcode;
1422 }
1423 else
1424 {
1425 char *prev_f;
1426 char temp[4];
1427
1428 /* It looks like we can actually do the swap. */
1429 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
1430 memcpy (temp, prev_f, 4);
1431 memcpy (prev_f, f, 4);
1432 memcpy (f, temp, 4);
1433 if (prev_insn_fixp)
1434 {
1435 prev_insn_fixp->fx_frag = frag_now;
1436 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
1437 }
1438 if (fixp)
1439 {
1440 fixp->fx_frag = prev_insn_frag;
1441 fixp->fx_where = prev_insn_where;
1442 }
1443 /* Update the previous insn information; leave prev_insn
1444 unchanged. */
1445 prev_prev_insn = *ip;
1446 }
1447 prev_insn_is_delay_slot = 1;
1448
1449 /* If that was an unconditional branch, forget the previous
1450 insn information. */
1aa6938e 1451 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
becfe05e
ILT		 1452 {
1453 prev_prev_insn.insn_mo = &dummy_opcode;
1454 prev_insn.insn_mo = &dummy_opcode;
1455 }
1456 }
1aa6938e 1457 else if (pinfo & INSN_COND_BRANCH_LIKELY)
8358c818
ILT		 1458 {
1459 /* We don't yet optimize a branch likely. What we should do
1460 is look at the target, copy the instruction found there
1461 into the delay slot, and increment the branch to jump to
1462 the next instruction. */
1463 emit_nop ();
1464 /* Update the previous insn information. */
1465 prev_prev_insn = *ip;
1466 prev_insn.insn_mo = &dummy_opcode;
1467 }
becfe05e 1468 else
670a50eb 1469 {
becfe05e
ILT		 1470 /* Update the previous insn information. */
1471 if (nops > 0)
1472 prev_prev_insn.insn_mo = &dummy_opcode;
1473 else
1474 prev_prev_insn = prev_insn;
1475 prev_insn = *ip;
1476
1477 /* Any time we see a branch, we always fill the delay slot
1478 immediately; since this insn is not a branch, we know it
1479 is not in a delay slot. */
1480 prev_insn_is_delay_slot = 0;
1481 }
1482
4e95866e
ILT		 1483 prev_prev_insn_unreordered = prev_insn_unreordered;
1484 prev_insn_unreordered = 0;
becfe05e
ILT		 1485 prev_insn_frag = frag_now;
1486 prev_insn_where = f - frag_now->fr_literal;
1487 prev_insn_fixp = fixp;
1488 prev_insn_valid = 1;
1489 }
3d3c5039 1490
becfe05e
ILT		 1491 /* We just output an insn, so the next one doesn't have a label. */
1492 insn_label = NULL;
1493}
1494
1495/* This function forgets that there was any previous instruction or
1496 label. */
1497
1498static void
1499mips_no_prev_insn ()
1500{
1501 prev_insn.insn_mo = &dummy_opcode;
1502 prev_prev_insn.insn_mo = &dummy_opcode;
1503 prev_insn_valid = 0;
1504 prev_insn_is_delay_slot = 0;
4e95866e
ILT		 1505 prev_insn_unreordered = 0;
1506 prev_prev_insn_unreordered = 0;
becfe05e
ILT		 1507 insn_label = NULL;
1508}
1509
1510/* This function must be called whenever we turn on noreorder or emit
1511 something other than instructions. It inserts any NOPS which might
1512 be needed by the previous instruction, and clears the information
1513 kept for the previous instructions. */
1514
1515static void
1516mips_emit_delays ()
1517{
1518 if (! mips_noreorder)
1519 {
1520 int nop;
1521
1522 nop = 0;
d8a1c247 1523 if ((mips_isa < 4
344a8d61
JSC		 1524 && (! cop_interlocks
1525 && (prev_insn.insn_mo->pinfo
1526 & (INSN_LOAD_COPROC_DELAY
1527 | INSN_COPROC_MOVE_DELAY
1528 | INSN_WRITE_COND_CODE))))
e532b44c 1529 || (! interlocks
b2b8c24e
ILT		 1530 && (prev_insn.insn_mo->pinfo
1531 & (INSN_READ_LO
1532 | INSN_READ_HI)))
8358c818
ILT		 1533 || (mips_isa < 2
1534 && (prev_insn.insn_mo->pinfo
1535 & (INSN_LOAD_MEMORY_DELAY
1536 | INSN_COPROC_MEMORY_DELAY))))
becfe05e
ILT		 1537 {
1538 nop = 1;
d8a1c247 1539 if ((mips_isa < 4
344a8d61
JSC		 1540 && (! cop_interlocks
1541 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
e532b44c 1542 || (! interlocks
b2b8c24e
ILT		 1543 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
1544 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
becfe05e
ILT		 1545 emit_nop ();
1546 }
d8a1c247 1547 else if ((mips_isa < 4
344a8d61
JSC		 1548 && (! cop_interlocks
1549 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
e532b44c 1550 || (! interlocks
b2b8c24e
ILT		 1551 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1552 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
becfe05e
ILT		 1553 nop = 1;
1554 if (nop)
670a50eb 1555 {
becfe05e
ILT		 1556 emit_nop ();
1557 if (insn_label != NULL)
1558 {
1559 assert (S_GET_SEGMENT (insn_label) == now_seg);
1560 insn_label->sy_frag = frag_now;
604633ae 1561 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e 1562 }
3d3c5039
ILT		 1563 }
1564 }
0221ddf7
ILT		 1565
1566 mips_no_prev_insn ();
3d3c5039
ILT		 1567}
1568
670a50eb
ILT		 1569/* Build an instruction created by a macro expansion. This is passed
1570 a pointer to the count of instructions created so far, an
1571 expression, the name of the instruction to build, an operand format
1572 string, and corresponding arguments. */
1573
1dc1e798 1574#ifdef USE_STDARG
3d3c5039 1575static void
0dd2d296
ILT		 1576macro_build (char *place,
1577 int *counter,
670a50eb 1578 expressionS * ep,
3d3c5039
ILT		 1579 const char *name,
1580 const char *fmt,
1581 ...)
1dc1e798 1582#else
3d3c5039 1583static void
0dd2d296
ILT		 1584macro_build (place, counter, ep, name, fmt, va_alist)
1585 char *place;
3d3c5039
ILT		 1586 int *counter;
1587 expressionS *ep;
1588 const char *name;
1589 const char *fmt;
1590 va_dcl
1dc1e798 1591#endif
3d3c5039 1592{
670a50eb
ILT		 1593 struct mips_cl_insn insn;
1594 bfd_reloc_code_real_type r;
1595 va_list args;
3d3c5039 1596
1dc1e798 1597#ifdef USE_STDARG
670a50eb 1598 va_start (args, fmt);
3d3c5039 1599#else
670a50eb 1600 va_start (args);
3d3c5039
ILT		 1601#endif
1602
670a50eb
ILT		 1603 /*
1604 * If the macro is about to expand into a second instruction,
1605 * print a warning if needed. We need to pass ip as a parameter
1606 * to generate a better warning message here...
1607 */
0dd2d296 1608 if (mips_warn_about_macros && place == NULL && *counter == 1)
670a50eb
ILT		 1609 as_warn ("Macro instruction expanded into multiple instructions");
1610
0dd2d296
ILT		 1611 if (place == NULL)
1612 *counter += 1; /* bump instruction counter */
670a50eb
ILT		 1613
1614 r = BFD_RELOC_UNUSED;
1615 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1616 assert (insn.insn_mo);
1617 assert (strcmp (name, insn.insn_mo->name) == 0);
1618
9226253a 1619 while (strcmp (fmt, insn.insn_mo->args) != 0
c625fc23
JSC		 1620 || insn.insn_mo->pinfo == INSN_MACRO
1621 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2
1622 && mips_isa < 2)
1623 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3
1624 && mips_isa < 3)
1625 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4
1626 && mips_isa < 4)
1627 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650
1628 && ! mips_4650)
1629 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010
1630 && ! mips_4010)
1631 || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100
1632 && ! mips_4100))
670a50eb
ILT		 1633 {
1634 ++insn.insn_mo;
1635 assert (insn.insn_mo->name);
1636 assert (strcmp (name, insn.insn_mo->name) == 0);
3d3c5039 1637 }
670a50eb
ILT		 1638 insn.insn_opcode = insn.insn_mo->match;
1639 for (;;)
1640 {
1641 switch (*fmt++)
1642 {
3d3c5039 1643 case '\0':
670a50eb 1644 break;
3d3c5039
ILT		 1645
1646 case ',':
1647 case '(':
1648 case ')':
670a50eb 1649 continue;
3d3c5039
ILT		 1650
1651 case 't':
1652 case 'w':
918692a5 1653 case 'E':
670a50eb
ILT		 1654 insn.insn_opcode |= va_arg (args, int) << 16;
1655 continue;
3d3c5039
ILT		 1656
1657 case 'c':
1658 case 'T':
1659 case 'W':
670a50eb
ILT		 1660 insn.insn_opcode |= va_arg (args, int) << 16;
1661 continue;
3d3c5039
ILT		 1662
1663 case 'd':
918692a5 1664 case 'G':
670a50eb
ILT		 1665 insn.insn_opcode |= va_arg (args, int) << 11;
1666 continue;
3d3c5039
ILT		 1667
1668 case 'V':
1669 case 'S':
670a50eb
ILT		 1670 insn.insn_opcode |= va_arg (args, int) << 11;
1671 continue;
3d3c5039 1672
ff3a5c18
ILT		 1673 case 'z':
1674 continue;
1675
3d3c5039 1676 case '<':
670a50eb
ILT		 1677 insn.insn_opcode |= va_arg (args, int) << 6;
1678 continue;
3d3c5039
ILT		 1679
1680 case 'D':
670a50eb
ILT		 1681 insn.insn_opcode |= va_arg (args, int) << 6;
1682 continue;
3d3c5039 1683
918692a5
ILT		 1684 case 'B':
1685 insn.insn_opcode |= va_arg (args, int) << 6;
1686 continue;
1687
3d3c5039
ILT		 1688 case 'b':
1689 case 's':
1690 case 'r':
1691 case 'v':
670a50eb
ILT		 1692 insn.insn_opcode |= va_arg (args, int) << 21;
1693 continue;
3d3c5039
ILT		 1694
1695 case 'i':
1696 case 'j':
1697 case 'o':
9226253a 1698 r = (bfd_reloc_code_real_type) va_arg (args, int);
0dd2d296
ILT		 1699 assert (r == BFD_RELOC_MIPS_GPREL
1700 || r == BFD_RELOC_MIPS_LITERAL
1701 || r == BFD_RELOC_LO16
1702 || r == BFD_RELOC_MIPS_GOT16
ecd4ca1c 1703 || r == BFD_RELOC_MIPS_CALL16
fb251650
ILT		 1704 || r == BFD_RELOC_MIPS_GOT_LO16
1705 || r == BFD_RELOC_MIPS_CALL_LO16
ecd4ca1c
ILT		 1706 || (ep->X_op == O_subtract
1707 && now_seg == text_section
ecd4ca1c 1708 && r == BFD_RELOC_PCREL_LO16));
670a50eb 1709 continue;
3d3c5039 1710
6e8dda9c 1711 case 'u':
ecd4ca1c
ILT		 1712 r = (bfd_reloc_code_real_type) va_arg (args, int);
1713 assert (ep != NULL
1714 && (ep->X_op == O_constant
1715 || (ep->X_op == O_symbol
1716 && (r == BFD_RELOC_HI16_S
fb251650
ILT		 1717 || r == BFD_RELOC_HI16
1718 || r == BFD_RELOC_MIPS_GOT_HI16
1719 || r == BFD_RELOC_MIPS_CALL_HI16))
ecd4ca1c
ILT		 1720 || (ep->X_op == O_subtract
1721 && now_seg == text_section
ecd4ca1c
ILT		 1722 && r == BFD_RELOC_PCREL_HI16_S)));
1723 if (ep->X_op == O_constant)
1724 {
1725 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
1726 ep = NULL;
1727 r = BFD_RELOC_UNUSED;
1728 }
6e8dda9c
ILT		 1729 continue;
1730
3d3c5039 1731 case 'p':
670a50eb
ILT		 1732 assert (ep != NULL);
1733 /*
1734 * This allows macro() to pass an immediate expression for
1735 * creating short branches without creating a symbol.
1736 * Note that the expression still might come from the assembly
1737 * input, in which case the value is not checked for range nor
1738 * is a relocation entry generated (yuck).
1739 */
5ac34ac3 1740 if (ep->X_op == O_constant)
670a50eb
ILT		 1741 {
1742 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
1743 ep = NULL;
1744 }
1745 else
1746 r = BFD_RELOC_16_PCREL_S2;
1747 continue;
3d3c5039 1748
9226253a
ILT		 1749 case 'a':
1750 assert (ep != NULL);
1751 r = BFD_RELOC_MIPS_JMP;
1752 continue;
1753
3d3c5039 1754 default:
670a50eb 1755 internalError ();
3d3c5039 1756 }
670a50eb 1757 break;
3d3c5039 1758 }
670a50eb
ILT		 1759 va_end (args);
1760 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1761
867a58b3 1762 append_insn (place, &insn, ep, r, false);
3d3c5039
ILT		 1763}
1764
1765/*
1766 * Generate a "lui" instruction.
1767 */
1768static void
0dd2d296
ILT		 1769macro_build_lui (place, counter, ep, regnum)
1770 char *place;
3d3c5039
ILT		 1771 int *counter;
1772 expressionS *ep;
1773 int regnum;
1774{
670a50eb
ILT		 1775 expressionS high_expr;
1776 struct mips_cl_insn insn;
1777 bfd_reloc_code_real_type r;
1778 CONST char *name = "lui";
1779 CONST char *fmt = "t,u";
1780
0dd2d296
ILT		 1781 if (place == NULL)
1782 high_expr = *ep;
1783 else
1784 {
1785 high_expr.X_op = O_constant;
fb251650 1786 high_expr.X_add_number = ep->X_add_number;
0dd2d296 1787 }
670a50eb 1788
5ac34ac3 1789 if (high_expr.X_op == O_constant)
670a50eb
ILT		 1790 {
1791 /* we can compute the instruction now without a relocation entry */
1792 if (high_expr.X_add_number & 0x8000)
1793 high_expr.X_add_number += 0x10000;
1794 high_expr.X_add_number =
1795 ((unsigned long) high_expr.X_add_number >> 16) & 0xffff;
1796 r = BFD_RELOC_UNUSED;
1797 }
1798 else
0dd2d296
ILT		 1799 {
1800 assert (ep->X_op == O_symbol);
1801 /* _gp_disp is a special case, used from s_cpload. */
d9aba805 1802 assert (mips_pic == NO_PIC
0dd2d296
ILT		 1803 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
1804 r = BFD_RELOC_HI16_S;
1805 }
670a50eb
ILT		 1806
1807 /*
1808 * If the macro is about to expand into a second instruction,
1809 * print a warning if needed. We need to pass ip as a parameter
1810 * to generate a better warning message here...
1811 */
0dd2d296 1812 if (mips_warn_about_macros && place == NULL && *counter == 1)
670a50eb
ILT		 1813 as_warn ("Macro instruction expanded into multiple instructions");
1814
0dd2d296
ILT		 1815 if (place == NULL)
1816 *counter += 1; /* bump instruction counter */
670a50eb
ILT		 1817
1818 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1819 assert (insn.insn_mo);
1820 assert (strcmp (name, insn.insn_mo->name) == 0);
1821 assert (strcmp (fmt, insn.insn_mo->args) == 0);
1822
0dd2d296 1823 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
670a50eb
ILT		 1824 if (r == BFD_RELOC_UNUSED)
1825 {
1826 insn.insn_opcode |= high_expr.X_add_number;
867a58b3 1827 append_insn (place, &insn, NULL, r, false);
670a50eb
ILT		 1828 }
1829 else
867a58b3 1830 append_insn (place, &insn, &high_expr, r, false);
3d3c5039
ILT		 1831}
1832
1833/* set_at()
1834 * Generates code to set the $at register to true (one)
1835 * if reg is less than the immediate expression.
1836 */
1837static void
6e8dda9c 1838set_at (counter, reg, unsignedp)
3d3c5039
ILT		 1839 int *counter;
1840 int reg;
6e8dda9c 1841 int unsignedp;
3d3c5039 1842{
6e8dda9c 1843 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
0dd2d296 1844 macro_build ((char *) NULL, counter, &imm_expr,
6e8dda9c 1845 unsignedp ? "sltiu" : "slti",
9226253a 1846 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
6e8dda9c 1847 else
670a50eb 1848 {
d8a1c247 1849 load_register (counter, AT, &imm_expr, 0);
0dd2d296 1850 macro_build ((char *) NULL, counter, NULL,
6e8dda9c
ILT		 1851 unsignedp ? "sltu" : "slt",
1852 "d,v,t", AT, reg, AT);
670a50eb 1853 }
3d3c5039
ILT		 1854}
1855
6e8dda9c 1856/* Warn if an expression is not a constant. */
3d3c5039
ILT		 1857
1858static void
19ed8960 1859check_absolute_expr (ip, ex)
3d3c5039 1860 struct mips_cl_insn *ip;
19ed8960 1861 expressionS *ex;
3d3c5039 1862{
19ed8960 1863 if (ex->X_op != O_constant)
670a50eb 1864 as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name);
3d3c5039
ILT		 1865}
1866
1867/* load_register()
1868 * This routine generates the least number of instructions neccessary to load
1869 * an absolute expression value into a register.
1870 */
1871static void
d8a1c247 1872load_register (counter, reg, ep, dbl)
670a50eb 1873 int *counter;
670a50eb
ILT		 1874 int reg;
1875 expressionS *ep;
d8a1c247 1876 int dbl;
3d3c5039 1877{
d8a1c247 1878 int shift, freg;
711254da 1879 expressionS hi32, lo32;
847a01cd
ILT		 1880
1881 if (ep->X_op != O_big)
6e8dda9c 1882 {
847a01cd 1883 assert (ep->X_op == O_constant);
d8a1c247
KR		 1884 if (ep->X_add_number < 0x8000
1885 && (ep->X_add_number >= 0
1886 || (ep->X_add_number >= -0x8000
1887 && (! dbl
1888 || ! ep->X_unsigned
1889 || sizeof (ep->X_add_number) > 4))))
847a01cd
ILT		 1890 {
1891 /* We can handle 16 bit signed values with an addiu to
1892 $zero. No need to ever use daddiu here, since $zero and
1893 the result are always correct in 32 bit mode. */
1894 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
1895 (int) BFD_RELOC_LO16);
1896 return;
1897 }
1898 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
1899 {
1900 /* We can handle 16 bit unsigned values with an ori to
1901 $zero. */
1902 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
1903 (int) BFD_RELOC_LO16);
1904 return;
1905 }
98bfd087
ILT		 1906 else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
1907 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
1908 == ~ (offsetT) 0x7fffffff))
1909 && (! dbl
1910 || ! ep->X_unsigned
1911 || sizeof (ep->X_add_number) > 4
1912 || (ep->X_add_number & 0x80000000) == 0))
1913 || (mips_isa < 3
1914 && (ep->X_add_number &~ 0xffffffff) == 0))
847a01cd
ILT		 1915 {
1916 /* 32 bit values require an lui. */
1917 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
1918 (int) BFD_RELOC_HI16);
1919 if ((ep->X_add_number & 0xffff) != 0)
1920 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
1921 (int) BFD_RELOC_LO16);
1922 return;
1923 }
6e8dda9c 1924 }
847a01cd
ILT		 1925
1926 /* The value is larger than 32 bits. */
1927
1928 if (mips_isa < 3)
670a50eb 1929 {
6e8dda9c 1930 as_bad ("Number larger than 32 bits");
0dd2d296 1931 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
9226253a 1932 (int) BFD_RELOC_LO16);
847a01cd 1933 return;
6e8dda9c 1934 }
6e8dda9c 1935
847a01cd
ILT		 1936 if (ep->X_op != O_big)
1937 {
6e8dda9c
ILT		 1938 hi32 = *ep;
1939 shift = 32;
1940 hi32.X_add_number >>= shift;
1941 hi32.X_add_number &= 0xffffffff;
1942 if ((hi32.X_add_number & 0x80000000) != 0)
1943 hi32.X_add_number |= ~ (offsetT) 0xffffffff;
6e8dda9c
ILT		 1944 lo32 = *ep;
1945 lo32.X_add_number &= 0xffffffff;
670a50eb 1946 }
847a01cd
ILT		 1947 else
1948 {
1949 assert (ep->X_add_number > 2);
1950 if (ep->X_add_number == 3)
1951 generic_bignum[3] = 0;
1952 else if (ep->X_add_number > 4)
1953 as_bad ("Number larger than 64 bits");
1954 lo32.X_op = O_constant;
1955 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
1956 hi32.X_op = O_constant;
1957 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
1958 }
1959
d8a1c247
KR		 1960 if (hi32.X_add_number == 0)
1961 freg = 0;
1962 else
1963 {
fb251650
ILT		 1964 if (hi32.X_add_number == 0xffffffff)
1965 {
1966 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
1967 {
1968 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
1969 (int) BFD_RELOC_LO16);
1970 return;
1971 }
1972 if (lo32.X_add_number & 0x80000000)
1973 {
1974 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
1975 (int) BFD_RELOC_HI16);
1976 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
1977 (int) BFD_RELOC_LO16);
1978 return;
1979 }
1980 }
d8a1c247
KR		 1981 load_register (counter, reg, &hi32, 0);
1982 freg = reg;
1983 }
847a01cd 1984 if ((lo32.X_add_number & 0xffff0000) == 0)
d8a1c247
KR		 1985 {
1986 if (freg != 0)
1987 {
1988 macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg,
1989 freg, 0);
1990 freg = reg;
1991 }
1992 }
847a01cd
ILT		 1993 else
1994 {
1995 expressionS mid16;
1996
fb251650
ILT		 1997 if ((freg == 0) && (lo32.X_add_number == 0xffffffff))
1998 {
1999 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
2000 (int) BFD_RELOC_HI16);
2001 macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg,
2002 reg, 32);
2003 return;
2004 }
2005
d8a1c247
KR		 2006 if (freg != 0)
2007 {
2008 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
2009 freg, 16);
2010 freg = reg;
2011 }
847a01cd
ILT		 2012 mid16 = lo32;
2013 mid16.X_add_number >>= 16;
2014 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
d8a1c247 2015 freg, (int) BFD_RELOC_LO16);
847a01cd
ILT		 2016 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
2017 reg, 16);
d8a1c247 2018 freg = reg;
847a01cd
ILT		 2019 }
2020 if ((lo32.X_add_number & 0xffff) != 0)
d8a1c247 2021 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
847a01cd 2022 (int) BFD_RELOC_LO16);
3d3c5039
ILT		 2023}
2024
0dd2d296
ILT		 2025/* Load an address into a register. */
2026
2027static void
2028load_address (counter, reg, ep)
2029 int *counter;
2030 int reg;
2031 expressionS *ep;
2032{
2033 char *p;
2034
2035 if (ep->X_op != O_constant
2036 && ep->X_op != O_symbol)
2037 {
2038 as_bad ("expression too complex");
2039 ep->X_op = O_constant;
2040 }
2041
2042 if (ep->X_op == O_constant)
d9aba805 2043 {
d8a1c247 2044 load_register (counter, reg, ep, 0);
d9aba805
ILT		 2045 return;
2046 }
2047
2048 if (mips_pic == NO_PIC)
0dd2d296
ILT		 2049 {
2050 /* If this is a reference to a GP relative symbol, we want
2051 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2052 Otherwise we want
04cb3372 2053 lui $reg,<sym> (BFD_RELOC_HI16_S)
0dd2d296
ILT		 2054 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2055 If we have an addend, we always use the latter form. */
7a15a226
ILT		 2056 if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET
2057 || nopic_need_relax (ep->X_add_symbol))
0dd2d296
ILT		 2058 p = NULL;
2059 else
2060 {
8ea7f4e8 2061 frag_grow (20);
0dd2d296
ILT		 2062 macro_build ((char *) NULL, counter, ep,
2063 mips_isa < 3 ? "addiu" : "daddiu",
2064 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
2065 p = frag_var (rs_machine_dependent, 8, 0,
847a01cd 2066 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros),
0dd2d296
ILT		 2067 ep->X_add_symbol, (long) 0, (char *) NULL);
2068 }
2069 macro_build_lui (p, counter, ep, reg);
2070 if (p != NULL)
2071 p += 4;
2072 macro_build (p, counter, ep,
2073 mips_isa < 3 ? "addiu" : "daddiu",
2074 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
2075 }
fb251650 2076 else if (mips_pic == SVR4_PIC && ! mips_big_got)
0dd2d296
ILT		 2077 {
2078 expressionS ex;
2079
2080 /* If this is a reference to an external symbol, we want
2081 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2082 Otherwise we want
2083 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2084 nop
2085 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d9aba805 2086 If there is a constant, it must be added in after. */
0dd2d296
ILT		 2087 ex.X_add_number = ep->X_add_number;
2088 ep->X_add_number = 0;
8ea7f4e8 2089 frag_grow (20);
0dd2d296
ILT		 2090 macro_build ((char *) NULL, counter, ep,
2091 mips_isa < 3 ? "lw" : "ld",
2092 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
2093 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
2094 p = frag_var (rs_machine_dependent, 4, 0,
2095 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros),
2096 ep->X_add_symbol, (long) 0, (char *) NULL);
2097 macro_build (p, counter, ep,
2098 mips_isa < 3 ? "addiu" : "daddiu",
2099 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
2100 if (ex.X_add_number != 0)
2101 {
2102 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
2103 as_bad ("PIC code offset overflow (max 16 signed bits)");
2104 ex.X_op = O_constant;
fb251650
ILT		 2105 macro_build ((char *) NULL, counter, &ex,
2106 mips_isa < 3 ? "addiu" : "daddiu",
2107 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
2108 }
2109 }
2110 else if (mips_pic == SVR4_PIC)
2111 {
2112 expressionS ex;
2113 int off;
2114
2115 /* This is the large GOT case. If this is a reference to an
2116 external symbol, we want
2117 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2118 addu $reg,$reg,$gp
2119 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2120 Otherwise, for a reference to a local symbol, we want
2121 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2122 nop
2123 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2124 If there is a constant, it must be added in after. */
2125 ex.X_add_number = ep->X_add_number;
2126 ep->X_add_number = 0;
2127 if (reg_needs_delay (GP))
2128 off = 4;
2129 else
2130 off = 0;
2131 frag_grow (32);
2132 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
2133 (int) BFD_RELOC_MIPS_GOT_HI16);
2134 macro_build ((char *) NULL, counter, (expressionS *) NULL,
2135 mips_isa < 3 ? "addu" : "daddu",
2136 "d,v,t", reg, reg, GP);
2137 macro_build ((char *) NULL, counter, ep,
2138 mips_isa < 3 ? "lw" : "ld",
2139 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
2140 p = frag_var (rs_machine_dependent, 12 + off, 0,
2141 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
2142 mips_warn_about_macros),
2143 ep->X_add_symbol, (long) 0, (char *) NULL);
2144 if (off > 0)
2145 {
2146 /* We need a nop before loading from $gp. This special
2147 check is required because the lui which starts the main
2148 instruction stream does not refer to $gp, and so will not
2149 insert the nop which may be required. */
2150 macro_build (p, counter, (expressionS *) NULL, "nop", "");
2151 p += 4;
2152 }
2153 macro_build (p, counter, ep,
2154 mips_isa < 3 ? "lw" : "ld",
2155 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
2156 p += 4;
2157 macro_build (p, counter, (expressionS *) NULL, "nop", "");
2158 p += 4;
2159 macro_build (p, counter, ep,
2160 mips_isa < 3 ? "addiu" : "daddiu",
2161 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
2162 if (ex.X_add_number != 0)
2163 {
2164 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
2165 as_bad ("PIC code offset overflow (max 16 signed bits)");
2166 ex.X_op = O_constant;
2167 macro_build ((char *) NULL, counter, &ex,
0dd2d296
ILT		 2168 mips_isa < 3 ? "addiu" : "daddiu",
2169 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
2170 }
d9aba805
ILT		 2171 }
2172 else if (mips_pic == EMBEDDED_PIC)
2173 {
2174 /* We always do
2175 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2176 */
2177 macro_build ((char *) NULL, counter, ep,
2178 mips_isa < 3 ? "addiu" : "daddiu",
2179 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
2180 }
2181 else
2182 abort ();
0dd2d296
ILT		 2183}
2184
3d3c5039
ILT		 2185/*
2186 * Build macros
2187 * This routine implements the seemingly endless macro or synthesized
2188 * instructions and addressing modes in the mips assembly language. Many
2189 * of these macros are simple and are similar to each other. These could
2190 * probably be handled by some kind of table or grammer aproach instead of
2191 * this verbose method. Others are not simple macros but are more like
2192 * optimizing code generation.
2193 * One interesting optimization is when several store macros appear
2194 * consecutivly that would load AT with the upper half of the same address.
2195 * The ensuing load upper instructions are ommited. This implies some kind
2196 * of global optimization. We currently only optimize within a single macro.
2197 * For many of the load and store macros if the address is specified as a
2198 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2199 * first load register 'at' with zero and use it as the base register. The
2200 * mips assembler simply uses register $zero. Just one tiny optimization
2201 * we're missing.
2202 */
2203static void
2204macro (ip)
2205 struct mips_cl_insn *ip;
2206{
670a50eb
ILT		 2207 register int treg, sreg, dreg, breg;
2208 int tempreg;
2209 int mask;
2210 int icnt = 0;
2211 int used_at;
670a50eb
ILT		 2212 expressionS expr1;
2213 const char *s;
8358c818 2214 const char *s2;
670a50eb 2215 const char *fmt;
8358c818
ILT		 2216 int likely = 0;
2217 int dbl = 0;
2218 int coproc = 0;
b2b8c24e 2219 int lr = 0;
6e8dda9c 2220 offsetT maxnum;
adcf2b9d 2221 int off;
9226253a 2222 bfd_reloc_code_real_type r;
0dd2d296 2223 char *p;
55933a58 2224 int hold_mips_optimize;
670a50eb
ILT		 2225
2226 treg = (ip->insn_opcode >> 16) & 0x1f;
2227 dreg = (ip->insn_opcode >> 11) & 0x1f;
2228 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
2229 mask = ip->insn_mo->mask;
2230
5ac34ac3
ILT		 2231 expr1.X_op = O_constant;
2232 expr1.X_op_symbol = NULL;
670a50eb
ILT		 2233 expr1.X_add_symbol = NULL;
2234 expr1.X_add_number = 1;
2235
2236 switch (mask)
2237 {
6e8dda9c
ILT		 2238 case M_DABS:
2239 dbl = 1;
3d3c5039 2240 case M_ABS:
6e8dda9c
ILT		 2241 /* bgez $a0,.+12
2242 move v0,$a0
2243 sub v0,$zero,$a0
2244 */
3d3c5039 2245
becfe05e
ILT		 2246 mips_emit_delays ();
2247 ++mips_noreorder;
0dd2d296 2248 mips_any_noreorder = 1;
3d3c5039 2249
670a50eb 2250 expr1.X_add_number = 8;
0dd2d296 2251 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
6e8dda9c 2252 if (dreg == sreg)
0dd2d296 2253 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
6e8dda9c 2254 else
0dd2d296
ILT		 2255 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0);
2256 macro_build ((char *) NULL, &icnt, NULL,
6e8dda9c
ILT		 2257 dbl ? "dsub" : "sub",
2258 "d,v,t", dreg, 0, sreg);
3d3c5039 2259
becfe05e 2260 --mips_noreorder;
670a50eb 2261 return;
3d3c5039
ILT		 2262
2263 case M_ADD_I:
8358c818
ILT		 2264 s = "addi";
2265 s2 = "add";
2266 goto do_addi;
3d3c5039 2267 case M_ADDU_I:
8358c818
ILT		 2268 s = "addiu";
2269 s2 = "addu";
2270 goto do_addi;
2271 case M_DADD_I:
6e8dda9c 2272 dbl = 1;
8358c818
ILT		 2273 s = "daddi";
2274 s2 = "dadd";
2275 goto do_addi;
2276 case M_DADDU_I:
6e8dda9c 2277 dbl = 1;
8358c818
ILT		 2278 s = "daddiu";
2279 s2 = "daddu";
2280 do_addi:
6e8dda9c 2281 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 2282 {
0dd2d296 2283 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
9226253a 2284 (int) BFD_RELOC_LO16);
670a50eb 2285 return;
3d3c5039 2286 }
d8a1c247 2287 load_register (&icnt, AT, &imm_expr, dbl);
0dd2d296 2288 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 2289 break;
3d3c5039
ILT		 2290
2291 case M_AND_I:
6e8dda9c
ILT		 2292 s = "andi";
2293 s2 = "and";
2294 goto do_bit;
3d3c5039 2295 case M_OR_I:
6e8dda9c
ILT		 2296 s = "ori";
2297 s2 = "or";
2298 goto do_bit;
3d3c5039 2299 case M_NOR_I:
6e8dda9c
ILT		 2300 s = "";
2301 s2 = "nor";
2302 goto do_bit;
3d3c5039 2303 case M_XOR_I:
6e8dda9c
ILT		 2304 s = "xori";
2305 s2 = "xor";
2306 do_bit:
2307 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 2308 {
6e8dda9c 2309 if (mask != M_NOR_I)
0dd2d296
ILT		 2310 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
2311 sreg, (int) BFD_RELOC_LO16);
6e8dda9c 2312 else
670a50eb 2313 {
0dd2d296
ILT		 2314 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
2315 treg, sreg, (int) BFD_RELOC_LO16);
1c803e52 2316 macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t",
0dd2d296 2317 treg, treg, 0);
3d3c5039 2318 }
6e8dda9c 2319 return;
3d3c5039 2320 }
6e8dda9c 2321
d8a1c247 2322 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 2323 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 2324 break;
3d3c5039
ILT		 2325
2326 case M_BEQ_I:
8358c818
ILT		 2327 s = "beq";
2328 goto beq_i;
2329 case M_BEQL_I:
2330 s = "beql";
2331 likely = 1;
2332 goto beq_i;
3d3c5039 2333 case M_BNE_I:
8358c818
ILT		 2334 s = "bne";
2335 goto beq_i;
2336 case M_BNEL_I:
2337 s = "bnel";
2338 likely = 1;
2339 beq_i:
670a50eb
ILT		 2340 if (imm_expr.X_add_number == 0)
2341 {
0dd2d296
ILT		 2342 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
2343 0);
670a50eb
ILT		 2344 return;
2345 }
d8a1c247 2346 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 2347 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
670a50eb 2348 break;
3d3c5039 2349
8358c818
ILT		 2350 case M_BGEL:
2351 likely = 1;
3d3c5039 2352 case M_BGE:
670a50eb
ILT		 2353 if (treg == 0)
2354 {
0dd2d296 2355 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2356 likely ? "bgezl" : "bgez",
2357 "s,p", sreg);
670a50eb 2358 return;
3d3c5039 2359 }
9a7d824a
ILT		 2360 if (sreg == 0)
2361 {
0dd2d296 2362 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2363 likely ? "blezl" : "blez",
2364 "s,p", treg);
9a7d824a
ILT		 2365 return;
2366 }
0dd2d296
ILT		 2367 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
2368 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2369 likely ? "beql" : "beq",
2370 "s,t,p", AT, 0);
670a50eb 2371 break;
3d3c5039 2372
8358c818
ILT		 2373 case M_BGTL_I:
2374 likely = 1;
3d3c5039 2375 case M_BGT_I:
9a7d824a 2376 /* check for > max integer */
6e8dda9c
ILT		 2377 maxnum = 0x7fffffff;
2378 if (mips_isa >= 3)
2379 {
2380 maxnum <<= 16;
2381 maxnum |= 0xffff;
2382 maxnum <<= 16;
2383 maxnum |= 0xffff;
2384 }
7b777690
ILT		 2385 if (imm_expr.X_add_number >= maxnum
2386 && (mips_isa < 3 || sizeof (maxnum) > 4))
9a7d824a
ILT		 2387 {
2388 do_false:
2389 /* result is always false */
8358c818
ILT		 2390 if (! likely)
2391 {
2392 as_warn ("Branch %s is always false (nop)", ip->insn_mo->name);
0dd2d296 2393 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
8358c818
ILT		 2394 }
2395 else
2396 {
2397 as_warn ("Branch likely %s is always false", ip->insn_mo->name);
0dd2d296
ILT		 2398 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
2399 "s,t,p", 0, 0);
8358c818 2400 }
9a7d824a
ILT		 2401 return;
2402 }
670a50eb
ILT		 2403 imm_expr.X_add_number++;
2404 /* FALLTHROUGH */
3d3c5039 2405 case M_BGE_I:
8358c818
ILT		 2406 case M_BGEL_I:
2407 if (mask == M_BGEL_I)
2408 likely = 1;
670a50eb
ILT		 2409 if (imm_expr.X_add_number == 0)
2410 {
0dd2d296 2411 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2412 likely ? "bgezl" : "bgez",
2413 "s,p", sreg);
670a50eb 2414 return;
3d3c5039 2415 }
670a50eb
ILT		 2416 if (imm_expr.X_add_number == 1)
2417 {
0dd2d296 2418 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2419 likely ? "bgtzl" : "bgtz",
2420 "s,p", sreg);
670a50eb 2421 return;
3d3c5039 2422 }
6e8dda9c
ILT		 2423 maxnum = 0x7fffffff;
2424 if (mips_isa >= 3)
2425 {
2426 maxnum <<= 16;
2427 maxnum |= 0xffff;
2428 maxnum <<= 16;
2429 maxnum |= 0xffff;
2430 }
2431 maxnum = - maxnum - 1;
7b777690
ILT		 2432 if (imm_expr.X_add_number <= maxnum
2433 && (mips_isa < 3 || sizeof (maxnum) > 4))
9a7d824a
ILT		 2434 {
2435 do_true:
2436 /* result is always true */
2437 as_warn ("Branch %s is always true", ip->insn_mo->name);
0dd2d296 2438 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
9a7d824a
ILT		 2439 return;
2440 }
6e8dda9c 2441 set_at (&icnt, sreg, 0);
0dd2d296 2442 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2443 likely ? "beql" : "beq",
2444 "s,t,p", AT, 0);
670a50eb 2445 break;
3d3c5039 2446
8358c818
ILT		 2447 case M_BGEUL:
2448 likely = 1;
3d3c5039 2449 case M_BGEU:
670a50eb 2450 if (treg == 0)
9a7d824a
ILT		 2451 goto do_true;
2452 if (sreg == 0)
670a50eb 2453 {
0dd2d296 2454 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2455 likely ? "beql" : "beq",
2456 "s,t,p", 0, treg);
670a50eb 2457 return;
3d3c5039 2458 }
0dd2d296
ILT		 2459 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
2460 treg);
2461 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2462 likely ? "beql" : "beq",
2463 "s,t,p", AT, 0);
670a50eb 2464 break;
3d3c5039 2465
8358c818
ILT		 2466 case M_BGTUL_I:
2467 likely = 1;
9a7d824a 2468 case M_BGTU_I:
6e8dda9c 2469 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 2470 goto do_false;
2471 imm_expr.X_add_number++;
2472 /* FALLTHROUGH */
3d3c5039 2473 case M_BGEU_I:
8358c818
ILT		 2474 case M_BGEUL_I:
2475 if (mask == M_BGEUL_I)
2476 likely = 1;
670a50eb 2477 if (imm_expr.X_add_number == 0)
9a7d824a 2478 goto do_true;
670a50eb
ILT		 2479 if (imm_expr.X_add_number == 1)
2480 {
0dd2d296 2481 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2482 likely ? "bnel" : "bne",
2483 "s,t,p", sreg, 0);
670a50eb 2484 return;
3d3c5039 2485 }
6e8dda9c 2486 set_at (&icnt, sreg, 1);
0dd2d296 2487 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2488 likely ? "beql" : "beq",
2489 "s,t,p", AT, 0);
670a50eb 2490 break;
3d3c5039 2491
8358c818
ILT		 2492 case M_BGTL:
2493 likely = 1;
3d3c5039 2494 case M_BGT:
670a50eb
ILT		 2495 if (treg == 0)
2496 {
0dd2d296 2497 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2498 likely ? "bgtzl" : "bgtz",
2499 "s,p", sreg);
670a50eb 2500 return;
3d3c5039 2501 }
9a7d824a
ILT		 2502 if (sreg == 0)
2503 {
0dd2d296 2504 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2505 likely ? "bltzl" : "bltz",
2506 "s,p", treg);
9a7d824a
ILT		 2507 return;
2508 }
0dd2d296
ILT		 2509 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
2510 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2511 likely ? "bnel" : "bne",
2512 "s,t,p", AT, 0);
670a50eb 2513 break;
3d3c5039 2514
8358c818
ILT		 2515 case M_BGTUL:
2516 likely = 1;
3d3c5039 2517 case M_BGTU:
670a50eb
ILT		 2518 if (treg == 0)
2519 {
0dd2d296 2520 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2521 likely ? "bnel" : "bne",
2522 "s,t,p", sreg, 0);
670a50eb 2523 return;
3d3c5039 2524 }
9a7d824a
ILT		 2525 if (sreg == 0)
2526 goto do_false;
0dd2d296
ILT		 2527 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
2528 sreg);
2529 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2530 likely ? "bnel" : "bne",
2531 "s,t,p", AT, 0);
670a50eb 2532 break;
3d3c5039 2533
8358c818
ILT		 2534 case M_BLEL:
2535 likely = 1;
3d3c5039 2536 case M_BLE:
670a50eb
ILT		 2537 if (treg == 0)
2538 {
0dd2d296 2539 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2540 likely ? "blezl" : "blez",
2541 "s,p", sreg);
670a50eb
ILT		 2542 return;
2543 }
9a7d824a
ILT		 2544 if (sreg == 0)
2545 {
0dd2d296 2546 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2547 likely ? "bgezl" : "bgez",
2548 "s,p", treg);
9a7d824a
ILT		 2549 return;
2550 }
0dd2d296
ILT		 2551 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
2552 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2553 likely ? "beql" : "beq",
2554 "s,t,p", AT, 0);
670a50eb 2555 break;
3d3c5039 2556
8358c818
ILT		 2557 case M_BLEL_I:
2558 likely = 1;
3d3c5039 2559 case M_BLE_I:
6e8dda9c
ILT		 2560 maxnum = 0x7fffffff;
2561 if (mips_isa >= 3)
2562 {
2563 maxnum <<= 16;
2564 maxnum |= 0xffff;
2565 maxnum <<= 16;
2566 maxnum |= 0xffff;
2567 }
7b777690
ILT		 2568 if (imm_expr.X_add_number >= maxnum
2569 && (mips_isa < 3 || sizeof (maxnum) > 4))
9a7d824a
ILT		 2570 goto do_true;
2571 imm_expr.X_add_number++;
2572 /* FALLTHROUGH */
9a7d824a 2573 case M_BLT_I:
8358c818
ILT		 2574 case M_BLTL_I:
2575 if (mask == M_BLTL_I)
2576 likely = 1;
670a50eb
ILT		 2577 if (imm_expr.X_add_number == 0)
2578 {
0dd2d296 2579 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2580 likely ? "bltzl" : "bltz",
2581 "s,p", sreg);
670a50eb
ILT		 2582 return;
2583 }
9a7d824a 2584 if (imm_expr.X_add_number == 1)
670a50eb 2585 {
0dd2d296 2586 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2587 likely ? "blezl" : "blez",
2588 "s,p", sreg);
670a50eb
ILT		 2589 return;
2590 }
6e8dda9c 2591 set_at (&icnt, sreg, 0);
0dd2d296 2592 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2593 likely ? "bnel" : "bne",
2594 "s,t,p", AT, 0);
670a50eb 2595 break;
3d3c5039 2596
8358c818
ILT		 2597 case M_BLEUL:
2598 likely = 1;
3d3c5039 2599 case M_BLEU:
670a50eb
ILT		 2600 if (treg == 0)
2601 {
0dd2d296 2602 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2603 likely ? "beql" : "beq",
2604 "s,t,p", sreg, 0);
670a50eb 2605 return;
3d3c5039 2606 }
9a7d824a
ILT		 2607 if (sreg == 0)
2608 goto do_true;
0dd2d296
ILT		 2609 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
2610 sreg);
2611 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2612 likely ? "beql" : "beq",
2613 "s,t,p", AT, 0);
670a50eb 2614 break;
3d3c5039 2615
8358c818
ILT		 2616 case M_BLEUL_I:
2617 likely = 1;
3d3c5039 2618 case M_BLEU_I:
6e8dda9c 2619 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 2620 goto do_true;
2621 imm_expr.X_add_number++;
2622 /* FALLTHROUGH */
9a7d824a 2623 case M_BLTU_I:
8358c818
ILT		 2624 case M_BLTUL_I:
2625 if (mask == M_BLTUL_I)
2626 likely = 1;
670a50eb 2627 if (imm_expr.X_add_number == 0)
9a7d824a
ILT		 2628 goto do_false;
2629 if (imm_expr.X_add_number == 1)
670a50eb 2630 {
0dd2d296 2631 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2632 likely ? "beql" : "beq",
2633 "s,t,p", sreg, 0);
670a50eb 2634 return;
3d3c5039 2635 }
6e8dda9c 2636 set_at (&icnt, sreg, 1);
0dd2d296 2637 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2638 likely ? "bnel" : "bne",
2639 "s,t,p", AT, 0);
670a50eb 2640 break;
3d3c5039 2641
8358c818
ILT		 2642 case M_BLTL:
2643 likely = 1;
3d3c5039 2644 case M_BLT:
670a50eb
ILT		 2645 if (treg == 0)
2646 {
0dd2d296 2647 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2648 likely ? "bltzl" : "bltz",
2649 "s,p", sreg);
670a50eb 2650 return;
3d3c5039 2651 }
9a7d824a 2652 if (sreg == 0)
670a50eb 2653 {
0dd2d296 2654 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2655 likely ? "bgtzl" : "bgtz",
2656 "s,p", treg);
670a50eb 2657 return;
3d3c5039 2658 }
0dd2d296
ILT		 2659 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
2660 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2661 likely ? "bnel" : "bne",
2662 "s,t,p", AT, 0);
670a50eb 2663 break;
3d3c5039 2664
8358c818
ILT		 2665 case M_BLTUL:
2666 likely = 1;
3d3c5039 2667 case M_BLTU:
670a50eb 2668 if (treg == 0)
9a7d824a
ILT		 2669 goto do_false;
2670 if (sreg == 0)
670a50eb 2671 {
0dd2d296 2672 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2673 likely ? "bnel" : "bne",
2674 "s,t,p", 0, treg);
670a50eb
ILT		 2675 return;
2676 }
0dd2d296
ILT		 2677 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
2678 treg);
2679 macro_build ((char *) NULL, &icnt, &offset_expr,
8358c818
ILT		 2680 likely ? "bnel" : "bne",
2681 "s,t,p", AT, 0);
670a50eb 2682 break;
3d3c5039 2683
8358c818
ILT		 2684 case M_DDIV_3:
2685 dbl = 1;
3d3c5039 2686 case M_DIV_3:
8358c818
ILT		 2687 s = "mflo";
2688 goto do_div3;
2689 case M_DREM_3:
2690 dbl = 1;
3d3c5039 2691 case M_REM_3:
8358c818
ILT		 2692 s = "mfhi";
2693 do_div3:
670a50eb
ILT		 2694 if (treg == 0)
2695 {
2696 as_warn ("Divide by zero.");
8ea7f4e8
ILT		 2697 if (mips_trap)
2698 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
2699 else
2700 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
670a50eb
ILT		 2701 return;
2702 }
2703
becfe05e
ILT		 2704 mips_emit_delays ();
2705 ++mips_noreorder;
0dd2d296
ILT		 2706 mips_any_noreorder = 1;
2707 macro_build ((char *) NULL, &icnt, NULL,
8358c818 2708 dbl ? "ddiv" : "div",
ff3a5c18 2709 "z,s,t", sreg, treg);
8ea7f4e8
ILT		 2710 if (mips_trap)
2711 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
2712 else
2713 {
2714 expr1.X_add_number = 8;
2715 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
2716 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2717 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2718 }
670a50eb 2719 expr1.X_add_number = -1;
0dd2d296 2720 macro_build ((char *) NULL, &icnt, &expr1,
8358c818 2721 dbl ? "daddiu" : "addiu",
9226253a 2722 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
8ea7f4e8 2723 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
0dd2d296 2724 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
8358c818
ILT		 2725 if (dbl)
2726 {
2727 expr1.X_add_number = 1;
0dd2d296 2728 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
9226253a 2729 (int) BFD_RELOC_LO16);
0dd2d296
ILT		 2730 macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT,
2731 31);
8358c818
ILT		 2732 }
2733 else
2734 {
2735 expr1.X_add_number = 0x80000000;
ecd4ca1c
ILT		 2736 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
2737 (int) BFD_RELOC_HI16);
8358c818 2738 }
8ea7f4e8
ILT		 2739 if (mips_trap)
2740 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT);
2741 else
2742 {
2743 expr1.X_add_number = 8;
2744 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
2745 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2746 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
2747 }
becfe05e 2748 --mips_noreorder;
0dd2d296 2749 macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg);
670a50eb 2750 break;
3d3c5039
ILT		 2751
2752 case M_DIV_3I:
8358c818
ILT		 2753 s = "div";
2754 s2 = "mflo";
2755 goto do_divi;
3d3c5039 2756 case M_DIVU_3I:
8358c818
ILT		 2757 s = "divu";
2758 s2 = "mflo";
2759 goto do_divi;
3d3c5039 2760 case M_REM_3I:
8358c818
ILT		 2761 s = "div";
2762 s2 = "mfhi";
2763 goto do_divi;
3d3c5039 2764 case M_REMU_3I:
8358c818
ILT		 2765 s = "divu";
2766 s2 = "mfhi";
2767 goto do_divi;
2768 case M_DDIV_3I:
2769 dbl = 1;
2770 s = "ddiv";
2771 s2 = "mflo";
2772 goto do_divi;
2773 case M_DDIVU_3I:
2774 dbl = 1;
2775 s = "ddivu";
2776 s2 = "mflo";
2777 goto do_divi;
2778 case M_DREM_3I:
2779 dbl = 1;
2780 s = "ddiv";
2781 s2 = "mfhi";
2782 goto do_divi;
2783 case M_DREMU_3I:
2784 dbl = 1;
2785 s = "ddivu";
2786 s2 = "mfhi";
2787 do_divi:
670a50eb
ILT		 2788 if (imm_expr.X_add_number == 0)
2789 {
2790 as_warn ("Divide by zero.");
8ea7f4e8
ILT		 2791 if (mips_trap)
2792 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
2793 else
2794 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
670a50eb
ILT		 2795 return;
2796 }
2797 if (imm_expr.X_add_number == 1)
2798 {
8358c818 2799 if (strcmp (s2, "mflo") == 0)
0dd2d296
ILT		 2800 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg,
2801 sreg);
3d3c5039 2802 else
0dd2d296 2803 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
3d3c5039
ILT		 2804 return;
2805 }
8358c818
ILT		 2806 if (imm_expr.X_add_number == -1
2807 && s[strlen (s) - 1] != 'u')
2808 {
2809 if (strcmp (s2, "mflo") == 0)
2810 {
2811 if (dbl)
0dd2d296
ILT		 2812 macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg,
2813 sreg);
8358c818 2814 else
0dd2d296
ILT		 2815 macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg,
2816 sreg);
8358c818
ILT		 2817 }
2818 else
0dd2d296 2819 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
8358c818
ILT		 2820 return;
2821 }
3d3c5039 2822
d8a1c247 2823 load_register (&icnt, AT, &imm_expr, dbl);
0dd2d296
ILT		 2824 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
2825 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
670a50eb
ILT		 2826 break;
2827
2828 case M_DIVU_3:
8358c818
ILT		 2829 s = "divu";
2830 s2 = "mflo";
2831 goto do_divu3;
670a50eb 2832 case M_REMU_3:
8358c818
ILT		 2833 s = "divu";
2834 s2 = "mfhi";
2835 goto do_divu3;
2836 case M_DDIVU_3:
2837 s = "ddivu";
2838 s2 = "mflo";
2839 goto do_divu3;
2840 case M_DREMU_3:
2841 s = "ddivu";
2842 s2 = "mfhi";
2843 do_divu3:
becfe05e
ILT		 2844 mips_emit_delays ();
2845 ++mips_noreorder;
0dd2d296
ILT		 2846 mips_any_noreorder = 1;
2847 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
8ea7f4e8
ILT		 2848 if (mips_trap)
2849 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
2850 else
2851 {
2852 expr1.X_add_number = 8;
2853 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
2854 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2855 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2856 }
becfe05e 2857 --mips_noreorder;
0dd2d296 2858 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
670a50eb 2859 return;
3d3c5039 2860
d8a1c247
KR		 2861 case M_DLA_AB:
2862 dbl = 1;
0dd2d296 2863 case M_LA_AB:
d9aba805
ILT		 2864 /* Load the address of a symbol into a register. If breg is not
2865 zero, we then add a base register to it. */
ecd4ca1c
ILT		 2866
2867 /* When generating embedded PIC code, we permit expressions of
2868 the form
2869 la $4,foo-bar
2870 where bar is an address in the .text section. These are used
2871 when getting the addresses of functions. We don't permit
2872 X_add_number to be non-zero, because if the symbol is
2873 external the relaxing code needs to know that any addend is
2874 purely the offset to X_op_symbol. */
2875 if (mips_pic == EMBEDDED_PIC
2876 && offset_expr.X_op == O_subtract
2877 && now_seg == text_section
847a01cd
ILT		 2878 && (offset_expr.X_op_symbol->sy_value.X_op == O_constant
2879 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section
2880 : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol
2881 && (S_GET_SEGMENT (offset_expr.X_op_symbol
2882 ->sy_value.X_add_symbol)
2883 == text_section)))
ecd4ca1c
ILT		 2884 && breg == 0
2885 && offset_expr.X_add_number == 0)
2886 {
2887 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
2888 treg, (int) BFD_RELOC_PCREL_HI16_S);
2889 macro_build ((char *) NULL, &icnt, &offset_expr,
2890 mips_isa < 3 ? "addiu" : "daddiu",
2891 "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
2892 return;
2893 }
2894
0dd2d296
ILT		 2895 if (offset_expr.X_op != O_symbol
2896 && offset_expr.X_op != O_constant)
670a50eb 2897 {
0dd2d296
ILT		 2898 as_bad ("expression too complex");
2899 offset_expr.X_op = O_constant;
2900 }
2901
2902 if (treg == breg)
2903 {
2904 tempreg = AT;
2905 used_at = 1;
3d3c5039 2906 }
670a50eb
ILT		 2907 else
2908 {
0dd2d296
ILT		 2909 tempreg = treg;
2910 used_at = 0;
670a50eb 2911 }
3d3c5039 2912
5ac34ac3 2913 if (offset_expr.X_op == O_constant)
d8a1c247 2914 load_register (&icnt, tempreg, &offset_expr, dbl);
d9aba805 2915 else if (mips_pic == NO_PIC)
670a50eb 2916 {
0dd2d296
ILT		 2917 /* If this is a reference to an GP relative symbol, we want
2918 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2919 Otherwise we want
2920 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2921 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2922 If we have a constant, we need two instructions anyhow,
2923 so we may as well always use the latter form. */
7a15a226 2924 if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET
d8a1c247 2925 || nopic_need_relax (offset_expr.X_add_symbol))
0dd2d296
ILT		 2926 p = NULL;
2927 else
2928 {
8ea7f4e8 2929 frag_grow (20);
0dd2d296
ILT		 2930 macro_build ((char *) NULL, &icnt, &offset_expr,
2931 mips_isa < 3 ? "addiu" : "daddiu",
2932 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
2933 p = frag_var (rs_machine_dependent, 8, 0,
2934 RELAX_ENCODE (4, 8, 0, 4, 0,
2935 mips_warn_about_macros),
2936 offset_expr.X_add_symbol, (long) 0,
2937 (char *) NULL);
2938 }
2939 macro_build_lui (p, &icnt, &offset_expr, tempreg);
2940 if (p != NULL)
2941 p += 4;
2942 macro_build (p, &icnt, &offset_expr,
6e8dda9c 2943 mips_isa < 3 ? "addiu" : "daddiu",
0dd2d296
ILT		 2944 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
2945 }
fb251650 2946 else if (mips_pic == SVR4_PIC && ! mips_big_got)
0dd2d296
ILT		 2947 {
2948 /* If this is a reference to an external symbol, and there
2949 is no constant, we want
2950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2951 For a local symbol, we want
2952 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2953 nop
2954 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2955
2956 If we have a small constant, and this is a reference to
2957 an external symbol, we want
2958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2959 nop
2960 addiu $tempreg,$tempreg,<constant>
2961 For a local symbol, we want the same instruction
2962 sequence, but we output a BFD_RELOC_LO16 reloc on the
2963 addiu instruction.
2964
2965 If we have a large constant, and this is a reference to
2966 an external symbol, we want
2967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2968 lui $at,<hiconstant>
2969 addiu $at,$at,<loconstant>
2970 addu $tempreg,$tempreg,$at
2971 For a local symbol, we want the same instruction
2972 sequence, but we output a BFD_RELOC_LO16 reloc on the
2973 addiu instruction. */
2974 expr1.X_add_number = offset_expr.X_add_number;
2975 offset_expr.X_add_number = 0;
8ea7f4e8 2976 frag_grow (32);
0dd2d296 2977 macro_build ((char *) NULL, &icnt, &offset_expr,
d8a1c247 2978 dbl ? "ld" : "lw",
0dd2d296
ILT		 2979 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
2980 if (expr1.X_add_number == 0)
2981 {
2982 int off;
2983
2984 if (breg == 0)
2985 off = 0;
2986 else
2987 {
2988 /* We're going to put in an addu instruction using
2989 tempreg, so we may as well insert the nop right
2990 now. */
2991 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2992 "nop", "");
2993 off = 4;
2994 }
2995 p = frag_var (rs_machine_dependent, 8 - off, 0,
2996 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
2997 (breg == 0
2998 ? mips_warn_about_macros
2999 : 0)),
3000 offset_expr.X_add_symbol, (long) 0,
3001 (char *) NULL);
3002 if (breg == 0)
3003 {
3004 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3005 p += 4;
3006 }
3007 macro_build (p, &icnt, &expr1,
3008 mips_isa < 3 ? "addiu" : "daddiu",
3009 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3010 /* FIXME: If breg == 0, and the next instruction uses
3011 $tempreg, then if this variant case is used an extra
3012 nop will be generated. */
3013 }
3014 else if (expr1.X_add_number >= -0x8000
3015 && expr1.X_add_number < 0x8000)
3016 {
3017 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3018 "nop", "");
3019 macro_build ((char *) NULL, &icnt, &expr1,
3020 mips_isa < 3 ? "addiu" : "daddiu",
3021 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3022 (void) frag_var (rs_machine_dependent, 0, 0,
3023 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3024 offset_expr.X_add_symbol, (long) 0,
3025 (char *) NULL);
3026 }
3027 else
3028 {
3029 int off1;
3030
3031 /* If we are going to add in a base register, and the
3032 target register and the base register are the same,
3033 then we are using AT as a temporary register. Since
3034 we want to load the constant into AT, we add our
3035 current AT (from the global offset table) and the
3036 register into the register now, and pretend we were
3037 not using a base register. */
3038 if (breg != treg)
3039 off1 = 0;
3040 else
3041 {
3042 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3043 "nop", "");
3044 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3045 mips_isa < 3 ? "addu" : "daddu",
3046 "d,v,t", treg, AT, breg);
3047 breg = 0;
3048 tempreg = treg;
3049 off1 = -8;
3050 }
3051
55933a58
ILT		 3052 /* Set mips_optimize around the lui instruction to avoid
3053 inserting an unnecessary nop after the lw. */
3054 hold_mips_optimize = mips_optimize;
3055 mips_optimize = 2;
0dd2d296 3056 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
55933a58
ILT		 3057 mips_optimize = hold_mips_optimize;
3058
0dd2d296
ILT		 3059 macro_build ((char *) NULL, &icnt, &expr1,
3060 mips_isa < 3 ? "addiu" : "daddiu",
3061 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
3062 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3063 mips_isa < 3 ? "addu" : "daddu",
3064 "d,v,t", tempreg, tempreg, AT);
3065 (void) frag_var (rs_machine_dependent, 0, 0,
3066 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
3067 offset_expr.X_add_symbol, (long) 0,
3068 (char *) NULL);
3069 used_at = 1;
3070 }
670a50eb 3071 }
fb251650
ILT		 3072 else if (mips_pic == SVR4_PIC)
3073 {
3074 int gpdel;
3075
3076 /* This is the large GOT case. If this is a reference to an
3077 external symbol, and there is no constant, we want
3078 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3079 addu $tempreg,$tempreg,$gp
3080 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3081 For a local symbol, we want
3082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3083 nop
3084 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3085
3086 If we have a small constant, and this is a reference to
3087 an external symbol, we want
3088 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3089 addu $tempreg,$tempreg,$gp
3090 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3091 nop
3092 addiu $tempreg,$tempreg,<constant>
3093 For a local symbol, we want
3094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3095 nop
3096 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3097
3098 If we have a large constant, and this is a reference to
3099 an external symbol, we want
3100 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3101 addu $tempreg,$tempreg,$gp
3102 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3103 lui $at,<hiconstant>
3104 addiu $at,$at,<loconstant>
3105 addu $tempreg,$tempreg,$at
3106 For a local symbol, we want
3107 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3108 lui $at,<hiconstant>
3109 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3110 addu $tempreg,$tempreg,$at
3111 */
3112 expr1.X_add_number = offset_expr.X_add_number;
3113 offset_expr.X_add_number = 0;
3114 frag_grow (52);
3115 if (reg_needs_delay (GP))
3116 gpdel = 4;
3117 else
3118 gpdel = 0;
3119 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
3120 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
3121 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3122 mips_isa < 3 ? "addu" : "daddu",
3123 "d,v,t", tempreg, tempreg, GP);
3124 macro_build ((char *) NULL, &icnt, &offset_expr,
3125 dbl ? "ld" : "lw",
3126 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
3127 tempreg);
3128 if (expr1.X_add_number == 0)
3129 {
3130 int off;
3131
3132 if (breg == 0)
3133 off = 0;
3134 else
3135 {
3136 /* We're going to put in an addu instruction using
3137 tempreg, so we may as well insert the nop right
3138 now. */
3139 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3140 "nop", "");
3141 off = 4;
3142 }
3143
3144 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
3145 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
3146 8 + gpdel, 0,
3147 (breg == 0
3148 ? mips_warn_about_macros
3149 : 0)),
3150 offset_expr.X_add_symbol, (long) 0,
3151 (char *) NULL);
3152 }
3153 else if (expr1.X_add_number >= -0x8000
3154 && expr1.X_add_number < 0x8000)
3155 {
3156 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3157 "nop", "");
3158 macro_build ((char *) NULL, &icnt, &expr1,
3159 mips_isa < 3 ? "addiu" : "daddiu",
3160 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3161
3162 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
3163 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
3164 (breg == 0
3165 ? mips_warn_about_macros
3166 : 0)),
3167 offset_expr.X_add_symbol, (long) 0,
3168 (char *) NULL);
3169 }
3170 else
3171 {
3172 int adj, dreg;
3173
3174 /* If we are going to add in a base register, and the
3175 target register and the base register are the same,
3176 then we are using AT as a temporary register. Since
3177 we want to load the constant into AT, we add our
3178 current AT (from the global offset table) and the
3179 register into the register now, and pretend we were
3180 not using a base register. */
3181 if (breg != treg)
3182 {
3183 adj = 0;
3184 dreg = tempreg;
3185 }
3186 else
3187 {
3188 assert (tempreg == AT);
3189 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3190 "nop", "");
3191 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3192 mips_isa < 3 ? "addu" : "daddu",
3193 "d,v,t", treg, AT, breg);
3194 dreg = treg;
3195 adj = 8;
3196 }
3197
3198 /* Set mips_optimize around the lui instruction to avoid
3199 inserting an unnecessary nop after the lw. */
3200 hold_mips_optimize = mips_optimize;
3201 mips_optimize = 2;
3202 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
3203 mips_optimize = hold_mips_optimize;
3204
3205 macro_build ((char *) NULL, &icnt, &expr1,
3206 mips_isa < 3 ? "addiu" : "daddiu",
3207 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
3208 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3209 mips_isa < 3 ? "addu" : "daddu",
3210 "d,v,t", dreg, dreg, AT);
3211
3212 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
3213 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
3214 8 + gpdel, 0,
3215 (breg == 0
3216 ? mips_warn_about_macros
3217 : 0)),
3218 offset_expr.X_add_symbol, (long) 0,
3219 (char *) NULL);
3220
3221 used_at = 1;
3222 }
3223
3224 if (gpdel > 0)
3225 {
3226 /* This is needed because this instruction uses $gp, but
3227 the first instruction on the main stream does not. */
3228 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3229 p += 4;
3230 }
3231 macro_build (p, &icnt, &offset_expr,
3232 dbl ? "ld" : "lw",
3233 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
3234 p += 4;
3235 if (expr1.X_add_number >= -0x8000
3236 && expr1.X_add_number < 0x8000)
3237 {
3238 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3239 p += 4;
3240 macro_build (p, &icnt, &expr1,
3241 mips_isa < 3 ? "addiu" : "daddiu",
3242 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3243 /* FIXME: If add_number is 0, and there was no base
3244 register, the external symbol case ended with a load,
3245 so if the symbol turns out to not be external, and
3246 the next instruction uses tempreg, an unnecessary nop
3247 will be inserted. */
3248 }
3249 else
3250 {
3251 if (breg == treg)
3252 {
3253 /* We must add in the base register now, as in the
3254 external symbol case. */
3255 assert (tempreg == AT);
3256 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3257 p += 4;
3258 macro_build (p, &icnt, (expressionS *) NULL,
3259 mips_isa < 3 ? "addu" : "daddu",
3260 "d,v,t", treg, AT, breg);
3261 p += 4;
3262 tempreg = treg;
3263 /* We set breg to 0 because we have arranged to add
3264 it in in both cases. */
3265 breg = 0;
3266 }
3267
3268 macro_build_lui (p, &icnt, &expr1, AT);
3269 p += 4;
3270 macro_build (p, &icnt, &expr1,
3271 mips_isa < 3 ? "addiu" : "daddiu",
3272 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
3273 p += 4;
3274 macro_build (p, &icnt, (expressionS *) NULL,
3275 mips_isa < 3 ? "addu" : "daddu",
3276 "d,v,t", tempreg, tempreg, AT);
3277 p += 4;
3278 }
3279 }
d9aba805
ILT		 3280 else if (mips_pic == EMBEDDED_PIC)
3281 {
3282 /* We use
3283 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3284 */
3285 macro_build ((char *) NULL, &icnt, &offset_expr,
3286 mips_isa < 3 ? "addiu" : "daddiu",
3287 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
3288 }
3289 else
3290 abort ();
0dd2d296 3291
670a50eb 3292 if (breg != 0)
0dd2d296
ILT		 3293 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3294 mips_isa < 3 ? "addu" : "daddu",
3295 "d,v,t", treg, tempreg, breg);
3296
3297 if (! used_at)
3298 return;
3299
3300 break;
3301
3302 case M_J_A:
3303 /* The j instruction may not be used in PIC code, since it
3304 requires an absolute address. We convert it to a b
3305 instruction. */
d9aba805 3306 if (mips_pic == NO_PIC)
0dd2d296
ILT		 3307 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
3308 else
3309 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
670a50eb 3310 return;
3d3c5039 3311
9226253a
ILT		 3312 /* The jal instructions must be handled as macros because when
3313 generating PIC code they expand to multi-instruction
3314 sequences. Normally they are simple instructions. */
3315 case M_JAL_1:
3316 dreg = RA;
3317 /* Fall through. */
3318 case M_JAL_2:
d9aba805
ILT		 3319 if (mips_pic == NO_PIC
3320 || mips_pic == EMBEDDED_PIC)
3321 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
3322 "d,s", dreg, sreg);
3323 else if (mips_pic == SVR4_PIC)
9226253a 3324 {
d9aba805
ILT		 3325 if (sreg != PIC_CALL_REG)
3326 as_warn ("MIPS PIC call to register other than $25");
3327
0dd2d296
ILT		 3328 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
3329 "d,s", dreg, sreg);
d9aba805
ILT		 3330 if (mips_cprestore_offset < 0)
3331 as_warn ("No .cprestore pseudo-op used in PIC code");
3332 else
3333 {
3334 expr1.X_add_number = mips_cprestore_offset;
3335 macro_build ((char *) NULL, &icnt, &expr1,
3336 mips_isa < 3 ? "lw" : "ld",
3337 "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
3338 }
9226253a 3339 }
0dd2d296 3340 else
d9aba805
ILT		 3341 abort ();
3342
9226253a
ILT		 3343 return;
3344
3345 case M_JAL_A:
d9aba805
ILT		 3346 if (mips_pic == NO_PIC)
3347 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
3348 else if (mips_pic == SVR4_PIC)
9226253a 3349 {
fb251650
ILT		 3350 /* If this is a reference to an external symbol, and we are
3351 using a small GOT, we want
d9aba805
ILT		 3352 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3353 nop
3354 jalr $25
3355 nop
3356 lw $gp,cprestore($sp)
3357 The cprestore value is set using the .cprestore
fb251650
ILT		 3358 pseudo-op. If we are using a big GOT, we want
3359 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3360 addu $25,$25,$gp
3361 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3362 nop
3363 jalr $25
3364 nop
3365 lw $gp,cprestore($sp)
3366 If the symbol is not external, we want
d9aba805
ILT		 3367 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3368 nop
3369 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3370 jalr $25
3371 nop
fb251650
ILT		 3372 lw $gp,cprestore($sp) */
3373 frag_grow (40);
3374 if (! mips_big_got)
3375 {
3376 macro_build ((char *) NULL, &icnt, &offset_expr,
3377 mips_isa < 3 ? "lw" : "ld",
3378 "t,o(b)", PIC_CALL_REG,
3379 (int) BFD_RELOC_MIPS_CALL16, GP);
3380 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3381 "nop", "");
3382 p = frag_var (rs_machine_dependent, 4, 0,
3383 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3384 offset_expr.X_add_symbol, (long) 0, (char *) NULL);
3385 }
3386 else
3387 {
3388 int gpdel;
3389
3390 if (reg_needs_delay (GP))
3391 gpdel = 4;
3392 else
3393 gpdel = 0;
3394 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
3395 PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
3396 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3397 mips_isa < 3 ? "addu" : "daddu",
3398 "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
3399 macro_build ((char *) NULL, &icnt, &offset_expr,
3400 mips_isa < 3 ? "lw" : "ld",
3401 "t,o(b)", PIC_CALL_REG,
3402 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
3403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3404 "nop", "");
3405 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
3406 RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel,
3407 0, 0),
3408 offset_expr.X_add_symbol, (long) 0, (char *) NULL);
3409 if (gpdel > 0)
3410 {
3411 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3412 p += 4;
3413 }
3414 macro_build (p, &icnt, &offset_expr,
3415 mips_isa < 3 ? "lw" : "ld",
3416 "t,o(b)", PIC_CALL_REG,
3417 (int) BFD_RELOC_MIPS_GOT16, GP);
3418 p += 4;
3419 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3420 p += 4;
3421 }
d9aba805
ILT		 3422 macro_build (p, &icnt, &offset_expr,
3423 mips_isa < 3 ? "addiu" : "daddiu",
3424 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
3425 (int) BFD_RELOC_LO16);
3426 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3427 "jalr", "s", PIC_CALL_REG);
3428 if (mips_cprestore_offset < 0)
3429 as_warn ("No .cprestore pseudo-op used in PIC code");
3430 else
3431 {
3432 if (mips_noreorder)
3433 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3434 "nop", "");
3435 expr1.X_add_number = mips_cprestore_offset;
3436 macro_build ((char *) NULL, &icnt, &expr1,
3437 mips_isa < 3 ? "lw" : "ld",
3438 "t,o(b)", GP, (int) BFD_RELOC_LO16,
3439 mips_frame_reg);
3440 }
0dd2d296 3441 }
d9aba805 3442 else if (mips_pic == EMBEDDED_PIC)
5b63f465
ILT		 3443 {
3444 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
3445 /* The linker may expand the call to a longer sequence which
3446 uses $at, so we must break rather than return. */
3447 break;
3448 }
d9aba805
ILT		 3449 else
3450 abort ();
3451
9226253a
ILT		 3452 return;
3453
3d3c5039 3454 case M_LB_AB:
670a50eb
ILT		 3455 s = "lb";
3456 goto ld;
3d3c5039 3457 case M_LBU_AB:
670a50eb
ILT		 3458 s = "lbu";
3459 goto ld;
3d3c5039 3460 case M_LH_AB:
670a50eb
ILT		 3461 s = "lh";
3462 goto ld;
3d3c5039 3463 case M_LHU_AB:
670a50eb
ILT		 3464 s = "lhu";
3465 goto ld;
3d3c5039 3466 case M_LW_AB:
670a50eb
ILT		 3467 s = "lw";
3468 goto ld;
3d3c5039 3469 case M_LWC0_AB:
670a50eb 3470 s = "lwc0";
8358c818 3471 coproc = 1;
670a50eb 3472 goto ld;
3d3c5039 3473 case M_LWC1_AB:
670a50eb 3474 s = "lwc1";
8358c818 3475 coproc = 1;
670a50eb 3476 goto ld;
3d3c5039 3477 case M_LWC2_AB:
670a50eb 3478 s = "lwc2";
8358c818 3479 coproc = 1;
670a50eb 3480 goto ld;
3d3c5039 3481 case M_LWC3_AB:
670a50eb 3482 s = "lwc3";
8358c818 3483 coproc = 1;
670a50eb 3484 goto ld;
3d3c5039 3485 case M_LWL_AB:
670a50eb 3486 s = "lwl";
b2b8c24e 3487 lr = 1;
670a50eb 3488 goto ld;
3d3c5039 3489 case M_LWR_AB:
670a50eb 3490 s = "lwr";
b2b8c24e 3491 lr = 1;
8358c818
ILT		 3492 goto ld;
3493 case M_LDC1_AB:
3494 s = "ldc1";
3495 coproc = 1;
3496 goto ld;
3497 case M_LDC2_AB:
3498 s = "ldc2";
3499 coproc = 1;
3500 goto ld;
3501 case M_LDC3_AB:
3502 s = "ldc3";
3503 coproc = 1;
3504 goto ld;
3505 case M_LDL_AB:
3506 s = "ldl";
b2b8c24e 3507 lr = 1;
8358c818
ILT		 3508 goto ld;
3509 case M_LDR_AB:
3510 s = "ldr";
b2b8c24e 3511 lr = 1;
8358c818
ILT		 3512 goto ld;
3513 case M_LL_AB:
3514 s = "ll";
3515 goto ld;
3516 case M_LLD_AB:
3517 s = "lld";
3518 goto ld;
3519 case M_LWU_AB:
3520 s = "lwu";
3d3c5039 3521 ld:
b2b8c24e 3522 if (breg == treg || coproc || lr)
670a50eb
ILT		 3523 {
3524 tempreg = AT;
3525 used_at = 1;
3526 }
3527 else
3528 {
3529 tempreg = treg;
3530 used_at = 0;
3531 }
3532 goto ld_st;
3d3c5039 3533 case M_SB_AB:
670a50eb
ILT		 3534 s = "sb";
3535 goto st;
3d3c5039 3536 case M_SH_AB:
670a50eb
ILT		 3537 s = "sh";
3538 goto st;
3d3c5039 3539 case M_SW_AB:
670a50eb
ILT		 3540 s = "sw";
3541 goto st;
3d3c5039 3542 case M_SWC0_AB:
670a50eb 3543 s = "swc0";
8358c818 3544 coproc = 1;
670a50eb 3545 goto st;
3d3c5039 3546 case M_SWC1_AB:
670a50eb 3547 s = "swc1";
8358c818 3548 coproc = 1;
670a50eb 3549 goto st;
3d3c5039 3550 case M_SWC2_AB:
670a50eb 3551 s = "swc2";
8358c818 3552 coproc = 1;
670a50eb 3553 goto st;
3d3c5039 3554 case M_SWC3_AB:
670a50eb 3555 s = "swc3";
8358c818 3556 coproc = 1;
670a50eb 3557 goto st;
3d3c5039 3558 case M_SWL_AB:
670a50eb
ILT		 3559 s = "swl";
3560 goto st;
3d3c5039 3561 case M_SWR_AB:
670a50eb 3562 s = "swr";
8358c818
ILT		 3563 goto st;
3564 case M_SC_AB:
3565 s = "sc";
3566 goto st;
3567 case M_SCD_AB:
3568 s = "scd";
3569 goto st;
3570 case M_SDC1_AB:
3571 s = "sdc1";
3572 coproc = 1;
3573 goto st;
3574 case M_SDC2_AB:
3575 s = "sdc2";
3576 coproc = 1;
3577 goto st;
3578 case M_SDC3_AB:
3579 s = "sdc3";
3580 coproc = 1;
3581 goto st;
3582 case M_SDL_AB:
3583 s = "sdl";
3584 goto st;
3585 case M_SDR_AB:
3586 s = "sdr";
3d3c5039 3587 st:
670a50eb
ILT		 3588 tempreg = AT;
3589 used_at = 1;
3d3c5039 3590 ld_st:
8358c818
ILT		 3591 if (mask == M_LWC1_AB
3592 || mask == M_SWC1_AB
8358c818 3593 || mask == M_LDC1_AB
0dd2d296
ILT		 3594 || mask == M_SDC1_AB
3595 || mask == M_L_DAB
3596 || mask == M_S_DAB)
670a50eb 3597 fmt = "T,o(b)";
8358c818 3598 else if (coproc)
19ed8960 3599 fmt = "E,o(b)";
670a50eb
ILT		 3600 else
3601 fmt = "t,o(b)";
0dd2d296
ILT		 3602
3603 if (offset_expr.X_op != O_constant
3604 && offset_expr.X_op != O_symbol)
3605 {
3606 as_bad ("expression too complex");
3607 offset_expr.X_op = O_constant;
3608 }
3609
3610 /* A constant expression in PIC code can be handled just as it
3611 is in non PIC code. */
d9aba805 3612 if (mips_pic == NO_PIC
0dd2d296 3613 || offset_expr.X_op == O_constant)
670a50eb 3614 {
0dd2d296
ILT		 3615 /* If this is a reference to a GP relative symbol, and there
3616 is no base register, we want
3617 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
d9aba805 3618 Otherwise, if there is no base register, we want
0dd2d296
ILT		 3619 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3620 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3621 If we have a constant, we need two instructions anyhow,
3622 so we always use the latter form.
3623
3624 If we have a base register, and this is a reference to a
3625 GP relative symbol, we want
3626 addu $tempreg,$breg,$gp
3627 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3628 Otherwise we want
3629 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3630 addu $tempreg,$tempreg,$breg
3631 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3632 With a constant we always use the latter case. */
670a50eb
ILT		 3633 if (breg == 0)
3634 {
7a15a226 3635 if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET
d8a1c247 3636 || nopic_need_relax (offset_expr.X_add_symbol))
0dd2d296
ILT		 3637 p = NULL;
3638 else
3639 {
8ea7f4e8 3640 frag_grow (20);
0dd2d296
ILT		 3641 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3642 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
3643 p = frag_var (rs_machine_dependent, 8, 0,
3644 RELAX_ENCODE (4, 8, 0, 4, 0,
8197b589
ILT		 3645 (mips_warn_about_macros
3646 || (used_at && mips_noat))),
0dd2d296
ILT		 3647 offset_expr.X_add_symbol, (long) 0,
3648 (char *) NULL);
8197b589 3649 used_at = 0;
0dd2d296
ILT		 3650 }
3651 macro_build_lui (p, &icnt, &offset_expr, tempreg);
3652 if (p != NULL)
3653 p += 4;
3654 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
3655 (int) BFD_RELOC_LO16, tempreg);
3656 }
3657 else
3658 {
7a15a226 3659 if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET
d8a1c247 3660 || nopic_need_relax (offset_expr.X_add_symbol))
0dd2d296
ILT		 3661 p = NULL;
3662 else
3663 {
8ea7f4e8 3664 frag_grow (28);
0dd2d296
ILT		 3665 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3666 mips_isa < 3 ? "addu" : "daddu",
3667 "d,v,t", tempreg, breg, GP);
3668 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3669 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
3670 p = frag_var (rs_machine_dependent, 12, 0,
3671 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3672 offset_expr.X_add_symbol, (long) 0,
3673 (char *) NULL);
3674 }
3675 macro_build_lui (p, &icnt, &offset_expr, tempreg);
3676 if (p != NULL)
3677 p += 4;
3678 macro_build (p, &icnt, (expressionS *) NULL,
3679 mips_isa < 3 ? "addu" : "daddu",
3680 "d,v,t", tempreg, tempreg, breg);
3681 if (p != NULL)
3682 p += 4;
3683 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
3684 (int) BFD_RELOC_LO16, tempreg);
670a50eb 3685 }
670a50eb 3686 }
fb251650 3687 else if (mips_pic == SVR4_PIC && ! mips_big_got)
670a50eb 3688 {
0dd2d296
ILT		 3689 /* If this is a reference to an external symbol, we want
3690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3691 nop
3692 <op> $treg,0($tempreg)
3693 Otherwise we want
3694 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3695 nop
3696 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3697 <op> $treg,0($tempreg)
3698 If there is a base register, we add it to $tempreg before
3699 the <op>. If there is a constant, we stick it in the
3700 <op> instruction. We don't handle constants larger than
3701 16 bits, because we have no way to load the upper 16 bits
3702 (actually, we could handle them for the subset of cases
3703 in which we are not using $at). */
3704 assert (offset_expr.X_op == O_symbol);
3705 expr1.X_add_number = offset_expr.X_add_number;
3706 offset_expr.X_add_number = 0;
3707 if (expr1.X_add_number < -0x8000
3708 || expr1.X_add_number >= 0x8000)
3709 as_bad ("PIC code offset overflow (max 16 signed bits)");
8ea7f4e8 3710 frag_grow (20);
0dd2d296
ILT		 3711 macro_build ((char *) NULL, &icnt, &offset_expr,
3712 mips_isa < 3 ? "lw" : "ld",
3713 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
3714 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
3715 p = frag_var (rs_machine_dependent, 4, 0,
3716 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3717 offset_expr.X_add_symbol, (long) 0,
3718 (char *) NULL);
3719 macro_build (p, &icnt, &offset_expr,
3720 mips_isa < 3 ? "addiu" : "daddiu",
3721 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
670a50eb 3722 if (breg != 0)
0dd2d296 3723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6e8dda9c
ILT		 3724 mips_isa < 3 ? "addu" : "daddu",
3725 "d,v,t", tempreg, tempreg, breg);
0dd2d296
ILT		 3726 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
3727 (int) BFD_RELOC_LO16, tempreg);
670a50eb 3728 }
fb251650
ILT		 3729 else if (mips_pic == SVR4_PIC)
3730 {
3731 int gpdel;
3732
3733 /* If this is a reference to an external symbol, we want
3734 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3735 addu $tempreg,$tempreg,$gp
3736 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3737 <op> $treg,0($tempreg)
3738 Otherwise we want
3739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3740 nop
3741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3742 <op> $treg,0($tempreg)
3743 If there is a base register, we add it to $tempreg before
3744 the <op>. If there is a constant, we stick it in the
3745 <op> instruction. We don't handle constants larger than
3746 16 bits, because we have no way to load the upper 16 bits
3747 (actually, we could handle them for the subset of cases
3748 in which we are not using $at). */
3749 assert (offset_expr.X_op == O_symbol);
3750 expr1.X_add_number = offset_expr.X_add_number;
3751 offset_expr.X_add_number = 0;
3752 if (expr1.X_add_number < -0x8000
3753 || expr1.X_add_number >= 0x8000)
3754 as_bad ("PIC code offset overflow (max 16 signed bits)");
3755 if (reg_needs_delay (GP))
3756 gpdel = 4;
3757 else
3758 gpdel = 0;
3759 frag_grow (36);
3760 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
3761 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
3762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3763 mips_isa < 3 ? "addu" : "daddu",
3764 "d,v,t", tempreg, tempreg, GP);
3765 macro_build ((char *) NULL, &icnt, &offset_expr,
3766 mips_isa < 3 ? "lw" : "ld",
867a58b3
ILT		 3767 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
3768 tempreg);
fb251650
ILT		 3769 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
3770 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
3771 offset_expr.X_add_symbol, (long) 0, (char *) NULL);
3772 if (gpdel > 0)
3773 {
3774 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3775 p += 4;
3776 }
3777 macro_build (p, &icnt, &offset_expr,
3778 mips_isa < 3 ? "lw" : "ld",
867a58b3 3779 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
fb251650
ILT		 3780 p += 4;
3781 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
3782 p += 4;
3783 macro_build (p, &icnt, &offset_expr,
3784 mips_isa < 3 ? "addiu" : "daddiu",
3785 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3786 if (breg != 0)
3787 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3788 mips_isa < 3 ? "addu" : "daddu",
3789 "d,v,t", tempreg, tempreg, breg);
3790 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
3791 (int) BFD_RELOC_LO16, tempreg);
3792 }
d9aba805
ILT		 3793 else if (mips_pic == EMBEDDED_PIC)
3794 {
3795 /* If there is no base register, we want
3796 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3797 If there is a base register, we want
3798 addu $tempreg,$breg,$gp
3799 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3800 */
3801 assert (offset_expr.X_op == O_symbol);
3802 if (breg == 0)
3803 {
3804 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3805 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
3806 used_at = 0;
3807 }
3808 else
3809 {
3810 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3811 mips_isa < 3 ? "addu" : "daddu",
3812 "d,v,t", tempreg, breg, GP);
3813 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3814 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
3815 }
3816 }
3817 else
3818 abort ();
0dd2d296
ILT		 3819
3820 if (! used_at)
3821 return;
3822
3823 break;
3d3c5039
ILT		 3824
3825 case M_LI:
19ed8960 3826 case M_LI_S:
d8a1c247
KR		 3827 load_register (&icnt, treg, &imm_expr, 0);
3828 return;
3829
3830 case M_DLI:
3831 load_register (&icnt, treg, &imm_expr, 1);
670a50eb 3832 return;
3d3c5039 3833
0dd2d296 3834 case M_LI_SS:
55933a58 3835 if (imm_expr.X_op == O_constant)
0dd2d296 3836 {
d8a1c247 3837 load_register (&icnt, AT, &imm_expr, 0);
d2c71068
ILT		 3838 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3839 "mtc1", "t,G", AT, treg);
3840 break;
0dd2d296 3841 }
d9aba805 3842 else
d2c71068 3843 {
55933a58
ILT		 3844 assert (offset_expr.X_op == O_symbol
3845 && strcmp (segment_name (S_GET_SEGMENT
3846 (offset_expr.X_add_symbol)),
3847 ".lit4") == 0
3848 && offset_expr.X_add_number == 0);
3849 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
3850 treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
d2c71068
ILT		 3851 return;
3852 }
0dd2d296 3853
3d3c5039 3854 case M_LI_D:
d9aba805
ILT		 3855 /* We know that sym is in the .rdata section. First we get the
3856 upper 16 bits of the address. */
3857 if (mips_pic == NO_PIC)
0dd2d296
ILT		 3858 {
3859 /* FIXME: This won't work for a 64 bit address. */
3860 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
3861 }
d9aba805 3862 else if (mips_pic == SVR4_PIC)
0dd2d296
ILT		 3863 {
3864 macro_build ((char *) NULL, &icnt, &offset_expr,
3865 mips_isa < 3 ? "lw" : "ld",
3866 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
3867 }
d9aba805
ILT		 3868 else if (mips_pic == EMBEDDED_PIC)
3869 {
3870 /* For embedded PIC we pick up the entire address off $gp in
3871 a single instruction. */
3872 macro_build ((char *) NULL, &icnt, &offset_expr,
3873 mips_isa < 3 ? "addiu" : "daddiu",
3874 "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
3875 offset_expr.X_op = O_constant;
3876 offset_expr.X_add_number = 0;
3877 }
3878 else
3879 abort ();
3880
0dd2d296 3881 /* Now we load the register(s). */
8358c818 3882 if (mips_isa >= 3)
0dd2d296
ILT		 3883 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
3884 treg, (int) BFD_RELOC_LO16, AT);
8358c818
ILT		 3885 else
3886 {
0dd2d296
ILT		 3887 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
3888 treg, (int) BFD_RELOC_LO16, AT);
3889 if (treg != 31)
3890 {
3891 /* FIXME: How in the world do we deal with the possible
3892 overflow here? */
3893 offset_expr.X_add_number += 4;
3894 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
3895 treg + 1, (int) BFD_RELOC_LO16, AT);
3896 }
8358c818 3897 }
d2c71068
ILT		 3898
3899 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3900 does not become a variant frag. */
3901 frag_wane (frag_now);
3902 frag_new (0);
3903
670a50eb 3904 break;
3d3c5039
ILT		 3905
3906 case M_LI_DD:
55933a58
ILT		 3907 assert (offset_expr.X_op == O_symbol
3908 && offset_expr.X_add_number == 0);
3909 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
3910 if (strcmp (s, ".lit8") == 0)
8358c818 3911 {
0dd2d296
ILT		 3912 if (mips_isa >= 2)
3913 {
3914 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
3915 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
3916 return;
3917 }
3918 breg = GP;
3919 r = BFD_RELOC_MIPS_LITERAL;
3920 goto dob;
3921 }
55933a58 3922 else
0dd2d296 3923 {
55933a58
ILT		 3924 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
3925 if (mips_pic == SVR4_PIC)
3926 macro_build ((char *) NULL, &icnt, &offset_expr,
3927 mips_isa < 3 ? "lw" : "ld",
3928 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
3929 else
3930 {
3931 /* FIXME: This won't work for a 64 bit address. */
3932 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
3933 }
3934
0dd2d296
ILT		 3935 if (mips_isa >= 2)
3936 {
3937 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
55933a58 3938 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
94b68f04
ILT		 3939
3940 /* To avoid confusion in tc_gen_reloc, we must ensure
3941 that this does not become a variant frag. */
3942 frag_wane (frag_now);
3943 frag_new (0);
3944
0dd2d296
ILT		 3945 break;
3946 }
3947 breg = AT;
3948 r = BFD_RELOC_LO16;
3949 goto dob;
8358c818 3950 }
9226253a 3951
3d3c5039 3952 case M_L_DOB:
9a7d824a
ILT		 3953 /* Even on a big endian machine $fn comes before $fn+1. We have
3954 to adjust when loading from memory. */
9226253a
ILT		 3955 r = BFD_RELOC_LO16;
3956 dob:
8358c818 3957 assert (mips_isa < 2);
0dd2d296 3958 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
9a7d824a 3959 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
9226253a 3960 (int) r, breg);
0dd2d296
ILT		 3961 /* FIXME: A possible overflow which I don't know how to deal
3962 with. */
670a50eb 3963 offset_expr.X_add_number += 4;
0dd2d296 3964 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
9a7d824a 3965 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
9226253a 3966 (int) r, breg);
d2c71068
ILT		 3967
3968 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3969 does not become a variant frag. */
3970 frag_wane (frag_now);
3971 frag_new (0);
3972
0dd2d296
ILT		 3973 if (breg != AT)
3974 return;
3975 break;
3d3c5039
ILT		 3976
3977 case M_L_DAB:
670a50eb
ILT		 3978 /*
3979 * The MIPS assembler seems to check for X_add_number not
3980 * being double aligned and generating:
3981 * lui at,%hi(foo+1)
3982 * addu at,at,v1
3983 * addiu at,at,%lo(foo+1)
3984 * lwc1 f2,0(at)
3985 * lwc1 f3,4(at)
3986 * But, the resulting address is the same after relocation so why
3987 * generate the extra instruction?
3988 */
4032d3f0 3989 coproc = 1;
0dd2d296 3990 if (mips_isa >= 2)
670a50eb 3991 {
0dd2d296
ILT		 3992 s = "ldc1";
3993 goto ld;
670a50eb 3994 }
0dd2d296
ILT		 3995
3996 s = "lwc1";
3997 fmt = "T,o(b)";
0dd2d296
ILT		 3998 goto ldd_std;
3999
4000 case M_S_DAB:
8358c818 4001 if (mips_isa >= 2)
8358c818 4002 {
0dd2d296
ILT		 4003 s = "sdc1";
4004 goto st;
8358c818 4005 }
3d3c5039 4006
0dd2d296
ILT		 4007 s = "swc1";
4008 fmt = "T,o(b)";
4009 coproc = 1;
4010 goto ldd_std;
3d3c5039
ILT		 4011
4012 case M_LD_AB:
0dd2d296 4013 if (mips_isa >= 3)
670a50eb 4014 {
0dd2d296
ILT		 4015 s = "ld";
4016 goto ld;
670a50eb 4017 }
0dd2d296
ILT		 4018
4019 s = "lw";
4020 fmt = "t,o(b)";
4021 goto ldd_std;
4022
4023 case M_SD_AB:
4024 if (mips_isa >= 3)
670a50eb 4025 {
0dd2d296
ILT		 4026 s = "sd";
4027 goto st;
670a50eb 4028 }
0dd2d296 4029
670a50eb 4030 s = "sw";
0dd2d296
ILT		 4031 fmt = "t,o(b)";
4032
4033 ldd_std:
4034 if (offset_expr.X_op != O_symbol
4035 && offset_expr.X_op != O_constant)
670a50eb 4036 {
0dd2d296
ILT		 4037 as_bad ("expression too complex");
4038 offset_expr.X_op = O_constant;
4039 }
4040
4041 /* Even on a big endian machine $fn comes before $fn+1. We have
4042 to adjust when loading from memory. We set coproc if we must
4043 load $fn+1 first. */
4044 if (byte_order == LITTLE_ENDIAN)
4045 coproc = 0;
4046
d9aba805 4047 if (mips_pic == NO_PIC
0dd2d296
ILT		 4048 || offset_expr.X_op == O_constant)
4049 {
4050 /* If this is a reference to a GP relative symbol, we want
4051 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4052 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4053 If we have a base register, we use this
4054 addu $at,$breg,$gp
4055 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4056 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4057 If this is not a GP relative symbol, we want
4058 lui $at,<sym> (BFD_RELOC_HI16_S)
4059 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4060 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4061 If there is a base register, we add it to $at after the
4062 lui instruction. If there is a constant, we always use
4063 the last case. */
7a15a226 4064 if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET
d8a1c247 4065 || nopic_need_relax (offset_expr.X_add_symbol))
670a50eb 4066 {
0dd2d296
ILT		 4067 p = NULL;
4068 used_at = 1;
670a50eb
ILT		 4069 }
4070 else
0dd2d296
ILT		 4071 {
4072 int off;
4073
4074 if (breg == 0)
4075 {
8ea7f4e8 4076 frag_grow (28);
0dd2d296
ILT		 4077 tempreg = GP;
4078 off = 0;
4079 used_at = 0;
4080 }
4081 else
4082 {
8ea7f4e8 4083 frag_grow (36);
0dd2d296
ILT		 4084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4085 mips_isa < 3 ? "addu" : "daddu",
4086 "d,v,t", AT, breg, GP);
4087 tempreg = AT;
4088 off = 4;
4089 used_at = 1;
4090 }
4091
4092 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
4093 coproc ? treg + 1 : treg,
4094 (int) BFD_RELOC_MIPS_GPREL, tempreg);
4095 offset_expr.X_add_number += 4;
55933a58
ILT		 4096
4097 /* Set mips_optimize to 2 to avoid inserting an
4098 undesired nop. */
4099 hold_mips_optimize = mips_optimize;
4100 mips_optimize = 2;
0dd2d296
ILT		 4101 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
4102 coproc ? treg : treg + 1,
4103 (int) BFD_RELOC_MIPS_GPREL, tempreg);
55933a58
ILT		 4104 mips_optimize = hold_mips_optimize;
4105
0dd2d296
ILT		 4106 p = frag_var (rs_machine_dependent, 12 + off, 0,
4107 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
8197b589 4108 used_at && mips_noat),
0dd2d296
ILT		 4109 offset_expr.X_add_symbol, (long) 0,
4110 (char *) NULL);
777ad64d
ILT		 4111
4112 /* We just generated two relocs. When tc_gen_reloc
4113 handles this case, it will skip the first reloc and
4114 handle the second. The second reloc already has an
4115 extra addend of 4, which we added above. We must
4116 subtract it out, and then subtract another 4 to make
4117 the first reloc come out right. The second reloc
4118 will come out right because we are going to add 4 to
4119 offset_expr when we build its instruction below. */
4120 offset_expr.X_add_number -= 8;
0dd2d296
ILT		 4121 offset_expr.X_op = O_constant;
4122 }
4123 macro_build_lui (p, &icnt, &offset_expr, AT);
4124 if (p != NULL)
4125 p += 4;
4126 if (breg != 0)
4127 {
4128 macro_build (p, &icnt, (expressionS *) NULL,
4129 mips_isa < 3 ? "addu" : "daddu",
4130 "d,v,t", AT, breg, AT);
4131 if (p != NULL)
4132 p += 4;
4133 }
4134 macro_build (p, &icnt, &offset_expr, s, fmt,
4135 coproc ? treg + 1 : treg,
4136 (int) BFD_RELOC_LO16, AT);
4137 if (p != NULL)
4138 p += 4;
4139 /* FIXME: How do we handle overflow here? */
4140 offset_expr.X_add_number += 4;
4141 macro_build (p, &icnt, &offset_expr, s, fmt,
4142 coproc ? treg : treg + 1,
4143 (int) BFD_RELOC_LO16, AT);
4144 }
fb251650 4145 else if (mips_pic == SVR4_PIC && ! mips_big_got)
670a50eb 4146 {
0dd2d296
ILT		 4147 int off;
4148
4149 /* If this is a reference to an external symbol, we want
4150 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4151 nop
4152 <op> $treg,0($at)
4153 <op> $treg+1,4($at)
4154 Otherwise we want
4155 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4156 nop
4157 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4158 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4159 If there is a base register we add it to $at before the
4160 lwc1 instructions. If there is a constant we include it
4161 in the lwc1 instructions. */
4162 used_at = 1;
4163 expr1.X_add_number = offset_expr.X_add_number;
4164 offset_expr.X_add_number = 0;
4165 if (expr1.X_add_number < -0x8000
4166 || expr1.X_add_number >= 0x8000 - 4)
4167 as_bad ("PIC code offset overflow (max 16 signed bits)");
4168 if (breg == 0)
4169 off = 0;
4170 else
4171 off = 4;
8ea7f4e8 4172 frag_grow (24 + off);
0dd2d296
ILT		 4173 macro_build ((char *) NULL, &icnt, &offset_expr,
4174 mips_isa < 3 ? "lw" : "ld",
4175 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
4176 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
670a50eb 4177 if (breg != 0)
0dd2d296 4178 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6e8dda9c 4179 mips_isa < 3 ? "addu" : "daddu",
0dd2d296
ILT		 4180 "d,v,t", AT, breg, AT);
4181 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
4182 coproc ? treg + 1 : treg,
4183 (int) BFD_RELOC_LO16, AT);
4184 expr1.X_add_number += 4;
55933a58
ILT		 4185
4186 /* Set mips_optimize to 2 to avoid inserting an undesired
4187 nop. */
4188 hold_mips_optimize = mips_optimize;
4189 mips_optimize = 2;
0dd2d296
ILT		 4190 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
4191 coproc ? treg : treg + 1,
4192 (int) BFD_RELOC_LO16, AT);
55933a58
ILT		 4193 mips_optimize = hold_mips_optimize;
4194
0dd2d296
ILT		 4195 (void) frag_var (rs_machine_dependent, 0, 0,
4196 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
4197 offset_expr.X_add_symbol, (long) 0,
4198 (char *) NULL);
8358c818 4199 }
fb251650
ILT		 4200 else if (mips_pic == SVR4_PIC)
4201 {
4202 int gpdel, off;
4203
4204 /* If this is a reference to an external symbol, we want
4205 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4206 addu $at,$at,$gp
4207 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4208 nop
4209 <op> $treg,0($at)
4210 <op> $treg+1,4($at)
4211 Otherwise we want
4212 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4213 nop
4214 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4215 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4216 If there is a base register we add it to $at before the
4217 lwc1 instructions. If there is a constant we include it
4218 in the lwc1 instructions. */
4219 used_at = 1;
4220 expr1.X_add_number = offset_expr.X_add_number;
4221 offset_expr.X_add_number = 0;
4222 if (expr1.X_add_number < -0x8000
4223 || expr1.X_add_number >= 0x8000 - 4)
4224 as_bad ("PIC code offset overflow (max 16 signed bits)");
4225 if (reg_needs_delay (GP))
4226 gpdel = 4;
4227 else
4228 gpdel = 0;
4229 if (breg == 0)
4230 off = 0;
4231 else
4232 off = 4;
4233 frag_grow (56);
4234 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4235 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
4236 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4237 mips_isa < 3 ? "addu" : "daddu",
4238 "d,v,t", AT, AT, GP);
4239 macro_build ((char *) NULL, &icnt, &offset_expr,
4240 mips_isa < 3 ? "lw" : "ld",
4241 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
4242 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
4243 if (breg != 0)
4244 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4245 mips_isa < 3 ? "addu" : "daddu",
4246 "d,v,t", AT, breg, AT);
4247 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
4248 coproc ? treg + 1 : treg,
4249 (int) BFD_RELOC_LO16, AT);
4250 expr1.X_add_number += 4;
4251
4252 /* Set mips_optimize to 2 to avoid inserting an undesired
4253 nop. */
4254 hold_mips_optimize = mips_optimize;
4255 mips_optimize = 2;
4256 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
4257 coproc ? treg : treg + 1,
4258 (int) BFD_RELOC_LO16, AT);
4259 mips_optimize = hold_mips_optimize;
4260 expr1.X_add_number -= 4;
4261
4262 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
4263 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
4264 8 + gpdel + off, 1, 0),
4265 offset_expr.X_add_symbol, (long) 0,
4266 (char *) NULL);
4267 if (gpdel > 0)
4268 {
4269 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4270 p += 4;
4271 }
4272 macro_build (p, &icnt, &offset_expr,
4273 mips_isa < 3 ? "lw" : "ld",
4274 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
4275 p += 4;
4276 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4277 p += 4;
4278 if (breg != 0)
4279 {
4280 macro_build (p, &icnt, (expressionS *) NULL,
4281 mips_isa < 3 ? "addu" : "daddu",
4282 "d,v,t", AT, breg, AT);
4283 p += 4;
4284 }
4285 macro_build (p, &icnt, &expr1, s, fmt,
4286 coproc ? treg + 1 : treg,
4287 (int) BFD_RELOC_LO16, AT);
4288 p += 4;
4289 expr1.X_add_number += 4;
4290
4291 /* Set mips_optimize to 2 to avoid inserting an undesired
4292 nop. */
4293 hold_mips_optimize = mips_optimize;
4294 mips_optimize = 2;
4295 macro_build (p, &icnt, &expr1, s, fmt,
4296 coproc ? treg : treg + 1,
4297 (int) BFD_RELOC_LO16, AT);
4298 mips_optimize = hold_mips_optimize;
4299 }
d9aba805
ILT		 4300 else if (mips_pic == EMBEDDED_PIC)
4301 {
4302 /* If there is no base register, we use
4303 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4304 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4305 If we have a base register, we use
4306 addu $at,$breg,$gp
4307 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4308 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4309 */
4310 if (breg == 0)
4311 {
4312 tempreg = GP;
4313 used_at = 0;
4314 }
4315 else
4316 {
4317 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4318 mips_isa < 3 ? "addu" : "daddu",
4319 "d,v,t", AT, breg, GP);
4320 tempreg = AT;
4321 used_at = 1;
4322 }
4323
4324 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
4325 coproc ? treg + 1 : treg,
4326 (int) BFD_RELOC_MIPS_GPREL, tempreg);
4327 offset_expr.X_add_number += 4;
4328 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
4329 coproc ? treg : treg + 1,
4330 (int) BFD_RELOC_MIPS_GPREL, tempreg);
4331 }
4332 else
4333 abort ();
0dd2d296
ILT		 4334
4335 if (! used_at)
4336 return;
4337
4338 break;
4339
4340 case M_LD_OB:
4341 s = "lw";
4342 goto sd_ob;
4343 case M_SD_OB:
4344 s = "sw";
4345 sd_ob:
4346 assert (mips_isa < 3);
4347 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
4348 (int) BFD_RELOC_LO16, breg);
4349 offset_expr.X_add_number += 4;
4350 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
4351 (int) BFD_RELOC_LO16, breg);
670a50eb 4352 return;
917fae09
SS		 4353#ifdef LOSING_COMPILER
4354 default:
4355 macro2 (ip);
4356 return;
4357 }
4358 if (mips_noat)
4359 as_warn ("Macro used $at after \".set noat\"");
4360}
4361
4362static void
4363macro2 (ip)
4364 struct mips_cl_insn *ip;
4365{
4366 register int treg, sreg, dreg, breg;
4367 int tempreg;
4368 int mask;
4369 int icnt = 0;
4370 int used_at;
4371 expressionS expr1;
4372 const char *s;
4373 const char *s2;
4374 const char *fmt;
4375 int likely = 0;
4376 int dbl = 0;
4377 int coproc = 0;
adcf2b9d
ILT		 4378 int lr = 0;
4379 int off;
917fae09
SS		 4380 offsetT maxnum;
4381 bfd_reloc_code_real_type r;
4382 char *p;
4383
4384 treg = (ip->insn_opcode >> 16) & 0x1f;
4385 dreg = (ip->insn_opcode >> 11) & 0x1f;
4386 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4387 mask = ip->insn_mo->mask;
4388
4389 expr1.X_op = O_constant;
4390 expr1.X_op_symbol = NULL;
4391 expr1.X_add_symbol = NULL;
4392 expr1.X_add_number = 1;
4393
4394 switch (mask)
4395 {
4396#endif /* LOSING_COMPILER */
3d3c5039 4397
8358c818
ILT		 4398 case M_DMUL:
4399 dbl = 1;
3d3c5039 4400 case M_MUL:
0dd2d296 4401 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4402 dbl ? "dmultu" : "multu",
4403 "s,t", sreg, treg);
0dd2d296 4404 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
670a50eb 4405 return;
3d3c5039 4406
8358c818
ILT		 4407 case M_DMUL_I:
4408 dbl = 1;
3d3c5039 4409 case M_MUL_I:
8358c818
ILT		 4410 /* The MIPS assembler some times generates shifts and adds. I'm
4411 not trying to be that fancy. GCC should do this for us
4412 anyway. */
d8a1c247 4413 load_register (&icnt, AT, &imm_expr, dbl);
0dd2d296 4414 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4415 dbl ? "dmult" : "mult",
4416 "s,t", sreg, AT);
0dd2d296 4417 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
670a50eb 4418 break;
3d3c5039 4419
8358c818
ILT		 4420 case M_DMULO:
4421 dbl = 1;
4422 case M_MULO:
4423 mips_emit_delays ();
4424 ++mips_noreorder;
0dd2d296
ILT		 4425 mips_any_noreorder = 1;
4426 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4427 dbl ? "dmult" : "mult",
4428 "s,t", sreg, treg);
0dd2d296
ILT		 4429 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
4430 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4431 dbl ? "dsra32" : "sra",
4432 "d,w,<", dreg, dreg, 31);
0dd2d296 4433 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
8ea7f4e8
ILT		 4434 if (mips_trap)
4435 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT);
4436 else
4437 {
4438 expr1.X_add_number = 8;
4439 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
4440 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
4441 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
4442 }
8358c818 4443 --mips_noreorder;
0dd2d296 4444 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
8358c818
ILT		 4445 break;
4446
4447 case M_DMULOU:
4448 dbl = 1;
4449 case M_MULOU:
4450 mips_emit_delays ();
4451 ++mips_noreorder;
0dd2d296
ILT		 4452 mips_any_noreorder = 1;
4453 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4454 dbl ? "dmultu" : "multu",
4455 "s,t", sreg, treg);
0dd2d296
ILT		 4456 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
4457 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
8ea7f4e8
ILT		 4458 if (mips_trap)
4459 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0);
4460 else
4461 {
4462 expr1.X_add_number = 8;
4463 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
4464 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
4465 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
4466 }
8358c818
ILT		 4467 --mips_noreorder;
4468 break;
4469
3d3c5039 4470 case M_ROL:
0dd2d296
ILT		 4471 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
4472 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
4473 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg,
4474 treg);
4475 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
670a50eb 4476 break;
3d3c5039
ILT		 4477
4478 case M_ROL_I:
0dd2d296 4479 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg,
a40aee38 4480 (int) (imm_expr.X_add_number & 0x1f));
0dd2d296 4481 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
a40aee38 4482 (int) ((0 - imm_expr.X_add_number) & 0x1f));
0dd2d296 4483 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
670a50eb 4484 break;
3d3c5039
ILT		 4485
4486 case M_ROR:
0dd2d296
ILT		 4487 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
4488 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
4489 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg,
4490 treg);
4491 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
670a50eb 4492 break;
3d3c5039
ILT		 4493
4494 case M_ROR_I:
0dd2d296 4495 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg,
a40aee38 4496 (int) (imm_expr.X_add_number & 0x1f));
0dd2d296 4497 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
a40aee38 4498 (int) ((0 - imm_expr.X_add_number) & 0x1f));
0dd2d296 4499 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
670a50eb 4500 break;
3d3c5039
ILT		 4501
4502 case M_S_DOB:
8358c818 4503 assert (mips_isa < 2);
9a7d824a
ILT		 4504 /* Even on a big endian machine $fn comes before $fn+1. We have
4505 to adjust when storing to memory. */
0dd2d296 4506 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
9a7d824a 4507 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
9226253a 4508 (int) BFD_RELOC_LO16, breg);
670a50eb 4509 offset_expr.X_add_number += 4;
0dd2d296 4510 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
9a7d824a 4511 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
9226253a 4512 (int) BFD_RELOC_LO16, breg);
670a50eb 4513 return;
3d3c5039 4514
3d3c5039 4515 case M_SEQ:
670a50eb 4516 if (sreg == 0)
0dd2d296
ILT		 4517 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
4518 treg, (int) BFD_RELOC_LO16);
670a50eb 4519 else if (treg == 0)
0dd2d296
ILT		 4520 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
4521 sreg, (int) BFD_RELOC_LO16);
670a50eb
ILT		 4522 else
4523 {
0dd2d296
ILT		 4524 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
4525 sreg, treg);
4526 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
4527 dreg, (int) BFD_RELOC_LO16);
3d3c5039 4528 }
670a50eb 4529 return;
3d3c5039
ILT		 4530
4531 case M_SEQ_I:
670a50eb
ILT		 4532 if (imm_expr.X_add_number == 0)
4533 {
0dd2d296
ILT		 4534 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
4535 sreg, (int) BFD_RELOC_LO16);
670a50eb 4536 return;
3d3c5039 4537 }
670a50eb
ILT		 4538 if (sreg == 0)
4539 {
9a7d824a 4540 as_warn ("Instruction %s: result is always false",
6e8dda9c 4541 ip->insn_mo->name);
0dd2d296 4542 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
670a50eb 4543 return;
3d3c5039 4544 }
6e8dda9c 4545 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 4546 {
0dd2d296
ILT		 4547 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
4548 sreg, (int) BFD_RELOC_LO16);
670a50eb 4549 used_at = 0;
6e8dda9c
ILT		 4550 }
4551 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
4552 {
4553 imm_expr.X_add_number = -imm_expr.X_add_number;
0dd2d296 4554 macro_build ((char *) NULL, &icnt, &imm_expr,
6e8dda9c 4555 mips_isa < 3 ? "addiu" : "daddiu",
9226253a
ILT		 4556 "t,r,j", dreg, sreg,
4557 (int) BFD_RELOC_LO16);
6e8dda9c
ILT		 4558 used_at = 0;
4559 }
4560 else
4561 {
d8a1c247 4562 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296
ILT		 4563 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
4564 sreg, AT);
670a50eb
ILT		 4565 used_at = 1;
4566 }
0dd2d296 4567 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
9226253a 4568 (int) BFD_RELOC_LO16);
670a50eb
ILT		 4569 if (used_at)
4570 break;
4571 return;
3d3c5039
ILT		 4572
4573 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
670a50eb
ILT		 4574 s = "slt";
4575 goto sge;
3d3c5039 4576 case M_SGEU:
670a50eb 4577 s = "sltu";
3d3c5039 4578 sge:
0dd2d296
ILT		 4579 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
4580 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
9226253a 4581 (int) BFD_RELOC_LO16);
670a50eb 4582 return;
3d3c5039 4583
670a50eb 4584 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
3d3c5039 4585 case M_SGEU_I:
6e8dda9c 4586 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 4587 {
0dd2d296 4588 macro_build ((char *) NULL, &icnt, &expr1,
6e8dda9c 4589 mask == M_SGE_I ? "slti" : "sltiu",
9226253a 4590 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb
ILT		 4591 used_at = 0;
4592 }
4593 else
4594 {
d8a1c247 4595 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 4596 macro_build ((char *) NULL, &icnt, NULL,
6e8dda9c
ILT		 4597 mask == M_SGE_I ? "slt" : "sltu",
4598 "d,v,t", dreg, sreg, AT);
670a50eb
ILT		 4599 used_at = 1;
4600 }
0dd2d296 4601 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
9226253a 4602 (int) BFD_RELOC_LO16);
670a50eb
ILT		 4603 if (used_at)
4604 break;
4605 return;
3d3c5039
ILT		 4606
4607 case M_SGT: /* sreg > treg <==> treg < sreg */
670a50eb
ILT		 4608 s = "slt";
4609 goto sgt;
3d3c5039 4610 case M_SGTU:
670a50eb 4611 s = "sltu";
3d3c5039 4612 sgt:
0dd2d296 4613 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
670a50eb 4614 return;
3d3c5039 4615
670a50eb
ILT		 4616 case M_SGT_I: /* sreg > I <==> I < sreg */
4617 s = "slt";
4618 goto sgti;
3d3c5039 4619 case M_SGTU_I:
670a50eb 4620 s = "sltu";
3d3c5039 4621 sgti:
d8a1c247 4622 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 4623 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
670a50eb 4624 break;
3d3c5039 4625
670a50eb
ILT		 4626 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4627 s = "slt";
4628 goto sle;
3d3c5039 4629 case M_SLEU:
670a50eb 4630 s = "sltu";
3d3c5039 4631 sle:
0dd2d296
ILT		 4632 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
4633 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
9226253a 4634 (int) BFD_RELOC_LO16);
670a50eb 4635 return;
3d3c5039 4636
670a50eb
ILT		 4637 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4638 s = "slt";
4639 goto slei;
3d3c5039 4640 case M_SLEU_I:
670a50eb 4641 s = "sltu";
3d3c5039 4642 slei:
d8a1c247 4643 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296
ILT		 4644 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
4645 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
9226253a 4646 (int) BFD_RELOC_LO16);
670a50eb 4647 break;
3d3c5039
ILT		 4648
4649 case M_SLT_I:
6e8dda9c 4650 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 4651 {
0dd2d296
ILT		 4652 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
4653 dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb 4654 return;
3d3c5039 4655 }
d8a1c247 4656 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 4657 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
670a50eb 4658 break;
3d3c5039
ILT		 4659
4660 case M_SLTU_I:
6e8dda9c 4661 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 4662 {
0dd2d296
ILT		 4663 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
4664 dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb 4665 return;
3d3c5039 4666 }
d8a1c247 4667 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296
ILT		 4668 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg,
4669 AT);
670a50eb 4670 break;
3d3c5039
ILT		 4671
4672 case M_SNE:
670a50eb 4673 if (sreg == 0)
0dd2d296
ILT		 4674 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
4675 treg);
670a50eb 4676 else if (treg == 0)
0dd2d296
ILT		 4677 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
4678 sreg);
670a50eb
ILT		 4679 else
4680 {
0dd2d296
ILT		 4681 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
4682 sreg, treg);
4683 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
4684 dreg);
3d3c5039 4685 }
670a50eb 4686 return;
3d3c5039
ILT		 4687
4688 case M_SNE_I:
670a50eb
ILT		 4689 if (imm_expr.X_add_number == 0)
4690 {
0dd2d296
ILT		 4691 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
4692 sreg);
670a50eb 4693 return;
3d3c5039 4694 }
670a50eb
ILT		 4695 if (sreg == 0)
4696 {
9a7d824a 4697 as_warn ("Instruction %s: result is always true",
6e8dda9c 4698 ip->insn_mo->name);
0dd2d296 4699 macro_build ((char *) NULL, &icnt, &expr1,
6e8dda9c 4700 mips_isa < 3 ? "addiu" : "daddiu",
9226253a 4701 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
670a50eb 4702 return;
3d3c5039 4703 }
6e8dda9c 4704 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 4705 {
0dd2d296
ILT		 4706 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
4707 dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb 4708 used_at = 0;
6e8dda9c
ILT		 4709 }
4710 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
4711 {
4712 imm_expr.X_add_number = -imm_expr.X_add_number;
0dd2d296 4713 macro_build ((char *) NULL, &icnt, &imm_expr,
6e8dda9c 4714 mips_isa < 3 ? "addiu" : "daddiu",
9226253a 4715 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6e8dda9c
ILT		 4716 used_at = 0;
4717 }
4718 else
4719 {
d8a1c247 4720 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296
ILT		 4721 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
4722 sreg, AT);
670a50eb
ILT		 4723 used_at = 1;
4724 }
0dd2d296 4725 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
670a50eb
ILT		 4726 if (used_at)
4727 break;
4728 return;
3d3c5039 4729
8358c818
ILT		 4730 case M_DSUB_I:
4731 dbl = 1;
3d3c5039 4732 case M_SUB_I:
6e8dda9c 4733 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 4734 {
4735 imm_expr.X_add_number = -imm_expr.X_add_number;
0dd2d296 4736 macro_build ((char *) NULL, &icnt, &imm_expr,
8358c818 4737 dbl ? "daddi" : "addi",
9226253a 4738 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb 4739 return;
3d3c5039 4740 }
d8a1c247 4741 load_register (&icnt, AT, &imm_expr, dbl);
0dd2d296 4742 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4743 dbl ? "dsub" : "sub",
4744 "d,v,t", dreg, sreg, AT);
670a50eb 4745 break;
3d3c5039 4746
8358c818
ILT		 4747 case M_DSUBU_I:
4748 dbl = 1;
3d3c5039 4749 case M_SUBU_I:
6e8dda9c 4750 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 4751 {
4752 imm_expr.X_add_number = -imm_expr.X_add_number;
0dd2d296 4753 macro_build ((char *) NULL, &icnt, &imm_expr,
8358c818 4754 dbl ? "daddiu" : "addiu",
9226253a 4755 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
670a50eb 4756 return;
3d3c5039 4757 }
d8a1c247 4758 load_register (&icnt, AT, &imm_expr, dbl);
0dd2d296 4759 macro_build ((char *) NULL, &icnt, NULL,
8358c818
ILT		 4760 dbl ? "dsubu" : "subu",
4761 "d,v,t", dreg, sreg, AT);
4762 break;
4763
4764 case M_TEQ_I:
4765 s = "teq";
4766 goto trap;
4767 case M_TGE_I:
4768 s = "tge";
4769 goto trap;
4770 case M_TGEU_I:
4771 s = "tgeu";
4772 goto trap;
4773 case M_TLT_I:
4774 s = "tlt";
4775 goto trap;
4776 case M_TLTU_I:
4777 s = "tltu";
4778 goto trap;
4779 case M_TNE_I:
4780 s = "tne";
4781 trap:
d8a1c247 4782 load_register (&icnt, AT, &imm_expr, 0);
0dd2d296 4783 macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT);
670a50eb 4784 break;
3d3c5039
ILT		 4785
4786 case M_TRUNCWD:
4787 case M_TRUNCWS:
8358c818 4788 assert (mips_isa < 2);
670a50eb
ILT		 4789 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
4790 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
4791
4792 /*
4793 * Is the double cfc1 instruction a bug in the mips assembler;
4794 * or is there a reason for it?
4795 */
becfe05e
ILT		 4796 mips_emit_delays ();
4797 ++mips_noreorder;
0dd2d296
ILT		 4798 mips_any_noreorder = 1;
4799 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
4800 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
4801 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
670a50eb 4802 expr1.X_add_number = 3;
0dd2d296 4803 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
9226253a 4804 (int) BFD_RELOC_LO16);
670a50eb 4805 expr1.X_add_number = 2;
0dd2d296 4806 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
9226253a 4807 (int) BFD_RELOC_LO16);
0dd2d296
ILT		 4808 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31);
4809 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
4810 macro_build ((char *) NULL, &icnt, NULL,
670a50eb 4811 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
0dd2d296
ILT		 4812 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31);
4813 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
becfe05e 4814 --mips_noreorder;
670a50eb 4815 break;
3d3c5039
ILT		 4816
4817 case M_ULH:
670a50eb
ILT		 4818 s = "lb";
4819 goto ulh;
3d3c5039 4820 case M_ULHU:
670a50eb 4821 s = "lbu";
3d3c5039 4822 ulh:
8ea7f4e8
ILT		 4823 if (offset_expr.X_add_number >= 0x7fff)
4824 as_bad ("operand overflow");
670a50eb 4825 /* avoid load delay */
8ea7f4e8
ILT		 4826 if (byte_order == LITTLE_ENDIAN)
4827 offset_expr.X_add_number += 1;
0dd2d296 4828 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
9226253a 4829 (int) BFD_RELOC_LO16, breg);
8ea7f4e8
ILT		 4830 if (byte_order == LITTLE_ENDIAN)
4831 offset_expr.X_add_number -= 1;
4832 else
4833 offset_expr.X_add_number += 1;
0dd2d296 4834 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
9226253a 4835 (int) BFD_RELOC_LO16, breg);
0dd2d296
ILT		 4836 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
4837 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
670a50eb 4838 break;
3d3c5039 4839
adcf2b9d
ILT		 4840 case M_ULD:
4841 s = "ldl";
4842 s2 = "ldr";
4843 off = 7;
4844 goto ulw;
3d3c5039 4845 case M_ULW:
adcf2b9d
ILT		 4846 s = "lwl";
4847 s2 = "lwr";
4848 off = 3;
4849 ulw:
4850 if (offset_expr.X_add_number >= 0x8000 - off)
8ea7f4e8
ILT		 4851 as_bad ("operand overflow");
4852 if (byte_order == LITTLE_ENDIAN)
adcf2b9d
ILT		 4853 offset_expr.X_add_number += off;
4854 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
9226253a 4855 (int) BFD_RELOC_LO16, breg);
8ea7f4e8 4856 if (byte_order == LITTLE_ENDIAN)
adcf2b9d 4857 offset_expr.X_add_number -= off;
8ea7f4e8 4858 else
adcf2b9d
ILT		 4859 offset_expr.X_add_number += off;
4860 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
9226253a 4861 (int) BFD_RELOC_LO16, breg);
670a50eb 4862 return;
3d3c5039 4863
adcf2b9d
ILT		 4864 case M_ULD_A:
4865 s = "ldl";
4866 s2 = "ldr";
4867 off = 7;
4868 goto ulwa;
4869 case M_ULW_A:
4870 s = "lwl";
4871 s2 = "lwr";
4872 off = 3;
4873 ulwa:
4874 load_address (&icnt, AT, &offset_expr);
c625fc23
JSC		 4875 if (breg != 0)
4876 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4877 mips_isa < 3 ? "addu" : "daddu",
4878 "d,v,t", AT, AT, breg);
adcf2b9d
ILT		 4879 if (byte_order == LITTLE_ENDIAN)
4880 expr1.X_add_number = off;
4881 else
4882 expr1.X_add_number = 0;
4883 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
4884 (int) BFD_RELOC_LO16, AT);
4885 if (byte_order == LITTLE_ENDIAN)
4886 expr1.X_add_number = 0;
4887 else
4888 expr1.X_add_number = off;
4889 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
4890 (int) BFD_RELOC_LO16, AT);
4891 break;
4892
3d3c5039
ILT		 4893 case M_ULH_A:
4894 case M_ULHU_A:
0dd2d296 4895 load_address (&icnt, AT, &offset_expr);
c625fc23
JSC		 4896 if (breg != 0)
4897 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4898 mips_isa < 3 ? "addu" : "daddu",
4899 "d,v,t", AT, AT, breg);
adcf2b9d
ILT		 4900 if (byte_order == BIG_ENDIAN)
4901 expr1.X_add_number = 0;
4902 macro_build ((char *) NULL, &icnt, &expr1,
4903 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
4904 (int) BFD_RELOC_LO16, AT);
4905 if (byte_order == BIG_ENDIAN)
4906 expr1.X_add_number = 1;
670a50eb 4907 else
adcf2b9d
ILT		 4908 expr1.X_add_number = 0;
4909 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
4910 (int) BFD_RELOC_LO16, AT);
4911 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
4912 treg, 8);
4913 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
4914 treg, AT);
670a50eb 4915 break;
3d3c5039
ILT		 4916
4917 case M_USH:
8ea7f4e8
ILT		 4918 if (offset_expr.X_add_number >= 0x7fff)
4919 as_bad ("operand overflow");
4920 if (byte_order == BIG_ENDIAN)
4921 offset_expr.X_add_number += 1;
0dd2d296 4922 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
9226253a 4923 (int) BFD_RELOC_LO16, breg);
0dd2d296 4924 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
8ea7f4e8
ILT		 4925 if (byte_order == BIG_ENDIAN)
4926 offset_expr.X_add_number -= 1;
4927 else
4928 offset_expr.X_add_number += 1;
0dd2d296 4929 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
9226253a 4930 (int) BFD_RELOC_LO16, breg);
670a50eb 4931 break;
3d3c5039 4932
adcf2b9d
ILT		 4933 case M_USD:
4934 s = "sdl";
4935 s2 = "sdr";
4936 off = 7;
4937 goto usw;
3d3c5039 4938 case M_USW:
adcf2b9d
ILT		 4939 s = "swl";
4940 s2 = "swr";
4941 off = 3;
4942 usw:
4943 if (offset_expr.X_add_number >= 0x8000 - off)
8ea7f4e8
ILT		 4944 as_bad ("operand overflow");
4945 if (byte_order == LITTLE_ENDIAN)
adcf2b9d
ILT		 4946 offset_expr.X_add_number += off;
4947 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
9226253a 4948 (int) BFD_RELOC_LO16, breg);
8ea7f4e8 4949 if (byte_order == LITTLE_ENDIAN)
adcf2b9d 4950 offset_expr.X_add_number -= off;
8ea7f4e8 4951 else
adcf2b9d
ILT		 4952 offset_expr.X_add_number += off;
4953 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
9226253a 4954 (int) BFD_RELOC_LO16, breg);
670a50eb 4955 return;
3d3c5039 4956
adcf2b9d
ILT		 4957 case M_USD_A:
4958 s = "sdl";
4959 s2 = "sdr";
4960 off = 7;
4961 goto uswa;
3d3c5039 4962 case M_USW_A:
adcf2b9d
ILT		 4963 s = "swl";
4964 s2 = "swr";
4965 off = 3;
4966 uswa:
0dd2d296 4967 load_address (&icnt, AT, &offset_expr);
c625fc23
JSC		 4968 if (breg != 0)
4969 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4970 mips_isa < 3 ? "addu" : "daddu",
4971 "d,v,t", AT, AT, breg);
adcf2b9d
ILT		 4972 if (byte_order == LITTLE_ENDIAN)
4973 expr1.X_add_number = off;
670a50eb 4974 else
adcf2b9d
ILT		 4975 expr1.X_add_number = 0;
4976 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
4977 (int) BFD_RELOC_LO16, AT);
4978 if (byte_order == LITTLE_ENDIAN)
4979 expr1.X_add_number = 0;
4980 else
4981 expr1.X_add_number = off;
4982 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
4983 (int) BFD_RELOC_LO16, AT);
4984 break;
4985
4986 case M_USH_A:
4987 load_address (&icnt, AT, &offset_expr);
c625fc23
JSC		 4988 if (breg != 0)
4989 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4990 mips_isa < 3 ? "addu" : "daddu",
4991 "d,v,t", AT, AT, breg);
adcf2b9d
ILT		 4992 if (byte_order == LITTLE_ENDIAN)
4993 expr1.X_add_number = 0;
4994 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
4995 (int) BFD_RELOC_LO16, AT);
4996 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg,
4997 treg, 8);
4998 if (byte_order == LITTLE_ENDIAN)
4999 expr1.X_add_number = 1;
5000 else
5001 expr1.X_add_number = 0;
5002 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
5003 (int) BFD_RELOC_LO16, AT);
5004 if (byte_order == LITTLE_ENDIAN)
5005 expr1.X_add_number = 0;
5006 else
5007 expr1.X_add_number = 1;
5008 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
5009 (int) BFD_RELOC_LO16, AT);
5010 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
5011 treg, 8);
5012 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
5013 treg, AT);
670a50eb 5014 break;
3d3c5039
ILT		 5015
5016 default:
670a50eb 5017 as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
8358c818 5018 break;
3d3c5039 5019 }
670a50eb
ILT		 5020 if (mips_noat)
5021 as_warn ("Macro used $at after \".set noat\"");
3d3c5039
ILT		 5022}
5023
867a58b3
ILT		 5024/* This routine assembles an instruction into its binary format. As a
5025 side effect, it sets one of the global variables imm_reloc or
5026 offset_reloc to the type of relocation to do if one of the operands
5027 is an address expression. */
3d3c5039 5028
3d3c5039
ILT		 5029static void
5030mips_ip (str, ip)
5031 char *str;
5032 struct mips_cl_insn *ip;
5033{
670a50eb
ILT		 5034 char *s;
5035 const char *args;
5036 char c;
5037 struct mips_opcode *insn;
5038 char *argsStart;
5039 unsigned int regno;
5040 unsigned int lastregno = 0;
5041 char *s_reset;
5042
5043 insn_error = NULL;
5044
c625fc23 5045 for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s)
670a50eb
ILT		 5046 continue;
5047 switch (*s)
5048 {
3d3c5039 5049 case '\0':
670a50eb 5050 break;
3d3c5039
ILT		 5051
5052 case ' ':
670a50eb
ILT		 5053 *s++ = '\0';
5054 break;
3d3c5039
ILT		 5055
5056 default:
460531da 5057 as_fatal ("Unknown opcode: `%s'", str);
3d3c5039 5058 }
670a50eb
ILT		 5059 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
5060 {
9753202d 5061 insn_error = "unrecognized opcode";
670a50eb 5062 return;
3d3c5039 5063 }
670a50eb
ILT		 5064 argsStart = s;
5065 for (;;)
5066 {
8358c818
ILT		 5067 int insn_isa;
5068
670a50eb 5069 assert (strcmp (insn->name, str) == 0);
8358c818
ILT		 5070
5071 if (insn->pinfo == INSN_MACRO)
5072 insn_isa = insn->match;
b2b8c24e 5073 else if ((insn->pinfo & INSN_ISA) == INSN_ISA2)
8358c818 5074 insn_isa = 2;
b2b8c24e 5075 else if ((insn->pinfo & INSN_ISA) == INSN_ISA3)
8358c818 5076 insn_isa = 3;
d8a1c247
KR		 5077 else if ((insn->pinfo & INSN_ISA) == INSN_ISA4)
5078 insn_isa = 4;
8358c818
ILT		 5079 else
5080 insn_isa = 1;
5081
b2b8c24e
ILT		 5082 if (insn_isa > mips_isa
5083 || ((insn->pinfo & INSN_ISA) == INSN_4650
e532b44c
ILT		 5084 && ! mips_4650)
5085 || ((insn->pinfo & INSN_ISA) == INSN_4010
c625fc23
JSC		 5086 && ! mips_4010)
5087 || ((insn->pinfo & INSN_ISA) == INSN_4100
5088 && ! mips_4100))
8358c818
ILT		 5089 {
5090 if (insn + 1 < &mips_opcodes[NUMOPCODES]
5091 && strcmp (insn->name, insn[1].name) == 0)
5092 {
5093 ++insn;
5094 continue;
5095 }
9753202d
ILT		 5096 insn_error = "opcode not supported on this processor";
5097 return;
8358c818
ILT		 5098 }
5099
670a50eb
ILT		 5100 ip->insn_mo = insn;
5101 ip->insn_opcode = insn->match;
5102 for (args = insn->args;; ++args)
5103 {
5104 if (*s == ' ')
5105 ++s;
5106 switch (*args)
5107 {
5108 case '\0': /* end of args */
5109 if (*s == '\0')
5110 return;
5111 break;
3d3c5039
ILT		 5112
5113 case ',':
670a50eb
ILT		 5114 if (*s++ == *args)
5115 continue;
5116 s--;
5117 switch (*++args)
5118 {
3d3c5039
ILT		 5119 case 'r':
5120 case 'v':
670a50eb
ILT		 5121 ip->insn_opcode |= lastregno << 21;
5122 continue;
3d3c5039
ILT		 5123
5124 case 'w':
5125 case 'W':
670a50eb
ILT		 5126 ip->insn_opcode |= lastregno << 16;
5127 continue;
3d3c5039
ILT		 5128
5129 case 'V':
670a50eb
ILT		 5130 ip->insn_opcode |= lastregno << 11;
5131 continue;
3d3c5039 5132 }
670a50eb 5133 break;
3d3c5039
ILT		 5134
5135 case '(':
670a50eb
ILT		 5136 /* handle optional base register.
5137 Either the base register is omitted or
5138 we must have a left paren. */
5139 /* this is dependent on the next operand specifier
5140 is a 'b' for base register */
5141 assert (args[1] == 'b');
5142 if (*s == '\0')
5143 return;
3d3c5039 5144
670a50eb
ILT		 5145 case ')': /* these must match exactly */
5146 if (*s++ == *args)
3d3c5039 5147 continue;
670a50eb
ILT		 5148 break;
5149
5150 case '<': /* must be at least one digit */
5151 /*
5152 * According to the manual, if the shift amount is greater
5153 * than 31 or less than 0 the the shift amount should be
5154 * mod 32. In reality the mips assembler issues an error.
9226253a 5155 * We issue a warning and mask out all but the low 5 bits.
670a50eb
ILT		 5156 */
5157 my_getExpression (&imm_expr, s);
5158 check_absolute_expr (ip, &imm_expr);
5159 if ((unsigned long) imm_expr.X_add_number > 31)
5160 {
58d4951d
ILT		 5161 as_warn ("Improper shift amount (%ld)",
5162 (long) imm_expr.X_add_number);
9226253a 5163 imm_expr.X_add_number = imm_expr.X_add_number & 0x1f;
670a50eb
ILT		 5164 }
5165 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 5166 imm_expr.X_op = O_absent;
670a50eb
ILT		 5167 s = expr_end;
5168 continue;
5169
56c96faa
ILT		 5170 case '>': /* shift amount minus 32 */
5171 my_getExpression (&imm_expr, s);
5172 check_absolute_expr (ip, &imm_expr);
5173 if ((unsigned long) imm_expr.X_add_number < 32
5174 || (unsigned long) imm_expr.X_add_number > 63)
5175 break;
5176 ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6;
5177 imm_expr.X_op = O_absent;
5178 s = expr_end;
5179 continue;
5180
9226253a 5181 case 'k': /* cache code */
d8a1c247 5182 case 'h': /* prefx code */
9226253a
ILT		 5183 my_getExpression (&imm_expr, s);
5184 check_absolute_expr (ip, &imm_expr);
5185 if ((unsigned long) imm_expr.X_add_number > 31)
5186 {
d8a1c247
KR		 5187 as_warn ("Invalid value for `%s' (%lu)",
5188 ip->insn_mo->name,
9226253a
ILT		 5189 (unsigned long) imm_expr.X_add_number);
5190 imm_expr.X_add_number &= 0x1f;
5191 }
d8a1c247
KR		 5192 if (*args == 'k')
5193 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
5194 else
5195 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
9226253a
ILT		 5196 imm_expr.X_op = O_absent;
5197 s = expr_end;
5198 continue;
5199
670a50eb
ILT		 5200 case 'c': /* break code */
5201 my_getExpression (&imm_expr, s);
5202 check_absolute_expr (ip, &imm_expr);
5203 if ((unsigned) imm_expr.X_add_number > 1023)
58d4951d
ILT		 5204 as_warn ("Illegal break code (%ld)",
5205 (long) imm_expr.X_add_number);
670a50eb 5206 ip->insn_opcode |= imm_expr.X_add_number << 16;
5ac34ac3 5207 imm_expr.X_op = O_absent;
670a50eb
ILT		 5208 s = expr_end;
5209 continue;
5210
918692a5
ILT		 5211 case 'B': /* syscall code */
5212 my_getExpression (&imm_expr, s);
5213 check_absolute_expr (ip, &imm_expr);
5214 if ((unsigned) imm_expr.X_add_number > 0xfffff)
58d4951d
ILT		 5215 as_warn ("Illegal syscall code (%ld)",
5216 (long) imm_expr.X_add_number);
918692a5 5217 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 5218 imm_expr.X_op = O_absent;
918692a5
ILT		 5219 s = expr_end;
5220 continue;
5221
0aa07269
ILT		 5222 case 'C': /* Coprocessor code */
5223 my_getExpression (&imm_expr, s);
5224 check_absolute_expr (ip, &imm_expr);
5225 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
5226 {
58d4951d
ILT		 5227 as_warn ("Coproccesor code > 25 bits (%ld)",
5228 (long) imm_expr.X_add_number);
0aa07269
ILT		 5229 imm_expr.X_add_number &= ((1<<25) - 1);
5230 }
5231 ip->insn_opcode |= imm_expr.X_add_number;
5232 imm_expr.X_op = O_absent;
5233 s = expr_end;
5234 continue;
5235
670a50eb
ILT		 5236 case 'b': /* base register */
5237 case 'd': /* destination register */
5238 case 's': /* source register */
5239 case 't': /* target register */
5240 case 'r': /* both target and source */
5241 case 'v': /* both dest and source */
5242 case 'w': /* both dest and target */
918692a5
ILT		 5243 case 'E': /* coprocessor target register */
5244 case 'G': /* coprocessor destination register */
8358c818 5245 case 'x': /* ignore register name */
ff3a5c18 5246 case 'z': /* must be zero register */
670a50eb
ILT		 5247 s_reset = s;
5248 if (s[0] == '$')
5249 {
5250 if (isdigit (s[1]))
5251 {
5252 ++s;
5253 regno = 0;
5254 do
5255 {
5256 regno *= 10;
5257 regno += *s - '0';
5258 ++s;
5259 }
5260 while (isdigit (*s));
0aa07269
ILT		 5261 if (regno > 31)
5262 as_bad ("Invalid register number (%d)", regno);
670a50eb 5263 }
0dd2d296
ILT		 5264 else if (*args == 'E' || *args == 'G')
5265 goto notreg;
5266 else
670a50eb 5267 {
0aa07269
ILT		 5268 if (s[1] == 'f' && s[2] == 'p')
5269 {
5270 s += 3;
9226253a 5271 regno = FP;
0aa07269
ILT		 5272 }
5273 else if (s[1] == 's' && s[2] == 'p')
5274 {
5275 s += 3;
9226253a 5276 regno = SP;
0aa07269
ILT		 5277 }
5278 else if (s[1] == 'g' && s[2] == 'p')
5279 {
5280 s += 3;
9226253a 5281 regno = GP;
0aa07269
ILT		 5282 }
5283 else if (s[1] == 'a' && s[2] == 't')
5284 {
5285 s += 3;
9226253a 5286 regno = AT;
0aa07269 5287 }
b2b8c24e
ILT		 5288 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
5289 {
5290 s += 4;
5291 regno = KT0;
5292 }
5293 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
5294 {
5295 s += 4;
5296 regno = KT1;
5297 }
0aa07269
ILT		 5298 else
5299 goto notreg;
670a50eb 5300 }
9753202d
ILT		 5301 if (regno == AT
5302 && ! mips_noat
5303 && *args != 'E'
5304 && *args != 'G')
13fe1379 5305 as_warn ("Used $at without \".set noat\"");
670a50eb
ILT		 5306 c = *args;
5307 if (*s == ' ')
5308 s++;
5309 if (args[1] != *s)
5310 {
5311 if (c == 'r' || c == 'v' || c == 'w')
5312 {
5313 regno = lastregno;
5314 s = s_reset;
5315 args++;
5316 }
5317 }
ff3a5c18
ILT		 5318 /* 'z' only matches $0. */
5319 if (c == 'z' && regno != 0)
5320 break;
670a50eb
ILT		 5321 switch (c)
5322 {
3d3c5039
ILT		 5323 case 'r':
5324 case 's':
5325 case 'v':
5326 case 'b':
670a50eb
ILT		 5327 ip->insn_opcode |= regno << 21;
5328 break;
3d3c5039 5329 case 'd':
918692a5 5330 case 'G':
670a50eb
ILT		 5331 ip->insn_opcode |= regno << 11;
5332 break;
3d3c5039
ILT		 5333 case 'w':
5334 case 't':
918692a5 5335 case 'E':
670a50eb 5336 ip->insn_opcode |= regno << 16;
8358c818
ILT		 5337 break;
5338 case 'x':
5339 /* This case exists because on the r3000 trunc
5340 expands into a macro which requires a gp
5341 register. On the r6000 or r4000 it is
5342 assembled into a single instruction which
5343 ignores the register. Thus the insn version
5344 is MIPS_ISA2 and uses 'x', and the macro
5345 version is MIPS_ISA1 and uses 't'. */
5346 break;
ff3a5c18
ILT		 5347 case 'z':
5348 /* This case is for the div instruction, which
5349 acts differently if the destination argument
5350 is $0. This only matches $0, and is checked
5351 outside the switch. */
5352 break;
3d3c5039 5353 }
670a50eb
ILT		 5354 lastregno = regno;
5355 continue;
3d3c5039
ILT		 5356 }
5357 notreg:
670a50eb
ILT		 5358 switch (*args++)
5359 {
3d3c5039
ILT		 5360 case 'r':
5361 case 'v':
670a50eb
ILT		 5362 ip->insn_opcode |= lastregno << 21;
5363 continue;
3d3c5039 5364 case 'w':
670a50eb
ILT		 5365 ip->insn_opcode |= lastregno << 16;
5366 continue;
3d3c5039 5367 }
670a50eb 5368 break;
3d3c5039 5369
670a50eb
ILT		 5370 case 'D': /* floating point destination register */
5371 case 'S': /* floating point source register */
5372 case 'T': /* floating point target register */
d8a1c247 5373 case 'R': /* floating point source register */
3d3c5039
ILT		 5374 case 'V':
5375 case 'W':
670a50eb
ILT		 5376 s_reset = s;
5377 if (s[0] == '$' && s[1] == 'f' && isdigit (s[2]))
5378 {
5379 s += 2;
5380 regno = 0;
5381 do
5382 {
5383 regno *= 10;
5384 regno += *s - '0';
5385 ++s;
5386 }
5387 while (isdigit (*s));
5388
5389 if (regno > 31)
5390 as_bad ("Invalid float register number (%d)", regno);
5391
9226253a
ILT		 5392 if ((regno & 1) != 0
5393 && mips_isa < 3
5394 && ! (strcmp (str, "mtc1") == 0 ||
5395 strcmp (str, "mfc1") == 0 ||
5396 strcmp (str, "lwc1") == 0 ||
5397 strcmp (str, "swc1") == 0))
670a50eb
ILT		 5398 as_warn ("Float register should be even, was %d",
5399 regno);
5400
5401 c = *args;
5402 if (*s == ' ')
5403 s++;
5404 if (args[1] != *s)
5405 {
5406 if (c == 'V' || c == 'W')
5407 {
5408 regno = lastregno;
5409 s = s_reset;
5410 args++;
3d3c5039
ILT		 5411 }
5412 }
670a50eb
ILT		 5413 switch (c)
5414 {
3d3c5039 5415 case 'D':
670a50eb
ILT		 5416 ip->insn_opcode |= regno << 6;
5417 break;
3d3c5039
ILT		 5418 case 'V':
5419 case 'S':
670a50eb
ILT		 5420 ip->insn_opcode |= regno << 11;
5421 break;
3d3c5039
ILT		 5422 case 'W':
5423 case 'T':
670a50eb 5424 ip->insn_opcode |= regno << 16;
d8a1c247
KR		 5425 break;
5426 case 'R':
5427 ip->insn_opcode |= regno << 21;
5428 break;
3d3c5039 5429 }
670a50eb
ILT		 5430 lastregno = regno;
5431 continue;
3d3c5039 5432 }
670a50eb
ILT		 5433 switch (*args++)
5434 {
3d3c5039 5435 case 'V':
670a50eb
ILT		 5436 ip->insn_opcode |= lastregno << 11;
5437 continue;
3d3c5039 5438 case 'W':
670a50eb
ILT		 5439 ip->insn_opcode |= lastregno << 16;
5440 continue;
3d3c5039 5441 }
670a50eb 5442 break;
3d3c5039
ILT		 5443
5444 case 'I':
670a50eb 5445 my_getExpression (&imm_expr, s);
9753202d
ILT		 5446 if (imm_expr.X_op != O_big
5447 && imm_expr.X_op != O_constant)
5448 insn_error = "absolute expression required";
670a50eb
ILT		 5449 s = expr_end;
5450 continue;
3d3c5039
ILT		 5451
5452 case 'A':
670a50eb
ILT		 5453 my_getExpression (&offset_expr, s);
5454 imm_reloc = BFD_RELOC_32;
5455 s = expr_end;
5456 continue;
3d3c5039
ILT		 5457
5458 case 'F':
19ed8960
ILT		 5459 case 'L':
5460 case 'f':
5461 case 'l':
5462 {
5463 int f64;
5464 char *save_in;
5465 char *err;
5466 unsigned char temp[8];
604633ae
ILT		 5467 int len;
5468 unsigned int length;
19ed8960
ILT		 5469 segT seg;
5470 subsegT subseg;
5471 char *p;
5472
5473 /* These only appear as the last operand in an
5474 instruction, and every instruction that accepts
5475 them in any variant accepts them in all variants.
5476 This means we don't have to worry about backing out
5477 any changes if the instruction does not match.
5478
5479 The difference between them is the size of the
5480 floating point constant and where it goes. For 'F'
5481 and 'L' the constant is 64 bits; for 'f' and 'l' it
5482 is 32 bits. Where the constant is placed is based
5483 on how the MIPS assembler does things:
5484 F -- .rdata
5485 L -- .lit8
5486 f -- immediate value
5487 l -- .lit4
0dd2d296 5488
55933a58
ILT		 5489 The .lit4 and .lit8 sections are only used if
5490 permitted by the -G argument.
5491
5492 When generating embedded PIC code, we use the
5493 .lit8 section but not the .lit4 section (we can do
5494 .lit4 inline easily; we need to put .lit8
5495 somewhere in the data segment, and using .lit8
5496 permits the linker to eventually combine identical
5497 .lit8 entries). */
19ed8960
ILT		 5498
5499 f64 = *args == 'F' || *args == 'L';
5500
5501 save_in = input_line_pointer;
5502 input_line_pointer = s;
604633ae
ILT		 5503 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
5504 length = len;
19ed8960
ILT		 5505 s = input_line_pointer;
5506 input_line_pointer = save_in;
5507 if (err != NULL && *err != '\0')
5508 {
5509 as_bad ("Bad floating point constant: %s", err);
5510 memset (temp, '\0', sizeof temp);
5511 length = f64 ? 8 : 4;
5512 }
5513
5514 assert (length == (f64 ? 8 : 4));
5515
0dd2d296 5516 if (*args == 'f'
55933a58 5517 || (*args == 'l'
1dc1e798
KR		 5518 && (! USE_GLOBAL_POINTER_OPT
5519 || mips_pic == EMBEDDED_PIC
1113140a 5520 || g_switch_value < 4)
1113140a 5521 ))
19ed8960
ILT		 5522 {
5523 imm_expr.X_op = O_constant;
5524 if (byte_order == LITTLE_ENDIAN)
5525 imm_expr.X_add_number =
5526 (((((((int) temp[3] << 8)
5527 | temp[2]) << 8)
5528 | temp[1]) << 8)
5529 | temp[0]);
5530 else
5531 imm_expr.X_add_number =
5532 (((((((int) temp[0] << 8)
5533 | temp[1]) << 8)
5534 | temp[2]) << 8)
5535 | temp[3]);
5536 }
5537 else
5538 {
0dd2d296
ILT		 5539 const char *newname;
5540 segT new_seg;
5541
19ed8960
ILT		 5542 /* Switch to the right section. */
5543 seg = now_seg;
5544 subseg = now_subseg;
5545 switch (*args)
5546 {
0dd2d296 5547 default: /* unused default case avoids warnings. */
19ed8960 5548 case 'L':
1113140a 5549 newname = RDATA_SECTION_NAME;
1dc1e798 5550 if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
1113140a 5551 newname = ".lit8";
0dd2d296
ILT		 5552 break;
5553 case 'F':
d2c71068 5554 newname = RDATA_SECTION_NAME;
19ed8960
ILT		 5555 break;
5556 case 'l':
1dc1e798
KR		 5557 assert (!USE_GLOBAL_POINTER_OPT
5558 || g_switch_value >= 4);
0dd2d296 5559 newname = ".lit4";
19ed8960
ILT		 5560 break;
5561 }
0dd2d296 5562 new_seg = subseg_new (newname, (subsegT) 0);
9b61d62b
ILT		 5563 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
5564 bfd_set_section_flags (stdoutput, new_seg,
5565 (SEC_ALLOC
5566 | SEC_LOAD
5567 | SEC_READONLY
5568 | SEC_DATA));
0221ddf7 5569 frag_align (*args == 'l' ? 2 : 3, 0);
1dc1e798
KR		 5570 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
5571 record_alignment (new_seg, 4);
5572 else
5573 record_alignment (new_seg, *args == 'l' ? 2 : 3);
19ed8960
ILT		 5574 if (seg == now_seg)
5575 as_bad ("Can't use floating point insn in this section");
5576
5577 /* Set the argument to the current address in the
6e8dda9c 5578 section. */
19ed8960
ILT		 5579 offset_expr.X_op = O_symbol;
5580 offset_expr.X_add_symbol =
5581 symbol_new ("L0\001", now_seg,
5582 (valueT) frag_now_fix (), frag_now);
5583 offset_expr.X_add_number = 0;
5584
5585 /* Put the floating point number into the section. */
604633ae 5586 p = frag_more ((int) length);
19ed8960
ILT		 5587 memcpy (p, temp, length);
5588
5589 /* Switch back to the original section. */
5590 subseg_set (seg, subseg);
5591 }
5592 }
670a50eb
ILT		 5593 continue;
5594
5595 case 'i': /* 16 bit unsigned immediate */
5596 case 'j': /* 16 bit signed immediate */
5597 imm_reloc = BFD_RELOC_LO16;
5598 c = my_getSmallExpression (&imm_expr, s);
344a8d61 5599 if (c != '\0')
670a50eb
ILT		 5600 {
5601 if (c != 'l')
5602 {
5ac34ac3 5603 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 5604 imm_expr.X_add_number =
5605 (imm_expr.X_add_number >> 16) & 0xffff;
5606 else if (c == 'h')
867a58b3
ILT		 5607 {
5608 imm_reloc = BFD_RELOC_HI16_S;
5609 imm_unmatched_hi = true;
5610 }
670a50eb
ILT		 5611 else
5612 imm_reloc = BFD_RELOC_HI16;
3d3c5039 5613 }
670a50eb 5614 }
670a50eb
ILT		 5615 if (*args == 'i')
5616 {
344a8d61 5617 if ((c == '\0' && imm_expr.X_op != O_constant)
a8aed9dd
ILT		 5618 || ((imm_expr.X_add_number < 0
5619 || imm_expr.X_add_number >= 0x10000)
5620 && imm_expr.X_op == O_constant))
99c24539
ILT		 5621 {
5622 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
5623 !strcmp (insn->name, insn[1].name))
5624 break;
9753202d
ILT		 5625 if (imm_expr.X_op != O_constant
5626 && imm_expr.X_op != O_big)
5627 insn_error = "absolute expression required";
5628 else
5629 as_bad ("16 bit expression not in range 0..65535");
99c24539 5630 }
670a50eb
ILT		 5631 }
5632 else
5633 {
d9aba805
ILT		 5634 int more;
5635 offsetT max;
5636
be22008b
ILT		 5637 /* The upper bound should be 0x8000, but
5638 unfortunately the MIPS assembler accepts numbers
5639 from 0x8000 to 0xffff and sign extends them, and
d9aba805
ILT		 5640 we want to be compatible. We only permit this
5641 extended range for an instruction which does not
5642 provide any further alternates, since those
5643 alternates may handle other cases. People should
5644 use the numbers they mean, rather than relying on
5645 a mysterious sign extension. */
5646 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
5647 strcmp (insn->name, insn[1].name) == 0);
5648 if (more)
5649 max = 0x8000;
5650 else
5651 max = 0x10000;
344a8d61 5652 if ((c == '\0' && imm_expr.X_op != O_constant)
a8aed9dd
ILT		 5653 || ((imm_expr.X_add_number < -0x8000
5654 || imm_expr.X_add_number >= max)
5655 && imm_expr.X_op == O_constant)
d8a1c247
KR		 5656 || (more
5657 && imm_expr.X_add_number < 0
5658 && mips_isa >= 3
5659 && imm_expr.X_unsigned
5660 && sizeof (imm_expr.X_add_number) <= 4))
99c24539 5661 {
d9aba805 5662 if (more)
99c24539 5663 break;
9753202d
ILT		 5664 if (imm_expr.X_op != O_constant
5665 && imm_expr.X_op != O_big)
5666 insn_error = "absolute expression required";
5667 else
5668 as_bad ("16 bit expression not in range -32768..32767");
99c24539 5669 }
3d3c5039 5670 }
670a50eb
ILT		 5671 s = expr_end;
5672 continue;
5673
5674 case 'o': /* 16 bit offset */
5675 c = my_getSmallExpression (&offset_expr, s);
f3645945
ILT		 5676
5677 /* If this value won't fit into a 16 bit offset, then go
5678 find a macro that will generate the 32 bit offset
5679 code pattern. As a special hack, we accept the
5680 difference of two local symbols as a constant. This
5681 is required to suppose embedded PIC switches, which
5682 use an instruction which looks like
5683 lw $4,$L12-$LS12($4)
5684 The problem with handling this in a more general
5685 fashion is that the macro function doesn't expect to
5686 see anything which can be handled in a single
5687 constant instruction. */
6f0b87c3
SS		 5688 if (c == 0
5689 && (offset_expr.X_op != O_constant
5690 || offset_expr.X_add_number >= 0x8000
5691 || offset_expr.X_add_number < -0x8000)
f3645945
ILT		 5692 && (mips_pic != EMBEDDED_PIC
5693 || offset_expr.X_op != O_subtract
9da4c5d1
ILT		 5694 || now_seg != text_section
5695 || (S_GET_SEGMENT (offset_expr.X_op_symbol)
5696 != text_section)))
670a50eb 5697 break;
3d3c5039 5698
670a50eb
ILT		 5699 offset_reloc = BFD_RELOC_LO16;
5700 if (c == 'h' || c == 'H')
6e8dda9c
ILT		 5701 {
5702 assert (offset_expr.X_op == O_constant);
5703 offset_expr.X_add_number =
5704 (offset_expr.X_add_number >> 16) & 0xffff;
5705 }
670a50eb
ILT		 5706 s = expr_end;
5707 continue;
5708
5709 case 'p': /* pc relative offset */
5710 offset_reloc = BFD_RELOC_16_PCREL_S2;
5711 my_getExpression (&offset_expr, s);
5712 s = expr_end;
5713 continue;
5714
5715 case 'u': /* upper 16 bits */
5716 c = my_getSmallExpression (&imm_expr, s);
36a87ad7
ILT		 5717 if (imm_expr.X_op == O_constant
5718 && (imm_expr.X_add_number < 0
5719 || imm_expr.X_add_number >= 0x10000))
670a50eb
ILT		 5720 as_bad ("lui expression not in range 0..65535");
5721 imm_reloc = BFD_RELOC_LO16;
5722 if (c)
5723 {
5724 if (c != 'l')
5725 {
5ac34ac3 5726 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 5727 imm_expr.X_add_number =
5728 (imm_expr.X_add_number >> 16) & 0xffff;
5729 else if (c == 'h')
867a58b3
ILT		 5730 {
5731 imm_reloc = BFD_RELOC_HI16_S;
5732 imm_unmatched_hi = true;
5733 }
670a50eb
ILT		 5734 else
5735 imm_reloc = BFD_RELOC_HI16;
3d3c5039
ILT		 5736 }
5737 }
670a50eb
ILT		 5738 s = expr_end;
5739 continue;
3d3c5039 5740
670a50eb
ILT		 5741 case 'a': /* 26 bit address */
5742 my_getExpression (&offset_expr, s);
5743 s = expr_end;
5744 offset_reloc = BFD_RELOC_MIPS_JMP;
5745 continue;
3d3c5039 5746
d8a1c247
KR		 5747 case 'N': /* 3 bit branch condition code */
5748 case 'M': /* 3 bit compare condition code */
5749 my_getExpression (&imm_expr, s);
5750 check_absolute_expr (ip, &imm_expr);
5751 if ((unsigned long) imm_expr.X_add_number > 7)
5752 {
5753 as_warn ("Condition code > 7 (%ld)",
5754 (long) imm_expr.X_add_number);
5755 imm_expr.X_add_number &= 7;
5756 }
5757 if (*args == 'N')
5758 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_BCC;
5759 else
5760 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CCC;
5761 imm_expr.X_op = O_absent;
5762 s = expr_end;
5763 continue;
5764
3d3c5039 5765 default:
670a50eb
ILT		 5766 fprintf (stderr, "bad char = '%c'\n", *args);
5767 internalError ();
3d3c5039 5768 }
670a50eb 5769 break;
3d3c5039 5770 }
670a50eb
ILT		 5771 /* Args don't match. */
5772 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
5773 !strcmp (insn->name, insn[1].name))
5774 {
5775 ++insn;
5776 s = argsStart;
5777 continue;
3d3c5039 5778 }
9753202d 5779 insn_error = "illegal operands";
670a50eb 5780 return;
3d3c5039
ILT		 5781 }
5782}
5783
5784#define LP '('
5785#define RP ')'
5786
5787static int
5788my_getSmallExpression (ep, str)
670a50eb
ILT		 5789 expressionS *ep;
5790 char *str;
3d3c5039 5791{
670a50eb
ILT		 5792 char *sp;
5793 int c = 0;
5794
5795 if (*str == ' ')
5796 str++;
5797 if (*str == LP
5798 || (*str == '%' &&
5799 ((str[1] == 'h' && str[2] == 'i')
5800 || (str[1] == 'H' && str[2] == 'I')
5801 || (str[1] == 'l' && str[2] == 'o'))
5802 && str[3] == LP))
5803 {
5804 if (*str == LP)
5805 c = 0;
5806 else
5807 {
5808 c = str[1];
5809 str += 3;
5810 }
5811
5812 /*
5813 * A small expression may be followed by a base register.
5814 * Scan to the end of this operand, and then back over a possible
5815 * base register. Then scan the small expression up to that
5816 * point. (Based on code in sparc.c...)
5817 */
5818 for (sp = str; *sp && *sp != ','; sp++)
5819 ;
5820 if (sp - 4 >= str && sp[-1] == RP)
5821 {
5822 if (isdigit (sp[-2]))
5823 {
5824 for (sp -= 3; sp >= str && isdigit (*sp); sp--)
5825 ;
5826 if (*sp == '$' && sp > str && sp[-1] == LP)
5827 {
5828 sp--;
5829 goto do_it;
3d3c5039 5830 }
670a50eb
ILT		 5831 }
5832 else if (sp - 5 >= str
5833 && sp[-5] == LP
5834 && sp[-4] == '$'
5835 && ((sp[-3] == 'f' && sp[-2] == 'p')
5836 || (sp[-3] == 's' && sp[-2] == 'p')
5837 || (sp[-3] == 'g' && sp[-2] == 'p')
5838 || (sp[-3] == 'a' && sp[-2] == 't')))
5839 {
5840 sp -= 5;
3d3c5039 5841 do_it:
670a50eb
ILT		 5842 if (sp == str)
5843 {
5844 /* no expression means zero offset */
5845 if (c)
5846 {
5847 /* %xx(reg) is an error */
5ac34ac3 5848 ep->X_op = O_absent;
670a50eb 5849 expr_end = str - 3;
3d3c5039 5850 }
670a50eb
ILT		 5851 else
5852 {
52aa70b5 5853 ep->X_op = O_constant;
670a50eb
ILT		 5854 expr_end = sp;
5855 }
5856 ep->X_add_symbol = NULL;
5ac34ac3 5857 ep->X_op_symbol = NULL;
670a50eb
ILT		 5858 ep->X_add_number = 0;
5859 }
5860 else
5861 {
5862 *sp = '\0';
5863 my_getExpression (ep, str);
5864 *sp = LP;
3d3c5039 5865 }
670a50eb 5866 return c;
3d3c5039
ILT		 5867 }
5868 }
5869 }
670a50eb
ILT		 5870 my_getExpression (ep, str);
5871 return c; /* => %hi or %lo encountered */
3d3c5039
ILT		 5872}
5873
5874static void
5875my_getExpression (ep, str)
670a50eb
ILT		 5876 expressionS *ep;
5877 char *str;
3d3c5039 5878{
670a50eb 5879 char *save_in;
670a50eb
ILT		 5880
5881 save_in = input_line_pointer;
5882 input_line_pointer = str;
5ac34ac3 5883 expression (ep);
670a50eb
ILT		 5884 expr_end = input_line_pointer;
5885 input_line_pointer = save_in;
3d3c5039
ILT		 5886}
5887
becfe05e
ILT		 5888/* Turn a string in input_line_pointer into a floating point constant
5889 of type type, and store the appropriate bytes in *litP. The number
5890 of LITTLENUMS emitted is stored in *sizeP . An error message is
5891 returned, or NULL on OK. */
5892
3d3c5039 5893char *
670a50eb 5894md_atof (type, litP, sizeP)
becfe05e 5895 int type;
3d3c5039
ILT		 5896 char *litP;
5897 int *sizeP;
5898{
becfe05e
ILT		 5899 int prec;
5900 LITTLENUM_TYPE words[4];
5901 char *t;
5902 int i;
5903
5904 switch (type)
5905 {
5906 case 'f':
5907 prec = 2;
5908 break;
5909
5910 case 'd':
5911 prec = 4;
5912 break;
5913
5914 default:
5915 *sizeP = 0;
5916 return "bad call to md_atof";
5917 }
5918
5919 t = atof_ieee (input_line_pointer, type, words);
5920 if (t)
5921 input_line_pointer = t;
5922
5923 *sizeP = prec * 2;
5924
5925 if (byte_order == LITTLE_ENDIAN)
5926 {
5927 for (i = prec - 1; i >= 0; i--)
5928 {
5929 md_number_to_chars (litP, (valueT) words[i], 2);
5930 litP += 2;
5931 }
5932 }
5933 else
5934 {
5935 for (i = 0; i < prec; i++)
5936 {
5937 md_number_to_chars (litP, (valueT) words[i], 2);
5938 litP += 2;
5939 }
5940 }
5941
670a50eb 5942 return NULL;
3d3c5039
ILT		 5943}
5944
5945void
5946md_number_to_chars (buf, val, n)
5947 char *buf;
918692a5 5948 valueT val;
3d3c5039
ILT		 5949 int n;
5950{
670a50eb
ILT		 5951 switch (byte_order)
5952 {
3d3c5039 5953 case LITTLE_ENDIAN:
13fe1379
ILT		 5954 number_to_chars_littleendian (buf, val, n);
5955 break;
3d3c5039
ILT		 5956
5957 case BIG_ENDIAN:
13fe1379
ILT		 5958 number_to_chars_bigendian (buf, val, n);
5959 break;
3d3c5039
ILT		 5960
5961 default:
670a50eb 5962 internalError ();
3d3c5039
ILT		 5963 }
5964}
f3d817d8 5965\f
e8d4d475 5966CONST char *md_shortopts = "O::g::G:";
1dc1e798 5967
f3d817d8
DM		 5968struct option md_longopts[] = {
5969#define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5970 {"mips0", no_argument, NULL, OPTION_MIPS1},
5971 {"mips1", no_argument, NULL, OPTION_MIPS1},
5972#define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5973 {"mips2", no_argument, NULL, OPTION_MIPS2},
5974#define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5975 {"mips3", no_argument, NULL, OPTION_MIPS3},
d8a1c247
KR		 5976#define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5977 {"mips4", no_argument, NULL, OPTION_MIPS4},
5978#define OPTION_MCPU (OPTION_MD_BASE + 5)
f3d817d8 5979 {"mcpu", required_argument, NULL, OPTION_MCPU},
d8a1c247 5980#define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
f3d817d8 5981 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
d8a1c247 5982#define OPTION_TRAP (OPTION_MD_BASE + 9)
f3d817d8
DM		 5983 {"trap", no_argument, NULL, OPTION_TRAP},
5984 {"no-break", no_argument, NULL, OPTION_TRAP},
d8a1c247 5985#define OPTION_BREAK (OPTION_MD_BASE + 10)
f3d817d8
DM		 5986 {"break", no_argument, NULL, OPTION_BREAK},
5987 {"no-trap", no_argument, NULL, OPTION_BREAK},
d8a1c247 5988#define OPTION_EB (OPTION_MD_BASE + 11)
e8d4d475 5989 {"EB", no_argument, NULL, OPTION_EB},
d8a1c247 5990#define OPTION_EL (OPTION_MD_BASE + 12)
e8d4d475 5991 {"EL", no_argument, NULL, OPTION_EL},
d8a1c247 5992#define OPTION_M4650 (OPTION_MD_BASE + 13)
b2b8c24e 5993 {"m4650", no_argument, NULL, OPTION_M4650},
d8a1c247 5994#define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
b2b8c24e 5995 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
e532b44c
ILT		 5996#define OPTION_M4010 (OPTION_MD_BASE + 15)
5997 {"m4010", no_argument, NULL, OPTION_M4010},
5998#define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5999 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
c625fc23
JSC		 6000#define OPTION_M4100 (OPTION_MD_BASE + 17)
6001 {"m4100", no_argument, NULL, OPTION_M4100},
6002#define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6003 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
f3d817d8 6004
d8a1c247 6005#define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
1dc1e798 6006#define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
fb251650 6007#define OPTION_XGOT (OPTION_MD_BASE + 19)
7f9880e5
ILT		 6008#define OPTION_32 (OPTION_MD_BASE + 20)
6009#define OPTION_64 (OPTION_MD_BASE + 21)
1dc1e798 6010#ifdef OBJ_ELF
f3d817d8 6011 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
fb251650 6012 {"xgot", no_argument, NULL, OPTION_XGOT},
f3d817d8 6013 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
f3d817d8 6014 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
7f9880e5
ILT		 6015 {"32", no_argument, NULL, OPTION_32},
6016 {"64", no_argument, NULL, OPTION_64},
f3d817d8
DM		 6017#endif
6018
6019 {NULL, no_argument, NULL, 0}
6020};
6021size_t md_longopts_size = sizeof(md_longopts);
3d3c5039
ILT		 6022
6023int
f3d817d8
DM		 6024md_parse_option (c, arg)
6025 int c;
6026 char *arg;
3d3c5039 6027{
f3d817d8 6028 switch (c)
670a50eb 6029 {
f3d817d8
DM		 6030 case OPTION_TRAP:
6031 mips_trap = 1;
6032 break;
670a50eb 6033
f3d817d8
DM		 6034 case OPTION_BREAK:
6035 mips_trap = 0;
6036 break;
6037
e8d4d475 6038 case OPTION_EB:
1dc1e798 6039 target_big_endian = 1;
e8d4d475 6040 break;
04cb3372 6041
e8d4d475 6042 case OPTION_EL:
1dc1e798 6043 target_big_endian = 0;
f3d817d8 6044 break;
670a50eb 6045
f3d817d8
DM		 6046 case 'O':
6047 if (arg && arg[1] == '0')
0aa07269
ILT		 6048 mips_optimize = 1;
6049 else
6050 mips_optimize = 2;
f3d817d8 6051 break;
0aa07269 6052
f3d817d8 6053 case 'g':
22ba90ce
ILT		 6054 if (arg == NULL)
6055 mips_debug = 2;
6056 else
6057 mips_debug = atoi (arg);
6058 /* When the MIPS assembler sees -g or -g2, it does not do
6059 optimizations which limit full symbolic debugging. We take
6060 that to be equivalent to -O0. */
6061 if (mips_debug == 2)
0aa07269 6062 mips_optimize = 0;
f3d817d8 6063 break;
4e95866e 6064
f3d817d8
DM		 6065 case OPTION_MIPS1:
6066 mips_isa = 1;
4bb0cc41
ILT		 6067 if (mips_cpu == -1)
6068 mips_cpu = 3000;
f3d817d8 6069 break;
8358c818 6070
f3d817d8
DM		 6071 case OPTION_MIPS2:
6072 mips_isa = 2;
4bb0cc41
ILT		 6073 if (mips_cpu == -1)
6074 mips_cpu = 6000;
f3d817d8 6075 break;
8358c818 6076
f3d817d8
DM		 6077 case OPTION_MIPS3:
6078 mips_isa = 3;
4bb0cc41
ILT		 6079 if (mips_cpu == -1)
6080 mips_cpu = 4000;
f3d817d8 6081 break;
8358c818 6082
d8a1c247
KR		 6083 case OPTION_MIPS4:
6084 mips_isa = 4;
6085 if (mips_cpu == -1)
6086 mips_cpu = 8000;
6087 break;
6088
f3d817d8
DM		 6089 case OPTION_MCPU:
6090 {
6091 char *p;
6092
6093 /* Identify the processor type */
6094 p = arg;
6095 if (strcmp (p, "default") == 0
6096 || strcmp (p, "DEFAULT") == 0)
4bb0cc41 6097 mips_cpu = -1;
f3d817d8
DM		 6098 else
6099 {
c625fc23
JSC		 6100 int sv = 0;
6101
6102 /* We need to cope with the various "vr" prefixes for the 4300
6103 processor. */
6104 if (*p == 'v' || *p == 'V')
6105 {
6106 sv = 1;
6107 p++;
6108 }
6109
f3d817d8
DM		 6110 if (*p == 'r' || *p == 'R')
6111 p++;
8358c818 6112
4bb0cc41 6113 mips_cpu = -1;
f3d817d8
DM		 6114 switch (*p)
6115 {
d8a1c247
KR		 6116 case '1':
6117 if (strcmp (p, "10000") == 0
6118 || strcmp (p, "10k") == 0
6119 || strcmp (p, "10K") == 0)
6120 mips_cpu = 10000;
6121 break;
6122
f3d817d8
DM		 6123 case '2':
6124 if (strcmp (p, "2000") == 0
6125 || strcmp (p, "2k") == 0
6126 || strcmp (p, "2K") == 0)
4bb0cc41 6127 mips_cpu = 2000;
f3d817d8 6128 break;
8358c818 6129
f3d817d8
DM		 6130 case '3':
6131 if (strcmp (p, "3000") == 0
6132 || strcmp (p, "3k") == 0
6133 || strcmp (p, "3K") == 0)
4bb0cc41 6134 mips_cpu = 3000;
f3d817d8 6135 break;
8358c818 6136
f3d817d8
DM		 6137 case '4':
6138 if (strcmp (p, "4000") == 0
6139 || strcmp (p, "4k") == 0
8c63448a 6140 || strcmp (p, "4K") == 0)
4bb0cc41 6141 mips_cpu = 4000;
c625fc23
JSC		 6142 else if (strcmp (p, "4100") == 0)
6143 {
6144 mips_cpu = 4100;
6145 if (mips_4100 < 0)
6146 mips_4100 = 1;
6147 }
6148 else if (strcmp (p, "4300") == 0)
6149 mips_cpu = 4300;
8c63448a 6150 else if (strcmp (p, "4400") == 0)
4bb0cc41 6151 mips_cpu = 4400;
8c63448a 6152 else if (strcmp (p, "4600") == 0)
4bb0cc41 6153 mips_cpu = 4600;
b2b8c24e
ILT		 6154 else if (strcmp (p, "4650") == 0)
6155 {
6156 mips_cpu = 4650;
6157 if (mips_4650 < 0)
6158 mips_4650 = 1;
6159 }
e532b44c
ILT		 6160 else if (strcmp (p, "4010") == 0)
6161 {
6162 mips_cpu = 4010;
6163 if (mips_4010 < 0)
6164 mips_4010 = 1;
6165 }
f3d817d8 6166 break;
8358c818 6167
f3d817d8
DM		 6168 case '6':
6169 if (strcmp (p, "6000") == 0
6170 || strcmp (p, "6k") == 0
6171 || strcmp (p, "6K") == 0)
4bb0cc41 6172 mips_cpu = 6000;
f3d817d8 6173 break;
55933a58 6174
d8a1c247
KR		 6175 case '8':
6176 if (strcmp (p, "8000") == 0
6177 || strcmp (p, "8k") == 0
6178 || strcmp (p, "8K") == 0)
6179 mips_cpu = 8000;
6180 break;
6181
55933a58
ILT		 6182 case 'o':
6183 if (strcmp (p, "orion") == 0)
4bb0cc41 6184 mips_cpu = 4600;
55933a58 6185 break;
f3d817d8 6186 }
8358c818 6187
c625fc23
JSC		 6188 if (sv && mips_cpu != 4300 && mips_cpu != 4100)
6189 {
6190 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg);
6191 return 0;
6192 }
6193
4bb0cc41 6194 if (mips_cpu == -1)
f3d817d8
DM		 6195 {
6196 as_bad ("invalid architecture -mcpu=%s", arg);
6197 return 0;
6198 }
6199 }
6200 }
6201 break;
8358c818 6202
b2b8c24e
ILT		 6203 case OPTION_M4650:
6204 mips_4650 = 1;
6205 break;
6206
6207 case OPTION_NO_M4650:
6208 mips_4650 = 0;
6209 break;
6210
e532b44c
ILT		 6211 case OPTION_M4010:
6212 mips_4010 = 1;
6213 break;
6214
6215 case OPTION_NO_M4010:
6216 mips_4010 = 0;
6217 break;
6218
c625fc23
JSC		 6219 case OPTION_M4100:
6220 mips_4100 = 1;
6221 break;
6222
6223 case OPTION_NO_M4100:
6224 mips_4100 = 0;
6225 break;
6226
f3d817d8 6227 case OPTION_MEMBEDDED_PIC:
d9aba805 6228 mips_pic = EMBEDDED_PIC;
1dc1e798 6229 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
f3d817d8
DM		 6230 {
6231 as_bad ("-G may not be used with embedded PIC code");
6232 return 0;
6233 }
5b63f465 6234 g_switch_value = 0x7fffffff;
f3d817d8 6235 break;
d9aba805 6236
fb251650
ILT		 6237 /* When generating ELF code, we permit -KPIC and -call_shared to
6238 select SVR4_PIC, and -non_shared to select no PIC. This is
6239 intended to be compatible with Irix 5. */
f3d817d8 6240 case OPTION_CALL_SHARED:
1dc1e798
KR		 6241 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
6242 {
6243 as_bad ("-call_shared is supported only for ELF format");
6244 return 0;
6245 }
d9aba805
ILT		 6246 mips_pic = SVR4_PIC;
6247 if (g_switch_seen && g_switch_value != 0)
f3d817d8
DM		 6248 {
6249 as_bad ("-G may not be used with SVR4 PIC code");
6250 return 0;
6251 }
d9aba805 6252 g_switch_value = 0;
f3d817d8
DM		 6253 break;
6254
6255 case OPTION_NON_SHARED:
1dc1e798
KR		 6256 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
6257 {
6258 as_bad ("-non_shared is supported only for ELF format");
6259 return 0;
6260 }
d9aba805 6261 mips_pic = NO_PIC;
f3d817d8 6262 break;
8358c818 6263
fb251650
ILT		 6264 /* The -xgot option tells the assembler to use 32 offsets when
6265 accessing the got in SVR4_PIC mode. It is for Irix
6266 compatibility. */
6267 case OPTION_XGOT:
6268 mips_big_got = 1;
6269 break;
6270
f3d817d8 6271 case 'G':
1dc1e798
KR		 6272 if (! USE_GLOBAL_POINTER_OPT)
6273 {
6274 as_bad ("-G is not supported for this configuration");
6275 return 0;
6276 }
6277 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
670a50eb 6278 {
f3d817d8
DM		 6279 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6280 return 0;
670a50eb
ILT		 6281 }
6282 else
f3d817d8 6283 g_switch_value = atoi (arg);
42562568 6284 g_switch_seen = 1;
f3d817d8 6285 break;
4e95866e 6286
7f9880e5
ILT		 6287 /* The -32 and -64 options tell the assembler to output the 32
6288 bit or the 64 bit MIPS ELF format. */
6289 case OPTION_32:
6290 mips_64 = 0;
6291 break;
6292
6293 case OPTION_64:
9c44af60
ILT		 6294 {
6295 const char **list, **l;
6296
6297 list = bfd_target_list ();
6298 for (l = list; *l != NULL; l++)
6299 if (strcmp (*l, "elf64-bigmips") == 0
6300 || strcmp (*l, "elf64-littlemips") == 0)
6301 break;
6302 if (*l == NULL)
6303 as_fatal ("No compiled in support for 64 bit object file format");
6304 free (list);
6305 mips_64 = 1;
6306 }
7f9880e5
ILT		 6307 break;
6308
f3d817d8
DM		 6309 default:
6310 return 0;
8ea7f4e8
ILT		 6311 }
6312
f3d817d8 6313 return 1;
8ea7f4e8
ILT		 6314}
6315
f3d817d8
DM		 6316void
6317md_show_usage (stream)
6318 FILE *stream;
6319{
6320 fprintf(stream, "\
6321MIPS options:\n\
6322-membedded-pic generate embedded position independent code\n\
f3d817d8
DM		 6323-EB generate big endian output\n\
6324-EL generate little endian output\n\
6325-g, -g2 do not remove uneeded NOPs or swap branches\n\
6326-G NUM allow referencing objects up to NUM bytes\n\
6f0b87c3
SS		 6327 implicitly with the gp register [default 8]\n");
6328 fprintf(stream, "\
f3d817d8
DM		 6329-mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6330-mips2, -mcpu=r6000 generate code for r6000\n\
6331-mips3, -mcpu=r4000 generate code for r4000\n\
d8a1c247 6332-mips4, -mcpu=r8000 generate code for r8000\n\
c625fc23 6333-mcpu=vr4300 generate code for vr4300\n\
fb251650 6334-mcpu=vr4100 generate code for vr4100\n\
e532b44c
ILT		 6335-m4650 permit R4650 instructions\n\
6336-no-m4650 do not permit R4650 instructions\n\
6337-m4010 permit R4010 instructions\n\
6338-no-m4010 do not permit R4010 instructions\n\
c625fc23
JSC		 6339-m4100 permit VR4100 instructions\n\
6340-no-m4100 do not permit VR4100 instructions\n");
6341 fprintf(stream, "\
f3d817d8
DM		 6342-O0 remove unneeded NOPs, do not swap branches\n\
6343-O remove unneeded NOPs and swap branches\n\
6344--trap, --no-break trap exception on div by 0 and mult overflow\n\
6345--break, --no-trap break exception on div by 0 and mult overflow\n");
6346#ifdef OBJ_ELF
6347 fprintf(stream, "\
6348-KPIC, -call_shared generate SVR4 position independent code\n\
fb251650 6349-non_shared do not generate position independent code\n\
7f9880e5
ILT		 6350-xgot assume a 32 bit GOT\n\
6351-32 create 32 bit object file (default)\n\
6352-64 create 64 bit object file\n");
f3d817d8
DM		 6353#endif
6354}
22ba90ce
ILT		 6355
6356void
6357mips_init_after_args ()
6358{
6359 if (target_big_endian)
6360 byte_order = BIG_ENDIAN;
6361 else
6362 byte_order = LITTLE_ENDIAN;
6363}
f3d817d8 6364\f
3d3c5039
ILT		 6365long
6366md_pcrel_from (fixP)
6367 fixS *fixP;
6368{
1dc1e798
KR		 6369 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
6370 && fixP->fx_addsy != (symbolS *) NULL
5b63f465
ILT		 6371 && ! S_IS_DEFINED (fixP->fx_addsy))
6372 {
6373 /* This makes a branch to an undefined symbol be a branch to the
6374 current location. */
6375 return 4;
6376 }
5b63f465 6377
670a50eb
ILT		 6378 /* return the address of the delay slot */
6379 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3d3c5039
ILT		 6380}
6381
abdad6bc
ILT		 6382/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6383 reloc for a cons. We could use the definition there, except that
6384 we want to handle 64 bit relocs specially. */
6385
6386void
6387cons_fix_new_mips (frag, where, nbytes, exp)
6388 fragS *frag;
6389 int where;
6390 unsigned int nbytes;
6391 expressionS *exp;
6392{
6393 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
7f9880e5
ILT		 6394 4 byte reloc. */
6395 if (nbytes == 8 && ! mips_64)
abdad6bc
ILT		 6396 {
6397 if (byte_order == BIG_ENDIAN)
6398 where += 4;
6399 nbytes = 4;
6400 }
6401
7f9880e5 6402 if (nbytes != 2 && nbytes != 4 && nbytes != 8)
abdad6bc
ILT		 6403 as_bad ("Unsupported reloc size %d", nbytes);
6404
6405 fix_new_exp (frag_now, where, (int) nbytes, exp, 0,
7f9880e5
ILT		 6406 (nbytes == 2
6407 ? BFD_RELOC_16
6408 : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
abdad6bc
ILT		 6409}
6410
867a58b3
ILT		 6411/* Sort any unmatched HI16_S relocs so that they immediately precede
6412 the corresponding LO reloc. This is called before md_apply_fix and
6413 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6414 explicit use of the %hi modifier. */
6415
6416void
6417mips_frob_file ()
6418{
6419 struct mips_hi_fixup *l;
6420
6421 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
6422 {
6423 segment_info_type *seginfo;
9b61d62b 6424 int pass;
867a58b3
ILT		 6425
6426 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
6427
6428 /* Check quickly whether the next fixup happens to be a matching
6429 %lo. */
6430 if (l->fixp->fx_next != NULL
6431 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
6432 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
6433 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
6434 continue;
6435
6436 /* Look through the fixups for this segment for a matching %lo.
9b61d62b
ILT		 6437 When we find one, move the %hi just in front of it. We do
6438 this in two passes. In the first pass, we try to find a
6439 unique %lo. In the second pass, we permit multiple %hi
6440 relocs for a single %lo (this is a GNU extension). */
867a58b3 6441 seginfo = seg_info (l->seg);
9b61d62b
ILT		 6442 for (pass = 0; pass < 2; pass++)
6443 {
6444 fixS *f, *prev;
6445
6446 prev = NULL;
6447 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
867a58b3 6448 {
9b61d62b
ILT		 6449 /* Check whether this is a %lo fixup which matches l->fixp. */
6450 if (f->fx_r_type == BFD_RELOC_LO16
6451 && f->fx_addsy == l->fixp->fx_addsy
6452 && f->fx_offset == l->fixp->fx_offset
6453 && (pass == 1
6454 || prev == NULL
6455 || prev->fx_r_type != BFD_RELOC_HI16_S
6456 || prev->fx_addsy != f->fx_addsy
6457 || prev->fx_offset != f->fx_offset))
6458 {
6459 fixS **pf;
867a58b3 6460
9b61d62b
ILT		 6461 /* Move l->fixp before f. */
6462 for (pf = &seginfo->fix_root;
6463 *pf != l->fixp;
6464 pf = &(*pf)->fx_next)
6465 assert (*pf != NULL);
867a58b3 6466
9b61d62b 6467 *pf = l->fixp->fx_next;
867a58b3 6468
9b61d62b
ILT		 6469 l->fixp->fx_next = f;
6470 if (prev == NULL)
6471 seginfo->fix_root = l->fixp;
6472 else
6473 prev->fx_next = l->fixp;
867a58b3 6474
9b61d62b
ILT		 6475 break;
6476 }
6477
6478 prev = f;
867a58b3
ILT		 6479 }
6480
9b61d62b
ILT		 6481 if (f != NULL)
6482 break;
867a58b3 6483
9b61d62b
ILT		 6484 if (pass == 1)
6485 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
6486 "Unmatched %%hi reloc");
6487 }
867a58b3
ILT		 6488 }
6489}
6490
1c803e52
ILT		 6491/* When generating embedded PIC code we need to use a special
6492 relocation to represent the difference of two symbols in the .text
6493 section (switch tables use a difference of this sort). See
6494 include/coff/mips.h for details. This macro checks whether this
6495 fixup requires the special reloc. */
6496#define SWITCH_TABLE(fixp) \
6497 ((fixp)->fx_r_type == BFD_RELOC_32 \
6498 && (fixp)->fx_addsy != NULL \
6499 && (fixp)->fx_subsy != NULL \
6500 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6501 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6502
5b63f465 6503/* When generating embedded PIC code we must keep all PC relative
1c803e52
ILT		 6504 relocations, in case the linker has to relax a call. We also need
6505 to keep relocations for switch table entries. */
5b63f465
ILT		 6506
6507/*ARGSUSED*/
6508int
6509mips_force_relocation (fixp)
6510 fixS *fixp;
6511{
1c803e52 6512 return (mips_pic == EMBEDDED_PIC
ecd4ca1c
ILT		 6513 && (fixp->fx_pcrel
6514 || SWITCH_TABLE (fixp)
6515 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
6516 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
5b63f465
ILT		 6517}
6518
6519/* Apply a fixup to the object file. */
6520
3d3c5039
ILT		 6521int
6522md_apply_fix (fixP, valueP)
6523 fixS *fixP;
918692a5 6524 valueT *valueP;
3d3c5039 6525{
670a50eb
ILT		 6526 unsigned char *buf;
6527 long insn, value;
3d3c5039 6528
49ad0c4c 6529 assert (fixP->fx_size == 4 || fixP->fx_r_type == BFD_RELOC_16);
3d3c5039 6530
670a50eb
ILT		 6531 value = *valueP;
6532 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
3d3c5039 6533
5b63f465
ILT		 6534 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
6535 fixP->fx_done = 1;
6536
670a50eb
ILT		 6537 switch (fixP->fx_r_type)
6538 {
3d3c5039
ILT		 6539 case BFD_RELOC_MIPS_JMP:
6540 case BFD_RELOC_HI16:
6541 case BFD_RELOC_HI16_S:
670a50eb 6542 case BFD_RELOC_MIPS_GPREL:
9226253a
ILT		 6543 case BFD_RELOC_MIPS_LITERAL:
6544 case BFD_RELOC_MIPS_CALL16:
0dd2d296
ILT		 6545 case BFD_RELOC_MIPS_GOT16:
6546 case BFD_RELOC_MIPS_GPREL32:
fb251650
ILT		 6547 case BFD_RELOC_MIPS_GOT_HI16:
6548 case BFD_RELOC_MIPS_GOT_LO16:
6549 case BFD_RELOC_MIPS_CALL_HI16:
6550 case BFD_RELOC_MIPS_CALL_LO16:
ecd4ca1c 6551 if (fixP->fx_pcrel)
7b777690
ILT		 6552 as_bad_where (fixP->fx_file, fixP->fx_line,
6553 "Invalid PC relative reloc");
670a50eb 6554 /* Nothing needed to do. The value comes from the reloc entry */
5b63f465 6555 break;
3d3c5039 6556
ecd4ca1c
ILT		 6557 case BFD_RELOC_PCREL_HI16_S:
6558 /* The addend for this is tricky if it is internal, so we just
6559 do everything here rather than in bfd_perform_relocation. */
6560 if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
6561 {
6562 /* For an external symbol adjust by the address to make it
6563 pcrel_offset. We use the address of the RELLO reloc
6564 which follows this one. */
6565 value += (fixP->fx_next->fx_frag->fr_address
6566 + fixP->fx_next->fx_where);
6567 }
6568 if (value & 0x8000)
6569 value += 0x10000;
6570 value >>= 16;
0221ddf7 6571 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
ecd4ca1c
ILT		 6572 if (byte_order == BIG_ENDIAN)
6573 buf += 2;
6574 md_number_to_chars (buf, value, 2);
6575 break;
6576
6577 case BFD_RELOC_PCREL_LO16:
6578 /* The addend for this is tricky if it is internal, so we just
6579 do everything here rather than in bfd_perform_relocation. */
6580 if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
6581 value += fixP->fx_frag->fr_address + fixP->fx_where;
0221ddf7 6582 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
ecd4ca1c
ILT		 6583 if (byte_order == BIG_ENDIAN)
6584 buf += 2;
6585 md_number_to_chars (buf, value, 2);
6586 break;
6587
f3645945
ILT		 6588 case BFD_RELOC_32:
6589 /* If we are deleting this reloc entry, we must fill in the
6590 value now. This can happen if we have a .word which is not
1c803e52
ILT		 6591 resolved when it appears but is later defined. We also need
6592 to fill in the value if this is an embedded PIC switch table
6593 entry. */
6594 if (fixP->fx_done
6595 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
f3645945
ILT		 6596 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
6597 value, 4);
6598 break;
6599
49ad0c4c
ILT		 6600 case BFD_RELOC_16:
6601 /* If we are deleting this reloc entry, we must fill in the
6602 value now. */
6603 assert (fixP->fx_size == 2);
6604 if (fixP->fx_done)
6605 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
6606 value, 2);
6607 break;
6608
f3645945
ILT		 6609 case BFD_RELOC_LO16:
6610 /* When handling an embedded PIC switch statement, we can wind
6611 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6612 if (fixP->fx_done)
6613 {
6614 if (value < -0x8000 || value > 0x7fff)
6615 as_bad_where (fixP->fx_file, fixP->fx_line,
6616 "relocation overflow");
0221ddf7 6617 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
f3645945
ILT		 6618 if (byte_order == BIG_ENDIAN)
6619 buf += 2;
6620 md_number_to_chars (buf, value, 2);
6621 }
6622 break;
6623
3d3c5039 6624 case BFD_RELOC_16_PCREL_S2:
670a50eb
ILT		 6625 /*
6626 * We need to save the bits in the instruction since fixup_segment()
6627 * might be deleting the relocation entry (i.e., a branch within
6628 * the current segment).
6629 */
6630 if (value & 0x3)
7b777690
ILT		 6631 as_warn_where (fixP->fx_file, fixP->fx_line,
6632 "Branch to odd address (%lx)", value);
670a50eb 6633 value >>= 2;
670a50eb
ILT		 6634
6635 /* update old instruction data */
6636 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
6637 switch (byte_order)
6638 {
3d3c5039 6639 case LITTLE_ENDIAN:
670a50eb
ILT		 6640 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
6641 break;
3d3c5039
ILT		 6642
6643 case BIG_ENDIAN:
670a50eb
ILT		 6644 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
6645 break;
3d3c5039
ILT		 6646
6647 default:
670a50eb
ILT		 6648 internalError ();
6649 return 0;
3d3c5039 6650 }
9da4c5d1
ILT		 6651
6652 if (value >= -0x8000 && value < 0x8000)
6653 insn |= value & 0xffff;
6654 else
6655 {
6656 /* The branch offset is too large. If this is an
6657 unconditional branch, and we are not generating PIC code,
6658 we can convert it to an absolute jump instruction. */
6659 if (mips_pic == NO_PIC
6660 && fixP->fx_done
6661 && fixP->fx_frag->fr_address >= text_section->vma
6662 && (fixP->fx_frag->fr_address
6663 < text_section->vma + text_section->_raw_size)
6664 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6665 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
6666 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6667 {
6668 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
6669 insn = 0x0c000000; /* jal */
6670 else
6671 insn = 0x08000000; /* j */
6672 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
6673 fixP->fx_done = 0;
6674 fixP->fx_addsy = section_symbol (text_section);
6675 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
6676 }
6677 else
6678 {
6679 /* FIXME. It would be possible in principle to handle
6680 conditional branches which overflow. They could be
6681 transformed into a branch around a jump. This would
6682 require setting up variant frags for each different
6683 branch type. The native MIPS assembler attempts to
6684 handle these cases, but it appears to do it
6685 incorrectly. */
6686 as_bad_where (fixP->fx_file, fixP->fx_line,
6687 "Relocation overflow");
6688 }
6689 }
6690
604633ae 6691 md_number_to_chars ((char *) buf, (valueT) insn, 4);
670a50eb 6692 break;
3d3c5039
ILT		 6693
6694 default:
670a50eb 6695 internalError ();
3d3c5039 6696 }
5b63f465 6697
670a50eb 6698 return 1;
3d3c5039
ILT		 6699}
6700
6701#if 0
6702void
670a50eb
ILT		 6703printInsn (oc)
6704 unsigned long oc;
3d3c5039 6705{
670a50eb
ILT		 6706 const struct mips_opcode *p;
6707 int treg, sreg, dreg, shamt;
6708 short imm;
6709 const char *args;
6710 int i;
3d3c5039 6711
670a50eb
ILT		 6712 for (i = 0; i < NUMOPCODES; ++i)
6713 {
6714 p = &mips_opcodes[i];
6715 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
6716 {
6717 printf ("%08lx %s\t", oc, p->name);
6718 treg = (oc >> 16) & 0x1f;
6719 sreg = (oc >> 21) & 0x1f;
6720 dreg = (oc >> 11) & 0x1f;
6721 shamt = (oc >> 6) & 0x1f;
6722 imm = oc;
6723 for (args = p->args;; ++args)
6724 {
6725 switch (*args)
6726 {
3d3c5039 6727 case '\0':
670a50eb
ILT		 6728 printf ("\n");
6729 break;
3d3c5039
ILT		 6730
6731 case ',':
6732 case '(':
6733 case ')':
670a50eb
ILT		 6734 printf ("%c", *args);
6735 continue;
3d3c5039
ILT		 6736
6737 case 'r':
670a50eb
ILT		 6738 assert (treg == sreg);
6739 printf ("$%d,$%d", treg, sreg);
6740 continue;
3d3c5039
ILT		 6741
6742 case 'd':
918692a5 6743 case 'G':
670a50eb
ILT		 6744 printf ("$%d", dreg);
6745 continue;
3d3c5039
ILT		 6746
6747 case 't':
918692a5 6748 case 'E':
670a50eb
ILT		 6749 printf ("$%d", treg);
6750 continue;
3d3c5039 6751
9226253a
ILT		 6752 case 'k':
6753 printf ("0x%x", treg);
6754 continue;
6755
3d3c5039
ILT		 6756 case 'b':
6757 case 's':
670a50eb
ILT		 6758 printf ("$%d", sreg);
6759 continue;
3d3c5039
ILT		 6760
6761 case 'a':
670a50eb
ILT		 6762 printf ("0x%08lx", oc & 0x1ffffff);
6763 continue;
3d3c5039
ILT		 6764
6765 case 'i':
6766 case 'j':
6767 case 'o':
6768 case 'u':
670a50eb
ILT		 6769 printf ("%d", imm);
6770 continue;
3d3c5039
ILT		 6771
6772 case '<':
56c96faa 6773 case '>':
670a50eb
ILT		 6774 printf ("$%d", shamt);
6775 continue;
3d3c5039
ILT		 6776
6777 default:
670a50eb 6778 internalError ();
3d3c5039 6779 }
670a50eb 6780 break;
3d3c5039 6781 }
670a50eb 6782 return;
3d3c5039
ILT		 6783 }
6784 }
670a50eb 6785 printf ("%08lx UNDEFINED\n", oc);
3d3c5039
ILT		 6786}
6787#endif
6788
6789static symbolS *
6790get_symbol ()
6791{
670a50eb
ILT		 6792 int c;
6793 char *name;
6794 symbolS *p;
6795
6796 name = input_line_pointer;
6797 c = get_symbol_end ();
6798 p = (symbolS *) symbol_find_or_make (name);
6799 *input_line_pointer = c;
6800 return p;
3d3c5039
ILT		 6801}
6802
becfe05e
ILT		 6803/* Align the current frag to a given power of two. The MIPS assembler
6804 also automatically adjusts any preceding label. */
6805
6806static void
23dc1ae3 6807mips_align (to, fill, label)
becfe05e
ILT		 6808 int to;
6809 int fill;
23dc1ae3 6810 symbolS *label;
becfe05e
ILT		 6811{
6812 mips_emit_delays ();
6813 frag_align (to, fill);
6814 record_alignment (now_seg, to);
23dc1ae3 6815 if (label != NULL)
becfe05e 6816 {
23dc1ae3
ILT		 6817 assert (S_GET_SEGMENT (label) == now_seg);
6818 label->sy_frag = frag_now;
6819 S_SET_VALUE (label, (valueT) frag_now_fix ());
becfe05e
ILT		 6820 }
6821}
6822
6823/* Align to a given power of two. .align 0 turns off the automatic
6824 alignment used by the data creating pseudo-ops. */
6825
3d3c5039
ILT		 6826static void
6827s_align (x)
6828 int x;
6829{
670a50eb
ILT		 6830 register int temp;
6831 register long temp_fill;
6832 long max_alignment = 15;
3d3c5039 6833
670a50eb 6834 /*
3d3c5039
ILT		 6835
6836 o Note that the assembler pulls down any immediately preceeding label
6837 to the aligned address.
6838 o It's not documented but auto alignment is reinstated by
6839 a .align pseudo instruction.
6840 o Note also that after auto alignment is turned off the mips assembler
6841 issues an error on attempt to assemble an improperly aligned data item.
6842 We don't.
6843
6844 */
6845
670a50eb
ILT		 6846 temp = get_absolute_expression ();
6847 if (temp > max_alignment)
6848 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
6849 else if (temp < 0)
6850 {
6851 as_warn ("Alignment negative: 0 assumed.");
6852 temp = 0;
6853 }
6854 if (*input_line_pointer == ',')
6855 {
6856 input_line_pointer++;
6857 temp_fill = get_absolute_expression ();
6858 }
6859 else
6860 temp_fill = 0;
6861 if (temp)
6862 {
6863 auto_align = 1;
23dc1ae3 6864 mips_align (temp, (int) temp_fill, insn_label);
3d3c5039 6865 }
670a50eb
ILT		 6866 else
6867 {
6868 auto_align = 0;
3d3c5039
ILT		 6869 }
6870
670a50eb 6871 demand_empty_rest_of_line ();
3d3c5039
ILT		 6872}
6873
739708fa
KR		 6874void
6875mips_flush_pending_output ()
becfe05e
ILT		 6876{
6877 mips_emit_delays ();
1849d646 6878 insn_label = NULL;
becfe05e
ILT		 6879}
6880
3d3c5039
ILT		 6881static void
6882s_change_sec (sec)
6883 int sec;
6884{
88225433 6885 segT seg;
becfe05e 6886
5b63f465
ILT		 6887 /* When generating embedded PIC code, we only use the .text, .lit8,
6888 .sdata and .sbss sections. We change the .data and .rdata
6889 pseudo-ops to use .sdata. */
6890 if (mips_pic == EMBEDDED_PIC
6891 && (sec == 'd' || sec == 'r'))
6892 sec = 's';
6893
becfe05e 6894 mips_emit_delays ();
670a50eb
ILT		 6895 switch (sec)
6896 {
3d3c5039 6897 case 't':
604633ae 6898 s_text (0);
670a50eb 6899 break;
3d3c5039 6900 case 'd':
604633ae 6901 s_data (0);
670a50eb 6902 break;
3d3c5039 6903 case 'b':
670a50eb 6904 subseg_set (bss_section, (subsegT) get_absolute_expression ());
670a50eb
ILT		 6905 demand_empty_rest_of_line ();
6906 break;
88225433
ILT		 6907
6908 case 'r':
1dc1e798
KR		 6909 if (USE_GLOBAL_POINTER_OPT)
6910 {
6911 seg = subseg_new (RDATA_SECTION_NAME,
6912 (subsegT) get_absolute_expression ());
6913 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6914 {
6915 bfd_set_section_flags (stdoutput, seg,
6916 (SEC_ALLOC
6917 | SEC_LOAD
6918 | SEC_READONLY
6919 | SEC_RELOC
6920 | SEC_DATA));
6921 bfd_set_section_alignment (stdoutput, seg, 4);
6922 }
6923 demand_empty_rest_of_line ();
6924 }
6925 else
6926 {
6927 as_bad ("No read only data section in this object file format");
6928 demand_empty_rest_of_line ();
6929 return;
6930 }
88225433 6931 break;
88225433
ILT		 6932
6933 case 's':
1dc1e798
KR		 6934 if (USE_GLOBAL_POINTER_OPT)
6935 {
6936 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
6937 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6938 {
6939 bfd_set_section_flags (stdoutput, seg,
6940 SEC_ALLOC | SEC_LOAD | SEC_RELOC
6941 | SEC_DATA);
6942 bfd_set_section_alignment (stdoutput, seg, 4);
6943 }
6944 demand_empty_rest_of_line ();
6945 break;
6946 }
6947 else
6948 {
6949 as_bad ("Global pointers not supported; recompile -G 0");
6950 demand_empty_rest_of_line ();
6951 return;
6952 }
3d3c5039 6953 }
88225433 6954
670a50eb 6955 auto_align = 1;
3d3c5039
ILT		 6956}
6957
739708fa
KR		 6958void
6959mips_enable_auto_align ()
9da4c5d1 6960{
9da4c5d1
ILT		 6961 auto_align = 1;
6962}
6963
3d3c5039
ILT		 6964static void
6965s_cons (log_size)
6966 int log_size;
6967{
23dc1ae3
ILT		 6968 symbolS *label;
6969
6970 label = insn_label;
becfe05e 6971 mips_emit_delays ();
670a50eb 6972 if (log_size > 0 && auto_align)
23dc1ae3 6973 mips_align (log_size, 0, label);
1849d646 6974 insn_label = NULL;
670a50eb 6975 cons (1 << log_size);
3d3c5039
ILT		 6976}
6977
3d3c5039 6978static void
becfe05e
ILT		 6979s_float_cons (type)
6980 int type;
3d3c5039 6981{
23dc1ae3
ILT		 6982 symbolS *label;
6983
6984 label = insn_label;
6985
becfe05e 6986 mips_emit_delays ();
670a50eb
ILT		 6987
6988 if (auto_align)
becfe05e 6989 if (type == 'd')
23dc1ae3 6990 mips_align (3, 0, label);
670a50eb 6991 else
23dc1ae3 6992 mips_align (2, 0, label);
670a50eb 6993
1849d646
ILT		 6994 insn_label = NULL;
6995
becfe05e 6996 float_cons (type);
3d3c5039
ILT		 6997}
6998
c1444ec4
ILT		 6999/* Handle .globl. We need to override it because on Irix 5 you are
7000 permitted to say
7001 .globl foo .text
7002 where foo is an undefined symbol, to mean that foo should be
7003 considered to be the address of a function. */
7004
7005static void
7006s_mips_globl (x)
7007 int x;
7008{
7009 char *name;
7010 int c;
7011 symbolS *symbolP;
fb251650 7012 flagword flag;
c1444ec4
ILT		 7013
7014 name = input_line_pointer;
7015 c = get_symbol_end ();
7016 symbolP = symbol_find_or_make (name);
7017 *input_line_pointer = c;
7018 SKIP_WHITESPACE ();
fb251650
ILT		 7019
7020 /* On Irix 5, every global symbol that is not explicitly labelled as
7021 being a function is apparently labelled as being an object. */
7022 flag = BSF_OBJECT;
7023
c1444ec4
ILT		 7024 if (! is_end_of_line[(unsigned char) *input_line_pointer])
7025 {
7026 char *secname;
7027 asection *sec;
7028
7029 secname = input_line_pointer;
7030 c = get_symbol_end ();
7031 sec = bfd_get_section_by_name (stdoutput, secname);
7032 if (sec == NULL)
7033 as_bad ("%s: no such section", secname);
7034 *input_line_pointer = c;
7035
7036 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
fb251650 7037 flag = BSF_FUNCTION;
c1444ec4
ILT		 7038 }
7039
fb251650
ILT		 7040 symbolP->bsym->flags |= flag;
7041
c1444ec4
ILT		 7042 S_SET_EXTERNAL (symbolP);
7043 demand_empty_rest_of_line ();
7044}
7045
3d3c5039
ILT		 7046static void
7047s_option (x)
7048 int x;
7049{
dd3f1f76
ILT		 7050 char *opt;
7051 char c;
7052
7053 opt = input_line_pointer;
7054 c = get_symbol_end ();
7055
dd3f1f76 7056 if (*opt == 'O')
9226253a
ILT		 7057 {
7058 /* FIXME: What does this mean? */
7059 }
dd3f1f76 7060 else if (strncmp (opt, "pic", 3) == 0)
9226253a 7061 {
d9aba805 7062 int i;
42562568 7063
d9aba805
ILT		 7064 i = atoi (opt + 3);
7065 if (i == 0)
7066 mips_pic = NO_PIC;
7067 else if (i == 2)
7068 mips_pic = SVR4_PIC;
7069 else
7070 as_bad (".option pic%d not supported", i);
7071
1dc1e798 7072 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
42562568
ILT		 7073 {
7074 if (g_switch_seen && g_switch_value != 0)
d9aba805 7075 as_warn ("-G may not be used with SVR4 PIC code");
42562568
ILT		 7076 g_switch_value = 0;
7077 bfd_set_gp_size (stdoutput, 0);
7078 }
9226253a 7079 }
dd3f1f76
ILT		 7080 else
7081 as_warn ("Unrecognized option \"%s\"", opt);
7082
7083 *input_line_pointer = c;
670a50eb 7084 demand_empty_rest_of_line ();
3d3c5039
ILT		 7085}
7086
7087static void
7088s_mipsset (x)
7089 int x;
7090{
670a50eb
ILT		 7091 char *name = input_line_pointer, ch;
7092
7093 while (!is_end_of_line[(unsigned char) *input_line_pointer])
7094 input_line_pointer++;
7095 ch = *input_line_pointer;
7096 *input_line_pointer = '\0';
7097
7098 if (strcmp (name, "reorder") == 0)
7099 {
4e95866e
ILT		 7100 if (mips_noreorder)
7101 {
7102 prev_insn_unreordered = 1;
7103 prev_prev_insn_unreordered = 1;
7104 }
670a50eb
ILT		 7105 mips_noreorder = 0;
7106 }
7107 else if (strcmp (name, "noreorder") == 0)
7108 {
becfe05e 7109 mips_emit_delays ();
670a50eb 7110 mips_noreorder = 1;
0dd2d296 7111 mips_any_noreorder = 1;
670a50eb
ILT		 7112 }
7113 else if (strcmp (name, "at") == 0)
7114 {
7115 mips_noat = 0;
7116 }
7117 else if (strcmp (name, "noat") == 0)
7118 {
7119 mips_noat = 1;
3d3c5039 7120 }
670a50eb
ILT		 7121 else if (strcmp (name, "macro") == 0)
7122 {
7123 mips_warn_about_macros = 0;
7124 }
7125 else if (strcmp (name, "nomacro") == 0)
7126 {
7127 if (mips_noreorder == 0)
7128 as_bad ("`noreorder' must be set before `nomacro'");
7129 mips_warn_about_macros = 1;
7130 }
7131 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
7132 {
7133 mips_nomove = 0;
7134 }
7135 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
7136 {
7137 mips_nomove = 1;
7138 }
7139 else if (strcmp (name, "bopt") == 0)
7140 {
7141 mips_nobopt = 0;
7142 }
7143 else if (strcmp (name, "nobopt") == 0)
7144 {
7145 mips_nobopt = 1;
7146 }
1051c97f
ILT		 7147 else if (strncmp (name, "mips", 4) == 0)
7148 {
7149 int isa;
7150
7151 /* Permit the user to change the ISA on the fly. Needless to
7152 say, misuse can cause serious problems. */
7153 isa = atoi (name + 4);
7154 if (isa == 0)
7155 mips_isa = file_mips_isa;
d8a1c247 7156 else if (isa < 1 || isa > 4)
1051c97f
ILT		 7157 as_bad ("unknown ISA level");
7158 else
7159 mips_isa = isa;
7160 }
670a50eb
ILT		 7161 else
7162 {
7163 as_warn ("Tried to set unrecognized symbol: %s\n", name);
7164 }
7165 *input_line_pointer = ch;
7166 demand_empty_rest_of_line ();
3d3c5039
ILT		 7167}
7168
9226253a
ILT		 7169/* Handle the .abicalls pseudo-op. I believe this is equivalent to
7170 .option pic2. It means to generate SVR4 PIC calls. */
7171
7172static void
7173s_abicalls (ignore)
7174 int ignore;
7175{
d9aba805 7176 mips_pic = SVR4_PIC;
1dc1e798
KR		 7177 if (USE_GLOBAL_POINTER_OPT)
7178 {
7179 if (g_switch_seen && g_switch_value != 0)
7180 as_warn ("-G may not be used with SVR4 PIC code");
7181 g_switch_value = 0;
7182 }
d9aba805 7183 bfd_set_gp_size (stdoutput, 0);
9226253a
ILT		 7184 demand_empty_rest_of_line ();
7185}
7186
7187/* Handle the .cpload pseudo-op. This is used when generating SVR4
7188 PIC code. It sets the $gp register for the function based on the
7189 function address, which is in the register named in the argument.
7190 This uses a relocation against _gp_disp, which is handled specially
7191 by the linker. The result is:
7192 lui $gp,%hi(_gp_disp)
7193 addiu $gp,$gp,%lo(_gp_disp)
7194 addu $gp,$gp,.cpload argument
0dd2d296 7195 The .cpload argument is normally $25 == $t9. */
9226253a
ILT		 7196
7197static void
7198s_cpload (ignore)
7199 int ignore;
7200{
7201 expressionS ex;
7202 int icnt = 0;
7203
d9aba805
ILT		 7204 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7205 if (mips_pic != SVR4_PIC)
0dd2d296
ILT		 7206 {
7207 s_ignore (0);
7208 return;
7209 }
7210
7211 /* .cpload should be a in .set noreorder section. */
7212 if (mips_noreorder == 0)
7213 as_warn (".cpload not in noreorder section");
7214
9226253a
ILT		 7215 ex.X_op = O_symbol;
7216 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
7217 ex.X_op_symbol = NULL;
7218 ex.X_add_number = 0;
7219
fb251650
ILT		 7220 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7221 ex.X_add_symbol->bsym->flags |= BSF_OBJECT;
7222
0dd2d296
ILT		 7223 macro_build_lui ((char *) NULL, &icnt, &ex, GP);
7224 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP,
9226253a
ILT		 7225 (int) BFD_RELOC_LO16);
7226
0dd2d296
ILT		 7227 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
7228 GP, GP, tc_get_register (0));
9226253a
ILT		 7229
7230 demand_empty_rest_of_line ();
7231}
7232
7233/* Handle the .cprestore pseudo-op. This stores $gp into a given
7234 offset from $sp. The offset is remembered, and after making a PIC
7235 call $gp is restored from that location. */
7236
7237static void
7238s_cprestore (ignore)
7239 int ignore;
7240{
7241 expressionS ex;
7242 int icnt = 0;
7243
d9aba805
ILT		 7244 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7245 if (mips_pic != SVR4_PIC)
0dd2d296
ILT		 7246 {
7247 s_ignore (0);
7248 return;
7249 }
7250
9226253a
ILT		 7251 mips_cprestore_offset = get_absolute_expression ();
7252
7253 ex.X_op = O_constant;
7254 ex.X_add_symbol = NULL;
7255 ex.X_op_symbol = NULL;
7256 ex.X_add_number = mips_cprestore_offset;
7257
0dd2d296 7258 macro_build ((char *) NULL, &icnt, &ex,
9226253a
ILT		 7259 mips_isa < 3 ? "sw" : "sd",
7260 "t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
7261
7262 demand_empty_rest_of_line ();
7263}
7264
0dd2d296
ILT		 7265/* Handle the .gpword pseudo-op. This is used when generating PIC
7266 code. It generates a 32 bit GP relative reloc. */
7267
7268static void
7269s_gpword (ignore)
7270 int ignore;
7271{
23dc1ae3 7272 symbolS *label;
0dd2d296
ILT		 7273 expressionS ex;
7274 char *p;
7275
7276 /* When not generating PIC code, this is treated as .word. */
7dfa376e 7277 if (mips_pic != SVR4_PIC)
0dd2d296
ILT		 7278 {
7279 s_cons (2);
7280 return;
7281 }
7282
23dc1ae3 7283 label = insn_label;
0dd2d296
ILT		 7284 mips_emit_delays ();
7285 if (auto_align)
23dc1ae3 7286 mips_align (2, 0, label);
0dd2d296
ILT		 7287 insn_label = NULL;
7288
7289 expression (&ex);
7290
7291 if (ex.X_op != O_symbol || ex.X_add_number != 0)
7292 {
7293 as_bad ("Unsupported use of .gpword");
7294 ignore_rest_of_line ();
7295 }
7296
7297 p = frag_more (4);
7298 md_number_to_chars (p, (valueT) 0, 4);
7299 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0,
7300 BFD_RELOC_MIPS_GPREL32);
7301
7302 demand_empty_rest_of_line ();
7303}
7304
7305/* Handle the .cpadd pseudo-op. This is used when dealing with switch
7306 tables in SVR4 PIC code. */
7307
7308static void
7309s_cpadd (ignore)
7310 int ignore;
7311{
7312 int icnt = 0;
7313 int reg;
7314
7315 /* This is ignored when not generating SVR4 PIC code. */
7dfa376e 7316 if (mips_pic != SVR4_PIC)
0dd2d296
ILT		 7317 {
7318 s_ignore (0);
7319 return;
7320 }
7321
7322 /* Add $gp to the register named as an argument. */
7323 reg = tc_get_register (0);
7324 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7325 mips_isa < 3 ? "addu" : "daddu",
7326 "d,v,t", reg, reg, GP);
7327
7328 demand_empty_rest_of_line ();
7329}
7330
9226253a 7331/* Parse a register string into a number. Called from the ECOFF code
0dd2d296
ILT		 7332 to parse .frame. The argument is non-zero if this is the frame
7333 register, so that we can record it in mips_frame_reg. */
9226253a 7334
3d3c5039 7335int
0dd2d296
ILT		 7336tc_get_register (frame)
7337 int frame;
3d3c5039
ILT		 7338{
7339 int reg;
7340
7341 SKIP_WHITESPACE ();
7342 if (*input_line_pointer++ != '$')
7343 {
7344 as_warn ("expected `$'");
0dd2d296 7345 reg = 0;
3d3c5039 7346 }
0dd2d296 7347 else if (isdigit ((unsigned char) *input_line_pointer))
3d3c5039
ILT		 7348 {
7349 reg = get_absolute_expression ();
7350 if (reg < 0 || reg >= 32)
7351 {
7352 as_warn ("Bad register number");
7353 reg = 0;
7354 }
7355 }
7356 else
7357 {
7358 if (strncmp (input_line_pointer, "fp", 2) == 0)
9226253a 7359 reg = FP;
3d3c5039 7360 else if (strncmp (input_line_pointer, "sp", 2) == 0)
9226253a 7361 reg = SP;
3d3c5039 7362 else if (strncmp (input_line_pointer, "gp", 2) == 0)
9226253a 7363 reg = GP;
3d3c5039 7364 else if (strncmp (input_line_pointer, "at", 2) == 0)
9226253a 7365 reg = AT;
3d3c5039
ILT		 7366 else
7367 {
7368 as_warn ("Unrecognized register name");
0dd2d296 7369 reg = 0;
3d3c5039
ILT		 7370 }
7371 input_line_pointer += 2;
7372 }
0dd2d296
ILT		 7373 if (frame)
7374 mips_frame_reg = reg != 0 ? reg : SP;
3d3c5039
ILT		 7375 return reg;
7376}
7377
0dd2d296
ILT		 7378valueT
7379md_section_align (seg, addr)
7380 asection *seg;
7381 valueT addr;
7382{
7383 int align = bfd_get_section_alignment (stdoutput, seg);
7384
cf32394d
ILT		 7385#ifdef OBJ_ELF
7386 /* We don't need to align ELF sections to the full alignment.
7387 However, Irix 5 may prefer that we align them at least to a 16
7388 byte boundary. */
7389 if (align > 16)
7390 align = 16;
10a14e36 7391#endif
cf32394d
ILT		 7392
7393 return ((addr + (1 << align) - 1) & (-1 << align));
0dd2d296
ILT		 7394}
7395
d8a1c247
KR		 7396/* Utility routine, called from above as well. If called while the
7397 input file is still being read, it's only an approximation. (For
7398 example, a symbol may later become defined which appeared to be
7399 undefined earlier.) */
22ba90ce
ILT		 7400
7401static int
7402nopic_need_relax (sym)
d8a1c247
KR		 7403 symbolS *sym;
7404{
7405 if (sym == 0)
7406 return 0;
7407
1dc1e798
KR		 7408 if (USE_GLOBAL_POINTER_OPT)
7409 {
7410 const char *symname;
7411 int change;
7412
7413 /* Find out whether this symbol can be referenced off the GP
7414 register. It can be if it is smaller than the -G size or if
7415 it is in the .sdata or .sbss section. Certain symbols can
7416 not be referenced off the GP, although it appears as though
7417 they can. */
7418 symname = S_GET_NAME (sym);
7419 if (symname != (const char *) NULL
7420 && (strcmp (symname, "eprol") == 0
7421 || strcmp (symname, "etext") == 0
7422 || strcmp (symname, "_gp") == 0
7423 || strcmp (symname, "edata") == 0
7424 || strcmp (symname, "_fbss") == 0
7425 || strcmp (symname, "_fdata") == 0
7426 || strcmp (symname, "_ftext") == 0
7427 || strcmp (symname, "end") == 0
7428 || strcmp (symname, "_gp_disp") == 0))
7429 change = 1;
7430 else if (! S_IS_DEFINED (sym)
c625fc23
JSC		 7431 && (0
7432#ifndef NO_ECOFF_DEBUGGING
7433 || (sym->ecoff_extern_size != 0
7434 && sym->ecoff_extern_size <= g_switch_value)
7435#endif
1dc1e798
KR		 7436 || (S_GET_VALUE (sym) != 0
7437 && S_GET_VALUE (sym) <= g_switch_value)))
7438 change = 0;
7439 else
7440 {
7441 const char *segname;
d8a1c247 7442
1dc1e798
KR		 7443 segname = segment_name (S_GET_SEGMENT (sym));
7444 assert (strcmp (segname, ".lit8") != 0
7445 && strcmp (segname, ".lit4") != 0);
7446 change = (strcmp (segname, ".sdata") != 0
7447 && strcmp (segname, ".sbss") != 0);
7448 }
7449 return change;
7450 }
7451 else
7452 /* We are not optimizing for the GP register. */
7453 return 1;
d8a1c247
KR		 7454}
7455
22ba90ce
ILT		 7456/* Estimate the size of a frag before relaxing. We are not really
7457 relaxing here, and the final size is encoded in the subtype
7458 information. */
7459
0dd2d296
ILT		 7460/*ARGSUSED*/
7461int
7462md_estimate_size_before_relax (fragp, segtype)
7463 fragS *fragp;
7464 asection *segtype;
7465{
7466 int change;
7467
d9aba805 7468 if (mips_pic == NO_PIC)
0dd2d296 7469 {
d8a1c247 7470 change = nopic_need_relax (fragp->fr_symbol);
0dd2d296 7471 }
d9aba805 7472 else if (mips_pic == SVR4_PIC)
0dd2d296
ILT		 7473 {
7474 asection *symsec = fragp->fr_symbol->bsym->section;
7475
7476 /* This must duplicate the test in adjust_reloc_syms. */
7477 change = (symsec != &bfd_und_section
7478 && symsec != &bfd_abs_section
7479 && ! bfd_is_com_section (symsec));
7480 }
d9aba805
ILT		 7481 else
7482 abort ();
0dd2d296
ILT		 7483
7484 if (change)
7485 {
7486 /* Record the offset to the first reloc in the fr_opcode field.
7487 This lets md_convert_frag and tc_gen_reloc know that the code
7488 must be expanded. */
7489 fragp->fr_opcode = (fragp->fr_literal
7490 + fragp->fr_fix
7491 - RELAX_OLD (fragp->fr_subtype)
7492 + RELAX_RELOC1 (fragp->fr_subtype));
7493 /* FIXME: This really needs as_warn_where. */
7494 if (RELAX_WARN (fragp->fr_subtype))
7495 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7496 }
7497
7498 if (! change)
7499 return 0;
7500 else
7501 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
7502}
7503
7504/* Translate internal representation of relocation info to BFD target
7505 format. */
7506
7507arelent **
3d3c5039
ILT		 7508tc_gen_reloc (section, fixp)
7509 asection *section;
7510 fixS *fixp;
7511{
0dd2d296 7512 static arelent *retval[4];
3d3c5039 7513 arelent *reloc;
a8aed9dd 7514 bfd_reloc_code_real_type code;
3d3c5039 7515
0dd2d296
ILT		 7516 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
7517 retval[1] = NULL;
3d3c5039
ILT		 7518
7519 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
7520 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1c803e52
ILT		 7521
7522 if (mips_pic == EMBEDDED_PIC
7523 && SWITCH_TABLE (fixp))
7524 {
7525 /* For a switch table entry we use a special reloc. The addend
7526 is actually the difference between the reloc address and the
7527 subtrahend. */
7528 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
1dc1e798
KR		 7529 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
7530 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
1c803e52
ILT		 7531 fixp->fx_r_type = BFD_RELOC_GPREL32;
7532 }
ecd4ca1c
ILT		 7533 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
7534 {
7535 /* We use a special addend for an internal RELLO reloc. */
7536 if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM)
7537 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
7538 else
7539 reloc->addend = fixp->fx_addnumber + reloc->address;
7540 }
7541 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
7542 {
7543 assert (fixp->fx_next != NULL
7544 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
7545 /* We use a special addend for an internal RELHI reloc. The
7546 reloc is relative to the RELLO; adjust the addend
7547 accordingly. */
7548 if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM)
7549 reloc->addend = (fixp->fx_next->fx_frag->fr_address
7550 + fixp->fx_next->fx_where
7551 - S_GET_VALUE (fixp->fx_subsy));
7552 else
7553 reloc->addend = (fixp->fx_addnumber
7554 + fixp->fx_next->fx_frag->fr_address
7555 + fixp->fx_next->fx_where);
7556 }
1c803e52 7557 else if (fixp->fx_pcrel == 0)
3d3c5039
ILT		 7558 reloc->addend = fixp->fx_addnumber;
7559 else
5b63f465 7560 {
1dc1e798
KR		 7561 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
7562 /* A gruesome hack which is a result of the gruesome gas reloc
7563 handling. */
7564 reloc->addend = reloc->address;
7565 else
7566 reloc->addend = -reloc->address;
5b63f465 7567 }
0dd2d296
ILT		 7568
7569 /* If this is a variant frag, we may need to adjust the existing
7570 reloc and generate a new one. */
7571 if (fixp->fx_frag->fr_opcode != NULL
7572 && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
7573 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
fb251650
ILT		 7574 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
7575 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
7576 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
7577 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
7578 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16))
0dd2d296
ILT		 7579 {
7580 arelent *reloc2;
7581
7582 /* If this is not the last reloc in this frag, then we have two
fb251650
ILT		 7583 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7584 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7585 the second one handle all of them. */
0dd2d296
ILT		 7586 if (fixp->fx_next != NULL
7587 && fixp->fx_frag == fixp->fx_next->fx_frag)
7588 {
fb251650
ILT		 7589 assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
7590 && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL)
7591 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
7592 && (fixp->fx_next->fx_r_type
7593 == BFD_RELOC_MIPS_GOT_LO16))
7594 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
7595 && (fixp->fx_next->fx_r_type
7596 == BFD_RELOC_MIPS_CALL_LO16)));
0dd2d296
ILT		 7597 retval[0] = NULL;
7598 return retval;
7599 }
7600
7601 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
7602 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7603 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
7604 retval[2] = NULL;
7605 reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym;
7606 reloc2->address = (reloc->address
7607 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
7608 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
7609 reloc2->addend = fixp->fx_addnumber;
7610 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
7611 assert (reloc2->howto != NULL);
7612
7613 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
7614 {
7615 arelent *reloc3;
7616
7617 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
7618 retval[3] = NULL;
7619 *reloc3 = *reloc2;
7620 reloc3->address += 4;
7621 }
7622
d9aba805 7623 if (mips_pic == NO_PIC)
0dd2d296
ILT		 7624 {
7625 assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL);
7626 fixp->fx_r_type = BFD_RELOC_HI16_S;
7627 }
d9aba805 7628 else if (mips_pic == SVR4_PIC)
0dd2d296 7629 {
fb251650 7630 switch (fixp->fx_r_type)
0dd2d296 7631 {
fb251650
ILT		 7632 default:
7633 abort ();
7634 case BFD_RELOC_MIPS_GOT16:
7635 break;
7636 case BFD_RELOC_MIPS_CALL16:
7637 case BFD_RELOC_MIPS_GOT_LO16:
7638 case BFD_RELOC_MIPS_CALL_LO16:
0dd2d296 7639 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
fb251650 7640 break;
0dd2d296
ILT		 7641 }
7642 }
d9aba805
ILT		 7643 else
7644 abort ();
0dd2d296
ILT		 7645 }
7646
a8aed9dd
ILT		 7647 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7648 fixup_segment converted a non-PC relative reloc into a PC
7649 relative reloc. In such a case, we need to convert the reloc
7650 code. */
7651 code = fixp->fx_r_type;
7652 if (fixp->fx_pcrel)
7653 {
7654 switch (code)
7655 {
7656 case BFD_RELOC_8:
7657 code = BFD_RELOC_8_PCREL;
7658 break;
7659 case BFD_RELOC_16:
7660 code = BFD_RELOC_16_PCREL;
7661 break;
7662 case BFD_RELOC_32:
7663 code = BFD_RELOC_32_PCREL;
7664 break;
7665 case BFD_RELOC_8_PCREL:
7666 case BFD_RELOC_16_PCREL:
7667 case BFD_RELOC_32_PCREL:
7668 case BFD_RELOC_16_PCREL_S2:
97aca1bc
ILT		 7669 case BFD_RELOC_PCREL_HI16_S:
7670 case BFD_RELOC_PCREL_LO16:
a8aed9dd
ILT		 7671 break;
7672 default:
7673 as_bad_where (fixp->fx_file, fixp->fx_line,
7674 "Cannot make %s relocation PC relative",
7675 bfd_get_reloc_code_name (code));
7676 }
7677 }
7678
d9aba805
ILT		 7679 /* To support a PC relative reloc when generating embedded PIC code
7680 for ECOFF, we use a Cygnus extension. We check for that here to
7681 make sure that we don't let such a reloc escape normally. */
1dc1e798 7682 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour
a8aed9dd 7683 && code == BFD_RELOC_16_PCREL_S2
d9aba805
ILT		 7684 && mips_pic != EMBEDDED_PIC)
7685 reloc->howto = NULL;
7686 else
a8aed9dd 7687 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
0dd2d296 7688
52aa70b5
JW		 7689 if (reloc->howto == NULL)
7690 {
7691 as_bad_where (fixp->fx_file, fixp->fx_line,
a8aed9dd
ILT		 7692 "Can not represent %s relocation in this object file format",
7693 bfd_get_reloc_code_name (code));
0dd2d296 7694 retval[0] = NULL;
52aa70b5 7695 }
3d3c5039 7696
0dd2d296 7697 return retval;
3d3c5039
ILT		 7698}
7699
0dd2d296
ILT		 7700/* Convert a machine dependent frag. */
7701
7702void
7703md_convert_frag (abfd, asec, fragp)
7704 bfd *abfd;
7705 segT asec;
7706 fragS *fragp;
3d3c5039 7707{
0dd2d296
ILT		 7708 int old, new;
7709 char *fixptr;
3d3c5039 7710
0dd2d296
ILT		 7711 if (fragp->fr_opcode == NULL)
7712 return;
3d3c5039 7713
0dd2d296
ILT		 7714 old = RELAX_OLD (fragp->fr_subtype);
7715 new = RELAX_NEW (fragp->fr_subtype);
7716 fixptr = fragp->fr_literal + fragp->fr_fix;
7717
7718 if (new > 0)
7719 memcpy (fixptr - old, fixptr, new);
7720
7721 fragp->fr_fix += new - old;
7722}
becfe05e
ILT		 7723
7724/* This function is called whenever a label is defined. It is used
7725 when handling branch delays; if a branch has a label, we assume we
7726 can not move it. */
7727
7728void
7729mips_define_label (sym)
7730 symbolS *sym;
7731{
7732 insn_label = sym;
7733}
22ba90ce
ILT		 7734
7735/* Decide whether a label is local. This is called by LOCAL_LABEL.
7736 In order to work with gcc when using mips-tfile, we must keep all
7737 local labels. However, in other cases, we want to discard them,
7738 since they are useless. */
7739
7740int
7741mips_local_label (name)
7742 const char *name;
7743{
c625fc23 7744#ifndef NO_ECOFF_DEBUGGING
22ba90ce
ILT		 7745 if (ECOFF_DEBUGGING
7746 && mips_debug != 0
7747 && ! ecoff_debugging_seen)
7748 {
7749 /* We were called with -g, but we didn't see any debugging
7750 information. That may mean that gcc is smuggling debugging
7751 information through to mips-tfile, in which case we must
7752 generate all local labels. */
7753 return 0;
7754 }
c625fc23 7755#endif
22ba90ce
ILT		 7756
7757 /* Here it's OK to discard local labels. */
7758
3af584b4 7759 return name[0] == '$';
22ba90ce 7760}
3d3c5039 7761\f
739708fa 7762#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
f2a663d3 7763
0dd2d296 7764/* Some special processing for a MIPS ELF file. */
f2a663d3
ILT		 7765
7766void
7767mips_elf_final_processing ()
7768{
87178180
ILT		 7769 /* Write out the register information. */
7770 if (! mips_64)
7771 {
7772 Elf32_RegInfo s;
7773
7774 s.ri_gprmask = mips_gprmask;
7775 s.ri_cprmask[0] = mips_cprmask[0];
7776 s.ri_cprmask[1] = mips_cprmask[1];
7777 s.ri_cprmask[2] = mips_cprmask[2];
7778 s.ri_cprmask[3] = mips_cprmask[3];
7779 /* The gp_value field is set by the MIPS ELF backend. */
7780
7781 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
7782 ((Elf32_External_RegInfo *)
7783 mips_regmask_frag));
7784 }
7785 else
7786 {
7787 Elf64_Internal_RegInfo s;
7788
7789 s.ri_gprmask = mips_gprmask;
7790 s.ri_pad = 0;
7791 s.ri_cprmask[0] = mips_cprmask[0];
7792 s.ri_cprmask[1] = mips_cprmask[1];
7793 s.ri_cprmask[2] = mips_cprmask[2];
7794 s.ri_cprmask[3] = mips_cprmask[3];
7795 /* The gp_value field is set by the MIPS ELF backend. */
7796
7797 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
7798 ((Elf64_External_RegInfo *)
7799 mips_regmask_frag));
7800 }
0dd2d296
ILT		 7801
7802 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7803 sort of BFD interface for this. */
7804 if (mips_any_noreorder)
7805 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
d9aba805 7806 if (mips_pic != NO_PIC)
0dd2d296 7807 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
f2a663d3
ILT		 7808}
7809
739708fa 7810#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
f2a663d3 7811\f
3d3c5039
ILT		 7812/* These functions should really be defined by the object file format,
7813 since they are related to debugging information. However, this
7814 code has to work for the a.out format, which does not define them,
7815 so we provide simple versions here. These don't actually generate
7816 any debugging information, but they do simple checking and someday
7817 somebody may make them useful. */
7818
670a50eb
ILT		 7819typedef struct loc
7820{
7821 struct loc *loc_next;
7822 unsigned long loc_fileno;
7823 unsigned long loc_lineno;
7824 unsigned long loc_offset;
7825 unsigned short loc_delta;
7826 unsigned short loc_count;
3d3c5039 7827#if 0
670a50eb 7828 fragS *loc_frag;
3d3c5039 7829#endif
670a50eb
ILT		 7830}
7831locS;
3d3c5039 7832
670a50eb
ILT		 7833typedef struct proc
7834 {
3d3c5039
ILT		 7835 struct proc *proc_next;
7836 struct symbol *proc_isym;
7837 struct symbol *proc_end;
7838 unsigned long proc_reg_mask;
7839 unsigned long proc_reg_offset;
7840 unsigned long proc_fpreg_mask;
7841 unsigned long proc_fpreg_offset;
7842 unsigned long proc_frameoffset;
7843 unsigned long proc_framereg;
7844 unsigned long proc_pcreg;
7845 locS *proc_iline;
7846 struct file *proc_file;
7847 int proc_index;
670a50eb
ILT		 7848 }
7849procS;
3d3c5039 7850
670a50eb
ILT		 7851typedef struct file
7852 {
3d3c5039
ILT		 7853 struct file *file_next;
7854 unsigned long file_fileno;
7855 struct symbol *file_symbol;
7856 struct symbol *file_end;
7857 struct proc *file_proc;
7858 int file_numprocs;
670a50eb
ILT		 7859 }
7860fileS;
3d3c5039
ILT		 7861
7862static struct obstack proc_frags;
7863static procS *proc_lastP;
7864static procS *proc_rootP;
7865static int numprocs;
7866
7867static void
7868md_obj_begin ()
7869{
670a50eb 7870 obstack_begin (&proc_frags, 0x2000);
3d3c5039
ILT		 7871}
7872
7873static void
7874md_obj_end ()
7875{
7876 /* check for premature end, nesting errors, etc */
7877 if (proc_lastP && proc_lastP->proc_end == NULL)
670a50eb 7878 as_warn ("missing `.end' at end of assembly");
3d3c5039
ILT		 7879}
7880
3d3c5039
ILT		 7881static long
7882get_number ()
7883{
670a50eb
ILT		 7884 int negative = 0;
7885 long val = 0;
3d3c5039 7886
670a50eb
ILT		 7887 if (*input_line_pointer == '-')
7888 {
7889 ++input_line_pointer;
7890 negative = 1;
3d3c5039 7891 }
670a50eb
ILT		 7892 if (!isdigit (*input_line_pointer))
7893 as_bad ("Expected simple number.");
7894 if (input_line_pointer[0] == '0')
7895 {
7896 if (input_line_pointer[1] == 'x')
7897 {
7898 input_line_pointer += 2;
7899 while (isxdigit (*input_line_pointer))
7900 {
7901 val <<= 4;
3a762a0b 7902 val |= hex_value (*input_line_pointer++);
3d3c5039 7903 }
670a50eb
ILT		 7904 return negative ? -val : val;
7905 }
7906 else
7907 {
7908 ++input_line_pointer;
7909 while (isdigit (*input_line_pointer))
7910 {
7911 val <<= 3;
7912 val |= *input_line_pointer++ - '0';
3d3c5039 7913 }
670a50eb 7914 return negative ? -val : val;
3d3c5039
ILT		 7915 }
7916 }
670a50eb
ILT		 7917 if (!isdigit (*input_line_pointer))
7918 {
7919 printf (" *input_line_pointer == '%c' 0x%02x\n",
7920 *input_line_pointer, *input_line_pointer);
7921 as_warn ("Invalid number");
7922 return -1;
3d3c5039 7923 }
670a50eb
ILT		 7924 while (isdigit (*input_line_pointer))
7925 {
7926 val *= 10;
7927 val += *input_line_pointer++ - '0';
3d3c5039 7928 }
670a50eb 7929 return negative ? -val : val;
3d3c5039
ILT		 7930}
7931
7932/* The .file directive; just like the usual .file directive, but there
7933 is an initial number which is the ECOFF file index. */
7934
7935static void
7936s_file (x)
7937 int x;
7938{
670a50eb 7939 int line;
3d3c5039 7940
670a50eb 7941 line = get_number ();
9a7d824a 7942 s_app_file (0);
3d3c5039
ILT		 7943}
7944
7945
7946/* The .end directive. */
7947
7948static void
7949s_mipsend (x)
7950 int x;
7951{
670a50eb
ILT		 7952 symbolS *p;
7953
7954 if (!is_end_of_line[(unsigned char) *input_line_pointer])
7955 {
7956 p = get_symbol ();
7957 demand_empty_rest_of_line ();
7958 }
7959 else
7960 p = NULL;
7961 if (now_seg != text_section)
7962 as_warn (".end not in text section");
7963 if (!proc_lastP)
7964 {
7965 as_warn (".end and no .ent seen yet.");
7966 return;
3d3c5039
ILT		 7967 }
7968
670a50eb
ILT		 7969 if (p != NULL)
7970 {
7971 assert (S_GET_NAME (p));
7972 if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym)))
7973 as_warn (".end symbol does not match .ent symbol.");
3d3c5039
ILT		 7974 }
7975
670a50eb 7976 proc_lastP->proc_end = (symbolS *) 1;
3d3c5039
ILT		 7977}
7978
7979/* The .aent and .ent directives. */
7980
7981static void
7982s_ent (aent)
7983 int aent;
7984{
670a50eb
ILT		 7985 int number = 0;
7986 procS *procP;
7987 symbolS *symbolP;
7988
7989 symbolP = get_symbol ();
7990 if (*input_line_pointer == ',')
7991 input_line_pointer++;
dd3f1f76 7992 SKIP_WHITESPACE ();
670a50eb
ILT		 7993 if (isdigit (*input_line_pointer) || *input_line_pointer == '-')
7994 number = get_number ();
7995 if (now_seg != text_section)
7996 as_warn (".ent or .aent not in text section.");
7997
7998 if (!aent && proc_lastP && proc_lastP->proc_end == NULL)
7999 as_warn ("missing `.end'");
8000
8001 if (!aent)
8002 {
8003 procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP));
8004 procP->proc_isym = symbolP;
8005 procP->proc_reg_mask = 0;
8006 procP->proc_reg_offset = 0;
8007 procP->proc_fpreg_mask = 0;
8008 procP->proc_fpreg_offset = 0;
8009 procP->proc_frameoffset = 0;
8010 procP->proc_framereg = 0;
8011 procP->proc_pcreg = 0;
8012 procP->proc_end = NULL;
8013 procP->proc_next = NULL;
8014 if (proc_lastP)
8015 proc_lastP->proc_next = procP;
8016 else
8017 proc_rootP = procP;
8018 proc_lastP = procP;
8019 numprocs++;
3d3c5039 8020 }
670a50eb 8021 demand_empty_rest_of_line ();
3d3c5039
ILT		 8022}
8023
8024/* The .frame directive. */
8025
88225433 8026#if 0
3d3c5039
ILT		 8027static void
8028s_frame (x)
670a50eb 8029 int x;
3d3c5039 8030{
670a50eb
ILT		 8031 char str[100];
8032 symbolS *symP;
8033 int frame_reg;
8034 int frame_off;
8035 int pcreg;
8036
0dd2d296 8037 frame_reg = tc_get_register (1);
670a50eb
ILT		 8038 if (*input_line_pointer == ',')
8039 input_line_pointer++;
5ac34ac3 8040 frame_off = get_absolute_expression ();
670a50eb
ILT		 8041 if (*input_line_pointer == ',')
8042 input_line_pointer++;
0dd2d296 8043 pcreg = tc_get_register (0);
670a50eb
ILT		 8044
8045 /* bob third eye */
8046 assert (proc_rootP);
8047 proc_rootP->proc_framereg = frame_reg;
8048 proc_rootP->proc_frameoffset = frame_off;
8049 proc_rootP->proc_pcreg = pcreg;
8050 /* bob macho .frame */
8051
8052 /* We don't have to write out a frame stab for unoptimized code. */
9226253a 8053 if (!(frame_reg == FP && frame_off == 0))
670a50eb
ILT		 8054 {
8055 if (!proc_lastP)
8056 as_warn ("No .ent for .frame to use.");
8057 (void) sprintf (str, "R%d;%d", frame_reg, frame_off);
8058 symP = symbol_new (str, N_VFP, 0, frag_now);
8059 S_SET_TYPE (symP, N_RMASK);
8060 S_SET_OTHER (symP, 0);
8061 S_SET_DESC (symP, 0);
8062 symP->sy_forward = proc_lastP->proc_isym;
8063 /* bob perhaps I should have used pseudo set */
3d3c5039 8064 }
670a50eb 8065 demand_empty_rest_of_line ();
3d3c5039 8066}
88225433 8067#endif
3d3c5039
ILT		 8068
8069/* The .fmask and .mask directives. */
8070
88225433 8071#if 0
3d3c5039
ILT		 8072static void
8073s_mask (reg_type)
8074 char reg_type;
8075{
670a50eb
ILT		 8076 char str[100], *strP;
8077 symbolS *symP;
8078 int i;
8079 unsigned int mask;
8080 int off;
8081
8082 mask = get_number ();
8083 if (*input_line_pointer == ',')
8084 input_line_pointer++;
8085 off = get_absolute_expression ();
8086
8087 /* bob only for coff */
8088 assert (proc_rootP);
8089 if (reg_type == 'F')
8090 {
8091 proc_rootP->proc_fpreg_mask = mask;
8092 proc_rootP->proc_fpreg_offset = off;
3d3c5039 8093 }
670a50eb
ILT		 8094 else
8095 {
8096 proc_rootP->proc_reg_mask = mask;
8097 proc_rootP->proc_reg_offset = off;
8098 }
8099
8100 /* bob macho .mask + .fmask */
3d3c5039 8101
670a50eb
ILT		 8102 /* We don't have to write out a mask stab if no saved regs. */
8103 if (!(mask == 0))
8104 {
8105 if (!proc_lastP)
8106 as_warn ("No .ent for .mask to use.");
8107 strP = str;
8108 for (i = 0; i < 32; i++)
8109 {
8110 if (mask % 2)
8111 {
8112 sprintf (strP, "%c%d,", reg_type, i);
8113 strP += strlen (strP);
8114 }
3d3c5039 8115 mask /= 2;
670a50eb
ILT		 8116 }
8117 sprintf (strP, ";%d,", off);
8118 symP = symbol_new (str, N_RMASK, 0, frag_now);
8119 S_SET_TYPE (symP, N_RMASK);
8120 S_SET_OTHER (symP, 0);
8121 S_SET_DESC (symP, 0);
8122 symP->sy_forward = proc_lastP->proc_isym;
8123 /* bob perhaps I should have used pseudo set */
3d3c5039 8124 }
3d3c5039 8125}
88225433 8126#endif
3d3c5039
ILT		 8127
8128/* The .loc directive. */
8129
88225433 8130#if 0
3d3c5039
ILT		 8131static void
8132s_loc (x)
8133 int x;
8134{
670a50eb
ILT		 8135 symbolS *symbolP;
8136 int lineno;
8137 int addroff;
3d3c5039 8138
670a50eb 8139 assert (now_seg == text_section);
3d3c5039 8140
670a50eb 8141 lineno = get_number ();
87e48495 8142 addroff = frag_now_fix ();
3d3c5039 8143
670a50eb
ILT		 8144 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
8145 S_SET_TYPE (symbolP, N_SLINE);
8146 S_SET_OTHER (symbolP, 0);
8147 S_SET_DESC (symbolP, lineno);
8148 symbolP->sy_segment = now_seg;
3d3c5039 8149}
88225433 8150#endif
GDB Binutils - Deliverables
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