Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
47e39b9d RS |
122 | /* Information about an instruction, including its format, operands |
123 | and fixups. */ | |
124 | struct mips_cl_insn | |
125 | { | |
126 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
127 | const struct mips_opcode *insn_mo; | |
128 | ||
129 | /* True if this is a mips16 instruction and if we want the extended | |
130 | form of INSN_MO. */ | |
131 | bfd_boolean use_extend; | |
132 | ||
133 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
134 | unsigned short extend; | |
135 | ||
136 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
137 | a copy of INSN_MO->match with the operands filled in. */ | |
138 | unsigned long insn_opcode; | |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d RS |
151 | |
152 | /* True if this instruction occured in a .set noreorder block. */ | |
153 | unsigned int noreorder_p : 1; | |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
157 | }; |
158 | ||
a325df1d TS |
159 | /* The ABI to use. */ |
160 | enum mips_abi_level | |
161 | { | |
162 | NO_ABI = 0, | |
163 | O32_ABI, | |
164 | O64_ABI, | |
165 | N32_ABI, | |
166 | N64_ABI, | |
167 | EABI_ABI | |
168 | }; | |
169 | ||
170 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 171 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 172 | |
143d77c5 EC |
173 | /* Whether or not we have code that can call pic code. */ |
174 | int mips_abicalls = FALSE; | |
175 | ||
aa6975fb ILT |
176 | /* Whether or not we have code which can be put into a shared |
177 | library. */ | |
178 | static bfd_boolean mips_in_shared = TRUE; | |
179 | ||
252b5132 RH |
180 | /* This is the set of options which may be modified by the .set |
181 | pseudo-op. We use a struct so that .set push and .set pop are more | |
182 | reliable. */ | |
183 | ||
e972090a NC |
184 | struct mips_set_options |
185 | { | |
252b5132 RH |
186 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
187 | if it has not been initialized. Changed by `.set mipsN', and the | |
188 | -mipsN command line option, and the default CPU. */ | |
189 | int isa; | |
1f25f5d3 CD |
190 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
191 | if they have not been initialized. Changed by `.set <asename>', by | |
192 | command line options, and based on the default architecture. */ | |
193 | int ase_mips3d; | |
deec1734 | 194 | int ase_mdmx; |
252b5132 RH |
195 | /* Whether we are assembling for the mips16 processor. 0 if we are |
196 | not, 1 if we are, and -1 if the value has not been initialized. | |
197 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
198 | -nomips16 command line options, and the default CPU. */ | |
199 | int mips16; | |
200 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
201 | reorder' and `.set noreorder'. */ | |
202 | int noreorder; | |
203 | /* Non-zero if we should not permit the $at ($1) register to be used | |
204 | in instructions. Changed by `.set at' and `.set noat'. */ | |
205 | int noat; | |
206 | /* Non-zero if we should warn when a macro instruction expands into | |
207 | more than one machine instruction. Changed by `.set nomacro' and | |
208 | `.set macro'. */ | |
209 | int warn_about_macros; | |
210 | /* Non-zero if we should not move instructions. Changed by `.set | |
211 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
212 | int nomove; | |
213 | /* Non-zero if we should not optimize branches by moving the target | |
214 | of the branch into the delay slot. Actually, we don't perform | |
215 | this optimization anyhow. Changed by `.set bopt' and `.set | |
216 | nobopt'. */ | |
217 | int nobopt; | |
218 | /* Non-zero if we should not autoextend mips16 instructions. | |
219 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
220 | int noautoextend; | |
a325df1d TS |
221 | /* Restrict general purpose registers and floating point registers |
222 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
223 | is passed but can changed if the assembler code uses .set mipsN. */ | |
224 | int gp32; | |
225 | int fp32; | |
fef14a42 TS |
226 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
227 | command line option, and the default CPU. */ | |
228 | int arch; | |
aed1a261 RS |
229 | /* True if ".set sym32" is in effect. */ |
230 | bfd_boolean sym32; | |
252b5132 RH |
231 | }; |
232 | ||
a325df1d | 233 | /* True if -mgp32 was passed. */ |
a8e8e863 | 234 | static int file_mips_gp32 = -1; |
a325df1d TS |
235 | |
236 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 237 | static int file_mips_fp32 = -1; |
a325df1d | 238 | |
252b5132 | 239 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 240 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 241 | -1 to indicate that they have not been initialized. */ |
252b5132 | 242 | |
e972090a NC |
243 | static struct mips_set_options mips_opts = |
244 | { | |
aed1a261 | 245 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 246 | }; |
252b5132 RH |
247 | |
248 | /* These variables are filled in with the masks of registers used. | |
249 | The object format code reads them and puts them in the appropriate | |
250 | place. */ | |
251 | unsigned long mips_gprmask; | |
252 | unsigned long mips_cprmask[4]; | |
253 | ||
254 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 255 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 256 | |
a4672219 TS |
257 | /* True if -mips16 was passed or implied by arguments passed on the |
258 | command line (e.g., by -march). */ | |
259 | static int file_ase_mips16; | |
260 | ||
1f25f5d3 CD |
261 | /* True if -mips3d was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips3d; | |
264 | ||
deec1734 CD |
265 | /* True if -mdmx was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mdmx; | |
268 | ||
ec68c924 | 269 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 270 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 271 | static const char *mips_arch_string; |
ec68c924 EC |
272 | |
273 | /* The argument of the -mtune= flag. The architecture for which we | |
274 | are optimizing. */ | |
275 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 276 | static const char *mips_tune_string; |
ec68c924 | 277 | |
316f5878 | 278 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
279 | static int mips_32bitmode = 0; |
280 | ||
316f5878 RS |
281 | /* True if the given ABI requires 32-bit registers. */ |
282 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
283 | ||
284 | /* Likewise 64-bit registers. */ | |
285 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
286 | ((ABI) == N32_ABI \ | |
287 | || (ABI) == N64_ABI \ | |
288 | || (ABI) == O64_ABI) | |
289 | ||
bdaaa2e1 | 290 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 291 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
292 | (ISA) == ISA_MIPS3 \ |
293 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 294 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 295 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 296 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
297 | ) |
298 | ||
af7ee8bf CD |
299 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
300 | instructions. */ | |
301 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 302 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
303 | ) |
304 | ||
305 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
306 | instructions. */ | |
307 | #define ISA_HAS_ROR(ISA) ( \ | |
308 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 309 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
310 | ) |
311 | ||
e013f690 | 312 | #define HAVE_32BIT_GPRS \ |
316f5878 | 313 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 314 | |
e013f690 | 315 | #define HAVE_32BIT_FPRS \ |
316f5878 | 316 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
317 | |
318 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
319 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
320 | ||
316f5878 | 321 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 322 | |
316f5878 | 323 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 324 | |
3b91255e RS |
325 | /* True if relocations are stored in-place. */ |
326 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
327 | ||
aed1a261 RS |
328 | /* The ABI-derived address size. */ |
329 | #define HAVE_64BIT_ADDRESSES \ | |
330 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
331 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 332 | |
aed1a261 RS |
333 | /* The size of symbolic constants (i.e., expressions of the form |
334 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
335 | #define HAVE_32BIT_SYMBOLS \ | |
336 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
337 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 338 | |
b7c7d6c1 TS |
339 | /* Addresses are loaded in different ways, depending on the address size |
340 | in use. The n32 ABI Documentation also mandates the use of additions | |
341 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 342 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 343 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
344 | |
345 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 346 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
347 | |
348 | #define ADDRESS_LOAD_INSN \ | |
349 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
350 | ||
351 | #define ADDRESS_STORE_INSN \ | |
352 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
353 | ||
a4672219 | 354 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
355 | #define CPU_HAS_MIPS16(cpu) \ |
356 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
357 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 358 | |
1f25f5d3 CD |
359 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
360 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
361 | ) | |
362 | ||
deec1734 | 363 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 364 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
365 | ) |
366 | ||
60b63b72 RS |
367 | /* True if CPU has a dror instruction. */ |
368 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
369 | ||
370 | /* True if CPU has a ror instruction. */ | |
371 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
372 | ||
c8978940 CD |
373 | /* True if mflo and mfhi can be immediately followed by instructions |
374 | which write to the HI and LO registers. | |
375 | ||
376 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
377 | (at least) two instructions between the reads of HI/LO and | |
378 | instructions which write them, and later ISAs do not. Contradicting | |
379 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
380 | the UM for the NEC Vr5000) document needing the instructions between | |
381 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
382 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
383 | earlier-ISA CPUs for which CPU documentation declares that the | |
384 | instructions are really interlocked. */ | |
385 | #define hilo_interlocks \ | |
386 | (mips_opts.isa == ISA_MIPS32 \ | |
387 | || mips_opts.isa == ISA_MIPS32R2 \ | |
388 | || mips_opts.isa == ISA_MIPS64 \ | |
389 | || mips_opts.isa == ISA_MIPS64R2 \ | |
390 | || mips_opts.arch == CPU_R4010 \ | |
391 | || mips_opts.arch == CPU_R10000 \ | |
392 | || mips_opts.arch == CPU_R12000 \ | |
393 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
394 | || mips_opts.arch == CPU_VR5500 \ |
395 | ) | |
252b5132 RH |
396 | |
397 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
398 | from the GPRs after they are loaded from memory, and thus does not |
399 | require nops to be inserted. This applies to instructions marked | |
400 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
401 | level I. */ | |
252b5132 | 402 | #define gpr_interlocks \ |
e7af610e | 403 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 404 | || mips_opts.arch == CPU_R3900) |
252b5132 | 405 | |
81912461 ILT |
406 | /* Whether the processor uses hardware interlocks to avoid delays |
407 | required by coprocessor instructions, and thus does not require | |
408 | nops to be inserted. This applies to instructions marked | |
409 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
410 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
411 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
412 | levels I, II, and III. */ | |
bdaaa2e1 | 413 | /* Itbl support may require additional care here. */ |
81912461 ILT |
414 | #define cop_interlocks \ |
415 | ((mips_opts.isa != ISA_MIPS1 \ | |
416 | && mips_opts.isa != ISA_MIPS2 \ | |
417 | && mips_opts.isa != ISA_MIPS3) \ | |
418 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
419 | ) |
420 | ||
421 | /* Whether the processor uses hardware interlocks to protect reads | |
422 | from coprocessor registers after they are loaded from memory, and | |
423 | thus does not require nops to be inserted. This applies to | |
424 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
425 | requires at MIPS ISA level I. */ | |
426 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 427 | |
6b76fefe CM |
428 | /* Is this a mfhi or mflo instruction? */ |
429 | #define MF_HILO_INSN(PINFO) \ | |
430 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
431 | ||
252b5132 RH |
432 | /* MIPS PIC level. */ |
433 | ||
a161fe53 | 434 | enum mips_pic_level mips_pic; |
252b5132 | 435 | |
c9914766 | 436 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 437 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 438 | static int mips_big_got = 0; |
252b5132 RH |
439 | |
440 | /* 1 if trap instructions should used for overflow rather than break | |
441 | instructions. */ | |
c9914766 | 442 | static int mips_trap = 0; |
252b5132 | 443 | |
119d663a | 444 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 445 | by assembling two single width halves into two single width floating |
119d663a NC |
446 | point registers which just happen to alias the double width destination |
447 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 448 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
449 | automatically at assemble time. */ |
450 | static int mips_disable_float_construction; | |
451 | ||
252b5132 RH |
452 | /* Non-zero if any .set noreorder directives were used. */ |
453 | ||
454 | static int mips_any_noreorder; | |
455 | ||
6b76fefe CM |
456 | /* Non-zero if nops should be inserted when the register referenced in |
457 | an mfhi/mflo instruction is read in the next two instructions. */ | |
458 | static int mips_7000_hilo_fix; | |
459 | ||
252b5132 | 460 | /* The size of the small data section. */ |
156c2f8b | 461 | static unsigned int g_switch_value = 8; |
252b5132 RH |
462 | /* Whether the -G option was used. */ |
463 | static int g_switch_seen = 0; | |
464 | ||
465 | #define N_RMASK 0xc4 | |
466 | #define N_VFP 0xd4 | |
467 | ||
468 | /* If we can determine in advance that GP optimization won't be | |
469 | possible, we can skip the relaxation stuff that tries to produce | |
470 | GP-relative references. This makes delay slot optimization work | |
471 | better. | |
472 | ||
473 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
474 | gcc output. It needs to guess right for gcc, otherwise gcc |
475 | will put what it thinks is a GP-relative instruction in a branch | |
476 | delay slot. | |
252b5132 RH |
477 | |
478 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
479 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 480 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
481 | |
482 | /* handle of the OPCODE hash table */ | |
483 | static struct hash_control *op_hash = NULL; | |
484 | ||
485 | /* The opcode hash table we use for the mips16. */ | |
486 | static struct hash_control *mips16_op_hash = NULL; | |
487 | ||
488 | /* This array holds the chars that always start a comment. If the | |
489 | pre-processor is disabled, these aren't very useful */ | |
490 | const char comment_chars[] = "#"; | |
491 | ||
492 | /* This array holds the chars that only start a comment at the beginning of | |
493 | a line. If the line seems to have the form '# 123 filename' | |
494 | .line and .file directives will appear in the pre-processed output */ | |
495 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
496 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 497 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
498 | /* Also note that C style comments are always supported. */ |
499 | const char line_comment_chars[] = "#"; | |
500 | ||
bdaaa2e1 | 501 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 502 | const char line_separator_chars[] = ";"; |
252b5132 RH |
503 | |
504 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
505 | const char EXP_CHARS[] = "eE"; | |
506 | ||
507 | /* Chars that mean this number is a floating point constant */ | |
508 | /* As in 0f12.456 */ | |
509 | /* or 0d1.2345e12 */ | |
510 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
511 | ||
512 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
513 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
514 | but nothing is ideal around here. | |
515 | */ | |
516 | ||
517 | static char *insn_error; | |
518 | ||
519 | static int auto_align = 1; | |
520 | ||
521 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
522 | offset in the stack frame from which to restore the $gp register. | |
523 | This is set by the .cprestore pseudo-op, and saved in this | |
524 | variable. */ | |
525 | static offsetT mips_cprestore_offset = -1; | |
526 | ||
67c1ffbe | 527 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 528 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 529 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
530 | static offsetT mips_cpreturn_offset = -1; |
531 | static int mips_cpreturn_register = -1; | |
532 | static int mips_gp_register = GP; | |
def2e0dd | 533 | static int mips_gprel_offset = 0; |
6478892d | 534 | |
7a621144 DJ |
535 | /* Whether mips_cprestore_offset has been set in the current function |
536 | (or whether it has already been warned about, if not). */ | |
537 | static int mips_cprestore_valid = 0; | |
538 | ||
252b5132 RH |
539 | /* This is the register which holds the stack frame, as set by the |
540 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
541 | static int mips_frame_reg = SP; | |
542 | ||
7a621144 DJ |
543 | /* Whether mips_frame_reg has been set in the current function |
544 | (or whether it has already been warned about, if not). */ | |
545 | static int mips_frame_reg_valid = 0; | |
546 | ||
252b5132 RH |
547 | /* To output NOP instructions correctly, we need to keep information |
548 | about the previous two instructions. */ | |
549 | ||
550 | /* Whether we are optimizing. The default value of 2 means to remove | |
551 | unneeded NOPs and swap branch instructions when possible. A value | |
552 | of 1 means to not swap branches. A value of 0 means to always | |
553 | insert NOPs. */ | |
554 | static int mips_optimize = 2; | |
555 | ||
556 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
557 | equivalent to seeing no -g option at all. */ | |
558 | static int mips_debug = 0; | |
559 | ||
7d8e00cf RS |
560 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
561 | #define MAX_VR4130_NOPS 4 | |
562 | ||
563 | /* The maximum number of NOPs needed to fill delay slots. */ | |
564 | #define MAX_DELAY_NOPS 2 | |
565 | ||
566 | /* The maximum number of NOPs needed for any purpose. */ | |
567 | #define MAX_NOPS 4 | |
71400594 RS |
568 | |
569 | /* A list of previous instructions, with index 0 being the most recent. | |
570 | We need to look back MAX_NOPS instructions when filling delay slots | |
571 | or working around processor errata. We need to look back one | |
572 | instruction further if we're thinking about using history[0] to | |
573 | fill a branch delay slot. */ | |
574 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 575 | |
1e915849 RS |
576 | /* Nop instructions used by emit_nop. */ |
577 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
578 | ||
579 | /* The appropriate nop for the current mode. */ | |
580 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 581 | |
252b5132 RH |
582 | /* If this is set, it points to a frag holding nop instructions which |
583 | were inserted before the start of a noreorder section. If those | |
584 | nops turn out to be unnecessary, the size of the frag can be | |
585 | decreased. */ | |
586 | static fragS *prev_nop_frag; | |
587 | ||
588 | /* The number of nop instructions we created in prev_nop_frag. */ | |
589 | static int prev_nop_frag_holds; | |
590 | ||
591 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 592 | prev_nop_frag. */ |
252b5132 RH |
593 | static int prev_nop_frag_required; |
594 | ||
595 | /* The number of instructions we've seen since prev_nop_frag. */ | |
596 | static int prev_nop_frag_since; | |
597 | ||
598 | /* For ECOFF and ELF, relocations against symbols are done in two | |
599 | parts, with a HI relocation and a LO relocation. Each relocation | |
600 | has only 16 bits of space to store an addend. This means that in | |
601 | order for the linker to handle carries correctly, it must be able | |
602 | to locate both the HI and the LO relocation. This means that the | |
603 | relocations must appear in order in the relocation table. | |
604 | ||
605 | In order to implement this, we keep track of each unmatched HI | |
606 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 607 | corresponding LO relocation. */ |
252b5132 | 608 | |
e972090a NC |
609 | struct mips_hi_fixup |
610 | { | |
252b5132 RH |
611 | /* Next HI fixup. */ |
612 | struct mips_hi_fixup *next; | |
613 | /* This fixup. */ | |
614 | fixS *fixp; | |
615 | /* The section this fixup is in. */ | |
616 | segT seg; | |
617 | }; | |
618 | ||
619 | /* The list of unmatched HI relocs. */ | |
620 | ||
621 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
622 | ||
64bdfcaf RS |
623 | /* The frag containing the last explicit relocation operator. |
624 | Null if explicit relocations have not been used. */ | |
625 | ||
626 | static fragS *prev_reloc_op_frag; | |
627 | ||
252b5132 RH |
628 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
629 | ||
630 | #define X ILLEGAL_REG | |
e972090a NC |
631 | static const int mips32_to_16_reg_map[] = |
632 | { | |
252b5132 RH |
633 | X, X, 2, 3, 4, 5, 6, 7, |
634 | X, X, X, X, X, X, X, X, | |
635 | 0, 1, X, X, X, X, X, X, | |
636 | X, X, X, X, X, X, X, X | |
637 | }; | |
638 | #undef X | |
639 | ||
640 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
641 | ||
e972090a NC |
642 | static const unsigned int mips16_to_32_reg_map[] = |
643 | { | |
252b5132 RH |
644 | 16, 17, 2, 3, 4, 5, 6, 7 |
645 | }; | |
60b63b72 | 646 | |
71400594 RS |
647 | /* Classifies the kind of instructions we're interested in when |
648 | implementing -mfix-vr4120. */ | |
649 | enum fix_vr4120_class { | |
650 | FIX_VR4120_MACC, | |
651 | FIX_VR4120_DMACC, | |
652 | FIX_VR4120_MULT, | |
653 | FIX_VR4120_DMULT, | |
654 | FIX_VR4120_DIV, | |
655 | FIX_VR4120_MTHILO, | |
656 | NUM_FIX_VR4120_CLASSES | |
657 | }; | |
658 | ||
659 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
660 | there must be at least one other instruction between an instruction | |
661 | of type X and an instruction of type Y. */ | |
662 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
663 | ||
664 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 665 | static int mips_fix_vr4120; |
4a6a3df4 | 666 | |
7d8e00cf RS |
667 | /* ...likewise -mfix-vr4130. */ |
668 | static int mips_fix_vr4130; | |
669 | ||
4a6a3df4 AO |
670 | /* We don't relax branches by default, since this causes us to expand |
671 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
672 | fail to compute the offset before expanding the macro to the most | |
673 | efficient expansion. */ | |
674 | ||
675 | static int mips_relax_branch; | |
252b5132 | 676 | \f |
4d7206a2 RS |
677 | /* The expansion of many macros depends on the type of symbol that |
678 | they refer to. For example, when generating position-dependent code, | |
679 | a macro that refers to a symbol may have two different expansions, | |
680 | one which uses GP-relative addresses and one which uses absolute | |
681 | addresses. When generating SVR4-style PIC, a macro may have | |
682 | different expansions for local and global symbols. | |
683 | ||
684 | We handle these situations by generating both sequences and putting | |
685 | them in variant frags. In position-dependent code, the first sequence | |
686 | will be the GP-relative one and the second sequence will be the | |
687 | absolute one. In SVR4 PIC, the first sequence will be for global | |
688 | symbols and the second will be for local symbols. | |
689 | ||
584892a6 RS |
690 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
691 | SECOND are the lengths of the two sequences in bytes. These fields | |
692 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
693 | the subtype has the following flags: | |
4d7206a2 | 694 | |
584892a6 RS |
695 | RELAX_USE_SECOND |
696 | Set if it has been decided that we should use the second | |
697 | sequence instead of the first. | |
698 | ||
699 | RELAX_SECOND_LONGER | |
700 | Set in the first variant frag if the macro's second implementation | |
701 | is longer than its first. This refers to the macro as a whole, | |
702 | not an individual relaxation. | |
703 | ||
704 | RELAX_NOMACRO | |
705 | Set in the first variant frag if the macro appeared in a .set nomacro | |
706 | block and if one alternative requires a warning but the other does not. | |
707 | ||
708 | RELAX_DELAY_SLOT | |
709 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
710 | delay slot. | |
4d7206a2 RS |
711 | |
712 | The frag's "opcode" points to the first fixup for relaxable code. | |
713 | ||
714 | Relaxable macros are generated using a sequence such as: | |
715 | ||
716 | relax_start (SYMBOL); | |
717 | ... generate first expansion ... | |
718 | relax_switch (); | |
719 | ... generate second expansion ... | |
720 | relax_end (); | |
721 | ||
722 | The code and fixups for the unwanted alternative are discarded | |
723 | by md_convert_frag. */ | |
584892a6 | 724 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 725 | |
584892a6 RS |
726 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
727 | #define RELAX_SECOND(X) ((X) & 0xff) | |
728 | #define RELAX_USE_SECOND 0x10000 | |
729 | #define RELAX_SECOND_LONGER 0x20000 | |
730 | #define RELAX_NOMACRO 0x40000 | |
731 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 732 | |
4a6a3df4 AO |
733 | /* Branch without likely bit. If label is out of range, we turn: |
734 | ||
735 | beq reg1, reg2, label | |
736 | delay slot | |
737 | ||
738 | into | |
739 | ||
740 | bne reg1, reg2, 0f | |
741 | nop | |
742 | j label | |
743 | 0: delay slot | |
744 | ||
745 | with the following opcode replacements: | |
746 | ||
747 | beq <-> bne | |
748 | blez <-> bgtz | |
749 | bltz <-> bgez | |
750 | bc1f <-> bc1t | |
751 | ||
752 | bltzal <-> bgezal (with jal label instead of j label) | |
753 | ||
754 | Even though keeping the delay slot instruction in the delay slot of | |
755 | the branch would be more efficient, it would be very tricky to do | |
756 | correctly, because we'd have to introduce a variable frag *after* | |
757 | the delay slot instruction, and expand that instead. Let's do it | |
758 | the easy way for now, even if the branch-not-taken case now costs | |
759 | one additional instruction. Out-of-range branches are not supposed | |
760 | to be common, anyway. | |
761 | ||
762 | Branch likely. If label is out of range, we turn: | |
763 | ||
764 | beql reg1, reg2, label | |
765 | delay slot (annulled if branch not taken) | |
766 | ||
767 | into | |
768 | ||
769 | beql reg1, reg2, 1f | |
770 | nop | |
771 | beql $0, $0, 2f | |
772 | nop | |
773 | 1: j[al] label | |
774 | delay slot (executed only if branch taken) | |
775 | 2: | |
776 | ||
777 | It would be possible to generate a shorter sequence by losing the | |
778 | likely bit, generating something like: | |
b34976b6 | 779 | |
4a6a3df4 AO |
780 | bne reg1, reg2, 0f |
781 | nop | |
782 | j[al] label | |
783 | delay slot (executed only if branch taken) | |
784 | 0: | |
785 | ||
786 | beql -> bne | |
787 | bnel -> beq | |
788 | blezl -> bgtz | |
789 | bgtzl -> blez | |
790 | bltzl -> bgez | |
791 | bgezl -> bltz | |
792 | bc1fl -> bc1t | |
793 | bc1tl -> bc1f | |
794 | ||
795 | bltzall -> bgezal (with jal label instead of j label) | |
796 | bgezall -> bltzal (ditto) | |
797 | ||
798 | ||
799 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 800 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
801 | ((relax_substateT) \ |
802 | (0xc0000000 \ | |
803 | | ((toofar) ? 1 : 0) \ | |
804 | | ((link) ? 2 : 0) \ | |
805 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 806 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 807 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
808 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
809 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
810 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 811 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 812 | |
252b5132 RH |
813 | /* For mips16 code, we use an entirely different form of relaxation. |
814 | mips16 supports two versions of most instructions which take | |
815 | immediate values: a small one which takes some small value, and a | |
816 | larger one which takes a 16 bit value. Since branches also follow | |
817 | this pattern, relaxing these values is required. | |
818 | ||
819 | We can assemble both mips16 and normal MIPS code in a single | |
820 | object. Therefore, we need to support this type of relaxation at | |
821 | the same time that we support the relaxation described above. We | |
822 | use the high bit of the subtype field to distinguish these cases. | |
823 | ||
824 | The information we store for this type of relaxation is the | |
825 | argument code found in the opcode file for this relocation, whether | |
826 | the user explicitly requested a small or extended form, and whether | |
827 | the relocation is in a jump or jal delay slot. That tells us the | |
828 | size of the value, and how it should be stored. We also store | |
829 | whether the fragment is considered to be extended or not. We also | |
830 | store whether this is known to be a branch to a different section, | |
831 | whether we have tried to relax this frag yet, and whether we have | |
832 | ever extended a PC relative fragment because of a shift count. */ | |
833 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
834 | (0x80000000 \ | |
835 | | ((type) & 0xff) \ | |
836 | | ((small) ? 0x100 : 0) \ | |
837 | | ((ext) ? 0x200 : 0) \ | |
838 | | ((dslot) ? 0x400 : 0) \ | |
839 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 840 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
841 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
842 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
843 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
844 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
845 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
846 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
847 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
848 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
849 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
850 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
851 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
852 | |
853 | /* Is the given value a sign-extended 32-bit value? */ | |
854 | #define IS_SEXT_32BIT_NUM(x) \ | |
855 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
856 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
857 | ||
858 | /* Is the given value a sign-extended 16-bit value? */ | |
859 | #define IS_SEXT_16BIT_NUM(x) \ | |
860 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
861 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
862 | ||
bf12938e RS |
863 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
864 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
865 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
866 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
867 | | (((VALUE) & (MASK)) << (SHIFT))) | |
868 | ||
869 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
870 | SHIFT places. */ | |
871 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
872 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
873 | ||
874 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
875 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
876 | ||
877 | include/opcode/mips.h specifies operand fields using the macros | |
878 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
879 | with "MIPS16OP" instead of "OP". */ | |
880 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
881 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
882 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
883 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
884 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
885 | ||
886 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
887 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
888 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
889 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
890 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
891 | MIPS16OP_MASK_##FIELD, \ | |
892 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
893 | \f |
894 | /* Global variables used when generating relaxable macros. See the | |
895 | comment above RELAX_ENCODE for more details about how relaxation | |
896 | is used. */ | |
897 | static struct { | |
898 | /* 0 if we're not emitting a relaxable macro. | |
899 | 1 if we're emitting the first of the two relaxation alternatives. | |
900 | 2 if we're emitting the second alternative. */ | |
901 | int sequence; | |
902 | ||
903 | /* The first relaxable fixup in the current frag. (In other words, | |
904 | the first fixup that refers to relaxable code.) */ | |
905 | fixS *first_fixup; | |
906 | ||
907 | /* sizes[0] says how many bytes of the first alternative are stored in | |
908 | the current frag. Likewise sizes[1] for the second alternative. */ | |
909 | unsigned int sizes[2]; | |
910 | ||
911 | /* The symbol on which the choice of sequence depends. */ | |
912 | symbolS *symbol; | |
913 | } mips_relax; | |
252b5132 | 914 | \f |
584892a6 RS |
915 | /* Global variables used to decide whether a macro needs a warning. */ |
916 | static struct { | |
917 | /* True if the macro is in a branch delay slot. */ | |
918 | bfd_boolean delay_slot_p; | |
919 | ||
920 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
921 | in bytes and sizes[1] is the length of the second alternative. | |
922 | For non-relaxable macros, both elements give the length of the | |
923 | macro in bytes. */ | |
924 | unsigned int sizes[2]; | |
925 | ||
926 | /* The first variant frag for this macro. */ | |
927 | fragS *first_frag; | |
928 | } mips_macro_warning; | |
929 | \f | |
252b5132 RH |
930 | /* Prototypes for static functions. */ |
931 | ||
17a2f251 | 932 | #define internalError() \ |
252b5132 | 933 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
934 | |
935 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
936 | ||
b34976b6 | 937 | static void append_insn |
4d7206a2 | 938 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 939 | static void mips_no_prev_insn (void); |
b34976b6 | 940 | static void mips16_macro_build |
67c0d1eb RS |
941 | (expressionS *, const char *, const char *, va_list); |
942 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
943 | static void macro_start (void); |
944 | static void macro_end (void); | |
17a2f251 TS |
945 | static void macro (struct mips_cl_insn * ip); |
946 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 947 | #ifdef LOSING_COMPILER |
17a2f251 | 948 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 949 | #endif |
17a2f251 TS |
950 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
951 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 952 | static void mips16_immed |
17a2f251 TS |
953 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
954 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 955 | static size_t my_getSmallExpression |
17a2f251 TS |
956 | (expressionS *, bfd_reloc_code_real_type *, char *); |
957 | static void my_getExpression (expressionS *, char *); | |
958 | static void s_align (int); | |
959 | static void s_change_sec (int); | |
960 | static void s_change_section (int); | |
961 | static void s_cons (int); | |
962 | static void s_float_cons (int); | |
963 | static void s_mips_globl (int); | |
964 | static void s_option (int); | |
965 | static void s_mipsset (int); | |
966 | static void s_abicalls (int); | |
967 | static void s_cpload (int); | |
968 | static void s_cpsetup (int); | |
969 | static void s_cplocal (int); | |
970 | static void s_cprestore (int); | |
971 | static void s_cpreturn (int); | |
972 | static void s_gpvalue (int); | |
973 | static void s_gpword (int); | |
974 | static void s_gpdword (int); | |
975 | static void s_cpadd (int); | |
976 | static void s_insn (int); | |
977 | static void md_obj_begin (void); | |
978 | static void md_obj_end (void); | |
979 | static void s_mips_ent (int); | |
980 | static void s_mips_end (int); | |
981 | static void s_mips_frame (int); | |
982 | static void s_mips_mask (int reg_type); | |
983 | static void s_mips_stab (int); | |
984 | static void s_mips_weakext (int); | |
985 | static void s_mips_file (int); | |
986 | static void s_mips_loc (int); | |
987 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 988 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 989 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
990 | |
991 | /* Table and functions used to map between CPU/ISA names, and | |
992 | ISA levels, and CPU numbers. */ | |
993 | ||
e972090a NC |
994 | struct mips_cpu_info |
995 | { | |
e7af610e NC |
996 | const char *name; /* CPU or ISA name. */ |
997 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
998 | int isa; /* ISA level. */ | |
999 | int cpu; /* CPU number (default CPU if ISA). */ | |
1000 | }; | |
1001 | ||
17a2f251 TS |
1002 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1003 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1004 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1005 | \f |
1006 | /* Pseudo-op table. | |
1007 | ||
1008 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1009 | should be defined here, but are currently unsupported: .alias, | |
1010 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1011 | ||
1012 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1013 | specific to the type of debugging information being generated, and | |
1014 | should be defined by the object format: .aent, .begin, .bend, | |
1015 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1016 | .vreg. | |
1017 | ||
1018 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1019 | not MIPS CPU specific, but are also not specific to the object file | |
1020 | format. This file is probably the best place to define them, but | |
1021 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1022 | .struct. */ | |
1023 | ||
e972090a NC |
1024 | static const pseudo_typeS mips_pseudo_table[] = |
1025 | { | |
beae10d5 | 1026 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1027 | {"option", s_option, 0}, |
1028 | {"set", s_mipsset, 0}, | |
1029 | {"rdata", s_change_sec, 'r'}, | |
1030 | {"sdata", s_change_sec, 's'}, | |
1031 | {"livereg", s_ignore, 0}, | |
1032 | {"abicalls", s_abicalls, 0}, | |
1033 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1034 | {"cpsetup", s_cpsetup, 0}, |
1035 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1036 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1037 | {"cpreturn", s_cpreturn, 0}, |
1038 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1039 | {"gpword", s_gpword, 0}, |
10181a0d | 1040 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1041 | {"cpadd", s_cpadd, 0}, |
1042 | {"insn", s_insn, 0}, | |
1043 | ||
beae10d5 | 1044 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1045 | chips. */ |
1046 | {"asciiz", stringer, 1}, | |
1047 | {"bss", s_change_sec, 'b'}, | |
1048 | {"err", s_err, 0}, | |
1049 | {"half", s_cons, 1}, | |
1050 | {"dword", s_cons, 3}, | |
1051 | {"weakext", s_mips_weakext, 0}, | |
1052 | ||
beae10d5 | 1053 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1054 | here for one reason or another. */ |
1055 | {"align", s_align, 0}, | |
1056 | {"byte", s_cons, 0}, | |
1057 | {"data", s_change_sec, 'd'}, | |
1058 | {"double", s_float_cons, 'd'}, | |
1059 | {"float", s_float_cons, 'f'}, | |
1060 | {"globl", s_mips_globl, 0}, | |
1061 | {"global", s_mips_globl, 0}, | |
1062 | {"hword", s_cons, 1}, | |
1063 | {"int", s_cons, 2}, | |
1064 | {"long", s_cons, 2}, | |
1065 | {"octa", s_cons, 4}, | |
1066 | {"quad", s_cons, 3}, | |
cca86cc8 | 1067 | {"section", s_change_section, 0}, |
252b5132 RH |
1068 | {"short", s_cons, 1}, |
1069 | {"single", s_float_cons, 'f'}, | |
1070 | {"stabn", s_mips_stab, 'n'}, | |
1071 | {"text", s_change_sec, 't'}, | |
1072 | {"word", s_cons, 2}, | |
add56521 | 1073 | |
add56521 | 1074 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1075 | |
43841e91 | 1076 | { NULL, NULL, 0 }, |
252b5132 RH |
1077 | }; |
1078 | ||
e972090a NC |
1079 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1080 | { | |
beae10d5 KH |
1081 | /* These pseudo-ops should be defined by the object file format. |
1082 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1083 | {"aent", s_mips_ent, 1}, |
1084 | {"bgnb", s_ignore, 0}, | |
1085 | {"end", s_mips_end, 0}, | |
1086 | {"endb", s_ignore, 0}, | |
1087 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1088 | {"file", s_mips_file, 0}, |
252b5132 RH |
1089 | {"fmask", s_mips_mask, 'F'}, |
1090 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1091 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1092 | {"mask", s_mips_mask, 'R'}, |
1093 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1094 | { NULL, NULL, 0 }, |
252b5132 RH |
1095 | }; |
1096 | ||
17a2f251 | 1097 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1098 | |
1099 | void | |
17a2f251 | 1100 | mips_pop_insert (void) |
252b5132 RH |
1101 | { |
1102 | pop_insert (mips_pseudo_table); | |
1103 | if (! ECOFF_DEBUGGING) | |
1104 | pop_insert (mips_nonecoff_pseudo_table); | |
1105 | } | |
1106 | \f | |
1107 | /* Symbols labelling the current insn. */ | |
1108 | ||
e972090a NC |
1109 | struct insn_label_list |
1110 | { | |
252b5132 RH |
1111 | struct insn_label_list *next; |
1112 | symbolS *label; | |
1113 | }; | |
1114 | ||
1115 | static struct insn_label_list *insn_labels; | |
1116 | static struct insn_label_list *free_insn_labels; | |
1117 | ||
17a2f251 | 1118 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1119 | |
1120 | static inline void | |
17a2f251 | 1121 | mips_clear_insn_labels (void) |
252b5132 RH |
1122 | { |
1123 | register struct insn_label_list **pl; | |
1124 | ||
1125 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1126 | ; | |
1127 | *pl = insn_labels; | |
1128 | insn_labels = NULL; | |
1129 | } | |
1130 | \f | |
1131 | static char *expr_end; | |
1132 | ||
1133 | /* Expressions which appear in instructions. These are set by | |
1134 | mips_ip. */ | |
1135 | ||
1136 | static expressionS imm_expr; | |
5f74bc13 | 1137 | static expressionS imm2_expr; |
252b5132 RH |
1138 | static expressionS offset_expr; |
1139 | ||
1140 | /* Relocs associated with imm_expr and offset_expr. */ | |
1141 | ||
f6688943 TS |
1142 | static bfd_reloc_code_real_type imm_reloc[3] |
1143 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1144 | static bfd_reloc_code_real_type offset_reloc[3] | |
1145 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1146 | |
252b5132 RH |
1147 | /* These are set by mips16_ip if an explicit extension is used. */ |
1148 | ||
b34976b6 | 1149 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1150 | |
7ed4a06a | 1151 | #ifdef OBJ_ELF |
ecb4347a DJ |
1152 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1153 | ECOFF debugging. */ | |
252b5132 RH |
1154 | |
1155 | static segT pdr_seg; | |
7ed4a06a | 1156 | #endif |
252b5132 | 1157 | |
e013f690 TS |
1158 | /* The default target format to use. */ |
1159 | ||
1160 | const char * | |
17a2f251 | 1161 | mips_target_format (void) |
e013f690 TS |
1162 | { |
1163 | switch (OUTPUT_FLAVOR) | |
1164 | { | |
e013f690 TS |
1165 | case bfd_target_ecoff_flavour: |
1166 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1167 | case bfd_target_coff_flavour: | |
1168 | return "pe-mips"; | |
1169 | case bfd_target_elf_flavour: | |
1170 | #ifdef TE_TMIPS | |
cfe86eaa | 1171 | /* This is traditional mips. */ |
e013f690 | 1172 | return (target_big_endian |
cfe86eaa TS |
1173 | ? (HAVE_64BIT_OBJECTS |
1174 | ? "elf64-tradbigmips" | |
1175 | : (HAVE_NEWABI | |
1176 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1177 | : (HAVE_64BIT_OBJECTS | |
1178 | ? "elf64-tradlittlemips" | |
1179 | : (HAVE_NEWABI | |
1180 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1181 | #else |
1182 | return (target_big_endian | |
cfe86eaa TS |
1183 | ? (HAVE_64BIT_OBJECTS |
1184 | ? "elf64-bigmips" | |
1185 | : (HAVE_NEWABI | |
1186 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1187 | : (HAVE_64BIT_OBJECTS | |
1188 | ? "elf64-littlemips" | |
1189 | : (HAVE_NEWABI | |
1190 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1191 | #endif |
1192 | default: | |
1193 | abort (); | |
1194 | return NULL; | |
1195 | } | |
1196 | } | |
1197 | ||
1e915849 RS |
1198 | /* Return the length of instruction INSN. */ |
1199 | ||
1200 | static inline unsigned int | |
1201 | insn_length (const struct mips_cl_insn *insn) | |
1202 | { | |
1203 | if (!mips_opts.mips16) | |
1204 | return 4; | |
1205 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1206 | } | |
1207 | ||
1208 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1209 | ||
1210 | static void | |
1211 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1212 | { | |
1213 | size_t i; | |
1214 | ||
1215 | insn->insn_mo = mo; | |
1216 | insn->use_extend = FALSE; | |
1217 | insn->extend = 0; | |
1218 | insn->insn_opcode = mo->match; | |
1219 | insn->frag = NULL; | |
1220 | insn->where = 0; | |
1221 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1222 | insn->fixp[i] = NULL; | |
1223 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1224 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1225 | insn->mips16_absolute_jump_p = 0; | |
1226 | } | |
1227 | ||
1228 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1229 | ||
1230 | static void | |
1231 | install_insn (const struct mips_cl_insn *insn) | |
1232 | { | |
1233 | char *f = insn->frag->fr_literal + insn->where; | |
1234 | if (!mips_opts.mips16) | |
1235 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1236 | else if (insn->mips16_absolute_jump_p) | |
1237 | { | |
1238 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1239 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1240 | } | |
1241 | else | |
1242 | { | |
1243 | if (insn->use_extend) | |
1244 | { | |
1245 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1246 | f += 2; | |
1247 | } | |
1248 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1253 | and install the opcode in the new location. */ | |
1254 | ||
1255 | static void | |
1256 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1257 | { | |
1258 | size_t i; | |
1259 | ||
1260 | insn->frag = frag; | |
1261 | insn->where = where; | |
1262 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1263 | if (insn->fixp[i] != NULL) | |
1264 | { | |
1265 | insn->fixp[i]->fx_frag = frag; | |
1266 | insn->fixp[i]->fx_where = where; | |
1267 | } | |
1268 | install_insn (insn); | |
1269 | } | |
1270 | ||
1271 | /* Add INSN to the end of the output. */ | |
1272 | ||
1273 | static void | |
1274 | add_fixed_insn (struct mips_cl_insn *insn) | |
1275 | { | |
1276 | char *f = frag_more (insn_length (insn)); | |
1277 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1278 | } | |
1279 | ||
1280 | /* Start a variant frag and move INSN to the start of the variant part, | |
1281 | marking it as fixed. The other arguments are as for frag_var. */ | |
1282 | ||
1283 | static void | |
1284 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1285 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1286 | { | |
1287 | frag_grow (max_chars); | |
1288 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1289 | insn->fixed_p = 1; | |
1290 | frag_var (rs_machine_dependent, max_chars, var, | |
1291 | subtype, symbol, offset, NULL); | |
1292 | } | |
1293 | ||
1294 | /* Insert N copies of INSN into the history buffer, starting at | |
1295 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1296 | ||
1297 | static void | |
1298 | insert_into_history (unsigned int first, unsigned int n, | |
1299 | const struct mips_cl_insn *insn) | |
1300 | { | |
1301 | if (mips_relax.sequence != 2) | |
1302 | { | |
1303 | unsigned int i; | |
1304 | ||
1305 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1306 | if (i >= first + n) | |
1307 | history[i] = history[i - n]; | |
1308 | else | |
1309 | history[i] = *insn; | |
1310 | } | |
1311 | } | |
1312 | ||
1313 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1314 | ||
1315 | static void | |
1316 | emit_nop (void) | |
1317 | { | |
1318 | add_fixed_insn (NOP_INSN); | |
1319 | insert_into_history (0, 1, NOP_INSN); | |
1320 | } | |
1321 | ||
71400594 RS |
1322 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1323 | the idea is to make it obvious at a glance that each errata is | |
1324 | included. */ | |
1325 | ||
1326 | static void | |
1327 | init_vr4120_conflicts (void) | |
1328 | { | |
1329 | #define CONFLICT(FIRST, SECOND) \ | |
1330 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1331 | ||
1332 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1333 | CONFLICT (MACC, DIV); | |
1334 | CONFLICT (DMACC, DIV); | |
1335 | ||
1336 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1337 | CONFLICT (DMULT, DMULT); | |
1338 | CONFLICT (DMULT, DMACC); | |
1339 | CONFLICT (DMACC, DMULT); | |
1340 | CONFLICT (DMACC, DMACC); | |
1341 | ||
1342 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1343 | CONFLICT (MACC, MTHILO); | |
1344 | CONFLICT (DMACC, MTHILO); | |
1345 | ||
1346 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1347 | instruction is executed immediately after a MACC or DMACC | |
1348 | instruction, the result of [either instruction] is incorrect." */ | |
1349 | CONFLICT (MACC, MULT); | |
1350 | CONFLICT (MACC, DMULT); | |
1351 | CONFLICT (DMACC, MULT); | |
1352 | CONFLICT (DMACC, DMULT); | |
1353 | ||
1354 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1355 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1356 | DDIV or DDIVU instruction, the result of the MACC or | |
1357 | DMACC instruction is incorrect.". */ | |
1358 | CONFLICT (DMULT, MACC); | |
1359 | CONFLICT (DMULT, DMACC); | |
1360 | CONFLICT (DIV, MACC); | |
1361 | CONFLICT (DIV, DMACC); | |
1362 | ||
1363 | #undef CONFLICT | |
1364 | } | |
1365 | ||
156c2f8b NC |
1366 | /* This function is called once, at assembler startup time. It should |
1367 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1368 | ||
252b5132 | 1369 | void |
17a2f251 | 1370 | md_begin (void) |
252b5132 | 1371 | { |
252b5132 | 1372 | register const char *retval = NULL; |
156c2f8b | 1373 | int i = 0; |
252b5132 | 1374 | int broken = 0; |
1f25f5d3 | 1375 | |
fef14a42 | 1376 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1377 | as_warn (_("Could not set architecture and machine")); |
1378 | ||
252b5132 RH |
1379 | op_hash = hash_new (); |
1380 | ||
1381 | for (i = 0; i < NUMOPCODES;) | |
1382 | { | |
1383 | const char *name = mips_opcodes[i].name; | |
1384 | ||
17a2f251 | 1385 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1386 | if (retval != NULL) |
1387 | { | |
1388 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1389 | mips_opcodes[i].name, retval); | |
1390 | /* Probably a memory allocation problem? Give up now. */ | |
1391 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1392 | } | |
1393 | do | |
1394 | { | |
1395 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1396 | { | |
1397 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1398 | broken = 1; | |
1e915849 RS |
1399 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1400 | { | |
1401 | create_insn (&nop_insn, mips_opcodes + i); | |
1402 | nop_insn.fixed_p = 1; | |
1403 | } | |
252b5132 RH |
1404 | } |
1405 | ++i; | |
1406 | } | |
1407 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1408 | } | |
1409 | ||
1410 | mips16_op_hash = hash_new (); | |
1411 | ||
1412 | i = 0; | |
1413 | while (i < bfd_mips16_num_opcodes) | |
1414 | { | |
1415 | const char *name = mips16_opcodes[i].name; | |
1416 | ||
17a2f251 | 1417 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1418 | if (retval != NULL) |
1419 | as_fatal (_("internal: can't hash `%s': %s"), | |
1420 | mips16_opcodes[i].name, retval); | |
1421 | do | |
1422 | { | |
1423 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1424 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1425 | != mips16_opcodes[i].match)) | |
1426 | { | |
1427 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1428 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1429 | broken = 1; | |
1430 | } | |
1e915849 RS |
1431 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1432 | { | |
1433 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1434 | mips16_nop_insn.fixed_p = 1; | |
1435 | } | |
252b5132 RH |
1436 | ++i; |
1437 | } | |
1438 | while (i < bfd_mips16_num_opcodes | |
1439 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1440 | } | |
1441 | ||
1442 | if (broken) | |
1443 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1444 | ||
1445 | /* We add all the general register names to the symbol table. This | |
1446 | helps us detect invalid uses of them. */ | |
1447 | for (i = 0; i < 32; i++) | |
1448 | { | |
1449 | char buf[5]; | |
1450 | ||
1451 | sprintf (buf, "$%d", i); | |
1452 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1453 | &zero_address_frag)); | |
1454 | } | |
76db943d TS |
1455 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1456 | &zero_address_frag)); | |
252b5132 RH |
1457 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1458 | &zero_address_frag)); | |
1459 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1460 | &zero_address_frag)); | |
1461 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1462 | &zero_address_frag)); | |
1463 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1464 | &zero_address_frag)); | |
1465 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1466 | &zero_address_frag)); | |
1467 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1468 | &zero_address_frag)); | |
85b51719 TS |
1469 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1470 | &zero_address_frag)); | |
252b5132 RH |
1471 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1472 | &zero_address_frag)); | |
1473 | ||
6047c971 AO |
1474 | /* If we don't add these register names to the symbol table, they |
1475 | may end up being added as regular symbols by operand(), and then | |
1476 | make it to the object file as undefined in case they're not | |
1477 | regarded as local symbols. They're local in o32, since `$' is a | |
1478 | local symbol prefix, but not in n32 or n64. */ | |
1479 | for (i = 0; i < 8; i++) | |
1480 | { | |
1481 | char buf[6]; | |
1482 | ||
1483 | sprintf (buf, "$fcc%i", i); | |
1484 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1485 | &zero_address_frag)); | |
1486 | } | |
1487 | ||
7d10b47d | 1488 | mips_no_prev_insn (); |
252b5132 RH |
1489 | |
1490 | mips_gprmask = 0; | |
1491 | mips_cprmask[0] = 0; | |
1492 | mips_cprmask[1] = 0; | |
1493 | mips_cprmask[2] = 0; | |
1494 | mips_cprmask[3] = 0; | |
1495 | ||
1496 | /* set the default alignment for the text section (2**2) */ | |
1497 | record_alignment (text_section, 2); | |
1498 | ||
4d0d148d | 1499 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1500 | |
1501 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1502 | { | |
1503 | /* On a native system, sections must be aligned to 16 byte | |
1504 | boundaries. When configured for an embedded ELF target, we | |
1505 | don't bother. */ | |
1506 | if (strcmp (TARGET_OS, "elf") != 0) | |
1507 | { | |
1508 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1509 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1510 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1511 | } | |
1512 | ||
1513 | /* Create a .reginfo section for register masks and a .mdebug | |
1514 | section for debugging information. */ | |
1515 | { | |
1516 | segT seg; | |
1517 | subsegT subseg; | |
1518 | flagword flags; | |
1519 | segT sec; | |
1520 | ||
1521 | seg = now_seg; | |
1522 | subseg = now_subseg; | |
1523 | ||
1524 | /* The ABI says this section should be loaded so that the | |
1525 | running program can access it. However, we don't load it | |
1526 | if we are configured for an embedded target */ | |
1527 | flags = SEC_READONLY | SEC_DATA; | |
1528 | if (strcmp (TARGET_OS, "elf") != 0) | |
1529 | flags |= SEC_ALLOC | SEC_LOAD; | |
1530 | ||
316f5878 | 1531 | if (mips_abi != N64_ABI) |
252b5132 RH |
1532 | { |
1533 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1534 | ||
195325d2 TS |
1535 | bfd_set_section_flags (stdoutput, sec, flags); |
1536 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1537 | |
252b5132 RH |
1538 | #ifdef OBJ_ELF |
1539 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1540 | #endif | |
1541 | } | |
1542 | else | |
1543 | { | |
1544 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1545 | .reginfo section. */ | |
1546 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1547 | bfd_set_section_flags (stdoutput, sec, flags); |
1548 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1549 | |
1550 | #ifdef OBJ_ELF | |
1551 | /* Set up the option header. */ | |
1552 | { | |
1553 | Elf_Internal_Options opthdr; | |
1554 | char *f; | |
1555 | ||
1556 | opthdr.kind = ODK_REGINFO; | |
1557 | opthdr.size = (sizeof (Elf_External_Options) | |
1558 | + sizeof (Elf64_External_RegInfo)); | |
1559 | opthdr.section = 0; | |
1560 | opthdr.info = 0; | |
1561 | f = frag_more (sizeof (Elf_External_Options)); | |
1562 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1563 | (Elf_External_Options *) f); | |
1564 | ||
1565 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1566 | } | |
1567 | #endif | |
1568 | } | |
1569 | ||
1570 | if (ECOFF_DEBUGGING) | |
1571 | { | |
1572 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1573 | (void) bfd_set_section_flags (stdoutput, sec, | |
1574 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1575 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1576 | } | |
ecb4347a | 1577 | #ifdef OBJ_ELF |
dcd410fe | 1578 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1579 | { |
1580 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1581 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1582 | SEC_READONLY | SEC_RELOC | |
1583 | | SEC_DEBUGGING); | |
1584 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1585 | } | |
252b5132 RH |
1586 | #endif |
1587 | ||
1588 | subseg_set (seg, subseg); | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | if (! ECOFF_DEBUGGING) | |
1593 | md_obj_begin (); | |
71400594 RS |
1594 | |
1595 | if (mips_fix_vr4120) | |
1596 | init_vr4120_conflicts (); | |
252b5132 RH |
1597 | } |
1598 | ||
1599 | void | |
17a2f251 | 1600 | md_mips_end (void) |
252b5132 RH |
1601 | { |
1602 | if (! ECOFF_DEBUGGING) | |
1603 | md_obj_end (); | |
1604 | } | |
1605 | ||
1606 | void | |
17a2f251 | 1607 | md_assemble (char *str) |
252b5132 RH |
1608 | { |
1609 | struct mips_cl_insn insn; | |
f6688943 TS |
1610 | bfd_reloc_code_real_type unused_reloc[3] |
1611 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1612 | |
1613 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1614 | imm2_expr.X_op = O_absent; |
252b5132 | 1615 | offset_expr.X_op = O_absent; |
f6688943 TS |
1616 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1617 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1618 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1619 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1620 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1621 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1622 | |
1623 | if (mips_opts.mips16) | |
1624 | mips16_ip (str, &insn); | |
1625 | else | |
1626 | { | |
1627 | mips_ip (str, &insn); | |
beae10d5 KH |
1628 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1629 | str, insn.insn_opcode)); | |
252b5132 RH |
1630 | } |
1631 | ||
1632 | if (insn_error) | |
1633 | { | |
1634 | as_bad ("%s `%s'", insn_error, str); | |
1635 | return; | |
1636 | } | |
1637 | ||
1638 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1639 | { | |
584892a6 | 1640 | macro_start (); |
252b5132 RH |
1641 | if (mips_opts.mips16) |
1642 | mips16_macro (&insn); | |
1643 | else | |
1644 | macro (&insn); | |
584892a6 | 1645 | macro_end (); |
252b5132 RH |
1646 | } |
1647 | else | |
1648 | { | |
1649 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1650 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1651 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1652 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1653 | else |
4d7206a2 | 1654 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1655 | } |
1656 | } | |
1657 | ||
5919d012 RS |
1658 | /* Return true if the given relocation might need a matching %lo(). |
1659 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1660 | applied to local symbols. */ | |
1661 | ||
1662 | static inline bfd_boolean | |
17a2f251 | 1663 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1664 | { |
3b91255e RS |
1665 | return (HAVE_IN_PLACE_ADDENDS |
1666 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1667 | || reloc == BFD_RELOC_MIPS_GOT16 |
1668 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1669 | } |
1670 | ||
1671 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1672 | relocation. */ | |
1673 | ||
1674 | static inline bfd_boolean | |
17a2f251 | 1675 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1676 | { |
1677 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1678 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1679 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1680 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1681 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1682 | } | |
1683 | ||
252b5132 RH |
1684 | /* See whether instruction IP reads register REG. CLASS is the type |
1685 | of register. */ | |
1686 | ||
1687 | static int | |
71400594 | 1688 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1689 | enum mips_regclass class) |
252b5132 RH |
1690 | { |
1691 | if (class == MIPS16_REG) | |
1692 | { | |
1693 | assert (mips_opts.mips16); | |
1694 | reg = mips16_to_32_reg_map[reg]; | |
1695 | class = MIPS_GR_REG; | |
1696 | } | |
1697 | ||
85b51719 TS |
1698 | /* Don't report on general register ZERO, since it never changes. */ |
1699 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1700 | return 0; |
1701 | ||
1702 | if (class == MIPS_FP_REG) | |
1703 | { | |
1704 | assert (! mips_opts.mips16); | |
1705 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1706 | This is not optimal, because it will introduce an unnecessary | |
1707 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1708 | need to distinguish reading both $f0 and $f1 or just one of | |
1709 | them. Note that we don't have to check the other way, | |
1710 | because there is no instruction that sets both $f0 and $f1 | |
1711 | and requires a delay. */ | |
1712 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1713 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1714 | == (reg &~ (unsigned) 1))) |
1715 | return 1; | |
1716 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1717 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1718 | == (reg &~ (unsigned) 1))) |
1719 | return 1; | |
1720 | } | |
1721 | else if (! mips_opts.mips16) | |
1722 | { | |
1723 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1724 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1725 | return 1; |
1726 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1727 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1728 | return 1; |
1729 | } | |
1730 | else | |
1731 | { | |
1732 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1733 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1734 | return 1; |
1735 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1736 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1737 | return 1; |
1738 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1739 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1740 | == reg)) |
1741 | return 1; | |
1742 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1743 | return 1; | |
1744 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1745 | return 1; | |
1746 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1747 | return 1; | |
1748 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1749 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1750 | return 1; |
1751 | } | |
1752 | ||
1753 | return 0; | |
1754 | } | |
1755 | ||
1756 | /* This function returns true if modifying a register requires a | |
1757 | delay. */ | |
1758 | ||
1759 | static int | |
17a2f251 | 1760 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1761 | { |
1762 | unsigned long prev_pinfo; | |
1763 | ||
47e39b9d | 1764 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1765 | if (! mips_opts.noreorder |
81912461 ILT |
1766 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1767 | && ! gpr_interlocks) | |
1768 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1769 | && ! cop_interlocks))) | |
252b5132 | 1770 | { |
81912461 ILT |
1771 | /* A load from a coprocessor or from memory. All load delays |
1772 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1773 | /* Itbl support may require additional care here. */ |
252b5132 | 1774 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1775 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1776 | return 1; |
1777 | } | |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
404a8071 RS |
1782 | /* Move all labels in insn_labels to the current insertion point. */ |
1783 | ||
1784 | static void | |
1785 | mips_move_labels (void) | |
1786 | { | |
1787 | struct insn_label_list *l; | |
1788 | valueT val; | |
1789 | ||
1790 | for (l = insn_labels; l != NULL; l = l->next) | |
1791 | { | |
1792 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1793 | symbol_set_frag (l->label, frag_now); | |
1794 | val = (valueT) frag_now_fix (); | |
1795 | /* mips16 text labels are stored as odd. */ | |
1796 | if (mips_opts.mips16) | |
1797 | ++val; | |
1798 | S_SET_VALUE (l->label, val); | |
1799 | } | |
1800 | } | |
1801 | ||
252b5132 RH |
1802 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1803 | handle them specially, such as generating jalx instructions when | |
1804 | needed. We also make them odd for the duration of the assembly, in | |
1805 | order to generate the right sort of code. We will make them even | |
1806 | in the adjust_symtab routine, while leaving them marked. This is | |
1807 | convenient for the debugger and the disassembler. The linker knows | |
1808 | to make them odd again. */ | |
1809 | ||
1810 | static void | |
17a2f251 | 1811 | mips16_mark_labels (void) |
252b5132 RH |
1812 | { |
1813 | if (mips_opts.mips16) | |
1814 | { | |
1815 | struct insn_label_list *l; | |
98aa84af | 1816 | valueT val; |
252b5132 RH |
1817 | |
1818 | for (l = insn_labels; l != NULL; l = l->next) | |
1819 | { | |
1820 | #ifdef OBJ_ELF | |
1821 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1822 | S_SET_OTHER (l->label, STO_MIPS16); | |
1823 | #endif | |
98aa84af AM |
1824 | val = S_GET_VALUE (l->label); |
1825 | if ((val & 1) == 0) | |
1826 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1827 | } |
1828 | } | |
1829 | } | |
1830 | ||
4d7206a2 RS |
1831 | /* End the current frag. Make it a variant frag and record the |
1832 | relaxation info. */ | |
1833 | ||
1834 | static void | |
1835 | relax_close_frag (void) | |
1836 | { | |
584892a6 | 1837 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1838 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1839 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1840 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1841 | ||
1842 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1843 | mips_relax.first_fixup = 0; | |
1844 | } | |
1845 | ||
1846 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1847 | See the comment above RELAX_ENCODE for more details. */ | |
1848 | ||
1849 | static void | |
1850 | relax_start (symbolS *symbol) | |
1851 | { | |
1852 | assert (mips_relax.sequence == 0); | |
1853 | mips_relax.sequence = 1; | |
1854 | mips_relax.symbol = symbol; | |
1855 | } | |
1856 | ||
1857 | /* Start generating the second version of a relaxable sequence. | |
1858 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1859 | |
1860 | static void | |
4d7206a2 RS |
1861 | relax_switch (void) |
1862 | { | |
1863 | assert (mips_relax.sequence == 1); | |
1864 | mips_relax.sequence = 2; | |
1865 | } | |
1866 | ||
1867 | /* End the current relaxable sequence. */ | |
1868 | ||
1869 | static void | |
1870 | relax_end (void) | |
1871 | { | |
1872 | assert (mips_relax.sequence == 2); | |
1873 | relax_close_frag (); | |
1874 | mips_relax.sequence = 0; | |
1875 | } | |
1876 | ||
71400594 RS |
1877 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1878 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1879 | by VR4120 errata. */ | |
4d7206a2 | 1880 | |
71400594 RS |
1881 | static unsigned int |
1882 | classify_vr4120_insn (const char *name) | |
252b5132 | 1883 | { |
71400594 RS |
1884 | if (strncmp (name, "macc", 4) == 0) |
1885 | return FIX_VR4120_MACC; | |
1886 | if (strncmp (name, "dmacc", 5) == 0) | |
1887 | return FIX_VR4120_DMACC; | |
1888 | if (strncmp (name, "mult", 4) == 0) | |
1889 | return FIX_VR4120_MULT; | |
1890 | if (strncmp (name, "dmult", 5) == 0) | |
1891 | return FIX_VR4120_DMULT; | |
1892 | if (strstr (name, "div")) | |
1893 | return FIX_VR4120_DIV; | |
1894 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1895 | return FIX_VR4120_MTHILO; | |
1896 | return NUM_FIX_VR4120_CLASSES; | |
1897 | } | |
252b5132 | 1898 | |
71400594 RS |
1899 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1900 | where INSN1 is the earlier instruction. Return the worst-case value | |
1901 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1902 | |
71400594 RS |
1903 | static unsigned int |
1904 | insns_between (const struct mips_cl_insn *insn1, | |
1905 | const struct mips_cl_insn *insn2) | |
1906 | { | |
1907 | unsigned long pinfo1, pinfo2; | |
1908 | ||
1909 | /* This function needs to know which pinfo flags are set for INSN2 | |
1910 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1911 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1912 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1913 | pinfo1 = insn1->insn_mo->pinfo; | |
1914 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1915 | |
71400594 RS |
1916 | #define INSN2_USES_REG(REG, CLASS) \ |
1917 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1918 | ||
1919 | /* For most targets, write-after-read dependencies on the HI and LO | |
1920 | registers must be separated by at least two instructions. */ | |
1921 | if (!hilo_interlocks) | |
252b5132 | 1922 | { |
71400594 RS |
1923 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1924 | return 2; | |
1925 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1926 | return 2; | |
1927 | } | |
1928 | ||
1929 | /* If we're working around r7000 errata, there must be two instructions | |
1930 | between an mfhi or mflo and any instruction that uses the result. */ | |
1931 | if (mips_7000_hilo_fix | |
1932 | && MF_HILO_INSN (pinfo1) | |
1933 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1934 | return 2; | |
1935 | ||
1936 | /* If working around VR4120 errata, check for combinations that need | |
1937 | a single intervening instruction. */ | |
1938 | if (mips_fix_vr4120) | |
1939 | { | |
1940 | unsigned int class1, class2; | |
252b5132 | 1941 | |
71400594 RS |
1942 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1943 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1944 | { |
71400594 RS |
1945 | if (insn2 == NULL) |
1946 | return 1; | |
1947 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1948 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1949 | return 1; | |
252b5132 | 1950 | } |
71400594 RS |
1951 | } |
1952 | ||
1953 | if (!mips_opts.mips16) | |
1954 | { | |
1955 | /* Check for GPR or coprocessor load delays. All such delays | |
1956 | are on the RT register. */ | |
1957 | /* Itbl support may require additional care here. */ | |
1958 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
1959 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 1960 | { |
71400594 RS |
1961 | know (pinfo1 & INSN_WRITE_GPR_T); |
1962 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
1963 | return 1; | |
1964 | } | |
1965 | ||
1966 | /* Check for generic coprocessor hazards. | |
1967 | ||
1968 | This case is not handled very well. There is no special | |
1969 | knowledge of CP0 handling, and the coprocessors other than | |
1970 | the floating point unit are not distinguished at all. */ | |
1971 | /* Itbl support may require additional care here. FIXME! | |
1972 | Need to modify this to include knowledge about | |
1973 | user specified delays! */ | |
1974 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
1975 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
1976 | { | |
1977 | /* Handle cases where INSN1 writes to a known general coprocessor | |
1978 | register. There must be a one instruction delay before INSN2 | |
1979 | if INSN2 reads that register, otherwise no delay is needed. */ | |
1980 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 1981 | { |
71400594 RS |
1982 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
1983 | return 1; | |
252b5132 | 1984 | } |
71400594 | 1985 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 1986 | { |
71400594 RS |
1987 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
1988 | return 1; | |
252b5132 RH |
1989 | } |
1990 | else | |
1991 | { | |
71400594 RS |
1992 | /* Read-after-write dependencies on the control registers |
1993 | require a two-instruction gap. */ | |
1994 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
1995 | && (pinfo2 & INSN_READ_COND_CODE)) | |
1996 | return 2; | |
1997 | ||
1998 | /* We don't know exactly what INSN1 does. If INSN2 is | |
1999 | also a coprocessor instruction, assume there must be | |
2000 | a one instruction gap. */ | |
2001 | if (pinfo2 & INSN_COP) | |
2002 | return 1; | |
252b5132 RH |
2003 | } |
2004 | } | |
6b76fefe | 2005 | |
71400594 RS |
2006 | /* Check for read-after-write dependencies on the coprocessor |
2007 | control registers in cases where INSN1 does not need a general | |
2008 | coprocessor delay. This means that INSN1 is a floating point | |
2009 | comparison instruction. */ | |
2010 | /* Itbl support may require additional care here. */ | |
2011 | else if (!cop_interlocks | |
2012 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2013 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2014 | return 1; | |
2015 | } | |
6b76fefe | 2016 | |
71400594 | 2017 | #undef INSN2_USES_REG |
6b76fefe | 2018 | |
71400594 RS |
2019 | return 0; |
2020 | } | |
6b76fefe | 2021 | |
7d8e00cf RS |
2022 | /* Return the number of nops that would be needed to work around the |
2023 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2024 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2025 | ||
2026 | static int | |
2027 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2028 | const struct mips_cl_insn *insn) | |
2029 | { | |
2030 | int i, j, reg; | |
2031 | ||
2032 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2033 | are not affected by the errata. */ | |
2034 | if (insn != 0 | |
2035 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2036 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2037 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2038 | return 0; | |
2039 | ||
2040 | /* Search for the first MFLO or MFHI. */ | |
2041 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2042 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2043 | { | |
2044 | /* Extract the destination register. */ | |
2045 | if (mips_opts.mips16) | |
2046 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2047 | else | |
2048 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2049 | ||
2050 | /* No nops are needed if INSN reads that register. */ | |
2051 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2052 | return 0; | |
2053 | ||
2054 | /* ...or if any of the intervening instructions do. */ | |
2055 | for (j = 0; j < i; j++) | |
2056 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2057 | return 0; | |
2058 | ||
2059 | return MAX_VR4130_NOPS - i; | |
2060 | } | |
2061 | return 0; | |
2062 | } | |
2063 | ||
71400594 RS |
2064 | /* Return the number of nops that would be needed if instruction INSN |
2065 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2066 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2067 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2068 | |
71400594 RS |
2069 | static int |
2070 | nops_for_insn (const struct mips_cl_insn *history, | |
2071 | const struct mips_cl_insn *insn) | |
2072 | { | |
2073 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2074 | |
71400594 | 2075 | nops = 0; |
7d8e00cf | 2076 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2077 | if (!history[i].noreorder_p) |
2078 | { | |
2079 | tmp_nops = insns_between (history + i, insn) - i; | |
2080 | if (tmp_nops > nops) | |
2081 | nops = tmp_nops; | |
2082 | } | |
7d8e00cf RS |
2083 | |
2084 | if (mips_fix_vr4130) | |
2085 | { | |
2086 | tmp_nops = nops_for_vr4130 (history, insn); | |
2087 | if (tmp_nops > nops) | |
2088 | nops = tmp_nops; | |
2089 | } | |
2090 | ||
71400594 RS |
2091 | return nops; |
2092 | } | |
252b5132 | 2093 | |
71400594 RS |
2094 | /* The variable arguments provide NUM_INSNS extra instructions that |
2095 | might be added to HISTORY. Return the largest number of nops that | |
2096 | would be needed after the extended sequence. */ | |
252b5132 | 2097 | |
71400594 RS |
2098 | static int |
2099 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2100 | { | |
2101 | va_list args; | |
2102 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2103 | struct mips_cl_insn *cursor; | |
2104 | int nops; | |
2105 | ||
2106 | va_start (args, history); | |
2107 | cursor = buffer + num_insns; | |
2108 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2109 | while (cursor > buffer) | |
2110 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2111 | ||
2112 | nops = nops_for_insn (buffer, NULL); | |
2113 | va_end (args); | |
2114 | return nops; | |
2115 | } | |
252b5132 | 2116 | |
71400594 RS |
2117 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2118 | worst-case delay for the branch target. */ | |
252b5132 | 2119 | |
71400594 RS |
2120 | static int |
2121 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2122 | const struct mips_cl_insn *insn) | |
2123 | { | |
2124 | int nops, tmp_nops; | |
60b63b72 | 2125 | |
71400594 RS |
2126 | nops = nops_for_insn (history, insn); |
2127 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2128 | | INSN_COND_BRANCH_DELAY | |
2129 | | INSN_COND_BRANCH_LIKELY)) | |
2130 | { | |
2131 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2132 | if (tmp_nops > nops) | |
2133 | nops = tmp_nops; | |
2134 | } | |
2135 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2136 | { | |
2137 | tmp_nops = nops_for_sequence (1, history, insn); | |
2138 | if (tmp_nops > nops) | |
2139 | nops = tmp_nops; | |
2140 | } | |
2141 | return nops; | |
2142 | } | |
2143 | ||
2144 | /* Output an instruction. IP is the instruction information. | |
2145 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2146 | RELOC_TYPE. */ | |
2147 | ||
2148 | static void | |
2149 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2150 | bfd_reloc_code_real_type *reloc_type) | |
2151 | { | |
2152 | register unsigned long prev_pinfo, pinfo; | |
2153 | relax_stateT prev_insn_frag_type = 0; | |
2154 | bfd_boolean relaxed_branch = FALSE; | |
2155 | ||
2156 | /* Mark instruction labels in mips16 mode. */ | |
2157 | mips16_mark_labels (); | |
2158 | ||
2159 | prev_pinfo = history[0].insn_mo->pinfo; | |
2160 | pinfo = ip->insn_mo->pinfo; | |
2161 | ||
2162 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2163 | { | |
2164 | /* There are a lot of optimizations we could do that we don't. | |
2165 | In particular, we do not, in general, reorder instructions. | |
2166 | If you use gcc with optimization, it will reorder | |
2167 | instructions and generally do much more optimization then we | |
2168 | do here; repeating all that work in the assembler would only | |
2169 | benefit hand written assembly code, and does not seem worth | |
2170 | it. */ | |
2171 | int nops = (mips_optimize == 0 | |
2172 | ? nops_for_insn (history, NULL) | |
2173 | : nops_for_insn_or_target (history, ip)); | |
2174 | if (nops > 0) | |
252b5132 RH |
2175 | { |
2176 | fragS *old_frag; | |
2177 | unsigned long old_frag_offset; | |
2178 | int i; | |
252b5132 RH |
2179 | |
2180 | old_frag = frag_now; | |
2181 | old_frag_offset = frag_now_fix (); | |
2182 | ||
2183 | for (i = 0; i < nops; i++) | |
2184 | emit_nop (); | |
2185 | ||
2186 | if (listing) | |
2187 | { | |
2188 | listing_prev_line (); | |
2189 | /* We may be at the start of a variant frag. In case we | |
2190 | are, make sure there is enough space for the frag | |
2191 | after the frags created by listing_prev_line. The | |
2192 | argument to frag_grow here must be at least as large | |
2193 | as the argument to all other calls to frag_grow in | |
2194 | this file. We don't have to worry about being in the | |
2195 | middle of a variant frag, because the variants insert | |
2196 | all needed nop instructions themselves. */ | |
2197 | frag_grow (40); | |
2198 | } | |
2199 | ||
404a8071 | 2200 | mips_move_labels (); |
252b5132 RH |
2201 | |
2202 | #ifndef NO_ECOFF_DEBUGGING | |
2203 | if (ECOFF_DEBUGGING) | |
2204 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2205 | #endif | |
2206 | } | |
71400594 RS |
2207 | } |
2208 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2209 | { | |
2210 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2211 | int nops = nops_for_insn_or_target (history, ip); | |
2212 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2213 | |
71400594 RS |
2214 | /* Enforce NOPS as a minimum. */ |
2215 | if (nops > prev_nop_frag_required) | |
2216 | prev_nop_frag_required = nops; | |
252b5132 | 2217 | |
71400594 RS |
2218 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2219 | { | |
2220 | /* Settle for the current number of nops. Update the history | |
2221 | accordingly (for the benefit of any future .set reorder code). */ | |
2222 | prev_nop_frag = NULL; | |
2223 | insert_into_history (prev_nop_frag_since, | |
2224 | prev_nop_frag_holds, NOP_INSN); | |
2225 | } | |
2226 | else | |
2227 | { | |
2228 | /* Allow this instruction to replace one of the nops that was | |
2229 | tentatively added to prev_nop_frag. */ | |
2230 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2231 | prev_nop_frag_holds--; | |
2232 | prev_nop_frag_since++; | |
252b5132 RH |
2233 | } |
2234 | } | |
2235 | ||
58e2ea4d MR |
2236 | #ifdef OBJ_ELF |
2237 | /* The value passed to dwarf2_emit_insn is the distance between | |
2238 | the beginning of the current instruction and the address that | |
2239 | should be recorded in the debug tables. For MIPS16 debug info | |
2240 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2241 | address higher by one than the current. */ | |
2242 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2243 | #endif | |
2244 | ||
895921c9 | 2245 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2246 | if (history[0].frag) |
2247 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2248 | |
4d7206a2 | 2249 | if (address_expr |
0b25d3e6 | 2250 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2251 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2252 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2253 | && mips_relax_branch | |
2254 | /* Don't try branch relaxation within .set nomacro, or within | |
2255 | .set noat if we use $at for PIC computations. If it turns | |
2256 | out that the branch was out-of-range, we'll get an error. */ | |
2257 | && !mips_opts.warn_about_macros | |
2258 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2259 | && !mips_opts.mips16) | |
2260 | { | |
895921c9 | 2261 | relaxed_branch = TRUE; |
1e915849 RS |
2262 | add_relaxed_insn (ip, (relaxed_branch_length |
2263 | (NULL, NULL, | |
2264 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2265 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2266 | : 0)), 4, | |
2267 | RELAX_BRANCH_ENCODE | |
2268 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2269 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2270 | pinfo & INSN_WRITE_GPR_31, | |
2271 | 0), | |
2272 | address_expr->X_add_symbol, | |
2273 | address_expr->X_add_number); | |
4a6a3df4 AO |
2274 | *reloc_type = BFD_RELOC_UNUSED; |
2275 | } | |
2276 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2277 | { |
2278 | /* We need to set up a variant frag. */ | |
2279 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2280 | add_relaxed_insn (ip, 4, 0, |
2281 | RELAX_MIPS16_ENCODE | |
2282 | (*reloc_type - BFD_RELOC_UNUSED, | |
2283 | mips16_small, mips16_ext, | |
2284 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2285 | history[0].mips16_absolute_jump_p), | |
2286 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2287 | } |
252b5132 RH |
2288 | else if (mips_opts.mips16 |
2289 | && ! ip->use_extend | |
f6688943 | 2290 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2291 | { |
2292 | /* Make sure there is enough room to swap this instruction with | |
2293 | a following jump instruction. */ | |
2294 | frag_grow (6); | |
1e915849 | 2295 | add_fixed_insn (ip); |
252b5132 RH |
2296 | } |
2297 | else | |
2298 | { | |
2299 | if (mips_opts.mips16 | |
2300 | && mips_opts.noreorder | |
2301 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2302 | as_warn (_("extended instruction in delay slot")); | |
2303 | ||
4d7206a2 RS |
2304 | if (mips_relax.sequence) |
2305 | { | |
2306 | /* If we've reached the end of this frag, turn it into a variant | |
2307 | frag and record the information for the instructions we've | |
2308 | written so far. */ | |
2309 | if (frag_room () < 4) | |
2310 | relax_close_frag (); | |
2311 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2312 | } | |
2313 | ||
584892a6 RS |
2314 | if (mips_relax.sequence != 2) |
2315 | mips_macro_warning.sizes[0] += 4; | |
2316 | if (mips_relax.sequence != 1) | |
2317 | mips_macro_warning.sizes[1] += 4; | |
2318 | ||
1e915849 RS |
2319 | if (mips_opts.mips16) |
2320 | { | |
2321 | ip->fixed_p = 1; | |
2322 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2323 | } | |
2324 | add_fixed_insn (ip); | |
252b5132 RH |
2325 | } |
2326 | ||
01a3f561 | 2327 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2328 | { |
2329 | if (address_expr->X_op == O_constant) | |
2330 | { | |
f17c130b | 2331 | unsigned int tmp; |
f6688943 TS |
2332 | |
2333 | switch (*reloc_type) | |
252b5132 RH |
2334 | { |
2335 | case BFD_RELOC_32: | |
2336 | ip->insn_opcode |= address_expr->X_add_number; | |
2337 | break; | |
2338 | ||
f6688943 | 2339 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2340 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2341 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2342 | break; |
2343 | ||
2344 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2345 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2346 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2347 | break; |
2348 | ||
2349 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2350 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2351 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2352 | break; |
2353 | ||
2354 | case BFD_RELOC_HI16: | |
2355 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2356 | break; | |
2357 | ||
01a3f561 | 2358 | case BFD_RELOC_UNUSED: |
252b5132 | 2359 | case BFD_RELOC_LO16: |
ed6fb7bd | 2360 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2361 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2362 | break; | |
2363 | ||
2364 | case BFD_RELOC_MIPS_JMP: | |
2365 | if ((address_expr->X_add_number & 3) != 0) | |
2366 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2367 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2368 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2369 | as_bad (_("jump address range overflow (0x%lx)"), |
2370 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2371 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2372 | break; | |
2373 | ||
2374 | case BFD_RELOC_MIPS16_JMP: | |
2375 | if ((address_expr->X_add_number & 3) != 0) | |
2376 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2377 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2378 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2379 | as_bad (_("jump address range overflow (0x%lx)"), |
2380 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2381 | ip->insn_opcode |= |
2382 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2383 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2384 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2385 | break; | |
2386 | ||
252b5132 RH |
2387 | case BFD_RELOC_16_PCREL_S2: |
2388 | goto need_reloc; | |
2389 | ||
2390 | default: | |
2391 | internalError (); | |
2392 | } | |
2393 | } | |
01a3f561 | 2394 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2395 | need_reloc: |
4d7206a2 RS |
2396 | { |
2397 | reloc_howto_type *howto; | |
2398 | int i; | |
34ce925e | 2399 | |
4d7206a2 RS |
2400 | /* In a compound relocation, it is the final (outermost) |
2401 | operator that determines the relocated field. */ | |
2402 | for (i = 1; i < 3; i++) | |
2403 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2404 | break; | |
34ce925e | 2405 | |
4d7206a2 | 2406 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2407 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2408 | bfd_get_reloc_size (howto), | |
2409 | address_expr, | |
2410 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2411 | reloc_type[0]); | |
4d7206a2 RS |
2412 | |
2413 | /* These relocations can have an addend that won't fit in | |
2414 | 4 octets for 64bit assembly. */ | |
2415 | if (HAVE_64BIT_GPRS | |
2416 | && ! howto->partial_inplace | |
2417 | && (reloc_type[0] == BFD_RELOC_16 | |
2418 | || reloc_type[0] == BFD_RELOC_32 | |
2419 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2420 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2421 | || reloc_type[0] == BFD_RELOC_LO16 | |
2422 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2423 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2424 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2425 | || reloc_type[0] == BFD_RELOC_64 | |
2426 | || reloc_type[0] == BFD_RELOC_CTOR | |
2427 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2428 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2429 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2430 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2431 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2432 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2433 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2434 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2435 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2436 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2437 | |
2438 | if (mips_relax.sequence) | |
2439 | { | |
2440 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2441 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2442 | } |
2443 | else if (reloc_needs_lo_p (*reloc_type)) | |
2444 | { | |
2445 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2446 | |
4d7206a2 RS |
2447 | /* Reuse the last entry if it already has a matching %lo. */ |
2448 | hi_fixup = mips_hi_fixup_list; | |
2449 | if (hi_fixup == 0 | |
2450 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2451 | { | |
2452 | hi_fixup = ((struct mips_hi_fixup *) | |
2453 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2454 | hi_fixup->next = mips_hi_fixup_list; | |
2455 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2456 | } |
1e915849 | 2457 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2458 | hi_fixup->seg = now_seg; |
2459 | } | |
f6688943 | 2460 | |
4d7206a2 RS |
2461 | /* Add fixups for the second and third relocations, if given. |
2462 | Note that the ABI allows the second relocation to be | |
2463 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2464 | moment we only use RSS_UNDEF, but we could add support | |
2465 | for the others if it ever becomes necessary. */ | |
2466 | for (i = 1; i < 3; i++) | |
2467 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2468 | { | |
1e915849 RS |
2469 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2470 | ip->fixp[0]->fx_size, NULL, 0, | |
2471 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2472 | |
2473 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2474 | ip->fixp[0]->fx_tcbit = 1; |
2475 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2476 | } |
252b5132 RH |
2477 | } |
2478 | } | |
1e915849 | 2479 | install_insn (ip); |
252b5132 RH |
2480 | |
2481 | /* Update the register mask information. */ | |
2482 | if (! mips_opts.mips16) | |
2483 | { | |
2484 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2485 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2486 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2487 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2488 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2489 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2490 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2491 | mips_gprmask |= 1 << RA; |
252b5132 | 2492 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2493 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2494 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2495 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2496 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2497 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2498 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2499 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2500 | if (pinfo & INSN_COP) |
2501 | { | |
bdaaa2e1 KH |
2502 | /* We don't keep enough information to sort these cases out. |
2503 | The itbl support does keep this information however, although | |
2504 | we currently don't support itbl fprmats as part of the cop | |
2505 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2506 | } |
2507 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2508 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2509 | } |
2510 | else | |
2511 | { | |
2512 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2513 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2514 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2515 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2516 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2517 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2518 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2519 | mips_gprmask |= 1 << TREG; | |
2520 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2521 | mips_gprmask |= 1 << SP; | |
2522 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2523 | mips_gprmask |= 1 << RA; | |
2524 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2525 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2526 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2527 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2528 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2529 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2530 | } |
2531 | ||
4d7206a2 | 2532 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2533 | { |
2534 | /* Filling the branch delay slot is more complex. We try to | |
2535 | switch the branch with the previous instruction, which we can | |
2536 | do if the previous instruction does not set up a condition | |
2537 | that the branch tests and if the branch is not itself the | |
2538 | target of any branch. */ | |
2539 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2540 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2541 | { | |
2542 | if (mips_optimize < 2 | |
2543 | /* If we have seen .set volatile or .set nomove, don't | |
2544 | optimize. */ | |
2545 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2546 | /* We can't swap if the previous instruction's position |
2547 | is fixed. */ | |
2548 | || history[0].fixed_p | |
252b5132 RH |
2549 | /* If the previous previous insn was in a .set |
2550 | noreorder, we can't swap. Actually, the MIPS | |
2551 | assembler will swap in this situation. However, gcc | |
2552 | configured -with-gnu-as will generate code like | |
2553 | .set noreorder | |
2554 | lw $4,XXX | |
2555 | .set reorder | |
2556 | INSN | |
2557 | bne $4,$0,foo | |
2558 | in which we can not swap the bne and INSN. If gcc is | |
2559 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2560 | .set pseudo-ops. */ |
47e39b9d | 2561 | || history[1].noreorder_p |
252b5132 RH |
2562 | /* If the branch is itself the target of a branch, we |
2563 | can not swap. We cheat on this; all we check for is | |
2564 | whether there is a label on this instruction. If | |
2565 | there are any branches to anything other than a | |
2566 | label, users must use .set noreorder. */ | |
2567 | || insn_labels != NULL | |
895921c9 MR |
2568 | /* If the previous instruction is in a variant frag |
2569 | other than this branch's one, we cannot do the swap. | |
2570 | This does not apply to the mips16, which uses variant | |
2571 | frags for different purposes. */ | |
252b5132 | 2572 | || (! mips_opts.mips16 |
895921c9 | 2573 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2574 | /* Check for conflicts between the branch and the instructions |
2575 | before the candidate delay slot. */ | |
2576 | || nops_for_insn (history + 1, ip) > 0 | |
2577 | /* Check for conflicts between the swapped sequence and the | |
2578 | target of the branch. */ | |
2579 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2580 | /* We do not swap with a trap instruction, since it |
2581 | complicates trap handlers to have the trap | |
2582 | instruction be in a delay slot. */ | |
2583 | || (prev_pinfo & INSN_TRAP) | |
2584 | /* If the branch reads a register that the previous | |
2585 | instruction sets, we can not swap. */ | |
2586 | || (! mips_opts.mips16 | |
2587 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2588 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2589 | MIPS_GR_REG)) |
2590 | || (! mips_opts.mips16 | |
2591 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2592 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2593 | MIPS_GR_REG)) |
2594 | || (mips_opts.mips16 | |
2595 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2596 | && (insn_uses_reg |
2597 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2598 | MIPS16_REG))) | |
252b5132 | 2599 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2600 | && (insn_uses_reg |
2601 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2602 | MIPS16_REG))) | |
252b5132 | 2603 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2604 | && (insn_uses_reg |
2605 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2606 | MIPS16_REG))) | |
252b5132 RH |
2607 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2608 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2609 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2610 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2611 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2612 | && insn_uses_reg (ip, | |
47e39b9d RS |
2613 | MIPS16OP_EXTRACT_REG32R |
2614 | (history[0].insn_opcode), | |
252b5132 RH |
2615 | MIPS_GR_REG)))) |
2616 | /* If the branch writes a register that the previous | |
2617 | instruction sets, we can not swap (we know that | |
2618 | branches write only to RD or to $31). */ | |
2619 | || (! mips_opts.mips16 | |
2620 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2621 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2622 | && (EXTRACT_OPERAND (RT, history[0]) |
2623 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2624 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2625 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2626 | || (! mips_opts.mips16 |
2627 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2628 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2629 | && (EXTRACT_OPERAND (RD, history[0]) |
2630 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2631 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2632 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2633 | || (mips_opts.mips16 |
2634 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2635 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2636 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2637 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2638 | == RA)))) |
2639 | /* If the branch writes a register that the previous | |
2640 | instruction reads, we can not swap (we know that | |
2641 | branches only write to RD or to $31). */ | |
2642 | || (! mips_opts.mips16 | |
2643 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2644 | && insn_uses_reg (&history[0], |
bf12938e | 2645 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2646 | MIPS_GR_REG)) |
2647 | || (! mips_opts.mips16 | |
2648 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2649 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2650 | || (mips_opts.mips16 |
2651 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2652 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2653 | /* If one instruction sets a condition code and the |
2654 | other one uses a condition code, we can not swap. */ | |
2655 | || ((pinfo & INSN_READ_COND_CODE) | |
2656 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2657 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2658 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2659 | /* If the previous instruction uses the PC, we can not | |
2660 | swap. */ | |
2661 | || (mips_opts.mips16 | |
2662 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2663 | /* If the previous instruction had a fixup in mips16 |
2664 | mode, we can not swap. This normally means that the | |
2665 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2666 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2667 | /* If the previous instruction is a sync, sync.l, or |
2668 | sync.p, we can not swap. */ | |
f173e82e | 2669 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2670 | { |
2671 | /* We could do even better for unconditional branches to | |
2672 | portions of this object file; we could pick up the | |
2673 | instruction at the destination, put it in the delay | |
2674 | slot, and bump the destination address. */ | |
1e915849 | 2675 | insert_into_history (0, 1, ip); |
252b5132 | 2676 | emit_nop (); |
dd22970f ILT |
2677 | if (mips_relax.sequence) |
2678 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2679 | } |
2680 | else | |
2681 | { | |
2682 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2683 | struct mips_cl_insn delay = history[0]; |
2684 | if (mips_opts.mips16) | |
252b5132 | 2685 | { |
1e915849 RS |
2686 | know (delay.frag == ip->frag); |
2687 | move_insn (ip, delay.frag, delay.where); | |
2688 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
2689 | } | |
2690 | else if (relaxed_branch) | |
2691 | { | |
2692 | /* Add the delay slot instruction to the end of the | |
2693 | current frag and shrink the fixed part of the | |
2694 | original frag. If the branch occupies the tail of | |
2695 | the latter, move it backwards to cover the gap. */ | |
2696 | delay.frag->fr_fix -= 4; | |
2697 | if (delay.frag == ip->frag) | |
2698 | move_insn (ip, ip->frag, ip->where - 4); | |
2699 | add_fixed_insn (&delay); | |
252b5132 RH |
2700 | } |
2701 | else | |
2702 | { | |
1e915849 RS |
2703 | move_insn (&delay, ip->frag, ip->where); |
2704 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2705 | } |
1e915849 RS |
2706 | history[0] = *ip; |
2707 | delay.fixed_p = 1; | |
2708 | insert_into_history (0, 1, &delay); | |
252b5132 | 2709 | } |
252b5132 RH |
2710 | |
2711 | /* If that was an unconditional branch, forget the previous | |
2712 | insn information. */ | |
2713 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2714 | mips_no_prev_insn (); |
252b5132 RH |
2715 | } |
2716 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2717 | { | |
2718 | /* We don't yet optimize a branch likely. What we should do | |
2719 | is look at the target, copy the instruction found there | |
2720 | into the delay slot, and increment the branch to jump to | |
2721 | the next instruction. */ | |
1e915849 | 2722 | insert_into_history (0, 1, ip); |
252b5132 | 2723 | emit_nop (); |
252b5132 RH |
2724 | } |
2725 | else | |
1e915849 | 2726 | insert_into_history (0, 1, ip); |
252b5132 | 2727 | } |
1e915849 RS |
2728 | else |
2729 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2730 | |
2731 | /* We just output an insn, so the next one doesn't have a label. */ | |
2732 | mips_clear_insn_labels (); | |
252b5132 RH |
2733 | } |
2734 | ||
7d10b47d | 2735 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2736 | |
2737 | static void | |
7d10b47d | 2738 | mips_no_prev_insn (void) |
252b5132 | 2739 | { |
7d10b47d RS |
2740 | prev_nop_frag = NULL; |
2741 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2742 | mips_clear_insn_labels (); |
2743 | } | |
2744 | ||
7d10b47d RS |
2745 | /* This function must be called before we emit something other than |
2746 | instructions. It is like mips_no_prev_insn except that it inserts | |
2747 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2748 | |
7d10b47d RS |
2749 | void |
2750 | mips_emit_delays (void) | |
252b5132 RH |
2751 | { |
2752 | if (! mips_opts.noreorder) | |
2753 | { | |
71400594 | 2754 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2755 | if (nops > 0) |
2756 | { | |
7d10b47d RS |
2757 | while (nops-- > 0) |
2758 | add_fixed_insn (NOP_INSN); | |
2759 | mips_move_labels (); | |
2760 | } | |
2761 | } | |
2762 | mips_no_prev_insn (); | |
2763 | } | |
2764 | ||
2765 | /* Start a (possibly nested) noreorder block. */ | |
2766 | ||
2767 | static void | |
2768 | start_noreorder (void) | |
2769 | { | |
2770 | if (mips_opts.noreorder == 0) | |
2771 | { | |
2772 | unsigned int i; | |
2773 | int nops; | |
2774 | ||
2775 | /* None of the instructions before the .set noreorder can be moved. */ | |
2776 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2777 | history[i].fixed_p = 1; | |
2778 | ||
2779 | /* Insert any nops that might be needed between the .set noreorder | |
2780 | block and the previous instructions. We will later remove any | |
2781 | nops that turn out not to be needed. */ | |
2782 | nops = nops_for_insn (history, NULL); | |
2783 | if (nops > 0) | |
2784 | { | |
2785 | if (mips_optimize != 0) | |
252b5132 RH |
2786 | { |
2787 | /* Record the frag which holds the nop instructions, so | |
2788 | that we can remove them if we don't need them. */ | |
2789 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2790 | prev_nop_frag = frag_now; | |
2791 | prev_nop_frag_holds = nops; | |
2792 | prev_nop_frag_required = 0; | |
2793 | prev_nop_frag_since = 0; | |
2794 | } | |
2795 | ||
2796 | for (; nops > 0; --nops) | |
1e915849 | 2797 | add_fixed_insn (NOP_INSN); |
252b5132 | 2798 | |
7d10b47d RS |
2799 | /* Move on to a new frag, so that it is safe to simply |
2800 | decrease the size of prev_nop_frag. */ | |
2801 | frag_wane (frag_now); | |
2802 | frag_new (0); | |
404a8071 | 2803 | mips_move_labels (); |
252b5132 | 2804 | } |
7d10b47d RS |
2805 | mips16_mark_labels (); |
2806 | mips_clear_insn_labels (); | |
252b5132 | 2807 | } |
7d10b47d RS |
2808 | mips_opts.noreorder++; |
2809 | mips_any_noreorder = 1; | |
2810 | } | |
252b5132 | 2811 | |
7d10b47d | 2812 | /* End a nested noreorder block. */ |
252b5132 | 2813 | |
7d10b47d RS |
2814 | static void |
2815 | end_noreorder (void) | |
2816 | { | |
2817 | mips_opts.noreorder--; | |
2818 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2819 | { | |
2820 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2821 | handling nop insertion the .set reorder way. */ | |
2822 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2823 | * (mips_opts.mips16 ? 2 : 4)); | |
2824 | insert_into_history (prev_nop_frag_since, | |
2825 | prev_nop_frag_required, NOP_INSN); | |
2826 | prev_nop_frag = NULL; | |
2827 | } | |
252b5132 RH |
2828 | } |
2829 | ||
584892a6 RS |
2830 | /* Set up global variables for the start of a new macro. */ |
2831 | ||
2832 | static void | |
2833 | macro_start (void) | |
2834 | { | |
2835 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2836 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2837 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2838 | & (INSN_UNCOND_BRANCH_DELAY |
2839 | | INSN_COND_BRANCH_DELAY | |
2840 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2841 | } | |
2842 | ||
2843 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2844 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2845 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2846 | ||
2847 | static const char * | |
2848 | macro_warning (relax_substateT subtype) | |
2849 | { | |
2850 | if (subtype & RELAX_DELAY_SLOT) | |
2851 | return _("Macro instruction expanded into multiple instructions" | |
2852 | " in a branch delay slot"); | |
2853 | else if (subtype & RELAX_NOMACRO) | |
2854 | return _("Macro instruction expanded into multiple instructions"); | |
2855 | else | |
2856 | return 0; | |
2857 | } | |
2858 | ||
2859 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2860 | ||
2861 | static void | |
2862 | macro_end (void) | |
2863 | { | |
2864 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2865 | { | |
2866 | relax_substateT subtype; | |
2867 | ||
2868 | /* Set up the relaxation warning flags. */ | |
2869 | subtype = 0; | |
2870 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2871 | subtype |= RELAX_SECOND_LONGER; | |
2872 | if (mips_opts.warn_about_macros) | |
2873 | subtype |= RELAX_NOMACRO; | |
2874 | if (mips_macro_warning.delay_slot_p) | |
2875 | subtype |= RELAX_DELAY_SLOT; | |
2876 | ||
2877 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2878 | { | |
2879 | /* Either the macro has a single implementation or both | |
2880 | implementations are longer than 4 bytes. Emit the | |
2881 | warning now. */ | |
2882 | const char *msg = macro_warning (subtype); | |
2883 | if (msg != 0) | |
2884 | as_warn (msg); | |
2885 | } | |
2886 | else | |
2887 | { | |
2888 | /* One implementation might need a warning but the other | |
2889 | definitely doesn't. */ | |
2890 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2891 | } | |
2892 | } | |
2893 | } | |
2894 | ||
6e1304d8 RS |
2895 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2896 | The first argument in *ARGS will be either the code for a single | |
2897 | relocation or -1 followed by the three codes that make up a | |
2898 | composite relocation. */ | |
2899 | ||
2900 | static void | |
2901 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2902 | { | |
2903 | int i, next; | |
2904 | ||
2905 | next = va_arg (*args, int); | |
2906 | if (next >= 0) | |
2907 | r[0] = (bfd_reloc_code_real_type) next; | |
2908 | else | |
2909 | for (i = 0; i < 3; i++) | |
2910 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2911 | } | |
2912 | ||
252b5132 RH |
2913 | /* Build an instruction created by a macro expansion. This is passed |
2914 | a pointer to the count of instructions created so far, an | |
2915 | expression, the name of the instruction to build, an operand format | |
2916 | string, and corresponding arguments. */ | |
2917 | ||
252b5132 | 2918 | static void |
67c0d1eb | 2919 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2920 | { |
1e915849 | 2921 | const struct mips_opcode *mo; |
252b5132 | 2922 | struct mips_cl_insn insn; |
f6688943 | 2923 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2924 | va_list args; |
252b5132 | 2925 | |
252b5132 | 2926 | va_start (args, fmt); |
252b5132 | 2927 | |
252b5132 RH |
2928 | if (mips_opts.mips16) |
2929 | { | |
67c0d1eb | 2930 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2931 | va_end (args); |
2932 | return; | |
2933 | } | |
2934 | ||
f6688943 TS |
2935 | r[0] = BFD_RELOC_UNUSED; |
2936 | r[1] = BFD_RELOC_UNUSED; | |
2937 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2938 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2939 | assert (mo); | |
2940 | assert (strcmp (name, mo->name) == 0); | |
2941 | ||
2942 | /* Search until we get a match for NAME. It is assumed here that | |
2943 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2944 | while (strcmp (fmt, mo->args) != 0 | |
2945 | || mo->pinfo == INSN_MACRO | |
2946 | || !OPCODE_IS_MEMBER (mo, | |
2947 | (mips_opts.isa | |
2948 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2949 | mips_opts.arch) |
1e915849 RS |
2950 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2951 | { | |
2952 | ++mo; | |
2953 | assert (mo->name); | |
2954 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2955 | } |
2956 | ||
1e915849 | 2957 | create_insn (&insn, mo); |
252b5132 RH |
2958 | for (;;) |
2959 | { | |
2960 | switch (*fmt++) | |
2961 | { | |
2962 | case '\0': | |
2963 | break; | |
2964 | ||
2965 | case ',': | |
2966 | case '(': | |
2967 | case ')': | |
2968 | continue; | |
2969 | ||
5f74bc13 CD |
2970 | case '+': |
2971 | switch (*fmt++) | |
2972 | { | |
2973 | case 'A': | |
2974 | case 'E': | |
bf12938e | 2975 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
2976 | continue; |
2977 | ||
2978 | case 'B': | |
2979 | case 'F': | |
2980 | /* Note that in the macro case, these arguments are already | |
2981 | in MSB form. (When handling the instruction in the | |
2982 | non-macro case, these arguments are sizes from which | |
2983 | MSB values must be calculated.) */ | |
bf12938e | 2984 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
2985 | continue; |
2986 | ||
2987 | case 'C': | |
2988 | case 'G': | |
2989 | case 'H': | |
2990 | /* Note that in the macro case, these arguments are already | |
2991 | in MSBD form. (When handling the instruction in the | |
2992 | non-macro case, these arguments are sizes from which | |
2993 | MSBD values must be calculated.) */ | |
bf12938e | 2994 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
2995 | continue; |
2996 | ||
2997 | default: | |
2998 | internalError (); | |
2999 | } | |
3000 | continue; | |
3001 | ||
252b5132 RH |
3002 | case 't': |
3003 | case 'w': | |
3004 | case 'E': | |
bf12938e | 3005 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3006 | continue; |
3007 | ||
3008 | case 'c': | |
bf12938e | 3009 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3010 | continue; |
3011 | ||
252b5132 RH |
3012 | case 'T': |
3013 | case 'W': | |
bf12938e | 3014 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3015 | continue; |
3016 | ||
3017 | case 'd': | |
3018 | case 'G': | |
af7ee8bf | 3019 | case 'K': |
bf12938e | 3020 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3021 | continue; |
3022 | ||
4372b673 NC |
3023 | case 'U': |
3024 | { | |
3025 | int tmp = va_arg (args, int); | |
3026 | ||
bf12938e RS |
3027 | INSERT_OPERAND (RT, insn, tmp); |
3028 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3029 | continue; |
4372b673 NC |
3030 | } |
3031 | ||
252b5132 RH |
3032 | case 'V': |
3033 | case 'S': | |
bf12938e | 3034 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3035 | continue; |
3036 | ||
3037 | case 'z': | |
3038 | continue; | |
3039 | ||
3040 | case '<': | |
bf12938e | 3041 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3042 | continue; |
3043 | ||
3044 | case 'D': | |
bf12938e | 3045 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3046 | continue; |
3047 | ||
3048 | case 'B': | |
bf12938e | 3049 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3050 | continue; |
3051 | ||
4372b673 | 3052 | case 'J': |
bf12938e | 3053 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3054 | continue; |
3055 | ||
252b5132 | 3056 | case 'q': |
bf12938e | 3057 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3058 | continue; |
3059 | ||
3060 | case 'b': | |
3061 | case 's': | |
3062 | case 'r': | |
3063 | case 'v': | |
bf12938e | 3064 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3065 | continue; |
3066 | ||
3067 | case 'i': | |
3068 | case 'j': | |
3069 | case 'o': | |
6e1304d8 | 3070 | macro_read_relocs (&args, r); |
cdf6fd85 | 3071 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3072 | || *r == BFD_RELOC_MIPS_LITERAL |
3073 | || *r == BFD_RELOC_MIPS_HIGHER | |
3074 | || *r == BFD_RELOC_HI16_S | |
3075 | || *r == BFD_RELOC_LO16 | |
3076 | || *r == BFD_RELOC_MIPS_GOT16 | |
3077 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3078 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3079 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3080 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3081 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3082 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3083 | continue; |
3084 | ||
3085 | case 'u': | |
6e1304d8 | 3086 | macro_read_relocs (&args, r); |
252b5132 RH |
3087 | assert (ep != NULL |
3088 | && (ep->X_op == O_constant | |
3089 | || (ep->X_op == O_symbol | |
f6688943 TS |
3090 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3091 | || *r == BFD_RELOC_HI16_S | |
3092 | || *r == BFD_RELOC_HI16 | |
3093 | || *r == BFD_RELOC_GPREL16 | |
3094 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3095 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3096 | continue; |
3097 | ||
3098 | case 'p': | |
3099 | assert (ep != NULL); | |
3100 | /* | |
3101 | * This allows macro() to pass an immediate expression for | |
3102 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3103 | * Note that the expression still might come from the assembly |
3104 | * input, in which case the value is not checked for range nor | |
3105 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3106 | */ |
3107 | if (ep->X_op == O_constant) | |
3108 | { | |
3109 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3110 | ep = NULL; | |
3111 | } | |
3112 | else | |
0b25d3e6 | 3113 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3114 | continue; |
3115 | ||
3116 | case 'a': | |
3117 | assert (ep != NULL); | |
f6688943 | 3118 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3119 | continue; |
3120 | ||
3121 | case 'C': | |
3122 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3123 | continue; | |
3124 | ||
3125 | default: | |
3126 | internalError (); | |
3127 | } | |
3128 | break; | |
3129 | } | |
3130 | va_end (args); | |
f6688943 | 3131 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3132 | |
4d7206a2 | 3133 | append_insn (&insn, ep, r); |
252b5132 RH |
3134 | } |
3135 | ||
3136 | static void | |
67c0d1eb | 3137 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3138 | va_list args) |
252b5132 | 3139 | { |
1e915849 | 3140 | struct mips_opcode *mo; |
252b5132 | 3141 | struct mips_cl_insn insn; |
f6688943 TS |
3142 | bfd_reloc_code_real_type r[3] |
3143 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3144 | |
1e915849 RS |
3145 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3146 | assert (mo); | |
3147 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3148 | |
1e915849 | 3149 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3150 | { |
1e915849 RS |
3151 | ++mo; |
3152 | assert (mo->name); | |
3153 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3154 | } |
3155 | ||
1e915849 | 3156 | create_insn (&insn, mo); |
252b5132 RH |
3157 | for (;;) |
3158 | { | |
3159 | int c; | |
3160 | ||
3161 | c = *fmt++; | |
3162 | switch (c) | |
3163 | { | |
3164 | case '\0': | |
3165 | break; | |
3166 | ||
3167 | case ',': | |
3168 | case '(': | |
3169 | case ')': | |
3170 | continue; | |
3171 | ||
3172 | case 'y': | |
3173 | case 'w': | |
bf12938e | 3174 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3175 | continue; |
3176 | ||
3177 | case 'x': | |
3178 | case 'v': | |
bf12938e | 3179 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3180 | continue; |
3181 | ||
3182 | case 'z': | |
bf12938e | 3183 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3184 | continue; |
3185 | ||
3186 | case 'Z': | |
bf12938e | 3187 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3188 | continue; |
3189 | ||
3190 | case '0': | |
3191 | case 'S': | |
3192 | case 'P': | |
3193 | case 'R': | |
3194 | continue; | |
3195 | ||
3196 | case 'X': | |
bf12938e | 3197 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3198 | continue; |
3199 | ||
3200 | case 'Y': | |
3201 | { | |
3202 | int regno; | |
3203 | ||
3204 | regno = va_arg (args, int); | |
3205 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3206 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3207 | } | |
3208 | continue; | |
3209 | ||
3210 | case '<': | |
3211 | case '>': | |
3212 | case '4': | |
3213 | case '5': | |
3214 | case 'H': | |
3215 | case 'W': | |
3216 | case 'D': | |
3217 | case 'j': | |
3218 | case '8': | |
3219 | case 'V': | |
3220 | case 'C': | |
3221 | case 'U': | |
3222 | case 'k': | |
3223 | case 'K': | |
3224 | case 'p': | |
3225 | case 'q': | |
3226 | { | |
3227 | assert (ep != NULL); | |
3228 | ||
3229 | if (ep->X_op != O_constant) | |
874e8986 | 3230 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3231 | else |
3232 | { | |
b34976b6 AM |
3233 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3234 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3235 | &insn.extend); |
252b5132 | 3236 | ep = NULL; |
f6688943 | 3237 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3238 | } |
3239 | } | |
3240 | continue; | |
3241 | ||
3242 | case '6': | |
bf12938e | 3243 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3244 | continue; |
3245 | } | |
3246 | ||
3247 | break; | |
3248 | } | |
3249 | ||
f6688943 | 3250 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3251 | |
4d7206a2 | 3252 | append_insn (&insn, ep, r); |
252b5132 RH |
3253 | } |
3254 | ||
438c16b8 TS |
3255 | /* |
3256 | * Generate a "jalr" instruction with a relocation hint to the called | |
3257 | * function. This occurs in NewABI PIC code. | |
3258 | */ | |
3259 | static void | |
67c0d1eb | 3260 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3261 | { |
685736be | 3262 | char *f = NULL; |
b34976b6 | 3263 | |
438c16b8 | 3264 | if (HAVE_NEWABI) |
f21f8242 | 3265 | { |
cc3d92a5 | 3266 | frag_grow (8); |
f21f8242 AO |
3267 | f = frag_more (0); |
3268 | } | |
67c0d1eb | 3269 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3270 | if (HAVE_NEWABI) |
f21f8242 | 3271 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3272 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3273 | } |
3274 | ||
252b5132 RH |
3275 | /* |
3276 | * Generate a "lui" instruction. | |
3277 | */ | |
3278 | static void | |
67c0d1eb | 3279 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3280 | { |
3281 | expressionS high_expr; | |
1e915849 | 3282 | const struct mips_opcode *mo; |
252b5132 | 3283 | struct mips_cl_insn insn; |
f6688943 TS |
3284 | bfd_reloc_code_real_type r[3] |
3285 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3286 | const char *name = "lui"; |
3287 | const char *fmt = "t,u"; | |
252b5132 RH |
3288 | |
3289 | assert (! mips_opts.mips16); | |
3290 | ||
4d7206a2 | 3291 | high_expr = *ep; |
252b5132 RH |
3292 | |
3293 | if (high_expr.X_op == O_constant) | |
3294 | { | |
3295 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3296 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3297 | >> 16) & 0xffff; | |
f6688943 | 3298 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3299 | } |
78e1bb40 | 3300 | else |
252b5132 RH |
3301 | { |
3302 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3303 | /* _gp_disp is a special case, used from s_cpload. |
3304 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3305 | assert (mips_pic == NO_PIC |
78e1bb40 | 3306 | || (! HAVE_NEWABI |
aa6975fb ILT |
3307 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3308 | || (! mips_in_shared | |
bbe506e8 TS |
3309 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3310 | "__gnu_local_gp") == 0)); | |
f6688943 | 3311 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3312 | } |
3313 | ||
1e915849 RS |
3314 | mo = hash_find (op_hash, name); |
3315 | assert (strcmp (name, mo->name) == 0); | |
3316 | assert (strcmp (fmt, mo->args) == 0); | |
3317 | create_insn (&insn, mo); | |
252b5132 | 3318 | |
bf12938e RS |
3319 | insn.insn_opcode = insn.insn_mo->match; |
3320 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3321 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3322 | { |
3323 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3324 | append_insn (&insn, NULL, r); |
252b5132 RH |
3325 | } |
3326 | else | |
4d7206a2 | 3327 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3328 | } |
3329 | ||
885add95 CD |
3330 | /* Generate a sequence of instructions to do a load or store from a constant |
3331 | offset off of a base register (breg) into/from a target register (treg), | |
3332 | using AT if necessary. */ | |
3333 | static void | |
67c0d1eb RS |
3334 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3335 | int treg, int breg, int dbl) | |
885add95 CD |
3336 | { |
3337 | assert (ep->X_op == O_constant); | |
3338 | ||
256ab948 | 3339 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3340 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3341 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3342 | { |
d17e7bce | 3343 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3344 | as_bad (_("constant too large")); |
ae826530 | 3345 | |
1b8e29e5 TS |
3346 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3347 | - 0x80000000); | |
ae826530 | 3348 | } |
256ab948 | 3349 | |
67c1ffbe | 3350 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3351 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3352 | as_warn (_("operand overflow")); |
3353 | ||
3354 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3355 | { | |
3356 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3357 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3358 | } |
3359 | else | |
3360 | { | |
3361 | /* 32-bit offset, need multiple instructions and AT, like: | |
3362 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3363 | addu $tempreg,$tempreg,$breg | |
3364 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3365 | to handle the complete offset. */ | |
67c0d1eb RS |
3366 | macro_build_lui (ep, AT); |
3367 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3368 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3369 | |
3370 | if (mips_opts.noat) | |
8fc2e39e | 3371 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3372 | } |
3373 | } | |
3374 | ||
252b5132 RH |
3375 | /* set_at() |
3376 | * Generates code to set the $at register to true (one) | |
3377 | * if reg is less than the immediate expression. | |
3378 | */ | |
3379 | static void | |
67c0d1eb | 3380 | set_at (int reg, int unsignedp) |
252b5132 RH |
3381 | { |
3382 | if (imm_expr.X_op == O_constant | |
3383 | && imm_expr.X_add_number >= -0x8000 | |
3384 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3385 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3386 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3387 | else |
3388 | { | |
67c0d1eb RS |
3389 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3390 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3391 | } |
3392 | } | |
3393 | ||
13757d0c TS |
3394 | static void |
3395 | normalize_constant_expr (expressionS *ex) | |
3396 | { | |
3397 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3398 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3399 | - 0x80000000); | |
3400 | } | |
3401 | ||
252b5132 RH |
3402 | /* Warn if an expression is not a constant. */ |
3403 | ||
3404 | static void | |
17a2f251 | 3405 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3406 | { |
3407 | if (ex->X_op == O_big) | |
3408 | as_bad (_("unsupported large constant")); | |
3409 | else if (ex->X_op != O_constant) | |
3410 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3411 | |
3412 | normalize_constant_expr (ex); | |
252b5132 RH |
3413 | } |
3414 | ||
3415 | /* Count the leading zeroes by performing a binary chop. This is a | |
3416 | bulky bit of source, but performance is a LOT better for the | |
3417 | majority of values than a simple loop to count the bits: | |
3418 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3419 | if ((v) & (1 << (31 - lcnt))) | |
3420 | break; | |
3421 | However it is not code size friendly, and the gain will drop a bit | |
3422 | on certain cached systems. | |
3423 | */ | |
3424 | #define COUNT_TOP_ZEROES(v) \ | |
3425 | (((v) & ~0xffff) == 0 \ | |
3426 | ? ((v) & ~0xff) == 0 \ | |
3427 | ? ((v) & ~0xf) == 0 \ | |
3428 | ? ((v) & ~0x3) == 0 \ | |
3429 | ? ((v) & ~0x1) == 0 \ | |
3430 | ? !(v) \ | |
3431 | ? 32 \ | |
3432 | : 31 \ | |
3433 | : 30 \ | |
3434 | : ((v) & ~0x7) == 0 \ | |
3435 | ? 29 \ | |
3436 | : 28 \ | |
3437 | : ((v) & ~0x3f) == 0 \ | |
3438 | ? ((v) & ~0x1f) == 0 \ | |
3439 | ? 27 \ | |
3440 | : 26 \ | |
3441 | : ((v) & ~0x7f) == 0 \ | |
3442 | ? 25 \ | |
3443 | : 24 \ | |
3444 | : ((v) & ~0xfff) == 0 \ | |
3445 | ? ((v) & ~0x3ff) == 0 \ | |
3446 | ? ((v) & ~0x1ff) == 0 \ | |
3447 | ? 23 \ | |
3448 | : 22 \ | |
3449 | : ((v) & ~0x7ff) == 0 \ | |
3450 | ? 21 \ | |
3451 | : 20 \ | |
3452 | : ((v) & ~0x3fff) == 0 \ | |
3453 | ? ((v) & ~0x1fff) == 0 \ | |
3454 | ? 19 \ | |
3455 | : 18 \ | |
3456 | : ((v) & ~0x7fff) == 0 \ | |
3457 | ? 17 \ | |
3458 | : 16 \ | |
3459 | : ((v) & ~0xffffff) == 0 \ | |
3460 | ? ((v) & ~0xfffff) == 0 \ | |
3461 | ? ((v) & ~0x3ffff) == 0 \ | |
3462 | ? ((v) & ~0x1ffff) == 0 \ | |
3463 | ? 15 \ | |
3464 | : 14 \ | |
3465 | : ((v) & ~0x7ffff) == 0 \ | |
3466 | ? 13 \ | |
3467 | : 12 \ | |
3468 | : ((v) & ~0x3fffff) == 0 \ | |
3469 | ? ((v) & ~0x1fffff) == 0 \ | |
3470 | ? 11 \ | |
3471 | : 10 \ | |
3472 | : ((v) & ~0x7fffff) == 0 \ | |
3473 | ? 9 \ | |
3474 | : 8 \ | |
3475 | : ((v) & ~0xfffffff) == 0 \ | |
3476 | ? ((v) & ~0x3ffffff) == 0 \ | |
3477 | ? ((v) & ~0x1ffffff) == 0 \ | |
3478 | ? 7 \ | |
3479 | : 6 \ | |
3480 | : ((v) & ~0x7ffffff) == 0 \ | |
3481 | ? 5 \ | |
3482 | : 4 \ | |
3483 | : ((v) & ~0x3fffffff) == 0 \ | |
3484 | ? ((v) & ~0x1fffffff) == 0 \ | |
3485 | ? 3 \ | |
3486 | : 2 \ | |
3487 | : ((v) & ~0x7fffffff) == 0 \ | |
3488 | ? 1 \ | |
3489 | : 0) | |
3490 | ||
3491 | /* load_register() | |
67c1ffbe | 3492 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3493 | * an absolute expression value into a register. |
3494 | */ | |
3495 | static void | |
67c0d1eb | 3496 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3497 | { |
3498 | int freg; | |
3499 | expressionS hi32, lo32; | |
3500 | ||
3501 | if (ep->X_op != O_big) | |
3502 | { | |
3503 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3504 | |
3505 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3506 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3507 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3508 | { |
d17e7bce | 3509 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3510 | as_bad (_("constant too large")); |
ae826530 | 3511 | |
1b8e29e5 TS |
3512 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3513 | - 0x80000000); | |
ae826530 | 3514 | } |
256ab948 TS |
3515 | |
3516 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3517 | { |
3518 | /* We can handle 16 bit signed values with an addiu to | |
3519 | $zero. No need to ever use daddiu here, since $zero and | |
3520 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3521 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3522 | return; |
3523 | } | |
3524 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3525 | { | |
3526 | /* We can handle 16 bit unsigned values with an ori to | |
3527 | $zero. */ | |
67c0d1eb | 3528 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3529 | return; |
3530 | } | |
256ab948 | 3531 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3532 | { |
3533 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3534 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3535 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3536 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3537 | return; |
3538 | } | |
3539 | } | |
3540 | ||
3541 | /* The value is larger than 32 bits. */ | |
3542 | ||
ca4e0257 | 3543 | if (HAVE_32BIT_GPRS) |
252b5132 | 3544 | { |
956cd1d6 TS |
3545 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3546 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3547 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3548 | return; |
3549 | } | |
3550 | ||
3551 | if (ep->X_op != O_big) | |
3552 | { | |
3553 | hi32 = *ep; | |
3554 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3555 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3556 | hi32.X_add_number &= 0xffffffff; | |
3557 | lo32 = *ep; | |
3558 | lo32.X_add_number &= 0xffffffff; | |
3559 | } | |
3560 | else | |
3561 | { | |
3562 | assert (ep->X_add_number > 2); | |
3563 | if (ep->X_add_number == 3) | |
3564 | generic_bignum[3] = 0; | |
3565 | else if (ep->X_add_number > 4) | |
3566 | as_bad (_("Number larger than 64 bits")); | |
3567 | lo32.X_op = O_constant; | |
3568 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3569 | hi32.X_op = O_constant; | |
3570 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3571 | } | |
3572 | ||
3573 | if (hi32.X_add_number == 0) | |
3574 | freg = 0; | |
3575 | else | |
3576 | { | |
3577 | int shift, bit; | |
3578 | unsigned long hi, lo; | |
3579 | ||
956cd1d6 | 3580 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3581 | { |
3582 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3583 | { | |
67c0d1eb | 3584 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3585 | return; |
3586 | } | |
3587 | if (lo32.X_add_number & 0x80000000) | |
3588 | { | |
67c0d1eb | 3589 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3590 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3591 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3592 | return; |
3593 | } | |
3594 | } | |
252b5132 RH |
3595 | |
3596 | /* Check for 16bit shifted constant. We know that hi32 is | |
3597 | non-zero, so start the mask on the first bit of the hi32 | |
3598 | value. */ | |
3599 | shift = 17; | |
3600 | do | |
beae10d5 KH |
3601 | { |
3602 | unsigned long himask, lomask; | |
3603 | ||
3604 | if (shift < 32) | |
3605 | { | |
3606 | himask = 0xffff >> (32 - shift); | |
3607 | lomask = (0xffff << shift) & 0xffffffff; | |
3608 | } | |
3609 | else | |
3610 | { | |
3611 | himask = 0xffff << (shift - 32); | |
3612 | lomask = 0; | |
3613 | } | |
3614 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3615 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3616 | { | |
3617 | expressionS tmp; | |
3618 | ||
3619 | tmp.X_op = O_constant; | |
3620 | if (shift < 32) | |
3621 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3622 | | (lo32.X_add_number >> shift)); | |
3623 | else | |
3624 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3625 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3626 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3627 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3628 | return; |
3629 | } | |
f9419b05 | 3630 | ++shift; |
beae10d5 KH |
3631 | } |
3632 | while (shift <= (64 - 16)); | |
252b5132 RH |
3633 | |
3634 | /* Find the bit number of the lowest one bit, and store the | |
3635 | shifted value in hi/lo. */ | |
3636 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3637 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3638 | if (lo != 0) | |
3639 | { | |
3640 | bit = 0; | |
3641 | while ((lo & 1) == 0) | |
3642 | { | |
3643 | lo >>= 1; | |
3644 | ++bit; | |
3645 | } | |
3646 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3647 | hi >>= bit; | |
3648 | } | |
3649 | else | |
3650 | { | |
3651 | bit = 32; | |
3652 | while ((hi & 1) == 0) | |
3653 | { | |
3654 | hi >>= 1; | |
3655 | ++bit; | |
3656 | } | |
3657 | lo = hi; | |
3658 | hi = 0; | |
3659 | } | |
3660 | ||
3661 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3662 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3663 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3664 | { |
3665 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3666 | if (shift != 0) |
beae10d5 | 3667 | { |
252b5132 RH |
3668 | expressionS tmp; |
3669 | ||
3670 | /* This instruction will set the register to be all | |
3671 | ones. */ | |
beae10d5 KH |
3672 | tmp.X_op = O_constant; |
3673 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3674 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3675 | if (bit != 0) |
3676 | { | |
3677 | bit += shift; | |
67c0d1eb RS |
3678 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3679 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3680 | } |
67c0d1eb RS |
3681 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3682 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3683 | return; |
3684 | } | |
3685 | } | |
252b5132 RH |
3686 | |
3687 | /* Sign extend hi32 before calling load_register, because we can | |
3688 | generally get better code when we load a sign extended value. */ | |
3689 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3690 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3691 | load_register (reg, &hi32, 0); |
252b5132 RH |
3692 | freg = reg; |
3693 | } | |
3694 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3695 | { | |
3696 | if (freg != 0) | |
3697 | { | |
67c0d1eb | 3698 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3699 | freg = reg; |
3700 | } | |
3701 | } | |
3702 | else | |
3703 | { | |
3704 | expressionS mid16; | |
3705 | ||
956cd1d6 | 3706 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3707 | { |
67c0d1eb RS |
3708 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3709 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3710 | return; |
3711 | } | |
252b5132 RH |
3712 | |
3713 | if (freg != 0) | |
3714 | { | |
67c0d1eb | 3715 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3716 | freg = reg; |
3717 | } | |
3718 | mid16 = lo32; | |
3719 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3720 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3721 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3722 | freg = reg; |
3723 | } | |
3724 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3725 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3726 | } |
3727 | ||
269137b2 TS |
3728 | static inline void |
3729 | load_delay_nop (void) | |
3730 | { | |
3731 | if (!gpr_interlocks) | |
3732 | macro_build (NULL, "nop", ""); | |
3733 | } | |
3734 | ||
252b5132 RH |
3735 | /* Load an address into a register. */ |
3736 | ||
3737 | static void | |
67c0d1eb | 3738 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3739 | { |
252b5132 RH |
3740 | if (ep->X_op != O_constant |
3741 | && ep->X_op != O_symbol) | |
3742 | { | |
3743 | as_bad (_("expression too complex")); | |
3744 | ep->X_op = O_constant; | |
3745 | } | |
3746 | ||
3747 | if (ep->X_op == O_constant) | |
3748 | { | |
67c0d1eb | 3749 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3750 | return; |
3751 | } | |
3752 | ||
3753 | if (mips_pic == NO_PIC) | |
3754 | { | |
3755 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3756 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3757 | Otherwise we want |
3758 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3759 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3760 | If we have an addend, we always use the latter form. |
76b3015f | 3761 | |
d6bc6245 TS |
3762 | With 64bit address space and a usable $at we want |
3763 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3764 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3765 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3766 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3767 | dsll32 $reg,0 | |
3a482fd5 | 3768 | daddu $reg,$reg,$at |
76b3015f | 3769 | |
c03099e6 | 3770 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3771 | on superscalar processors. |
3772 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3773 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3774 | dsll $reg,16 | |
3775 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3776 | dsll $reg,16 | |
3777 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3778 | |
3779 | For GP relative symbols in 64bit address space we can use | |
3780 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3781 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3782 | { |
6caf9ef4 TS |
3783 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3784 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3785 | { | |
3786 | relax_start (ep->X_add_symbol); | |
3787 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3788 | mips_gp_register, BFD_RELOC_GPREL16); | |
3789 | relax_switch (); | |
3790 | } | |
d6bc6245 | 3791 | |
b8285c27 | 3792 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3793 | { |
67c0d1eb RS |
3794 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3795 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3796 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3797 | BFD_RELOC_MIPS_HIGHER); | |
3798 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3799 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3800 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3801 | *used_at = 1; |
3802 | } | |
3803 | else | |
3804 | { | |
67c0d1eb RS |
3805 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3806 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3807 | BFD_RELOC_MIPS_HIGHER); | |
3808 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3809 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3810 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3811 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3812 | } |
6caf9ef4 TS |
3813 | |
3814 | if (mips_relax.sequence) | |
3815 | relax_end (); | |
d6bc6245 | 3816 | } |
252b5132 RH |
3817 | else |
3818 | { | |
d6bc6245 | 3819 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3820 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3821 | { |
4d7206a2 | 3822 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3823 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3824 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3825 | relax_switch (); |
d6bc6245 | 3826 | } |
67c0d1eb RS |
3827 | macro_build_lui (ep, reg); |
3828 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3829 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3830 | if (mips_relax.sequence) |
3831 | relax_end (); | |
d6bc6245 | 3832 | } |
252b5132 RH |
3833 | } |
3834 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3835 | { | |
3836 | expressionS ex; | |
3837 | ||
3838 | /* If this is a reference to an external symbol, we want | |
3839 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3840 | Otherwise we want | |
3841 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3842 | nop | |
3843 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3844 | If there is a constant, it must be added in after. |
3845 | ||
ed6fb7bd | 3846 | If we have NewABI, we want |
f5040a92 AO |
3847 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3848 | unless we're referencing a global symbol with a non-zero | |
3849 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3850 | if (HAVE_NEWABI) |
3851 | { | |
f5040a92 AO |
3852 | if (ep->X_add_number) |
3853 | { | |
4d7206a2 | 3854 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3855 | ep->X_add_number = 0; |
4d7206a2 | 3856 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3857 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3858 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3859 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3860 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3861 | ex.X_op = O_constant; | |
67c0d1eb | 3862 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3863 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3864 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3865 | relax_switch (); |
f5040a92 | 3866 | } |
67c0d1eb | 3867 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3868 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3869 | if (mips_relax.sequence) |
3870 | relax_end (); | |
ed6fb7bd SC |
3871 | } |
3872 | else | |
3873 | { | |
f5040a92 AO |
3874 | ex.X_add_number = ep->X_add_number; |
3875 | ep->X_add_number = 0; | |
67c0d1eb RS |
3876 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3877 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3878 | load_delay_nop (); |
4d7206a2 RS |
3879 | relax_start (ep->X_add_symbol); |
3880 | relax_switch (); | |
67c0d1eb | 3881 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3882 | BFD_RELOC_LO16); |
4d7206a2 | 3883 | relax_end (); |
ed6fb7bd | 3884 | |
f5040a92 AO |
3885 | if (ex.X_add_number != 0) |
3886 | { | |
3887 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3888 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3889 | ex.X_op = O_constant; | |
67c0d1eb | 3890 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3891 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3892 | } |
252b5132 RH |
3893 | } |
3894 | } | |
3895 | else if (mips_pic == SVR4_PIC) | |
3896 | { | |
3897 | expressionS ex; | |
252b5132 RH |
3898 | |
3899 | /* This is the large GOT case. If this is a reference to an | |
3900 | external symbol, we want | |
3901 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3902 | addu $reg,$reg,$gp | |
3903 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3904 | |
3905 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3906 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3907 | nop | |
3908 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3909 | If there is a constant, it must be added in after. |
f5040a92 AO |
3910 | |
3911 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3912 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3913 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3914 | */ |
438c16b8 TS |
3915 | if (HAVE_NEWABI) |
3916 | { | |
4d7206a2 | 3917 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3918 | ep->X_add_number = 0; |
4d7206a2 | 3919 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3920 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3921 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3922 | reg, reg, mips_gp_register); | |
3923 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3924 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3925 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3926 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3927 | else if (ex.X_add_number) | |
3928 | { | |
3929 | ex.X_op = O_constant; | |
67c0d1eb RS |
3930 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3931 | BFD_RELOC_LO16); | |
f5040a92 AO |
3932 | } |
3933 | ||
3934 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3935 | relax_switch (); |
67c0d1eb | 3936 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3937 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3938 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3939 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3940 | relax_end (); |
438c16b8 | 3941 | } |
252b5132 | 3942 | else |
438c16b8 | 3943 | { |
f5040a92 AO |
3944 | ex.X_add_number = ep->X_add_number; |
3945 | ep->X_add_number = 0; | |
4d7206a2 | 3946 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3947 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3948 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3949 | reg, reg, mips_gp_register); | |
3950 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3951 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3952 | relax_switch (); |
3953 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3954 | { |
3955 | /* We need a nop before loading from $gp. This special | |
3956 | check is required because the lui which starts the main | |
3957 | instruction stream does not refer to $gp, and so will not | |
3958 | insert the nop which may be required. */ | |
67c0d1eb | 3959 | macro_build (NULL, "nop", ""); |
438c16b8 | 3960 | } |
67c0d1eb | 3961 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3962 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3963 | load_delay_nop (); |
67c0d1eb | 3964 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3965 | BFD_RELOC_LO16); |
4d7206a2 | 3966 | relax_end (); |
438c16b8 | 3967 | |
f5040a92 AO |
3968 | if (ex.X_add_number != 0) |
3969 | { | |
3970 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3971 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3972 | ex.X_op = O_constant; | |
67c0d1eb RS |
3973 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3974 | BFD_RELOC_LO16); | |
f5040a92 | 3975 | } |
252b5132 RH |
3976 | } |
3977 | } | |
252b5132 RH |
3978 | else |
3979 | abort (); | |
8fc2e39e TS |
3980 | |
3981 | if (mips_opts.noat && *used_at == 1) | |
3982 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
3983 | } |
3984 | ||
ea1fb5dc RS |
3985 | /* Move the contents of register SOURCE into register DEST. */ |
3986 | ||
3987 | static void | |
67c0d1eb | 3988 | move_register (int dest, int source) |
ea1fb5dc | 3989 | { |
67c0d1eb RS |
3990 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
3991 | dest, source, 0); | |
ea1fb5dc RS |
3992 | } |
3993 | ||
4d7206a2 | 3994 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
3995 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
3996 | The two alternatives are: | |
4d7206a2 RS |
3997 | |
3998 | Global symbol Local sybmol | |
3999 | ------------- ------------ | |
4000 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4001 | ... ... | |
4002 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4003 | ||
4004 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4005 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4006 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4007 | |
4008 | static void | |
67c0d1eb | 4009 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4010 | { |
4011 | expressionS global; | |
4012 | ||
4013 | global = *local; | |
4014 | global.X_add_number = 0; | |
4015 | ||
4016 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4017 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4018 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4019 | relax_switch (); |
67c0d1eb RS |
4020 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4021 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4022 | relax_end (); |
4023 | } | |
4024 | ||
4025 | static void | |
67c0d1eb | 4026 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4027 | { |
4028 | expressionS global; | |
4029 | ||
4030 | global.X_op = O_constant; | |
4031 | global.X_op_symbol = NULL; | |
4032 | global.X_add_symbol = NULL; | |
4033 | global.X_add_number = local->X_add_number; | |
4034 | ||
4035 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4036 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4037 | dest, dest, BFD_RELOC_LO16); |
4038 | relax_switch (); | |
67c0d1eb | 4039 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4040 | relax_end (); |
4041 | } | |
4042 | ||
f6a22291 MR |
4043 | static void |
4044 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4045 | { | |
4046 | expressionS global; | |
4047 | int hold_mips_optimize; | |
4048 | ||
4049 | global.X_op = O_constant; | |
4050 | global.X_op_symbol = NULL; | |
4051 | global.X_add_symbol = NULL; | |
4052 | global.X_add_number = local->X_add_number; | |
4053 | ||
4054 | relax_start (local->X_add_symbol); | |
4055 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4056 | relax_switch (); | |
4057 | /* Set mips_optimize around the lui instruction to avoid | |
4058 | inserting an unnecessary nop after the lw. */ | |
4059 | hold_mips_optimize = mips_optimize; | |
4060 | mips_optimize = 2; | |
4061 | macro_build_lui (&global, tmp); | |
4062 | mips_optimize = hold_mips_optimize; | |
4063 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4064 | relax_end (); | |
4065 | ||
4066 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4067 | } | |
4068 | ||
252b5132 RH |
4069 | /* |
4070 | * Build macros | |
4071 | * This routine implements the seemingly endless macro or synthesized | |
4072 | * instructions and addressing modes in the mips assembly language. Many | |
4073 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4074 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4075 | * this verbose method. Others are not simple macros but are more like |
4076 | * optimizing code generation. | |
4077 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4078 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4079 | * The ensuing load upper instructions are ommited. This implies some kind |
4080 | * of global optimization. We currently only optimize within a single macro. | |
4081 | * For many of the load and store macros if the address is specified as a | |
4082 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4083 | * first load register 'at' with zero and use it as the base register. The | |
4084 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4085 | * we're missing. | |
4086 | */ | |
4087 | static void | |
17a2f251 | 4088 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4089 | { |
4090 | register int treg, sreg, dreg, breg; | |
4091 | int tempreg; | |
4092 | int mask; | |
43841e91 | 4093 | int used_at = 0; |
252b5132 RH |
4094 | expressionS expr1; |
4095 | const char *s; | |
4096 | const char *s2; | |
4097 | const char *fmt; | |
4098 | int likely = 0; | |
4099 | int dbl = 0; | |
4100 | int coproc = 0; | |
4101 | int lr = 0; | |
4102 | int imm = 0; | |
1abe91b1 | 4103 | int call = 0; |
252b5132 | 4104 | int off; |
67c0d1eb | 4105 | offsetT maxnum; |
252b5132 | 4106 | bfd_reloc_code_real_type r; |
252b5132 RH |
4107 | int hold_mips_optimize; |
4108 | ||
4109 | assert (! mips_opts.mips16); | |
4110 | ||
4111 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4112 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4113 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4114 | mask = ip->insn_mo->mask; | |
4115 | ||
4116 | expr1.X_op = O_constant; | |
4117 | expr1.X_op_symbol = NULL; | |
4118 | expr1.X_add_symbol = NULL; | |
4119 | expr1.X_add_number = 1; | |
4120 | ||
4121 | switch (mask) | |
4122 | { | |
4123 | case M_DABS: | |
4124 | dbl = 1; | |
4125 | case M_ABS: | |
4126 | /* bgez $a0,.+12 | |
4127 | move v0,$a0 | |
4128 | sub v0,$zero,$a0 | |
4129 | */ | |
4130 | ||
7d10b47d | 4131 | start_noreorder (); |
252b5132 RH |
4132 | |
4133 | expr1.X_add_number = 8; | |
67c0d1eb | 4134 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4135 | if (dreg == sreg) |
67c0d1eb | 4136 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4137 | else |
67c0d1eb RS |
4138 | move_register (dreg, sreg); |
4139 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4140 | |
7d10b47d | 4141 | end_noreorder (); |
8fc2e39e | 4142 | break; |
252b5132 RH |
4143 | |
4144 | case M_ADD_I: | |
4145 | s = "addi"; | |
4146 | s2 = "add"; | |
4147 | goto do_addi; | |
4148 | case M_ADDU_I: | |
4149 | s = "addiu"; | |
4150 | s2 = "addu"; | |
4151 | goto do_addi; | |
4152 | case M_DADD_I: | |
4153 | dbl = 1; | |
4154 | s = "daddi"; | |
4155 | s2 = "dadd"; | |
4156 | goto do_addi; | |
4157 | case M_DADDU_I: | |
4158 | dbl = 1; | |
4159 | s = "daddiu"; | |
4160 | s2 = "daddu"; | |
4161 | do_addi: | |
4162 | if (imm_expr.X_op == O_constant | |
4163 | && imm_expr.X_add_number >= -0x8000 | |
4164 | && imm_expr.X_add_number < 0x8000) | |
4165 | { | |
67c0d1eb | 4166 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4167 | break; |
252b5132 | 4168 | } |
8fc2e39e | 4169 | used_at = 1; |
67c0d1eb RS |
4170 | load_register (AT, &imm_expr, dbl); |
4171 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4172 | break; |
4173 | ||
4174 | case M_AND_I: | |
4175 | s = "andi"; | |
4176 | s2 = "and"; | |
4177 | goto do_bit; | |
4178 | case M_OR_I: | |
4179 | s = "ori"; | |
4180 | s2 = "or"; | |
4181 | goto do_bit; | |
4182 | case M_NOR_I: | |
4183 | s = ""; | |
4184 | s2 = "nor"; | |
4185 | goto do_bit; | |
4186 | case M_XOR_I: | |
4187 | s = "xori"; | |
4188 | s2 = "xor"; | |
4189 | do_bit: | |
4190 | if (imm_expr.X_op == O_constant | |
4191 | && imm_expr.X_add_number >= 0 | |
4192 | && imm_expr.X_add_number < 0x10000) | |
4193 | { | |
4194 | if (mask != M_NOR_I) | |
67c0d1eb | 4195 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4196 | else |
4197 | { | |
67c0d1eb RS |
4198 | macro_build (&imm_expr, "ori", "t,r,i", |
4199 | treg, sreg, BFD_RELOC_LO16); | |
4200 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4201 | } |
8fc2e39e | 4202 | break; |
252b5132 RH |
4203 | } |
4204 | ||
8fc2e39e | 4205 | used_at = 1; |
67c0d1eb RS |
4206 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4207 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4208 | break; |
4209 | ||
4210 | case M_BEQ_I: | |
4211 | s = "beq"; | |
4212 | goto beq_i; | |
4213 | case M_BEQL_I: | |
4214 | s = "beql"; | |
4215 | likely = 1; | |
4216 | goto beq_i; | |
4217 | case M_BNE_I: | |
4218 | s = "bne"; | |
4219 | goto beq_i; | |
4220 | case M_BNEL_I: | |
4221 | s = "bnel"; | |
4222 | likely = 1; | |
4223 | beq_i: | |
4224 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4225 | { | |
67c0d1eb | 4226 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4227 | break; |
252b5132 | 4228 | } |
8fc2e39e | 4229 | used_at = 1; |
67c0d1eb RS |
4230 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4231 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4232 | break; |
4233 | ||
4234 | case M_BGEL: | |
4235 | likely = 1; | |
4236 | case M_BGE: | |
4237 | if (treg == 0) | |
4238 | { | |
67c0d1eb | 4239 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4240 | break; |
252b5132 RH |
4241 | } |
4242 | if (sreg == 0) | |
4243 | { | |
67c0d1eb | 4244 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4245 | break; |
252b5132 | 4246 | } |
8fc2e39e | 4247 | used_at = 1; |
67c0d1eb RS |
4248 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4249 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4250 | break; |
4251 | ||
4252 | case M_BGTL_I: | |
4253 | likely = 1; | |
4254 | case M_BGT_I: | |
4255 | /* check for > max integer */ | |
4256 | maxnum = 0x7fffffff; | |
ca4e0257 | 4257 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4258 | { |
4259 | maxnum <<= 16; | |
4260 | maxnum |= 0xffff; | |
4261 | maxnum <<= 16; | |
4262 | maxnum |= 0xffff; | |
4263 | } | |
4264 | if (imm_expr.X_op == O_constant | |
4265 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4266 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4267 | { |
4268 | do_false: | |
4269 | /* result is always false */ | |
4270 | if (! likely) | |
67c0d1eb | 4271 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4272 | else |
67c0d1eb | 4273 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4274 | break; |
252b5132 RH |
4275 | } |
4276 | if (imm_expr.X_op != O_constant) | |
4277 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4278 | ++imm_expr.X_add_number; |
252b5132 RH |
4279 | /* FALLTHROUGH */ |
4280 | case M_BGE_I: | |
4281 | case M_BGEL_I: | |
4282 | if (mask == M_BGEL_I) | |
4283 | likely = 1; | |
4284 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4285 | { | |
67c0d1eb | 4286 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4287 | break; |
252b5132 RH |
4288 | } |
4289 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4290 | { | |
67c0d1eb | 4291 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4292 | break; |
252b5132 RH |
4293 | } |
4294 | maxnum = 0x7fffffff; | |
ca4e0257 | 4295 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4296 | { |
4297 | maxnum <<= 16; | |
4298 | maxnum |= 0xffff; | |
4299 | maxnum <<= 16; | |
4300 | maxnum |= 0xffff; | |
4301 | } | |
4302 | maxnum = - maxnum - 1; | |
4303 | if (imm_expr.X_op == O_constant | |
4304 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4305 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4306 | { |
4307 | do_true: | |
4308 | /* result is always true */ | |
4309 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4310 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4311 | break; |
252b5132 | 4312 | } |
8fc2e39e | 4313 | used_at = 1; |
67c0d1eb RS |
4314 | set_at (sreg, 0); |
4315 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4316 | break; |
4317 | ||
4318 | case M_BGEUL: | |
4319 | likely = 1; | |
4320 | case M_BGEU: | |
4321 | if (treg == 0) | |
4322 | goto do_true; | |
4323 | if (sreg == 0) | |
4324 | { | |
67c0d1eb | 4325 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4326 | "s,t,p", 0, treg); |
8fc2e39e | 4327 | break; |
252b5132 | 4328 | } |
8fc2e39e | 4329 | used_at = 1; |
67c0d1eb RS |
4330 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4331 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4332 | break; |
4333 | ||
4334 | case M_BGTUL_I: | |
4335 | likely = 1; | |
4336 | case M_BGTU_I: | |
4337 | if (sreg == 0 | |
ca4e0257 | 4338 | || (HAVE_32BIT_GPRS |
252b5132 | 4339 | && imm_expr.X_op == O_constant |
956cd1d6 | 4340 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4341 | goto do_false; |
4342 | if (imm_expr.X_op != O_constant) | |
4343 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4344 | ++imm_expr.X_add_number; |
252b5132 RH |
4345 | /* FALLTHROUGH */ |
4346 | case M_BGEU_I: | |
4347 | case M_BGEUL_I: | |
4348 | if (mask == M_BGEUL_I) | |
4349 | likely = 1; | |
4350 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4351 | goto do_true; | |
4352 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4353 | { | |
67c0d1eb | 4354 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4355 | "s,t,p", sreg, 0); |
8fc2e39e | 4356 | break; |
252b5132 | 4357 | } |
8fc2e39e | 4358 | used_at = 1; |
67c0d1eb RS |
4359 | set_at (sreg, 1); |
4360 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4361 | break; |
4362 | ||
4363 | case M_BGTL: | |
4364 | likely = 1; | |
4365 | case M_BGT: | |
4366 | if (treg == 0) | |
4367 | { | |
67c0d1eb | 4368 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4369 | break; |
252b5132 RH |
4370 | } |
4371 | if (sreg == 0) | |
4372 | { | |
67c0d1eb | 4373 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4374 | break; |
252b5132 | 4375 | } |
8fc2e39e | 4376 | used_at = 1; |
67c0d1eb RS |
4377 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4378 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4379 | break; |
4380 | ||
4381 | case M_BGTUL: | |
4382 | likely = 1; | |
4383 | case M_BGTU: | |
4384 | if (treg == 0) | |
4385 | { | |
67c0d1eb | 4386 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4387 | "s,t,p", sreg, 0); |
8fc2e39e | 4388 | break; |
252b5132 RH |
4389 | } |
4390 | if (sreg == 0) | |
4391 | goto do_false; | |
8fc2e39e | 4392 | used_at = 1; |
67c0d1eb RS |
4393 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4394 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4395 | break; |
4396 | ||
4397 | case M_BLEL: | |
4398 | likely = 1; | |
4399 | case M_BLE: | |
4400 | if (treg == 0) | |
4401 | { | |
67c0d1eb | 4402 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4403 | break; |
252b5132 RH |
4404 | } |
4405 | if (sreg == 0) | |
4406 | { | |
67c0d1eb | 4407 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4408 | break; |
252b5132 | 4409 | } |
8fc2e39e | 4410 | used_at = 1; |
67c0d1eb RS |
4411 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4412 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4413 | break; |
4414 | ||
4415 | case M_BLEL_I: | |
4416 | likely = 1; | |
4417 | case M_BLE_I: | |
4418 | maxnum = 0x7fffffff; | |
ca4e0257 | 4419 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4420 | { |
4421 | maxnum <<= 16; | |
4422 | maxnum |= 0xffff; | |
4423 | maxnum <<= 16; | |
4424 | maxnum |= 0xffff; | |
4425 | } | |
4426 | if (imm_expr.X_op == O_constant | |
4427 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4428 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4429 | goto do_true; |
4430 | if (imm_expr.X_op != O_constant) | |
4431 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4432 | ++imm_expr.X_add_number; |
252b5132 RH |
4433 | /* FALLTHROUGH */ |
4434 | case M_BLT_I: | |
4435 | case M_BLTL_I: | |
4436 | if (mask == M_BLTL_I) | |
4437 | likely = 1; | |
4438 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4439 | { | |
67c0d1eb | 4440 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4441 | break; |
252b5132 RH |
4442 | } |
4443 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4444 | { | |
67c0d1eb | 4445 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4446 | break; |
252b5132 | 4447 | } |
8fc2e39e | 4448 | used_at = 1; |
67c0d1eb RS |
4449 | set_at (sreg, 0); |
4450 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4451 | break; |
4452 | ||
4453 | case M_BLEUL: | |
4454 | likely = 1; | |
4455 | case M_BLEU: | |
4456 | if (treg == 0) | |
4457 | { | |
67c0d1eb | 4458 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4459 | "s,t,p", sreg, 0); |
8fc2e39e | 4460 | break; |
252b5132 RH |
4461 | } |
4462 | if (sreg == 0) | |
4463 | goto do_true; | |
8fc2e39e | 4464 | used_at = 1; |
67c0d1eb RS |
4465 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4466 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4467 | break; |
4468 | ||
4469 | case M_BLEUL_I: | |
4470 | likely = 1; | |
4471 | case M_BLEU_I: | |
4472 | if (sreg == 0 | |
ca4e0257 | 4473 | || (HAVE_32BIT_GPRS |
252b5132 | 4474 | && imm_expr.X_op == O_constant |
956cd1d6 | 4475 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4476 | goto do_true; |
4477 | if (imm_expr.X_op != O_constant) | |
4478 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4479 | ++imm_expr.X_add_number; |
252b5132 RH |
4480 | /* FALLTHROUGH */ |
4481 | case M_BLTU_I: | |
4482 | case M_BLTUL_I: | |
4483 | if (mask == M_BLTUL_I) | |
4484 | likely = 1; | |
4485 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4486 | goto do_false; | |
4487 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4488 | { | |
67c0d1eb | 4489 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4490 | "s,t,p", sreg, 0); |
8fc2e39e | 4491 | break; |
252b5132 | 4492 | } |
8fc2e39e | 4493 | used_at = 1; |
67c0d1eb RS |
4494 | set_at (sreg, 1); |
4495 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4496 | break; |
4497 | ||
4498 | case M_BLTL: | |
4499 | likely = 1; | |
4500 | case M_BLT: | |
4501 | if (treg == 0) | |
4502 | { | |
67c0d1eb | 4503 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4504 | break; |
252b5132 RH |
4505 | } |
4506 | if (sreg == 0) | |
4507 | { | |
67c0d1eb | 4508 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4509 | break; |
252b5132 | 4510 | } |
8fc2e39e | 4511 | used_at = 1; |
67c0d1eb RS |
4512 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4513 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4514 | break; |
4515 | ||
4516 | case M_BLTUL: | |
4517 | likely = 1; | |
4518 | case M_BLTU: | |
4519 | if (treg == 0) | |
4520 | goto do_false; | |
4521 | if (sreg == 0) | |
4522 | { | |
67c0d1eb | 4523 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4524 | "s,t,p", 0, treg); |
8fc2e39e | 4525 | break; |
252b5132 | 4526 | } |
8fc2e39e | 4527 | used_at = 1; |
67c0d1eb RS |
4528 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4529 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4530 | break; |
4531 | ||
5f74bc13 CD |
4532 | case M_DEXT: |
4533 | { | |
4534 | unsigned long pos; | |
4535 | unsigned long size; | |
4536 | ||
4537 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4538 | { | |
4539 | as_bad (_("Unsupported large constant")); | |
4540 | pos = size = 1; | |
4541 | } | |
4542 | else | |
4543 | { | |
4544 | pos = (unsigned long) imm_expr.X_add_number; | |
4545 | size = (unsigned long) imm2_expr.X_add_number; | |
4546 | } | |
4547 | ||
4548 | if (pos > 63) | |
4549 | { | |
4550 | as_bad (_("Improper position (%lu)"), pos); | |
4551 | pos = 1; | |
4552 | } | |
4553 | if (size == 0 || size > 64 | |
4554 | || (pos + size - 1) > 63) | |
4555 | { | |
4556 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4557 | size, pos); | |
4558 | size = 1; | |
4559 | } | |
4560 | ||
4561 | if (size <= 32 && pos < 32) | |
4562 | { | |
4563 | s = "dext"; | |
4564 | fmt = "t,r,+A,+C"; | |
4565 | } | |
4566 | else if (size <= 32) | |
4567 | { | |
4568 | s = "dextu"; | |
4569 | fmt = "t,r,+E,+H"; | |
4570 | } | |
4571 | else | |
4572 | { | |
4573 | s = "dextm"; | |
4574 | fmt = "t,r,+A,+G"; | |
4575 | } | |
67c0d1eb | 4576 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4577 | } |
8fc2e39e | 4578 | break; |
5f74bc13 CD |
4579 | |
4580 | case M_DINS: | |
4581 | { | |
4582 | unsigned long pos; | |
4583 | unsigned long size; | |
4584 | ||
4585 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4586 | { | |
4587 | as_bad (_("Unsupported large constant")); | |
4588 | pos = size = 1; | |
4589 | } | |
4590 | else | |
4591 | { | |
4592 | pos = (unsigned long) imm_expr.X_add_number; | |
4593 | size = (unsigned long) imm2_expr.X_add_number; | |
4594 | } | |
4595 | ||
4596 | if (pos > 63) | |
4597 | { | |
4598 | as_bad (_("Improper position (%lu)"), pos); | |
4599 | pos = 1; | |
4600 | } | |
4601 | if (size == 0 || size > 64 | |
4602 | || (pos + size - 1) > 63) | |
4603 | { | |
4604 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4605 | size, pos); | |
4606 | size = 1; | |
4607 | } | |
4608 | ||
4609 | if (pos < 32 && (pos + size - 1) < 32) | |
4610 | { | |
4611 | s = "dins"; | |
4612 | fmt = "t,r,+A,+B"; | |
4613 | } | |
4614 | else if (pos >= 32) | |
4615 | { | |
4616 | s = "dinsu"; | |
4617 | fmt = "t,r,+E,+F"; | |
4618 | } | |
4619 | else | |
4620 | { | |
4621 | s = "dinsm"; | |
4622 | fmt = "t,r,+A,+F"; | |
4623 | } | |
67c0d1eb RS |
4624 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4625 | pos + size - 1); | |
5f74bc13 | 4626 | } |
8fc2e39e | 4627 | break; |
5f74bc13 | 4628 | |
252b5132 RH |
4629 | case M_DDIV_3: |
4630 | dbl = 1; | |
4631 | case M_DIV_3: | |
4632 | s = "mflo"; | |
4633 | goto do_div3; | |
4634 | case M_DREM_3: | |
4635 | dbl = 1; | |
4636 | case M_REM_3: | |
4637 | s = "mfhi"; | |
4638 | do_div3: | |
4639 | if (treg == 0) | |
4640 | { | |
4641 | as_warn (_("Divide by zero.")); | |
4642 | if (mips_trap) | |
67c0d1eb | 4643 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4644 | else |
67c0d1eb | 4645 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4646 | break; |
252b5132 RH |
4647 | } |
4648 | ||
7d10b47d | 4649 | start_noreorder (); |
252b5132 RH |
4650 | if (mips_trap) |
4651 | { | |
67c0d1eb RS |
4652 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4653 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4654 | } |
4655 | else | |
4656 | { | |
4657 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4658 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4659 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4660 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4661 | } |
4662 | expr1.X_add_number = -1; | |
8fc2e39e | 4663 | used_at = 1; |
f6a22291 | 4664 | load_register (AT, &expr1, dbl); |
252b5132 | 4665 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4666 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4667 | if (dbl) |
4668 | { | |
4669 | expr1.X_add_number = 1; | |
f6a22291 | 4670 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4671 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4672 | } |
4673 | else | |
4674 | { | |
4675 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4676 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4677 | } |
4678 | if (mips_trap) | |
4679 | { | |
67c0d1eb | 4680 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4681 | /* We want to close the noreorder block as soon as possible, so |
4682 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4683 | end_noreorder (); |
252b5132 RH |
4684 | } |
4685 | else | |
4686 | { | |
4687 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4688 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4689 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4690 | |
4691 | /* We want to close the noreorder block as soon as possible, so | |
4692 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4693 | end_noreorder (); |
252b5132 | 4694 | |
67c0d1eb | 4695 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4696 | } |
67c0d1eb | 4697 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4698 | break; |
4699 | ||
4700 | case M_DIV_3I: | |
4701 | s = "div"; | |
4702 | s2 = "mflo"; | |
4703 | goto do_divi; | |
4704 | case M_DIVU_3I: | |
4705 | s = "divu"; | |
4706 | s2 = "mflo"; | |
4707 | goto do_divi; | |
4708 | case M_REM_3I: | |
4709 | s = "div"; | |
4710 | s2 = "mfhi"; | |
4711 | goto do_divi; | |
4712 | case M_REMU_3I: | |
4713 | s = "divu"; | |
4714 | s2 = "mfhi"; | |
4715 | goto do_divi; | |
4716 | case M_DDIV_3I: | |
4717 | dbl = 1; | |
4718 | s = "ddiv"; | |
4719 | s2 = "mflo"; | |
4720 | goto do_divi; | |
4721 | case M_DDIVU_3I: | |
4722 | dbl = 1; | |
4723 | s = "ddivu"; | |
4724 | s2 = "mflo"; | |
4725 | goto do_divi; | |
4726 | case M_DREM_3I: | |
4727 | dbl = 1; | |
4728 | s = "ddiv"; | |
4729 | s2 = "mfhi"; | |
4730 | goto do_divi; | |
4731 | case M_DREMU_3I: | |
4732 | dbl = 1; | |
4733 | s = "ddivu"; | |
4734 | s2 = "mfhi"; | |
4735 | do_divi: | |
4736 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4737 | { | |
4738 | as_warn (_("Divide by zero.")); | |
4739 | if (mips_trap) | |
67c0d1eb | 4740 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4741 | else |
67c0d1eb | 4742 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4743 | break; |
252b5132 RH |
4744 | } |
4745 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4746 | { | |
4747 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4748 | move_register (dreg, sreg); |
252b5132 | 4749 | else |
67c0d1eb | 4750 | move_register (dreg, 0); |
8fc2e39e | 4751 | break; |
252b5132 RH |
4752 | } |
4753 | if (imm_expr.X_op == O_constant | |
4754 | && imm_expr.X_add_number == -1 | |
4755 | && s[strlen (s) - 1] != 'u') | |
4756 | { | |
4757 | if (strcmp (s2, "mflo") == 0) | |
4758 | { | |
67c0d1eb | 4759 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4760 | } |
4761 | else | |
67c0d1eb | 4762 | move_register (dreg, 0); |
8fc2e39e | 4763 | break; |
252b5132 RH |
4764 | } |
4765 | ||
8fc2e39e | 4766 | used_at = 1; |
67c0d1eb RS |
4767 | load_register (AT, &imm_expr, dbl); |
4768 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4769 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4770 | break; |
4771 | ||
4772 | case M_DIVU_3: | |
4773 | s = "divu"; | |
4774 | s2 = "mflo"; | |
4775 | goto do_divu3; | |
4776 | case M_REMU_3: | |
4777 | s = "divu"; | |
4778 | s2 = "mfhi"; | |
4779 | goto do_divu3; | |
4780 | case M_DDIVU_3: | |
4781 | s = "ddivu"; | |
4782 | s2 = "mflo"; | |
4783 | goto do_divu3; | |
4784 | case M_DREMU_3: | |
4785 | s = "ddivu"; | |
4786 | s2 = "mfhi"; | |
4787 | do_divu3: | |
7d10b47d | 4788 | start_noreorder (); |
252b5132 RH |
4789 | if (mips_trap) |
4790 | { | |
67c0d1eb RS |
4791 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4792 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4793 | /* We want to close the noreorder block as soon as possible, so |
4794 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4795 | end_noreorder (); |
252b5132 RH |
4796 | } |
4797 | else | |
4798 | { | |
4799 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4800 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4801 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4802 | |
4803 | /* We want to close the noreorder block as soon as possible, so | |
4804 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4805 | end_noreorder (); |
67c0d1eb | 4806 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4807 | } |
67c0d1eb | 4808 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4809 | break; |
252b5132 | 4810 | |
1abe91b1 MR |
4811 | case M_DLCA_AB: |
4812 | dbl = 1; | |
4813 | case M_LCA_AB: | |
4814 | call = 1; | |
4815 | goto do_la; | |
252b5132 RH |
4816 | case M_DLA_AB: |
4817 | dbl = 1; | |
4818 | case M_LA_AB: | |
1abe91b1 | 4819 | do_la: |
252b5132 RH |
4820 | /* Load the address of a symbol into a register. If breg is not |
4821 | zero, we then add a base register to it. */ | |
4822 | ||
3bec30a8 TS |
4823 | if (dbl && HAVE_32BIT_GPRS) |
4824 | as_warn (_("dla used to load 32-bit register")); | |
4825 | ||
c90bbe5b | 4826 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4827 | as_warn (_("la used to load 64-bit address")); |
4828 | ||
0c11417f MR |
4829 | if (offset_expr.X_op == O_constant |
4830 | && offset_expr.X_add_number >= -0x8000 | |
4831 | && offset_expr.X_add_number < 0x8000) | |
4832 | { | |
aed1a261 | 4833 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4834 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4835 | break; |
0c11417f MR |
4836 | } |
4837 | ||
b8285c27 | 4838 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4839 | { |
4840 | tempreg = AT; | |
4841 | used_at = 1; | |
4842 | } | |
4843 | else | |
4844 | { | |
4845 | tempreg = treg; | |
afdbd6d0 CD |
4846 | } |
4847 | ||
252b5132 RH |
4848 | if (offset_expr.X_op != O_symbol |
4849 | && offset_expr.X_op != O_constant) | |
4850 | { | |
4851 | as_bad (_("expression too complex")); | |
4852 | offset_expr.X_op = O_constant; | |
4853 | } | |
4854 | ||
252b5132 | 4855 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4856 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4857 | else if (mips_pic == NO_PIC) |
4858 | { | |
d6bc6245 | 4859 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4860 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4861 | Otherwise we want |
4862 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4863 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4864 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4865 | so we may as well always use the latter form. |
76b3015f | 4866 | |
6caf9ef4 TS |
4867 | With 64bit address space and a usable $at we want |
4868 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4869 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4870 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4871 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4872 | dsll32 $tempreg,0 | |
4873 | daddu $tempreg,$tempreg,$at | |
4874 | ||
4875 | If $at is already in use, we use a path which is suboptimal | |
4876 | on superscalar processors. | |
4877 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4878 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4879 | dsll $tempreg,16 | |
4880 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4881 | dsll $tempreg,16 | |
4882 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4883 | ||
4884 | For GP relative symbols in 64bit address space we can use | |
4885 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4886 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4887 | { |
6caf9ef4 TS |
4888 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4889 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4890 | { | |
4891 | relax_start (offset_expr.X_add_symbol); | |
4892 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4893 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4894 | relax_switch (); | |
4895 | } | |
d6bc6245 | 4896 | |
b8285c27 | 4897 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4898 | { |
67c0d1eb | 4899 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4900 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4901 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4902 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4903 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4904 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4905 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4906 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4907 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4908 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4909 | used_at = 1; |
4910 | } | |
4911 | else | |
4912 | { | |
67c0d1eb | 4913 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4914 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4915 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4916 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4917 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4918 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4919 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4920 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4921 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4922 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4923 | } |
6caf9ef4 TS |
4924 | |
4925 | if (mips_relax.sequence) | |
4926 | relax_end (); | |
98d3f06f KH |
4927 | } |
4928 | else | |
4929 | { | |
4930 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4931 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4932 | { |
4d7206a2 | 4933 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4934 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4935 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4936 | relax_switch (); |
98d3f06f | 4937 | } |
6943caf0 ILT |
4938 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4939 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4940 | macro_build_lui (&offset_expr, tempreg); |
4941 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4942 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4943 | if (mips_relax.sequence) |
4944 | relax_end (); | |
98d3f06f | 4945 | } |
252b5132 | 4946 | } |
f5040a92 | 4947 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4948 | { |
9117d219 NC |
4949 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4950 | ||
252b5132 RH |
4951 | /* If this is a reference to an external symbol, and there |
4952 | is no constant, we want | |
4953 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4954 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4955 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4956 | For a local symbol, we want |
4957 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4958 | nop | |
4959 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4960 | ||
4961 | If we have a small constant, and this is a reference to | |
4962 | an external symbol, we want | |
4963 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4964 | nop | |
4965 | addiu $tempreg,$tempreg,<constant> | |
4966 | For a local symbol, we want the same instruction | |
4967 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4968 | addiu instruction. | |
4969 | ||
4970 | If we have a large constant, and this is a reference to | |
4971 | an external symbol, we want | |
4972 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4973 | lui $at,<hiconstant> | |
4974 | addiu $at,$at,<loconstant> | |
4975 | addu $tempreg,$tempreg,$at | |
4976 | For a local symbol, we want the same instruction | |
4977 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4978 | addiu instruction. |
ed6fb7bd SC |
4979 | */ |
4980 | ||
4d7206a2 | 4981 | if (offset_expr.X_add_number == 0) |
252b5132 | 4982 | { |
4d7206a2 RS |
4983 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
4984 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4985 | ||
4986 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
4987 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
4988 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 4989 | if (breg != 0) |
252b5132 RH |
4990 | { |
4991 | /* We're going to put in an addu instruction using | |
4992 | tempreg, so we may as well insert the nop right | |
4993 | now. */ | |
269137b2 | 4994 | load_delay_nop (); |
252b5132 | 4995 | } |
4d7206a2 | 4996 | relax_switch (); |
67c0d1eb RS |
4997 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
4998 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4999 | load_delay_nop (); |
67c0d1eb RS |
5000 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5001 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5002 | relax_end (); |
252b5132 RH |
5003 | /* FIXME: If breg == 0, and the next instruction uses |
5004 | $tempreg, then if this variant case is used an extra | |
5005 | nop will be generated. */ | |
5006 | } | |
4d7206a2 RS |
5007 | else if (offset_expr.X_add_number >= -0x8000 |
5008 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5009 | { |
67c0d1eb | 5010 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5011 | load_delay_nop (); |
67c0d1eb | 5012 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5013 | } |
5014 | else | |
5015 | { | |
4d7206a2 RS |
5016 | expr1.X_add_number = offset_expr.X_add_number; |
5017 | offset_expr.X_add_number = | |
5018 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5019 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5020 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5021 | /* If we are going to add in a base register, and the |
5022 | target register and the base register are the same, | |
5023 | then we are using AT as a temporary register. Since | |
5024 | we want to load the constant into AT, we add our | |
5025 | current AT (from the global offset table) and the | |
5026 | register into the register now, and pretend we were | |
5027 | not using a base register. */ | |
67c0d1eb | 5028 | if (breg == treg) |
252b5132 | 5029 | { |
269137b2 | 5030 | load_delay_nop (); |
67c0d1eb | 5031 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5032 | treg, AT, breg); |
252b5132 RH |
5033 | breg = 0; |
5034 | tempreg = treg; | |
252b5132 | 5035 | } |
f6a22291 | 5036 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5037 | used_at = 1; |
5038 | } | |
5039 | } | |
f5040a92 AO |
5040 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5041 | { | |
67c0d1eb | 5042 | int add_breg_early = 0; |
f5040a92 AO |
5043 | |
5044 | /* If this is a reference to an external, and there is no | |
5045 | constant, or local symbol (*), with or without a | |
5046 | constant, we want | |
5047 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5048 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5049 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5050 | ||
5051 | If we have a small constant, and this is a reference to | |
5052 | an external symbol, we want | |
5053 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5054 | addiu $tempreg,$tempreg,<constant> | |
5055 | ||
5056 | If we have a large constant, and this is a reference to | |
5057 | an external symbol, we want | |
5058 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5059 | lui $at,<hiconstant> | |
5060 | addiu $at,$at,<loconstant> | |
5061 | addu $tempreg,$tempreg,$at | |
5062 | ||
5063 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5064 | local symbols, even though it introduces an additional | |
5065 | instruction. */ | |
5066 | ||
f5040a92 AO |
5067 | if (offset_expr.X_add_number) |
5068 | { | |
4d7206a2 | 5069 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5070 | offset_expr.X_add_number = 0; |
5071 | ||
4d7206a2 | 5072 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5073 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5074 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5075 | |
5076 | if (expr1.X_add_number >= -0x8000 | |
5077 | && expr1.X_add_number < 0x8000) | |
5078 | { | |
67c0d1eb RS |
5079 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5080 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5081 | } |
ecd13cd3 | 5082 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5083 | { |
5084 | int dreg; | |
5085 | ||
5086 | /* If we are going to add in a base register, and the | |
5087 | target register and the base register are the same, | |
5088 | then we are using AT as a temporary register. Since | |
5089 | we want to load the constant into AT, we add our | |
5090 | current AT (from the global offset table) and the | |
5091 | register into the register now, and pretend we were | |
5092 | not using a base register. */ | |
5093 | if (breg != treg) | |
5094 | dreg = tempreg; | |
5095 | else | |
5096 | { | |
5097 | assert (tempreg == AT); | |
67c0d1eb RS |
5098 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5099 | treg, AT, breg); | |
f5040a92 | 5100 | dreg = treg; |
67c0d1eb | 5101 | add_breg_early = 1; |
f5040a92 AO |
5102 | } |
5103 | ||
f6a22291 | 5104 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5105 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5106 | dreg, dreg, AT); |
f5040a92 | 5107 | |
f5040a92 AO |
5108 | used_at = 1; |
5109 | } | |
5110 | else | |
5111 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5112 | ||
4d7206a2 | 5113 | relax_switch (); |
f5040a92 AO |
5114 | offset_expr.X_add_number = expr1.X_add_number; |
5115 | ||
67c0d1eb RS |
5116 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5117 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5118 | if (add_breg_early) | |
f5040a92 | 5119 | { |
67c0d1eb | 5120 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5121 | treg, tempreg, breg); |
f5040a92 AO |
5122 | breg = 0; |
5123 | tempreg = treg; | |
5124 | } | |
4d7206a2 | 5125 | relax_end (); |
f5040a92 | 5126 | } |
4d7206a2 | 5127 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5128 | { |
4d7206a2 | 5129 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5130 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5131 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5132 | relax_switch (); |
67c0d1eb RS |
5133 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5134 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5135 | relax_end (); |
f5040a92 | 5136 | } |
4d7206a2 | 5137 | else |
f5040a92 | 5138 | { |
67c0d1eb RS |
5139 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5140 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5141 | } |
5142 | } | |
5143 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5144 | { |
67c0d1eb | 5145 | int gpdelay; |
9117d219 NC |
5146 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5147 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5148 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5149 | |
5150 | /* This is the large GOT case. If this is a reference to an | |
5151 | external symbol, and there is no constant, we want | |
5152 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5153 | addu $tempreg,$tempreg,$gp | |
5154 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5155 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5156 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5157 | addu $tempreg,$tempreg,$gp | |
5158 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5159 | For a local symbol, we want |
5160 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5161 | nop | |
5162 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5163 | ||
5164 | If we have a small constant, and this is a reference to | |
5165 | an external symbol, we want | |
5166 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5167 | addu $tempreg,$tempreg,$gp | |
5168 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5169 | nop | |
5170 | addiu $tempreg,$tempreg,<constant> | |
5171 | For a local symbol, we want | |
5172 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5173 | nop | |
5174 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5175 | ||
5176 | If we have a large constant, and this is a reference to | |
5177 | an external symbol, we want | |
5178 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5179 | addu $tempreg,$tempreg,$gp | |
5180 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5181 | lui $at,<hiconstant> | |
5182 | addiu $at,$at,<loconstant> | |
5183 | addu $tempreg,$tempreg,$at | |
5184 | For a local symbol, we want | |
5185 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5186 | lui $at,<hiconstant> | |
5187 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5188 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5189 | */ |
438c16b8 | 5190 | |
252b5132 RH |
5191 | expr1.X_add_number = offset_expr.X_add_number; |
5192 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5193 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5194 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5195 | if (expr1.X_add_number == 0 && breg == 0 |
5196 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5197 | { |
5198 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5199 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5200 | } | |
67c0d1eb RS |
5201 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5202 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5203 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5204 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5205 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5206 | if (expr1.X_add_number == 0) |
5207 | { | |
67c0d1eb | 5208 | if (breg != 0) |
252b5132 RH |
5209 | { |
5210 | /* We're going to put in an addu instruction using | |
5211 | tempreg, so we may as well insert the nop right | |
5212 | now. */ | |
269137b2 | 5213 | load_delay_nop (); |
252b5132 | 5214 | } |
252b5132 RH |
5215 | } |
5216 | else if (expr1.X_add_number >= -0x8000 | |
5217 | && expr1.X_add_number < 0x8000) | |
5218 | { | |
269137b2 | 5219 | load_delay_nop (); |
67c0d1eb | 5220 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5221 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5222 | } |
5223 | else | |
5224 | { | |
67c0d1eb | 5225 | int dreg; |
252b5132 RH |
5226 | |
5227 | /* If we are going to add in a base register, and the | |
5228 | target register and the base register are the same, | |
5229 | then we are using AT as a temporary register. Since | |
5230 | we want to load the constant into AT, we add our | |
5231 | current AT (from the global offset table) and the | |
5232 | register into the register now, and pretend we were | |
5233 | not using a base register. */ | |
5234 | if (breg != treg) | |
67c0d1eb | 5235 | dreg = tempreg; |
252b5132 RH |
5236 | else |
5237 | { | |
5238 | assert (tempreg == AT); | |
269137b2 | 5239 | load_delay_nop (); |
67c0d1eb | 5240 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5241 | treg, AT, breg); |
252b5132 | 5242 | dreg = treg; |
252b5132 RH |
5243 | } |
5244 | ||
f6a22291 | 5245 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5246 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5247 | |
252b5132 RH |
5248 | used_at = 1; |
5249 | } | |
4d7206a2 RS |
5250 | offset_expr.X_add_number = |
5251 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5252 | relax_switch (); | |
252b5132 | 5253 | |
67c0d1eb | 5254 | if (gpdelay) |
252b5132 RH |
5255 | { |
5256 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5257 | the first instruction on the main stream does not. */ |
67c0d1eb | 5258 | macro_build (NULL, "nop", ""); |
252b5132 | 5259 | } |
ed6fb7bd | 5260 | |
67c0d1eb RS |
5261 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5262 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5263 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5264 | && expr1.X_add_number < 0x8000) |
5265 | { | |
269137b2 | 5266 | load_delay_nop (); |
67c0d1eb RS |
5267 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5268 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5269 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5270 | register, the external symbol case ended with a load, |
5271 | so if the symbol turns out to not be external, and | |
5272 | the next instruction uses tempreg, an unnecessary nop | |
5273 | will be inserted. */ | |
252b5132 RH |
5274 | } |
5275 | else | |
5276 | { | |
5277 | if (breg == treg) | |
5278 | { | |
5279 | /* We must add in the base register now, as in the | |
f5040a92 | 5280 | external symbol case. */ |
252b5132 | 5281 | assert (tempreg == AT); |
269137b2 | 5282 | load_delay_nop (); |
67c0d1eb | 5283 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5284 | treg, AT, breg); |
252b5132 RH |
5285 | tempreg = treg; |
5286 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5287 | it in in both cases. */ |
252b5132 RH |
5288 | breg = 0; |
5289 | } | |
5290 | ||
67c0d1eb RS |
5291 | macro_build_lui (&expr1, AT); |
5292 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5293 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5294 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5295 | tempreg, tempreg, AT); |
8fc2e39e | 5296 | used_at = 1; |
252b5132 | 5297 | } |
4d7206a2 | 5298 | relax_end (); |
252b5132 | 5299 | } |
f5040a92 AO |
5300 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5301 | { | |
f5040a92 AO |
5302 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5303 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5304 | int add_breg_early = 0; |
f5040a92 AO |
5305 | |
5306 | /* This is the large GOT case. If this is a reference to an | |
5307 | external symbol, and there is no constant, we want | |
5308 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5309 | add $tempreg,$tempreg,$gp | |
5310 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5311 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5312 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5313 | add $tempreg,$tempreg,$gp | |
5314 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5315 | ||
5316 | If we have a small constant, and this is a reference to | |
5317 | an external symbol, we want | |
5318 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5319 | add $tempreg,$tempreg,$gp | |
5320 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5321 | addi $tempreg,$tempreg,<constant> | |
5322 | ||
5323 | If we have a large constant, and this is a reference to | |
5324 | an external symbol, we want | |
5325 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5326 | addu $tempreg,$tempreg,$gp | |
5327 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5328 | lui $at,<hiconstant> | |
5329 | addi $at,$at,<loconstant> | |
5330 | add $tempreg,$tempreg,$at | |
5331 | ||
5332 | If we have NewABI, and we know it's a local symbol, we want | |
5333 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5334 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5335 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5336 | ||
4d7206a2 | 5337 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5338 | |
4d7206a2 | 5339 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5340 | offset_expr.X_add_number = 0; |
5341 | ||
1abe91b1 MR |
5342 | if (expr1.X_add_number == 0 && breg == 0 |
5343 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5344 | { |
5345 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5346 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5347 | } | |
67c0d1eb RS |
5348 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5349 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5350 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5351 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5352 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5353 | |
5354 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5355 | ; |
f5040a92 AO |
5356 | else if (expr1.X_add_number >= -0x8000 |
5357 | && expr1.X_add_number < 0x8000) | |
5358 | { | |
67c0d1eb | 5359 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5360 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5361 | } |
ecd13cd3 | 5362 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5363 | { |
5364 | int dreg; | |
5365 | ||
5366 | /* If we are going to add in a base register, and the | |
5367 | target register and the base register are the same, | |
5368 | then we are using AT as a temporary register. Since | |
5369 | we want to load the constant into AT, we add our | |
5370 | current AT (from the global offset table) and the | |
5371 | register into the register now, and pretend we were | |
5372 | not using a base register. */ | |
5373 | if (breg != treg) | |
5374 | dreg = tempreg; | |
5375 | else | |
5376 | { | |
5377 | assert (tempreg == AT); | |
67c0d1eb | 5378 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5379 | treg, AT, breg); |
f5040a92 | 5380 | dreg = treg; |
67c0d1eb | 5381 | add_breg_early = 1; |
f5040a92 AO |
5382 | } |
5383 | ||
f6a22291 | 5384 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5385 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5386 | |
f5040a92 AO |
5387 | used_at = 1; |
5388 | } | |
5389 | else | |
5390 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5391 | ||
4d7206a2 | 5392 | relax_switch (); |
f5040a92 | 5393 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5394 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5395 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5396 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5397 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5398 | if (add_breg_early) | |
f5040a92 | 5399 | { |
67c0d1eb | 5400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5401 | treg, tempreg, breg); |
f5040a92 AO |
5402 | breg = 0; |
5403 | tempreg = treg; | |
5404 | } | |
4d7206a2 | 5405 | relax_end (); |
f5040a92 | 5406 | } |
252b5132 RH |
5407 | else |
5408 | abort (); | |
5409 | ||
5410 | if (breg != 0) | |
aed1a261 | 5411 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5412 | break; |
5413 | ||
5414 | case M_J_A: | |
5415 | /* The j instruction may not be used in PIC code, since it | |
5416 | requires an absolute address. We convert it to a b | |
5417 | instruction. */ | |
5418 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5419 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5420 | else |
67c0d1eb | 5421 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5422 | break; |
252b5132 RH |
5423 | |
5424 | /* The jal instructions must be handled as macros because when | |
5425 | generating PIC code they expand to multi-instruction | |
5426 | sequences. Normally they are simple instructions. */ | |
5427 | case M_JAL_1: | |
5428 | dreg = RA; | |
5429 | /* Fall through. */ | |
5430 | case M_JAL_2: | |
3e722fb5 | 5431 | if (mips_pic == NO_PIC) |
67c0d1eb | 5432 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5433 | else if (mips_pic == SVR4_PIC) |
5434 | { | |
5435 | if (sreg != PIC_CALL_REG) | |
5436 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5437 | |
67c0d1eb | 5438 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5439 | if (! HAVE_NEWABI) |
252b5132 | 5440 | { |
6478892d TS |
5441 | if (mips_cprestore_offset < 0) |
5442 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5443 | else | |
5444 | { | |
7a621144 DJ |
5445 | if (! mips_frame_reg_valid) |
5446 | { | |
5447 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5448 | /* Quiet this warning. */ | |
5449 | mips_frame_reg_valid = 1; | |
5450 | } | |
5451 | if (! mips_cprestore_valid) | |
5452 | { | |
5453 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5454 | /* Quiet this warning. */ | |
5455 | mips_cprestore_valid = 1; | |
5456 | } | |
6478892d | 5457 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5458 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5459 | mips_gp_register, |
256ab948 TS |
5460 | mips_frame_reg, |
5461 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5462 | } |
252b5132 RH |
5463 | } |
5464 | } | |
5465 | else | |
5466 | abort (); | |
5467 | ||
8fc2e39e | 5468 | break; |
252b5132 RH |
5469 | |
5470 | case M_JAL_A: | |
5471 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5472 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5473 | else if (mips_pic == SVR4_PIC) |
5474 | { | |
5475 | /* If this is a reference to an external symbol, and we are | |
5476 | using a small GOT, we want | |
5477 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5478 | nop | |
f9419b05 | 5479 | jalr $ra,$25 |
252b5132 RH |
5480 | nop |
5481 | lw $gp,cprestore($sp) | |
5482 | The cprestore value is set using the .cprestore | |
5483 | pseudo-op. If we are using a big GOT, we want | |
5484 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5485 | addu $25,$25,$gp | |
5486 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5487 | nop | |
f9419b05 | 5488 | jalr $ra,$25 |
252b5132 RH |
5489 | nop |
5490 | lw $gp,cprestore($sp) | |
5491 | If the symbol is not external, we want | |
5492 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5493 | nop | |
5494 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5495 | jalr $ra,$25 |
252b5132 | 5496 | nop |
438c16b8 | 5497 | lw $gp,cprestore($sp) |
f5040a92 AO |
5498 | |
5499 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5500 | sequences above, minus nops, unless the symbol is local, | |
5501 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5502 | GOT_DISP. */ | |
438c16b8 | 5503 | if (HAVE_NEWABI) |
252b5132 | 5504 | { |
f5040a92 AO |
5505 | if (! mips_big_got) |
5506 | { | |
4d7206a2 | 5507 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5508 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5509 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5510 | mips_gp_register); |
4d7206a2 | 5511 | relax_switch (); |
67c0d1eb RS |
5512 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5513 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5514 | mips_gp_register); |
5515 | relax_end (); | |
f5040a92 AO |
5516 | } |
5517 | else | |
5518 | { | |
4d7206a2 | 5519 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5520 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5521 | BFD_RELOC_MIPS_CALL_HI16); | |
5522 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5523 | PIC_CALL_REG, mips_gp_register); | |
5524 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5525 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5526 | PIC_CALL_REG); | |
4d7206a2 | 5527 | relax_switch (); |
67c0d1eb RS |
5528 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5529 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5530 | mips_gp_register); | |
5531 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5532 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5533 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5534 | relax_end (); |
f5040a92 | 5535 | } |
684022ea | 5536 | |
67c0d1eb | 5537 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5538 | } |
5539 | else | |
5540 | { | |
4d7206a2 | 5541 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5542 | if (! mips_big_got) |
5543 | { | |
67c0d1eb RS |
5544 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5545 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5546 | mips_gp_register); |
269137b2 | 5547 | load_delay_nop (); |
4d7206a2 | 5548 | relax_switch (); |
438c16b8 | 5549 | } |
252b5132 | 5550 | else |
252b5132 | 5551 | { |
67c0d1eb RS |
5552 | int gpdelay; |
5553 | ||
5554 | gpdelay = reg_needs_delay (mips_gp_register); | |
5555 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5556 | BFD_RELOC_MIPS_CALL_HI16); | |
5557 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5558 | PIC_CALL_REG, mips_gp_register); | |
5559 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5560 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5561 | PIC_CALL_REG); | |
269137b2 | 5562 | load_delay_nop (); |
4d7206a2 | 5563 | relax_switch (); |
67c0d1eb RS |
5564 | if (gpdelay) |
5565 | macro_build (NULL, "nop", ""); | |
252b5132 | 5566 | } |
67c0d1eb RS |
5567 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5568 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5569 | mips_gp_register); |
269137b2 | 5570 | load_delay_nop (); |
67c0d1eb RS |
5571 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5572 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5573 | relax_end (); |
67c0d1eb | 5574 | macro_build_jalr (&offset_expr); |
438c16b8 | 5575 | |
6478892d TS |
5576 | if (mips_cprestore_offset < 0) |
5577 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5578 | else | |
5579 | { | |
7a621144 DJ |
5580 | if (! mips_frame_reg_valid) |
5581 | { | |
5582 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5583 | /* Quiet this warning. */ | |
5584 | mips_frame_reg_valid = 1; | |
5585 | } | |
5586 | if (! mips_cprestore_valid) | |
5587 | { | |
5588 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5589 | /* Quiet this warning. */ | |
5590 | mips_cprestore_valid = 1; | |
5591 | } | |
6478892d | 5592 | if (mips_opts.noreorder) |
67c0d1eb | 5593 | macro_build (NULL, "nop", ""); |
6478892d | 5594 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5595 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5596 | mips_gp_register, |
256ab948 TS |
5597 | mips_frame_reg, |
5598 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5599 | } |
252b5132 RH |
5600 | } |
5601 | } | |
252b5132 RH |
5602 | else |
5603 | abort (); | |
5604 | ||
8fc2e39e | 5605 | break; |
252b5132 RH |
5606 | |
5607 | case M_LB_AB: | |
5608 | s = "lb"; | |
5609 | goto ld; | |
5610 | case M_LBU_AB: | |
5611 | s = "lbu"; | |
5612 | goto ld; | |
5613 | case M_LH_AB: | |
5614 | s = "lh"; | |
5615 | goto ld; | |
5616 | case M_LHU_AB: | |
5617 | s = "lhu"; | |
5618 | goto ld; | |
5619 | case M_LW_AB: | |
5620 | s = "lw"; | |
5621 | goto ld; | |
5622 | case M_LWC0_AB: | |
5623 | s = "lwc0"; | |
bdaaa2e1 | 5624 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5625 | coproc = 1; |
5626 | goto ld; | |
5627 | case M_LWC1_AB: | |
5628 | s = "lwc1"; | |
bdaaa2e1 | 5629 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5630 | coproc = 1; |
5631 | goto ld; | |
5632 | case M_LWC2_AB: | |
5633 | s = "lwc2"; | |
bdaaa2e1 | 5634 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5635 | coproc = 1; |
5636 | goto ld; | |
5637 | case M_LWC3_AB: | |
5638 | s = "lwc3"; | |
bdaaa2e1 | 5639 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5640 | coproc = 1; |
5641 | goto ld; | |
5642 | case M_LWL_AB: | |
5643 | s = "lwl"; | |
5644 | lr = 1; | |
5645 | goto ld; | |
5646 | case M_LWR_AB: | |
5647 | s = "lwr"; | |
5648 | lr = 1; | |
5649 | goto ld; | |
5650 | case M_LDC1_AB: | |
fef14a42 | 5651 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5652 | { |
5653 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5654 | break; |
252b5132 RH |
5655 | } |
5656 | s = "ldc1"; | |
bdaaa2e1 | 5657 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5658 | coproc = 1; |
5659 | goto ld; | |
5660 | case M_LDC2_AB: | |
5661 | s = "ldc2"; | |
bdaaa2e1 | 5662 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5663 | coproc = 1; |
5664 | goto ld; | |
5665 | case M_LDC3_AB: | |
5666 | s = "ldc3"; | |
bdaaa2e1 | 5667 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5668 | coproc = 1; |
5669 | goto ld; | |
5670 | case M_LDL_AB: | |
5671 | s = "ldl"; | |
5672 | lr = 1; | |
5673 | goto ld; | |
5674 | case M_LDR_AB: | |
5675 | s = "ldr"; | |
5676 | lr = 1; | |
5677 | goto ld; | |
5678 | case M_LL_AB: | |
5679 | s = "ll"; | |
5680 | goto ld; | |
5681 | case M_LLD_AB: | |
5682 | s = "lld"; | |
5683 | goto ld; | |
5684 | case M_LWU_AB: | |
5685 | s = "lwu"; | |
5686 | ld: | |
8fc2e39e | 5687 | if (breg == treg || coproc || lr) |
252b5132 RH |
5688 | { |
5689 | tempreg = AT; | |
5690 | used_at = 1; | |
5691 | } | |
5692 | else | |
5693 | { | |
5694 | tempreg = treg; | |
252b5132 RH |
5695 | } |
5696 | goto ld_st; | |
5697 | case M_SB_AB: | |
5698 | s = "sb"; | |
5699 | goto st; | |
5700 | case M_SH_AB: | |
5701 | s = "sh"; | |
5702 | goto st; | |
5703 | case M_SW_AB: | |
5704 | s = "sw"; | |
5705 | goto st; | |
5706 | case M_SWC0_AB: | |
5707 | s = "swc0"; | |
bdaaa2e1 | 5708 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5709 | coproc = 1; |
5710 | goto st; | |
5711 | case M_SWC1_AB: | |
5712 | s = "swc1"; | |
bdaaa2e1 | 5713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5714 | coproc = 1; |
5715 | goto st; | |
5716 | case M_SWC2_AB: | |
5717 | s = "swc2"; | |
bdaaa2e1 | 5718 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5719 | coproc = 1; |
5720 | goto st; | |
5721 | case M_SWC3_AB: | |
5722 | s = "swc3"; | |
bdaaa2e1 | 5723 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5724 | coproc = 1; |
5725 | goto st; | |
5726 | case M_SWL_AB: | |
5727 | s = "swl"; | |
5728 | goto st; | |
5729 | case M_SWR_AB: | |
5730 | s = "swr"; | |
5731 | goto st; | |
5732 | case M_SC_AB: | |
5733 | s = "sc"; | |
5734 | goto st; | |
5735 | case M_SCD_AB: | |
5736 | s = "scd"; | |
5737 | goto st; | |
5738 | case M_SDC1_AB: | |
fef14a42 | 5739 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5740 | { |
5741 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5742 | break; |
252b5132 RH |
5743 | } |
5744 | s = "sdc1"; | |
5745 | coproc = 1; | |
bdaaa2e1 | 5746 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5747 | goto st; |
5748 | case M_SDC2_AB: | |
5749 | s = "sdc2"; | |
bdaaa2e1 | 5750 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5751 | coproc = 1; |
5752 | goto st; | |
5753 | case M_SDC3_AB: | |
5754 | s = "sdc3"; | |
bdaaa2e1 | 5755 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5756 | coproc = 1; |
5757 | goto st; | |
5758 | case M_SDL_AB: | |
5759 | s = "sdl"; | |
5760 | goto st; | |
5761 | case M_SDR_AB: | |
5762 | s = "sdr"; | |
5763 | st: | |
8fc2e39e TS |
5764 | tempreg = AT; |
5765 | used_at = 1; | |
252b5132 | 5766 | ld_st: |
bdaaa2e1 | 5767 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5768 | if (mask == M_LWC1_AB |
5769 | || mask == M_SWC1_AB | |
5770 | || mask == M_LDC1_AB | |
5771 | || mask == M_SDC1_AB | |
5772 | || mask == M_L_DAB | |
5773 | || mask == M_S_DAB) | |
5774 | fmt = "T,o(b)"; | |
5775 | else if (coproc) | |
5776 | fmt = "E,o(b)"; | |
5777 | else | |
5778 | fmt = "t,o(b)"; | |
5779 | ||
5780 | if (offset_expr.X_op != O_constant | |
5781 | && offset_expr.X_op != O_symbol) | |
5782 | { | |
5783 | as_bad (_("expression too complex")); | |
5784 | offset_expr.X_op = O_constant; | |
5785 | } | |
5786 | ||
5787 | /* A constant expression in PIC code can be handled just as it | |
5788 | is in non PIC code. */ | |
aed1a261 RS |
5789 | if (offset_expr.X_op == O_constant) |
5790 | { | |
5791 | if (HAVE_32BIT_ADDRESSES | |
5792 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5793 | as_bad (_("constant too large")); | |
5794 | ||
5795 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) | |
5796 | & ~(bfd_vma) 0xffff); | |
5797 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
5798 | if (breg != 0) | |
5799 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5800 | tempreg, tempreg, breg); | |
5801 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5802 | } | |
5803 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5804 | { |
5805 | /* If this is a reference to a GP relative symbol, and there | |
5806 | is no base register, we want | |
cdf6fd85 | 5807 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5808 | Otherwise, if there is no base register, we want |
5809 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5810 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5811 | If we have a constant, we need two instructions anyhow, | |
5812 | so we always use the latter form. | |
5813 | ||
5814 | If we have a base register, and this is a reference to a | |
5815 | GP relative symbol, we want | |
5816 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5817 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5818 | Otherwise we want |
5819 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5820 | addu $tempreg,$tempreg,$breg | |
5821 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5822 | With a constant we always use the latter case. |
76b3015f | 5823 | |
d6bc6245 TS |
5824 | With 64bit address space and no base register and $at usable, |
5825 | we want | |
5826 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5827 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5828 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5829 | dsll32 $tempreg,0 | |
5830 | daddu $tempreg,$at | |
5831 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5832 | If we have a base register, we want | |
5833 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5834 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5835 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5836 | daddu $at,$breg | |
5837 | dsll32 $tempreg,0 | |
5838 | daddu $tempreg,$at | |
5839 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5840 | ||
5841 | Without $at we can't generate the optimal path for superscalar | |
5842 | processors here since this would require two temporary registers. | |
5843 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5844 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5845 | dsll $tempreg,16 | |
5846 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5847 | dsll $tempreg,16 | |
5848 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5849 | If we have a base register, we want | |
5850 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5851 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5852 | dsll $tempreg,16 | |
5853 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5854 | dsll $tempreg,16 | |
5855 | daddu $tempreg,$tempreg,$breg | |
5856 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5857 | |
6caf9ef4 | 5858 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5859 | the same sequence as in 32bit address space. */ |
5860 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5861 | { |
aed1a261 | 5862 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5863 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5864 | { | |
5865 | relax_start (offset_expr.X_add_symbol); | |
5866 | if (breg == 0) | |
5867 | { | |
5868 | macro_build (&offset_expr, s, fmt, treg, | |
5869 | BFD_RELOC_GPREL16, mips_gp_register); | |
5870 | } | |
5871 | else | |
5872 | { | |
5873 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5874 | tempreg, breg, mips_gp_register); | |
5875 | macro_build (&offset_expr, s, fmt, treg, | |
5876 | BFD_RELOC_GPREL16, tempreg); | |
5877 | } | |
5878 | relax_switch (); | |
5879 | } | |
d6bc6245 | 5880 | |
b8285c27 | 5881 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5882 | { |
67c0d1eb RS |
5883 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5884 | BFD_RELOC_MIPS_HIGHEST); | |
5885 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5886 | BFD_RELOC_HI16_S); | |
5887 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5888 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5889 | if (breg != 0) |
67c0d1eb RS |
5890 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5891 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5892 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5893 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5894 | tempreg); | |
d6bc6245 TS |
5895 | used_at = 1; |
5896 | } | |
5897 | else | |
5898 | { | |
67c0d1eb RS |
5899 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5900 | BFD_RELOC_MIPS_HIGHEST); | |
5901 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5902 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5903 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5904 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5905 | tempreg, BFD_RELOC_HI16_S); | |
5906 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5907 | if (breg != 0) |
67c0d1eb | 5908 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5909 | tempreg, tempreg, breg); |
67c0d1eb | 5910 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5911 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5912 | } |
6caf9ef4 TS |
5913 | |
5914 | if (mips_relax.sequence) | |
5915 | relax_end (); | |
8fc2e39e | 5916 | break; |
d6bc6245 | 5917 | } |
256ab948 | 5918 | |
252b5132 RH |
5919 | if (breg == 0) |
5920 | { | |
67c0d1eb | 5921 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5922 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5923 | { |
4d7206a2 | 5924 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5925 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5926 | mips_gp_register); | |
4d7206a2 | 5927 | relax_switch (); |
252b5132 | 5928 | } |
67c0d1eb RS |
5929 | macro_build_lui (&offset_expr, tempreg); |
5930 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5931 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5932 | if (mips_relax.sequence) |
5933 | relax_end (); | |
252b5132 RH |
5934 | } |
5935 | else | |
5936 | { | |
67c0d1eb | 5937 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5938 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5939 | { |
4d7206a2 | 5940 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5941 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5942 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5943 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5944 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5945 | relax_switch (); |
252b5132 | 5946 | } |
67c0d1eb RS |
5947 | macro_build_lui (&offset_expr, tempreg); |
5948 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5949 | tempreg, tempreg, breg); |
67c0d1eb | 5950 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5951 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5952 | if (mips_relax.sequence) |
5953 | relax_end (); | |
252b5132 RH |
5954 | } |
5955 | } | |
5956 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5957 | { | |
ed6fb7bd | 5958 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5959 | |
252b5132 RH |
5960 | /* If this is a reference to an external symbol, we want |
5961 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5962 | nop | |
5963 | <op> $treg,0($tempreg) | |
5964 | Otherwise we want | |
5965 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5966 | nop | |
5967 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5968 | <op> $treg,0($tempreg) | |
f5040a92 AO |
5969 | |
5970 | For NewABI, we want | |
5971 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5972 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
5973 | ||
252b5132 RH |
5974 | If there is a base register, we add it to $tempreg before |
5975 | the <op>. If there is a constant, we stick it in the | |
5976 | <op> instruction. We don't handle constants larger than | |
5977 | 16 bits, because we have no way to load the upper 16 bits | |
5978 | (actually, we could handle them for the subset of cases | |
5979 | in which we are not using $at). */ | |
5980 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
5981 | if (HAVE_NEWABI) |
5982 | { | |
67c0d1eb RS |
5983 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5984 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 5985 | if (breg != 0) |
67c0d1eb | 5986 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5987 | tempreg, tempreg, breg); |
67c0d1eb | 5988 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5989 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
5990 | break; |
5991 | } | |
252b5132 RH |
5992 | expr1.X_add_number = offset_expr.X_add_number; |
5993 | offset_expr.X_add_number = 0; | |
5994 | if (expr1.X_add_number < -0x8000 | |
5995 | || expr1.X_add_number >= 0x8000) | |
5996 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
5997 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5998 | lw_reloc_type, mips_gp_register); | |
269137b2 | 5999 | load_delay_nop (); |
4d7206a2 RS |
6000 | relax_start (offset_expr.X_add_symbol); |
6001 | relax_switch (); | |
67c0d1eb RS |
6002 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6003 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6004 | relax_end (); |
252b5132 | 6005 | if (breg != 0) |
67c0d1eb | 6006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6007 | tempreg, tempreg, breg); |
67c0d1eb | 6008 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6009 | } |
f5040a92 | 6010 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6011 | { |
67c0d1eb | 6012 | int gpdelay; |
252b5132 RH |
6013 | |
6014 | /* If this is a reference to an external symbol, we want | |
6015 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6016 | addu $tempreg,$tempreg,$gp | |
6017 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6018 | <op> $treg,0($tempreg) | |
6019 | Otherwise we want | |
6020 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6021 | nop | |
6022 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6023 | <op> $treg,0($tempreg) | |
6024 | If there is a base register, we add it to $tempreg before | |
6025 | the <op>. If there is a constant, we stick it in the | |
6026 | <op> instruction. We don't handle constants larger than | |
6027 | 16 bits, because we have no way to load the upper 16 bits | |
6028 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6029 | in which we are not using $at). */ |
252b5132 RH |
6030 | assert (offset_expr.X_op == O_symbol); |
6031 | expr1.X_add_number = offset_expr.X_add_number; | |
6032 | offset_expr.X_add_number = 0; | |
6033 | if (expr1.X_add_number < -0x8000 | |
6034 | || expr1.X_add_number >= 0x8000) | |
6035 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6036 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6037 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6038 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6039 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6040 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6041 | mips_gp_register); | |
6042 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6043 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6044 | relax_switch (); |
67c0d1eb RS |
6045 | if (gpdelay) |
6046 | macro_build (NULL, "nop", ""); | |
6047 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6048 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6049 | load_delay_nop (); |
67c0d1eb RS |
6050 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6051 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6052 | relax_end (); |
6053 | ||
252b5132 | 6054 | if (breg != 0) |
67c0d1eb | 6055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6056 | tempreg, tempreg, breg); |
67c0d1eb | 6057 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6058 | } |
f5040a92 AO |
6059 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6060 | { | |
f5040a92 AO |
6061 | /* If this is a reference to an external symbol, we want |
6062 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6063 | add $tempreg,$tempreg,$gp | |
6064 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6065 | <op> $treg,<ofst>($tempreg) | |
6066 | Otherwise, for local symbols, we want: | |
6067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6068 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6069 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6070 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6071 | offset_expr.X_add_number = 0; |
6072 | if (expr1.X_add_number < -0x8000 | |
6073 | || expr1.X_add_number >= 0x8000) | |
6074 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6075 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6076 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6077 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6078 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6079 | mips_gp_register); | |
6080 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6081 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6082 | if (breg != 0) |
67c0d1eb | 6083 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6084 | tempreg, tempreg, breg); |
67c0d1eb | 6085 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6086 | |
4d7206a2 | 6087 | relax_switch (); |
f5040a92 | 6088 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6089 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6090 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6091 | if (breg != 0) |
67c0d1eb | 6092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6093 | tempreg, tempreg, breg); |
67c0d1eb | 6094 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6095 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6096 | relax_end (); |
f5040a92 | 6097 | } |
252b5132 RH |
6098 | else |
6099 | abort (); | |
6100 | ||
252b5132 RH |
6101 | break; |
6102 | ||
6103 | case M_LI: | |
6104 | case M_LI_S: | |
67c0d1eb | 6105 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6106 | break; |
252b5132 RH |
6107 | |
6108 | case M_DLI: | |
67c0d1eb | 6109 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6110 | break; |
252b5132 RH |
6111 | |
6112 | case M_LI_SS: | |
6113 | if (imm_expr.X_op == O_constant) | |
6114 | { | |
8fc2e39e | 6115 | used_at = 1; |
67c0d1eb RS |
6116 | load_register (AT, &imm_expr, 0); |
6117 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6118 | break; |
6119 | } | |
6120 | else | |
6121 | { | |
6122 | assert (offset_expr.X_op == O_symbol | |
6123 | && strcmp (segment_name (S_GET_SEGMENT | |
6124 | (offset_expr.X_add_symbol)), | |
6125 | ".lit4") == 0 | |
6126 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6127 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6128 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6129 | break; |
252b5132 RH |
6130 | } |
6131 | ||
6132 | case M_LI_D: | |
ca4e0257 RS |
6133 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6134 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6135 | order 32 bits of the value and the low order 32 bits are either | |
6136 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6137 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6138 | { | |
ca4e0257 | 6139 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6140 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6141 | else |
6142 | { | |
6143 | int hreg, lreg; | |
6144 | ||
6145 | if (target_big_endian) | |
6146 | { | |
6147 | hreg = treg; | |
6148 | lreg = treg + 1; | |
6149 | } | |
6150 | else | |
6151 | { | |
6152 | hreg = treg + 1; | |
6153 | lreg = treg; | |
6154 | } | |
6155 | ||
6156 | if (hreg <= 31) | |
67c0d1eb | 6157 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6158 | if (lreg <= 31) |
6159 | { | |
6160 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6161 | move_register (lreg, 0); |
252b5132 RH |
6162 | else |
6163 | { | |
6164 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6165 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6166 | } |
6167 | } | |
6168 | } | |
8fc2e39e | 6169 | break; |
252b5132 RH |
6170 | } |
6171 | ||
6172 | /* We know that sym is in the .rdata section. First we get the | |
6173 | upper 16 bits of the address. */ | |
6174 | if (mips_pic == NO_PIC) | |
6175 | { | |
67c0d1eb | 6176 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6177 | used_at = 1; |
252b5132 RH |
6178 | } |
6179 | else if (mips_pic == SVR4_PIC) | |
6180 | { | |
67c0d1eb RS |
6181 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6182 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6183 | used_at = 1; |
252b5132 | 6184 | } |
252b5132 RH |
6185 | else |
6186 | abort (); | |
bdaaa2e1 | 6187 | |
252b5132 | 6188 | /* Now we load the register(s). */ |
ca4e0257 | 6189 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6190 | { |
6191 | used_at = 1; | |
6192 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6193 | } | |
252b5132 RH |
6194 | else |
6195 | { | |
8fc2e39e | 6196 | used_at = 1; |
67c0d1eb | 6197 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6198 | if (treg != RA) |
252b5132 RH |
6199 | { |
6200 | /* FIXME: How in the world do we deal with the possible | |
6201 | overflow here? */ | |
6202 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6203 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6204 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6205 | } |
6206 | } | |
252b5132 RH |
6207 | break; |
6208 | ||
6209 | case M_LI_DD: | |
ca4e0257 RS |
6210 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6211 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6212 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6213 | the value and the low order 32 bits are either zero or in | |
6214 | OFFSET_EXPR. */ | |
252b5132 RH |
6215 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6216 | { | |
8fc2e39e | 6217 | used_at = 1; |
67c0d1eb | 6218 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6219 | if (HAVE_64BIT_FPRS) |
6220 | { | |
6221 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6222 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6223 | } |
252b5132 RH |
6224 | else |
6225 | { | |
67c0d1eb | 6226 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6227 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6228 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6229 | else |
6230 | { | |
6231 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6232 | load_register (AT, &offset_expr, 0); |
6233 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6234 | } |
6235 | } | |
6236 | break; | |
6237 | } | |
6238 | ||
6239 | assert (offset_expr.X_op == O_symbol | |
6240 | && offset_expr.X_add_number == 0); | |
6241 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6242 | if (strcmp (s, ".lit8") == 0) | |
6243 | { | |
e7af610e | 6244 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6245 | { |
67c0d1eb | 6246 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6247 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6248 | break; |
252b5132 | 6249 | } |
c9914766 | 6250 | breg = mips_gp_register; |
252b5132 RH |
6251 | r = BFD_RELOC_MIPS_LITERAL; |
6252 | goto dob; | |
6253 | } | |
6254 | else | |
6255 | { | |
6256 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6257 | used_at = 1; |
252b5132 | 6258 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6259 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6260 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6261 | else |
6262 | { | |
6263 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6264 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6265 | } |
bdaaa2e1 | 6266 | |
e7af610e | 6267 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6268 | { |
67c0d1eb RS |
6269 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6270 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6271 | break; |
6272 | } | |
6273 | breg = AT; | |
6274 | r = BFD_RELOC_LO16; | |
6275 | goto dob; | |
6276 | } | |
6277 | ||
6278 | case M_L_DOB: | |
fef14a42 | 6279 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6280 | { |
6281 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6282 | break; |
252b5132 RH |
6283 | } |
6284 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6285 | to adjust when loading from memory. */ | |
6286 | r = BFD_RELOC_LO16; | |
6287 | dob: | |
e7af610e | 6288 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6289 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6290 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6291 | /* FIXME: A possible overflow which I don't know how to deal |
6292 | with. */ | |
6293 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6294 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6295 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6296 | break; |
6297 | ||
6298 | case M_L_DAB: | |
6299 | /* | |
6300 | * The MIPS assembler seems to check for X_add_number not | |
6301 | * being double aligned and generating: | |
6302 | * lui at,%hi(foo+1) | |
6303 | * addu at,at,v1 | |
6304 | * addiu at,at,%lo(foo+1) | |
6305 | * lwc1 f2,0(at) | |
6306 | * lwc1 f3,4(at) | |
6307 | * But, the resulting address is the same after relocation so why | |
6308 | * generate the extra instruction? | |
6309 | */ | |
fef14a42 | 6310 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6311 | { |
6312 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6313 | break; |
252b5132 | 6314 | } |
bdaaa2e1 | 6315 | /* Itbl support may require additional care here. */ |
252b5132 | 6316 | coproc = 1; |
e7af610e | 6317 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6318 | { |
6319 | s = "ldc1"; | |
6320 | goto ld; | |
6321 | } | |
6322 | ||
6323 | s = "lwc1"; | |
6324 | fmt = "T,o(b)"; | |
6325 | goto ldd_std; | |
6326 | ||
6327 | case M_S_DAB: | |
fef14a42 | 6328 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6329 | { |
6330 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6331 | break; |
252b5132 RH |
6332 | } |
6333 | ||
e7af610e | 6334 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6335 | { |
6336 | s = "sdc1"; | |
6337 | goto st; | |
6338 | } | |
6339 | ||
6340 | s = "swc1"; | |
6341 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6342 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6343 | coproc = 1; |
6344 | goto ldd_std; | |
6345 | ||
6346 | case M_LD_AB: | |
ca4e0257 | 6347 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6348 | { |
6349 | s = "ld"; | |
6350 | goto ld; | |
6351 | } | |
6352 | ||
6353 | s = "lw"; | |
6354 | fmt = "t,o(b)"; | |
6355 | goto ldd_std; | |
6356 | ||
6357 | case M_SD_AB: | |
ca4e0257 | 6358 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6359 | { |
6360 | s = "sd"; | |
6361 | goto st; | |
6362 | } | |
6363 | ||
6364 | s = "sw"; | |
6365 | fmt = "t,o(b)"; | |
6366 | ||
6367 | ldd_std: | |
6368 | if (offset_expr.X_op != O_symbol | |
6369 | && offset_expr.X_op != O_constant) | |
6370 | { | |
6371 | as_bad (_("expression too complex")); | |
6372 | offset_expr.X_op = O_constant; | |
6373 | } | |
6374 | ||
6375 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6376 | to adjust when loading from memory. We set coproc if we must | |
6377 | load $fn+1 first. */ | |
bdaaa2e1 | 6378 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6379 | if (! target_big_endian) |
6380 | coproc = 0; | |
6381 | ||
6382 | if (mips_pic == NO_PIC | |
6383 | || offset_expr.X_op == O_constant) | |
6384 | { | |
6385 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6386 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6387 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6388 | If we have a base register, we use this |
6389 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6390 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6391 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6392 | If this is not a GP relative symbol, we want |
6393 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6394 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6395 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6396 | If there is a base register, we add it to $at after the | |
6397 | lui instruction. If there is a constant, we always use | |
6398 | the last case. */ | |
6caf9ef4 TS |
6399 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6400 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6401 | { |
4d7206a2 | 6402 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6403 | if (breg == 0) |
6404 | { | |
c9914766 | 6405 | tempreg = mips_gp_register; |
252b5132 RH |
6406 | } |
6407 | else | |
6408 | { | |
67c0d1eb | 6409 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6410 | AT, breg, mips_gp_register); |
252b5132 | 6411 | tempreg = AT; |
252b5132 RH |
6412 | used_at = 1; |
6413 | } | |
6414 | ||
beae10d5 | 6415 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6416 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6417 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6418 | offset_expr.X_add_number += 4; |
6419 | ||
6420 | /* Set mips_optimize to 2 to avoid inserting an | |
6421 | undesired nop. */ | |
6422 | hold_mips_optimize = mips_optimize; | |
6423 | mips_optimize = 2; | |
beae10d5 | 6424 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6425 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6426 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6427 | mips_optimize = hold_mips_optimize; |
6428 | ||
4d7206a2 | 6429 | relax_switch (); |
252b5132 RH |
6430 | |
6431 | /* We just generated two relocs. When tc_gen_reloc | |
6432 | handles this case, it will skip the first reloc and | |
6433 | handle the second. The second reloc already has an | |
6434 | extra addend of 4, which we added above. We must | |
6435 | subtract it out, and then subtract another 4 to make | |
6436 | the first reloc come out right. The second reloc | |
6437 | will come out right because we are going to add 4 to | |
6438 | offset_expr when we build its instruction below. | |
6439 | ||
6440 | If we have a symbol, then we don't want to include | |
6441 | the offset, because it will wind up being included | |
6442 | when we generate the reloc. */ | |
6443 | ||
6444 | if (offset_expr.X_op == O_constant) | |
6445 | offset_expr.X_add_number -= 8; | |
6446 | else | |
6447 | { | |
6448 | offset_expr.X_add_number = -4; | |
6449 | offset_expr.X_op = O_constant; | |
6450 | } | |
6451 | } | |
8fc2e39e | 6452 | used_at = 1; |
67c0d1eb | 6453 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6454 | if (breg != 0) |
67c0d1eb | 6455 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6456 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6457 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6458 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6459 | /* FIXME: How do we handle overflow here? */ |
6460 | offset_expr.X_add_number += 4; | |
beae10d5 | 6461 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6462 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6463 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6464 | if (mips_relax.sequence) |
6465 | relax_end (); | |
bdaaa2e1 | 6466 | } |
252b5132 RH |
6467 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6468 | { | |
252b5132 RH |
6469 | /* If this is a reference to an external symbol, we want |
6470 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6471 | nop | |
6472 | <op> $treg,0($at) | |
6473 | <op> $treg+1,4($at) | |
6474 | Otherwise we want | |
6475 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6476 | nop | |
6477 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6478 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6479 | If there is a base register we add it to $at before the | |
6480 | lwc1 instructions. If there is a constant we include it | |
6481 | in the lwc1 instructions. */ | |
6482 | used_at = 1; | |
6483 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6484 | if (expr1.X_add_number < -0x8000 |
6485 | || expr1.X_add_number >= 0x8000 - 4) | |
6486 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6487 | load_got_offset (AT, &offset_expr); |
269137b2 | 6488 | load_delay_nop (); |
252b5132 | 6489 | if (breg != 0) |
67c0d1eb | 6490 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6491 | |
6492 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6493 | nop. */ | |
6494 | hold_mips_optimize = mips_optimize; | |
6495 | mips_optimize = 2; | |
4d7206a2 | 6496 | |
beae10d5 | 6497 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6498 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6499 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6500 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6501 | expr1.X_add_number += 4; |
67c0d1eb RS |
6502 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6503 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6504 | relax_switch (); |
67c0d1eb RS |
6505 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6506 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6507 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6508 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6509 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6510 | relax_end (); |
252b5132 | 6511 | |
4d7206a2 | 6512 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6513 | } |
6514 | else if (mips_pic == SVR4_PIC) | |
6515 | { | |
67c0d1eb | 6516 | int gpdelay; |
252b5132 RH |
6517 | |
6518 | /* If this is a reference to an external symbol, we want | |
6519 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6520 | addu $at,$at,$gp | |
6521 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6522 | nop | |
6523 | <op> $treg,0($at) | |
6524 | <op> $treg+1,4($at) | |
6525 | Otherwise we want | |
6526 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6527 | nop | |
6528 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6529 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6530 | If there is a base register we add it to $at before the | |
6531 | lwc1 instructions. If there is a constant we include it | |
6532 | in the lwc1 instructions. */ | |
6533 | used_at = 1; | |
6534 | expr1.X_add_number = offset_expr.X_add_number; | |
6535 | offset_expr.X_add_number = 0; | |
6536 | if (expr1.X_add_number < -0x8000 | |
6537 | || expr1.X_add_number >= 0x8000 - 4) | |
6538 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6539 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6540 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6541 | macro_build (&offset_expr, "lui", "t,u", |
6542 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6543 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6544 | AT, AT, mips_gp_register); |
67c0d1eb | 6545 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6546 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6547 | load_delay_nop (); |
252b5132 | 6548 | if (breg != 0) |
67c0d1eb | 6549 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6550 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6551 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6552 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6553 | expr1.X_add_number += 4; |
6554 | ||
6555 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6556 | nop. */ | |
6557 | hold_mips_optimize = mips_optimize; | |
6558 | mips_optimize = 2; | |
beae10d5 | 6559 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6560 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6561 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6562 | mips_optimize = hold_mips_optimize; |
6563 | expr1.X_add_number -= 4; | |
6564 | ||
4d7206a2 RS |
6565 | relax_switch (); |
6566 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6567 | if (gpdelay) |
6568 | macro_build (NULL, "nop", ""); | |
6569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6570 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6571 | load_delay_nop (); |
252b5132 | 6572 | if (breg != 0) |
67c0d1eb | 6573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6574 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6575 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6576 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6577 | offset_expr.X_add_number += 4; |
252b5132 RH |
6578 | |
6579 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6580 | nop. */ | |
6581 | hold_mips_optimize = mips_optimize; | |
6582 | mips_optimize = 2; | |
beae10d5 | 6583 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6584 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6585 | BFD_RELOC_LO16, AT); | |
252b5132 | 6586 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6587 | relax_end (); |
252b5132 | 6588 | } |
252b5132 RH |
6589 | else |
6590 | abort (); | |
6591 | ||
252b5132 RH |
6592 | break; |
6593 | ||
6594 | case M_LD_OB: | |
6595 | s = "lw"; | |
6596 | goto sd_ob; | |
6597 | case M_SD_OB: | |
6598 | s = "sw"; | |
6599 | sd_ob: | |
ca4e0257 | 6600 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6601 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6602 | offset_expr.X_add_number += 4; |
67c0d1eb | 6603 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6604 | break; |
252b5132 RH |
6605 | |
6606 | /* New code added to support COPZ instructions. | |
6607 | This code builds table entries out of the macros in mip_opcodes. | |
6608 | R4000 uses interlocks to handle coproc delays. | |
6609 | Other chips (like the R3000) require nops to be inserted for delays. | |
6610 | ||
f72c8c98 | 6611 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6612 | In order to fill delay slots for non-interlocked chips, |
6613 | we must have a way to specify delays based on the coprocessor. | |
6614 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6615 | What are the side-effects of the cop instruction? | |
6616 | What cache support might we have and what are its effects? | |
6617 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6618 | What registers are read/set/modified? |
252b5132 RH |
6619 | |
6620 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6621 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6622 | |
6623 | case M_COP0: | |
6624 | s = "c0"; | |
6625 | goto copz; | |
6626 | case M_COP1: | |
6627 | s = "c1"; | |
6628 | goto copz; | |
6629 | case M_COP2: | |
6630 | s = "c2"; | |
6631 | goto copz; | |
6632 | case M_COP3: | |
6633 | s = "c3"; | |
6634 | copz: | |
6635 | /* For now we just do C (same as Cz). The parameter will be | |
6636 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6637 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6638 | break; |
252b5132 | 6639 | |
ea1fb5dc | 6640 | case M_MOVE: |
67c0d1eb | 6641 | move_register (dreg, sreg); |
8fc2e39e | 6642 | break; |
ea1fb5dc | 6643 | |
252b5132 RH |
6644 | #ifdef LOSING_COMPILER |
6645 | default: | |
6646 | /* Try and see if this is a new itbl instruction. | |
6647 | This code builds table entries out of the macros in mip_opcodes. | |
6648 | FIXME: For now we just assemble the expression and pass it's | |
6649 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6650 | We may want to have the assembler assemble this value, |
252b5132 RH |
6651 | so that we gain the assembler's knowledge of delay slots, |
6652 | symbols, etc. | |
6653 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6654 | if (itbl_have_entries |
252b5132 | 6655 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6656 | { |
252b5132 RH |
6657 | s = ip->insn_mo->name; |
6658 | s2 = "cop3"; | |
6659 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6660 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6661 | break; |
beae10d5 | 6662 | } |
252b5132 | 6663 | macro2 (ip); |
8fc2e39e | 6664 | break; |
252b5132 | 6665 | } |
8fc2e39e TS |
6666 | if (mips_opts.noat && used_at) |
6667 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6668 | } |
bdaaa2e1 | 6669 | |
252b5132 | 6670 | static void |
17a2f251 | 6671 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6672 | { |
6673 | register int treg, sreg, dreg, breg; | |
6674 | int tempreg; | |
6675 | int mask; | |
252b5132 RH |
6676 | int used_at; |
6677 | expressionS expr1; | |
6678 | const char *s; | |
6679 | const char *s2; | |
6680 | const char *fmt; | |
6681 | int likely = 0; | |
6682 | int dbl = 0; | |
6683 | int coproc = 0; | |
6684 | int lr = 0; | |
6685 | int imm = 0; | |
6686 | int off; | |
6687 | offsetT maxnum; | |
6688 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6689 | |
252b5132 RH |
6690 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6691 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6692 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6693 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6694 | |
252b5132 RH |
6695 | expr1.X_op = O_constant; |
6696 | expr1.X_op_symbol = NULL; | |
6697 | expr1.X_add_symbol = NULL; | |
6698 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6699 | |
252b5132 RH |
6700 | switch (mask) |
6701 | { | |
6702 | #endif /* LOSING_COMPILER */ | |
6703 | ||
6704 | case M_DMUL: | |
6705 | dbl = 1; | |
6706 | case M_MUL: | |
67c0d1eb RS |
6707 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6708 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6709 | break; |
252b5132 RH |
6710 | |
6711 | case M_DMUL_I: | |
6712 | dbl = 1; | |
6713 | case M_MUL_I: | |
6714 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6715 | not trying to be that fancy. GCC should do this for us | |
6716 | anyway. */ | |
8fc2e39e | 6717 | used_at = 1; |
67c0d1eb RS |
6718 | load_register (AT, &imm_expr, dbl); |
6719 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6720 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6721 | break; |
6722 | ||
6723 | case M_DMULO_I: | |
6724 | dbl = 1; | |
6725 | case M_MULO_I: | |
6726 | imm = 1; | |
6727 | goto do_mulo; | |
6728 | ||
6729 | case M_DMULO: | |
6730 | dbl = 1; | |
6731 | case M_MULO: | |
6732 | do_mulo: | |
7d10b47d | 6733 | start_noreorder (); |
8fc2e39e | 6734 | used_at = 1; |
252b5132 | 6735 | if (imm) |
67c0d1eb RS |
6736 | load_register (AT, &imm_expr, dbl); |
6737 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6738 | macro_build (NULL, "mflo", "d", dreg); | |
6739 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6740 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6741 | if (mips_trap) |
67c0d1eb | 6742 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6743 | else |
6744 | { | |
6745 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6746 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6747 | macro_build (NULL, "nop", "", 0); | |
6748 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6749 | } |
7d10b47d | 6750 | end_noreorder (); |
67c0d1eb | 6751 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6752 | break; |
6753 | ||
6754 | case M_DMULOU_I: | |
6755 | dbl = 1; | |
6756 | case M_MULOU_I: | |
6757 | imm = 1; | |
6758 | goto do_mulou; | |
6759 | ||
6760 | case M_DMULOU: | |
6761 | dbl = 1; | |
6762 | case M_MULOU: | |
6763 | do_mulou: | |
7d10b47d | 6764 | start_noreorder (); |
8fc2e39e | 6765 | used_at = 1; |
252b5132 | 6766 | if (imm) |
67c0d1eb RS |
6767 | load_register (AT, &imm_expr, dbl); |
6768 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6769 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6770 | macro_build (NULL, "mfhi", "d", AT); |
6771 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6772 | if (mips_trap) |
67c0d1eb | 6773 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6774 | else |
6775 | { | |
6776 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6777 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6778 | macro_build (NULL, "nop", "", 0); | |
6779 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6780 | } |
7d10b47d | 6781 | end_noreorder (); |
252b5132 RH |
6782 | break; |
6783 | ||
771c7ce4 | 6784 | case M_DROL: |
fef14a42 | 6785 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6786 | { |
6787 | if (dreg == sreg) | |
6788 | { | |
6789 | tempreg = AT; | |
6790 | used_at = 1; | |
6791 | } | |
6792 | else | |
6793 | { | |
6794 | tempreg = dreg; | |
82dd0097 | 6795 | } |
67c0d1eb RS |
6796 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6797 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6798 | break; |
82dd0097 | 6799 | } |
8fc2e39e | 6800 | used_at = 1; |
67c0d1eb RS |
6801 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6802 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6803 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6804 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6805 | break; |
6806 | ||
252b5132 | 6807 | case M_ROL: |
fef14a42 | 6808 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6809 | { |
6810 | if (dreg == sreg) | |
6811 | { | |
6812 | tempreg = AT; | |
6813 | used_at = 1; | |
6814 | } | |
6815 | else | |
6816 | { | |
6817 | tempreg = dreg; | |
82dd0097 | 6818 | } |
67c0d1eb RS |
6819 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6820 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6821 | break; |
82dd0097 | 6822 | } |
8fc2e39e | 6823 | used_at = 1; |
67c0d1eb RS |
6824 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6825 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6826 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6827 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6828 | break; |
6829 | ||
771c7ce4 TS |
6830 | case M_DROL_I: |
6831 | { | |
6832 | unsigned int rot; | |
82dd0097 | 6833 | char *l, *r; |
771c7ce4 TS |
6834 | |
6835 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6836 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6837 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6838 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6839 | { |
6840 | rot = (64 - rot) & 0x3f; | |
6841 | if (rot >= 32) | |
67c0d1eb | 6842 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6843 | else |
67c0d1eb | 6844 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6845 | break; |
60b63b72 | 6846 | } |
483fc7cd | 6847 | if (rot == 0) |
483fc7cd | 6848 | { |
67c0d1eb | 6849 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6850 | break; |
483fc7cd | 6851 | } |
82dd0097 CD |
6852 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6853 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6854 | rot &= 0x1f; | |
8fc2e39e | 6855 | used_at = 1; |
67c0d1eb RS |
6856 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6857 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6858 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6859 | } |
6860 | break; | |
6861 | ||
252b5132 | 6862 | case M_ROL_I: |
771c7ce4 TS |
6863 | { |
6864 | unsigned int rot; | |
6865 | ||
6866 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6867 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6868 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6869 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6870 | { |
67c0d1eb | 6871 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6872 | break; |
60b63b72 | 6873 | } |
483fc7cd | 6874 | if (rot == 0) |
483fc7cd | 6875 | { |
67c0d1eb | 6876 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6877 | break; |
483fc7cd | 6878 | } |
8fc2e39e | 6879 | used_at = 1; |
67c0d1eb RS |
6880 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6881 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6882 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6883 | } |
6884 | break; | |
6885 | ||
6886 | case M_DROR: | |
fef14a42 | 6887 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6888 | { |
67c0d1eb | 6889 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6890 | break; |
82dd0097 | 6891 | } |
8fc2e39e | 6892 | used_at = 1; |
67c0d1eb RS |
6893 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6894 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6895 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6896 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6897 | break; |
6898 | ||
6899 | case M_ROR: | |
fef14a42 | 6900 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6901 | { |
67c0d1eb | 6902 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6903 | break; |
82dd0097 | 6904 | } |
8fc2e39e | 6905 | used_at = 1; |
67c0d1eb RS |
6906 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6907 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6908 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6909 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6910 | break; |
6911 | ||
771c7ce4 TS |
6912 | case M_DROR_I: |
6913 | { | |
6914 | unsigned int rot; | |
82dd0097 | 6915 | char *l, *r; |
771c7ce4 TS |
6916 | |
6917 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6918 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6919 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6920 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6921 | { |
6922 | if (rot >= 32) | |
67c0d1eb | 6923 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6924 | else |
67c0d1eb | 6925 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6926 | break; |
82dd0097 | 6927 | } |
483fc7cd | 6928 | if (rot == 0) |
483fc7cd | 6929 | { |
67c0d1eb | 6930 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6931 | break; |
483fc7cd | 6932 | } |
82dd0097 CD |
6933 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6934 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6935 | rot &= 0x1f; | |
8fc2e39e | 6936 | used_at = 1; |
67c0d1eb RS |
6937 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6938 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6939 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6940 | } |
6941 | break; | |
6942 | ||
252b5132 | 6943 | case M_ROR_I: |
771c7ce4 TS |
6944 | { |
6945 | unsigned int rot; | |
6946 | ||
6947 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6948 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6949 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6950 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6951 | { |
67c0d1eb | 6952 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6953 | break; |
82dd0097 | 6954 | } |
483fc7cd | 6955 | if (rot == 0) |
483fc7cd | 6956 | { |
67c0d1eb | 6957 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6958 | break; |
483fc7cd | 6959 | } |
8fc2e39e | 6960 | used_at = 1; |
67c0d1eb RS |
6961 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
6962 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6963 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 6964 | } |
252b5132 RH |
6965 | break; |
6966 | ||
6967 | case M_S_DOB: | |
fef14a42 | 6968 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6969 | { |
6970 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6971 | break; |
252b5132 | 6972 | } |
e7af610e | 6973 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6974 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6975 | to adjust when storing to memory. */ | |
67c0d1eb RS |
6976 | macro_build (&offset_expr, "swc1", "T,o(b)", |
6977 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 6978 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6979 | macro_build (&offset_expr, "swc1", "T,o(b)", |
6980 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 6981 | break; |
252b5132 RH |
6982 | |
6983 | case M_SEQ: | |
6984 | if (sreg == 0) | |
67c0d1eb | 6985 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 6986 | else if (treg == 0) |
67c0d1eb | 6987 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6988 | else |
6989 | { | |
67c0d1eb RS |
6990 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
6991 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 6992 | } |
8fc2e39e | 6993 | break; |
252b5132 RH |
6994 | |
6995 | case M_SEQ_I: | |
6996 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6997 | { | |
67c0d1eb | 6998 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6999 | break; |
252b5132 RH |
7000 | } |
7001 | if (sreg == 0) | |
7002 | { | |
7003 | as_warn (_("Instruction %s: result is always false"), | |
7004 | ip->insn_mo->name); | |
67c0d1eb | 7005 | move_register (dreg, 0); |
8fc2e39e | 7006 | break; |
252b5132 RH |
7007 | } |
7008 | if (imm_expr.X_op == O_constant | |
7009 | && imm_expr.X_add_number >= 0 | |
7010 | && imm_expr.X_add_number < 0x10000) | |
7011 | { | |
67c0d1eb | 7012 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7013 | } |
7014 | else if (imm_expr.X_op == O_constant | |
7015 | && imm_expr.X_add_number > -0x8000 | |
7016 | && imm_expr.X_add_number < 0) | |
7017 | { | |
7018 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7019 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7020 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7021 | } |
7022 | else | |
7023 | { | |
67c0d1eb RS |
7024 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7025 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7026 | used_at = 1; |
7027 | } | |
67c0d1eb | 7028 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7029 | break; |
252b5132 RH |
7030 | |
7031 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7032 | s = "slt"; | |
7033 | goto sge; | |
7034 | case M_SGEU: | |
7035 | s = "sltu"; | |
7036 | sge: | |
67c0d1eb RS |
7037 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7038 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7039 | break; |
252b5132 RH |
7040 | |
7041 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7042 | case M_SGEU_I: | |
7043 | if (imm_expr.X_op == O_constant | |
7044 | && imm_expr.X_add_number >= -0x8000 | |
7045 | && imm_expr.X_add_number < 0x8000) | |
7046 | { | |
67c0d1eb RS |
7047 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7048 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7049 | } |
7050 | else | |
7051 | { | |
67c0d1eb RS |
7052 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7053 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7054 | dreg, sreg, AT); | |
252b5132 RH |
7055 | used_at = 1; |
7056 | } | |
67c0d1eb | 7057 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7058 | break; |
252b5132 RH |
7059 | |
7060 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7061 | s = "slt"; | |
7062 | goto sgt; | |
7063 | case M_SGTU: | |
7064 | s = "sltu"; | |
7065 | sgt: | |
67c0d1eb | 7066 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7067 | break; |
252b5132 RH |
7068 | |
7069 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7070 | s = "slt"; | |
7071 | goto sgti; | |
7072 | case M_SGTU_I: | |
7073 | s = "sltu"; | |
7074 | sgti: | |
8fc2e39e | 7075 | used_at = 1; |
67c0d1eb RS |
7076 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7077 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7078 | break; |
7079 | ||
2396cfb9 | 7080 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7081 | s = "slt"; |
7082 | goto sle; | |
7083 | case M_SLEU: | |
7084 | s = "sltu"; | |
7085 | sle: | |
67c0d1eb RS |
7086 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7087 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7088 | break; |
252b5132 | 7089 | |
2396cfb9 | 7090 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7091 | s = "slt"; |
7092 | goto slei; | |
7093 | case M_SLEU_I: | |
7094 | s = "sltu"; | |
7095 | slei: | |
8fc2e39e | 7096 | used_at = 1; |
67c0d1eb RS |
7097 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7098 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7099 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7100 | break; |
7101 | ||
7102 | case M_SLT_I: | |
7103 | if (imm_expr.X_op == O_constant | |
7104 | && imm_expr.X_add_number >= -0x8000 | |
7105 | && imm_expr.X_add_number < 0x8000) | |
7106 | { | |
67c0d1eb | 7107 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7108 | break; |
252b5132 | 7109 | } |
8fc2e39e | 7110 | used_at = 1; |
67c0d1eb RS |
7111 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7112 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7113 | break; |
7114 | ||
7115 | case M_SLTU_I: | |
7116 | if (imm_expr.X_op == O_constant | |
7117 | && imm_expr.X_add_number >= -0x8000 | |
7118 | && imm_expr.X_add_number < 0x8000) | |
7119 | { | |
67c0d1eb | 7120 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7121 | BFD_RELOC_LO16); |
8fc2e39e | 7122 | break; |
252b5132 | 7123 | } |
8fc2e39e | 7124 | used_at = 1; |
67c0d1eb RS |
7125 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7126 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7127 | break; |
7128 | ||
7129 | case M_SNE: | |
7130 | if (sreg == 0) | |
67c0d1eb | 7131 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7132 | else if (treg == 0) |
67c0d1eb | 7133 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7134 | else |
7135 | { | |
67c0d1eb RS |
7136 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7137 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7138 | } |
8fc2e39e | 7139 | break; |
252b5132 RH |
7140 | |
7141 | case M_SNE_I: | |
7142 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7143 | { | |
67c0d1eb | 7144 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7145 | break; |
252b5132 RH |
7146 | } |
7147 | if (sreg == 0) | |
7148 | { | |
7149 | as_warn (_("Instruction %s: result is always true"), | |
7150 | ip->insn_mo->name); | |
67c0d1eb RS |
7151 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7152 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7153 | break; |
252b5132 RH |
7154 | } |
7155 | if (imm_expr.X_op == O_constant | |
7156 | && imm_expr.X_add_number >= 0 | |
7157 | && imm_expr.X_add_number < 0x10000) | |
7158 | { | |
67c0d1eb | 7159 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7160 | } |
7161 | else if (imm_expr.X_op == O_constant | |
7162 | && imm_expr.X_add_number > -0x8000 | |
7163 | && imm_expr.X_add_number < 0) | |
7164 | { | |
7165 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7166 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7167 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7168 | } |
7169 | else | |
7170 | { | |
67c0d1eb RS |
7171 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7172 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7173 | used_at = 1; |
7174 | } | |
67c0d1eb | 7175 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7176 | break; |
252b5132 RH |
7177 | |
7178 | case M_DSUB_I: | |
7179 | dbl = 1; | |
7180 | case M_SUB_I: | |
7181 | if (imm_expr.X_op == O_constant | |
7182 | && imm_expr.X_add_number > -0x8000 | |
7183 | && imm_expr.X_add_number <= 0x8000) | |
7184 | { | |
7185 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7186 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7187 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7188 | break; |
252b5132 | 7189 | } |
8fc2e39e | 7190 | used_at = 1; |
67c0d1eb RS |
7191 | load_register (AT, &imm_expr, dbl); |
7192 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7193 | break; |
7194 | ||
7195 | case M_DSUBU_I: | |
7196 | dbl = 1; | |
7197 | case M_SUBU_I: | |
7198 | if (imm_expr.X_op == O_constant | |
7199 | && imm_expr.X_add_number > -0x8000 | |
7200 | && imm_expr.X_add_number <= 0x8000) | |
7201 | { | |
7202 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7203 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7204 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7205 | break; |
252b5132 | 7206 | } |
8fc2e39e | 7207 | used_at = 1; |
67c0d1eb RS |
7208 | load_register (AT, &imm_expr, dbl); |
7209 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7210 | break; |
7211 | ||
7212 | case M_TEQ_I: | |
7213 | s = "teq"; | |
7214 | goto trap; | |
7215 | case M_TGE_I: | |
7216 | s = "tge"; | |
7217 | goto trap; | |
7218 | case M_TGEU_I: | |
7219 | s = "tgeu"; | |
7220 | goto trap; | |
7221 | case M_TLT_I: | |
7222 | s = "tlt"; | |
7223 | goto trap; | |
7224 | case M_TLTU_I: | |
7225 | s = "tltu"; | |
7226 | goto trap; | |
7227 | case M_TNE_I: | |
7228 | s = "tne"; | |
7229 | trap: | |
8fc2e39e | 7230 | used_at = 1; |
67c0d1eb RS |
7231 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7232 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7233 | break; |
7234 | ||
252b5132 | 7235 | case M_TRUNCWS: |
43841e91 | 7236 | case M_TRUNCWD: |
e7af610e | 7237 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7238 | used_at = 1; |
252b5132 RH |
7239 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7240 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7241 | ||
7242 | /* | |
7243 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7244 | * or is there a reason for it? | |
7245 | */ | |
7d10b47d | 7246 | start_noreorder (); |
67c0d1eb RS |
7247 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7248 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7249 | macro_build (NULL, "nop", ""); | |
252b5132 | 7250 | expr1.X_add_number = 3; |
67c0d1eb | 7251 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7252 | expr1.X_add_number = 2; |
67c0d1eb RS |
7253 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7254 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7255 | macro_build (NULL, "nop", ""); | |
7256 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7257 | dreg, sreg); | |
7258 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7259 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7260 | end_noreorder (); |
252b5132 RH |
7261 | break; |
7262 | ||
7263 | case M_ULH: | |
7264 | s = "lb"; | |
7265 | goto ulh; | |
7266 | case M_ULHU: | |
7267 | s = "lbu"; | |
7268 | ulh: | |
8fc2e39e | 7269 | used_at = 1; |
252b5132 RH |
7270 | if (offset_expr.X_add_number >= 0x7fff) |
7271 | as_bad (_("operand overflow")); | |
252b5132 | 7272 | if (! target_big_endian) |
f9419b05 | 7273 | ++offset_expr.X_add_number; |
67c0d1eb | 7274 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7275 | if (! target_big_endian) |
f9419b05 | 7276 | --offset_expr.X_add_number; |
252b5132 | 7277 | else |
f9419b05 | 7278 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7279 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7280 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7281 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7282 | break; |
7283 | ||
7284 | case M_ULD: | |
7285 | s = "ldl"; | |
7286 | s2 = "ldr"; | |
7287 | off = 7; | |
7288 | goto ulw; | |
7289 | case M_ULW: | |
7290 | s = "lwl"; | |
7291 | s2 = "lwr"; | |
7292 | off = 3; | |
7293 | ulw: | |
7294 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7295 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7296 | if (treg != breg) |
7297 | tempreg = treg; | |
7298 | else | |
8fc2e39e TS |
7299 | { |
7300 | used_at = 1; | |
7301 | tempreg = AT; | |
7302 | } | |
252b5132 RH |
7303 | if (! target_big_endian) |
7304 | offset_expr.X_add_number += off; | |
67c0d1eb | 7305 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7306 | if (! target_big_endian) |
7307 | offset_expr.X_add_number -= off; | |
7308 | else | |
7309 | offset_expr.X_add_number += off; | |
67c0d1eb | 7310 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7311 | |
7312 | /* If necessary, move the result in tempreg the final destination. */ | |
7313 | if (treg == tempreg) | |
8fc2e39e | 7314 | break; |
af22f5b2 | 7315 | /* Protect second load's delay slot. */ |
017315e4 | 7316 | load_delay_nop (); |
67c0d1eb | 7317 | move_register (treg, tempreg); |
af22f5b2 | 7318 | break; |
252b5132 RH |
7319 | |
7320 | case M_ULD_A: | |
7321 | s = "ldl"; | |
7322 | s2 = "ldr"; | |
7323 | off = 7; | |
7324 | goto ulwa; | |
7325 | case M_ULW_A: | |
7326 | s = "lwl"; | |
7327 | s2 = "lwr"; | |
7328 | off = 3; | |
7329 | ulwa: | |
d6bc6245 | 7330 | used_at = 1; |
67c0d1eb | 7331 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7332 | if (breg != 0) |
67c0d1eb | 7333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7334 | if (! target_big_endian) |
7335 | expr1.X_add_number = off; | |
7336 | else | |
7337 | expr1.X_add_number = 0; | |
67c0d1eb | 7338 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7339 | if (! target_big_endian) |
7340 | expr1.X_add_number = 0; | |
7341 | else | |
7342 | expr1.X_add_number = off; | |
67c0d1eb | 7343 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7344 | break; |
7345 | ||
7346 | case M_ULH_A: | |
7347 | case M_ULHU_A: | |
d6bc6245 | 7348 | used_at = 1; |
67c0d1eb | 7349 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7350 | if (breg != 0) |
67c0d1eb | 7351 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7352 | if (target_big_endian) |
7353 | expr1.X_add_number = 0; | |
67c0d1eb | 7354 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7355 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7356 | if (target_big_endian) |
7357 | expr1.X_add_number = 1; | |
7358 | else | |
7359 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7360 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7361 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7362 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7363 | break; |
7364 | ||
7365 | case M_USH: | |
8fc2e39e | 7366 | used_at = 1; |
252b5132 RH |
7367 | if (offset_expr.X_add_number >= 0x7fff) |
7368 | as_bad (_("operand overflow")); | |
7369 | if (target_big_endian) | |
f9419b05 | 7370 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7371 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7372 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7373 | if (target_big_endian) |
f9419b05 | 7374 | --offset_expr.X_add_number; |
252b5132 | 7375 | else |
f9419b05 | 7376 | ++offset_expr.X_add_number; |
67c0d1eb | 7377 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7378 | break; |
7379 | ||
7380 | case M_USD: | |
7381 | s = "sdl"; | |
7382 | s2 = "sdr"; | |
7383 | off = 7; | |
7384 | goto usw; | |
7385 | case M_USW: | |
7386 | s = "swl"; | |
7387 | s2 = "swr"; | |
7388 | off = 3; | |
7389 | usw: | |
7390 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7391 | as_bad (_("operand overflow")); | |
7392 | if (! target_big_endian) | |
7393 | offset_expr.X_add_number += off; | |
67c0d1eb | 7394 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7395 | if (! target_big_endian) |
7396 | offset_expr.X_add_number -= off; | |
7397 | else | |
7398 | offset_expr.X_add_number += off; | |
67c0d1eb | 7399 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7400 | break; |
252b5132 RH |
7401 | |
7402 | case M_USD_A: | |
7403 | s = "sdl"; | |
7404 | s2 = "sdr"; | |
7405 | off = 7; | |
7406 | goto uswa; | |
7407 | case M_USW_A: | |
7408 | s = "swl"; | |
7409 | s2 = "swr"; | |
7410 | off = 3; | |
7411 | uswa: | |
d6bc6245 | 7412 | used_at = 1; |
67c0d1eb | 7413 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7414 | if (breg != 0) |
67c0d1eb | 7415 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7416 | if (! target_big_endian) |
7417 | expr1.X_add_number = off; | |
7418 | else | |
7419 | expr1.X_add_number = 0; | |
67c0d1eb | 7420 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7421 | if (! target_big_endian) |
7422 | expr1.X_add_number = 0; | |
7423 | else | |
7424 | expr1.X_add_number = off; | |
67c0d1eb | 7425 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7426 | break; |
7427 | ||
7428 | case M_USH_A: | |
d6bc6245 | 7429 | used_at = 1; |
67c0d1eb | 7430 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7431 | if (breg != 0) |
67c0d1eb | 7432 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7433 | if (! target_big_endian) |
7434 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7435 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7436 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7437 | if (! target_big_endian) |
7438 | expr1.X_add_number = 1; | |
7439 | else | |
7440 | expr1.X_add_number = 0; | |
67c0d1eb | 7441 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7442 | if (! target_big_endian) |
7443 | expr1.X_add_number = 0; | |
7444 | else | |
7445 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7446 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7447 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7448 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7449 | break; |
7450 | ||
7451 | default: | |
7452 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7453 | are added dynamically. */ |
252b5132 RH |
7454 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7455 | break; | |
7456 | } | |
8fc2e39e TS |
7457 | if (mips_opts.noat && used_at) |
7458 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7459 | } |
7460 | ||
7461 | /* Implement macros in mips16 mode. */ | |
7462 | ||
7463 | static void | |
17a2f251 | 7464 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7465 | { |
7466 | int mask; | |
7467 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7468 | expressionS expr1; |
7469 | int dbl; | |
7470 | const char *s, *s2, *s3; | |
7471 | ||
7472 | mask = ip->insn_mo->mask; | |
7473 | ||
bf12938e RS |
7474 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7475 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7476 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7477 | |
252b5132 RH |
7478 | expr1.X_op = O_constant; |
7479 | expr1.X_op_symbol = NULL; | |
7480 | expr1.X_add_symbol = NULL; | |
7481 | expr1.X_add_number = 1; | |
7482 | ||
7483 | dbl = 0; | |
7484 | ||
7485 | switch (mask) | |
7486 | { | |
7487 | default: | |
7488 | internalError (); | |
7489 | ||
7490 | case M_DDIV_3: | |
7491 | dbl = 1; | |
7492 | case M_DIV_3: | |
7493 | s = "mflo"; | |
7494 | goto do_div3; | |
7495 | case M_DREM_3: | |
7496 | dbl = 1; | |
7497 | case M_REM_3: | |
7498 | s = "mfhi"; | |
7499 | do_div3: | |
7d10b47d | 7500 | start_noreorder (); |
67c0d1eb | 7501 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7502 | expr1.X_add_number = 2; |
67c0d1eb RS |
7503 | macro_build (&expr1, "bnez", "x,p", yreg); |
7504 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7505 | |
252b5132 RH |
7506 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7507 | since that causes an overflow. We should do that as well, | |
7508 | but I don't see how to do the comparisons without a temporary | |
7509 | register. */ | |
7d10b47d | 7510 | end_noreorder (); |
67c0d1eb | 7511 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7512 | break; |
7513 | ||
7514 | case M_DIVU_3: | |
7515 | s = "divu"; | |
7516 | s2 = "mflo"; | |
7517 | goto do_divu3; | |
7518 | case M_REMU_3: | |
7519 | s = "divu"; | |
7520 | s2 = "mfhi"; | |
7521 | goto do_divu3; | |
7522 | case M_DDIVU_3: | |
7523 | s = "ddivu"; | |
7524 | s2 = "mflo"; | |
7525 | goto do_divu3; | |
7526 | case M_DREMU_3: | |
7527 | s = "ddivu"; | |
7528 | s2 = "mfhi"; | |
7529 | do_divu3: | |
7d10b47d | 7530 | start_noreorder (); |
67c0d1eb | 7531 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7532 | expr1.X_add_number = 2; |
67c0d1eb RS |
7533 | macro_build (&expr1, "bnez", "x,p", yreg); |
7534 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7535 | end_noreorder (); |
67c0d1eb | 7536 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7537 | break; |
7538 | ||
7539 | case M_DMUL: | |
7540 | dbl = 1; | |
7541 | case M_MUL: | |
67c0d1eb RS |
7542 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7543 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7544 | break; |
252b5132 RH |
7545 | |
7546 | case M_DSUBU_I: | |
7547 | dbl = 1; | |
7548 | goto do_subu; | |
7549 | case M_SUBU_I: | |
7550 | do_subu: | |
7551 | if (imm_expr.X_op != O_constant) | |
7552 | as_bad (_("Unsupported large constant")); | |
7553 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7554 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7555 | break; |
7556 | ||
7557 | case M_SUBU_I_2: | |
7558 | if (imm_expr.X_op != O_constant) | |
7559 | as_bad (_("Unsupported large constant")); | |
7560 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7561 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7562 | break; |
7563 | ||
7564 | case M_DSUBU_I_2: | |
7565 | if (imm_expr.X_op != O_constant) | |
7566 | as_bad (_("Unsupported large constant")); | |
7567 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7568 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7569 | break; |
7570 | ||
7571 | case M_BEQ: | |
7572 | s = "cmp"; | |
7573 | s2 = "bteqz"; | |
7574 | goto do_branch; | |
7575 | case M_BNE: | |
7576 | s = "cmp"; | |
7577 | s2 = "btnez"; | |
7578 | goto do_branch; | |
7579 | case M_BLT: | |
7580 | s = "slt"; | |
7581 | s2 = "btnez"; | |
7582 | goto do_branch; | |
7583 | case M_BLTU: | |
7584 | s = "sltu"; | |
7585 | s2 = "btnez"; | |
7586 | goto do_branch; | |
7587 | case M_BLE: | |
7588 | s = "slt"; | |
7589 | s2 = "bteqz"; | |
7590 | goto do_reverse_branch; | |
7591 | case M_BLEU: | |
7592 | s = "sltu"; | |
7593 | s2 = "bteqz"; | |
7594 | goto do_reverse_branch; | |
7595 | case M_BGE: | |
7596 | s = "slt"; | |
7597 | s2 = "bteqz"; | |
7598 | goto do_branch; | |
7599 | case M_BGEU: | |
7600 | s = "sltu"; | |
7601 | s2 = "bteqz"; | |
7602 | goto do_branch; | |
7603 | case M_BGT: | |
7604 | s = "slt"; | |
7605 | s2 = "btnez"; | |
7606 | goto do_reverse_branch; | |
7607 | case M_BGTU: | |
7608 | s = "sltu"; | |
7609 | s2 = "btnez"; | |
7610 | ||
7611 | do_reverse_branch: | |
7612 | tmp = xreg; | |
7613 | xreg = yreg; | |
7614 | yreg = tmp; | |
7615 | ||
7616 | do_branch: | |
67c0d1eb RS |
7617 | macro_build (NULL, s, "x,y", xreg, yreg); |
7618 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7619 | break; |
7620 | ||
7621 | case M_BEQ_I: | |
7622 | s = "cmpi"; | |
7623 | s2 = "bteqz"; | |
7624 | s3 = "x,U"; | |
7625 | goto do_branch_i; | |
7626 | case M_BNE_I: | |
7627 | s = "cmpi"; | |
7628 | s2 = "btnez"; | |
7629 | s3 = "x,U"; | |
7630 | goto do_branch_i; | |
7631 | case M_BLT_I: | |
7632 | s = "slti"; | |
7633 | s2 = "btnez"; | |
7634 | s3 = "x,8"; | |
7635 | goto do_branch_i; | |
7636 | case M_BLTU_I: | |
7637 | s = "sltiu"; | |
7638 | s2 = "btnez"; | |
7639 | s3 = "x,8"; | |
7640 | goto do_branch_i; | |
7641 | case M_BLE_I: | |
7642 | s = "slti"; | |
7643 | s2 = "btnez"; | |
7644 | s3 = "x,8"; | |
7645 | goto do_addone_branch_i; | |
7646 | case M_BLEU_I: | |
7647 | s = "sltiu"; | |
7648 | s2 = "btnez"; | |
7649 | s3 = "x,8"; | |
7650 | goto do_addone_branch_i; | |
7651 | case M_BGE_I: | |
7652 | s = "slti"; | |
7653 | s2 = "bteqz"; | |
7654 | s3 = "x,8"; | |
7655 | goto do_branch_i; | |
7656 | case M_BGEU_I: | |
7657 | s = "sltiu"; | |
7658 | s2 = "bteqz"; | |
7659 | s3 = "x,8"; | |
7660 | goto do_branch_i; | |
7661 | case M_BGT_I: | |
7662 | s = "slti"; | |
7663 | s2 = "bteqz"; | |
7664 | s3 = "x,8"; | |
7665 | goto do_addone_branch_i; | |
7666 | case M_BGTU_I: | |
7667 | s = "sltiu"; | |
7668 | s2 = "bteqz"; | |
7669 | s3 = "x,8"; | |
7670 | ||
7671 | do_addone_branch_i: | |
7672 | if (imm_expr.X_op != O_constant) | |
7673 | as_bad (_("Unsupported large constant")); | |
7674 | ++imm_expr.X_add_number; | |
7675 | ||
7676 | do_branch_i: | |
67c0d1eb RS |
7677 | macro_build (&imm_expr, s, s3, xreg); |
7678 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7679 | break; |
7680 | ||
7681 | case M_ABS: | |
7682 | expr1.X_add_number = 0; | |
67c0d1eb | 7683 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7684 | if (xreg != yreg) |
67c0d1eb | 7685 | move_register (xreg, yreg); |
252b5132 | 7686 | expr1.X_add_number = 2; |
67c0d1eb RS |
7687 | macro_build (&expr1, "bteqz", "p"); |
7688 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7689 | } |
7690 | } | |
7691 | ||
7692 | /* For consistency checking, verify that all bits are specified either | |
7693 | by the match/mask part of the instruction definition, or by the | |
7694 | operand list. */ | |
7695 | static int | |
17a2f251 | 7696 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7697 | { |
7698 | const char *p = opc->args; | |
7699 | char c; | |
7700 | unsigned long used_bits = opc->mask; | |
7701 | ||
7702 | if ((used_bits & opc->match) != opc->match) | |
7703 | { | |
7704 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7705 | opc->name, opc->args); | |
7706 | return 0; | |
7707 | } | |
7708 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7709 | while (*p) | |
7710 | switch (c = *p++) | |
7711 | { | |
7712 | case ',': break; | |
7713 | case '(': break; | |
7714 | case ')': break; | |
af7ee8bf CD |
7715 | case '+': |
7716 | switch (c = *p++) | |
7717 | { | |
7718 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7719 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7720 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7721 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7722 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7723 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7724 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7725 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7726 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7727 | case 'I': break; | |
af7ee8bf CD |
7728 | default: |
7729 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7730 | c, opc->name, opc->args); | |
7731 | return 0; | |
7732 | } | |
7733 | break; | |
252b5132 RH |
7734 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7735 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7736 | case 'A': break; | |
4372b673 | 7737 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7738 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7739 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7740 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7741 | case 'F': break; | |
7742 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7743 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7744 | case 'I': break; |
e972090a | 7745 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7746 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7747 | case 'L': break; |
7748 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7749 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7750 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7751 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7752 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7753 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7754 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7755 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7756 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7757 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7758 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7759 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7760 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7761 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7762 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7763 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7764 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7765 | case 'f': break; | |
7766 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7767 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7768 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7769 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7770 | case 'l': break; | |
7771 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7772 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7773 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7774 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7775 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7776 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7777 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7778 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7779 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7780 | case 'x': break; | |
7781 | case 'z': break; | |
7782 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7783 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7784 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7785 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7786 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7787 | case '[': break; | |
7788 | case ']': break; | |
252b5132 RH |
7789 | default: |
7790 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7791 | c, opc->name, opc->args); | |
7792 | return 0; | |
7793 | } | |
7794 | #undef USE_BITS | |
7795 | if (used_bits != 0xffffffff) | |
7796 | { | |
7797 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7798 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7799 | return 0; | |
7800 | } | |
7801 | return 1; | |
7802 | } | |
7803 | ||
7804 | /* This routine assembles an instruction into its binary format. As a | |
7805 | side effect, it sets one of the global variables imm_reloc or | |
7806 | offset_reloc to the type of relocation to do if one of the operands | |
7807 | is an address expression. */ | |
7808 | ||
7809 | static void | |
17a2f251 | 7810 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7811 | { |
7812 | char *s; | |
7813 | const char *args; | |
43841e91 | 7814 | char c = 0; |
252b5132 RH |
7815 | struct mips_opcode *insn; |
7816 | char *argsStart; | |
7817 | unsigned int regno; | |
7818 | unsigned int lastregno = 0; | |
af7ee8bf | 7819 | unsigned int lastpos = 0; |
071742cf | 7820 | unsigned int limlo, limhi; |
252b5132 RH |
7821 | char *s_reset; |
7822 | char save_c = 0; | |
252b5132 RH |
7823 | |
7824 | insn_error = NULL; | |
7825 | ||
7826 | /* If the instruction contains a '.', we first try to match an instruction | |
7827 | including the '.'. Then we try again without the '.'. */ | |
7828 | insn = NULL; | |
3882b010 | 7829 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7830 | continue; |
7831 | ||
7832 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7833 | the call to hash_find. Save the character we replaced just in case we | |
7834 | have to re-parse the instruction. */ | |
3882b010 | 7835 | if (ISSPACE (*s)) |
252b5132 RH |
7836 | { |
7837 | save_c = *s; | |
7838 | *s++ = '\0'; | |
7839 | } | |
bdaaa2e1 | 7840 | |
252b5132 RH |
7841 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7842 | ||
7843 | /* If we didn't find the instruction in the opcode table, try again, but | |
7844 | this time with just the instruction up to, but not including the | |
7845 | first '.'. */ | |
7846 | if (insn == NULL) | |
7847 | { | |
bdaaa2e1 | 7848 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7849 | if (save_c) |
7850 | *(--s) = save_c; | |
7851 | ||
7852 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7853 | for (s = str; |
7854 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7855 | ++s) | |
252b5132 RH |
7856 | continue; |
7857 | ||
7858 | /* If we did not find a '.', then we can quit now. */ | |
7859 | if (*s != '.') | |
7860 | { | |
7861 | insn_error = "unrecognized opcode"; | |
7862 | return; | |
7863 | } | |
7864 | ||
7865 | /* Lookup the instruction in the hash table. */ | |
7866 | *s++ = '\0'; | |
7867 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7868 | { | |
7869 | insn_error = "unrecognized opcode"; | |
7870 | return; | |
7871 | } | |
252b5132 RH |
7872 | } |
7873 | ||
7874 | argsStart = s; | |
7875 | for (;;) | |
7876 | { | |
b34976b6 | 7877 | bfd_boolean ok; |
252b5132 RH |
7878 | |
7879 | assert (strcmp (insn->name, str) == 0); | |
7880 | ||
1f25f5d3 CD |
7881 | if (OPCODE_IS_MEMBER (insn, |
7882 | (mips_opts.isa | |
3396de36 | 7883 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7884 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7885 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7886 | mips_opts.arch)) |
b34976b6 | 7887 | ok = TRUE; |
bdaaa2e1 | 7888 | else |
b34976b6 | 7889 | ok = FALSE; |
bdaaa2e1 | 7890 | |
252b5132 RH |
7891 | if (insn->pinfo != INSN_MACRO) |
7892 | { | |
fef14a42 | 7893 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7894 | ok = FALSE; |
252b5132 RH |
7895 | } |
7896 | ||
7897 | if (! ok) | |
7898 | { | |
7899 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7900 | && strcmp (insn->name, insn[1].name) == 0) | |
7901 | { | |
7902 | ++insn; | |
7903 | continue; | |
7904 | } | |
252b5132 | 7905 | else |
beae10d5 | 7906 | { |
268f6bed L |
7907 | if (!insn_error) |
7908 | { | |
7909 | static char buf[100]; | |
fef14a42 TS |
7910 | sprintf (buf, |
7911 | _("opcode not supported on this processor: %s (%s)"), | |
7912 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7913 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7914 | insn_error = buf; |
7915 | } | |
7916 | if (save_c) | |
7917 | *(--s) = save_c; | |
2bd7f1f3 | 7918 | return; |
252b5132 | 7919 | } |
252b5132 RH |
7920 | } |
7921 | ||
1e915849 | 7922 | create_insn (ip, insn); |
268f6bed | 7923 | insn_error = NULL; |
252b5132 RH |
7924 | for (args = insn->args;; ++args) |
7925 | { | |
deec1734 CD |
7926 | int is_mdmx; |
7927 | ||
ad8d3bb3 | 7928 | s += strspn (s, " \t"); |
deec1734 | 7929 | is_mdmx = 0; |
252b5132 RH |
7930 | switch (*args) |
7931 | { | |
7932 | case '\0': /* end of args */ | |
7933 | if (*s == '\0') | |
7934 | return; | |
7935 | break; | |
7936 | ||
7937 | case ',': | |
7938 | if (*s++ == *args) | |
7939 | continue; | |
7940 | s--; | |
7941 | switch (*++args) | |
7942 | { | |
7943 | case 'r': | |
7944 | case 'v': | |
bf12938e | 7945 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
7946 | continue; |
7947 | ||
7948 | case 'w': | |
bf12938e | 7949 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
7950 | continue; |
7951 | ||
252b5132 | 7952 | case 'W': |
bf12938e | 7953 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
7954 | continue; |
7955 | ||
7956 | case 'V': | |
bf12938e | 7957 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
7958 | continue; |
7959 | } | |
7960 | break; | |
7961 | ||
7962 | case '(': | |
7963 | /* Handle optional base register. | |
7964 | Either the base register is omitted or | |
bdaaa2e1 | 7965 | we must have a left paren. */ |
252b5132 RH |
7966 | /* This is dependent on the next operand specifier |
7967 | is a base register specification. */ | |
7968 | assert (args[1] == 'b' || args[1] == '5' | |
7969 | || args[1] == '-' || args[1] == '4'); | |
7970 | if (*s == '\0') | |
7971 | return; | |
7972 | ||
7973 | case ')': /* these must match exactly */ | |
60b63b72 RS |
7974 | case '[': |
7975 | case ']': | |
252b5132 RH |
7976 | if (*s++ == *args) |
7977 | continue; | |
7978 | break; | |
7979 | ||
af7ee8bf CD |
7980 | case '+': /* Opcode extension character. */ |
7981 | switch (*++args) | |
7982 | { | |
071742cf CD |
7983 | case 'A': /* ins/ext position, becomes LSB. */ |
7984 | limlo = 0; | |
7985 | limhi = 31; | |
5f74bc13 CD |
7986 | goto do_lsb; |
7987 | case 'E': | |
7988 | limlo = 32; | |
7989 | limhi = 63; | |
7990 | goto do_lsb; | |
7991 | do_lsb: | |
071742cf CD |
7992 | my_getExpression (&imm_expr, s); |
7993 | check_absolute_expr (ip, &imm_expr); | |
7994 | if ((unsigned long) imm_expr.X_add_number < limlo | |
7995 | || (unsigned long) imm_expr.X_add_number > limhi) | |
7996 | { | |
7997 | as_bad (_("Improper position (%lu)"), | |
7998 | (unsigned long) imm_expr.X_add_number); | |
7999 | imm_expr.X_add_number = limlo; | |
8000 | } | |
8001 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8002 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8003 | imm_expr.X_op = O_absent; |
8004 | s = expr_end; | |
8005 | continue; | |
8006 | ||
8007 | case 'B': /* ins size, becomes MSB. */ | |
8008 | limlo = 1; | |
8009 | limhi = 32; | |
5f74bc13 CD |
8010 | goto do_msb; |
8011 | case 'F': | |
8012 | limlo = 33; | |
8013 | limhi = 64; | |
8014 | goto do_msb; | |
8015 | do_msb: | |
071742cf CD |
8016 | my_getExpression (&imm_expr, s); |
8017 | check_absolute_expr (ip, &imm_expr); | |
8018 | /* Check for negative input so that small negative numbers | |
8019 | will not succeed incorrectly. The checks against | |
8020 | (pos+size) transitively check "size" itself, | |
8021 | assuming that "pos" is reasonable. */ | |
8022 | if ((long) imm_expr.X_add_number < 0 | |
8023 | || ((unsigned long) imm_expr.X_add_number | |
8024 | + lastpos) < limlo | |
8025 | || ((unsigned long) imm_expr.X_add_number | |
8026 | + lastpos) > limhi) | |
8027 | { | |
8028 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8029 | (unsigned long) imm_expr.X_add_number, | |
8030 | (unsigned long) lastpos); | |
8031 | imm_expr.X_add_number = limlo - lastpos; | |
8032 | } | |
bf12938e RS |
8033 | INSERT_OPERAND (INSMSB, *ip, |
8034 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8035 | imm_expr.X_op = O_absent; |
8036 | s = expr_end; | |
8037 | continue; | |
8038 | ||
8039 | case 'C': /* ext size, becomes MSBD. */ | |
8040 | limlo = 1; | |
8041 | limhi = 32; | |
5f74bc13 CD |
8042 | goto do_msbd; |
8043 | case 'G': | |
8044 | limlo = 33; | |
8045 | limhi = 64; | |
8046 | goto do_msbd; | |
8047 | case 'H': | |
8048 | limlo = 33; | |
8049 | limhi = 64; | |
8050 | goto do_msbd; | |
8051 | do_msbd: | |
071742cf CD |
8052 | my_getExpression (&imm_expr, s); |
8053 | check_absolute_expr (ip, &imm_expr); | |
8054 | /* Check for negative input so that small negative numbers | |
8055 | will not succeed incorrectly. The checks against | |
8056 | (pos+size) transitively check "size" itself, | |
8057 | assuming that "pos" is reasonable. */ | |
8058 | if ((long) imm_expr.X_add_number < 0 | |
8059 | || ((unsigned long) imm_expr.X_add_number | |
8060 | + lastpos) < limlo | |
8061 | || ((unsigned long) imm_expr.X_add_number | |
8062 | + lastpos) > limhi) | |
8063 | { | |
8064 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8065 | (unsigned long) imm_expr.X_add_number, | |
8066 | (unsigned long) lastpos); | |
8067 | imm_expr.X_add_number = limlo - lastpos; | |
8068 | } | |
bf12938e | 8069 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8070 | imm_expr.X_op = O_absent; |
8071 | s = expr_end; | |
8072 | continue; | |
af7ee8bf | 8073 | |
bbcc0807 CD |
8074 | case 'D': |
8075 | /* +D is for disassembly only; never match. */ | |
8076 | break; | |
8077 | ||
5f74bc13 CD |
8078 | case 'I': |
8079 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8080 | my_getExpression (&imm2_expr, s); | |
8081 | if (imm2_expr.X_op != O_big | |
8082 | && imm2_expr.X_op != O_constant) | |
8083 | insn_error = _("absolute expression required"); | |
13757d0c | 8084 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8085 | s = expr_end; |
8086 | continue; | |
8087 | ||
af7ee8bf CD |
8088 | default: |
8089 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8090 | *args, insn->name, insn->args); | |
8091 | /* Further processing is fruitless. */ | |
8092 | return; | |
8093 | } | |
8094 | break; | |
8095 | ||
252b5132 RH |
8096 | case '<': /* must be at least one digit */ |
8097 | /* | |
8098 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8099 | * than 31 or less than 0, then the shift amount should be |
8100 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8101 | * We issue a warning and mask out all but the low 5 bits. |
8102 | */ | |
8103 | my_getExpression (&imm_expr, s); | |
8104 | check_absolute_expr (ip, &imm_expr); | |
8105 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8106 | as_warn (_("Improper shift amount (%lu)"), |
8107 | (unsigned long) imm_expr.X_add_number); | |
8108 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8109 | imm_expr.X_op = O_absent; |
8110 | s = expr_end; | |
8111 | continue; | |
8112 | ||
8113 | case '>': /* shift amount minus 32 */ | |
8114 | my_getExpression (&imm_expr, s); | |
8115 | check_absolute_expr (ip, &imm_expr); | |
8116 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8117 | || (unsigned long) imm_expr.X_add_number > 63) | |
8118 | break; | |
bf12938e | 8119 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8120 | imm_expr.X_op = O_absent; |
8121 | s = expr_end; | |
8122 | continue; | |
8123 | ||
252b5132 RH |
8124 | case 'k': /* cache code */ |
8125 | case 'h': /* prefx code */ | |
8126 | my_getExpression (&imm_expr, s); | |
8127 | check_absolute_expr (ip, &imm_expr); | |
8128 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8129 | as_warn (_("Invalid value for `%s' (%lu)"), |
8130 | ip->insn_mo->name, | |
8131 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8132 | if (*args == 'k') |
bf12938e | 8133 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8134 | else |
bf12938e | 8135 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8136 | imm_expr.X_op = O_absent; |
8137 | s = expr_end; | |
8138 | continue; | |
8139 | ||
8140 | case 'c': /* break code */ | |
8141 | my_getExpression (&imm_expr, s); | |
8142 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8143 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8144 | as_warn (_("Illegal break code (%lu)"), |
8145 | (unsigned long) imm_expr.X_add_number); | |
8146 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8147 | imm_expr.X_op = O_absent; |
8148 | s = expr_end; | |
8149 | continue; | |
8150 | ||
8151 | case 'q': /* lower break code */ | |
8152 | my_getExpression (&imm_expr, s); | |
8153 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8154 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8155 | as_warn (_("Illegal lower break code (%lu)"), |
8156 | (unsigned long) imm_expr.X_add_number); | |
8157 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8158 | imm_expr.X_op = O_absent; |
8159 | s = expr_end; | |
8160 | continue; | |
8161 | ||
4372b673 | 8162 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8163 | my_getExpression (&imm_expr, s); |
156c2f8b | 8164 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8165 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8166 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8167 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8168 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8169 | imm_expr.X_op = O_absent; |
8170 | s = expr_end; | |
8171 | continue; | |
8172 | ||
98d3f06f | 8173 | case 'C': /* Coprocessor code */ |
beae10d5 | 8174 | my_getExpression (&imm_expr, s); |
252b5132 | 8175 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8176 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8177 | { |
793b27f4 TS |
8178 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8179 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8180 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8181 | } |
beae10d5 KH |
8182 | ip->insn_opcode |= imm_expr.X_add_number; |
8183 | imm_expr.X_op = O_absent; | |
8184 | s = expr_end; | |
8185 | continue; | |
252b5132 | 8186 | |
4372b673 NC |
8187 | case 'J': /* 19-bit wait code. */ |
8188 | my_getExpression (&imm_expr, s); | |
8189 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8190 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8191 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8192 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8193 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8194 | imm_expr.X_op = O_absent; |
8195 | s = expr_end; | |
8196 | continue; | |
8197 | ||
252b5132 | 8198 | case 'P': /* Performance register */ |
beae10d5 | 8199 | my_getExpression (&imm_expr, s); |
252b5132 | 8200 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8201 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8202 | as_warn (_("Invalid performance register (%lu)"), |
8203 | (unsigned long) imm_expr.X_add_number); | |
8204 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8205 | imm_expr.X_op = O_absent; |
8206 | s = expr_end; | |
8207 | continue; | |
252b5132 RH |
8208 | |
8209 | case 'b': /* base register */ | |
8210 | case 'd': /* destination register */ | |
8211 | case 's': /* source register */ | |
8212 | case 't': /* target register */ | |
8213 | case 'r': /* both target and source */ | |
8214 | case 'v': /* both dest and source */ | |
8215 | case 'w': /* both dest and target */ | |
8216 | case 'E': /* coprocessor target register */ | |
8217 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8218 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8219 | case 'x': /* ignore register name */ |
8220 | case 'z': /* must be zero register */ | |
4372b673 | 8221 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8222 | s_reset = s; |
8223 | if (s[0] == '$') | |
8224 | { | |
8225 | ||
3882b010 | 8226 | if (ISDIGIT (s[1])) |
252b5132 RH |
8227 | { |
8228 | ++s; | |
8229 | regno = 0; | |
8230 | do | |
8231 | { | |
8232 | regno *= 10; | |
8233 | regno += *s - '0'; | |
8234 | ++s; | |
8235 | } | |
3882b010 | 8236 | while (ISDIGIT (*s)); |
252b5132 RH |
8237 | if (regno > 31) |
8238 | as_bad (_("Invalid register number (%d)"), regno); | |
8239 | } | |
af7ee8bf | 8240 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8241 | goto notreg; |
8242 | else | |
8243 | { | |
76db943d TS |
8244 | if (s[1] == 'r' && s[2] == 'a') |
8245 | { | |
8246 | s += 3; | |
8247 | regno = RA; | |
8248 | } | |
8249 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8250 | { |
8251 | s += 3; | |
8252 | regno = FP; | |
8253 | } | |
8254 | else if (s[1] == 's' && s[2] == 'p') | |
8255 | { | |
8256 | s += 3; | |
8257 | regno = SP; | |
8258 | } | |
8259 | else if (s[1] == 'g' && s[2] == 'p') | |
8260 | { | |
8261 | s += 3; | |
8262 | regno = GP; | |
8263 | } | |
8264 | else if (s[1] == 'a' && s[2] == 't') | |
8265 | { | |
8266 | s += 3; | |
8267 | regno = AT; | |
8268 | } | |
8269 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8270 | { | |
8271 | s += 4; | |
8272 | regno = KT0; | |
8273 | } | |
8274 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8275 | { | |
8276 | s += 4; | |
8277 | regno = KT1; | |
8278 | } | |
85b51719 TS |
8279 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8280 | { | |
8281 | s += 5; | |
8282 | regno = ZERO; | |
8283 | } | |
252b5132 RH |
8284 | else if (itbl_have_entries) |
8285 | { | |
8286 | char *p, *n; | |
d7ba4a77 | 8287 | unsigned long r; |
252b5132 | 8288 | |
d7ba4a77 | 8289 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8290 | n = itbl_get_field (&p); /* n is name */ |
8291 | ||
d7ba4a77 ILT |
8292 | /* See if this is a register defined in an |
8293 | itbl entry. */ | |
8294 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8295 | { |
8296 | /* Get_field advances to the start of | |
8297 | the next field, so we need to back | |
d7ba4a77 | 8298 | rack to the end of the last field. */ |
bdaaa2e1 | 8299 | if (p) |
252b5132 | 8300 | s = p - 1; |
bdaaa2e1 | 8301 | else |
d7ba4a77 | 8302 | s = strchr (s, '\0'); |
252b5132 RH |
8303 | regno = r; |
8304 | } | |
8305 | else | |
8306 | goto notreg; | |
beae10d5 | 8307 | } |
252b5132 RH |
8308 | else |
8309 | goto notreg; | |
8310 | } | |
8311 | if (regno == AT | |
8312 | && ! mips_opts.noat | |
8313 | && *args != 'E' | |
af7ee8bf CD |
8314 | && *args != 'G' |
8315 | && *args != 'K') | |
252b5132 RH |
8316 | as_warn (_("Used $at without \".set noat\"")); |
8317 | c = *args; | |
8318 | if (*s == ' ') | |
f9419b05 | 8319 | ++s; |
252b5132 RH |
8320 | if (args[1] != *s) |
8321 | { | |
8322 | if (c == 'r' || c == 'v' || c == 'w') | |
8323 | { | |
8324 | regno = lastregno; | |
8325 | s = s_reset; | |
f9419b05 | 8326 | ++args; |
252b5132 RH |
8327 | } |
8328 | } | |
8329 | /* 'z' only matches $0. */ | |
8330 | if (c == 'z' && regno != 0) | |
8331 | break; | |
8332 | ||
bdaaa2e1 KH |
8333 | /* Now that we have assembled one operand, we use the args string |
8334 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8335 | switch (c) |
8336 | { | |
8337 | case 'r': | |
8338 | case 's': | |
8339 | case 'v': | |
8340 | case 'b': | |
bf12938e | 8341 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8342 | break; |
8343 | case 'd': | |
8344 | case 'G': | |
af7ee8bf | 8345 | case 'K': |
bf12938e | 8346 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8347 | break; |
4372b673 | 8348 | case 'U': |
bf12938e RS |
8349 | INSERT_OPERAND (RD, *ip, regno); |
8350 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8351 | break; |
252b5132 RH |
8352 | case 'w': |
8353 | case 't': | |
8354 | case 'E': | |
bf12938e | 8355 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8356 | break; |
8357 | case 'x': | |
8358 | /* This case exists because on the r3000 trunc | |
8359 | expands into a macro which requires a gp | |
8360 | register. On the r6000 or r4000 it is | |
8361 | assembled into a single instruction which | |
8362 | ignores the register. Thus the insn version | |
8363 | is MIPS_ISA2 and uses 'x', and the macro | |
8364 | version is MIPS_ISA1 and uses 't'. */ | |
8365 | break; | |
8366 | case 'z': | |
8367 | /* This case is for the div instruction, which | |
8368 | acts differently if the destination argument | |
8369 | is $0. This only matches $0, and is checked | |
8370 | outside the switch. */ | |
8371 | break; | |
8372 | case 'D': | |
8373 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8374 | break; | |
8375 | /* What about all other operands like 'i', which | |
8376 | can be specified in the opcode table? */ | |
8377 | } | |
8378 | lastregno = regno; | |
8379 | continue; | |
8380 | } | |
8381 | notreg: | |
8382 | switch (*args++) | |
8383 | { | |
8384 | case 'r': | |
8385 | case 'v': | |
bf12938e | 8386 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8387 | continue; |
8388 | case 'w': | |
bf12938e | 8389 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8390 | continue; |
8391 | } | |
8392 | break; | |
8393 | ||
deec1734 CD |
8394 | case 'O': /* MDMX alignment immediate constant. */ |
8395 | my_getExpression (&imm_expr, s); | |
8396 | check_absolute_expr (ip, &imm_expr); | |
8397 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8398 | as_warn ("Improper align amount (%ld), using low bits", |
8399 | (long) imm_expr.X_add_number); | |
8400 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8401 | imm_expr.X_op = O_absent; |
8402 | s = expr_end; | |
8403 | continue; | |
8404 | ||
8405 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8406 | if (s[0] != '$') | |
8407 | { | |
8408 | /* MDMX Immediate. */ | |
8409 | my_getExpression (&imm_expr, s); | |
8410 | check_absolute_expr (ip, &imm_expr); | |
8411 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8412 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8413 | (long) imm_expr.X_add_number); | |
8414 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8415 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8416 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8417 | else | |
8418 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8419 | imm_expr.X_op = O_absent; |
8420 | s = expr_end; | |
8421 | continue; | |
8422 | } | |
8423 | /* Not MDMX Immediate. Fall through. */ | |
8424 | case 'X': /* MDMX destination register. */ | |
8425 | case 'Y': /* MDMX source register. */ | |
8426 | case 'Z': /* MDMX target register. */ | |
8427 | is_mdmx = 1; | |
252b5132 RH |
8428 | case 'D': /* floating point destination register */ |
8429 | case 'S': /* floating point source register */ | |
8430 | case 'T': /* floating point target register */ | |
8431 | case 'R': /* floating point source register */ | |
8432 | case 'V': | |
8433 | case 'W': | |
8434 | s_reset = s; | |
deec1734 CD |
8435 | /* Accept $fN for FP and MDMX register numbers, and in |
8436 | addition accept $vN for MDMX register numbers. */ | |
8437 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8438 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8439 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8440 | { |
8441 | s += 2; | |
8442 | regno = 0; | |
8443 | do | |
8444 | { | |
8445 | regno *= 10; | |
8446 | regno += *s - '0'; | |
8447 | ++s; | |
8448 | } | |
3882b010 | 8449 | while (ISDIGIT (*s)); |
252b5132 RH |
8450 | |
8451 | if (regno > 31) | |
8452 | as_bad (_("Invalid float register number (%d)"), regno); | |
8453 | ||
8454 | if ((regno & 1) != 0 | |
ca4e0257 | 8455 | && HAVE_32BIT_FPRS |
252b5132 RH |
8456 | && ! (strcmp (str, "mtc1") == 0 |
8457 | || strcmp (str, "mfc1") == 0 | |
8458 | || strcmp (str, "lwc1") == 0 | |
8459 | || strcmp (str, "swc1") == 0 | |
8460 | || strcmp (str, "l.s") == 0 | |
8461 | || strcmp (str, "s.s") == 0)) | |
8462 | as_warn (_("Float register should be even, was %d"), | |
8463 | regno); | |
8464 | ||
8465 | c = *args; | |
8466 | if (*s == ' ') | |
f9419b05 | 8467 | ++s; |
252b5132 RH |
8468 | if (args[1] != *s) |
8469 | { | |
8470 | if (c == 'V' || c == 'W') | |
8471 | { | |
8472 | regno = lastregno; | |
8473 | s = s_reset; | |
f9419b05 | 8474 | ++args; |
252b5132 RH |
8475 | } |
8476 | } | |
8477 | switch (c) | |
8478 | { | |
8479 | case 'D': | |
deec1734 | 8480 | case 'X': |
bf12938e | 8481 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8482 | break; |
8483 | case 'V': | |
8484 | case 'S': | |
deec1734 | 8485 | case 'Y': |
bf12938e | 8486 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8487 | break; |
deec1734 CD |
8488 | case 'Q': |
8489 | /* This is like 'Z', but also needs to fix the MDMX | |
8490 | vector/scalar select bits. Note that the | |
8491 | scalar immediate case is handled above. */ | |
8492 | if (*s == '[') | |
8493 | { | |
8494 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8495 | int max_el = (is_qh ? 3 : 7); | |
8496 | s++; | |
8497 | my_getExpression(&imm_expr, s); | |
8498 | check_absolute_expr (ip, &imm_expr); | |
8499 | s = expr_end; | |
8500 | if (imm_expr.X_add_number > max_el) | |
8501 | as_bad(_("Bad element selector %ld"), | |
8502 | (long) imm_expr.X_add_number); | |
8503 | imm_expr.X_add_number &= max_el; | |
8504 | ip->insn_opcode |= (imm_expr.X_add_number | |
8505 | << (OP_SH_VSEL + | |
8506 | (is_qh ? 2 : 1))); | |
01a3f561 | 8507 | imm_expr.X_op = O_absent; |
deec1734 CD |
8508 | if (*s != ']') |
8509 | as_warn(_("Expecting ']' found '%s'"), s); | |
8510 | else | |
8511 | s++; | |
8512 | } | |
8513 | else | |
8514 | { | |
8515 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8516 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8517 | << OP_SH_VSEL); | |
8518 | else | |
8519 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8520 | OP_SH_VSEL); | |
8521 | } | |
8522 | /* Fall through */ | |
252b5132 RH |
8523 | case 'W': |
8524 | case 'T': | |
deec1734 | 8525 | case 'Z': |
bf12938e | 8526 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8527 | break; |
8528 | case 'R': | |
bf12938e | 8529 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8530 | break; |
8531 | } | |
8532 | lastregno = regno; | |
8533 | continue; | |
8534 | } | |
8535 | ||
252b5132 RH |
8536 | switch (*args++) |
8537 | { | |
8538 | case 'V': | |
bf12938e | 8539 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8540 | continue; |
8541 | case 'W': | |
bf12938e | 8542 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8543 | continue; |
8544 | } | |
8545 | break; | |
8546 | ||
8547 | case 'I': | |
8548 | my_getExpression (&imm_expr, s); | |
8549 | if (imm_expr.X_op != O_big | |
8550 | && imm_expr.X_op != O_constant) | |
8551 | insn_error = _("absolute expression required"); | |
13757d0c | 8552 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8553 | s = expr_end; |
8554 | continue; | |
8555 | ||
8556 | case 'A': | |
8557 | my_getExpression (&offset_expr, s); | |
f6688943 | 8558 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8559 | s = expr_end; |
8560 | continue; | |
8561 | ||
8562 | case 'F': | |
8563 | case 'L': | |
8564 | case 'f': | |
8565 | case 'l': | |
8566 | { | |
8567 | int f64; | |
ca4e0257 | 8568 | int using_gprs; |
252b5132 RH |
8569 | char *save_in; |
8570 | char *err; | |
8571 | unsigned char temp[8]; | |
8572 | int len; | |
8573 | unsigned int length; | |
8574 | segT seg; | |
8575 | subsegT subseg; | |
8576 | char *p; | |
8577 | ||
8578 | /* These only appear as the last operand in an | |
8579 | instruction, and every instruction that accepts | |
8580 | them in any variant accepts them in all variants. | |
8581 | This means we don't have to worry about backing out | |
8582 | any changes if the instruction does not match. | |
8583 | ||
8584 | The difference between them is the size of the | |
8585 | floating point constant and where it goes. For 'F' | |
8586 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8587 | is 32 bits. Where the constant is placed is based | |
8588 | on how the MIPS assembler does things: | |
8589 | F -- .rdata | |
8590 | L -- .lit8 | |
8591 | f -- immediate value | |
8592 | l -- .lit4 | |
8593 | ||
8594 | The .lit4 and .lit8 sections are only used if | |
8595 | permitted by the -G argument. | |
8596 | ||
ca4e0257 RS |
8597 | The code below needs to know whether the target register |
8598 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8599 | 'F' are used with GPR-based instructions and 'l' and | |
8600 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8601 | |
8602 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8603 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8604 | |
8605 | save_in = input_line_pointer; | |
8606 | input_line_pointer = s; | |
8607 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8608 | length = len; | |
8609 | s = input_line_pointer; | |
8610 | input_line_pointer = save_in; | |
8611 | if (err != NULL && *err != '\0') | |
8612 | { | |
8613 | as_bad (_("Bad floating point constant: %s"), err); | |
8614 | memset (temp, '\0', sizeof temp); | |
8615 | length = f64 ? 8 : 4; | |
8616 | } | |
8617 | ||
156c2f8b | 8618 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8619 | |
8620 | if (*args == 'f' | |
8621 | || (*args == 'l' | |
3e722fb5 | 8622 | && (g_switch_value < 4 |
252b5132 RH |
8623 | || (temp[0] == 0 && temp[1] == 0) |
8624 | || (temp[2] == 0 && temp[3] == 0)))) | |
8625 | { | |
8626 | imm_expr.X_op = O_constant; | |
8627 | if (! target_big_endian) | |
8628 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8629 | else | |
8630 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8631 | } | |
8632 | else if (length > 4 | |
119d663a | 8633 | && ! mips_disable_float_construction |
ca4e0257 RS |
8634 | /* Constants can only be constructed in GPRs and |
8635 | copied to FPRs if the GPRs are at least as wide | |
8636 | as the FPRs. Force the constant into memory if | |
8637 | we are using 64-bit FPRs but the GPRs are only | |
8638 | 32 bits wide. */ | |
8639 | && (using_gprs | |
8640 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8641 | && ((temp[0] == 0 && temp[1] == 0) |
8642 | || (temp[2] == 0 && temp[3] == 0)) | |
8643 | && ((temp[4] == 0 && temp[5] == 0) | |
8644 | || (temp[6] == 0 && temp[7] == 0))) | |
8645 | { | |
ca4e0257 RS |
8646 | /* The value is simple enough to load with a couple of |
8647 | instructions. If using 32-bit registers, set | |
8648 | imm_expr to the high order 32 bits and offset_expr to | |
8649 | the low order 32 bits. Otherwise, set imm_expr to | |
8650 | the entire 64 bit constant. */ | |
8651 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8652 | { |
8653 | imm_expr.X_op = O_constant; | |
8654 | offset_expr.X_op = O_constant; | |
8655 | if (! target_big_endian) | |
8656 | { | |
8657 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8658 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8659 | } | |
8660 | else | |
8661 | { | |
8662 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8663 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8664 | } | |
8665 | if (offset_expr.X_add_number == 0) | |
8666 | offset_expr.X_op = O_absent; | |
8667 | } | |
8668 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8669 | { | |
8670 | imm_expr.X_op = O_constant; | |
8671 | if (! target_big_endian) | |
8672 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8673 | else | |
8674 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8675 | } | |
8676 | else | |
8677 | { | |
8678 | imm_expr.X_op = O_big; | |
8679 | imm_expr.X_add_number = 4; | |
8680 | if (! target_big_endian) | |
8681 | { | |
8682 | generic_bignum[0] = bfd_getl16 (temp); | |
8683 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8684 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8685 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8686 | } | |
8687 | else | |
8688 | { | |
8689 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8690 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8691 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8692 | generic_bignum[3] = bfd_getb16 (temp); | |
8693 | } | |
8694 | } | |
8695 | } | |
8696 | else | |
8697 | { | |
8698 | const char *newname; | |
8699 | segT new_seg; | |
8700 | ||
8701 | /* Switch to the right section. */ | |
8702 | seg = now_seg; | |
8703 | subseg = now_subseg; | |
8704 | switch (*args) | |
8705 | { | |
8706 | default: /* unused default case avoids warnings. */ | |
8707 | case 'L': | |
8708 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8709 | if (g_switch_value >= 8) |
252b5132 RH |
8710 | newname = ".lit8"; |
8711 | break; | |
8712 | case 'F': | |
3e722fb5 | 8713 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8714 | break; |
8715 | case 'l': | |
4d0d148d | 8716 | assert (g_switch_value >= 4); |
252b5132 RH |
8717 | newname = ".lit4"; |
8718 | break; | |
8719 | } | |
8720 | new_seg = subseg_new (newname, (subsegT) 0); | |
8721 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8722 | bfd_set_section_flags (stdoutput, new_seg, | |
8723 | (SEC_ALLOC | |
8724 | | SEC_LOAD | |
8725 | | SEC_READONLY | |
8726 | | SEC_DATA)); | |
8727 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8728 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8729 | && strcmp (TARGET_OS, "elf") != 0) | |
8730 | record_alignment (new_seg, 4); | |
8731 | else | |
8732 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8733 | if (seg == now_seg) | |
8734 | as_bad (_("Can't use floating point insn in this section")); | |
8735 | ||
8736 | /* Set the argument to the current address in the | |
8737 | section. */ | |
8738 | offset_expr.X_op = O_symbol; | |
8739 | offset_expr.X_add_symbol = | |
8740 | symbol_new ("L0\001", now_seg, | |
8741 | (valueT) frag_now_fix (), frag_now); | |
8742 | offset_expr.X_add_number = 0; | |
8743 | ||
8744 | /* Put the floating point number into the section. */ | |
8745 | p = frag_more ((int) length); | |
8746 | memcpy (p, temp, length); | |
8747 | ||
8748 | /* Switch back to the original section. */ | |
8749 | subseg_set (seg, subseg); | |
8750 | } | |
8751 | } | |
8752 | continue; | |
8753 | ||
8754 | case 'i': /* 16 bit unsigned immediate */ | |
8755 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8756 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8757 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8758 | { |
8759 | int more; | |
5e0116d5 RS |
8760 | offsetT minval, maxval; |
8761 | ||
8762 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8763 | && strcmp (insn->name, insn[1].name) == 0); | |
8764 | ||
8765 | /* If the expression was written as an unsigned number, | |
8766 | only treat it as signed if there are no more | |
8767 | alternatives. */ | |
8768 | if (more | |
8769 | && *args == 'j' | |
8770 | && sizeof (imm_expr.X_add_number) <= 4 | |
8771 | && imm_expr.X_op == O_constant | |
8772 | && imm_expr.X_add_number < 0 | |
8773 | && imm_expr.X_unsigned | |
8774 | && HAVE_64BIT_GPRS) | |
8775 | break; | |
8776 | ||
8777 | /* For compatibility with older assemblers, we accept | |
8778 | 0x8000-0xffff as signed 16-bit numbers when only | |
8779 | signed numbers are allowed. */ | |
8780 | if (*args == 'i') | |
8781 | minval = 0, maxval = 0xffff; | |
8782 | else if (more) | |
8783 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8784 | else |
5e0116d5 RS |
8785 | minval = -0x8000, maxval = 0xffff; |
8786 | ||
8787 | if (imm_expr.X_op != O_constant | |
8788 | || imm_expr.X_add_number < minval | |
8789 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8790 | { |
8791 | if (more) | |
8792 | break; | |
2ae7e77b AH |
8793 | if (imm_expr.X_op == O_constant |
8794 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8795 | as_bad (_("expression out of range")); |
252b5132 RH |
8796 | } |
8797 | } | |
8798 | s = expr_end; | |
8799 | continue; | |
8800 | ||
8801 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8802 | /* Check whether there is only a single bracketed expression |
8803 | left. If so, it must be the base register and the | |
8804 | constant must be zero. */ | |
8805 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8806 | { | |
8807 | offset_expr.X_op = O_constant; | |
8808 | offset_expr.X_add_number = 0; | |
8809 | continue; | |
8810 | } | |
252b5132 RH |
8811 | |
8812 | /* If this value won't fit into a 16 bit offset, then go | |
8813 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8814 | code pattern. */ |
5e0116d5 | 8815 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8816 | && (offset_expr.X_op != O_constant |
8817 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8818 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8819 | break; |
8820 | ||
252b5132 RH |
8821 | s = expr_end; |
8822 | continue; | |
8823 | ||
8824 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8825 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8826 | my_getExpression (&offset_expr, s); |
8827 | s = expr_end; | |
8828 | continue; | |
8829 | ||
8830 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8831 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8832 | && imm_expr.X_op == O_constant | |
8833 | && (imm_expr.X_add_number < 0 | |
8834 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8835 | as_bad (_("lui expression not in range 0..65535")); |
8836 | s = expr_end; | |
8837 | continue; | |
8838 | ||
8839 | case 'a': /* 26 bit address */ | |
8840 | my_getExpression (&offset_expr, s); | |
8841 | s = expr_end; | |
f6688943 | 8842 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8843 | continue; |
8844 | ||
8845 | case 'N': /* 3 bit branch condition code */ | |
8846 | case 'M': /* 3 bit compare condition code */ | |
8847 | if (strncmp (s, "$fcc", 4) != 0) | |
8848 | break; | |
8849 | s += 4; | |
8850 | regno = 0; | |
8851 | do | |
8852 | { | |
8853 | regno *= 10; | |
8854 | regno += *s - '0'; | |
8855 | ++s; | |
8856 | } | |
3882b010 | 8857 | while (ISDIGIT (*s)); |
252b5132 | 8858 | if (regno > 7) |
30c378fd CD |
8859 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8860 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8861 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8862 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8863 | && (regno & 1) != 0) | |
8864 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8865 | str, regno); | |
8866 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8867 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8868 | && (regno & 3) != 0) | |
8869 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8870 | str, regno); | |
252b5132 | 8871 | if (*args == 'N') |
bf12938e | 8872 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 8873 | else |
bf12938e | 8874 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 8875 | continue; |
252b5132 | 8876 | |
156c2f8b NC |
8877 | case 'H': |
8878 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8879 | s += 2; | |
3882b010 | 8880 | if (ISDIGIT (*s)) |
156c2f8b NC |
8881 | { |
8882 | c = 0; | |
8883 | do | |
8884 | { | |
8885 | c *= 10; | |
8886 | c += *s - '0'; | |
8887 | ++s; | |
8888 | } | |
3882b010 | 8889 | while (ISDIGIT (*s)); |
156c2f8b NC |
8890 | } |
8891 | else | |
8892 | c = 8; /* Invalid sel value. */ | |
8893 | ||
8894 | if (c > 7) | |
8895 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8896 | ip->insn_opcode |= c; | |
8897 | continue; | |
8898 | ||
60b63b72 RS |
8899 | case 'e': |
8900 | /* Must be at least one digit. */ | |
8901 | my_getExpression (&imm_expr, s); | |
8902 | check_absolute_expr (ip, &imm_expr); | |
8903 | ||
8904 | if ((unsigned long) imm_expr.X_add_number | |
8905 | > (unsigned long) OP_MASK_VECBYTE) | |
8906 | { | |
8907 | as_bad (_("bad byte vector index (%ld)"), | |
8908 | (long) imm_expr.X_add_number); | |
8909 | imm_expr.X_add_number = 0; | |
8910 | } | |
8911 | ||
bf12938e | 8912 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8913 | imm_expr.X_op = O_absent; |
8914 | s = expr_end; | |
8915 | continue; | |
8916 | ||
8917 | case '%': | |
8918 | my_getExpression (&imm_expr, s); | |
8919 | check_absolute_expr (ip, &imm_expr); | |
8920 | ||
8921 | if ((unsigned long) imm_expr.X_add_number | |
8922 | > (unsigned long) OP_MASK_VECALIGN) | |
8923 | { | |
8924 | as_bad (_("bad byte vector index (%ld)"), | |
8925 | (long) imm_expr.X_add_number); | |
8926 | imm_expr.X_add_number = 0; | |
8927 | } | |
8928 | ||
bf12938e | 8929 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8930 | imm_expr.X_op = O_absent; |
8931 | s = expr_end; | |
8932 | continue; | |
8933 | ||
252b5132 RH |
8934 | default: |
8935 | as_bad (_("bad char = '%c'\n"), *args); | |
8936 | internalError (); | |
8937 | } | |
8938 | break; | |
8939 | } | |
8940 | /* Args don't match. */ | |
8941 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8942 | !strcmp (insn->name, insn[1].name)) | |
8943 | { | |
8944 | ++insn; | |
8945 | s = argsStart; | |
268f6bed | 8946 | insn_error = _("illegal operands"); |
252b5132 RH |
8947 | continue; |
8948 | } | |
268f6bed L |
8949 | if (save_c) |
8950 | *(--s) = save_c; | |
252b5132 RH |
8951 | insn_error = _("illegal operands"); |
8952 | return; | |
8953 | } | |
8954 | } | |
8955 | ||
8956 | /* This routine assembles an instruction into its binary format when | |
8957 | assembling for the mips16. As a side effect, it sets one of the | |
8958 | global variables imm_reloc or offset_reloc to the type of | |
8959 | relocation to do if one of the operands is an address expression. | |
8960 | It also sets mips16_small and mips16_ext if the user explicitly | |
8961 | requested a small or extended instruction. */ | |
8962 | ||
8963 | static void | |
17a2f251 | 8964 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8965 | { |
8966 | char *s; | |
8967 | const char *args; | |
8968 | struct mips_opcode *insn; | |
8969 | char *argsstart; | |
8970 | unsigned int regno; | |
8971 | unsigned int lastregno = 0; | |
8972 | char *s_reset; | |
d6f16593 | 8973 | size_t i; |
252b5132 RH |
8974 | |
8975 | insn_error = NULL; | |
8976 | ||
b34976b6 AM |
8977 | mips16_small = FALSE; |
8978 | mips16_ext = FALSE; | |
252b5132 | 8979 | |
3882b010 | 8980 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8981 | ; |
8982 | switch (*s) | |
8983 | { | |
8984 | case '\0': | |
8985 | break; | |
8986 | ||
8987 | case ' ': | |
8988 | *s++ = '\0'; | |
8989 | break; | |
8990 | ||
8991 | case '.': | |
8992 | if (s[1] == 't' && s[2] == ' ') | |
8993 | { | |
8994 | *s = '\0'; | |
b34976b6 | 8995 | mips16_small = TRUE; |
252b5132 RH |
8996 | s += 3; |
8997 | break; | |
8998 | } | |
8999 | else if (s[1] == 'e' && s[2] == ' ') | |
9000 | { | |
9001 | *s = '\0'; | |
b34976b6 | 9002 | mips16_ext = TRUE; |
252b5132 RH |
9003 | s += 3; |
9004 | break; | |
9005 | } | |
9006 | /* Fall through. */ | |
9007 | default: | |
9008 | insn_error = _("unknown opcode"); | |
9009 | return; | |
9010 | } | |
9011 | ||
9012 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9013 | mips16_small = TRUE; |
252b5132 RH |
9014 | |
9015 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9016 | { | |
9017 | insn_error = _("unrecognized opcode"); | |
9018 | return; | |
9019 | } | |
9020 | ||
9021 | argsstart = s; | |
9022 | for (;;) | |
9023 | { | |
9024 | assert (strcmp (insn->name, str) == 0); | |
9025 | ||
1e915849 | 9026 | create_insn (ip, insn); |
252b5132 | 9027 | imm_expr.X_op = O_absent; |
f6688943 TS |
9028 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9029 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9030 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9031 | imm2_expr.X_op = O_absent; |
252b5132 | 9032 | offset_expr.X_op = O_absent; |
f6688943 TS |
9033 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9034 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9035 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9036 | for (args = insn->args; 1; ++args) |
9037 | { | |
9038 | int c; | |
9039 | ||
9040 | if (*s == ' ') | |
9041 | ++s; | |
9042 | ||
9043 | /* In this switch statement we call break if we did not find | |
9044 | a match, continue if we did find a match, or return if we | |
9045 | are done. */ | |
9046 | ||
9047 | c = *args; | |
9048 | switch (c) | |
9049 | { | |
9050 | case '\0': | |
9051 | if (*s == '\0') | |
9052 | { | |
9053 | /* Stuff the immediate value in now, if we can. */ | |
9054 | if (imm_expr.X_op == O_constant | |
f6688943 | 9055 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9056 | && insn->pinfo != INSN_MACRO) |
9057 | { | |
d6f16593 MR |
9058 | valueT tmp; |
9059 | ||
9060 | switch (*offset_reloc) | |
9061 | { | |
9062 | case BFD_RELOC_MIPS16_HI16_S: | |
9063 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9064 | break; | |
9065 | ||
9066 | case BFD_RELOC_MIPS16_HI16: | |
9067 | tmp = imm_expr.X_add_number >> 16; | |
9068 | break; | |
9069 | ||
9070 | case BFD_RELOC_MIPS16_LO16: | |
9071 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9072 | - 0x8000; | |
9073 | break; | |
9074 | ||
9075 | case BFD_RELOC_UNUSED: | |
9076 | tmp = imm_expr.X_add_number; | |
9077 | break; | |
9078 | ||
9079 | default: | |
9080 | internalError (); | |
9081 | } | |
9082 | *offset_reloc = BFD_RELOC_UNUSED; | |
9083 | ||
c4e7957c | 9084 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9085 | tmp, TRUE, mips16_small, |
252b5132 RH |
9086 | mips16_ext, &ip->insn_opcode, |
9087 | &ip->use_extend, &ip->extend); | |
9088 | imm_expr.X_op = O_absent; | |
f6688943 | 9089 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9090 | } |
9091 | ||
9092 | return; | |
9093 | } | |
9094 | break; | |
9095 | ||
9096 | case ',': | |
9097 | if (*s++ == c) | |
9098 | continue; | |
9099 | s--; | |
9100 | switch (*++args) | |
9101 | { | |
9102 | case 'v': | |
bf12938e | 9103 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9104 | continue; |
9105 | case 'w': | |
bf12938e | 9106 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9107 | continue; |
9108 | } | |
9109 | break; | |
9110 | ||
9111 | case '(': | |
9112 | case ')': | |
9113 | if (*s++ == c) | |
9114 | continue; | |
9115 | break; | |
9116 | ||
9117 | case 'v': | |
9118 | case 'w': | |
9119 | if (s[0] != '$') | |
9120 | { | |
9121 | if (c == 'v') | |
bf12938e | 9122 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9123 | else |
bf12938e | 9124 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9125 | ++args; |
9126 | continue; | |
9127 | } | |
9128 | /* Fall through. */ | |
9129 | case 'x': | |
9130 | case 'y': | |
9131 | case 'z': | |
9132 | case 'Z': | |
9133 | case '0': | |
9134 | case 'S': | |
9135 | case 'R': | |
9136 | case 'X': | |
9137 | case 'Y': | |
9138 | if (s[0] != '$') | |
9139 | break; | |
9140 | s_reset = s; | |
3882b010 | 9141 | if (ISDIGIT (s[1])) |
252b5132 RH |
9142 | { |
9143 | ++s; | |
9144 | regno = 0; | |
9145 | do | |
9146 | { | |
9147 | regno *= 10; | |
9148 | regno += *s - '0'; | |
9149 | ++s; | |
9150 | } | |
3882b010 | 9151 | while (ISDIGIT (*s)); |
252b5132 RH |
9152 | if (regno > 31) |
9153 | { | |
9154 | as_bad (_("invalid register number (%d)"), regno); | |
9155 | regno = 2; | |
9156 | } | |
9157 | } | |
9158 | else | |
9159 | { | |
76db943d TS |
9160 | if (s[1] == 'r' && s[2] == 'a') |
9161 | { | |
9162 | s += 3; | |
9163 | regno = RA; | |
9164 | } | |
9165 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9166 | { |
9167 | s += 3; | |
9168 | regno = FP; | |
9169 | } | |
9170 | else if (s[1] == 's' && s[2] == 'p') | |
9171 | { | |
9172 | s += 3; | |
9173 | regno = SP; | |
9174 | } | |
9175 | else if (s[1] == 'g' && s[2] == 'p') | |
9176 | { | |
9177 | s += 3; | |
9178 | regno = GP; | |
9179 | } | |
9180 | else if (s[1] == 'a' && s[2] == 't') | |
9181 | { | |
9182 | s += 3; | |
9183 | regno = AT; | |
9184 | } | |
9185 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9186 | { | |
9187 | s += 4; | |
9188 | regno = KT0; | |
9189 | } | |
9190 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9191 | { | |
9192 | s += 4; | |
9193 | regno = KT1; | |
9194 | } | |
85b51719 TS |
9195 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9196 | { | |
9197 | s += 5; | |
9198 | regno = ZERO; | |
9199 | } | |
252b5132 RH |
9200 | else |
9201 | break; | |
9202 | } | |
9203 | ||
9204 | if (*s == ' ') | |
9205 | ++s; | |
9206 | if (args[1] != *s) | |
9207 | { | |
9208 | if (c == 'v' || c == 'w') | |
9209 | { | |
9210 | regno = mips16_to_32_reg_map[lastregno]; | |
9211 | s = s_reset; | |
f9419b05 | 9212 | ++args; |
252b5132 RH |
9213 | } |
9214 | } | |
9215 | ||
9216 | switch (c) | |
9217 | { | |
9218 | case 'x': | |
9219 | case 'y': | |
9220 | case 'z': | |
9221 | case 'v': | |
9222 | case 'w': | |
9223 | case 'Z': | |
9224 | regno = mips32_to_16_reg_map[regno]; | |
9225 | break; | |
9226 | ||
9227 | case '0': | |
9228 | if (regno != 0) | |
9229 | regno = ILLEGAL_REG; | |
9230 | break; | |
9231 | ||
9232 | case 'S': | |
9233 | if (regno != SP) | |
9234 | regno = ILLEGAL_REG; | |
9235 | break; | |
9236 | ||
9237 | case 'R': | |
9238 | if (regno != RA) | |
9239 | regno = ILLEGAL_REG; | |
9240 | break; | |
9241 | ||
9242 | case 'X': | |
9243 | case 'Y': | |
9244 | if (regno == AT && ! mips_opts.noat) | |
9245 | as_warn (_("used $at without \".set noat\"")); | |
9246 | break; | |
9247 | ||
9248 | default: | |
9249 | internalError (); | |
9250 | } | |
9251 | ||
9252 | if (regno == ILLEGAL_REG) | |
9253 | break; | |
9254 | ||
9255 | switch (c) | |
9256 | { | |
9257 | case 'x': | |
9258 | case 'v': | |
bf12938e | 9259 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9260 | break; |
9261 | case 'y': | |
9262 | case 'w': | |
bf12938e | 9263 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9264 | break; |
9265 | case 'z': | |
bf12938e | 9266 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9267 | break; |
9268 | case 'Z': | |
bf12938e | 9269 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9270 | case '0': |
9271 | case 'S': | |
9272 | case 'R': | |
9273 | break; | |
9274 | case 'X': | |
bf12938e | 9275 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9276 | break; |
9277 | case 'Y': | |
9278 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9279 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9280 | break; |
9281 | default: | |
9282 | internalError (); | |
9283 | } | |
9284 | ||
9285 | lastregno = regno; | |
9286 | continue; | |
9287 | ||
9288 | case 'P': | |
9289 | if (strncmp (s, "$pc", 3) == 0) | |
9290 | { | |
9291 | s += 3; | |
9292 | continue; | |
9293 | } | |
9294 | break; | |
9295 | ||
252b5132 RH |
9296 | case '5': |
9297 | case 'H': | |
9298 | case 'W': | |
9299 | case 'D': | |
9300 | case 'j': | |
252b5132 RH |
9301 | case 'V': |
9302 | case 'C': | |
9303 | case 'U': | |
9304 | case 'k': | |
9305 | case 'K': | |
d6f16593 MR |
9306 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9307 | if (i > 0) | |
252b5132 | 9308 | { |
d6f16593 | 9309 | if (imm_expr.X_op != O_constant) |
252b5132 | 9310 | { |
b34976b6 | 9311 | mips16_ext = TRUE; |
b34976b6 | 9312 | ip->use_extend = TRUE; |
252b5132 | 9313 | ip->extend = 0; |
252b5132 | 9314 | } |
d6f16593 MR |
9315 | else |
9316 | { | |
9317 | /* We need to relax this instruction. */ | |
9318 | *offset_reloc = *imm_reloc; | |
9319 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9320 | } | |
9321 | s = expr_end; | |
9322 | continue; | |
252b5132 | 9323 | } |
d6f16593 MR |
9324 | *imm_reloc = BFD_RELOC_UNUSED; |
9325 | /* Fall through. */ | |
9326 | case '<': | |
9327 | case '>': | |
9328 | case '[': | |
9329 | case ']': | |
9330 | case '4': | |
9331 | case '8': | |
9332 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9333 | if (imm_expr.X_op == O_register) |
9334 | { | |
9335 | /* What we thought was an expression turned out to | |
9336 | be a register. */ | |
9337 | ||
9338 | if (s[0] == '(' && args[1] == '(') | |
9339 | { | |
9340 | /* It looks like the expression was omitted | |
9341 | before a register indirection, which means | |
9342 | that the expression is implicitly zero. We | |
9343 | still set up imm_expr, so that we handle | |
9344 | explicit extensions correctly. */ | |
9345 | imm_expr.X_op = O_constant; | |
9346 | imm_expr.X_add_number = 0; | |
f6688943 | 9347 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9348 | continue; |
9349 | } | |
9350 | ||
9351 | break; | |
9352 | } | |
9353 | ||
9354 | /* We need to relax this instruction. */ | |
f6688943 | 9355 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9356 | s = expr_end; |
9357 | continue; | |
9358 | ||
9359 | case 'p': | |
9360 | case 'q': | |
9361 | case 'A': | |
9362 | case 'B': | |
9363 | case 'E': | |
9364 | /* We use offset_reloc rather than imm_reloc for the PC | |
9365 | relative operands. This lets macros with both | |
9366 | immediate and address operands work correctly. */ | |
9367 | my_getExpression (&offset_expr, s); | |
9368 | ||
9369 | if (offset_expr.X_op == O_register) | |
9370 | break; | |
9371 | ||
9372 | /* We need to relax this instruction. */ | |
f6688943 | 9373 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9374 | s = expr_end; |
9375 | continue; | |
9376 | ||
9377 | case '6': /* break code */ | |
9378 | my_getExpression (&imm_expr, s); | |
9379 | check_absolute_expr (ip, &imm_expr); | |
9380 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9381 | as_warn (_("Invalid value for `%s' (%lu)"), |
9382 | ip->insn_mo->name, | |
9383 | (unsigned long) imm_expr.X_add_number); | |
9384 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9385 | imm_expr.X_op = O_absent; |
9386 | s = expr_end; | |
9387 | continue; | |
9388 | ||
9389 | case 'a': /* 26 bit address */ | |
9390 | my_getExpression (&offset_expr, s); | |
9391 | s = expr_end; | |
f6688943 | 9392 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9393 | ip->insn_opcode <<= 16; |
9394 | continue; | |
9395 | ||
9396 | case 'l': /* register list for entry macro */ | |
9397 | case 'L': /* register list for exit macro */ | |
9398 | { | |
9399 | int mask; | |
9400 | ||
9401 | if (c == 'l') | |
9402 | mask = 0; | |
9403 | else | |
9404 | mask = 7 << 3; | |
9405 | while (*s != '\0') | |
9406 | { | |
9407 | int freg, reg1, reg2; | |
9408 | ||
9409 | while (*s == ' ' || *s == ',') | |
9410 | ++s; | |
9411 | if (*s != '$') | |
9412 | { | |
9413 | as_bad (_("can't parse register list")); | |
9414 | break; | |
9415 | } | |
9416 | ++s; | |
9417 | if (*s != 'f') | |
9418 | freg = 0; | |
9419 | else | |
9420 | { | |
9421 | freg = 1; | |
9422 | ++s; | |
9423 | } | |
9424 | reg1 = 0; | |
3882b010 | 9425 | while (ISDIGIT (*s)) |
252b5132 RH |
9426 | { |
9427 | reg1 *= 10; | |
9428 | reg1 += *s - '0'; | |
9429 | ++s; | |
9430 | } | |
9431 | if (*s == ' ') | |
9432 | ++s; | |
9433 | if (*s != '-') | |
9434 | reg2 = reg1; | |
9435 | else | |
9436 | { | |
9437 | ++s; | |
9438 | if (*s != '$') | |
9439 | break; | |
9440 | ++s; | |
9441 | if (freg) | |
9442 | { | |
9443 | if (*s == 'f') | |
9444 | ++s; | |
9445 | else | |
9446 | { | |
9447 | as_bad (_("invalid register list")); | |
9448 | break; | |
9449 | } | |
9450 | } | |
9451 | reg2 = 0; | |
3882b010 | 9452 | while (ISDIGIT (*s)) |
252b5132 RH |
9453 | { |
9454 | reg2 *= 10; | |
9455 | reg2 += *s - '0'; | |
9456 | ++s; | |
9457 | } | |
9458 | } | |
9459 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9460 | { | |
9461 | mask &= ~ (7 << 3); | |
9462 | mask |= 5 << 3; | |
9463 | } | |
9464 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9465 | { | |
9466 | mask &= ~ (7 << 3); | |
9467 | mask |= 6 << 3; | |
9468 | } | |
9469 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9470 | mask |= (reg2 - 3) << 3; | |
9471 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9472 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9473 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9474 | mask |= 1; |
9475 | else | |
9476 | { | |
9477 | as_bad (_("invalid register list")); | |
9478 | break; | |
9479 | } | |
9480 | } | |
9481 | /* The mask is filled in in the opcode table for the | |
9482 | benefit of the disassembler. We remove it before | |
9483 | applying the actual mask. */ | |
9484 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9485 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9486 | } | |
9487 | continue; | |
9488 | ||
9489 | case 'e': /* extend code */ | |
9490 | my_getExpression (&imm_expr, s); | |
9491 | check_absolute_expr (ip, &imm_expr); | |
9492 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9493 | { | |
9494 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9495 | ip->insn_mo->name, | |
9496 | (unsigned long) imm_expr.X_add_number); | |
9497 | imm_expr.X_add_number &= 0x7ff; | |
9498 | } | |
9499 | ip->insn_opcode |= imm_expr.X_add_number; | |
9500 | imm_expr.X_op = O_absent; | |
9501 | s = expr_end; | |
9502 | continue; | |
9503 | ||
9504 | default: | |
9505 | internalError (); | |
9506 | } | |
9507 | break; | |
9508 | } | |
9509 | ||
9510 | /* Args don't match. */ | |
9511 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9512 | strcmp (insn->name, insn[1].name) == 0) | |
9513 | { | |
9514 | ++insn; | |
9515 | s = argsstart; | |
9516 | continue; | |
9517 | } | |
9518 | ||
9519 | insn_error = _("illegal operands"); | |
9520 | ||
9521 | return; | |
9522 | } | |
9523 | } | |
9524 | ||
9525 | /* This structure holds information we know about a mips16 immediate | |
9526 | argument type. */ | |
9527 | ||
e972090a NC |
9528 | struct mips16_immed_operand |
9529 | { | |
252b5132 RH |
9530 | /* The type code used in the argument string in the opcode table. */ |
9531 | int type; | |
9532 | /* The number of bits in the short form of the opcode. */ | |
9533 | int nbits; | |
9534 | /* The number of bits in the extended form of the opcode. */ | |
9535 | int extbits; | |
9536 | /* The amount by which the short form is shifted when it is used; | |
9537 | for example, the sw instruction has a shift count of 2. */ | |
9538 | int shift; | |
9539 | /* The amount by which the short form is shifted when it is stored | |
9540 | into the instruction code. */ | |
9541 | int op_shift; | |
9542 | /* Non-zero if the short form is unsigned. */ | |
9543 | int unsp; | |
9544 | /* Non-zero if the extended form is unsigned. */ | |
9545 | int extu; | |
9546 | /* Non-zero if the value is PC relative. */ | |
9547 | int pcrel; | |
9548 | }; | |
9549 | ||
9550 | /* The mips16 immediate operand types. */ | |
9551 | ||
9552 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9553 | { | |
9554 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9555 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9556 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9557 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9558 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9559 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9560 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9561 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9562 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9563 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9564 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9565 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9566 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9567 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9568 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9569 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9570 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9571 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9572 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9573 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9574 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9575 | }; | |
9576 | ||
9577 | #define MIPS16_NUM_IMMED \ | |
9578 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9579 | ||
9580 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9581 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9582 | whether an extended value is needed; if one is needed, it sets | |
9583 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9584 | If SMALL is true, an unextended opcode was explicitly requested. | |
9585 | If EXT is true, an extended opcode was explicitly requested. If | |
9586 | WARN is true, warn if EXT does not match reality. */ | |
9587 | ||
9588 | static void | |
17a2f251 TS |
9589 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9590 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9591 | unsigned long *insn, bfd_boolean *use_extend, | |
9592 | unsigned short *extend) | |
252b5132 RH |
9593 | { |
9594 | register const struct mips16_immed_operand *op; | |
9595 | int mintiny, maxtiny; | |
b34976b6 | 9596 | bfd_boolean needext; |
252b5132 RH |
9597 | |
9598 | op = mips16_immed_operands; | |
9599 | while (op->type != type) | |
9600 | { | |
9601 | ++op; | |
9602 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9603 | } | |
9604 | ||
9605 | if (op->unsp) | |
9606 | { | |
9607 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9608 | { | |
9609 | mintiny = 1; | |
9610 | maxtiny = 1 << op->nbits; | |
9611 | } | |
9612 | else | |
9613 | { | |
9614 | mintiny = 0; | |
9615 | maxtiny = (1 << op->nbits) - 1; | |
9616 | } | |
9617 | } | |
9618 | else | |
9619 | { | |
9620 | mintiny = - (1 << (op->nbits - 1)); | |
9621 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9622 | } | |
9623 | ||
9624 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9625 | if (type == 'p' || type == 'q') | |
9626 | val /= 2; | |
9627 | ||
9628 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9629 | || val < (mintiny << op->shift) | |
9630 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9631 | needext = TRUE; |
252b5132 | 9632 | else |
b34976b6 | 9633 | needext = FALSE; |
252b5132 RH |
9634 | |
9635 | if (warn && ext && ! needext) | |
beae10d5 KH |
9636 | as_warn_where (file, line, |
9637 | _("extended operand requested but not required")); | |
252b5132 RH |
9638 | if (small && needext) |
9639 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9640 | ||
9641 | if (small || (! ext && ! needext)) | |
9642 | { | |
9643 | int insnval; | |
9644 | ||
b34976b6 | 9645 | *use_extend = FALSE; |
252b5132 RH |
9646 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9647 | insnval <<= op->op_shift; | |
9648 | *insn |= insnval; | |
9649 | } | |
9650 | else | |
9651 | { | |
9652 | long minext, maxext; | |
9653 | int extval; | |
9654 | ||
9655 | if (op->extu) | |
9656 | { | |
9657 | minext = 0; | |
9658 | maxext = (1 << op->extbits) - 1; | |
9659 | } | |
9660 | else | |
9661 | { | |
9662 | minext = - (1 << (op->extbits - 1)); | |
9663 | maxext = (1 << (op->extbits - 1)) - 1; | |
9664 | } | |
9665 | if (val < minext || val > maxext) | |
9666 | as_bad_where (file, line, | |
9667 | _("operand value out of range for instruction")); | |
9668 | ||
b34976b6 | 9669 | *use_extend = TRUE; |
252b5132 RH |
9670 | if (op->extbits == 16) |
9671 | { | |
9672 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9673 | val &= 0x1f; | |
9674 | } | |
9675 | else if (op->extbits == 15) | |
9676 | { | |
9677 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9678 | val &= 0xf; | |
9679 | } | |
9680 | else | |
9681 | { | |
9682 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9683 | val = 0; | |
9684 | } | |
9685 | ||
9686 | *extend = (unsigned short) extval; | |
9687 | *insn |= val; | |
9688 | } | |
9689 | } | |
9690 | \f | |
d6f16593 | 9691 | struct percent_op_match |
ad8d3bb3 | 9692 | { |
5e0116d5 RS |
9693 | const char *str; |
9694 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9695 | }; |
9696 | ||
9697 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9698 | { |
5e0116d5 | 9699 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9700 | #ifdef OBJ_ELF |
5e0116d5 RS |
9701 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9702 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9703 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9704 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9705 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9706 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9707 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9708 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9709 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9710 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9711 | {"%half", BFD_RELOC_16}, | |
9712 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9713 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9714 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9715 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9716 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9717 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9718 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9719 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9720 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9721 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9722 | #endif |
5e0116d5 | 9723 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9724 | }; |
9725 | ||
d6f16593 MR |
9726 | static const struct percent_op_match mips16_percent_op[] = |
9727 | { | |
9728 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9729 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9730 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9731 | }; | |
9732 | ||
252b5132 | 9733 | |
5e0116d5 RS |
9734 | /* Return true if *STR points to a relocation operator. When returning true, |
9735 | move *STR over the operator and store its relocation code in *RELOC. | |
9736 | Leave both *STR and *RELOC alone when returning false. */ | |
9737 | ||
9738 | static bfd_boolean | |
17a2f251 | 9739 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9740 | { |
d6f16593 MR |
9741 | const struct percent_op_match *percent_op; |
9742 | size_t limit, i; | |
9743 | ||
9744 | if (mips_opts.mips16) | |
9745 | { | |
9746 | percent_op = mips16_percent_op; | |
9747 | limit = ARRAY_SIZE (mips16_percent_op); | |
9748 | } | |
9749 | else | |
9750 | { | |
9751 | percent_op = mips_percent_op; | |
9752 | limit = ARRAY_SIZE (mips_percent_op); | |
9753 | } | |
76b3015f | 9754 | |
d6f16593 | 9755 | for (i = 0; i < limit; i++) |
5e0116d5 | 9756 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9757 | { |
3f98094e DJ |
9758 | int len = strlen (percent_op[i].str); |
9759 | ||
9760 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9761 | continue; | |
9762 | ||
5e0116d5 RS |
9763 | *str += strlen (percent_op[i].str); |
9764 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9765 | |
5e0116d5 RS |
9766 | /* Check whether the output BFD supports this relocation. |
9767 | If not, issue an error and fall back on something safe. */ | |
9768 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9769 | { |
5e0116d5 RS |
9770 | as_bad ("relocation %s isn't supported by the current ABI", |
9771 | percent_op[i].str); | |
01a3f561 | 9772 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9773 | } |
5e0116d5 | 9774 | return TRUE; |
394f9b3a | 9775 | } |
5e0116d5 | 9776 | return FALSE; |
394f9b3a | 9777 | } |
ad8d3bb3 | 9778 | |
ad8d3bb3 | 9779 | |
5e0116d5 RS |
9780 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9781 | expression in *EP and the relocations in the array starting | |
9782 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9783 | |
01a3f561 | 9784 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9785 | |
5e0116d5 | 9786 | static size_t |
17a2f251 TS |
9787 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9788 | char *str) | |
ad8d3bb3 | 9789 | { |
5e0116d5 RS |
9790 | bfd_reloc_code_real_type reversed_reloc[3]; |
9791 | size_t reloc_index, i; | |
09b8f35a RS |
9792 | int crux_depth, str_depth; |
9793 | char *crux; | |
5e0116d5 RS |
9794 | |
9795 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9796 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9797 | of the main expression and with CRUX_DEPTH containing the number | |
9798 | of open brackets at that point. */ | |
9799 | reloc_index = -1; | |
9800 | str_depth = 0; | |
9801 | do | |
fb1b3232 | 9802 | { |
09b8f35a RS |
9803 | reloc_index++; |
9804 | crux = str; | |
9805 | crux_depth = str_depth; | |
9806 | ||
9807 | /* Skip over whitespace and brackets, keeping count of the number | |
9808 | of brackets. */ | |
9809 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9810 | if (*str++ == '(') | |
9811 | str_depth++; | |
5e0116d5 | 9812 | } |
09b8f35a RS |
9813 | while (*str == '%' |
9814 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9815 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9816 | |
09b8f35a | 9817 | my_getExpression (ep, crux); |
5e0116d5 | 9818 | str = expr_end; |
394f9b3a | 9819 | |
5e0116d5 | 9820 | /* Match every open bracket. */ |
09b8f35a | 9821 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9822 | if (*str++ == ')') |
09b8f35a | 9823 | crux_depth--; |
394f9b3a | 9824 | |
09b8f35a | 9825 | if (crux_depth > 0) |
5e0116d5 | 9826 | as_bad ("unclosed '('"); |
394f9b3a | 9827 | |
5e0116d5 | 9828 | expr_end = str; |
252b5132 | 9829 | |
01a3f561 | 9830 | if (reloc_index != 0) |
64bdfcaf RS |
9831 | { |
9832 | prev_reloc_op_frag = frag_now; | |
9833 | for (i = 0; i < reloc_index; i++) | |
9834 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9835 | } | |
fb1b3232 | 9836 | |
5e0116d5 | 9837 | return reloc_index; |
252b5132 RH |
9838 | } |
9839 | ||
9840 | static void | |
17a2f251 | 9841 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9842 | { |
9843 | char *save_in; | |
98aa84af | 9844 | valueT val; |
252b5132 RH |
9845 | |
9846 | save_in = input_line_pointer; | |
9847 | input_line_pointer = str; | |
9848 | expression (ep); | |
9849 | expr_end = input_line_pointer; | |
9850 | input_line_pointer = save_in; | |
9851 | ||
9852 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9853 | then we bump the value of the symbol by 1 since that is how other | |
9854 | text symbols are handled. We don't bother to handle complex | |
9855 | expressions, just `.' plus or minus a constant. */ | |
9856 | if (mips_opts.mips16 | |
9857 | && ep->X_op == O_symbol | |
9858 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9859 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9860 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9861 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9862 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9863 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9864 | } |
9865 | ||
9866 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9867 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9868 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9869 | returned, or NULL on OK. */ |
9870 | ||
9871 | char * | |
17a2f251 | 9872 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9873 | { |
9874 | int prec; | |
9875 | LITTLENUM_TYPE words[4]; | |
9876 | char *t; | |
9877 | int i; | |
9878 | ||
9879 | switch (type) | |
9880 | { | |
9881 | case 'f': | |
9882 | prec = 2; | |
9883 | break; | |
9884 | ||
9885 | case 'd': | |
9886 | prec = 4; | |
9887 | break; | |
9888 | ||
9889 | default: | |
9890 | *sizeP = 0; | |
9891 | return _("bad call to md_atof"); | |
9892 | } | |
9893 | ||
9894 | t = atof_ieee (input_line_pointer, type, words); | |
9895 | if (t) | |
9896 | input_line_pointer = t; | |
9897 | ||
9898 | *sizeP = prec * 2; | |
9899 | ||
9900 | if (! target_big_endian) | |
9901 | { | |
9902 | for (i = prec - 1; i >= 0; i--) | |
9903 | { | |
17a2f251 | 9904 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9905 | litP += 2; |
9906 | } | |
9907 | } | |
9908 | else | |
9909 | { | |
9910 | for (i = 0; i < prec; i++) | |
9911 | { | |
17a2f251 | 9912 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9913 | litP += 2; |
9914 | } | |
9915 | } | |
bdaaa2e1 | 9916 | |
252b5132 RH |
9917 | return NULL; |
9918 | } | |
9919 | ||
9920 | void | |
17a2f251 | 9921 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9922 | { |
9923 | if (target_big_endian) | |
9924 | number_to_chars_bigendian (buf, val, n); | |
9925 | else | |
9926 | number_to_chars_littleendian (buf, val, n); | |
9927 | } | |
9928 | \f | |
ae948b86 | 9929 | #ifdef OBJ_ELF |
e013f690 TS |
9930 | static int support_64bit_objects(void) |
9931 | { | |
9932 | const char **list, **l; | |
aa3d8fdf | 9933 | int yes; |
e013f690 TS |
9934 | |
9935 | list = bfd_target_list (); | |
9936 | for (l = list; *l != NULL; l++) | |
9937 | #ifdef TE_TMIPS | |
9938 | /* This is traditional mips */ | |
9939 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9940 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9941 | #else | |
9942 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9943 | || strcmp (*l, "elf64-littlemips") == 0) | |
9944 | #endif | |
9945 | break; | |
aa3d8fdf | 9946 | yes = (*l != NULL); |
e013f690 | 9947 | free (list); |
aa3d8fdf | 9948 | return yes; |
e013f690 | 9949 | } |
ae948b86 | 9950 | #endif /* OBJ_ELF */ |
e013f690 | 9951 | |
78849248 | 9952 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 9953 | |
e972090a NC |
9954 | struct option md_longopts[] = |
9955 | { | |
f9b4148d CD |
9956 | /* Options which specify architecture. */ |
9957 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
9958 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
9959 | {"march", required_argument, NULL, OPTION_MARCH}, | |
9960 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
9961 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
9962 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
9963 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
9964 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 9965 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 9966 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 9967 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 9968 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 9969 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 9970 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 9971 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 9972 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 9973 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 9974 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 9975 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 9976 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
9977 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
9978 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
9979 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
9980 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
9981 | |
9982 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 9983 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
9984 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
9985 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
9986 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
9987 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
9988 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
9989 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
9990 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
9991 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
9992 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
9993 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
9994 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
9995 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
9996 | ||
9997 | /* Old-style architecture options. Don't add more of these. */ | |
9998 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
9999 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10000 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10001 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10002 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10003 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10004 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10005 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10006 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10007 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10008 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10009 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10010 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10011 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10012 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10013 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10014 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10015 | ||
10016 | /* Options which enable bug fixes. */ | |
10017 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10018 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10019 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10020 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10021 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10022 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10023 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10024 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10025 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10026 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10027 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10028 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10029 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10030 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10031 | |
10032 | /* Miscellaneous options. */ | |
7d8e00cf | 10033 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10034 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10035 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10036 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10037 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10038 | {"break", no_argument, NULL, OPTION_BREAK}, |
10039 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10040 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10041 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10042 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10043 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10044 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10045 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10046 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10047 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10048 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10049 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10050 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10051 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10052 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10053 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10054 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10055 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10056 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10057 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10058 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10059 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10060 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10061 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10062 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10063 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10064 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10065 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10066 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10067 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10068 | |
10069 | /* ELF-specific options. */ | |
156c2f8b | 10070 | #ifdef OBJ_ELF |
aed1a261 | 10071 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10072 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10073 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10074 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10075 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10076 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10077 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10078 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10079 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10080 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10081 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10082 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10083 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10084 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10085 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10086 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10087 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10088 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10089 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10090 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10091 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10092 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10093 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10094 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10095 | #endif /* OBJ_ELF */ |
f9b4148d | 10096 | |
252b5132 RH |
10097 | {NULL, no_argument, NULL, 0} |
10098 | }; | |
156c2f8b | 10099 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10100 | |
316f5878 RS |
10101 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10102 | NEW_VALUE. Warn if another value was already specified. Note: | |
10103 | we have to defer parsing the -march and -mtune arguments in order | |
10104 | to handle 'from-abi' correctly, since the ABI might be specified | |
10105 | in a later argument. */ | |
10106 | ||
10107 | static void | |
17a2f251 | 10108 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10109 | { |
10110 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10111 | as_warn (_("A different %s was already specified, is now %s"), | |
10112 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10113 | new_value); | |
10114 | ||
10115 | *string_ptr = new_value; | |
10116 | } | |
10117 | ||
252b5132 | 10118 | int |
17a2f251 | 10119 | md_parse_option (int c, char *arg) |
252b5132 RH |
10120 | { |
10121 | switch (c) | |
10122 | { | |
119d663a NC |
10123 | case OPTION_CONSTRUCT_FLOATS: |
10124 | mips_disable_float_construction = 0; | |
10125 | break; | |
bdaaa2e1 | 10126 | |
119d663a NC |
10127 | case OPTION_NO_CONSTRUCT_FLOATS: |
10128 | mips_disable_float_construction = 1; | |
10129 | break; | |
bdaaa2e1 | 10130 | |
252b5132 RH |
10131 | case OPTION_TRAP: |
10132 | mips_trap = 1; | |
10133 | break; | |
10134 | ||
10135 | case OPTION_BREAK: | |
10136 | mips_trap = 0; | |
10137 | break; | |
10138 | ||
10139 | case OPTION_EB: | |
10140 | target_big_endian = 1; | |
10141 | break; | |
10142 | ||
10143 | case OPTION_EL: | |
10144 | target_big_endian = 0; | |
10145 | break; | |
10146 | ||
10147 | case 'O': | |
10148 | if (arg && arg[1] == '0') | |
10149 | mips_optimize = 1; | |
10150 | else | |
10151 | mips_optimize = 2; | |
10152 | break; | |
10153 | ||
10154 | case 'g': | |
10155 | if (arg == NULL) | |
10156 | mips_debug = 2; | |
10157 | else | |
10158 | mips_debug = atoi (arg); | |
10159 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10160 | optimizations which limit full symbolic debugging. We take | |
10161 | that to be equivalent to -O0. */ | |
10162 | if (mips_debug == 2) | |
10163 | mips_optimize = 1; | |
10164 | break; | |
10165 | ||
10166 | case OPTION_MIPS1: | |
316f5878 | 10167 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10168 | break; |
10169 | ||
10170 | case OPTION_MIPS2: | |
316f5878 | 10171 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10172 | break; |
10173 | ||
10174 | case OPTION_MIPS3: | |
316f5878 | 10175 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10176 | break; |
10177 | ||
10178 | case OPTION_MIPS4: | |
316f5878 | 10179 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10180 | break; |
10181 | ||
84ea6cf2 | 10182 | case OPTION_MIPS5: |
316f5878 | 10183 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10184 | break; |
10185 | ||
e7af610e | 10186 | case OPTION_MIPS32: |
316f5878 | 10187 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10188 | break; |
10189 | ||
af7ee8bf CD |
10190 | case OPTION_MIPS32R2: |
10191 | file_mips_isa = ISA_MIPS32R2; | |
10192 | break; | |
10193 | ||
5f74bc13 CD |
10194 | case OPTION_MIPS64R2: |
10195 | file_mips_isa = ISA_MIPS64R2; | |
10196 | break; | |
10197 | ||
84ea6cf2 | 10198 | case OPTION_MIPS64: |
316f5878 | 10199 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10200 | break; |
10201 | ||
ec68c924 | 10202 | case OPTION_MTUNE: |
316f5878 RS |
10203 | mips_set_option_string (&mips_tune_string, arg); |
10204 | break; | |
ec68c924 | 10205 | |
316f5878 RS |
10206 | case OPTION_MARCH: |
10207 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10208 | break; |
10209 | ||
10210 | case OPTION_M4650: | |
316f5878 RS |
10211 | mips_set_option_string (&mips_arch_string, "4650"); |
10212 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10213 | break; |
10214 | ||
10215 | case OPTION_NO_M4650: | |
10216 | break; | |
10217 | ||
10218 | case OPTION_M4010: | |
316f5878 RS |
10219 | mips_set_option_string (&mips_arch_string, "4010"); |
10220 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10221 | break; |
10222 | ||
10223 | case OPTION_NO_M4010: | |
10224 | break; | |
10225 | ||
10226 | case OPTION_M4100: | |
316f5878 RS |
10227 | mips_set_option_string (&mips_arch_string, "4100"); |
10228 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10229 | break; |
10230 | ||
10231 | case OPTION_NO_M4100: | |
10232 | break; | |
10233 | ||
252b5132 | 10234 | case OPTION_M3900: |
316f5878 RS |
10235 | mips_set_option_string (&mips_arch_string, "3900"); |
10236 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10237 | break; |
bdaaa2e1 | 10238 | |
252b5132 RH |
10239 | case OPTION_NO_M3900: |
10240 | break; | |
10241 | ||
deec1734 CD |
10242 | case OPTION_MDMX: |
10243 | mips_opts.ase_mdmx = 1; | |
10244 | break; | |
10245 | ||
10246 | case OPTION_NO_MDMX: | |
10247 | mips_opts.ase_mdmx = 0; | |
10248 | break; | |
10249 | ||
252b5132 RH |
10250 | case OPTION_MIPS16: |
10251 | mips_opts.mips16 = 1; | |
7d10b47d | 10252 | mips_no_prev_insn (); |
252b5132 RH |
10253 | break; |
10254 | ||
10255 | case OPTION_NO_MIPS16: | |
10256 | mips_opts.mips16 = 0; | |
7d10b47d | 10257 | mips_no_prev_insn (); |
252b5132 RH |
10258 | break; |
10259 | ||
1f25f5d3 CD |
10260 | case OPTION_MIPS3D: |
10261 | mips_opts.ase_mips3d = 1; | |
10262 | break; | |
10263 | ||
10264 | case OPTION_NO_MIPS3D: | |
10265 | mips_opts.ase_mips3d = 0; | |
10266 | break; | |
10267 | ||
d766e8ec RS |
10268 | case OPTION_FIX_VR4120: |
10269 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10270 | break; |
10271 | ||
d766e8ec RS |
10272 | case OPTION_NO_FIX_VR4120: |
10273 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10274 | break; |
10275 | ||
7d8e00cf RS |
10276 | case OPTION_FIX_VR4130: |
10277 | mips_fix_vr4130 = 1; | |
10278 | break; | |
10279 | ||
10280 | case OPTION_NO_FIX_VR4130: | |
10281 | mips_fix_vr4130 = 0; | |
10282 | break; | |
10283 | ||
4a6a3df4 AO |
10284 | case OPTION_RELAX_BRANCH: |
10285 | mips_relax_branch = 1; | |
10286 | break; | |
10287 | ||
10288 | case OPTION_NO_RELAX_BRANCH: | |
10289 | mips_relax_branch = 0; | |
10290 | break; | |
10291 | ||
aa6975fb ILT |
10292 | case OPTION_MSHARED: |
10293 | mips_in_shared = TRUE; | |
10294 | break; | |
10295 | ||
10296 | case OPTION_MNO_SHARED: | |
10297 | mips_in_shared = FALSE; | |
10298 | break; | |
10299 | ||
aed1a261 RS |
10300 | case OPTION_MSYM32: |
10301 | mips_opts.sym32 = TRUE; | |
10302 | break; | |
10303 | ||
10304 | case OPTION_MNO_SYM32: | |
10305 | mips_opts.sym32 = FALSE; | |
10306 | break; | |
10307 | ||
0f074f60 | 10308 | #ifdef OBJ_ELF |
252b5132 RH |
10309 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10310 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10311 | intended to be compatible with Irix 5. */ | |
10312 | case OPTION_CALL_SHARED: | |
10313 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10314 | { | |
10315 | as_bad (_("-call_shared is supported only for ELF format")); | |
10316 | return 0; | |
10317 | } | |
10318 | mips_pic = SVR4_PIC; | |
143d77c5 | 10319 | mips_abicalls = TRUE; |
252b5132 RH |
10320 | if (g_switch_seen && g_switch_value != 0) |
10321 | { | |
10322 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10323 | return 0; | |
10324 | } | |
10325 | g_switch_value = 0; | |
10326 | break; | |
10327 | ||
10328 | case OPTION_NON_SHARED: | |
10329 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10330 | { | |
10331 | as_bad (_("-non_shared is supported only for ELF format")); | |
10332 | return 0; | |
10333 | } | |
10334 | mips_pic = NO_PIC; | |
143d77c5 | 10335 | mips_abicalls = FALSE; |
252b5132 RH |
10336 | break; |
10337 | ||
10338 | /* The -xgot option tells the assembler to use 32 offsets when | |
10339 | accessing the got in SVR4_PIC mode. It is for Irix | |
10340 | compatibility. */ | |
10341 | case OPTION_XGOT: | |
10342 | mips_big_got = 1; | |
10343 | break; | |
0f074f60 | 10344 | #endif /* OBJ_ELF */ |
252b5132 RH |
10345 | |
10346 | case 'G': | |
6caf9ef4 TS |
10347 | g_switch_value = atoi (arg); |
10348 | g_switch_seen = 1; | |
10349 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10350 | { |
3e722fb5 | 10351 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10352 | return 0; |
10353 | } | |
252b5132 RH |
10354 | break; |
10355 | ||
0f074f60 | 10356 | #ifdef OBJ_ELF |
34ba82a8 TS |
10357 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10358 | and -mabi=64. */ | |
252b5132 | 10359 | case OPTION_32: |
34ba82a8 TS |
10360 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10361 | { | |
10362 | as_bad (_("-32 is supported for ELF format only")); | |
10363 | return 0; | |
10364 | } | |
316f5878 | 10365 | mips_abi = O32_ABI; |
252b5132 RH |
10366 | break; |
10367 | ||
e013f690 | 10368 | case OPTION_N32: |
34ba82a8 TS |
10369 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10370 | { | |
10371 | as_bad (_("-n32 is supported for ELF format only")); | |
10372 | return 0; | |
10373 | } | |
316f5878 | 10374 | mips_abi = N32_ABI; |
e013f690 | 10375 | break; |
252b5132 | 10376 | |
e013f690 | 10377 | case OPTION_64: |
34ba82a8 TS |
10378 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10379 | { | |
10380 | as_bad (_("-64 is supported for ELF format only")); | |
10381 | return 0; | |
10382 | } | |
316f5878 | 10383 | mips_abi = N64_ABI; |
e013f690 TS |
10384 | if (! support_64bit_objects()) |
10385 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10386 | break; |
ae948b86 | 10387 | #endif /* OBJ_ELF */ |
252b5132 | 10388 | |
c97ef257 | 10389 | case OPTION_GP32: |
a325df1d | 10390 | file_mips_gp32 = 1; |
c97ef257 AH |
10391 | break; |
10392 | ||
10393 | case OPTION_GP64: | |
a325df1d | 10394 | file_mips_gp32 = 0; |
c97ef257 | 10395 | break; |
252b5132 | 10396 | |
ca4e0257 | 10397 | case OPTION_FP32: |
a325df1d | 10398 | file_mips_fp32 = 1; |
316f5878 RS |
10399 | break; |
10400 | ||
10401 | case OPTION_FP64: | |
10402 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10403 | break; |
10404 | ||
ae948b86 | 10405 | #ifdef OBJ_ELF |
252b5132 | 10406 | case OPTION_MABI: |
34ba82a8 TS |
10407 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10408 | { | |
10409 | as_bad (_("-mabi is supported for ELF format only")); | |
10410 | return 0; | |
10411 | } | |
e013f690 | 10412 | if (strcmp (arg, "32") == 0) |
316f5878 | 10413 | mips_abi = O32_ABI; |
e013f690 | 10414 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10415 | mips_abi = O64_ABI; |
e013f690 | 10416 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10417 | mips_abi = N32_ABI; |
e013f690 TS |
10418 | else if (strcmp (arg, "64") == 0) |
10419 | { | |
316f5878 | 10420 | mips_abi = N64_ABI; |
e013f690 TS |
10421 | if (! support_64bit_objects()) |
10422 | as_fatal (_("No compiled in support for 64 bit object file " | |
10423 | "format")); | |
10424 | } | |
10425 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10426 | mips_abi = EABI_ABI; |
e013f690 | 10427 | else |
da0e507f TS |
10428 | { |
10429 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10430 | return 0; | |
10431 | } | |
252b5132 | 10432 | break; |
e013f690 | 10433 | #endif /* OBJ_ELF */ |
252b5132 | 10434 | |
6b76fefe | 10435 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10436 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10437 | break; |
10438 | ||
9ee72ff1 | 10439 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10440 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10441 | break; |
10442 | ||
ecb4347a DJ |
10443 | #ifdef OBJ_ELF |
10444 | case OPTION_MDEBUG: | |
b34976b6 | 10445 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10446 | break; |
10447 | ||
10448 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10449 | mips_flag_mdebug = FALSE; |
ecb4347a | 10450 | break; |
dcd410fe RO |
10451 | |
10452 | case OPTION_PDR: | |
10453 | mips_flag_pdr = TRUE; | |
10454 | break; | |
10455 | ||
10456 | case OPTION_NO_PDR: | |
10457 | mips_flag_pdr = FALSE; | |
10458 | break; | |
ecb4347a DJ |
10459 | #endif /* OBJ_ELF */ |
10460 | ||
252b5132 RH |
10461 | default: |
10462 | return 0; | |
10463 | } | |
10464 | ||
10465 | return 1; | |
10466 | } | |
316f5878 RS |
10467 | \f |
10468 | /* Set up globals to generate code for the ISA or processor | |
10469 | described by INFO. */ | |
252b5132 | 10470 | |
252b5132 | 10471 | static void |
17a2f251 | 10472 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10473 | { |
316f5878 | 10474 | if (info != 0) |
252b5132 | 10475 | { |
fef14a42 TS |
10476 | file_mips_arch = info->cpu; |
10477 | mips_opts.arch = info->cpu; | |
316f5878 | 10478 | mips_opts.isa = info->isa; |
252b5132 | 10479 | } |
252b5132 RH |
10480 | } |
10481 | ||
252b5132 | 10482 | |
316f5878 | 10483 | /* Likewise for tuning. */ |
252b5132 | 10484 | |
316f5878 | 10485 | static void |
17a2f251 | 10486 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10487 | { |
10488 | if (info != 0) | |
fef14a42 | 10489 | mips_tune = info->cpu; |
316f5878 | 10490 | } |
80cc45a5 | 10491 | |
34ba82a8 | 10492 | |
252b5132 | 10493 | void |
17a2f251 | 10494 | mips_after_parse_args (void) |
e9670677 | 10495 | { |
fef14a42 TS |
10496 | const struct mips_cpu_info *arch_info = 0; |
10497 | const struct mips_cpu_info *tune_info = 0; | |
10498 | ||
e9670677 | 10499 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10500 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10501 | { |
6caf9ef4 | 10502 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10503 | as_bad (_("-G not supported in this configuration.")); |
10504 | g_switch_value = 0; | |
10505 | } | |
10506 | ||
cac012d6 AO |
10507 | if (mips_abi == NO_ABI) |
10508 | mips_abi = MIPS_DEFAULT_ABI; | |
10509 | ||
22923709 RS |
10510 | /* The following code determines the architecture and register size. |
10511 | Similar code was added to GCC 3.3 (see override_options() in | |
10512 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10513 | as much as possible. */ | |
e9670677 | 10514 | |
316f5878 | 10515 | if (mips_arch_string != 0) |
fef14a42 | 10516 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10517 | |
316f5878 | 10518 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10519 | { |
316f5878 | 10520 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10521 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10522 | the -march selection (if any). */ |
fef14a42 | 10523 | if (arch_info != 0) |
e9670677 | 10524 | { |
316f5878 RS |
10525 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10526 | There's no harm in specifying both as long as the ISA levels | |
10527 | are the same. */ | |
fef14a42 | 10528 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10529 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10530 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10531 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10532 | } |
316f5878 | 10533 | else |
fef14a42 | 10534 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10535 | } |
10536 | ||
fef14a42 TS |
10537 | if (arch_info == 0) |
10538 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10539 | |
fef14a42 | 10540 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10541 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10542 | arch_info->name); |
10543 | ||
10544 | mips_set_architecture (arch_info); | |
10545 | ||
10546 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10547 | if (mips_tune_string != 0) | |
10548 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10549 | |
fef14a42 TS |
10550 | if (tune_info == 0) |
10551 | mips_set_tune (arch_info); | |
10552 | else | |
10553 | mips_set_tune (tune_info); | |
e9670677 | 10554 | |
316f5878 | 10555 | if (file_mips_gp32 >= 0) |
e9670677 | 10556 | { |
316f5878 RS |
10557 | /* The user specified the size of the integer registers. Make sure |
10558 | it agrees with the ABI and ISA. */ | |
10559 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10560 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10561 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10562 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10563 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10564 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10565 | } |
10566 | else | |
10567 | { | |
316f5878 RS |
10568 | /* Infer the integer register size from the ABI and processor. |
10569 | Restrict ourselves to 32-bit registers if that's all the | |
10570 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10571 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10572 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10573 | } |
10574 | ||
316f5878 RS |
10575 | /* ??? GAS treats single-float processors as though they had 64-bit |
10576 | float registers (although it complains when double-precision | |
10577 | instructions are used). As things stand, saying they have 32-bit | |
10578 | registers would lead to spurious "register must be even" messages. | |
10579 | So here we assume float registers are always the same size as | |
10580 | integer ones, unless the user says otherwise. */ | |
10581 | if (file_mips_fp32 < 0) | |
10582 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10583 | |
316f5878 | 10584 | /* End of GCC-shared inference code. */ |
e9670677 | 10585 | |
17a2f251 TS |
10586 | /* This flag is set when we have a 64-bit capable CPU but use only |
10587 | 32-bit wide registers. Note that EABI does not use it. */ | |
10588 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10589 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10590 | || mips_abi == O32_ABI)) | |
316f5878 | 10591 | mips_32bitmode = 1; |
e9670677 MR |
10592 | |
10593 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10594 | as_bad (_("trap exception not supported at ISA 1")); | |
10595 | ||
e9670677 MR |
10596 | /* If the selected architecture includes support for ASEs, enable |
10597 | generation of code for them. */ | |
a4672219 | 10598 | if (mips_opts.mips16 == -1) |
fef14a42 | 10599 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10600 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10601 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10602 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10603 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10604 | |
e9670677 | 10605 | file_mips_isa = mips_opts.isa; |
a4672219 | 10606 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10607 | file_ase_mips3d = mips_opts.ase_mips3d; |
10608 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10609 | mips_opts.gp32 = file_mips_gp32; | |
10610 | mips_opts.fp32 = file_mips_fp32; | |
10611 | ||
ecb4347a DJ |
10612 | if (mips_flag_mdebug < 0) |
10613 | { | |
10614 | #ifdef OBJ_MAYBE_ECOFF | |
10615 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10616 | mips_flag_mdebug = 1; | |
10617 | else | |
10618 | #endif /* OBJ_MAYBE_ECOFF */ | |
10619 | mips_flag_mdebug = 0; | |
10620 | } | |
e9670677 MR |
10621 | } |
10622 | \f | |
10623 | void | |
17a2f251 | 10624 | mips_init_after_args (void) |
252b5132 RH |
10625 | { |
10626 | /* initialize opcodes */ | |
10627 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10628 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10629 | } |
10630 | ||
10631 | long | |
17a2f251 | 10632 | md_pcrel_from (fixS *fixP) |
252b5132 | 10633 | { |
a7ebbfdf TS |
10634 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10635 | switch (fixP->fx_r_type) | |
10636 | { | |
10637 | case BFD_RELOC_16_PCREL_S2: | |
10638 | case BFD_RELOC_MIPS_JMP: | |
10639 | /* Return the address of the delay slot. */ | |
10640 | return addr + 4; | |
10641 | default: | |
10642 | return addr; | |
10643 | } | |
252b5132 RH |
10644 | } |
10645 | ||
252b5132 RH |
10646 | /* This is called before the symbol table is processed. In order to |
10647 | work with gcc when using mips-tfile, we must keep all local labels. | |
10648 | However, in other cases, we want to discard them. If we were | |
10649 | called with -g, but we didn't see any debugging information, it may | |
10650 | mean that gcc is smuggling debugging information through to | |
10651 | mips-tfile, in which case we must generate all local labels. */ | |
10652 | ||
10653 | void | |
17a2f251 | 10654 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10655 | { |
10656 | #ifndef NO_ECOFF_DEBUGGING | |
10657 | if (ECOFF_DEBUGGING | |
10658 | && mips_debug != 0 | |
10659 | && ! ecoff_debugging_seen) | |
10660 | flag_keep_locals = 1; | |
10661 | #endif | |
10662 | } | |
10663 | ||
3b91255e RS |
10664 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10665 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10666 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10667 | relocation operators. | |
10668 | ||
10669 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10670 | expression if: | |
10671 | ||
10672 | (a) it refers to the same symbol; and | |
10673 | (b) the offset applied in the %lo() expression is no lower than | |
10674 | the offset applied in the %got() or %hi(). | |
10675 | ||
10676 | (b) allows us to cope with code like: | |
10677 | ||
10678 | lui $4,%hi(foo) | |
10679 | lh $4,%lo(foo+2)($4) | |
10680 | ||
10681 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10682 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10683 | the high 16 bits. | |
10684 | ||
10685 | When several %lo()s match a particular %got() or %hi(), we use the | |
10686 | following rules to distinguish them: | |
10687 | ||
10688 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10689 | higher offsets. | |
10690 | ||
10691 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10692 | that already have a matching %got() or %hi(). | |
10693 | ||
10694 | (3) later %lo()s are better than earlier %lo()s. | |
10695 | ||
10696 | These rules are applied in order. | |
10697 | ||
10698 | (1) means, among other things, that %lo()s with identical offsets are | |
10699 | chosen if they exist. | |
10700 | ||
10701 | (2) means that we won't associate several high-part relocations with | |
10702 | the same low-part relocation unless there's no alternative. Having | |
10703 | several high parts for the same low part is a GNU extension; this rule | |
10704 | allows careful users to avoid it. | |
10705 | ||
10706 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10707 | with the last high-part relocation being at the front of the list. | |
10708 | It therefore makes sense to choose the last matching low-part | |
10709 | relocation, all other things being equal. It's also easier | |
10710 | to code that way. */ | |
252b5132 RH |
10711 | |
10712 | void | |
17a2f251 | 10713 | mips_frob_file (void) |
252b5132 RH |
10714 | { |
10715 | struct mips_hi_fixup *l; | |
10716 | ||
10717 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10718 | { | |
10719 | segment_info_type *seginfo; | |
3b91255e RS |
10720 | bfd_boolean matched_lo_p; |
10721 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10722 | |
5919d012 | 10723 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10724 | |
5919d012 RS |
10725 | /* If a GOT16 relocation turns out to be against a global symbol, |
10726 | there isn't supposed to be a matching LO. */ | |
10727 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10728 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10729 | continue; | |
10730 | ||
10731 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10732 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10733 | continue; |
10734 | ||
252b5132 | 10735 | seginfo = seg_info (l->seg); |
252b5132 | 10736 | |
3b91255e RS |
10737 | /* Set HI_POS to the position of this relocation in the chain. |
10738 | Set LO_POS to the position of the chosen low-part relocation. | |
10739 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10740 | relocation that matches an immediately-preceding high-part | |
10741 | relocation. */ | |
10742 | hi_pos = NULL; | |
10743 | lo_pos = NULL; | |
10744 | matched_lo_p = FALSE; | |
10745 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10746 | { | |
10747 | if (*pos == l->fixp) | |
10748 | hi_pos = pos; | |
10749 | ||
10750 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10751 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10752 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10753 | && (lo_pos == NULL | |
10754 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10755 | || (!matched_lo_p | |
10756 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10757 | lo_pos = pos; | |
10758 | ||
10759 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10760 | && fixup_has_matching_lo_p (*pos)); | |
10761 | } | |
10762 | ||
10763 | /* If we found a match, remove the high-part relocation from its | |
10764 | current position and insert it before the low-part relocation. | |
10765 | Make the offsets match so that fixup_has_matching_lo_p() | |
10766 | will return true. | |
10767 | ||
10768 | We don't warn about unmatched high-part relocations since some | |
10769 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10770 | instructions. */ | |
10771 | if (lo_pos != NULL) | |
10772 | { | |
10773 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10774 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10775 | { |
3b91255e RS |
10776 | *hi_pos = l->fixp->fx_next; |
10777 | l->fixp->fx_next = *lo_pos; | |
10778 | *lo_pos = l->fixp; | |
252b5132 | 10779 | } |
252b5132 RH |
10780 | } |
10781 | } | |
10782 | } | |
10783 | ||
3e722fb5 | 10784 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10785 | We have to prevent gas from dropping them. */ |
252b5132 | 10786 | |
252b5132 | 10787 | int |
17a2f251 | 10788 | mips_force_relocation (fixS *fixp) |
252b5132 | 10789 | { |
ae6063d4 | 10790 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10791 | return 1; |
10792 | ||
f6688943 TS |
10793 | if (HAVE_NEWABI |
10794 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10795 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10796 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10797 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10798 | return 1; | |
10799 | ||
3e722fb5 | 10800 | return 0; |
252b5132 RH |
10801 | } |
10802 | ||
45f8dfe8 AO |
10803 | /* This hook is called before a fix is simplified. We don't really |
10804 | decide whether to skip a fix here. Rather, we turn global symbols | |
10805 | used as branch targets into local symbols, such that they undergo | |
10806 | simplification. We can only do this if the symbol is defined and | |
10807 | it is in the same section as the branch. If this doesn't hold, we | |
10808 | emit a better error message than just saying the relocation is not | |
10809 | valid for the selected object format. | |
10810 | ||
10811 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10812 | segment in which the fix up occurs. The return value should be | |
10813 | non-zero to indicate the fix-up is valid for further | |
10814 | simplifications. */ | |
10815 | ||
10816 | int | |
17a2f251 | 10817 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10818 | { |
10819 | /* There's a lot of discussion on whether it should be possible to | |
10820 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10821 | seems to be that it can, but gas/bfd are very broken in creating | |
10822 | RELA relocations for this, so for now we only accept branches to | |
10823 | symbols in the same section. Anything else is of dubious value, | |
10824 | since there's no guarantee that at link time the symbol would be | |
10825 | in range. Even for branches to local symbols this is arguably | |
10826 | wrong, since it we assume the symbol is not going to be | |
10827 | overridden, which should be possible per ELF library semantics, | |
10828 | but then, there isn't a dynamic relocation that could be used to | |
10829 | this effect, and the target would likely be out of range as well. | |
10830 | ||
10831 | Unfortunately, it seems that there is too much code out there | |
10832 | that relies on branches to symbols that are global to be resolved | |
10833 | as if they were local, like the IRIX tools do, so we do it as | |
10834 | well, but with a warning so that people are reminded to fix their | |
10835 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10836 | targets, this entire block should go away (and probably the | |
10837 | whole function). */ | |
10838 | ||
10839 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10840 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10841 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10842 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10843 | && fixP->fx_addsy) | |
10844 | { | |
10845 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10846 | { | |
10847 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10848 | _("Cannot branch to undefined symbol.")); | |
10849 | /* Avoid any further errors about this fixup. */ | |
10850 | fixP->fx_done = 1; | |
10851 | } | |
10852 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10853 | { | |
10854 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10855 | _("Cannot branch to symbol in another section.")); | |
10856 | fixP->fx_done = 1; | |
10857 | } | |
10858 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10859 | { | |
10860 | symbolS *sym = fixP->fx_addsy; | |
10861 | ||
115695a8 CD |
10862 | if (mips_pic == SVR4_PIC) |
10863 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10864 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10865 | |
10866 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10867 | S_GET_SEGMENT (sym), | |
10868 | S_GET_VALUE (sym), | |
10869 | symbol_get_frag (sym)); | |
10870 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10871 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10872 | assert (symbol_resolved_p (sym)); | |
10873 | symbol_mark_resolved (fixP->fx_addsy); | |
10874 | } | |
10875 | } | |
10876 | ||
10877 | return 1; | |
10878 | } | |
10879 | ||
252b5132 RH |
10880 | /* Apply a fixup to the object file. */ |
10881 | ||
94f592af | 10882 | void |
17a2f251 | 10883 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10884 | { |
874e8986 | 10885 | bfd_byte *buf; |
98aa84af | 10886 | long insn; |
a7ebbfdf | 10887 | reloc_howto_type *howto; |
252b5132 | 10888 | |
a7ebbfdf TS |
10889 | /* We ignore generic BFD relocations we don't know about. */ |
10890 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10891 | if (! howto) | |
10892 | return; | |
65551fa4 | 10893 | |
252b5132 RH |
10894 | assert (fixP->fx_size == 4 |
10895 | || fixP->fx_r_type == BFD_RELOC_16 | |
10896 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10897 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10898 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10899 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10900 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10901 | |
a7ebbfdf | 10902 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10903 | |
3e722fb5 | 10904 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10905 | |
10906 | /* Don't treat parts of a composite relocation as done. There are two | |
10907 | reasons for this: | |
10908 | ||
10909 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
10910 | should nevertheless be emitted if the first part is. | |
10911 | ||
10912 | (2) In normal usage, composite relocations are never assembly-time | |
10913 | constants. The easiest way of dealing with the pathological | |
10914 | exceptions is to generate a relocation against STN_UNDEF and | |
10915 | leave everything up to the linker. */ | |
10916 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
10917 | fixP->fx_done = 1; |
10918 | ||
10919 | switch (fixP->fx_r_type) | |
10920 | { | |
3f98094e DJ |
10921 | case BFD_RELOC_MIPS_TLS_GD: |
10922 | case BFD_RELOC_MIPS_TLS_LDM: | |
10923 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
10924 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
10925 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
10926 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
10927 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
10928 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10929 | /* fall through */ | |
10930 | ||
252b5132 | 10931 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
10932 | case BFD_RELOC_MIPS_SHIFT5: |
10933 | case BFD_RELOC_MIPS_SHIFT6: | |
10934 | case BFD_RELOC_MIPS_GOT_DISP: | |
10935 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10936 | case BFD_RELOC_MIPS_GOT_OFST: | |
10937 | case BFD_RELOC_MIPS_SUB: | |
10938 | case BFD_RELOC_MIPS_INSERT_A: | |
10939 | case BFD_RELOC_MIPS_INSERT_B: | |
10940 | case BFD_RELOC_MIPS_DELETE: | |
10941 | case BFD_RELOC_MIPS_HIGHEST: | |
10942 | case BFD_RELOC_MIPS_HIGHER: | |
10943 | case BFD_RELOC_MIPS_SCN_DISP: | |
10944 | case BFD_RELOC_MIPS_REL16: | |
10945 | case BFD_RELOC_MIPS_RELGOT: | |
10946 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10947 | case BFD_RELOC_HI16: |
10948 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10949 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10950 | case BFD_RELOC_MIPS_LITERAL: |
10951 | case BFD_RELOC_MIPS_CALL16: | |
10952 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10953 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10954 | case BFD_RELOC_MIPS_GOT_HI16: |
10955 | case BFD_RELOC_MIPS_GOT_LO16: | |
10956 | case BFD_RELOC_MIPS_CALL_HI16: | |
10957 | case BFD_RELOC_MIPS_CALL_LO16: | |
10958 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
10959 | case BFD_RELOC_MIPS16_HI16: |
10960 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 10961 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10962 | /* Nothing needed to do. The value comes from the reloc entry */ |
10963 | break; | |
10964 | ||
10965 | case BFD_RELOC_MIPS16_JMP: | |
10966 | /* We currently always generate a reloc against a symbol, which | |
10967 | means that we don't want an addend even if the symbol is | |
10968 | defined. */ | |
a7ebbfdf | 10969 | *valP = 0; |
252b5132 RH |
10970 | break; |
10971 | ||
252b5132 RH |
10972 | case BFD_RELOC_64: |
10973 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10974 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10975 | if (fixP->fx_done) |
252b5132 RH |
10976 | { |
10977 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 10978 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
10979 | else |
10980 | { | |
a7ebbfdf | 10981 | valueT hiv; |
252b5132 | 10982 | |
a7ebbfdf | 10983 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
10984 | hiv = 0xffffffff; |
10985 | else | |
10986 | hiv = 0; | |
a7ebbfdf TS |
10987 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
10988 | *valP, 4); | |
10989 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
10990 | hiv, 4); | |
252b5132 RH |
10991 | } |
10992 | } | |
10993 | break; | |
10994 | ||
056350c6 | 10995 | case BFD_RELOC_RVA: |
252b5132 RH |
10996 | case BFD_RELOC_32: |
10997 | /* If we are deleting this reloc entry, we must fill in the | |
10998 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
10999 | resolved when it appears but is later defined. */ |
11000 | if (fixP->fx_done) | |
2132e3a3 | 11001 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11002 | break; |
11003 | ||
11004 | case BFD_RELOC_16: | |
11005 | /* If we are deleting this reloc entry, we must fill in the | |
11006 | value now. */ | |
252b5132 | 11007 | if (fixP->fx_done) |
2132e3a3 | 11008 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11009 | break; |
11010 | ||
11011 | case BFD_RELOC_LO16: | |
d6f16593 | 11012 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11013 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11014 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11015 | /* When handling an embedded PIC switch statement, we can wind |
11016 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11017 | if (fixP->fx_done) | |
11018 | { | |
a7ebbfdf | 11019 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11020 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11021 | _("relocation overflow")); | |
252b5132 RH |
11022 | if (target_big_endian) |
11023 | buf += 2; | |
2132e3a3 | 11024 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11025 | } |
11026 | break; | |
11027 | ||
11028 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11029 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11030 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11031 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11032 | |
252b5132 RH |
11033 | /* |
11034 | * We need to save the bits in the instruction since fixup_segment() | |
11035 | * might be deleting the relocation entry (i.e., a branch within | |
11036 | * the current segment). | |
11037 | */ | |
a7ebbfdf | 11038 | if (! fixP->fx_done) |
bb2d6cd7 | 11039 | break; |
252b5132 RH |
11040 | |
11041 | /* update old instruction data */ | |
252b5132 RH |
11042 | if (target_big_endian) |
11043 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11044 | else | |
11045 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11046 | ||
a7ebbfdf TS |
11047 | if (*valP + 0x20000 <= 0x3ffff) |
11048 | { | |
11049 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11050 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11051 | } |
11052 | else if (mips_pic == NO_PIC | |
11053 | && fixP->fx_done | |
11054 | && fixP->fx_frag->fr_address >= text_section->vma | |
11055 | && (fixP->fx_frag->fr_address | |
587aac4e | 11056 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11057 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11058 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11059 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11060 | { |
11061 | /* The branch offset is too large. If this is an | |
11062 | unconditional branch, and we are not generating PIC code, | |
11063 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11064 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11065 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11066 | else |
a7ebbfdf TS |
11067 | insn = 0x08000000; /* j */ |
11068 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11069 | fixP->fx_done = 0; | |
11070 | fixP->fx_addsy = section_symbol (text_section); | |
11071 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11072 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11073 | } |
11074 | else | |
11075 | { | |
11076 | /* If we got here, we have branch-relaxation disabled, | |
11077 | and there's nothing we can do to fix this instruction | |
11078 | without turning it into a longer sequence. */ | |
11079 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11080 | _("Branch out of range")); | |
252b5132 | 11081 | } |
252b5132 RH |
11082 | break; |
11083 | ||
11084 | case BFD_RELOC_VTABLE_INHERIT: | |
11085 | fixP->fx_done = 0; | |
11086 | if (fixP->fx_addsy | |
11087 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11088 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11089 | S_SET_WEAK (fixP->fx_addsy); | |
11090 | break; | |
11091 | ||
11092 | case BFD_RELOC_VTABLE_ENTRY: | |
11093 | fixP->fx_done = 0; | |
11094 | break; | |
11095 | ||
11096 | default: | |
11097 | internalError (); | |
11098 | } | |
a7ebbfdf TS |
11099 | |
11100 | /* Remember value for tc_gen_reloc. */ | |
11101 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11102 | } |
11103 | ||
252b5132 | 11104 | static symbolS * |
17a2f251 | 11105 | get_symbol (void) |
252b5132 RH |
11106 | { |
11107 | int c; | |
11108 | char *name; | |
11109 | symbolS *p; | |
11110 | ||
11111 | name = input_line_pointer; | |
11112 | c = get_symbol_end (); | |
11113 | p = (symbolS *) symbol_find_or_make (name); | |
11114 | *input_line_pointer = c; | |
11115 | return p; | |
11116 | } | |
11117 | ||
11118 | /* Align the current frag to a given power of two. The MIPS assembler | |
11119 | also automatically adjusts any preceding label. */ | |
11120 | ||
11121 | static void | |
17a2f251 | 11122 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11123 | { |
7d10b47d | 11124 | mips_emit_delays (); |
252b5132 RH |
11125 | frag_align (to, fill, 0); |
11126 | record_alignment (now_seg, to); | |
11127 | if (label != NULL) | |
11128 | { | |
11129 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11130 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11131 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11132 | } | |
11133 | } | |
11134 | ||
11135 | /* Align to a given power of two. .align 0 turns off the automatic | |
11136 | alignment used by the data creating pseudo-ops. */ | |
11137 | ||
11138 | static void | |
17a2f251 | 11139 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11140 | { |
11141 | register int temp; | |
11142 | register long temp_fill; | |
11143 | long max_alignment = 15; | |
11144 | ||
11145 | /* | |
11146 | ||
67c1ffbe | 11147 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11148 | to the aligned address. |
11149 | o It's not documented but auto alignment is reinstated by | |
11150 | a .align pseudo instruction. | |
11151 | o Note also that after auto alignment is turned off the mips assembler | |
11152 | issues an error on attempt to assemble an improperly aligned data item. | |
11153 | We don't. | |
11154 | ||
11155 | */ | |
11156 | ||
11157 | temp = get_absolute_expression (); | |
11158 | if (temp > max_alignment) | |
11159 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11160 | else if (temp < 0) | |
11161 | { | |
11162 | as_warn (_("Alignment negative: 0 assumed.")); | |
11163 | temp = 0; | |
11164 | } | |
11165 | if (*input_line_pointer == ',') | |
11166 | { | |
f9419b05 | 11167 | ++input_line_pointer; |
252b5132 RH |
11168 | temp_fill = get_absolute_expression (); |
11169 | } | |
11170 | else | |
11171 | temp_fill = 0; | |
11172 | if (temp) | |
11173 | { | |
11174 | auto_align = 1; | |
11175 | mips_align (temp, (int) temp_fill, | |
11176 | insn_labels != NULL ? insn_labels->label : NULL); | |
11177 | } | |
11178 | else | |
11179 | { | |
11180 | auto_align = 0; | |
11181 | } | |
11182 | ||
11183 | demand_empty_rest_of_line (); | |
11184 | } | |
11185 | ||
252b5132 | 11186 | static void |
17a2f251 | 11187 | s_change_sec (int sec) |
252b5132 RH |
11188 | { |
11189 | segT seg; | |
11190 | ||
252b5132 RH |
11191 | #ifdef OBJ_ELF |
11192 | /* The ELF backend needs to know that we are changing sections, so | |
11193 | that .previous works correctly. We could do something like check | |
b6ff326e | 11194 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11195 | as it would not be appropriate to use it in the section changing |
11196 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11197 | This should be cleaner, somehow. */ | |
11198 | obj_elf_section_change_hook (); | |
11199 | #endif | |
11200 | ||
7d10b47d | 11201 | mips_emit_delays (); |
252b5132 RH |
11202 | switch (sec) |
11203 | { | |
11204 | case 't': | |
11205 | s_text (0); | |
11206 | break; | |
11207 | case 'd': | |
11208 | s_data (0); | |
11209 | break; | |
11210 | case 'b': | |
11211 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11212 | demand_empty_rest_of_line (); | |
11213 | break; | |
11214 | ||
11215 | case 'r': | |
4d0d148d TS |
11216 | seg = subseg_new (RDATA_SECTION_NAME, |
11217 | (subsegT) get_absolute_expression ()); | |
11218 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11219 | { |
4d0d148d TS |
11220 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11221 | | SEC_READONLY | SEC_RELOC | |
11222 | | SEC_DATA)); | |
11223 | if (strcmp (TARGET_OS, "elf") != 0) | |
11224 | record_alignment (seg, 4); | |
252b5132 | 11225 | } |
4d0d148d | 11226 | demand_empty_rest_of_line (); |
252b5132 RH |
11227 | break; |
11228 | ||
11229 | case 's': | |
4d0d148d TS |
11230 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11231 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11232 | { |
4d0d148d TS |
11233 | bfd_set_section_flags (stdoutput, seg, |
11234 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11235 | if (strcmp (TARGET_OS, "elf") != 0) | |
11236 | record_alignment (seg, 4); | |
252b5132 | 11237 | } |
4d0d148d TS |
11238 | demand_empty_rest_of_line (); |
11239 | break; | |
252b5132 RH |
11240 | } |
11241 | ||
11242 | auto_align = 1; | |
11243 | } | |
b34976b6 | 11244 | |
cca86cc8 | 11245 | void |
17a2f251 | 11246 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11247 | { |
7ed4a06a | 11248 | #ifdef OBJ_ELF |
cca86cc8 SC |
11249 | char *section_name; |
11250 | char c; | |
684022ea | 11251 | char next_c = 0; |
cca86cc8 SC |
11252 | int section_type; |
11253 | int section_flag; | |
11254 | int section_entry_size; | |
11255 | int section_alignment; | |
b34976b6 | 11256 | |
7ed4a06a TS |
11257 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11258 | return; | |
11259 | ||
cca86cc8 SC |
11260 | section_name = input_line_pointer; |
11261 | c = get_symbol_end (); | |
a816d1ed AO |
11262 | if (c) |
11263 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11264 | |
4cf0dd0d TS |
11265 | /* Do we have .section Name<,"flags">? */ |
11266 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11267 | { |
4cf0dd0d TS |
11268 | /* just after name is now '\0'. */ |
11269 | *input_line_pointer = c; | |
cca86cc8 SC |
11270 | input_line_pointer = section_name; |
11271 | obj_elf_section (ignore); | |
11272 | return; | |
11273 | } | |
11274 | input_line_pointer++; | |
11275 | ||
11276 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11277 | if (c == ',') | |
11278 | section_type = get_absolute_expression (); | |
11279 | else | |
11280 | section_type = 0; | |
11281 | if (*input_line_pointer++ == ',') | |
11282 | section_flag = get_absolute_expression (); | |
11283 | else | |
11284 | section_flag = 0; | |
11285 | if (*input_line_pointer++ == ',') | |
11286 | section_entry_size = get_absolute_expression (); | |
11287 | else | |
11288 | section_entry_size = 0; | |
11289 | if (*input_line_pointer++ == ',') | |
11290 | section_alignment = get_absolute_expression (); | |
11291 | else | |
11292 | section_alignment = 0; | |
11293 | ||
a816d1ed AO |
11294 | section_name = xstrdup (section_name); |
11295 | ||
8ab8a5c8 RS |
11296 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11297 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11298 | traditionally had to fall back on the more common @progbits instead. | |
11299 | ||
11300 | There's nothing really harmful in this, since bfd will correct | |
11301 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11302 | means that, for backwards compatibiltiy, the special_section entries | |
11303 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11304 | ||
11305 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11306 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11307 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11308 | generic type-checking code. */ | |
11309 | if (section_type == SHT_MIPS_DWARF) | |
11310 | section_type = SHT_PROGBITS; | |
11311 | ||
cca86cc8 SC |
11312 | obj_elf_change_section (section_name, section_type, section_flag, |
11313 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11314 | |
11315 | if (now_seg->name != section_name) | |
11316 | free (section_name); | |
7ed4a06a | 11317 | #endif /* OBJ_ELF */ |
cca86cc8 | 11318 | } |
252b5132 RH |
11319 | |
11320 | void | |
17a2f251 | 11321 | mips_enable_auto_align (void) |
252b5132 RH |
11322 | { |
11323 | auto_align = 1; | |
11324 | } | |
11325 | ||
11326 | static void | |
17a2f251 | 11327 | s_cons (int log_size) |
252b5132 RH |
11328 | { |
11329 | symbolS *label; | |
11330 | ||
11331 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11332 | mips_emit_delays (); |
252b5132 RH |
11333 | if (log_size > 0 && auto_align) |
11334 | mips_align (log_size, 0, label); | |
11335 | mips_clear_insn_labels (); | |
11336 | cons (1 << log_size); | |
11337 | } | |
11338 | ||
11339 | static void | |
17a2f251 | 11340 | s_float_cons (int type) |
252b5132 RH |
11341 | { |
11342 | symbolS *label; | |
11343 | ||
11344 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11345 | ||
7d10b47d | 11346 | mips_emit_delays (); |
252b5132 RH |
11347 | |
11348 | if (auto_align) | |
49309057 ILT |
11349 | { |
11350 | if (type == 'd') | |
11351 | mips_align (3, 0, label); | |
11352 | else | |
11353 | mips_align (2, 0, label); | |
11354 | } | |
252b5132 RH |
11355 | |
11356 | mips_clear_insn_labels (); | |
11357 | ||
11358 | float_cons (type); | |
11359 | } | |
11360 | ||
11361 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11362 | permitted to say | |
11363 | .globl foo .text | |
11364 | where foo is an undefined symbol, to mean that foo should be | |
11365 | considered to be the address of a function. */ | |
11366 | ||
11367 | static void | |
17a2f251 | 11368 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11369 | { |
11370 | char *name; | |
11371 | int c; | |
11372 | symbolS *symbolP; | |
11373 | flagword flag; | |
11374 | ||
11375 | name = input_line_pointer; | |
11376 | c = get_symbol_end (); | |
11377 | symbolP = symbol_find_or_make (name); | |
11378 | *input_line_pointer = c; | |
11379 | SKIP_WHITESPACE (); | |
11380 | ||
11381 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11382 | being a function is apparently labelled as being an object. */ | |
11383 | flag = BSF_OBJECT; | |
11384 | ||
11385 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11386 | { | |
11387 | char *secname; | |
11388 | asection *sec; | |
11389 | ||
11390 | secname = input_line_pointer; | |
11391 | c = get_symbol_end (); | |
11392 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11393 | if (sec == NULL) | |
11394 | as_bad (_("%s: no such section"), secname); | |
11395 | *input_line_pointer = c; | |
11396 | ||
11397 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11398 | flag = BSF_FUNCTION; | |
11399 | } | |
11400 | ||
49309057 | 11401 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11402 | |
11403 | S_SET_EXTERNAL (symbolP); | |
11404 | demand_empty_rest_of_line (); | |
11405 | } | |
11406 | ||
11407 | static void | |
17a2f251 | 11408 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11409 | { |
11410 | char *opt; | |
11411 | char c; | |
11412 | ||
11413 | opt = input_line_pointer; | |
11414 | c = get_symbol_end (); | |
11415 | ||
11416 | if (*opt == 'O') | |
11417 | { | |
11418 | /* FIXME: What does this mean? */ | |
11419 | } | |
11420 | else if (strncmp (opt, "pic", 3) == 0) | |
11421 | { | |
11422 | int i; | |
11423 | ||
11424 | i = atoi (opt + 3); | |
11425 | if (i == 0) | |
11426 | mips_pic = NO_PIC; | |
11427 | else if (i == 2) | |
143d77c5 | 11428 | { |
252b5132 | 11429 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11430 | mips_abicalls = TRUE; |
11431 | } | |
252b5132 RH |
11432 | else |
11433 | as_bad (_(".option pic%d not supported"), i); | |
11434 | ||
4d0d148d | 11435 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11436 | { |
11437 | if (g_switch_seen && g_switch_value != 0) | |
11438 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11439 | g_switch_value = 0; | |
11440 | bfd_set_gp_size (stdoutput, 0); | |
11441 | } | |
11442 | } | |
11443 | else | |
11444 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11445 | ||
11446 | *input_line_pointer = c; | |
11447 | demand_empty_rest_of_line (); | |
11448 | } | |
11449 | ||
11450 | /* This structure is used to hold a stack of .set values. */ | |
11451 | ||
e972090a NC |
11452 | struct mips_option_stack |
11453 | { | |
252b5132 RH |
11454 | struct mips_option_stack *next; |
11455 | struct mips_set_options options; | |
11456 | }; | |
11457 | ||
11458 | static struct mips_option_stack *mips_opts_stack; | |
11459 | ||
11460 | /* Handle the .set pseudo-op. */ | |
11461 | ||
11462 | static void | |
17a2f251 | 11463 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11464 | { |
11465 | char *name = input_line_pointer, ch; | |
11466 | ||
11467 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11468 | ++input_line_pointer; |
252b5132 RH |
11469 | ch = *input_line_pointer; |
11470 | *input_line_pointer = '\0'; | |
11471 | ||
11472 | if (strcmp (name, "reorder") == 0) | |
11473 | { | |
7d10b47d RS |
11474 | if (mips_opts.noreorder) |
11475 | end_noreorder (); | |
252b5132 RH |
11476 | } |
11477 | else if (strcmp (name, "noreorder") == 0) | |
11478 | { | |
7d10b47d RS |
11479 | if (!mips_opts.noreorder) |
11480 | start_noreorder (); | |
252b5132 RH |
11481 | } |
11482 | else if (strcmp (name, "at") == 0) | |
11483 | { | |
11484 | mips_opts.noat = 0; | |
11485 | } | |
11486 | else if (strcmp (name, "noat") == 0) | |
11487 | { | |
11488 | mips_opts.noat = 1; | |
11489 | } | |
11490 | else if (strcmp (name, "macro") == 0) | |
11491 | { | |
11492 | mips_opts.warn_about_macros = 0; | |
11493 | } | |
11494 | else if (strcmp (name, "nomacro") == 0) | |
11495 | { | |
11496 | if (mips_opts.noreorder == 0) | |
11497 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11498 | mips_opts.warn_about_macros = 1; | |
11499 | } | |
11500 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11501 | { | |
11502 | mips_opts.nomove = 0; | |
11503 | } | |
11504 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11505 | { | |
11506 | mips_opts.nomove = 1; | |
11507 | } | |
11508 | else if (strcmp (name, "bopt") == 0) | |
11509 | { | |
11510 | mips_opts.nobopt = 0; | |
11511 | } | |
11512 | else if (strcmp (name, "nobopt") == 0) | |
11513 | { | |
11514 | mips_opts.nobopt = 1; | |
11515 | } | |
11516 | else if (strcmp (name, "mips16") == 0 | |
11517 | || strcmp (name, "MIPS-16") == 0) | |
11518 | mips_opts.mips16 = 1; | |
11519 | else if (strcmp (name, "nomips16") == 0 | |
11520 | || strcmp (name, "noMIPS-16") == 0) | |
11521 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11522 | else if (strcmp (name, "mips3d") == 0) |
11523 | mips_opts.ase_mips3d = 1; | |
11524 | else if (strcmp (name, "nomips3d") == 0) | |
11525 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11526 | else if (strcmp (name, "mdmx") == 0) |
11527 | mips_opts.ase_mdmx = 1; | |
11528 | else if (strcmp (name, "nomdmx") == 0) | |
11529 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11530 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11531 | { |
af7ee8bf | 11532 | int reset = 0; |
252b5132 | 11533 | |
1a2c1fad CD |
11534 | /* Permit the user to change the ISA and architecture on the fly. |
11535 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11536 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11537 | { |
11538 | reset = 1; | |
11539 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11540 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11541 | } |
11542 | else if (strncmp (name, "arch=", 5) == 0) | |
11543 | { | |
11544 | const struct mips_cpu_info *p; | |
11545 | ||
11546 | p = mips_parse_cpu("internal use", name + 5); | |
11547 | if (!p) | |
11548 | as_bad (_("unknown architecture %s"), name + 5); | |
11549 | else | |
11550 | { | |
11551 | mips_opts.arch = p->cpu; | |
11552 | mips_opts.isa = p->isa; | |
11553 | } | |
11554 | } | |
81a21e38 TS |
11555 | else if (strncmp (name, "mips", 4) == 0) |
11556 | { | |
11557 | const struct mips_cpu_info *p; | |
11558 | ||
11559 | p = mips_parse_cpu("internal use", name); | |
11560 | if (!p) | |
11561 | as_bad (_("unknown ISA level %s"), name + 4); | |
11562 | else | |
11563 | { | |
11564 | mips_opts.arch = p->cpu; | |
11565 | mips_opts.isa = p->isa; | |
11566 | } | |
11567 | } | |
af7ee8bf | 11568 | else |
81a21e38 | 11569 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11570 | |
11571 | switch (mips_opts.isa) | |
98d3f06f KH |
11572 | { |
11573 | case 0: | |
98d3f06f | 11574 | break; |
af7ee8bf CD |
11575 | case ISA_MIPS1: |
11576 | case ISA_MIPS2: | |
11577 | case ISA_MIPS32: | |
11578 | case ISA_MIPS32R2: | |
98d3f06f KH |
11579 | mips_opts.gp32 = 1; |
11580 | mips_opts.fp32 = 1; | |
11581 | break; | |
af7ee8bf CD |
11582 | case ISA_MIPS3: |
11583 | case ISA_MIPS4: | |
11584 | case ISA_MIPS5: | |
11585 | case ISA_MIPS64: | |
5f74bc13 | 11586 | case ISA_MIPS64R2: |
98d3f06f KH |
11587 | mips_opts.gp32 = 0; |
11588 | mips_opts.fp32 = 0; | |
11589 | break; | |
11590 | default: | |
11591 | as_bad (_("unknown ISA level %s"), name + 4); | |
11592 | break; | |
11593 | } | |
af7ee8bf | 11594 | if (reset) |
98d3f06f | 11595 | { |
af7ee8bf CD |
11596 | mips_opts.gp32 = file_mips_gp32; |
11597 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11598 | } |
252b5132 RH |
11599 | } |
11600 | else if (strcmp (name, "autoextend") == 0) | |
11601 | mips_opts.noautoextend = 0; | |
11602 | else if (strcmp (name, "noautoextend") == 0) | |
11603 | mips_opts.noautoextend = 1; | |
11604 | else if (strcmp (name, "push") == 0) | |
11605 | { | |
11606 | struct mips_option_stack *s; | |
11607 | ||
11608 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11609 | s->next = mips_opts_stack; | |
11610 | s->options = mips_opts; | |
11611 | mips_opts_stack = s; | |
11612 | } | |
11613 | else if (strcmp (name, "pop") == 0) | |
11614 | { | |
11615 | struct mips_option_stack *s; | |
11616 | ||
11617 | s = mips_opts_stack; | |
11618 | if (s == NULL) | |
11619 | as_bad (_(".set pop with no .set push")); | |
11620 | else | |
11621 | { | |
11622 | /* If we're changing the reorder mode we need to handle | |
11623 | delay slots correctly. */ | |
11624 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 11625 | start_noreorder (); |
252b5132 | 11626 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 11627 | end_noreorder (); |
252b5132 RH |
11628 | |
11629 | mips_opts = s->options; | |
11630 | mips_opts_stack = s->next; | |
11631 | free (s); | |
11632 | } | |
11633 | } | |
aed1a261 RS |
11634 | else if (strcmp (name, "sym32") == 0) |
11635 | mips_opts.sym32 = TRUE; | |
11636 | else if (strcmp (name, "nosym32") == 0) | |
11637 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11638 | else |
11639 | { | |
11640 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11641 | } | |
11642 | *input_line_pointer = ch; | |
11643 | demand_empty_rest_of_line (); | |
11644 | } | |
11645 | ||
11646 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11647 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11648 | ||
11649 | static void | |
17a2f251 | 11650 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11651 | { |
11652 | mips_pic = SVR4_PIC; | |
143d77c5 | 11653 | mips_abicalls = TRUE; |
4d0d148d TS |
11654 | |
11655 | if (g_switch_seen && g_switch_value != 0) | |
11656 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11657 | g_switch_value = 0; | |
11658 | ||
252b5132 RH |
11659 | bfd_set_gp_size (stdoutput, 0); |
11660 | demand_empty_rest_of_line (); | |
11661 | } | |
11662 | ||
11663 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11664 | PIC code. It sets the $gp register for the function based on the | |
11665 | function address, which is in the register named in the argument. | |
11666 | This uses a relocation against _gp_disp, which is handled specially | |
11667 | by the linker. The result is: | |
11668 | lui $gp,%hi(_gp_disp) | |
11669 | addiu $gp,$gp,%lo(_gp_disp) | |
11670 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11671 | The .cpload argument is normally $25 == $t9. |
11672 | ||
11673 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11674 | lui $gp,%hi(__gnu_local_gp) |
11675 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11676 | and the argument is ignored. This saves an instruction, but the |
11677 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11678 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11679 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11680 | |
11681 | static void | |
17a2f251 | 11682 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11683 | { |
11684 | expressionS ex; | |
aa6975fb ILT |
11685 | int reg; |
11686 | int in_shared; | |
252b5132 | 11687 | |
6478892d TS |
11688 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11689 | .cpload is ignored. */ | |
11690 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11691 | { |
11692 | s_ignore (0); | |
11693 | return; | |
11694 | } | |
11695 | ||
d3ecfc59 | 11696 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11697 | if (mips_opts.noreorder == 0) |
11698 | as_warn (_(".cpload not in noreorder section")); | |
11699 | ||
aa6975fb ILT |
11700 | reg = tc_get_register (0); |
11701 | ||
11702 | /* If we need to produce a 64-bit address, we are better off using | |
11703 | the default instruction sequence. */ | |
aed1a261 | 11704 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11705 | |
252b5132 | 11706 | ex.X_op = O_symbol; |
bbe506e8 TS |
11707 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11708 | "__gnu_local_gp"); | |
252b5132 RH |
11709 | ex.X_op_symbol = NULL; |
11710 | ex.X_add_number = 0; | |
11711 | ||
11712 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11713 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11714 | |
584892a6 | 11715 | macro_start (); |
67c0d1eb RS |
11716 | macro_build_lui (&ex, mips_gp_register); |
11717 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11718 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11719 | if (in_shared) |
11720 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11721 | mips_gp_register, reg); | |
584892a6 | 11722 | macro_end (); |
252b5132 RH |
11723 | |
11724 | demand_empty_rest_of_line (); | |
11725 | } | |
11726 | ||
6478892d TS |
11727 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11728 | .cpsetup $reg1, offset|$reg2, label | |
11729 | ||
11730 | If offset is given, this results in: | |
11731 | sd $gp, offset($sp) | |
956cd1d6 | 11732 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11733 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11734 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11735 | |
11736 | If $reg2 is given, this results in: | |
11737 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11738 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11739 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11740 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11741 | $reg1 is normally $25 == $t9. |
11742 | ||
11743 | The -mno-shared option replaces the last three instructions with | |
11744 | lui $gp,%hi(_gp) | |
11745 | addiu $gp,$gp,%lo(_gp) | |
11746 | */ | |
11747 | ||
6478892d | 11748 | static void |
17a2f251 | 11749 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11750 | { |
11751 | expressionS ex_off; | |
11752 | expressionS ex_sym; | |
11753 | int reg1; | |
6478892d | 11754 | |
8586fc66 | 11755 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11756 | We also need NewABI support. */ |
11757 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11758 | { | |
11759 | s_ignore (0); | |
11760 | return; | |
11761 | } | |
11762 | ||
11763 | reg1 = tc_get_register (0); | |
11764 | SKIP_WHITESPACE (); | |
11765 | if (*input_line_pointer != ',') | |
11766 | { | |
11767 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11768 | return; | |
11769 | } | |
11770 | else | |
80245285 | 11771 | ++input_line_pointer; |
6478892d TS |
11772 | SKIP_WHITESPACE (); |
11773 | if (*input_line_pointer == '$') | |
80245285 TS |
11774 | { |
11775 | mips_cpreturn_register = tc_get_register (0); | |
11776 | mips_cpreturn_offset = -1; | |
11777 | } | |
6478892d | 11778 | else |
80245285 TS |
11779 | { |
11780 | mips_cpreturn_offset = get_absolute_expression (); | |
11781 | mips_cpreturn_register = -1; | |
11782 | } | |
6478892d TS |
11783 | SKIP_WHITESPACE (); |
11784 | if (*input_line_pointer != ',') | |
11785 | { | |
11786 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11787 | return; | |
11788 | } | |
11789 | else | |
f9419b05 | 11790 | ++input_line_pointer; |
6478892d | 11791 | SKIP_WHITESPACE (); |
f21f8242 | 11792 | expression (&ex_sym); |
6478892d | 11793 | |
584892a6 | 11794 | macro_start (); |
6478892d TS |
11795 | if (mips_cpreturn_register == -1) |
11796 | { | |
11797 | ex_off.X_op = O_constant; | |
11798 | ex_off.X_add_symbol = NULL; | |
11799 | ex_off.X_op_symbol = NULL; | |
11800 | ex_off.X_add_number = mips_cpreturn_offset; | |
11801 | ||
67c0d1eb | 11802 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11803 | BFD_RELOC_LO16, SP); |
6478892d TS |
11804 | } |
11805 | else | |
67c0d1eb | 11806 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11807 | mips_gp_register, 0); |
6478892d | 11808 | |
aed1a261 | 11809 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
11810 | { |
11811 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11812 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11813 | BFD_RELOC_HI16_S); | |
11814 | ||
11815 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11816 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11817 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11818 | ||
11819 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11820 | mips_gp_register, reg1); | |
11821 | } | |
11822 | else | |
11823 | { | |
11824 | expressionS ex; | |
11825 | ||
11826 | ex.X_op = O_symbol; | |
4184909a | 11827 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
11828 | ex.X_op_symbol = NULL; |
11829 | ex.X_add_number = 0; | |
6e1304d8 | 11830 | |
aa6975fb ILT |
11831 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11832 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11833 | ||
11834 | macro_build_lui (&ex, mips_gp_register); | |
11835 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11836 | mips_gp_register, BFD_RELOC_LO16); | |
11837 | } | |
f21f8242 | 11838 | |
584892a6 | 11839 | macro_end (); |
6478892d TS |
11840 | |
11841 | demand_empty_rest_of_line (); | |
11842 | } | |
11843 | ||
11844 | static void | |
17a2f251 | 11845 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11846 | { |
11847 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11848 | .cplocal is ignored. */ | |
11849 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11850 | { | |
11851 | s_ignore (0); | |
11852 | return; | |
11853 | } | |
11854 | ||
11855 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11856 | demand_empty_rest_of_line (); |
6478892d TS |
11857 | } |
11858 | ||
252b5132 RH |
11859 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11860 | offset from $sp. The offset is remembered, and after making a PIC | |
11861 | call $gp is restored from that location. */ | |
11862 | ||
11863 | static void | |
17a2f251 | 11864 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11865 | { |
11866 | expressionS ex; | |
252b5132 | 11867 | |
6478892d | 11868 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11869 | .cprestore is ignored. */ |
6478892d | 11870 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11871 | { |
11872 | s_ignore (0); | |
11873 | return; | |
11874 | } | |
11875 | ||
11876 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11877 | mips_cprestore_valid = 1; |
252b5132 RH |
11878 | |
11879 | ex.X_op = O_constant; | |
11880 | ex.X_add_symbol = NULL; | |
11881 | ex.X_op_symbol = NULL; | |
11882 | ex.X_add_number = mips_cprestore_offset; | |
11883 | ||
584892a6 | 11884 | macro_start (); |
67c0d1eb RS |
11885 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11886 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11887 | macro_end (); |
252b5132 RH |
11888 | |
11889 | demand_empty_rest_of_line (); | |
11890 | } | |
11891 | ||
6478892d | 11892 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11893 | was given in the preceding .cpsetup, it results in: |
6478892d | 11894 | ld $gp, offset($sp) |
76b3015f | 11895 | |
6478892d | 11896 | If a register $reg2 was given there, it results in: |
609f23f4 | 11897 | daddu $gp, $reg2, $0 |
6478892d TS |
11898 | */ |
11899 | static void | |
17a2f251 | 11900 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11901 | { |
11902 | expressionS ex; | |
6478892d TS |
11903 | |
11904 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11905 | We also need NewABI support. */ | |
11906 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11907 | { | |
11908 | s_ignore (0); | |
11909 | return; | |
11910 | } | |
11911 | ||
584892a6 | 11912 | macro_start (); |
6478892d TS |
11913 | if (mips_cpreturn_register == -1) |
11914 | { | |
11915 | ex.X_op = O_constant; | |
11916 | ex.X_add_symbol = NULL; | |
11917 | ex.X_op_symbol = NULL; | |
11918 | ex.X_add_number = mips_cpreturn_offset; | |
11919 | ||
67c0d1eb | 11920 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11921 | } |
11922 | else | |
67c0d1eb | 11923 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11924 | mips_cpreturn_register, 0); |
584892a6 | 11925 | macro_end (); |
6478892d TS |
11926 | |
11927 | demand_empty_rest_of_line (); | |
11928 | } | |
11929 | ||
11930 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11931 | code. It sets the offset to use in gp_rel relocations. */ | |
11932 | ||
11933 | static void | |
17a2f251 | 11934 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11935 | { |
11936 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11937 | We also need NewABI support. */ | |
11938 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11939 | { | |
11940 | s_ignore (0); | |
11941 | return; | |
11942 | } | |
11943 | ||
def2e0dd | 11944 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11945 | |
11946 | demand_empty_rest_of_line (); | |
11947 | } | |
11948 | ||
252b5132 RH |
11949 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11950 | code. It generates a 32 bit GP relative reloc. */ | |
11951 | ||
11952 | static void | |
17a2f251 | 11953 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11954 | { |
11955 | symbolS *label; | |
11956 | expressionS ex; | |
11957 | char *p; | |
11958 | ||
11959 | /* When not generating PIC code, this is treated as .word. */ | |
11960 | if (mips_pic != SVR4_PIC) | |
11961 | { | |
11962 | s_cons (2); | |
11963 | return; | |
11964 | } | |
11965 | ||
11966 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11967 | mips_emit_delays (); |
252b5132 RH |
11968 | if (auto_align) |
11969 | mips_align (2, 0, label); | |
11970 | mips_clear_insn_labels (); | |
11971 | ||
11972 | expression (&ex); | |
11973 | ||
11974 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11975 | { | |
11976 | as_bad (_("Unsupported use of .gpword")); | |
11977 | ignore_rest_of_line (); | |
11978 | } | |
11979 | ||
11980 | p = frag_more (4); | |
17a2f251 | 11981 | md_number_to_chars (p, 0, 4); |
b34976b6 | 11982 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 11983 | BFD_RELOC_GPREL32); |
252b5132 RH |
11984 | |
11985 | demand_empty_rest_of_line (); | |
11986 | } | |
11987 | ||
10181a0d | 11988 | static void |
17a2f251 | 11989 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
11990 | { |
11991 | symbolS *label; | |
11992 | expressionS ex; | |
11993 | char *p; | |
11994 | ||
11995 | /* When not generating PIC code, this is treated as .dword. */ | |
11996 | if (mips_pic != SVR4_PIC) | |
11997 | { | |
11998 | s_cons (3); | |
11999 | return; | |
12000 | } | |
12001 | ||
12002 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12003 | mips_emit_delays (); |
10181a0d AO |
12004 | if (auto_align) |
12005 | mips_align (3, 0, label); | |
12006 | mips_clear_insn_labels (); | |
12007 | ||
12008 | expression (&ex); | |
12009 | ||
12010 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12011 | { | |
12012 | as_bad (_("Unsupported use of .gpdword")); | |
12013 | ignore_rest_of_line (); | |
12014 | } | |
12015 | ||
12016 | p = frag_more (8); | |
17a2f251 | 12017 | md_number_to_chars (p, 0, 8); |
a105a300 | 12018 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12019 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12020 | |
12021 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12022 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12023 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12024 | |
12025 | demand_empty_rest_of_line (); | |
12026 | } | |
12027 | ||
252b5132 RH |
12028 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12029 | tables in SVR4 PIC code. */ | |
12030 | ||
12031 | static void | |
17a2f251 | 12032 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12033 | { |
252b5132 RH |
12034 | int reg; |
12035 | ||
10181a0d AO |
12036 | /* This is ignored when not generating SVR4 PIC code. */ |
12037 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12038 | { |
12039 | s_ignore (0); | |
12040 | return; | |
12041 | } | |
12042 | ||
12043 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12044 | macro_start (); |
252b5132 | 12045 | reg = tc_get_register (0); |
67c0d1eb | 12046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12047 | macro_end (); |
252b5132 | 12048 | |
bdaaa2e1 | 12049 | demand_empty_rest_of_line (); |
252b5132 RH |
12050 | } |
12051 | ||
12052 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12053 | mips16 mode. This permits the linker to handle them specially, | |
12054 | such as generating jalx instructions when needed. We also make | |
12055 | them odd for the duration of the assembly, in order to generate the | |
12056 | right sort of code. We will make them even in the adjust_symtab | |
12057 | routine, while leaving them marked. This is convenient for the | |
12058 | debugger and the disassembler. The linker knows to make them odd | |
12059 | again. */ | |
12060 | ||
12061 | static void | |
17a2f251 | 12062 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12063 | { |
f9419b05 | 12064 | mips16_mark_labels (); |
252b5132 RH |
12065 | |
12066 | demand_empty_rest_of_line (); | |
12067 | } | |
12068 | ||
12069 | /* Handle a .stabn directive. We need these in order to mark a label | |
12070 | as being a mips16 text label correctly. Sometimes the compiler | |
12071 | will emit a label, followed by a .stabn, and then switch sections. | |
12072 | If the label and .stabn are in mips16 mode, then the label is | |
12073 | really a mips16 text label. */ | |
12074 | ||
12075 | static void | |
17a2f251 | 12076 | s_mips_stab (int type) |
252b5132 | 12077 | { |
f9419b05 | 12078 | if (type == 'n') |
252b5132 RH |
12079 | mips16_mark_labels (); |
12080 | ||
12081 | s_stab (type); | |
12082 | } | |
12083 | ||
12084 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12085 | */ | |
12086 | ||
12087 | static void | |
17a2f251 | 12088 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12089 | { |
12090 | char *name; | |
12091 | int c; | |
12092 | symbolS *symbolP; | |
12093 | expressionS exp; | |
12094 | ||
12095 | name = input_line_pointer; | |
12096 | c = get_symbol_end (); | |
12097 | symbolP = symbol_find_or_make (name); | |
12098 | S_SET_WEAK (symbolP); | |
12099 | *input_line_pointer = c; | |
12100 | ||
12101 | SKIP_WHITESPACE (); | |
12102 | ||
12103 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12104 | { | |
12105 | if (S_IS_DEFINED (symbolP)) | |
12106 | { | |
956cd1d6 | 12107 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12108 | S_GET_NAME (symbolP)); |
12109 | ignore_rest_of_line (); | |
12110 | return; | |
12111 | } | |
bdaaa2e1 | 12112 | |
252b5132 RH |
12113 | if (*input_line_pointer == ',') |
12114 | { | |
12115 | ++input_line_pointer; | |
12116 | SKIP_WHITESPACE (); | |
12117 | } | |
bdaaa2e1 | 12118 | |
252b5132 RH |
12119 | expression (&exp); |
12120 | if (exp.X_op != O_symbol) | |
12121 | { | |
12122 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12123 | ignore_rest_of_line (); |
252b5132 RH |
12124 | return; |
12125 | } | |
49309057 | 12126 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12127 | } |
12128 | ||
12129 | demand_empty_rest_of_line (); | |
12130 | } | |
12131 | ||
12132 | /* Parse a register string into a number. Called from the ECOFF code | |
12133 | to parse .frame. The argument is non-zero if this is the frame | |
12134 | register, so that we can record it in mips_frame_reg. */ | |
12135 | ||
12136 | int | |
17a2f251 | 12137 | tc_get_register (int frame) |
252b5132 RH |
12138 | { |
12139 | int reg; | |
12140 | ||
12141 | SKIP_WHITESPACE (); | |
12142 | if (*input_line_pointer++ != '$') | |
12143 | { | |
12144 | as_warn (_("expected `$'")); | |
85b51719 | 12145 | reg = ZERO; |
252b5132 | 12146 | } |
3882b010 | 12147 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12148 | { |
12149 | reg = get_absolute_expression (); | |
12150 | if (reg < 0 || reg >= 32) | |
12151 | { | |
12152 | as_warn (_("Bad register number")); | |
85b51719 | 12153 | reg = ZERO; |
252b5132 RH |
12154 | } |
12155 | } | |
12156 | else | |
12157 | { | |
76db943d | 12158 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12159 | { |
12160 | reg = RA; | |
12161 | input_line_pointer += 2; | |
12162 | } | |
76db943d | 12163 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12164 | { |
12165 | reg = FP; | |
12166 | input_line_pointer += 2; | |
12167 | } | |
252b5132 | 12168 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12169 | { |
12170 | reg = SP; | |
12171 | input_line_pointer += 2; | |
12172 | } | |
252b5132 | 12173 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12174 | { |
12175 | reg = GP; | |
12176 | input_line_pointer += 2; | |
12177 | } | |
252b5132 | 12178 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12179 | { |
12180 | reg = AT; | |
12181 | input_line_pointer += 2; | |
12182 | } | |
12183 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12184 | { | |
12185 | reg = KT0; | |
12186 | input_line_pointer += 3; | |
12187 | } | |
12188 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12189 | { | |
12190 | reg = KT1; | |
12191 | input_line_pointer += 3; | |
12192 | } | |
12193 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12194 | { | |
12195 | reg = ZERO; | |
12196 | input_line_pointer += 4; | |
12197 | } | |
252b5132 RH |
12198 | else |
12199 | { | |
12200 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12201 | reg = ZERO; |
12202 | while (ISALNUM(*input_line_pointer)) | |
12203 | input_line_pointer++; | |
252b5132 | 12204 | } |
252b5132 RH |
12205 | } |
12206 | if (frame) | |
7a621144 DJ |
12207 | { |
12208 | mips_frame_reg = reg != 0 ? reg : SP; | |
12209 | mips_frame_reg_valid = 1; | |
12210 | mips_cprestore_valid = 0; | |
12211 | } | |
252b5132 RH |
12212 | return reg; |
12213 | } | |
12214 | ||
12215 | valueT | |
17a2f251 | 12216 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12217 | { |
12218 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12219 | ||
12220 | #ifdef OBJ_ELF | |
12221 | /* We don't need to align ELF sections to the full alignment. | |
12222 | However, Irix 5 may prefer that we align them at least to a 16 | |
12223 | byte boundary. We don't bother to align the sections if we are | |
12224 | targeted for an embedded system. */ | |
12225 | if (strcmp (TARGET_OS, "elf") == 0) | |
12226 | return addr; | |
12227 | if (align > 4) | |
12228 | align = 4; | |
12229 | #endif | |
12230 | ||
12231 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12232 | } | |
12233 | ||
12234 | /* Utility routine, called from above as well. If called while the | |
12235 | input file is still being read, it's only an approximation. (For | |
12236 | example, a symbol may later become defined which appeared to be | |
12237 | undefined earlier.) */ | |
12238 | ||
12239 | static int | |
17a2f251 | 12240 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12241 | { |
12242 | if (sym == 0) | |
12243 | return 0; | |
12244 | ||
4d0d148d | 12245 | if (g_switch_value > 0) |
252b5132 RH |
12246 | { |
12247 | const char *symname; | |
12248 | int change; | |
12249 | ||
c9914766 | 12250 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12251 | register. It can be if it is smaller than the -G size or if |
12252 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12253 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12254 | they can. */ |
12255 | symname = S_GET_NAME (sym); | |
12256 | if (symname != (const char *) NULL | |
12257 | && (strcmp (symname, "eprol") == 0 | |
12258 | || strcmp (symname, "etext") == 0 | |
12259 | || strcmp (symname, "_gp") == 0 | |
12260 | || strcmp (symname, "edata") == 0 | |
12261 | || strcmp (symname, "_fbss") == 0 | |
12262 | || strcmp (symname, "_fdata") == 0 | |
12263 | || strcmp (symname, "_ftext") == 0 | |
12264 | || strcmp (symname, "end") == 0 | |
12265 | || strcmp (symname, "_gp_disp") == 0)) | |
12266 | change = 1; | |
12267 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12268 | && (0 | |
12269 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12270 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12271 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12272 | <= g_switch_value)) | |
252b5132 RH |
12273 | #endif |
12274 | /* We must defer this decision until after the whole | |
12275 | file has been read, since there might be a .extern | |
12276 | after the first use of this symbol. */ | |
12277 | || (before_relaxing | |
12278 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12279 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12280 | #endif |
12281 | && S_GET_VALUE (sym) == 0) | |
12282 | || (S_GET_VALUE (sym) != 0 | |
12283 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12284 | change = 0; | |
12285 | else | |
12286 | { | |
12287 | const char *segname; | |
12288 | ||
12289 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12290 | assert (strcmp (segname, ".lit8") != 0 | |
12291 | && strcmp (segname, ".lit4") != 0); | |
12292 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12293 | && strcmp (segname, ".sbss") != 0 |
12294 | && strncmp (segname, ".sdata.", 7) != 0 | |
12295 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12296 | } |
12297 | return change; | |
12298 | } | |
12299 | else | |
c9914766 | 12300 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12301 | return 1; |
12302 | } | |
12303 | ||
5919d012 RS |
12304 | |
12305 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12306 | ||
12307 | static bfd_boolean | |
17a2f251 | 12308 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12309 | { |
12310 | asection *symsec; | |
12311 | bfd_boolean linkonce; | |
12312 | ||
12313 | /* Handle the case of a symbol equated to another symbol. */ | |
12314 | while (symbol_equated_reloc_p (sym)) | |
12315 | { | |
12316 | symbolS *n; | |
12317 | ||
12318 | /* It's possible to get a loop here in a badly written | |
12319 | program. */ | |
12320 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12321 | if (n == sym) | |
12322 | break; | |
12323 | sym = n; | |
12324 | } | |
12325 | ||
12326 | symsec = S_GET_SEGMENT (sym); | |
12327 | ||
12328 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12329 | linkonce = FALSE; | |
12330 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12331 | { | |
12332 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12333 | != 0) | |
12334 | linkonce = TRUE; | |
12335 | ||
12336 | /* The GNU toolchain uses an extension for ELF: a section | |
12337 | beginning with the magic string .gnu.linkonce is a linkonce | |
12338 | section. */ | |
12339 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12340 | sizeof ".gnu.linkonce" - 1) == 0) | |
12341 | linkonce = TRUE; | |
12342 | } | |
12343 | ||
12344 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12345 | return (symsec != &bfd_und_section | |
12346 | && symsec != &bfd_abs_section | |
12347 | && ! bfd_is_com_section (symsec) | |
12348 | && !linkonce | |
12349 | #ifdef OBJ_ELF | |
12350 | /* A global or weak symbol is treated as external. */ | |
12351 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12352 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12353 | #endif |
12354 | ); | |
12355 | } | |
12356 | ||
12357 | ||
252b5132 RH |
12358 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12359 | extended opcode. SEC is the section the frag is in. */ | |
12360 | ||
12361 | static int | |
17a2f251 | 12362 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12363 | { |
12364 | int type; | |
12365 | register const struct mips16_immed_operand *op; | |
12366 | offsetT val; | |
12367 | int mintiny, maxtiny; | |
12368 | segT symsec; | |
98aa84af | 12369 | fragS *sym_frag; |
252b5132 RH |
12370 | |
12371 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12372 | return 0; | |
12373 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12374 | return 1; | |
12375 | ||
12376 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12377 | op = mips16_immed_operands; | |
12378 | while (op->type != type) | |
12379 | { | |
12380 | ++op; | |
12381 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12382 | } | |
12383 | ||
12384 | if (op->unsp) | |
12385 | { | |
12386 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12387 | { | |
12388 | mintiny = 1; | |
12389 | maxtiny = 1 << op->nbits; | |
12390 | } | |
12391 | else | |
12392 | { | |
12393 | mintiny = 0; | |
12394 | maxtiny = (1 << op->nbits) - 1; | |
12395 | } | |
12396 | } | |
12397 | else | |
12398 | { | |
12399 | mintiny = - (1 << (op->nbits - 1)); | |
12400 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12401 | } | |
12402 | ||
98aa84af | 12403 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12404 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12405 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12406 | |
12407 | if (op->pcrel) | |
12408 | { | |
12409 | addressT addr; | |
12410 | ||
12411 | /* We won't have the section when we are called from | |
12412 | mips_relax_frag. However, we will always have been called | |
12413 | from md_estimate_size_before_relax first. If this is a | |
12414 | branch to a different section, we mark it as such. If SEC is | |
12415 | NULL, and the frag is not marked, then it must be a branch to | |
12416 | the same section. */ | |
12417 | if (sec == NULL) | |
12418 | { | |
12419 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12420 | return 1; | |
12421 | } | |
12422 | else | |
12423 | { | |
98aa84af | 12424 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12425 | if (symsec != sec) |
12426 | { | |
12427 | fragp->fr_subtype = | |
12428 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12429 | ||
12430 | /* FIXME: We should support this, and let the linker | |
12431 | catch branches and loads that are out of range. */ | |
12432 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12433 | _("unsupported PC relative reference to different section")); | |
12434 | ||
12435 | return 1; | |
12436 | } | |
98aa84af AM |
12437 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12438 | /* Assume non-extended on the first relaxation pass. | |
12439 | The address we have calculated will be bogus if this is | |
12440 | a forward branch to another frag, as the forward frag | |
12441 | will have fr_address == 0. */ | |
12442 | return 0; | |
252b5132 RH |
12443 | } |
12444 | ||
12445 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12446 | the same section. If the relax_marker of the symbol fragment |
12447 | differs from the relax_marker of this fragment, we have not | |
12448 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12449 | in STRETCH in order to get a better estimate of the address. |
12450 | This particularly matters because of the shift bits. */ | |
12451 | if (stretch != 0 | |
98aa84af | 12452 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12453 | { |
12454 | fragS *f; | |
12455 | ||
12456 | /* Adjust stretch for any alignment frag. Note that if have | |
12457 | been expanding the earlier code, the symbol may be | |
12458 | defined in what appears to be an earlier frag. FIXME: | |
12459 | This doesn't handle the fr_subtype field, which specifies | |
12460 | a maximum number of bytes to skip when doing an | |
12461 | alignment. */ | |
98aa84af | 12462 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12463 | { |
12464 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12465 | { | |
12466 | if (stretch < 0) | |
12467 | stretch = - ((- stretch) | |
12468 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12469 | else | |
12470 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12471 | if (stretch == 0) | |
12472 | break; | |
12473 | } | |
12474 | } | |
12475 | if (f != NULL) | |
12476 | val += stretch; | |
12477 | } | |
12478 | ||
12479 | addr = fragp->fr_address + fragp->fr_fix; | |
12480 | ||
12481 | /* The base address rules are complicated. The base address of | |
12482 | a branch is the following instruction. The base address of a | |
12483 | PC relative load or add is the instruction itself, but if it | |
12484 | is in a delay slot (in which case it can not be extended) use | |
12485 | the address of the instruction whose delay slot it is in. */ | |
12486 | if (type == 'p' || type == 'q') | |
12487 | { | |
12488 | addr += 2; | |
12489 | ||
12490 | /* If we are currently assuming that this frag should be | |
12491 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12492 | higher. */ |
252b5132 RH |
12493 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12494 | addr += 2; | |
12495 | ||
12496 | /* Ignore the low bit in the target, since it will be set | |
12497 | for a text label. */ | |
12498 | if ((val & 1) != 0) | |
12499 | --val; | |
12500 | } | |
12501 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12502 | addr -= 4; | |
12503 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12504 | addr -= 2; | |
12505 | ||
12506 | val -= addr & ~ ((1 << op->shift) - 1); | |
12507 | ||
12508 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12509 | if (type == 'p' || type == 'q') | |
12510 | val /= 2; | |
12511 | ||
12512 | /* If any of the shifted bits are set, we must use an extended | |
12513 | opcode. If the address depends on the size of this | |
12514 | instruction, this can lead to a loop, so we arrange to always | |
12515 | use an extended opcode. We only check this when we are in | |
12516 | the main relaxation loop, when SEC is NULL. */ | |
12517 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12518 | { | |
12519 | fragp->fr_subtype = | |
12520 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12521 | return 1; | |
12522 | } | |
12523 | ||
12524 | /* If we are about to mark a frag as extended because the value | |
12525 | is precisely maxtiny + 1, then there is a chance of an | |
12526 | infinite loop as in the following code: | |
12527 | la $4,foo | |
12528 | .skip 1020 | |
12529 | .align 2 | |
12530 | foo: | |
12531 | In this case when the la is extended, foo is 0x3fc bytes | |
12532 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12533 | the la must be extended. To avoid this loop, we mark the | |
12534 | frag as extended if it was small, and is about to become | |
12535 | extended with a value of maxtiny + 1. */ | |
12536 | if (val == ((maxtiny + 1) << op->shift) | |
12537 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12538 | && sec == NULL) | |
12539 | { | |
12540 | fragp->fr_subtype = | |
12541 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12542 | return 1; | |
12543 | } | |
12544 | } | |
12545 | else if (symsec != absolute_section && sec != NULL) | |
12546 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12547 | ||
12548 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12549 | || val < (mintiny << op->shift) | |
12550 | || val > (maxtiny << op->shift)) | |
12551 | return 1; | |
12552 | else | |
12553 | return 0; | |
12554 | } | |
12555 | ||
4a6a3df4 AO |
12556 | /* Compute the length of a branch sequence, and adjust the |
12557 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12558 | worst-case length is computed, with UPDATE being used to indicate | |
12559 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12560 | branch is to be computed. */ | |
12561 | static int | |
17a2f251 | 12562 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12563 | { |
b34976b6 | 12564 | bfd_boolean toofar; |
4a6a3df4 AO |
12565 | int length; |
12566 | ||
12567 | if (fragp | |
12568 | && S_IS_DEFINED (fragp->fr_symbol) | |
12569 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12570 | { | |
12571 | addressT addr; | |
12572 | offsetT val; | |
12573 | ||
12574 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12575 | ||
12576 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12577 | ||
12578 | val -= addr; | |
12579 | ||
12580 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12581 | } | |
12582 | else if (fragp) | |
12583 | /* If the symbol is not defined or it's in a different segment, | |
12584 | assume the user knows what's going on and emit a short | |
12585 | branch. */ | |
b34976b6 | 12586 | toofar = FALSE; |
4a6a3df4 | 12587 | else |
b34976b6 | 12588 | toofar = TRUE; |
4a6a3df4 AO |
12589 | |
12590 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12591 | fragp->fr_subtype | |
af6ae2ad | 12592 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12593 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12594 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12595 | toofar); | |
12596 | ||
12597 | length = 4; | |
12598 | if (toofar) | |
12599 | { | |
12600 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12601 | length += 8; | |
12602 | ||
12603 | if (mips_pic != NO_PIC) | |
12604 | { | |
12605 | /* Additional space for PIC loading of target address. */ | |
12606 | length += 8; | |
12607 | if (mips_opts.isa == ISA_MIPS1) | |
12608 | /* Additional space for $at-stabilizing nop. */ | |
12609 | length += 4; | |
12610 | } | |
12611 | ||
12612 | /* If branch is conditional. */ | |
12613 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12614 | length += 8; | |
12615 | } | |
b34976b6 | 12616 | |
4a6a3df4 AO |
12617 | return length; |
12618 | } | |
12619 | ||
252b5132 RH |
12620 | /* Estimate the size of a frag before relaxing. Unless this is the |
12621 | mips16, we are not really relaxing here, and the final size is | |
12622 | encoded in the subtype information. For the mips16, we have to | |
12623 | decide whether we are using an extended opcode or not. */ | |
12624 | ||
252b5132 | 12625 | int |
17a2f251 | 12626 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12627 | { |
5919d012 | 12628 | int change; |
252b5132 | 12629 | |
4a6a3df4 AO |
12630 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12631 | { | |
12632 | ||
b34976b6 AM |
12633 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12634 | ||
4a6a3df4 AO |
12635 | return fragp->fr_var; |
12636 | } | |
12637 | ||
252b5132 | 12638 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12639 | /* We don't want to modify the EXTENDED bit here; it might get us |
12640 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12641 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12642 | |
12643 | if (mips_pic == NO_PIC) | |
5919d012 | 12644 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12645 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12646 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12647 | else |
12648 | abort (); | |
12649 | ||
12650 | if (change) | |
12651 | { | |
4d7206a2 | 12652 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12653 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12654 | } |
4d7206a2 RS |
12655 | else |
12656 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12657 | } |
12658 | ||
12659 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12660 | should be converted into a reloc against a section. */ |
252b5132 RH |
12661 | |
12662 | int | |
17a2f251 | 12663 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12664 | { |
de7e6852 RS |
12665 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12666 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12667 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12668 | return 0; | |
a161fe53 | 12669 | |
252b5132 RH |
12670 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12671 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12672 | return 0; | |
a161fe53 | 12673 | |
252b5132 RH |
12674 | if (fixp->fx_addsy == NULL) |
12675 | return 1; | |
a161fe53 | 12676 | |
de7e6852 RS |
12677 | /* If symbol SYM is in a mergeable section, relocations of the form |
12678 | SYM + 0 can usually be made section-relative. The mergeable data | |
12679 | is then identified by the section offset rather than by the symbol. | |
12680 | ||
12681 | However, if we're generating REL LO16 relocations, the offset is split | |
12682 | between the LO16 and parterning high part relocation. The linker will | |
12683 | need to recalculate the complete offset in order to correctly identify | |
12684 | the merge data. | |
12685 | ||
12686 | The linker has traditionally not looked for the parterning high part | |
12687 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12688 | placed anywhere. Rather than break backwards compatibility by changing | |
12689 | this, it seems better not to force the issue, and instead keep the | |
12690 | original symbol. This will work with either linker behavior. */ | |
12691 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12692 | && HAVE_IN_PLACE_ADDENDS | |
12693 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12694 | return 0; | |
12695 | ||
252b5132 | 12696 | #ifdef OBJ_ELF |
de7e6852 RS |
12697 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12698 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12699 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12700 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12701 | && fixp->fx_subsy == NULL) | |
12702 | return 0; | |
12703 | #endif | |
a161fe53 | 12704 | |
252b5132 RH |
12705 | return 1; |
12706 | } | |
12707 | ||
12708 | /* Translate internal representation of relocation info to BFD target | |
12709 | format. */ | |
12710 | ||
12711 | arelent ** | |
17a2f251 | 12712 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12713 | { |
12714 | static arelent *retval[4]; | |
12715 | arelent *reloc; | |
12716 | bfd_reloc_code_real_type code; | |
12717 | ||
4b0cff4e TS |
12718 | memset (retval, 0, sizeof(retval)); |
12719 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12720 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12721 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12722 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12723 | ||
3e722fb5 CD |
12724 | assert (! fixp->fx_pcrel); |
12725 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12726 | |
438c16b8 TS |
12727 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12728 | entry to be used in the relocation's section offset. */ | |
12729 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12730 | { |
12731 | reloc->address = reloc->addend; | |
12732 | reloc->addend = 0; | |
12733 | } | |
12734 | ||
252b5132 | 12735 | code = fixp->fx_r_type; |
252b5132 | 12736 | |
3e722fb5 CD |
12737 | /* To support a PC relative reloc, we used a Cygnus extension. |
12738 | We check for that here to make sure that we don't let such a | |
12739 | reloc escape normally. (FIXME: This was formerly used by | |
12740 | embedded-PIC support, but is now used by branch handling in | |
12741 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12742 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12743 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12744 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12745 | reloc->howto = NULL; |
12746 | else | |
12747 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12748 | ||
252b5132 RH |
12749 | if (reloc->howto == NULL) |
12750 | { | |
12751 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12752 | _("Can not represent %s relocation in this object file format"), | |
12753 | bfd_get_reloc_code_name (code)); | |
12754 | retval[0] = NULL; | |
12755 | } | |
12756 | ||
12757 | return retval; | |
12758 | } | |
12759 | ||
12760 | /* Relax a machine dependent frag. This returns the amount by which | |
12761 | the current size of the frag should change. */ | |
12762 | ||
12763 | int | |
17a2f251 | 12764 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12765 | { |
4a6a3df4 AO |
12766 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12767 | { | |
12768 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12769 | |
12770 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12771 | |
12772 | return fragp->fr_var - old_var; | |
12773 | } | |
12774 | ||
252b5132 RH |
12775 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12776 | return 0; | |
12777 | ||
c4e7957c | 12778 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12779 | { |
12780 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12781 | return 0; | |
12782 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12783 | return 2; | |
12784 | } | |
12785 | else | |
12786 | { | |
12787 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12788 | return 0; | |
12789 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12790 | return -2; | |
12791 | } | |
12792 | ||
12793 | return 0; | |
12794 | } | |
12795 | ||
12796 | /* Convert a machine dependent frag. */ | |
12797 | ||
12798 | void | |
17a2f251 | 12799 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12800 | { |
4a6a3df4 AO |
12801 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12802 | { | |
12803 | bfd_byte *buf; | |
12804 | unsigned long insn; | |
12805 | expressionS exp; | |
12806 | fixS *fixp; | |
b34976b6 | 12807 | |
4a6a3df4 AO |
12808 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12809 | ||
12810 | if (target_big_endian) | |
12811 | insn = bfd_getb32 (buf); | |
12812 | else | |
12813 | insn = bfd_getl32 (buf); | |
b34976b6 | 12814 | |
4a6a3df4 AO |
12815 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12816 | { | |
12817 | /* We generate a fixup instead of applying it right now | |
12818 | because, if there are linker relaxations, we're going to | |
12819 | need the relocations. */ | |
12820 | exp.X_op = O_symbol; | |
12821 | exp.X_add_symbol = fragp->fr_symbol; | |
12822 | exp.X_add_number = fragp->fr_offset; | |
12823 | ||
12824 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12825 | 4, &exp, 1, |
12826 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12827 | fixp->fx_file = fragp->fr_file; |
12828 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12829 | |
2132e3a3 | 12830 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12831 | buf += 4; |
12832 | } | |
12833 | else | |
12834 | { | |
12835 | int i; | |
12836 | ||
12837 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12838 | _("relaxed out-of-range branch into a jump")); | |
12839 | ||
12840 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12841 | goto uncond; | |
12842 | ||
12843 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12844 | { | |
12845 | /* Reverse the branch. */ | |
12846 | switch ((insn >> 28) & 0xf) | |
12847 | { | |
12848 | case 4: | |
12849 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12850 | have the condition reversed by tweaking a single | |
12851 | bit, and their opcodes all have 0x4???????. */ | |
12852 | assert ((insn & 0xf1000000) == 0x41000000); | |
12853 | insn ^= 0x00010000; | |
12854 | break; | |
12855 | ||
12856 | case 0: | |
12857 | /* bltz 0x04000000 bgez 0x04010000 | |
12858 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12859 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12860 | insn ^= 0x00010000; | |
12861 | break; | |
b34976b6 | 12862 | |
4a6a3df4 AO |
12863 | case 1: |
12864 | /* beq 0x10000000 bne 0x14000000 | |
12865 | blez 0x18000000 bgtz 0x1c000000 */ | |
12866 | insn ^= 0x04000000; | |
12867 | break; | |
12868 | ||
12869 | default: | |
12870 | abort (); | |
12871 | } | |
12872 | } | |
12873 | ||
12874 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12875 | { | |
12876 | /* Clear the and-link bit. */ | |
12877 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12878 | ||
12879 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12880 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12881 | insn &= ~0x00100000; | |
12882 | } | |
12883 | ||
12884 | /* Branch over the branch (if the branch was likely) or the | |
12885 | full jump (not likely case). Compute the offset from the | |
12886 | current instruction to branch to. */ | |
12887 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12888 | i = 16; | |
12889 | else | |
12890 | { | |
12891 | /* How many bytes in instructions we've already emitted? */ | |
12892 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12893 | /* How many bytes in instructions from here to the end? */ | |
12894 | i = fragp->fr_var - i; | |
12895 | } | |
12896 | /* Convert to instruction count. */ | |
12897 | i >>= 2; | |
12898 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12899 | i--; |
4a6a3df4 AO |
12900 | insn |= i; |
12901 | /* Branch over the jump. */ | |
2132e3a3 | 12902 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12903 | buf += 4; |
12904 | ||
12905 | /* Nop */ | |
2132e3a3 | 12906 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12907 | buf += 4; |
12908 | ||
12909 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12910 | { | |
12911 | /* beql $0, $0, 2f */ | |
12912 | insn = 0x50000000; | |
12913 | /* Compute the PC offset from the current instruction to | |
12914 | the end of the variable frag. */ | |
12915 | /* How many bytes in instructions we've already emitted? */ | |
12916 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12917 | /* How many bytes in instructions from here to the end? */ | |
12918 | i = fragp->fr_var - i; | |
12919 | /* Convert to instruction count. */ | |
12920 | i >>= 2; | |
12921 | /* Don't decrement i, because we want to branch over the | |
12922 | delay slot. */ | |
12923 | ||
12924 | insn |= i; | |
2132e3a3 | 12925 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12926 | buf += 4; |
12927 | ||
2132e3a3 | 12928 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12929 | buf += 4; |
12930 | } | |
12931 | ||
12932 | uncond: | |
12933 | if (mips_pic == NO_PIC) | |
12934 | { | |
12935 | /* j or jal. */ | |
12936 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12937 | ? 0x0c000000 : 0x08000000); | |
12938 | exp.X_op = O_symbol; | |
12939 | exp.X_add_symbol = fragp->fr_symbol; | |
12940 | exp.X_add_number = fragp->fr_offset; | |
12941 | ||
12942 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12943 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
12944 | fixp->fx_file = fragp->fr_file; | |
12945 | fixp->fx_line = fragp->fr_line; | |
12946 | ||
2132e3a3 | 12947 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12948 | buf += 4; |
12949 | } | |
12950 | else | |
12951 | { | |
12952 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
12953 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
12954 | exp.X_op = O_symbol; | |
12955 | exp.X_add_symbol = fragp->fr_symbol; | |
12956 | exp.X_add_number = fragp->fr_offset; | |
12957 | ||
12958 | if (fragp->fr_offset) | |
12959 | { | |
12960 | exp.X_add_symbol = make_expr_symbol (&exp); | |
12961 | exp.X_add_number = 0; | |
12962 | } | |
12963 | ||
12964 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12965 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
12966 | fixp->fx_file = fragp->fr_file; | |
12967 | fixp->fx_line = fragp->fr_line; | |
12968 | ||
2132e3a3 | 12969 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 12970 | buf += 4; |
b34976b6 | 12971 | |
4a6a3df4 AO |
12972 | if (mips_opts.isa == ISA_MIPS1) |
12973 | { | |
12974 | /* nop */ | |
2132e3a3 | 12975 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12976 | buf += 4; |
12977 | } | |
12978 | ||
12979 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
12980 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
12981 | ||
12982 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12983 | 4, &exp, 0, BFD_RELOC_LO16); | |
12984 | fixp->fx_file = fragp->fr_file; | |
12985 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12986 | |
2132e3a3 | 12987 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12988 | buf += 4; |
12989 | ||
12990 | /* j(al)r $at. */ | |
12991 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12992 | insn = 0x0020f809; | |
12993 | else | |
12994 | insn = 0x00200008; | |
12995 | ||
2132e3a3 | 12996 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12997 | buf += 4; |
12998 | } | |
12999 | } | |
13000 | ||
13001 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13002 | + fragp->fr_fix + fragp->fr_var); | |
13003 | ||
13004 | fragp->fr_fix += fragp->fr_var; | |
13005 | ||
13006 | return; | |
13007 | } | |
13008 | ||
252b5132 RH |
13009 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13010 | { | |
13011 | int type; | |
13012 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13013 | bfd_boolean small, ext; |
252b5132 RH |
13014 | offsetT val; |
13015 | bfd_byte *buf; | |
13016 | unsigned long insn; | |
b34976b6 | 13017 | bfd_boolean use_extend; |
252b5132 RH |
13018 | unsigned short extend; |
13019 | ||
13020 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13021 | op = mips16_immed_operands; | |
13022 | while (op->type != type) | |
13023 | ++op; | |
13024 | ||
13025 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13026 | { | |
b34976b6 AM |
13027 | small = FALSE; |
13028 | ext = TRUE; | |
252b5132 RH |
13029 | } |
13030 | else | |
13031 | { | |
b34976b6 AM |
13032 | small = TRUE; |
13033 | ext = FALSE; | |
252b5132 RH |
13034 | } |
13035 | ||
6386f3a7 | 13036 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13037 | val = S_GET_VALUE (fragp->fr_symbol); |
13038 | if (op->pcrel) | |
13039 | { | |
13040 | addressT addr; | |
13041 | ||
13042 | addr = fragp->fr_address + fragp->fr_fix; | |
13043 | ||
13044 | /* The rules for the base address of a PC relative reloc are | |
13045 | complicated; see mips16_extended_frag. */ | |
13046 | if (type == 'p' || type == 'q') | |
13047 | { | |
13048 | addr += 2; | |
13049 | if (ext) | |
13050 | addr += 2; | |
13051 | /* Ignore the low bit in the target, since it will be | |
13052 | set for a text label. */ | |
13053 | if ((val & 1) != 0) | |
13054 | --val; | |
13055 | } | |
13056 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13057 | addr -= 4; | |
13058 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13059 | addr -= 2; | |
13060 | ||
13061 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13062 | val -= addr; | |
13063 | ||
13064 | /* Make sure the section winds up with the alignment we have | |
13065 | assumed. */ | |
13066 | if (op->shift > 0) | |
13067 | record_alignment (asec, op->shift); | |
13068 | } | |
13069 | ||
13070 | if (ext | |
13071 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13072 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13073 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13074 | _("extended instruction in delay slot")); | |
13075 | ||
13076 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13077 | ||
13078 | if (target_big_endian) | |
13079 | insn = bfd_getb16 (buf); | |
13080 | else | |
13081 | insn = bfd_getl16 (buf); | |
13082 | ||
13083 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13084 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13085 | small, ext, &insn, &use_extend, &extend); | |
13086 | ||
13087 | if (use_extend) | |
13088 | { | |
2132e3a3 | 13089 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13090 | fragp->fr_fix += 2; |
13091 | buf += 2; | |
13092 | } | |
13093 | ||
2132e3a3 | 13094 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13095 | fragp->fr_fix += 2; |
13096 | buf += 2; | |
13097 | } | |
13098 | else | |
13099 | { | |
4d7206a2 RS |
13100 | int first, second; |
13101 | fixS *fixp; | |
252b5132 | 13102 | |
4d7206a2 RS |
13103 | first = RELAX_FIRST (fragp->fr_subtype); |
13104 | second = RELAX_SECOND (fragp->fr_subtype); | |
13105 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13106 | |
584892a6 RS |
13107 | /* Possibly emit a warning if we've chosen the longer option. */ |
13108 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13109 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13110 | { | |
13111 | const char *msg = macro_warning (fragp->fr_subtype); | |
13112 | if (msg != 0) | |
13113 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13114 | } | |
13115 | ||
4d7206a2 RS |
13116 | /* Go through all the fixups for the first sequence. Disable them |
13117 | (by marking them as done) if we're going to use the second | |
13118 | sequence instead. */ | |
13119 | while (fixp | |
13120 | && fixp->fx_frag == fragp | |
13121 | && fixp->fx_where < fragp->fr_fix - second) | |
13122 | { | |
13123 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13124 | fixp->fx_done = 1; | |
13125 | fixp = fixp->fx_next; | |
13126 | } | |
252b5132 | 13127 | |
4d7206a2 RS |
13128 | /* Go through the fixups for the second sequence. Disable them if |
13129 | we're going to use the first sequence, otherwise adjust their | |
13130 | addresses to account for the relaxation. */ | |
13131 | while (fixp && fixp->fx_frag == fragp) | |
13132 | { | |
13133 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13134 | fixp->fx_where -= first; | |
13135 | else | |
13136 | fixp->fx_done = 1; | |
13137 | fixp = fixp->fx_next; | |
13138 | } | |
13139 | ||
13140 | /* Now modify the frag contents. */ | |
13141 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13142 | { | |
13143 | char *start; | |
13144 | ||
13145 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13146 | memmove (start, start + first, second); | |
13147 | fragp->fr_fix -= first; | |
13148 | } | |
13149 | else | |
13150 | fragp->fr_fix -= second; | |
252b5132 RH |
13151 | } |
13152 | } | |
13153 | ||
13154 | #ifdef OBJ_ELF | |
13155 | ||
13156 | /* This function is called after the relocs have been generated. | |
13157 | We've been storing mips16 text labels as odd. Here we convert them | |
13158 | back to even for the convenience of the debugger. */ | |
13159 | ||
13160 | void | |
17a2f251 | 13161 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13162 | { |
13163 | asymbol **syms; | |
13164 | unsigned int count, i; | |
13165 | ||
13166 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13167 | return; | |
13168 | ||
13169 | syms = bfd_get_outsymbols (stdoutput); | |
13170 | count = bfd_get_symcount (stdoutput); | |
13171 | for (i = 0; i < count; i++, syms++) | |
13172 | { | |
13173 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13174 | && ((*syms)->value & 1) != 0) | |
13175 | { | |
13176 | (*syms)->value &= ~1; | |
13177 | /* If the symbol has an odd size, it was probably computed | |
13178 | incorrectly, so adjust that as well. */ | |
13179 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13180 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13181 | } | |
13182 | } | |
13183 | } | |
13184 | ||
13185 | #endif | |
13186 | ||
13187 | /* This function is called whenever a label is defined. It is used | |
13188 | when handling branch delays; if a branch has a label, we assume we | |
13189 | can not move it. */ | |
13190 | ||
13191 | void | |
17a2f251 | 13192 | mips_define_label (symbolS *sym) |
252b5132 RH |
13193 | { |
13194 | struct insn_label_list *l; | |
13195 | ||
13196 | if (free_insn_labels == NULL) | |
13197 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13198 | else | |
13199 | { | |
13200 | l = free_insn_labels; | |
13201 | free_insn_labels = l->next; | |
13202 | } | |
13203 | ||
13204 | l->label = sym; | |
13205 | l->next = insn_labels; | |
13206 | insn_labels = l; | |
13207 | } | |
13208 | \f | |
13209 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13210 | ||
13211 | /* Some special processing for a MIPS ELF file. */ | |
13212 | ||
13213 | void | |
17a2f251 | 13214 | mips_elf_final_processing (void) |
252b5132 RH |
13215 | { |
13216 | /* Write out the register information. */ | |
316f5878 | 13217 | if (mips_abi != N64_ABI) |
252b5132 RH |
13218 | { |
13219 | Elf32_RegInfo s; | |
13220 | ||
13221 | s.ri_gprmask = mips_gprmask; | |
13222 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13223 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13224 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13225 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13226 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13227 | ||
13228 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13229 | ((Elf32_External_RegInfo *) | |
13230 | mips_regmask_frag)); | |
13231 | } | |
13232 | else | |
13233 | { | |
13234 | Elf64_Internal_RegInfo s; | |
13235 | ||
13236 | s.ri_gprmask = mips_gprmask; | |
13237 | s.ri_pad = 0; | |
13238 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13239 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13240 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13241 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13242 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13243 | ||
13244 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13245 | ((Elf64_External_RegInfo *) | |
13246 | mips_regmask_frag)); | |
13247 | } | |
13248 | ||
13249 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13250 | sort of BFD interface for this. */ | |
13251 | if (mips_any_noreorder) | |
13252 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13253 | if (mips_pic != NO_PIC) | |
143d77c5 | 13254 | { |
252b5132 | 13255 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13256 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13257 | } | |
13258 | if (mips_abicalls) | |
13259 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13260 | |
98d3f06f | 13261 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13262 | if (file_ase_mips16) |
13263 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13264 | #if 0 /* XXX FIXME */ |
13265 | if (file_ase_mips3d) | |
13266 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13267 | #endif | |
deec1734 CD |
13268 | if (file_ase_mdmx) |
13269 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13270 | |
bdaaa2e1 | 13271 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13272 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13273 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13274 | else if (mips_abi == O64_ABI) |
252b5132 | 13275 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13276 | else if (mips_abi == EABI_ABI) |
252b5132 | 13277 | { |
316f5878 | 13278 | if (!file_mips_gp32) |
252b5132 RH |
13279 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13280 | else | |
13281 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13282 | } | |
316f5878 | 13283 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13284 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13285 | ||
c9914766 | 13286 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13287 | |
13288 | if (mips_32bitmode) | |
13289 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13290 | } | |
13291 | ||
13292 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13293 | \f | |
beae10d5 | 13294 | typedef struct proc { |
9b2f1d35 EC |
13295 | symbolS *func_sym; |
13296 | symbolS *func_end_sym; | |
beae10d5 KH |
13297 | unsigned long reg_mask; |
13298 | unsigned long reg_offset; | |
13299 | unsigned long fpreg_mask; | |
13300 | unsigned long fpreg_offset; | |
13301 | unsigned long frame_offset; | |
13302 | unsigned long frame_reg; | |
13303 | unsigned long pc_reg; | |
13304 | } procS; | |
252b5132 RH |
13305 | |
13306 | static procS cur_proc; | |
13307 | static procS *cur_proc_ptr; | |
13308 | static int numprocs; | |
13309 | ||
0a9ef439 | 13310 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13311 | |
0a9ef439 | 13312 | void |
17a2f251 | 13313 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13314 | { |
0a9ef439 RH |
13315 | if (fragp->fr_type != rs_align_code) |
13316 | return; | |
13317 | ||
13318 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13319 | { |
13320 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13321 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13322 | ||
0a9ef439 RH |
13323 | int bytes; |
13324 | char *p; | |
a19d8eb0 | 13325 | |
0a9ef439 RH |
13326 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13327 | p = fragp->fr_literal + fragp->fr_fix; | |
13328 | ||
13329 | if (bytes & 1) | |
13330 | { | |
13331 | *p++ = 0; | |
f9419b05 | 13332 | fragp->fr_fix++; |
0a9ef439 RH |
13333 | } |
13334 | ||
13335 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13336 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13337 | } |
13338 | ||
0a9ef439 | 13339 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13340 | } |
13341 | ||
252b5132 | 13342 | static void |
17a2f251 | 13343 | md_obj_begin (void) |
252b5132 RH |
13344 | { |
13345 | } | |
13346 | ||
13347 | static void | |
17a2f251 | 13348 | md_obj_end (void) |
252b5132 RH |
13349 | { |
13350 | /* check for premature end, nesting errors, etc */ | |
13351 | if (cur_proc_ptr) | |
9a41af64 | 13352 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13353 | } |
13354 | ||
13355 | static long | |
17a2f251 | 13356 | get_number (void) |
252b5132 RH |
13357 | { |
13358 | int negative = 0; | |
13359 | long val = 0; | |
13360 | ||
13361 | if (*input_line_pointer == '-') | |
13362 | { | |
13363 | ++input_line_pointer; | |
13364 | negative = 1; | |
13365 | } | |
3882b010 | 13366 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13367 | as_bad (_("expected simple number")); |
252b5132 RH |
13368 | if (input_line_pointer[0] == '0') |
13369 | { | |
13370 | if (input_line_pointer[1] == 'x') | |
13371 | { | |
13372 | input_line_pointer += 2; | |
3882b010 | 13373 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13374 | { |
13375 | val <<= 4; | |
13376 | val |= hex_value (*input_line_pointer++); | |
13377 | } | |
13378 | return negative ? -val : val; | |
13379 | } | |
13380 | else | |
13381 | { | |
13382 | ++input_line_pointer; | |
3882b010 | 13383 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13384 | { |
13385 | val <<= 3; | |
13386 | val |= *input_line_pointer++ - '0'; | |
13387 | } | |
13388 | return negative ? -val : val; | |
13389 | } | |
13390 | } | |
3882b010 | 13391 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13392 | { |
13393 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13394 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13395 | as_warn (_("invalid number")); |
252b5132 RH |
13396 | return -1; |
13397 | } | |
3882b010 | 13398 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13399 | { |
13400 | val *= 10; | |
13401 | val += *input_line_pointer++ - '0'; | |
13402 | } | |
13403 | return negative ? -val : val; | |
13404 | } | |
13405 | ||
13406 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13407 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13408 | case .file implies DWARF-2. */ | |
13409 | ||
13410 | static void | |
17a2f251 | 13411 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13412 | { |
ecb4347a DJ |
13413 | static int first_file_directive = 0; |
13414 | ||
c5dd6aab DJ |
13415 | if (ECOFF_DEBUGGING) |
13416 | { | |
13417 | get_number (); | |
13418 | s_app_file (0); | |
13419 | } | |
13420 | else | |
ecb4347a DJ |
13421 | { |
13422 | char *filename; | |
13423 | ||
13424 | filename = dwarf2_directive_file (0); | |
13425 | ||
13426 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13427 | directive even for stabs output. Make sure that this | |
13428 | ".file" is handled. Note that you need a version of GCC | |
13429 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13430 | if (filename != NULL && ! first_file_directive) | |
13431 | { | |
13432 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13433 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13434 | } |
13435 | first_file_directive = 1; | |
13436 | } | |
c5dd6aab DJ |
13437 | } |
13438 | ||
13439 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13440 | |
13441 | static void | |
17a2f251 | 13442 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13443 | { |
c5dd6aab DJ |
13444 | if (!ECOFF_DEBUGGING) |
13445 | dwarf2_directive_loc (0); | |
252b5132 RH |
13446 | } |
13447 | ||
252b5132 RH |
13448 | /* The .end directive. */ |
13449 | ||
13450 | static void | |
17a2f251 | 13451 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13452 | { |
13453 | symbolS *p; | |
252b5132 | 13454 | |
7a621144 DJ |
13455 | /* Following functions need their own .frame and .cprestore directives. */ |
13456 | mips_frame_reg_valid = 0; | |
13457 | mips_cprestore_valid = 0; | |
13458 | ||
252b5132 RH |
13459 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13460 | { | |
13461 | p = get_symbol (); | |
13462 | demand_empty_rest_of_line (); | |
13463 | } | |
13464 | else | |
13465 | p = NULL; | |
13466 | ||
14949570 | 13467 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13468 | as_warn (_(".end not in text section")); |
13469 | ||
13470 | if (!cur_proc_ptr) | |
13471 | { | |
13472 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13473 | demand_empty_rest_of_line (); | |
13474 | return; | |
13475 | } | |
13476 | ||
13477 | if (p != NULL) | |
13478 | { | |
13479 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13480 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13481 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13482 | |
13483 | if (debug_type == DEBUG_STABS) | |
13484 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13485 | S_GET_NAME (p)); | |
252b5132 RH |
13486 | } |
13487 | else | |
13488 | as_warn (_(".end directive missing or unknown symbol")); | |
13489 | ||
2132e3a3 | 13490 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13491 | /* Create an expression to calculate the size of the function. */ |
13492 | if (p && cur_proc_ptr) | |
13493 | { | |
13494 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13495 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13496 | ||
13497 | obj->size = exp; | |
13498 | exp->X_op = O_subtract; | |
13499 | exp->X_add_symbol = symbol_temp_new_now (); | |
13500 | exp->X_op_symbol = p; | |
13501 | exp->X_add_number = 0; | |
13502 | ||
13503 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13504 | } | |
13505 | ||
ecb4347a | 13506 | /* Generate a .pdr section. */ |
dcd410fe RO |
13507 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13508 | && mips_flag_pdr) | |
ecb4347a DJ |
13509 | { |
13510 | segT saved_seg = now_seg; | |
13511 | subsegT saved_subseg = now_subseg; | |
13512 | valueT dot; | |
13513 | expressionS exp; | |
13514 | char *fragp; | |
252b5132 | 13515 | |
ecb4347a | 13516 | dot = frag_now_fix (); |
252b5132 RH |
13517 | |
13518 | #ifdef md_flush_pending_output | |
ecb4347a | 13519 | md_flush_pending_output (); |
252b5132 RH |
13520 | #endif |
13521 | ||
ecb4347a DJ |
13522 | assert (pdr_seg); |
13523 | subseg_set (pdr_seg, 0); | |
252b5132 | 13524 | |
ecb4347a DJ |
13525 | /* Write the symbol. */ |
13526 | exp.X_op = O_symbol; | |
13527 | exp.X_add_symbol = p; | |
13528 | exp.X_add_number = 0; | |
13529 | emit_expr (&exp, 4); | |
252b5132 | 13530 | |
ecb4347a | 13531 | fragp = frag_more (7 * 4); |
252b5132 | 13532 | |
17a2f251 TS |
13533 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13534 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13535 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13536 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13537 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13538 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13539 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13540 | |
ecb4347a DJ |
13541 | subseg_set (saved_seg, saved_subseg); |
13542 | } | |
13543 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13544 | |
13545 | cur_proc_ptr = NULL; | |
13546 | } | |
13547 | ||
13548 | /* The .aent and .ent directives. */ | |
13549 | ||
13550 | static void | |
17a2f251 | 13551 | s_mips_ent (int aent) |
252b5132 | 13552 | { |
252b5132 | 13553 | symbolS *symbolP; |
252b5132 RH |
13554 | |
13555 | symbolP = get_symbol (); | |
13556 | if (*input_line_pointer == ',') | |
f9419b05 | 13557 | ++input_line_pointer; |
252b5132 | 13558 | SKIP_WHITESPACE (); |
3882b010 | 13559 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13560 | || *input_line_pointer == '-') |
874e8986 | 13561 | get_number (); |
252b5132 | 13562 | |
14949570 | 13563 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13564 | as_warn (_(".ent or .aent not in text section.")); |
13565 | ||
13566 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13567 | as_warn (_("missing .end")); |
252b5132 RH |
13568 | |
13569 | if (!aent) | |
13570 | { | |
7a621144 DJ |
13571 | /* This function needs its own .frame and .cprestore directives. */ |
13572 | mips_frame_reg_valid = 0; | |
13573 | mips_cprestore_valid = 0; | |
13574 | ||
252b5132 RH |
13575 | cur_proc_ptr = &cur_proc; |
13576 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13577 | ||
9b2f1d35 | 13578 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13579 | |
49309057 | 13580 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13581 | |
f9419b05 | 13582 | ++numprocs; |
ecb4347a DJ |
13583 | |
13584 | if (debug_type == DEBUG_STABS) | |
13585 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13586 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13587 | } |
13588 | ||
13589 | demand_empty_rest_of_line (); | |
13590 | } | |
13591 | ||
13592 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13593 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13594 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13595 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13596 | symbol table (in the mdebug section). */ |
13597 | ||
13598 | static void | |
17a2f251 | 13599 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13600 | { |
ecb4347a DJ |
13601 | #ifdef OBJ_ELF |
13602 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13603 | { | |
13604 | long val; | |
252b5132 | 13605 | |
ecb4347a DJ |
13606 | if (cur_proc_ptr == (procS *) NULL) |
13607 | { | |
13608 | as_warn (_(".frame outside of .ent")); | |
13609 | demand_empty_rest_of_line (); | |
13610 | return; | |
13611 | } | |
252b5132 | 13612 | |
ecb4347a DJ |
13613 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13614 | ||
13615 | SKIP_WHITESPACE (); | |
13616 | if (*input_line_pointer++ != ',' | |
13617 | || get_absolute_expression_and_terminator (&val) != ',') | |
13618 | { | |
13619 | as_warn (_("Bad .frame directive")); | |
13620 | --input_line_pointer; | |
13621 | demand_empty_rest_of_line (); | |
13622 | return; | |
13623 | } | |
252b5132 | 13624 | |
ecb4347a DJ |
13625 | cur_proc_ptr->frame_offset = val; |
13626 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13627 | |
252b5132 | 13628 | demand_empty_rest_of_line (); |
252b5132 | 13629 | } |
ecb4347a DJ |
13630 | else |
13631 | #endif /* OBJ_ELF */ | |
13632 | s_ignore (ignore); | |
252b5132 RH |
13633 | } |
13634 | ||
bdaaa2e1 KH |
13635 | /* The .fmask and .mask directives. If the mdebug section is present |
13636 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13637 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13638 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13639 | make reference to the ecoff symbol table (in the mdebug section). */ |
13640 | ||
13641 | static void | |
17a2f251 | 13642 | s_mips_mask (int reg_type) |
252b5132 | 13643 | { |
ecb4347a DJ |
13644 | #ifdef OBJ_ELF |
13645 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13646 | { |
ecb4347a | 13647 | long mask, off; |
252b5132 | 13648 | |
ecb4347a DJ |
13649 | if (cur_proc_ptr == (procS *) NULL) |
13650 | { | |
13651 | as_warn (_(".mask/.fmask outside of .ent")); | |
13652 | demand_empty_rest_of_line (); | |
13653 | return; | |
13654 | } | |
252b5132 | 13655 | |
ecb4347a DJ |
13656 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13657 | { | |
13658 | as_warn (_("Bad .mask/.fmask directive")); | |
13659 | --input_line_pointer; | |
13660 | demand_empty_rest_of_line (); | |
13661 | return; | |
13662 | } | |
252b5132 | 13663 | |
ecb4347a DJ |
13664 | off = get_absolute_expression (); |
13665 | ||
13666 | if (reg_type == 'F') | |
13667 | { | |
13668 | cur_proc_ptr->fpreg_mask = mask; | |
13669 | cur_proc_ptr->fpreg_offset = off; | |
13670 | } | |
13671 | else | |
13672 | { | |
13673 | cur_proc_ptr->reg_mask = mask; | |
13674 | cur_proc_ptr->reg_offset = off; | |
13675 | } | |
13676 | ||
13677 | demand_empty_rest_of_line (); | |
252b5132 RH |
13678 | } |
13679 | else | |
ecb4347a DJ |
13680 | #endif /* OBJ_ELF */ |
13681 | s_ignore (reg_type); | |
252b5132 RH |
13682 | } |
13683 | ||
316f5878 RS |
13684 | /* A table describing all the processors gas knows about. Names are |
13685 | matched in the order listed. | |
e7af610e | 13686 | |
316f5878 RS |
13687 | To ease comparison, please keep this table in the same order as |
13688 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13689 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13690 | { | |
316f5878 RS |
13691 | /* Entries for generic ISAs */ |
13692 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13693 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13694 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13695 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13696 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13697 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13698 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13699 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13700 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13701 | |
13702 | /* MIPS I */ | |
13703 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13704 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13705 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13706 | ||
13707 | /* MIPS II */ | |
13708 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13709 | ||
13710 | /* MIPS III */ | |
13711 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13712 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13713 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13714 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13715 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13716 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13717 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13718 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13719 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13720 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13721 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13722 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13723 | ||
13724 | /* MIPS IV */ | |
13725 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13726 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13727 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13728 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13729 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13730 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13731 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13732 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13733 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13734 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13735 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13736 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13737 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13738 | |
13739 | /* MIPS 32 */ | |
fef14a42 | 13740 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13741 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13742 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13743 | |
316f5878 RS |
13744 | /* MIPS 64 */ |
13745 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13746 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13747 | |
c7a23324 | 13748 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13749 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13750 | |
316f5878 RS |
13751 | /* End marker */ |
13752 | { NULL, 0, 0, 0 } | |
13753 | }; | |
e7af610e | 13754 | |
84ea6cf2 | 13755 | |
316f5878 RS |
13756 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13757 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13758 | |
316f5878 | 13759 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13760 | |
b34976b6 | 13761 | static bfd_boolean |
17a2f251 | 13762 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13763 | { |
13764 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13765 | given++, canonical++; | |
13766 | ||
13767 | return ((*given == 0 && *canonical == 0) | |
13768 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13769 | } | |
13770 | ||
13771 | ||
13772 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13773 | CPU name. We've traditionally allowed a lot of variation here. | |
13774 | ||
13775 | Note: this function is shared between GCC and GAS. */ | |
13776 | ||
b34976b6 | 13777 | static bfd_boolean |
17a2f251 | 13778 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13779 | { |
13780 | /* First see if the name matches exactly, or with a final "000" | |
13781 | turned into "k". */ | |
13782 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13783 | return TRUE; |
316f5878 RS |
13784 | |
13785 | /* If not, try comparing based on numerical designation alone. | |
13786 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13787 | if (TOLOWER (*given) == 'r') | |
13788 | given++; | |
13789 | if (!ISDIGIT (*given)) | |
b34976b6 | 13790 | return FALSE; |
316f5878 RS |
13791 | |
13792 | /* Skip over some well-known prefixes in the canonical name, | |
13793 | hoping to find a number there too. */ | |
13794 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13795 | canonical += 2; | |
13796 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13797 | canonical += 2; | |
13798 | else if (TOLOWER (canonical[0]) == 'r') | |
13799 | canonical += 1; | |
13800 | ||
13801 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13802 | } | |
13803 | ||
13804 | ||
13805 | /* Parse an option that takes the name of a processor as its argument. | |
13806 | OPTION is the name of the option and CPU_STRING is the argument. | |
13807 | Return the corresponding processor enumeration if the CPU_STRING is | |
13808 | recognized, otherwise report an error and return null. | |
13809 | ||
13810 | A similar function exists in GCC. */ | |
e7af610e NC |
13811 | |
13812 | static const struct mips_cpu_info * | |
17a2f251 | 13813 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13814 | { |
316f5878 | 13815 | const struct mips_cpu_info *p; |
e7af610e | 13816 | |
316f5878 RS |
13817 | /* 'from-abi' selects the most compatible architecture for the given |
13818 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13819 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13820 | version. Look first at the -mgp options, if given, otherwise base | |
13821 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13822 | |
316f5878 RS |
13823 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13824 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13825 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13826 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13827 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13828 | { | |
13829 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13830 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13831 | ||
13832 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13833 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13834 | ||
13835 | if (file_mips_gp32 >= 0) | |
13836 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13837 | ||
13838 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13839 | ? ISA_MIPS3 | |
13840 | : ISA_MIPS1); | |
13841 | } | |
13842 | ||
13843 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13844 | if (strcasecmp (cpu_string, "default") == 0) | |
13845 | return 0; | |
13846 | ||
13847 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13848 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13849 | return p; | |
13850 | ||
13851 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13852 | return 0; | |
e7af610e NC |
13853 | } |
13854 | ||
316f5878 RS |
13855 | /* Return the canonical processor information for ISA (a member of the |
13856 | ISA_MIPS* enumeration). */ | |
13857 | ||
e7af610e | 13858 | static const struct mips_cpu_info * |
17a2f251 | 13859 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13860 | { |
13861 | int i; | |
13862 | ||
13863 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13864 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13865 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13866 | return (&mips_cpu_info_table[i]); |
13867 | ||
e972090a | 13868 | return NULL; |
e7af610e | 13869 | } |
fef14a42 TS |
13870 | |
13871 | static const struct mips_cpu_info * | |
17a2f251 | 13872 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13873 | { |
13874 | int i; | |
13875 | ||
13876 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13877 | if (arch == mips_cpu_info_table[i].cpu) | |
13878 | return (&mips_cpu_info_table[i]); | |
13879 | ||
13880 | return NULL; | |
13881 | } | |
316f5878 RS |
13882 | \f |
13883 | static void | |
17a2f251 | 13884 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13885 | { |
13886 | if (*first_p) | |
13887 | { | |
13888 | fprintf (stream, "%24s", ""); | |
13889 | *col_p = 24; | |
13890 | } | |
13891 | else | |
13892 | { | |
13893 | fprintf (stream, ", "); | |
13894 | *col_p += 2; | |
13895 | } | |
e7af610e | 13896 | |
316f5878 RS |
13897 | if (*col_p + strlen (string) > 72) |
13898 | { | |
13899 | fprintf (stream, "\n%24s", ""); | |
13900 | *col_p = 24; | |
13901 | } | |
13902 | ||
13903 | fprintf (stream, "%s", string); | |
13904 | *col_p += strlen (string); | |
13905 | ||
13906 | *first_p = 0; | |
13907 | } | |
13908 | ||
13909 | void | |
17a2f251 | 13910 | md_show_usage (FILE *stream) |
e7af610e | 13911 | { |
316f5878 RS |
13912 | int column, first; |
13913 | size_t i; | |
13914 | ||
13915 | fprintf (stream, _("\ | |
13916 | MIPS options:\n\ | |
316f5878 RS |
13917 | -EB generate big endian output\n\ |
13918 | -EL generate little endian output\n\ | |
13919 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13920 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13921 | implicitly with the gp register [default 8]\n")); | |
13922 | fprintf (stream, _("\ | |
13923 | -mips1 generate MIPS ISA I instructions\n\ | |
13924 | -mips2 generate MIPS ISA II instructions\n\ | |
13925 | -mips3 generate MIPS ISA III instructions\n\ | |
13926 | -mips4 generate MIPS ISA IV instructions\n\ | |
13927 | -mips5 generate MIPS ISA V instructions\n\ | |
13928 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13929 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13930 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13931 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13932 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13933 | ||
13934 | first = 1; | |
e7af610e NC |
13935 | |
13936 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13937 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13938 | show (stream, "from-abi", &column, &first); | |
13939 | fputc ('\n', stream); | |
e7af610e | 13940 | |
316f5878 RS |
13941 | fprintf (stream, _("\ |
13942 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13943 | -no-mCPU don't generate code specific to CPU.\n\ | |
13944 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13945 | ||
13946 | first = 1; | |
13947 | ||
13948 | show (stream, "3900", &column, &first); | |
13949 | show (stream, "4010", &column, &first); | |
13950 | show (stream, "4100", &column, &first); | |
13951 | show (stream, "4650", &column, &first); | |
13952 | fputc ('\n', stream); | |
13953 | ||
13954 | fprintf (stream, _("\ | |
13955 | -mips16 generate mips16 instructions\n\ | |
13956 | -no-mips16 do not generate mips16 instructions\n")); | |
13957 | fprintf (stream, _("\ | |
d766e8ec | 13958 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 13959 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
13960 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
13961 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
13962 | -mno-shared optimize output for executables\n\ |
13963 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
13964 | -O0 remove unneeded NOPs, do not swap branches\n\ |
13965 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
13966 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
13967 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
13968 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
13969 | #ifdef OBJ_ELF | |
13970 | fprintf (stream, _("\ | |
13971 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
13972 | -non_shared do not generate position independent code\n\ | |
13973 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 13974 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
13975 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
13976 | non-shared code\n\ | |
316f5878 RS |
13977 | -mabi=ABI create ABI conformant object file for:\n")); |
13978 | ||
13979 | first = 1; | |
13980 | ||
13981 | show (stream, "32", &column, &first); | |
13982 | show (stream, "o64", &column, &first); | |
13983 | show (stream, "n32", &column, &first); | |
13984 | show (stream, "64", &column, &first); | |
13985 | show (stream, "eabi", &column, &first); | |
13986 | ||
13987 | fputc ('\n', stream); | |
13988 | ||
13989 | fprintf (stream, _("\ | |
13990 | -32 create o32 ABI object file (default)\n\ | |
13991 | -n32 create n32 ABI object file\n\ | |
13992 | -64 create 64 ABI object file\n")); | |
13993 | #endif | |
e7af610e | 13994 | } |
14e777e0 KB |
13995 | |
13996 | enum dwarf2_format | |
17a2f251 | 13997 | mips_dwarf2_format (void) |
14e777e0 KB |
13998 | { |
13999 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14000 | { |
14001 | #ifdef TE_IRIX | |
14002 | return dwarf2_format_64bit_irix; | |
14003 | #else | |
14004 | return dwarf2_format_64bit; | |
14005 | #endif | |
14006 | } | |
14e777e0 KB |
14007 | else |
14008 | return dwarf2_format_32bit; | |
14009 | } | |
73369e65 EC |
14010 | |
14011 | int | |
14012 | mips_dwarf2_addr_size (void) | |
14013 | { | |
14014 | if (mips_abi == N64_ABI) | |
14015 | return 8; | |
73369e65 EC |
14016 | else |
14017 | return 4; | |
14018 | } |