Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d RS |
152 | |
153 | /* True if this instruction occured in a .set noreorder block. */ | |
154 | unsigned int noreorder_p : 1; | |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
74cd071d | 196 | int ase_dsp; |
252b5132 RH |
197 | /* Whether we are assembling for the mips16 processor. 0 if we are |
198 | not, 1 if we are, and -1 if the value has not been initialized. | |
199 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
200 | -nomips16 command line options, and the default CPU. */ | |
201 | int mips16; | |
202 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
203 | reorder' and `.set noreorder'. */ | |
204 | int noreorder; | |
205 | /* Non-zero if we should not permit the $at ($1) register to be used | |
206 | in instructions. Changed by `.set at' and `.set noat'. */ | |
207 | int noat; | |
208 | /* Non-zero if we should warn when a macro instruction expands into | |
209 | more than one machine instruction. Changed by `.set nomacro' and | |
210 | `.set macro'. */ | |
211 | int warn_about_macros; | |
212 | /* Non-zero if we should not move instructions. Changed by `.set | |
213 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
214 | int nomove; | |
215 | /* Non-zero if we should not optimize branches by moving the target | |
216 | of the branch into the delay slot. Actually, we don't perform | |
217 | this optimization anyhow. Changed by `.set bopt' and `.set | |
218 | nobopt'. */ | |
219 | int nobopt; | |
220 | /* Non-zero if we should not autoextend mips16 instructions. | |
221 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
222 | int noautoextend; | |
a325df1d TS |
223 | /* Restrict general purpose registers and floating point registers |
224 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
225 | is passed but can changed if the assembler code uses .set mipsN. */ | |
226 | int gp32; | |
227 | int fp32; | |
fef14a42 TS |
228 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
229 | command line option, and the default CPU. */ | |
230 | int arch; | |
aed1a261 RS |
231 | /* True if ".set sym32" is in effect. */ |
232 | bfd_boolean sym32; | |
252b5132 RH |
233 | }; |
234 | ||
a325df1d | 235 | /* True if -mgp32 was passed. */ |
a8e8e863 | 236 | static int file_mips_gp32 = -1; |
a325df1d TS |
237 | |
238 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 239 | static int file_mips_fp32 = -1; |
a325df1d | 240 | |
252b5132 | 241 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 242 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 243 | -1 to indicate that they have not been initialized. */ |
252b5132 | 244 | |
e972090a NC |
245 | static struct mips_set_options mips_opts = |
246 | { | |
74cd071d | 247 | ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 248 | }; |
252b5132 RH |
249 | |
250 | /* These variables are filled in with the masks of registers used. | |
251 | The object format code reads them and puts them in the appropriate | |
252 | place. */ | |
253 | unsigned long mips_gprmask; | |
254 | unsigned long mips_cprmask[4]; | |
255 | ||
256 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 257 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 258 | |
a4672219 TS |
259 | /* True if -mips16 was passed or implied by arguments passed on the |
260 | command line (e.g., by -march). */ | |
261 | static int file_ase_mips16; | |
262 | ||
1f25f5d3 CD |
263 | /* True if -mips3d was passed or implied by arguments passed on the |
264 | command line (e.g., by -march). */ | |
265 | static int file_ase_mips3d; | |
266 | ||
deec1734 CD |
267 | /* True if -mdmx was passed or implied by arguments passed on the |
268 | command line (e.g., by -march). */ | |
269 | static int file_ase_mdmx; | |
270 | ||
74cd071d CF |
271 | /* True if -mdsp was passed or implied by arguments passed on the |
272 | command line (e.g., by -march). */ | |
273 | static int file_ase_dsp; | |
274 | ||
ec68c924 | 275 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 276 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 277 | static const char *mips_arch_string; |
ec68c924 EC |
278 | |
279 | /* The argument of the -mtune= flag. The architecture for which we | |
280 | are optimizing. */ | |
281 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 282 | static const char *mips_tune_string; |
ec68c924 | 283 | |
316f5878 | 284 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
285 | static int mips_32bitmode = 0; |
286 | ||
316f5878 RS |
287 | /* True if the given ABI requires 32-bit registers. */ |
288 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
289 | ||
290 | /* Likewise 64-bit registers. */ | |
291 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
292 | ((ABI) == N32_ABI \ | |
293 | || (ABI) == N64_ABI \ | |
294 | || (ABI) == O64_ABI) | |
295 | ||
bdaaa2e1 | 296 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 297 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
298 | (ISA) == ISA_MIPS3 \ |
299 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 300 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 301 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 302 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
303 | ) |
304 | ||
af7ee8bf CD |
305 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
306 | instructions. */ | |
307 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 308 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
309 | ) |
310 | ||
311 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
312 | instructions. */ | |
313 | #define ISA_HAS_ROR(ISA) ( \ | |
314 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 315 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
316 | ) |
317 | ||
e013f690 | 318 | #define HAVE_32BIT_GPRS \ |
316f5878 | 319 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 320 | |
e013f690 | 321 | #define HAVE_32BIT_FPRS \ |
316f5878 | 322 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
323 | |
324 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
325 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
326 | ||
316f5878 | 327 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 328 | |
316f5878 | 329 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 330 | |
3b91255e RS |
331 | /* True if relocations are stored in-place. */ |
332 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
333 | ||
aed1a261 RS |
334 | /* The ABI-derived address size. */ |
335 | #define HAVE_64BIT_ADDRESSES \ | |
336 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
337 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 338 | |
aed1a261 RS |
339 | /* The size of symbolic constants (i.e., expressions of the form |
340 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
341 | #define HAVE_32BIT_SYMBOLS \ | |
342 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
343 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 344 | |
b7c7d6c1 TS |
345 | /* Addresses are loaded in different ways, depending on the address size |
346 | in use. The n32 ABI Documentation also mandates the use of additions | |
347 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 348 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 349 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
350 | |
351 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 352 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
353 | |
354 | #define ADDRESS_LOAD_INSN \ | |
355 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
356 | ||
357 | #define ADDRESS_STORE_INSN \ | |
358 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
359 | ||
a4672219 | 360 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
361 | #define CPU_HAS_MIPS16(cpu) \ |
362 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
363 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 364 | |
1f25f5d3 CD |
365 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
366 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
367 | ) | |
368 | ||
deec1734 | 369 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 370 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
371 | ) |
372 | ||
74cd071d CF |
373 | /* Return true if the given CPU supports the DSP ASE. */ |
374 | #define CPU_HAS_DSP(cpu) (FALSE \ | |
375 | ) | |
376 | ||
60b63b72 RS |
377 | /* True if CPU has a dror instruction. */ |
378 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
379 | ||
380 | /* True if CPU has a ror instruction. */ | |
381 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
382 | ||
c8978940 CD |
383 | /* True if mflo and mfhi can be immediately followed by instructions |
384 | which write to the HI and LO registers. | |
385 | ||
386 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
387 | (at least) two instructions between the reads of HI/LO and | |
388 | instructions which write them, and later ISAs do not. Contradicting | |
389 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
390 | the UM for the NEC Vr5000) document needing the instructions between | |
391 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
392 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
393 | earlier-ISA CPUs for which CPU documentation declares that the | |
394 | instructions are really interlocked. */ | |
395 | #define hilo_interlocks \ | |
396 | (mips_opts.isa == ISA_MIPS32 \ | |
397 | || mips_opts.isa == ISA_MIPS32R2 \ | |
398 | || mips_opts.isa == ISA_MIPS64 \ | |
399 | || mips_opts.isa == ISA_MIPS64R2 \ | |
400 | || mips_opts.arch == CPU_R4010 \ | |
401 | || mips_opts.arch == CPU_R10000 \ | |
402 | || mips_opts.arch == CPU_R12000 \ | |
403 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
404 | || mips_opts.arch == CPU_VR5500 \ |
405 | ) | |
252b5132 RH |
406 | |
407 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
408 | from the GPRs after they are loaded from memory, and thus does not |
409 | require nops to be inserted. This applies to instructions marked | |
410 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
411 | level I. */ | |
252b5132 | 412 | #define gpr_interlocks \ |
e7af610e | 413 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 414 | || mips_opts.arch == CPU_R3900) |
252b5132 | 415 | |
81912461 ILT |
416 | /* Whether the processor uses hardware interlocks to avoid delays |
417 | required by coprocessor instructions, and thus does not require | |
418 | nops to be inserted. This applies to instructions marked | |
419 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
420 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
421 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
422 | levels I, II, and III. */ | |
bdaaa2e1 | 423 | /* Itbl support may require additional care here. */ |
81912461 ILT |
424 | #define cop_interlocks \ |
425 | ((mips_opts.isa != ISA_MIPS1 \ | |
426 | && mips_opts.isa != ISA_MIPS2 \ | |
427 | && mips_opts.isa != ISA_MIPS3) \ | |
428 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
429 | ) |
430 | ||
431 | /* Whether the processor uses hardware interlocks to protect reads | |
432 | from coprocessor registers after they are loaded from memory, and | |
433 | thus does not require nops to be inserted. This applies to | |
434 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
435 | requires at MIPS ISA level I. */ | |
436 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 437 | |
6b76fefe CM |
438 | /* Is this a mfhi or mflo instruction? */ |
439 | #define MF_HILO_INSN(PINFO) \ | |
440 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
441 | ||
252b5132 RH |
442 | /* MIPS PIC level. */ |
443 | ||
a161fe53 | 444 | enum mips_pic_level mips_pic; |
252b5132 | 445 | |
c9914766 | 446 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 447 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 448 | static int mips_big_got = 0; |
252b5132 RH |
449 | |
450 | /* 1 if trap instructions should used for overflow rather than break | |
451 | instructions. */ | |
c9914766 | 452 | static int mips_trap = 0; |
252b5132 | 453 | |
119d663a | 454 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 455 | by assembling two single width halves into two single width floating |
119d663a NC |
456 | point registers which just happen to alias the double width destination |
457 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 458 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
459 | automatically at assemble time. */ |
460 | static int mips_disable_float_construction; | |
461 | ||
252b5132 RH |
462 | /* Non-zero if any .set noreorder directives were used. */ |
463 | ||
464 | static int mips_any_noreorder; | |
465 | ||
6b76fefe CM |
466 | /* Non-zero if nops should be inserted when the register referenced in |
467 | an mfhi/mflo instruction is read in the next two instructions. */ | |
468 | static int mips_7000_hilo_fix; | |
469 | ||
252b5132 | 470 | /* The size of the small data section. */ |
156c2f8b | 471 | static unsigned int g_switch_value = 8; |
252b5132 RH |
472 | /* Whether the -G option was used. */ |
473 | static int g_switch_seen = 0; | |
474 | ||
475 | #define N_RMASK 0xc4 | |
476 | #define N_VFP 0xd4 | |
477 | ||
478 | /* If we can determine in advance that GP optimization won't be | |
479 | possible, we can skip the relaxation stuff that tries to produce | |
480 | GP-relative references. This makes delay slot optimization work | |
481 | better. | |
482 | ||
483 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
484 | gcc output. It needs to guess right for gcc, otherwise gcc |
485 | will put what it thinks is a GP-relative instruction in a branch | |
486 | delay slot. | |
252b5132 RH |
487 | |
488 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
489 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 490 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
491 | |
492 | /* handle of the OPCODE hash table */ | |
493 | static struct hash_control *op_hash = NULL; | |
494 | ||
495 | /* The opcode hash table we use for the mips16. */ | |
496 | static struct hash_control *mips16_op_hash = NULL; | |
497 | ||
498 | /* This array holds the chars that always start a comment. If the | |
499 | pre-processor is disabled, these aren't very useful */ | |
500 | const char comment_chars[] = "#"; | |
501 | ||
502 | /* This array holds the chars that only start a comment at the beginning of | |
503 | a line. If the line seems to have the form '# 123 filename' | |
504 | .line and .file directives will appear in the pre-processed output */ | |
505 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
506 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 507 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
508 | /* Also note that C style comments are always supported. */ |
509 | const char line_comment_chars[] = "#"; | |
510 | ||
bdaaa2e1 | 511 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 512 | const char line_separator_chars[] = ";"; |
252b5132 RH |
513 | |
514 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
515 | const char EXP_CHARS[] = "eE"; | |
516 | ||
517 | /* Chars that mean this number is a floating point constant */ | |
518 | /* As in 0f12.456 */ | |
519 | /* or 0d1.2345e12 */ | |
520 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
521 | ||
522 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
523 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
524 | but nothing is ideal around here. | |
525 | */ | |
526 | ||
527 | static char *insn_error; | |
528 | ||
529 | static int auto_align = 1; | |
530 | ||
531 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
532 | offset in the stack frame from which to restore the $gp register. | |
533 | This is set by the .cprestore pseudo-op, and saved in this | |
534 | variable. */ | |
535 | static offsetT mips_cprestore_offset = -1; | |
536 | ||
67c1ffbe | 537 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 538 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 539 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
540 | static offsetT mips_cpreturn_offset = -1; |
541 | static int mips_cpreturn_register = -1; | |
542 | static int mips_gp_register = GP; | |
def2e0dd | 543 | static int mips_gprel_offset = 0; |
6478892d | 544 | |
7a621144 DJ |
545 | /* Whether mips_cprestore_offset has been set in the current function |
546 | (or whether it has already been warned about, if not). */ | |
547 | static int mips_cprestore_valid = 0; | |
548 | ||
252b5132 RH |
549 | /* This is the register which holds the stack frame, as set by the |
550 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
551 | static int mips_frame_reg = SP; | |
552 | ||
7a621144 DJ |
553 | /* Whether mips_frame_reg has been set in the current function |
554 | (or whether it has already been warned about, if not). */ | |
555 | static int mips_frame_reg_valid = 0; | |
556 | ||
252b5132 RH |
557 | /* To output NOP instructions correctly, we need to keep information |
558 | about the previous two instructions. */ | |
559 | ||
560 | /* Whether we are optimizing. The default value of 2 means to remove | |
561 | unneeded NOPs and swap branch instructions when possible. A value | |
562 | of 1 means to not swap branches. A value of 0 means to always | |
563 | insert NOPs. */ | |
564 | static int mips_optimize = 2; | |
565 | ||
566 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
567 | equivalent to seeing no -g option at all. */ | |
568 | static int mips_debug = 0; | |
569 | ||
7d8e00cf RS |
570 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
571 | #define MAX_VR4130_NOPS 4 | |
572 | ||
573 | /* The maximum number of NOPs needed to fill delay slots. */ | |
574 | #define MAX_DELAY_NOPS 2 | |
575 | ||
576 | /* The maximum number of NOPs needed for any purpose. */ | |
577 | #define MAX_NOPS 4 | |
71400594 RS |
578 | |
579 | /* A list of previous instructions, with index 0 being the most recent. | |
580 | We need to look back MAX_NOPS instructions when filling delay slots | |
581 | or working around processor errata. We need to look back one | |
582 | instruction further if we're thinking about using history[0] to | |
583 | fill a branch delay slot. */ | |
584 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 585 | |
1e915849 RS |
586 | /* Nop instructions used by emit_nop. */ |
587 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
588 | ||
589 | /* The appropriate nop for the current mode. */ | |
590 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 591 | |
252b5132 RH |
592 | /* If this is set, it points to a frag holding nop instructions which |
593 | were inserted before the start of a noreorder section. If those | |
594 | nops turn out to be unnecessary, the size of the frag can be | |
595 | decreased. */ | |
596 | static fragS *prev_nop_frag; | |
597 | ||
598 | /* The number of nop instructions we created in prev_nop_frag. */ | |
599 | static int prev_nop_frag_holds; | |
600 | ||
601 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 602 | prev_nop_frag. */ |
252b5132 RH |
603 | static int prev_nop_frag_required; |
604 | ||
605 | /* The number of instructions we've seen since prev_nop_frag. */ | |
606 | static int prev_nop_frag_since; | |
607 | ||
608 | /* For ECOFF and ELF, relocations against symbols are done in two | |
609 | parts, with a HI relocation and a LO relocation. Each relocation | |
610 | has only 16 bits of space to store an addend. This means that in | |
611 | order for the linker to handle carries correctly, it must be able | |
612 | to locate both the HI and the LO relocation. This means that the | |
613 | relocations must appear in order in the relocation table. | |
614 | ||
615 | In order to implement this, we keep track of each unmatched HI | |
616 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 617 | corresponding LO relocation. */ |
252b5132 | 618 | |
e972090a NC |
619 | struct mips_hi_fixup |
620 | { | |
252b5132 RH |
621 | /* Next HI fixup. */ |
622 | struct mips_hi_fixup *next; | |
623 | /* This fixup. */ | |
624 | fixS *fixp; | |
625 | /* The section this fixup is in. */ | |
626 | segT seg; | |
627 | }; | |
628 | ||
629 | /* The list of unmatched HI relocs. */ | |
630 | ||
631 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
632 | ||
64bdfcaf RS |
633 | /* The frag containing the last explicit relocation operator. |
634 | Null if explicit relocations have not been used. */ | |
635 | ||
636 | static fragS *prev_reloc_op_frag; | |
637 | ||
252b5132 RH |
638 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
639 | ||
640 | #define X ILLEGAL_REG | |
e972090a NC |
641 | static const int mips32_to_16_reg_map[] = |
642 | { | |
252b5132 RH |
643 | X, X, 2, 3, 4, 5, 6, 7, |
644 | X, X, X, X, X, X, X, X, | |
645 | 0, 1, X, X, X, X, X, X, | |
646 | X, X, X, X, X, X, X, X | |
647 | }; | |
648 | #undef X | |
649 | ||
650 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
651 | ||
e972090a NC |
652 | static const unsigned int mips16_to_32_reg_map[] = |
653 | { | |
252b5132 RH |
654 | 16, 17, 2, 3, 4, 5, 6, 7 |
655 | }; | |
60b63b72 | 656 | |
71400594 RS |
657 | /* Classifies the kind of instructions we're interested in when |
658 | implementing -mfix-vr4120. */ | |
659 | enum fix_vr4120_class { | |
660 | FIX_VR4120_MACC, | |
661 | FIX_VR4120_DMACC, | |
662 | FIX_VR4120_MULT, | |
663 | FIX_VR4120_DMULT, | |
664 | FIX_VR4120_DIV, | |
665 | FIX_VR4120_MTHILO, | |
666 | NUM_FIX_VR4120_CLASSES | |
667 | }; | |
668 | ||
669 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
670 | there must be at least one other instruction between an instruction | |
671 | of type X and an instruction of type Y. */ | |
672 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
673 | ||
674 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 675 | static int mips_fix_vr4120; |
4a6a3df4 | 676 | |
7d8e00cf RS |
677 | /* ...likewise -mfix-vr4130. */ |
678 | static int mips_fix_vr4130; | |
679 | ||
4a6a3df4 AO |
680 | /* We don't relax branches by default, since this causes us to expand |
681 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
682 | fail to compute the offset before expanding the macro to the most | |
683 | efficient expansion. */ | |
684 | ||
685 | static int mips_relax_branch; | |
252b5132 | 686 | \f |
4d7206a2 RS |
687 | /* The expansion of many macros depends on the type of symbol that |
688 | they refer to. For example, when generating position-dependent code, | |
689 | a macro that refers to a symbol may have two different expansions, | |
690 | one which uses GP-relative addresses and one which uses absolute | |
691 | addresses. When generating SVR4-style PIC, a macro may have | |
692 | different expansions for local and global symbols. | |
693 | ||
694 | We handle these situations by generating both sequences and putting | |
695 | them in variant frags. In position-dependent code, the first sequence | |
696 | will be the GP-relative one and the second sequence will be the | |
697 | absolute one. In SVR4 PIC, the first sequence will be for global | |
698 | symbols and the second will be for local symbols. | |
699 | ||
584892a6 RS |
700 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
701 | SECOND are the lengths of the two sequences in bytes. These fields | |
702 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
703 | the subtype has the following flags: | |
4d7206a2 | 704 | |
584892a6 RS |
705 | RELAX_USE_SECOND |
706 | Set if it has been decided that we should use the second | |
707 | sequence instead of the first. | |
708 | ||
709 | RELAX_SECOND_LONGER | |
710 | Set in the first variant frag if the macro's second implementation | |
711 | is longer than its first. This refers to the macro as a whole, | |
712 | not an individual relaxation. | |
713 | ||
714 | RELAX_NOMACRO | |
715 | Set in the first variant frag if the macro appeared in a .set nomacro | |
716 | block and if one alternative requires a warning but the other does not. | |
717 | ||
718 | RELAX_DELAY_SLOT | |
719 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
720 | delay slot. | |
4d7206a2 RS |
721 | |
722 | The frag's "opcode" points to the first fixup for relaxable code. | |
723 | ||
724 | Relaxable macros are generated using a sequence such as: | |
725 | ||
726 | relax_start (SYMBOL); | |
727 | ... generate first expansion ... | |
728 | relax_switch (); | |
729 | ... generate second expansion ... | |
730 | relax_end (); | |
731 | ||
732 | The code and fixups for the unwanted alternative are discarded | |
733 | by md_convert_frag. */ | |
584892a6 | 734 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 735 | |
584892a6 RS |
736 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
737 | #define RELAX_SECOND(X) ((X) & 0xff) | |
738 | #define RELAX_USE_SECOND 0x10000 | |
739 | #define RELAX_SECOND_LONGER 0x20000 | |
740 | #define RELAX_NOMACRO 0x40000 | |
741 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 742 | |
4a6a3df4 AO |
743 | /* Branch without likely bit. If label is out of range, we turn: |
744 | ||
745 | beq reg1, reg2, label | |
746 | delay slot | |
747 | ||
748 | into | |
749 | ||
750 | bne reg1, reg2, 0f | |
751 | nop | |
752 | j label | |
753 | 0: delay slot | |
754 | ||
755 | with the following opcode replacements: | |
756 | ||
757 | beq <-> bne | |
758 | blez <-> bgtz | |
759 | bltz <-> bgez | |
760 | bc1f <-> bc1t | |
761 | ||
762 | bltzal <-> bgezal (with jal label instead of j label) | |
763 | ||
764 | Even though keeping the delay slot instruction in the delay slot of | |
765 | the branch would be more efficient, it would be very tricky to do | |
766 | correctly, because we'd have to introduce a variable frag *after* | |
767 | the delay slot instruction, and expand that instead. Let's do it | |
768 | the easy way for now, even if the branch-not-taken case now costs | |
769 | one additional instruction. Out-of-range branches are not supposed | |
770 | to be common, anyway. | |
771 | ||
772 | Branch likely. If label is out of range, we turn: | |
773 | ||
774 | beql reg1, reg2, label | |
775 | delay slot (annulled if branch not taken) | |
776 | ||
777 | into | |
778 | ||
779 | beql reg1, reg2, 1f | |
780 | nop | |
781 | beql $0, $0, 2f | |
782 | nop | |
783 | 1: j[al] label | |
784 | delay slot (executed only if branch taken) | |
785 | 2: | |
786 | ||
787 | It would be possible to generate a shorter sequence by losing the | |
788 | likely bit, generating something like: | |
b34976b6 | 789 | |
4a6a3df4 AO |
790 | bne reg1, reg2, 0f |
791 | nop | |
792 | j[al] label | |
793 | delay slot (executed only if branch taken) | |
794 | 0: | |
795 | ||
796 | beql -> bne | |
797 | bnel -> beq | |
798 | blezl -> bgtz | |
799 | bgtzl -> blez | |
800 | bltzl -> bgez | |
801 | bgezl -> bltz | |
802 | bc1fl -> bc1t | |
803 | bc1tl -> bc1f | |
804 | ||
805 | bltzall -> bgezal (with jal label instead of j label) | |
806 | bgezall -> bltzal (ditto) | |
807 | ||
808 | ||
809 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 810 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
811 | ((relax_substateT) \ |
812 | (0xc0000000 \ | |
813 | | ((toofar) ? 1 : 0) \ | |
814 | | ((link) ? 2 : 0) \ | |
815 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 816 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 817 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
818 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
819 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
820 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 821 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 822 | |
252b5132 RH |
823 | /* For mips16 code, we use an entirely different form of relaxation. |
824 | mips16 supports two versions of most instructions which take | |
825 | immediate values: a small one which takes some small value, and a | |
826 | larger one which takes a 16 bit value. Since branches also follow | |
827 | this pattern, relaxing these values is required. | |
828 | ||
829 | We can assemble both mips16 and normal MIPS code in a single | |
830 | object. Therefore, we need to support this type of relaxation at | |
831 | the same time that we support the relaxation described above. We | |
832 | use the high bit of the subtype field to distinguish these cases. | |
833 | ||
834 | The information we store for this type of relaxation is the | |
835 | argument code found in the opcode file for this relocation, whether | |
836 | the user explicitly requested a small or extended form, and whether | |
837 | the relocation is in a jump or jal delay slot. That tells us the | |
838 | size of the value, and how it should be stored. We also store | |
839 | whether the fragment is considered to be extended or not. We also | |
840 | store whether this is known to be a branch to a different section, | |
841 | whether we have tried to relax this frag yet, and whether we have | |
842 | ever extended a PC relative fragment because of a shift count. */ | |
843 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
844 | (0x80000000 \ | |
845 | | ((type) & 0xff) \ | |
846 | | ((small) ? 0x100 : 0) \ | |
847 | | ((ext) ? 0x200 : 0) \ | |
848 | | ((dslot) ? 0x400 : 0) \ | |
849 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 850 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
851 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
852 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
853 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
854 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
855 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
856 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
857 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
858 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
859 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
860 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
861 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
862 | |
863 | /* Is the given value a sign-extended 32-bit value? */ | |
864 | #define IS_SEXT_32BIT_NUM(x) \ | |
865 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
866 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
867 | ||
868 | /* Is the given value a sign-extended 16-bit value? */ | |
869 | #define IS_SEXT_16BIT_NUM(x) \ | |
870 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
871 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
872 | ||
2051e8c4 MR |
873 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
874 | #define IS_ZEXT_32BIT_NUM(x) \ | |
875 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
876 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
877 | ||
bf12938e RS |
878 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
879 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
880 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
881 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
882 | | (((VALUE) & (MASK)) << (SHIFT))) | |
883 | ||
884 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
885 | SHIFT places. */ | |
886 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
887 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
888 | ||
889 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
890 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
891 | ||
892 | include/opcode/mips.h specifies operand fields using the macros | |
893 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
894 | with "MIPS16OP" instead of "OP". */ | |
895 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
896 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
897 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
898 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
899 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
900 | ||
901 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
902 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
903 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
904 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
905 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
906 | MIPS16OP_MASK_##FIELD, \ | |
907 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
908 | \f |
909 | /* Global variables used when generating relaxable macros. See the | |
910 | comment above RELAX_ENCODE for more details about how relaxation | |
911 | is used. */ | |
912 | static struct { | |
913 | /* 0 if we're not emitting a relaxable macro. | |
914 | 1 if we're emitting the first of the two relaxation alternatives. | |
915 | 2 if we're emitting the second alternative. */ | |
916 | int sequence; | |
917 | ||
918 | /* The first relaxable fixup in the current frag. (In other words, | |
919 | the first fixup that refers to relaxable code.) */ | |
920 | fixS *first_fixup; | |
921 | ||
922 | /* sizes[0] says how many bytes of the first alternative are stored in | |
923 | the current frag. Likewise sizes[1] for the second alternative. */ | |
924 | unsigned int sizes[2]; | |
925 | ||
926 | /* The symbol on which the choice of sequence depends. */ | |
927 | symbolS *symbol; | |
928 | } mips_relax; | |
252b5132 | 929 | \f |
584892a6 RS |
930 | /* Global variables used to decide whether a macro needs a warning. */ |
931 | static struct { | |
932 | /* True if the macro is in a branch delay slot. */ | |
933 | bfd_boolean delay_slot_p; | |
934 | ||
935 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
936 | in bytes and sizes[1] is the length of the second alternative. | |
937 | For non-relaxable macros, both elements give the length of the | |
938 | macro in bytes. */ | |
939 | unsigned int sizes[2]; | |
940 | ||
941 | /* The first variant frag for this macro. */ | |
942 | fragS *first_frag; | |
943 | } mips_macro_warning; | |
944 | \f | |
252b5132 RH |
945 | /* Prototypes for static functions. */ |
946 | ||
17a2f251 | 947 | #define internalError() \ |
252b5132 | 948 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
949 | |
950 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
951 | ||
b34976b6 | 952 | static void append_insn |
4d7206a2 | 953 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 954 | static void mips_no_prev_insn (void); |
b34976b6 | 955 | static void mips16_macro_build |
67c0d1eb RS |
956 | (expressionS *, const char *, const char *, va_list); |
957 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
958 | static void macro_start (void); |
959 | static void macro_end (void); | |
17a2f251 TS |
960 | static void macro (struct mips_cl_insn * ip); |
961 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 962 | #ifdef LOSING_COMPILER |
17a2f251 | 963 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 964 | #endif |
17a2f251 TS |
965 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
966 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 967 | static void mips16_immed |
17a2f251 TS |
968 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
969 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 970 | static size_t my_getSmallExpression |
17a2f251 TS |
971 | (expressionS *, bfd_reloc_code_real_type *, char *); |
972 | static void my_getExpression (expressionS *, char *); | |
973 | static void s_align (int); | |
974 | static void s_change_sec (int); | |
975 | static void s_change_section (int); | |
976 | static void s_cons (int); | |
977 | static void s_float_cons (int); | |
978 | static void s_mips_globl (int); | |
979 | static void s_option (int); | |
980 | static void s_mipsset (int); | |
981 | static void s_abicalls (int); | |
982 | static void s_cpload (int); | |
983 | static void s_cpsetup (int); | |
984 | static void s_cplocal (int); | |
985 | static void s_cprestore (int); | |
986 | static void s_cpreturn (int); | |
987 | static void s_gpvalue (int); | |
988 | static void s_gpword (int); | |
989 | static void s_gpdword (int); | |
990 | static void s_cpadd (int); | |
991 | static void s_insn (int); | |
992 | static void md_obj_begin (void); | |
993 | static void md_obj_end (void); | |
994 | static void s_mips_ent (int); | |
995 | static void s_mips_end (int); | |
996 | static void s_mips_frame (int); | |
997 | static void s_mips_mask (int reg_type); | |
998 | static void s_mips_stab (int); | |
999 | static void s_mips_weakext (int); | |
1000 | static void s_mips_file (int); | |
1001 | static void s_mips_loc (int); | |
1002 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1003 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1004 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1005 | |
1006 | /* Table and functions used to map between CPU/ISA names, and | |
1007 | ISA levels, and CPU numbers. */ | |
1008 | ||
e972090a NC |
1009 | struct mips_cpu_info |
1010 | { | |
e7af610e NC |
1011 | const char *name; /* CPU or ISA name. */ |
1012 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
1013 | int isa; /* ISA level. */ | |
1014 | int cpu; /* CPU number (default CPU if ISA). */ | |
1015 | }; | |
1016 | ||
17a2f251 TS |
1017 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1018 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1019 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1020 | \f |
1021 | /* Pseudo-op table. | |
1022 | ||
1023 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1024 | should be defined here, but are currently unsupported: .alias, | |
1025 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1026 | ||
1027 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1028 | specific to the type of debugging information being generated, and | |
1029 | should be defined by the object format: .aent, .begin, .bend, | |
1030 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1031 | .vreg. | |
1032 | ||
1033 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1034 | not MIPS CPU specific, but are also not specific to the object file | |
1035 | format. This file is probably the best place to define them, but | |
1036 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1037 | .struct. */ | |
1038 | ||
e972090a NC |
1039 | static const pseudo_typeS mips_pseudo_table[] = |
1040 | { | |
beae10d5 | 1041 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1042 | {"option", s_option, 0}, |
1043 | {"set", s_mipsset, 0}, | |
1044 | {"rdata", s_change_sec, 'r'}, | |
1045 | {"sdata", s_change_sec, 's'}, | |
1046 | {"livereg", s_ignore, 0}, | |
1047 | {"abicalls", s_abicalls, 0}, | |
1048 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1049 | {"cpsetup", s_cpsetup, 0}, |
1050 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1051 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1052 | {"cpreturn", s_cpreturn, 0}, |
1053 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1054 | {"gpword", s_gpword, 0}, |
10181a0d | 1055 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1056 | {"cpadd", s_cpadd, 0}, |
1057 | {"insn", s_insn, 0}, | |
1058 | ||
beae10d5 | 1059 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1060 | chips. */ |
1061 | {"asciiz", stringer, 1}, | |
1062 | {"bss", s_change_sec, 'b'}, | |
1063 | {"err", s_err, 0}, | |
1064 | {"half", s_cons, 1}, | |
1065 | {"dword", s_cons, 3}, | |
1066 | {"weakext", s_mips_weakext, 0}, | |
1067 | ||
beae10d5 | 1068 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1069 | here for one reason or another. */ |
1070 | {"align", s_align, 0}, | |
1071 | {"byte", s_cons, 0}, | |
1072 | {"data", s_change_sec, 'd'}, | |
1073 | {"double", s_float_cons, 'd'}, | |
1074 | {"float", s_float_cons, 'f'}, | |
1075 | {"globl", s_mips_globl, 0}, | |
1076 | {"global", s_mips_globl, 0}, | |
1077 | {"hword", s_cons, 1}, | |
1078 | {"int", s_cons, 2}, | |
1079 | {"long", s_cons, 2}, | |
1080 | {"octa", s_cons, 4}, | |
1081 | {"quad", s_cons, 3}, | |
cca86cc8 | 1082 | {"section", s_change_section, 0}, |
252b5132 RH |
1083 | {"short", s_cons, 1}, |
1084 | {"single", s_float_cons, 'f'}, | |
1085 | {"stabn", s_mips_stab, 'n'}, | |
1086 | {"text", s_change_sec, 't'}, | |
1087 | {"word", s_cons, 2}, | |
add56521 | 1088 | |
add56521 | 1089 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1090 | |
43841e91 | 1091 | { NULL, NULL, 0 }, |
252b5132 RH |
1092 | }; |
1093 | ||
e972090a NC |
1094 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1095 | { | |
beae10d5 KH |
1096 | /* These pseudo-ops should be defined by the object file format. |
1097 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1098 | {"aent", s_mips_ent, 1}, |
1099 | {"bgnb", s_ignore, 0}, | |
1100 | {"end", s_mips_end, 0}, | |
1101 | {"endb", s_ignore, 0}, | |
1102 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1103 | {"file", s_mips_file, 0}, |
252b5132 RH |
1104 | {"fmask", s_mips_mask, 'F'}, |
1105 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1106 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1107 | {"mask", s_mips_mask, 'R'}, |
1108 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1109 | { NULL, NULL, 0 }, |
252b5132 RH |
1110 | }; |
1111 | ||
17a2f251 | 1112 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1113 | |
1114 | void | |
17a2f251 | 1115 | mips_pop_insert (void) |
252b5132 RH |
1116 | { |
1117 | pop_insert (mips_pseudo_table); | |
1118 | if (! ECOFF_DEBUGGING) | |
1119 | pop_insert (mips_nonecoff_pseudo_table); | |
1120 | } | |
1121 | \f | |
1122 | /* Symbols labelling the current insn. */ | |
1123 | ||
e972090a NC |
1124 | struct insn_label_list |
1125 | { | |
252b5132 RH |
1126 | struct insn_label_list *next; |
1127 | symbolS *label; | |
1128 | }; | |
1129 | ||
1130 | static struct insn_label_list *insn_labels; | |
1131 | static struct insn_label_list *free_insn_labels; | |
1132 | ||
17a2f251 | 1133 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1134 | |
1135 | static inline void | |
17a2f251 | 1136 | mips_clear_insn_labels (void) |
252b5132 RH |
1137 | { |
1138 | register struct insn_label_list **pl; | |
1139 | ||
1140 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1141 | ; | |
1142 | *pl = insn_labels; | |
1143 | insn_labels = NULL; | |
1144 | } | |
1145 | \f | |
1146 | static char *expr_end; | |
1147 | ||
1148 | /* Expressions which appear in instructions. These are set by | |
1149 | mips_ip. */ | |
1150 | ||
1151 | static expressionS imm_expr; | |
5f74bc13 | 1152 | static expressionS imm2_expr; |
252b5132 RH |
1153 | static expressionS offset_expr; |
1154 | ||
1155 | /* Relocs associated with imm_expr and offset_expr. */ | |
1156 | ||
f6688943 TS |
1157 | static bfd_reloc_code_real_type imm_reloc[3] |
1158 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1159 | static bfd_reloc_code_real_type offset_reloc[3] | |
1160 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1161 | |
252b5132 RH |
1162 | /* These are set by mips16_ip if an explicit extension is used. */ |
1163 | ||
b34976b6 | 1164 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1165 | |
7ed4a06a | 1166 | #ifdef OBJ_ELF |
ecb4347a DJ |
1167 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1168 | ECOFF debugging. */ | |
252b5132 RH |
1169 | |
1170 | static segT pdr_seg; | |
7ed4a06a | 1171 | #endif |
252b5132 | 1172 | |
e013f690 TS |
1173 | /* The default target format to use. */ |
1174 | ||
1175 | const char * | |
17a2f251 | 1176 | mips_target_format (void) |
e013f690 TS |
1177 | { |
1178 | switch (OUTPUT_FLAVOR) | |
1179 | { | |
e013f690 TS |
1180 | case bfd_target_ecoff_flavour: |
1181 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1182 | case bfd_target_coff_flavour: | |
1183 | return "pe-mips"; | |
1184 | case bfd_target_elf_flavour: | |
1185 | #ifdef TE_TMIPS | |
cfe86eaa | 1186 | /* This is traditional mips. */ |
e013f690 | 1187 | return (target_big_endian |
cfe86eaa TS |
1188 | ? (HAVE_64BIT_OBJECTS |
1189 | ? "elf64-tradbigmips" | |
1190 | : (HAVE_NEWABI | |
1191 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1192 | : (HAVE_64BIT_OBJECTS | |
1193 | ? "elf64-tradlittlemips" | |
1194 | : (HAVE_NEWABI | |
1195 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1196 | #else |
1197 | return (target_big_endian | |
cfe86eaa TS |
1198 | ? (HAVE_64BIT_OBJECTS |
1199 | ? "elf64-bigmips" | |
1200 | : (HAVE_NEWABI | |
1201 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1202 | : (HAVE_64BIT_OBJECTS | |
1203 | ? "elf64-littlemips" | |
1204 | : (HAVE_NEWABI | |
1205 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1206 | #endif |
1207 | default: | |
1208 | abort (); | |
1209 | return NULL; | |
1210 | } | |
1211 | } | |
1212 | ||
1e915849 RS |
1213 | /* Return the length of instruction INSN. */ |
1214 | ||
1215 | static inline unsigned int | |
1216 | insn_length (const struct mips_cl_insn *insn) | |
1217 | { | |
1218 | if (!mips_opts.mips16) | |
1219 | return 4; | |
1220 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1221 | } | |
1222 | ||
1223 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1224 | ||
1225 | static void | |
1226 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1227 | { | |
1228 | size_t i; | |
1229 | ||
1230 | insn->insn_mo = mo; | |
1231 | insn->use_extend = FALSE; | |
1232 | insn->extend = 0; | |
1233 | insn->insn_opcode = mo->match; | |
1234 | insn->frag = NULL; | |
1235 | insn->where = 0; | |
1236 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1237 | insn->fixp[i] = NULL; | |
1238 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1239 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1240 | insn->mips16_absolute_jump_p = 0; | |
1241 | } | |
1242 | ||
1243 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1244 | ||
1245 | static void | |
1246 | install_insn (const struct mips_cl_insn *insn) | |
1247 | { | |
1248 | char *f = insn->frag->fr_literal + insn->where; | |
1249 | if (!mips_opts.mips16) | |
1250 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1251 | else if (insn->mips16_absolute_jump_p) | |
1252 | { | |
1253 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1254 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1255 | } | |
1256 | else | |
1257 | { | |
1258 | if (insn->use_extend) | |
1259 | { | |
1260 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1261 | f += 2; | |
1262 | } | |
1263 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1268 | and install the opcode in the new location. */ | |
1269 | ||
1270 | static void | |
1271 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1272 | { | |
1273 | size_t i; | |
1274 | ||
1275 | insn->frag = frag; | |
1276 | insn->where = where; | |
1277 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1278 | if (insn->fixp[i] != NULL) | |
1279 | { | |
1280 | insn->fixp[i]->fx_frag = frag; | |
1281 | insn->fixp[i]->fx_where = where; | |
1282 | } | |
1283 | install_insn (insn); | |
1284 | } | |
1285 | ||
1286 | /* Add INSN to the end of the output. */ | |
1287 | ||
1288 | static void | |
1289 | add_fixed_insn (struct mips_cl_insn *insn) | |
1290 | { | |
1291 | char *f = frag_more (insn_length (insn)); | |
1292 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1293 | } | |
1294 | ||
1295 | /* Start a variant frag and move INSN to the start of the variant part, | |
1296 | marking it as fixed. The other arguments are as for frag_var. */ | |
1297 | ||
1298 | static void | |
1299 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1300 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1301 | { | |
1302 | frag_grow (max_chars); | |
1303 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1304 | insn->fixed_p = 1; | |
1305 | frag_var (rs_machine_dependent, max_chars, var, | |
1306 | subtype, symbol, offset, NULL); | |
1307 | } | |
1308 | ||
1309 | /* Insert N copies of INSN into the history buffer, starting at | |
1310 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1311 | ||
1312 | static void | |
1313 | insert_into_history (unsigned int first, unsigned int n, | |
1314 | const struct mips_cl_insn *insn) | |
1315 | { | |
1316 | if (mips_relax.sequence != 2) | |
1317 | { | |
1318 | unsigned int i; | |
1319 | ||
1320 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1321 | if (i >= first + n) | |
1322 | history[i] = history[i - n]; | |
1323 | else | |
1324 | history[i] = *insn; | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1329 | ||
1330 | static void | |
1331 | emit_nop (void) | |
1332 | { | |
1333 | add_fixed_insn (NOP_INSN); | |
1334 | insert_into_history (0, 1, NOP_INSN); | |
1335 | } | |
1336 | ||
71400594 RS |
1337 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1338 | the idea is to make it obvious at a glance that each errata is | |
1339 | included. */ | |
1340 | ||
1341 | static void | |
1342 | init_vr4120_conflicts (void) | |
1343 | { | |
1344 | #define CONFLICT(FIRST, SECOND) \ | |
1345 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1346 | ||
1347 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1348 | CONFLICT (MACC, DIV); | |
1349 | CONFLICT (DMACC, DIV); | |
1350 | ||
1351 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1352 | CONFLICT (DMULT, DMULT); | |
1353 | CONFLICT (DMULT, DMACC); | |
1354 | CONFLICT (DMACC, DMULT); | |
1355 | CONFLICT (DMACC, DMACC); | |
1356 | ||
1357 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1358 | CONFLICT (MACC, MTHILO); | |
1359 | CONFLICT (DMACC, MTHILO); | |
1360 | ||
1361 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1362 | instruction is executed immediately after a MACC or DMACC | |
1363 | instruction, the result of [either instruction] is incorrect." */ | |
1364 | CONFLICT (MACC, MULT); | |
1365 | CONFLICT (MACC, DMULT); | |
1366 | CONFLICT (DMACC, MULT); | |
1367 | CONFLICT (DMACC, DMULT); | |
1368 | ||
1369 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1370 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1371 | DDIV or DDIVU instruction, the result of the MACC or | |
1372 | DMACC instruction is incorrect.". */ | |
1373 | CONFLICT (DMULT, MACC); | |
1374 | CONFLICT (DMULT, DMACC); | |
1375 | CONFLICT (DIV, MACC); | |
1376 | CONFLICT (DIV, DMACC); | |
1377 | ||
1378 | #undef CONFLICT | |
1379 | } | |
1380 | ||
156c2f8b NC |
1381 | /* This function is called once, at assembler startup time. It should |
1382 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1383 | ||
252b5132 | 1384 | void |
17a2f251 | 1385 | md_begin (void) |
252b5132 | 1386 | { |
252b5132 | 1387 | register const char *retval = NULL; |
156c2f8b | 1388 | int i = 0; |
252b5132 | 1389 | int broken = 0; |
1f25f5d3 | 1390 | |
fef14a42 | 1391 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1392 | as_warn (_("Could not set architecture and machine")); |
1393 | ||
252b5132 RH |
1394 | op_hash = hash_new (); |
1395 | ||
1396 | for (i = 0; i < NUMOPCODES;) | |
1397 | { | |
1398 | const char *name = mips_opcodes[i].name; | |
1399 | ||
17a2f251 | 1400 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1401 | if (retval != NULL) |
1402 | { | |
1403 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1404 | mips_opcodes[i].name, retval); | |
1405 | /* Probably a memory allocation problem? Give up now. */ | |
1406 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1407 | } | |
1408 | do | |
1409 | { | |
1410 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1411 | { | |
1412 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1413 | broken = 1; | |
1e915849 RS |
1414 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1415 | { | |
1416 | create_insn (&nop_insn, mips_opcodes + i); | |
1417 | nop_insn.fixed_p = 1; | |
1418 | } | |
252b5132 RH |
1419 | } |
1420 | ++i; | |
1421 | } | |
1422 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1423 | } | |
1424 | ||
1425 | mips16_op_hash = hash_new (); | |
1426 | ||
1427 | i = 0; | |
1428 | while (i < bfd_mips16_num_opcodes) | |
1429 | { | |
1430 | const char *name = mips16_opcodes[i].name; | |
1431 | ||
17a2f251 | 1432 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1433 | if (retval != NULL) |
1434 | as_fatal (_("internal: can't hash `%s': %s"), | |
1435 | mips16_opcodes[i].name, retval); | |
1436 | do | |
1437 | { | |
1438 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1439 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1440 | != mips16_opcodes[i].match)) | |
1441 | { | |
1442 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1443 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1444 | broken = 1; | |
1445 | } | |
1e915849 RS |
1446 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1447 | { | |
1448 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1449 | mips16_nop_insn.fixed_p = 1; | |
1450 | } | |
252b5132 RH |
1451 | ++i; |
1452 | } | |
1453 | while (i < bfd_mips16_num_opcodes | |
1454 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1455 | } | |
1456 | ||
1457 | if (broken) | |
1458 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1459 | ||
1460 | /* We add all the general register names to the symbol table. This | |
1461 | helps us detect invalid uses of them. */ | |
1462 | for (i = 0; i < 32; i++) | |
1463 | { | |
1464 | char buf[5]; | |
1465 | ||
1466 | sprintf (buf, "$%d", i); | |
1467 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1468 | &zero_address_frag)); | |
1469 | } | |
76db943d TS |
1470 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1471 | &zero_address_frag)); | |
252b5132 RH |
1472 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1473 | &zero_address_frag)); | |
1474 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1475 | &zero_address_frag)); | |
1476 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1477 | &zero_address_frag)); | |
1478 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1479 | &zero_address_frag)); | |
1480 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1481 | &zero_address_frag)); | |
1482 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1483 | &zero_address_frag)); | |
85b51719 TS |
1484 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1485 | &zero_address_frag)); | |
252b5132 RH |
1486 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1487 | &zero_address_frag)); | |
1488 | ||
6047c971 AO |
1489 | /* If we don't add these register names to the symbol table, they |
1490 | may end up being added as regular symbols by operand(), and then | |
1491 | make it to the object file as undefined in case they're not | |
1492 | regarded as local symbols. They're local in o32, since `$' is a | |
1493 | local symbol prefix, but not in n32 or n64. */ | |
1494 | for (i = 0; i < 8; i++) | |
1495 | { | |
1496 | char buf[6]; | |
1497 | ||
1498 | sprintf (buf, "$fcc%i", i); | |
1499 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1500 | &zero_address_frag)); | |
1501 | } | |
1502 | ||
7d10b47d | 1503 | mips_no_prev_insn (); |
252b5132 RH |
1504 | |
1505 | mips_gprmask = 0; | |
1506 | mips_cprmask[0] = 0; | |
1507 | mips_cprmask[1] = 0; | |
1508 | mips_cprmask[2] = 0; | |
1509 | mips_cprmask[3] = 0; | |
1510 | ||
1511 | /* set the default alignment for the text section (2**2) */ | |
1512 | record_alignment (text_section, 2); | |
1513 | ||
4d0d148d | 1514 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1515 | |
1516 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1517 | { | |
1518 | /* On a native system, sections must be aligned to 16 byte | |
1519 | boundaries. When configured for an embedded ELF target, we | |
1520 | don't bother. */ | |
1521 | if (strcmp (TARGET_OS, "elf") != 0) | |
1522 | { | |
1523 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1524 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1525 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1526 | } | |
1527 | ||
1528 | /* Create a .reginfo section for register masks and a .mdebug | |
1529 | section for debugging information. */ | |
1530 | { | |
1531 | segT seg; | |
1532 | subsegT subseg; | |
1533 | flagword flags; | |
1534 | segT sec; | |
1535 | ||
1536 | seg = now_seg; | |
1537 | subseg = now_subseg; | |
1538 | ||
1539 | /* The ABI says this section should be loaded so that the | |
1540 | running program can access it. However, we don't load it | |
1541 | if we are configured for an embedded target */ | |
1542 | flags = SEC_READONLY | SEC_DATA; | |
1543 | if (strcmp (TARGET_OS, "elf") != 0) | |
1544 | flags |= SEC_ALLOC | SEC_LOAD; | |
1545 | ||
316f5878 | 1546 | if (mips_abi != N64_ABI) |
252b5132 RH |
1547 | { |
1548 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1549 | ||
195325d2 TS |
1550 | bfd_set_section_flags (stdoutput, sec, flags); |
1551 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1552 | |
252b5132 RH |
1553 | #ifdef OBJ_ELF |
1554 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1555 | #endif | |
1556 | } | |
1557 | else | |
1558 | { | |
1559 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1560 | .reginfo section. */ | |
1561 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1562 | bfd_set_section_flags (stdoutput, sec, flags); |
1563 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1564 | |
1565 | #ifdef OBJ_ELF | |
1566 | /* Set up the option header. */ | |
1567 | { | |
1568 | Elf_Internal_Options opthdr; | |
1569 | char *f; | |
1570 | ||
1571 | opthdr.kind = ODK_REGINFO; | |
1572 | opthdr.size = (sizeof (Elf_External_Options) | |
1573 | + sizeof (Elf64_External_RegInfo)); | |
1574 | opthdr.section = 0; | |
1575 | opthdr.info = 0; | |
1576 | f = frag_more (sizeof (Elf_External_Options)); | |
1577 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1578 | (Elf_External_Options *) f); | |
1579 | ||
1580 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1581 | } | |
1582 | #endif | |
1583 | } | |
1584 | ||
1585 | if (ECOFF_DEBUGGING) | |
1586 | { | |
1587 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1588 | (void) bfd_set_section_flags (stdoutput, sec, | |
1589 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1590 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1591 | } | |
ecb4347a | 1592 | #ifdef OBJ_ELF |
dcd410fe | 1593 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1594 | { |
1595 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1596 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1597 | SEC_READONLY | SEC_RELOC | |
1598 | | SEC_DEBUGGING); | |
1599 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1600 | } | |
252b5132 RH |
1601 | #endif |
1602 | ||
1603 | subseg_set (seg, subseg); | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | if (! ECOFF_DEBUGGING) | |
1608 | md_obj_begin (); | |
71400594 RS |
1609 | |
1610 | if (mips_fix_vr4120) | |
1611 | init_vr4120_conflicts (); | |
252b5132 RH |
1612 | } |
1613 | ||
1614 | void | |
17a2f251 | 1615 | md_mips_end (void) |
252b5132 RH |
1616 | { |
1617 | if (! ECOFF_DEBUGGING) | |
1618 | md_obj_end (); | |
1619 | } | |
1620 | ||
1621 | void | |
17a2f251 | 1622 | md_assemble (char *str) |
252b5132 RH |
1623 | { |
1624 | struct mips_cl_insn insn; | |
f6688943 TS |
1625 | bfd_reloc_code_real_type unused_reloc[3] |
1626 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1627 | |
1628 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1629 | imm2_expr.X_op = O_absent; |
252b5132 | 1630 | offset_expr.X_op = O_absent; |
f6688943 TS |
1631 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1632 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1633 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1634 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1635 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1636 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1637 | |
1638 | if (mips_opts.mips16) | |
1639 | mips16_ip (str, &insn); | |
1640 | else | |
1641 | { | |
1642 | mips_ip (str, &insn); | |
beae10d5 KH |
1643 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1644 | str, insn.insn_opcode)); | |
252b5132 RH |
1645 | } |
1646 | ||
1647 | if (insn_error) | |
1648 | { | |
1649 | as_bad ("%s `%s'", insn_error, str); | |
1650 | return; | |
1651 | } | |
1652 | ||
1653 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1654 | { | |
584892a6 | 1655 | macro_start (); |
252b5132 RH |
1656 | if (mips_opts.mips16) |
1657 | mips16_macro (&insn); | |
1658 | else | |
1659 | macro (&insn); | |
584892a6 | 1660 | macro_end (); |
252b5132 RH |
1661 | } |
1662 | else | |
1663 | { | |
1664 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1665 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1666 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1667 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1668 | else |
4d7206a2 | 1669 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1670 | } |
1671 | } | |
1672 | ||
5919d012 RS |
1673 | /* Return true if the given relocation might need a matching %lo(). |
1674 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1675 | applied to local symbols. */ | |
1676 | ||
1677 | static inline bfd_boolean | |
17a2f251 | 1678 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1679 | { |
3b91255e RS |
1680 | return (HAVE_IN_PLACE_ADDENDS |
1681 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1682 | || reloc == BFD_RELOC_MIPS_GOT16 |
1683 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1684 | } |
1685 | ||
1686 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1687 | relocation. */ | |
1688 | ||
1689 | static inline bfd_boolean | |
17a2f251 | 1690 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1691 | { |
1692 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1693 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1694 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1695 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1696 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1697 | } | |
1698 | ||
252b5132 RH |
1699 | /* See whether instruction IP reads register REG. CLASS is the type |
1700 | of register. */ | |
1701 | ||
1702 | static int | |
71400594 | 1703 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1704 | enum mips_regclass class) |
252b5132 RH |
1705 | { |
1706 | if (class == MIPS16_REG) | |
1707 | { | |
1708 | assert (mips_opts.mips16); | |
1709 | reg = mips16_to_32_reg_map[reg]; | |
1710 | class = MIPS_GR_REG; | |
1711 | } | |
1712 | ||
85b51719 TS |
1713 | /* Don't report on general register ZERO, since it never changes. */ |
1714 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1715 | return 0; |
1716 | ||
1717 | if (class == MIPS_FP_REG) | |
1718 | { | |
1719 | assert (! mips_opts.mips16); | |
1720 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1721 | This is not optimal, because it will introduce an unnecessary | |
1722 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1723 | need to distinguish reading both $f0 and $f1 or just one of | |
1724 | them. Note that we don't have to check the other way, | |
1725 | because there is no instruction that sets both $f0 and $f1 | |
1726 | and requires a delay. */ | |
1727 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1728 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1729 | == (reg &~ (unsigned) 1))) |
1730 | return 1; | |
1731 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1732 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1733 | == (reg &~ (unsigned) 1))) |
1734 | return 1; | |
1735 | } | |
1736 | else if (! mips_opts.mips16) | |
1737 | { | |
1738 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1739 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1740 | return 1; |
1741 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1742 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1743 | return 1; |
1744 | } | |
1745 | else | |
1746 | { | |
1747 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1748 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1749 | return 1; |
1750 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1751 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1752 | return 1; |
1753 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1754 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1755 | == reg)) |
1756 | return 1; | |
1757 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1758 | return 1; | |
1759 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1760 | return 1; | |
1761 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1762 | return 1; | |
1763 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1764 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1765 | return 1; |
1766 | } | |
1767 | ||
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | /* This function returns true if modifying a register requires a | |
1772 | delay. */ | |
1773 | ||
1774 | static int | |
17a2f251 | 1775 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1776 | { |
1777 | unsigned long prev_pinfo; | |
1778 | ||
47e39b9d | 1779 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1780 | if (! mips_opts.noreorder |
81912461 ILT |
1781 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1782 | && ! gpr_interlocks) | |
1783 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1784 | && ! cop_interlocks))) | |
252b5132 | 1785 | { |
81912461 ILT |
1786 | /* A load from a coprocessor or from memory. All load delays |
1787 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1788 | /* Itbl support may require additional care here. */ |
252b5132 | 1789 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1790 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1791 | return 1; |
1792 | } | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
404a8071 RS |
1797 | /* Move all labels in insn_labels to the current insertion point. */ |
1798 | ||
1799 | static void | |
1800 | mips_move_labels (void) | |
1801 | { | |
1802 | struct insn_label_list *l; | |
1803 | valueT val; | |
1804 | ||
1805 | for (l = insn_labels; l != NULL; l = l->next) | |
1806 | { | |
1807 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1808 | symbol_set_frag (l->label, frag_now); | |
1809 | val = (valueT) frag_now_fix (); | |
1810 | /* mips16 text labels are stored as odd. */ | |
1811 | if (mips_opts.mips16) | |
1812 | ++val; | |
1813 | S_SET_VALUE (l->label, val); | |
1814 | } | |
1815 | } | |
1816 | ||
252b5132 RH |
1817 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1818 | handle them specially, such as generating jalx instructions when | |
1819 | needed. We also make them odd for the duration of the assembly, in | |
1820 | order to generate the right sort of code. We will make them even | |
1821 | in the adjust_symtab routine, while leaving them marked. This is | |
1822 | convenient for the debugger and the disassembler. The linker knows | |
1823 | to make them odd again. */ | |
1824 | ||
1825 | static void | |
17a2f251 | 1826 | mips16_mark_labels (void) |
252b5132 RH |
1827 | { |
1828 | if (mips_opts.mips16) | |
1829 | { | |
1830 | struct insn_label_list *l; | |
98aa84af | 1831 | valueT val; |
252b5132 RH |
1832 | |
1833 | for (l = insn_labels; l != NULL; l = l->next) | |
1834 | { | |
1835 | #ifdef OBJ_ELF | |
1836 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1837 | S_SET_OTHER (l->label, STO_MIPS16); | |
1838 | #endif | |
98aa84af AM |
1839 | val = S_GET_VALUE (l->label); |
1840 | if ((val & 1) == 0) | |
1841 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1842 | } |
1843 | } | |
1844 | } | |
1845 | ||
4d7206a2 RS |
1846 | /* End the current frag. Make it a variant frag and record the |
1847 | relaxation info. */ | |
1848 | ||
1849 | static void | |
1850 | relax_close_frag (void) | |
1851 | { | |
584892a6 | 1852 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1853 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1854 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1855 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1856 | ||
1857 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1858 | mips_relax.first_fixup = 0; | |
1859 | } | |
1860 | ||
1861 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1862 | See the comment above RELAX_ENCODE for more details. */ | |
1863 | ||
1864 | static void | |
1865 | relax_start (symbolS *symbol) | |
1866 | { | |
1867 | assert (mips_relax.sequence == 0); | |
1868 | mips_relax.sequence = 1; | |
1869 | mips_relax.symbol = symbol; | |
1870 | } | |
1871 | ||
1872 | /* Start generating the second version of a relaxable sequence. | |
1873 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1874 | |
1875 | static void | |
4d7206a2 RS |
1876 | relax_switch (void) |
1877 | { | |
1878 | assert (mips_relax.sequence == 1); | |
1879 | mips_relax.sequence = 2; | |
1880 | } | |
1881 | ||
1882 | /* End the current relaxable sequence. */ | |
1883 | ||
1884 | static void | |
1885 | relax_end (void) | |
1886 | { | |
1887 | assert (mips_relax.sequence == 2); | |
1888 | relax_close_frag (); | |
1889 | mips_relax.sequence = 0; | |
1890 | } | |
1891 | ||
71400594 RS |
1892 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1893 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1894 | by VR4120 errata. */ | |
4d7206a2 | 1895 | |
71400594 RS |
1896 | static unsigned int |
1897 | classify_vr4120_insn (const char *name) | |
252b5132 | 1898 | { |
71400594 RS |
1899 | if (strncmp (name, "macc", 4) == 0) |
1900 | return FIX_VR4120_MACC; | |
1901 | if (strncmp (name, "dmacc", 5) == 0) | |
1902 | return FIX_VR4120_DMACC; | |
1903 | if (strncmp (name, "mult", 4) == 0) | |
1904 | return FIX_VR4120_MULT; | |
1905 | if (strncmp (name, "dmult", 5) == 0) | |
1906 | return FIX_VR4120_DMULT; | |
1907 | if (strstr (name, "div")) | |
1908 | return FIX_VR4120_DIV; | |
1909 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1910 | return FIX_VR4120_MTHILO; | |
1911 | return NUM_FIX_VR4120_CLASSES; | |
1912 | } | |
252b5132 | 1913 | |
71400594 RS |
1914 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1915 | where INSN1 is the earlier instruction. Return the worst-case value | |
1916 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1917 | |
71400594 RS |
1918 | static unsigned int |
1919 | insns_between (const struct mips_cl_insn *insn1, | |
1920 | const struct mips_cl_insn *insn2) | |
1921 | { | |
1922 | unsigned long pinfo1, pinfo2; | |
1923 | ||
1924 | /* This function needs to know which pinfo flags are set for INSN2 | |
1925 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1926 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1927 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1928 | pinfo1 = insn1->insn_mo->pinfo; | |
1929 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1930 | |
71400594 RS |
1931 | #define INSN2_USES_REG(REG, CLASS) \ |
1932 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1933 | ||
1934 | /* For most targets, write-after-read dependencies on the HI and LO | |
1935 | registers must be separated by at least two instructions. */ | |
1936 | if (!hilo_interlocks) | |
252b5132 | 1937 | { |
71400594 RS |
1938 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1939 | return 2; | |
1940 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1941 | return 2; | |
1942 | } | |
1943 | ||
1944 | /* If we're working around r7000 errata, there must be two instructions | |
1945 | between an mfhi or mflo and any instruction that uses the result. */ | |
1946 | if (mips_7000_hilo_fix | |
1947 | && MF_HILO_INSN (pinfo1) | |
1948 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1949 | return 2; | |
1950 | ||
1951 | /* If working around VR4120 errata, check for combinations that need | |
1952 | a single intervening instruction. */ | |
1953 | if (mips_fix_vr4120) | |
1954 | { | |
1955 | unsigned int class1, class2; | |
252b5132 | 1956 | |
71400594 RS |
1957 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1958 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1959 | { |
71400594 RS |
1960 | if (insn2 == NULL) |
1961 | return 1; | |
1962 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1963 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1964 | return 1; | |
252b5132 | 1965 | } |
71400594 RS |
1966 | } |
1967 | ||
1968 | if (!mips_opts.mips16) | |
1969 | { | |
1970 | /* Check for GPR or coprocessor load delays. All such delays | |
1971 | are on the RT register. */ | |
1972 | /* Itbl support may require additional care here. */ | |
1973 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
1974 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 1975 | { |
71400594 RS |
1976 | know (pinfo1 & INSN_WRITE_GPR_T); |
1977 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
1978 | return 1; | |
1979 | } | |
1980 | ||
1981 | /* Check for generic coprocessor hazards. | |
1982 | ||
1983 | This case is not handled very well. There is no special | |
1984 | knowledge of CP0 handling, and the coprocessors other than | |
1985 | the floating point unit are not distinguished at all. */ | |
1986 | /* Itbl support may require additional care here. FIXME! | |
1987 | Need to modify this to include knowledge about | |
1988 | user specified delays! */ | |
1989 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
1990 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
1991 | { | |
1992 | /* Handle cases where INSN1 writes to a known general coprocessor | |
1993 | register. There must be a one instruction delay before INSN2 | |
1994 | if INSN2 reads that register, otherwise no delay is needed. */ | |
1995 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 1996 | { |
71400594 RS |
1997 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
1998 | return 1; | |
252b5132 | 1999 | } |
71400594 | 2000 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2001 | { |
71400594 RS |
2002 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2003 | return 1; | |
252b5132 RH |
2004 | } |
2005 | else | |
2006 | { | |
71400594 RS |
2007 | /* Read-after-write dependencies on the control registers |
2008 | require a two-instruction gap. */ | |
2009 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2010 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2011 | return 2; | |
2012 | ||
2013 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2014 | also a coprocessor instruction, assume there must be | |
2015 | a one instruction gap. */ | |
2016 | if (pinfo2 & INSN_COP) | |
2017 | return 1; | |
252b5132 RH |
2018 | } |
2019 | } | |
6b76fefe | 2020 | |
71400594 RS |
2021 | /* Check for read-after-write dependencies on the coprocessor |
2022 | control registers in cases where INSN1 does not need a general | |
2023 | coprocessor delay. This means that INSN1 is a floating point | |
2024 | comparison instruction. */ | |
2025 | /* Itbl support may require additional care here. */ | |
2026 | else if (!cop_interlocks | |
2027 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2028 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2029 | return 1; | |
2030 | } | |
6b76fefe | 2031 | |
71400594 | 2032 | #undef INSN2_USES_REG |
6b76fefe | 2033 | |
71400594 RS |
2034 | return 0; |
2035 | } | |
6b76fefe | 2036 | |
7d8e00cf RS |
2037 | /* Return the number of nops that would be needed to work around the |
2038 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2039 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2040 | ||
2041 | static int | |
2042 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2043 | const struct mips_cl_insn *insn) | |
2044 | { | |
2045 | int i, j, reg; | |
2046 | ||
2047 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2048 | are not affected by the errata. */ | |
2049 | if (insn != 0 | |
2050 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2051 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2052 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2053 | return 0; | |
2054 | ||
2055 | /* Search for the first MFLO or MFHI. */ | |
2056 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2057 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2058 | { | |
2059 | /* Extract the destination register. */ | |
2060 | if (mips_opts.mips16) | |
2061 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2062 | else | |
2063 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2064 | ||
2065 | /* No nops are needed if INSN reads that register. */ | |
2066 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2067 | return 0; | |
2068 | ||
2069 | /* ...or if any of the intervening instructions do. */ | |
2070 | for (j = 0; j < i; j++) | |
2071 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2072 | return 0; | |
2073 | ||
2074 | return MAX_VR4130_NOPS - i; | |
2075 | } | |
2076 | return 0; | |
2077 | } | |
2078 | ||
71400594 RS |
2079 | /* Return the number of nops that would be needed if instruction INSN |
2080 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2081 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2082 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2083 | |
71400594 RS |
2084 | static int |
2085 | nops_for_insn (const struct mips_cl_insn *history, | |
2086 | const struct mips_cl_insn *insn) | |
2087 | { | |
2088 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2089 | |
71400594 | 2090 | nops = 0; |
7d8e00cf | 2091 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2092 | if (!history[i].noreorder_p) |
2093 | { | |
2094 | tmp_nops = insns_between (history + i, insn) - i; | |
2095 | if (tmp_nops > nops) | |
2096 | nops = tmp_nops; | |
2097 | } | |
7d8e00cf RS |
2098 | |
2099 | if (mips_fix_vr4130) | |
2100 | { | |
2101 | tmp_nops = nops_for_vr4130 (history, insn); | |
2102 | if (tmp_nops > nops) | |
2103 | nops = tmp_nops; | |
2104 | } | |
2105 | ||
71400594 RS |
2106 | return nops; |
2107 | } | |
252b5132 | 2108 | |
71400594 RS |
2109 | /* The variable arguments provide NUM_INSNS extra instructions that |
2110 | might be added to HISTORY. Return the largest number of nops that | |
2111 | would be needed after the extended sequence. */ | |
252b5132 | 2112 | |
71400594 RS |
2113 | static int |
2114 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2115 | { | |
2116 | va_list args; | |
2117 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2118 | struct mips_cl_insn *cursor; | |
2119 | int nops; | |
2120 | ||
2121 | va_start (args, history); | |
2122 | cursor = buffer + num_insns; | |
2123 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2124 | while (cursor > buffer) | |
2125 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2126 | ||
2127 | nops = nops_for_insn (buffer, NULL); | |
2128 | va_end (args); | |
2129 | return nops; | |
2130 | } | |
252b5132 | 2131 | |
71400594 RS |
2132 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2133 | worst-case delay for the branch target. */ | |
252b5132 | 2134 | |
71400594 RS |
2135 | static int |
2136 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2137 | const struct mips_cl_insn *insn) | |
2138 | { | |
2139 | int nops, tmp_nops; | |
60b63b72 | 2140 | |
71400594 RS |
2141 | nops = nops_for_insn (history, insn); |
2142 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2143 | | INSN_COND_BRANCH_DELAY | |
2144 | | INSN_COND_BRANCH_LIKELY)) | |
2145 | { | |
2146 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2147 | if (tmp_nops > nops) | |
2148 | nops = tmp_nops; | |
2149 | } | |
2150 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2151 | { | |
2152 | tmp_nops = nops_for_sequence (1, history, insn); | |
2153 | if (tmp_nops > nops) | |
2154 | nops = tmp_nops; | |
2155 | } | |
2156 | return nops; | |
2157 | } | |
2158 | ||
2159 | /* Output an instruction. IP is the instruction information. | |
2160 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2161 | RELOC_TYPE. */ | |
2162 | ||
2163 | static void | |
2164 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2165 | bfd_reloc_code_real_type *reloc_type) | |
2166 | { | |
2167 | register unsigned long prev_pinfo, pinfo; | |
2168 | relax_stateT prev_insn_frag_type = 0; | |
2169 | bfd_boolean relaxed_branch = FALSE; | |
2170 | ||
2171 | /* Mark instruction labels in mips16 mode. */ | |
2172 | mips16_mark_labels (); | |
2173 | ||
2174 | prev_pinfo = history[0].insn_mo->pinfo; | |
2175 | pinfo = ip->insn_mo->pinfo; | |
2176 | ||
2177 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2178 | { | |
2179 | /* There are a lot of optimizations we could do that we don't. | |
2180 | In particular, we do not, in general, reorder instructions. | |
2181 | If you use gcc with optimization, it will reorder | |
2182 | instructions and generally do much more optimization then we | |
2183 | do here; repeating all that work in the assembler would only | |
2184 | benefit hand written assembly code, and does not seem worth | |
2185 | it. */ | |
2186 | int nops = (mips_optimize == 0 | |
2187 | ? nops_for_insn (history, NULL) | |
2188 | : nops_for_insn_or_target (history, ip)); | |
2189 | if (nops > 0) | |
252b5132 RH |
2190 | { |
2191 | fragS *old_frag; | |
2192 | unsigned long old_frag_offset; | |
2193 | int i; | |
252b5132 RH |
2194 | |
2195 | old_frag = frag_now; | |
2196 | old_frag_offset = frag_now_fix (); | |
2197 | ||
2198 | for (i = 0; i < nops; i++) | |
2199 | emit_nop (); | |
2200 | ||
2201 | if (listing) | |
2202 | { | |
2203 | listing_prev_line (); | |
2204 | /* We may be at the start of a variant frag. In case we | |
2205 | are, make sure there is enough space for the frag | |
2206 | after the frags created by listing_prev_line. The | |
2207 | argument to frag_grow here must be at least as large | |
2208 | as the argument to all other calls to frag_grow in | |
2209 | this file. We don't have to worry about being in the | |
2210 | middle of a variant frag, because the variants insert | |
2211 | all needed nop instructions themselves. */ | |
2212 | frag_grow (40); | |
2213 | } | |
2214 | ||
404a8071 | 2215 | mips_move_labels (); |
252b5132 RH |
2216 | |
2217 | #ifndef NO_ECOFF_DEBUGGING | |
2218 | if (ECOFF_DEBUGGING) | |
2219 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2220 | #endif | |
2221 | } | |
71400594 RS |
2222 | } |
2223 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2224 | { | |
2225 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2226 | int nops = nops_for_insn_or_target (history, ip); | |
2227 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2228 | |
71400594 RS |
2229 | /* Enforce NOPS as a minimum. */ |
2230 | if (nops > prev_nop_frag_required) | |
2231 | prev_nop_frag_required = nops; | |
252b5132 | 2232 | |
71400594 RS |
2233 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2234 | { | |
2235 | /* Settle for the current number of nops. Update the history | |
2236 | accordingly (for the benefit of any future .set reorder code). */ | |
2237 | prev_nop_frag = NULL; | |
2238 | insert_into_history (prev_nop_frag_since, | |
2239 | prev_nop_frag_holds, NOP_INSN); | |
2240 | } | |
2241 | else | |
2242 | { | |
2243 | /* Allow this instruction to replace one of the nops that was | |
2244 | tentatively added to prev_nop_frag. */ | |
2245 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2246 | prev_nop_frag_holds--; | |
2247 | prev_nop_frag_since++; | |
252b5132 RH |
2248 | } |
2249 | } | |
2250 | ||
58e2ea4d MR |
2251 | #ifdef OBJ_ELF |
2252 | /* The value passed to dwarf2_emit_insn is the distance between | |
2253 | the beginning of the current instruction and the address that | |
2254 | should be recorded in the debug tables. For MIPS16 debug info | |
2255 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2256 | address higher by one than the current. */ | |
2257 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2258 | #endif | |
2259 | ||
895921c9 | 2260 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2261 | if (history[0].frag) |
2262 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2263 | |
4d7206a2 | 2264 | if (address_expr |
0b25d3e6 | 2265 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2266 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2267 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2268 | && mips_relax_branch | |
2269 | /* Don't try branch relaxation within .set nomacro, or within | |
2270 | .set noat if we use $at for PIC computations. If it turns | |
2271 | out that the branch was out-of-range, we'll get an error. */ | |
2272 | && !mips_opts.warn_about_macros | |
2273 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2274 | && !mips_opts.mips16) | |
2275 | { | |
895921c9 | 2276 | relaxed_branch = TRUE; |
1e915849 RS |
2277 | add_relaxed_insn (ip, (relaxed_branch_length |
2278 | (NULL, NULL, | |
2279 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2280 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2281 | : 0)), 4, | |
2282 | RELAX_BRANCH_ENCODE | |
2283 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2284 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2285 | pinfo & INSN_WRITE_GPR_31, | |
2286 | 0), | |
2287 | address_expr->X_add_symbol, | |
2288 | address_expr->X_add_number); | |
4a6a3df4 AO |
2289 | *reloc_type = BFD_RELOC_UNUSED; |
2290 | } | |
2291 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2292 | { |
2293 | /* We need to set up a variant frag. */ | |
2294 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2295 | add_relaxed_insn (ip, 4, 0, |
2296 | RELAX_MIPS16_ENCODE | |
2297 | (*reloc_type - BFD_RELOC_UNUSED, | |
2298 | mips16_small, mips16_ext, | |
2299 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2300 | history[0].mips16_absolute_jump_p), | |
2301 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2302 | } |
252b5132 RH |
2303 | else if (mips_opts.mips16 |
2304 | && ! ip->use_extend | |
f6688943 | 2305 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2306 | { |
2307 | /* Make sure there is enough room to swap this instruction with | |
2308 | a following jump instruction. */ | |
2309 | frag_grow (6); | |
1e915849 | 2310 | add_fixed_insn (ip); |
252b5132 RH |
2311 | } |
2312 | else | |
2313 | { | |
2314 | if (mips_opts.mips16 | |
2315 | && mips_opts.noreorder | |
2316 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2317 | as_warn (_("extended instruction in delay slot")); | |
2318 | ||
4d7206a2 RS |
2319 | if (mips_relax.sequence) |
2320 | { | |
2321 | /* If we've reached the end of this frag, turn it into a variant | |
2322 | frag and record the information for the instructions we've | |
2323 | written so far. */ | |
2324 | if (frag_room () < 4) | |
2325 | relax_close_frag (); | |
2326 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2327 | } | |
2328 | ||
584892a6 RS |
2329 | if (mips_relax.sequence != 2) |
2330 | mips_macro_warning.sizes[0] += 4; | |
2331 | if (mips_relax.sequence != 1) | |
2332 | mips_macro_warning.sizes[1] += 4; | |
2333 | ||
1e915849 RS |
2334 | if (mips_opts.mips16) |
2335 | { | |
2336 | ip->fixed_p = 1; | |
2337 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2338 | } | |
2339 | add_fixed_insn (ip); | |
252b5132 RH |
2340 | } |
2341 | ||
01a3f561 | 2342 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2343 | { |
2344 | if (address_expr->X_op == O_constant) | |
2345 | { | |
f17c130b | 2346 | unsigned int tmp; |
f6688943 TS |
2347 | |
2348 | switch (*reloc_type) | |
252b5132 RH |
2349 | { |
2350 | case BFD_RELOC_32: | |
2351 | ip->insn_opcode |= address_expr->X_add_number; | |
2352 | break; | |
2353 | ||
f6688943 | 2354 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2355 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2356 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2357 | break; |
2358 | ||
2359 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2360 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2361 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2362 | break; |
2363 | ||
2364 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2365 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2366 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2367 | break; |
2368 | ||
2369 | case BFD_RELOC_HI16: | |
2370 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2371 | break; | |
2372 | ||
01a3f561 | 2373 | case BFD_RELOC_UNUSED: |
252b5132 | 2374 | case BFD_RELOC_LO16: |
ed6fb7bd | 2375 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2376 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2377 | break; | |
2378 | ||
2379 | case BFD_RELOC_MIPS_JMP: | |
2380 | if ((address_expr->X_add_number & 3) != 0) | |
2381 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2382 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2383 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2384 | as_bad (_("jump address range overflow (0x%lx)"), |
2385 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2386 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2387 | break; | |
2388 | ||
2389 | case BFD_RELOC_MIPS16_JMP: | |
2390 | if ((address_expr->X_add_number & 3) != 0) | |
2391 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2392 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2393 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2394 | as_bad (_("jump address range overflow (0x%lx)"), |
2395 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2396 | ip->insn_opcode |= |
2397 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2398 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2399 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2400 | break; | |
2401 | ||
252b5132 RH |
2402 | case BFD_RELOC_16_PCREL_S2: |
2403 | goto need_reloc; | |
2404 | ||
2405 | default: | |
2406 | internalError (); | |
2407 | } | |
2408 | } | |
01a3f561 | 2409 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2410 | need_reloc: |
4d7206a2 RS |
2411 | { |
2412 | reloc_howto_type *howto; | |
2413 | int i; | |
34ce925e | 2414 | |
4d7206a2 RS |
2415 | /* In a compound relocation, it is the final (outermost) |
2416 | operator that determines the relocated field. */ | |
2417 | for (i = 1; i < 3; i++) | |
2418 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2419 | break; | |
34ce925e | 2420 | |
4d7206a2 | 2421 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2422 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2423 | bfd_get_reloc_size (howto), | |
2424 | address_expr, | |
2425 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2426 | reloc_type[0]); | |
4d7206a2 RS |
2427 | |
2428 | /* These relocations can have an addend that won't fit in | |
2429 | 4 octets for 64bit assembly. */ | |
2430 | if (HAVE_64BIT_GPRS | |
2431 | && ! howto->partial_inplace | |
2432 | && (reloc_type[0] == BFD_RELOC_16 | |
2433 | || reloc_type[0] == BFD_RELOC_32 | |
2434 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2435 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2436 | || reloc_type[0] == BFD_RELOC_LO16 | |
2437 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2438 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2439 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2440 | || reloc_type[0] == BFD_RELOC_64 | |
2441 | || reloc_type[0] == BFD_RELOC_CTOR | |
2442 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2443 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2444 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2445 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2446 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2447 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2448 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2449 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2450 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2451 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2452 | |
2453 | if (mips_relax.sequence) | |
2454 | { | |
2455 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2456 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2457 | } |
2458 | else if (reloc_needs_lo_p (*reloc_type)) | |
2459 | { | |
2460 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2461 | |
4d7206a2 RS |
2462 | /* Reuse the last entry if it already has a matching %lo. */ |
2463 | hi_fixup = mips_hi_fixup_list; | |
2464 | if (hi_fixup == 0 | |
2465 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2466 | { | |
2467 | hi_fixup = ((struct mips_hi_fixup *) | |
2468 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2469 | hi_fixup->next = mips_hi_fixup_list; | |
2470 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2471 | } |
1e915849 | 2472 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2473 | hi_fixup->seg = now_seg; |
2474 | } | |
f6688943 | 2475 | |
4d7206a2 RS |
2476 | /* Add fixups for the second and third relocations, if given. |
2477 | Note that the ABI allows the second relocation to be | |
2478 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2479 | moment we only use RSS_UNDEF, but we could add support | |
2480 | for the others if it ever becomes necessary. */ | |
2481 | for (i = 1; i < 3; i++) | |
2482 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2483 | { | |
1e915849 RS |
2484 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2485 | ip->fixp[0]->fx_size, NULL, 0, | |
2486 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2487 | |
2488 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2489 | ip->fixp[0]->fx_tcbit = 1; |
2490 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2491 | } |
252b5132 RH |
2492 | } |
2493 | } | |
1e915849 | 2494 | install_insn (ip); |
252b5132 RH |
2495 | |
2496 | /* Update the register mask information. */ | |
2497 | if (! mips_opts.mips16) | |
2498 | { | |
2499 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2500 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2501 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2502 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2503 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2504 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2505 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2506 | mips_gprmask |= 1 << RA; |
252b5132 | 2507 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2508 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2509 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2510 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2511 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2512 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2513 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2514 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2515 | if (pinfo & INSN_COP) |
2516 | { | |
bdaaa2e1 KH |
2517 | /* We don't keep enough information to sort these cases out. |
2518 | The itbl support does keep this information however, although | |
2519 | we currently don't support itbl fprmats as part of the cop | |
2520 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2521 | } |
2522 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2523 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2524 | } |
2525 | else | |
2526 | { | |
2527 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2528 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2529 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2530 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2531 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2532 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2533 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2534 | mips_gprmask |= 1 << TREG; | |
2535 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2536 | mips_gprmask |= 1 << SP; | |
2537 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2538 | mips_gprmask |= 1 << RA; | |
2539 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2540 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2541 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2542 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2543 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2544 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2545 | } |
2546 | ||
4d7206a2 | 2547 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2548 | { |
2549 | /* Filling the branch delay slot is more complex. We try to | |
2550 | switch the branch with the previous instruction, which we can | |
2551 | do if the previous instruction does not set up a condition | |
2552 | that the branch tests and if the branch is not itself the | |
2553 | target of any branch. */ | |
2554 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2555 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2556 | { | |
2557 | if (mips_optimize < 2 | |
2558 | /* If we have seen .set volatile or .set nomove, don't | |
2559 | optimize. */ | |
2560 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2561 | /* We can't swap if the previous instruction's position |
2562 | is fixed. */ | |
2563 | || history[0].fixed_p | |
252b5132 RH |
2564 | /* If the previous previous insn was in a .set |
2565 | noreorder, we can't swap. Actually, the MIPS | |
2566 | assembler will swap in this situation. However, gcc | |
2567 | configured -with-gnu-as will generate code like | |
2568 | .set noreorder | |
2569 | lw $4,XXX | |
2570 | .set reorder | |
2571 | INSN | |
2572 | bne $4,$0,foo | |
2573 | in which we can not swap the bne and INSN. If gcc is | |
2574 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2575 | .set pseudo-ops. */ |
47e39b9d | 2576 | || history[1].noreorder_p |
252b5132 RH |
2577 | /* If the branch is itself the target of a branch, we |
2578 | can not swap. We cheat on this; all we check for is | |
2579 | whether there is a label on this instruction. If | |
2580 | there are any branches to anything other than a | |
2581 | label, users must use .set noreorder. */ | |
2582 | || insn_labels != NULL | |
895921c9 MR |
2583 | /* If the previous instruction is in a variant frag |
2584 | other than this branch's one, we cannot do the swap. | |
2585 | This does not apply to the mips16, which uses variant | |
2586 | frags for different purposes. */ | |
252b5132 | 2587 | || (! mips_opts.mips16 |
895921c9 | 2588 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2589 | /* Check for conflicts between the branch and the instructions |
2590 | before the candidate delay slot. */ | |
2591 | || nops_for_insn (history + 1, ip) > 0 | |
2592 | /* Check for conflicts between the swapped sequence and the | |
2593 | target of the branch. */ | |
2594 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2595 | /* We do not swap with a trap instruction, since it |
2596 | complicates trap handlers to have the trap | |
2597 | instruction be in a delay slot. */ | |
2598 | || (prev_pinfo & INSN_TRAP) | |
2599 | /* If the branch reads a register that the previous | |
2600 | instruction sets, we can not swap. */ | |
2601 | || (! mips_opts.mips16 | |
2602 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2603 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2604 | MIPS_GR_REG)) |
2605 | || (! mips_opts.mips16 | |
2606 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2607 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2608 | MIPS_GR_REG)) |
2609 | || (mips_opts.mips16 | |
2610 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2611 | && (insn_uses_reg |
2612 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2613 | MIPS16_REG))) | |
252b5132 | 2614 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2615 | && (insn_uses_reg |
2616 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2617 | MIPS16_REG))) | |
252b5132 | 2618 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2619 | && (insn_uses_reg |
2620 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2621 | MIPS16_REG))) | |
252b5132 RH |
2622 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2623 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2624 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2625 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2626 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2627 | && insn_uses_reg (ip, | |
47e39b9d RS |
2628 | MIPS16OP_EXTRACT_REG32R |
2629 | (history[0].insn_opcode), | |
252b5132 RH |
2630 | MIPS_GR_REG)))) |
2631 | /* If the branch writes a register that the previous | |
2632 | instruction sets, we can not swap (we know that | |
2633 | branches write only to RD or to $31). */ | |
2634 | || (! mips_opts.mips16 | |
2635 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2636 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2637 | && (EXTRACT_OPERAND (RT, history[0]) |
2638 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2639 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2640 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2641 | || (! mips_opts.mips16 |
2642 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2643 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2644 | && (EXTRACT_OPERAND (RD, history[0]) |
2645 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2646 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2647 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2648 | || (mips_opts.mips16 |
2649 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2650 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2651 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2652 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2653 | == RA)))) |
2654 | /* If the branch writes a register that the previous | |
2655 | instruction reads, we can not swap (we know that | |
2656 | branches only write to RD or to $31). */ | |
2657 | || (! mips_opts.mips16 | |
2658 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2659 | && insn_uses_reg (&history[0], |
bf12938e | 2660 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2661 | MIPS_GR_REG)) |
2662 | || (! mips_opts.mips16 | |
2663 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2664 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2665 | || (mips_opts.mips16 |
2666 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2667 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2668 | /* If one instruction sets a condition code and the |
2669 | other one uses a condition code, we can not swap. */ | |
2670 | || ((pinfo & INSN_READ_COND_CODE) | |
2671 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2672 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2673 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2674 | /* If the previous instruction uses the PC, we can not | |
2675 | swap. */ | |
2676 | || (mips_opts.mips16 | |
2677 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2678 | /* If the previous instruction had a fixup in mips16 |
2679 | mode, we can not swap. This normally means that the | |
2680 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2681 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2682 | /* If the previous instruction is a sync, sync.l, or |
2683 | sync.p, we can not swap. */ | |
f173e82e | 2684 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2685 | { |
2686 | /* We could do even better for unconditional branches to | |
2687 | portions of this object file; we could pick up the | |
2688 | instruction at the destination, put it in the delay | |
2689 | slot, and bump the destination address. */ | |
1e915849 | 2690 | insert_into_history (0, 1, ip); |
252b5132 | 2691 | emit_nop (); |
dd22970f ILT |
2692 | if (mips_relax.sequence) |
2693 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2694 | } |
2695 | else | |
2696 | { | |
2697 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2698 | struct mips_cl_insn delay = history[0]; |
2699 | if (mips_opts.mips16) | |
252b5132 | 2700 | { |
1e915849 RS |
2701 | know (delay.frag == ip->frag); |
2702 | move_insn (ip, delay.frag, delay.where); | |
2703 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
2704 | } | |
2705 | else if (relaxed_branch) | |
2706 | { | |
2707 | /* Add the delay slot instruction to the end of the | |
2708 | current frag and shrink the fixed part of the | |
2709 | original frag. If the branch occupies the tail of | |
2710 | the latter, move it backwards to cover the gap. */ | |
2711 | delay.frag->fr_fix -= 4; | |
2712 | if (delay.frag == ip->frag) | |
2713 | move_insn (ip, ip->frag, ip->where - 4); | |
2714 | add_fixed_insn (&delay); | |
252b5132 RH |
2715 | } |
2716 | else | |
2717 | { | |
1e915849 RS |
2718 | move_insn (&delay, ip->frag, ip->where); |
2719 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2720 | } |
1e915849 RS |
2721 | history[0] = *ip; |
2722 | delay.fixed_p = 1; | |
2723 | insert_into_history (0, 1, &delay); | |
252b5132 | 2724 | } |
252b5132 RH |
2725 | |
2726 | /* If that was an unconditional branch, forget the previous | |
2727 | insn information. */ | |
2728 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2729 | mips_no_prev_insn (); |
252b5132 RH |
2730 | } |
2731 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2732 | { | |
2733 | /* We don't yet optimize a branch likely. What we should do | |
2734 | is look at the target, copy the instruction found there | |
2735 | into the delay slot, and increment the branch to jump to | |
2736 | the next instruction. */ | |
1e915849 | 2737 | insert_into_history (0, 1, ip); |
252b5132 | 2738 | emit_nop (); |
252b5132 RH |
2739 | } |
2740 | else | |
1e915849 | 2741 | insert_into_history (0, 1, ip); |
252b5132 | 2742 | } |
1e915849 RS |
2743 | else |
2744 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2745 | |
2746 | /* We just output an insn, so the next one doesn't have a label. */ | |
2747 | mips_clear_insn_labels (); | |
252b5132 RH |
2748 | } |
2749 | ||
7d10b47d | 2750 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2751 | |
2752 | static void | |
7d10b47d | 2753 | mips_no_prev_insn (void) |
252b5132 | 2754 | { |
7d10b47d RS |
2755 | prev_nop_frag = NULL; |
2756 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2757 | mips_clear_insn_labels (); |
2758 | } | |
2759 | ||
7d10b47d RS |
2760 | /* This function must be called before we emit something other than |
2761 | instructions. It is like mips_no_prev_insn except that it inserts | |
2762 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2763 | |
7d10b47d RS |
2764 | void |
2765 | mips_emit_delays (void) | |
252b5132 RH |
2766 | { |
2767 | if (! mips_opts.noreorder) | |
2768 | { | |
71400594 | 2769 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2770 | if (nops > 0) |
2771 | { | |
7d10b47d RS |
2772 | while (nops-- > 0) |
2773 | add_fixed_insn (NOP_INSN); | |
2774 | mips_move_labels (); | |
2775 | } | |
2776 | } | |
2777 | mips_no_prev_insn (); | |
2778 | } | |
2779 | ||
2780 | /* Start a (possibly nested) noreorder block. */ | |
2781 | ||
2782 | static void | |
2783 | start_noreorder (void) | |
2784 | { | |
2785 | if (mips_opts.noreorder == 0) | |
2786 | { | |
2787 | unsigned int i; | |
2788 | int nops; | |
2789 | ||
2790 | /* None of the instructions before the .set noreorder can be moved. */ | |
2791 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2792 | history[i].fixed_p = 1; | |
2793 | ||
2794 | /* Insert any nops that might be needed between the .set noreorder | |
2795 | block and the previous instructions. We will later remove any | |
2796 | nops that turn out not to be needed. */ | |
2797 | nops = nops_for_insn (history, NULL); | |
2798 | if (nops > 0) | |
2799 | { | |
2800 | if (mips_optimize != 0) | |
252b5132 RH |
2801 | { |
2802 | /* Record the frag which holds the nop instructions, so | |
2803 | that we can remove them if we don't need them. */ | |
2804 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2805 | prev_nop_frag = frag_now; | |
2806 | prev_nop_frag_holds = nops; | |
2807 | prev_nop_frag_required = 0; | |
2808 | prev_nop_frag_since = 0; | |
2809 | } | |
2810 | ||
2811 | for (; nops > 0; --nops) | |
1e915849 | 2812 | add_fixed_insn (NOP_INSN); |
252b5132 | 2813 | |
7d10b47d RS |
2814 | /* Move on to a new frag, so that it is safe to simply |
2815 | decrease the size of prev_nop_frag. */ | |
2816 | frag_wane (frag_now); | |
2817 | frag_new (0); | |
404a8071 | 2818 | mips_move_labels (); |
252b5132 | 2819 | } |
7d10b47d RS |
2820 | mips16_mark_labels (); |
2821 | mips_clear_insn_labels (); | |
252b5132 | 2822 | } |
7d10b47d RS |
2823 | mips_opts.noreorder++; |
2824 | mips_any_noreorder = 1; | |
2825 | } | |
252b5132 | 2826 | |
7d10b47d | 2827 | /* End a nested noreorder block. */ |
252b5132 | 2828 | |
7d10b47d RS |
2829 | static void |
2830 | end_noreorder (void) | |
2831 | { | |
2832 | mips_opts.noreorder--; | |
2833 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2834 | { | |
2835 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2836 | handling nop insertion the .set reorder way. */ | |
2837 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2838 | * (mips_opts.mips16 ? 2 : 4)); | |
2839 | insert_into_history (prev_nop_frag_since, | |
2840 | prev_nop_frag_required, NOP_INSN); | |
2841 | prev_nop_frag = NULL; | |
2842 | } | |
252b5132 RH |
2843 | } |
2844 | ||
584892a6 RS |
2845 | /* Set up global variables for the start of a new macro. */ |
2846 | ||
2847 | static void | |
2848 | macro_start (void) | |
2849 | { | |
2850 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2851 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2852 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2853 | & (INSN_UNCOND_BRANCH_DELAY |
2854 | | INSN_COND_BRANCH_DELAY | |
2855 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2856 | } | |
2857 | ||
2858 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2859 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2860 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2861 | ||
2862 | static const char * | |
2863 | macro_warning (relax_substateT subtype) | |
2864 | { | |
2865 | if (subtype & RELAX_DELAY_SLOT) | |
2866 | return _("Macro instruction expanded into multiple instructions" | |
2867 | " in a branch delay slot"); | |
2868 | else if (subtype & RELAX_NOMACRO) | |
2869 | return _("Macro instruction expanded into multiple instructions"); | |
2870 | else | |
2871 | return 0; | |
2872 | } | |
2873 | ||
2874 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2875 | ||
2876 | static void | |
2877 | macro_end (void) | |
2878 | { | |
2879 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2880 | { | |
2881 | relax_substateT subtype; | |
2882 | ||
2883 | /* Set up the relaxation warning flags. */ | |
2884 | subtype = 0; | |
2885 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2886 | subtype |= RELAX_SECOND_LONGER; | |
2887 | if (mips_opts.warn_about_macros) | |
2888 | subtype |= RELAX_NOMACRO; | |
2889 | if (mips_macro_warning.delay_slot_p) | |
2890 | subtype |= RELAX_DELAY_SLOT; | |
2891 | ||
2892 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2893 | { | |
2894 | /* Either the macro has a single implementation or both | |
2895 | implementations are longer than 4 bytes. Emit the | |
2896 | warning now. */ | |
2897 | const char *msg = macro_warning (subtype); | |
2898 | if (msg != 0) | |
2899 | as_warn (msg); | |
2900 | } | |
2901 | else | |
2902 | { | |
2903 | /* One implementation might need a warning but the other | |
2904 | definitely doesn't. */ | |
2905 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2906 | } | |
2907 | } | |
2908 | } | |
2909 | ||
6e1304d8 RS |
2910 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2911 | The first argument in *ARGS will be either the code for a single | |
2912 | relocation or -1 followed by the three codes that make up a | |
2913 | composite relocation. */ | |
2914 | ||
2915 | static void | |
2916 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2917 | { | |
2918 | int i, next; | |
2919 | ||
2920 | next = va_arg (*args, int); | |
2921 | if (next >= 0) | |
2922 | r[0] = (bfd_reloc_code_real_type) next; | |
2923 | else | |
2924 | for (i = 0; i < 3; i++) | |
2925 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2926 | } | |
2927 | ||
252b5132 RH |
2928 | /* Build an instruction created by a macro expansion. This is passed |
2929 | a pointer to the count of instructions created so far, an | |
2930 | expression, the name of the instruction to build, an operand format | |
2931 | string, and corresponding arguments. */ | |
2932 | ||
252b5132 | 2933 | static void |
67c0d1eb | 2934 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2935 | { |
1e915849 | 2936 | const struct mips_opcode *mo; |
252b5132 | 2937 | struct mips_cl_insn insn; |
f6688943 | 2938 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2939 | va_list args; |
252b5132 | 2940 | |
252b5132 | 2941 | va_start (args, fmt); |
252b5132 | 2942 | |
252b5132 RH |
2943 | if (mips_opts.mips16) |
2944 | { | |
67c0d1eb | 2945 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2946 | va_end (args); |
2947 | return; | |
2948 | } | |
2949 | ||
f6688943 TS |
2950 | r[0] = BFD_RELOC_UNUSED; |
2951 | r[1] = BFD_RELOC_UNUSED; | |
2952 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2953 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2954 | assert (mo); | |
2955 | assert (strcmp (name, mo->name) == 0); | |
2956 | ||
2957 | /* Search until we get a match for NAME. It is assumed here that | |
2958 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2959 | while (strcmp (fmt, mo->args) != 0 | |
2960 | || mo->pinfo == INSN_MACRO | |
2961 | || !OPCODE_IS_MEMBER (mo, | |
2962 | (mips_opts.isa | |
2963 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2964 | mips_opts.arch) |
1e915849 RS |
2965 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2966 | { | |
2967 | ++mo; | |
2968 | assert (mo->name); | |
2969 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2970 | } |
2971 | ||
1e915849 | 2972 | create_insn (&insn, mo); |
252b5132 RH |
2973 | for (;;) |
2974 | { | |
2975 | switch (*fmt++) | |
2976 | { | |
2977 | case '\0': | |
2978 | break; | |
2979 | ||
2980 | case ',': | |
2981 | case '(': | |
2982 | case ')': | |
2983 | continue; | |
2984 | ||
5f74bc13 CD |
2985 | case '+': |
2986 | switch (*fmt++) | |
2987 | { | |
2988 | case 'A': | |
2989 | case 'E': | |
bf12938e | 2990 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
2991 | continue; |
2992 | ||
2993 | case 'B': | |
2994 | case 'F': | |
2995 | /* Note that in the macro case, these arguments are already | |
2996 | in MSB form. (When handling the instruction in the | |
2997 | non-macro case, these arguments are sizes from which | |
2998 | MSB values must be calculated.) */ | |
bf12938e | 2999 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3000 | continue; |
3001 | ||
3002 | case 'C': | |
3003 | case 'G': | |
3004 | case 'H': | |
3005 | /* Note that in the macro case, these arguments are already | |
3006 | in MSBD form. (When handling the instruction in the | |
3007 | non-macro case, these arguments are sizes from which | |
3008 | MSBD values must be calculated.) */ | |
bf12938e | 3009 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3010 | continue; |
3011 | ||
3012 | default: | |
3013 | internalError (); | |
3014 | } | |
3015 | continue; | |
3016 | ||
252b5132 RH |
3017 | case 't': |
3018 | case 'w': | |
3019 | case 'E': | |
bf12938e | 3020 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3021 | continue; |
3022 | ||
3023 | case 'c': | |
bf12938e | 3024 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3025 | continue; |
3026 | ||
252b5132 RH |
3027 | case 'T': |
3028 | case 'W': | |
bf12938e | 3029 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3030 | continue; |
3031 | ||
3032 | case 'd': | |
3033 | case 'G': | |
af7ee8bf | 3034 | case 'K': |
bf12938e | 3035 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3036 | continue; |
3037 | ||
4372b673 NC |
3038 | case 'U': |
3039 | { | |
3040 | int tmp = va_arg (args, int); | |
3041 | ||
bf12938e RS |
3042 | INSERT_OPERAND (RT, insn, tmp); |
3043 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3044 | continue; |
4372b673 NC |
3045 | } |
3046 | ||
252b5132 RH |
3047 | case 'V': |
3048 | case 'S': | |
bf12938e | 3049 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3050 | continue; |
3051 | ||
3052 | case 'z': | |
3053 | continue; | |
3054 | ||
3055 | case '<': | |
bf12938e | 3056 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3057 | continue; |
3058 | ||
3059 | case 'D': | |
bf12938e | 3060 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3061 | continue; |
3062 | ||
3063 | case 'B': | |
bf12938e | 3064 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3065 | continue; |
3066 | ||
4372b673 | 3067 | case 'J': |
bf12938e | 3068 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3069 | continue; |
3070 | ||
252b5132 | 3071 | case 'q': |
bf12938e | 3072 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3073 | continue; |
3074 | ||
3075 | case 'b': | |
3076 | case 's': | |
3077 | case 'r': | |
3078 | case 'v': | |
bf12938e | 3079 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3080 | continue; |
3081 | ||
3082 | case 'i': | |
3083 | case 'j': | |
3084 | case 'o': | |
6e1304d8 | 3085 | macro_read_relocs (&args, r); |
cdf6fd85 | 3086 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3087 | || *r == BFD_RELOC_MIPS_LITERAL |
3088 | || *r == BFD_RELOC_MIPS_HIGHER | |
3089 | || *r == BFD_RELOC_HI16_S | |
3090 | || *r == BFD_RELOC_LO16 | |
3091 | || *r == BFD_RELOC_MIPS_GOT16 | |
3092 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3093 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3094 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3095 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3096 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3097 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3098 | continue; |
3099 | ||
3100 | case 'u': | |
6e1304d8 | 3101 | macro_read_relocs (&args, r); |
252b5132 RH |
3102 | assert (ep != NULL |
3103 | && (ep->X_op == O_constant | |
3104 | || (ep->X_op == O_symbol | |
f6688943 TS |
3105 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3106 | || *r == BFD_RELOC_HI16_S | |
3107 | || *r == BFD_RELOC_HI16 | |
3108 | || *r == BFD_RELOC_GPREL16 | |
3109 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3110 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3111 | continue; |
3112 | ||
3113 | case 'p': | |
3114 | assert (ep != NULL); | |
3115 | /* | |
3116 | * This allows macro() to pass an immediate expression for | |
3117 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3118 | * Note that the expression still might come from the assembly |
3119 | * input, in which case the value is not checked for range nor | |
3120 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3121 | */ |
3122 | if (ep->X_op == O_constant) | |
3123 | { | |
3124 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3125 | ep = NULL; | |
3126 | } | |
3127 | else | |
0b25d3e6 | 3128 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3129 | continue; |
3130 | ||
3131 | case 'a': | |
3132 | assert (ep != NULL); | |
f6688943 | 3133 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3134 | continue; |
3135 | ||
3136 | case 'C': | |
3137 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3138 | continue; | |
3139 | ||
3140 | default: | |
3141 | internalError (); | |
3142 | } | |
3143 | break; | |
3144 | } | |
3145 | va_end (args); | |
f6688943 | 3146 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3147 | |
4d7206a2 | 3148 | append_insn (&insn, ep, r); |
252b5132 RH |
3149 | } |
3150 | ||
3151 | static void | |
67c0d1eb | 3152 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3153 | va_list args) |
252b5132 | 3154 | { |
1e915849 | 3155 | struct mips_opcode *mo; |
252b5132 | 3156 | struct mips_cl_insn insn; |
f6688943 TS |
3157 | bfd_reloc_code_real_type r[3] |
3158 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3159 | |
1e915849 RS |
3160 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3161 | assert (mo); | |
3162 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3163 | |
1e915849 | 3164 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3165 | { |
1e915849 RS |
3166 | ++mo; |
3167 | assert (mo->name); | |
3168 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3169 | } |
3170 | ||
1e915849 | 3171 | create_insn (&insn, mo); |
252b5132 RH |
3172 | for (;;) |
3173 | { | |
3174 | int c; | |
3175 | ||
3176 | c = *fmt++; | |
3177 | switch (c) | |
3178 | { | |
3179 | case '\0': | |
3180 | break; | |
3181 | ||
3182 | case ',': | |
3183 | case '(': | |
3184 | case ')': | |
3185 | continue; | |
3186 | ||
3187 | case 'y': | |
3188 | case 'w': | |
bf12938e | 3189 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3190 | continue; |
3191 | ||
3192 | case 'x': | |
3193 | case 'v': | |
bf12938e | 3194 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3195 | continue; |
3196 | ||
3197 | case 'z': | |
bf12938e | 3198 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3199 | continue; |
3200 | ||
3201 | case 'Z': | |
bf12938e | 3202 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3203 | continue; |
3204 | ||
3205 | case '0': | |
3206 | case 'S': | |
3207 | case 'P': | |
3208 | case 'R': | |
3209 | continue; | |
3210 | ||
3211 | case 'X': | |
bf12938e | 3212 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3213 | continue; |
3214 | ||
3215 | case 'Y': | |
3216 | { | |
3217 | int regno; | |
3218 | ||
3219 | regno = va_arg (args, int); | |
3220 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3221 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3222 | } | |
3223 | continue; | |
3224 | ||
3225 | case '<': | |
3226 | case '>': | |
3227 | case '4': | |
3228 | case '5': | |
3229 | case 'H': | |
3230 | case 'W': | |
3231 | case 'D': | |
3232 | case 'j': | |
3233 | case '8': | |
3234 | case 'V': | |
3235 | case 'C': | |
3236 | case 'U': | |
3237 | case 'k': | |
3238 | case 'K': | |
3239 | case 'p': | |
3240 | case 'q': | |
3241 | { | |
3242 | assert (ep != NULL); | |
3243 | ||
3244 | if (ep->X_op != O_constant) | |
874e8986 | 3245 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3246 | else |
3247 | { | |
b34976b6 AM |
3248 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3249 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3250 | &insn.extend); |
252b5132 | 3251 | ep = NULL; |
f6688943 | 3252 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3253 | } |
3254 | } | |
3255 | continue; | |
3256 | ||
3257 | case '6': | |
bf12938e | 3258 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3259 | continue; |
3260 | } | |
3261 | ||
3262 | break; | |
3263 | } | |
3264 | ||
f6688943 | 3265 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3266 | |
4d7206a2 | 3267 | append_insn (&insn, ep, r); |
252b5132 RH |
3268 | } |
3269 | ||
2051e8c4 MR |
3270 | /* |
3271 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3272 | * higher bits unset. | |
3273 | */ | |
9f872bbe | 3274 | static void |
2051e8c4 MR |
3275 | normalize_constant_expr (expressionS *ex) |
3276 | { | |
9ee2a2d4 | 3277 | if (ex->X_op == O_constant |
2051e8c4 MR |
3278 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3279 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3280 | - 0x80000000); | |
3281 | } | |
3282 | ||
3283 | /* | |
3284 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3285 | * all higher bits unset. | |
3286 | */ | |
3287 | static void | |
3288 | normalize_address_expr (expressionS *ex) | |
3289 | { | |
3290 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3291 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3292 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3293 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3294 | - 0x80000000); | |
3295 | } | |
3296 | ||
438c16b8 TS |
3297 | /* |
3298 | * Generate a "jalr" instruction with a relocation hint to the called | |
3299 | * function. This occurs in NewABI PIC code. | |
3300 | */ | |
3301 | static void | |
67c0d1eb | 3302 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3303 | { |
685736be | 3304 | char *f = NULL; |
b34976b6 | 3305 | |
438c16b8 | 3306 | if (HAVE_NEWABI) |
f21f8242 | 3307 | { |
cc3d92a5 | 3308 | frag_grow (8); |
f21f8242 AO |
3309 | f = frag_more (0); |
3310 | } | |
67c0d1eb | 3311 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3312 | if (HAVE_NEWABI) |
f21f8242 | 3313 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3314 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3315 | } |
3316 | ||
252b5132 RH |
3317 | /* |
3318 | * Generate a "lui" instruction. | |
3319 | */ | |
3320 | static void | |
67c0d1eb | 3321 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3322 | { |
3323 | expressionS high_expr; | |
1e915849 | 3324 | const struct mips_opcode *mo; |
252b5132 | 3325 | struct mips_cl_insn insn; |
f6688943 TS |
3326 | bfd_reloc_code_real_type r[3] |
3327 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3328 | const char *name = "lui"; |
3329 | const char *fmt = "t,u"; | |
252b5132 RH |
3330 | |
3331 | assert (! mips_opts.mips16); | |
3332 | ||
4d7206a2 | 3333 | high_expr = *ep; |
252b5132 RH |
3334 | |
3335 | if (high_expr.X_op == O_constant) | |
3336 | { | |
3337 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3338 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3339 | >> 16) & 0xffff; | |
f6688943 | 3340 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3341 | } |
78e1bb40 | 3342 | else |
252b5132 RH |
3343 | { |
3344 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3345 | /* _gp_disp is a special case, used from s_cpload. |
3346 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3347 | assert (mips_pic == NO_PIC |
78e1bb40 | 3348 | || (! HAVE_NEWABI |
aa6975fb ILT |
3349 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3350 | || (! mips_in_shared | |
bbe506e8 TS |
3351 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3352 | "__gnu_local_gp") == 0)); | |
f6688943 | 3353 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3354 | } |
3355 | ||
1e915849 RS |
3356 | mo = hash_find (op_hash, name); |
3357 | assert (strcmp (name, mo->name) == 0); | |
3358 | assert (strcmp (fmt, mo->args) == 0); | |
3359 | create_insn (&insn, mo); | |
252b5132 | 3360 | |
bf12938e RS |
3361 | insn.insn_opcode = insn.insn_mo->match; |
3362 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3363 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3364 | { |
3365 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3366 | append_insn (&insn, NULL, r); |
252b5132 RH |
3367 | } |
3368 | else | |
4d7206a2 | 3369 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3370 | } |
3371 | ||
885add95 CD |
3372 | /* Generate a sequence of instructions to do a load or store from a constant |
3373 | offset off of a base register (breg) into/from a target register (treg), | |
3374 | using AT if necessary. */ | |
3375 | static void | |
67c0d1eb RS |
3376 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3377 | int treg, int breg, int dbl) | |
885add95 CD |
3378 | { |
3379 | assert (ep->X_op == O_constant); | |
3380 | ||
256ab948 | 3381 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3382 | if (!dbl) |
3383 | normalize_constant_expr (ep); | |
256ab948 | 3384 | |
67c1ffbe | 3385 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3386 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3387 | as_warn (_("operand overflow")); |
3388 | ||
3389 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3390 | { | |
3391 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3392 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3393 | } |
3394 | else | |
3395 | { | |
3396 | /* 32-bit offset, need multiple instructions and AT, like: | |
3397 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3398 | addu $tempreg,$tempreg,$breg | |
3399 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3400 | to handle the complete offset. */ | |
67c0d1eb RS |
3401 | macro_build_lui (ep, AT); |
3402 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3403 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3404 | |
3405 | if (mips_opts.noat) | |
8fc2e39e | 3406 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3407 | } |
3408 | } | |
3409 | ||
252b5132 RH |
3410 | /* set_at() |
3411 | * Generates code to set the $at register to true (one) | |
3412 | * if reg is less than the immediate expression. | |
3413 | */ | |
3414 | static void | |
67c0d1eb | 3415 | set_at (int reg, int unsignedp) |
252b5132 RH |
3416 | { |
3417 | if (imm_expr.X_op == O_constant | |
3418 | && imm_expr.X_add_number >= -0x8000 | |
3419 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3420 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3421 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3422 | else |
3423 | { | |
67c0d1eb RS |
3424 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3425 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3426 | } |
3427 | } | |
3428 | ||
3429 | /* Warn if an expression is not a constant. */ | |
3430 | ||
3431 | static void | |
17a2f251 | 3432 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3433 | { |
3434 | if (ex->X_op == O_big) | |
3435 | as_bad (_("unsupported large constant")); | |
3436 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3437 | as_bad (_("Instruction %s requires absolute expression"), |
3438 | ip->insn_mo->name); | |
13757d0c | 3439 | |
9ee2a2d4 MR |
3440 | if (HAVE_32BIT_GPRS) |
3441 | normalize_constant_expr (ex); | |
252b5132 RH |
3442 | } |
3443 | ||
3444 | /* Count the leading zeroes by performing a binary chop. This is a | |
3445 | bulky bit of source, but performance is a LOT better for the | |
3446 | majority of values than a simple loop to count the bits: | |
3447 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3448 | if ((v) & (1 << (31 - lcnt))) | |
3449 | break; | |
3450 | However it is not code size friendly, and the gain will drop a bit | |
3451 | on certain cached systems. | |
3452 | */ | |
3453 | #define COUNT_TOP_ZEROES(v) \ | |
3454 | (((v) & ~0xffff) == 0 \ | |
3455 | ? ((v) & ~0xff) == 0 \ | |
3456 | ? ((v) & ~0xf) == 0 \ | |
3457 | ? ((v) & ~0x3) == 0 \ | |
3458 | ? ((v) & ~0x1) == 0 \ | |
3459 | ? !(v) \ | |
3460 | ? 32 \ | |
3461 | : 31 \ | |
3462 | : 30 \ | |
3463 | : ((v) & ~0x7) == 0 \ | |
3464 | ? 29 \ | |
3465 | : 28 \ | |
3466 | : ((v) & ~0x3f) == 0 \ | |
3467 | ? ((v) & ~0x1f) == 0 \ | |
3468 | ? 27 \ | |
3469 | : 26 \ | |
3470 | : ((v) & ~0x7f) == 0 \ | |
3471 | ? 25 \ | |
3472 | : 24 \ | |
3473 | : ((v) & ~0xfff) == 0 \ | |
3474 | ? ((v) & ~0x3ff) == 0 \ | |
3475 | ? ((v) & ~0x1ff) == 0 \ | |
3476 | ? 23 \ | |
3477 | : 22 \ | |
3478 | : ((v) & ~0x7ff) == 0 \ | |
3479 | ? 21 \ | |
3480 | : 20 \ | |
3481 | : ((v) & ~0x3fff) == 0 \ | |
3482 | ? ((v) & ~0x1fff) == 0 \ | |
3483 | ? 19 \ | |
3484 | : 18 \ | |
3485 | : ((v) & ~0x7fff) == 0 \ | |
3486 | ? 17 \ | |
3487 | : 16 \ | |
3488 | : ((v) & ~0xffffff) == 0 \ | |
3489 | ? ((v) & ~0xfffff) == 0 \ | |
3490 | ? ((v) & ~0x3ffff) == 0 \ | |
3491 | ? ((v) & ~0x1ffff) == 0 \ | |
3492 | ? 15 \ | |
3493 | : 14 \ | |
3494 | : ((v) & ~0x7ffff) == 0 \ | |
3495 | ? 13 \ | |
3496 | : 12 \ | |
3497 | : ((v) & ~0x3fffff) == 0 \ | |
3498 | ? ((v) & ~0x1fffff) == 0 \ | |
3499 | ? 11 \ | |
3500 | : 10 \ | |
3501 | : ((v) & ~0x7fffff) == 0 \ | |
3502 | ? 9 \ | |
3503 | : 8 \ | |
3504 | : ((v) & ~0xfffffff) == 0 \ | |
3505 | ? ((v) & ~0x3ffffff) == 0 \ | |
3506 | ? ((v) & ~0x1ffffff) == 0 \ | |
3507 | ? 7 \ | |
3508 | : 6 \ | |
3509 | : ((v) & ~0x7ffffff) == 0 \ | |
3510 | ? 5 \ | |
3511 | : 4 \ | |
3512 | : ((v) & ~0x3fffffff) == 0 \ | |
3513 | ? ((v) & ~0x1fffffff) == 0 \ | |
3514 | ? 3 \ | |
3515 | : 2 \ | |
3516 | : ((v) & ~0x7fffffff) == 0 \ | |
3517 | ? 1 \ | |
3518 | : 0) | |
3519 | ||
3520 | /* load_register() | |
67c1ffbe | 3521 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3522 | * an absolute expression value into a register. |
3523 | */ | |
3524 | static void | |
67c0d1eb | 3525 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3526 | { |
3527 | int freg; | |
3528 | expressionS hi32, lo32; | |
3529 | ||
3530 | if (ep->X_op != O_big) | |
3531 | { | |
3532 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3533 | |
3534 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3535 | if (!dbl) |
3536 | normalize_constant_expr (ep); | |
256ab948 TS |
3537 | |
3538 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3539 | { |
3540 | /* We can handle 16 bit signed values with an addiu to | |
3541 | $zero. No need to ever use daddiu here, since $zero and | |
3542 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3543 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3544 | return; |
3545 | } | |
3546 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3547 | { | |
3548 | /* We can handle 16 bit unsigned values with an ori to | |
3549 | $zero. */ | |
67c0d1eb | 3550 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3551 | return; |
3552 | } | |
256ab948 | 3553 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3554 | { |
3555 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3556 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3557 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3558 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3559 | return; |
3560 | } | |
3561 | } | |
3562 | ||
3563 | /* The value is larger than 32 bits. */ | |
3564 | ||
2051e8c4 | 3565 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3566 | { |
55e08f71 NC |
3567 | char value[32]; |
3568 | ||
3569 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3570 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3571 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3572 | return; |
3573 | } | |
3574 | ||
3575 | if (ep->X_op != O_big) | |
3576 | { | |
3577 | hi32 = *ep; | |
3578 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3579 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3580 | hi32.X_add_number &= 0xffffffff; | |
3581 | lo32 = *ep; | |
3582 | lo32.X_add_number &= 0xffffffff; | |
3583 | } | |
3584 | else | |
3585 | { | |
3586 | assert (ep->X_add_number > 2); | |
3587 | if (ep->X_add_number == 3) | |
3588 | generic_bignum[3] = 0; | |
3589 | else if (ep->X_add_number > 4) | |
3590 | as_bad (_("Number larger than 64 bits")); | |
3591 | lo32.X_op = O_constant; | |
3592 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3593 | hi32.X_op = O_constant; | |
3594 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3595 | } | |
3596 | ||
3597 | if (hi32.X_add_number == 0) | |
3598 | freg = 0; | |
3599 | else | |
3600 | { | |
3601 | int shift, bit; | |
3602 | unsigned long hi, lo; | |
3603 | ||
956cd1d6 | 3604 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3605 | { |
3606 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3607 | { | |
67c0d1eb | 3608 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3609 | return; |
3610 | } | |
3611 | if (lo32.X_add_number & 0x80000000) | |
3612 | { | |
67c0d1eb | 3613 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3614 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3615 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3616 | return; |
3617 | } | |
3618 | } | |
252b5132 RH |
3619 | |
3620 | /* Check for 16bit shifted constant. We know that hi32 is | |
3621 | non-zero, so start the mask on the first bit of the hi32 | |
3622 | value. */ | |
3623 | shift = 17; | |
3624 | do | |
beae10d5 KH |
3625 | { |
3626 | unsigned long himask, lomask; | |
3627 | ||
3628 | if (shift < 32) | |
3629 | { | |
3630 | himask = 0xffff >> (32 - shift); | |
3631 | lomask = (0xffff << shift) & 0xffffffff; | |
3632 | } | |
3633 | else | |
3634 | { | |
3635 | himask = 0xffff << (shift - 32); | |
3636 | lomask = 0; | |
3637 | } | |
3638 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3639 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3640 | { | |
3641 | expressionS tmp; | |
3642 | ||
3643 | tmp.X_op = O_constant; | |
3644 | if (shift < 32) | |
3645 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3646 | | (lo32.X_add_number >> shift)); | |
3647 | else | |
3648 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3649 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3650 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3651 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3652 | return; |
3653 | } | |
f9419b05 | 3654 | ++shift; |
beae10d5 KH |
3655 | } |
3656 | while (shift <= (64 - 16)); | |
252b5132 RH |
3657 | |
3658 | /* Find the bit number of the lowest one bit, and store the | |
3659 | shifted value in hi/lo. */ | |
3660 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3661 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3662 | if (lo != 0) | |
3663 | { | |
3664 | bit = 0; | |
3665 | while ((lo & 1) == 0) | |
3666 | { | |
3667 | lo >>= 1; | |
3668 | ++bit; | |
3669 | } | |
3670 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3671 | hi >>= bit; | |
3672 | } | |
3673 | else | |
3674 | { | |
3675 | bit = 32; | |
3676 | while ((hi & 1) == 0) | |
3677 | { | |
3678 | hi >>= 1; | |
3679 | ++bit; | |
3680 | } | |
3681 | lo = hi; | |
3682 | hi = 0; | |
3683 | } | |
3684 | ||
3685 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3686 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3687 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3688 | { |
3689 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3690 | if (shift != 0) |
beae10d5 | 3691 | { |
252b5132 RH |
3692 | expressionS tmp; |
3693 | ||
3694 | /* This instruction will set the register to be all | |
3695 | ones. */ | |
beae10d5 KH |
3696 | tmp.X_op = O_constant; |
3697 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3698 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3699 | if (bit != 0) |
3700 | { | |
3701 | bit += shift; | |
67c0d1eb RS |
3702 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3703 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3704 | } |
67c0d1eb RS |
3705 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3706 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3707 | return; |
3708 | } | |
3709 | } | |
252b5132 RH |
3710 | |
3711 | /* Sign extend hi32 before calling load_register, because we can | |
3712 | generally get better code when we load a sign extended value. */ | |
3713 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3714 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3715 | load_register (reg, &hi32, 0); |
252b5132 RH |
3716 | freg = reg; |
3717 | } | |
3718 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3719 | { | |
3720 | if (freg != 0) | |
3721 | { | |
67c0d1eb | 3722 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3723 | freg = reg; |
3724 | } | |
3725 | } | |
3726 | else | |
3727 | { | |
3728 | expressionS mid16; | |
3729 | ||
956cd1d6 | 3730 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3731 | { |
67c0d1eb RS |
3732 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3733 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3734 | return; |
3735 | } | |
252b5132 RH |
3736 | |
3737 | if (freg != 0) | |
3738 | { | |
67c0d1eb | 3739 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3740 | freg = reg; |
3741 | } | |
3742 | mid16 = lo32; | |
3743 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3744 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3745 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3746 | freg = reg; |
3747 | } | |
3748 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3749 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3750 | } |
3751 | ||
269137b2 TS |
3752 | static inline void |
3753 | load_delay_nop (void) | |
3754 | { | |
3755 | if (!gpr_interlocks) | |
3756 | macro_build (NULL, "nop", ""); | |
3757 | } | |
3758 | ||
252b5132 RH |
3759 | /* Load an address into a register. */ |
3760 | ||
3761 | static void | |
67c0d1eb | 3762 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3763 | { |
252b5132 RH |
3764 | if (ep->X_op != O_constant |
3765 | && ep->X_op != O_symbol) | |
3766 | { | |
3767 | as_bad (_("expression too complex")); | |
3768 | ep->X_op = O_constant; | |
3769 | } | |
3770 | ||
3771 | if (ep->X_op == O_constant) | |
3772 | { | |
67c0d1eb | 3773 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3774 | return; |
3775 | } | |
3776 | ||
3777 | if (mips_pic == NO_PIC) | |
3778 | { | |
3779 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3780 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3781 | Otherwise we want |
3782 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3783 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3784 | If we have an addend, we always use the latter form. |
76b3015f | 3785 | |
d6bc6245 TS |
3786 | With 64bit address space and a usable $at we want |
3787 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3788 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3789 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3790 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3791 | dsll32 $reg,0 | |
3a482fd5 | 3792 | daddu $reg,$reg,$at |
76b3015f | 3793 | |
c03099e6 | 3794 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3795 | on superscalar processors. |
3796 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3797 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3798 | dsll $reg,16 | |
3799 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3800 | dsll $reg,16 | |
3801 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3802 | |
3803 | For GP relative symbols in 64bit address space we can use | |
3804 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3805 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3806 | { |
6caf9ef4 TS |
3807 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3808 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3809 | { | |
3810 | relax_start (ep->X_add_symbol); | |
3811 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3812 | mips_gp_register, BFD_RELOC_GPREL16); | |
3813 | relax_switch (); | |
3814 | } | |
d6bc6245 | 3815 | |
b8285c27 | 3816 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3817 | { |
67c0d1eb RS |
3818 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3819 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3820 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3821 | BFD_RELOC_MIPS_HIGHER); | |
3822 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3823 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3824 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3825 | *used_at = 1; |
3826 | } | |
3827 | else | |
3828 | { | |
67c0d1eb RS |
3829 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3830 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3831 | BFD_RELOC_MIPS_HIGHER); | |
3832 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3833 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3834 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3835 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3836 | } |
6caf9ef4 TS |
3837 | |
3838 | if (mips_relax.sequence) | |
3839 | relax_end (); | |
d6bc6245 | 3840 | } |
252b5132 RH |
3841 | else |
3842 | { | |
d6bc6245 | 3843 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3844 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3845 | { |
4d7206a2 | 3846 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3847 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3848 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3849 | relax_switch (); |
d6bc6245 | 3850 | } |
67c0d1eb RS |
3851 | macro_build_lui (ep, reg); |
3852 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3853 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3854 | if (mips_relax.sequence) |
3855 | relax_end (); | |
d6bc6245 | 3856 | } |
252b5132 RH |
3857 | } |
3858 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3859 | { | |
3860 | expressionS ex; | |
3861 | ||
3862 | /* If this is a reference to an external symbol, we want | |
3863 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3864 | Otherwise we want | |
3865 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3866 | nop | |
3867 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3868 | If there is a constant, it must be added in after. |
3869 | ||
ed6fb7bd | 3870 | If we have NewABI, we want |
f5040a92 AO |
3871 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3872 | unless we're referencing a global symbol with a non-zero | |
3873 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3874 | if (HAVE_NEWABI) |
3875 | { | |
f5040a92 AO |
3876 | if (ep->X_add_number) |
3877 | { | |
4d7206a2 | 3878 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3879 | ep->X_add_number = 0; |
4d7206a2 | 3880 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3881 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3882 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3883 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3884 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3885 | ex.X_op = O_constant; | |
67c0d1eb | 3886 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3887 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3888 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3889 | relax_switch (); |
f5040a92 | 3890 | } |
67c0d1eb | 3891 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3892 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3893 | if (mips_relax.sequence) |
3894 | relax_end (); | |
ed6fb7bd SC |
3895 | } |
3896 | else | |
3897 | { | |
f5040a92 AO |
3898 | ex.X_add_number = ep->X_add_number; |
3899 | ep->X_add_number = 0; | |
67c0d1eb RS |
3900 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3901 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3902 | load_delay_nop (); |
4d7206a2 RS |
3903 | relax_start (ep->X_add_symbol); |
3904 | relax_switch (); | |
67c0d1eb | 3905 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3906 | BFD_RELOC_LO16); |
4d7206a2 | 3907 | relax_end (); |
ed6fb7bd | 3908 | |
f5040a92 AO |
3909 | if (ex.X_add_number != 0) |
3910 | { | |
3911 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3912 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3913 | ex.X_op = O_constant; | |
67c0d1eb | 3914 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3915 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3916 | } |
252b5132 RH |
3917 | } |
3918 | } | |
3919 | else if (mips_pic == SVR4_PIC) | |
3920 | { | |
3921 | expressionS ex; | |
252b5132 RH |
3922 | |
3923 | /* This is the large GOT case. If this is a reference to an | |
3924 | external symbol, we want | |
3925 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3926 | addu $reg,$reg,$gp | |
3927 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3928 | |
3929 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3930 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3931 | nop | |
3932 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3933 | If there is a constant, it must be added in after. |
f5040a92 AO |
3934 | |
3935 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3936 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3937 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3938 | */ |
438c16b8 TS |
3939 | if (HAVE_NEWABI) |
3940 | { | |
4d7206a2 | 3941 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3942 | ep->X_add_number = 0; |
4d7206a2 | 3943 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3944 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3945 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3946 | reg, reg, mips_gp_register); | |
3947 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3948 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3949 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3950 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3951 | else if (ex.X_add_number) | |
3952 | { | |
3953 | ex.X_op = O_constant; | |
67c0d1eb RS |
3954 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3955 | BFD_RELOC_LO16); | |
f5040a92 AO |
3956 | } |
3957 | ||
3958 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3959 | relax_switch (); |
67c0d1eb | 3960 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3961 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3962 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3963 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3964 | relax_end (); |
438c16b8 | 3965 | } |
252b5132 | 3966 | else |
438c16b8 | 3967 | { |
f5040a92 AO |
3968 | ex.X_add_number = ep->X_add_number; |
3969 | ep->X_add_number = 0; | |
4d7206a2 | 3970 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3971 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3972 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3973 | reg, reg, mips_gp_register); | |
3974 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3975 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3976 | relax_switch (); |
3977 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3978 | { |
3979 | /* We need a nop before loading from $gp. This special | |
3980 | check is required because the lui which starts the main | |
3981 | instruction stream does not refer to $gp, and so will not | |
3982 | insert the nop which may be required. */ | |
67c0d1eb | 3983 | macro_build (NULL, "nop", ""); |
438c16b8 | 3984 | } |
67c0d1eb | 3985 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3986 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3987 | load_delay_nop (); |
67c0d1eb | 3988 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3989 | BFD_RELOC_LO16); |
4d7206a2 | 3990 | relax_end (); |
438c16b8 | 3991 | |
f5040a92 AO |
3992 | if (ex.X_add_number != 0) |
3993 | { | |
3994 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3995 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3996 | ex.X_op = O_constant; | |
67c0d1eb RS |
3997 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3998 | BFD_RELOC_LO16); | |
f5040a92 | 3999 | } |
252b5132 RH |
4000 | } |
4001 | } | |
252b5132 RH |
4002 | else |
4003 | abort (); | |
8fc2e39e TS |
4004 | |
4005 | if (mips_opts.noat && *used_at == 1) | |
4006 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4007 | } |
4008 | ||
ea1fb5dc RS |
4009 | /* Move the contents of register SOURCE into register DEST. */ |
4010 | ||
4011 | static void | |
67c0d1eb | 4012 | move_register (int dest, int source) |
ea1fb5dc | 4013 | { |
67c0d1eb RS |
4014 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4015 | dest, source, 0); | |
ea1fb5dc RS |
4016 | } |
4017 | ||
4d7206a2 | 4018 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4019 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4020 | The two alternatives are: | |
4d7206a2 RS |
4021 | |
4022 | Global symbol Local sybmol | |
4023 | ------------- ------------ | |
4024 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4025 | ... ... | |
4026 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4027 | ||
4028 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4029 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4030 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4031 | |
4032 | static void | |
67c0d1eb | 4033 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4034 | { |
4035 | expressionS global; | |
4036 | ||
4037 | global = *local; | |
4038 | global.X_add_number = 0; | |
4039 | ||
4040 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4041 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4042 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4043 | relax_switch (); |
67c0d1eb RS |
4044 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4045 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4046 | relax_end (); |
4047 | } | |
4048 | ||
4049 | static void | |
67c0d1eb | 4050 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4051 | { |
4052 | expressionS global; | |
4053 | ||
4054 | global.X_op = O_constant; | |
4055 | global.X_op_symbol = NULL; | |
4056 | global.X_add_symbol = NULL; | |
4057 | global.X_add_number = local->X_add_number; | |
4058 | ||
4059 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4060 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4061 | dest, dest, BFD_RELOC_LO16); |
4062 | relax_switch (); | |
67c0d1eb | 4063 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4064 | relax_end (); |
4065 | } | |
4066 | ||
f6a22291 MR |
4067 | static void |
4068 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4069 | { | |
4070 | expressionS global; | |
4071 | int hold_mips_optimize; | |
4072 | ||
4073 | global.X_op = O_constant; | |
4074 | global.X_op_symbol = NULL; | |
4075 | global.X_add_symbol = NULL; | |
4076 | global.X_add_number = local->X_add_number; | |
4077 | ||
4078 | relax_start (local->X_add_symbol); | |
4079 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4080 | relax_switch (); | |
4081 | /* Set mips_optimize around the lui instruction to avoid | |
4082 | inserting an unnecessary nop after the lw. */ | |
4083 | hold_mips_optimize = mips_optimize; | |
4084 | mips_optimize = 2; | |
4085 | macro_build_lui (&global, tmp); | |
4086 | mips_optimize = hold_mips_optimize; | |
4087 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4088 | relax_end (); | |
4089 | ||
4090 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4091 | } | |
4092 | ||
252b5132 RH |
4093 | /* |
4094 | * Build macros | |
4095 | * This routine implements the seemingly endless macro or synthesized | |
4096 | * instructions and addressing modes in the mips assembly language. Many | |
4097 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4098 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4099 | * this verbose method. Others are not simple macros but are more like |
4100 | * optimizing code generation. | |
4101 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4102 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4103 | * The ensuing load upper instructions are ommited. This implies some kind |
4104 | * of global optimization. We currently only optimize within a single macro. | |
4105 | * For many of the load and store macros if the address is specified as a | |
4106 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4107 | * first load register 'at' with zero and use it as the base register. The | |
4108 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4109 | * we're missing. | |
4110 | */ | |
4111 | static void | |
17a2f251 | 4112 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4113 | { |
4114 | register int treg, sreg, dreg, breg; | |
4115 | int tempreg; | |
4116 | int mask; | |
43841e91 | 4117 | int used_at = 0; |
252b5132 RH |
4118 | expressionS expr1; |
4119 | const char *s; | |
4120 | const char *s2; | |
4121 | const char *fmt; | |
4122 | int likely = 0; | |
4123 | int dbl = 0; | |
4124 | int coproc = 0; | |
4125 | int lr = 0; | |
4126 | int imm = 0; | |
1abe91b1 | 4127 | int call = 0; |
252b5132 | 4128 | int off; |
67c0d1eb | 4129 | offsetT maxnum; |
252b5132 | 4130 | bfd_reloc_code_real_type r; |
252b5132 RH |
4131 | int hold_mips_optimize; |
4132 | ||
4133 | assert (! mips_opts.mips16); | |
4134 | ||
4135 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4136 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4137 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4138 | mask = ip->insn_mo->mask; | |
4139 | ||
4140 | expr1.X_op = O_constant; | |
4141 | expr1.X_op_symbol = NULL; | |
4142 | expr1.X_add_symbol = NULL; | |
4143 | expr1.X_add_number = 1; | |
4144 | ||
4145 | switch (mask) | |
4146 | { | |
4147 | case M_DABS: | |
4148 | dbl = 1; | |
4149 | case M_ABS: | |
4150 | /* bgez $a0,.+12 | |
4151 | move v0,$a0 | |
4152 | sub v0,$zero,$a0 | |
4153 | */ | |
4154 | ||
7d10b47d | 4155 | start_noreorder (); |
252b5132 RH |
4156 | |
4157 | expr1.X_add_number = 8; | |
67c0d1eb | 4158 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4159 | if (dreg == sreg) |
67c0d1eb | 4160 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4161 | else |
67c0d1eb RS |
4162 | move_register (dreg, sreg); |
4163 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4164 | |
7d10b47d | 4165 | end_noreorder (); |
8fc2e39e | 4166 | break; |
252b5132 RH |
4167 | |
4168 | case M_ADD_I: | |
4169 | s = "addi"; | |
4170 | s2 = "add"; | |
4171 | goto do_addi; | |
4172 | case M_ADDU_I: | |
4173 | s = "addiu"; | |
4174 | s2 = "addu"; | |
4175 | goto do_addi; | |
4176 | case M_DADD_I: | |
4177 | dbl = 1; | |
4178 | s = "daddi"; | |
4179 | s2 = "dadd"; | |
4180 | goto do_addi; | |
4181 | case M_DADDU_I: | |
4182 | dbl = 1; | |
4183 | s = "daddiu"; | |
4184 | s2 = "daddu"; | |
4185 | do_addi: | |
4186 | if (imm_expr.X_op == O_constant | |
4187 | && imm_expr.X_add_number >= -0x8000 | |
4188 | && imm_expr.X_add_number < 0x8000) | |
4189 | { | |
67c0d1eb | 4190 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4191 | break; |
252b5132 | 4192 | } |
8fc2e39e | 4193 | used_at = 1; |
67c0d1eb RS |
4194 | load_register (AT, &imm_expr, dbl); |
4195 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4196 | break; |
4197 | ||
4198 | case M_AND_I: | |
4199 | s = "andi"; | |
4200 | s2 = "and"; | |
4201 | goto do_bit; | |
4202 | case M_OR_I: | |
4203 | s = "ori"; | |
4204 | s2 = "or"; | |
4205 | goto do_bit; | |
4206 | case M_NOR_I: | |
4207 | s = ""; | |
4208 | s2 = "nor"; | |
4209 | goto do_bit; | |
4210 | case M_XOR_I: | |
4211 | s = "xori"; | |
4212 | s2 = "xor"; | |
4213 | do_bit: | |
4214 | if (imm_expr.X_op == O_constant | |
4215 | && imm_expr.X_add_number >= 0 | |
4216 | && imm_expr.X_add_number < 0x10000) | |
4217 | { | |
4218 | if (mask != M_NOR_I) | |
67c0d1eb | 4219 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4220 | else |
4221 | { | |
67c0d1eb RS |
4222 | macro_build (&imm_expr, "ori", "t,r,i", |
4223 | treg, sreg, BFD_RELOC_LO16); | |
4224 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4225 | } |
8fc2e39e | 4226 | break; |
252b5132 RH |
4227 | } |
4228 | ||
8fc2e39e | 4229 | used_at = 1; |
67c0d1eb RS |
4230 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4231 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4232 | break; |
4233 | ||
4234 | case M_BEQ_I: | |
4235 | s = "beq"; | |
4236 | goto beq_i; | |
4237 | case M_BEQL_I: | |
4238 | s = "beql"; | |
4239 | likely = 1; | |
4240 | goto beq_i; | |
4241 | case M_BNE_I: | |
4242 | s = "bne"; | |
4243 | goto beq_i; | |
4244 | case M_BNEL_I: | |
4245 | s = "bnel"; | |
4246 | likely = 1; | |
4247 | beq_i: | |
4248 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4249 | { | |
67c0d1eb | 4250 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4251 | break; |
252b5132 | 4252 | } |
8fc2e39e | 4253 | used_at = 1; |
67c0d1eb RS |
4254 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4255 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4256 | break; |
4257 | ||
4258 | case M_BGEL: | |
4259 | likely = 1; | |
4260 | case M_BGE: | |
4261 | if (treg == 0) | |
4262 | { | |
67c0d1eb | 4263 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4264 | break; |
252b5132 RH |
4265 | } |
4266 | if (sreg == 0) | |
4267 | { | |
67c0d1eb | 4268 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4269 | break; |
252b5132 | 4270 | } |
8fc2e39e | 4271 | used_at = 1; |
67c0d1eb RS |
4272 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4273 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4274 | break; |
4275 | ||
4276 | case M_BGTL_I: | |
4277 | likely = 1; | |
4278 | case M_BGT_I: | |
4279 | /* check for > max integer */ | |
4280 | maxnum = 0x7fffffff; | |
ca4e0257 | 4281 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4282 | { |
4283 | maxnum <<= 16; | |
4284 | maxnum |= 0xffff; | |
4285 | maxnum <<= 16; | |
4286 | maxnum |= 0xffff; | |
4287 | } | |
4288 | if (imm_expr.X_op == O_constant | |
4289 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4290 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4291 | { |
4292 | do_false: | |
4293 | /* result is always false */ | |
4294 | if (! likely) | |
67c0d1eb | 4295 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4296 | else |
67c0d1eb | 4297 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4298 | break; |
252b5132 RH |
4299 | } |
4300 | if (imm_expr.X_op != O_constant) | |
4301 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4302 | ++imm_expr.X_add_number; |
252b5132 RH |
4303 | /* FALLTHROUGH */ |
4304 | case M_BGE_I: | |
4305 | case M_BGEL_I: | |
4306 | if (mask == M_BGEL_I) | |
4307 | likely = 1; | |
4308 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4309 | { | |
67c0d1eb | 4310 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4311 | break; |
252b5132 RH |
4312 | } |
4313 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4314 | { | |
67c0d1eb | 4315 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4316 | break; |
252b5132 RH |
4317 | } |
4318 | maxnum = 0x7fffffff; | |
ca4e0257 | 4319 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4320 | { |
4321 | maxnum <<= 16; | |
4322 | maxnum |= 0xffff; | |
4323 | maxnum <<= 16; | |
4324 | maxnum |= 0xffff; | |
4325 | } | |
4326 | maxnum = - maxnum - 1; | |
4327 | if (imm_expr.X_op == O_constant | |
4328 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4329 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4330 | { |
4331 | do_true: | |
4332 | /* result is always true */ | |
4333 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4334 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4335 | break; |
252b5132 | 4336 | } |
8fc2e39e | 4337 | used_at = 1; |
67c0d1eb RS |
4338 | set_at (sreg, 0); |
4339 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4340 | break; |
4341 | ||
4342 | case M_BGEUL: | |
4343 | likely = 1; | |
4344 | case M_BGEU: | |
4345 | if (treg == 0) | |
4346 | goto do_true; | |
4347 | if (sreg == 0) | |
4348 | { | |
67c0d1eb | 4349 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4350 | "s,t,p", 0, treg); |
8fc2e39e | 4351 | break; |
252b5132 | 4352 | } |
8fc2e39e | 4353 | used_at = 1; |
67c0d1eb RS |
4354 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4355 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4356 | break; |
4357 | ||
4358 | case M_BGTUL_I: | |
4359 | likely = 1; | |
4360 | case M_BGTU_I: | |
4361 | if (sreg == 0 | |
ca4e0257 | 4362 | || (HAVE_32BIT_GPRS |
252b5132 | 4363 | && imm_expr.X_op == O_constant |
956cd1d6 | 4364 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4365 | goto do_false; |
4366 | if (imm_expr.X_op != O_constant) | |
4367 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4368 | ++imm_expr.X_add_number; |
252b5132 RH |
4369 | /* FALLTHROUGH */ |
4370 | case M_BGEU_I: | |
4371 | case M_BGEUL_I: | |
4372 | if (mask == M_BGEUL_I) | |
4373 | likely = 1; | |
4374 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4375 | goto do_true; | |
4376 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4377 | { | |
67c0d1eb | 4378 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4379 | "s,t,p", sreg, 0); |
8fc2e39e | 4380 | break; |
252b5132 | 4381 | } |
8fc2e39e | 4382 | used_at = 1; |
67c0d1eb RS |
4383 | set_at (sreg, 1); |
4384 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4385 | break; |
4386 | ||
4387 | case M_BGTL: | |
4388 | likely = 1; | |
4389 | case M_BGT: | |
4390 | if (treg == 0) | |
4391 | { | |
67c0d1eb | 4392 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4393 | break; |
252b5132 RH |
4394 | } |
4395 | if (sreg == 0) | |
4396 | { | |
67c0d1eb | 4397 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4398 | break; |
252b5132 | 4399 | } |
8fc2e39e | 4400 | used_at = 1; |
67c0d1eb RS |
4401 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4402 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4403 | break; |
4404 | ||
4405 | case M_BGTUL: | |
4406 | likely = 1; | |
4407 | case M_BGTU: | |
4408 | if (treg == 0) | |
4409 | { | |
67c0d1eb | 4410 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4411 | "s,t,p", sreg, 0); |
8fc2e39e | 4412 | break; |
252b5132 RH |
4413 | } |
4414 | if (sreg == 0) | |
4415 | goto do_false; | |
8fc2e39e | 4416 | used_at = 1; |
67c0d1eb RS |
4417 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4418 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4419 | break; |
4420 | ||
4421 | case M_BLEL: | |
4422 | likely = 1; | |
4423 | case M_BLE: | |
4424 | if (treg == 0) | |
4425 | { | |
67c0d1eb | 4426 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4427 | break; |
252b5132 RH |
4428 | } |
4429 | if (sreg == 0) | |
4430 | { | |
67c0d1eb | 4431 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4432 | break; |
252b5132 | 4433 | } |
8fc2e39e | 4434 | used_at = 1; |
67c0d1eb RS |
4435 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4436 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4437 | break; |
4438 | ||
4439 | case M_BLEL_I: | |
4440 | likely = 1; | |
4441 | case M_BLE_I: | |
4442 | maxnum = 0x7fffffff; | |
ca4e0257 | 4443 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4444 | { |
4445 | maxnum <<= 16; | |
4446 | maxnum |= 0xffff; | |
4447 | maxnum <<= 16; | |
4448 | maxnum |= 0xffff; | |
4449 | } | |
4450 | if (imm_expr.X_op == O_constant | |
4451 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4452 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4453 | goto do_true; |
4454 | if (imm_expr.X_op != O_constant) | |
4455 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4456 | ++imm_expr.X_add_number; |
252b5132 RH |
4457 | /* FALLTHROUGH */ |
4458 | case M_BLT_I: | |
4459 | case M_BLTL_I: | |
4460 | if (mask == M_BLTL_I) | |
4461 | likely = 1; | |
4462 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4463 | { | |
67c0d1eb | 4464 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4465 | break; |
252b5132 RH |
4466 | } |
4467 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4468 | { | |
67c0d1eb | 4469 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4470 | break; |
252b5132 | 4471 | } |
8fc2e39e | 4472 | used_at = 1; |
67c0d1eb RS |
4473 | set_at (sreg, 0); |
4474 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4475 | break; |
4476 | ||
4477 | case M_BLEUL: | |
4478 | likely = 1; | |
4479 | case M_BLEU: | |
4480 | if (treg == 0) | |
4481 | { | |
67c0d1eb | 4482 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4483 | "s,t,p", sreg, 0); |
8fc2e39e | 4484 | break; |
252b5132 RH |
4485 | } |
4486 | if (sreg == 0) | |
4487 | goto do_true; | |
8fc2e39e | 4488 | used_at = 1; |
67c0d1eb RS |
4489 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4490 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4491 | break; |
4492 | ||
4493 | case M_BLEUL_I: | |
4494 | likely = 1; | |
4495 | case M_BLEU_I: | |
4496 | if (sreg == 0 | |
ca4e0257 | 4497 | || (HAVE_32BIT_GPRS |
252b5132 | 4498 | && imm_expr.X_op == O_constant |
956cd1d6 | 4499 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4500 | goto do_true; |
4501 | if (imm_expr.X_op != O_constant) | |
4502 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4503 | ++imm_expr.X_add_number; |
252b5132 RH |
4504 | /* FALLTHROUGH */ |
4505 | case M_BLTU_I: | |
4506 | case M_BLTUL_I: | |
4507 | if (mask == M_BLTUL_I) | |
4508 | likely = 1; | |
4509 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4510 | goto do_false; | |
4511 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4512 | { | |
67c0d1eb | 4513 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4514 | "s,t,p", sreg, 0); |
8fc2e39e | 4515 | break; |
252b5132 | 4516 | } |
8fc2e39e | 4517 | used_at = 1; |
67c0d1eb RS |
4518 | set_at (sreg, 1); |
4519 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4520 | break; |
4521 | ||
4522 | case M_BLTL: | |
4523 | likely = 1; | |
4524 | case M_BLT: | |
4525 | if (treg == 0) | |
4526 | { | |
67c0d1eb | 4527 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4528 | break; |
252b5132 RH |
4529 | } |
4530 | if (sreg == 0) | |
4531 | { | |
67c0d1eb | 4532 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4533 | break; |
252b5132 | 4534 | } |
8fc2e39e | 4535 | used_at = 1; |
67c0d1eb RS |
4536 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4537 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4538 | break; |
4539 | ||
4540 | case M_BLTUL: | |
4541 | likely = 1; | |
4542 | case M_BLTU: | |
4543 | if (treg == 0) | |
4544 | goto do_false; | |
4545 | if (sreg == 0) | |
4546 | { | |
67c0d1eb | 4547 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4548 | "s,t,p", 0, treg); |
8fc2e39e | 4549 | break; |
252b5132 | 4550 | } |
8fc2e39e | 4551 | used_at = 1; |
67c0d1eb RS |
4552 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4553 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4554 | break; |
4555 | ||
5f74bc13 CD |
4556 | case M_DEXT: |
4557 | { | |
4558 | unsigned long pos; | |
4559 | unsigned long size; | |
4560 | ||
4561 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4562 | { | |
4563 | as_bad (_("Unsupported large constant")); | |
4564 | pos = size = 1; | |
4565 | } | |
4566 | else | |
4567 | { | |
4568 | pos = (unsigned long) imm_expr.X_add_number; | |
4569 | size = (unsigned long) imm2_expr.X_add_number; | |
4570 | } | |
4571 | ||
4572 | if (pos > 63) | |
4573 | { | |
4574 | as_bad (_("Improper position (%lu)"), pos); | |
4575 | pos = 1; | |
4576 | } | |
4577 | if (size == 0 || size > 64 | |
4578 | || (pos + size - 1) > 63) | |
4579 | { | |
4580 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4581 | size, pos); | |
4582 | size = 1; | |
4583 | } | |
4584 | ||
4585 | if (size <= 32 && pos < 32) | |
4586 | { | |
4587 | s = "dext"; | |
4588 | fmt = "t,r,+A,+C"; | |
4589 | } | |
4590 | else if (size <= 32) | |
4591 | { | |
4592 | s = "dextu"; | |
4593 | fmt = "t,r,+E,+H"; | |
4594 | } | |
4595 | else | |
4596 | { | |
4597 | s = "dextm"; | |
4598 | fmt = "t,r,+A,+G"; | |
4599 | } | |
67c0d1eb | 4600 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4601 | } |
8fc2e39e | 4602 | break; |
5f74bc13 CD |
4603 | |
4604 | case M_DINS: | |
4605 | { | |
4606 | unsigned long pos; | |
4607 | unsigned long size; | |
4608 | ||
4609 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4610 | { | |
4611 | as_bad (_("Unsupported large constant")); | |
4612 | pos = size = 1; | |
4613 | } | |
4614 | else | |
4615 | { | |
4616 | pos = (unsigned long) imm_expr.X_add_number; | |
4617 | size = (unsigned long) imm2_expr.X_add_number; | |
4618 | } | |
4619 | ||
4620 | if (pos > 63) | |
4621 | { | |
4622 | as_bad (_("Improper position (%lu)"), pos); | |
4623 | pos = 1; | |
4624 | } | |
4625 | if (size == 0 || size > 64 | |
4626 | || (pos + size - 1) > 63) | |
4627 | { | |
4628 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4629 | size, pos); | |
4630 | size = 1; | |
4631 | } | |
4632 | ||
4633 | if (pos < 32 && (pos + size - 1) < 32) | |
4634 | { | |
4635 | s = "dins"; | |
4636 | fmt = "t,r,+A,+B"; | |
4637 | } | |
4638 | else if (pos >= 32) | |
4639 | { | |
4640 | s = "dinsu"; | |
4641 | fmt = "t,r,+E,+F"; | |
4642 | } | |
4643 | else | |
4644 | { | |
4645 | s = "dinsm"; | |
4646 | fmt = "t,r,+A,+F"; | |
4647 | } | |
67c0d1eb RS |
4648 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4649 | pos + size - 1); | |
5f74bc13 | 4650 | } |
8fc2e39e | 4651 | break; |
5f74bc13 | 4652 | |
252b5132 RH |
4653 | case M_DDIV_3: |
4654 | dbl = 1; | |
4655 | case M_DIV_3: | |
4656 | s = "mflo"; | |
4657 | goto do_div3; | |
4658 | case M_DREM_3: | |
4659 | dbl = 1; | |
4660 | case M_REM_3: | |
4661 | s = "mfhi"; | |
4662 | do_div3: | |
4663 | if (treg == 0) | |
4664 | { | |
4665 | as_warn (_("Divide by zero.")); | |
4666 | if (mips_trap) | |
67c0d1eb | 4667 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4668 | else |
67c0d1eb | 4669 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4670 | break; |
252b5132 RH |
4671 | } |
4672 | ||
7d10b47d | 4673 | start_noreorder (); |
252b5132 RH |
4674 | if (mips_trap) |
4675 | { | |
67c0d1eb RS |
4676 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4677 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4678 | } |
4679 | else | |
4680 | { | |
4681 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4682 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4683 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4684 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4685 | } |
4686 | expr1.X_add_number = -1; | |
8fc2e39e | 4687 | used_at = 1; |
f6a22291 | 4688 | load_register (AT, &expr1, dbl); |
252b5132 | 4689 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4690 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4691 | if (dbl) |
4692 | { | |
4693 | expr1.X_add_number = 1; | |
f6a22291 | 4694 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4695 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4696 | } |
4697 | else | |
4698 | { | |
4699 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4700 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4701 | } |
4702 | if (mips_trap) | |
4703 | { | |
67c0d1eb | 4704 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4705 | /* We want to close the noreorder block as soon as possible, so |
4706 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4707 | end_noreorder (); |
252b5132 RH |
4708 | } |
4709 | else | |
4710 | { | |
4711 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4712 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4713 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4714 | |
4715 | /* We want to close the noreorder block as soon as possible, so | |
4716 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4717 | end_noreorder (); |
252b5132 | 4718 | |
67c0d1eb | 4719 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4720 | } |
67c0d1eb | 4721 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4722 | break; |
4723 | ||
4724 | case M_DIV_3I: | |
4725 | s = "div"; | |
4726 | s2 = "mflo"; | |
4727 | goto do_divi; | |
4728 | case M_DIVU_3I: | |
4729 | s = "divu"; | |
4730 | s2 = "mflo"; | |
4731 | goto do_divi; | |
4732 | case M_REM_3I: | |
4733 | s = "div"; | |
4734 | s2 = "mfhi"; | |
4735 | goto do_divi; | |
4736 | case M_REMU_3I: | |
4737 | s = "divu"; | |
4738 | s2 = "mfhi"; | |
4739 | goto do_divi; | |
4740 | case M_DDIV_3I: | |
4741 | dbl = 1; | |
4742 | s = "ddiv"; | |
4743 | s2 = "mflo"; | |
4744 | goto do_divi; | |
4745 | case M_DDIVU_3I: | |
4746 | dbl = 1; | |
4747 | s = "ddivu"; | |
4748 | s2 = "mflo"; | |
4749 | goto do_divi; | |
4750 | case M_DREM_3I: | |
4751 | dbl = 1; | |
4752 | s = "ddiv"; | |
4753 | s2 = "mfhi"; | |
4754 | goto do_divi; | |
4755 | case M_DREMU_3I: | |
4756 | dbl = 1; | |
4757 | s = "ddivu"; | |
4758 | s2 = "mfhi"; | |
4759 | do_divi: | |
4760 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4761 | { | |
4762 | as_warn (_("Divide by zero.")); | |
4763 | if (mips_trap) | |
67c0d1eb | 4764 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4765 | else |
67c0d1eb | 4766 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4767 | break; |
252b5132 RH |
4768 | } |
4769 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4770 | { | |
4771 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4772 | move_register (dreg, sreg); |
252b5132 | 4773 | else |
67c0d1eb | 4774 | move_register (dreg, 0); |
8fc2e39e | 4775 | break; |
252b5132 RH |
4776 | } |
4777 | if (imm_expr.X_op == O_constant | |
4778 | && imm_expr.X_add_number == -1 | |
4779 | && s[strlen (s) - 1] != 'u') | |
4780 | { | |
4781 | if (strcmp (s2, "mflo") == 0) | |
4782 | { | |
67c0d1eb | 4783 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4784 | } |
4785 | else | |
67c0d1eb | 4786 | move_register (dreg, 0); |
8fc2e39e | 4787 | break; |
252b5132 RH |
4788 | } |
4789 | ||
8fc2e39e | 4790 | used_at = 1; |
67c0d1eb RS |
4791 | load_register (AT, &imm_expr, dbl); |
4792 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4793 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4794 | break; |
4795 | ||
4796 | case M_DIVU_3: | |
4797 | s = "divu"; | |
4798 | s2 = "mflo"; | |
4799 | goto do_divu3; | |
4800 | case M_REMU_3: | |
4801 | s = "divu"; | |
4802 | s2 = "mfhi"; | |
4803 | goto do_divu3; | |
4804 | case M_DDIVU_3: | |
4805 | s = "ddivu"; | |
4806 | s2 = "mflo"; | |
4807 | goto do_divu3; | |
4808 | case M_DREMU_3: | |
4809 | s = "ddivu"; | |
4810 | s2 = "mfhi"; | |
4811 | do_divu3: | |
7d10b47d | 4812 | start_noreorder (); |
252b5132 RH |
4813 | if (mips_trap) |
4814 | { | |
67c0d1eb RS |
4815 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4816 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4817 | /* We want to close the noreorder block as soon as possible, so |
4818 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4819 | end_noreorder (); |
252b5132 RH |
4820 | } |
4821 | else | |
4822 | { | |
4823 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4824 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4825 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4826 | |
4827 | /* We want to close the noreorder block as soon as possible, so | |
4828 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4829 | end_noreorder (); |
67c0d1eb | 4830 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4831 | } |
67c0d1eb | 4832 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4833 | break; |
252b5132 | 4834 | |
1abe91b1 MR |
4835 | case M_DLCA_AB: |
4836 | dbl = 1; | |
4837 | case M_LCA_AB: | |
4838 | call = 1; | |
4839 | goto do_la; | |
252b5132 RH |
4840 | case M_DLA_AB: |
4841 | dbl = 1; | |
4842 | case M_LA_AB: | |
1abe91b1 | 4843 | do_la: |
252b5132 RH |
4844 | /* Load the address of a symbol into a register. If breg is not |
4845 | zero, we then add a base register to it. */ | |
4846 | ||
3bec30a8 TS |
4847 | if (dbl && HAVE_32BIT_GPRS) |
4848 | as_warn (_("dla used to load 32-bit register")); | |
4849 | ||
c90bbe5b | 4850 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4851 | as_warn (_("la used to load 64-bit address")); |
4852 | ||
0c11417f MR |
4853 | if (offset_expr.X_op == O_constant |
4854 | && offset_expr.X_add_number >= -0x8000 | |
4855 | && offset_expr.X_add_number < 0x8000) | |
4856 | { | |
aed1a261 | 4857 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4858 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4859 | break; |
0c11417f MR |
4860 | } |
4861 | ||
b8285c27 | 4862 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4863 | { |
4864 | tempreg = AT; | |
4865 | used_at = 1; | |
4866 | } | |
4867 | else | |
4868 | { | |
4869 | tempreg = treg; | |
afdbd6d0 CD |
4870 | } |
4871 | ||
252b5132 RH |
4872 | if (offset_expr.X_op != O_symbol |
4873 | && offset_expr.X_op != O_constant) | |
4874 | { | |
4875 | as_bad (_("expression too complex")); | |
4876 | offset_expr.X_op = O_constant; | |
4877 | } | |
4878 | ||
252b5132 | 4879 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4880 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4881 | else if (mips_pic == NO_PIC) |
4882 | { | |
d6bc6245 | 4883 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4884 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4885 | Otherwise we want |
4886 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4887 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4888 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4889 | so we may as well always use the latter form. |
76b3015f | 4890 | |
6caf9ef4 TS |
4891 | With 64bit address space and a usable $at we want |
4892 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4893 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4894 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4895 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4896 | dsll32 $tempreg,0 | |
4897 | daddu $tempreg,$tempreg,$at | |
4898 | ||
4899 | If $at is already in use, we use a path which is suboptimal | |
4900 | on superscalar processors. | |
4901 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4902 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4903 | dsll $tempreg,16 | |
4904 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4905 | dsll $tempreg,16 | |
4906 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4907 | ||
4908 | For GP relative symbols in 64bit address space we can use | |
4909 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4910 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4911 | { |
6caf9ef4 TS |
4912 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4913 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4914 | { | |
4915 | relax_start (offset_expr.X_add_symbol); | |
4916 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4917 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4918 | relax_switch (); | |
4919 | } | |
d6bc6245 | 4920 | |
b8285c27 | 4921 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4922 | { |
67c0d1eb | 4923 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4924 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4925 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4926 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4927 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4928 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4929 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4930 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4931 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4932 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4933 | used_at = 1; |
4934 | } | |
4935 | else | |
4936 | { | |
67c0d1eb | 4937 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4938 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4939 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4940 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4941 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4942 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4943 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4944 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4945 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4946 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4947 | } |
6caf9ef4 TS |
4948 | |
4949 | if (mips_relax.sequence) | |
4950 | relax_end (); | |
98d3f06f KH |
4951 | } |
4952 | else | |
4953 | { | |
4954 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4955 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4956 | { |
4d7206a2 | 4957 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4958 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4959 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4960 | relax_switch (); |
98d3f06f | 4961 | } |
6943caf0 ILT |
4962 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4963 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4964 | macro_build_lui (&offset_expr, tempreg); |
4965 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4966 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4967 | if (mips_relax.sequence) |
4968 | relax_end (); | |
98d3f06f | 4969 | } |
252b5132 | 4970 | } |
f5040a92 | 4971 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4972 | { |
9117d219 NC |
4973 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4974 | ||
252b5132 RH |
4975 | /* If this is a reference to an external symbol, and there |
4976 | is no constant, we want | |
4977 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4978 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4979 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4980 | For a local symbol, we want |
4981 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4982 | nop | |
4983 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4984 | ||
4985 | If we have a small constant, and this is a reference to | |
4986 | an external symbol, we want | |
4987 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4988 | nop | |
4989 | addiu $tempreg,$tempreg,<constant> | |
4990 | For a local symbol, we want the same instruction | |
4991 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4992 | addiu instruction. | |
4993 | ||
4994 | If we have a large constant, and this is a reference to | |
4995 | an external symbol, we want | |
4996 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4997 | lui $at,<hiconstant> | |
4998 | addiu $at,$at,<loconstant> | |
4999 | addu $tempreg,$tempreg,$at | |
5000 | For a local symbol, we want the same instruction | |
5001 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5002 | addiu instruction. |
ed6fb7bd SC |
5003 | */ |
5004 | ||
4d7206a2 | 5005 | if (offset_expr.X_add_number == 0) |
252b5132 | 5006 | { |
4d7206a2 RS |
5007 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5008 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5009 | ||
5010 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5012 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5013 | if (breg != 0) |
252b5132 RH |
5014 | { |
5015 | /* We're going to put in an addu instruction using | |
5016 | tempreg, so we may as well insert the nop right | |
5017 | now. */ | |
269137b2 | 5018 | load_delay_nop (); |
252b5132 | 5019 | } |
4d7206a2 | 5020 | relax_switch (); |
67c0d1eb RS |
5021 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5022 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5023 | load_delay_nop (); |
67c0d1eb RS |
5024 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5025 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5026 | relax_end (); |
252b5132 RH |
5027 | /* FIXME: If breg == 0, and the next instruction uses |
5028 | $tempreg, then if this variant case is used an extra | |
5029 | nop will be generated. */ | |
5030 | } | |
4d7206a2 RS |
5031 | else if (offset_expr.X_add_number >= -0x8000 |
5032 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5033 | { |
67c0d1eb | 5034 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5035 | load_delay_nop (); |
67c0d1eb | 5036 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5037 | } |
5038 | else | |
5039 | { | |
4d7206a2 RS |
5040 | expr1.X_add_number = offset_expr.X_add_number; |
5041 | offset_expr.X_add_number = | |
5042 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5043 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5044 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5045 | /* If we are going to add in a base register, and the |
5046 | target register and the base register are the same, | |
5047 | then we are using AT as a temporary register. Since | |
5048 | we want to load the constant into AT, we add our | |
5049 | current AT (from the global offset table) and the | |
5050 | register into the register now, and pretend we were | |
5051 | not using a base register. */ | |
67c0d1eb | 5052 | if (breg == treg) |
252b5132 | 5053 | { |
269137b2 | 5054 | load_delay_nop (); |
67c0d1eb | 5055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5056 | treg, AT, breg); |
252b5132 RH |
5057 | breg = 0; |
5058 | tempreg = treg; | |
252b5132 | 5059 | } |
f6a22291 | 5060 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5061 | used_at = 1; |
5062 | } | |
5063 | } | |
f5040a92 AO |
5064 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5065 | { | |
67c0d1eb | 5066 | int add_breg_early = 0; |
f5040a92 AO |
5067 | |
5068 | /* If this is a reference to an external, and there is no | |
5069 | constant, or local symbol (*), with or without a | |
5070 | constant, we want | |
5071 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5072 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5074 | ||
5075 | If we have a small constant, and this is a reference to | |
5076 | an external symbol, we want | |
5077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5078 | addiu $tempreg,$tempreg,<constant> | |
5079 | ||
5080 | If we have a large constant, and this is a reference to | |
5081 | an external symbol, we want | |
5082 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5083 | lui $at,<hiconstant> | |
5084 | addiu $at,$at,<loconstant> | |
5085 | addu $tempreg,$tempreg,$at | |
5086 | ||
5087 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5088 | local symbols, even though it introduces an additional | |
5089 | instruction. */ | |
5090 | ||
f5040a92 AO |
5091 | if (offset_expr.X_add_number) |
5092 | { | |
4d7206a2 | 5093 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5094 | offset_expr.X_add_number = 0; |
5095 | ||
4d7206a2 | 5096 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5097 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5098 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5099 | |
5100 | if (expr1.X_add_number >= -0x8000 | |
5101 | && expr1.X_add_number < 0x8000) | |
5102 | { | |
67c0d1eb RS |
5103 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5104 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5105 | } |
ecd13cd3 | 5106 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5107 | { |
5108 | int dreg; | |
5109 | ||
5110 | /* If we are going to add in a base register, and the | |
5111 | target register and the base register are the same, | |
5112 | then we are using AT as a temporary register. Since | |
5113 | we want to load the constant into AT, we add our | |
5114 | current AT (from the global offset table) and the | |
5115 | register into the register now, and pretend we were | |
5116 | not using a base register. */ | |
5117 | if (breg != treg) | |
5118 | dreg = tempreg; | |
5119 | else | |
5120 | { | |
5121 | assert (tempreg == AT); | |
67c0d1eb RS |
5122 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5123 | treg, AT, breg); | |
f5040a92 | 5124 | dreg = treg; |
67c0d1eb | 5125 | add_breg_early = 1; |
f5040a92 AO |
5126 | } |
5127 | ||
f6a22291 | 5128 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5130 | dreg, dreg, AT); |
f5040a92 | 5131 | |
f5040a92 AO |
5132 | used_at = 1; |
5133 | } | |
5134 | else | |
5135 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5136 | ||
4d7206a2 | 5137 | relax_switch (); |
f5040a92 AO |
5138 | offset_expr.X_add_number = expr1.X_add_number; |
5139 | ||
67c0d1eb RS |
5140 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5141 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5142 | if (add_breg_early) | |
f5040a92 | 5143 | { |
67c0d1eb | 5144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5145 | treg, tempreg, breg); |
f5040a92 AO |
5146 | breg = 0; |
5147 | tempreg = treg; | |
5148 | } | |
4d7206a2 | 5149 | relax_end (); |
f5040a92 | 5150 | } |
4d7206a2 | 5151 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5152 | { |
4d7206a2 | 5153 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5154 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5155 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5156 | relax_switch (); |
67c0d1eb RS |
5157 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5158 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5159 | relax_end (); |
f5040a92 | 5160 | } |
4d7206a2 | 5161 | else |
f5040a92 | 5162 | { |
67c0d1eb RS |
5163 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5164 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5165 | } |
5166 | } | |
5167 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5168 | { |
67c0d1eb | 5169 | int gpdelay; |
9117d219 NC |
5170 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5171 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5172 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5173 | |
5174 | /* This is the large GOT case. If this is a reference to an | |
5175 | external symbol, and there is no constant, we want | |
5176 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5177 | addu $tempreg,$tempreg,$gp | |
5178 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5179 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5180 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5181 | addu $tempreg,$tempreg,$gp | |
5182 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5183 | For a local symbol, we want |
5184 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5185 | nop | |
5186 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5187 | ||
5188 | If we have a small constant, and this is a reference to | |
5189 | an external symbol, we want | |
5190 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5191 | addu $tempreg,$tempreg,$gp | |
5192 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5193 | nop | |
5194 | addiu $tempreg,$tempreg,<constant> | |
5195 | For a local symbol, we want | |
5196 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5197 | nop | |
5198 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5199 | ||
5200 | If we have a large constant, and this is a reference to | |
5201 | an external symbol, we want | |
5202 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5203 | addu $tempreg,$tempreg,$gp | |
5204 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5205 | lui $at,<hiconstant> | |
5206 | addiu $at,$at,<loconstant> | |
5207 | addu $tempreg,$tempreg,$at | |
5208 | For a local symbol, we want | |
5209 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5210 | lui $at,<hiconstant> | |
5211 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5212 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5213 | */ |
438c16b8 | 5214 | |
252b5132 RH |
5215 | expr1.X_add_number = offset_expr.X_add_number; |
5216 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5217 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5218 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5219 | if (expr1.X_add_number == 0 && breg == 0 |
5220 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5221 | { |
5222 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5223 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5224 | } | |
67c0d1eb RS |
5225 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5227 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5229 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5230 | if (expr1.X_add_number == 0) |
5231 | { | |
67c0d1eb | 5232 | if (breg != 0) |
252b5132 RH |
5233 | { |
5234 | /* We're going to put in an addu instruction using | |
5235 | tempreg, so we may as well insert the nop right | |
5236 | now. */ | |
269137b2 | 5237 | load_delay_nop (); |
252b5132 | 5238 | } |
252b5132 RH |
5239 | } |
5240 | else if (expr1.X_add_number >= -0x8000 | |
5241 | && expr1.X_add_number < 0x8000) | |
5242 | { | |
269137b2 | 5243 | load_delay_nop (); |
67c0d1eb | 5244 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5245 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5246 | } |
5247 | else | |
5248 | { | |
67c0d1eb | 5249 | int dreg; |
252b5132 RH |
5250 | |
5251 | /* If we are going to add in a base register, and the | |
5252 | target register and the base register are the same, | |
5253 | then we are using AT as a temporary register. Since | |
5254 | we want to load the constant into AT, we add our | |
5255 | current AT (from the global offset table) and the | |
5256 | register into the register now, and pretend we were | |
5257 | not using a base register. */ | |
5258 | if (breg != treg) | |
67c0d1eb | 5259 | dreg = tempreg; |
252b5132 RH |
5260 | else |
5261 | { | |
5262 | assert (tempreg == AT); | |
269137b2 | 5263 | load_delay_nop (); |
67c0d1eb | 5264 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5265 | treg, AT, breg); |
252b5132 | 5266 | dreg = treg; |
252b5132 RH |
5267 | } |
5268 | ||
f6a22291 | 5269 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5270 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5271 | |
252b5132 RH |
5272 | used_at = 1; |
5273 | } | |
4d7206a2 RS |
5274 | offset_expr.X_add_number = |
5275 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5276 | relax_switch (); | |
252b5132 | 5277 | |
67c0d1eb | 5278 | if (gpdelay) |
252b5132 RH |
5279 | { |
5280 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5281 | the first instruction on the main stream does not. */ |
67c0d1eb | 5282 | macro_build (NULL, "nop", ""); |
252b5132 | 5283 | } |
ed6fb7bd | 5284 | |
67c0d1eb RS |
5285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5286 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5287 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5288 | && expr1.X_add_number < 0x8000) |
5289 | { | |
269137b2 | 5290 | load_delay_nop (); |
67c0d1eb RS |
5291 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5292 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5293 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5294 | register, the external symbol case ended with a load, |
5295 | so if the symbol turns out to not be external, and | |
5296 | the next instruction uses tempreg, an unnecessary nop | |
5297 | will be inserted. */ | |
252b5132 RH |
5298 | } |
5299 | else | |
5300 | { | |
5301 | if (breg == treg) | |
5302 | { | |
5303 | /* We must add in the base register now, as in the | |
f5040a92 | 5304 | external symbol case. */ |
252b5132 | 5305 | assert (tempreg == AT); |
269137b2 | 5306 | load_delay_nop (); |
67c0d1eb | 5307 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5308 | treg, AT, breg); |
252b5132 RH |
5309 | tempreg = treg; |
5310 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5311 | it in in both cases. */ |
252b5132 RH |
5312 | breg = 0; |
5313 | } | |
5314 | ||
67c0d1eb RS |
5315 | macro_build_lui (&expr1, AT); |
5316 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5317 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5318 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5319 | tempreg, tempreg, AT); |
8fc2e39e | 5320 | used_at = 1; |
252b5132 | 5321 | } |
4d7206a2 | 5322 | relax_end (); |
252b5132 | 5323 | } |
f5040a92 AO |
5324 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5325 | { | |
f5040a92 AO |
5326 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5327 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5328 | int add_breg_early = 0; |
f5040a92 AO |
5329 | |
5330 | /* This is the large GOT case. If this is a reference to an | |
5331 | external symbol, and there is no constant, we want | |
5332 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5333 | add $tempreg,$tempreg,$gp | |
5334 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5335 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5336 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5337 | add $tempreg,$tempreg,$gp | |
5338 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5339 | ||
5340 | If we have a small constant, and this is a reference to | |
5341 | an external symbol, we want | |
5342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5343 | add $tempreg,$tempreg,$gp | |
5344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5345 | addi $tempreg,$tempreg,<constant> | |
5346 | ||
5347 | If we have a large constant, and this is a reference to | |
5348 | an external symbol, we want | |
5349 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5350 | addu $tempreg,$tempreg,$gp | |
5351 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5352 | lui $at,<hiconstant> | |
5353 | addi $at,$at,<loconstant> | |
5354 | add $tempreg,$tempreg,$at | |
5355 | ||
5356 | If we have NewABI, and we know it's a local symbol, we want | |
5357 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5358 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5359 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5360 | ||
4d7206a2 | 5361 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5362 | |
4d7206a2 | 5363 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5364 | offset_expr.X_add_number = 0; |
5365 | ||
1abe91b1 MR |
5366 | if (expr1.X_add_number == 0 && breg == 0 |
5367 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5368 | { |
5369 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5370 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5371 | } | |
67c0d1eb RS |
5372 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5374 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5375 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5376 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5377 | |
5378 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5379 | ; |
f5040a92 AO |
5380 | else if (expr1.X_add_number >= -0x8000 |
5381 | && expr1.X_add_number < 0x8000) | |
5382 | { | |
67c0d1eb | 5383 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5384 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5385 | } |
ecd13cd3 | 5386 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5387 | { |
5388 | int dreg; | |
5389 | ||
5390 | /* If we are going to add in a base register, and the | |
5391 | target register and the base register are the same, | |
5392 | then we are using AT as a temporary register. Since | |
5393 | we want to load the constant into AT, we add our | |
5394 | current AT (from the global offset table) and the | |
5395 | register into the register now, and pretend we were | |
5396 | not using a base register. */ | |
5397 | if (breg != treg) | |
5398 | dreg = tempreg; | |
5399 | else | |
5400 | { | |
5401 | assert (tempreg == AT); | |
67c0d1eb | 5402 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5403 | treg, AT, breg); |
f5040a92 | 5404 | dreg = treg; |
67c0d1eb | 5405 | add_breg_early = 1; |
f5040a92 AO |
5406 | } |
5407 | ||
f6a22291 | 5408 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5409 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5410 | |
f5040a92 AO |
5411 | used_at = 1; |
5412 | } | |
5413 | else | |
5414 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5415 | ||
4d7206a2 | 5416 | relax_switch (); |
f5040a92 | 5417 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5418 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5419 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5420 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5421 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5422 | if (add_breg_early) | |
f5040a92 | 5423 | { |
67c0d1eb | 5424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5425 | treg, tempreg, breg); |
f5040a92 AO |
5426 | breg = 0; |
5427 | tempreg = treg; | |
5428 | } | |
4d7206a2 | 5429 | relax_end (); |
f5040a92 | 5430 | } |
252b5132 RH |
5431 | else |
5432 | abort (); | |
5433 | ||
5434 | if (breg != 0) | |
aed1a261 | 5435 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5436 | break; |
5437 | ||
5438 | case M_J_A: | |
5439 | /* The j instruction may not be used in PIC code, since it | |
5440 | requires an absolute address. We convert it to a b | |
5441 | instruction. */ | |
5442 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5443 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5444 | else |
67c0d1eb | 5445 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5446 | break; |
252b5132 RH |
5447 | |
5448 | /* The jal instructions must be handled as macros because when | |
5449 | generating PIC code they expand to multi-instruction | |
5450 | sequences. Normally they are simple instructions. */ | |
5451 | case M_JAL_1: | |
5452 | dreg = RA; | |
5453 | /* Fall through. */ | |
5454 | case M_JAL_2: | |
3e722fb5 | 5455 | if (mips_pic == NO_PIC) |
67c0d1eb | 5456 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5457 | else if (mips_pic == SVR4_PIC) |
5458 | { | |
5459 | if (sreg != PIC_CALL_REG) | |
5460 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5461 | |
67c0d1eb | 5462 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5463 | if (! HAVE_NEWABI) |
252b5132 | 5464 | { |
6478892d TS |
5465 | if (mips_cprestore_offset < 0) |
5466 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5467 | else | |
5468 | { | |
7a621144 DJ |
5469 | if (! mips_frame_reg_valid) |
5470 | { | |
5471 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5472 | /* Quiet this warning. */ | |
5473 | mips_frame_reg_valid = 1; | |
5474 | } | |
5475 | if (! mips_cprestore_valid) | |
5476 | { | |
5477 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5478 | /* Quiet this warning. */ | |
5479 | mips_cprestore_valid = 1; | |
5480 | } | |
6478892d | 5481 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5482 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5483 | mips_gp_register, |
256ab948 TS |
5484 | mips_frame_reg, |
5485 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5486 | } |
252b5132 RH |
5487 | } |
5488 | } | |
5489 | else | |
5490 | abort (); | |
5491 | ||
8fc2e39e | 5492 | break; |
252b5132 RH |
5493 | |
5494 | case M_JAL_A: | |
5495 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5496 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5497 | else if (mips_pic == SVR4_PIC) |
5498 | { | |
5499 | /* If this is a reference to an external symbol, and we are | |
5500 | using a small GOT, we want | |
5501 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5502 | nop | |
f9419b05 | 5503 | jalr $ra,$25 |
252b5132 RH |
5504 | nop |
5505 | lw $gp,cprestore($sp) | |
5506 | The cprestore value is set using the .cprestore | |
5507 | pseudo-op. If we are using a big GOT, we want | |
5508 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5509 | addu $25,$25,$gp | |
5510 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5511 | nop | |
f9419b05 | 5512 | jalr $ra,$25 |
252b5132 RH |
5513 | nop |
5514 | lw $gp,cprestore($sp) | |
5515 | If the symbol is not external, we want | |
5516 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5517 | nop | |
5518 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5519 | jalr $ra,$25 |
252b5132 | 5520 | nop |
438c16b8 | 5521 | lw $gp,cprestore($sp) |
f5040a92 AO |
5522 | |
5523 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5524 | sequences above, minus nops, unless the symbol is local, | |
5525 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5526 | GOT_DISP. */ | |
438c16b8 | 5527 | if (HAVE_NEWABI) |
252b5132 | 5528 | { |
f5040a92 AO |
5529 | if (! mips_big_got) |
5530 | { | |
4d7206a2 | 5531 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5532 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5533 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5534 | mips_gp_register); |
4d7206a2 | 5535 | relax_switch (); |
67c0d1eb RS |
5536 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5537 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5538 | mips_gp_register); |
5539 | relax_end (); | |
f5040a92 AO |
5540 | } |
5541 | else | |
5542 | { | |
4d7206a2 | 5543 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5544 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5545 | BFD_RELOC_MIPS_CALL_HI16); | |
5546 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5547 | PIC_CALL_REG, mips_gp_register); | |
5548 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5549 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5550 | PIC_CALL_REG); | |
4d7206a2 | 5551 | relax_switch (); |
67c0d1eb RS |
5552 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5553 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5554 | mips_gp_register); | |
5555 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5556 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5557 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5558 | relax_end (); |
f5040a92 | 5559 | } |
684022ea | 5560 | |
67c0d1eb | 5561 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5562 | } |
5563 | else | |
5564 | { | |
4d7206a2 | 5565 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5566 | if (! mips_big_got) |
5567 | { | |
67c0d1eb RS |
5568 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5569 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5570 | mips_gp_register); |
269137b2 | 5571 | load_delay_nop (); |
4d7206a2 | 5572 | relax_switch (); |
438c16b8 | 5573 | } |
252b5132 | 5574 | else |
252b5132 | 5575 | { |
67c0d1eb RS |
5576 | int gpdelay; |
5577 | ||
5578 | gpdelay = reg_needs_delay (mips_gp_register); | |
5579 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5580 | BFD_RELOC_MIPS_CALL_HI16); | |
5581 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5582 | PIC_CALL_REG, mips_gp_register); | |
5583 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5584 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5585 | PIC_CALL_REG); | |
269137b2 | 5586 | load_delay_nop (); |
4d7206a2 | 5587 | relax_switch (); |
67c0d1eb RS |
5588 | if (gpdelay) |
5589 | macro_build (NULL, "nop", ""); | |
252b5132 | 5590 | } |
67c0d1eb RS |
5591 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5592 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5593 | mips_gp_register); |
269137b2 | 5594 | load_delay_nop (); |
67c0d1eb RS |
5595 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5596 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5597 | relax_end (); |
67c0d1eb | 5598 | macro_build_jalr (&offset_expr); |
438c16b8 | 5599 | |
6478892d TS |
5600 | if (mips_cprestore_offset < 0) |
5601 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5602 | else | |
5603 | { | |
7a621144 DJ |
5604 | if (! mips_frame_reg_valid) |
5605 | { | |
5606 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5607 | /* Quiet this warning. */ | |
5608 | mips_frame_reg_valid = 1; | |
5609 | } | |
5610 | if (! mips_cprestore_valid) | |
5611 | { | |
5612 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5613 | /* Quiet this warning. */ | |
5614 | mips_cprestore_valid = 1; | |
5615 | } | |
6478892d | 5616 | if (mips_opts.noreorder) |
67c0d1eb | 5617 | macro_build (NULL, "nop", ""); |
6478892d | 5618 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5619 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5620 | mips_gp_register, |
256ab948 TS |
5621 | mips_frame_reg, |
5622 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5623 | } |
252b5132 RH |
5624 | } |
5625 | } | |
252b5132 RH |
5626 | else |
5627 | abort (); | |
5628 | ||
8fc2e39e | 5629 | break; |
252b5132 RH |
5630 | |
5631 | case M_LB_AB: | |
5632 | s = "lb"; | |
5633 | goto ld; | |
5634 | case M_LBU_AB: | |
5635 | s = "lbu"; | |
5636 | goto ld; | |
5637 | case M_LH_AB: | |
5638 | s = "lh"; | |
5639 | goto ld; | |
5640 | case M_LHU_AB: | |
5641 | s = "lhu"; | |
5642 | goto ld; | |
5643 | case M_LW_AB: | |
5644 | s = "lw"; | |
5645 | goto ld; | |
5646 | case M_LWC0_AB: | |
5647 | s = "lwc0"; | |
bdaaa2e1 | 5648 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5649 | coproc = 1; |
5650 | goto ld; | |
5651 | case M_LWC1_AB: | |
5652 | s = "lwc1"; | |
bdaaa2e1 | 5653 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5654 | coproc = 1; |
5655 | goto ld; | |
5656 | case M_LWC2_AB: | |
5657 | s = "lwc2"; | |
bdaaa2e1 | 5658 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5659 | coproc = 1; |
5660 | goto ld; | |
5661 | case M_LWC3_AB: | |
5662 | s = "lwc3"; | |
bdaaa2e1 | 5663 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5664 | coproc = 1; |
5665 | goto ld; | |
5666 | case M_LWL_AB: | |
5667 | s = "lwl"; | |
5668 | lr = 1; | |
5669 | goto ld; | |
5670 | case M_LWR_AB: | |
5671 | s = "lwr"; | |
5672 | lr = 1; | |
5673 | goto ld; | |
5674 | case M_LDC1_AB: | |
fef14a42 | 5675 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5676 | { |
5677 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5678 | break; |
252b5132 RH |
5679 | } |
5680 | s = "ldc1"; | |
bdaaa2e1 | 5681 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5682 | coproc = 1; |
5683 | goto ld; | |
5684 | case M_LDC2_AB: | |
5685 | s = "ldc2"; | |
bdaaa2e1 | 5686 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5687 | coproc = 1; |
5688 | goto ld; | |
5689 | case M_LDC3_AB: | |
5690 | s = "ldc3"; | |
bdaaa2e1 | 5691 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5692 | coproc = 1; |
5693 | goto ld; | |
5694 | case M_LDL_AB: | |
5695 | s = "ldl"; | |
5696 | lr = 1; | |
5697 | goto ld; | |
5698 | case M_LDR_AB: | |
5699 | s = "ldr"; | |
5700 | lr = 1; | |
5701 | goto ld; | |
5702 | case M_LL_AB: | |
5703 | s = "ll"; | |
5704 | goto ld; | |
5705 | case M_LLD_AB: | |
5706 | s = "lld"; | |
5707 | goto ld; | |
5708 | case M_LWU_AB: | |
5709 | s = "lwu"; | |
5710 | ld: | |
8fc2e39e | 5711 | if (breg == treg || coproc || lr) |
252b5132 RH |
5712 | { |
5713 | tempreg = AT; | |
5714 | used_at = 1; | |
5715 | } | |
5716 | else | |
5717 | { | |
5718 | tempreg = treg; | |
252b5132 RH |
5719 | } |
5720 | goto ld_st; | |
5721 | case M_SB_AB: | |
5722 | s = "sb"; | |
5723 | goto st; | |
5724 | case M_SH_AB: | |
5725 | s = "sh"; | |
5726 | goto st; | |
5727 | case M_SW_AB: | |
5728 | s = "sw"; | |
5729 | goto st; | |
5730 | case M_SWC0_AB: | |
5731 | s = "swc0"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto st; | |
5735 | case M_SWC1_AB: | |
5736 | s = "swc1"; | |
bdaaa2e1 | 5737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5738 | coproc = 1; |
5739 | goto st; | |
5740 | case M_SWC2_AB: | |
5741 | s = "swc2"; | |
bdaaa2e1 | 5742 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5743 | coproc = 1; |
5744 | goto st; | |
5745 | case M_SWC3_AB: | |
5746 | s = "swc3"; | |
bdaaa2e1 | 5747 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5748 | coproc = 1; |
5749 | goto st; | |
5750 | case M_SWL_AB: | |
5751 | s = "swl"; | |
5752 | goto st; | |
5753 | case M_SWR_AB: | |
5754 | s = "swr"; | |
5755 | goto st; | |
5756 | case M_SC_AB: | |
5757 | s = "sc"; | |
5758 | goto st; | |
5759 | case M_SCD_AB: | |
5760 | s = "scd"; | |
5761 | goto st; | |
5762 | case M_SDC1_AB: | |
fef14a42 | 5763 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5764 | { |
5765 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5766 | break; |
252b5132 RH |
5767 | } |
5768 | s = "sdc1"; | |
5769 | coproc = 1; | |
bdaaa2e1 | 5770 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5771 | goto st; |
5772 | case M_SDC2_AB: | |
5773 | s = "sdc2"; | |
bdaaa2e1 | 5774 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5775 | coproc = 1; |
5776 | goto st; | |
5777 | case M_SDC3_AB: | |
5778 | s = "sdc3"; | |
bdaaa2e1 | 5779 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5780 | coproc = 1; |
5781 | goto st; | |
5782 | case M_SDL_AB: | |
5783 | s = "sdl"; | |
5784 | goto st; | |
5785 | case M_SDR_AB: | |
5786 | s = "sdr"; | |
5787 | st: | |
8fc2e39e TS |
5788 | tempreg = AT; |
5789 | used_at = 1; | |
252b5132 | 5790 | ld_st: |
bdaaa2e1 | 5791 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5792 | if (mask == M_LWC1_AB |
5793 | || mask == M_SWC1_AB | |
5794 | || mask == M_LDC1_AB | |
5795 | || mask == M_SDC1_AB | |
5796 | || mask == M_L_DAB | |
5797 | || mask == M_S_DAB) | |
5798 | fmt = "T,o(b)"; | |
5799 | else if (coproc) | |
5800 | fmt = "E,o(b)"; | |
5801 | else | |
5802 | fmt = "t,o(b)"; | |
5803 | ||
5804 | if (offset_expr.X_op != O_constant | |
5805 | && offset_expr.X_op != O_symbol) | |
5806 | { | |
5807 | as_bad (_("expression too complex")); | |
5808 | offset_expr.X_op = O_constant; | |
5809 | } | |
5810 | ||
2051e8c4 MR |
5811 | if (HAVE_32BIT_ADDRESSES |
5812 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
5813 | { |
5814 | char value [32]; | |
5815 | ||
5816 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 5817 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 5818 | } |
2051e8c4 | 5819 | |
252b5132 RH |
5820 | /* A constant expression in PIC code can be handled just as it |
5821 | is in non PIC code. */ | |
aed1a261 RS |
5822 | if (offset_expr.X_op == O_constant) |
5823 | { | |
aed1a261 RS |
5824 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
5825 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 5826 | normalize_address_expr (&expr1); |
aed1a261 RS |
5827 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
5828 | if (breg != 0) | |
5829 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5830 | tempreg, tempreg, breg); | |
5831 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5832 | } | |
5833 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5834 | { |
5835 | /* If this is a reference to a GP relative symbol, and there | |
5836 | is no base register, we want | |
cdf6fd85 | 5837 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5838 | Otherwise, if there is no base register, we want |
5839 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5840 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5841 | If we have a constant, we need two instructions anyhow, | |
5842 | so we always use the latter form. | |
5843 | ||
5844 | If we have a base register, and this is a reference to a | |
5845 | GP relative symbol, we want | |
5846 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5847 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5848 | Otherwise we want |
5849 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5850 | addu $tempreg,$tempreg,$breg | |
5851 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5852 | With a constant we always use the latter case. |
76b3015f | 5853 | |
d6bc6245 TS |
5854 | With 64bit address space and no base register and $at usable, |
5855 | we want | |
5856 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5857 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5858 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5859 | dsll32 $tempreg,0 | |
5860 | daddu $tempreg,$at | |
5861 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5862 | If we have a base register, we want | |
5863 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5864 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5865 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5866 | daddu $at,$breg | |
5867 | dsll32 $tempreg,0 | |
5868 | daddu $tempreg,$at | |
5869 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5870 | ||
5871 | Without $at we can't generate the optimal path for superscalar | |
5872 | processors here since this would require two temporary registers. | |
5873 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5874 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5875 | dsll $tempreg,16 | |
5876 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5877 | dsll $tempreg,16 | |
5878 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5879 | If we have a base register, we want | |
5880 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5881 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5882 | dsll $tempreg,16 | |
5883 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5884 | dsll $tempreg,16 | |
5885 | daddu $tempreg,$tempreg,$breg | |
5886 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5887 | |
6caf9ef4 | 5888 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5889 | the same sequence as in 32bit address space. */ |
5890 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5891 | { |
aed1a261 | 5892 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5893 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5894 | { | |
5895 | relax_start (offset_expr.X_add_symbol); | |
5896 | if (breg == 0) | |
5897 | { | |
5898 | macro_build (&offset_expr, s, fmt, treg, | |
5899 | BFD_RELOC_GPREL16, mips_gp_register); | |
5900 | } | |
5901 | else | |
5902 | { | |
5903 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5904 | tempreg, breg, mips_gp_register); | |
5905 | macro_build (&offset_expr, s, fmt, treg, | |
5906 | BFD_RELOC_GPREL16, tempreg); | |
5907 | } | |
5908 | relax_switch (); | |
5909 | } | |
d6bc6245 | 5910 | |
b8285c27 | 5911 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5912 | { |
67c0d1eb RS |
5913 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5914 | BFD_RELOC_MIPS_HIGHEST); | |
5915 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5916 | BFD_RELOC_HI16_S); | |
5917 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5918 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5919 | if (breg != 0) |
67c0d1eb RS |
5920 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5921 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5922 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5923 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5924 | tempreg); | |
d6bc6245 TS |
5925 | used_at = 1; |
5926 | } | |
5927 | else | |
5928 | { | |
67c0d1eb RS |
5929 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5930 | BFD_RELOC_MIPS_HIGHEST); | |
5931 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5932 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5933 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5934 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5935 | tempreg, BFD_RELOC_HI16_S); | |
5936 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5937 | if (breg != 0) |
67c0d1eb | 5938 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5939 | tempreg, tempreg, breg); |
67c0d1eb | 5940 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5941 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5942 | } |
6caf9ef4 TS |
5943 | |
5944 | if (mips_relax.sequence) | |
5945 | relax_end (); | |
8fc2e39e | 5946 | break; |
d6bc6245 | 5947 | } |
256ab948 | 5948 | |
252b5132 RH |
5949 | if (breg == 0) |
5950 | { | |
67c0d1eb | 5951 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5952 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5953 | { |
4d7206a2 | 5954 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5955 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5956 | mips_gp_register); | |
4d7206a2 | 5957 | relax_switch (); |
252b5132 | 5958 | } |
67c0d1eb RS |
5959 | macro_build_lui (&offset_expr, tempreg); |
5960 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5961 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5962 | if (mips_relax.sequence) |
5963 | relax_end (); | |
252b5132 RH |
5964 | } |
5965 | else | |
5966 | { | |
67c0d1eb | 5967 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5968 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5969 | { |
4d7206a2 | 5970 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5971 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5972 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5973 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5974 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5975 | relax_switch (); |
252b5132 | 5976 | } |
67c0d1eb RS |
5977 | macro_build_lui (&offset_expr, tempreg); |
5978 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5979 | tempreg, tempreg, breg); |
67c0d1eb | 5980 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5981 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5982 | if (mips_relax.sequence) |
5983 | relax_end (); | |
252b5132 RH |
5984 | } |
5985 | } | |
5986 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5987 | { | |
ed6fb7bd | 5988 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5989 | |
252b5132 RH |
5990 | /* If this is a reference to an external symbol, we want |
5991 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5992 | nop | |
5993 | <op> $treg,0($tempreg) | |
5994 | Otherwise we want | |
5995 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5996 | nop | |
5997 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5998 | <op> $treg,0($tempreg) | |
f5040a92 AO |
5999 | |
6000 | For NewABI, we want | |
6001 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6002 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6003 | ||
252b5132 RH |
6004 | If there is a base register, we add it to $tempreg before |
6005 | the <op>. If there is a constant, we stick it in the | |
6006 | <op> instruction. We don't handle constants larger than | |
6007 | 16 bits, because we have no way to load the upper 16 bits | |
6008 | (actually, we could handle them for the subset of cases | |
6009 | in which we are not using $at). */ | |
6010 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6011 | if (HAVE_NEWABI) |
6012 | { | |
67c0d1eb RS |
6013 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6014 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6015 | if (breg != 0) |
67c0d1eb | 6016 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6017 | tempreg, tempreg, breg); |
67c0d1eb | 6018 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6019 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6020 | break; |
6021 | } | |
252b5132 RH |
6022 | expr1.X_add_number = offset_expr.X_add_number; |
6023 | offset_expr.X_add_number = 0; | |
6024 | if (expr1.X_add_number < -0x8000 | |
6025 | || expr1.X_add_number >= 0x8000) | |
6026 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6027 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6028 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6029 | load_delay_nop (); |
4d7206a2 RS |
6030 | relax_start (offset_expr.X_add_symbol); |
6031 | relax_switch (); | |
67c0d1eb RS |
6032 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6033 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6034 | relax_end (); |
252b5132 | 6035 | if (breg != 0) |
67c0d1eb | 6036 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6037 | tempreg, tempreg, breg); |
67c0d1eb | 6038 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6039 | } |
f5040a92 | 6040 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6041 | { |
67c0d1eb | 6042 | int gpdelay; |
252b5132 RH |
6043 | |
6044 | /* If this is a reference to an external symbol, we want | |
6045 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6046 | addu $tempreg,$tempreg,$gp | |
6047 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6048 | <op> $treg,0($tempreg) | |
6049 | Otherwise we want | |
6050 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6051 | nop | |
6052 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6053 | <op> $treg,0($tempreg) | |
6054 | If there is a base register, we add it to $tempreg before | |
6055 | the <op>. If there is a constant, we stick it in the | |
6056 | <op> instruction. We don't handle constants larger than | |
6057 | 16 bits, because we have no way to load the upper 16 bits | |
6058 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6059 | in which we are not using $at). */ |
252b5132 RH |
6060 | assert (offset_expr.X_op == O_symbol); |
6061 | expr1.X_add_number = offset_expr.X_add_number; | |
6062 | offset_expr.X_add_number = 0; | |
6063 | if (expr1.X_add_number < -0x8000 | |
6064 | || expr1.X_add_number >= 0x8000) | |
6065 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6066 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6067 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6068 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6069 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6070 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6071 | mips_gp_register); | |
6072 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6073 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6074 | relax_switch (); |
67c0d1eb RS |
6075 | if (gpdelay) |
6076 | macro_build (NULL, "nop", ""); | |
6077 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6078 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6079 | load_delay_nop (); |
67c0d1eb RS |
6080 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6081 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6082 | relax_end (); |
6083 | ||
252b5132 | 6084 | if (breg != 0) |
67c0d1eb | 6085 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6086 | tempreg, tempreg, breg); |
67c0d1eb | 6087 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6088 | } |
f5040a92 AO |
6089 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6090 | { | |
f5040a92 AO |
6091 | /* If this is a reference to an external symbol, we want |
6092 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6093 | add $tempreg,$tempreg,$gp | |
6094 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6095 | <op> $treg,<ofst>($tempreg) | |
6096 | Otherwise, for local symbols, we want: | |
6097 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6098 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6099 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6100 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6101 | offset_expr.X_add_number = 0; |
6102 | if (expr1.X_add_number < -0x8000 | |
6103 | || expr1.X_add_number >= 0x8000) | |
6104 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6105 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6106 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6107 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6109 | mips_gp_register); | |
6110 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6111 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6112 | if (breg != 0) |
67c0d1eb | 6113 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6114 | tempreg, tempreg, breg); |
67c0d1eb | 6115 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6116 | |
4d7206a2 | 6117 | relax_switch (); |
f5040a92 | 6118 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6119 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6120 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6121 | if (breg != 0) |
67c0d1eb | 6122 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6123 | tempreg, tempreg, breg); |
67c0d1eb | 6124 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6125 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6126 | relax_end (); |
f5040a92 | 6127 | } |
252b5132 RH |
6128 | else |
6129 | abort (); | |
6130 | ||
252b5132 RH |
6131 | break; |
6132 | ||
6133 | case M_LI: | |
6134 | case M_LI_S: | |
67c0d1eb | 6135 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6136 | break; |
252b5132 RH |
6137 | |
6138 | case M_DLI: | |
67c0d1eb | 6139 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6140 | break; |
252b5132 RH |
6141 | |
6142 | case M_LI_SS: | |
6143 | if (imm_expr.X_op == O_constant) | |
6144 | { | |
8fc2e39e | 6145 | used_at = 1; |
67c0d1eb RS |
6146 | load_register (AT, &imm_expr, 0); |
6147 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6148 | break; |
6149 | } | |
6150 | else | |
6151 | { | |
6152 | assert (offset_expr.X_op == O_symbol | |
6153 | && strcmp (segment_name (S_GET_SEGMENT | |
6154 | (offset_expr.X_add_symbol)), | |
6155 | ".lit4") == 0 | |
6156 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6157 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6158 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6159 | break; |
252b5132 RH |
6160 | } |
6161 | ||
6162 | case M_LI_D: | |
ca4e0257 RS |
6163 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6164 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6165 | order 32 bits of the value and the low order 32 bits are either | |
6166 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6167 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6168 | { | |
ca4e0257 | 6169 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6170 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6171 | else |
6172 | { | |
6173 | int hreg, lreg; | |
6174 | ||
6175 | if (target_big_endian) | |
6176 | { | |
6177 | hreg = treg; | |
6178 | lreg = treg + 1; | |
6179 | } | |
6180 | else | |
6181 | { | |
6182 | hreg = treg + 1; | |
6183 | lreg = treg; | |
6184 | } | |
6185 | ||
6186 | if (hreg <= 31) | |
67c0d1eb | 6187 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6188 | if (lreg <= 31) |
6189 | { | |
6190 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6191 | move_register (lreg, 0); |
252b5132 RH |
6192 | else |
6193 | { | |
6194 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6195 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6196 | } |
6197 | } | |
6198 | } | |
8fc2e39e | 6199 | break; |
252b5132 RH |
6200 | } |
6201 | ||
6202 | /* We know that sym is in the .rdata section. First we get the | |
6203 | upper 16 bits of the address. */ | |
6204 | if (mips_pic == NO_PIC) | |
6205 | { | |
67c0d1eb | 6206 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6207 | used_at = 1; |
252b5132 RH |
6208 | } |
6209 | else if (mips_pic == SVR4_PIC) | |
6210 | { | |
67c0d1eb RS |
6211 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6212 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6213 | used_at = 1; |
252b5132 | 6214 | } |
252b5132 RH |
6215 | else |
6216 | abort (); | |
bdaaa2e1 | 6217 | |
252b5132 | 6218 | /* Now we load the register(s). */ |
ca4e0257 | 6219 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6220 | { |
6221 | used_at = 1; | |
6222 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6223 | } | |
252b5132 RH |
6224 | else |
6225 | { | |
8fc2e39e | 6226 | used_at = 1; |
67c0d1eb | 6227 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6228 | if (treg != RA) |
252b5132 RH |
6229 | { |
6230 | /* FIXME: How in the world do we deal with the possible | |
6231 | overflow here? */ | |
6232 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6233 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6234 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6235 | } |
6236 | } | |
252b5132 RH |
6237 | break; |
6238 | ||
6239 | case M_LI_DD: | |
ca4e0257 RS |
6240 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6241 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6242 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6243 | the value and the low order 32 bits are either zero or in | |
6244 | OFFSET_EXPR. */ | |
252b5132 RH |
6245 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6246 | { | |
8fc2e39e | 6247 | used_at = 1; |
67c0d1eb | 6248 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6249 | if (HAVE_64BIT_FPRS) |
6250 | { | |
6251 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6252 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6253 | } |
252b5132 RH |
6254 | else |
6255 | { | |
67c0d1eb | 6256 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6257 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6258 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6259 | else |
6260 | { | |
6261 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6262 | load_register (AT, &offset_expr, 0); |
6263 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6264 | } |
6265 | } | |
6266 | break; | |
6267 | } | |
6268 | ||
6269 | assert (offset_expr.X_op == O_symbol | |
6270 | && offset_expr.X_add_number == 0); | |
6271 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6272 | if (strcmp (s, ".lit8") == 0) | |
6273 | { | |
e7af610e | 6274 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6275 | { |
67c0d1eb | 6276 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6277 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6278 | break; |
252b5132 | 6279 | } |
c9914766 | 6280 | breg = mips_gp_register; |
252b5132 RH |
6281 | r = BFD_RELOC_MIPS_LITERAL; |
6282 | goto dob; | |
6283 | } | |
6284 | else | |
6285 | { | |
6286 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6287 | used_at = 1; |
252b5132 | 6288 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6289 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6290 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6291 | else |
6292 | { | |
6293 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6294 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6295 | } |
bdaaa2e1 | 6296 | |
e7af610e | 6297 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6298 | { |
67c0d1eb RS |
6299 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6300 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6301 | break; |
6302 | } | |
6303 | breg = AT; | |
6304 | r = BFD_RELOC_LO16; | |
6305 | goto dob; | |
6306 | } | |
6307 | ||
6308 | case M_L_DOB: | |
fef14a42 | 6309 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6310 | { |
6311 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6312 | break; |
252b5132 RH |
6313 | } |
6314 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6315 | to adjust when loading from memory. */ | |
6316 | r = BFD_RELOC_LO16; | |
6317 | dob: | |
e7af610e | 6318 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6319 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6320 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6321 | /* FIXME: A possible overflow which I don't know how to deal |
6322 | with. */ | |
6323 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6324 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6325 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6326 | break; |
6327 | ||
6328 | case M_L_DAB: | |
6329 | /* | |
6330 | * The MIPS assembler seems to check for X_add_number not | |
6331 | * being double aligned and generating: | |
6332 | * lui at,%hi(foo+1) | |
6333 | * addu at,at,v1 | |
6334 | * addiu at,at,%lo(foo+1) | |
6335 | * lwc1 f2,0(at) | |
6336 | * lwc1 f3,4(at) | |
6337 | * But, the resulting address is the same after relocation so why | |
6338 | * generate the extra instruction? | |
6339 | */ | |
fef14a42 | 6340 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6341 | { |
6342 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6343 | break; |
252b5132 | 6344 | } |
bdaaa2e1 | 6345 | /* Itbl support may require additional care here. */ |
252b5132 | 6346 | coproc = 1; |
e7af610e | 6347 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6348 | { |
6349 | s = "ldc1"; | |
6350 | goto ld; | |
6351 | } | |
6352 | ||
6353 | s = "lwc1"; | |
6354 | fmt = "T,o(b)"; | |
6355 | goto ldd_std; | |
6356 | ||
6357 | case M_S_DAB: | |
fef14a42 | 6358 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6359 | { |
6360 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6361 | break; |
252b5132 RH |
6362 | } |
6363 | ||
e7af610e | 6364 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6365 | { |
6366 | s = "sdc1"; | |
6367 | goto st; | |
6368 | } | |
6369 | ||
6370 | s = "swc1"; | |
6371 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6372 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6373 | coproc = 1; |
6374 | goto ldd_std; | |
6375 | ||
6376 | case M_LD_AB: | |
ca4e0257 | 6377 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6378 | { |
6379 | s = "ld"; | |
6380 | goto ld; | |
6381 | } | |
6382 | ||
6383 | s = "lw"; | |
6384 | fmt = "t,o(b)"; | |
6385 | goto ldd_std; | |
6386 | ||
6387 | case M_SD_AB: | |
ca4e0257 | 6388 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6389 | { |
6390 | s = "sd"; | |
6391 | goto st; | |
6392 | } | |
6393 | ||
6394 | s = "sw"; | |
6395 | fmt = "t,o(b)"; | |
6396 | ||
6397 | ldd_std: | |
6398 | if (offset_expr.X_op != O_symbol | |
6399 | && offset_expr.X_op != O_constant) | |
6400 | { | |
6401 | as_bad (_("expression too complex")); | |
6402 | offset_expr.X_op = O_constant; | |
6403 | } | |
6404 | ||
2051e8c4 MR |
6405 | if (HAVE_32BIT_ADDRESSES |
6406 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6407 | { |
6408 | char value [32]; | |
6409 | ||
6410 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6411 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6412 | } |
2051e8c4 | 6413 | |
252b5132 RH |
6414 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6415 | to adjust when loading from memory. We set coproc if we must | |
6416 | load $fn+1 first. */ | |
bdaaa2e1 | 6417 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6418 | if (! target_big_endian) |
6419 | coproc = 0; | |
6420 | ||
6421 | if (mips_pic == NO_PIC | |
6422 | || offset_expr.X_op == O_constant) | |
6423 | { | |
6424 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6425 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6426 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6427 | If we have a base register, we use this |
6428 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6429 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6430 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6431 | If this is not a GP relative symbol, we want |
6432 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6433 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6434 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6435 | If there is a base register, we add it to $at after the | |
6436 | lui instruction. If there is a constant, we always use | |
6437 | the last case. */ | |
39a59cf8 MR |
6438 | if (offset_expr.X_op == O_symbol |
6439 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6440 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6441 | { |
4d7206a2 | 6442 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6443 | if (breg == 0) |
6444 | { | |
c9914766 | 6445 | tempreg = mips_gp_register; |
252b5132 RH |
6446 | } |
6447 | else | |
6448 | { | |
67c0d1eb | 6449 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6450 | AT, breg, mips_gp_register); |
252b5132 | 6451 | tempreg = AT; |
252b5132 RH |
6452 | used_at = 1; |
6453 | } | |
6454 | ||
beae10d5 | 6455 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6456 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6457 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6458 | offset_expr.X_add_number += 4; |
6459 | ||
6460 | /* Set mips_optimize to 2 to avoid inserting an | |
6461 | undesired nop. */ | |
6462 | hold_mips_optimize = mips_optimize; | |
6463 | mips_optimize = 2; | |
beae10d5 | 6464 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6465 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6466 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6467 | mips_optimize = hold_mips_optimize; |
6468 | ||
4d7206a2 | 6469 | relax_switch (); |
252b5132 RH |
6470 | |
6471 | /* We just generated two relocs. When tc_gen_reloc | |
6472 | handles this case, it will skip the first reloc and | |
6473 | handle the second. The second reloc already has an | |
6474 | extra addend of 4, which we added above. We must | |
6475 | subtract it out, and then subtract another 4 to make | |
6476 | the first reloc come out right. The second reloc | |
6477 | will come out right because we are going to add 4 to | |
6478 | offset_expr when we build its instruction below. | |
6479 | ||
6480 | If we have a symbol, then we don't want to include | |
6481 | the offset, because it will wind up being included | |
6482 | when we generate the reloc. */ | |
6483 | ||
6484 | if (offset_expr.X_op == O_constant) | |
6485 | offset_expr.X_add_number -= 8; | |
6486 | else | |
6487 | { | |
6488 | offset_expr.X_add_number = -4; | |
6489 | offset_expr.X_op = O_constant; | |
6490 | } | |
6491 | } | |
8fc2e39e | 6492 | used_at = 1; |
67c0d1eb | 6493 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6494 | if (breg != 0) |
67c0d1eb | 6495 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6496 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6497 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6498 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6499 | /* FIXME: How do we handle overflow here? */ |
6500 | offset_expr.X_add_number += 4; | |
beae10d5 | 6501 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6502 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6503 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6504 | if (mips_relax.sequence) |
6505 | relax_end (); | |
bdaaa2e1 | 6506 | } |
252b5132 RH |
6507 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6508 | { | |
252b5132 RH |
6509 | /* If this is a reference to an external symbol, we want |
6510 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6511 | nop | |
6512 | <op> $treg,0($at) | |
6513 | <op> $treg+1,4($at) | |
6514 | Otherwise we want | |
6515 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6516 | nop | |
6517 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6518 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6519 | If there is a base register we add it to $at before the | |
6520 | lwc1 instructions. If there is a constant we include it | |
6521 | in the lwc1 instructions. */ | |
6522 | used_at = 1; | |
6523 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6524 | if (expr1.X_add_number < -0x8000 |
6525 | || expr1.X_add_number >= 0x8000 - 4) | |
6526 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6527 | load_got_offset (AT, &offset_expr); |
269137b2 | 6528 | load_delay_nop (); |
252b5132 | 6529 | if (breg != 0) |
67c0d1eb | 6530 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6531 | |
6532 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6533 | nop. */ | |
6534 | hold_mips_optimize = mips_optimize; | |
6535 | mips_optimize = 2; | |
4d7206a2 | 6536 | |
beae10d5 | 6537 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6538 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6539 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6540 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6541 | expr1.X_add_number += 4; |
67c0d1eb RS |
6542 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6543 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6544 | relax_switch (); |
67c0d1eb RS |
6545 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6546 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6547 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6548 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6549 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6550 | relax_end (); |
252b5132 | 6551 | |
4d7206a2 | 6552 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6553 | } |
6554 | else if (mips_pic == SVR4_PIC) | |
6555 | { | |
67c0d1eb | 6556 | int gpdelay; |
252b5132 RH |
6557 | |
6558 | /* If this is a reference to an external symbol, we want | |
6559 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6560 | addu $at,$at,$gp | |
6561 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6562 | nop | |
6563 | <op> $treg,0($at) | |
6564 | <op> $treg+1,4($at) | |
6565 | Otherwise we want | |
6566 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6567 | nop | |
6568 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6569 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6570 | If there is a base register we add it to $at before the | |
6571 | lwc1 instructions. If there is a constant we include it | |
6572 | in the lwc1 instructions. */ | |
6573 | used_at = 1; | |
6574 | expr1.X_add_number = offset_expr.X_add_number; | |
6575 | offset_expr.X_add_number = 0; | |
6576 | if (expr1.X_add_number < -0x8000 | |
6577 | || expr1.X_add_number >= 0x8000 - 4) | |
6578 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6579 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6580 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6581 | macro_build (&offset_expr, "lui", "t,u", |
6582 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6583 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6584 | AT, AT, mips_gp_register); |
67c0d1eb | 6585 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6586 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6587 | load_delay_nop (); |
252b5132 | 6588 | if (breg != 0) |
67c0d1eb | 6589 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6590 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6591 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6592 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6593 | expr1.X_add_number += 4; |
6594 | ||
6595 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6596 | nop. */ | |
6597 | hold_mips_optimize = mips_optimize; | |
6598 | mips_optimize = 2; | |
beae10d5 | 6599 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6600 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6601 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6602 | mips_optimize = hold_mips_optimize; |
6603 | expr1.X_add_number -= 4; | |
6604 | ||
4d7206a2 RS |
6605 | relax_switch (); |
6606 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6607 | if (gpdelay) |
6608 | macro_build (NULL, "nop", ""); | |
6609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6610 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6611 | load_delay_nop (); |
252b5132 | 6612 | if (breg != 0) |
67c0d1eb | 6613 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6614 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6615 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6616 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6617 | offset_expr.X_add_number += 4; |
252b5132 RH |
6618 | |
6619 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6620 | nop. */ | |
6621 | hold_mips_optimize = mips_optimize; | |
6622 | mips_optimize = 2; | |
beae10d5 | 6623 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6624 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6625 | BFD_RELOC_LO16, AT); | |
252b5132 | 6626 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6627 | relax_end (); |
252b5132 | 6628 | } |
252b5132 RH |
6629 | else |
6630 | abort (); | |
6631 | ||
252b5132 RH |
6632 | break; |
6633 | ||
6634 | case M_LD_OB: | |
6635 | s = "lw"; | |
6636 | goto sd_ob; | |
6637 | case M_SD_OB: | |
6638 | s = "sw"; | |
6639 | sd_ob: | |
ca4e0257 | 6640 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6641 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6642 | offset_expr.X_add_number += 4; |
67c0d1eb | 6643 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6644 | break; |
252b5132 RH |
6645 | |
6646 | /* New code added to support COPZ instructions. | |
6647 | This code builds table entries out of the macros in mip_opcodes. | |
6648 | R4000 uses interlocks to handle coproc delays. | |
6649 | Other chips (like the R3000) require nops to be inserted for delays. | |
6650 | ||
f72c8c98 | 6651 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6652 | In order to fill delay slots for non-interlocked chips, |
6653 | we must have a way to specify delays based on the coprocessor. | |
6654 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6655 | What are the side-effects of the cop instruction? | |
6656 | What cache support might we have and what are its effects? | |
6657 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6658 | What registers are read/set/modified? |
252b5132 RH |
6659 | |
6660 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6661 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6662 | |
6663 | case M_COP0: | |
6664 | s = "c0"; | |
6665 | goto copz; | |
6666 | case M_COP1: | |
6667 | s = "c1"; | |
6668 | goto copz; | |
6669 | case M_COP2: | |
6670 | s = "c2"; | |
6671 | goto copz; | |
6672 | case M_COP3: | |
6673 | s = "c3"; | |
6674 | copz: | |
6675 | /* For now we just do C (same as Cz). The parameter will be | |
6676 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6677 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6678 | break; |
252b5132 | 6679 | |
ea1fb5dc | 6680 | case M_MOVE: |
67c0d1eb | 6681 | move_register (dreg, sreg); |
8fc2e39e | 6682 | break; |
ea1fb5dc | 6683 | |
252b5132 RH |
6684 | #ifdef LOSING_COMPILER |
6685 | default: | |
6686 | /* Try and see if this is a new itbl instruction. | |
6687 | This code builds table entries out of the macros in mip_opcodes. | |
6688 | FIXME: For now we just assemble the expression and pass it's | |
6689 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6690 | We may want to have the assembler assemble this value, |
252b5132 RH |
6691 | so that we gain the assembler's knowledge of delay slots, |
6692 | symbols, etc. | |
6693 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6694 | if (itbl_have_entries |
252b5132 | 6695 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6696 | { |
252b5132 RH |
6697 | s = ip->insn_mo->name; |
6698 | s2 = "cop3"; | |
6699 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6700 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6701 | break; |
beae10d5 | 6702 | } |
252b5132 | 6703 | macro2 (ip); |
8fc2e39e | 6704 | break; |
252b5132 | 6705 | } |
8fc2e39e TS |
6706 | if (mips_opts.noat && used_at) |
6707 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6708 | } |
bdaaa2e1 | 6709 | |
252b5132 | 6710 | static void |
17a2f251 | 6711 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6712 | { |
6713 | register int treg, sreg, dreg, breg; | |
6714 | int tempreg; | |
6715 | int mask; | |
252b5132 RH |
6716 | int used_at; |
6717 | expressionS expr1; | |
6718 | const char *s; | |
6719 | const char *s2; | |
6720 | const char *fmt; | |
6721 | int likely = 0; | |
6722 | int dbl = 0; | |
6723 | int coproc = 0; | |
6724 | int lr = 0; | |
6725 | int imm = 0; | |
6726 | int off; | |
6727 | offsetT maxnum; | |
6728 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6729 | |
252b5132 RH |
6730 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6731 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6732 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6733 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6734 | |
252b5132 RH |
6735 | expr1.X_op = O_constant; |
6736 | expr1.X_op_symbol = NULL; | |
6737 | expr1.X_add_symbol = NULL; | |
6738 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6739 | |
252b5132 RH |
6740 | switch (mask) |
6741 | { | |
6742 | #endif /* LOSING_COMPILER */ | |
6743 | ||
6744 | case M_DMUL: | |
6745 | dbl = 1; | |
6746 | case M_MUL: | |
67c0d1eb RS |
6747 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6748 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6749 | break; |
252b5132 RH |
6750 | |
6751 | case M_DMUL_I: | |
6752 | dbl = 1; | |
6753 | case M_MUL_I: | |
6754 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6755 | not trying to be that fancy. GCC should do this for us | |
6756 | anyway. */ | |
8fc2e39e | 6757 | used_at = 1; |
67c0d1eb RS |
6758 | load_register (AT, &imm_expr, dbl); |
6759 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6760 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6761 | break; |
6762 | ||
6763 | case M_DMULO_I: | |
6764 | dbl = 1; | |
6765 | case M_MULO_I: | |
6766 | imm = 1; | |
6767 | goto do_mulo; | |
6768 | ||
6769 | case M_DMULO: | |
6770 | dbl = 1; | |
6771 | case M_MULO: | |
6772 | do_mulo: | |
7d10b47d | 6773 | start_noreorder (); |
8fc2e39e | 6774 | used_at = 1; |
252b5132 | 6775 | if (imm) |
67c0d1eb RS |
6776 | load_register (AT, &imm_expr, dbl); |
6777 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6778 | macro_build (NULL, "mflo", "d", dreg); | |
6779 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6780 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6781 | if (mips_trap) |
67c0d1eb | 6782 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6783 | else |
6784 | { | |
6785 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6786 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6787 | macro_build (NULL, "nop", "", 0); | |
6788 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6789 | } |
7d10b47d | 6790 | end_noreorder (); |
67c0d1eb | 6791 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6792 | break; |
6793 | ||
6794 | case M_DMULOU_I: | |
6795 | dbl = 1; | |
6796 | case M_MULOU_I: | |
6797 | imm = 1; | |
6798 | goto do_mulou; | |
6799 | ||
6800 | case M_DMULOU: | |
6801 | dbl = 1; | |
6802 | case M_MULOU: | |
6803 | do_mulou: | |
7d10b47d | 6804 | start_noreorder (); |
8fc2e39e | 6805 | used_at = 1; |
252b5132 | 6806 | if (imm) |
67c0d1eb RS |
6807 | load_register (AT, &imm_expr, dbl); |
6808 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6809 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6810 | macro_build (NULL, "mfhi", "d", AT); |
6811 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6812 | if (mips_trap) |
67c0d1eb | 6813 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6814 | else |
6815 | { | |
6816 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6817 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6818 | macro_build (NULL, "nop", "", 0); | |
6819 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6820 | } |
7d10b47d | 6821 | end_noreorder (); |
252b5132 RH |
6822 | break; |
6823 | ||
771c7ce4 | 6824 | case M_DROL: |
fef14a42 | 6825 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6826 | { |
6827 | if (dreg == sreg) | |
6828 | { | |
6829 | tempreg = AT; | |
6830 | used_at = 1; | |
6831 | } | |
6832 | else | |
6833 | { | |
6834 | tempreg = dreg; | |
82dd0097 | 6835 | } |
67c0d1eb RS |
6836 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6837 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6838 | break; |
82dd0097 | 6839 | } |
8fc2e39e | 6840 | used_at = 1; |
67c0d1eb RS |
6841 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6842 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6843 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6844 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6845 | break; |
6846 | ||
252b5132 | 6847 | case M_ROL: |
fef14a42 | 6848 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6849 | { |
6850 | if (dreg == sreg) | |
6851 | { | |
6852 | tempreg = AT; | |
6853 | used_at = 1; | |
6854 | } | |
6855 | else | |
6856 | { | |
6857 | tempreg = dreg; | |
82dd0097 | 6858 | } |
67c0d1eb RS |
6859 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6860 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6861 | break; |
82dd0097 | 6862 | } |
8fc2e39e | 6863 | used_at = 1; |
67c0d1eb RS |
6864 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6865 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6866 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6867 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6868 | break; |
6869 | ||
771c7ce4 TS |
6870 | case M_DROL_I: |
6871 | { | |
6872 | unsigned int rot; | |
82dd0097 | 6873 | char *l, *r; |
771c7ce4 TS |
6874 | |
6875 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6876 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6877 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6878 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6879 | { |
6880 | rot = (64 - rot) & 0x3f; | |
6881 | if (rot >= 32) | |
67c0d1eb | 6882 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6883 | else |
67c0d1eb | 6884 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6885 | break; |
60b63b72 | 6886 | } |
483fc7cd | 6887 | if (rot == 0) |
483fc7cd | 6888 | { |
67c0d1eb | 6889 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6890 | break; |
483fc7cd | 6891 | } |
82dd0097 CD |
6892 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6893 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6894 | rot &= 0x1f; | |
8fc2e39e | 6895 | used_at = 1; |
67c0d1eb RS |
6896 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6897 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6898 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6899 | } |
6900 | break; | |
6901 | ||
252b5132 | 6902 | case M_ROL_I: |
771c7ce4 TS |
6903 | { |
6904 | unsigned int rot; | |
6905 | ||
6906 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6907 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6908 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6909 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6910 | { |
67c0d1eb | 6911 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6912 | break; |
60b63b72 | 6913 | } |
483fc7cd | 6914 | if (rot == 0) |
483fc7cd | 6915 | { |
67c0d1eb | 6916 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6917 | break; |
483fc7cd | 6918 | } |
8fc2e39e | 6919 | used_at = 1; |
67c0d1eb RS |
6920 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6921 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6922 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6923 | } |
6924 | break; | |
6925 | ||
6926 | case M_DROR: | |
fef14a42 | 6927 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6928 | { |
67c0d1eb | 6929 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6930 | break; |
82dd0097 | 6931 | } |
8fc2e39e | 6932 | used_at = 1; |
67c0d1eb RS |
6933 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6934 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6935 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6936 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6937 | break; |
6938 | ||
6939 | case M_ROR: | |
fef14a42 | 6940 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6941 | { |
67c0d1eb | 6942 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6943 | break; |
82dd0097 | 6944 | } |
8fc2e39e | 6945 | used_at = 1; |
67c0d1eb RS |
6946 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6947 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6948 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6949 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6950 | break; |
6951 | ||
771c7ce4 TS |
6952 | case M_DROR_I: |
6953 | { | |
6954 | unsigned int rot; | |
82dd0097 | 6955 | char *l, *r; |
771c7ce4 TS |
6956 | |
6957 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6958 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6959 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6960 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6961 | { |
6962 | if (rot >= 32) | |
67c0d1eb | 6963 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6964 | else |
67c0d1eb | 6965 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6966 | break; |
82dd0097 | 6967 | } |
483fc7cd | 6968 | if (rot == 0) |
483fc7cd | 6969 | { |
67c0d1eb | 6970 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6971 | break; |
483fc7cd | 6972 | } |
82dd0097 CD |
6973 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6974 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6975 | rot &= 0x1f; | |
8fc2e39e | 6976 | used_at = 1; |
67c0d1eb RS |
6977 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6978 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6979 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6980 | } |
6981 | break; | |
6982 | ||
252b5132 | 6983 | case M_ROR_I: |
771c7ce4 TS |
6984 | { |
6985 | unsigned int rot; | |
6986 | ||
6987 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6988 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6989 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6990 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6991 | { |
67c0d1eb | 6992 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6993 | break; |
82dd0097 | 6994 | } |
483fc7cd | 6995 | if (rot == 0) |
483fc7cd | 6996 | { |
67c0d1eb | 6997 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6998 | break; |
483fc7cd | 6999 | } |
8fc2e39e | 7000 | used_at = 1; |
67c0d1eb RS |
7001 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7002 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7003 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7004 | } |
252b5132 RH |
7005 | break; |
7006 | ||
7007 | case M_S_DOB: | |
fef14a42 | 7008 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7009 | { |
7010 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7011 | break; |
252b5132 | 7012 | } |
e7af610e | 7013 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7014 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7015 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7016 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7017 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7018 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7019 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7020 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7021 | break; |
252b5132 RH |
7022 | |
7023 | case M_SEQ: | |
7024 | if (sreg == 0) | |
67c0d1eb | 7025 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7026 | else if (treg == 0) |
67c0d1eb | 7027 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7028 | else |
7029 | { | |
67c0d1eb RS |
7030 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7031 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7032 | } |
8fc2e39e | 7033 | break; |
252b5132 RH |
7034 | |
7035 | case M_SEQ_I: | |
7036 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7037 | { | |
67c0d1eb | 7038 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7039 | break; |
252b5132 RH |
7040 | } |
7041 | if (sreg == 0) | |
7042 | { | |
7043 | as_warn (_("Instruction %s: result is always false"), | |
7044 | ip->insn_mo->name); | |
67c0d1eb | 7045 | move_register (dreg, 0); |
8fc2e39e | 7046 | break; |
252b5132 RH |
7047 | } |
7048 | if (imm_expr.X_op == O_constant | |
7049 | && imm_expr.X_add_number >= 0 | |
7050 | && imm_expr.X_add_number < 0x10000) | |
7051 | { | |
67c0d1eb | 7052 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7053 | } |
7054 | else if (imm_expr.X_op == O_constant | |
7055 | && imm_expr.X_add_number > -0x8000 | |
7056 | && imm_expr.X_add_number < 0) | |
7057 | { | |
7058 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7059 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7060 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7061 | } |
7062 | else | |
7063 | { | |
67c0d1eb RS |
7064 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7065 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7066 | used_at = 1; |
7067 | } | |
67c0d1eb | 7068 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7069 | break; |
252b5132 RH |
7070 | |
7071 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7072 | s = "slt"; | |
7073 | goto sge; | |
7074 | case M_SGEU: | |
7075 | s = "sltu"; | |
7076 | sge: | |
67c0d1eb RS |
7077 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7078 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7079 | break; |
252b5132 RH |
7080 | |
7081 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7082 | case M_SGEU_I: | |
7083 | if (imm_expr.X_op == O_constant | |
7084 | && imm_expr.X_add_number >= -0x8000 | |
7085 | && imm_expr.X_add_number < 0x8000) | |
7086 | { | |
67c0d1eb RS |
7087 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7088 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7089 | } |
7090 | else | |
7091 | { | |
67c0d1eb RS |
7092 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7093 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7094 | dreg, sreg, AT); | |
252b5132 RH |
7095 | used_at = 1; |
7096 | } | |
67c0d1eb | 7097 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7098 | break; |
252b5132 RH |
7099 | |
7100 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7101 | s = "slt"; | |
7102 | goto sgt; | |
7103 | case M_SGTU: | |
7104 | s = "sltu"; | |
7105 | sgt: | |
67c0d1eb | 7106 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7107 | break; |
252b5132 RH |
7108 | |
7109 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7110 | s = "slt"; | |
7111 | goto sgti; | |
7112 | case M_SGTU_I: | |
7113 | s = "sltu"; | |
7114 | sgti: | |
8fc2e39e | 7115 | used_at = 1; |
67c0d1eb RS |
7116 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7117 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7118 | break; |
7119 | ||
2396cfb9 | 7120 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7121 | s = "slt"; |
7122 | goto sle; | |
7123 | case M_SLEU: | |
7124 | s = "sltu"; | |
7125 | sle: | |
67c0d1eb RS |
7126 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7127 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7128 | break; |
252b5132 | 7129 | |
2396cfb9 | 7130 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7131 | s = "slt"; |
7132 | goto slei; | |
7133 | case M_SLEU_I: | |
7134 | s = "sltu"; | |
7135 | slei: | |
8fc2e39e | 7136 | used_at = 1; |
67c0d1eb RS |
7137 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7138 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7139 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7140 | break; |
7141 | ||
7142 | case M_SLT_I: | |
7143 | if (imm_expr.X_op == O_constant | |
7144 | && imm_expr.X_add_number >= -0x8000 | |
7145 | && imm_expr.X_add_number < 0x8000) | |
7146 | { | |
67c0d1eb | 7147 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7148 | break; |
252b5132 | 7149 | } |
8fc2e39e | 7150 | used_at = 1; |
67c0d1eb RS |
7151 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7152 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7153 | break; |
7154 | ||
7155 | case M_SLTU_I: | |
7156 | if (imm_expr.X_op == O_constant | |
7157 | && imm_expr.X_add_number >= -0x8000 | |
7158 | && imm_expr.X_add_number < 0x8000) | |
7159 | { | |
67c0d1eb | 7160 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7161 | BFD_RELOC_LO16); |
8fc2e39e | 7162 | break; |
252b5132 | 7163 | } |
8fc2e39e | 7164 | used_at = 1; |
67c0d1eb RS |
7165 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7166 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7167 | break; |
7168 | ||
7169 | case M_SNE: | |
7170 | if (sreg == 0) | |
67c0d1eb | 7171 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7172 | else if (treg == 0) |
67c0d1eb | 7173 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7174 | else |
7175 | { | |
67c0d1eb RS |
7176 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7177 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7178 | } |
8fc2e39e | 7179 | break; |
252b5132 RH |
7180 | |
7181 | case M_SNE_I: | |
7182 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7183 | { | |
67c0d1eb | 7184 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7185 | break; |
252b5132 RH |
7186 | } |
7187 | if (sreg == 0) | |
7188 | { | |
7189 | as_warn (_("Instruction %s: result is always true"), | |
7190 | ip->insn_mo->name); | |
67c0d1eb RS |
7191 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7192 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7193 | break; |
252b5132 RH |
7194 | } |
7195 | if (imm_expr.X_op == O_constant | |
7196 | && imm_expr.X_add_number >= 0 | |
7197 | && imm_expr.X_add_number < 0x10000) | |
7198 | { | |
67c0d1eb | 7199 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7200 | } |
7201 | else if (imm_expr.X_op == O_constant | |
7202 | && imm_expr.X_add_number > -0x8000 | |
7203 | && imm_expr.X_add_number < 0) | |
7204 | { | |
7205 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7206 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7207 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7208 | } |
7209 | else | |
7210 | { | |
67c0d1eb RS |
7211 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7212 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7213 | used_at = 1; |
7214 | } | |
67c0d1eb | 7215 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7216 | break; |
252b5132 RH |
7217 | |
7218 | case M_DSUB_I: | |
7219 | dbl = 1; | |
7220 | case M_SUB_I: | |
7221 | if (imm_expr.X_op == O_constant | |
7222 | && imm_expr.X_add_number > -0x8000 | |
7223 | && imm_expr.X_add_number <= 0x8000) | |
7224 | { | |
7225 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7226 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7227 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7228 | break; |
252b5132 | 7229 | } |
8fc2e39e | 7230 | used_at = 1; |
67c0d1eb RS |
7231 | load_register (AT, &imm_expr, dbl); |
7232 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7233 | break; |
7234 | ||
7235 | case M_DSUBU_I: | |
7236 | dbl = 1; | |
7237 | case M_SUBU_I: | |
7238 | if (imm_expr.X_op == O_constant | |
7239 | && imm_expr.X_add_number > -0x8000 | |
7240 | && imm_expr.X_add_number <= 0x8000) | |
7241 | { | |
7242 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7243 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7244 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7245 | break; |
252b5132 | 7246 | } |
8fc2e39e | 7247 | used_at = 1; |
67c0d1eb RS |
7248 | load_register (AT, &imm_expr, dbl); |
7249 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7250 | break; |
7251 | ||
7252 | case M_TEQ_I: | |
7253 | s = "teq"; | |
7254 | goto trap; | |
7255 | case M_TGE_I: | |
7256 | s = "tge"; | |
7257 | goto trap; | |
7258 | case M_TGEU_I: | |
7259 | s = "tgeu"; | |
7260 | goto trap; | |
7261 | case M_TLT_I: | |
7262 | s = "tlt"; | |
7263 | goto trap; | |
7264 | case M_TLTU_I: | |
7265 | s = "tltu"; | |
7266 | goto trap; | |
7267 | case M_TNE_I: | |
7268 | s = "tne"; | |
7269 | trap: | |
8fc2e39e | 7270 | used_at = 1; |
67c0d1eb RS |
7271 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7272 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7273 | break; |
7274 | ||
252b5132 | 7275 | case M_TRUNCWS: |
43841e91 | 7276 | case M_TRUNCWD: |
e7af610e | 7277 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7278 | used_at = 1; |
252b5132 RH |
7279 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7280 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7281 | ||
7282 | /* | |
7283 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7284 | * or is there a reason for it? | |
7285 | */ | |
7d10b47d | 7286 | start_noreorder (); |
67c0d1eb RS |
7287 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7288 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7289 | macro_build (NULL, "nop", ""); | |
252b5132 | 7290 | expr1.X_add_number = 3; |
67c0d1eb | 7291 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7292 | expr1.X_add_number = 2; |
67c0d1eb RS |
7293 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7294 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7295 | macro_build (NULL, "nop", ""); | |
7296 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7297 | dreg, sreg); | |
7298 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7299 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7300 | end_noreorder (); |
252b5132 RH |
7301 | break; |
7302 | ||
7303 | case M_ULH: | |
7304 | s = "lb"; | |
7305 | goto ulh; | |
7306 | case M_ULHU: | |
7307 | s = "lbu"; | |
7308 | ulh: | |
8fc2e39e | 7309 | used_at = 1; |
252b5132 RH |
7310 | if (offset_expr.X_add_number >= 0x7fff) |
7311 | as_bad (_("operand overflow")); | |
252b5132 | 7312 | if (! target_big_endian) |
f9419b05 | 7313 | ++offset_expr.X_add_number; |
67c0d1eb | 7314 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7315 | if (! target_big_endian) |
f9419b05 | 7316 | --offset_expr.X_add_number; |
252b5132 | 7317 | else |
f9419b05 | 7318 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7319 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7320 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7321 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7322 | break; |
7323 | ||
7324 | case M_ULD: | |
7325 | s = "ldl"; | |
7326 | s2 = "ldr"; | |
7327 | off = 7; | |
7328 | goto ulw; | |
7329 | case M_ULW: | |
7330 | s = "lwl"; | |
7331 | s2 = "lwr"; | |
7332 | off = 3; | |
7333 | ulw: | |
7334 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7335 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7336 | if (treg != breg) |
7337 | tempreg = treg; | |
7338 | else | |
8fc2e39e TS |
7339 | { |
7340 | used_at = 1; | |
7341 | tempreg = AT; | |
7342 | } | |
252b5132 RH |
7343 | if (! target_big_endian) |
7344 | offset_expr.X_add_number += off; | |
67c0d1eb | 7345 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7346 | if (! target_big_endian) |
7347 | offset_expr.X_add_number -= off; | |
7348 | else | |
7349 | offset_expr.X_add_number += off; | |
67c0d1eb | 7350 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7351 | |
7352 | /* If necessary, move the result in tempreg the final destination. */ | |
7353 | if (treg == tempreg) | |
8fc2e39e | 7354 | break; |
af22f5b2 | 7355 | /* Protect second load's delay slot. */ |
017315e4 | 7356 | load_delay_nop (); |
67c0d1eb | 7357 | move_register (treg, tempreg); |
af22f5b2 | 7358 | break; |
252b5132 RH |
7359 | |
7360 | case M_ULD_A: | |
7361 | s = "ldl"; | |
7362 | s2 = "ldr"; | |
7363 | off = 7; | |
7364 | goto ulwa; | |
7365 | case M_ULW_A: | |
7366 | s = "lwl"; | |
7367 | s2 = "lwr"; | |
7368 | off = 3; | |
7369 | ulwa: | |
d6bc6245 | 7370 | used_at = 1; |
67c0d1eb | 7371 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7372 | if (breg != 0) |
67c0d1eb | 7373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7374 | if (! target_big_endian) |
7375 | expr1.X_add_number = off; | |
7376 | else | |
7377 | expr1.X_add_number = 0; | |
67c0d1eb | 7378 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7379 | if (! target_big_endian) |
7380 | expr1.X_add_number = 0; | |
7381 | else | |
7382 | expr1.X_add_number = off; | |
67c0d1eb | 7383 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7384 | break; |
7385 | ||
7386 | case M_ULH_A: | |
7387 | case M_ULHU_A: | |
d6bc6245 | 7388 | used_at = 1; |
67c0d1eb | 7389 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7390 | if (breg != 0) |
67c0d1eb | 7391 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7392 | if (target_big_endian) |
7393 | expr1.X_add_number = 0; | |
67c0d1eb | 7394 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7395 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7396 | if (target_big_endian) |
7397 | expr1.X_add_number = 1; | |
7398 | else | |
7399 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7400 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7401 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7402 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7403 | break; |
7404 | ||
7405 | case M_USH: | |
8fc2e39e | 7406 | used_at = 1; |
252b5132 RH |
7407 | if (offset_expr.X_add_number >= 0x7fff) |
7408 | as_bad (_("operand overflow")); | |
7409 | if (target_big_endian) | |
f9419b05 | 7410 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7411 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7412 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7413 | if (target_big_endian) |
f9419b05 | 7414 | --offset_expr.X_add_number; |
252b5132 | 7415 | else |
f9419b05 | 7416 | ++offset_expr.X_add_number; |
67c0d1eb | 7417 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7418 | break; |
7419 | ||
7420 | case M_USD: | |
7421 | s = "sdl"; | |
7422 | s2 = "sdr"; | |
7423 | off = 7; | |
7424 | goto usw; | |
7425 | case M_USW: | |
7426 | s = "swl"; | |
7427 | s2 = "swr"; | |
7428 | off = 3; | |
7429 | usw: | |
7430 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7431 | as_bad (_("operand overflow")); | |
7432 | if (! target_big_endian) | |
7433 | offset_expr.X_add_number += off; | |
67c0d1eb | 7434 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7435 | if (! target_big_endian) |
7436 | offset_expr.X_add_number -= off; | |
7437 | else | |
7438 | offset_expr.X_add_number += off; | |
67c0d1eb | 7439 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7440 | break; |
252b5132 RH |
7441 | |
7442 | case M_USD_A: | |
7443 | s = "sdl"; | |
7444 | s2 = "sdr"; | |
7445 | off = 7; | |
7446 | goto uswa; | |
7447 | case M_USW_A: | |
7448 | s = "swl"; | |
7449 | s2 = "swr"; | |
7450 | off = 3; | |
7451 | uswa: | |
d6bc6245 | 7452 | used_at = 1; |
67c0d1eb | 7453 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7454 | if (breg != 0) |
67c0d1eb | 7455 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7456 | if (! target_big_endian) |
7457 | expr1.X_add_number = off; | |
7458 | else | |
7459 | expr1.X_add_number = 0; | |
67c0d1eb | 7460 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7461 | if (! target_big_endian) |
7462 | expr1.X_add_number = 0; | |
7463 | else | |
7464 | expr1.X_add_number = off; | |
67c0d1eb | 7465 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7466 | break; |
7467 | ||
7468 | case M_USH_A: | |
d6bc6245 | 7469 | used_at = 1; |
67c0d1eb | 7470 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7471 | if (breg != 0) |
67c0d1eb | 7472 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7473 | if (! target_big_endian) |
7474 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7475 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7476 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7477 | if (! target_big_endian) |
7478 | expr1.X_add_number = 1; | |
7479 | else | |
7480 | expr1.X_add_number = 0; | |
67c0d1eb | 7481 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7482 | if (! target_big_endian) |
7483 | expr1.X_add_number = 0; | |
7484 | else | |
7485 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7486 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7487 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7488 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7489 | break; |
7490 | ||
7491 | default: | |
7492 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7493 | are added dynamically. */ |
252b5132 RH |
7494 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7495 | break; | |
7496 | } | |
8fc2e39e TS |
7497 | if (mips_opts.noat && used_at) |
7498 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7499 | } |
7500 | ||
7501 | /* Implement macros in mips16 mode. */ | |
7502 | ||
7503 | static void | |
17a2f251 | 7504 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7505 | { |
7506 | int mask; | |
7507 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7508 | expressionS expr1; |
7509 | int dbl; | |
7510 | const char *s, *s2, *s3; | |
7511 | ||
7512 | mask = ip->insn_mo->mask; | |
7513 | ||
bf12938e RS |
7514 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7515 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7516 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7517 | |
252b5132 RH |
7518 | expr1.X_op = O_constant; |
7519 | expr1.X_op_symbol = NULL; | |
7520 | expr1.X_add_symbol = NULL; | |
7521 | expr1.X_add_number = 1; | |
7522 | ||
7523 | dbl = 0; | |
7524 | ||
7525 | switch (mask) | |
7526 | { | |
7527 | default: | |
7528 | internalError (); | |
7529 | ||
7530 | case M_DDIV_3: | |
7531 | dbl = 1; | |
7532 | case M_DIV_3: | |
7533 | s = "mflo"; | |
7534 | goto do_div3; | |
7535 | case M_DREM_3: | |
7536 | dbl = 1; | |
7537 | case M_REM_3: | |
7538 | s = "mfhi"; | |
7539 | do_div3: | |
7d10b47d | 7540 | start_noreorder (); |
67c0d1eb | 7541 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7542 | expr1.X_add_number = 2; |
67c0d1eb RS |
7543 | macro_build (&expr1, "bnez", "x,p", yreg); |
7544 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7545 | |
252b5132 RH |
7546 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7547 | since that causes an overflow. We should do that as well, | |
7548 | but I don't see how to do the comparisons without a temporary | |
7549 | register. */ | |
7d10b47d | 7550 | end_noreorder (); |
67c0d1eb | 7551 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7552 | break; |
7553 | ||
7554 | case M_DIVU_3: | |
7555 | s = "divu"; | |
7556 | s2 = "mflo"; | |
7557 | goto do_divu3; | |
7558 | case M_REMU_3: | |
7559 | s = "divu"; | |
7560 | s2 = "mfhi"; | |
7561 | goto do_divu3; | |
7562 | case M_DDIVU_3: | |
7563 | s = "ddivu"; | |
7564 | s2 = "mflo"; | |
7565 | goto do_divu3; | |
7566 | case M_DREMU_3: | |
7567 | s = "ddivu"; | |
7568 | s2 = "mfhi"; | |
7569 | do_divu3: | |
7d10b47d | 7570 | start_noreorder (); |
67c0d1eb | 7571 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7572 | expr1.X_add_number = 2; |
67c0d1eb RS |
7573 | macro_build (&expr1, "bnez", "x,p", yreg); |
7574 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7575 | end_noreorder (); |
67c0d1eb | 7576 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7577 | break; |
7578 | ||
7579 | case M_DMUL: | |
7580 | dbl = 1; | |
7581 | case M_MUL: | |
67c0d1eb RS |
7582 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7583 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7584 | break; |
252b5132 RH |
7585 | |
7586 | case M_DSUBU_I: | |
7587 | dbl = 1; | |
7588 | goto do_subu; | |
7589 | case M_SUBU_I: | |
7590 | do_subu: | |
7591 | if (imm_expr.X_op != O_constant) | |
7592 | as_bad (_("Unsupported large constant")); | |
7593 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7594 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7595 | break; |
7596 | ||
7597 | case M_SUBU_I_2: | |
7598 | if (imm_expr.X_op != O_constant) | |
7599 | as_bad (_("Unsupported large constant")); | |
7600 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7601 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7602 | break; |
7603 | ||
7604 | case M_DSUBU_I_2: | |
7605 | if (imm_expr.X_op != O_constant) | |
7606 | as_bad (_("Unsupported large constant")); | |
7607 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7608 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7609 | break; |
7610 | ||
7611 | case M_BEQ: | |
7612 | s = "cmp"; | |
7613 | s2 = "bteqz"; | |
7614 | goto do_branch; | |
7615 | case M_BNE: | |
7616 | s = "cmp"; | |
7617 | s2 = "btnez"; | |
7618 | goto do_branch; | |
7619 | case M_BLT: | |
7620 | s = "slt"; | |
7621 | s2 = "btnez"; | |
7622 | goto do_branch; | |
7623 | case M_BLTU: | |
7624 | s = "sltu"; | |
7625 | s2 = "btnez"; | |
7626 | goto do_branch; | |
7627 | case M_BLE: | |
7628 | s = "slt"; | |
7629 | s2 = "bteqz"; | |
7630 | goto do_reverse_branch; | |
7631 | case M_BLEU: | |
7632 | s = "sltu"; | |
7633 | s2 = "bteqz"; | |
7634 | goto do_reverse_branch; | |
7635 | case M_BGE: | |
7636 | s = "slt"; | |
7637 | s2 = "bteqz"; | |
7638 | goto do_branch; | |
7639 | case M_BGEU: | |
7640 | s = "sltu"; | |
7641 | s2 = "bteqz"; | |
7642 | goto do_branch; | |
7643 | case M_BGT: | |
7644 | s = "slt"; | |
7645 | s2 = "btnez"; | |
7646 | goto do_reverse_branch; | |
7647 | case M_BGTU: | |
7648 | s = "sltu"; | |
7649 | s2 = "btnez"; | |
7650 | ||
7651 | do_reverse_branch: | |
7652 | tmp = xreg; | |
7653 | xreg = yreg; | |
7654 | yreg = tmp; | |
7655 | ||
7656 | do_branch: | |
67c0d1eb RS |
7657 | macro_build (NULL, s, "x,y", xreg, yreg); |
7658 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7659 | break; |
7660 | ||
7661 | case M_BEQ_I: | |
7662 | s = "cmpi"; | |
7663 | s2 = "bteqz"; | |
7664 | s3 = "x,U"; | |
7665 | goto do_branch_i; | |
7666 | case M_BNE_I: | |
7667 | s = "cmpi"; | |
7668 | s2 = "btnez"; | |
7669 | s3 = "x,U"; | |
7670 | goto do_branch_i; | |
7671 | case M_BLT_I: | |
7672 | s = "slti"; | |
7673 | s2 = "btnez"; | |
7674 | s3 = "x,8"; | |
7675 | goto do_branch_i; | |
7676 | case M_BLTU_I: | |
7677 | s = "sltiu"; | |
7678 | s2 = "btnez"; | |
7679 | s3 = "x,8"; | |
7680 | goto do_branch_i; | |
7681 | case M_BLE_I: | |
7682 | s = "slti"; | |
7683 | s2 = "btnez"; | |
7684 | s3 = "x,8"; | |
7685 | goto do_addone_branch_i; | |
7686 | case M_BLEU_I: | |
7687 | s = "sltiu"; | |
7688 | s2 = "btnez"; | |
7689 | s3 = "x,8"; | |
7690 | goto do_addone_branch_i; | |
7691 | case M_BGE_I: | |
7692 | s = "slti"; | |
7693 | s2 = "bteqz"; | |
7694 | s3 = "x,8"; | |
7695 | goto do_branch_i; | |
7696 | case M_BGEU_I: | |
7697 | s = "sltiu"; | |
7698 | s2 = "bteqz"; | |
7699 | s3 = "x,8"; | |
7700 | goto do_branch_i; | |
7701 | case M_BGT_I: | |
7702 | s = "slti"; | |
7703 | s2 = "bteqz"; | |
7704 | s3 = "x,8"; | |
7705 | goto do_addone_branch_i; | |
7706 | case M_BGTU_I: | |
7707 | s = "sltiu"; | |
7708 | s2 = "bteqz"; | |
7709 | s3 = "x,8"; | |
7710 | ||
7711 | do_addone_branch_i: | |
7712 | if (imm_expr.X_op != O_constant) | |
7713 | as_bad (_("Unsupported large constant")); | |
7714 | ++imm_expr.X_add_number; | |
7715 | ||
7716 | do_branch_i: | |
67c0d1eb RS |
7717 | macro_build (&imm_expr, s, s3, xreg); |
7718 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7719 | break; |
7720 | ||
7721 | case M_ABS: | |
7722 | expr1.X_add_number = 0; | |
67c0d1eb | 7723 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7724 | if (xreg != yreg) |
67c0d1eb | 7725 | move_register (xreg, yreg); |
252b5132 | 7726 | expr1.X_add_number = 2; |
67c0d1eb RS |
7727 | macro_build (&expr1, "bteqz", "p"); |
7728 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7729 | } |
7730 | } | |
7731 | ||
7732 | /* For consistency checking, verify that all bits are specified either | |
7733 | by the match/mask part of the instruction definition, or by the | |
7734 | operand list. */ | |
7735 | static int | |
17a2f251 | 7736 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7737 | { |
7738 | const char *p = opc->args; | |
7739 | char c; | |
7740 | unsigned long used_bits = opc->mask; | |
7741 | ||
7742 | if ((used_bits & opc->match) != opc->match) | |
7743 | { | |
7744 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7745 | opc->name, opc->args); | |
7746 | return 0; | |
7747 | } | |
7748 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7749 | while (*p) | |
7750 | switch (c = *p++) | |
7751 | { | |
7752 | case ',': break; | |
7753 | case '(': break; | |
7754 | case ')': break; | |
af7ee8bf CD |
7755 | case '+': |
7756 | switch (c = *p++) | |
7757 | { | |
7758 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7759 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7760 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7761 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7762 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7763 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7764 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7765 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7766 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7767 | case 'I': break; | |
af7ee8bf CD |
7768 | default: |
7769 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7770 | c, opc->name, opc->args); | |
7771 | return 0; | |
7772 | } | |
7773 | break; | |
252b5132 RH |
7774 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7775 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7776 | case 'A': break; | |
4372b673 | 7777 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7778 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7779 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7780 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7781 | case 'F': break; | |
7782 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7783 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7784 | case 'I': break; |
e972090a | 7785 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7786 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7787 | case 'L': break; |
7788 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7789 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7790 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7791 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7792 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7793 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7794 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7795 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7796 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7797 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7798 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7799 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7800 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7801 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7802 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7803 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7804 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7805 | case 'f': break; | |
7806 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7807 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7808 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7809 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7810 | case 'l': break; | |
7811 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7812 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7813 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7814 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7815 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7816 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7817 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7818 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7819 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7820 | case 'x': break; | |
7821 | case 'z': break; | |
7822 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7823 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7824 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7825 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7826 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7827 | case '[': break; | |
7828 | case ']': break; | |
74cd071d CF |
7829 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
7830 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
7831 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
7832 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7833 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
7834 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
7835 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
7836 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
7837 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
7838 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
7839 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
252b5132 RH |
7840 | default: |
7841 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7842 | c, opc->name, opc->args); | |
7843 | return 0; | |
7844 | } | |
7845 | #undef USE_BITS | |
7846 | if (used_bits != 0xffffffff) | |
7847 | { | |
7848 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7849 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7850 | return 0; | |
7851 | } | |
7852 | return 1; | |
7853 | } | |
7854 | ||
7855 | /* This routine assembles an instruction into its binary format. As a | |
7856 | side effect, it sets one of the global variables imm_reloc or | |
7857 | offset_reloc to the type of relocation to do if one of the operands | |
7858 | is an address expression. */ | |
7859 | ||
7860 | static void | |
17a2f251 | 7861 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7862 | { |
7863 | char *s; | |
7864 | const char *args; | |
43841e91 | 7865 | char c = 0; |
252b5132 RH |
7866 | struct mips_opcode *insn; |
7867 | char *argsStart; | |
7868 | unsigned int regno; | |
7869 | unsigned int lastregno = 0; | |
af7ee8bf | 7870 | unsigned int lastpos = 0; |
071742cf | 7871 | unsigned int limlo, limhi; |
252b5132 RH |
7872 | char *s_reset; |
7873 | char save_c = 0; | |
74cd071d | 7874 | offsetT min_range, max_range; |
252b5132 RH |
7875 | |
7876 | insn_error = NULL; | |
7877 | ||
7878 | /* If the instruction contains a '.', we first try to match an instruction | |
7879 | including the '.'. Then we try again without the '.'. */ | |
7880 | insn = NULL; | |
3882b010 | 7881 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7882 | continue; |
7883 | ||
7884 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7885 | the call to hash_find. Save the character we replaced just in case we | |
7886 | have to re-parse the instruction. */ | |
3882b010 | 7887 | if (ISSPACE (*s)) |
252b5132 RH |
7888 | { |
7889 | save_c = *s; | |
7890 | *s++ = '\0'; | |
7891 | } | |
bdaaa2e1 | 7892 | |
252b5132 RH |
7893 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7894 | ||
7895 | /* If we didn't find the instruction in the opcode table, try again, but | |
7896 | this time with just the instruction up to, but not including the | |
7897 | first '.'. */ | |
7898 | if (insn == NULL) | |
7899 | { | |
bdaaa2e1 | 7900 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7901 | if (save_c) |
7902 | *(--s) = save_c; | |
7903 | ||
7904 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7905 | for (s = str; |
7906 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7907 | ++s) | |
252b5132 RH |
7908 | continue; |
7909 | ||
7910 | /* If we did not find a '.', then we can quit now. */ | |
7911 | if (*s != '.') | |
7912 | { | |
7913 | insn_error = "unrecognized opcode"; | |
7914 | return; | |
7915 | } | |
7916 | ||
7917 | /* Lookup the instruction in the hash table. */ | |
7918 | *s++ = '\0'; | |
7919 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7920 | { | |
7921 | insn_error = "unrecognized opcode"; | |
7922 | return; | |
7923 | } | |
252b5132 RH |
7924 | } |
7925 | ||
7926 | argsStart = s; | |
7927 | for (;;) | |
7928 | { | |
b34976b6 | 7929 | bfd_boolean ok; |
252b5132 RH |
7930 | |
7931 | assert (strcmp (insn->name, str) == 0); | |
7932 | ||
1f25f5d3 CD |
7933 | if (OPCODE_IS_MEMBER (insn, |
7934 | (mips_opts.isa | |
3396de36 | 7935 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7936 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 7937 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
98d3f06f | 7938 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7939 | mips_opts.arch)) |
b34976b6 | 7940 | ok = TRUE; |
bdaaa2e1 | 7941 | else |
b34976b6 | 7942 | ok = FALSE; |
bdaaa2e1 | 7943 | |
252b5132 RH |
7944 | if (insn->pinfo != INSN_MACRO) |
7945 | { | |
fef14a42 | 7946 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7947 | ok = FALSE; |
252b5132 RH |
7948 | } |
7949 | ||
7950 | if (! ok) | |
7951 | { | |
7952 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7953 | && strcmp (insn->name, insn[1].name) == 0) | |
7954 | { | |
7955 | ++insn; | |
7956 | continue; | |
7957 | } | |
252b5132 | 7958 | else |
beae10d5 | 7959 | { |
268f6bed L |
7960 | if (!insn_error) |
7961 | { | |
7962 | static char buf[100]; | |
fef14a42 TS |
7963 | sprintf (buf, |
7964 | _("opcode not supported on this processor: %s (%s)"), | |
7965 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7966 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7967 | insn_error = buf; |
7968 | } | |
7969 | if (save_c) | |
7970 | *(--s) = save_c; | |
2bd7f1f3 | 7971 | return; |
252b5132 | 7972 | } |
252b5132 RH |
7973 | } |
7974 | ||
1e915849 | 7975 | create_insn (ip, insn); |
268f6bed | 7976 | insn_error = NULL; |
252b5132 RH |
7977 | for (args = insn->args;; ++args) |
7978 | { | |
deec1734 CD |
7979 | int is_mdmx; |
7980 | ||
ad8d3bb3 | 7981 | s += strspn (s, " \t"); |
deec1734 | 7982 | is_mdmx = 0; |
252b5132 RH |
7983 | switch (*args) |
7984 | { | |
7985 | case '\0': /* end of args */ | |
7986 | if (*s == '\0') | |
7987 | return; | |
7988 | break; | |
7989 | ||
74cd071d CF |
7990 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
7991 | my_getExpression (&imm_expr, s); | |
7992 | check_absolute_expr (ip, &imm_expr); | |
7993 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
7994 | { | |
7995 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
7996 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
7997 | imm_expr.X_add_number &= OP_MASK_SA3; | |
7998 | } | |
7999 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3; | |
8000 | imm_expr.X_op = O_absent; | |
8001 | s = expr_end; | |
8002 | continue; | |
8003 | ||
8004 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8005 | my_getExpression (&imm_expr, s); | |
8006 | check_absolute_expr (ip, &imm_expr); | |
8007 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8008 | { | |
8009 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8010 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
8011 | imm_expr.X_add_number &= OP_MASK_SA4; | |
8012 | } | |
8013 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4; | |
8014 | imm_expr.X_op = O_absent; | |
8015 | s = expr_end; | |
8016 | continue; | |
8017 | ||
8018 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8019 | my_getExpression (&imm_expr, s); | |
8020 | check_absolute_expr (ip, &imm_expr); | |
8021 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8022 | { | |
8023 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8024 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
8025 | imm_expr.X_add_number &= OP_MASK_IMM8; | |
8026 | } | |
8027 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8; | |
8028 | imm_expr.X_op = O_absent; | |
8029 | s = expr_end; | |
8030 | continue; | |
8031 | ||
8032 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8033 | my_getExpression (&imm_expr, s); | |
8034 | check_absolute_expr (ip, &imm_expr); | |
8035 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8036 | { | |
8037 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8038 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
8039 | imm_expr.X_add_number &= OP_MASK_RS; | |
8040 | } | |
8041 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS; | |
8042 | imm_expr.X_op = O_absent; | |
8043 | s = expr_end; | |
8044 | continue; | |
8045 | ||
8046 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8047 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8048 | s[3] >= '0' && s[3] <= '3') | |
8049 | { | |
8050 | regno = s[3] - '0'; | |
8051 | s += 4; | |
8052 | ip->insn_opcode |= regno << OP_SH_DSPACC; | |
8053 | continue; | |
8054 | } | |
8055 | else | |
8056 | as_bad (_("Invalid dsp acc register")); | |
8057 | break; | |
8058 | ||
8059 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8060 | my_getExpression (&imm_expr, s); | |
8061 | check_absolute_expr (ip, &imm_expr); | |
8062 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8063 | { | |
8064 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8065 | OP_MASK_WRDSP, | |
8066 | (unsigned long) imm_expr.X_add_number); | |
8067 | imm_expr.X_add_number &= OP_MASK_WRDSP; | |
8068 | } | |
8069 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP; | |
8070 | imm_expr.X_op = O_absent; | |
8071 | s = expr_end; | |
8072 | continue; | |
8073 | ||
8074 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8075 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8076 | s[3] >= '0' && s[3] <= '3') | |
8077 | { | |
8078 | regno = s[3] - '0'; | |
8079 | s += 4; | |
8080 | ip->insn_opcode |= regno << OP_SH_DSPACC_S; | |
8081 | continue; | |
8082 | } | |
8083 | else | |
8084 | as_bad (_("Invalid dsp acc register")); | |
8085 | break; | |
8086 | ||
8087 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8088 | my_getExpression (&imm_expr, s); | |
8089 | check_absolute_expr (ip, &imm_expr); | |
8090 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8091 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8092 | if (imm_expr.X_add_number < min_range || | |
8093 | imm_expr.X_add_number > max_range) | |
8094 | { | |
8095 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8096 | (long) min_range, (long) max_range, | |
8097 | (long) imm_expr.X_add_number); | |
8098 | } | |
8099 | imm_expr.X_add_number &= OP_MASK_DSPSFT; | |
8100 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8101 | << OP_SH_DSPSFT); | |
8102 | imm_expr.X_op = O_absent; | |
8103 | s = expr_end; | |
8104 | continue; | |
8105 | ||
8106 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8107 | my_getExpression (&imm_expr, s); | |
8108 | check_absolute_expr (ip, &imm_expr); | |
8109 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8110 | { | |
8111 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8112 | OP_MASK_RDDSP, | |
8113 | (unsigned long) imm_expr.X_add_number); | |
8114 | imm_expr.X_add_number &= OP_MASK_RDDSP; | |
8115 | } | |
8116 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP; | |
8117 | imm_expr.X_op = O_absent; | |
8118 | s = expr_end; | |
8119 | continue; | |
8120 | ||
8121 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8122 | my_getExpression (&imm_expr, s); | |
8123 | check_absolute_expr (ip, &imm_expr); | |
8124 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8125 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8126 | if (imm_expr.X_add_number < min_range || | |
8127 | imm_expr.X_add_number > max_range) | |
8128 | { | |
8129 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8130 | (long) min_range, (long) max_range, | |
8131 | (long) imm_expr.X_add_number); | |
8132 | } | |
8133 | imm_expr.X_add_number &= OP_MASK_DSPSFT_7; | |
8134 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8135 | << OP_SH_DSPSFT_7); | |
8136 | imm_expr.X_op = O_absent; | |
8137 | s = expr_end; | |
8138 | continue; | |
8139 | ||
8140 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8141 | my_getExpression (&imm_expr, s); | |
8142 | check_absolute_expr (ip, &imm_expr); | |
8143 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8144 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8145 | if (imm_expr.X_add_number < min_range || | |
8146 | imm_expr.X_add_number > max_range) | |
8147 | { | |
8148 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8149 | (long) min_range, (long) max_range, | |
8150 | (long) imm_expr.X_add_number); | |
8151 | } | |
8152 | imm_expr.X_add_number &= OP_MASK_IMM10; | |
8153 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8154 | << OP_SH_IMM10); | |
8155 | imm_expr.X_op = O_absent; | |
8156 | s = expr_end; | |
8157 | continue; | |
8158 | ||
252b5132 RH |
8159 | case ',': |
8160 | if (*s++ == *args) | |
8161 | continue; | |
8162 | s--; | |
8163 | switch (*++args) | |
8164 | { | |
8165 | case 'r': | |
8166 | case 'v': | |
bf12938e | 8167 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8168 | continue; |
8169 | ||
8170 | case 'w': | |
bf12938e | 8171 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8172 | continue; |
8173 | ||
252b5132 | 8174 | case 'W': |
bf12938e | 8175 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8176 | continue; |
8177 | ||
8178 | case 'V': | |
bf12938e | 8179 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8180 | continue; |
8181 | } | |
8182 | break; | |
8183 | ||
8184 | case '(': | |
8185 | /* Handle optional base register. | |
8186 | Either the base register is omitted or | |
bdaaa2e1 | 8187 | we must have a left paren. */ |
252b5132 RH |
8188 | /* This is dependent on the next operand specifier |
8189 | is a base register specification. */ | |
8190 | assert (args[1] == 'b' || args[1] == '5' | |
8191 | || args[1] == '-' || args[1] == '4'); | |
8192 | if (*s == '\0') | |
8193 | return; | |
8194 | ||
8195 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8196 | case '[': |
8197 | case ']': | |
252b5132 RH |
8198 | if (*s++ == *args) |
8199 | continue; | |
8200 | break; | |
8201 | ||
af7ee8bf CD |
8202 | case '+': /* Opcode extension character. */ |
8203 | switch (*++args) | |
8204 | { | |
071742cf CD |
8205 | case 'A': /* ins/ext position, becomes LSB. */ |
8206 | limlo = 0; | |
8207 | limhi = 31; | |
5f74bc13 CD |
8208 | goto do_lsb; |
8209 | case 'E': | |
8210 | limlo = 32; | |
8211 | limhi = 63; | |
8212 | goto do_lsb; | |
8213 | do_lsb: | |
071742cf CD |
8214 | my_getExpression (&imm_expr, s); |
8215 | check_absolute_expr (ip, &imm_expr); | |
8216 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8217 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8218 | { | |
8219 | as_bad (_("Improper position (%lu)"), | |
8220 | (unsigned long) imm_expr.X_add_number); | |
8221 | imm_expr.X_add_number = limlo; | |
8222 | } | |
8223 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8224 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8225 | imm_expr.X_op = O_absent; |
8226 | s = expr_end; | |
8227 | continue; | |
8228 | ||
8229 | case 'B': /* ins size, becomes MSB. */ | |
8230 | limlo = 1; | |
8231 | limhi = 32; | |
5f74bc13 CD |
8232 | goto do_msb; |
8233 | case 'F': | |
8234 | limlo = 33; | |
8235 | limhi = 64; | |
8236 | goto do_msb; | |
8237 | do_msb: | |
071742cf CD |
8238 | my_getExpression (&imm_expr, s); |
8239 | check_absolute_expr (ip, &imm_expr); | |
8240 | /* Check for negative input so that small negative numbers | |
8241 | will not succeed incorrectly. The checks against | |
8242 | (pos+size) transitively check "size" itself, | |
8243 | assuming that "pos" is reasonable. */ | |
8244 | if ((long) imm_expr.X_add_number < 0 | |
8245 | || ((unsigned long) imm_expr.X_add_number | |
8246 | + lastpos) < limlo | |
8247 | || ((unsigned long) imm_expr.X_add_number | |
8248 | + lastpos) > limhi) | |
8249 | { | |
8250 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8251 | (unsigned long) imm_expr.X_add_number, | |
8252 | (unsigned long) lastpos); | |
8253 | imm_expr.X_add_number = limlo - lastpos; | |
8254 | } | |
bf12938e RS |
8255 | INSERT_OPERAND (INSMSB, *ip, |
8256 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8257 | imm_expr.X_op = O_absent; |
8258 | s = expr_end; | |
8259 | continue; | |
8260 | ||
8261 | case 'C': /* ext size, becomes MSBD. */ | |
8262 | limlo = 1; | |
8263 | limhi = 32; | |
5f74bc13 CD |
8264 | goto do_msbd; |
8265 | case 'G': | |
8266 | limlo = 33; | |
8267 | limhi = 64; | |
8268 | goto do_msbd; | |
8269 | case 'H': | |
8270 | limlo = 33; | |
8271 | limhi = 64; | |
8272 | goto do_msbd; | |
8273 | do_msbd: | |
071742cf CD |
8274 | my_getExpression (&imm_expr, s); |
8275 | check_absolute_expr (ip, &imm_expr); | |
8276 | /* Check for negative input so that small negative numbers | |
8277 | will not succeed incorrectly. The checks against | |
8278 | (pos+size) transitively check "size" itself, | |
8279 | assuming that "pos" is reasonable. */ | |
8280 | if ((long) imm_expr.X_add_number < 0 | |
8281 | || ((unsigned long) imm_expr.X_add_number | |
8282 | + lastpos) < limlo | |
8283 | || ((unsigned long) imm_expr.X_add_number | |
8284 | + lastpos) > limhi) | |
8285 | { | |
8286 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8287 | (unsigned long) imm_expr.X_add_number, | |
8288 | (unsigned long) lastpos); | |
8289 | imm_expr.X_add_number = limlo - lastpos; | |
8290 | } | |
bf12938e | 8291 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8292 | imm_expr.X_op = O_absent; |
8293 | s = expr_end; | |
8294 | continue; | |
af7ee8bf | 8295 | |
bbcc0807 CD |
8296 | case 'D': |
8297 | /* +D is for disassembly only; never match. */ | |
8298 | break; | |
8299 | ||
5f74bc13 CD |
8300 | case 'I': |
8301 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8302 | my_getExpression (&imm2_expr, s); | |
8303 | if (imm2_expr.X_op != O_big | |
8304 | && imm2_expr.X_op != O_constant) | |
8305 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8306 | if (HAVE_32BIT_GPRS) |
8307 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8308 | s = expr_end; |
8309 | continue; | |
8310 | ||
af7ee8bf CD |
8311 | default: |
8312 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8313 | *args, insn->name, insn->args); | |
8314 | /* Further processing is fruitless. */ | |
8315 | return; | |
8316 | } | |
8317 | break; | |
8318 | ||
252b5132 RH |
8319 | case '<': /* must be at least one digit */ |
8320 | /* | |
8321 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8322 | * than 31 or less than 0, then the shift amount should be |
8323 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8324 | * We issue a warning and mask out all but the low 5 bits. |
8325 | */ | |
8326 | my_getExpression (&imm_expr, s); | |
8327 | check_absolute_expr (ip, &imm_expr); | |
8328 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8329 | as_warn (_("Improper shift amount (%lu)"), |
8330 | (unsigned long) imm_expr.X_add_number); | |
8331 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8332 | imm_expr.X_op = O_absent; |
8333 | s = expr_end; | |
8334 | continue; | |
8335 | ||
8336 | case '>': /* shift amount minus 32 */ | |
8337 | my_getExpression (&imm_expr, s); | |
8338 | check_absolute_expr (ip, &imm_expr); | |
8339 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8340 | || (unsigned long) imm_expr.X_add_number > 63) | |
8341 | break; | |
bf12938e | 8342 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8343 | imm_expr.X_op = O_absent; |
8344 | s = expr_end; | |
8345 | continue; | |
8346 | ||
252b5132 RH |
8347 | case 'k': /* cache code */ |
8348 | case 'h': /* prefx code */ | |
8349 | my_getExpression (&imm_expr, s); | |
8350 | check_absolute_expr (ip, &imm_expr); | |
8351 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8352 | as_warn (_("Invalid value for `%s' (%lu)"), |
8353 | ip->insn_mo->name, | |
8354 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8355 | if (*args == 'k') |
bf12938e | 8356 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8357 | else |
bf12938e | 8358 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8359 | imm_expr.X_op = O_absent; |
8360 | s = expr_end; | |
8361 | continue; | |
8362 | ||
8363 | case 'c': /* break code */ | |
8364 | my_getExpression (&imm_expr, s); | |
8365 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8366 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8367 | as_warn (_("Illegal break code (%lu)"), |
8368 | (unsigned long) imm_expr.X_add_number); | |
8369 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8370 | imm_expr.X_op = O_absent; |
8371 | s = expr_end; | |
8372 | continue; | |
8373 | ||
8374 | case 'q': /* lower break code */ | |
8375 | my_getExpression (&imm_expr, s); | |
8376 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8377 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8378 | as_warn (_("Illegal lower break code (%lu)"), |
8379 | (unsigned long) imm_expr.X_add_number); | |
8380 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8381 | imm_expr.X_op = O_absent; |
8382 | s = expr_end; | |
8383 | continue; | |
8384 | ||
4372b673 | 8385 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8386 | my_getExpression (&imm_expr, s); |
156c2f8b | 8387 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8388 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8389 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8390 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8391 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8392 | imm_expr.X_op = O_absent; |
8393 | s = expr_end; | |
8394 | continue; | |
8395 | ||
98d3f06f | 8396 | case 'C': /* Coprocessor code */ |
beae10d5 | 8397 | my_getExpression (&imm_expr, s); |
252b5132 | 8398 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8399 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8400 | { |
793b27f4 TS |
8401 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8402 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8403 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8404 | } |
beae10d5 KH |
8405 | ip->insn_opcode |= imm_expr.X_add_number; |
8406 | imm_expr.X_op = O_absent; | |
8407 | s = expr_end; | |
8408 | continue; | |
252b5132 | 8409 | |
4372b673 NC |
8410 | case 'J': /* 19-bit wait code. */ |
8411 | my_getExpression (&imm_expr, s); | |
8412 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8413 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8414 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8415 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8416 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8417 | imm_expr.X_op = O_absent; |
8418 | s = expr_end; | |
8419 | continue; | |
8420 | ||
252b5132 | 8421 | case 'P': /* Performance register */ |
beae10d5 | 8422 | my_getExpression (&imm_expr, s); |
252b5132 | 8423 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8424 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8425 | as_warn (_("Invalid performance register (%lu)"), |
8426 | (unsigned long) imm_expr.X_add_number); | |
8427 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8428 | imm_expr.X_op = O_absent; |
8429 | s = expr_end; | |
8430 | continue; | |
252b5132 RH |
8431 | |
8432 | case 'b': /* base register */ | |
8433 | case 'd': /* destination register */ | |
8434 | case 's': /* source register */ | |
8435 | case 't': /* target register */ | |
8436 | case 'r': /* both target and source */ | |
8437 | case 'v': /* both dest and source */ | |
8438 | case 'w': /* both dest and target */ | |
8439 | case 'E': /* coprocessor target register */ | |
8440 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8441 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8442 | case 'x': /* ignore register name */ |
8443 | case 'z': /* must be zero register */ | |
4372b673 | 8444 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8445 | s_reset = s; |
8446 | if (s[0] == '$') | |
8447 | { | |
8448 | ||
3882b010 | 8449 | if (ISDIGIT (s[1])) |
252b5132 RH |
8450 | { |
8451 | ++s; | |
8452 | regno = 0; | |
8453 | do | |
8454 | { | |
8455 | regno *= 10; | |
8456 | regno += *s - '0'; | |
8457 | ++s; | |
8458 | } | |
3882b010 | 8459 | while (ISDIGIT (*s)); |
252b5132 RH |
8460 | if (regno > 31) |
8461 | as_bad (_("Invalid register number (%d)"), regno); | |
8462 | } | |
af7ee8bf | 8463 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8464 | goto notreg; |
8465 | else | |
8466 | { | |
76db943d TS |
8467 | if (s[1] == 'r' && s[2] == 'a') |
8468 | { | |
8469 | s += 3; | |
8470 | regno = RA; | |
8471 | } | |
8472 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8473 | { |
8474 | s += 3; | |
8475 | regno = FP; | |
8476 | } | |
8477 | else if (s[1] == 's' && s[2] == 'p') | |
8478 | { | |
8479 | s += 3; | |
8480 | regno = SP; | |
8481 | } | |
8482 | else if (s[1] == 'g' && s[2] == 'p') | |
8483 | { | |
8484 | s += 3; | |
8485 | regno = GP; | |
8486 | } | |
8487 | else if (s[1] == 'a' && s[2] == 't') | |
8488 | { | |
8489 | s += 3; | |
8490 | regno = AT; | |
8491 | } | |
8492 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8493 | { | |
8494 | s += 4; | |
8495 | regno = KT0; | |
8496 | } | |
8497 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8498 | { | |
8499 | s += 4; | |
8500 | regno = KT1; | |
8501 | } | |
85b51719 TS |
8502 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8503 | { | |
8504 | s += 5; | |
8505 | regno = ZERO; | |
8506 | } | |
252b5132 RH |
8507 | else if (itbl_have_entries) |
8508 | { | |
8509 | char *p, *n; | |
d7ba4a77 | 8510 | unsigned long r; |
252b5132 | 8511 | |
d7ba4a77 | 8512 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8513 | n = itbl_get_field (&p); /* n is name */ |
8514 | ||
d7ba4a77 ILT |
8515 | /* See if this is a register defined in an |
8516 | itbl entry. */ | |
8517 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8518 | { |
8519 | /* Get_field advances to the start of | |
8520 | the next field, so we need to back | |
d7ba4a77 | 8521 | rack to the end of the last field. */ |
bdaaa2e1 | 8522 | if (p) |
252b5132 | 8523 | s = p - 1; |
bdaaa2e1 | 8524 | else |
d7ba4a77 | 8525 | s = strchr (s, '\0'); |
252b5132 RH |
8526 | regno = r; |
8527 | } | |
8528 | else | |
8529 | goto notreg; | |
beae10d5 | 8530 | } |
252b5132 RH |
8531 | else |
8532 | goto notreg; | |
8533 | } | |
8534 | if (regno == AT | |
8535 | && ! mips_opts.noat | |
8536 | && *args != 'E' | |
af7ee8bf CD |
8537 | && *args != 'G' |
8538 | && *args != 'K') | |
252b5132 RH |
8539 | as_warn (_("Used $at without \".set noat\"")); |
8540 | c = *args; | |
8541 | if (*s == ' ') | |
f9419b05 | 8542 | ++s; |
252b5132 RH |
8543 | if (args[1] != *s) |
8544 | { | |
8545 | if (c == 'r' || c == 'v' || c == 'w') | |
8546 | { | |
8547 | regno = lastregno; | |
8548 | s = s_reset; | |
f9419b05 | 8549 | ++args; |
252b5132 RH |
8550 | } |
8551 | } | |
8552 | /* 'z' only matches $0. */ | |
8553 | if (c == 'z' && regno != 0) | |
8554 | break; | |
8555 | ||
bdaaa2e1 KH |
8556 | /* Now that we have assembled one operand, we use the args string |
8557 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8558 | switch (c) |
8559 | { | |
8560 | case 'r': | |
8561 | case 's': | |
8562 | case 'v': | |
8563 | case 'b': | |
bf12938e | 8564 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8565 | break; |
8566 | case 'd': | |
8567 | case 'G': | |
af7ee8bf | 8568 | case 'K': |
bf12938e | 8569 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8570 | break; |
4372b673 | 8571 | case 'U': |
bf12938e RS |
8572 | INSERT_OPERAND (RD, *ip, regno); |
8573 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8574 | break; |
252b5132 RH |
8575 | case 'w': |
8576 | case 't': | |
8577 | case 'E': | |
bf12938e | 8578 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8579 | break; |
8580 | case 'x': | |
8581 | /* This case exists because on the r3000 trunc | |
8582 | expands into a macro which requires a gp | |
8583 | register. On the r6000 or r4000 it is | |
8584 | assembled into a single instruction which | |
8585 | ignores the register. Thus the insn version | |
8586 | is MIPS_ISA2 and uses 'x', and the macro | |
8587 | version is MIPS_ISA1 and uses 't'. */ | |
8588 | break; | |
8589 | case 'z': | |
8590 | /* This case is for the div instruction, which | |
8591 | acts differently if the destination argument | |
8592 | is $0. This only matches $0, and is checked | |
8593 | outside the switch. */ | |
8594 | break; | |
8595 | case 'D': | |
8596 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8597 | break; | |
8598 | /* What about all other operands like 'i', which | |
8599 | can be specified in the opcode table? */ | |
8600 | } | |
8601 | lastregno = regno; | |
8602 | continue; | |
8603 | } | |
8604 | notreg: | |
8605 | switch (*args++) | |
8606 | { | |
8607 | case 'r': | |
8608 | case 'v': | |
bf12938e | 8609 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8610 | continue; |
8611 | case 'w': | |
bf12938e | 8612 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8613 | continue; |
8614 | } | |
8615 | break; | |
8616 | ||
deec1734 CD |
8617 | case 'O': /* MDMX alignment immediate constant. */ |
8618 | my_getExpression (&imm_expr, s); | |
8619 | check_absolute_expr (ip, &imm_expr); | |
8620 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8621 | as_warn ("Improper align amount (%ld), using low bits", |
8622 | (long) imm_expr.X_add_number); | |
8623 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8624 | imm_expr.X_op = O_absent; |
8625 | s = expr_end; | |
8626 | continue; | |
8627 | ||
8628 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8629 | if (s[0] != '$') | |
8630 | { | |
8631 | /* MDMX Immediate. */ | |
8632 | my_getExpression (&imm_expr, s); | |
8633 | check_absolute_expr (ip, &imm_expr); | |
8634 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8635 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8636 | (long) imm_expr.X_add_number); | |
8637 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8638 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8639 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8640 | else | |
8641 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8642 | imm_expr.X_op = O_absent; |
8643 | s = expr_end; | |
8644 | continue; | |
8645 | } | |
8646 | /* Not MDMX Immediate. Fall through. */ | |
8647 | case 'X': /* MDMX destination register. */ | |
8648 | case 'Y': /* MDMX source register. */ | |
8649 | case 'Z': /* MDMX target register. */ | |
8650 | is_mdmx = 1; | |
252b5132 RH |
8651 | case 'D': /* floating point destination register */ |
8652 | case 'S': /* floating point source register */ | |
8653 | case 'T': /* floating point target register */ | |
8654 | case 'R': /* floating point source register */ | |
8655 | case 'V': | |
8656 | case 'W': | |
8657 | s_reset = s; | |
deec1734 CD |
8658 | /* Accept $fN for FP and MDMX register numbers, and in |
8659 | addition accept $vN for MDMX register numbers. */ | |
8660 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8661 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8662 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8663 | { |
8664 | s += 2; | |
8665 | regno = 0; | |
8666 | do | |
8667 | { | |
8668 | regno *= 10; | |
8669 | regno += *s - '0'; | |
8670 | ++s; | |
8671 | } | |
3882b010 | 8672 | while (ISDIGIT (*s)); |
252b5132 RH |
8673 | |
8674 | if (regno > 31) | |
8675 | as_bad (_("Invalid float register number (%d)"), regno); | |
8676 | ||
8677 | if ((regno & 1) != 0 | |
ca4e0257 | 8678 | && HAVE_32BIT_FPRS |
252b5132 RH |
8679 | && ! (strcmp (str, "mtc1") == 0 |
8680 | || strcmp (str, "mfc1") == 0 | |
8681 | || strcmp (str, "lwc1") == 0 | |
8682 | || strcmp (str, "swc1") == 0 | |
8683 | || strcmp (str, "l.s") == 0 | |
8684 | || strcmp (str, "s.s") == 0)) | |
8685 | as_warn (_("Float register should be even, was %d"), | |
8686 | regno); | |
8687 | ||
8688 | c = *args; | |
8689 | if (*s == ' ') | |
f9419b05 | 8690 | ++s; |
252b5132 RH |
8691 | if (args[1] != *s) |
8692 | { | |
8693 | if (c == 'V' || c == 'W') | |
8694 | { | |
8695 | regno = lastregno; | |
8696 | s = s_reset; | |
f9419b05 | 8697 | ++args; |
252b5132 RH |
8698 | } |
8699 | } | |
8700 | switch (c) | |
8701 | { | |
8702 | case 'D': | |
deec1734 | 8703 | case 'X': |
bf12938e | 8704 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8705 | break; |
8706 | case 'V': | |
8707 | case 'S': | |
deec1734 | 8708 | case 'Y': |
bf12938e | 8709 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8710 | break; |
deec1734 CD |
8711 | case 'Q': |
8712 | /* This is like 'Z', but also needs to fix the MDMX | |
8713 | vector/scalar select bits. Note that the | |
8714 | scalar immediate case is handled above. */ | |
8715 | if (*s == '[') | |
8716 | { | |
8717 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8718 | int max_el = (is_qh ? 3 : 7); | |
8719 | s++; | |
8720 | my_getExpression(&imm_expr, s); | |
8721 | check_absolute_expr (ip, &imm_expr); | |
8722 | s = expr_end; | |
8723 | if (imm_expr.X_add_number > max_el) | |
8724 | as_bad(_("Bad element selector %ld"), | |
8725 | (long) imm_expr.X_add_number); | |
8726 | imm_expr.X_add_number &= max_el; | |
8727 | ip->insn_opcode |= (imm_expr.X_add_number | |
8728 | << (OP_SH_VSEL + | |
8729 | (is_qh ? 2 : 1))); | |
01a3f561 | 8730 | imm_expr.X_op = O_absent; |
deec1734 CD |
8731 | if (*s != ']') |
8732 | as_warn(_("Expecting ']' found '%s'"), s); | |
8733 | else | |
8734 | s++; | |
8735 | } | |
8736 | else | |
8737 | { | |
8738 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8739 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8740 | << OP_SH_VSEL); | |
8741 | else | |
8742 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8743 | OP_SH_VSEL); | |
8744 | } | |
8745 | /* Fall through */ | |
252b5132 RH |
8746 | case 'W': |
8747 | case 'T': | |
deec1734 | 8748 | case 'Z': |
bf12938e | 8749 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8750 | break; |
8751 | case 'R': | |
bf12938e | 8752 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8753 | break; |
8754 | } | |
8755 | lastregno = regno; | |
8756 | continue; | |
8757 | } | |
8758 | ||
252b5132 RH |
8759 | switch (*args++) |
8760 | { | |
8761 | case 'V': | |
bf12938e | 8762 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8763 | continue; |
8764 | case 'W': | |
bf12938e | 8765 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8766 | continue; |
8767 | } | |
8768 | break; | |
8769 | ||
8770 | case 'I': | |
8771 | my_getExpression (&imm_expr, s); | |
8772 | if (imm_expr.X_op != O_big | |
8773 | && imm_expr.X_op != O_constant) | |
8774 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8775 | if (HAVE_32BIT_GPRS) |
8776 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
8777 | s = expr_end; |
8778 | continue; | |
8779 | ||
8780 | case 'A': | |
8781 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 8782 | normalize_address_expr (&offset_expr); |
f6688943 | 8783 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8784 | s = expr_end; |
8785 | continue; | |
8786 | ||
8787 | case 'F': | |
8788 | case 'L': | |
8789 | case 'f': | |
8790 | case 'l': | |
8791 | { | |
8792 | int f64; | |
ca4e0257 | 8793 | int using_gprs; |
252b5132 RH |
8794 | char *save_in; |
8795 | char *err; | |
8796 | unsigned char temp[8]; | |
8797 | int len; | |
8798 | unsigned int length; | |
8799 | segT seg; | |
8800 | subsegT subseg; | |
8801 | char *p; | |
8802 | ||
8803 | /* These only appear as the last operand in an | |
8804 | instruction, and every instruction that accepts | |
8805 | them in any variant accepts them in all variants. | |
8806 | This means we don't have to worry about backing out | |
8807 | any changes if the instruction does not match. | |
8808 | ||
8809 | The difference between them is the size of the | |
8810 | floating point constant and where it goes. For 'F' | |
8811 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8812 | is 32 bits. Where the constant is placed is based | |
8813 | on how the MIPS assembler does things: | |
8814 | F -- .rdata | |
8815 | L -- .lit8 | |
8816 | f -- immediate value | |
8817 | l -- .lit4 | |
8818 | ||
8819 | The .lit4 and .lit8 sections are only used if | |
8820 | permitted by the -G argument. | |
8821 | ||
ca4e0257 RS |
8822 | The code below needs to know whether the target register |
8823 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8824 | 'F' are used with GPR-based instructions and 'l' and | |
8825 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8826 | |
8827 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8828 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8829 | |
8830 | save_in = input_line_pointer; | |
8831 | input_line_pointer = s; | |
8832 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8833 | length = len; | |
8834 | s = input_line_pointer; | |
8835 | input_line_pointer = save_in; | |
8836 | if (err != NULL && *err != '\0') | |
8837 | { | |
8838 | as_bad (_("Bad floating point constant: %s"), err); | |
8839 | memset (temp, '\0', sizeof temp); | |
8840 | length = f64 ? 8 : 4; | |
8841 | } | |
8842 | ||
156c2f8b | 8843 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8844 | |
8845 | if (*args == 'f' | |
8846 | || (*args == 'l' | |
3e722fb5 | 8847 | && (g_switch_value < 4 |
252b5132 RH |
8848 | || (temp[0] == 0 && temp[1] == 0) |
8849 | || (temp[2] == 0 && temp[3] == 0)))) | |
8850 | { | |
8851 | imm_expr.X_op = O_constant; | |
8852 | if (! target_big_endian) | |
8853 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8854 | else | |
8855 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8856 | } | |
8857 | else if (length > 4 | |
119d663a | 8858 | && ! mips_disable_float_construction |
ca4e0257 RS |
8859 | /* Constants can only be constructed in GPRs and |
8860 | copied to FPRs if the GPRs are at least as wide | |
8861 | as the FPRs. Force the constant into memory if | |
8862 | we are using 64-bit FPRs but the GPRs are only | |
8863 | 32 bits wide. */ | |
8864 | && (using_gprs | |
8865 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8866 | && ((temp[0] == 0 && temp[1] == 0) |
8867 | || (temp[2] == 0 && temp[3] == 0)) | |
8868 | && ((temp[4] == 0 && temp[5] == 0) | |
8869 | || (temp[6] == 0 && temp[7] == 0))) | |
8870 | { | |
ca4e0257 RS |
8871 | /* The value is simple enough to load with a couple of |
8872 | instructions. If using 32-bit registers, set | |
8873 | imm_expr to the high order 32 bits and offset_expr to | |
8874 | the low order 32 bits. Otherwise, set imm_expr to | |
8875 | the entire 64 bit constant. */ | |
8876 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8877 | { |
8878 | imm_expr.X_op = O_constant; | |
8879 | offset_expr.X_op = O_constant; | |
8880 | if (! target_big_endian) | |
8881 | { | |
8882 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8883 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8884 | } | |
8885 | else | |
8886 | { | |
8887 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8888 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8889 | } | |
8890 | if (offset_expr.X_add_number == 0) | |
8891 | offset_expr.X_op = O_absent; | |
8892 | } | |
8893 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8894 | { | |
8895 | imm_expr.X_op = O_constant; | |
8896 | if (! target_big_endian) | |
8897 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8898 | else | |
8899 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8900 | } | |
8901 | else | |
8902 | { | |
8903 | imm_expr.X_op = O_big; | |
8904 | imm_expr.X_add_number = 4; | |
8905 | if (! target_big_endian) | |
8906 | { | |
8907 | generic_bignum[0] = bfd_getl16 (temp); | |
8908 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8909 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8910 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8911 | } | |
8912 | else | |
8913 | { | |
8914 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8915 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8916 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8917 | generic_bignum[3] = bfd_getb16 (temp); | |
8918 | } | |
8919 | } | |
8920 | } | |
8921 | else | |
8922 | { | |
8923 | const char *newname; | |
8924 | segT new_seg; | |
8925 | ||
8926 | /* Switch to the right section. */ | |
8927 | seg = now_seg; | |
8928 | subseg = now_subseg; | |
8929 | switch (*args) | |
8930 | { | |
8931 | default: /* unused default case avoids warnings. */ | |
8932 | case 'L': | |
8933 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8934 | if (g_switch_value >= 8) |
252b5132 RH |
8935 | newname = ".lit8"; |
8936 | break; | |
8937 | case 'F': | |
3e722fb5 | 8938 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8939 | break; |
8940 | case 'l': | |
4d0d148d | 8941 | assert (g_switch_value >= 4); |
252b5132 RH |
8942 | newname = ".lit4"; |
8943 | break; | |
8944 | } | |
8945 | new_seg = subseg_new (newname, (subsegT) 0); | |
8946 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8947 | bfd_set_section_flags (stdoutput, new_seg, | |
8948 | (SEC_ALLOC | |
8949 | | SEC_LOAD | |
8950 | | SEC_READONLY | |
8951 | | SEC_DATA)); | |
8952 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8953 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8954 | && strcmp (TARGET_OS, "elf") != 0) | |
8955 | record_alignment (new_seg, 4); | |
8956 | else | |
8957 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8958 | if (seg == now_seg) | |
8959 | as_bad (_("Can't use floating point insn in this section")); | |
8960 | ||
8961 | /* Set the argument to the current address in the | |
8962 | section. */ | |
8963 | offset_expr.X_op = O_symbol; | |
8964 | offset_expr.X_add_symbol = | |
8965 | symbol_new ("L0\001", now_seg, | |
8966 | (valueT) frag_now_fix (), frag_now); | |
8967 | offset_expr.X_add_number = 0; | |
8968 | ||
8969 | /* Put the floating point number into the section. */ | |
8970 | p = frag_more ((int) length); | |
8971 | memcpy (p, temp, length); | |
8972 | ||
8973 | /* Switch back to the original section. */ | |
8974 | subseg_set (seg, subseg); | |
8975 | } | |
8976 | } | |
8977 | continue; | |
8978 | ||
8979 | case 'i': /* 16 bit unsigned immediate */ | |
8980 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8981 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8982 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8983 | { |
8984 | int more; | |
5e0116d5 RS |
8985 | offsetT minval, maxval; |
8986 | ||
8987 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8988 | && strcmp (insn->name, insn[1].name) == 0); | |
8989 | ||
8990 | /* If the expression was written as an unsigned number, | |
8991 | only treat it as signed if there are no more | |
8992 | alternatives. */ | |
8993 | if (more | |
8994 | && *args == 'j' | |
8995 | && sizeof (imm_expr.X_add_number) <= 4 | |
8996 | && imm_expr.X_op == O_constant | |
8997 | && imm_expr.X_add_number < 0 | |
8998 | && imm_expr.X_unsigned | |
8999 | && HAVE_64BIT_GPRS) | |
9000 | break; | |
9001 | ||
9002 | /* For compatibility with older assemblers, we accept | |
9003 | 0x8000-0xffff as signed 16-bit numbers when only | |
9004 | signed numbers are allowed. */ | |
9005 | if (*args == 'i') | |
9006 | minval = 0, maxval = 0xffff; | |
9007 | else if (more) | |
9008 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9009 | else |
5e0116d5 RS |
9010 | minval = -0x8000, maxval = 0xffff; |
9011 | ||
9012 | if (imm_expr.X_op != O_constant | |
9013 | || imm_expr.X_add_number < minval | |
9014 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9015 | { |
9016 | if (more) | |
9017 | break; | |
2ae7e77b AH |
9018 | if (imm_expr.X_op == O_constant |
9019 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9020 | as_bad (_("expression out of range")); |
252b5132 RH |
9021 | } |
9022 | } | |
9023 | s = expr_end; | |
9024 | continue; | |
9025 | ||
9026 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9027 | /* Check whether there is only a single bracketed expression |
9028 | left. If so, it must be the base register and the | |
9029 | constant must be zero. */ | |
9030 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9031 | { | |
9032 | offset_expr.X_op = O_constant; | |
9033 | offset_expr.X_add_number = 0; | |
9034 | continue; | |
9035 | } | |
252b5132 RH |
9036 | |
9037 | /* If this value won't fit into a 16 bit offset, then go | |
9038 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9039 | code pattern. */ |
5e0116d5 | 9040 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9041 | && (offset_expr.X_op != O_constant |
9042 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9043 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9044 | break; |
9045 | ||
252b5132 RH |
9046 | s = expr_end; |
9047 | continue; | |
9048 | ||
9049 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9050 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9051 | my_getExpression (&offset_expr, s); |
9052 | s = expr_end; | |
9053 | continue; | |
9054 | ||
9055 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9056 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9057 | && imm_expr.X_op == O_constant | |
9058 | && (imm_expr.X_add_number < 0 | |
9059 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9060 | as_bad (_("lui expression not in range 0..65535")); |
9061 | s = expr_end; | |
9062 | continue; | |
9063 | ||
9064 | case 'a': /* 26 bit address */ | |
9065 | my_getExpression (&offset_expr, s); | |
9066 | s = expr_end; | |
f6688943 | 9067 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9068 | continue; |
9069 | ||
9070 | case 'N': /* 3 bit branch condition code */ | |
9071 | case 'M': /* 3 bit compare condition code */ | |
9072 | if (strncmp (s, "$fcc", 4) != 0) | |
9073 | break; | |
9074 | s += 4; | |
9075 | regno = 0; | |
9076 | do | |
9077 | { | |
9078 | regno *= 10; | |
9079 | regno += *s - '0'; | |
9080 | ++s; | |
9081 | } | |
3882b010 | 9082 | while (ISDIGIT (*s)); |
252b5132 | 9083 | if (regno > 7) |
30c378fd CD |
9084 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9085 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9086 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9087 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9088 | && (regno & 1) != 0) | |
9089 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9090 | str, regno); | |
9091 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9092 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9093 | && (regno & 3) != 0) | |
9094 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9095 | str, regno); | |
252b5132 | 9096 | if (*args == 'N') |
bf12938e | 9097 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9098 | else |
bf12938e | 9099 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9100 | continue; |
252b5132 | 9101 | |
156c2f8b NC |
9102 | case 'H': |
9103 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9104 | s += 2; | |
3882b010 | 9105 | if (ISDIGIT (*s)) |
156c2f8b NC |
9106 | { |
9107 | c = 0; | |
9108 | do | |
9109 | { | |
9110 | c *= 10; | |
9111 | c += *s - '0'; | |
9112 | ++s; | |
9113 | } | |
3882b010 | 9114 | while (ISDIGIT (*s)); |
156c2f8b NC |
9115 | } |
9116 | else | |
9117 | c = 8; /* Invalid sel value. */ | |
9118 | ||
9119 | if (c > 7) | |
9120 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9121 | ip->insn_opcode |= c; | |
9122 | continue; | |
9123 | ||
60b63b72 RS |
9124 | case 'e': |
9125 | /* Must be at least one digit. */ | |
9126 | my_getExpression (&imm_expr, s); | |
9127 | check_absolute_expr (ip, &imm_expr); | |
9128 | ||
9129 | if ((unsigned long) imm_expr.X_add_number | |
9130 | > (unsigned long) OP_MASK_VECBYTE) | |
9131 | { | |
9132 | as_bad (_("bad byte vector index (%ld)"), | |
9133 | (long) imm_expr.X_add_number); | |
9134 | imm_expr.X_add_number = 0; | |
9135 | } | |
9136 | ||
bf12938e | 9137 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9138 | imm_expr.X_op = O_absent; |
9139 | s = expr_end; | |
9140 | continue; | |
9141 | ||
9142 | case '%': | |
9143 | my_getExpression (&imm_expr, s); | |
9144 | check_absolute_expr (ip, &imm_expr); | |
9145 | ||
9146 | if ((unsigned long) imm_expr.X_add_number | |
9147 | > (unsigned long) OP_MASK_VECALIGN) | |
9148 | { | |
9149 | as_bad (_("bad byte vector index (%ld)"), | |
9150 | (long) imm_expr.X_add_number); | |
9151 | imm_expr.X_add_number = 0; | |
9152 | } | |
9153 | ||
bf12938e | 9154 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9155 | imm_expr.X_op = O_absent; |
9156 | s = expr_end; | |
9157 | continue; | |
9158 | ||
252b5132 RH |
9159 | default: |
9160 | as_bad (_("bad char = '%c'\n"), *args); | |
9161 | internalError (); | |
9162 | } | |
9163 | break; | |
9164 | } | |
9165 | /* Args don't match. */ | |
9166 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9167 | !strcmp (insn->name, insn[1].name)) | |
9168 | { | |
9169 | ++insn; | |
9170 | s = argsStart; | |
268f6bed | 9171 | insn_error = _("illegal operands"); |
252b5132 RH |
9172 | continue; |
9173 | } | |
268f6bed L |
9174 | if (save_c) |
9175 | *(--s) = save_c; | |
252b5132 RH |
9176 | insn_error = _("illegal operands"); |
9177 | return; | |
9178 | } | |
9179 | } | |
9180 | ||
9181 | /* This routine assembles an instruction into its binary format when | |
9182 | assembling for the mips16. As a side effect, it sets one of the | |
9183 | global variables imm_reloc or offset_reloc to the type of | |
9184 | relocation to do if one of the operands is an address expression. | |
9185 | It also sets mips16_small and mips16_ext if the user explicitly | |
9186 | requested a small or extended instruction. */ | |
9187 | ||
9188 | static void | |
17a2f251 | 9189 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9190 | { |
9191 | char *s; | |
9192 | const char *args; | |
9193 | struct mips_opcode *insn; | |
9194 | char *argsstart; | |
9195 | unsigned int regno; | |
9196 | unsigned int lastregno = 0; | |
9197 | char *s_reset; | |
d6f16593 | 9198 | size_t i; |
252b5132 RH |
9199 | |
9200 | insn_error = NULL; | |
9201 | ||
b34976b6 AM |
9202 | mips16_small = FALSE; |
9203 | mips16_ext = FALSE; | |
252b5132 | 9204 | |
3882b010 | 9205 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9206 | ; |
9207 | switch (*s) | |
9208 | { | |
9209 | case '\0': | |
9210 | break; | |
9211 | ||
9212 | case ' ': | |
9213 | *s++ = '\0'; | |
9214 | break; | |
9215 | ||
9216 | case '.': | |
9217 | if (s[1] == 't' && s[2] == ' ') | |
9218 | { | |
9219 | *s = '\0'; | |
b34976b6 | 9220 | mips16_small = TRUE; |
252b5132 RH |
9221 | s += 3; |
9222 | break; | |
9223 | } | |
9224 | else if (s[1] == 'e' && s[2] == ' ') | |
9225 | { | |
9226 | *s = '\0'; | |
b34976b6 | 9227 | mips16_ext = TRUE; |
252b5132 RH |
9228 | s += 3; |
9229 | break; | |
9230 | } | |
9231 | /* Fall through. */ | |
9232 | default: | |
9233 | insn_error = _("unknown opcode"); | |
9234 | return; | |
9235 | } | |
9236 | ||
9237 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9238 | mips16_small = TRUE; |
252b5132 RH |
9239 | |
9240 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9241 | { | |
9242 | insn_error = _("unrecognized opcode"); | |
9243 | return; | |
9244 | } | |
9245 | ||
9246 | argsstart = s; | |
9247 | for (;;) | |
9248 | { | |
9249 | assert (strcmp (insn->name, str) == 0); | |
9250 | ||
1e915849 | 9251 | create_insn (ip, insn); |
252b5132 | 9252 | imm_expr.X_op = O_absent; |
f6688943 TS |
9253 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9254 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9255 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9256 | imm2_expr.X_op = O_absent; |
252b5132 | 9257 | offset_expr.X_op = O_absent; |
f6688943 TS |
9258 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9259 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9260 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9261 | for (args = insn->args; 1; ++args) |
9262 | { | |
9263 | int c; | |
9264 | ||
9265 | if (*s == ' ') | |
9266 | ++s; | |
9267 | ||
9268 | /* In this switch statement we call break if we did not find | |
9269 | a match, continue if we did find a match, or return if we | |
9270 | are done. */ | |
9271 | ||
9272 | c = *args; | |
9273 | switch (c) | |
9274 | { | |
9275 | case '\0': | |
9276 | if (*s == '\0') | |
9277 | { | |
9278 | /* Stuff the immediate value in now, if we can. */ | |
9279 | if (imm_expr.X_op == O_constant | |
f6688943 | 9280 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9281 | && insn->pinfo != INSN_MACRO) |
9282 | { | |
d6f16593 MR |
9283 | valueT tmp; |
9284 | ||
9285 | switch (*offset_reloc) | |
9286 | { | |
9287 | case BFD_RELOC_MIPS16_HI16_S: | |
9288 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9289 | break; | |
9290 | ||
9291 | case BFD_RELOC_MIPS16_HI16: | |
9292 | tmp = imm_expr.X_add_number >> 16; | |
9293 | break; | |
9294 | ||
9295 | case BFD_RELOC_MIPS16_LO16: | |
9296 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9297 | - 0x8000; | |
9298 | break; | |
9299 | ||
9300 | case BFD_RELOC_UNUSED: | |
9301 | tmp = imm_expr.X_add_number; | |
9302 | break; | |
9303 | ||
9304 | default: | |
9305 | internalError (); | |
9306 | } | |
9307 | *offset_reloc = BFD_RELOC_UNUSED; | |
9308 | ||
c4e7957c | 9309 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9310 | tmp, TRUE, mips16_small, |
252b5132 RH |
9311 | mips16_ext, &ip->insn_opcode, |
9312 | &ip->use_extend, &ip->extend); | |
9313 | imm_expr.X_op = O_absent; | |
f6688943 | 9314 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9315 | } |
9316 | ||
9317 | return; | |
9318 | } | |
9319 | break; | |
9320 | ||
9321 | case ',': | |
9322 | if (*s++ == c) | |
9323 | continue; | |
9324 | s--; | |
9325 | switch (*++args) | |
9326 | { | |
9327 | case 'v': | |
bf12938e | 9328 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9329 | continue; |
9330 | case 'w': | |
bf12938e | 9331 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9332 | continue; |
9333 | } | |
9334 | break; | |
9335 | ||
9336 | case '(': | |
9337 | case ')': | |
9338 | if (*s++ == c) | |
9339 | continue; | |
9340 | break; | |
9341 | ||
9342 | case 'v': | |
9343 | case 'w': | |
9344 | if (s[0] != '$') | |
9345 | { | |
9346 | if (c == 'v') | |
bf12938e | 9347 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9348 | else |
bf12938e | 9349 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9350 | ++args; |
9351 | continue; | |
9352 | } | |
9353 | /* Fall through. */ | |
9354 | case 'x': | |
9355 | case 'y': | |
9356 | case 'z': | |
9357 | case 'Z': | |
9358 | case '0': | |
9359 | case 'S': | |
9360 | case 'R': | |
9361 | case 'X': | |
9362 | case 'Y': | |
9363 | if (s[0] != '$') | |
9364 | break; | |
9365 | s_reset = s; | |
3882b010 | 9366 | if (ISDIGIT (s[1])) |
252b5132 RH |
9367 | { |
9368 | ++s; | |
9369 | regno = 0; | |
9370 | do | |
9371 | { | |
9372 | regno *= 10; | |
9373 | regno += *s - '0'; | |
9374 | ++s; | |
9375 | } | |
3882b010 | 9376 | while (ISDIGIT (*s)); |
252b5132 RH |
9377 | if (regno > 31) |
9378 | { | |
9379 | as_bad (_("invalid register number (%d)"), regno); | |
9380 | regno = 2; | |
9381 | } | |
9382 | } | |
9383 | else | |
9384 | { | |
76db943d TS |
9385 | if (s[1] == 'r' && s[2] == 'a') |
9386 | { | |
9387 | s += 3; | |
9388 | regno = RA; | |
9389 | } | |
9390 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9391 | { |
9392 | s += 3; | |
9393 | regno = FP; | |
9394 | } | |
9395 | else if (s[1] == 's' && s[2] == 'p') | |
9396 | { | |
9397 | s += 3; | |
9398 | regno = SP; | |
9399 | } | |
9400 | else if (s[1] == 'g' && s[2] == 'p') | |
9401 | { | |
9402 | s += 3; | |
9403 | regno = GP; | |
9404 | } | |
9405 | else if (s[1] == 'a' && s[2] == 't') | |
9406 | { | |
9407 | s += 3; | |
9408 | regno = AT; | |
9409 | } | |
9410 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9411 | { | |
9412 | s += 4; | |
9413 | regno = KT0; | |
9414 | } | |
9415 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9416 | { | |
9417 | s += 4; | |
9418 | regno = KT1; | |
9419 | } | |
85b51719 TS |
9420 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9421 | { | |
9422 | s += 5; | |
9423 | regno = ZERO; | |
9424 | } | |
252b5132 RH |
9425 | else |
9426 | break; | |
9427 | } | |
9428 | ||
9429 | if (*s == ' ') | |
9430 | ++s; | |
9431 | if (args[1] != *s) | |
9432 | { | |
9433 | if (c == 'v' || c == 'w') | |
9434 | { | |
9435 | regno = mips16_to_32_reg_map[lastregno]; | |
9436 | s = s_reset; | |
f9419b05 | 9437 | ++args; |
252b5132 RH |
9438 | } |
9439 | } | |
9440 | ||
9441 | switch (c) | |
9442 | { | |
9443 | case 'x': | |
9444 | case 'y': | |
9445 | case 'z': | |
9446 | case 'v': | |
9447 | case 'w': | |
9448 | case 'Z': | |
9449 | regno = mips32_to_16_reg_map[regno]; | |
9450 | break; | |
9451 | ||
9452 | case '0': | |
9453 | if (regno != 0) | |
9454 | regno = ILLEGAL_REG; | |
9455 | break; | |
9456 | ||
9457 | case 'S': | |
9458 | if (regno != SP) | |
9459 | regno = ILLEGAL_REG; | |
9460 | break; | |
9461 | ||
9462 | case 'R': | |
9463 | if (regno != RA) | |
9464 | regno = ILLEGAL_REG; | |
9465 | break; | |
9466 | ||
9467 | case 'X': | |
9468 | case 'Y': | |
9469 | if (regno == AT && ! mips_opts.noat) | |
9470 | as_warn (_("used $at without \".set noat\"")); | |
9471 | break; | |
9472 | ||
9473 | default: | |
9474 | internalError (); | |
9475 | } | |
9476 | ||
9477 | if (regno == ILLEGAL_REG) | |
9478 | break; | |
9479 | ||
9480 | switch (c) | |
9481 | { | |
9482 | case 'x': | |
9483 | case 'v': | |
bf12938e | 9484 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9485 | break; |
9486 | case 'y': | |
9487 | case 'w': | |
bf12938e | 9488 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9489 | break; |
9490 | case 'z': | |
bf12938e | 9491 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9492 | break; |
9493 | case 'Z': | |
bf12938e | 9494 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9495 | case '0': |
9496 | case 'S': | |
9497 | case 'R': | |
9498 | break; | |
9499 | case 'X': | |
bf12938e | 9500 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9501 | break; |
9502 | case 'Y': | |
9503 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9504 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9505 | break; |
9506 | default: | |
9507 | internalError (); | |
9508 | } | |
9509 | ||
9510 | lastregno = regno; | |
9511 | continue; | |
9512 | ||
9513 | case 'P': | |
9514 | if (strncmp (s, "$pc", 3) == 0) | |
9515 | { | |
9516 | s += 3; | |
9517 | continue; | |
9518 | } | |
9519 | break; | |
9520 | ||
252b5132 RH |
9521 | case '5': |
9522 | case 'H': | |
9523 | case 'W': | |
9524 | case 'D': | |
9525 | case 'j': | |
252b5132 RH |
9526 | case 'V': |
9527 | case 'C': | |
9528 | case 'U': | |
9529 | case 'k': | |
9530 | case 'K': | |
d6f16593 MR |
9531 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9532 | if (i > 0) | |
252b5132 | 9533 | { |
d6f16593 | 9534 | if (imm_expr.X_op != O_constant) |
252b5132 | 9535 | { |
b34976b6 | 9536 | mips16_ext = TRUE; |
b34976b6 | 9537 | ip->use_extend = TRUE; |
252b5132 | 9538 | ip->extend = 0; |
252b5132 | 9539 | } |
d6f16593 MR |
9540 | else |
9541 | { | |
9542 | /* We need to relax this instruction. */ | |
9543 | *offset_reloc = *imm_reloc; | |
9544 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9545 | } | |
9546 | s = expr_end; | |
9547 | continue; | |
252b5132 | 9548 | } |
d6f16593 MR |
9549 | *imm_reloc = BFD_RELOC_UNUSED; |
9550 | /* Fall through. */ | |
9551 | case '<': | |
9552 | case '>': | |
9553 | case '[': | |
9554 | case ']': | |
9555 | case '4': | |
9556 | case '8': | |
9557 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9558 | if (imm_expr.X_op == O_register) |
9559 | { | |
9560 | /* What we thought was an expression turned out to | |
9561 | be a register. */ | |
9562 | ||
9563 | if (s[0] == '(' && args[1] == '(') | |
9564 | { | |
9565 | /* It looks like the expression was omitted | |
9566 | before a register indirection, which means | |
9567 | that the expression is implicitly zero. We | |
9568 | still set up imm_expr, so that we handle | |
9569 | explicit extensions correctly. */ | |
9570 | imm_expr.X_op = O_constant; | |
9571 | imm_expr.X_add_number = 0; | |
f6688943 | 9572 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9573 | continue; |
9574 | } | |
9575 | ||
9576 | break; | |
9577 | } | |
9578 | ||
9579 | /* We need to relax this instruction. */ | |
f6688943 | 9580 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9581 | s = expr_end; |
9582 | continue; | |
9583 | ||
9584 | case 'p': | |
9585 | case 'q': | |
9586 | case 'A': | |
9587 | case 'B': | |
9588 | case 'E': | |
9589 | /* We use offset_reloc rather than imm_reloc for the PC | |
9590 | relative operands. This lets macros with both | |
9591 | immediate and address operands work correctly. */ | |
9592 | my_getExpression (&offset_expr, s); | |
9593 | ||
9594 | if (offset_expr.X_op == O_register) | |
9595 | break; | |
9596 | ||
9597 | /* We need to relax this instruction. */ | |
f6688943 | 9598 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9599 | s = expr_end; |
9600 | continue; | |
9601 | ||
9602 | case '6': /* break code */ | |
9603 | my_getExpression (&imm_expr, s); | |
9604 | check_absolute_expr (ip, &imm_expr); | |
9605 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9606 | as_warn (_("Invalid value for `%s' (%lu)"), |
9607 | ip->insn_mo->name, | |
9608 | (unsigned long) imm_expr.X_add_number); | |
9609 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9610 | imm_expr.X_op = O_absent; |
9611 | s = expr_end; | |
9612 | continue; | |
9613 | ||
9614 | case 'a': /* 26 bit address */ | |
9615 | my_getExpression (&offset_expr, s); | |
9616 | s = expr_end; | |
f6688943 | 9617 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9618 | ip->insn_opcode <<= 16; |
9619 | continue; | |
9620 | ||
9621 | case 'l': /* register list for entry macro */ | |
9622 | case 'L': /* register list for exit macro */ | |
9623 | { | |
9624 | int mask; | |
9625 | ||
9626 | if (c == 'l') | |
9627 | mask = 0; | |
9628 | else | |
9629 | mask = 7 << 3; | |
9630 | while (*s != '\0') | |
9631 | { | |
9632 | int freg, reg1, reg2; | |
9633 | ||
9634 | while (*s == ' ' || *s == ',') | |
9635 | ++s; | |
9636 | if (*s != '$') | |
9637 | { | |
9638 | as_bad (_("can't parse register list")); | |
9639 | break; | |
9640 | } | |
9641 | ++s; | |
9642 | if (*s != 'f') | |
9643 | freg = 0; | |
9644 | else | |
9645 | { | |
9646 | freg = 1; | |
9647 | ++s; | |
9648 | } | |
9649 | reg1 = 0; | |
3882b010 | 9650 | while (ISDIGIT (*s)) |
252b5132 RH |
9651 | { |
9652 | reg1 *= 10; | |
9653 | reg1 += *s - '0'; | |
9654 | ++s; | |
9655 | } | |
9656 | if (*s == ' ') | |
9657 | ++s; | |
9658 | if (*s != '-') | |
9659 | reg2 = reg1; | |
9660 | else | |
9661 | { | |
9662 | ++s; | |
9663 | if (*s != '$') | |
9664 | break; | |
9665 | ++s; | |
9666 | if (freg) | |
9667 | { | |
9668 | if (*s == 'f') | |
9669 | ++s; | |
9670 | else | |
9671 | { | |
9672 | as_bad (_("invalid register list")); | |
9673 | break; | |
9674 | } | |
9675 | } | |
9676 | reg2 = 0; | |
3882b010 | 9677 | while (ISDIGIT (*s)) |
252b5132 RH |
9678 | { |
9679 | reg2 *= 10; | |
9680 | reg2 += *s - '0'; | |
9681 | ++s; | |
9682 | } | |
9683 | } | |
9684 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9685 | { | |
9686 | mask &= ~ (7 << 3); | |
9687 | mask |= 5 << 3; | |
9688 | } | |
9689 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9690 | { | |
9691 | mask &= ~ (7 << 3); | |
9692 | mask |= 6 << 3; | |
9693 | } | |
9694 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9695 | mask |= (reg2 - 3) << 3; | |
9696 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9697 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9698 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9699 | mask |= 1; |
9700 | else | |
9701 | { | |
9702 | as_bad (_("invalid register list")); | |
9703 | break; | |
9704 | } | |
9705 | } | |
9706 | /* The mask is filled in in the opcode table for the | |
9707 | benefit of the disassembler. We remove it before | |
9708 | applying the actual mask. */ | |
9709 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9710 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9711 | } | |
9712 | continue; | |
9713 | ||
9714 | case 'e': /* extend code */ | |
9715 | my_getExpression (&imm_expr, s); | |
9716 | check_absolute_expr (ip, &imm_expr); | |
9717 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9718 | { | |
9719 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9720 | ip->insn_mo->name, | |
9721 | (unsigned long) imm_expr.X_add_number); | |
9722 | imm_expr.X_add_number &= 0x7ff; | |
9723 | } | |
9724 | ip->insn_opcode |= imm_expr.X_add_number; | |
9725 | imm_expr.X_op = O_absent; | |
9726 | s = expr_end; | |
9727 | continue; | |
9728 | ||
9729 | default: | |
9730 | internalError (); | |
9731 | } | |
9732 | break; | |
9733 | } | |
9734 | ||
9735 | /* Args don't match. */ | |
9736 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9737 | strcmp (insn->name, insn[1].name) == 0) | |
9738 | { | |
9739 | ++insn; | |
9740 | s = argsstart; | |
9741 | continue; | |
9742 | } | |
9743 | ||
9744 | insn_error = _("illegal operands"); | |
9745 | ||
9746 | return; | |
9747 | } | |
9748 | } | |
9749 | ||
9750 | /* This structure holds information we know about a mips16 immediate | |
9751 | argument type. */ | |
9752 | ||
e972090a NC |
9753 | struct mips16_immed_operand |
9754 | { | |
252b5132 RH |
9755 | /* The type code used in the argument string in the opcode table. */ |
9756 | int type; | |
9757 | /* The number of bits in the short form of the opcode. */ | |
9758 | int nbits; | |
9759 | /* The number of bits in the extended form of the opcode. */ | |
9760 | int extbits; | |
9761 | /* The amount by which the short form is shifted when it is used; | |
9762 | for example, the sw instruction has a shift count of 2. */ | |
9763 | int shift; | |
9764 | /* The amount by which the short form is shifted when it is stored | |
9765 | into the instruction code. */ | |
9766 | int op_shift; | |
9767 | /* Non-zero if the short form is unsigned. */ | |
9768 | int unsp; | |
9769 | /* Non-zero if the extended form is unsigned. */ | |
9770 | int extu; | |
9771 | /* Non-zero if the value is PC relative. */ | |
9772 | int pcrel; | |
9773 | }; | |
9774 | ||
9775 | /* The mips16 immediate operand types. */ | |
9776 | ||
9777 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9778 | { | |
9779 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9780 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9781 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9782 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9783 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9784 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9785 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9786 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9787 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9788 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9789 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9790 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9791 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9792 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9793 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9794 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9795 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9796 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9797 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9798 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9799 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9800 | }; | |
9801 | ||
9802 | #define MIPS16_NUM_IMMED \ | |
9803 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9804 | ||
9805 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9806 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9807 | whether an extended value is needed; if one is needed, it sets | |
9808 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9809 | If SMALL is true, an unextended opcode was explicitly requested. | |
9810 | If EXT is true, an extended opcode was explicitly requested. If | |
9811 | WARN is true, warn if EXT does not match reality. */ | |
9812 | ||
9813 | static void | |
17a2f251 TS |
9814 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9815 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9816 | unsigned long *insn, bfd_boolean *use_extend, | |
9817 | unsigned short *extend) | |
252b5132 RH |
9818 | { |
9819 | register const struct mips16_immed_operand *op; | |
9820 | int mintiny, maxtiny; | |
b34976b6 | 9821 | bfd_boolean needext; |
252b5132 RH |
9822 | |
9823 | op = mips16_immed_operands; | |
9824 | while (op->type != type) | |
9825 | { | |
9826 | ++op; | |
9827 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9828 | } | |
9829 | ||
9830 | if (op->unsp) | |
9831 | { | |
9832 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9833 | { | |
9834 | mintiny = 1; | |
9835 | maxtiny = 1 << op->nbits; | |
9836 | } | |
9837 | else | |
9838 | { | |
9839 | mintiny = 0; | |
9840 | maxtiny = (1 << op->nbits) - 1; | |
9841 | } | |
9842 | } | |
9843 | else | |
9844 | { | |
9845 | mintiny = - (1 << (op->nbits - 1)); | |
9846 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9847 | } | |
9848 | ||
9849 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9850 | if (type == 'p' || type == 'q') | |
9851 | val /= 2; | |
9852 | ||
9853 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9854 | || val < (mintiny << op->shift) | |
9855 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9856 | needext = TRUE; |
252b5132 | 9857 | else |
b34976b6 | 9858 | needext = FALSE; |
252b5132 RH |
9859 | |
9860 | if (warn && ext && ! needext) | |
beae10d5 KH |
9861 | as_warn_where (file, line, |
9862 | _("extended operand requested but not required")); | |
252b5132 RH |
9863 | if (small && needext) |
9864 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9865 | ||
9866 | if (small || (! ext && ! needext)) | |
9867 | { | |
9868 | int insnval; | |
9869 | ||
b34976b6 | 9870 | *use_extend = FALSE; |
252b5132 RH |
9871 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9872 | insnval <<= op->op_shift; | |
9873 | *insn |= insnval; | |
9874 | } | |
9875 | else | |
9876 | { | |
9877 | long minext, maxext; | |
9878 | int extval; | |
9879 | ||
9880 | if (op->extu) | |
9881 | { | |
9882 | minext = 0; | |
9883 | maxext = (1 << op->extbits) - 1; | |
9884 | } | |
9885 | else | |
9886 | { | |
9887 | minext = - (1 << (op->extbits - 1)); | |
9888 | maxext = (1 << (op->extbits - 1)) - 1; | |
9889 | } | |
9890 | if (val < minext || val > maxext) | |
9891 | as_bad_where (file, line, | |
9892 | _("operand value out of range for instruction")); | |
9893 | ||
b34976b6 | 9894 | *use_extend = TRUE; |
252b5132 RH |
9895 | if (op->extbits == 16) |
9896 | { | |
9897 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9898 | val &= 0x1f; | |
9899 | } | |
9900 | else if (op->extbits == 15) | |
9901 | { | |
9902 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9903 | val &= 0xf; | |
9904 | } | |
9905 | else | |
9906 | { | |
9907 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9908 | val = 0; | |
9909 | } | |
9910 | ||
9911 | *extend = (unsigned short) extval; | |
9912 | *insn |= val; | |
9913 | } | |
9914 | } | |
9915 | \f | |
d6f16593 | 9916 | struct percent_op_match |
ad8d3bb3 | 9917 | { |
5e0116d5 RS |
9918 | const char *str; |
9919 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9920 | }; |
9921 | ||
9922 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9923 | { |
5e0116d5 | 9924 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9925 | #ifdef OBJ_ELF |
5e0116d5 RS |
9926 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9927 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9928 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9929 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9930 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9931 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9932 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9933 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9934 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9935 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9936 | {"%half", BFD_RELOC_16}, | |
9937 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9938 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9939 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9940 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9941 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9942 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9943 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9944 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9945 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9946 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9947 | #endif |
5e0116d5 | 9948 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9949 | }; |
9950 | ||
d6f16593 MR |
9951 | static const struct percent_op_match mips16_percent_op[] = |
9952 | { | |
9953 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9954 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9955 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9956 | }; | |
9957 | ||
252b5132 | 9958 | |
5e0116d5 RS |
9959 | /* Return true if *STR points to a relocation operator. When returning true, |
9960 | move *STR over the operator and store its relocation code in *RELOC. | |
9961 | Leave both *STR and *RELOC alone when returning false. */ | |
9962 | ||
9963 | static bfd_boolean | |
17a2f251 | 9964 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9965 | { |
d6f16593 MR |
9966 | const struct percent_op_match *percent_op; |
9967 | size_t limit, i; | |
9968 | ||
9969 | if (mips_opts.mips16) | |
9970 | { | |
9971 | percent_op = mips16_percent_op; | |
9972 | limit = ARRAY_SIZE (mips16_percent_op); | |
9973 | } | |
9974 | else | |
9975 | { | |
9976 | percent_op = mips_percent_op; | |
9977 | limit = ARRAY_SIZE (mips_percent_op); | |
9978 | } | |
76b3015f | 9979 | |
d6f16593 | 9980 | for (i = 0; i < limit; i++) |
5e0116d5 | 9981 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9982 | { |
3f98094e DJ |
9983 | int len = strlen (percent_op[i].str); |
9984 | ||
9985 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9986 | continue; | |
9987 | ||
5e0116d5 RS |
9988 | *str += strlen (percent_op[i].str); |
9989 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9990 | |
5e0116d5 RS |
9991 | /* Check whether the output BFD supports this relocation. |
9992 | If not, issue an error and fall back on something safe. */ | |
9993 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9994 | { |
5e0116d5 RS |
9995 | as_bad ("relocation %s isn't supported by the current ABI", |
9996 | percent_op[i].str); | |
01a3f561 | 9997 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9998 | } |
5e0116d5 | 9999 | return TRUE; |
394f9b3a | 10000 | } |
5e0116d5 | 10001 | return FALSE; |
394f9b3a | 10002 | } |
ad8d3bb3 | 10003 | |
ad8d3bb3 | 10004 | |
5e0116d5 RS |
10005 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10006 | expression in *EP and the relocations in the array starting | |
10007 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10008 | |
01a3f561 | 10009 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10010 | |
5e0116d5 | 10011 | static size_t |
17a2f251 TS |
10012 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10013 | char *str) | |
ad8d3bb3 | 10014 | { |
5e0116d5 RS |
10015 | bfd_reloc_code_real_type reversed_reloc[3]; |
10016 | size_t reloc_index, i; | |
09b8f35a RS |
10017 | int crux_depth, str_depth; |
10018 | char *crux; | |
5e0116d5 RS |
10019 | |
10020 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10021 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10022 | of the main expression and with CRUX_DEPTH containing the number | |
10023 | of open brackets at that point. */ | |
10024 | reloc_index = -1; | |
10025 | str_depth = 0; | |
10026 | do | |
fb1b3232 | 10027 | { |
09b8f35a RS |
10028 | reloc_index++; |
10029 | crux = str; | |
10030 | crux_depth = str_depth; | |
10031 | ||
10032 | /* Skip over whitespace and brackets, keeping count of the number | |
10033 | of brackets. */ | |
10034 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10035 | if (*str++ == '(') | |
10036 | str_depth++; | |
5e0116d5 | 10037 | } |
09b8f35a RS |
10038 | while (*str == '%' |
10039 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10040 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10041 | |
09b8f35a | 10042 | my_getExpression (ep, crux); |
5e0116d5 | 10043 | str = expr_end; |
394f9b3a | 10044 | |
5e0116d5 | 10045 | /* Match every open bracket. */ |
09b8f35a | 10046 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10047 | if (*str++ == ')') |
09b8f35a | 10048 | crux_depth--; |
394f9b3a | 10049 | |
09b8f35a | 10050 | if (crux_depth > 0) |
5e0116d5 | 10051 | as_bad ("unclosed '('"); |
394f9b3a | 10052 | |
5e0116d5 | 10053 | expr_end = str; |
252b5132 | 10054 | |
01a3f561 | 10055 | if (reloc_index != 0) |
64bdfcaf RS |
10056 | { |
10057 | prev_reloc_op_frag = frag_now; | |
10058 | for (i = 0; i < reloc_index; i++) | |
10059 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10060 | } | |
fb1b3232 | 10061 | |
5e0116d5 | 10062 | return reloc_index; |
252b5132 RH |
10063 | } |
10064 | ||
10065 | static void | |
17a2f251 | 10066 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10067 | { |
10068 | char *save_in; | |
98aa84af | 10069 | valueT val; |
252b5132 RH |
10070 | |
10071 | save_in = input_line_pointer; | |
10072 | input_line_pointer = str; | |
10073 | expression (ep); | |
10074 | expr_end = input_line_pointer; | |
10075 | input_line_pointer = save_in; | |
10076 | ||
10077 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10078 | then we bump the value of the symbol by 1 since that is how other | |
10079 | text symbols are handled. We don't bother to handle complex | |
10080 | expressions, just `.' plus or minus a constant. */ | |
10081 | if (mips_opts.mips16 | |
10082 | && ep->X_op == O_symbol | |
10083 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10084 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10085 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10086 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10087 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10088 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10089 | } |
10090 | ||
10091 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10092 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10093 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10094 | returned, or NULL on OK. */ |
10095 | ||
10096 | char * | |
17a2f251 | 10097 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10098 | { |
10099 | int prec; | |
10100 | LITTLENUM_TYPE words[4]; | |
10101 | char *t; | |
10102 | int i; | |
10103 | ||
10104 | switch (type) | |
10105 | { | |
10106 | case 'f': | |
10107 | prec = 2; | |
10108 | break; | |
10109 | ||
10110 | case 'd': | |
10111 | prec = 4; | |
10112 | break; | |
10113 | ||
10114 | default: | |
10115 | *sizeP = 0; | |
10116 | return _("bad call to md_atof"); | |
10117 | } | |
10118 | ||
10119 | t = atof_ieee (input_line_pointer, type, words); | |
10120 | if (t) | |
10121 | input_line_pointer = t; | |
10122 | ||
10123 | *sizeP = prec * 2; | |
10124 | ||
10125 | if (! target_big_endian) | |
10126 | { | |
10127 | for (i = prec - 1; i >= 0; i--) | |
10128 | { | |
17a2f251 | 10129 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10130 | litP += 2; |
10131 | } | |
10132 | } | |
10133 | else | |
10134 | { | |
10135 | for (i = 0; i < prec; i++) | |
10136 | { | |
17a2f251 | 10137 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10138 | litP += 2; |
10139 | } | |
10140 | } | |
bdaaa2e1 | 10141 | |
252b5132 RH |
10142 | return NULL; |
10143 | } | |
10144 | ||
10145 | void | |
17a2f251 | 10146 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10147 | { |
10148 | if (target_big_endian) | |
10149 | number_to_chars_bigendian (buf, val, n); | |
10150 | else | |
10151 | number_to_chars_littleendian (buf, val, n); | |
10152 | } | |
10153 | \f | |
ae948b86 | 10154 | #ifdef OBJ_ELF |
e013f690 TS |
10155 | static int support_64bit_objects(void) |
10156 | { | |
10157 | const char **list, **l; | |
aa3d8fdf | 10158 | int yes; |
e013f690 TS |
10159 | |
10160 | list = bfd_target_list (); | |
10161 | for (l = list; *l != NULL; l++) | |
10162 | #ifdef TE_TMIPS | |
10163 | /* This is traditional mips */ | |
10164 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10165 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10166 | #else | |
10167 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10168 | || strcmp (*l, "elf64-littlemips") == 0) | |
10169 | #endif | |
10170 | break; | |
aa3d8fdf | 10171 | yes = (*l != NULL); |
e013f690 | 10172 | free (list); |
aa3d8fdf | 10173 | return yes; |
e013f690 | 10174 | } |
ae948b86 | 10175 | #endif /* OBJ_ELF */ |
e013f690 | 10176 | |
78849248 | 10177 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10178 | |
e972090a NC |
10179 | struct option md_longopts[] = |
10180 | { | |
f9b4148d CD |
10181 | /* Options which specify architecture. */ |
10182 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10183 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10184 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10185 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10186 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10187 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10188 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10189 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10190 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10191 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10192 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10193 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10194 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10195 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10196 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10197 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10198 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10199 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10200 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10201 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10202 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10203 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10204 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10205 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10206 | |
10207 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10208 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10209 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10210 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10211 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10212 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10213 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10214 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10215 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10216 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10217 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10218 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10219 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10220 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10221 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10222 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10223 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10224 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
f9b4148d CD |
10225 | |
10226 | /* Old-style architecture options. Don't add more of these. */ | |
74cd071d | 10227 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8) |
f9b4148d CD |
10228 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10229 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10230 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10231 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10232 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10233 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10234 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10235 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10236 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10237 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10238 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10239 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10240 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10241 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10242 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10243 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10244 | ||
10245 | /* Options which enable bug fixes. */ | |
10246 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10247 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10248 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10249 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10250 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10251 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10252 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10253 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10254 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10255 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10256 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10257 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10258 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10259 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10260 | |
10261 | /* Miscellaneous options. */ | |
7d8e00cf | 10262 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10263 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10264 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10265 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10266 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10267 | {"break", no_argument, NULL, OPTION_BREAK}, |
10268 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10269 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10270 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10271 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10272 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10273 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10274 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10275 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10276 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10277 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10278 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10279 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10280 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10281 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10282 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10283 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10284 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10285 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10286 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10287 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10288 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10289 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10290 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10291 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10292 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10293 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10294 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10295 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10296 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10297 | |
10298 | /* ELF-specific options. */ | |
156c2f8b | 10299 | #ifdef OBJ_ELF |
aed1a261 | 10300 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10301 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10302 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10303 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10304 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10305 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10306 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10307 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10308 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10309 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10310 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10311 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10312 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10313 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10314 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10315 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10316 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10317 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10318 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10319 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10320 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10321 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10322 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10323 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10324 | #endif /* OBJ_ELF */ |
f9b4148d | 10325 | |
252b5132 RH |
10326 | {NULL, no_argument, NULL, 0} |
10327 | }; | |
156c2f8b | 10328 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10329 | |
316f5878 RS |
10330 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10331 | NEW_VALUE. Warn if another value was already specified. Note: | |
10332 | we have to defer parsing the -march and -mtune arguments in order | |
10333 | to handle 'from-abi' correctly, since the ABI might be specified | |
10334 | in a later argument. */ | |
10335 | ||
10336 | static void | |
17a2f251 | 10337 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10338 | { |
10339 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10340 | as_warn (_("A different %s was already specified, is now %s"), | |
10341 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10342 | new_value); | |
10343 | ||
10344 | *string_ptr = new_value; | |
10345 | } | |
10346 | ||
252b5132 | 10347 | int |
17a2f251 | 10348 | md_parse_option (int c, char *arg) |
252b5132 RH |
10349 | { |
10350 | switch (c) | |
10351 | { | |
119d663a NC |
10352 | case OPTION_CONSTRUCT_FLOATS: |
10353 | mips_disable_float_construction = 0; | |
10354 | break; | |
bdaaa2e1 | 10355 | |
119d663a NC |
10356 | case OPTION_NO_CONSTRUCT_FLOATS: |
10357 | mips_disable_float_construction = 1; | |
10358 | break; | |
bdaaa2e1 | 10359 | |
252b5132 RH |
10360 | case OPTION_TRAP: |
10361 | mips_trap = 1; | |
10362 | break; | |
10363 | ||
10364 | case OPTION_BREAK: | |
10365 | mips_trap = 0; | |
10366 | break; | |
10367 | ||
10368 | case OPTION_EB: | |
10369 | target_big_endian = 1; | |
10370 | break; | |
10371 | ||
10372 | case OPTION_EL: | |
10373 | target_big_endian = 0; | |
10374 | break; | |
10375 | ||
10376 | case 'O': | |
10377 | if (arg && arg[1] == '0') | |
10378 | mips_optimize = 1; | |
10379 | else | |
10380 | mips_optimize = 2; | |
10381 | break; | |
10382 | ||
10383 | case 'g': | |
10384 | if (arg == NULL) | |
10385 | mips_debug = 2; | |
10386 | else | |
10387 | mips_debug = atoi (arg); | |
10388 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10389 | optimizations which limit full symbolic debugging. We take | |
10390 | that to be equivalent to -O0. */ | |
10391 | if (mips_debug == 2) | |
10392 | mips_optimize = 1; | |
10393 | break; | |
10394 | ||
10395 | case OPTION_MIPS1: | |
316f5878 | 10396 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10397 | break; |
10398 | ||
10399 | case OPTION_MIPS2: | |
316f5878 | 10400 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10401 | break; |
10402 | ||
10403 | case OPTION_MIPS3: | |
316f5878 | 10404 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10405 | break; |
10406 | ||
10407 | case OPTION_MIPS4: | |
316f5878 | 10408 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10409 | break; |
10410 | ||
84ea6cf2 | 10411 | case OPTION_MIPS5: |
316f5878 | 10412 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10413 | break; |
10414 | ||
e7af610e | 10415 | case OPTION_MIPS32: |
316f5878 | 10416 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10417 | break; |
10418 | ||
af7ee8bf CD |
10419 | case OPTION_MIPS32R2: |
10420 | file_mips_isa = ISA_MIPS32R2; | |
10421 | break; | |
10422 | ||
5f74bc13 CD |
10423 | case OPTION_MIPS64R2: |
10424 | file_mips_isa = ISA_MIPS64R2; | |
10425 | break; | |
10426 | ||
84ea6cf2 | 10427 | case OPTION_MIPS64: |
316f5878 | 10428 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10429 | break; |
10430 | ||
ec68c924 | 10431 | case OPTION_MTUNE: |
316f5878 RS |
10432 | mips_set_option_string (&mips_tune_string, arg); |
10433 | break; | |
ec68c924 | 10434 | |
316f5878 RS |
10435 | case OPTION_MARCH: |
10436 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10437 | break; |
10438 | ||
10439 | case OPTION_M4650: | |
316f5878 RS |
10440 | mips_set_option_string (&mips_arch_string, "4650"); |
10441 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10442 | break; |
10443 | ||
10444 | case OPTION_NO_M4650: | |
10445 | break; | |
10446 | ||
10447 | case OPTION_M4010: | |
316f5878 RS |
10448 | mips_set_option_string (&mips_arch_string, "4010"); |
10449 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10450 | break; |
10451 | ||
10452 | case OPTION_NO_M4010: | |
10453 | break; | |
10454 | ||
10455 | case OPTION_M4100: | |
316f5878 RS |
10456 | mips_set_option_string (&mips_arch_string, "4100"); |
10457 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10458 | break; |
10459 | ||
10460 | case OPTION_NO_M4100: | |
10461 | break; | |
10462 | ||
252b5132 | 10463 | case OPTION_M3900: |
316f5878 RS |
10464 | mips_set_option_string (&mips_arch_string, "3900"); |
10465 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10466 | break; |
bdaaa2e1 | 10467 | |
252b5132 RH |
10468 | case OPTION_NO_M3900: |
10469 | break; | |
10470 | ||
deec1734 CD |
10471 | case OPTION_MDMX: |
10472 | mips_opts.ase_mdmx = 1; | |
10473 | break; | |
10474 | ||
10475 | case OPTION_NO_MDMX: | |
10476 | mips_opts.ase_mdmx = 0; | |
10477 | break; | |
10478 | ||
74cd071d CF |
10479 | case OPTION_DSP: |
10480 | mips_opts.ase_dsp = 1; | |
10481 | break; | |
10482 | ||
10483 | case OPTION_NO_DSP: | |
10484 | mips_opts.ase_dsp = 0; | |
10485 | break; | |
10486 | ||
252b5132 RH |
10487 | case OPTION_MIPS16: |
10488 | mips_opts.mips16 = 1; | |
7d10b47d | 10489 | mips_no_prev_insn (); |
252b5132 RH |
10490 | break; |
10491 | ||
10492 | case OPTION_NO_MIPS16: | |
10493 | mips_opts.mips16 = 0; | |
7d10b47d | 10494 | mips_no_prev_insn (); |
252b5132 RH |
10495 | break; |
10496 | ||
1f25f5d3 CD |
10497 | case OPTION_MIPS3D: |
10498 | mips_opts.ase_mips3d = 1; | |
10499 | break; | |
10500 | ||
10501 | case OPTION_NO_MIPS3D: | |
10502 | mips_opts.ase_mips3d = 0; | |
10503 | break; | |
10504 | ||
d766e8ec RS |
10505 | case OPTION_FIX_VR4120: |
10506 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10507 | break; |
10508 | ||
d766e8ec RS |
10509 | case OPTION_NO_FIX_VR4120: |
10510 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10511 | break; |
10512 | ||
7d8e00cf RS |
10513 | case OPTION_FIX_VR4130: |
10514 | mips_fix_vr4130 = 1; | |
10515 | break; | |
10516 | ||
10517 | case OPTION_NO_FIX_VR4130: | |
10518 | mips_fix_vr4130 = 0; | |
10519 | break; | |
10520 | ||
4a6a3df4 AO |
10521 | case OPTION_RELAX_BRANCH: |
10522 | mips_relax_branch = 1; | |
10523 | break; | |
10524 | ||
10525 | case OPTION_NO_RELAX_BRANCH: | |
10526 | mips_relax_branch = 0; | |
10527 | break; | |
10528 | ||
aa6975fb ILT |
10529 | case OPTION_MSHARED: |
10530 | mips_in_shared = TRUE; | |
10531 | break; | |
10532 | ||
10533 | case OPTION_MNO_SHARED: | |
10534 | mips_in_shared = FALSE; | |
10535 | break; | |
10536 | ||
aed1a261 RS |
10537 | case OPTION_MSYM32: |
10538 | mips_opts.sym32 = TRUE; | |
10539 | break; | |
10540 | ||
10541 | case OPTION_MNO_SYM32: | |
10542 | mips_opts.sym32 = FALSE; | |
10543 | break; | |
10544 | ||
0f074f60 | 10545 | #ifdef OBJ_ELF |
252b5132 RH |
10546 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10547 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10548 | intended to be compatible with Irix 5. */ | |
10549 | case OPTION_CALL_SHARED: | |
10550 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10551 | { | |
10552 | as_bad (_("-call_shared is supported only for ELF format")); | |
10553 | return 0; | |
10554 | } | |
10555 | mips_pic = SVR4_PIC; | |
143d77c5 | 10556 | mips_abicalls = TRUE; |
252b5132 RH |
10557 | if (g_switch_seen && g_switch_value != 0) |
10558 | { | |
10559 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10560 | return 0; | |
10561 | } | |
10562 | g_switch_value = 0; | |
10563 | break; | |
10564 | ||
10565 | case OPTION_NON_SHARED: | |
10566 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10567 | { | |
10568 | as_bad (_("-non_shared is supported only for ELF format")); | |
10569 | return 0; | |
10570 | } | |
10571 | mips_pic = NO_PIC; | |
143d77c5 | 10572 | mips_abicalls = FALSE; |
252b5132 RH |
10573 | break; |
10574 | ||
10575 | /* The -xgot option tells the assembler to use 32 offsets when | |
10576 | accessing the got in SVR4_PIC mode. It is for Irix | |
10577 | compatibility. */ | |
10578 | case OPTION_XGOT: | |
10579 | mips_big_got = 1; | |
10580 | break; | |
0f074f60 | 10581 | #endif /* OBJ_ELF */ |
252b5132 RH |
10582 | |
10583 | case 'G': | |
6caf9ef4 TS |
10584 | g_switch_value = atoi (arg); |
10585 | g_switch_seen = 1; | |
10586 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10587 | { |
3e722fb5 | 10588 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10589 | return 0; |
10590 | } | |
252b5132 RH |
10591 | break; |
10592 | ||
0f074f60 | 10593 | #ifdef OBJ_ELF |
34ba82a8 TS |
10594 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10595 | and -mabi=64. */ | |
252b5132 | 10596 | case OPTION_32: |
34ba82a8 TS |
10597 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10598 | { | |
10599 | as_bad (_("-32 is supported for ELF format only")); | |
10600 | return 0; | |
10601 | } | |
316f5878 | 10602 | mips_abi = O32_ABI; |
252b5132 RH |
10603 | break; |
10604 | ||
e013f690 | 10605 | case OPTION_N32: |
34ba82a8 TS |
10606 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10607 | { | |
10608 | as_bad (_("-n32 is supported for ELF format only")); | |
10609 | return 0; | |
10610 | } | |
316f5878 | 10611 | mips_abi = N32_ABI; |
e013f690 | 10612 | break; |
252b5132 | 10613 | |
e013f690 | 10614 | case OPTION_64: |
34ba82a8 TS |
10615 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10616 | { | |
10617 | as_bad (_("-64 is supported for ELF format only")); | |
10618 | return 0; | |
10619 | } | |
316f5878 | 10620 | mips_abi = N64_ABI; |
e013f690 TS |
10621 | if (! support_64bit_objects()) |
10622 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10623 | break; |
ae948b86 | 10624 | #endif /* OBJ_ELF */ |
252b5132 | 10625 | |
c97ef257 | 10626 | case OPTION_GP32: |
a325df1d | 10627 | file_mips_gp32 = 1; |
c97ef257 AH |
10628 | break; |
10629 | ||
10630 | case OPTION_GP64: | |
a325df1d | 10631 | file_mips_gp32 = 0; |
c97ef257 | 10632 | break; |
252b5132 | 10633 | |
ca4e0257 | 10634 | case OPTION_FP32: |
a325df1d | 10635 | file_mips_fp32 = 1; |
316f5878 RS |
10636 | break; |
10637 | ||
10638 | case OPTION_FP64: | |
10639 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10640 | break; |
10641 | ||
ae948b86 | 10642 | #ifdef OBJ_ELF |
252b5132 | 10643 | case OPTION_MABI: |
34ba82a8 TS |
10644 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10645 | { | |
10646 | as_bad (_("-mabi is supported for ELF format only")); | |
10647 | return 0; | |
10648 | } | |
e013f690 | 10649 | if (strcmp (arg, "32") == 0) |
316f5878 | 10650 | mips_abi = O32_ABI; |
e013f690 | 10651 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10652 | mips_abi = O64_ABI; |
e013f690 | 10653 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10654 | mips_abi = N32_ABI; |
e013f690 TS |
10655 | else if (strcmp (arg, "64") == 0) |
10656 | { | |
316f5878 | 10657 | mips_abi = N64_ABI; |
e013f690 TS |
10658 | if (! support_64bit_objects()) |
10659 | as_fatal (_("No compiled in support for 64 bit object file " | |
10660 | "format")); | |
10661 | } | |
10662 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10663 | mips_abi = EABI_ABI; |
e013f690 | 10664 | else |
da0e507f TS |
10665 | { |
10666 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10667 | return 0; | |
10668 | } | |
252b5132 | 10669 | break; |
e013f690 | 10670 | #endif /* OBJ_ELF */ |
252b5132 | 10671 | |
6b76fefe | 10672 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10673 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10674 | break; |
10675 | ||
9ee72ff1 | 10676 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10677 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10678 | break; |
10679 | ||
ecb4347a DJ |
10680 | #ifdef OBJ_ELF |
10681 | case OPTION_MDEBUG: | |
b34976b6 | 10682 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10683 | break; |
10684 | ||
10685 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10686 | mips_flag_mdebug = FALSE; |
ecb4347a | 10687 | break; |
dcd410fe RO |
10688 | |
10689 | case OPTION_PDR: | |
10690 | mips_flag_pdr = TRUE; | |
10691 | break; | |
10692 | ||
10693 | case OPTION_NO_PDR: | |
10694 | mips_flag_pdr = FALSE; | |
10695 | break; | |
ecb4347a DJ |
10696 | #endif /* OBJ_ELF */ |
10697 | ||
252b5132 RH |
10698 | default: |
10699 | return 0; | |
10700 | } | |
10701 | ||
10702 | return 1; | |
10703 | } | |
316f5878 RS |
10704 | \f |
10705 | /* Set up globals to generate code for the ISA or processor | |
10706 | described by INFO. */ | |
252b5132 | 10707 | |
252b5132 | 10708 | static void |
17a2f251 | 10709 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10710 | { |
316f5878 | 10711 | if (info != 0) |
252b5132 | 10712 | { |
fef14a42 TS |
10713 | file_mips_arch = info->cpu; |
10714 | mips_opts.arch = info->cpu; | |
316f5878 | 10715 | mips_opts.isa = info->isa; |
252b5132 | 10716 | } |
252b5132 RH |
10717 | } |
10718 | ||
252b5132 | 10719 | |
316f5878 | 10720 | /* Likewise for tuning. */ |
252b5132 | 10721 | |
316f5878 | 10722 | static void |
17a2f251 | 10723 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10724 | { |
10725 | if (info != 0) | |
fef14a42 | 10726 | mips_tune = info->cpu; |
316f5878 | 10727 | } |
80cc45a5 | 10728 | |
34ba82a8 | 10729 | |
252b5132 | 10730 | void |
17a2f251 | 10731 | mips_after_parse_args (void) |
e9670677 | 10732 | { |
fef14a42 TS |
10733 | const struct mips_cpu_info *arch_info = 0; |
10734 | const struct mips_cpu_info *tune_info = 0; | |
10735 | ||
e9670677 | 10736 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10737 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10738 | { |
6caf9ef4 | 10739 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10740 | as_bad (_("-G not supported in this configuration.")); |
10741 | g_switch_value = 0; | |
10742 | } | |
10743 | ||
cac012d6 AO |
10744 | if (mips_abi == NO_ABI) |
10745 | mips_abi = MIPS_DEFAULT_ABI; | |
10746 | ||
22923709 RS |
10747 | /* The following code determines the architecture and register size. |
10748 | Similar code was added to GCC 3.3 (see override_options() in | |
10749 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10750 | as much as possible. */ | |
e9670677 | 10751 | |
316f5878 | 10752 | if (mips_arch_string != 0) |
fef14a42 | 10753 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10754 | |
316f5878 | 10755 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10756 | { |
316f5878 | 10757 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10758 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10759 | the -march selection (if any). */ |
fef14a42 | 10760 | if (arch_info != 0) |
e9670677 | 10761 | { |
316f5878 RS |
10762 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10763 | There's no harm in specifying both as long as the ISA levels | |
10764 | are the same. */ | |
fef14a42 | 10765 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10766 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10767 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10768 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10769 | } |
316f5878 | 10770 | else |
fef14a42 | 10771 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10772 | } |
10773 | ||
fef14a42 TS |
10774 | if (arch_info == 0) |
10775 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10776 | |
fef14a42 | 10777 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10778 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10779 | arch_info->name); |
10780 | ||
10781 | mips_set_architecture (arch_info); | |
10782 | ||
10783 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10784 | if (mips_tune_string != 0) | |
10785 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10786 | |
fef14a42 TS |
10787 | if (tune_info == 0) |
10788 | mips_set_tune (arch_info); | |
10789 | else | |
10790 | mips_set_tune (tune_info); | |
e9670677 | 10791 | |
316f5878 | 10792 | if (file_mips_gp32 >= 0) |
e9670677 | 10793 | { |
316f5878 RS |
10794 | /* The user specified the size of the integer registers. Make sure |
10795 | it agrees with the ABI and ISA. */ | |
10796 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10797 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10798 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10799 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10800 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10801 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10802 | } |
10803 | else | |
10804 | { | |
316f5878 RS |
10805 | /* Infer the integer register size from the ABI and processor. |
10806 | Restrict ourselves to 32-bit registers if that's all the | |
10807 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10808 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10809 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10810 | } |
10811 | ||
316f5878 RS |
10812 | /* ??? GAS treats single-float processors as though they had 64-bit |
10813 | float registers (although it complains when double-precision | |
10814 | instructions are used). As things stand, saying they have 32-bit | |
10815 | registers would lead to spurious "register must be even" messages. | |
10816 | So here we assume float registers are always the same size as | |
10817 | integer ones, unless the user says otherwise. */ | |
10818 | if (file_mips_fp32 < 0) | |
10819 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10820 | |
316f5878 | 10821 | /* End of GCC-shared inference code. */ |
e9670677 | 10822 | |
17a2f251 TS |
10823 | /* This flag is set when we have a 64-bit capable CPU but use only |
10824 | 32-bit wide registers. Note that EABI does not use it. */ | |
10825 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10826 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10827 | || mips_abi == O32_ABI)) | |
316f5878 | 10828 | mips_32bitmode = 1; |
e9670677 MR |
10829 | |
10830 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10831 | as_bad (_("trap exception not supported at ISA 1")); | |
10832 | ||
e9670677 MR |
10833 | /* If the selected architecture includes support for ASEs, enable |
10834 | generation of code for them. */ | |
a4672219 | 10835 | if (mips_opts.mips16 == -1) |
fef14a42 | 10836 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10837 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10838 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10839 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10840 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
74cd071d CF |
10841 | if (mips_opts.ase_dsp == -1) |
10842 | mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0; | |
e9670677 | 10843 | |
e9670677 | 10844 | file_mips_isa = mips_opts.isa; |
a4672219 | 10845 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10846 | file_ase_mips3d = mips_opts.ase_mips3d; |
10847 | file_ase_mdmx = mips_opts.ase_mdmx; | |
74cd071d | 10848 | file_ase_dsp = mips_opts.ase_dsp; |
e9670677 MR |
10849 | mips_opts.gp32 = file_mips_gp32; |
10850 | mips_opts.fp32 = file_mips_fp32; | |
10851 | ||
ecb4347a DJ |
10852 | if (mips_flag_mdebug < 0) |
10853 | { | |
10854 | #ifdef OBJ_MAYBE_ECOFF | |
10855 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10856 | mips_flag_mdebug = 1; | |
10857 | else | |
10858 | #endif /* OBJ_MAYBE_ECOFF */ | |
10859 | mips_flag_mdebug = 0; | |
10860 | } | |
e9670677 MR |
10861 | } |
10862 | \f | |
10863 | void | |
17a2f251 | 10864 | mips_init_after_args (void) |
252b5132 RH |
10865 | { |
10866 | /* initialize opcodes */ | |
10867 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10868 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10869 | } |
10870 | ||
10871 | long | |
17a2f251 | 10872 | md_pcrel_from (fixS *fixP) |
252b5132 | 10873 | { |
a7ebbfdf TS |
10874 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10875 | switch (fixP->fx_r_type) | |
10876 | { | |
10877 | case BFD_RELOC_16_PCREL_S2: | |
10878 | case BFD_RELOC_MIPS_JMP: | |
10879 | /* Return the address of the delay slot. */ | |
10880 | return addr + 4; | |
10881 | default: | |
10882 | return addr; | |
10883 | } | |
252b5132 RH |
10884 | } |
10885 | ||
252b5132 RH |
10886 | /* This is called before the symbol table is processed. In order to |
10887 | work with gcc when using mips-tfile, we must keep all local labels. | |
10888 | However, in other cases, we want to discard them. If we were | |
10889 | called with -g, but we didn't see any debugging information, it may | |
10890 | mean that gcc is smuggling debugging information through to | |
10891 | mips-tfile, in which case we must generate all local labels. */ | |
10892 | ||
10893 | void | |
17a2f251 | 10894 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10895 | { |
10896 | #ifndef NO_ECOFF_DEBUGGING | |
10897 | if (ECOFF_DEBUGGING | |
10898 | && mips_debug != 0 | |
10899 | && ! ecoff_debugging_seen) | |
10900 | flag_keep_locals = 1; | |
10901 | #endif | |
10902 | } | |
10903 | ||
3b91255e | 10904 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 10905 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
10906 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
10907 | relocation operators. | |
10908 | ||
10909 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10910 | expression if: | |
10911 | ||
10912 | (a) it refers to the same symbol; and | |
10913 | (b) the offset applied in the %lo() expression is no lower than | |
10914 | the offset applied in the %got() or %hi(). | |
10915 | ||
10916 | (b) allows us to cope with code like: | |
10917 | ||
10918 | lui $4,%hi(foo) | |
10919 | lh $4,%lo(foo+2)($4) | |
10920 | ||
10921 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10922 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10923 | the high 16 bits. | |
10924 | ||
10925 | When several %lo()s match a particular %got() or %hi(), we use the | |
10926 | following rules to distinguish them: | |
10927 | ||
10928 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10929 | higher offsets. | |
10930 | ||
10931 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10932 | that already have a matching %got() or %hi(). | |
10933 | ||
10934 | (3) later %lo()s are better than earlier %lo()s. | |
10935 | ||
10936 | These rules are applied in order. | |
10937 | ||
10938 | (1) means, among other things, that %lo()s with identical offsets are | |
10939 | chosen if they exist. | |
10940 | ||
10941 | (2) means that we won't associate several high-part relocations with | |
10942 | the same low-part relocation unless there's no alternative. Having | |
10943 | several high parts for the same low part is a GNU extension; this rule | |
10944 | allows careful users to avoid it. | |
10945 | ||
10946 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10947 | with the last high-part relocation being at the front of the list. | |
10948 | It therefore makes sense to choose the last matching low-part | |
10949 | relocation, all other things being equal. It's also easier | |
10950 | to code that way. */ | |
252b5132 RH |
10951 | |
10952 | void | |
17a2f251 | 10953 | mips_frob_file (void) |
252b5132 RH |
10954 | { |
10955 | struct mips_hi_fixup *l; | |
10956 | ||
10957 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10958 | { | |
10959 | segment_info_type *seginfo; | |
3b91255e RS |
10960 | bfd_boolean matched_lo_p; |
10961 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10962 | |
5919d012 | 10963 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10964 | |
5919d012 RS |
10965 | /* If a GOT16 relocation turns out to be against a global symbol, |
10966 | there isn't supposed to be a matching LO. */ | |
10967 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10968 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10969 | continue; | |
10970 | ||
10971 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10972 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10973 | continue; |
10974 | ||
252b5132 | 10975 | seginfo = seg_info (l->seg); |
252b5132 | 10976 | |
3b91255e RS |
10977 | /* Set HI_POS to the position of this relocation in the chain. |
10978 | Set LO_POS to the position of the chosen low-part relocation. | |
10979 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10980 | relocation that matches an immediately-preceding high-part | |
10981 | relocation. */ | |
10982 | hi_pos = NULL; | |
10983 | lo_pos = NULL; | |
10984 | matched_lo_p = FALSE; | |
10985 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10986 | { | |
10987 | if (*pos == l->fixp) | |
10988 | hi_pos = pos; | |
10989 | ||
704803a9 MR |
10990 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
10991 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
10992 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
10993 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10994 | && (lo_pos == NULL | |
10995 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10996 | || (!matched_lo_p | |
10997 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10998 | lo_pos = pos; | |
10999 | ||
11000 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11001 | && fixup_has_matching_lo_p (*pos)); | |
11002 | } | |
11003 | ||
11004 | /* If we found a match, remove the high-part relocation from its | |
11005 | current position and insert it before the low-part relocation. | |
11006 | Make the offsets match so that fixup_has_matching_lo_p() | |
11007 | will return true. | |
11008 | ||
11009 | We don't warn about unmatched high-part relocations since some | |
11010 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11011 | instructions. */ | |
11012 | if (lo_pos != NULL) | |
11013 | { | |
11014 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11015 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11016 | { |
3b91255e RS |
11017 | *hi_pos = l->fixp->fx_next; |
11018 | l->fixp->fx_next = *lo_pos; | |
11019 | *lo_pos = l->fixp; | |
252b5132 | 11020 | } |
252b5132 RH |
11021 | } |
11022 | } | |
11023 | } | |
11024 | ||
3e722fb5 | 11025 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11026 | We have to prevent gas from dropping them. */ |
252b5132 | 11027 | |
252b5132 | 11028 | int |
17a2f251 | 11029 | mips_force_relocation (fixS *fixp) |
252b5132 | 11030 | { |
ae6063d4 | 11031 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11032 | return 1; |
11033 | ||
f6688943 TS |
11034 | if (HAVE_NEWABI |
11035 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11036 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11037 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11038 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11039 | return 1; | |
11040 | ||
3e722fb5 | 11041 | return 0; |
252b5132 RH |
11042 | } |
11043 | ||
45f8dfe8 AO |
11044 | /* This hook is called before a fix is simplified. We don't really |
11045 | decide whether to skip a fix here. Rather, we turn global symbols | |
11046 | used as branch targets into local symbols, such that they undergo | |
11047 | simplification. We can only do this if the symbol is defined and | |
11048 | it is in the same section as the branch. If this doesn't hold, we | |
11049 | emit a better error message than just saying the relocation is not | |
11050 | valid for the selected object format. | |
11051 | ||
11052 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11053 | segment in which the fix up occurs. The return value should be | |
11054 | non-zero to indicate the fix-up is valid for further | |
11055 | simplifications. */ | |
11056 | ||
11057 | int | |
17a2f251 | 11058 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11059 | { |
11060 | /* There's a lot of discussion on whether it should be possible to | |
11061 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11062 | seems to be that it can, but gas/bfd are very broken in creating | |
11063 | RELA relocations for this, so for now we only accept branches to | |
11064 | symbols in the same section. Anything else is of dubious value, | |
11065 | since there's no guarantee that at link time the symbol would be | |
11066 | in range. Even for branches to local symbols this is arguably | |
11067 | wrong, since it we assume the symbol is not going to be | |
11068 | overridden, which should be possible per ELF library semantics, | |
11069 | but then, there isn't a dynamic relocation that could be used to | |
11070 | this effect, and the target would likely be out of range as well. | |
11071 | ||
11072 | Unfortunately, it seems that there is too much code out there | |
11073 | that relies on branches to symbols that are global to be resolved | |
11074 | as if they were local, like the IRIX tools do, so we do it as | |
11075 | well, but with a warning so that people are reminded to fix their | |
11076 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11077 | targets, this entire block should go away (and probably the | |
11078 | whole function). */ | |
11079 | ||
11080 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
11081 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11082 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
11083 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
11084 | && fixP->fx_addsy) | |
11085 | { | |
11086 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11087 | { | |
11088 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11089 | _("Cannot branch to undefined symbol.")); | |
11090 | /* Avoid any further errors about this fixup. */ | |
11091 | fixP->fx_done = 1; | |
11092 | } | |
11093 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11094 | { | |
11095 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11096 | _("Cannot branch to symbol in another section.")); | |
11097 | fixP->fx_done = 1; | |
11098 | } | |
11099 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11100 | { | |
11101 | symbolS *sym = fixP->fx_addsy; | |
11102 | ||
115695a8 CD |
11103 | if (mips_pic == SVR4_PIC) |
11104 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11105 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11106 | |
11107 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11108 | S_GET_SEGMENT (sym), | |
11109 | S_GET_VALUE (sym), | |
11110 | symbol_get_frag (sym)); | |
11111 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11112 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11113 | assert (symbol_resolved_p (sym)); | |
11114 | symbol_mark_resolved (fixP->fx_addsy); | |
11115 | } | |
11116 | } | |
11117 | ||
11118 | return 1; | |
11119 | } | |
11120 | ||
252b5132 RH |
11121 | /* Apply a fixup to the object file. */ |
11122 | ||
94f592af | 11123 | void |
55cf6793 | 11124 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11125 | { |
874e8986 | 11126 | bfd_byte *buf; |
98aa84af | 11127 | long insn; |
a7ebbfdf | 11128 | reloc_howto_type *howto; |
252b5132 | 11129 | |
a7ebbfdf TS |
11130 | /* We ignore generic BFD relocations we don't know about. */ |
11131 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11132 | if (! howto) | |
11133 | return; | |
65551fa4 | 11134 | |
252b5132 RH |
11135 | assert (fixP->fx_size == 4 |
11136 | || fixP->fx_r_type == BFD_RELOC_16 | |
11137 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11138 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11139 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11140 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11141 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11142 | |
a7ebbfdf | 11143 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11144 | |
3e722fb5 | 11145 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
11146 | |
11147 | /* Don't treat parts of a composite relocation as done. There are two | |
11148 | reasons for this: | |
11149 | ||
11150 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11151 | should nevertheless be emitted if the first part is. | |
11152 | ||
11153 | (2) In normal usage, composite relocations are never assembly-time | |
11154 | constants. The easiest way of dealing with the pathological | |
11155 | exceptions is to generate a relocation against STN_UNDEF and | |
11156 | leave everything up to the linker. */ | |
11157 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11158 | fixP->fx_done = 1; |
11159 | ||
11160 | switch (fixP->fx_r_type) | |
11161 | { | |
3f98094e DJ |
11162 | case BFD_RELOC_MIPS_TLS_GD: |
11163 | case BFD_RELOC_MIPS_TLS_LDM: | |
11164 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11165 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11166 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11167 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11168 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11169 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11170 | /* fall through */ | |
11171 | ||
252b5132 | 11172 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11173 | case BFD_RELOC_MIPS_SHIFT5: |
11174 | case BFD_RELOC_MIPS_SHIFT6: | |
11175 | case BFD_RELOC_MIPS_GOT_DISP: | |
11176 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11177 | case BFD_RELOC_MIPS_GOT_OFST: | |
11178 | case BFD_RELOC_MIPS_SUB: | |
11179 | case BFD_RELOC_MIPS_INSERT_A: | |
11180 | case BFD_RELOC_MIPS_INSERT_B: | |
11181 | case BFD_RELOC_MIPS_DELETE: | |
11182 | case BFD_RELOC_MIPS_HIGHEST: | |
11183 | case BFD_RELOC_MIPS_HIGHER: | |
11184 | case BFD_RELOC_MIPS_SCN_DISP: | |
11185 | case BFD_RELOC_MIPS_REL16: | |
11186 | case BFD_RELOC_MIPS_RELGOT: | |
11187 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11188 | case BFD_RELOC_HI16: |
11189 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11190 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11191 | case BFD_RELOC_MIPS_LITERAL: |
11192 | case BFD_RELOC_MIPS_CALL16: | |
11193 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11194 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11195 | case BFD_RELOC_MIPS_GOT_HI16: |
11196 | case BFD_RELOC_MIPS_GOT_LO16: | |
11197 | case BFD_RELOC_MIPS_CALL_HI16: | |
11198 | case BFD_RELOC_MIPS_CALL_LO16: | |
11199 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11200 | case BFD_RELOC_MIPS16_HI16: |
11201 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11202 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11203 | /* Nothing needed to do. The value comes from the reloc entry */ |
11204 | break; | |
11205 | ||
11206 | case BFD_RELOC_MIPS16_JMP: | |
11207 | /* We currently always generate a reloc against a symbol, which | |
11208 | means that we don't want an addend even if the symbol is | |
11209 | defined. */ | |
a7ebbfdf | 11210 | *valP = 0; |
252b5132 RH |
11211 | break; |
11212 | ||
252b5132 RH |
11213 | case BFD_RELOC_64: |
11214 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11215 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11216 | if (fixP->fx_done) |
252b5132 RH |
11217 | { |
11218 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11219 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11220 | else |
11221 | { | |
a7ebbfdf | 11222 | valueT hiv; |
252b5132 | 11223 | |
a7ebbfdf | 11224 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11225 | hiv = 0xffffffff; |
11226 | else | |
11227 | hiv = 0; | |
b215186b | 11228 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11229 | *valP, 4); |
b215186b | 11230 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11231 | hiv, 4); |
252b5132 RH |
11232 | } |
11233 | } | |
11234 | break; | |
11235 | ||
056350c6 | 11236 | case BFD_RELOC_RVA: |
252b5132 RH |
11237 | case BFD_RELOC_32: |
11238 | /* If we are deleting this reloc entry, we must fill in the | |
11239 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11240 | resolved when it appears but is later defined. */ |
11241 | if (fixP->fx_done) | |
2132e3a3 | 11242 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11243 | break; |
11244 | ||
11245 | case BFD_RELOC_16: | |
11246 | /* If we are deleting this reloc entry, we must fill in the | |
11247 | value now. */ | |
252b5132 | 11248 | if (fixP->fx_done) |
2132e3a3 | 11249 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11250 | break; |
11251 | ||
11252 | case BFD_RELOC_LO16: | |
d6f16593 | 11253 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11254 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11255 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11256 | /* When handling an embedded PIC switch statement, we can wind |
11257 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11258 | if (fixP->fx_done) | |
11259 | { | |
a7ebbfdf | 11260 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11261 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11262 | _("relocation overflow")); | |
252b5132 RH |
11263 | if (target_big_endian) |
11264 | buf += 2; | |
2132e3a3 | 11265 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11266 | } |
11267 | break; | |
11268 | ||
11269 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11270 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11271 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11272 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11273 | |
252b5132 RH |
11274 | /* |
11275 | * We need to save the bits in the instruction since fixup_segment() | |
11276 | * might be deleting the relocation entry (i.e., a branch within | |
11277 | * the current segment). | |
11278 | */ | |
a7ebbfdf | 11279 | if (! fixP->fx_done) |
bb2d6cd7 | 11280 | break; |
252b5132 RH |
11281 | |
11282 | /* update old instruction data */ | |
252b5132 RH |
11283 | if (target_big_endian) |
11284 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11285 | else | |
11286 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11287 | ||
a7ebbfdf TS |
11288 | if (*valP + 0x20000 <= 0x3ffff) |
11289 | { | |
11290 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11291 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11292 | } |
11293 | else if (mips_pic == NO_PIC | |
11294 | && fixP->fx_done | |
11295 | && fixP->fx_frag->fr_address >= text_section->vma | |
11296 | && (fixP->fx_frag->fr_address | |
587aac4e | 11297 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11298 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11299 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11300 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11301 | { |
11302 | /* The branch offset is too large. If this is an | |
11303 | unconditional branch, and we are not generating PIC code, | |
11304 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11305 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11306 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11307 | else |
a7ebbfdf TS |
11308 | insn = 0x08000000; /* j */ |
11309 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11310 | fixP->fx_done = 0; | |
11311 | fixP->fx_addsy = section_symbol (text_section); | |
11312 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11313 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11314 | } |
11315 | else | |
11316 | { | |
11317 | /* If we got here, we have branch-relaxation disabled, | |
11318 | and there's nothing we can do to fix this instruction | |
11319 | without turning it into a longer sequence. */ | |
11320 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11321 | _("Branch out of range")); | |
252b5132 | 11322 | } |
252b5132 RH |
11323 | break; |
11324 | ||
11325 | case BFD_RELOC_VTABLE_INHERIT: | |
11326 | fixP->fx_done = 0; | |
11327 | if (fixP->fx_addsy | |
11328 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11329 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11330 | S_SET_WEAK (fixP->fx_addsy); | |
11331 | break; | |
11332 | ||
11333 | case BFD_RELOC_VTABLE_ENTRY: | |
11334 | fixP->fx_done = 0; | |
11335 | break; | |
11336 | ||
11337 | default: | |
11338 | internalError (); | |
11339 | } | |
a7ebbfdf TS |
11340 | |
11341 | /* Remember value for tc_gen_reloc. */ | |
11342 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11343 | } |
11344 | ||
252b5132 | 11345 | static symbolS * |
17a2f251 | 11346 | get_symbol (void) |
252b5132 RH |
11347 | { |
11348 | int c; | |
11349 | char *name; | |
11350 | symbolS *p; | |
11351 | ||
11352 | name = input_line_pointer; | |
11353 | c = get_symbol_end (); | |
11354 | p = (symbolS *) symbol_find_or_make (name); | |
11355 | *input_line_pointer = c; | |
11356 | return p; | |
11357 | } | |
11358 | ||
11359 | /* Align the current frag to a given power of two. The MIPS assembler | |
11360 | also automatically adjusts any preceding label. */ | |
11361 | ||
11362 | static void | |
17a2f251 | 11363 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11364 | { |
7d10b47d | 11365 | mips_emit_delays (); |
252b5132 RH |
11366 | frag_align (to, fill, 0); |
11367 | record_alignment (now_seg, to); | |
11368 | if (label != NULL) | |
11369 | { | |
11370 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11371 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11372 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11373 | } | |
11374 | } | |
11375 | ||
11376 | /* Align to a given power of two. .align 0 turns off the automatic | |
11377 | alignment used by the data creating pseudo-ops. */ | |
11378 | ||
11379 | static void | |
17a2f251 | 11380 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11381 | { |
11382 | register int temp; | |
11383 | register long temp_fill; | |
11384 | long max_alignment = 15; | |
11385 | ||
11386 | /* | |
11387 | ||
67c1ffbe | 11388 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11389 | to the aligned address. |
11390 | o It's not documented but auto alignment is reinstated by | |
11391 | a .align pseudo instruction. | |
11392 | o Note also that after auto alignment is turned off the mips assembler | |
11393 | issues an error on attempt to assemble an improperly aligned data item. | |
11394 | We don't. | |
11395 | ||
11396 | */ | |
11397 | ||
11398 | temp = get_absolute_expression (); | |
11399 | if (temp > max_alignment) | |
11400 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11401 | else if (temp < 0) | |
11402 | { | |
11403 | as_warn (_("Alignment negative: 0 assumed.")); | |
11404 | temp = 0; | |
11405 | } | |
11406 | if (*input_line_pointer == ',') | |
11407 | { | |
f9419b05 | 11408 | ++input_line_pointer; |
252b5132 RH |
11409 | temp_fill = get_absolute_expression (); |
11410 | } | |
11411 | else | |
11412 | temp_fill = 0; | |
11413 | if (temp) | |
11414 | { | |
11415 | auto_align = 1; | |
11416 | mips_align (temp, (int) temp_fill, | |
11417 | insn_labels != NULL ? insn_labels->label : NULL); | |
11418 | } | |
11419 | else | |
11420 | { | |
11421 | auto_align = 0; | |
11422 | } | |
11423 | ||
11424 | demand_empty_rest_of_line (); | |
11425 | } | |
11426 | ||
252b5132 | 11427 | static void |
17a2f251 | 11428 | s_change_sec (int sec) |
252b5132 RH |
11429 | { |
11430 | segT seg; | |
11431 | ||
252b5132 RH |
11432 | #ifdef OBJ_ELF |
11433 | /* The ELF backend needs to know that we are changing sections, so | |
11434 | that .previous works correctly. We could do something like check | |
b6ff326e | 11435 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11436 | as it would not be appropriate to use it in the section changing |
11437 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11438 | This should be cleaner, somehow. */ | |
11439 | obj_elf_section_change_hook (); | |
11440 | #endif | |
11441 | ||
7d10b47d | 11442 | mips_emit_delays (); |
252b5132 RH |
11443 | switch (sec) |
11444 | { | |
11445 | case 't': | |
11446 | s_text (0); | |
11447 | break; | |
11448 | case 'd': | |
11449 | s_data (0); | |
11450 | break; | |
11451 | case 'b': | |
11452 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11453 | demand_empty_rest_of_line (); | |
11454 | break; | |
11455 | ||
11456 | case 'r': | |
4d0d148d TS |
11457 | seg = subseg_new (RDATA_SECTION_NAME, |
11458 | (subsegT) get_absolute_expression ()); | |
11459 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11460 | { |
4d0d148d TS |
11461 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11462 | | SEC_READONLY | SEC_RELOC | |
11463 | | SEC_DATA)); | |
11464 | if (strcmp (TARGET_OS, "elf") != 0) | |
11465 | record_alignment (seg, 4); | |
252b5132 | 11466 | } |
4d0d148d | 11467 | demand_empty_rest_of_line (); |
252b5132 RH |
11468 | break; |
11469 | ||
11470 | case 's': | |
4d0d148d TS |
11471 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11472 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11473 | { |
4d0d148d TS |
11474 | bfd_set_section_flags (stdoutput, seg, |
11475 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11476 | if (strcmp (TARGET_OS, "elf") != 0) | |
11477 | record_alignment (seg, 4); | |
252b5132 | 11478 | } |
4d0d148d TS |
11479 | demand_empty_rest_of_line (); |
11480 | break; | |
252b5132 RH |
11481 | } |
11482 | ||
11483 | auto_align = 1; | |
11484 | } | |
b34976b6 | 11485 | |
cca86cc8 | 11486 | void |
17a2f251 | 11487 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11488 | { |
7ed4a06a | 11489 | #ifdef OBJ_ELF |
cca86cc8 SC |
11490 | char *section_name; |
11491 | char c; | |
684022ea | 11492 | char next_c = 0; |
cca86cc8 SC |
11493 | int section_type; |
11494 | int section_flag; | |
11495 | int section_entry_size; | |
11496 | int section_alignment; | |
b34976b6 | 11497 | |
7ed4a06a TS |
11498 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11499 | return; | |
11500 | ||
cca86cc8 SC |
11501 | section_name = input_line_pointer; |
11502 | c = get_symbol_end (); | |
a816d1ed AO |
11503 | if (c) |
11504 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11505 | |
4cf0dd0d TS |
11506 | /* Do we have .section Name<,"flags">? */ |
11507 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11508 | { |
4cf0dd0d TS |
11509 | /* just after name is now '\0'. */ |
11510 | *input_line_pointer = c; | |
cca86cc8 SC |
11511 | input_line_pointer = section_name; |
11512 | obj_elf_section (ignore); | |
11513 | return; | |
11514 | } | |
11515 | input_line_pointer++; | |
11516 | ||
11517 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11518 | if (c == ',') | |
11519 | section_type = get_absolute_expression (); | |
11520 | else | |
11521 | section_type = 0; | |
11522 | if (*input_line_pointer++ == ',') | |
11523 | section_flag = get_absolute_expression (); | |
11524 | else | |
11525 | section_flag = 0; | |
11526 | if (*input_line_pointer++ == ',') | |
11527 | section_entry_size = get_absolute_expression (); | |
11528 | else | |
11529 | section_entry_size = 0; | |
11530 | if (*input_line_pointer++ == ',') | |
11531 | section_alignment = get_absolute_expression (); | |
11532 | else | |
11533 | section_alignment = 0; | |
11534 | ||
a816d1ed AO |
11535 | section_name = xstrdup (section_name); |
11536 | ||
8ab8a5c8 RS |
11537 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11538 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11539 | traditionally had to fall back on the more common @progbits instead. | |
11540 | ||
11541 | There's nothing really harmful in this, since bfd will correct | |
11542 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11543 | means that, for backwards compatibiltiy, the special_section entries | |
11544 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11545 | ||
11546 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11547 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11548 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11549 | generic type-checking code. */ | |
11550 | if (section_type == SHT_MIPS_DWARF) | |
11551 | section_type = SHT_PROGBITS; | |
11552 | ||
cca86cc8 SC |
11553 | obj_elf_change_section (section_name, section_type, section_flag, |
11554 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11555 | |
11556 | if (now_seg->name != section_name) | |
11557 | free (section_name); | |
7ed4a06a | 11558 | #endif /* OBJ_ELF */ |
cca86cc8 | 11559 | } |
252b5132 RH |
11560 | |
11561 | void | |
17a2f251 | 11562 | mips_enable_auto_align (void) |
252b5132 RH |
11563 | { |
11564 | auto_align = 1; | |
11565 | } | |
11566 | ||
11567 | static void | |
17a2f251 | 11568 | s_cons (int log_size) |
252b5132 RH |
11569 | { |
11570 | symbolS *label; | |
11571 | ||
11572 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11573 | mips_emit_delays (); |
252b5132 RH |
11574 | if (log_size > 0 && auto_align) |
11575 | mips_align (log_size, 0, label); | |
11576 | mips_clear_insn_labels (); | |
11577 | cons (1 << log_size); | |
11578 | } | |
11579 | ||
11580 | static void | |
17a2f251 | 11581 | s_float_cons (int type) |
252b5132 RH |
11582 | { |
11583 | symbolS *label; | |
11584 | ||
11585 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11586 | ||
7d10b47d | 11587 | mips_emit_delays (); |
252b5132 RH |
11588 | |
11589 | if (auto_align) | |
49309057 ILT |
11590 | { |
11591 | if (type == 'd') | |
11592 | mips_align (3, 0, label); | |
11593 | else | |
11594 | mips_align (2, 0, label); | |
11595 | } | |
252b5132 RH |
11596 | |
11597 | mips_clear_insn_labels (); | |
11598 | ||
11599 | float_cons (type); | |
11600 | } | |
11601 | ||
11602 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11603 | permitted to say | |
11604 | .globl foo .text | |
11605 | where foo is an undefined symbol, to mean that foo should be | |
11606 | considered to be the address of a function. */ | |
11607 | ||
11608 | static void | |
17a2f251 | 11609 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11610 | { |
11611 | char *name; | |
11612 | int c; | |
11613 | symbolS *symbolP; | |
11614 | flagword flag; | |
11615 | ||
8a06b769 | 11616 | do |
252b5132 | 11617 | { |
8a06b769 | 11618 | name = input_line_pointer; |
252b5132 | 11619 | c = get_symbol_end (); |
8a06b769 TS |
11620 | symbolP = symbol_find_or_make (name); |
11621 | S_SET_EXTERNAL (symbolP); | |
11622 | ||
252b5132 | 11623 | *input_line_pointer = c; |
8a06b769 | 11624 | SKIP_WHITESPACE (); |
252b5132 | 11625 | |
8a06b769 TS |
11626 | /* On Irix 5, every global symbol that is not explicitly labelled as |
11627 | being a function is apparently labelled as being an object. */ | |
11628 | flag = BSF_OBJECT; | |
252b5132 | 11629 | |
8a06b769 TS |
11630 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
11631 | && (*input_line_pointer != ',')) | |
11632 | { | |
11633 | char *secname; | |
11634 | asection *sec; | |
11635 | ||
11636 | secname = input_line_pointer; | |
11637 | c = get_symbol_end (); | |
11638 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11639 | if (sec == NULL) | |
11640 | as_bad (_("%s: no such section"), secname); | |
11641 | *input_line_pointer = c; | |
11642 | ||
11643 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11644 | flag = BSF_FUNCTION; | |
11645 | } | |
11646 | ||
11647 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
11648 | ||
11649 | c = *input_line_pointer; | |
11650 | if (c == ',') | |
11651 | { | |
11652 | input_line_pointer++; | |
11653 | SKIP_WHITESPACE (); | |
11654 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
11655 | c = '\n'; | |
11656 | } | |
11657 | } | |
11658 | while (c == ','); | |
252b5132 | 11659 | |
252b5132 RH |
11660 | demand_empty_rest_of_line (); |
11661 | } | |
11662 | ||
11663 | static void | |
17a2f251 | 11664 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11665 | { |
11666 | char *opt; | |
11667 | char c; | |
11668 | ||
11669 | opt = input_line_pointer; | |
11670 | c = get_symbol_end (); | |
11671 | ||
11672 | if (*opt == 'O') | |
11673 | { | |
11674 | /* FIXME: What does this mean? */ | |
11675 | } | |
11676 | else if (strncmp (opt, "pic", 3) == 0) | |
11677 | { | |
11678 | int i; | |
11679 | ||
11680 | i = atoi (opt + 3); | |
11681 | if (i == 0) | |
11682 | mips_pic = NO_PIC; | |
11683 | else if (i == 2) | |
143d77c5 | 11684 | { |
252b5132 | 11685 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11686 | mips_abicalls = TRUE; |
11687 | } | |
252b5132 RH |
11688 | else |
11689 | as_bad (_(".option pic%d not supported"), i); | |
11690 | ||
4d0d148d | 11691 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11692 | { |
11693 | if (g_switch_seen && g_switch_value != 0) | |
11694 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11695 | g_switch_value = 0; | |
11696 | bfd_set_gp_size (stdoutput, 0); | |
11697 | } | |
11698 | } | |
11699 | else | |
11700 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11701 | ||
11702 | *input_line_pointer = c; | |
11703 | demand_empty_rest_of_line (); | |
11704 | } | |
11705 | ||
11706 | /* This structure is used to hold a stack of .set values. */ | |
11707 | ||
e972090a NC |
11708 | struct mips_option_stack |
11709 | { | |
252b5132 RH |
11710 | struct mips_option_stack *next; |
11711 | struct mips_set_options options; | |
11712 | }; | |
11713 | ||
11714 | static struct mips_option_stack *mips_opts_stack; | |
11715 | ||
11716 | /* Handle the .set pseudo-op. */ | |
11717 | ||
11718 | static void | |
17a2f251 | 11719 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11720 | { |
11721 | char *name = input_line_pointer, ch; | |
11722 | ||
11723 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11724 | ++input_line_pointer; |
252b5132 RH |
11725 | ch = *input_line_pointer; |
11726 | *input_line_pointer = '\0'; | |
11727 | ||
11728 | if (strcmp (name, "reorder") == 0) | |
11729 | { | |
7d10b47d RS |
11730 | if (mips_opts.noreorder) |
11731 | end_noreorder (); | |
252b5132 RH |
11732 | } |
11733 | else if (strcmp (name, "noreorder") == 0) | |
11734 | { | |
7d10b47d RS |
11735 | if (!mips_opts.noreorder) |
11736 | start_noreorder (); | |
252b5132 RH |
11737 | } |
11738 | else if (strcmp (name, "at") == 0) | |
11739 | { | |
11740 | mips_opts.noat = 0; | |
11741 | } | |
11742 | else if (strcmp (name, "noat") == 0) | |
11743 | { | |
11744 | mips_opts.noat = 1; | |
11745 | } | |
11746 | else if (strcmp (name, "macro") == 0) | |
11747 | { | |
11748 | mips_opts.warn_about_macros = 0; | |
11749 | } | |
11750 | else if (strcmp (name, "nomacro") == 0) | |
11751 | { | |
11752 | if (mips_opts.noreorder == 0) | |
11753 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11754 | mips_opts.warn_about_macros = 1; | |
11755 | } | |
11756 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11757 | { | |
11758 | mips_opts.nomove = 0; | |
11759 | } | |
11760 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11761 | { | |
11762 | mips_opts.nomove = 1; | |
11763 | } | |
11764 | else if (strcmp (name, "bopt") == 0) | |
11765 | { | |
11766 | mips_opts.nobopt = 0; | |
11767 | } | |
11768 | else if (strcmp (name, "nobopt") == 0) | |
11769 | { | |
11770 | mips_opts.nobopt = 1; | |
11771 | } | |
11772 | else if (strcmp (name, "mips16") == 0 | |
11773 | || strcmp (name, "MIPS-16") == 0) | |
11774 | mips_opts.mips16 = 1; | |
11775 | else if (strcmp (name, "nomips16") == 0 | |
11776 | || strcmp (name, "noMIPS-16") == 0) | |
11777 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11778 | else if (strcmp (name, "mips3d") == 0) |
11779 | mips_opts.ase_mips3d = 1; | |
11780 | else if (strcmp (name, "nomips3d") == 0) | |
11781 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11782 | else if (strcmp (name, "mdmx") == 0) |
11783 | mips_opts.ase_mdmx = 1; | |
11784 | else if (strcmp (name, "nomdmx") == 0) | |
11785 | mips_opts.ase_mdmx = 0; | |
74cd071d CF |
11786 | else if (strcmp (name, "dsp") == 0) |
11787 | mips_opts.ase_dsp = 1; | |
11788 | else if (strcmp (name, "nodsp") == 0) | |
11789 | mips_opts.ase_dsp = 0; | |
1a2c1fad | 11790 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11791 | { |
af7ee8bf | 11792 | int reset = 0; |
252b5132 | 11793 | |
1a2c1fad CD |
11794 | /* Permit the user to change the ISA and architecture on the fly. |
11795 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11796 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11797 | { |
11798 | reset = 1; | |
11799 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11800 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11801 | } |
11802 | else if (strncmp (name, "arch=", 5) == 0) | |
11803 | { | |
11804 | const struct mips_cpu_info *p; | |
11805 | ||
11806 | p = mips_parse_cpu("internal use", name + 5); | |
11807 | if (!p) | |
11808 | as_bad (_("unknown architecture %s"), name + 5); | |
11809 | else | |
11810 | { | |
11811 | mips_opts.arch = p->cpu; | |
11812 | mips_opts.isa = p->isa; | |
11813 | } | |
11814 | } | |
81a21e38 TS |
11815 | else if (strncmp (name, "mips", 4) == 0) |
11816 | { | |
11817 | const struct mips_cpu_info *p; | |
11818 | ||
11819 | p = mips_parse_cpu("internal use", name); | |
11820 | if (!p) | |
11821 | as_bad (_("unknown ISA level %s"), name + 4); | |
11822 | else | |
11823 | { | |
11824 | mips_opts.arch = p->cpu; | |
11825 | mips_opts.isa = p->isa; | |
11826 | } | |
11827 | } | |
af7ee8bf | 11828 | else |
81a21e38 | 11829 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11830 | |
11831 | switch (mips_opts.isa) | |
98d3f06f KH |
11832 | { |
11833 | case 0: | |
98d3f06f | 11834 | break; |
af7ee8bf CD |
11835 | case ISA_MIPS1: |
11836 | case ISA_MIPS2: | |
11837 | case ISA_MIPS32: | |
11838 | case ISA_MIPS32R2: | |
98d3f06f KH |
11839 | mips_opts.gp32 = 1; |
11840 | mips_opts.fp32 = 1; | |
11841 | break; | |
af7ee8bf CD |
11842 | case ISA_MIPS3: |
11843 | case ISA_MIPS4: | |
11844 | case ISA_MIPS5: | |
11845 | case ISA_MIPS64: | |
5f74bc13 | 11846 | case ISA_MIPS64R2: |
98d3f06f KH |
11847 | mips_opts.gp32 = 0; |
11848 | mips_opts.fp32 = 0; | |
11849 | break; | |
11850 | default: | |
11851 | as_bad (_("unknown ISA level %s"), name + 4); | |
11852 | break; | |
11853 | } | |
af7ee8bf | 11854 | if (reset) |
98d3f06f | 11855 | { |
af7ee8bf CD |
11856 | mips_opts.gp32 = file_mips_gp32; |
11857 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11858 | } |
252b5132 RH |
11859 | } |
11860 | else if (strcmp (name, "autoextend") == 0) | |
11861 | mips_opts.noautoextend = 0; | |
11862 | else if (strcmp (name, "noautoextend") == 0) | |
11863 | mips_opts.noautoextend = 1; | |
11864 | else if (strcmp (name, "push") == 0) | |
11865 | { | |
11866 | struct mips_option_stack *s; | |
11867 | ||
11868 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11869 | s->next = mips_opts_stack; | |
11870 | s->options = mips_opts; | |
11871 | mips_opts_stack = s; | |
11872 | } | |
11873 | else if (strcmp (name, "pop") == 0) | |
11874 | { | |
11875 | struct mips_option_stack *s; | |
11876 | ||
11877 | s = mips_opts_stack; | |
11878 | if (s == NULL) | |
11879 | as_bad (_(".set pop with no .set push")); | |
11880 | else | |
11881 | { | |
11882 | /* If we're changing the reorder mode we need to handle | |
11883 | delay slots correctly. */ | |
11884 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 11885 | start_noreorder (); |
252b5132 | 11886 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 11887 | end_noreorder (); |
252b5132 RH |
11888 | |
11889 | mips_opts = s->options; | |
11890 | mips_opts_stack = s->next; | |
11891 | free (s); | |
11892 | } | |
11893 | } | |
aed1a261 RS |
11894 | else if (strcmp (name, "sym32") == 0) |
11895 | mips_opts.sym32 = TRUE; | |
11896 | else if (strcmp (name, "nosym32") == 0) | |
11897 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11898 | else |
11899 | { | |
11900 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11901 | } | |
11902 | *input_line_pointer = ch; | |
11903 | demand_empty_rest_of_line (); | |
11904 | } | |
11905 | ||
11906 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11907 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11908 | ||
11909 | static void | |
17a2f251 | 11910 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11911 | { |
11912 | mips_pic = SVR4_PIC; | |
143d77c5 | 11913 | mips_abicalls = TRUE; |
4d0d148d TS |
11914 | |
11915 | if (g_switch_seen && g_switch_value != 0) | |
11916 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11917 | g_switch_value = 0; | |
11918 | ||
252b5132 RH |
11919 | bfd_set_gp_size (stdoutput, 0); |
11920 | demand_empty_rest_of_line (); | |
11921 | } | |
11922 | ||
11923 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11924 | PIC code. It sets the $gp register for the function based on the | |
11925 | function address, which is in the register named in the argument. | |
11926 | This uses a relocation against _gp_disp, which is handled specially | |
11927 | by the linker. The result is: | |
11928 | lui $gp,%hi(_gp_disp) | |
11929 | addiu $gp,$gp,%lo(_gp_disp) | |
11930 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11931 | The .cpload argument is normally $25 == $t9. |
11932 | ||
11933 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11934 | lui $gp,%hi(__gnu_local_gp) |
11935 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11936 | and the argument is ignored. This saves an instruction, but the |
11937 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11938 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11939 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11940 | |
11941 | static void | |
17a2f251 | 11942 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11943 | { |
11944 | expressionS ex; | |
aa6975fb ILT |
11945 | int reg; |
11946 | int in_shared; | |
252b5132 | 11947 | |
6478892d TS |
11948 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11949 | .cpload is ignored. */ | |
11950 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11951 | { |
11952 | s_ignore (0); | |
11953 | return; | |
11954 | } | |
11955 | ||
d3ecfc59 | 11956 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11957 | if (mips_opts.noreorder == 0) |
11958 | as_warn (_(".cpload not in noreorder section")); | |
11959 | ||
aa6975fb ILT |
11960 | reg = tc_get_register (0); |
11961 | ||
11962 | /* If we need to produce a 64-bit address, we are better off using | |
11963 | the default instruction sequence. */ | |
aed1a261 | 11964 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11965 | |
252b5132 | 11966 | ex.X_op = O_symbol; |
bbe506e8 TS |
11967 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11968 | "__gnu_local_gp"); | |
252b5132 RH |
11969 | ex.X_op_symbol = NULL; |
11970 | ex.X_add_number = 0; | |
11971 | ||
11972 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11973 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11974 | |
584892a6 | 11975 | macro_start (); |
67c0d1eb RS |
11976 | macro_build_lui (&ex, mips_gp_register); |
11977 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11978 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11979 | if (in_shared) |
11980 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11981 | mips_gp_register, reg); | |
584892a6 | 11982 | macro_end (); |
252b5132 RH |
11983 | |
11984 | demand_empty_rest_of_line (); | |
11985 | } | |
11986 | ||
6478892d TS |
11987 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11988 | .cpsetup $reg1, offset|$reg2, label | |
11989 | ||
11990 | If offset is given, this results in: | |
11991 | sd $gp, offset($sp) | |
956cd1d6 | 11992 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11993 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11994 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11995 | |
11996 | If $reg2 is given, this results in: | |
11997 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11998 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11999 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12000 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12001 | $reg1 is normally $25 == $t9. |
12002 | ||
12003 | The -mno-shared option replaces the last three instructions with | |
12004 | lui $gp,%hi(_gp) | |
12005 | addiu $gp,$gp,%lo(_gp) | |
12006 | */ | |
12007 | ||
6478892d | 12008 | static void |
17a2f251 | 12009 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12010 | { |
12011 | expressionS ex_off; | |
12012 | expressionS ex_sym; | |
12013 | int reg1; | |
6478892d | 12014 | |
8586fc66 | 12015 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12016 | We also need NewABI support. */ |
12017 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12018 | { | |
12019 | s_ignore (0); | |
12020 | return; | |
12021 | } | |
12022 | ||
12023 | reg1 = tc_get_register (0); | |
12024 | SKIP_WHITESPACE (); | |
12025 | if (*input_line_pointer != ',') | |
12026 | { | |
12027 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12028 | return; | |
12029 | } | |
12030 | else | |
80245285 | 12031 | ++input_line_pointer; |
6478892d TS |
12032 | SKIP_WHITESPACE (); |
12033 | if (*input_line_pointer == '$') | |
80245285 TS |
12034 | { |
12035 | mips_cpreturn_register = tc_get_register (0); | |
12036 | mips_cpreturn_offset = -1; | |
12037 | } | |
6478892d | 12038 | else |
80245285 TS |
12039 | { |
12040 | mips_cpreturn_offset = get_absolute_expression (); | |
12041 | mips_cpreturn_register = -1; | |
12042 | } | |
6478892d TS |
12043 | SKIP_WHITESPACE (); |
12044 | if (*input_line_pointer != ',') | |
12045 | { | |
12046 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12047 | return; | |
12048 | } | |
12049 | else | |
f9419b05 | 12050 | ++input_line_pointer; |
6478892d | 12051 | SKIP_WHITESPACE (); |
f21f8242 | 12052 | expression (&ex_sym); |
6478892d | 12053 | |
584892a6 | 12054 | macro_start (); |
6478892d TS |
12055 | if (mips_cpreturn_register == -1) |
12056 | { | |
12057 | ex_off.X_op = O_constant; | |
12058 | ex_off.X_add_symbol = NULL; | |
12059 | ex_off.X_op_symbol = NULL; | |
12060 | ex_off.X_add_number = mips_cpreturn_offset; | |
12061 | ||
67c0d1eb | 12062 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12063 | BFD_RELOC_LO16, SP); |
6478892d TS |
12064 | } |
12065 | else | |
67c0d1eb | 12066 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12067 | mips_gp_register, 0); |
6478892d | 12068 | |
aed1a261 | 12069 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12070 | { |
12071 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12072 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12073 | BFD_RELOC_HI16_S); | |
12074 | ||
12075 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12076 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12077 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12078 | ||
12079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12080 | mips_gp_register, reg1); | |
12081 | } | |
12082 | else | |
12083 | { | |
12084 | expressionS ex; | |
12085 | ||
12086 | ex.X_op = O_symbol; | |
4184909a | 12087 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12088 | ex.X_op_symbol = NULL; |
12089 | ex.X_add_number = 0; | |
6e1304d8 | 12090 | |
aa6975fb ILT |
12091 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12092 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12093 | ||
12094 | macro_build_lui (&ex, mips_gp_register); | |
12095 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12096 | mips_gp_register, BFD_RELOC_LO16); | |
12097 | } | |
f21f8242 | 12098 | |
584892a6 | 12099 | macro_end (); |
6478892d TS |
12100 | |
12101 | demand_empty_rest_of_line (); | |
12102 | } | |
12103 | ||
12104 | static void | |
17a2f251 | 12105 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12106 | { |
12107 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12108 | .cplocal is ignored. */ | |
12109 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12110 | { | |
12111 | s_ignore (0); | |
12112 | return; | |
12113 | } | |
12114 | ||
12115 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12116 | demand_empty_rest_of_line (); |
6478892d TS |
12117 | } |
12118 | ||
252b5132 RH |
12119 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12120 | offset from $sp. The offset is remembered, and after making a PIC | |
12121 | call $gp is restored from that location. */ | |
12122 | ||
12123 | static void | |
17a2f251 | 12124 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12125 | { |
12126 | expressionS ex; | |
252b5132 | 12127 | |
6478892d | 12128 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12129 | .cprestore is ignored. */ |
6478892d | 12130 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12131 | { |
12132 | s_ignore (0); | |
12133 | return; | |
12134 | } | |
12135 | ||
12136 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12137 | mips_cprestore_valid = 1; |
252b5132 RH |
12138 | |
12139 | ex.X_op = O_constant; | |
12140 | ex.X_add_symbol = NULL; | |
12141 | ex.X_op_symbol = NULL; | |
12142 | ex.X_add_number = mips_cprestore_offset; | |
12143 | ||
584892a6 | 12144 | macro_start (); |
67c0d1eb RS |
12145 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12146 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12147 | macro_end (); |
252b5132 RH |
12148 | |
12149 | demand_empty_rest_of_line (); | |
12150 | } | |
12151 | ||
6478892d | 12152 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12153 | was given in the preceding .cpsetup, it results in: |
6478892d | 12154 | ld $gp, offset($sp) |
76b3015f | 12155 | |
6478892d | 12156 | If a register $reg2 was given there, it results in: |
609f23f4 | 12157 | daddu $gp, $reg2, $0 |
6478892d TS |
12158 | */ |
12159 | static void | |
17a2f251 | 12160 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12161 | { |
12162 | expressionS ex; | |
6478892d TS |
12163 | |
12164 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12165 | We also need NewABI support. */ | |
12166 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12167 | { | |
12168 | s_ignore (0); | |
12169 | return; | |
12170 | } | |
12171 | ||
584892a6 | 12172 | macro_start (); |
6478892d TS |
12173 | if (mips_cpreturn_register == -1) |
12174 | { | |
12175 | ex.X_op = O_constant; | |
12176 | ex.X_add_symbol = NULL; | |
12177 | ex.X_op_symbol = NULL; | |
12178 | ex.X_add_number = mips_cpreturn_offset; | |
12179 | ||
67c0d1eb | 12180 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12181 | } |
12182 | else | |
67c0d1eb | 12183 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12184 | mips_cpreturn_register, 0); |
584892a6 | 12185 | macro_end (); |
6478892d TS |
12186 | |
12187 | demand_empty_rest_of_line (); | |
12188 | } | |
12189 | ||
12190 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12191 | code. It sets the offset to use in gp_rel relocations. */ | |
12192 | ||
12193 | static void | |
17a2f251 | 12194 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12195 | { |
12196 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12197 | We also need NewABI support. */ | |
12198 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12199 | { | |
12200 | s_ignore (0); | |
12201 | return; | |
12202 | } | |
12203 | ||
def2e0dd | 12204 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12205 | |
12206 | demand_empty_rest_of_line (); | |
12207 | } | |
12208 | ||
252b5132 RH |
12209 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12210 | code. It generates a 32 bit GP relative reloc. */ | |
12211 | ||
12212 | static void | |
17a2f251 | 12213 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12214 | { |
12215 | symbolS *label; | |
12216 | expressionS ex; | |
12217 | char *p; | |
12218 | ||
12219 | /* When not generating PIC code, this is treated as .word. */ | |
12220 | if (mips_pic != SVR4_PIC) | |
12221 | { | |
12222 | s_cons (2); | |
12223 | return; | |
12224 | } | |
12225 | ||
12226 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12227 | mips_emit_delays (); |
252b5132 RH |
12228 | if (auto_align) |
12229 | mips_align (2, 0, label); | |
12230 | mips_clear_insn_labels (); | |
12231 | ||
12232 | expression (&ex); | |
12233 | ||
12234 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12235 | { | |
12236 | as_bad (_("Unsupported use of .gpword")); | |
12237 | ignore_rest_of_line (); | |
12238 | } | |
12239 | ||
12240 | p = frag_more (4); | |
17a2f251 | 12241 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12242 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12243 | BFD_RELOC_GPREL32); |
252b5132 RH |
12244 | |
12245 | demand_empty_rest_of_line (); | |
12246 | } | |
12247 | ||
10181a0d | 12248 | static void |
17a2f251 | 12249 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12250 | { |
12251 | symbolS *label; | |
12252 | expressionS ex; | |
12253 | char *p; | |
12254 | ||
12255 | /* When not generating PIC code, this is treated as .dword. */ | |
12256 | if (mips_pic != SVR4_PIC) | |
12257 | { | |
12258 | s_cons (3); | |
12259 | return; | |
12260 | } | |
12261 | ||
12262 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12263 | mips_emit_delays (); |
10181a0d AO |
12264 | if (auto_align) |
12265 | mips_align (3, 0, label); | |
12266 | mips_clear_insn_labels (); | |
12267 | ||
12268 | expression (&ex); | |
12269 | ||
12270 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12271 | { | |
12272 | as_bad (_("Unsupported use of .gpdword")); | |
12273 | ignore_rest_of_line (); | |
12274 | } | |
12275 | ||
12276 | p = frag_more (8); | |
17a2f251 | 12277 | md_number_to_chars (p, 0, 8); |
a105a300 | 12278 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12279 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12280 | |
12281 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12282 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12283 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12284 | |
12285 | demand_empty_rest_of_line (); | |
12286 | } | |
12287 | ||
252b5132 RH |
12288 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12289 | tables in SVR4 PIC code. */ | |
12290 | ||
12291 | static void | |
17a2f251 | 12292 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12293 | { |
252b5132 RH |
12294 | int reg; |
12295 | ||
10181a0d AO |
12296 | /* This is ignored when not generating SVR4 PIC code. */ |
12297 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12298 | { |
12299 | s_ignore (0); | |
12300 | return; | |
12301 | } | |
12302 | ||
12303 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12304 | macro_start (); |
252b5132 | 12305 | reg = tc_get_register (0); |
67c0d1eb | 12306 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12307 | macro_end (); |
252b5132 | 12308 | |
bdaaa2e1 | 12309 | demand_empty_rest_of_line (); |
252b5132 RH |
12310 | } |
12311 | ||
12312 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12313 | mips16 mode. This permits the linker to handle them specially, | |
12314 | such as generating jalx instructions when needed. We also make | |
12315 | them odd for the duration of the assembly, in order to generate the | |
12316 | right sort of code. We will make them even in the adjust_symtab | |
12317 | routine, while leaving them marked. This is convenient for the | |
12318 | debugger and the disassembler. The linker knows to make them odd | |
12319 | again. */ | |
12320 | ||
12321 | static void | |
17a2f251 | 12322 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12323 | { |
f9419b05 | 12324 | mips16_mark_labels (); |
252b5132 RH |
12325 | |
12326 | demand_empty_rest_of_line (); | |
12327 | } | |
12328 | ||
12329 | /* Handle a .stabn directive. We need these in order to mark a label | |
12330 | as being a mips16 text label correctly. Sometimes the compiler | |
12331 | will emit a label, followed by a .stabn, and then switch sections. | |
12332 | If the label and .stabn are in mips16 mode, then the label is | |
12333 | really a mips16 text label. */ | |
12334 | ||
12335 | static void | |
17a2f251 | 12336 | s_mips_stab (int type) |
252b5132 | 12337 | { |
f9419b05 | 12338 | if (type == 'n') |
252b5132 RH |
12339 | mips16_mark_labels (); |
12340 | ||
12341 | s_stab (type); | |
12342 | } | |
12343 | ||
12344 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12345 | */ | |
12346 | ||
12347 | static void | |
17a2f251 | 12348 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12349 | { |
12350 | char *name; | |
12351 | int c; | |
12352 | symbolS *symbolP; | |
12353 | expressionS exp; | |
12354 | ||
12355 | name = input_line_pointer; | |
12356 | c = get_symbol_end (); | |
12357 | symbolP = symbol_find_or_make (name); | |
12358 | S_SET_WEAK (symbolP); | |
12359 | *input_line_pointer = c; | |
12360 | ||
12361 | SKIP_WHITESPACE (); | |
12362 | ||
12363 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12364 | { | |
12365 | if (S_IS_DEFINED (symbolP)) | |
12366 | { | |
956cd1d6 | 12367 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12368 | S_GET_NAME (symbolP)); |
12369 | ignore_rest_of_line (); | |
12370 | return; | |
12371 | } | |
bdaaa2e1 | 12372 | |
252b5132 RH |
12373 | if (*input_line_pointer == ',') |
12374 | { | |
12375 | ++input_line_pointer; | |
12376 | SKIP_WHITESPACE (); | |
12377 | } | |
bdaaa2e1 | 12378 | |
252b5132 RH |
12379 | expression (&exp); |
12380 | if (exp.X_op != O_symbol) | |
12381 | { | |
12382 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12383 | ignore_rest_of_line (); |
252b5132 RH |
12384 | return; |
12385 | } | |
49309057 | 12386 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12387 | } |
12388 | ||
12389 | demand_empty_rest_of_line (); | |
12390 | } | |
12391 | ||
12392 | /* Parse a register string into a number. Called from the ECOFF code | |
12393 | to parse .frame. The argument is non-zero if this is the frame | |
12394 | register, so that we can record it in mips_frame_reg. */ | |
12395 | ||
12396 | int | |
17a2f251 | 12397 | tc_get_register (int frame) |
252b5132 RH |
12398 | { |
12399 | int reg; | |
12400 | ||
12401 | SKIP_WHITESPACE (); | |
12402 | if (*input_line_pointer++ != '$') | |
12403 | { | |
12404 | as_warn (_("expected `$'")); | |
85b51719 | 12405 | reg = ZERO; |
252b5132 | 12406 | } |
3882b010 | 12407 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12408 | { |
12409 | reg = get_absolute_expression (); | |
12410 | if (reg < 0 || reg >= 32) | |
12411 | { | |
12412 | as_warn (_("Bad register number")); | |
85b51719 | 12413 | reg = ZERO; |
252b5132 RH |
12414 | } |
12415 | } | |
12416 | else | |
12417 | { | |
76db943d | 12418 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12419 | { |
12420 | reg = RA; | |
12421 | input_line_pointer += 2; | |
12422 | } | |
76db943d | 12423 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12424 | { |
12425 | reg = FP; | |
12426 | input_line_pointer += 2; | |
12427 | } | |
252b5132 | 12428 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12429 | { |
12430 | reg = SP; | |
12431 | input_line_pointer += 2; | |
12432 | } | |
252b5132 | 12433 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12434 | { |
12435 | reg = GP; | |
12436 | input_line_pointer += 2; | |
12437 | } | |
252b5132 | 12438 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12439 | { |
12440 | reg = AT; | |
12441 | input_line_pointer += 2; | |
12442 | } | |
12443 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12444 | { | |
12445 | reg = KT0; | |
12446 | input_line_pointer += 3; | |
12447 | } | |
12448 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12449 | { | |
12450 | reg = KT1; | |
12451 | input_line_pointer += 3; | |
12452 | } | |
12453 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12454 | { | |
12455 | reg = ZERO; | |
12456 | input_line_pointer += 4; | |
12457 | } | |
252b5132 RH |
12458 | else |
12459 | { | |
12460 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12461 | reg = ZERO; |
12462 | while (ISALNUM(*input_line_pointer)) | |
12463 | input_line_pointer++; | |
252b5132 | 12464 | } |
252b5132 RH |
12465 | } |
12466 | if (frame) | |
7a621144 DJ |
12467 | { |
12468 | mips_frame_reg = reg != 0 ? reg : SP; | |
12469 | mips_frame_reg_valid = 1; | |
12470 | mips_cprestore_valid = 0; | |
12471 | } | |
252b5132 RH |
12472 | return reg; |
12473 | } | |
12474 | ||
12475 | valueT | |
17a2f251 | 12476 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12477 | { |
12478 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12479 | ||
12480 | #ifdef OBJ_ELF | |
12481 | /* We don't need to align ELF sections to the full alignment. | |
12482 | However, Irix 5 may prefer that we align them at least to a 16 | |
12483 | byte boundary. We don't bother to align the sections if we are | |
12484 | targeted for an embedded system. */ | |
12485 | if (strcmp (TARGET_OS, "elf") == 0) | |
12486 | return addr; | |
12487 | if (align > 4) | |
12488 | align = 4; | |
12489 | #endif | |
12490 | ||
12491 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12492 | } | |
12493 | ||
12494 | /* Utility routine, called from above as well. If called while the | |
12495 | input file is still being read, it's only an approximation. (For | |
12496 | example, a symbol may later become defined which appeared to be | |
12497 | undefined earlier.) */ | |
12498 | ||
12499 | static int | |
17a2f251 | 12500 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12501 | { |
12502 | if (sym == 0) | |
12503 | return 0; | |
12504 | ||
4d0d148d | 12505 | if (g_switch_value > 0) |
252b5132 RH |
12506 | { |
12507 | const char *symname; | |
12508 | int change; | |
12509 | ||
c9914766 | 12510 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12511 | register. It can be if it is smaller than the -G size or if |
12512 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12513 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12514 | they can. */ |
12515 | symname = S_GET_NAME (sym); | |
12516 | if (symname != (const char *) NULL | |
12517 | && (strcmp (symname, "eprol") == 0 | |
12518 | || strcmp (symname, "etext") == 0 | |
12519 | || strcmp (symname, "_gp") == 0 | |
12520 | || strcmp (symname, "edata") == 0 | |
12521 | || strcmp (symname, "_fbss") == 0 | |
12522 | || strcmp (symname, "_fdata") == 0 | |
12523 | || strcmp (symname, "_ftext") == 0 | |
12524 | || strcmp (symname, "end") == 0 | |
12525 | || strcmp (symname, "_gp_disp") == 0)) | |
12526 | change = 1; | |
12527 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12528 | && (0 | |
12529 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12530 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12531 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12532 | <= g_switch_value)) | |
252b5132 RH |
12533 | #endif |
12534 | /* We must defer this decision until after the whole | |
12535 | file has been read, since there might be a .extern | |
12536 | after the first use of this symbol. */ | |
12537 | || (before_relaxing | |
12538 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12539 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12540 | #endif |
12541 | && S_GET_VALUE (sym) == 0) | |
12542 | || (S_GET_VALUE (sym) != 0 | |
12543 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12544 | change = 0; | |
12545 | else | |
12546 | { | |
12547 | const char *segname; | |
12548 | ||
12549 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12550 | assert (strcmp (segname, ".lit8") != 0 | |
12551 | && strcmp (segname, ".lit4") != 0); | |
12552 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12553 | && strcmp (segname, ".sbss") != 0 |
12554 | && strncmp (segname, ".sdata.", 7) != 0 | |
12555 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12556 | } |
12557 | return change; | |
12558 | } | |
12559 | else | |
c9914766 | 12560 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12561 | return 1; |
12562 | } | |
12563 | ||
5919d012 RS |
12564 | |
12565 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12566 | ||
12567 | static bfd_boolean | |
17a2f251 | 12568 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12569 | { |
12570 | asection *symsec; | |
12571 | bfd_boolean linkonce; | |
12572 | ||
12573 | /* Handle the case of a symbol equated to another symbol. */ | |
12574 | while (symbol_equated_reloc_p (sym)) | |
12575 | { | |
12576 | symbolS *n; | |
12577 | ||
12578 | /* It's possible to get a loop here in a badly written | |
12579 | program. */ | |
12580 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12581 | if (n == sym) | |
12582 | break; | |
12583 | sym = n; | |
12584 | } | |
12585 | ||
12586 | symsec = S_GET_SEGMENT (sym); | |
12587 | ||
12588 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12589 | linkonce = FALSE; | |
12590 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12591 | { | |
12592 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12593 | != 0) | |
12594 | linkonce = TRUE; | |
12595 | ||
12596 | /* The GNU toolchain uses an extension for ELF: a section | |
12597 | beginning with the magic string .gnu.linkonce is a linkonce | |
12598 | section. */ | |
12599 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12600 | sizeof ".gnu.linkonce" - 1) == 0) | |
12601 | linkonce = TRUE; | |
12602 | } | |
12603 | ||
12604 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12605 | return (symsec != &bfd_und_section | |
12606 | && symsec != &bfd_abs_section | |
12607 | && ! bfd_is_com_section (symsec) | |
12608 | && !linkonce | |
12609 | #ifdef OBJ_ELF | |
12610 | /* A global or weak symbol is treated as external. */ | |
12611 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12612 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12613 | #endif |
12614 | ); | |
12615 | } | |
12616 | ||
12617 | ||
252b5132 RH |
12618 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12619 | extended opcode. SEC is the section the frag is in. */ | |
12620 | ||
12621 | static int | |
17a2f251 | 12622 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12623 | { |
12624 | int type; | |
12625 | register const struct mips16_immed_operand *op; | |
12626 | offsetT val; | |
12627 | int mintiny, maxtiny; | |
12628 | segT symsec; | |
98aa84af | 12629 | fragS *sym_frag; |
252b5132 RH |
12630 | |
12631 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12632 | return 0; | |
12633 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12634 | return 1; | |
12635 | ||
12636 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12637 | op = mips16_immed_operands; | |
12638 | while (op->type != type) | |
12639 | { | |
12640 | ++op; | |
12641 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12642 | } | |
12643 | ||
12644 | if (op->unsp) | |
12645 | { | |
12646 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12647 | { | |
12648 | mintiny = 1; | |
12649 | maxtiny = 1 << op->nbits; | |
12650 | } | |
12651 | else | |
12652 | { | |
12653 | mintiny = 0; | |
12654 | maxtiny = (1 << op->nbits) - 1; | |
12655 | } | |
12656 | } | |
12657 | else | |
12658 | { | |
12659 | mintiny = - (1 << (op->nbits - 1)); | |
12660 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12661 | } | |
12662 | ||
98aa84af | 12663 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12664 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12665 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12666 | |
12667 | if (op->pcrel) | |
12668 | { | |
12669 | addressT addr; | |
12670 | ||
12671 | /* We won't have the section when we are called from | |
12672 | mips_relax_frag. However, we will always have been called | |
12673 | from md_estimate_size_before_relax first. If this is a | |
12674 | branch to a different section, we mark it as such. If SEC is | |
12675 | NULL, and the frag is not marked, then it must be a branch to | |
12676 | the same section. */ | |
12677 | if (sec == NULL) | |
12678 | { | |
12679 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12680 | return 1; | |
12681 | } | |
12682 | else | |
12683 | { | |
98aa84af | 12684 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12685 | if (symsec != sec) |
12686 | { | |
12687 | fragp->fr_subtype = | |
12688 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12689 | ||
12690 | /* FIXME: We should support this, and let the linker | |
12691 | catch branches and loads that are out of range. */ | |
12692 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12693 | _("unsupported PC relative reference to different section")); | |
12694 | ||
12695 | return 1; | |
12696 | } | |
98aa84af AM |
12697 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12698 | /* Assume non-extended on the first relaxation pass. | |
12699 | The address we have calculated will be bogus if this is | |
12700 | a forward branch to another frag, as the forward frag | |
12701 | will have fr_address == 0. */ | |
12702 | return 0; | |
252b5132 RH |
12703 | } |
12704 | ||
12705 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12706 | the same section. If the relax_marker of the symbol fragment |
12707 | differs from the relax_marker of this fragment, we have not | |
12708 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12709 | in STRETCH in order to get a better estimate of the address. |
12710 | This particularly matters because of the shift bits. */ | |
12711 | if (stretch != 0 | |
98aa84af | 12712 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12713 | { |
12714 | fragS *f; | |
12715 | ||
12716 | /* Adjust stretch for any alignment frag. Note that if have | |
12717 | been expanding the earlier code, the symbol may be | |
12718 | defined in what appears to be an earlier frag. FIXME: | |
12719 | This doesn't handle the fr_subtype field, which specifies | |
12720 | a maximum number of bytes to skip when doing an | |
12721 | alignment. */ | |
98aa84af | 12722 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12723 | { |
12724 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12725 | { | |
12726 | if (stretch < 0) | |
12727 | stretch = - ((- stretch) | |
12728 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12729 | else | |
12730 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12731 | if (stretch == 0) | |
12732 | break; | |
12733 | } | |
12734 | } | |
12735 | if (f != NULL) | |
12736 | val += stretch; | |
12737 | } | |
12738 | ||
12739 | addr = fragp->fr_address + fragp->fr_fix; | |
12740 | ||
12741 | /* The base address rules are complicated. The base address of | |
12742 | a branch is the following instruction. The base address of a | |
12743 | PC relative load or add is the instruction itself, but if it | |
12744 | is in a delay slot (in which case it can not be extended) use | |
12745 | the address of the instruction whose delay slot it is in. */ | |
12746 | if (type == 'p' || type == 'q') | |
12747 | { | |
12748 | addr += 2; | |
12749 | ||
12750 | /* If we are currently assuming that this frag should be | |
12751 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12752 | higher. */ |
252b5132 RH |
12753 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12754 | addr += 2; | |
12755 | ||
12756 | /* Ignore the low bit in the target, since it will be set | |
12757 | for a text label. */ | |
12758 | if ((val & 1) != 0) | |
12759 | --val; | |
12760 | } | |
12761 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12762 | addr -= 4; | |
12763 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12764 | addr -= 2; | |
12765 | ||
12766 | val -= addr & ~ ((1 << op->shift) - 1); | |
12767 | ||
12768 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12769 | if (type == 'p' || type == 'q') | |
12770 | val /= 2; | |
12771 | ||
12772 | /* If any of the shifted bits are set, we must use an extended | |
12773 | opcode. If the address depends on the size of this | |
12774 | instruction, this can lead to a loop, so we arrange to always | |
12775 | use an extended opcode. We only check this when we are in | |
12776 | the main relaxation loop, when SEC is NULL. */ | |
12777 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12778 | { | |
12779 | fragp->fr_subtype = | |
12780 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12781 | return 1; | |
12782 | } | |
12783 | ||
12784 | /* If we are about to mark a frag as extended because the value | |
12785 | is precisely maxtiny + 1, then there is a chance of an | |
12786 | infinite loop as in the following code: | |
12787 | la $4,foo | |
12788 | .skip 1020 | |
12789 | .align 2 | |
12790 | foo: | |
12791 | In this case when the la is extended, foo is 0x3fc bytes | |
12792 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12793 | the la must be extended. To avoid this loop, we mark the | |
12794 | frag as extended if it was small, and is about to become | |
12795 | extended with a value of maxtiny + 1. */ | |
12796 | if (val == ((maxtiny + 1) << op->shift) | |
12797 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12798 | && sec == NULL) | |
12799 | { | |
12800 | fragp->fr_subtype = | |
12801 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12802 | return 1; | |
12803 | } | |
12804 | } | |
12805 | else if (symsec != absolute_section && sec != NULL) | |
12806 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12807 | ||
12808 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12809 | || val < (mintiny << op->shift) | |
12810 | || val > (maxtiny << op->shift)) | |
12811 | return 1; | |
12812 | else | |
12813 | return 0; | |
12814 | } | |
12815 | ||
4a6a3df4 AO |
12816 | /* Compute the length of a branch sequence, and adjust the |
12817 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12818 | worst-case length is computed, with UPDATE being used to indicate | |
12819 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12820 | branch is to be computed. */ | |
12821 | static int | |
17a2f251 | 12822 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12823 | { |
b34976b6 | 12824 | bfd_boolean toofar; |
4a6a3df4 AO |
12825 | int length; |
12826 | ||
12827 | if (fragp | |
12828 | && S_IS_DEFINED (fragp->fr_symbol) | |
12829 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12830 | { | |
12831 | addressT addr; | |
12832 | offsetT val; | |
12833 | ||
12834 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12835 | ||
12836 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12837 | ||
12838 | val -= addr; | |
12839 | ||
12840 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12841 | } | |
12842 | else if (fragp) | |
12843 | /* If the symbol is not defined or it's in a different segment, | |
12844 | assume the user knows what's going on and emit a short | |
12845 | branch. */ | |
b34976b6 | 12846 | toofar = FALSE; |
4a6a3df4 | 12847 | else |
b34976b6 | 12848 | toofar = TRUE; |
4a6a3df4 AO |
12849 | |
12850 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12851 | fragp->fr_subtype | |
af6ae2ad | 12852 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12853 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12854 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12855 | toofar); | |
12856 | ||
12857 | length = 4; | |
12858 | if (toofar) | |
12859 | { | |
12860 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12861 | length += 8; | |
12862 | ||
12863 | if (mips_pic != NO_PIC) | |
12864 | { | |
12865 | /* Additional space for PIC loading of target address. */ | |
12866 | length += 8; | |
12867 | if (mips_opts.isa == ISA_MIPS1) | |
12868 | /* Additional space for $at-stabilizing nop. */ | |
12869 | length += 4; | |
12870 | } | |
12871 | ||
12872 | /* If branch is conditional. */ | |
12873 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12874 | length += 8; | |
12875 | } | |
b34976b6 | 12876 | |
4a6a3df4 AO |
12877 | return length; |
12878 | } | |
12879 | ||
252b5132 RH |
12880 | /* Estimate the size of a frag before relaxing. Unless this is the |
12881 | mips16, we are not really relaxing here, and the final size is | |
12882 | encoded in the subtype information. For the mips16, we have to | |
12883 | decide whether we are using an extended opcode or not. */ | |
12884 | ||
252b5132 | 12885 | int |
17a2f251 | 12886 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12887 | { |
5919d012 | 12888 | int change; |
252b5132 | 12889 | |
4a6a3df4 AO |
12890 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12891 | { | |
12892 | ||
b34976b6 AM |
12893 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12894 | ||
4a6a3df4 AO |
12895 | return fragp->fr_var; |
12896 | } | |
12897 | ||
252b5132 | 12898 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12899 | /* We don't want to modify the EXTENDED bit here; it might get us |
12900 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12901 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12902 | |
12903 | if (mips_pic == NO_PIC) | |
5919d012 | 12904 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12905 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12906 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12907 | else |
12908 | abort (); | |
12909 | ||
12910 | if (change) | |
12911 | { | |
4d7206a2 | 12912 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12913 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12914 | } |
4d7206a2 RS |
12915 | else |
12916 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12917 | } |
12918 | ||
12919 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12920 | should be converted into a reloc against a section. */ |
252b5132 RH |
12921 | |
12922 | int | |
17a2f251 | 12923 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12924 | { |
de7e6852 RS |
12925 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12926 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12927 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12928 | return 0; | |
a161fe53 | 12929 | |
252b5132 RH |
12930 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12931 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12932 | return 0; | |
a161fe53 | 12933 | |
252b5132 RH |
12934 | if (fixp->fx_addsy == NULL) |
12935 | return 1; | |
a161fe53 | 12936 | |
de7e6852 RS |
12937 | /* If symbol SYM is in a mergeable section, relocations of the form |
12938 | SYM + 0 can usually be made section-relative. The mergeable data | |
12939 | is then identified by the section offset rather than by the symbol. | |
12940 | ||
12941 | However, if we're generating REL LO16 relocations, the offset is split | |
12942 | between the LO16 and parterning high part relocation. The linker will | |
12943 | need to recalculate the complete offset in order to correctly identify | |
12944 | the merge data. | |
12945 | ||
12946 | The linker has traditionally not looked for the parterning high part | |
12947 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12948 | placed anywhere. Rather than break backwards compatibility by changing | |
12949 | this, it seems better not to force the issue, and instead keep the | |
12950 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
12951 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
12952 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
12953 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
12954 | && HAVE_IN_PLACE_ADDENDS |
12955 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12956 | return 0; | |
12957 | ||
252b5132 | 12958 | #ifdef OBJ_ELF |
de7e6852 RS |
12959 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12960 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12961 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12962 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12963 | && fixp->fx_subsy == NULL) | |
12964 | return 0; | |
12965 | #endif | |
a161fe53 | 12966 | |
252b5132 RH |
12967 | return 1; |
12968 | } | |
12969 | ||
12970 | /* Translate internal representation of relocation info to BFD target | |
12971 | format. */ | |
12972 | ||
12973 | arelent ** | |
17a2f251 | 12974 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12975 | { |
12976 | static arelent *retval[4]; | |
12977 | arelent *reloc; | |
12978 | bfd_reloc_code_real_type code; | |
12979 | ||
4b0cff4e TS |
12980 | memset (retval, 0, sizeof(retval)); |
12981 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12982 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12983 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12984 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12985 | ||
3e722fb5 CD |
12986 | assert (! fixp->fx_pcrel); |
12987 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12988 | |
438c16b8 TS |
12989 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12990 | entry to be used in the relocation's section offset. */ | |
12991 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12992 | { |
12993 | reloc->address = reloc->addend; | |
12994 | reloc->addend = 0; | |
12995 | } | |
12996 | ||
252b5132 | 12997 | code = fixp->fx_r_type; |
252b5132 | 12998 | |
3e722fb5 CD |
12999 | /* To support a PC relative reloc, we used a Cygnus extension. |
13000 | We check for that here to make sure that we don't let such a | |
13001 | reloc escape normally. (FIXME: This was formerly used by | |
13002 | embedded-PIC support, but is now used by branch handling in | |
13003 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
13004 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
13005 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 13006 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
13007 | reloc->howto = NULL; |
13008 | else | |
13009 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13010 | ||
252b5132 RH |
13011 | if (reloc->howto == NULL) |
13012 | { | |
13013 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13014 | _("Can not represent %s relocation in this object file format"), | |
13015 | bfd_get_reloc_code_name (code)); | |
13016 | retval[0] = NULL; | |
13017 | } | |
13018 | ||
13019 | return retval; | |
13020 | } | |
13021 | ||
13022 | /* Relax a machine dependent frag. This returns the amount by which | |
13023 | the current size of the frag should change. */ | |
13024 | ||
13025 | int | |
17a2f251 | 13026 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13027 | { |
4a6a3df4 AO |
13028 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13029 | { | |
13030 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13031 | |
13032 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13033 | |
13034 | return fragp->fr_var - old_var; | |
13035 | } | |
13036 | ||
252b5132 RH |
13037 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13038 | return 0; | |
13039 | ||
c4e7957c | 13040 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13041 | { |
13042 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13043 | return 0; | |
13044 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13045 | return 2; | |
13046 | } | |
13047 | else | |
13048 | { | |
13049 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13050 | return 0; | |
13051 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13052 | return -2; | |
13053 | } | |
13054 | ||
13055 | return 0; | |
13056 | } | |
13057 | ||
13058 | /* Convert a machine dependent frag. */ | |
13059 | ||
13060 | void | |
17a2f251 | 13061 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13062 | { |
4a6a3df4 AO |
13063 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13064 | { | |
13065 | bfd_byte *buf; | |
13066 | unsigned long insn; | |
13067 | expressionS exp; | |
13068 | fixS *fixp; | |
b34976b6 | 13069 | |
4a6a3df4 AO |
13070 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13071 | ||
13072 | if (target_big_endian) | |
13073 | insn = bfd_getb32 (buf); | |
13074 | else | |
13075 | insn = bfd_getl32 (buf); | |
b34976b6 | 13076 | |
4a6a3df4 AO |
13077 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13078 | { | |
13079 | /* We generate a fixup instead of applying it right now | |
13080 | because, if there are linker relaxations, we're going to | |
13081 | need the relocations. */ | |
13082 | exp.X_op = O_symbol; | |
13083 | exp.X_add_symbol = fragp->fr_symbol; | |
13084 | exp.X_add_number = fragp->fr_offset; | |
13085 | ||
13086 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13087 | 4, &exp, 1, |
13088 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13089 | fixp->fx_file = fragp->fr_file; |
13090 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13091 | |
2132e3a3 | 13092 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13093 | buf += 4; |
13094 | } | |
13095 | else | |
13096 | { | |
13097 | int i; | |
13098 | ||
13099 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13100 | _("relaxed out-of-range branch into a jump")); | |
13101 | ||
13102 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13103 | goto uncond; | |
13104 | ||
13105 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13106 | { | |
13107 | /* Reverse the branch. */ | |
13108 | switch ((insn >> 28) & 0xf) | |
13109 | { | |
13110 | case 4: | |
13111 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13112 | have the condition reversed by tweaking a single | |
13113 | bit, and their opcodes all have 0x4???????. */ | |
13114 | assert ((insn & 0xf1000000) == 0x41000000); | |
13115 | insn ^= 0x00010000; | |
13116 | break; | |
13117 | ||
13118 | case 0: | |
13119 | /* bltz 0x04000000 bgez 0x04010000 | |
13120 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13121 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13122 | insn ^= 0x00010000; | |
13123 | break; | |
b34976b6 | 13124 | |
4a6a3df4 AO |
13125 | case 1: |
13126 | /* beq 0x10000000 bne 0x14000000 | |
13127 | blez 0x18000000 bgtz 0x1c000000 */ | |
13128 | insn ^= 0x04000000; | |
13129 | break; | |
13130 | ||
13131 | default: | |
13132 | abort (); | |
13133 | } | |
13134 | } | |
13135 | ||
13136 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13137 | { | |
13138 | /* Clear the and-link bit. */ | |
13139 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13140 | ||
13141 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13142 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13143 | insn &= ~0x00100000; | |
13144 | } | |
13145 | ||
13146 | /* Branch over the branch (if the branch was likely) or the | |
13147 | full jump (not likely case). Compute the offset from the | |
13148 | current instruction to branch to. */ | |
13149 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13150 | i = 16; | |
13151 | else | |
13152 | { | |
13153 | /* How many bytes in instructions we've already emitted? */ | |
13154 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13155 | /* How many bytes in instructions from here to the end? */ | |
13156 | i = fragp->fr_var - i; | |
13157 | } | |
13158 | /* Convert to instruction count. */ | |
13159 | i >>= 2; | |
13160 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13161 | i--; |
4a6a3df4 AO |
13162 | insn |= i; |
13163 | /* Branch over the jump. */ | |
2132e3a3 | 13164 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13165 | buf += 4; |
13166 | ||
13167 | /* Nop */ | |
2132e3a3 | 13168 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13169 | buf += 4; |
13170 | ||
13171 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13172 | { | |
13173 | /* beql $0, $0, 2f */ | |
13174 | insn = 0x50000000; | |
13175 | /* Compute the PC offset from the current instruction to | |
13176 | the end of the variable frag. */ | |
13177 | /* How many bytes in instructions we've already emitted? */ | |
13178 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13179 | /* How many bytes in instructions from here to the end? */ | |
13180 | i = fragp->fr_var - i; | |
13181 | /* Convert to instruction count. */ | |
13182 | i >>= 2; | |
13183 | /* Don't decrement i, because we want to branch over the | |
13184 | delay slot. */ | |
13185 | ||
13186 | insn |= i; | |
2132e3a3 | 13187 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13188 | buf += 4; |
13189 | ||
2132e3a3 | 13190 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13191 | buf += 4; |
13192 | } | |
13193 | ||
13194 | uncond: | |
13195 | if (mips_pic == NO_PIC) | |
13196 | { | |
13197 | /* j or jal. */ | |
13198 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13199 | ? 0x0c000000 : 0x08000000); | |
13200 | exp.X_op = O_symbol; | |
13201 | exp.X_add_symbol = fragp->fr_symbol; | |
13202 | exp.X_add_number = fragp->fr_offset; | |
13203 | ||
13204 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13205 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13206 | fixp->fx_file = fragp->fr_file; | |
13207 | fixp->fx_line = fragp->fr_line; | |
13208 | ||
2132e3a3 | 13209 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13210 | buf += 4; |
13211 | } | |
13212 | else | |
13213 | { | |
13214 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13215 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13216 | exp.X_op = O_symbol; | |
13217 | exp.X_add_symbol = fragp->fr_symbol; | |
13218 | exp.X_add_number = fragp->fr_offset; | |
13219 | ||
13220 | if (fragp->fr_offset) | |
13221 | { | |
13222 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13223 | exp.X_add_number = 0; | |
13224 | } | |
13225 | ||
13226 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13227 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13228 | fixp->fx_file = fragp->fr_file; | |
13229 | fixp->fx_line = fragp->fr_line; | |
13230 | ||
2132e3a3 | 13231 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13232 | buf += 4; |
b34976b6 | 13233 | |
4a6a3df4 AO |
13234 | if (mips_opts.isa == ISA_MIPS1) |
13235 | { | |
13236 | /* nop */ | |
2132e3a3 | 13237 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13238 | buf += 4; |
13239 | } | |
13240 | ||
13241 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13242 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13243 | ||
13244 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13245 | 4, &exp, 0, BFD_RELOC_LO16); | |
13246 | fixp->fx_file = fragp->fr_file; | |
13247 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13248 | |
2132e3a3 | 13249 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13250 | buf += 4; |
13251 | ||
13252 | /* j(al)r $at. */ | |
13253 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13254 | insn = 0x0020f809; | |
13255 | else | |
13256 | insn = 0x00200008; | |
13257 | ||
2132e3a3 | 13258 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13259 | buf += 4; |
13260 | } | |
13261 | } | |
13262 | ||
13263 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13264 | + fragp->fr_fix + fragp->fr_var); | |
13265 | ||
13266 | fragp->fr_fix += fragp->fr_var; | |
13267 | ||
13268 | return; | |
13269 | } | |
13270 | ||
252b5132 RH |
13271 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13272 | { | |
13273 | int type; | |
13274 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13275 | bfd_boolean small, ext; |
252b5132 RH |
13276 | offsetT val; |
13277 | bfd_byte *buf; | |
13278 | unsigned long insn; | |
b34976b6 | 13279 | bfd_boolean use_extend; |
252b5132 RH |
13280 | unsigned short extend; |
13281 | ||
13282 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13283 | op = mips16_immed_operands; | |
13284 | while (op->type != type) | |
13285 | ++op; | |
13286 | ||
13287 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13288 | { | |
b34976b6 AM |
13289 | small = FALSE; |
13290 | ext = TRUE; | |
252b5132 RH |
13291 | } |
13292 | else | |
13293 | { | |
b34976b6 AM |
13294 | small = TRUE; |
13295 | ext = FALSE; | |
252b5132 RH |
13296 | } |
13297 | ||
6386f3a7 | 13298 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13299 | val = S_GET_VALUE (fragp->fr_symbol); |
13300 | if (op->pcrel) | |
13301 | { | |
13302 | addressT addr; | |
13303 | ||
13304 | addr = fragp->fr_address + fragp->fr_fix; | |
13305 | ||
13306 | /* The rules for the base address of a PC relative reloc are | |
13307 | complicated; see mips16_extended_frag. */ | |
13308 | if (type == 'p' || type == 'q') | |
13309 | { | |
13310 | addr += 2; | |
13311 | if (ext) | |
13312 | addr += 2; | |
13313 | /* Ignore the low bit in the target, since it will be | |
13314 | set for a text label. */ | |
13315 | if ((val & 1) != 0) | |
13316 | --val; | |
13317 | } | |
13318 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13319 | addr -= 4; | |
13320 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13321 | addr -= 2; | |
13322 | ||
13323 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13324 | val -= addr; | |
13325 | ||
13326 | /* Make sure the section winds up with the alignment we have | |
13327 | assumed. */ | |
13328 | if (op->shift > 0) | |
13329 | record_alignment (asec, op->shift); | |
13330 | } | |
13331 | ||
13332 | if (ext | |
13333 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13334 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13335 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13336 | _("extended instruction in delay slot")); | |
13337 | ||
13338 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13339 | ||
13340 | if (target_big_endian) | |
13341 | insn = bfd_getb16 (buf); | |
13342 | else | |
13343 | insn = bfd_getl16 (buf); | |
13344 | ||
13345 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13346 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13347 | small, ext, &insn, &use_extend, &extend); | |
13348 | ||
13349 | if (use_extend) | |
13350 | { | |
2132e3a3 | 13351 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13352 | fragp->fr_fix += 2; |
13353 | buf += 2; | |
13354 | } | |
13355 | ||
2132e3a3 | 13356 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13357 | fragp->fr_fix += 2; |
13358 | buf += 2; | |
13359 | } | |
13360 | else | |
13361 | { | |
4d7206a2 RS |
13362 | int first, second; |
13363 | fixS *fixp; | |
252b5132 | 13364 | |
4d7206a2 RS |
13365 | first = RELAX_FIRST (fragp->fr_subtype); |
13366 | second = RELAX_SECOND (fragp->fr_subtype); | |
13367 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13368 | |
584892a6 RS |
13369 | /* Possibly emit a warning if we've chosen the longer option. */ |
13370 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13371 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13372 | { | |
13373 | const char *msg = macro_warning (fragp->fr_subtype); | |
13374 | if (msg != 0) | |
13375 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13376 | } | |
13377 | ||
4d7206a2 RS |
13378 | /* Go through all the fixups for the first sequence. Disable them |
13379 | (by marking them as done) if we're going to use the second | |
13380 | sequence instead. */ | |
13381 | while (fixp | |
13382 | && fixp->fx_frag == fragp | |
13383 | && fixp->fx_where < fragp->fr_fix - second) | |
13384 | { | |
13385 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13386 | fixp->fx_done = 1; | |
13387 | fixp = fixp->fx_next; | |
13388 | } | |
252b5132 | 13389 | |
4d7206a2 RS |
13390 | /* Go through the fixups for the second sequence. Disable them if |
13391 | we're going to use the first sequence, otherwise adjust their | |
13392 | addresses to account for the relaxation. */ | |
13393 | while (fixp && fixp->fx_frag == fragp) | |
13394 | { | |
13395 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13396 | fixp->fx_where -= first; | |
13397 | else | |
13398 | fixp->fx_done = 1; | |
13399 | fixp = fixp->fx_next; | |
13400 | } | |
13401 | ||
13402 | /* Now modify the frag contents. */ | |
13403 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13404 | { | |
13405 | char *start; | |
13406 | ||
13407 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13408 | memmove (start, start + first, second); | |
13409 | fragp->fr_fix -= first; | |
13410 | } | |
13411 | else | |
13412 | fragp->fr_fix -= second; | |
252b5132 RH |
13413 | } |
13414 | } | |
13415 | ||
13416 | #ifdef OBJ_ELF | |
13417 | ||
13418 | /* This function is called after the relocs have been generated. | |
13419 | We've been storing mips16 text labels as odd. Here we convert them | |
13420 | back to even for the convenience of the debugger. */ | |
13421 | ||
13422 | void | |
17a2f251 | 13423 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13424 | { |
13425 | asymbol **syms; | |
13426 | unsigned int count, i; | |
13427 | ||
13428 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13429 | return; | |
13430 | ||
13431 | syms = bfd_get_outsymbols (stdoutput); | |
13432 | count = bfd_get_symcount (stdoutput); | |
13433 | for (i = 0; i < count; i++, syms++) | |
13434 | { | |
13435 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13436 | && ((*syms)->value & 1) != 0) | |
13437 | { | |
13438 | (*syms)->value &= ~1; | |
13439 | /* If the symbol has an odd size, it was probably computed | |
13440 | incorrectly, so adjust that as well. */ | |
13441 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13442 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13443 | } | |
13444 | } | |
13445 | } | |
13446 | ||
13447 | #endif | |
13448 | ||
13449 | /* This function is called whenever a label is defined. It is used | |
13450 | when handling branch delays; if a branch has a label, we assume we | |
13451 | can not move it. */ | |
13452 | ||
13453 | void | |
17a2f251 | 13454 | mips_define_label (symbolS *sym) |
252b5132 RH |
13455 | { |
13456 | struct insn_label_list *l; | |
13457 | ||
13458 | if (free_insn_labels == NULL) | |
13459 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13460 | else | |
13461 | { | |
13462 | l = free_insn_labels; | |
13463 | free_insn_labels = l->next; | |
13464 | } | |
13465 | ||
13466 | l->label = sym; | |
13467 | l->next = insn_labels; | |
13468 | insn_labels = l; | |
13469 | } | |
13470 | \f | |
13471 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13472 | ||
13473 | /* Some special processing for a MIPS ELF file. */ | |
13474 | ||
13475 | void | |
17a2f251 | 13476 | mips_elf_final_processing (void) |
252b5132 RH |
13477 | { |
13478 | /* Write out the register information. */ | |
316f5878 | 13479 | if (mips_abi != N64_ABI) |
252b5132 RH |
13480 | { |
13481 | Elf32_RegInfo s; | |
13482 | ||
13483 | s.ri_gprmask = mips_gprmask; | |
13484 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13485 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13486 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13487 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13488 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13489 | ||
13490 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13491 | ((Elf32_External_RegInfo *) | |
13492 | mips_regmask_frag)); | |
13493 | } | |
13494 | else | |
13495 | { | |
13496 | Elf64_Internal_RegInfo s; | |
13497 | ||
13498 | s.ri_gprmask = mips_gprmask; | |
13499 | s.ri_pad = 0; | |
13500 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13501 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13502 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13503 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13504 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13505 | ||
13506 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13507 | ((Elf64_External_RegInfo *) | |
13508 | mips_regmask_frag)); | |
13509 | } | |
13510 | ||
13511 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13512 | sort of BFD interface for this. */ | |
13513 | if (mips_any_noreorder) | |
13514 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13515 | if (mips_pic != NO_PIC) | |
143d77c5 | 13516 | { |
252b5132 | 13517 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13518 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13519 | } | |
13520 | if (mips_abicalls) | |
13521 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13522 | |
98d3f06f | 13523 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
13524 | /* We may need to define a new flag for DSP ASE, and set this flag when |
13525 | file_ase_dsp is true. */ | |
a4672219 TS |
13526 | if (file_ase_mips16) |
13527 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13528 | #if 0 /* XXX FIXME */ |
13529 | if (file_ase_mips3d) | |
13530 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13531 | #endif | |
deec1734 CD |
13532 | if (file_ase_mdmx) |
13533 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13534 | |
bdaaa2e1 | 13535 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13536 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13537 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13538 | else if (mips_abi == O64_ABI) |
252b5132 | 13539 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13540 | else if (mips_abi == EABI_ABI) |
252b5132 | 13541 | { |
316f5878 | 13542 | if (!file_mips_gp32) |
252b5132 RH |
13543 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13544 | else | |
13545 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13546 | } | |
316f5878 | 13547 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13548 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13549 | ||
c9914766 | 13550 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13551 | |
13552 | if (mips_32bitmode) | |
13553 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13554 | } | |
13555 | ||
13556 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13557 | \f | |
beae10d5 | 13558 | typedef struct proc { |
9b2f1d35 EC |
13559 | symbolS *func_sym; |
13560 | symbolS *func_end_sym; | |
beae10d5 KH |
13561 | unsigned long reg_mask; |
13562 | unsigned long reg_offset; | |
13563 | unsigned long fpreg_mask; | |
13564 | unsigned long fpreg_offset; | |
13565 | unsigned long frame_offset; | |
13566 | unsigned long frame_reg; | |
13567 | unsigned long pc_reg; | |
13568 | } procS; | |
252b5132 RH |
13569 | |
13570 | static procS cur_proc; | |
13571 | static procS *cur_proc_ptr; | |
13572 | static int numprocs; | |
13573 | ||
0a9ef439 | 13574 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13575 | |
0a9ef439 | 13576 | void |
17a2f251 | 13577 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13578 | { |
0a9ef439 RH |
13579 | if (fragp->fr_type != rs_align_code) |
13580 | return; | |
13581 | ||
13582 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13583 | { |
13584 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13585 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13586 | ||
0a9ef439 RH |
13587 | int bytes; |
13588 | char *p; | |
a19d8eb0 | 13589 | |
0a9ef439 RH |
13590 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13591 | p = fragp->fr_literal + fragp->fr_fix; | |
13592 | ||
13593 | if (bytes & 1) | |
13594 | { | |
13595 | *p++ = 0; | |
f9419b05 | 13596 | fragp->fr_fix++; |
0a9ef439 RH |
13597 | } |
13598 | ||
13599 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13600 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13601 | } |
13602 | ||
0a9ef439 | 13603 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13604 | } |
13605 | ||
252b5132 | 13606 | static void |
17a2f251 | 13607 | md_obj_begin (void) |
252b5132 RH |
13608 | { |
13609 | } | |
13610 | ||
13611 | static void | |
17a2f251 | 13612 | md_obj_end (void) |
252b5132 RH |
13613 | { |
13614 | /* check for premature end, nesting errors, etc */ | |
13615 | if (cur_proc_ptr) | |
9a41af64 | 13616 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13617 | } |
13618 | ||
13619 | static long | |
17a2f251 | 13620 | get_number (void) |
252b5132 RH |
13621 | { |
13622 | int negative = 0; | |
13623 | long val = 0; | |
13624 | ||
13625 | if (*input_line_pointer == '-') | |
13626 | { | |
13627 | ++input_line_pointer; | |
13628 | negative = 1; | |
13629 | } | |
3882b010 | 13630 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13631 | as_bad (_("expected simple number")); |
252b5132 RH |
13632 | if (input_line_pointer[0] == '0') |
13633 | { | |
13634 | if (input_line_pointer[1] == 'x') | |
13635 | { | |
13636 | input_line_pointer += 2; | |
3882b010 | 13637 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13638 | { |
13639 | val <<= 4; | |
13640 | val |= hex_value (*input_line_pointer++); | |
13641 | } | |
13642 | return negative ? -val : val; | |
13643 | } | |
13644 | else | |
13645 | { | |
13646 | ++input_line_pointer; | |
3882b010 | 13647 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13648 | { |
13649 | val <<= 3; | |
13650 | val |= *input_line_pointer++ - '0'; | |
13651 | } | |
13652 | return negative ? -val : val; | |
13653 | } | |
13654 | } | |
3882b010 | 13655 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13656 | { |
13657 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13658 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13659 | as_warn (_("invalid number")); |
252b5132 RH |
13660 | return -1; |
13661 | } | |
3882b010 | 13662 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13663 | { |
13664 | val *= 10; | |
13665 | val += *input_line_pointer++ - '0'; | |
13666 | } | |
13667 | return negative ? -val : val; | |
13668 | } | |
13669 | ||
13670 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13671 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13672 | case .file implies DWARF-2. */ | |
13673 | ||
13674 | static void | |
17a2f251 | 13675 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13676 | { |
ecb4347a DJ |
13677 | static int first_file_directive = 0; |
13678 | ||
c5dd6aab DJ |
13679 | if (ECOFF_DEBUGGING) |
13680 | { | |
13681 | get_number (); | |
13682 | s_app_file (0); | |
13683 | } | |
13684 | else | |
ecb4347a DJ |
13685 | { |
13686 | char *filename; | |
13687 | ||
13688 | filename = dwarf2_directive_file (0); | |
13689 | ||
13690 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13691 | directive even for stabs output. Make sure that this | |
13692 | ".file" is handled. Note that you need a version of GCC | |
13693 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13694 | if (filename != NULL && ! first_file_directive) | |
13695 | { | |
13696 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13697 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13698 | } |
13699 | first_file_directive = 1; | |
13700 | } | |
c5dd6aab DJ |
13701 | } |
13702 | ||
13703 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13704 | |
13705 | static void | |
17a2f251 | 13706 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13707 | { |
c5dd6aab DJ |
13708 | if (!ECOFF_DEBUGGING) |
13709 | dwarf2_directive_loc (0); | |
252b5132 RH |
13710 | } |
13711 | ||
252b5132 RH |
13712 | /* The .end directive. */ |
13713 | ||
13714 | static void | |
17a2f251 | 13715 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13716 | { |
13717 | symbolS *p; | |
252b5132 | 13718 | |
7a621144 DJ |
13719 | /* Following functions need their own .frame and .cprestore directives. */ |
13720 | mips_frame_reg_valid = 0; | |
13721 | mips_cprestore_valid = 0; | |
13722 | ||
252b5132 RH |
13723 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13724 | { | |
13725 | p = get_symbol (); | |
13726 | demand_empty_rest_of_line (); | |
13727 | } | |
13728 | else | |
13729 | p = NULL; | |
13730 | ||
14949570 | 13731 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13732 | as_warn (_(".end not in text section")); |
13733 | ||
13734 | if (!cur_proc_ptr) | |
13735 | { | |
13736 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13737 | demand_empty_rest_of_line (); | |
13738 | return; | |
13739 | } | |
13740 | ||
13741 | if (p != NULL) | |
13742 | { | |
13743 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13744 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13745 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13746 | |
13747 | if (debug_type == DEBUG_STABS) | |
13748 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13749 | S_GET_NAME (p)); | |
252b5132 RH |
13750 | } |
13751 | else | |
13752 | as_warn (_(".end directive missing or unknown symbol")); | |
13753 | ||
2132e3a3 | 13754 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13755 | /* Create an expression to calculate the size of the function. */ |
13756 | if (p && cur_proc_ptr) | |
13757 | { | |
13758 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13759 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13760 | ||
13761 | obj->size = exp; | |
13762 | exp->X_op = O_subtract; | |
13763 | exp->X_add_symbol = symbol_temp_new_now (); | |
13764 | exp->X_op_symbol = p; | |
13765 | exp->X_add_number = 0; | |
13766 | ||
13767 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13768 | } | |
13769 | ||
ecb4347a | 13770 | /* Generate a .pdr section. */ |
dcd410fe RO |
13771 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13772 | && mips_flag_pdr) | |
ecb4347a DJ |
13773 | { |
13774 | segT saved_seg = now_seg; | |
13775 | subsegT saved_subseg = now_subseg; | |
13776 | valueT dot; | |
13777 | expressionS exp; | |
13778 | char *fragp; | |
252b5132 | 13779 | |
ecb4347a | 13780 | dot = frag_now_fix (); |
252b5132 RH |
13781 | |
13782 | #ifdef md_flush_pending_output | |
ecb4347a | 13783 | md_flush_pending_output (); |
252b5132 RH |
13784 | #endif |
13785 | ||
ecb4347a DJ |
13786 | assert (pdr_seg); |
13787 | subseg_set (pdr_seg, 0); | |
252b5132 | 13788 | |
ecb4347a DJ |
13789 | /* Write the symbol. */ |
13790 | exp.X_op = O_symbol; | |
13791 | exp.X_add_symbol = p; | |
13792 | exp.X_add_number = 0; | |
13793 | emit_expr (&exp, 4); | |
252b5132 | 13794 | |
ecb4347a | 13795 | fragp = frag_more (7 * 4); |
252b5132 | 13796 | |
17a2f251 TS |
13797 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13798 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13799 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13800 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13801 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13802 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13803 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13804 | |
ecb4347a DJ |
13805 | subseg_set (saved_seg, saved_subseg); |
13806 | } | |
13807 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13808 | |
13809 | cur_proc_ptr = NULL; | |
13810 | } | |
13811 | ||
13812 | /* The .aent and .ent directives. */ | |
13813 | ||
13814 | static void | |
17a2f251 | 13815 | s_mips_ent (int aent) |
252b5132 | 13816 | { |
252b5132 | 13817 | symbolS *symbolP; |
252b5132 RH |
13818 | |
13819 | symbolP = get_symbol (); | |
13820 | if (*input_line_pointer == ',') | |
f9419b05 | 13821 | ++input_line_pointer; |
252b5132 | 13822 | SKIP_WHITESPACE (); |
3882b010 | 13823 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13824 | || *input_line_pointer == '-') |
874e8986 | 13825 | get_number (); |
252b5132 | 13826 | |
14949570 | 13827 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13828 | as_warn (_(".ent or .aent not in text section.")); |
13829 | ||
13830 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13831 | as_warn (_("missing .end")); |
252b5132 RH |
13832 | |
13833 | if (!aent) | |
13834 | { | |
7a621144 DJ |
13835 | /* This function needs its own .frame and .cprestore directives. */ |
13836 | mips_frame_reg_valid = 0; | |
13837 | mips_cprestore_valid = 0; | |
13838 | ||
252b5132 RH |
13839 | cur_proc_ptr = &cur_proc; |
13840 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13841 | ||
9b2f1d35 | 13842 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13843 | |
49309057 | 13844 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13845 | |
f9419b05 | 13846 | ++numprocs; |
ecb4347a DJ |
13847 | |
13848 | if (debug_type == DEBUG_STABS) | |
13849 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13850 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13851 | } |
13852 | ||
13853 | demand_empty_rest_of_line (); | |
13854 | } | |
13855 | ||
13856 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13857 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13858 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13859 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13860 | symbol table (in the mdebug section). */ |
13861 | ||
13862 | static void | |
17a2f251 | 13863 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13864 | { |
ecb4347a DJ |
13865 | #ifdef OBJ_ELF |
13866 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13867 | { | |
13868 | long val; | |
252b5132 | 13869 | |
ecb4347a DJ |
13870 | if (cur_proc_ptr == (procS *) NULL) |
13871 | { | |
13872 | as_warn (_(".frame outside of .ent")); | |
13873 | demand_empty_rest_of_line (); | |
13874 | return; | |
13875 | } | |
252b5132 | 13876 | |
ecb4347a DJ |
13877 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13878 | ||
13879 | SKIP_WHITESPACE (); | |
13880 | if (*input_line_pointer++ != ',' | |
13881 | || get_absolute_expression_and_terminator (&val) != ',') | |
13882 | { | |
13883 | as_warn (_("Bad .frame directive")); | |
13884 | --input_line_pointer; | |
13885 | demand_empty_rest_of_line (); | |
13886 | return; | |
13887 | } | |
252b5132 | 13888 | |
ecb4347a DJ |
13889 | cur_proc_ptr->frame_offset = val; |
13890 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13891 | |
252b5132 | 13892 | demand_empty_rest_of_line (); |
252b5132 | 13893 | } |
ecb4347a DJ |
13894 | else |
13895 | #endif /* OBJ_ELF */ | |
13896 | s_ignore (ignore); | |
252b5132 RH |
13897 | } |
13898 | ||
bdaaa2e1 KH |
13899 | /* The .fmask and .mask directives. If the mdebug section is present |
13900 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13901 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13902 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13903 | make reference to the ecoff symbol table (in the mdebug section). */ |
13904 | ||
13905 | static void | |
17a2f251 | 13906 | s_mips_mask (int reg_type) |
252b5132 | 13907 | { |
ecb4347a DJ |
13908 | #ifdef OBJ_ELF |
13909 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13910 | { |
ecb4347a | 13911 | long mask, off; |
252b5132 | 13912 | |
ecb4347a DJ |
13913 | if (cur_proc_ptr == (procS *) NULL) |
13914 | { | |
13915 | as_warn (_(".mask/.fmask outside of .ent")); | |
13916 | demand_empty_rest_of_line (); | |
13917 | return; | |
13918 | } | |
252b5132 | 13919 | |
ecb4347a DJ |
13920 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13921 | { | |
13922 | as_warn (_("Bad .mask/.fmask directive")); | |
13923 | --input_line_pointer; | |
13924 | demand_empty_rest_of_line (); | |
13925 | return; | |
13926 | } | |
252b5132 | 13927 | |
ecb4347a DJ |
13928 | off = get_absolute_expression (); |
13929 | ||
13930 | if (reg_type == 'F') | |
13931 | { | |
13932 | cur_proc_ptr->fpreg_mask = mask; | |
13933 | cur_proc_ptr->fpreg_offset = off; | |
13934 | } | |
13935 | else | |
13936 | { | |
13937 | cur_proc_ptr->reg_mask = mask; | |
13938 | cur_proc_ptr->reg_offset = off; | |
13939 | } | |
13940 | ||
13941 | demand_empty_rest_of_line (); | |
252b5132 RH |
13942 | } |
13943 | else | |
ecb4347a DJ |
13944 | #endif /* OBJ_ELF */ |
13945 | s_ignore (reg_type); | |
252b5132 RH |
13946 | } |
13947 | ||
316f5878 RS |
13948 | /* A table describing all the processors gas knows about. Names are |
13949 | matched in the order listed. | |
e7af610e | 13950 | |
316f5878 RS |
13951 | To ease comparison, please keep this table in the same order as |
13952 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13953 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13954 | { | |
316f5878 RS |
13955 | /* Entries for generic ISAs */ |
13956 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13957 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13958 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13959 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13960 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13961 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13962 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13963 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13964 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13965 | |
13966 | /* MIPS I */ | |
13967 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13968 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13969 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13970 | ||
13971 | /* MIPS II */ | |
13972 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13973 | ||
13974 | /* MIPS III */ | |
13975 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13976 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13977 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13978 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13979 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13980 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13981 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13982 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13983 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13984 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13985 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13986 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13987 | ||
13988 | /* MIPS IV */ | |
13989 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13990 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13991 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13992 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13993 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13994 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13995 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13996 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13997 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13998 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13999 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 14000 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 14001 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
14002 | |
14003 | /* MIPS 32 */ | |
fef14a42 | 14004 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14005 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14006 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14007 | |
32b26a03 MR |
14008 | /* MIPS32 Release 2 */ |
14009 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14010 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14011 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14012 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14013 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14014 | ||
316f5878 RS |
14015 | /* MIPS 64 */ |
14016 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
ff324200 | 14017 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, |
316f5878 | 14018 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
e7af610e | 14019 | |
c7a23324 | 14020 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14021 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14022 | |
316f5878 RS |
14023 | /* End marker */ |
14024 | { NULL, 0, 0, 0 } | |
14025 | }; | |
e7af610e | 14026 | |
84ea6cf2 | 14027 | |
316f5878 RS |
14028 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14029 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14030 | |
316f5878 | 14031 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14032 | |
b34976b6 | 14033 | static bfd_boolean |
17a2f251 | 14034 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14035 | { |
14036 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14037 | given++, canonical++; | |
14038 | ||
14039 | return ((*given == 0 && *canonical == 0) | |
14040 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14041 | } | |
14042 | ||
14043 | ||
14044 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14045 | CPU name. We've traditionally allowed a lot of variation here. | |
14046 | ||
14047 | Note: this function is shared between GCC and GAS. */ | |
14048 | ||
b34976b6 | 14049 | static bfd_boolean |
17a2f251 | 14050 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14051 | { |
14052 | /* First see if the name matches exactly, or with a final "000" | |
14053 | turned into "k". */ | |
14054 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14055 | return TRUE; |
316f5878 RS |
14056 | |
14057 | /* If not, try comparing based on numerical designation alone. | |
14058 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14059 | if (TOLOWER (*given) == 'r') | |
14060 | given++; | |
14061 | if (!ISDIGIT (*given)) | |
b34976b6 | 14062 | return FALSE; |
316f5878 RS |
14063 | |
14064 | /* Skip over some well-known prefixes in the canonical name, | |
14065 | hoping to find a number there too. */ | |
14066 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14067 | canonical += 2; | |
14068 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14069 | canonical += 2; | |
14070 | else if (TOLOWER (canonical[0]) == 'r') | |
14071 | canonical += 1; | |
14072 | ||
14073 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14074 | } | |
14075 | ||
14076 | ||
14077 | /* Parse an option that takes the name of a processor as its argument. | |
14078 | OPTION is the name of the option and CPU_STRING is the argument. | |
14079 | Return the corresponding processor enumeration if the CPU_STRING is | |
14080 | recognized, otherwise report an error and return null. | |
14081 | ||
14082 | A similar function exists in GCC. */ | |
e7af610e NC |
14083 | |
14084 | static const struct mips_cpu_info * | |
17a2f251 | 14085 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14086 | { |
316f5878 | 14087 | const struct mips_cpu_info *p; |
e7af610e | 14088 | |
316f5878 RS |
14089 | /* 'from-abi' selects the most compatible architecture for the given |
14090 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14091 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14092 | version. Look first at the -mgp options, if given, otherwise base | |
14093 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14094 | |
316f5878 RS |
14095 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14096 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14097 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14098 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14099 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14100 | { | |
14101 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14102 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14103 | ||
14104 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14105 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14106 | ||
14107 | if (file_mips_gp32 >= 0) | |
14108 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14109 | ||
14110 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14111 | ? ISA_MIPS3 | |
14112 | : ISA_MIPS1); | |
14113 | } | |
14114 | ||
14115 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14116 | if (strcasecmp (cpu_string, "default") == 0) | |
14117 | return 0; | |
14118 | ||
14119 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14120 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14121 | return p; | |
14122 | ||
14123 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14124 | return 0; | |
e7af610e NC |
14125 | } |
14126 | ||
316f5878 RS |
14127 | /* Return the canonical processor information for ISA (a member of the |
14128 | ISA_MIPS* enumeration). */ | |
14129 | ||
e7af610e | 14130 | static const struct mips_cpu_info * |
17a2f251 | 14131 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14132 | { |
14133 | int i; | |
14134 | ||
14135 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14136 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14137 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14138 | return (&mips_cpu_info_table[i]); |
14139 | ||
e972090a | 14140 | return NULL; |
e7af610e | 14141 | } |
fef14a42 TS |
14142 | |
14143 | static const struct mips_cpu_info * | |
17a2f251 | 14144 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14145 | { |
14146 | int i; | |
14147 | ||
14148 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14149 | if (arch == mips_cpu_info_table[i].cpu) | |
14150 | return (&mips_cpu_info_table[i]); | |
14151 | ||
14152 | return NULL; | |
14153 | } | |
316f5878 RS |
14154 | \f |
14155 | static void | |
17a2f251 | 14156 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14157 | { |
14158 | if (*first_p) | |
14159 | { | |
14160 | fprintf (stream, "%24s", ""); | |
14161 | *col_p = 24; | |
14162 | } | |
14163 | else | |
14164 | { | |
14165 | fprintf (stream, ", "); | |
14166 | *col_p += 2; | |
14167 | } | |
e7af610e | 14168 | |
316f5878 RS |
14169 | if (*col_p + strlen (string) > 72) |
14170 | { | |
14171 | fprintf (stream, "\n%24s", ""); | |
14172 | *col_p = 24; | |
14173 | } | |
14174 | ||
14175 | fprintf (stream, "%s", string); | |
14176 | *col_p += strlen (string); | |
14177 | ||
14178 | *first_p = 0; | |
14179 | } | |
14180 | ||
14181 | void | |
17a2f251 | 14182 | md_show_usage (FILE *stream) |
e7af610e | 14183 | { |
316f5878 RS |
14184 | int column, first; |
14185 | size_t i; | |
14186 | ||
14187 | fprintf (stream, _("\ | |
14188 | MIPS options:\n\ | |
316f5878 RS |
14189 | -EB generate big endian output\n\ |
14190 | -EL generate little endian output\n\ | |
14191 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14192 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14193 | implicitly with the gp register [default 8]\n")); | |
14194 | fprintf (stream, _("\ | |
14195 | -mips1 generate MIPS ISA I instructions\n\ | |
14196 | -mips2 generate MIPS ISA II instructions\n\ | |
14197 | -mips3 generate MIPS ISA III instructions\n\ | |
14198 | -mips4 generate MIPS ISA IV instructions\n\ | |
14199 | -mips5 generate MIPS ISA V instructions\n\ | |
14200 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14201 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14202 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14203 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14204 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14205 | ||
14206 | first = 1; | |
e7af610e NC |
14207 | |
14208 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14209 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14210 | show (stream, "from-abi", &column, &first); | |
14211 | fputc ('\n', stream); | |
e7af610e | 14212 | |
316f5878 RS |
14213 | fprintf (stream, _("\ |
14214 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14215 | -no-mCPU don't generate code specific to CPU.\n\ | |
14216 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14217 | ||
14218 | first = 1; | |
14219 | ||
14220 | show (stream, "3900", &column, &first); | |
14221 | show (stream, "4010", &column, &first); | |
14222 | show (stream, "4100", &column, &first); | |
14223 | show (stream, "4650", &column, &first); | |
14224 | fputc ('\n', stream); | |
14225 | ||
14226 | fprintf (stream, _("\ | |
14227 | -mips16 generate mips16 instructions\n\ | |
14228 | -no-mips16 do not generate mips16 instructions\n")); | |
14229 | fprintf (stream, _("\ | |
74cd071d CF |
14230 | -mdsp generate DSP instructions\n\ |
14231 | -mno-dsp do not generate DSP instructions\n")); | |
14232 | fprintf (stream, _("\ | |
d766e8ec | 14233 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14234 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14235 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14236 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14237 | -mno-shared optimize output for executables\n\ |
14238 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14239 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14240 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14241 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14242 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14243 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14244 | #ifdef OBJ_ELF | |
14245 | fprintf (stream, _("\ | |
14246 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14247 | -non_shared do not generate position independent code\n\ | |
14248 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14249 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14250 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14251 | non-shared code\n\ | |
316f5878 RS |
14252 | -mabi=ABI create ABI conformant object file for:\n")); |
14253 | ||
14254 | first = 1; | |
14255 | ||
14256 | show (stream, "32", &column, &first); | |
14257 | show (stream, "o64", &column, &first); | |
14258 | show (stream, "n32", &column, &first); | |
14259 | show (stream, "64", &column, &first); | |
14260 | show (stream, "eabi", &column, &first); | |
14261 | ||
14262 | fputc ('\n', stream); | |
14263 | ||
14264 | fprintf (stream, _("\ | |
14265 | -32 create o32 ABI object file (default)\n\ | |
14266 | -n32 create n32 ABI object file\n\ | |
14267 | -64 create 64 ABI object file\n")); | |
14268 | #endif | |
e7af610e | 14269 | } |
14e777e0 KB |
14270 | |
14271 | enum dwarf2_format | |
17a2f251 | 14272 | mips_dwarf2_format (void) |
14e777e0 KB |
14273 | { |
14274 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14275 | { |
14276 | #ifdef TE_IRIX | |
14277 | return dwarf2_format_64bit_irix; | |
14278 | #else | |
14279 | return dwarf2_format_64bit; | |
14280 | #endif | |
14281 | } | |
14e777e0 KB |
14282 | else |
14283 | return dwarf2_format_32bit; | |
14284 | } | |
73369e65 EC |
14285 | |
14286 | int | |
14287 | mips_dwarf2_addr_size (void) | |
14288 | { | |
14289 | if (mips_abi == N64_ABI) | |
14290 | return 8; | |
73369e65 EC |
14291 | else |
14292 | return 4; | |
14293 | } | |
5862107c EC |
14294 | |
14295 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14296 | void | |
14297 | mips_cfi_frame_initial_instructions (void) | |
14298 | { | |
14299 | cfi_add_CFA_def_cfa_register (SP); | |
14300 | } | |
14301 |