Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
071742cf | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
c5dd6aab | 40 | #include "dwarf2dbg.h" |
252b5132 RH |
41 | |
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
ecb4347a DJ |
80 | int mips_flag_mdebug = -1; |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
85 | static char *mips_regmask_frag; | |
86 | #endif | |
87 | ||
85b51719 | 88 | #define ZERO 0 |
252b5132 RH |
89 | #define AT 1 |
90 | #define TREG 24 | |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
101 | /* Allow override of standard little-endian ECOFF format. */ | |
102 | ||
103 | #ifndef ECOFF_LITTLE_FORMAT | |
104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
105 | #endif | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
252b5132 RH |
109 | /* The name of the readonly data section. */ |
110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
111 | ? ".data" \ | |
112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
113 | ? ".rdata" \ | |
056350c6 NC |
114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
115 | ? ".rdata" \ | |
252b5132 RH |
116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
117 | ? ".rodata" \ | |
118 | : (abort (), "")) | |
119 | ||
a325df1d TS |
120 | /* The ABI to use. */ |
121 | enum mips_abi_level | |
122 | { | |
123 | NO_ABI = 0, | |
124 | O32_ABI, | |
125 | O64_ABI, | |
126 | N32_ABI, | |
127 | N64_ABI, | |
128 | EABI_ABI | |
129 | }; | |
130 | ||
131 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 132 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 133 | |
143d77c5 EC |
134 | /* Whether or not we have code that can call pic code. */ |
135 | int mips_abicalls = FALSE; | |
136 | ||
252b5132 RH |
137 | /* This is the set of options which may be modified by the .set |
138 | pseudo-op. We use a struct so that .set push and .set pop are more | |
139 | reliable. */ | |
140 | ||
e972090a NC |
141 | struct mips_set_options |
142 | { | |
252b5132 RH |
143 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
144 | if it has not been initialized. Changed by `.set mipsN', and the | |
145 | -mipsN command line option, and the default CPU. */ | |
146 | int isa; | |
1f25f5d3 CD |
147 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
148 | if they have not been initialized. Changed by `.set <asename>', by | |
149 | command line options, and based on the default architecture. */ | |
150 | int ase_mips3d; | |
deec1734 | 151 | int ase_mdmx; |
252b5132 RH |
152 | /* Whether we are assembling for the mips16 processor. 0 if we are |
153 | not, 1 if we are, and -1 if the value has not been initialized. | |
154 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
155 | -nomips16 command line options, and the default CPU. */ | |
156 | int mips16; | |
157 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
158 | reorder' and `.set noreorder'. */ | |
159 | int noreorder; | |
160 | /* Non-zero if we should not permit the $at ($1) register to be used | |
161 | in instructions. Changed by `.set at' and `.set noat'. */ | |
162 | int noat; | |
163 | /* Non-zero if we should warn when a macro instruction expands into | |
164 | more than one machine instruction. Changed by `.set nomacro' and | |
165 | `.set macro'. */ | |
166 | int warn_about_macros; | |
167 | /* Non-zero if we should not move instructions. Changed by `.set | |
168 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
169 | int nomove; | |
170 | /* Non-zero if we should not optimize branches by moving the target | |
171 | of the branch into the delay slot. Actually, we don't perform | |
172 | this optimization anyhow. Changed by `.set bopt' and `.set | |
173 | nobopt'. */ | |
174 | int nobopt; | |
175 | /* Non-zero if we should not autoextend mips16 instructions. | |
176 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
177 | int noautoextend; | |
a325df1d TS |
178 | /* Restrict general purpose registers and floating point registers |
179 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
180 | is passed but can changed if the assembler code uses .set mipsN. */ | |
181 | int gp32; | |
182 | int fp32; | |
252b5132 RH |
183 | }; |
184 | ||
a325df1d | 185 | /* True if -mgp32 was passed. */ |
a8e8e863 | 186 | static int file_mips_gp32 = -1; |
a325df1d TS |
187 | |
188 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 189 | static int file_mips_fp32 = -1; |
a325df1d | 190 | |
252b5132 | 191 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 192 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 193 | -1 to indicate that they have not been initialized. */ |
252b5132 | 194 | |
e972090a NC |
195 | static struct mips_set_options mips_opts = |
196 | { | |
316f5878 | 197 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
e7af610e | 198 | }; |
252b5132 RH |
199 | |
200 | /* These variables are filled in with the masks of registers used. | |
201 | The object format code reads them and puts them in the appropriate | |
202 | place. */ | |
203 | unsigned long mips_gprmask; | |
204 | unsigned long mips_cprmask[4]; | |
205 | ||
206 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 207 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 208 | |
a4672219 TS |
209 | /* True if -mips16 was passed or implied by arguments passed on the |
210 | command line (e.g., by -march). */ | |
211 | static int file_ase_mips16; | |
212 | ||
1f25f5d3 CD |
213 | /* True if -mips3d was passed or implied by arguments passed on the |
214 | command line (e.g., by -march). */ | |
215 | static int file_ase_mips3d; | |
216 | ||
deec1734 CD |
217 | /* True if -mdmx was passed or implied by arguments passed on the |
218 | command line (e.g., by -march). */ | |
219 | static int file_ase_mdmx; | |
220 | ||
ec68c924 EC |
221 | /* The argument of the -march= flag. The architecture we are assembling. */ |
222 | static int mips_arch = CPU_UNKNOWN; | |
316f5878 RS |
223 | static const char *mips_arch_string; |
224 | static const struct mips_cpu_info *mips_arch_info; | |
ec68c924 EC |
225 | |
226 | /* The argument of the -mtune= flag. The architecture for which we | |
227 | are optimizing. */ | |
228 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 RS |
229 | static const char *mips_tune_string; |
230 | static const struct mips_cpu_info *mips_tune_info; | |
ec68c924 | 231 | |
316f5878 | 232 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
233 | static int mips_32bitmode = 0; |
234 | ||
9ce8a5dd GRK |
235 | /* Some ISA's have delay slots for instructions which read or write |
236 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 237 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
238 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
239 | delay slot in this ISA. The uses of this macro assume that any | |
240 | ISA that has delay slots for one of these, has them for all. They | |
241 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 242 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 243 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
244 | (ISA) == ISA_MIPS1 \ |
245 | || (ISA) == ISA_MIPS2 \ | |
246 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
247 | ) |
248 | ||
316f5878 RS |
249 | /* True if the given ABI requires 32-bit registers. */ |
250 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
251 | ||
252 | /* Likewise 64-bit registers. */ | |
253 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
254 | ((ABI) == N32_ABI \ | |
255 | || (ABI) == N64_ABI \ | |
256 | || (ABI) == O64_ABI) | |
257 | ||
bdaaa2e1 | 258 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 259 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
260 | (ISA) == ISA_MIPS3 \ |
261 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 262 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 263 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
264 | ) |
265 | ||
af7ee8bf CD |
266 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
267 | instructions. */ | |
268 | #define ISA_HAS_DROR(ISA) ( \ | |
269 | 0 \ | |
270 | ) | |
271 | ||
272 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
273 | instructions. */ | |
274 | #define ISA_HAS_ROR(ISA) ( \ | |
275 | (ISA) == ISA_MIPS32R2 \ | |
276 | ) | |
277 | ||
e013f690 | 278 | #define HAVE_32BIT_GPRS \ |
316f5878 | 279 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 280 | |
e013f690 | 281 | #define HAVE_32BIT_FPRS \ |
316f5878 | 282 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
283 | |
284 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
285 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
286 | ||
316f5878 | 287 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 288 | |
316f5878 | 289 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
290 | |
291 | /* We can only have 64bit addresses if the object file format | |
292 | supports it. */ | |
afdbd6d0 CD |
293 | #define HAVE_32BIT_ADDRESSES \ |
294 | (HAVE_32BIT_GPRS \ | |
295 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
296 | || ! HAVE_64BIT_OBJECTS) \ | |
297 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
298 | |
299 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
5a7a0b7b AO |
300 | #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \ |
301 | || HAVE_64BIT_GPRS) | |
ca4e0257 | 302 | |
b7c7d6c1 TS |
303 | /* Addresses are loaded in different ways, depending on the address size |
304 | in use. The n32 ABI Documentation also mandates the use of additions | |
305 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 306 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 307 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
308 | |
309 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 310 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
311 | |
312 | #define ADDRESS_LOAD_INSN \ | |
313 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
314 | ||
315 | #define ADDRESS_STORE_INSN \ | |
316 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
317 | ||
a4672219 | 318 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
319 | #define CPU_HAS_MIPS16(cpu) \ |
320 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
321 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 322 | |
1f25f5d3 CD |
323 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
324 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
325 | ) | |
326 | ||
deec1734 | 327 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 328 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
329 | ) |
330 | ||
60b63b72 RS |
331 | /* True if CPU has a dror instruction. */ |
332 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
333 | ||
334 | /* True if CPU has a ror instruction. */ | |
335 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
336 | ||
bdaaa2e1 | 337 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 338 | reads from the HI and LO registers, and thus does not |
ec68c924 | 339 | require nops to be inserted. */ |
252b5132 | 340 | |
ec68c924 | 341 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
60b63b72 | 342 | || mips_arch == CPU_VR5500 \ |
0a758a12 | 343 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
344 | ) |
345 | ||
346 | /* Whether the processor uses hardware interlocks to protect reads | |
347 | from the GPRs, and thus does not require nops to be inserted. */ | |
348 | #define gpr_interlocks \ | |
e7af610e | 349 | (mips_opts.isa != ISA_MIPS1 \ |
60b63b72 RS |
350 | || mips_arch == CPU_VR5400 \ |
351 | || mips_arch == CPU_VR5500 \ | |
ec68c924 | 352 | || mips_arch == CPU_R3900) |
252b5132 RH |
353 | |
354 | /* As with other "interlocks" this is used by hardware that has FP | |
355 | (co-processor) interlocks. */ | |
bdaaa2e1 | 356 | /* Itbl support may require additional care here. */ |
ec68c924 | 357 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
60b63b72 RS |
358 | || mips_arch == CPU_VR5400 \ |
359 | || mips_arch == CPU_VR5500 \ | |
0a758a12 | 360 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
361 | ) |
362 | ||
6b76fefe CM |
363 | /* Is this a mfhi or mflo instruction? */ |
364 | #define MF_HILO_INSN(PINFO) \ | |
365 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
366 | ||
252b5132 RH |
367 | /* MIPS PIC level. */ |
368 | ||
a161fe53 | 369 | enum mips_pic_level mips_pic; |
252b5132 | 370 | |
39c0a331 L |
371 | /* Warn about all NOPS that the assembler generates. */ |
372 | static int warn_nops = 0; | |
373 | ||
c9914766 | 374 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 375 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 376 | static int mips_big_got = 0; |
252b5132 RH |
377 | |
378 | /* 1 if trap instructions should used for overflow rather than break | |
379 | instructions. */ | |
c9914766 | 380 | static int mips_trap = 0; |
252b5132 | 381 | |
119d663a | 382 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 383 | by assembling two single width halves into two single width floating |
119d663a NC |
384 | point registers which just happen to alias the double width destination |
385 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 386 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
387 | automatically at assemble time. */ |
388 | static int mips_disable_float_construction; | |
389 | ||
252b5132 RH |
390 | /* Non-zero if any .set noreorder directives were used. */ |
391 | ||
392 | static int mips_any_noreorder; | |
393 | ||
6b76fefe CM |
394 | /* Non-zero if nops should be inserted when the register referenced in |
395 | an mfhi/mflo instruction is read in the next two instructions. */ | |
396 | static int mips_7000_hilo_fix; | |
397 | ||
252b5132 | 398 | /* The size of the small data section. */ |
156c2f8b | 399 | static unsigned int g_switch_value = 8; |
252b5132 RH |
400 | /* Whether the -G option was used. */ |
401 | static int g_switch_seen = 0; | |
402 | ||
403 | #define N_RMASK 0xc4 | |
404 | #define N_VFP 0xd4 | |
405 | ||
406 | /* If we can determine in advance that GP optimization won't be | |
407 | possible, we can skip the relaxation stuff that tries to produce | |
408 | GP-relative references. This makes delay slot optimization work | |
409 | better. | |
410 | ||
411 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
412 | gcc output. It needs to guess right for gcc, otherwise gcc |
413 | will put what it thinks is a GP-relative instruction in a branch | |
414 | delay slot. | |
252b5132 RH |
415 | |
416 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
417 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
418 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
419 | ||
420 | /* handle of the OPCODE hash table */ | |
421 | static struct hash_control *op_hash = NULL; | |
422 | ||
423 | /* The opcode hash table we use for the mips16. */ | |
424 | static struct hash_control *mips16_op_hash = NULL; | |
425 | ||
426 | /* This array holds the chars that always start a comment. If the | |
427 | pre-processor is disabled, these aren't very useful */ | |
428 | const char comment_chars[] = "#"; | |
429 | ||
430 | /* This array holds the chars that only start a comment at the beginning of | |
431 | a line. If the line seems to have the form '# 123 filename' | |
432 | .line and .file directives will appear in the pre-processed output */ | |
433 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
434 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 435 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
436 | /* Also note that C style comments are always supported. */ |
437 | const char line_comment_chars[] = "#"; | |
438 | ||
bdaaa2e1 | 439 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 440 | const char line_separator_chars[] = ";"; |
252b5132 RH |
441 | |
442 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
443 | const char EXP_CHARS[] = "eE"; | |
444 | ||
445 | /* Chars that mean this number is a floating point constant */ | |
446 | /* As in 0f12.456 */ | |
447 | /* or 0d1.2345e12 */ | |
448 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
449 | ||
450 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
451 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
452 | but nothing is ideal around here. | |
453 | */ | |
454 | ||
455 | static char *insn_error; | |
456 | ||
457 | static int auto_align = 1; | |
458 | ||
459 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
460 | offset in the stack frame from which to restore the $gp register. | |
461 | This is set by the .cprestore pseudo-op, and saved in this | |
462 | variable. */ | |
463 | static offsetT mips_cprestore_offset = -1; | |
464 | ||
6478892d TS |
465 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
466 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 467 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
468 | static offsetT mips_cpreturn_offset = -1; |
469 | static int mips_cpreturn_register = -1; | |
470 | static int mips_gp_register = GP; | |
def2e0dd | 471 | static int mips_gprel_offset = 0; |
6478892d | 472 | |
7a621144 DJ |
473 | /* Whether mips_cprestore_offset has been set in the current function |
474 | (or whether it has already been warned about, if not). */ | |
475 | static int mips_cprestore_valid = 0; | |
476 | ||
252b5132 RH |
477 | /* This is the register which holds the stack frame, as set by the |
478 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
479 | static int mips_frame_reg = SP; | |
480 | ||
7a621144 DJ |
481 | /* Whether mips_frame_reg has been set in the current function |
482 | (or whether it has already been warned about, if not). */ | |
483 | static int mips_frame_reg_valid = 0; | |
484 | ||
252b5132 RH |
485 | /* To output NOP instructions correctly, we need to keep information |
486 | about the previous two instructions. */ | |
487 | ||
488 | /* Whether we are optimizing. The default value of 2 means to remove | |
489 | unneeded NOPs and swap branch instructions when possible. A value | |
490 | of 1 means to not swap branches. A value of 0 means to always | |
491 | insert NOPs. */ | |
492 | static int mips_optimize = 2; | |
493 | ||
494 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
495 | equivalent to seeing no -g option at all. */ | |
496 | static int mips_debug = 0; | |
497 | ||
498 | /* The previous instruction. */ | |
499 | static struct mips_cl_insn prev_insn; | |
500 | ||
501 | /* The instruction before prev_insn. */ | |
502 | static struct mips_cl_insn prev_prev_insn; | |
503 | ||
504 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
505 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 506 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
507 | |
508 | /* Non-zero if prev_insn is valid. */ | |
509 | static int prev_insn_valid; | |
510 | ||
511 | /* The frag for the previous instruction. */ | |
512 | static struct frag *prev_insn_frag; | |
513 | ||
514 | /* The offset into prev_insn_frag for the previous instruction. */ | |
515 | static long prev_insn_where; | |
516 | ||
517 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 518 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
519 | |
520 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 521 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
522 | |
523 | /* Non-zero if the previous instruction was in a delay slot. */ | |
524 | static int prev_insn_is_delay_slot; | |
525 | ||
526 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
527 | static int prev_insn_unreordered; | |
528 | ||
529 | /* Non-zero if the previous instruction uses an extend opcode (if | |
530 | mips16). */ | |
531 | static int prev_insn_extended; | |
532 | ||
533 | /* Non-zero if the previous previous instruction was in a .set | |
534 | noreorder. */ | |
535 | static int prev_prev_insn_unreordered; | |
536 | ||
537 | /* If this is set, it points to a frag holding nop instructions which | |
538 | were inserted before the start of a noreorder section. If those | |
539 | nops turn out to be unnecessary, the size of the frag can be | |
540 | decreased. */ | |
541 | static fragS *prev_nop_frag; | |
542 | ||
543 | /* The number of nop instructions we created in prev_nop_frag. */ | |
544 | static int prev_nop_frag_holds; | |
545 | ||
546 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 547 | prev_nop_frag. */ |
252b5132 RH |
548 | static int prev_nop_frag_required; |
549 | ||
550 | /* The number of instructions we've seen since prev_nop_frag. */ | |
551 | static int prev_nop_frag_since; | |
552 | ||
553 | /* For ECOFF and ELF, relocations against symbols are done in two | |
554 | parts, with a HI relocation and a LO relocation. Each relocation | |
555 | has only 16 bits of space to store an addend. This means that in | |
556 | order for the linker to handle carries correctly, it must be able | |
557 | to locate both the HI and the LO relocation. This means that the | |
558 | relocations must appear in order in the relocation table. | |
559 | ||
560 | In order to implement this, we keep track of each unmatched HI | |
561 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 562 | corresponding LO relocation. */ |
252b5132 | 563 | |
e972090a NC |
564 | struct mips_hi_fixup |
565 | { | |
252b5132 RH |
566 | /* Next HI fixup. */ |
567 | struct mips_hi_fixup *next; | |
568 | /* This fixup. */ | |
569 | fixS *fixp; | |
570 | /* The section this fixup is in. */ | |
571 | segT seg; | |
572 | }; | |
573 | ||
574 | /* The list of unmatched HI relocs. */ | |
575 | ||
576 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
577 | ||
64bdfcaf RS |
578 | /* The frag containing the last explicit relocation operator. |
579 | Null if explicit relocations have not been used. */ | |
580 | ||
581 | static fragS *prev_reloc_op_frag; | |
582 | ||
252b5132 RH |
583 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
584 | ||
585 | #define X ILLEGAL_REG | |
e972090a NC |
586 | static const int mips32_to_16_reg_map[] = |
587 | { | |
252b5132 RH |
588 | X, X, 2, 3, 4, 5, 6, 7, |
589 | X, X, X, X, X, X, X, X, | |
590 | 0, 1, X, X, X, X, X, X, | |
591 | X, X, X, X, X, X, X, X | |
592 | }; | |
593 | #undef X | |
594 | ||
595 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
596 | ||
e972090a NC |
597 | static const unsigned int mips16_to_32_reg_map[] = |
598 | { | |
252b5132 RH |
599 | 16, 17, 2, 3, 4, 5, 6, 7 |
600 | }; | |
60b63b72 RS |
601 | |
602 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
603 | |
604 | /* We don't relax branches by default, since this causes us to expand | |
605 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
606 | fail to compute the offset before expanding the macro to the most | |
607 | efficient expansion. */ | |
608 | ||
609 | static int mips_relax_branch; | |
252b5132 RH |
610 | \f |
611 | /* Since the MIPS does not have multiple forms of PC relative | |
612 | instructions, we do not have to do relaxing as is done on other | |
613 | platforms. However, we do have to handle GP relative addressing | |
614 | correctly, which turns out to be a similar problem. | |
615 | ||
616 | Every macro that refers to a symbol can occur in (at least) two | |
617 | forms, one with GP relative addressing and one without. For | |
618 | example, loading a global variable into a register generally uses | |
619 | a macro instruction like this: | |
620 | lw $4,i | |
621 | If i can be addressed off the GP register (this is true if it is in | |
622 | the .sbss or .sdata section, or if it is known to be smaller than | |
623 | the -G argument) this will generate the following instruction: | |
624 | lw $4,i($gp) | |
625 | This instruction will use a GPREL reloc. If i can not be addressed | |
626 | off the GP register, the following instruction sequence will be used: | |
627 | lui $at,i | |
628 | lw $4,i($at) | |
629 | In this case the first instruction will have a HI16 reloc, and the | |
630 | second reloc will have a LO16 reloc. Both relocs will be against | |
631 | the symbol i. | |
632 | ||
633 | The issue here is that we may not know whether i is GP addressable | |
634 | until after we see the instruction that uses it. Therefore, we | |
635 | want to be able to choose the final instruction sequence only at | |
636 | the end of the assembly. This is similar to the way other | |
637 | platforms choose the size of a PC relative instruction only at the | |
638 | end of assembly. | |
639 | ||
640 | When generating position independent code we do not use GP | |
641 | addressing in quite the same way, but the issue still arises as | |
642 | external symbols and local symbols must be handled differently. | |
643 | ||
644 | We handle these issues by actually generating both possible | |
645 | instruction sequences. The longer one is put in a frag_var with | |
646 | type rs_machine_dependent. We encode what to do with the frag in | |
647 | the subtype field. We encode (1) the number of existing bytes to | |
648 | replace, (2) the number of new bytes to use, (3) the offset from | |
649 | the start of the existing bytes to the first reloc we must generate | |
650 | (that is, the offset is applied from the start of the existing | |
651 | bytes after they are replaced by the new bytes, if any), (4) the | |
652 | offset from the start of the existing bytes to the second reloc, | |
653 | (5) whether a third reloc is needed (the third reloc is always four | |
654 | bytes after the second reloc), and (6) whether to warn if this | |
655 | variant is used (this is sometimes needed if .set nomacro or .set | |
656 | noat is in effect). All these numbers are reasonably small. | |
657 | ||
658 | Generating two instruction sequences must be handled carefully to | |
659 | ensure that delay slots are handled correctly. Fortunately, there | |
660 | are a limited number of cases. When the second instruction | |
661 | sequence is generated, append_insn is directed to maintain the | |
662 | existing delay slot information, so it continues to apply to any | |
663 | code after the second instruction sequence. This means that the | |
664 | second instruction sequence must not impose any requirements not | |
665 | required by the first instruction sequence. | |
666 | ||
667 | These variant frags are then handled in functions called by the | |
668 | machine independent code. md_estimate_size_before_relax returns | |
669 | the final size of the frag. md_convert_frag sets up the final form | |
670 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
671 | one if needed. */ | |
672 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
673 | ((relax_substateT) \ | |
674 | (((old) << 23) \ | |
675 | | ((new) << 16) \ | |
676 | | (((reloc1) + 64) << 9) \ | |
677 | | (((reloc2) + 64) << 2) \ | |
678 | | ((reloc3) ? (1 << 1) : 0) \ | |
679 | | ((warn) ? 1 : 0))) | |
680 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
681 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
682 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
683 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
684 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
685 | #define RELAX_WARN(i) ((i) & 1) | |
686 | ||
4a6a3df4 AO |
687 | /* Branch without likely bit. If label is out of range, we turn: |
688 | ||
689 | beq reg1, reg2, label | |
690 | delay slot | |
691 | ||
692 | into | |
693 | ||
694 | bne reg1, reg2, 0f | |
695 | nop | |
696 | j label | |
697 | 0: delay slot | |
698 | ||
699 | with the following opcode replacements: | |
700 | ||
701 | beq <-> bne | |
702 | blez <-> bgtz | |
703 | bltz <-> bgez | |
704 | bc1f <-> bc1t | |
705 | ||
706 | bltzal <-> bgezal (with jal label instead of j label) | |
707 | ||
708 | Even though keeping the delay slot instruction in the delay slot of | |
709 | the branch would be more efficient, it would be very tricky to do | |
710 | correctly, because we'd have to introduce a variable frag *after* | |
711 | the delay slot instruction, and expand that instead. Let's do it | |
712 | the easy way for now, even if the branch-not-taken case now costs | |
713 | one additional instruction. Out-of-range branches are not supposed | |
714 | to be common, anyway. | |
715 | ||
716 | Branch likely. If label is out of range, we turn: | |
717 | ||
718 | beql reg1, reg2, label | |
719 | delay slot (annulled if branch not taken) | |
720 | ||
721 | into | |
722 | ||
723 | beql reg1, reg2, 1f | |
724 | nop | |
725 | beql $0, $0, 2f | |
726 | nop | |
727 | 1: j[al] label | |
728 | delay slot (executed only if branch taken) | |
729 | 2: | |
730 | ||
731 | It would be possible to generate a shorter sequence by losing the | |
732 | likely bit, generating something like: | |
b34976b6 | 733 | |
4a6a3df4 AO |
734 | bne reg1, reg2, 0f |
735 | nop | |
736 | j[al] label | |
737 | delay slot (executed only if branch taken) | |
738 | 0: | |
739 | ||
740 | beql -> bne | |
741 | bnel -> beq | |
742 | blezl -> bgtz | |
743 | bgtzl -> blez | |
744 | bltzl -> bgez | |
745 | bgezl -> bltz | |
746 | bc1fl -> bc1t | |
747 | bc1tl -> bc1f | |
748 | ||
749 | bltzall -> bgezal (with jal label instead of j label) | |
750 | bgezall -> bltzal (ditto) | |
751 | ||
752 | ||
753 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 754 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
755 | ((relax_substateT) \ |
756 | (0xc0000000 \ | |
757 | | ((toofar) ? 1 : 0) \ | |
758 | | ((link) ? 2 : 0) \ | |
759 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 760 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 761 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
762 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
763 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
764 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 765 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 766 | |
252b5132 RH |
767 | /* For mips16 code, we use an entirely different form of relaxation. |
768 | mips16 supports two versions of most instructions which take | |
769 | immediate values: a small one which takes some small value, and a | |
770 | larger one which takes a 16 bit value. Since branches also follow | |
771 | this pattern, relaxing these values is required. | |
772 | ||
773 | We can assemble both mips16 and normal MIPS code in a single | |
774 | object. Therefore, we need to support this type of relaxation at | |
775 | the same time that we support the relaxation described above. We | |
776 | use the high bit of the subtype field to distinguish these cases. | |
777 | ||
778 | The information we store for this type of relaxation is the | |
779 | argument code found in the opcode file for this relocation, whether | |
780 | the user explicitly requested a small or extended form, and whether | |
781 | the relocation is in a jump or jal delay slot. That tells us the | |
782 | size of the value, and how it should be stored. We also store | |
783 | whether the fragment is considered to be extended or not. We also | |
784 | store whether this is known to be a branch to a different section, | |
785 | whether we have tried to relax this frag yet, and whether we have | |
786 | ever extended a PC relative fragment because of a shift count. */ | |
787 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
788 | (0x80000000 \ | |
789 | | ((type) & 0xff) \ | |
790 | | ((small) ? 0x100 : 0) \ | |
791 | | ((ext) ? 0x200 : 0) \ | |
792 | | ((dslot) ? 0x400 : 0) \ | |
793 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 794 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
795 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
796 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
797 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
798 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
799 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
800 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
801 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
802 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
803 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
804 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
805 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
806 | |
807 | /* Is the given value a sign-extended 32-bit value? */ | |
808 | #define IS_SEXT_32BIT_NUM(x) \ | |
809 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
810 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
811 | ||
812 | /* Is the given value a sign-extended 16-bit value? */ | |
813 | #define IS_SEXT_16BIT_NUM(x) \ | |
814 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
815 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
816 | ||
252b5132 RH |
817 | \f |
818 | /* Prototypes for static functions. */ | |
819 | ||
820 | #ifdef __STDC__ | |
821 | #define internalError() \ | |
822 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
823 | #else | |
824 | #define internalError() as_fatal (_("MIPS internal Error")); | |
825 | #endif | |
826 | ||
827 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
828 | ||
5919d012 RS |
829 | static inline bfd_boolean reloc_needs_lo_p |
830 | PARAMS ((bfd_reloc_code_real_type)); | |
831 | static inline bfd_boolean fixup_has_matching_lo_p | |
832 | PARAMS ((fixS *)); | |
b34976b6 AM |
833 | static int insn_uses_reg |
834 | PARAMS ((struct mips_cl_insn *ip, unsigned int reg, | |
835 | enum mips_regclass class)); | |
836 | static int reg_needs_delay | |
837 | PARAMS ((unsigned int)); | |
838 | static void mips16_mark_labels | |
839 | PARAMS ((void)); | |
840 | static void append_insn | |
841 | PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p, | |
5e0116d5 | 842 | bfd_reloc_code_real_type *r)); |
b34976b6 AM |
843 | static void mips_no_prev_insn |
844 | PARAMS ((int)); | |
845 | static void mips_emit_delays | |
846 | PARAMS ((bfd_boolean)); | |
252b5132 | 847 | #ifdef USE_STDARG |
b34976b6 AM |
848 | static void macro_build |
849 | PARAMS ((char *place, int *counter, expressionS * ep, const char *name, | |
850 | const char *fmt, ...)); | |
252b5132 RH |
851 | #else |
852 | static void macro_build (); | |
853 | #endif | |
b34976b6 AM |
854 | static void mips16_macro_build |
855 | PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list)); | |
856 | static void macro_build_jalr | |
857 | PARAMS ((int, expressionS *)); | |
858 | static void macro_build_lui | |
859 | PARAMS ((char *place, int *counter, expressionS * ep, int regnum)); | |
860 | static void macro_build_ldst_constoffset | |
861 | PARAMS ((char *place, int *counter, expressionS * ep, const char *op, | |
862 | int valreg, int breg)); | |
863 | static void set_at | |
864 | PARAMS ((int *counter, int reg, int unsignedp)); | |
865 | static void check_absolute_expr | |
866 | PARAMS ((struct mips_cl_insn * ip, expressionS *)); | |
867 | static void load_register | |
868 | PARAMS ((int *, int, expressionS *, int)); | |
869 | static void load_address | |
870 | PARAMS ((int *, int, expressionS *, int *)); | |
871 | static void move_register | |
872 | PARAMS ((int *, int, int)); | |
873 | static void macro | |
874 | PARAMS ((struct mips_cl_insn * ip)); | |
875 | static void mips16_macro | |
876 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 877 | #ifdef LOSING_COMPILER |
b34976b6 AM |
878 | static void macro2 |
879 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 880 | #endif |
b34976b6 AM |
881 | static void mips_ip |
882 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
883 | static void mips16_ip | |
884 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
885 | static void mips16_immed | |
886 | PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, | |
887 | bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *)); | |
5e0116d5 RS |
888 | static bfd_boolean parse_relocation |
889 | PARAMS ((char **, bfd_reloc_code_real_type *)); | |
890 | static size_t my_getSmallExpression | |
891 | PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *)); | |
b34976b6 AM |
892 | static void my_getExpression |
893 | PARAMS ((expressionS *, char *)); | |
ae948b86 | 894 | #ifdef OBJ_ELF |
b34976b6 AM |
895 | static int support_64bit_objects |
896 | PARAMS((void)); | |
ae948b86 | 897 | #endif |
b34976b6 AM |
898 | static void mips_set_option_string |
899 | PARAMS ((const char **, const char *)); | |
900 | static symbolS *get_symbol | |
901 | PARAMS ((void)); | |
902 | static void mips_align | |
903 | PARAMS ((int to, int fill, symbolS *label)); | |
904 | static void s_align | |
905 | PARAMS ((int)); | |
906 | static void s_change_sec | |
907 | PARAMS ((int)); | |
908 | static void s_change_section | |
909 | PARAMS ((int)); | |
910 | static void s_cons | |
911 | PARAMS ((int)); | |
912 | static void s_float_cons | |
913 | PARAMS ((int)); | |
914 | static void s_mips_globl | |
915 | PARAMS ((int)); | |
916 | static void s_option | |
917 | PARAMS ((int)); | |
918 | static void s_mipsset | |
919 | PARAMS ((int)); | |
920 | static void s_abicalls | |
921 | PARAMS ((int)); | |
922 | static void s_cpload | |
923 | PARAMS ((int)); | |
924 | static void s_cpsetup | |
925 | PARAMS ((int)); | |
926 | static void s_cplocal | |
927 | PARAMS ((int)); | |
928 | static void s_cprestore | |
929 | PARAMS ((int)); | |
930 | static void s_cpreturn | |
931 | PARAMS ((int)); | |
932 | static void s_gpvalue | |
933 | PARAMS ((int)); | |
934 | static void s_gpword | |
935 | PARAMS ((int)); | |
936 | static void s_gpdword | |
937 | PARAMS ((int)); | |
938 | static void s_cpadd | |
939 | PARAMS ((int)); | |
940 | static void s_insn | |
941 | PARAMS ((int)); | |
942 | static void md_obj_begin | |
943 | PARAMS ((void)); | |
944 | static void md_obj_end | |
945 | PARAMS ((void)); | |
946 | static long get_number | |
947 | PARAMS ((void)); | |
948 | static void s_mips_ent | |
949 | PARAMS ((int)); | |
950 | static void s_mips_end | |
951 | PARAMS ((int)); | |
952 | static void s_mips_frame | |
953 | PARAMS ((int)); | |
954 | static void s_mips_mask | |
955 | PARAMS ((int)); | |
956 | static void s_mips_stab | |
957 | PARAMS ((int)); | |
958 | static void s_mips_weakext | |
959 | PARAMS ((int)); | |
960 | static void s_mips_file | |
961 | PARAMS ((int)); | |
962 | static void s_mips_loc | |
963 | PARAMS ((int)); | |
5919d012 RS |
964 | static bfd_boolean pic_need_relax |
965 | PARAMS ((symbolS *, asection *)); | |
b34976b6 AM |
966 | static int mips16_extended_frag |
967 | PARAMS ((fragS *, asection *, long)); | |
4a6a3df4 | 968 | static int relaxed_branch_length (fragS *, asection *, int); |
b34976b6 AM |
969 | static int validate_mips_insn |
970 | PARAMS ((const struct mips_opcode *)); | |
971 | static void show | |
972 | PARAMS ((FILE *, const char *, int *, int *)); | |
add55e1f | 973 | #ifdef OBJ_ELF |
b34976b6 AM |
974 | static int mips_need_elf_addend_fixup |
975 | PARAMS ((fixS *)); | |
add55e1f | 976 | #endif |
e7af610e NC |
977 | |
978 | /* Table and functions used to map between CPU/ISA names, and | |
979 | ISA levels, and CPU numbers. */ | |
980 | ||
e972090a NC |
981 | struct mips_cpu_info |
982 | { | |
e7af610e NC |
983 | const char *name; /* CPU or ISA name. */ |
984 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
985 | int isa; /* ISA level. */ | |
986 | int cpu; /* CPU number (default CPU if ISA). */ | |
987 | }; | |
988 | ||
b34976b6 AM |
989 | static void mips_set_architecture |
990 | PARAMS ((const struct mips_cpu_info *)); | |
991 | static void mips_set_tune | |
992 | PARAMS ((const struct mips_cpu_info *)); | |
993 | static bfd_boolean mips_strict_matching_cpu_name_p | |
994 | PARAMS ((const char *, const char *)); | |
995 | static bfd_boolean mips_matching_cpu_name_p | |
996 | PARAMS ((const char *, const char *)); | |
997 | static const struct mips_cpu_info *mips_parse_cpu | |
998 | PARAMS ((const char *, const char *)); | |
999 | static const struct mips_cpu_info *mips_cpu_info_from_isa | |
1000 | PARAMS ((int)); | |
252b5132 RH |
1001 | \f |
1002 | /* Pseudo-op table. | |
1003 | ||
1004 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1005 | should be defined here, but are currently unsupported: .alias, | |
1006 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1007 | ||
1008 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1009 | specific to the type of debugging information being generated, and | |
1010 | should be defined by the object format: .aent, .begin, .bend, | |
1011 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1012 | .vreg. | |
1013 | ||
1014 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1015 | not MIPS CPU specific, but are also not specific to the object file | |
1016 | format. This file is probably the best place to define them, but | |
1017 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1018 | .struct. */ | |
1019 | ||
e972090a NC |
1020 | static const pseudo_typeS mips_pseudo_table[] = |
1021 | { | |
beae10d5 | 1022 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1023 | {"option", s_option, 0}, |
1024 | {"set", s_mipsset, 0}, | |
1025 | {"rdata", s_change_sec, 'r'}, | |
1026 | {"sdata", s_change_sec, 's'}, | |
1027 | {"livereg", s_ignore, 0}, | |
1028 | {"abicalls", s_abicalls, 0}, | |
1029 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1030 | {"cpsetup", s_cpsetup, 0}, |
1031 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1032 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1033 | {"cpreturn", s_cpreturn, 0}, |
1034 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1035 | {"gpword", s_gpword, 0}, |
10181a0d | 1036 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1037 | {"cpadd", s_cpadd, 0}, |
1038 | {"insn", s_insn, 0}, | |
1039 | ||
beae10d5 | 1040 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1041 | chips. */ |
1042 | {"asciiz", stringer, 1}, | |
1043 | {"bss", s_change_sec, 'b'}, | |
1044 | {"err", s_err, 0}, | |
1045 | {"half", s_cons, 1}, | |
1046 | {"dword", s_cons, 3}, | |
1047 | {"weakext", s_mips_weakext, 0}, | |
1048 | ||
beae10d5 | 1049 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1050 | here for one reason or another. */ |
1051 | {"align", s_align, 0}, | |
1052 | {"byte", s_cons, 0}, | |
1053 | {"data", s_change_sec, 'd'}, | |
1054 | {"double", s_float_cons, 'd'}, | |
1055 | {"float", s_float_cons, 'f'}, | |
1056 | {"globl", s_mips_globl, 0}, | |
1057 | {"global", s_mips_globl, 0}, | |
1058 | {"hword", s_cons, 1}, | |
1059 | {"int", s_cons, 2}, | |
1060 | {"long", s_cons, 2}, | |
1061 | {"octa", s_cons, 4}, | |
1062 | {"quad", s_cons, 3}, | |
cca86cc8 | 1063 | {"section", s_change_section, 0}, |
252b5132 RH |
1064 | {"short", s_cons, 1}, |
1065 | {"single", s_float_cons, 'f'}, | |
1066 | {"stabn", s_mips_stab, 'n'}, | |
1067 | {"text", s_change_sec, 't'}, | |
1068 | {"word", s_cons, 2}, | |
add56521 | 1069 | |
add56521 | 1070 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1071 | |
43841e91 | 1072 | { NULL, NULL, 0 }, |
252b5132 RH |
1073 | }; |
1074 | ||
e972090a NC |
1075 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1076 | { | |
beae10d5 KH |
1077 | /* These pseudo-ops should be defined by the object file format. |
1078 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1079 | {"aent", s_mips_ent, 1}, |
1080 | {"bgnb", s_ignore, 0}, | |
1081 | {"end", s_mips_end, 0}, | |
1082 | {"endb", s_ignore, 0}, | |
1083 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1084 | {"file", s_mips_file, 0}, |
252b5132 RH |
1085 | {"fmask", s_mips_mask, 'F'}, |
1086 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1087 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1088 | {"mask", s_mips_mask, 'R'}, |
1089 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1090 | { NULL, NULL, 0 }, |
252b5132 RH |
1091 | }; |
1092 | ||
1093 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
1094 | ||
1095 | void | |
1096 | mips_pop_insert () | |
1097 | { | |
1098 | pop_insert (mips_pseudo_table); | |
1099 | if (! ECOFF_DEBUGGING) | |
1100 | pop_insert (mips_nonecoff_pseudo_table); | |
1101 | } | |
1102 | \f | |
1103 | /* Symbols labelling the current insn. */ | |
1104 | ||
e972090a NC |
1105 | struct insn_label_list |
1106 | { | |
252b5132 RH |
1107 | struct insn_label_list *next; |
1108 | symbolS *label; | |
1109 | }; | |
1110 | ||
1111 | static struct insn_label_list *insn_labels; | |
1112 | static struct insn_label_list *free_insn_labels; | |
1113 | ||
1114 | static void mips_clear_insn_labels PARAMS ((void)); | |
1115 | ||
1116 | static inline void | |
1117 | mips_clear_insn_labels () | |
1118 | { | |
1119 | register struct insn_label_list **pl; | |
1120 | ||
1121 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1122 | ; | |
1123 | *pl = insn_labels; | |
1124 | insn_labels = NULL; | |
1125 | } | |
1126 | \f | |
1127 | static char *expr_end; | |
1128 | ||
1129 | /* Expressions which appear in instructions. These are set by | |
1130 | mips_ip. */ | |
1131 | ||
1132 | static expressionS imm_expr; | |
1133 | static expressionS offset_expr; | |
1134 | ||
1135 | /* Relocs associated with imm_expr and offset_expr. */ | |
1136 | ||
f6688943 TS |
1137 | static bfd_reloc_code_real_type imm_reloc[3] |
1138 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1139 | static bfd_reloc_code_real_type offset_reloc[3] | |
1140 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1141 | |
252b5132 RH |
1142 | /* These are set by mips16_ip if an explicit extension is used. */ |
1143 | ||
b34976b6 | 1144 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1145 | |
7ed4a06a | 1146 | #ifdef OBJ_ELF |
ecb4347a DJ |
1147 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1148 | ECOFF debugging. */ | |
252b5132 RH |
1149 | |
1150 | static segT pdr_seg; | |
7ed4a06a | 1151 | #endif |
252b5132 | 1152 | |
e013f690 TS |
1153 | /* The default target format to use. */ |
1154 | ||
1155 | const char * | |
1156 | mips_target_format () | |
1157 | { | |
1158 | switch (OUTPUT_FLAVOR) | |
1159 | { | |
1160 | case bfd_target_aout_flavour: | |
1161 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1162 | case bfd_target_ecoff_flavour: | |
1163 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1164 | case bfd_target_coff_flavour: | |
1165 | return "pe-mips"; | |
1166 | case bfd_target_elf_flavour: | |
1167 | #ifdef TE_TMIPS | |
cfe86eaa | 1168 | /* This is traditional mips. */ |
e013f690 | 1169 | return (target_big_endian |
cfe86eaa TS |
1170 | ? (HAVE_64BIT_OBJECTS |
1171 | ? "elf64-tradbigmips" | |
1172 | : (HAVE_NEWABI | |
1173 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1174 | : (HAVE_64BIT_OBJECTS | |
1175 | ? "elf64-tradlittlemips" | |
1176 | : (HAVE_NEWABI | |
1177 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1178 | #else |
1179 | return (target_big_endian | |
cfe86eaa TS |
1180 | ? (HAVE_64BIT_OBJECTS |
1181 | ? "elf64-bigmips" | |
1182 | : (HAVE_NEWABI | |
1183 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1184 | : (HAVE_64BIT_OBJECTS | |
1185 | ? "elf64-littlemips" | |
1186 | : (HAVE_NEWABI | |
1187 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1188 | #endif |
1189 | default: | |
1190 | abort (); | |
1191 | return NULL; | |
1192 | } | |
1193 | } | |
1194 | ||
156c2f8b NC |
1195 | /* This function is called once, at assembler startup time. It should |
1196 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1197 | ||
252b5132 RH |
1198 | void |
1199 | md_begin () | |
1200 | { | |
252b5132 | 1201 | register const char *retval = NULL; |
156c2f8b | 1202 | int i = 0; |
252b5132 | 1203 | int broken = 0; |
1f25f5d3 | 1204 | |
ec68c924 | 1205 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1206 | as_warn (_("Could not set architecture and machine")); |
1207 | ||
252b5132 RH |
1208 | op_hash = hash_new (); |
1209 | ||
1210 | for (i = 0; i < NUMOPCODES;) | |
1211 | { | |
1212 | const char *name = mips_opcodes[i].name; | |
1213 | ||
1214 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1215 | if (retval != NULL) | |
1216 | { | |
1217 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1218 | mips_opcodes[i].name, retval); | |
1219 | /* Probably a memory allocation problem? Give up now. */ | |
1220 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1221 | } | |
1222 | do | |
1223 | { | |
1224 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1225 | { | |
1226 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1227 | broken = 1; | |
1228 | } | |
1229 | ++i; | |
1230 | } | |
1231 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1232 | } | |
1233 | ||
1234 | mips16_op_hash = hash_new (); | |
1235 | ||
1236 | i = 0; | |
1237 | while (i < bfd_mips16_num_opcodes) | |
1238 | { | |
1239 | const char *name = mips16_opcodes[i].name; | |
1240 | ||
1241 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1242 | if (retval != NULL) | |
1243 | as_fatal (_("internal: can't hash `%s': %s"), | |
1244 | mips16_opcodes[i].name, retval); | |
1245 | do | |
1246 | { | |
1247 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1248 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1249 | != mips16_opcodes[i].match)) | |
1250 | { | |
1251 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1252 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1253 | broken = 1; | |
1254 | } | |
1255 | ++i; | |
1256 | } | |
1257 | while (i < bfd_mips16_num_opcodes | |
1258 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1259 | } | |
1260 | ||
1261 | if (broken) | |
1262 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1263 | ||
1264 | /* We add all the general register names to the symbol table. This | |
1265 | helps us detect invalid uses of them. */ | |
1266 | for (i = 0; i < 32; i++) | |
1267 | { | |
1268 | char buf[5]; | |
1269 | ||
1270 | sprintf (buf, "$%d", i); | |
1271 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1272 | &zero_address_frag)); | |
1273 | } | |
76db943d TS |
1274 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1275 | &zero_address_frag)); | |
252b5132 RH |
1276 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1277 | &zero_address_frag)); | |
1278 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1279 | &zero_address_frag)); | |
1280 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1281 | &zero_address_frag)); | |
1282 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1283 | &zero_address_frag)); | |
1284 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1285 | &zero_address_frag)); | |
1286 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1287 | &zero_address_frag)); | |
85b51719 TS |
1288 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1289 | &zero_address_frag)); | |
252b5132 RH |
1290 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1291 | &zero_address_frag)); | |
1292 | ||
6047c971 AO |
1293 | /* If we don't add these register names to the symbol table, they |
1294 | may end up being added as regular symbols by operand(), and then | |
1295 | make it to the object file as undefined in case they're not | |
1296 | regarded as local symbols. They're local in o32, since `$' is a | |
1297 | local symbol prefix, but not in n32 or n64. */ | |
1298 | for (i = 0; i < 8; i++) | |
1299 | { | |
1300 | char buf[6]; | |
1301 | ||
1302 | sprintf (buf, "$fcc%i", i); | |
1303 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1304 | &zero_address_frag)); | |
1305 | } | |
1306 | ||
b34976b6 | 1307 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1308 | |
1309 | mips_gprmask = 0; | |
1310 | mips_cprmask[0] = 0; | |
1311 | mips_cprmask[1] = 0; | |
1312 | mips_cprmask[2] = 0; | |
1313 | mips_cprmask[3] = 0; | |
1314 | ||
1315 | /* set the default alignment for the text section (2**2) */ | |
1316 | record_alignment (text_section, 2); | |
1317 | ||
1318 | if (USE_GLOBAL_POINTER_OPT) | |
1319 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1320 | ||
1321 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1322 | { | |
1323 | /* On a native system, sections must be aligned to 16 byte | |
1324 | boundaries. When configured for an embedded ELF target, we | |
1325 | don't bother. */ | |
1326 | if (strcmp (TARGET_OS, "elf") != 0) | |
1327 | { | |
1328 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1329 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1330 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1331 | } | |
1332 | ||
1333 | /* Create a .reginfo section for register masks and a .mdebug | |
1334 | section for debugging information. */ | |
1335 | { | |
1336 | segT seg; | |
1337 | subsegT subseg; | |
1338 | flagword flags; | |
1339 | segT sec; | |
1340 | ||
1341 | seg = now_seg; | |
1342 | subseg = now_subseg; | |
1343 | ||
1344 | /* The ABI says this section should be loaded so that the | |
1345 | running program can access it. However, we don't load it | |
1346 | if we are configured for an embedded target */ | |
1347 | flags = SEC_READONLY | SEC_DATA; | |
1348 | if (strcmp (TARGET_OS, "elf") != 0) | |
1349 | flags |= SEC_ALLOC | SEC_LOAD; | |
1350 | ||
316f5878 | 1351 | if (mips_abi != N64_ABI) |
252b5132 RH |
1352 | { |
1353 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1354 | ||
195325d2 TS |
1355 | bfd_set_section_flags (stdoutput, sec, flags); |
1356 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1357 | |
252b5132 RH |
1358 | #ifdef OBJ_ELF |
1359 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1360 | #endif | |
1361 | } | |
1362 | else | |
1363 | { | |
1364 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1365 | .reginfo section. */ | |
1366 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1367 | bfd_set_section_flags (stdoutput, sec, flags); |
1368 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1369 | |
1370 | #ifdef OBJ_ELF | |
1371 | /* Set up the option header. */ | |
1372 | { | |
1373 | Elf_Internal_Options opthdr; | |
1374 | char *f; | |
1375 | ||
1376 | opthdr.kind = ODK_REGINFO; | |
1377 | opthdr.size = (sizeof (Elf_External_Options) | |
1378 | + sizeof (Elf64_External_RegInfo)); | |
1379 | opthdr.section = 0; | |
1380 | opthdr.info = 0; | |
1381 | f = frag_more (sizeof (Elf_External_Options)); | |
1382 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1383 | (Elf_External_Options *) f); | |
1384 | ||
1385 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1386 | } | |
1387 | #endif | |
1388 | } | |
1389 | ||
1390 | if (ECOFF_DEBUGGING) | |
1391 | { | |
1392 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1393 | (void) bfd_set_section_flags (stdoutput, sec, | |
1394 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1395 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1396 | } | |
ecb4347a DJ |
1397 | #ifdef OBJ_ELF |
1398 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1399 | { | |
1400 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1401 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1402 | SEC_READONLY | SEC_RELOC | |
1403 | | SEC_DEBUGGING); | |
1404 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1405 | } | |
252b5132 RH |
1406 | #endif |
1407 | ||
1408 | subseg_set (seg, subseg); | |
1409 | } | |
1410 | } | |
1411 | ||
1412 | if (! ECOFF_DEBUGGING) | |
1413 | md_obj_begin (); | |
1414 | } | |
1415 | ||
1416 | void | |
1417 | md_mips_end () | |
1418 | { | |
1419 | if (! ECOFF_DEBUGGING) | |
1420 | md_obj_end (); | |
1421 | } | |
1422 | ||
1423 | void | |
1424 | md_assemble (str) | |
1425 | char *str; | |
1426 | { | |
1427 | struct mips_cl_insn insn; | |
f6688943 TS |
1428 | bfd_reloc_code_real_type unused_reloc[3] |
1429 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1430 | |
1431 | imm_expr.X_op = O_absent; | |
252b5132 | 1432 | offset_expr.X_op = O_absent; |
f6688943 TS |
1433 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1434 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1435 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1436 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1437 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1438 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1439 | |
1440 | if (mips_opts.mips16) | |
1441 | mips16_ip (str, &insn); | |
1442 | else | |
1443 | { | |
1444 | mips_ip (str, &insn); | |
beae10d5 KH |
1445 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1446 | str, insn.insn_opcode)); | |
252b5132 RH |
1447 | } |
1448 | ||
1449 | if (insn_error) | |
1450 | { | |
1451 | as_bad ("%s `%s'", insn_error, str); | |
1452 | return; | |
1453 | } | |
1454 | ||
1455 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1456 | { | |
1457 | if (mips_opts.mips16) | |
1458 | mips16_macro (&insn); | |
1459 | else | |
1460 | macro (&insn); | |
1461 | } | |
1462 | else | |
1463 | { | |
1464 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1465 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1466 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1467 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1468 | else |
5e0116d5 | 1469 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1470 | } |
1471 | } | |
1472 | ||
5919d012 RS |
1473 | /* Return true if the given relocation might need a matching %lo(). |
1474 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1475 | applied to local symbols. */ | |
1476 | ||
1477 | static inline bfd_boolean | |
1478 | reloc_needs_lo_p (reloc) | |
1479 | bfd_reloc_code_real_type reloc; | |
1480 | { | |
1481 | return (reloc == BFD_RELOC_HI16_S | |
1482 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1483 | } | |
1484 | ||
1485 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1486 | relocation. */ | |
1487 | ||
1488 | static inline bfd_boolean | |
1489 | fixup_has_matching_lo_p (fixp) | |
1490 | fixS *fixp; | |
1491 | { | |
1492 | return (fixp->fx_next != NULL | |
1493 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1494 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1495 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1496 | } | |
1497 | ||
252b5132 RH |
1498 | /* See whether instruction IP reads register REG. CLASS is the type |
1499 | of register. */ | |
1500 | ||
1501 | static int | |
1502 | insn_uses_reg (ip, reg, class) | |
1503 | struct mips_cl_insn *ip; | |
1504 | unsigned int reg; | |
1505 | enum mips_regclass class; | |
1506 | { | |
1507 | if (class == MIPS16_REG) | |
1508 | { | |
1509 | assert (mips_opts.mips16); | |
1510 | reg = mips16_to_32_reg_map[reg]; | |
1511 | class = MIPS_GR_REG; | |
1512 | } | |
1513 | ||
85b51719 TS |
1514 | /* Don't report on general register ZERO, since it never changes. */ |
1515 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1516 | return 0; |
1517 | ||
1518 | if (class == MIPS_FP_REG) | |
1519 | { | |
1520 | assert (! mips_opts.mips16); | |
1521 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1522 | This is not optimal, because it will introduce an unnecessary | |
1523 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1524 | need to distinguish reading both $f0 and $f1 or just one of | |
1525 | them. Note that we don't have to check the other way, | |
1526 | because there is no instruction that sets both $f0 and $f1 | |
1527 | and requires a delay. */ | |
1528 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1529 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1530 | == (reg &~ (unsigned) 1))) | |
1531 | return 1; | |
1532 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1533 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1534 | == (reg &~ (unsigned) 1))) | |
1535 | return 1; | |
1536 | } | |
1537 | else if (! mips_opts.mips16) | |
1538 | { | |
1539 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1540 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1541 | return 1; | |
1542 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1543 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1544 | return 1; | |
1545 | } | |
1546 | else | |
1547 | { | |
1548 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1549 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1550 | & MIPS16OP_MASK_RX)] | |
1551 | == reg)) | |
1552 | return 1; | |
1553 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1554 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1555 | & MIPS16OP_MASK_RY)] | |
1556 | == reg)) | |
1557 | return 1; | |
1558 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1559 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1560 | & MIPS16OP_MASK_MOVE32Z)] | |
1561 | == reg)) | |
1562 | return 1; | |
1563 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1564 | return 1; | |
1565 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1566 | return 1; | |
1567 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1568 | return 1; | |
1569 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1570 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1571 | & MIPS16OP_MASK_REGR32) == reg) | |
1572 | return 1; | |
1573 | } | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
1578 | /* This function returns true if modifying a register requires a | |
1579 | delay. */ | |
1580 | ||
1581 | static int | |
1582 | reg_needs_delay (reg) | |
156c2f8b | 1583 | unsigned int reg; |
252b5132 RH |
1584 | { |
1585 | unsigned long prev_pinfo; | |
1586 | ||
1587 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1588 | if (! mips_opts.noreorder | |
9ce8a5dd | 1589 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1590 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1591 | || (! gpr_interlocks | |
1592 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1593 | { | |
1594 | /* A load from a coprocessor or from memory. All load | |
1595 | delays delay the use of general register rt for one | |
1596 | instruction on the r3000. The r6000 and r4000 use | |
1597 | interlocks. */ | |
bdaaa2e1 | 1598 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1599 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1600 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1601 | return 1; | |
1602 | } | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1608 | handle them specially, such as generating jalx instructions when | |
1609 | needed. We also make them odd for the duration of the assembly, in | |
1610 | order to generate the right sort of code. We will make them even | |
1611 | in the adjust_symtab routine, while leaving them marked. This is | |
1612 | convenient for the debugger and the disassembler. The linker knows | |
1613 | to make them odd again. */ | |
1614 | ||
1615 | static void | |
1616 | mips16_mark_labels () | |
1617 | { | |
1618 | if (mips_opts.mips16) | |
1619 | { | |
1620 | struct insn_label_list *l; | |
98aa84af | 1621 | valueT val; |
252b5132 RH |
1622 | |
1623 | for (l = insn_labels; l != NULL; l = l->next) | |
1624 | { | |
1625 | #ifdef OBJ_ELF | |
1626 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1627 | S_SET_OTHER (l->label, STO_MIPS16); | |
1628 | #endif | |
98aa84af AM |
1629 | val = S_GET_VALUE (l->label); |
1630 | if ((val & 1) == 0) | |
1631 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1632 | } |
1633 | } | |
1634 | } | |
1635 | ||
1636 | /* Output an instruction. PLACE is where to put the instruction; if | |
1637 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1638 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1639 | used with RELOC_TYPE. */ | |
1640 | ||
1641 | static void | |
5e0116d5 | 1642 | append_insn (place, ip, address_expr, reloc_type) |
252b5132 RH |
1643 | char *place; |
1644 | struct mips_cl_insn *ip; | |
1645 | expressionS *address_expr; | |
f6688943 | 1646 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1647 | { |
1648 | register unsigned long prev_pinfo, pinfo; | |
1649 | char *f; | |
f6688943 | 1650 | fixS *fixp[3]; |
252b5132 | 1651 | int nops = 0; |
f5040a92 | 1652 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1653 | |
1654 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1655 | mips16_mark_labels (); |
252b5132 RH |
1656 | |
1657 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1658 | pinfo = ip->insn_mo->pinfo; | |
1659 | ||
1660 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1661 | { | |
1662 | int prev_prev_nop; | |
1663 | ||
1664 | /* If the previous insn required any delay slots, see if we need | |
1665 | to insert a NOP or two. There are eight kinds of possible | |
1666 | hazards, of which an instruction can have at most one type. | |
1667 | (1) a load from memory delay | |
1668 | (2) a load from a coprocessor delay | |
1669 | (3) an unconditional branch delay | |
1670 | (4) a conditional branch delay | |
1671 | (5) a move to coprocessor register delay | |
1672 | (6) a load coprocessor register from memory delay | |
1673 | (7) a coprocessor condition code delay | |
1674 | (8) a HI/LO special register delay | |
1675 | ||
1676 | There are a lot of optimizations we could do that we don't. | |
1677 | In particular, we do not, in general, reorder instructions. | |
1678 | If you use gcc with optimization, it will reorder | |
1679 | instructions and generally do much more optimization then we | |
1680 | do here; repeating all that work in the assembler would only | |
1681 | benefit hand written assembly code, and does not seem worth | |
1682 | it. */ | |
1683 | ||
1684 | /* This is how a NOP is emitted. */ | |
1685 | #define emit_nop() \ | |
1686 | (mips_opts.mips16 \ | |
1687 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1688 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1689 | ||
1690 | /* The previous insn might require a delay slot, depending upon | |
1691 | the contents of the current insn. */ | |
1692 | if (! mips_opts.mips16 | |
9ce8a5dd | 1693 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1694 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1695 | && ! cop_interlocks) | |
1696 | || (! gpr_interlocks | |
1697 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1698 | { | |
1699 | /* A load from a coprocessor or from memory. All load | |
1700 | delays delay the use of general register rt for one | |
1701 | instruction on the r3000. The r6000 and r4000 use | |
1702 | interlocks. */ | |
beae10d5 | 1703 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1704 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1705 | if (mips_optimize == 0 | |
1706 | || insn_uses_reg (ip, | |
1707 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1708 | & OP_MASK_RT), | |
1709 | MIPS_GR_REG)) | |
1710 | ++nops; | |
1711 | } | |
1712 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1713 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1714 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1715 | && ! cop_interlocks) |
e7af610e | 1716 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1717 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1718 | { | |
1719 | /* A generic coprocessor delay. The previous instruction | |
1720 | modified a coprocessor general or control register. If | |
1721 | it modified a control register, we need to avoid any | |
1722 | coprocessor instruction (this is probably not always | |
1723 | required, but it sometimes is). If it modified a general | |
1724 | register, we avoid using that register. | |
1725 | ||
1726 | On the r6000 and r4000 loading a coprocessor register | |
1727 | from memory is interlocked, and does not require a delay. | |
1728 | ||
1729 | This case is not handled very well. There is no special | |
1730 | knowledge of CP0 handling, and the coprocessors other | |
1731 | than the floating point unit are not distinguished at | |
1732 | all. */ | |
1733 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1734 | Need to modify this to include knowledge about |
252b5132 RH |
1735 | user specified delays! */ |
1736 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1737 | { | |
1738 | if (mips_optimize == 0 | |
1739 | || insn_uses_reg (ip, | |
1740 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1741 | & OP_MASK_FT), | |
1742 | MIPS_FP_REG)) | |
1743 | ++nops; | |
1744 | } | |
1745 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1746 | { | |
1747 | if (mips_optimize == 0 | |
1748 | || insn_uses_reg (ip, | |
1749 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1750 | & OP_MASK_FS), | |
1751 | MIPS_FP_REG)) | |
1752 | ++nops; | |
1753 | } | |
1754 | else | |
1755 | { | |
1756 | /* We don't know exactly what the previous instruction | |
1757 | does. If the current instruction uses a coprocessor | |
1758 | register, we must insert a NOP. If previous | |
1759 | instruction may set the condition codes, and the | |
1760 | current instruction uses them, we must insert two | |
1761 | NOPS. */ | |
bdaaa2e1 | 1762 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1763 | if (mips_optimize == 0 |
1764 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1765 | && (pinfo & INSN_READ_COND_CODE))) | |
1766 | nops += 2; | |
1767 | else if (pinfo & INSN_COP) | |
1768 | ++nops; | |
1769 | } | |
1770 | } | |
1771 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1772 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1773 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1774 | && ! cop_interlocks) | |
1775 | { | |
1776 | /* The previous instruction sets the coprocessor condition | |
1777 | codes, but does not require a general coprocessor delay | |
1778 | (this means it is a floating point comparison | |
1779 | instruction). If this instruction uses the condition | |
1780 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1781 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1782 | if (mips_optimize == 0 |
1783 | || (pinfo & INSN_READ_COND_CODE)) | |
1784 | ++nops; | |
1785 | } | |
6b76fefe CM |
1786 | |
1787 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1788 | previous insn was an mfhi/mflo and the current insn | |
1789 | reads the register that the mfhi/mflo wrote to, then | |
1790 | insert two nops. */ | |
1791 | ||
1792 | else if (mips_7000_hilo_fix | |
1793 | && MF_HILO_INSN (prev_pinfo) | |
1794 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1795 | & OP_MASK_RD), |
1796 | MIPS_GR_REG)) | |
6b76fefe CM |
1797 | { |
1798 | nops += 2; | |
1799 | } | |
1800 | ||
1801 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1802 | 2nd previous insn was an mfhi/mflo and the current insn | |
1803 | reads the register that the mfhi/mflo wrote to, then | |
1804 | insert one nop. */ | |
1805 | ||
1806 | else if (mips_7000_hilo_fix | |
1807 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1808 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1809 | & OP_MASK_RD), | |
1810 | MIPS_GR_REG)) | |
bdaaa2e1 | 1811 | |
6b76fefe | 1812 | { |
f9419b05 | 1813 | ++nops; |
6b76fefe | 1814 | } |
bdaaa2e1 | 1815 | |
252b5132 RH |
1816 | else if (prev_pinfo & INSN_READ_LO) |
1817 | { | |
1818 | /* The previous instruction reads the LO register; if the | |
1819 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1820 | insert two NOPS. Some newer processors have interlocks. |
1821 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1822 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1823 | though the tx39's divide insns still do require the |
1824 | delay. */ | |
252b5132 | 1825 | if (! (hilo_interlocks |
ec68c924 | 1826 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1827 | && (mips_optimize == 0 |
1828 | || (pinfo & INSN_WRITE_LO))) | |
1829 | nops += 2; | |
1830 | /* Most mips16 branch insns don't have a delay slot. | |
1831 | If a read from LO is immediately followed by a branch | |
1832 | to a write to LO we have a read followed by a write | |
1833 | less than 2 insns away. We assume the target of | |
1834 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1835 | between a read and an immediately following branch. */ |
252b5132 RH |
1836 | else if (mips_opts.mips16 |
1837 | && (mips_optimize == 0 | |
1838 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1839 | ++nops; |
252b5132 RH |
1840 | } |
1841 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1842 | { | |
1843 | /* The previous instruction reads the HI register; if the | |
1844 | current instruction writes to the HI register, we must | |
1845 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1846 | Also the note tx39's multiply above. */ |
252b5132 | 1847 | if (! (hilo_interlocks |
ec68c924 | 1848 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1849 | && (mips_optimize == 0 |
1850 | || (pinfo & INSN_WRITE_HI))) | |
1851 | nops += 2; | |
1852 | /* Most mips16 branch insns don't have a delay slot. | |
1853 | If a read from HI is immediately followed by a branch | |
1854 | to a write to HI we have a read followed by a write | |
1855 | less than 2 insns away. We assume the target of | |
1856 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1857 | between a read and an immediately following branch. */ |
252b5132 RH |
1858 | else if (mips_opts.mips16 |
1859 | && (mips_optimize == 0 | |
1860 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1861 | ++nops; |
252b5132 RH |
1862 | } |
1863 | ||
1864 | /* If the previous instruction was in a noreorder section, then | |
1865 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1866 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1867 | if (prev_insn_unreordered) |
1868 | nops = 0; | |
1869 | ||
1870 | /* There are two cases which require two intervening | |
1871 | instructions: 1) setting the condition codes using a move to | |
1872 | coprocessor instruction which requires a general coprocessor | |
1873 | delay and then reading the condition codes 2) reading the HI | |
1874 | or LO register and then writing to it (except on processors | |
1875 | which have interlocks). If we are not already emitting a NOP | |
1876 | instruction, we must check for these cases compared to the | |
1877 | instruction previous to the previous instruction. */ | |
1878 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1879 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1880 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1881 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1882 | && (pinfo & INSN_READ_COND_CODE) | |
1883 | && ! cop_interlocks) | |
1884 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1885 | && (pinfo & INSN_WRITE_LO) | |
1886 | && ! (hilo_interlocks | |
ec68c924 | 1887 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1888 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1889 | && (pinfo & INSN_WRITE_HI) | |
1890 | && ! (hilo_interlocks | |
ec68c924 | 1891 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1892 | prev_prev_nop = 1; |
1893 | else | |
1894 | prev_prev_nop = 0; | |
1895 | ||
1896 | if (prev_prev_insn_unreordered) | |
1897 | prev_prev_nop = 0; | |
1898 | ||
1899 | if (prev_prev_nop && nops == 0) | |
1900 | ++nops; | |
1901 | ||
60b63b72 RS |
1902 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1903 | { | |
1904 | /* We're out of bits in pinfo, so we must resort to string | |
1905 | ops here. Shortcuts are selected based on opcodes being | |
1906 | limited to the VR4122 instruction set. */ | |
1907 | int min_nops = 0; | |
1908 | const char *pn = prev_insn.insn_mo->name; | |
1909 | const char *tn = ip->insn_mo->name; | |
1910 | if (strncmp(pn, "macc", 4) == 0 | |
1911 | || strncmp(pn, "dmacc", 5) == 0) | |
1912 | { | |
1913 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1914 | if (strstr (tn, "div")) | |
1915 | { | |
1916 | min_nops = 1; | |
1917 | } | |
1918 | ||
1919 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1920 | if (pn[0] == 'd' /* dmacc */ | |
1921 | && (strncmp(tn, "dmult", 5) == 0 | |
1922 | || strncmp(tn, "dmacc", 5) == 0)) | |
1923 | { | |
1924 | min_nops = 1; | |
1925 | } | |
1926 | ||
1927 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1928 | if (strcmp (tn, "mtlo") == 0 | |
1929 | || strcmp (tn, "mthi") == 0) | |
1930 | { | |
1931 | min_nops = 1; | |
1932 | } | |
1933 | ||
1934 | } | |
1935 | else if (strncmp(pn, "dmult", 5) == 0 | |
1936 | && (strncmp(tn, "dmult", 5) == 0 | |
1937 | || strncmp(tn, "dmacc", 5) == 0)) | |
1938 | { | |
1939 | /* Here is the rest of errata 23. */ | |
1940 | min_nops = 1; | |
1941 | } | |
1942 | if (nops < min_nops) | |
1943 | nops = min_nops; | |
1944 | } | |
1945 | ||
252b5132 RH |
1946 | /* If we are being given a nop instruction, don't bother with |
1947 | one of the nops we would otherwise output. This will only | |
1948 | happen when a nop instruction is used with mips_optimize set | |
1949 | to 0. */ | |
1950 | if (nops > 0 | |
1951 | && ! mips_opts.noreorder | |
156c2f8b | 1952 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1953 | --nops; |
1954 | ||
1955 | /* Now emit the right number of NOP instructions. */ | |
1956 | if (nops > 0 && ! mips_opts.noreorder) | |
1957 | { | |
1958 | fragS *old_frag; | |
1959 | unsigned long old_frag_offset; | |
1960 | int i; | |
1961 | struct insn_label_list *l; | |
1962 | ||
1963 | old_frag = frag_now; | |
1964 | old_frag_offset = frag_now_fix (); | |
1965 | ||
1966 | for (i = 0; i < nops; i++) | |
1967 | emit_nop (); | |
1968 | ||
1969 | if (listing) | |
1970 | { | |
1971 | listing_prev_line (); | |
1972 | /* We may be at the start of a variant frag. In case we | |
1973 | are, make sure there is enough space for the frag | |
1974 | after the frags created by listing_prev_line. The | |
1975 | argument to frag_grow here must be at least as large | |
1976 | as the argument to all other calls to frag_grow in | |
1977 | this file. We don't have to worry about being in the | |
1978 | middle of a variant frag, because the variants insert | |
1979 | all needed nop instructions themselves. */ | |
1980 | frag_grow (40); | |
1981 | } | |
1982 | ||
1983 | for (l = insn_labels; l != NULL; l = l->next) | |
1984 | { | |
98aa84af AM |
1985 | valueT val; |
1986 | ||
252b5132 | 1987 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1988 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1989 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1990 | /* mips16 text labels are stored as odd. */ |
1991 | if (mips_opts.mips16) | |
f9419b05 | 1992 | ++val; |
98aa84af | 1993 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1994 | } |
1995 | ||
1996 | #ifndef NO_ECOFF_DEBUGGING | |
1997 | if (ECOFF_DEBUGGING) | |
1998 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1999 | #endif | |
2000 | } | |
2001 | else if (prev_nop_frag != NULL) | |
2002 | { | |
2003 | /* We have a frag holding nops we may be able to remove. If | |
2004 | we don't need any nops, we can decrease the size of | |
2005 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 2006 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
2007 | if (prev_nop_frag_since == 0) |
2008 | { | |
2009 | if (nops == 0) | |
2010 | { | |
2011 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2012 | --prev_nop_frag_holds; | |
2013 | } | |
2014 | else | |
2015 | prev_nop_frag_required += nops; | |
2016 | } | |
2017 | else | |
2018 | { | |
2019 | if (prev_prev_nop == 0) | |
2020 | { | |
2021 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2022 | --prev_nop_frag_holds; | |
2023 | } | |
2024 | else | |
2025 | ++prev_nop_frag_required; | |
2026 | } | |
2027 | ||
2028 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2029 | prev_nop_frag = NULL; | |
2030 | ||
2031 | ++prev_nop_frag_since; | |
2032 | ||
2033 | /* Sanity check: by the time we reach the second instruction | |
2034 | after prev_nop_frag, we should have used up all the nops | |
2035 | one way or another. */ | |
2036 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2037 | } | |
2038 | } | |
2039 | ||
4a6a3df4 AO |
2040 | if (place == NULL |
2041 | && address_expr | |
0b25d3e6 | 2042 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2043 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2044 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2045 | && mips_relax_branch | |
2046 | /* Don't try branch relaxation within .set nomacro, or within | |
2047 | .set noat if we use $at for PIC computations. If it turns | |
2048 | out that the branch was out-of-range, we'll get an error. */ | |
2049 | && !mips_opts.warn_about_macros | |
2050 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2051 | && !mips_opts.mips16) | |
2052 | { | |
2053 | f = frag_var (rs_machine_dependent, | |
2054 | relaxed_branch_length | |
2055 | (NULL, NULL, | |
2056 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2057 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2058 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2059 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2060 | pinfo & INSN_COND_BRANCH_LIKELY, |
2061 | pinfo & INSN_WRITE_GPR_31, | |
2062 | 0), | |
2063 | address_expr->X_add_symbol, | |
2064 | address_expr->X_add_number, | |
2065 | 0); | |
2066 | *reloc_type = BFD_RELOC_UNUSED; | |
2067 | } | |
2068 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2069 | { |
2070 | /* We need to set up a variant frag. */ | |
2071 | assert (mips_opts.mips16 && address_expr != NULL); | |
2072 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2073 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2074 | mips16_small, mips16_ext, |
2075 | (prev_pinfo | |
2076 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2077 | (*prev_insn_reloc_type |
252b5132 | 2078 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2079 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2080 | } |
2081 | else if (place != NULL) | |
2082 | f = place; | |
2083 | else if (mips_opts.mips16 | |
2084 | && ! ip->use_extend | |
f6688943 | 2085 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2086 | { |
2087 | /* Make sure there is enough room to swap this instruction with | |
2088 | a following jump instruction. */ | |
2089 | frag_grow (6); | |
2090 | f = frag_more (2); | |
2091 | } | |
2092 | else | |
2093 | { | |
2094 | if (mips_opts.mips16 | |
2095 | && mips_opts.noreorder | |
2096 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2097 | as_warn (_("extended instruction in delay slot")); | |
2098 | ||
2099 | f = frag_more (4); | |
2100 | } | |
2101 | ||
f6688943 TS |
2102 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2103 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2104 | { |
2105 | if (address_expr->X_op == O_constant) | |
2106 | { | |
4db1a35d | 2107 | valueT tmp; |
f6688943 TS |
2108 | |
2109 | switch (*reloc_type) | |
252b5132 RH |
2110 | { |
2111 | case BFD_RELOC_32: | |
2112 | ip->insn_opcode |= address_expr->X_add_number; | |
2113 | break; | |
2114 | ||
f6688943 TS |
2115 | case BFD_RELOC_MIPS_HIGHEST: |
2116 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2117 | tmp >>= 16; | |
2118 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2119 | break; | |
2120 | ||
2121 | case BFD_RELOC_MIPS_HIGHER: | |
2122 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2123 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2124 | break; | |
2125 | ||
2126 | case BFD_RELOC_HI16_S: | |
2127 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2128 | >> 16) & 0xffff; | |
2129 | break; | |
2130 | ||
2131 | case BFD_RELOC_HI16: | |
2132 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2133 | break; | |
2134 | ||
252b5132 | 2135 | case BFD_RELOC_LO16: |
ed6fb7bd | 2136 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2137 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2138 | break; | |
2139 | ||
2140 | case BFD_RELOC_MIPS_JMP: | |
2141 | if ((address_expr->X_add_number & 3) != 0) | |
2142 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2143 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2144 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2145 | as_bad (_("jump address range overflow (0x%lx)"), |
2146 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2147 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2148 | break; | |
2149 | ||
2150 | case BFD_RELOC_MIPS16_JMP: | |
2151 | if ((address_expr->X_add_number & 3) != 0) | |
2152 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2153 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2154 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2155 | as_bad (_("jump address range overflow (0x%lx)"), |
2156 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2157 | ip->insn_opcode |= |
2158 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2159 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2160 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2161 | break; | |
2162 | ||
252b5132 RH |
2163 | case BFD_RELOC_16_PCREL_S2: |
2164 | goto need_reloc; | |
2165 | ||
2166 | default: | |
2167 | internalError (); | |
2168 | } | |
2169 | } | |
2170 | else | |
2171 | { | |
2172 | need_reloc: | |
f6688943 | 2173 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2174 | if (place == NULL) |
2175 | { | |
34ce925e RS |
2176 | reloc_howto_type *howto; |
2177 | int i; | |
2178 | ||
2179 | /* In a compound relocation, it is the final (outermost) | |
2180 | operator that determines the relocated field. */ | |
2181 | for (i = 1; i < 3; i++) | |
2182 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2183 | break; | |
2184 | ||
2185 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); | |
a105a300 TS |
2186 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
2187 | bfd_get_reloc_size(howto), | |
f6688943 | 2188 | address_expr, |
a105a300 | 2189 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2190 | reloc_type[0]); |
2191 | ||
b6ff326e | 2192 | /* These relocations can have an addend that won't fit in |
f6688943 | 2193 | 4 octets for 64bit assembly. */ |
a105a300 TS |
2194 | if (HAVE_64BIT_GPRS |
2195 | && ! howto->partial_inplace | |
2196 | && (reloc_type[0] == BFD_RELOC_16 | |
2197 | || reloc_type[0] == BFD_RELOC_32 | |
2198 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2199 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2200 | || reloc_type[0] == BFD_RELOC_LO16 | |
2201 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2202 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2203 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2204 | || reloc_type[0] == BFD_RELOC_64 | |
2205 | || reloc_type[0] == BFD_RELOC_CTOR | |
2206 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2207 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2208 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2209 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2210 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2211 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2212 | fixp[0]->fx_no_overflow = 1; |
2213 | ||
5919d012 | 2214 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2215 | { |
2216 | struct mips_hi_fixup *hi_fixup; | |
2217 | ||
5919d012 RS |
2218 | /* Reuse the last entry if it already has a matching %lo. */ |
2219 | hi_fixup = mips_hi_fixup_list; | |
2220 | if (hi_fixup == 0 | |
2221 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2222 | { | |
2223 | hi_fixup = ((struct mips_hi_fixup *) | |
2224 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2225 | hi_fixup->next = mips_hi_fixup_list; | |
2226 | mips_hi_fixup_list = hi_fixup; | |
2227 | } | |
f6688943 | 2228 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2229 | hi_fixup->seg = now_seg; |
252b5132 | 2230 | } |
f6688943 | 2231 | |
34ce925e RS |
2232 | /* Add fixups for the second and third relocations, if given. |
2233 | Note that the ABI allows the second relocation to be | |
2234 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2235 | moment we only use RSS_UNDEF, but we could add support | |
2236 | for the others if it ever becomes necessary. */ | |
2237 | for (i = 1; i < 3; i++) | |
2238 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2239 | { | |
2240 | address_expr->X_op = O_absent; | |
2241 | address_expr->X_add_symbol = 0; | |
2242 | address_expr->X_add_number = 0; | |
2243 | ||
2244 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, | |
2245 | fixp[0]->fx_size, address_expr, | |
2246 | FALSE, reloc_type[i]); | |
2247 | } | |
252b5132 RH |
2248 | } |
2249 | } | |
2250 | } | |
2251 | ||
2252 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2253 | { |
2254 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2255 | #ifdef OBJ_ELF | |
2256 | dwarf2_emit_insn (4); | |
2257 | #endif | |
2258 | } | |
f6688943 | 2259 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2260 | { |
2261 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2262 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2263 | #ifdef OBJ_ELF |
2264 | dwarf2_emit_insn (4); | |
2265 | #endif | |
252b5132 RH |
2266 | } |
2267 | else | |
2268 | { | |
2269 | if (ip->use_extend) | |
2270 | { | |
2271 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2272 | f += 2; | |
2273 | } | |
2274 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2275 | #ifdef OBJ_ELF |
2276 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2277 | #endif | |
252b5132 RH |
2278 | } |
2279 | ||
2280 | /* Update the register mask information. */ | |
2281 | if (! mips_opts.mips16) | |
2282 | { | |
2283 | if (pinfo & INSN_WRITE_GPR_D) | |
2284 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2285 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2286 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2287 | if (pinfo & INSN_READ_GPR_S) | |
2288 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2289 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2290 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2291 | if (pinfo & INSN_WRITE_FPR_D) |
2292 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2293 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2294 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2295 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2296 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2297 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2298 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2299 | if (pinfo & INSN_COP) | |
2300 | { | |
bdaaa2e1 KH |
2301 | /* We don't keep enough information to sort these cases out. |
2302 | The itbl support does keep this information however, although | |
2303 | we currently don't support itbl fprmats as part of the cop | |
2304 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2305 | } |
2306 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2307 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2308 | } |
2309 | else | |
2310 | { | |
2311 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2312 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2313 | & MIPS16OP_MASK_RX); | |
2314 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2315 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2316 | & MIPS16OP_MASK_RY); | |
2317 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2318 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2319 | & MIPS16OP_MASK_RZ); | |
2320 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2321 | mips_gprmask |= 1 << TREG; | |
2322 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2323 | mips_gprmask |= 1 << SP; | |
2324 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2325 | mips_gprmask |= 1 << RA; | |
2326 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2327 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2328 | if (pinfo & MIPS16_INSN_READ_Z) | |
2329 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2330 | & MIPS16OP_MASK_MOVE32Z); | |
2331 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2332 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2333 | & MIPS16OP_MASK_REGR32); | |
2334 | } | |
2335 | ||
2336 | if (place == NULL && ! mips_opts.noreorder) | |
2337 | { | |
2338 | /* Filling the branch delay slot is more complex. We try to | |
2339 | switch the branch with the previous instruction, which we can | |
2340 | do if the previous instruction does not set up a condition | |
2341 | that the branch tests and if the branch is not itself the | |
2342 | target of any branch. */ | |
2343 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2344 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2345 | { | |
2346 | if (mips_optimize < 2 | |
2347 | /* If we have seen .set volatile or .set nomove, don't | |
2348 | optimize. */ | |
2349 | || mips_opts.nomove != 0 | |
2350 | /* If we had to emit any NOP instructions, then we | |
2351 | already know we can not swap. */ | |
2352 | || nops != 0 | |
2353 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2354 | swap. */ |
252b5132 RH |
2355 | || ! prev_insn_valid |
2356 | /* If the previous insn is already in a branch delay | |
2357 | slot, then we can not swap. */ | |
2358 | || prev_insn_is_delay_slot | |
2359 | /* If the previous previous insn was in a .set | |
2360 | noreorder, we can't swap. Actually, the MIPS | |
2361 | assembler will swap in this situation. However, gcc | |
2362 | configured -with-gnu-as will generate code like | |
2363 | .set noreorder | |
2364 | lw $4,XXX | |
2365 | .set reorder | |
2366 | INSN | |
2367 | bne $4,$0,foo | |
2368 | in which we can not swap the bne and INSN. If gcc is | |
2369 | not configured -with-gnu-as, it does not output the | |
2370 | .set pseudo-ops. We don't have to check | |
2371 | prev_insn_unreordered, because prev_insn_valid will | |
2372 | be 0 in that case. We don't want to use | |
2373 | prev_prev_insn_valid, because we do want to be able | |
2374 | to swap at the start of a function. */ | |
2375 | || prev_prev_insn_unreordered | |
2376 | /* If the branch is itself the target of a branch, we | |
2377 | can not swap. We cheat on this; all we check for is | |
2378 | whether there is a label on this instruction. If | |
2379 | there are any branches to anything other than a | |
2380 | label, users must use .set noreorder. */ | |
2381 | || insn_labels != NULL | |
2382 | /* If the previous instruction is in a variant frag, we | |
2383 | can not do the swap. This does not apply to the | |
2384 | mips16, which uses variant frags for different | |
2385 | purposes. */ | |
2386 | || (! mips_opts.mips16 | |
2387 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2388 | /* If the branch reads the condition codes, we don't | |
2389 | even try to swap, because in the sequence | |
2390 | ctc1 $X,$31 | |
2391 | INSN | |
2392 | INSN | |
2393 | bc1t LABEL | |
2394 | we can not swap, and I don't feel like handling that | |
2395 | case. */ | |
2396 | || (! mips_opts.mips16 | |
9ce8a5dd | 2397 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2398 | && (pinfo & INSN_READ_COND_CODE)) |
2399 | /* We can not swap with an instruction that requires a | |
2400 | delay slot, becase the target of the branch might | |
2401 | interfere with that instruction. */ | |
2402 | || (! mips_opts.mips16 | |
9ce8a5dd | 2403 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2404 | && (prev_pinfo |
bdaaa2e1 | 2405 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2406 | & (INSN_LOAD_COPROC_DELAY |
2407 | | INSN_COPROC_MOVE_DELAY | |
2408 | | INSN_WRITE_COND_CODE))) | |
2409 | || (! (hilo_interlocks | |
ec68c924 | 2410 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2411 | && (prev_pinfo |
2412 | & (INSN_READ_LO | |
2413 | | INSN_READ_HI))) | |
2414 | || (! mips_opts.mips16 | |
2415 | && ! gpr_interlocks | |
2416 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2417 | || (! mips_opts.mips16 | |
e7af610e | 2418 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2419 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2420 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2421 | /* We can not swap with a branch instruction. */ | |
2422 | || (prev_pinfo | |
2423 | & (INSN_UNCOND_BRANCH_DELAY | |
2424 | | INSN_COND_BRANCH_DELAY | |
2425 | | INSN_COND_BRANCH_LIKELY)) | |
2426 | /* We do not swap with a trap instruction, since it | |
2427 | complicates trap handlers to have the trap | |
2428 | instruction be in a delay slot. */ | |
2429 | || (prev_pinfo & INSN_TRAP) | |
2430 | /* If the branch reads a register that the previous | |
2431 | instruction sets, we can not swap. */ | |
2432 | || (! mips_opts.mips16 | |
2433 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2434 | && insn_uses_reg (ip, | |
2435 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2436 | & OP_MASK_RT), | |
2437 | MIPS_GR_REG)) | |
2438 | || (! mips_opts.mips16 | |
2439 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2440 | && insn_uses_reg (ip, | |
2441 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2442 | & OP_MASK_RD), | |
2443 | MIPS_GR_REG)) | |
2444 | || (mips_opts.mips16 | |
2445 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2446 | && insn_uses_reg (ip, | |
2447 | ((prev_insn.insn_opcode | |
2448 | >> MIPS16OP_SH_RX) | |
2449 | & MIPS16OP_MASK_RX), | |
2450 | MIPS16_REG)) | |
2451 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2452 | && insn_uses_reg (ip, | |
2453 | ((prev_insn.insn_opcode | |
2454 | >> MIPS16OP_SH_RY) | |
2455 | & MIPS16OP_MASK_RY), | |
2456 | MIPS16_REG)) | |
2457 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2458 | && insn_uses_reg (ip, | |
2459 | ((prev_insn.insn_opcode | |
2460 | >> MIPS16OP_SH_RZ) | |
2461 | & MIPS16OP_MASK_RZ), | |
2462 | MIPS16_REG)) | |
2463 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2464 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2465 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2466 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2467 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2468 | && insn_uses_reg (ip, | |
2469 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2470 | insn_opcode), | |
2471 | MIPS_GR_REG)))) | |
2472 | /* If the branch writes a register that the previous | |
2473 | instruction sets, we can not swap (we know that | |
2474 | branches write only to RD or to $31). */ | |
2475 | || (! mips_opts.mips16 | |
2476 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2477 | && (((pinfo & INSN_WRITE_GPR_D) | |
2478 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2479 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2480 | || ((pinfo & INSN_WRITE_GPR_31) | |
2481 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2482 | & OP_MASK_RT) | |
f9419b05 | 2483 | == RA)))) |
252b5132 RH |
2484 | || (! mips_opts.mips16 |
2485 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2486 | && (((pinfo & INSN_WRITE_GPR_D) | |
2487 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2488 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2489 | || ((pinfo & INSN_WRITE_GPR_31) | |
2490 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2491 | & OP_MASK_RD) | |
f9419b05 | 2492 | == RA)))) |
252b5132 RH |
2493 | || (mips_opts.mips16 |
2494 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2495 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2496 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2497 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2498 | == RA)))) | |
2499 | /* If the branch writes a register that the previous | |
2500 | instruction reads, we can not swap (we know that | |
2501 | branches only write to RD or to $31). */ | |
2502 | || (! mips_opts.mips16 | |
2503 | && (pinfo & INSN_WRITE_GPR_D) | |
2504 | && insn_uses_reg (&prev_insn, | |
2505 | ((ip->insn_opcode >> OP_SH_RD) | |
2506 | & OP_MASK_RD), | |
2507 | MIPS_GR_REG)) | |
2508 | || (! mips_opts.mips16 | |
2509 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2510 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2511 | || (mips_opts.mips16 |
2512 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2513 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2514 | /* If we are generating embedded PIC code, the branch | |
2515 | might be expanded into a sequence which uses $at, so | |
2516 | we can't swap with an instruction which reads it. */ | |
2517 | || (mips_pic == EMBEDDED_PIC | |
2518 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2519 | /* If the previous previous instruction has a load | |
2520 | delay, and sets a register that the branch reads, we | |
2521 | can not swap. */ | |
2522 | || (! mips_opts.mips16 | |
9ce8a5dd | 2523 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2524 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2525 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2526 | || (! gpr_interlocks | |
2527 | && (prev_prev_insn.insn_mo->pinfo | |
2528 | & INSN_LOAD_MEMORY_DELAY))) | |
2529 | && insn_uses_reg (ip, | |
2530 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2531 | & OP_MASK_RT), | |
2532 | MIPS_GR_REG)) | |
2533 | /* If one instruction sets a condition code and the | |
2534 | other one uses a condition code, we can not swap. */ | |
2535 | || ((pinfo & INSN_READ_COND_CODE) | |
2536 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2537 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2538 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2539 | /* If the previous instruction uses the PC, we can not | |
2540 | swap. */ | |
2541 | || (mips_opts.mips16 | |
2542 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2543 | /* If the previous instruction was extended, we can not | |
2544 | swap. */ | |
2545 | || (mips_opts.mips16 && prev_insn_extended) | |
2546 | /* If the previous instruction had a fixup in mips16 | |
2547 | mode, we can not swap. This normally means that the | |
2548 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2549 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2550 | /* If the previous instruction is a sync, sync.l, or |
2551 | sync.p, we can not swap. */ | |
f173e82e | 2552 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2553 | { |
2554 | /* We could do even better for unconditional branches to | |
2555 | portions of this object file; we could pick up the | |
2556 | instruction at the destination, put it in the delay | |
2557 | slot, and bump the destination address. */ | |
2558 | emit_nop (); | |
2559 | /* Update the previous insn information. */ | |
2560 | prev_prev_insn = *ip; | |
2561 | prev_insn.insn_mo = &dummy_opcode; | |
2562 | } | |
2563 | else | |
2564 | { | |
2565 | /* It looks like we can actually do the swap. */ | |
2566 | if (! mips_opts.mips16) | |
2567 | { | |
2568 | char *prev_f; | |
2569 | char temp[4]; | |
2570 | ||
2571 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2572 | memcpy (temp, prev_f, 4); | |
2573 | memcpy (prev_f, f, 4); | |
2574 | memcpy (f, temp, 4); | |
f6688943 TS |
2575 | if (prev_insn_fixp[0]) |
2576 | { | |
2577 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2578 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2579 | } | |
2580 | if (prev_insn_fixp[1]) | |
2581 | { | |
2582 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2583 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2584 | } | |
2585 | if (prev_insn_fixp[2]) | |
252b5132 | 2586 | { |
f6688943 TS |
2587 | prev_insn_fixp[2]->fx_frag = frag_now; |
2588 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2589 | } |
f5040a92 AO |
2590 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2591 | && prev_insn_frag != frag_now | |
2592 | && (prev_insn_fixp[0]->fx_r_type | |
2593 | == BFD_RELOC_MIPS_GOT_DISP | |
2594 | || (prev_insn_fixp[0]->fx_r_type | |
2595 | == BFD_RELOC_MIPS_CALL16))) | |
2596 | { | |
2597 | /* To avoid confusion in tc_gen_reloc, we must | |
2598 | ensure that this does not become a variant | |
2599 | frag. */ | |
2600 | force_new_frag = TRUE; | |
2601 | } | |
f6688943 | 2602 | if (fixp[0]) |
252b5132 | 2603 | { |
f6688943 TS |
2604 | fixp[0]->fx_frag = prev_insn_frag; |
2605 | fixp[0]->fx_where = prev_insn_where; | |
2606 | } | |
2607 | if (fixp[1]) | |
2608 | { | |
2609 | fixp[1]->fx_frag = prev_insn_frag; | |
2610 | fixp[1]->fx_where = prev_insn_where; | |
2611 | } | |
2612 | if (fixp[2]) | |
2613 | { | |
2614 | fixp[2]->fx_frag = prev_insn_frag; | |
2615 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2616 | } |
2617 | } | |
2618 | else | |
2619 | { | |
2620 | char *prev_f; | |
2621 | char temp[2]; | |
2622 | ||
f6688943 TS |
2623 | assert (prev_insn_fixp[0] == NULL); |
2624 | assert (prev_insn_fixp[1] == NULL); | |
2625 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2626 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2627 | memcpy (temp, prev_f, 2); | |
2628 | memcpy (prev_f, f, 2); | |
f6688943 | 2629 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2630 | { |
f6688943 | 2631 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2632 | memcpy (f, temp, 2); |
2633 | } | |
2634 | else | |
2635 | { | |
2636 | memcpy (f, f + 2, 2); | |
2637 | memcpy (f + 2, temp, 2); | |
2638 | } | |
f6688943 TS |
2639 | if (fixp[0]) |
2640 | { | |
2641 | fixp[0]->fx_frag = prev_insn_frag; | |
2642 | fixp[0]->fx_where = prev_insn_where; | |
2643 | } | |
2644 | if (fixp[1]) | |
2645 | { | |
2646 | fixp[1]->fx_frag = prev_insn_frag; | |
2647 | fixp[1]->fx_where = prev_insn_where; | |
2648 | } | |
2649 | if (fixp[2]) | |
252b5132 | 2650 | { |
f6688943 TS |
2651 | fixp[2]->fx_frag = prev_insn_frag; |
2652 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2653 | } |
2654 | } | |
2655 | ||
2656 | /* Update the previous insn information; leave prev_insn | |
2657 | unchanged. */ | |
2658 | prev_prev_insn = *ip; | |
2659 | } | |
2660 | prev_insn_is_delay_slot = 1; | |
2661 | ||
2662 | /* If that was an unconditional branch, forget the previous | |
2663 | insn information. */ | |
2664 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2665 | { | |
2666 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2667 | prev_insn.insn_mo = &dummy_opcode; | |
2668 | } | |
2669 | ||
f6688943 TS |
2670 | prev_insn_fixp[0] = NULL; |
2671 | prev_insn_fixp[1] = NULL; | |
2672 | prev_insn_fixp[2] = NULL; | |
2673 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2674 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2675 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2676 | prev_insn_extended = 0; |
2677 | } | |
2678 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2679 | { | |
2680 | /* We don't yet optimize a branch likely. What we should do | |
2681 | is look at the target, copy the instruction found there | |
2682 | into the delay slot, and increment the branch to jump to | |
2683 | the next instruction. */ | |
2684 | emit_nop (); | |
2685 | /* Update the previous insn information. */ | |
2686 | prev_prev_insn = *ip; | |
2687 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2688 | prev_insn_fixp[0] = NULL; |
2689 | prev_insn_fixp[1] = NULL; | |
2690 | prev_insn_fixp[2] = NULL; | |
2691 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2692 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2693 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2694 | prev_insn_extended = 0; |
2695 | } | |
2696 | else | |
2697 | { | |
2698 | /* Update the previous insn information. */ | |
2699 | if (nops > 0) | |
2700 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2701 | else | |
2702 | prev_prev_insn = prev_insn; | |
2703 | prev_insn = *ip; | |
2704 | ||
2705 | /* Any time we see a branch, we always fill the delay slot | |
2706 | immediately; since this insn is not a branch, we know it | |
2707 | is not in a delay slot. */ | |
2708 | prev_insn_is_delay_slot = 0; | |
2709 | ||
f6688943 TS |
2710 | prev_insn_fixp[0] = fixp[0]; |
2711 | prev_insn_fixp[1] = fixp[1]; | |
2712 | prev_insn_fixp[2] = fixp[2]; | |
2713 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2714 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2715 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2716 | if (mips_opts.mips16) |
2717 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2718 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2719 | } |
2720 | ||
2721 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2722 | prev_insn_unreordered = 0; | |
2723 | prev_insn_frag = frag_now; | |
2724 | prev_insn_where = f - frag_now->fr_literal; | |
2725 | prev_insn_valid = 1; | |
2726 | } | |
2727 | else if (place == NULL) | |
2728 | { | |
2729 | /* We need to record a bit of information even when we are not | |
2730 | reordering, in order to determine the base address for mips16 | |
2731 | PC relative relocs. */ | |
2732 | prev_prev_insn = prev_insn; | |
2733 | prev_insn = *ip; | |
f6688943 TS |
2734 | prev_insn_reloc_type[0] = reloc_type[0]; |
2735 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2736 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2737 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2738 | prev_insn_unreordered = 1; | |
2739 | } | |
2740 | ||
2741 | /* We just output an insn, so the next one doesn't have a label. */ | |
2742 | mips_clear_insn_labels (); | |
f5040a92 AO |
2743 | |
2744 | /* We must ensure that the frag to which an instruction that was | |
2745 | moved from a non-variant frag doesn't become a variant frag, | |
2746 | otherwise tc_gen_reloc may get confused. */ | |
2747 | if (force_new_frag) | |
2748 | { | |
2749 | frag_wane (frag_now); | |
2750 | frag_new (0); | |
2751 | } | |
252b5132 RH |
2752 | } |
2753 | ||
2754 | /* This function forgets that there was any previous instruction or | |
2755 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2756 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2757 | |
2758 | static void | |
2759 | mips_no_prev_insn (preserve) | |
2760 | int preserve; | |
2761 | { | |
2762 | if (! preserve) | |
2763 | { | |
2764 | prev_insn.insn_mo = &dummy_opcode; | |
2765 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2766 | prev_nop_frag = NULL; | |
2767 | prev_nop_frag_holds = 0; | |
2768 | prev_nop_frag_required = 0; | |
2769 | prev_nop_frag_since = 0; | |
2770 | } | |
2771 | prev_insn_valid = 0; | |
2772 | prev_insn_is_delay_slot = 0; | |
2773 | prev_insn_unreordered = 0; | |
2774 | prev_insn_extended = 0; | |
f6688943 TS |
2775 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2776 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2777 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2778 | prev_prev_insn_unreordered = 0; |
2779 | mips_clear_insn_labels (); | |
2780 | } | |
2781 | ||
2782 | /* This function must be called whenever we turn on noreorder or emit | |
2783 | something other than instructions. It inserts any NOPS which might | |
2784 | be needed by the previous instruction, and clears the information | |
2785 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2786 | instructions are to follow. */ |
252b5132 RH |
2787 | |
2788 | static void | |
2789 | mips_emit_delays (insns) | |
b34976b6 | 2790 | bfd_boolean insns; |
252b5132 RH |
2791 | { |
2792 | if (! mips_opts.noreorder) | |
2793 | { | |
2794 | int nops; | |
2795 | ||
2796 | nops = 0; | |
2797 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2798 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2799 | && (! cop_interlocks |
2800 | && (prev_insn.insn_mo->pinfo | |
2801 | & (INSN_LOAD_COPROC_DELAY | |
2802 | | INSN_COPROC_MOVE_DELAY | |
2803 | | INSN_WRITE_COND_CODE)))) | |
2804 | || (! hilo_interlocks | |
2805 | && (prev_insn.insn_mo->pinfo | |
2806 | & (INSN_READ_LO | |
2807 | | INSN_READ_HI))) | |
2808 | || (! mips_opts.mips16 | |
2809 | && ! gpr_interlocks | |
bdaaa2e1 | 2810 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2811 | & INSN_LOAD_MEMORY_DELAY)) |
2812 | || (! mips_opts.mips16 | |
e7af610e | 2813 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2814 | && (prev_insn.insn_mo->pinfo |
2815 | & INSN_COPROC_MEMORY_DELAY))) | |
2816 | { | |
beae10d5 | 2817 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2818 | ++nops; |
2819 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2820 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2821 | && (! cop_interlocks |
2822 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2823 | || (! hilo_interlocks | |
2824 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2825 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2826 | ++nops; | |
2827 | ||
2828 | if (prev_insn_unreordered) | |
2829 | nops = 0; | |
2830 | } | |
2831 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2832 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2833 | && (! cop_interlocks |
2834 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2835 | || (! hilo_interlocks | |
2836 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2837 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2838 | { | |
beae10d5 | 2839 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2840 | if (! prev_prev_insn_unreordered) |
2841 | ++nops; | |
2842 | } | |
2843 | ||
60b63b72 RS |
2844 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2845 | { | |
2846 | int min_nops = 0; | |
2847 | const char *pn = prev_insn.insn_mo->name; | |
2848 | if (strncmp(pn, "macc", 4) == 0 | |
2849 | || strncmp(pn, "dmacc", 5) == 0 | |
2850 | || strncmp(pn, "dmult", 5) == 0) | |
2851 | { | |
2852 | min_nops = 1; | |
2853 | } | |
2854 | if (nops < min_nops) | |
2855 | nops = min_nops; | |
2856 | } | |
2857 | ||
252b5132 RH |
2858 | if (nops > 0) |
2859 | { | |
2860 | struct insn_label_list *l; | |
2861 | ||
2862 | if (insns) | |
2863 | { | |
2864 | /* Record the frag which holds the nop instructions, so | |
2865 | that we can remove them if we don't need them. */ | |
2866 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2867 | prev_nop_frag = frag_now; | |
2868 | prev_nop_frag_holds = nops; | |
2869 | prev_nop_frag_required = 0; | |
2870 | prev_nop_frag_since = 0; | |
2871 | } | |
2872 | ||
2873 | for (; nops > 0; --nops) | |
2874 | emit_nop (); | |
2875 | ||
2876 | if (insns) | |
2877 | { | |
2878 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2879 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2880 | frag_wane (frag_now); |
2881 | frag_new (0); | |
2882 | } | |
2883 | ||
2884 | for (l = insn_labels; l != NULL; l = l->next) | |
2885 | { | |
98aa84af AM |
2886 | valueT val; |
2887 | ||
252b5132 | 2888 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2889 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2890 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2891 | /* mips16 text labels are stored as odd. */ |
2892 | if (mips_opts.mips16) | |
f9419b05 | 2893 | ++val; |
98aa84af | 2894 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2895 | } |
2896 | } | |
2897 | } | |
2898 | ||
2899 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2900 | if (insns) |
252b5132 RH |
2901 | mips16_mark_labels (); |
2902 | ||
2903 | mips_no_prev_insn (insns); | |
2904 | } | |
2905 | ||
2906 | /* Build an instruction created by a macro expansion. This is passed | |
2907 | a pointer to the count of instructions created so far, an | |
2908 | expression, the name of the instruction to build, an operand format | |
2909 | string, and corresponding arguments. */ | |
2910 | ||
2911 | #ifdef USE_STDARG | |
2912 | static void | |
2913 | macro_build (char *place, | |
2914 | int *counter, | |
2915 | expressionS * ep, | |
2916 | const char *name, | |
2917 | const char *fmt, | |
2918 | ...) | |
2919 | #else | |
2920 | static void | |
2921 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2922 | char *place; | |
2923 | int *counter; | |
2924 | expressionS *ep; | |
2925 | const char *name; | |
2926 | const char *fmt; | |
2927 | va_dcl | |
2928 | #endif | |
2929 | { | |
2930 | struct mips_cl_insn insn; | |
f6688943 | 2931 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2932 | va_list args; |
252b5132 RH |
2933 | |
2934 | #ifdef USE_STDARG | |
2935 | va_start (args, fmt); | |
2936 | #else | |
2937 | va_start (args); | |
2938 | #endif | |
2939 | ||
2940 | /* | |
2941 | * If the macro is about to expand into a second instruction, | |
2942 | * print a warning if needed. We need to pass ip as a parameter | |
2943 | * to generate a better warning message here... | |
2944 | */ | |
2945 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2946 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2947 | ||
80cc45a5 EC |
2948 | /* |
2949 | * If the macro is about to expand into a second instruction, | |
2950 | * and it is in a delay slot, print a warning. | |
2951 | */ | |
2952 | if (place == NULL | |
2953 | && *counter == 1 | |
2954 | && mips_opts.noreorder | |
2955 | && (prev_prev_insn.insn_mo->pinfo | |
2956 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2957 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2958 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2959 | ||
252b5132 | 2960 | if (place == NULL) |
f9419b05 | 2961 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2962 | |
2963 | if (mips_opts.mips16) | |
2964 | { | |
2965 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2966 | va_end (args); | |
2967 | return; | |
2968 | } | |
2969 | ||
f6688943 TS |
2970 | r[0] = BFD_RELOC_UNUSED; |
2971 | r[1] = BFD_RELOC_UNUSED; | |
2972 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2973 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2974 | assert (insn.insn_mo); | |
2975 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2976 | ||
2977 | /* Search until we get a match for NAME. */ | |
2978 | while (1) | |
2979 | { | |
b34976b6 | 2980 | /* It is assumed here that macros will never generate |
deec1734 | 2981 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2982 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2983 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2984 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2985 | (mips_opts.isa | |
3396de36 | 2986 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
aec421e0 | 2987 | mips_arch) |
ec68c924 | 2988 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2989 | break; |
2990 | ||
2991 | ++insn.insn_mo; | |
2992 | assert (insn.insn_mo->name); | |
2993 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2994 | } | |
2995 | ||
2996 | insn.insn_opcode = insn.insn_mo->match; | |
2997 | for (;;) | |
2998 | { | |
2999 | switch (*fmt++) | |
3000 | { | |
3001 | case '\0': | |
3002 | break; | |
3003 | ||
3004 | case ',': | |
3005 | case '(': | |
3006 | case ')': | |
3007 | continue; | |
3008 | ||
3009 | case 't': | |
3010 | case 'w': | |
3011 | case 'E': | |
38487616 | 3012 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3013 | continue; |
3014 | ||
3015 | case 'c': | |
38487616 TS |
3016 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3017 | continue; | |
3018 | ||
252b5132 RH |
3019 | case 'T': |
3020 | case 'W': | |
38487616 | 3021 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3022 | continue; |
3023 | ||
3024 | case 'd': | |
3025 | case 'G': | |
af7ee8bf | 3026 | case 'K': |
38487616 | 3027 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3028 | continue; |
3029 | ||
4372b673 NC |
3030 | case 'U': |
3031 | { | |
3032 | int tmp = va_arg (args, int); | |
3033 | ||
38487616 TS |
3034 | insn.insn_opcode |= tmp << OP_SH_RT; |
3035 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3036 | continue; |
4372b673 NC |
3037 | } |
3038 | ||
252b5132 RH |
3039 | case 'V': |
3040 | case 'S': | |
38487616 | 3041 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3042 | continue; |
3043 | ||
3044 | case 'z': | |
3045 | continue; | |
3046 | ||
3047 | case '<': | |
38487616 | 3048 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3049 | continue; |
3050 | ||
3051 | case 'D': | |
38487616 | 3052 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3053 | continue; |
3054 | ||
3055 | case 'B': | |
38487616 | 3056 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3057 | continue; |
3058 | ||
4372b673 | 3059 | case 'J': |
38487616 | 3060 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3061 | continue; |
3062 | ||
252b5132 | 3063 | case 'q': |
38487616 | 3064 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3065 | continue; |
3066 | ||
3067 | case 'b': | |
3068 | case 's': | |
3069 | case 'r': | |
3070 | case 'v': | |
38487616 | 3071 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3072 | continue; |
3073 | ||
3074 | case 'i': | |
3075 | case 'j': | |
3076 | case 'o': | |
f6688943 | 3077 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3078 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3079 | || *r == BFD_RELOC_MIPS_LITERAL |
3080 | || *r == BFD_RELOC_MIPS_HIGHER | |
3081 | || *r == BFD_RELOC_HI16_S | |
3082 | || *r == BFD_RELOC_LO16 | |
3083 | || *r == BFD_RELOC_MIPS_GOT16 | |
3084 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3085 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3086 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3087 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3088 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3089 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3090 | || (ep->X_op == O_subtract |
f6688943 | 3091 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3092 | continue; |
3093 | ||
3094 | case 'u': | |
f6688943 | 3095 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3096 | assert (ep != NULL |
3097 | && (ep->X_op == O_constant | |
3098 | || (ep->X_op == O_symbol | |
f6688943 TS |
3099 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3100 | || *r == BFD_RELOC_HI16_S | |
3101 | || *r == BFD_RELOC_HI16 | |
3102 | || *r == BFD_RELOC_GPREL16 | |
3103 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3104 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3105 | || (ep->X_op == O_subtract |
f6688943 | 3106 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3107 | continue; |
3108 | ||
3109 | case 'p': | |
3110 | assert (ep != NULL); | |
3111 | /* | |
3112 | * This allows macro() to pass an immediate expression for | |
3113 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3114 | * Note that the expression still might come from the assembly |
3115 | * input, in which case the value is not checked for range nor | |
3116 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3117 | */ |
3118 | if (ep->X_op == O_constant) | |
3119 | { | |
3120 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3121 | ep = NULL; | |
3122 | } | |
3123 | else | |
0b25d3e6 | 3124 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3125 | continue; |
3126 | ||
3127 | case 'a': | |
3128 | assert (ep != NULL); | |
f6688943 | 3129 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3130 | continue; |
3131 | ||
3132 | case 'C': | |
3133 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3134 | continue; | |
3135 | ||
3136 | default: | |
3137 | internalError (); | |
3138 | } | |
3139 | break; | |
3140 | } | |
3141 | va_end (args); | |
f6688943 | 3142 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3143 | |
5e0116d5 | 3144 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3145 | } |
3146 | ||
3147 | static void | |
3148 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3149 | char *place; | |
43841e91 | 3150 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3151 | expressionS *ep; |
3152 | const char *name; | |
3153 | const char *fmt; | |
3154 | va_list args; | |
3155 | { | |
3156 | struct mips_cl_insn insn; | |
f6688943 TS |
3157 | bfd_reloc_code_real_type r[3] |
3158 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3159 | |
252b5132 RH |
3160 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3161 | assert (insn.insn_mo); | |
3162 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3163 | ||
3164 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3165 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3166 | { | |
3167 | ++insn.insn_mo; | |
3168 | assert (insn.insn_mo->name); | |
3169 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3170 | } | |
3171 | ||
3172 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3173 | insn.use_extend = FALSE; |
252b5132 RH |
3174 | |
3175 | for (;;) | |
3176 | { | |
3177 | int c; | |
3178 | ||
3179 | c = *fmt++; | |
3180 | switch (c) | |
3181 | { | |
3182 | case '\0': | |
3183 | break; | |
3184 | ||
3185 | case ',': | |
3186 | case '(': | |
3187 | case ')': | |
3188 | continue; | |
3189 | ||
3190 | case 'y': | |
3191 | case 'w': | |
3192 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3193 | continue; | |
3194 | ||
3195 | case 'x': | |
3196 | case 'v': | |
3197 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3198 | continue; | |
3199 | ||
3200 | case 'z': | |
3201 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3202 | continue; | |
3203 | ||
3204 | case 'Z': | |
3205 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3206 | continue; | |
3207 | ||
3208 | case '0': | |
3209 | case 'S': | |
3210 | case 'P': | |
3211 | case 'R': | |
3212 | continue; | |
3213 | ||
3214 | case 'X': | |
3215 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3216 | continue; | |
3217 | ||
3218 | case 'Y': | |
3219 | { | |
3220 | int regno; | |
3221 | ||
3222 | regno = va_arg (args, int); | |
3223 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3224 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3225 | } | |
3226 | continue; | |
3227 | ||
3228 | case '<': | |
3229 | case '>': | |
3230 | case '4': | |
3231 | case '5': | |
3232 | case 'H': | |
3233 | case 'W': | |
3234 | case 'D': | |
3235 | case 'j': | |
3236 | case '8': | |
3237 | case 'V': | |
3238 | case 'C': | |
3239 | case 'U': | |
3240 | case 'k': | |
3241 | case 'K': | |
3242 | case 'p': | |
3243 | case 'q': | |
3244 | { | |
3245 | assert (ep != NULL); | |
3246 | ||
3247 | if (ep->X_op != O_constant) | |
874e8986 | 3248 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3249 | else |
3250 | { | |
b34976b6 AM |
3251 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3252 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3253 | &insn.extend); |
252b5132 | 3254 | ep = NULL; |
f6688943 | 3255 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3256 | } |
3257 | } | |
3258 | continue; | |
3259 | ||
3260 | case '6': | |
3261 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3262 | continue; | |
3263 | } | |
3264 | ||
3265 | break; | |
3266 | } | |
3267 | ||
f6688943 | 3268 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3269 | |
5e0116d5 | 3270 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3271 | } |
3272 | ||
438c16b8 TS |
3273 | /* |
3274 | * Generate a "jalr" instruction with a relocation hint to the called | |
3275 | * function. This occurs in NewABI PIC code. | |
3276 | */ | |
3277 | static void | |
3278 | macro_build_jalr (icnt, ep) | |
3279 | int icnt; | |
3280 | expressionS *ep; | |
3281 | { | |
685736be | 3282 | char *f = NULL; |
b34976b6 | 3283 | |
438c16b8 | 3284 | if (HAVE_NEWABI) |
f21f8242 AO |
3285 | { |
3286 | frag_grow (4); | |
3287 | f = frag_more (0); | |
3288 | } | |
438c16b8 TS |
3289 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
3290 | RA, PIC_CALL_REG); | |
3291 | if (HAVE_NEWABI) | |
f21f8242 | 3292 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3293 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3294 | } |
3295 | ||
252b5132 RH |
3296 | /* |
3297 | * Generate a "lui" instruction. | |
3298 | */ | |
3299 | static void | |
3300 | macro_build_lui (place, counter, ep, regnum) | |
3301 | char *place; | |
3302 | int *counter; | |
3303 | expressionS *ep; | |
3304 | int regnum; | |
3305 | { | |
3306 | expressionS high_expr; | |
3307 | struct mips_cl_insn insn; | |
f6688943 TS |
3308 | bfd_reloc_code_real_type r[3] |
3309 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3310 | const char *name = "lui"; |
3311 | const char *fmt = "t,u"; | |
252b5132 RH |
3312 | |
3313 | assert (! mips_opts.mips16); | |
3314 | ||
3315 | if (place == NULL) | |
3316 | high_expr = *ep; | |
3317 | else | |
3318 | { | |
3319 | high_expr.X_op = O_constant; | |
3320 | high_expr.X_add_number = ep->X_add_number; | |
3321 | } | |
3322 | ||
3323 | if (high_expr.X_op == O_constant) | |
3324 | { | |
3325 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3326 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3327 | >> 16) & 0xffff; | |
f6688943 | 3328 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3329 | } |
78e1bb40 | 3330 | else |
252b5132 RH |
3331 | { |
3332 | assert (ep->X_op == O_symbol); | |
3333 | /* _gp_disp is a special case, used from s_cpload. */ | |
3334 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3335 | || (! HAVE_NEWABI |
3336 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3337 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3338 | } |
3339 | ||
3340 | /* | |
3341 | * If the macro is about to expand into a second instruction, | |
3342 | * print a warning if needed. We need to pass ip as a parameter | |
3343 | * to generate a better warning message here... | |
3344 | */ | |
3345 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3346 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3347 | ||
3348 | if (place == NULL) | |
f9419b05 | 3349 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3350 | |
3351 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3352 | assert (insn.insn_mo); | |
3353 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3354 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3355 | ||
3356 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3357 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3358 | { |
3359 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3360 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3361 | } |
3362 | else | |
5e0116d5 | 3363 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3364 | } |
3365 | ||
885add95 CD |
3366 | /* Generate a sequence of instructions to do a load or store from a constant |
3367 | offset off of a base register (breg) into/from a target register (treg), | |
3368 | using AT if necessary. */ | |
3369 | static void | |
3370 | macro_build_ldst_constoffset (place, counter, ep, op, treg, breg) | |
3371 | char *place; | |
3372 | int *counter; | |
3373 | expressionS *ep; | |
3374 | const char *op; | |
3375 | int treg, breg; | |
3376 | { | |
3377 | assert (ep->X_op == O_constant); | |
3378 | ||
3379 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3380 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3381 | as_warn (_("operand overflow")); | |
3382 | ||
3383 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3384 | { | |
3385 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
3386 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3387 | (int) BFD_RELOC_LO16, breg); | |
3388 | } | |
3389 | else | |
3390 | { | |
3391 | /* 32-bit offset, need multiple instructions and AT, like: | |
3392 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3393 | addu $tempreg,$tempreg,$breg | |
3394 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3395 | to handle the complete offset. */ | |
3396 | macro_build_lui (place, counter, ep, AT); | |
3397 | if (place != NULL) | |
3398 | place += 4; | |
f899b4b8 | 3399 | macro_build (place, counter, (expressionS *) NULL, ADDRESS_ADD_INSN, |
885add95 CD |
3400 | "d,v,t", AT, AT, breg); |
3401 | if (place != NULL) | |
3402 | place += 4; | |
3403 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3404 | (int) BFD_RELOC_LO16, AT); | |
3405 | ||
3406 | if (mips_opts.noat) | |
3407 | as_warn (_("Macro used $at after \".set noat\"")); | |
3408 | } | |
3409 | } | |
3410 | ||
252b5132 RH |
3411 | /* set_at() |
3412 | * Generates code to set the $at register to true (one) | |
3413 | * if reg is less than the immediate expression. | |
3414 | */ | |
3415 | static void | |
3416 | set_at (counter, reg, unsignedp) | |
3417 | int *counter; | |
3418 | int reg; | |
3419 | int unsignedp; | |
3420 | { | |
3421 | if (imm_expr.X_op == O_constant | |
3422 | && imm_expr.X_add_number >= -0x8000 | |
3423 | && imm_expr.X_add_number < 0x8000) | |
3424 | macro_build ((char *) NULL, counter, &imm_expr, | |
3425 | unsignedp ? "sltiu" : "slti", | |
3426 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3427 | else | |
3428 | { | |
4d34fb5f | 3429 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3430 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3431 | unsignedp ? "sltu" : "slt", |
3432 | "d,v,t", AT, reg, AT); | |
3433 | } | |
3434 | } | |
3435 | ||
3436 | /* Warn if an expression is not a constant. */ | |
3437 | ||
3438 | static void | |
3439 | check_absolute_expr (ip, ex) | |
3440 | struct mips_cl_insn *ip; | |
3441 | expressionS *ex; | |
3442 | { | |
3443 | if (ex->X_op == O_big) | |
3444 | as_bad (_("unsupported large constant")); | |
3445 | else if (ex->X_op != O_constant) | |
3446 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3447 | } | |
3448 | ||
3449 | /* Count the leading zeroes by performing a binary chop. This is a | |
3450 | bulky bit of source, but performance is a LOT better for the | |
3451 | majority of values than a simple loop to count the bits: | |
3452 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3453 | if ((v) & (1 << (31 - lcnt))) | |
3454 | break; | |
3455 | However it is not code size friendly, and the gain will drop a bit | |
3456 | on certain cached systems. | |
3457 | */ | |
3458 | #define COUNT_TOP_ZEROES(v) \ | |
3459 | (((v) & ~0xffff) == 0 \ | |
3460 | ? ((v) & ~0xff) == 0 \ | |
3461 | ? ((v) & ~0xf) == 0 \ | |
3462 | ? ((v) & ~0x3) == 0 \ | |
3463 | ? ((v) & ~0x1) == 0 \ | |
3464 | ? !(v) \ | |
3465 | ? 32 \ | |
3466 | : 31 \ | |
3467 | : 30 \ | |
3468 | : ((v) & ~0x7) == 0 \ | |
3469 | ? 29 \ | |
3470 | : 28 \ | |
3471 | : ((v) & ~0x3f) == 0 \ | |
3472 | ? ((v) & ~0x1f) == 0 \ | |
3473 | ? 27 \ | |
3474 | : 26 \ | |
3475 | : ((v) & ~0x7f) == 0 \ | |
3476 | ? 25 \ | |
3477 | : 24 \ | |
3478 | : ((v) & ~0xfff) == 0 \ | |
3479 | ? ((v) & ~0x3ff) == 0 \ | |
3480 | ? ((v) & ~0x1ff) == 0 \ | |
3481 | ? 23 \ | |
3482 | : 22 \ | |
3483 | : ((v) & ~0x7ff) == 0 \ | |
3484 | ? 21 \ | |
3485 | : 20 \ | |
3486 | : ((v) & ~0x3fff) == 0 \ | |
3487 | ? ((v) & ~0x1fff) == 0 \ | |
3488 | ? 19 \ | |
3489 | : 18 \ | |
3490 | : ((v) & ~0x7fff) == 0 \ | |
3491 | ? 17 \ | |
3492 | : 16 \ | |
3493 | : ((v) & ~0xffffff) == 0 \ | |
3494 | ? ((v) & ~0xfffff) == 0 \ | |
3495 | ? ((v) & ~0x3ffff) == 0 \ | |
3496 | ? ((v) & ~0x1ffff) == 0 \ | |
3497 | ? 15 \ | |
3498 | : 14 \ | |
3499 | : ((v) & ~0x7ffff) == 0 \ | |
3500 | ? 13 \ | |
3501 | : 12 \ | |
3502 | : ((v) & ~0x3fffff) == 0 \ | |
3503 | ? ((v) & ~0x1fffff) == 0 \ | |
3504 | ? 11 \ | |
3505 | : 10 \ | |
3506 | : ((v) & ~0x7fffff) == 0 \ | |
3507 | ? 9 \ | |
3508 | : 8 \ | |
3509 | : ((v) & ~0xfffffff) == 0 \ | |
3510 | ? ((v) & ~0x3ffffff) == 0 \ | |
3511 | ? ((v) & ~0x1ffffff) == 0 \ | |
3512 | ? 7 \ | |
3513 | : 6 \ | |
3514 | : ((v) & ~0x7ffffff) == 0 \ | |
3515 | ? 5 \ | |
3516 | : 4 \ | |
3517 | : ((v) & ~0x3fffffff) == 0 \ | |
3518 | ? ((v) & ~0x1fffffff) == 0 \ | |
3519 | ? 3 \ | |
3520 | : 2 \ | |
3521 | : ((v) & ~0x7fffffff) == 0 \ | |
3522 | ? 1 \ | |
3523 | : 0) | |
3524 | ||
3525 | /* load_register() | |
3526 | * This routine generates the least number of instructions neccessary to load | |
3527 | * an absolute expression value into a register. | |
3528 | */ | |
3529 | static void | |
3530 | load_register (counter, reg, ep, dbl) | |
3531 | int *counter; | |
3532 | int reg; | |
3533 | expressionS *ep; | |
3534 | int dbl; | |
3535 | { | |
3536 | int freg; | |
3537 | expressionS hi32, lo32; | |
3538 | ||
3539 | if (ep->X_op != O_big) | |
3540 | { | |
3541 | assert (ep->X_op == O_constant); | |
3542 | if (ep->X_add_number < 0x8000 | |
3543 | && (ep->X_add_number >= 0 | |
3544 | || (ep->X_add_number >= -0x8000 | |
3545 | && (! dbl | |
3546 | || ! ep->X_unsigned | |
3547 | || sizeof (ep->X_add_number) > 4)))) | |
3548 | { | |
3549 | /* We can handle 16 bit signed values with an addiu to | |
3550 | $zero. No need to ever use daddiu here, since $zero and | |
3551 | the result are always correct in 32 bit mode. */ | |
3552 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3553 | (int) BFD_RELOC_LO16); | |
3554 | return; | |
3555 | } | |
3556 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3557 | { | |
3558 | /* We can handle 16 bit unsigned values with an ori to | |
3559 | $zero. */ | |
3560 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3561 | (int) BFD_RELOC_LO16); | |
3562 | return; | |
3563 | } | |
6373ee54 | 3564 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3565 | && (! dbl |
3566 | || ! ep->X_unsigned | |
3567 | || sizeof (ep->X_add_number) > 4 | |
3568 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3569 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3570 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3571 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3572 | && ! dbl |
3573 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3574 | == ~ (offsetT) 0xffffffff))) | |
3575 | { | |
3576 | /* 32 bit values require an lui. */ | |
3577 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3578 | (int) BFD_RELOC_HI16); | |
3579 | if ((ep->X_add_number & 0xffff) != 0) | |
3580 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3581 | (int) BFD_RELOC_LO16); | |
3582 | return; | |
3583 | } | |
3584 | } | |
3585 | ||
3586 | /* The value is larger than 32 bits. */ | |
3587 | ||
ca4e0257 | 3588 | if (HAVE_32BIT_GPRS) |
252b5132 | 3589 | { |
956cd1d6 TS |
3590 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3591 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3592 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3593 | (int) BFD_RELOC_LO16); | |
3594 | return; | |
3595 | } | |
3596 | ||
3597 | if (ep->X_op != O_big) | |
3598 | { | |
3599 | hi32 = *ep; | |
3600 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3601 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3602 | hi32.X_add_number &= 0xffffffff; | |
3603 | lo32 = *ep; | |
3604 | lo32.X_add_number &= 0xffffffff; | |
3605 | } | |
3606 | else | |
3607 | { | |
3608 | assert (ep->X_add_number > 2); | |
3609 | if (ep->X_add_number == 3) | |
3610 | generic_bignum[3] = 0; | |
3611 | else if (ep->X_add_number > 4) | |
3612 | as_bad (_("Number larger than 64 bits")); | |
3613 | lo32.X_op = O_constant; | |
3614 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3615 | hi32.X_op = O_constant; | |
3616 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3617 | } | |
3618 | ||
3619 | if (hi32.X_add_number == 0) | |
3620 | freg = 0; | |
3621 | else | |
3622 | { | |
3623 | int shift, bit; | |
3624 | unsigned long hi, lo; | |
3625 | ||
956cd1d6 | 3626 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3627 | { |
3628 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3629 | { | |
3630 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3631 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3632 | return; |
3633 | } | |
3634 | if (lo32.X_add_number & 0x80000000) | |
3635 | { | |
3636 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3637 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3638 | if (lo32.X_add_number & 0xffff) |
3639 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3640 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3641 | return; |
3642 | } | |
3643 | } | |
252b5132 RH |
3644 | |
3645 | /* Check for 16bit shifted constant. We know that hi32 is | |
3646 | non-zero, so start the mask on the first bit of the hi32 | |
3647 | value. */ | |
3648 | shift = 17; | |
3649 | do | |
beae10d5 KH |
3650 | { |
3651 | unsigned long himask, lomask; | |
3652 | ||
3653 | if (shift < 32) | |
3654 | { | |
3655 | himask = 0xffff >> (32 - shift); | |
3656 | lomask = (0xffff << shift) & 0xffffffff; | |
3657 | } | |
3658 | else | |
3659 | { | |
3660 | himask = 0xffff << (shift - 32); | |
3661 | lomask = 0; | |
3662 | } | |
3663 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3664 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3665 | { | |
3666 | expressionS tmp; | |
3667 | ||
3668 | tmp.X_op = O_constant; | |
3669 | if (shift < 32) | |
3670 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3671 | | (lo32.X_add_number >> shift)); | |
3672 | else | |
3673 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3674 | macro_build ((char *) NULL, counter, &tmp, | |
3675 | "ori", "t,r,i", reg, 0, | |
3676 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3677 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3678 | (shift >= 32) ? "dsll32" : "dsll", |
3679 | "d,w,<", reg, reg, | |
3680 | (shift >= 32) ? shift - 32 : shift); | |
3681 | return; | |
3682 | } | |
f9419b05 | 3683 | ++shift; |
beae10d5 KH |
3684 | } |
3685 | while (shift <= (64 - 16)); | |
252b5132 RH |
3686 | |
3687 | /* Find the bit number of the lowest one bit, and store the | |
3688 | shifted value in hi/lo. */ | |
3689 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3690 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3691 | if (lo != 0) | |
3692 | { | |
3693 | bit = 0; | |
3694 | while ((lo & 1) == 0) | |
3695 | { | |
3696 | lo >>= 1; | |
3697 | ++bit; | |
3698 | } | |
3699 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3700 | hi >>= bit; | |
3701 | } | |
3702 | else | |
3703 | { | |
3704 | bit = 32; | |
3705 | while ((hi & 1) == 0) | |
3706 | { | |
3707 | hi >>= 1; | |
3708 | ++bit; | |
3709 | } | |
3710 | lo = hi; | |
3711 | hi = 0; | |
3712 | } | |
3713 | ||
3714 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3715 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3716 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3717 | { |
3718 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3719 | if (shift != 0) |
beae10d5 | 3720 | { |
252b5132 RH |
3721 | expressionS tmp; |
3722 | ||
3723 | /* This instruction will set the register to be all | |
3724 | ones. */ | |
beae10d5 KH |
3725 | tmp.X_op = O_constant; |
3726 | tmp.X_add_number = (offsetT) -1; | |
3727 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3728 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3729 | if (bit != 0) |
3730 | { | |
3731 | bit += shift; | |
2396cfb9 | 3732 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3733 | (bit >= 32) ? "dsll32" : "dsll", |
3734 | "d,w,<", reg, reg, | |
3735 | (bit >= 32) ? bit - 32 : bit); | |
3736 | } | |
2396cfb9 | 3737 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3738 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3739 | "d,w,<", reg, reg, |
252b5132 | 3740 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3741 | return; |
3742 | } | |
3743 | } | |
252b5132 RH |
3744 | |
3745 | /* Sign extend hi32 before calling load_register, because we can | |
3746 | generally get better code when we load a sign extended value. */ | |
3747 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3748 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3749 | load_register (counter, reg, &hi32, 0); |
3750 | freg = reg; | |
3751 | } | |
3752 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3753 | { | |
3754 | if (freg != 0) | |
3755 | { | |
2396cfb9 TS |
3756 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3757 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3758 | freg = reg; |
3759 | } | |
3760 | } | |
3761 | else | |
3762 | { | |
3763 | expressionS mid16; | |
3764 | ||
956cd1d6 | 3765 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3766 | { |
252b5132 RH |
3767 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3768 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3769 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3770 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3771 | return; |
3772 | } | |
252b5132 RH |
3773 | |
3774 | if (freg != 0) | |
3775 | { | |
956cd1d6 TS |
3776 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3777 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3778 | freg = reg; |
3779 | } | |
3780 | mid16 = lo32; | |
3781 | mid16.X_add_number >>= 16; | |
3782 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3783 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3784 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3785 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3786 | freg = reg; |
3787 | } | |
3788 | if ((lo32.X_add_number & 0xffff) != 0) | |
3789 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3790 | (int) BFD_RELOC_LO16); | |
3791 | } | |
3792 | ||
3793 | /* Load an address into a register. */ | |
3794 | ||
3795 | static void | |
c9914766 | 3796 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3797 | int *counter; |
3798 | int reg; | |
3799 | expressionS *ep; | |
d6bc6245 | 3800 | int *used_at; |
252b5132 | 3801 | { |
f9419b05 | 3802 | char *p = NULL; |
252b5132 RH |
3803 | |
3804 | if (ep->X_op != O_constant | |
3805 | && ep->X_op != O_symbol) | |
3806 | { | |
3807 | as_bad (_("expression too complex")); | |
3808 | ep->X_op = O_constant; | |
3809 | } | |
3810 | ||
3811 | if (ep->X_op == O_constant) | |
3812 | { | |
c9914766 | 3813 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3814 | return; |
3815 | } | |
3816 | ||
3817 | if (mips_pic == NO_PIC) | |
3818 | { | |
3819 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3820 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3821 | Otherwise we want |
3822 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3823 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3824 | If we have an addend, we always use the latter form. |
76b3015f | 3825 | |
d6bc6245 TS |
3826 | With 64bit address space and a usable $at we want |
3827 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3828 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3829 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3830 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3831 | dsll32 $reg,0 | |
3a482fd5 | 3832 | daddu $reg,$reg,$at |
76b3015f | 3833 | |
c03099e6 | 3834 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3835 | on superscalar processors. |
3836 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3837 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3838 | dsll $reg,16 | |
3839 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3840 | dsll $reg,16 | |
3841 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3842 | */ | |
c9914766 | 3843 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3844 | { |
d6bc6245 TS |
3845 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3846 | hold the data for such large chunks. */ | |
3847 | ||
460597ba | 3848 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3849 | { |
3850 | macro_build (p, counter, ep, "lui", "t,u", | |
3851 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3852 | macro_build (p, counter, ep, "lui", "t,u", | |
3853 | AT, (int) BFD_RELOC_HI16_S); | |
3854 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3855 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3856 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3857 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3858 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3859 | "d,w,<", reg, reg, 0); | |
3a482fd5 | 3860 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
2396cfb9 | 3861 | "d,v,t", reg, reg, AT); |
d6bc6245 TS |
3862 | *used_at = 1; |
3863 | } | |
3864 | else | |
3865 | { | |
3866 | macro_build (p, counter, ep, "lui", "t,u", | |
3867 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3868 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3869 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3870 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3871 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3872 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3873 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3874 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3875 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3876 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3877 | reg, reg, (int) BFD_RELOC_LO16); | |
3878 | } | |
3879 | } | |
252b5132 RH |
3880 | else |
3881 | { | |
d6bc6245 TS |
3882 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3883 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3884 | { | |
3885 | frag_grow (20); | |
f899b4b8 TS |
3886 | macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN, |
3887 | "t,r,j", reg, mips_gp_register, | |
3888 | (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3889 | p = frag_var (rs_machine_dependent, 8, 0, |
3890 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3891 | mips_opts.warn_about_macros), | |
956cd1d6 | 3892 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3893 | } |
3894 | macro_build_lui (p, counter, ep, reg); | |
3895 | if (p != NULL) | |
3896 | p += 4; | |
f899b4b8 | 3897 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
d6bc6245 TS |
3898 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3899 | } | |
252b5132 RH |
3900 | } |
3901 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3902 | { | |
3903 | expressionS ex; | |
3904 | ||
3905 | /* If this is a reference to an external symbol, we want | |
3906 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3907 | Otherwise we want | |
3908 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3909 | nop | |
3910 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3911 | If there is a constant, it must be added in after. |
3912 | ||
ed6fb7bd | 3913 | If we have NewABI, we want |
f5040a92 AO |
3914 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3915 | unless we're referencing a global symbol with a non-zero | |
3916 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3917 | if (HAVE_NEWABI) |
3918 | { | |
f5040a92 | 3919 | frag_grow (12); |
684022ea | 3920 | |
f5040a92 AO |
3921 | if (ep->X_add_number) |
3922 | { | |
3923 | frag_now->tc_frag_data.tc_fr_offset = | |
3924 | ex.X_add_number = ep->X_add_number; | |
3925 | ep->X_add_number = 0; | |
f899b4b8 TS |
3926 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, |
3927 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_DISP, | |
3928 | mips_gp_register); | |
f5040a92 AO |
3929 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3930 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3931 | ex.X_op = O_constant; | |
f899b4b8 | 3932 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
3933 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3934 | p = frag_var (rs_machine_dependent, 8, 0, | |
3935 | RELAX_ENCODE (8, 4, 0, 0, 0, | |
3936 | mips_opts.warn_about_macros), | |
3937 | ep->X_add_symbol, 0, (char *) NULL); | |
3938 | ep->X_add_number = ex.X_add_number; | |
3939 | } | |
3940 | ||
f899b4b8 | 3941 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
ed6fb7bd | 3942 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
f5040a92 AO |
3943 | |
3944 | if (! p) | |
3945 | { | |
3946 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3947 | that this does not become a variant frag. */ | |
3948 | frag_wane (frag_now); | |
3949 | frag_new (0); | |
3950 | } | |
ed6fb7bd SC |
3951 | } |
3952 | else | |
3953 | { | |
f5040a92 AO |
3954 | ex.X_add_number = ep->X_add_number; |
3955 | ep->X_add_number = 0; | |
3956 | frag_grow (20); | |
f899b4b8 TS |
3957 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, |
3958 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, | |
3959 | mips_gp_register); | |
ed6fb7bd SC |
3960 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
3961 | p = frag_var (rs_machine_dependent, 4, 0, | |
3962 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3963 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
f899b4b8 | 3964 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
ed6fb7bd | 3965 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
ed6fb7bd | 3966 | |
f5040a92 AO |
3967 | if (ex.X_add_number != 0) |
3968 | { | |
3969 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3970 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3971 | ex.X_op = O_constant; | |
f899b4b8 | 3972 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
3973 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3974 | } | |
252b5132 RH |
3975 | } |
3976 | } | |
3977 | else if (mips_pic == SVR4_PIC) | |
3978 | { | |
3979 | expressionS ex; | |
3980 | int off; | |
3981 | ||
3982 | /* This is the large GOT case. If this is a reference to an | |
3983 | external symbol, we want | |
3984 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3985 | addu $reg,$reg,$gp | |
3986 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3987 | |
3988 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3989 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3990 | nop | |
3991 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3992 | If there is a constant, it must be added in after. |
f5040a92 AO |
3993 | |
3994 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3995 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3996 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3997 | */ |
438c16b8 TS |
3998 | if (HAVE_NEWABI) |
3999 | { | |
f5040a92 AO |
4000 | frag_grow (24); |
4001 | ||
4002 | frag_now->tc_frag_data.tc_fr_offset = | |
4003 | ex.X_add_number = ep->X_add_number; | |
4004 | ep->X_add_number = 0; | |
4005 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
4006 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
4007 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
f899b4b8 TS |
4008 | ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
4009 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
4010 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
4011 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4012 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4013 | else if (ex.X_add_number) | |
4014 | { | |
4015 | ex.X_op = O_constant; | |
f899b4b8 | 4016 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
4017 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4018 | } | |
4019 | ||
4020 | ep->X_add_number = ex.X_add_number; | |
4021 | p = frag_var (rs_machine_dependent, 8, 0, | |
4022 | RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0, | |
4023 | mips_opts.warn_about_macros), | |
4024 | ep->X_add_symbol, 0, (char *) NULL); | |
f899b4b8 | 4025 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
438c16b8 | 4026 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 4027 | macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", |
438c16b8 TS |
4028 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); |
4029 | } | |
252b5132 | 4030 | else |
438c16b8 | 4031 | { |
f5040a92 AO |
4032 | ex.X_add_number = ep->X_add_number; |
4033 | ep->X_add_number = 0; | |
438c16b8 TS |
4034 | if (reg_needs_delay (mips_gp_register)) |
4035 | off = 4; | |
4036 | else | |
4037 | off = 0; | |
4038 | frag_grow (32); | |
4039 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
4040 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
4041 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
f899b4b8 TS |
4042 | ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
4043 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, | |
438c16b8 TS |
4044 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
4045 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
4046 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
4047 | mips_opts.warn_about_macros), | |
4048 | ep->X_add_symbol, 0, NULL); | |
4049 | if (off > 0) | |
4050 | { | |
4051 | /* We need a nop before loading from $gp. This special | |
4052 | check is required because the lui which starts the main | |
4053 | instruction stream does not refer to $gp, and so will not | |
4054 | insert the nop which may be required. */ | |
4055 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
4056 | p += 4; | |
4057 | } | |
f899b4b8 | 4058 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
438c16b8 TS |
4059 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
4060 | p += 4; | |
252b5132 RH |
4061 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
4062 | p += 4; | |
f899b4b8 | 4063 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
438c16b8 | 4064 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
438c16b8 | 4065 | |
f5040a92 AO |
4066 | if (ex.X_add_number != 0) |
4067 | { | |
4068 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4069 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4070 | ex.X_op = O_constant; | |
f899b4b8 | 4071 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
4072 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4073 | } | |
252b5132 RH |
4074 | } |
4075 | } | |
4076 | else if (mips_pic == EMBEDDED_PIC) | |
4077 | { | |
4078 | /* We always do | |
cdf6fd85 | 4079 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 4080 | */ |
f899b4b8 | 4081 | macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN, |
c9914766 | 4082 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
4083 | } |
4084 | else | |
4085 | abort (); | |
4086 | } | |
4087 | ||
ea1fb5dc RS |
4088 | /* Move the contents of register SOURCE into register DEST. */ |
4089 | ||
4090 | static void | |
4091 | move_register (counter, dest, source) | |
4092 | int *counter; | |
4093 | int dest; | |
4094 | int source; | |
4095 | { | |
4096 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
4097 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
4098 | "d,v,t", dest, source, 0); | |
4099 | } | |
4100 | ||
252b5132 RH |
4101 | /* |
4102 | * Build macros | |
4103 | * This routine implements the seemingly endless macro or synthesized | |
4104 | * instructions and addressing modes in the mips assembly language. Many | |
4105 | * of these macros are simple and are similar to each other. These could | |
4106 | * probably be handled by some kind of table or grammer aproach instead of | |
4107 | * this verbose method. Others are not simple macros but are more like | |
4108 | * optimizing code generation. | |
4109 | * One interesting optimization is when several store macros appear | |
4110 | * consecutivly that would load AT with the upper half of the same address. | |
4111 | * The ensuing load upper instructions are ommited. This implies some kind | |
4112 | * of global optimization. We currently only optimize within a single macro. | |
4113 | * For many of the load and store macros if the address is specified as a | |
4114 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4115 | * first load register 'at' with zero and use it as the base register. The | |
4116 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4117 | * we're missing. | |
4118 | */ | |
4119 | static void | |
4120 | macro (ip) | |
4121 | struct mips_cl_insn *ip; | |
4122 | { | |
4123 | register int treg, sreg, dreg, breg; | |
4124 | int tempreg; | |
4125 | int mask; | |
4126 | int icnt = 0; | |
43841e91 | 4127 | int used_at = 0; |
252b5132 RH |
4128 | expressionS expr1; |
4129 | const char *s; | |
4130 | const char *s2; | |
4131 | const char *fmt; | |
4132 | int likely = 0; | |
4133 | int dbl = 0; | |
4134 | int coproc = 0; | |
4135 | int lr = 0; | |
4136 | int imm = 0; | |
4137 | offsetT maxnum; | |
4138 | int off; | |
4139 | bfd_reloc_code_real_type r; | |
252b5132 RH |
4140 | int hold_mips_optimize; |
4141 | ||
4142 | assert (! mips_opts.mips16); | |
4143 | ||
4144 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4145 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4146 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4147 | mask = ip->insn_mo->mask; | |
4148 | ||
4149 | expr1.X_op = O_constant; | |
4150 | expr1.X_op_symbol = NULL; | |
4151 | expr1.X_add_symbol = NULL; | |
4152 | expr1.X_add_number = 1; | |
4153 | ||
5919d012 RS |
4154 | /* Umatched fixups should not be put in the same frag as a relaxable |
4155 | macro. For example, suppose we have: | |
4156 | ||
4157 | lui $4,%hi(l1) # 1 | |
4158 | la $5,l2 # 2 | |
4159 | addiu $4,$4,%lo(l1) # 3 | |
4160 | ||
4161 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
4162 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
4163 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
4164 | for #2 to be the last for that frag. | |
4165 | ||
64bdfcaf RS |
4166 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
4167 | it assumes that they belong to a relaxable macro. We mustn't put | |
4168 | other uses of such relocations into a variant frag. | |
4169 | ||
4170 | To avoid both problems, finish the current frag it contains a | |
4171 | %reloc() operator. The macro then goes into a new frag. */ | |
4172 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
4173 | { |
4174 | frag_wane (frag_now); | |
4175 | frag_new (0); | |
4176 | } | |
4177 | ||
252b5132 RH |
4178 | switch (mask) |
4179 | { | |
4180 | case M_DABS: | |
4181 | dbl = 1; | |
4182 | case M_ABS: | |
4183 | /* bgez $a0,.+12 | |
4184 | move v0,$a0 | |
4185 | sub v0,$zero,$a0 | |
4186 | */ | |
4187 | ||
b34976b6 | 4188 | mips_emit_delays (TRUE); |
252b5132 RH |
4189 | ++mips_opts.noreorder; |
4190 | mips_any_noreorder = 1; | |
4191 | ||
4192 | expr1.X_add_number = 8; | |
4193 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4194 | if (dreg == sreg) | |
2396cfb9 TS |
4195 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4196 | 0); | |
252b5132 | 4197 | else |
ea1fb5dc | 4198 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4200 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4201 | |
4202 | --mips_opts.noreorder; | |
4203 | return; | |
4204 | ||
4205 | case M_ADD_I: | |
4206 | s = "addi"; | |
4207 | s2 = "add"; | |
4208 | goto do_addi; | |
4209 | case M_ADDU_I: | |
4210 | s = "addiu"; | |
4211 | s2 = "addu"; | |
4212 | goto do_addi; | |
4213 | case M_DADD_I: | |
4214 | dbl = 1; | |
4215 | s = "daddi"; | |
4216 | s2 = "dadd"; | |
4217 | goto do_addi; | |
4218 | case M_DADDU_I: | |
4219 | dbl = 1; | |
4220 | s = "daddiu"; | |
4221 | s2 = "daddu"; | |
4222 | do_addi: | |
4223 | if (imm_expr.X_op == O_constant | |
4224 | && imm_expr.X_add_number >= -0x8000 | |
4225 | && imm_expr.X_add_number < 0x8000) | |
4226 | { | |
4227 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4228 | (int) BFD_RELOC_LO16); | |
4229 | return; | |
4230 | } | |
4231 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4232 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4233 | treg, sreg, AT); | |
252b5132 RH |
4234 | break; |
4235 | ||
4236 | case M_AND_I: | |
4237 | s = "andi"; | |
4238 | s2 = "and"; | |
4239 | goto do_bit; | |
4240 | case M_OR_I: | |
4241 | s = "ori"; | |
4242 | s2 = "or"; | |
4243 | goto do_bit; | |
4244 | case M_NOR_I: | |
4245 | s = ""; | |
4246 | s2 = "nor"; | |
4247 | goto do_bit; | |
4248 | case M_XOR_I: | |
4249 | s = "xori"; | |
4250 | s2 = "xor"; | |
4251 | do_bit: | |
4252 | if (imm_expr.X_op == O_constant | |
4253 | && imm_expr.X_add_number >= 0 | |
4254 | && imm_expr.X_add_number < 0x10000) | |
4255 | { | |
4256 | if (mask != M_NOR_I) | |
4257 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4258 | sreg, (int) BFD_RELOC_LO16); | |
4259 | else | |
4260 | { | |
4261 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4262 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4264 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4265 | } |
4266 | return; | |
4267 | } | |
4268 | ||
d6bc6245 | 4269 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4270 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4271 | treg, sreg, AT); | |
252b5132 RH |
4272 | break; |
4273 | ||
4274 | case M_BEQ_I: | |
4275 | s = "beq"; | |
4276 | goto beq_i; | |
4277 | case M_BEQL_I: | |
4278 | s = "beql"; | |
4279 | likely = 1; | |
4280 | goto beq_i; | |
4281 | case M_BNE_I: | |
4282 | s = "bne"; | |
4283 | goto beq_i; | |
4284 | case M_BNEL_I: | |
4285 | s = "bnel"; | |
4286 | likely = 1; | |
4287 | beq_i: | |
4288 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4289 | { | |
4290 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4291 | 0); | |
4292 | return; | |
4293 | } | |
4d34fb5f | 4294 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4295 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4296 | break; | |
4297 | ||
4298 | case M_BGEL: | |
4299 | likely = 1; | |
4300 | case M_BGE: | |
4301 | if (treg == 0) | |
4302 | { | |
4303 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4304 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4305 | return; |
4306 | } | |
4307 | if (sreg == 0) | |
4308 | { | |
4309 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4310 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4311 | return; |
4312 | } | |
2396cfb9 TS |
4313 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4314 | AT, sreg, treg); | |
252b5132 | 4315 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4316 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4317 | break; |
4318 | ||
4319 | case M_BGTL_I: | |
4320 | likely = 1; | |
4321 | case M_BGT_I: | |
4322 | /* check for > max integer */ | |
4323 | maxnum = 0x7fffffff; | |
ca4e0257 | 4324 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4325 | { |
4326 | maxnum <<= 16; | |
4327 | maxnum |= 0xffff; | |
4328 | maxnum <<= 16; | |
4329 | maxnum |= 0xffff; | |
4330 | } | |
4331 | if (imm_expr.X_op == O_constant | |
4332 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4333 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4334 | { |
4335 | do_false: | |
4336 | /* result is always false */ | |
4337 | if (! likely) | |
4338 | { | |
39c0a331 L |
4339 | if (warn_nops) |
4340 | as_warn (_("Branch %s is always false (nop)"), | |
4341 | ip->insn_mo->name); | |
2396cfb9 TS |
4342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4343 | "", 0); | |
252b5132 RH |
4344 | } |
4345 | else | |
4346 | { | |
39c0a331 L |
4347 | if (warn_nops) |
4348 | as_warn (_("Branch likely %s is always false"), | |
4349 | ip->insn_mo->name); | |
252b5132 RH |
4350 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4351 | "s,t,p", 0, 0); | |
4352 | } | |
4353 | return; | |
4354 | } | |
4355 | if (imm_expr.X_op != O_constant) | |
4356 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4357 | ++imm_expr.X_add_number; |
252b5132 RH |
4358 | /* FALLTHROUGH */ |
4359 | case M_BGE_I: | |
4360 | case M_BGEL_I: | |
4361 | if (mask == M_BGEL_I) | |
4362 | likely = 1; | |
4363 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4364 | { | |
4365 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4366 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4367 | return; |
4368 | } | |
4369 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4370 | { | |
4371 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4372 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4373 | return; |
4374 | } | |
4375 | maxnum = 0x7fffffff; | |
ca4e0257 | 4376 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4377 | { |
4378 | maxnum <<= 16; | |
4379 | maxnum |= 0xffff; | |
4380 | maxnum <<= 16; | |
4381 | maxnum |= 0xffff; | |
4382 | } | |
4383 | maxnum = - maxnum - 1; | |
4384 | if (imm_expr.X_op == O_constant | |
4385 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4386 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4387 | { |
4388 | do_true: | |
4389 | /* result is always true */ | |
4390 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4391 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4392 | return; | |
4393 | } | |
4394 | set_at (&icnt, sreg, 0); | |
4395 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4396 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4397 | break; |
4398 | ||
4399 | case M_BGEUL: | |
4400 | likely = 1; | |
4401 | case M_BGEU: | |
4402 | if (treg == 0) | |
4403 | goto do_true; | |
4404 | if (sreg == 0) | |
4405 | { | |
4406 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4407 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4408 | return; |
4409 | } | |
2396cfb9 TS |
4410 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4411 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4412 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4413 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4414 | break; |
4415 | ||
4416 | case M_BGTUL_I: | |
4417 | likely = 1; | |
4418 | case M_BGTU_I: | |
4419 | if (sreg == 0 | |
ca4e0257 | 4420 | || (HAVE_32BIT_GPRS |
252b5132 | 4421 | && imm_expr.X_op == O_constant |
956cd1d6 | 4422 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4423 | goto do_false; |
4424 | if (imm_expr.X_op != O_constant) | |
4425 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4426 | ++imm_expr.X_add_number; |
252b5132 RH |
4427 | /* FALLTHROUGH */ |
4428 | case M_BGEU_I: | |
4429 | case M_BGEUL_I: | |
4430 | if (mask == M_BGEUL_I) | |
4431 | likely = 1; | |
4432 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4433 | goto do_true; | |
4434 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4435 | { | |
4436 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4437 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4438 | return; |
4439 | } | |
4440 | set_at (&icnt, sreg, 1); | |
4441 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4442 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4443 | break; |
4444 | ||
4445 | case M_BGTL: | |
4446 | likely = 1; | |
4447 | case M_BGT: | |
4448 | if (treg == 0) | |
4449 | { | |
4450 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4451 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4452 | return; |
4453 | } | |
4454 | if (sreg == 0) | |
4455 | { | |
4456 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4457 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4458 | return; |
4459 | } | |
2396cfb9 TS |
4460 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4461 | AT, treg, sreg); | |
252b5132 | 4462 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4463 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4464 | break; |
4465 | ||
4466 | case M_BGTUL: | |
4467 | likely = 1; | |
4468 | case M_BGTU: | |
4469 | if (treg == 0) | |
4470 | { | |
4471 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4472 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4473 | return; |
4474 | } | |
4475 | if (sreg == 0) | |
4476 | goto do_false; | |
2396cfb9 TS |
4477 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4478 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4479 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4480 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4481 | break; |
4482 | ||
4483 | case M_BLEL: | |
4484 | likely = 1; | |
4485 | case M_BLE: | |
4486 | if (treg == 0) | |
4487 | { | |
4488 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4489 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4490 | return; |
4491 | } | |
4492 | if (sreg == 0) | |
4493 | { | |
4494 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4495 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4496 | return; |
4497 | } | |
2396cfb9 TS |
4498 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4499 | AT, treg, sreg); | |
252b5132 | 4500 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4501 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4502 | break; |
4503 | ||
4504 | case M_BLEL_I: | |
4505 | likely = 1; | |
4506 | case M_BLE_I: | |
4507 | maxnum = 0x7fffffff; | |
ca4e0257 | 4508 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4509 | { |
4510 | maxnum <<= 16; | |
4511 | maxnum |= 0xffff; | |
4512 | maxnum <<= 16; | |
4513 | maxnum |= 0xffff; | |
4514 | } | |
4515 | if (imm_expr.X_op == O_constant | |
4516 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4517 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4518 | goto do_true; |
4519 | if (imm_expr.X_op != O_constant) | |
4520 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4521 | ++imm_expr.X_add_number; |
252b5132 RH |
4522 | /* FALLTHROUGH */ |
4523 | case M_BLT_I: | |
4524 | case M_BLTL_I: | |
4525 | if (mask == M_BLTL_I) | |
4526 | likely = 1; | |
4527 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4528 | { | |
4529 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4530 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4531 | return; |
4532 | } | |
4533 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4534 | { | |
4535 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4536 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4537 | return; |
4538 | } | |
4539 | set_at (&icnt, sreg, 0); | |
4540 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4541 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4542 | break; |
4543 | ||
4544 | case M_BLEUL: | |
4545 | likely = 1; | |
4546 | case M_BLEU: | |
4547 | if (treg == 0) | |
4548 | { | |
4549 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4550 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4551 | return; |
4552 | } | |
4553 | if (sreg == 0) | |
4554 | goto do_true; | |
2396cfb9 TS |
4555 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4556 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4557 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4558 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4559 | break; |
4560 | ||
4561 | case M_BLEUL_I: | |
4562 | likely = 1; | |
4563 | case M_BLEU_I: | |
4564 | if (sreg == 0 | |
ca4e0257 | 4565 | || (HAVE_32BIT_GPRS |
252b5132 | 4566 | && imm_expr.X_op == O_constant |
956cd1d6 | 4567 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4568 | goto do_true; |
4569 | if (imm_expr.X_op != O_constant) | |
4570 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4571 | ++imm_expr.X_add_number; |
252b5132 RH |
4572 | /* FALLTHROUGH */ |
4573 | case M_BLTU_I: | |
4574 | case M_BLTUL_I: | |
4575 | if (mask == M_BLTUL_I) | |
4576 | likely = 1; | |
4577 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4578 | goto do_false; | |
4579 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4580 | { | |
4581 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4582 | likely ? "beql" : "beq", | |
4583 | "s,t,p", sreg, 0); | |
4584 | return; | |
4585 | } | |
4586 | set_at (&icnt, sreg, 1); | |
4587 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4588 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4589 | break; |
4590 | ||
4591 | case M_BLTL: | |
4592 | likely = 1; | |
4593 | case M_BLT: | |
4594 | if (treg == 0) | |
4595 | { | |
4596 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4597 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4598 | return; |
4599 | } | |
4600 | if (sreg == 0) | |
4601 | { | |
4602 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4603 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4604 | return; |
4605 | } | |
2396cfb9 TS |
4606 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4607 | AT, sreg, treg); | |
252b5132 | 4608 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4609 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4610 | break; |
4611 | ||
4612 | case M_BLTUL: | |
4613 | likely = 1; | |
4614 | case M_BLTU: | |
4615 | if (treg == 0) | |
4616 | goto do_false; | |
4617 | if (sreg == 0) | |
4618 | { | |
4619 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4620 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4621 | return; |
4622 | } | |
2396cfb9 TS |
4623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4624 | "d,v,t", AT, sreg, | |
252b5132 RH |
4625 | treg); |
4626 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4627 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4628 | break; |
4629 | ||
4630 | case M_DDIV_3: | |
4631 | dbl = 1; | |
4632 | case M_DIV_3: | |
4633 | s = "mflo"; | |
4634 | goto do_div3; | |
4635 | case M_DREM_3: | |
4636 | dbl = 1; | |
4637 | case M_REM_3: | |
4638 | s = "mfhi"; | |
4639 | do_div3: | |
4640 | if (treg == 0) | |
4641 | { | |
4642 | as_warn (_("Divide by zero.")); | |
4643 | if (mips_trap) | |
2396cfb9 | 4644 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4645 | "s,t,q", 0, 0, 7); |
252b5132 | 4646 | else |
2396cfb9 TS |
4647 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4648 | "c", 7); | |
252b5132 RH |
4649 | return; |
4650 | } | |
4651 | ||
b34976b6 | 4652 | mips_emit_delays (TRUE); |
252b5132 RH |
4653 | ++mips_opts.noreorder; |
4654 | mips_any_noreorder = 1; | |
4655 | if (mips_trap) | |
4656 | { | |
2396cfb9 | 4657 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4658 | "s,t,q", treg, 0, 7); |
2396cfb9 | 4659 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4660 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4661 | } |
4662 | else | |
4663 | { | |
4664 | expr1.X_add_number = 8; | |
4665 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4666 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4667 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4668 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4669 | "c", 7); | |
252b5132 RH |
4670 | } |
4671 | expr1.X_add_number = -1; | |
4672 | macro_build ((char *) NULL, &icnt, &expr1, | |
4673 | dbl ? "daddiu" : "addiu", | |
4674 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4675 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4676 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4677 | if (dbl) | |
4678 | { | |
4679 | expr1.X_add_number = 1; | |
4680 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4681 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4682 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4683 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4684 | } |
4685 | else | |
4686 | { | |
4687 | expr1.X_add_number = 0x80000000; | |
4688 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4689 | (int) BFD_RELOC_HI16); | |
4690 | } | |
4691 | if (mips_trap) | |
4692 | { | |
2396cfb9 | 4693 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4694 | "s,t,q", sreg, AT, 6); |
252b5132 RH |
4695 | /* We want to close the noreorder block as soon as possible, so |
4696 | that later insns are available for delay slot filling. */ | |
4697 | --mips_opts.noreorder; | |
4698 | } | |
4699 | else | |
4700 | { | |
4701 | expr1.X_add_number = 8; | |
4702 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4703 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4704 | 0); | |
252b5132 RH |
4705 | |
4706 | /* We want to close the noreorder block as soon as possible, so | |
4707 | that later insns are available for delay slot filling. */ | |
4708 | --mips_opts.noreorder; | |
4709 | ||
2396cfb9 TS |
4710 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4711 | "c", 6); | |
252b5132 | 4712 | } |
2396cfb9 | 4713 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4714 | break; |
4715 | ||
4716 | case M_DIV_3I: | |
4717 | s = "div"; | |
4718 | s2 = "mflo"; | |
4719 | goto do_divi; | |
4720 | case M_DIVU_3I: | |
4721 | s = "divu"; | |
4722 | s2 = "mflo"; | |
4723 | goto do_divi; | |
4724 | case M_REM_3I: | |
4725 | s = "div"; | |
4726 | s2 = "mfhi"; | |
4727 | goto do_divi; | |
4728 | case M_REMU_3I: | |
4729 | s = "divu"; | |
4730 | s2 = "mfhi"; | |
4731 | goto do_divi; | |
4732 | case M_DDIV_3I: | |
4733 | dbl = 1; | |
4734 | s = "ddiv"; | |
4735 | s2 = "mflo"; | |
4736 | goto do_divi; | |
4737 | case M_DDIVU_3I: | |
4738 | dbl = 1; | |
4739 | s = "ddivu"; | |
4740 | s2 = "mflo"; | |
4741 | goto do_divi; | |
4742 | case M_DREM_3I: | |
4743 | dbl = 1; | |
4744 | s = "ddiv"; | |
4745 | s2 = "mfhi"; | |
4746 | goto do_divi; | |
4747 | case M_DREMU_3I: | |
4748 | dbl = 1; | |
4749 | s = "ddivu"; | |
4750 | s2 = "mfhi"; | |
4751 | do_divi: | |
4752 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4753 | { | |
4754 | as_warn (_("Divide by zero.")); | |
4755 | if (mips_trap) | |
2396cfb9 | 4756 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4757 | "s,t,q", 0, 0, 7); |
252b5132 | 4758 | else |
2396cfb9 TS |
4759 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4760 | "c", 7); | |
252b5132 RH |
4761 | return; |
4762 | } | |
4763 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4764 | { | |
4765 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4766 | move_register (&icnt, dreg, sreg); |
252b5132 | 4767 | else |
ea1fb5dc | 4768 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4769 | return; |
4770 | } | |
4771 | if (imm_expr.X_op == O_constant | |
4772 | && imm_expr.X_add_number == -1 | |
4773 | && s[strlen (s) - 1] != 'u') | |
4774 | { | |
4775 | if (strcmp (s2, "mflo") == 0) | |
4776 | { | |
2396cfb9 TS |
4777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4778 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4779 | } |
4780 | else | |
ea1fb5dc | 4781 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4782 | return; |
4783 | } | |
4784 | ||
4785 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4786 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4787 | sreg, AT); | |
4788 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4789 | break; |
4790 | ||
4791 | case M_DIVU_3: | |
4792 | s = "divu"; | |
4793 | s2 = "mflo"; | |
4794 | goto do_divu3; | |
4795 | case M_REMU_3: | |
4796 | s = "divu"; | |
4797 | s2 = "mfhi"; | |
4798 | goto do_divu3; | |
4799 | case M_DDIVU_3: | |
4800 | s = "ddivu"; | |
4801 | s2 = "mflo"; | |
4802 | goto do_divu3; | |
4803 | case M_DREMU_3: | |
4804 | s = "ddivu"; | |
4805 | s2 = "mfhi"; | |
4806 | do_divu3: | |
b34976b6 | 4807 | mips_emit_delays (TRUE); |
252b5132 RH |
4808 | ++mips_opts.noreorder; |
4809 | mips_any_noreorder = 1; | |
4810 | if (mips_trap) | |
4811 | { | |
2396cfb9 | 4812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4813 | "s,t,q", treg, 0, 7); |
2396cfb9 TS |
4814 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4815 | sreg, treg); | |
252b5132 RH |
4816 | /* We want to close the noreorder block as soon as possible, so |
4817 | that later insns are available for delay slot filling. */ | |
4818 | --mips_opts.noreorder; | |
4819 | } | |
4820 | else | |
4821 | { | |
4822 | expr1.X_add_number = 8; | |
4823 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4824 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4825 | sreg, treg); | |
252b5132 RH |
4826 | |
4827 | /* We want to close the noreorder block as soon as possible, so | |
4828 | that later insns are available for delay slot filling. */ | |
4829 | --mips_opts.noreorder; | |
2396cfb9 TS |
4830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4831 | "c", 7); | |
252b5132 | 4832 | } |
2396cfb9 | 4833 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4834 | return; |
4835 | ||
4836 | case M_DLA_AB: | |
4837 | dbl = 1; | |
4838 | case M_LA_AB: | |
4839 | /* Load the address of a symbol into a register. If breg is not | |
4840 | zero, we then add a base register to it. */ | |
4841 | ||
3bec30a8 TS |
4842 | if (dbl && HAVE_32BIT_GPRS) |
4843 | as_warn (_("dla used to load 32-bit register")); | |
4844 | ||
c90bbe5b | 4845 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4846 | as_warn (_("la used to load 64-bit address")); |
4847 | ||
0c11417f MR |
4848 | if (offset_expr.X_op == O_constant |
4849 | && offset_expr.X_add_number >= -0x8000 | |
4850 | && offset_expr.X_add_number < 0x8000) | |
4851 | { | |
4852 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
b7c7d6c1 | 4853 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
0c11417f MR |
4854 | "t,r,j", treg, sreg, (int) BFD_RELOC_LO16); |
4855 | return; | |
4856 | } | |
4857 | ||
afdbd6d0 CD |
4858 | if (treg == breg) |
4859 | { | |
4860 | tempreg = AT; | |
4861 | used_at = 1; | |
4862 | } | |
4863 | else | |
4864 | { | |
4865 | tempreg = treg; | |
4866 | used_at = 0; | |
4867 | } | |
4868 | ||
252b5132 RH |
4869 | /* When generating embedded PIC code, we permit expressions of |
4870 | the form | |
afdbd6d0 CD |
4871 | la $treg,foo-bar |
4872 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4873 | where bar is an address in the current section. These are used |
252b5132 RH |
4874 | when getting the addresses of functions. We don't permit |
4875 | X_add_number to be non-zero, because if the symbol is | |
4876 | external the relaxing code needs to know that any addend is | |
4877 | purely the offset to X_op_symbol. */ | |
4878 | if (mips_pic == EMBEDDED_PIC | |
4879 | && offset_expr.X_op == O_subtract | |
49309057 | 4880 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4881 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4882 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4883 | && (S_GET_SEGMENT | |
4884 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4885 | ->X_add_symbol) | |
bb2d6cd7 | 4886 | == now_seg))) |
bb2d6cd7 GK |
4887 | && (offset_expr.X_add_number == 0 |
4888 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4889 | { |
afdbd6d0 CD |
4890 | if (breg == 0) |
4891 | { | |
4892 | tempreg = treg; | |
4893 | used_at = 0; | |
4894 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4895 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4896 | } | |
4897 | else | |
4898 | { | |
4899 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4900 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4901 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4902 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4903 | "d,v,t", tempreg, tempreg, breg); |
4904 | } | |
252b5132 | 4905 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4906 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4907 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4908 | if (! used_at) | |
4909 | return; | |
4910 | break; | |
252b5132 RH |
4911 | } |
4912 | ||
4913 | if (offset_expr.X_op != O_symbol | |
4914 | && offset_expr.X_op != O_constant) | |
4915 | { | |
4916 | as_bad (_("expression too complex")); | |
4917 | offset_expr.X_op = O_constant; | |
4918 | } | |
4919 | ||
252b5132 | 4920 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4921 | load_register (&icnt, tempreg, &offset_expr, |
4922 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4923 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4924 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4925 | else if (mips_pic == NO_PIC) |
4926 | { | |
d6bc6245 | 4927 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4928 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4929 | Otherwise we want |
4930 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4931 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4932 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4933 | so we may as well always use the latter form. |
76b3015f | 4934 | |
d6bc6245 TS |
4935 | With 64bit address space and a usable $at we want |
4936 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4937 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4938 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4939 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4940 | dsll32 $tempreg,0 | |
3a482fd5 | 4941 | daddu $tempreg,$tempreg,$at |
76b3015f | 4942 | |
c03099e6 | 4943 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4944 | on superscalar processors. |
4945 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4946 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4947 | dsll $tempreg,16 | |
4948 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4949 | dsll $tempreg,16 | |
4950 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4951 | */ | |
f9419b05 | 4952 | char *p = NULL; |
d6bc6245 | 4953 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4954 | { |
d6bc6245 TS |
4955 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4956 | hold the data for such large chunks. */ | |
4957 | ||
460597ba | 4958 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4959 | { |
4960 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4961 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4962 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4963 | AT, (int) BFD_RELOC_HI16_S); | |
4964 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4965 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4966 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4967 | AT, AT, (int) BFD_RELOC_LO16); | |
4968 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4969 | "d,w,<", tempreg, tempreg, 0); | |
3a482fd5 MR |
4970 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
4971 | "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4972 | used_at = 1; |
4973 | } | |
4974 | else | |
4975 | { | |
4976 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4977 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4978 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4979 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4980 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4981 | tempreg, tempreg, 16); | |
4982 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4983 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4984 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4985 | tempreg, tempreg, 16); | |
4986 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4987 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4988 | } | |
4989 | } | |
4990 | else | |
4991 | { | |
4992 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4993 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4994 | { | |
4995 | frag_grow (20); | |
f5040a92 | 4996 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 TS |
4997 | ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
4998 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4999 | p = frag_var (rs_machine_dependent, 8, 0, |
5000 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5001 | mips_opts.warn_about_macros), | |
5002 | offset_expr.X_add_symbol, 0, NULL); | |
5003 | } | |
5004 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5005 | if (p != NULL) | |
5006 | p += 4; | |
f899b4b8 | 5007 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
98d3f06f KH |
5008 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5009 | } | |
252b5132 | 5010 | } |
f5040a92 | 5011 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5012 | { |
9117d219 NC |
5013 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5014 | ||
252b5132 RH |
5015 | /* If this is a reference to an external symbol, and there |
5016 | is no constant, we want | |
5017 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
5018 | or if tempreg is PIC_CALL_REG |
5019 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
5020 | For a local symbol, we want |
5021 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5022 | nop | |
5023 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5024 | ||
5025 | If we have a small constant, and this is a reference to | |
5026 | an external symbol, we want | |
5027 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5028 | nop | |
5029 | addiu $tempreg,$tempreg,<constant> | |
5030 | For a local symbol, we want the same instruction | |
5031 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5032 | addiu instruction. | |
5033 | ||
5034 | If we have a large constant, and this is a reference to | |
5035 | an external symbol, we want | |
5036 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5037 | lui $at,<hiconstant> | |
5038 | addiu $at,$at,<loconstant> | |
5039 | addu $tempreg,$tempreg,$at | |
5040 | For a local symbol, we want the same instruction | |
5041 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5042 | addiu instruction. |
ed6fb7bd SC |
5043 | */ |
5044 | ||
252b5132 RH |
5045 | expr1.X_add_number = offset_expr.X_add_number; |
5046 | offset_expr.X_add_number = 0; | |
5047 | frag_grow (32); | |
9117d219 NC |
5048 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5049 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
f899b4b8 | 5050 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 | 5051 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
5052 | if (expr1.X_add_number == 0) |
5053 | { | |
5054 | int off; | |
f9419b05 | 5055 | char *p; |
252b5132 RH |
5056 | |
5057 | if (breg == 0) | |
5058 | off = 0; | |
5059 | else | |
5060 | { | |
5061 | /* We're going to put in an addu instruction using | |
5062 | tempreg, so we may as well insert the nop right | |
5063 | now. */ | |
5064 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5065 | "nop", ""); | |
5066 | off = 4; | |
5067 | } | |
5068 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
5069 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
5070 | (breg == 0 | |
5071 | ? mips_opts.warn_about_macros | |
5072 | : 0)), | |
c4e7957c | 5073 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5074 | if (breg == 0) |
5075 | { | |
5076 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5077 | p += 4; | |
5078 | } | |
f899b4b8 | 5079 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5080 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5081 | /* FIXME: If breg == 0, and the next instruction uses | |
5082 | $tempreg, then if this variant case is used an extra | |
5083 | nop will be generated. */ | |
5084 | } | |
5085 | else if (expr1.X_add_number >= -0x8000 | |
5086 | && expr1.X_add_number < 0x8000) | |
5087 | { | |
5088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5089 | "nop", ""); | |
f899b4b8 | 5090 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 | 5091 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
5092 | frag_var (rs_machine_dependent, 0, 0, |
5093 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
5094 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5095 | } |
5096 | else | |
5097 | { | |
5098 | int off1; | |
5099 | ||
5100 | /* If we are going to add in a base register, and the | |
5101 | target register and the base register are the same, | |
5102 | then we are using AT as a temporary register. Since | |
5103 | we want to load the constant into AT, we add our | |
5104 | current AT (from the global offset table) and the | |
5105 | register into the register now, and pretend we were | |
5106 | not using a base register. */ | |
5107 | if (breg != treg) | |
5108 | off1 = 0; | |
5109 | else | |
5110 | { | |
5111 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5112 | "nop", ""); | |
5113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5114 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5115 | breg = 0; |
5116 | tempreg = treg; | |
5117 | off1 = -8; | |
5118 | } | |
5119 | ||
5120 | /* Set mips_optimize around the lui instruction to avoid | |
5121 | inserting an unnecessary nop after the lw. */ | |
5122 | hold_mips_optimize = mips_optimize; | |
5123 | mips_optimize = 2; | |
c4e7957c | 5124 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5125 | mips_optimize = hold_mips_optimize; |
5126 | ||
f899b4b8 | 5127 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5128 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5129 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5130 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
5131 | frag_var (rs_machine_dependent, 0, 0, |
5132 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
5133 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5134 | used_at = 1; |
5135 | } | |
5136 | } | |
f5040a92 AO |
5137 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5138 | { | |
5139 | char *p = NULL; | |
5140 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
5141 | int adj = 0; | |
5142 | ||
5143 | /* If this is a reference to an external, and there is no | |
5144 | constant, or local symbol (*), with or without a | |
5145 | constant, we want | |
5146 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5147 | or if tempreg is PIC_CALL_REG | |
5148 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5149 | ||
5150 | If we have a small constant, and this is a reference to | |
5151 | an external symbol, we want | |
5152 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5153 | addiu $tempreg,$tempreg,<constant> | |
5154 | ||
5155 | If we have a large constant, and this is a reference to | |
5156 | an external symbol, we want | |
5157 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5158 | lui $at,<hiconstant> | |
5159 | addiu $at,$at,<loconstant> | |
5160 | addu $tempreg,$tempreg,$at | |
5161 | ||
5162 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5163 | local symbols, even though it introduces an additional | |
5164 | instruction. */ | |
5165 | ||
5166 | frag_grow (28); | |
5167 | if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5168 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5169 | if (offset_expr.X_add_number) | |
5170 | { | |
5171 | frag_now->tc_frag_data.tc_fr_offset = | |
5172 | expr1.X_add_number = offset_expr.X_add_number; | |
5173 | offset_expr.X_add_number = 0; | |
5174 | ||
5175 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
5176 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5177 | lw_reloc_type, mips_gp_register); | |
f5040a92 AO |
5178 | |
5179 | if (expr1.X_add_number >= -0x8000 | |
5180 | && expr1.X_add_number < 0x8000) | |
5181 | { | |
5182 | macro_build ((char *) NULL, &icnt, &expr1, | |
f899b4b8 | 5183 | ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, |
f5040a92 AO |
5184 | (int) BFD_RELOC_LO16); |
5185 | p = frag_var (rs_machine_dependent, 4, 0, | |
5186 | RELAX_ENCODE (8, 4, 0, 0, 0, 0), | |
5187 | offset_expr.X_add_symbol, 0, NULL); | |
5188 | } | |
5189 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5190 | { | |
5191 | int dreg; | |
5192 | ||
5193 | /* If we are going to add in a base register, and the | |
5194 | target register and the base register are the same, | |
5195 | then we are using AT as a temporary register. Since | |
5196 | we want to load the constant into AT, we add our | |
5197 | current AT (from the global offset table) and the | |
5198 | register into the register now, and pretend we were | |
5199 | not using a base register. */ | |
5200 | if (breg != treg) | |
5201 | dreg = tempreg; | |
5202 | else | |
5203 | { | |
5204 | assert (tempreg == AT); | |
5205 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5206 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
f5040a92 AO |
5207 | dreg = treg; |
5208 | adj = 4; | |
5209 | } | |
5210 | ||
5211 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
5212 | macro_build ((char *) NULL, &icnt, &expr1, | |
f899b4b8 TS |
5213 | ADDRESS_ADDI_INSN, "t,r,j", AT, AT, |
5214 | (int) BFD_RELOC_LO16); | |
f5040a92 | 5215 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
f899b4b8 | 5216 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 AO |
5217 | |
5218 | p = frag_var (rs_machine_dependent, 4 + adj, 0, | |
5219 | RELAX_ENCODE (16 + adj, 4 + adj, | |
5220 | 0, 0, 0, 0), | |
5221 | offset_expr.X_add_symbol, 0, NULL); | |
5222 | ||
5223 | used_at = 1; | |
5224 | } | |
5225 | else | |
5226 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5227 | ||
5228 | offset_expr.X_add_number = expr1.X_add_number; | |
5229 | ||
f899b4b8 | 5230 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
f5040a92 AO |
5231 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_DISP, |
5232 | mips_gp_register); | |
5233 | if (adj) | |
5234 | { | |
5235 | macro_build (p + 4, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5236 | ADDRESS_ADD_INSN, "d,v,t", |
5237 | treg, tempreg, breg); | |
f5040a92 AO |
5238 | breg = 0; |
5239 | tempreg = treg; | |
5240 | } | |
5241 | } | |
5242 | else | |
5243 | { | |
5244 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
5245 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5246 | lw_reloc_type, mips_gp_register); | |
f5040a92 AO |
5247 | if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP) |
5248 | p = frag_var (rs_machine_dependent, 0, 0, | |
5249 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5250 | offset_expr.X_add_symbol, 0, NULL); | |
5251 | } | |
5252 | ||
5253 | if (! p) | |
5254 | { | |
5255 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5256 | that this does not become a variant frag. */ | |
5257 | frag_wane (frag_now); | |
5258 | frag_new (0); | |
5259 | } | |
5260 | } | |
5261 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 RH |
5262 | { |
5263 | int gpdel; | |
f9419b05 | 5264 | char *p; |
9117d219 NC |
5265 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5266 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5267 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5268 | |
5269 | /* This is the large GOT case. If this is a reference to an | |
5270 | external symbol, and there is no constant, we want | |
5271 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5272 | addu $tempreg,$tempreg,$gp | |
5273 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5274 | or if tempreg is PIC_CALL_REG |
5275 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5276 | addu $tempreg,$tempreg,$gp | |
5277 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5278 | For a local symbol, we want |
5279 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5280 | nop | |
5281 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5282 | ||
5283 | If we have a small constant, and this is a reference to | |
5284 | an external symbol, we want | |
5285 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5286 | addu $tempreg,$tempreg,$gp | |
5287 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5288 | nop | |
5289 | addiu $tempreg,$tempreg,<constant> | |
5290 | For a local symbol, we want | |
5291 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5292 | nop | |
5293 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5294 | ||
5295 | If we have a large constant, and this is a reference to | |
5296 | an external symbol, we want | |
5297 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5298 | addu $tempreg,$tempreg,$gp | |
5299 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5300 | lui $at,<hiconstant> | |
5301 | addiu $at,$at,<loconstant> | |
5302 | addu $tempreg,$tempreg,$at | |
5303 | For a local symbol, we want | |
5304 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5305 | lui $at,<hiconstant> | |
5306 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5307 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5308 | */ |
438c16b8 | 5309 | |
252b5132 RH |
5310 | expr1.X_add_number = offset_expr.X_add_number; |
5311 | offset_expr.X_add_number = 0; | |
5312 | frag_grow (52); | |
f7ea7ef2 | 5313 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5314 | gpdel = 4; |
5315 | else | |
5316 | gpdel = 0; | |
9117d219 NC |
5317 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5318 | { | |
5319 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5320 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5321 | } | |
252b5132 | 5322 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5323 | tempreg, lui_reloc_type); |
252b5132 | 5324 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
f899b4b8 TS |
5325 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
5326 | mips_gp_register); | |
5327 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
9117d219 | 5328 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5329 | if (expr1.X_add_number == 0) |
5330 | { | |
5331 | int off; | |
5332 | ||
5333 | if (breg == 0) | |
5334 | off = 0; | |
5335 | else | |
5336 | { | |
5337 | /* We're going to put in an addu instruction using | |
5338 | tempreg, so we may as well insert the nop right | |
5339 | now. */ | |
5340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5341 | "nop", ""); | |
5342 | off = 4; | |
5343 | } | |
5344 | ||
5345 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5346 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5347 | 8 + gpdel, 0, | |
5348 | (breg == 0 | |
5349 | ? mips_opts.warn_about_macros | |
5350 | : 0)), | |
c4e7957c | 5351 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5352 | } |
5353 | else if (expr1.X_add_number >= -0x8000 | |
5354 | && expr1.X_add_number < 0x8000) | |
5355 | { | |
5356 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5357 | "nop", ""); | |
f899b4b8 | 5358 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5359 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5360 | ||
5361 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5362 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5363 | (breg == 0 | |
5364 | ? mips_opts.warn_about_macros | |
5365 | : 0)), | |
c4e7957c | 5366 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5367 | } |
5368 | else | |
5369 | { | |
5370 | int adj, dreg; | |
5371 | ||
5372 | /* If we are going to add in a base register, and the | |
5373 | target register and the base register are the same, | |
5374 | then we are using AT as a temporary register. Since | |
5375 | we want to load the constant into AT, we add our | |
5376 | current AT (from the global offset table) and the | |
5377 | register into the register now, and pretend we were | |
5378 | not using a base register. */ | |
5379 | if (breg != treg) | |
5380 | { | |
5381 | adj = 0; | |
5382 | dreg = tempreg; | |
5383 | } | |
5384 | else | |
5385 | { | |
5386 | assert (tempreg == AT); | |
5387 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5388 | "nop", ""); | |
5389 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5390 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5391 | dreg = treg; |
5392 | adj = 8; | |
5393 | } | |
5394 | ||
5395 | /* Set mips_optimize around the lui instruction to avoid | |
5396 | inserting an unnecessary nop after the lw. */ | |
5397 | hold_mips_optimize = mips_optimize; | |
5398 | mips_optimize = 2; | |
c4e7957c | 5399 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5400 | mips_optimize = hold_mips_optimize; |
5401 | ||
f899b4b8 | 5402 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5403 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5404 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5405 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 RH |
5406 | |
5407 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5408 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5409 | 8 + gpdel, 0, | |
5410 | (breg == 0 | |
5411 | ? mips_opts.warn_about_macros | |
5412 | : 0)), | |
c4e7957c | 5413 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5414 | |
5415 | used_at = 1; | |
5416 | } | |
5417 | ||
5418 | if (gpdel > 0) | |
5419 | { | |
5420 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5421 | the first instruction on the main stream does not. */ |
252b5132 RH |
5422 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5423 | p += 4; | |
5424 | } | |
ed6fb7bd | 5425 | |
f899b4b8 TS |
5426 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5427 | tempreg, local_reloc_type, mips_gp_register); | |
252b5132 | 5428 | p += 4; |
f5040a92 | 5429 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5430 | && expr1.X_add_number < 0x8000) |
5431 | { | |
5432 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5433 | p += 4; | |
f899b4b8 | 5434 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5435 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5436 | /* FIXME: If add_number is 0, and there was no base | |
f5040a92 AO |
5437 | register, the external symbol case ended with a load, |
5438 | so if the symbol turns out to not be external, and | |
5439 | the next instruction uses tempreg, an unnecessary nop | |
5440 | will be inserted. */ | |
252b5132 RH |
5441 | } |
5442 | else | |
5443 | { | |
5444 | if (breg == treg) | |
5445 | { | |
5446 | /* We must add in the base register now, as in the | |
f5040a92 | 5447 | external symbol case. */ |
252b5132 RH |
5448 | assert (tempreg == AT); |
5449 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5450 | p += 4; | |
5451 | macro_build (p, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5452 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5453 | p += 4; |
5454 | tempreg = treg; | |
5455 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5456 | it in in both cases. */ |
252b5132 RH |
5457 | breg = 0; |
5458 | } | |
5459 | ||
5460 | macro_build_lui (p, &icnt, &expr1, AT); | |
5461 | p += 4; | |
f899b4b8 | 5462 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5463 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5464 | p += 4; | |
f899b4b8 | 5465 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
5466 | "d,v,t", tempreg, tempreg, AT); |
5467 | p += 4; | |
5468 | } | |
5469 | } | |
f5040a92 AO |
5470 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5471 | { | |
5472 | char *p = NULL; | |
5473 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; | |
5474 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
5475 | int adj = 0; | |
5476 | ||
5477 | /* This is the large GOT case. If this is a reference to an | |
5478 | external symbol, and there is no constant, we want | |
5479 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5480 | add $tempreg,$tempreg,$gp | |
5481 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5482 | or if tempreg is PIC_CALL_REG | |
5483 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5484 | add $tempreg,$tempreg,$gp | |
5485 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5486 | ||
5487 | If we have a small constant, and this is a reference to | |
5488 | an external symbol, we want | |
5489 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5490 | add $tempreg,$tempreg,$gp | |
5491 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5492 | addi $tempreg,$tempreg,<constant> | |
5493 | ||
5494 | If we have a large constant, and this is a reference to | |
5495 | an external symbol, we want | |
5496 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5497 | addu $tempreg,$tempreg,$gp | |
5498 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5499 | lui $at,<hiconstant> | |
5500 | addi $at,$at,<loconstant> | |
5501 | add $tempreg,$tempreg,$at | |
5502 | ||
5503 | If we have NewABI, and we know it's a local symbol, we want | |
5504 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5505 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5506 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5507 | ||
5508 | frag_grow (40); | |
5509 | ||
5510 | frag_now->tc_frag_data.tc_fr_offset = | |
5511 | expr1.X_add_number = offset_expr.X_add_number; | |
5512 | offset_expr.X_add_number = 0; | |
5513 | ||
5514 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5515 | { | |
5516 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5517 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5518 | } | |
5519 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5520 | tempreg, lui_reloc_type); | |
5521 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5522 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
5523 | mips_gp_register); | |
5524 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
5525 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
5526 | ||
5527 | if (expr1.X_add_number == 0) | |
5528 | { | |
5529 | p = frag_var (rs_machine_dependent, 8, 0, | |
5530 | RELAX_ENCODE (12, 8, 0, 4, 0, | |
5531 | mips_opts.warn_about_macros), | |
5532 | offset_expr.X_add_symbol, 0, NULL); | |
684022ea | 5533 | } |
f5040a92 AO |
5534 | else if (expr1.X_add_number >= -0x8000 |
5535 | && expr1.X_add_number < 0x8000) | |
5536 | { | |
f899b4b8 | 5537 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
f5040a92 AO |
5538 | "t,r,j", tempreg, tempreg, |
5539 | (int) BFD_RELOC_LO16); | |
5540 | p = frag_var (rs_machine_dependent, 8, 0, | |
5541 | RELAX_ENCODE (16, 8, 0, 4, 0, | |
5542 | mips_opts.warn_about_macros), | |
5543 | offset_expr.X_add_symbol, 0, NULL); | |
5544 | } | |
5545 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5546 | { | |
5547 | int dreg; | |
5548 | ||
5549 | /* If we are going to add in a base register, and the | |
5550 | target register and the base register are the same, | |
5551 | then we are using AT as a temporary register. Since | |
5552 | we want to load the constant into AT, we add our | |
5553 | current AT (from the global offset table) and the | |
5554 | register into the register now, and pretend we were | |
5555 | not using a base register. */ | |
5556 | if (breg != treg) | |
5557 | dreg = tempreg; | |
5558 | else | |
5559 | { | |
5560 | assert (tempreg == AT); | |
5561 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5562 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
f5040a92 AO |
5563 | dreg = treg; |
5564 | adj = 4; | |
5565 | } | |
5566 | ||
5567 | /* Set mips_optimize around the lui instruction to avoid | |
5568 | inserting an unnecessary nop after the lw. */ | |
5569 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
f899b4b8 | 5570 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
f5040a92 AO |
5571 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5572 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5573 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 AO |
5574 | |
5575 | p = frag_var (rs_machine_dependent, 8 + adj, 0, | |
5576 | RELAX_ENCODE (24 + adj, 8 + adj, | |
5577 | 0, 4, 0, | |
5578 | (breg == 0 | |
5579 | ? mips_opts.warn_about_macros | |
5580 | : 0)), | |
5581 | offset_expr.X_add_symbol, 0, NULL); | |
5582 | ||
5583 | used_at = 1; | |
5584 | } | |
5585 | else | |
5586 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5587 | ||
5588 | offset_expr.X_add_number = expr1.X_add_number; | |
f899b4b8 TS |
5589 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5590 | tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE, | |
5591 | mips_gp_register); | |
5592 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
f5040a92 AO |
5593 | tempreg, tempreg, (int) BFD_RELOC_MIPS_GOT_OFST); |
5594 | if (adj) | |
5595 | { | |
5596 | macro_build (p + 8, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5597 | ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
f5040a92 AO |
5598 | breg = 0; |
5599 | tempreg = treg; | |
5600 | } | |
5601 | } | |
252b5132 RH |
5602 | else if (mips_pic == EMBEDDED_PIC) |
5603 | { | |
5604 | /* We use | |
cdf6fd85 | 5605 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5606 | */ |
f899b4b8 TS |
5607 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
5608 | "t,r,j", tempreg, mips_gp_register, | |
5609 | (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5610 | } |
5611 | else | |
5612 | abort (); | |
5613 | ||
5614 | if (breg != 0) | |
4d34fb5f TS |
5615 | { |
5616 | char *s; | |
5617 | ||
5618 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5619 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5620 | else |
f899b4b8 | 5621 | s = ADDRESS_ADD_INSN; |
4d34fb5f TS |
5622 | |
5623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5624 | "d,v,t", treg, tempreg, breg); | |
5625 | } | |
252b5132 RH |
5626 | |
5627 | if (! used_at) | |
5628 | return; | |
5629 | ||
5630 | break; | |
5631 | ||
5632 | case M_J_A: | |
5633 | /* The j instruction may not be used in PIC code, since it | |
5634 | requires an absolute address. We convert it to a b | |
5635 | instruction. */ | |
5636 | if (mips_pic == NO_PIC) | |
5637 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5638 | else | |
5639 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5640 | return; | |
5641 | ||
5642 | /* The jal instructions must be handled as macros because when | |
5643 | generating PIC code they expand to multi-instruction | |
5644 | sequences. Normally they are simple instructions. */ | |
5645 | case M_JAL_1: | |
5646 | dreg = RA; | |
5647 | /* Fall through. */ | |
5648 | case M_JAL_2: | |
5649 | if (mips_pic == NO_PIC | |
5650 | || mips_pic == EMBEDDED_PIC) | |
5651 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5652 | "d,s", dreg, sreg); | |
5653 | else if (mips_pic == SVR4_PIC) | |
5654 | { | |
5655 | if (sreg != PIC_CALL_REG) | |
5656 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5657 | |
252b5132 RH |
5658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5659 | "d,s", dreg, sreg); | |
6478892d | 5660 | if (! HAVE_NEWABI) |
252b5132 | 5661 | { |
6478892d TS |
5662 | if (mips_cprestore_offset < 0) |
5663 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5664 | else | |
5665 | { | |
7a621144 DJ |
5666 | if (! mips_frame_reg_valid) |
5667 | { | |
5668 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5669 | /* Quiet this warning. */ | |
5670 | mips_frame_reg_valid = 1; | |
5671 | } | |
5672 | if (! mips_cprestore_valid) | |
5673 | { | |
5674 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5675 | /* Quiet this warning. */ | |
5676 | mips_cprestore_valid = 1; | |
5677 | } | |
6478892d | 5678 | expr1.X_add_number = mips_cprestore_offset; |
885add95 | 5679 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
f899b4b8 TS |
5680 | ADDRESS_LOAD_INSN, |
5681 | mips_gp_register, | |
5682 | mips_frame_reg); | |
6478892d | 5683 | } |
252b5132 RH |
5684 | } |
5685 | } | |
5686 | else | |
5687 | abort (); | |
5688 | ||
5689 | return; | |
5690 | ||
5691 | case M_JAL_A: | |
5692 | if (mips_pic == NO_PIC) | |
5693 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5694 | else if (mips_pic == SVR4_PIC) | |
5695 | { | |
f9419b05 TS |
5696 | char *p; |
5697 | ||
252b5132 RH |
5698 | /* If this is a reference to an external symbol, and we are |
5699 | using a small GOT, we want | |
5700 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5701 | nop | |
f9419b05 | 5702 | jalr $ra,$25 |
252b5132 RH |
5703 | nop |
5704 | lw $gp,cprestore($sp) | |
5705 | The cprestore value is set using the .cprestore | |
5706 | pseudo-op. If we are using a big GOT, we want | |
5707 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5708 | addu $25,$25,$gp | |
5709 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5710 | nop | |
f9419b05 | 5711 | jalr $ra,$25 |
252b5132 RH |
5712 | nop |
5713 | lw $gp,cprestore($sp) | |
5714 | If the symbol is not external, we want | |
5715 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5716 | nop | |
5717 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5718 | jalr $ra,$25 |
252b5132 | 5719 | nop |
438c16b8 | 5720 | lw $gp,cprestore($sp) |
f5040a92 AO |
5721 | |
5722 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5723 | sequences above, minus nops, unless the symbol is local, | |
5724 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5725 | GOT_DISP. */ | |
438c16b8 | 5726 | if (HAVE_NEWABI) |
252b5132 | 5727 | { |
f5040a92 AO |
5728 | if (! mips_big_got) |
5729 | { | |
5730 | frag_grow (4); | |
5731 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 | 5732 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
f5040a92 AO |
5733 | (int) BFD_RELOC_MIPS_CALL16, |
5734 | mips_gp_register); | |
5735 | frag_var (rs_machine_dependent, 0, 0, | |
5736 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5737 | offset_expr.X_add_symbol, 0, NULL); | |
5738 | } | |
5739 | else | |
5740 | { | |
5741 | frag_grow (20); | |
5742 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5743 | "t,u", PIC_CALL_REG, | |
5744 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5745 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5746 | ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
5747 | PIC_CALL_REG, mips_gp_register); | |
f5040a92 | 5748 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 | 5749 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
f5040a92 AO |
5750 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
5751 | p = frag_var (rs_machine_dependent, 8, 0, | |
5752 | RELAX_ENCODE (12, 8, 0, 4, 0, 0), | |
5753 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
5754 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5755 | "t,o(b)", PIC_CALL_REG, | |
5756 | (int) BFD_RELOC_MIPS_GOT_PAGE, | |
f5040a92 | 5757 | mips_gp_register); |
f899b4b8 | 5758 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
dc9461f6 | 5759 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
f5040a92 AO |
5760 | (int) BFD_RELOC_MIPS_GOT_OFST); |
5761 | } | |
684022ea | 5762 | |
438c16b8 | 5763 | macro_build_jalr (icnt, &offset_expr); |
252b5132 RH |
5764 | } |
5765 | else | |
5766 | { | |
438c16b8 TS |
5767 | frag_grow (40); |
5768 | if (! mips_big_got) | |
5769 | { | |
5770 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 | 5771 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5772 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); |
5773 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5774 | "nop", ""); | |
5775 | p = frag_var (rs_machine_dependent, 4, 0, | |
5776 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5777 | offset_expr.X_add_symbol, 0, NULL); | |
5778 | } | |
252b5132 | 5779 | else |
252b5132 | 5780 | { |
438c16b8 TS |
5781 | int gpdel; |
5782 | ||
5783 | if (reg_needs_delay (mips_gp_register)) | |
5784 | gpdel = 4; | |
5785 | else | |
5786 | gpdel = 0; | |
5787 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5788 | "t,u", PIC_CALL_REG, | |
5789 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5791 | ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
5792 | PIC_CALL_REG, mips_gp_register); | |
438c16b8 | 5793 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 | 5794 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5795 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
5796 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5797 | "nop", ""); | |
5798 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5799 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5800 | 8 + gpdel, 0, 0), | |
5801 | offset_expr.X_add_symbol, 0, NULL); | |
5802 | if (gpdel > 0) | |
5803 | { | |
5804 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5805 | p += 4; | |
5806 | } | |
f899b4b8 | 5807 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
438c16b8 TS |
5808 | "t,o(b)", PIC_CALL_REG, |
5809 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5810 | p += 4; | |
252b5132 RH |
5811 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5812 | p += 4; | |
5813 | } | |
f899b4b8 | 5814 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
438c16b8 TS |
5815 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
5816 | (int) BFD_RELOC_LO16); | |
5817 | macro_build_jalr (icnt, &offset_expr); | |
5818 | ||
6478892d TS |
5819 | if (mips_cprestore_offset < 0) |
5820 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5821 | else | |
5822 | { | |
7a621144 DJ |
5823 | if (! mips_frame_reg_valid) |
5824 | { | |
5825 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5826 | /* Quiet this warning. */ | |
5827 | mips_frame_reg_valid = 1; | |
5828 | } | |
5829 | if (! mips_cprestore_valid) | |
5830 | { | |
5831 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5832 | /* Quiet this warning. */ | |
5833 | mips_cprestore_valid = 1; | |
5834 | } | |
6478892d TS |
5835 | if (mips_opts.noreorder) |
5836 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5837 | "nop", ""); |
6478892d | 5838 | expr1.X_add_number = mips_cprestore_offset; |
885add95 | 5839 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
f899b4b8 TS |
5840 | ADDRESS_LOAD_INSN, |
5841 | mips_gp_register, | |
5842 | mips_frame_reg); | |
6478892d | 5843 | } |
252b5132 RH |
5844 | } |
5845 | } | |
5846 | else if (mips_pic == EMBEDDED_PIC) | |
5847 | { | |
5848 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5849 | /* The linker may expand the call to a longer sequence which | |
5850 | uses $at, so we must break rather than return. */ | |
5851 | break; | |
5852 | } | |
5853 | else | |
5854 | abort (); | |
5855 | ||
5856 | return; | |
5857 | ||
5858 | case M_LB_AB: | |
5859 | s = "lb"; | |
5860 | goto ld; | |
5861 | case M_LBU_AB: | |
5862 | s = "lbu"; | |
5863 | goto ld; | |
5864 | case M_LH_AB: | |
5865 | s = "lh"; | |
5866 | goto ld; | |
5867 | case M_LHU_AB: | |
5868 | s = "lhu"; | |
5869 | goto ld; | |
5870 | case M_LW_AB: | |
5871 | s = "lw"; | |
5872 | goto ld; | |
5873 | case M_LWC0_AB: | |
5874 | s = "lwc0"; | |
bdaaa2e1 | 5875 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5876 | coproc = 1; |
5877 | goto ld; | |
5878 | case M_LWC1_AB: | |
5879 | s = "lwc1"; | |
bdaaa2e1 | 5880 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5881 | coproc = 1; |
5882 | goto ld; | |
5883 | case M_LWC2_AB: | |
5884 | s = "lwc2"; | |
bdaaa2e1 | 5885 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5886 | coproc = 1; |
5887 | goto ld; | |
5888 | case M_LWC3_AB: | |
5889 | s = "lwc3"; | |
bdaaa2e1 | 5890 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5891 | coproc = 1; |
5892 | goto ld; | |
5893 | case M_LWL_AB: | |
5894 | s = "lwl"; | |
5895 | lr = 1; | |
5896 | goto ld; | |
5897 | case M_LWR_AB: | |
5898 | s = "lwr"; | |
5899 | lr = 1; | |
5900 | goto ld; | |
5901 | case M_LDC1_AB: | |
ec68c924 | 5902 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5903 | { |
5904 | as_bad (_("opcode not supported on this processor")); | |
5905 | return; | |
5906 | } | |
5907 | s = "ldc1"; | |
bdaaa2e1 | 5908 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5909 | coproc = 1; |
5910 | goto ld; | |
5911 | case M_LDC2_AB: | |
5912 | s = "ldc2"; | |
bdaaa2e1 | 5913 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5914 | coproc = 1; |
5915 | goto ld; | |
5916 | case M_LDC3_AB: | |
5917 | s = "ldc3"; | |
bdaaa2e1 | 5918 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5919 | coproc = 1; |
5920 | goto ld; | |
5921 | case M_LDL_AB: | |
5922 | s = "ldl"; | |
5923 | lr = 1; | |
5924 | goto ld; | |
5925 | case M_LDR_AB: | |
5926 | s = "ldr"; | |
5927 | lr = 1; | |
5928 | goto ld; | |
5929 | case M_LL_AB: | |
5930 | s = "ll"; | |
5931 | goto ld; | |
5932 | case M_LLD_AB: | |
5933 | s = "lld"; | |
5934 | goto ld; | |
5935 | case M_LWU_AB: | |
5936 | s = "lwu"; | |
5937 | ld: | |
5938 | if (breg == treg || coproc || lr) | |
5939 | { | |
5940 | tempreg = AT; | |
5941 | used_at = 1; | |
5942 | } | |
5943 | else | |
5944 | { | |
5945 | tempreg = treg; | |
5946 | used_at = 0; | |
5947 | } | |
5948 | goto ld_st; | |
5949 | case M_SB_AB: | |
5950 | s = "sb"; | |
5951 | goto st; | |
5952 | case M_SH_AB: | |
5953 | s = "sh"; | |
5954 | goto st; | |
5955 | case M_SW_AB: | |
5956 | s = "sw"; | |
5957 | goto st; | |
5958 | case M_SWC0_AB: | |
5959 | s = "swc0"; | |
bdaaa2e1 | 5960 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5961 | coproc = 1; |
5962 | goto st; | |
5963 | case M_SWC1_AB: | |
5964 | s = "swc1"; | |
bdaaa2e1 | 5965 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5966 | coproc = 1; |
5967 | goto st; | |
5968 | case M_SWC2_AB: | |
5969 | s = "swc2"; | |
bdaaa2e1 | 5970 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5971 | coproc = 1; |
5972 | goto st; | |
5973 | case M_SWC3_AB: | |
5974 | s = "swc3"; | |
bdaaa2e1 | 5975 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5976 | coproc = 1; |
5977 | goto st; | |
5978 | case M_SWL_AB: | |
5979 | s = "swl"; | |
5980 | goto st; | |
5981 | case M_SWR_AB: | |
5982 | s = "swr"; | |
5983 | goto st; | |
5984 | case M_SC_AB: | |
5985 | s = "sc"; | |
5986 | goto st; | |
5987 | case M_SCD_AB: | |
5988 | s = "scd"; | |
5989 | goto st; | |
5990 | case M_SDC1_AB: | |
ec68c924 | 5991 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5992 | { |
5993 | as_bad (_("opcode not supported on this processor")); | |
5994 | return; | |
5995 | } | |
5996 | s = "sdc1"; | |
5997 | coproc = 1; | |
bdaaa2e1 | 5998 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5999 | goto st; |
6000 | case M_SDC2_AB: | |
6001 | s = "sdc2"; | |
bdaaa2e1 | 6002 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6003 | coproc = 1; |
6004 | goto st; | |
6005 | case M_SDC3_AB: | |
6006 | s = "sdc3"; | |
bdaaa2e1 | 6007 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6008 | coproc = 1; |
6009 | goto st; | |
6010 | case M_SDL_AB: | |
6011 | s = "sdl"; | |
6012 | goto st; | |
6013 | case M_SDR_AB: | |
6014 | s = "sdr"; | |
6015 | st: | |
6016 | tempreg = AT; | |
6017 | used_at = 1; | |
6018 | ld_st: | |
bdaaa2e1 | 6019 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6020 | if (mask == M_LWC1_AB |
6021 | || mask == M_SWC1_AB | |
6022 | || mask == M_LDC1_AB | |
6023 | || mask == M_SDC1_AB | |
6024 | || mask == M_L_DAB | |
6025 | || mask == M_S_DAB) | |
6026 | fmt = "T,o(b)"; | |
6027 | else if (coproc) | |
6028 | fmt = "E,o(b)"; | |
6029 | else | |
6030 | fmt = "t,o(b)"; | |
6031 | ||
afdbd6d0 CD |
6032 | /* For embedded PIC, we allow loads where the offset is calculated |
6033 | by subtracting a symbol in the current segment from an unknown | |
6034 | symbol, relative to a base register, e.g.: | |
6035 | <op> $treg, <sym>-<localsym>($breg) | |
6036 | This is used by the compiler for switch statements. */ | |
76b3015f | 6037 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
6038 | && offset_expr.X_op == O_subtract |
6039 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
6040 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
6041 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
6042 | && (S_GET_SEGMENT | |
6043 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
6044 | ->X_add_symbol) | |
6045 | == now_seg))) | |
6046 | && breg != 0 | |
6047 | && (offset_expr.X_add_number == 0 | |
6048 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
6049 | { | |
6050 | /* For this case, we output the instructions: | |
6051 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
6052 | addiu $tempreg,$tempreg,$breg | |
6053 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
6054 | If the relocation would fit entirely in 16 bits, it would be | |
6055 | nice to emit: | |
6056 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
6057 | instead, but that seems quite difficult. */ | |
6058 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6059 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
6060 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6061 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
6062 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
b7c7d6c1 | 6063 | ? "addu" : "daddu"), |
afdbd6d0 CD |
6064 | "d,v,t", tempreg, tempreg, breg); |
6065 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
6066 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
6067 | if (! used_at) | |
6068 | return; | |
6069 | break; | |
6070 | } | |
6071 | ||
252b5132 RH |
6072 | if (offset_expr.X_op != O_constant |
6073 | && offset_expr.X_op != O_symbol) | |
6074 | { | |
6075 | as_bad (_("expression too complex")); | |
6076 | offset_expr.X_op = O_constant; | |
6077 | } | |
6078 | ||
6079 | /* A constant expression in PIC code can be handled just as it | |
6080 | is in non PIC code. */ | |
6081 | if (mips_pic == NO_PIC | |
6082 | || offset_expr.X_op == O_constant) | |
6083 | { | |
f9419b05 TS |
6084 | char *p; |
6085 | ||
252b5132 RH |
6086 | /* If this is a reference to a GP relative symbol, and there |
6087 | is no base register, we want | |
cdf6fd85 | 6088 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6089 | Otherwise, if there is no base register, we want |
6090 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6091 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6092 | If we have a constant, we need two instructions anyhow, | |
6093 | so we always use the latter form. | |
6094 | ||
6095 | If we have a base register, and this is a reference to a | |
6096 | GP relative symbol, we want | |
6097 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6098 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6099 | Otherwise we want |
6100 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6101 | addu $tempreg,$tempreg,$breg | |
6102 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6103 | With a constant we always use the latter case. |
76b3015f | 6104 | |
d6bc6245 TS |
6105 | With 64bit address space and no base register and $at usable, |
6106 | we want | |
6107 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6108 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6109 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6110 | dsll32 $tempreg,0 | |
6111 | daddu $tempreg,$at | |
6112 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6113 | If we have a base register, we want | |
6114 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6115 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6116 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6117 | daddu $at,$breg | |
6118 | dsll32 $tempreg,0 | |
6119 | daddu $tempreg,$at | |
6120 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6121 | ||
6122 | Without $at we can't generate the optimal path for superscalar | |
6123 | processors here since this would require two temporary registers. | |
6124 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6125 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6126 | dsll $tempreg,16 | |
6127 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6128 | dsll $tempreg,16 | |
6129 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6130 | If we have a base register, we want | |
6131 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6132 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6133 | dsll $tempreg,16 | |
6134 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6135 | dsll $tempreg,16 | |
6136 | daddu $tempreg,$tempreg,$breg | |
6137 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
6138 | |
6139 | If we have 64-bit addresses, as an optimization, for | |
6140 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
6141 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
6142 | mechanism since it is more efficient. Note that due to |
6143 | the signed offset used by memory operations, the 32-bit | |
6144 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
6145 | probably attempt to generate 64-bit constants more |
6146 | efficiently in general. | |
9214dd3b AO |
6147 | |
6148 | As an extension for architectures with 64-bit registers, | |
6149 | we don't truncate 64-bit addresses given as literal | |
6150 | constants down to 32 bits, to support existing practice | |
6151 | in the mips64 Linux (the kernel), that compiles source | |
6152 | files with -mabi=64, assembling them as o32 or n32 (with | |
6153 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
6154 | the whole kernel is loaded into a memory region that is | |
6155 | addressible with sign-extended 32-bit addresses, it is | |
6156 | wasteful to compute the upper 32 bits of every | |
6157 | non-literal address, that takes more space and time. | |
6158 | Some day this should probably be implemented as an | |
6159 | assembler option, such that the kernel doesn't have to | |
6160 | use such ugly hacks, even though it will still have to | |
6161 | end up converting the binary to ELF32 for a number of | |
6162 | platforms whose boot loaders don't support ELF64 | |
6163 | binaries. */ | |
5a7a0b7b AO |
6164 | if ((offset_expr.X_op != O_constant && HAVE_64BIT_ADDRESSES) |
6165 | || (offset_expr.X_op == O_constant | |
eb0a7d52 | 6166 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000) |
5a7a0b7b | 6167 | && HAVE_64BIT_ADDRESS_CONSTANTS)) |
d6bc6245 TS |
6168 | { |
6169 | p = NULL; | |
6170 | ||
6171 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
6172 | hold the data for such large chunks. */ | |
6173 | ||
460597ba | 6174 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
6175 | { |
6176 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6177 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
6178 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6179 | AT, (int) BFD_RELOC_HI16_S); | |
6180 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
6181 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
6182 | if (breg != 0) | |
2396cfb9 TS |
6183 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
6184 | "d,v,t", AT, AT, breg); | |
6185 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
6186 | "d,w,<", tempreg, tempreg, 0); | |
6187 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
6188 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
6189 | macro_build (p, &icnt, &offset_expr, s, |
6190 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
6191 | used_at = 1; | |
6192 | } | |
6193 | else | |
6194 | { | |
6195 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6196 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
6197 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
6198 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
6199 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
6200 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
6201 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
6202 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
6203 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
6204 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6205 | if (breg != 0) |
2396cfb9 TS |
6206 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
6207 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
6208 | macro_build (p, &icnt, &offset_expr, s, |
6209 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
6210 | } | |
6211 | ||
6212 | return; | |
6213 | } | |
5a7a0b7b | 6214 | else if (offset_expr.X_op == O_constant |
eb0a7d52 | 6215 | && !HAVE_64BIT_ADDRESS_CONSTANTS |
5a7a0b7b AO |
6216 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
6217 | as_bad (_("load/store address overflow (max 32 bits)")); | |
76b3015f | 6218 | |
252b5132 RH |
6219 | if (breg == 0) |
6220 | { | |
e7d556df | 6221 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6222 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6223 | p = NULL; | |
6224 | else | |
6225 | { | |
6226 | frag_grow (20); | |
6227 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
6228 | treg, (int) BFD_RELOC_GPREL16, |
6229 | mips_gp_register); | |
252b5132 RH |
6230 | p = frag_var (rs_machine_dependent, 8, 0, |
6231 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
6232 | (mips_opts.warn_about_macros | |
6233 | || (used_at | |
6234 | && mips_opts.noat))), | |
956cd1d6 | 6235 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6236 | used_at = 0; |
6237 | } | |
6238 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6239 | if (p != NULL) | |
6240 | p += 4; | |
6241 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6242 | (int) BFD_RELOC_LO16, tempreg); | |
6243 | } | |
6244 | else | |
6245 | { | |
e7d556df | 6246 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6247 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6248 | p = NULL; | |
6249 | else | |
6250 | { | |
6251 | frag_grow (28); | |
6252 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6253 | ADDRESS_ADD_INSN, "d,v,t", tempreg, breg, |
6254 | mips_gp_register); | |
252b5132 | 6255 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6256 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6257 | p = frag_var (rs_machine_dependent, 12, 0, |
6258 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 6259 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6260 | } |
6261 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6262 | if (p != NULL) | |
6263 | p += 4; | |
f899b4b8 | 6264 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
6265 | "d,v,t", tempreg, tempreg, breg); |
6266 | if (p != NULL) | |
6267 | p += 4; | |
6268 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6269 | (int) BFD_RELOC_LO16, tempreg); | |
6270 | } | |
6271 | } | |
6272 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6273 | { | |
f9419b05 | 6274 | char *p; |
ed6fb7bd | 6275 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6276 | |
252b5132 RH |
6277 | /* If this is a reference to an external symbol, we want |
6278 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6279 | nop | |
6280 | <op> $treg,0($tempreg) | |
6281 | Otherwise we want | |
6282 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6283 | nop | |
6284 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6285 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6286 | |
6287 | For NewABI, we want | |
6288 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6289 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6290 | ||
252b5132 RH |
6291 | If there is a base register, we add it to $tempreg before |
6292 | the <op>. If there is a constant, we stick it in the | |
6293 | <op> instruction. We don't handle constants larger than | |
6294 | 16 bits, because we have no way to load the upper 16 bits | |
6295 | (actually, we could handle them for the subset of cases | |
6296 | in which we are not using $at). */ | |
6297 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6298 | if (HAVE_NEWABI) |
6299 | { | |
6300 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
6301 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6302 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 AO |
6303 | if (breg != 0) |
6304 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6305 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6306 | breg); | |
f5040a92 AO |
6307 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, |
6308 | (int) BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
6309 | ||
6310 | if (! used_at) | |
6311 | return; | |
6312 | ||
6313 | break; | |
6314 | } | |
252b5132 RH |
6315 | expr1.X_add_number = offset_expr.X_add_number; |
6316 | offset_expr.X_add_number = 0; | |
6317 | if (expr1.X_add_number < -0x8000 | |
6318 | || expr1.X_add_number >= 0x8000) | |
6319 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6320 | frag_grow (20); | |
f899b4b8 TS |
6321 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6322 | "t,o(b)", tempreg, (int) lw_reloc_type, | |
6323 | mips_gp_register); | |
252b5132 | 6324 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 6325 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 6326 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 6327 | offset_expr.X_add_symbol, 0, NULL); |
f899b4b8 | 6328 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
252b5132 RH |
6329 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6330 | if (breg != 0) | |
6331 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6332 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
252b5132 RH |
6333 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6334 | (int) BFD_RELOC_LO16, tempreg); | |
6335 | } | |
f5040a92 | 6336 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 RH |
6337 | { |
6338 | int gpdel; | |
f9419b05 | 6339 | char *p; |
252b5132 RH |
6340 | |
6341 | /* If this is a reference to an external symbol, we want | |
6342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6343 | addu $tempreg,$tempreg,$gp | |
6344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6345 | <op> $treg,0($tempreg) | |
6346 | Otherwise we want | |
6347 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6348 | nop | |
6349 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6350 | <op> $treg,0($tempreg) | |
6351 | If there is a base register, we add it to $tempreg before | |
6352 | the <op>. If there is a constant, we stick it in the | |
6353 | <op> instruction. We don't handle constants larger than | |
6354 | 16 bits, because we have no way to load the upper 16 bits | |
6355 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6356 | in which we are not using $at). */ |
252b5132 RH |
6357 | assert (offset_expr.X_op == O_symbol); |
6358 | expr1.X_add_number = offset_expr.X_add_number; | |
6359 | offset_expr.X_add_number = 0; | |
6360 | if (expr1.X_add_number < -0x8000 | |
6361 | || expr1.X_add_number >= 0x8000) | |
6362 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
f7ea7ef2 | 6363 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6364 | gpdel = 4; |
6365 | else | |
6366 | gpdel = 0; | |
6367 | frag_grow (36); | |
6368 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6369 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6370 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6371 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6372 | mips_gp_register); | |
6373 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
252b5132 RH |
6374 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6375 | tempreg); | |
6376 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
6377 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6378 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6379 | if (gpdel > 0) |
6380 | { | |
6381 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6382 | p += 4; | |
6383 | } | |
f899b4b8 | 6384 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
6385 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
6386 | mips_gp_register); | |
252b5132 RH |
6387 | p += 4; |
6388 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6389 | p += 4; | |
f899b4b8 | 6390 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
252b5132 RH |
6391 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6392 | if (breg != 0) | |
6393 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6394 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
252b5132 RH |
6395 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6396 | (int) BFD_RELOC_LO16, tempreg); | |
6397 | } | |
f5040a92 AO |
6398 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6399 | { | |
6400 | char *p; | |
6401 | int bregsz = breg != 0 ? 4 : 0; | |
6402 | ||
6403 | /* If this is a reference to an external symbol, we want | |
6404 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6405 | add $tempreg,$tempreg,$gp | |
6406 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6407 | <op> $treg,<ofst>($tempreg) | |
6408 | Otherwise, for local symbols, we want: | |
6409 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6410 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6411 | assert (offset_expr.X_op == O_symbol); | |
6412 | frag_now->tc_frag_data.tc_fr_offset = | |
6413 | expr1.X_add_number = offset_expr.X_add_number; | |
6414 | offset_expr.X_add_number = 0; | |
6415 | if (expr1.X_add_number < -0x8000 | |
6416 | || expr1.X_add_number >= 0x8000) | |
6417 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6418 | frag_grow (36); | |
6419 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6420 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6421 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6422 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6423 | mips_gp_register); | |
6424 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
6425 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6426 | tempreg); | |
6427 | if (breg != 0) | |
6428 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6429 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
f5040a92 AO |
6430 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6431 | (int) BFD_RELOC_LO16, tempreg); | |
684022ea | 6432 | |
f5040a92 AO |
6433 | offset_expr.X_add_number = expr1.X_add_number; |
6434 | p = frag_var (rs_machine_dependent, 12 + bregsz, 0, | |
6435 | RELAX_ENCODE (16 + bregsz, 8 + bregsz, | |
6436 | 0, 4 + bregsz, 0, 0), | |
6437 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
6438 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6439 | tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE, | |
f5040a92 AO |
6440 | mips_gp_register); |
6441 | if (breg != 0) | |
6442 | macro_build (p + 4, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6443 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
f5040a92 AO |
6444 | macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg, |
6445 | (int) BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
6446 | } | |
252b5132 RH |
6447 | else if (mips_pic == EMBEDDED_PIC) |
6448 | { | |
6449 | /* If there is no base register, we want | |
cdf6fd85 | 6450 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6451 | If there is a base register, we want |
6452 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6453 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6454 | */ |
6455 | assert (offset_expr.X_op == O_symbol); | |
6456 | if (breg == 0) | |
6457 | { | |
6458 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 6459 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
6460 | used_at = 0; |
6461 | } | |
6462 | else | |
6463 | { | |
6464 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6465 | ADDRESS_ADD_INSN, "d,v,t", tempreg, breg, |
6466 | mips_gp_register); | |
252b5132 | 6467 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6468 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6469 | } |
6470 | } | |
6471 | else | |
6472 | abort (); | |
6473 | ||
6474 | if (! used_at) | |
6475 | return; | |
6476 | ||
6477 | break; | |
6478 | ||
6479 | case M_LI: | |
6480 | case M_LI_S: | |
6481 | load_register (&icnt, treg, &imm_expr, 0); | |
6482 | return; | |
6483 | ||
6484 | case M_DLI: | |
6485 | load_register (&icnt, treg, &imm_expr, 1); | |
6486 | return; | |
6487 | ||
6488 | case M_LI_SS: | |
6489 | if (imm_expr.X_op == O_constant) | |
6490 | { | |
6491 | load_register (&icnt, AT, &imm_expr, 0); | |
6492 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6493 | "mtc1", "t,G", AT, treg); | |
6494 | break; | |
6495 | } | |
6496 | else | |
6497 | { | |
6498 | assert (offset_expr.X_op == O_symbol | |
6499 | && strcmp (segment_name (S_GET_SEGMENT | |
6500 | (offset_expr.X_add_symbol)), | |
6501 | ".lit4") == 0 | |
6502 | && offset_expr.X_add_number == 0); | |
6503 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 6504 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6505 | return; |
6506 | } | |
6507 | ||
6508 | case M_LI_D: | |
ca4e0257 RS |
6509 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6510 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6511 | order 32 bits of the value and the low order 32 bits are either | |
6512 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6513 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6514 | { | |
ca4e0257 | 6515 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6516 | load_register (&icnt, treg, &imm_expr, 1); |
6517 | else | |
6518 | { | |
6519 | int hreg, lreg; | |
6520 | ||
6521 | if (target_big_endian) | |
6522 | { | |
6523 | hreg = treg; | |
6524 | lreg = treg + 1; | |
6525 | } | |
6526 | else | |
6527 | { | |
6528 | hreg = treg + 1; | |
6529 | lreg = treg; | |
6530 | } | |
6531 | ||
6532 | if (hreg <= 31) | |
6533 | load_register (&icnt, hreg, &imm_expr, 0); | |
6534 | if (lreg <= 31) | |
6535 | { | |
6536 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6537 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6538 | else |
6539 | { | |
6540 | assert (offset_expr.X_op == O_constant); | |
6541 | load_register (&icnt, lreg, &offset_expr, 0); | |
6542 | } | |
6543 | } | |
6544 | } | |
6545 | return; | |
6546 | } | |
6547 | ||
6548 | /* We know that sym is in the .rdata section. First we get the | |
6549 | upper 16 bits of the address. */ | |
6550 | if (mips_pic == NO_PIC) | |
6551 | { | |
956cd1d6 | 6552 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6553 | } |
6554 | else if (mips_pic == SVR4_PIC) | |
6555 | { | |
f899b4b8 | 6556 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
6557 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6558 | mips_gp_register); | |
252b5132 RH |
6559 | } |
6560 | else if (mips_pic == EMBEDDED_PIC) | |
6561 | { | |
6562 | /* For embedded PIC we pick up the entire address off $gp in | |
6563 | a single instruction. */ | |
f899b4b8 TS |
6564 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
6565 | "t,r,j", AT, mips_gp_register, | |
6566 | (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6567 | offset_expr.X_op = O_constant; |
6568 | offset_expr.X_add_number = 0; | |
6569 | } | |
6570 | else | |
6571 | abort (); | |
bdaaa2e1 | 6572 | |
252b5132 | 6573 | /* Now we load the register(s). */ |
ca4e0257 | 6574 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6575 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6576 | treg, (int) BFD_RELOC_LO16, AT); | |
6577 | else | |
6578 | { | |
6579 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6580 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6581 | if (treg != RA) |
252b5132 RH |
6582 | { |
6583 | /* FIXME: How in the world do we deal with the possible | |
6584 | overflow here? */ | |
6585 | offset_expr.X_add_number += 4; | |
6586 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6587 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6588 | } | |
6589 | } | |
6590 | ||
6591 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6592 | does not become a variant frag. */ | |
6593 | frag_wane (frag_now); | |
6594 | frag_new (0); | |
6595 | ||
6596 | break; | |
6597 | ||
6598 | case M_LI_DD: | |
ca4e0257 RS |
6599 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6600 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6601 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6602 | the value and the low order 32 bits are either zero or in | |
6603 | OFFSET_EXPR. */ | |
252b5132 RH |
6604 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6605 | { | |
ca4e0257 RS |
6606 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6607 | if (HAVE_64BIT_FPRS) | |
6608 | { | |
6609 | assert (HAVE_64BIT_GPRS); | |
6610 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6611 | "dmtc1", "t,S", AT, treg); | |
6612 | } | |
252b5132 RH |
6613 | else |
6614 | { | |
6615 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6616 | "mtc1", "t,G", AT, treg + 1); | |
6617 | if (offset_expr.X_op == O_absent) | |
6618 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6619 | "mtc1", "t,G", 0, treg); | |
6620 | else | |
6621 | { | |
6622 | assert (offset_expr.X_op == O_constant); | |
6623 | load_register (&icnt, AT, &offset_expr, 0); | |
6624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6625 | "mtc1", "t,G", AT, treg); | |
6626 | } | |
6627 | } | |
6628 | break; | |
6629 | } | |
6630 | ||
6631 | assert (offset_expr.X_op == O_symbol | |
6632 | && offset_expr.X_add_number == 0); | |
6633 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6634 | if (strcmp (s, ".lit8") == 0) | |
6635 | { | |
e7af610e | 6636 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6637 | { |
6638 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6639 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6640 | mips_gp_register); | |
252b5132 RH |
6641 | return; |
6642 | } | |
c9914766 | 6643 | breg = mips_gp_register; |
252b5132 RH |
6644 | r = BFD_RELOC_MIPS_LITERAL; |
6645 | goto dob; | |
6646 | } | |
6647 | else | |
6648 | { | |
6649 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6650 | if (mips_pic == SVR4_PIC) | |
6651 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
6652 | ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6653 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6654 | else |
6655 | { | |
6656 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6657 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6658 | } |
bdaaa2e1 | 6659 | |
e7af610e | 6660 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6661 | { |
6662 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6663 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6664 | ||
6665 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6666 | that this does not become a variant frag. */ | |
6667 | frag_wane (frag_now); | |
6668 | frag_new (0); | |
6669 | ||
6670 | break; | |
6671 | } | |
6672 | breg = AT; | |
6673 | r = BFD_RELOC_LO16; | |
6674 | goto dob; | |
6675 | } | |
6676 | ||
6677 | case M_L_DOB: | |
ec68c924 | 6678 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6679 | { |
6680 | as_bad (_("opcode not supported on this processor")); | |
6681 | return; | |
6682 | } | |
6683 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6684 | to adjust when loading from memory. */ | |
6685 | r = BFD_RELOC_LO16; | |
6686 | dob: | |
e7af610e | 6687 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6688 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6689 | target_big_endian ? treg + 1 : treg, | |
6690 | (int) r, breg); | |
6691 | /* FIXME: A possible overflow which I don't know how to deal | |
6692 | with. */ | |
6693 | offset_expr.X_add_number += 4; | |
6694 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6695 | target_big_endian ? treg : treg + 1, | |
6696 | (int) r, breg); | |
6697 | ||
6698 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6699 | does not become a variant frag. */ | |
6700 | frag_wane (frag_now); | |
6701 | frag_new (0); | |
6702 | ||
6703 | if (breg != AT) | |
6704 | return; | |
6705 | break; | |
6706 | ||
6707 | case M_L_DAB: | |
6708 | /* | |
6709 | * The MIPS assembler seems to check for X_add_number not | |
6710 | * being double aligned and generating: | |
6711 | * lui at,%hi(foo+1) | |
6712 | * addu at,at,v1 | |
6713 | * addiu at,at,%lo(foo+1) | |
6714 | * lwc1 f2,0(at) | |
6715 | * lwc1 f3,4(at) | |
6716 | * But, the resulting address is the same after relocation so why | |
6717 | * generate the extra instruction? | |
6718 | */ | |
ec68c924 | 6719 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6720 | { |
6721 | as_bad (_("opcode not supported on this processor")); | |
6722 | return; | |
6723 | } | |
bdaaa2e1 | 6724 | /* Itbl support may require additional care here. */ |
252b5132 | 6725 | coproc = 1; |
e7af610e | 6726 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6727 | { |
6728 | s = "ldc1"; | |
6729 | goto ld; | |
6730 | } | |
6731 | ||
6732 | s = "lwc1"; | |
6733 | fmt = "T,o(b)"; | |
6734 | goto ldd_std; | |
6735 | ||
6736 | case M_S_DAB: | |
ec68c924 | 6737 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6738 | { |
6739 | as_bad (_("opcode not supported on this processor")); | |
6740 | return; | |
6741 | } | |
6742 | ||
e7af610e | 6743 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6744 | { |
6745 | s = "sdc1"; | |
6746 | goto st; | |
6747 | } | |
6748 | ||
6749 | s = "swc1"; | |
6750 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6751 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6752 | coproc = 1; |
6753 | goto ldd_std; | |
6754 | ||
6755 | case M_LD_AB: | |
ca4e0257 | 6756 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6757 | { |
6758 | s = "ld"; | |
6759 | goto ld; | |
6760 | } | |
6761 | ||
6762 | s = "lw"; | |
6763 | fmt = "t,o(b)"; | |
6764 | goto ldd_std; | |
6765 | ||
6766 | case M_SD_AB: | |
ca4e0257 | 6767 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6768 | { |
6769 | s = "sd"; | |
6770 | goto st; | |
6771 | } | |
6772 | ||
6773 | s = "sw"; | |
6774 | fmt = "t,o(b)"; | |
6775 | ||
6776 | ldd_std: | |
afdbd6d0 CD |
6777 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6778 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6779 | This is not currently done by the compiler, and assembly coders | |
6780 | writing embedded-pic code can cope. */ | |
6781 | ||
252b5132 RH |
6782 | if (offset_expr.X_op != O_symbol |
6783 | && offset_expr.X_op != O_constant) | |
6784 | { | |
6785 | as_bad (_("expression too complex")); | |
6786 | offset_expr.X_op = O_constant; | |
6787 | } | |
6788 | ||
6789 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6790 | to adjust when loading from memory. We set coproc if we must | |
6791 | load $fn+1 first. */ | |
bdaaa2e1 | 6792 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6793 | if (! target_big_endian) |
6794 | coproc = 0; | |
6795 | ||
6796 | if (mips_pic == NO_PIC | |
6797 | || offset_expr.X_op == O_constant) | |
6798 | { | |
f9419b05 TS |
6799 | char *p; |
6800 | ||
252b5132 | 6801 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6802 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6803 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6804 | If we have a base register, we use this |
6805 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6806 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6807 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6808 | If this is not a GP relative symbol, we want |
6809 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6810 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6811 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6812 | If there is a base register, we add it to $at after the | |
6813 | lui instruction. If there is a constant, we always use | |
6814 | the last case. */ | |
e7d556df | 6815 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6816 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6817 | { | |
6818 | p = NULL; | |
6819 | used_at = 1; | |
6820 | } | |
6821 | else | |
6822 | { | |
6823 | int off; | |
6824 | ||
6825 | if (breg == 0) | |
6826 | { | |
6827 | frag_grow (28); | |
c9914766 | 6828 | tempreg = mips_gp_register; |
252b5132 RH |
6829 | off = 0; |
6830 | used_at = 0; | |
6831 | } | |
6832 | else | |
6833 | { | |
6834 | frag_grow (36); | |
6835 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6836 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, |
6837 | mips_gp_register); | |
252b5132 RH |
6838 | tempreg = AT; |
6839 | off = 4; | |
6840 | used_at = 1; | |
6841 | } | |
6842 | ||
beae10d5 | 6843 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6844 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6845 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6846 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6847 | offset_expr.X_add_number += 4; |
6848 | ||
6849 | /* Set mips_optimize to 2 to avoid inserting an | |
6850 | undesired nop. */ | |
6851 | hold_mips_optimize = mips_optimize; | |
6852 | mips_optimize = 2; | |
beae10d5 | 6853 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6854 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6855 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6856 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6857 | mips_optimize = hold_mips_optimize; |
6858 | ||
6859 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6860 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6861 | used_at && mips_opts.noat), | |
956cd1d6 | 6862 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6863 | |
6864 | /* We just generated two relocs. When tc_gen_reloc | |
6865 | handles this case, it will skip the first reloc and | |
6866 | handle the second. The second reloc already has an | |
6867 | extra addend of 4, which we added above. We must | |
6868 | subtract it out, and then subtract another 4 to make | |
6869 | the first reloc come out right. The second reloc | |
6870 | will come out right because we are going to add 4 to | |
6871 | offset_expr when we build its instruction below. | |
6872 | ||
6873 | If we have a symbol, then we don't want to include | |
6874 | the offset, because it will wind up being included | |
6875 | when we generate the reloc. */ | |
6876 | ||
6877 | if (offset_expr.X_op == O_constant) | |
6878 | offset_expr.X_add_number -= 8; | |
6879 | else | |
6880 | { | |
6881 | offset_expr.X_add_number = -4; | |
6882 | offset_expr.X_op = O_constant; | |
6883 | } | |
6884 | } | |
6885 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6886 | if (p != NULL) | |
6887 | p += 4; | |
6888 | if (breg != 0) | |
6889 | { | |
f899b4b8 | 6890 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
6891 | "d,v,t", AT, breg, AT); |
6892 | if (p != NULL) | |
6893 | p += 4; | |
6894 | } | |
beae10d5 | 6895 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6896 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6897 | coproc ? treg + 1 : treg, | |
6898 | (int) BFD_RELOC_LO16, AT); | |
6899 | if (p != NULL) | |
6900 | p += 4; | |
6901 | /* FIXME: How do we handle overflow here? */ | |
6902 | offset_expr.X_add_number += 4; | |
beae10d5 | 6903 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6904 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6905 | coproc ? treg : treg + 1, | |
6906 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6907 | } |
252b5132 RH |
6908 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6909 | { | |
6910 | int off; | |
6911 | ||
6912 | /* If this is a reference to an external symbol, we want | |
6913 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6914 | nop | |
6915 | <op> $treg,0($at) | |
6916 | <op> $treg+1,4($at) | |
6917 | Otherwise we want | |
6918 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6919 | nop | |
6920 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6921 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6922 | If there is a base register we add it to $at before the | |
6923 | lwc1 instructions. If there is a constant we include it | |
6924 | in the lwc1 instructions. */ | |
6925 | used_at = 1; | |
6926 | expr1.X_add_number = offset_expr.X_add_number; | |
6927 | offset_expr.X_add_number = 0; | |
6928 | if (expr1.X_add_number < -0x8000 | |
6929 | || expr1.X_add_number >= 0x8000 - 4) | |
6930 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6931 | if (breg == 0) | |
6932 | off = 0; | |
6933 | else | |
6934 | off = 4; | |
6935 | frag_grow (24 + off); | |
f899b4b8 TS |
6936 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6937 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, | |
6938 | mips_gp_register); | |
252b5132 RH |
6939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6940 | if (breg != 0) | |
6941 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6942 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6943 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6944 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6945 | coproc ? treg + 1 : treg, | |
6946 | (int) BFD_RELOC_LO16, AT); | |
6947 | expr1.X_add_number += 4; | |
6948 | ||
6949 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6950 | nop. */ | |
6951 | hold_mips_optimize = mips_optimize; | |
6952 | mips_optimize = 2; | |
beae10d5 | 6953 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6954 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6955 | coproc ? treg : treg + 1, | |
6956 | (int) BFD_RELOC_LO16, AT); | |
6957 | mips_optimize = hold_mips_optimize; | |
6958 | ||
6959 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6960 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6961 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6962 | } |
6963 | else if (mips_pic == SVR4_PIC) | |
6964 | { | |
6965 | int gpdel, off; | |
f9419b05 | 6966 | char *p; |
252b5132 RH |
6967 | |
6968 | /* If this is a reference to an external symbol, we want | |
6969 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6970 | addu $at,$at,$gp | |
6971 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6972 | nop | |
6973 | <op> $treg,0($at) | |
6974 | <op> $treg+1,4($at) | |
6975 | Otherwise we want | |
6976 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6977 | nop | |
6978 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6979 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6980 | If there is a base register we add it to $at before the | |
6981 | lwc1 instructions. If there is a constant we include it | |
6982 | in the lwc1 instructions. */ | |
6983 | used_at = 1; | |
6984 | expr1.X_add_number = offset_expr.X_add_number; | |
6985 | offset_expr.X_add_number = 0; | |
6986 | if (expr1.X_add_number < -0x8000 | |
6987 | || expr1.X_add_number >= 0x8000 - 4) | |
6988 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6989 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6990 | gpdel = 4; |
6991 | else | |
6992 | gpdel = 0; | |
6993 | if (breg == 0) | |
6994 | off = 0; | |
6995 | else | |
6996 | off = 4; | |
6997 | frag_grow (56); | |
6998 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6999 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
7000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
7001 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, mips_gp_register); |
7002 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
252b5132 RH |
7003 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
7004 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
7005 | if (breg != 0) | |
7006 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7007 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7008 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7009 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
7010 | coproc ? treg + 1 : treg, | |
7011 | (int) BFD_RELOC_LO16, AT); | |
7012 | expr1.X_add_number += 4; | |
7013 | ||
7014 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7015 | nop. */ | |
7016 | hold_mips_optimize = mips_optimize; | |
7017 | mips_optimize = 2; | |
beae10d5 | 7018 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7019 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
7020 | coproc ? treg : treg + 1, | |
7021 | (int) BFD_RELOC_LO16, AT); | |
7022 | mips_optimize = hold_mips_optimize; | |
7023 | expr1.X_add_number -= 4; | |
7024 | ||
7025 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
7026 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
7027 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 7028 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
7029 | if (gpdel > 0) |
7030 | { | |
7031 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
7032 | p += 4; | |
7033 | } | |
f899b4b8 | 7034 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
7035 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
7036 | mips_gp_register); | |
252b5132 RH |
7037 | p += 4; |
7038 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
7039 | p += 4; | |
7040 | if (breg != 0) | |
7041 | { | |
f899b4b8 | 7042 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
7043 | "d,v,t", AT, breg, AT); |
7044 | p += 4; | |
7045 | } | |
beae10d5 | 7046 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7047 | macro_build (p, &icnt, &expr1, s, fmt, |
7048 | coproc ? treg + 1 : treg, | |
7049 | (int) BFD_RELOC_LO16, AT); | |
7050 | p += 4; | |
7051 | expr1.X_add_number += 4; | |
7052 | ||
7053 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7054 | nop. */ | |
7055 | hold_mips_optimize = mips_optimize; | |
7056 | mips_optimize = 2; | |
beae10d5 | 7057 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7058 | macro_build (p, &icnt, &expr1, s, fmt, |
7059 | coproc ? treg : treg + 1, | |
7060 | (int) BFD_RELOC_LO16, AT); | |
7061 | mips_optimize = hold_mips_optimize; | |
7062 | } | |
7063 | else if (mips_pic == EMBEDDED_PIC) | |
7064 | { | |
7065 | /* If there is no base register, we use | |
cdf6fd85 TS |
7066 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7067 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7068 | If we have a base register, we use |
7069 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7070 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7071 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7072 | */ |
7073 | if (breg == 0) | |
7074 | { | |
c9914766 | 7075 | tempreg = mips_gp_register; |
252b5132 RH |
7076 | used_at = 0; |
7077 | } | |
7078 | else | |
7079 | { | |
7080 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
7081 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, |
7082 | mips_gp_register); | |
252b5132 RH |
7083 | tempreg = AT; |
7084 | used_at = 1; | |
7085 | } | |
7086 | ||
beae10d5 | 7087 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7088 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
7089 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 7090 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 7091 | offset_expr.X_add_number += 4; |
beae10d5 | 7092 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7093 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
7094 | coproc ? treg : treg + 1, | |
cdf6fd85 | 7095 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7096 | } |
7097 | else | |
7098 | abort (); | |
7099 | ||
7100 | if (! used_at) | |
7101 | return; | |
7102 | ||
7103 | break; | |
7104 | ||
7105 | case M_LD_OB: | |
7106 | s = "lw"; | |
7107 | goto sd_ob; | |
7108 | case M_SD_OB: | |
7109 | s = "sw"; | |
7110 | sd_ob: | |
ca4e0257 | 7111 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
7112 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7113 | (int) BFD_RELOC_LO16, breg); | |
7114 | offset_expr.X_add_number += 4; | |
7115 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
7116 | (int) BFD_RELOC_LO16, breg); | |
7117 | return; | |
7118 | ||
7119 | /* New code added to support COPZ instructions. | |
7120 | This code builds table entries out of the macros in mip_opcodes. | |
7121 | R4000 uses interlocks to handle coproc delays. | |
7122 | Other chips (like the R3000) require nops to be inserted for delays. | |
7123 | ||
f72c8c98 | 7124 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7125 | In order to fill delay slots for non-interlocked chips, |
7126 | we must have a way to specify delays based on the coprocessor. | |
7127 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7128 | What are the side-effects of the cop instruction? | |
7129 | What cache support might we have and what are its effects? | |
7130 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7131 | What registers are read/set/modified? |
252b5132 RH |
7132 | |
7133 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7134 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7135 | |
7136 | case M_COP0: | |
7137 | s = "c0"; | |
7138 | goto copz; | |
7139 | case M_COP1: | |
7140 | s = "c1"; | |
7141 | goto copz; | |
7142 | case M_COP2: | |
7143 | s = "c2"; | |
7144 | goto copz; | |
7145 | case M_COP3: | |
7146 | s = "c3"; | |
7147 | copz: | |
7148 | /* For now we just do C (same as Cz). The parameter will be | |
7149 | stored in insn_opcode by mips_ip. */ | |
7150 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
7151 | ip->insn_opcode); | |
7152 | return; | |
7153 | ||
ea1fb5dc RS |
7154 | case M_MOVE: |
7155 | move_register (&icnt, dreg, sreg); | |
7156 | return; | |
7157 | ||
252b5132 RH |
7158 | #ifdef LOSING_COMPILER |
7159 | default: | |
7160 | /* Try and see if this is a new itbl instruction. | |
7161 | This code builds table entries out of the macros in mip_opcodes. | |
7162 | FIXME: For now we just assemble the expression and pass it's | |
7163 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7164 | We may want to have the assembler assemble this value, |
252b5132 RH |
7165 | so that we gain the assembler's knowledge of delay slots, |
7166 | symbols, etc. | |
7167 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7168 | if (itbl_have_entries |
252b5132 | 7169 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7170 | { |
252b5132 RH |
7171 | s = ip->insn_mo->name; |
7172 | s2 = "cop3"; | |
7173 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
7174 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
7175 | return; | |
beae10d5 | 7176 | } |
252b5132 RH |
7177 | macro2 (ip); |
7178 | return; | |
7179 | } | |
7180 | if (mips_opts.noat) | |
7181 | as_warn (_("Macro used $at after \".set noat\"")); | |
7182 | } | |
bdaaa2e1 | 7183 | |
252b5132 RH |
7184 | static void |
7185 | macro2 (ip) | |
7186 | struct mips_cl_insn *ip; | |
7187 | { | |
7188 | register int treg, sreg, dreg, breg; | |
7189 | int tempreg; | |
7190 | int mask; | |
7191 | int icnt = 0; | |
7192 | int used_at; | |
7193 | expressionS expr1; | |
7194 | const char *s; | |
7195 | const char *s2; | |
7196 | const char *fmt; | |
7197 | int likely = 0; | |
7198 | int dbl = 0; | |
7199 | int coproc = 0; | |
7200 | int lr = 0; | |
7201 | int imm = 0; | |
7202 | int off; | |
7203 | offsetT maxnum; | |
7204 | bfd_reloc_code_real_type r; | |
7205 | char *p; | |
bdaaa2e1 | 7206 | |
252b5132 RH |
7207 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7208 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7209 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7210 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7211 | |
252b5132 RH |
7212 | expr1.X_op = O_constant; |
7213 | expr1.X_op_symbol = NULL; | |
7214 | expr1.X_add_symbol = NULL; | |
7215 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7216 | |
252b5132 RH |
7217 | switch (mask) |
7218 | { | |
7219 | #endif /* LOSING_COMPILER */ | |
7220 | ||
7221 | case M_DMUL: | |
7222 | dbl = 1; | |
7223 | case M_MUL: | |
2396cfb9 TS |
7224 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7225 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
7226 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
7227 | dreg); | |
252b5132 RH |
7228 | return; |
7229 | ||
7230 | case M_DMUL_I: | |
7231 | dbl = 1; | |
7232 | case M_MUL_I: | |
7233 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7234 | not trying to be that fancy. GCC should do this for us | |
7235 | anyway. */ | |
7236 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7237 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7238 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
7239 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
7240 | dreg); | |
252b5132 RH |
7241 | break; |
7242 | ||
7243 | case M_DMULO_I: | |
7244 | dbl = 1; | |
7245 | case M_MULO_I: | |
7246 | imm = 1; | |
7247 | goto do_mulo; | |
7248 | ||
7249 | case M_DMULO: | |
7250 | dbl = 1; | |
7251 | case M_MULO: | |
7252 | do_mulo: | |
b34976b6 | 7253 | mips_emit_delays (TRUE); |
252b5132 RH |
7254 | ++mips_opts.noreorder; |
7255 | mips_any_noreorder = 1; | |
7256 | if (imm) | |
7257 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7258 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7259 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
7260 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
7261 | dreg); | |
7262 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 7263 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
7264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
7265 | AT); | |
252b5132 | 7266 | if (mips_trap) |
9bd7d936 MR |
7267 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
7268 | "s,t,q", dreg, AT, 6); | |
252b5132 RH |
7269 | else |
7270 | { | |
7271 | expr1.X_add_number = 8; | |
2396cfb9 TS |
7272 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
7273 | AT); | |
7274 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
7275 | 0); | |
7276 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
7277 | "c", 6); | |
252b5132 RH |
7278 | } |
7279 | --mips_opts.noreorder; | |
2396cfb9 | 7280 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
7281 | break; |
7282 | ||
7283 | case M_DMULOU_I: | |
7284 | dbl = 1; | |
7285 | case M_MULOU_I: | |
7286 | imm = 1; | |
7287 | goto do_mulou; | |
7288 | ||
7289 | case M_DMULOU: | |
7290 | dbl = 1; | |
7291 | case M_MULOU: | |
7292 | do_mulou: | |
b34976b6 | 7293 | mips_emit_delays (TRUE); |
252b5132 RH |
7294 | ++mips_opts.noreorder; |
7295 | mips_any_noreorder = 1; | |
7296 | if (imm) | |
7297 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7299 | dbl ? "dmultu" : "multu", |
7300 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
7301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
7302 | AT); | |
7303 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
7304 | dreg); | |
252b5132 | 7305 | if (mips_trap) |
9bd7d936 MR |
7306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
7307 | "s,t,q", AT, 0, 6); | |
252b5132 RH |
7308 | else |
7309 | { | |
7310 | expr1.X_add_number = 8; | |
7311 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
7312 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
7313 | 0); | |
7314 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
7315 | "c", 6); | |
252b5132 RH |
7316 | } |
7317 | --mips_opts.noreorder; | |
7318 | break; | |
7319 | ||
771c7ce4 | 7320 | case M_DROL: |
af7ee8bf | 7321 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7322 | { |
7323 | if (dreg == sreg) | |
7324 | { | |
7325 | tempreg = AT; | |
7326 | used_at = 1; | |
7327 | } | |
7328 | else | |
7329 | { | |
7330 | tempreg = dreg; | |
7331 | used_at = 0; | |
7332 | } | |
7333 | macro_build ((char *) NULL, &icnt, NULL, "dnegu", | |
7334 | "d,w", tempreg, treg); | |
7335 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7336 | "d,t,s", dreg, sreg, tempreg); | |
7337 | if (used_at) | |
7338 | break; | |
7339 | return; | |
7340 | } | |
771c7ce4 TS |
7341 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7342 | "d,v,t", AT, 0, treg); | |
7343 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7344 | "d,t,s", AT, sreg, AT); | |
7345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7346 | "d,t,s", dreg, sreg, treg); | |
7347 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7348 | "d,v,t", dreg, dreg, AT); | |
7349 | break; | |
7350 | ||
252b5132 | 7351 | case M_ROL: |
af7ee8bf | 7352 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7353 | { |
7354 | if (dreg == sreg) | |
7355 | { | |
7356 | tempreg = AT; | |
7357 | used_at = 1; | |
7358 | } | |
7359 | else | |
7360 | { | |
7361 | tempreg = dreg; | |
7362 | used_at = 0; | |
7363 | } | |
7364 | macro_build ((char *) NULL, &icnt, NULL, "negu", | |
7365 | "d,w", tempreg, treg); | |
7366 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7367 | "d,t,s", dreg, sreg, tempreg); | |
7368 | if (used_at) | |
7369 | break; | |
7370 | return; | |
7371 | } | |
2396cfb9 TS |
7372 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7373 | "d,v,t", AT, 0, treg); | |
7374 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7375 | "d,t,s", AT, sreg, AT); | |
7376 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7377 | "d,t,s", dreg, sreg, treg); | |
7378 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7379 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7380 | break; |
7381 | ||
771c7ce4 TS |
7382 | case M_DROL_I: |
7383 | { | |
7384 | unsigned int rot; | |
82dd0097 | 7385 | char *l, *r; |
771c7ce4 TS |
7386 | |
7387 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7388 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7389 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7390 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
60b63b72 RS |
7391 | { |
7392 | rot = (64 - rot) & 0x3f; | |
7393 | if (rot >= 32) | |
7394 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7395 | "d,w,<", dreg, sreg, rot - 32); | |
7396 | else | |
7397 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7398 | "d,w,<", dreg, sreg, rot); | |
82dd0097 | 7399 | return; |
60b63b72 | 7400 | } |
483fc7cd | 7401 | if (rot == 0) |
483fc7cd | 7402 | { |
82dd0097 CD |
7403 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7404 | "d,w,<", dreg, sreg, 0); | |
7405 | return; | |
483fc7cd | 7406 | } |
82dd0097 CD |
7407 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7408 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7409 | rot &= 0x1f; | |
7410 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7411 | "d,w,<", AT, sreg, rot); | |
7412 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7413 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7414 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7415 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7416 | } |
7417 | break; | |
7418 | ||
252b5132 | 7419 | case M_ROL_I: |
771c7ce4 TS |
7420 | { |
7421 | unsigned int rot; | |
7422 | ||
7423 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7424 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7425 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7426 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
60b63b72 RS |
7427 | { |
7428 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7429 | "d,w,<", dreg, sreg, (32 - rot) & 0x1f); | |
82dd0097 | 7430 | return; |
60b63b72 | 7431 | } |
483fc7cd | 7432 | if (rot == 0) |
483fc7cd | 7433 | { |
483fc7cd | 7434 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
82dd0097 CD |
7435 | "d,w,<", dreg, sreg, 0); |
7436 | return; | |
483fc7cd | 7437 | } |
82dd0097 CD |
7438 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
7439 | "d,w,<", AT, sreg, rot); | |
7440 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
7441 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7442 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7443 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7444 | } |
7445 | break; | |
7446 | ||
7447 | case M_DROR: | |
af7ee8bf | 7448 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7449 | { |
7450 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7451 | "d,t,s", dreg, sreg, treg); | |
7452 | return; | |
7453 | } | |
771c7ce4 TS |
7454 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7455 | "d,v,t", AT, 0, treg); | |
7456 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7457 | "d,t,s", AT, sreg, AT); | |
7458 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7459 | "d,t,s", dreg, sreg, treg); | |
7460 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7461 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7462 | break; |
7463 | ||
7464 | case M_ROR: | |
af7ee8bf | 7465 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7466 | { |
7467 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7468 | "d,t,s", dreg, sreg, treg); | |
7469 | return; | |
7470 | } | |
2396cfb9 TS |
7471 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7472 | "d,v,t", AT, 0, treg); | |
7473 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7474 | "d,t,s", AT, sreg, AT); | |
7475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7476 | "d,t,s", dreg, sreg, treg); | |
7477 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7478 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7479 | break; |
7480 | ||
771c7ce4 TS |
7481 | case M_DROR_I: |
7482 | { | |
7483 | unsigned int rot; | |
82dd0097 | 7484 | char *l, *r; |
771c7ce4 TS |
7485 | |
7486 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7487 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7488 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7489 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7490 | { |
7491 | if (rot >= 32) | |
7492 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7493 | "d,w,<", dreg, sreg, rot - 32); | |
7494 | else | |
7495 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7496 | "d,w,<", dreg, sreg, rot); | |
7497 | return; | |
7498 | } | |
483fc7cd | 7499 | if (rot == 0) |
483fc7cd | 7500 | { |
82dd0097 CD |
7501 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7502 | "d,w,<", dreg, sreg, 0); | |
7503 | return; | |
483fc7cd | 7504 | } |
82dd0097 CD |
7505 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7506 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7507 | rot &= 0x1f; | |
7508 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7509 | "d,w,<", AT, sreg, rot); | |
7510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7511 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7512 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7513 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7514 | } |
7515 | break; | |
7516 | ||
252b5132 | 7517 | case M_ROR_I: |
771c7ce4 TS |
7518 | { |
7519 | unsigned int rot; | |
7520 | ||
7521 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7522 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7523 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7524 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7525 | { |
7526 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7527 | "d,w,<", dreg, sreg, rot); | |
7528 | return; | |
7529 | } | |
483fc7cd | 7530 | if (rot == 0) |
483fc7cd RS |
7531 | { |
7532 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
82dd0097 CD |
7533 | "d,w,<", dreg, sreg, 0); |
7534 | return; | |
483fc7cd | 7535 | } |
82dd0097 CD |
7536 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
7537 | "d,w,<", AT, sreg, rot); | |
7538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
7539 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7540 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7541 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7542 | } |
252b5132 RH |
7543 | break; |
7544 | ||
7545 | case M_S_DOB: | |
ec68c924 | 7546 | if (mips_arch == CPU_R4650) |
252b5132 RH |
7547 | { |
7548 | as_bad (_("opcode not supported on this processor")); | |
7549 | return; | |
7550 | } | |
e7af610e | 7551 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7552 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7553 | to adjust when storing to memory. */ | |
7554 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7555 | target_big_endian ? treg + 1 : treg, | |
7556 | (int) BFD_RELOC_LO16, breg); | |
7557 | offset_expr.X_add_number += 4; | |
7558 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7559 | target_big_endian ? treg : treg + 1, | |
7560 | (int) BFD_RELOC_LO16, breg); | |
7561 | return; | |
7562 | ||
7563 | case M_SEQ: | |
7564 | if (sreg == 0) | |
7565 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7566 | treg, (int) BFD_RELOC_LO16); | |
7567 | else if (treg == 0) | |
7568 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7569 | sreg, (int) BFD_RELOC_LO16); | |
7570 | else | |
7571 | { | |
2396cfb9 TS |
7572 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7573 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
7574 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
7575 | dreg, (int) BFD_RELOC_LO16); | |
7576 | } | |
7577 | return; | |
7578 | ||
7579 | case M_SEQ_I: | |
7580 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7581 | { | |
7582 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7583 | sreg, (int) BFD_RELOC_LO16); | |
7584 | return; | |
7585 | } | |
7586 | if (sreg == 0) | |
7587 | { | |
7588 | as_warn (_("Instruction %s: result is always false"), | |
7589 | ip->insn_mo->name); | |
ea1fb5dc | 7590 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7591 | return; |
7592 | } | |
7593 | if (imm_expr.X_op == O_constant | |
7594 | && imm_expr.X_add_number >= 0 | |
7595 | && imm_expr.X_add_number < 0x10000) | |
7596 | { | |
7597 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
7598 | sreg, (int) BFD_RELOC_LO16); | |
7599 | used_at = 0; | |
7600 | } | |
7601 | else if (imm_expr.X_op == O_constant | |
7602 | && imm_expr.X_add_number > -0x8000 | |
7603 | && imm_expr.X_add_number < 0) | |
7604 | { | |
7605 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7606 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7607 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
f899b4b8 | 7608 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
252b5132 RH |
7609 | used_at = 0; |
7610 | } | |
7611 | else | |
7612 | { | |
4d34fb5f | 7613 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7615 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7616 | used_at = 1; |
7617 | } | |
7618 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7619 | (int) BFD_RELOC_LO16); | |
7620 | if (used_at) | |
7621 | break; | |
7622 | return; | |
7623 | ||
7624 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7625 | s = "slt"; | |
7626 | goto sge; | |
7627 | case M_SGEU: | |
7628 | s = "sltu"; | |
7629 | sge: | |
2396cfb9 TS |
7630 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7631 | dreg, sreg, treg); | |
252b5132 RH |
7632 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7633 | (int) BFD_RELOC_LO16); | |
7634 | return; | |
7635 | ||
7636 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7637 | case M_SGEU_I: | |
7638 | if (imm_expr.X_op == O_constant | |
7639 | && imm_expr.X_add_number >= -0x8000 | |
7640 | && imm_expr.X_add_number < 0x8000) | |
7641 | { | |
7642 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7643 | mask == M_SGE_I ? "slti" : "sltiu", | |
7644 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7645 | used_at = 0; | |
7646 | } | |
7647 | else | |
7648 | { | |
4d34fb5f | 7649 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7650 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7651 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7652 | AT); | |
252b5132 RH |
7653 | used_at = 1; |
7654 | } | |
7655 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7656 | (int) BFD_RELOC_LO16); | |
7657 | if (used_at) | |
7658 | break; | |
7659 | return; | |
7660 | ||
7661 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7662 | s = "slt"; | |
7663 | goto sgt; | |
7664 | case M_SGTU: | |
7665 | s = "sltu"; | |
7666 | sgt: | |
2396cfb9 TS |
7667 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7668 | dreg, treg, sreg); | |
252b5132 RH |
7669 | return; |
7670 | ||
7671 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7672 | s = "slt"; | |
7673 | goto sgti; | |
7674 | case M_SGTU_I: | |
7675 | s = "sltu"; | |
7676 | sgti: | |
4d34fb5f | 7677 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7678 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7679 | dreg, AT, sreg); | |
252b5132 RH |
7680 | break; |
7681 | ||
2396cfb9 | 7682 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7683 | s = "slt"; |
7684 | goto sle; | |
7685 | case M_SLEU: | |
7686 | s = "sltu"; | |
7687 | sle: | |
2396cfb9 TS |
7688 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7689 | dreg, treg, sreg); | |
252b5132 RH |
7690 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7691 | (int) BFD_RELOC_LO16); | |
7692 | return; | |
7693 | ||
2396cfb9 | 7694 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7695 | s = "slt"; |
7696 | goto slei; | |
7697 | case M_SLEU_I: | |
7698 | s = "sltu"; | |
7699 | slei: | |
4d34fb5f | 7700 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7702 | dreg, AT, sreg); | |
252b5132 RH |
7703 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7704 | (int) BFD_RELOC_LO16); | |
7705 | break; | |
7706 | ||
7707 | case M_SLT_I: | |
7708 | if (imm_expr.X_op == O_constant | |
7709 | && imm_expr.X_add_number >= -0x8000 | |
7710 | && imm_expr.X_add_number < 0x8000) | |
7711 | { | |
7712 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7713 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7714 | return; | |
7715 | } | |
4d34fb5f | 7716 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7718 | dreg, sreg, AT); | |
252b5132 RH |
7719 | break; |
7720 | ||
7721 | case M_SLTU_I: | |
7722 | if (imm_expr.X_op == O_constant | |
7723 | && imm_expr.X_add_number >= -0x8000 | |
7724 | && imm_expr.X_add_number < 0x8000) | |
7725 | { | |
7726 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7727 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7728 | return; | |
7729 | } | |
4d34fb5f | 7730 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7731 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7732 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7733 | break; |
7734 | ||
7735 | case M_SNE: | |
7736 | if (sreg == 0) | |
2396cfb9 TS |
7737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7738 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7739 | else if (treg == 0) |
2396cfb9 TS |
7740 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7741 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7742 | else |
7743 | { | |
2396cfb9 TS |
7744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7745 | "d,v,t", dreg, sreg, treg); | |
7746 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7747 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7748 | } |
7749 | return; | |
7750 | ||
7751 | case M_SNE_I: | |
7752 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7753 | { | |
2396cfb9 TS |
7754 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7755 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7756 | return; |
7757 | } | |
7758 | if (sreg == 0) | |
7759 | { | |
7760 | as_warn (_("Instruction %s: result is always true"), | |
7761 | ip->insn_mo->name); | |
7762 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7763 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7764 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7765 | return; | |
7766 | } | |
7767 | if (imm_expr.X_op == O_constant | |
7768 | && imm_expr.X_add_number >= 0 | |
7769 | && imm_expr.X_add_number < 0x10000) | |
7770 | { | |
7771 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7772 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7773 | used_at = 0; | |
7774 | } | |
7775 | else if (imm_expr.X_op == O_constant | |
7776 | && imm_expr.X_add_number > -0x8000 | |
7777 | && imm_expr.X_add_number < 0) | |
7778 | { | |
7779 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7780 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7781 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7782 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7783 | used_at = 0; | |
7784 | } | |
7785 | else | |
7786 | { | |
4d34fb5f | 7787 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7788 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7789 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7790 | used_at = 1; |
7791 | } | |
2396cfb9 TS |
7792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7793 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7794 | if (used_at) |
7795 | break; | |
7796 | return; | |
7797 | ||
7798 | case M_DSUB_I: | |
7799 | dbl = 1; | |
7800 | case M_SUB_I: | |
7801 | if (imm_expr.X_op == O_constant | |
7802 | && imm_expr.X_add_number > -0x8000 | |
7803 | && imm_expr.X_add_number <= 0x8000) | |
7804 | { | |
7805 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7806 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7807 | dbl ? "daddi" : "addi", | |
7808 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7809 | return; | |
7810 | } | |
7811 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7813 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7814 | break; |
7815 | ||
7816 | case M_DSUBU_I: | |
7817 | dbl = 1; | |
7818 | case M_SUBU_I: | |
7819 | if (imm_expr.X_op == O_constant | |
7820 | && imm_expr.X_add_number > -0x8000 | |
7821 | && imm_expr.X_add_number <= 0x8000) | |
7822 | { | |
7823 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7824 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7825 | dbl ? "daddiu" : "addiu", | |
7826 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7827 | return; | |
7828 | } | |
7829 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7831 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7832 | break; |
7833 | ||
7834 | case M_TEQ_I: | |
7835 | s = "teq"; | |
7836 | goto trap; | |
7837 | case M_TGE_I: | |
7838 | s = "tge"; | |
7839 | goto trap; | |
7840 | case M_TGEU_I: | |
7841 | s = "tgeu"; | |
7842 | goto trap; | |
7843 | case M_TLT_I: | |
7844 | s = "tlt"; | |
7845 | goto trap; | |
7846 | case M_TLTU_I: | |
7847 | s = "tltu"; | |
7848 | goto trap; | |
7849 | case M_TNE_I: | |
7850 | s = "tne"; | |
7851 | trap: | |
4d34fb5f | 7852 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7853 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7854 | AT); | |
252b5132 RH |
7855 | break; |
7856 | ||
252b5132 | 7857 | case M_TRUNCWS: |
43841e91 | 7858 | case M_TRUNCWD: |
e7af610e | 7859 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7860 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7861 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7862 | ||
7863 | /* | |
7864 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7865 | * or is there a reason for it? | |
7866 | */ | |
b34976b6 | 7867 | mips_emit_delays (TRUE); |
252b5132 RH |
7868 | ++mips_opts.noreorder; |
7869 | mips_any_noreorder = 1; | |
2396cfb9 | 7870 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7871 | treg, RA); |
2396cfb9 | 7872 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7873 | treg, RA); |
2396cfb9 | 7874 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7875 | expr1.X_add_number = 3; |
7876 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7877 | (int) BFD_RELOC_LO16); | |
7878 | expr1.X_add_number = 2; | |
7879 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7880 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7881 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7882 | AT, RA); |
2396cfb9 TS |
7883 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7884 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7885 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7886 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7887 | treg, RA); |
2396cfb9 | 7888 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7889 | --mips_opts.noreorder; |
7890 | break; | |
7891 | ||
7892 | case M_ULH: | |
7893 | s = "lb"; | |
7894 | goto ulh; | |
7895 | case M_ULHU: | |
7896 | s = "lbu"; | |
7897 | ulh: | |
7898 | if (offset_expr.X_add_number >= 0x7fff) | |
7899 | as_bad (_("operand overflow")); | |
252b5132 | 7900 | if (! target_big_endian) |
f9419b05 | 7901 | ++offset_expr.X_add_number; |
af22f5b2 | 7902 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT, |
252b5132 RH |
7903 | (int) BFD_RELOC_LO16, breg); |
7904 | if (! target_big_endian) | |
f9419b05 | 7905 | --offset_expr.X_add_number; |
252b5132 | 7906 | else |
f9419b05 | 7907 | ++offset_expr.X_add_number; |
af22f5b2 | 7908 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg, |
252b5132 | 7909 | (int) BFD_RELOC_LO16, breg); |
2396cfb9 | 7910 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
af22f5b2 | 7911 | AT, AT, 8); |
2396cfb9 TS |
7912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", |
7913 | treg, treg, AT); | |
252b5132 RH |
7914 | break; |
7915 | ||
7916 | case M_ULD: | |
7917 | s = "ldl"; | |
7918 | s2 = "ldr"; | |
7919 | off = 7; | |
7920 | goto ulw; | |
7921 | case M_ULW: | |
7922 | s = "lwl"; | |
7923 | s2 = "lwr"; | |
7924 | off = 3; | |
7925 | ulw: | |
7926 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7927 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7928 | if (treg != breg) |
7929 | tempreg = treg; | |
7930 | else | |
7931 | tempreg = AT; | |
252b5132 RH |
7932 | if (! target_big_endian) |
7933 | offset_expr.X_add_number += off; | |
af22f5b2 | 7934 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg, |
252b5132 RH |
7935 | (int) BFD_RELOC_LO16, breg); |
7936 | if (! target_big_endian) | |
7937 | offset_expr.X_add_number -= off; | |
7938 | else | |
7939 | offset_expr.X_add_number += off; | |
af22f5b2 | 7940 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg, |
252b5132 | 7941 | (int) BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7942 | |
7943 | /* If necessary, move the result in tempreg the final destination. */ | |
7944 | if (treg == tempreg) | |
7945 | return; | |
7946 | /* Protect second load's delay slot. */ | |
7947 | if (!gpr_interlocks) | |
7948 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
7949 | move_register (&icnt, treg, tempreg); | |
7950 | break; | |
252b5132 RH |
7951 | |
7952 | case M_ULD_A: | |
7953 | s = "ldl"; | |
7954 | s2 = "ldr"; | |
7955 | off = 7; | |
7956 | goto ulwa; | |
7957 | case M_ULW_A: | |
7958 | s = "lwl"; | |
7959 | s2 = "lwr"; | |
7960 | off = 3; | |
7961 | ulwa: | |
d6bc6245 | 7962 | used_at = 1; |
c9914766 | 7963 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7964 | if (breg != 0) |
7965 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7966 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7967 | if (! target_big_endian) |
7968 | expr1.X_add_number = off; | |
7969 | else | |
7970 | expr1.X_add_number = 0; | |
7971 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7972 | (int) BFD_RELOC_LO16, AT); | |
7973 | if (! target_big_endian) | |
7974 | expr1.X_add_number = 0; | |
7975 | else | |
7976 | expr1.X_add_number = off; | |
7977 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7978 | (int) BFD_RELOC_LO16, AT); | |
7979 | break; | |
7980 | ||
7981 | case M_ULH_A: | |
7982 | case M_ULHU_A: | |
d6bc6245 | 7983 | used_at = 1; |
c9914766 | 7984 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7985 | if (breg != 0) |
7986 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7987 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7988 | if (target_big_endian) |
7989 | expr1.X_add_number = 0; | |
7990 | macro_build ((char *) NULL, &icnt, &expr1, | |
7991 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7992 | (int) BFD_RELOC_LO16, AT); | |
7993 | if (target_big_endian) | |
7994 | expr1.X_add_number = 1; | |
7995 | else | |
7996 | expr1.X_add_number = 0; | |
7997 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7998 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7999 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
8000 | treg, treg, 8); | |
8001 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
8002 | treg, treg, AT); | |
252b5132 RH |
8003 | break; |
8004 | ||
8005 | case M_USH: | |
8006 | if (offset_expr.X_add_number >= 0x7fff) | |
8007 | as_bad (_("operand overflow")); | |
8008 | if (target_big_endian) | |
f9419b05 | 8009 | ++offset_expr.X_add_number; |
252b5132 RH |
8010 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
8011 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
8012 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
8013 | AT, treg, 8); | |
252b5132 | 8014 | if (target_big_endian) |
f9419b05 | 8015 | --offset_expr.X_add_number; |
252b5132 | 8016 | else |
f9419b05 | 8017 | ++offset_expr.X_add_number; |
252b5132 RH |
8018 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
8019 | (int) BFD_RELOC_LO16, breg); | |
8020 | break; | |
8021 | ||
8022 | case M_USD: | |
8023 | s = "sdl"; | |
8024 | s2 = "sdr"; | |
8025 | off = 7; | |
8026 | goto usw; | |
8027 | case M_USW: | |
8028 | s = "swl"; | |
8029 | s2 = "swr"; | |
8030 | off = 3; | |
8031 | usw: | |
8032 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8033 | as_bad (_("operand overflow")); | |
8034 | if (! target_big_endian) | |
8035 | offset_expr.X_add_number += off; | |
8036 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
8037 | (int) BFD_RELOC_LO16, breg); | |
8038 | if (! target_big_endian) | |
8039 | offset_expr.X_add_number -= off; | |
8040 | else | |
8041 | offset_expr.X_add_number += off; | |
8042 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
8043 | (int) BFD_RELOC_LO16, breg); | |
8044 | return; | |
8045 | ||
8046 | case M_USD_A: | |
8047 | s = "sdl"; | |
8048 | s2 = "sdr"; | |
8049 | off = 7; | |
8050 | goto uswa; | |
8051 | case M_USW_A: | |
8052 | s = "swl"; | |
8053 | s2 = "swr"; | |
8054 | off = 3; | |
8055 | uswa: | |
d6bc6245 | 8056 | used_at = 1; |
c9914766 | 8057 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
8058 | if (breg != 0) |
8059 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 8060 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8061 | if (! target_big_endian) |
8062 | expr1.X_add_number = off; | |
8063 | else | |
8064 | expr1.X_add_number = 0; | |
8065 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
8066 | (int) BFD_RELOC_LO16, AT); | |
8067 | if (! target_big_endian) | |
8068 | expr1.X_add_number = 0; | |
8069 | else | |
8070 | expr1.X_add_number = off; | |
8071 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
8072 | (int) BFD_RELOC_LO16, AT); | |
8073 | break; | |
8074 | ||
8075 | case M_USH_A: | |
d6bc6245 | 8076 | used_at = 1; |
c9914766 | 8077 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
8078 | if (breg != 0) |
8079 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 8080 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8081 | if (! target_big_endian) |
8082 | expr1.X_add_number = 0; | |
8083 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
8084 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
8085 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
8086 | treg, treg, 8); | |
252b5132 RH |
8087 | if (! target_big_endian) |
8088 | expr1.X_add_number = 1; | |
8089 | else | |
8090 | expr1.X_add_number = 0; | |
8091 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
8092 | (int) BFD_RELOC_LO16, AT); | |
8093 | if (! target_big_endian) | |
8094 | expr1.X_add_number = 0; | |
8095 | else | |
8096 | expr1.X_add_number = 1; | |
8097 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
8098 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
8099 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
8100 | treg, treg, 8); | |
8101 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
8102 | treg, treg, AT); | |
252b5132 RH |
8103 | break; |
8104 | ||
8105 | default: | |
8106 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8107 | are added dynamically. */ |
252b5132 RH |
8108 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8109 | break; | |
8110 | } | |
8111 | if (mips_opts.noat) | |
8112 | as_warn (_("Macro used $at after \".set noat\"")); | |
8113 | } | |
8114 | ||
8115 | /* Implement macros in mips16 mode. */ | |
8116 | ||
8117 | static void | |
8118 | mips16_macro (ip) | |
8119 | struct mips_cl_insn *ip; | |
8120 | { | |
8121 | int mask; | |
8122 | int xreg, yreg, zreg, tmp; | |
8123 | int icnt; | |
8124 | expressionS expr1; | |
8125 | int dbl; | |
8126 | const char *s, *s2, *s3; | |
8127 | ||
8128 | mask = ip->insn_mo->mask; | |
8129 | ||
8130 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
8131 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
8132 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8133 | ||
8134 | icnt = 0; | |
8135 | ||
8136 | expr1.X_op = O_constant; | |
8137 | expr1.X_op_symbol = NULL; | |
8138 | expr1.X_add_symbol = NULL; | |
8139 | expr1.X_add_number = 1; | |
8140 | ||
8141 | dbl = 0; | |
8142 | ||
8143 | switch (mask) | |
8144 | { | |
8145 | default: | |
8146 | internalError (); | |
8147 | ||
8148 | case M_DDIV_3: | |
8149 | dbl = 1; | |
8150 | case M_DIV_3: | |
8151 | s = "mflo"; | |
8152 | goto do_div3; | |
8153 | case M_DREM_3: | |
8154 | dbl = 1; | |
8155 | case M_REM_3: | |
8156 | s = "mfhi"; | |
8157 | do_div3: | |
b34976b6 | 8158 | mips_emit_delays (TRUE); |
252b5132 RH |
8159 | ++mips_opts.noreorder; |
8160 | mips_any_noreorder = 1; | |
2396cfb9 | 8161 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
8162 | dbl ? "ddiv" : "div", |
8163 | "0,x,y", xreg, yreg); | |
8164 | expr1.X_add_number = 2; | |
8165 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
8166 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
8167 | 7); | |
bdaaa2e1 | 8168 | |
252b5132 RH |
8169 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8170 | since that causes an overflow. We should do that as well, | |
8171 | but I don't see how to do the comparisons without a temporary | |
8172 | register. */ | |
8173 | --mips_opts.noreorder; | |
2396cfb9 | 8174 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
8175 | break; |
8176 | ||
8177 | case M_DIVU_3: | |
8178 | s = "divu"; | |
8179 | s2 = "mflo"; | |
8180 | goto do_divu3; | |
8181 | case M_REMU_3: | |
8182 | s = "divu"; | |
8183 | s2 = "mfhi"; | |
8184 | goto do_divu3; | |
8185 | case M_DDIVU_3: | |
8186 | s = "ddivu"; | |
8187 | s2 = "mflo"; | |
8188 | goto do_divu3; | |
8189 | case M_DREMU_3: | |
8190 | s = "ddivu"; | |
8191 | s2 = "mfhi"; | |
8192 | do_divu3: | |
b34976b6 | 8193 | mips_emit_delays (TRUE); |
252b5132 RH |
8194 | ++mips_opts.noreorder; |
8195 | mips_any_noreorder = 1; | |
2396cfb9 TS |
8196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
8197 | xreg, yreg); | |
252b5132 RH |
8198 | expr1.X_add_number = 2; |
8199 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
8200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
8201 | "6", 7); | |
252b5132 | 8202 | --mips_opts.noreorder; |
2396cfb9 | 8203 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
8204 | break; |
8205 | ||
8206 | case M_DMUL: | |
8207 | dbl = 1; | |
8208 | case M_MUL: | |
2396cfb9 | 8209 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 8210 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
8211 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
8212 | zreg); | |
252b5132 RH |
8213 | return; |
8214 | ||
8215 | case M_DSUBU_I: | |
8216 | dbl = 1; | |
8217 | goto do_subu; | |
8218 | case M_SUBU_I: | |
8219 | do_subu: | |
8220 | if (imm_expr.X_op != O_constant) | |
8221 | as_bad (_("Unsupported large constant")); | |
8222 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8223 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 8224 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8225 | break; |
8226 | ||
8227 | case M_SUBU_I_2: | |
8228 | if (imm_expr.X_op != O_constant) | |
8229 | as_bad (_("Unsupported large constant")); | |
8230 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8231 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
8232 | "x,k", xreg); | |
8233 | break; | |
8234 | ||
8235 | case M_DSUBU_I_2: | |
8236 | if (imm_expr.X_op != O_constant) | |
8237 | as_bad (_("Unsupported large constant")); | |
8238 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8239 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
8240 | "y,j", yreg); | |
8241 | break; | |
8242 | ||
8243 | case M_BEQ: | |
8244 | s = "cmp"; | |
8245 | s2 = "bteqz"; | |
8246 | goto do_branch; | |
8247 | case M_BNE: | |
8248 | s = "cmp"; | |
8249 | s2 = "btnez"; | |
8250 | goto do_branch; | |
8251 | case M_BLT: | |
8252 | s = "slt"; | |
8253 | s2 = "btnez"; | |
8254 | goto do_branch; | |
8255 | case M_BLTU: | |
8256 | s = "sltu"; | |
8257 | s2 = "btnez"; | |
8258 | goto do_branch; | |
8259 | case M_BLE: | |
8260 | s = "slt"; | |
8261 | s2 = "bteqz"; | |
8262 | goto do_reverse_branch; | |
8263 | case M_BLEU: | |
8264 | s = "sltu"; | |
8265 | s2 = "bteqz"; | |
8266 | goto do_reverse_branch; | |
8267 | case M_BGE: | |
8268 | s = "slt"; | |
8269 | s2 = "bteqz"; | |
8270 | goto do_branch; | |
8271 | case M_BGEU: | |
8272 | s = "sltu"; | |
8273 | s2 = "bteqz"; | |
8274 | goto do_branch; | |
8275 | case M_BGT: | |
8276 | s = "slt"; | |
8277 | s2 = "btnez"; | |
8278 | goto do_reverse_branch; | |
8279 | case M_BGTU: | |
8280 | s = "sltu"; | |
8281 | s2 = "btnez"; | |
8282 | ||
8283 | do_reverse_branch: | |
8284 | tmp = xreg; | |
8285 | xreg = yreg; | |
8286 | yreg = tmp; | |
8287 | ||
8288 | do_branch: | |
8289 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
8290 | xreg, yreg); | |
8291 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
8292 | break; | |
8293 | ||
8294 | case M_BEQ_I: | |
8295 | s = "cmpi"; | |
8296 | s2 = "bteqz"; | |
8297 | s3 = "x,U"; | |
8298 | goto do_branch_i; | |
8299 | case M_BNE_I: | |
8300 | s = "cmpi"; | |
8301 | s2 = "btnez"; | |
8302 | s3 = "x,U"; | |
8303 | goto do_branch_i; | |
8304 | case M_BLT_I: | |
8305 | s = "slti"; | |
8306 | s2 = "btnez"; | |
8307 | s3 = "x,8"; | |
8308 | goto do_branch_i; | |
8309 | case M_BLTU_I: | |
8310 | s = "sltiu"; | |
8311 | s2 = "btnez"; | |
8312 | s3 = "x,8"; | |
8313 | goto do_branch_i; | |
8314 | case M_BLE_I: | |
8315 | s = "slti"; | |
8316 | s2 = "btnez"; | |
8317 | s3 = "x,8"; | |
8318 | goto do_addone_branch_i; | |
8319 | case M_BLEU_I: | |
8320 | s = "sltiu"; | |
8321 | s2 = "btnez"; | |
8322 | s3 = "x,8"; | |
8323 | goto do_addone_branch_i; | |
8324 | case M_BGE_I: | |
8325 | s = "slti"; | |
8326 | s2 = "bteqz"; | |
8327 | s3 = "x,8"; | |
8328 | goto do_branch_i; | |
8329 | case M_BGEU_I: | |
8330 | s = "sltiu"; | |
8331 | s2 = "bteqz"; | |
8332 | s3 = "x,8"; | |
8333 | goto do_branch_i; | |
8334 | case M_BGT_I: | |
8335 | s = "slti"; | |
8336 | s2 = "bteqz"; | |
8337 | s3 = "x,8"; | |
8338 | goto do_addone_branch_i; | |
8339 | case M_BGTU_I: | |
8340 | s = "sltiu"; | |
8341 | s2 = "bteqz"; | |
8342 | s3 = "x,8"; | |
8343 | ||
8344 | do_addone_branch_i: | |
8345 | if (imm_expr.X_op != O_constant) | |
8346 | as_bad (_("Unsupported large constant")); | |
8347 | ++imm_expr.X_add_number; | |
8348 | ||
8349 | do_branch_i: | |
8350 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
8351 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
8352 | break; | |
8353 | ||
8354 | case M_ABS: | |
8355 | expr1.X_add_number = 0; | |
98d3f06f | 8356 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 8357 | if (xreg != yreg) |
ea1fb5dc | 8358 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
8359 | expr1.X_add_number = 2; |
8360 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
8361 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
8362 | "neg", "x,w", xreg, xreg); | |
8363 | } | |
8364 | } | |
8365 | ||
8366 | /* For consistency checking, verify that all bits are specified either | |
8367 | by the match/mask part of the instruction definition, or by the | |
8368 | operand list. */ | |
8369 | static int | |
8370 | validate_mips_insn (opc) | |
8371 | const struct mips_opcode *opc; | |
8372 | { | |
8373 | const char *p = opc->args; | |
8374 | char c; | |
8375 | unsigned long used_bits = opc->mask; | |
8376 | ||
8377 | if ((used_bits & opc->match) != opc->match) | |
8378 | { | |
8379 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8380 | opc->name, opc->args); | |
8381 | return 0; | |
8382 | } | |
8383 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8384 | while (*p) | |
8385 | switch (c = *p++) | |
8386 | { | |
8387 | case ',': break; | |
8388 | case '(': break; | |
8389 | case ')': break; | |
af7ee8bf CD |
8390 | case '+': |
8391 | switch (c = *p++) | |
8392 | { | |
8393 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8394 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8395 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8396 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8397 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8398 | default: |
8399 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8400 | c, opc->name, opc->args); | |
8401 | return 0; | |
8402 | } | |
8403 | break; | |
252b5132 RH |
8404 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8405 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8406 | case 'A': break; | |
4372b673 | 8407 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8408 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8409 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8410 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8411 | case 'F': break; | |
8412 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8413 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8414 | case 'I': break; |
e972090a | 8415 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8416 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8417 | case 'L': break; |
8418 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8419 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8420 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8421 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8422 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8423 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8424 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8425 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8426 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8427 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8428 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8429 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8430 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8431 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8432 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8433 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8434 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8435 | case 'f': break; | |
8436 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8437 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8438 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8439 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8440 | case 'l': break; | |
8441 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8442 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8443 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8444 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8445 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8446 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8447 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8448 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8449 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8450 | case 'x': break; | |
8451 | case 'z': break; | |
8452 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8453 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8454 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8455 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8456 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8457 | case '[': break; | |
8458 | case ']': break; | |
252b5132 RH |
8459 | default: |
8460 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8461 | c, opc->name, opc->args); | |
8462 | return 0; | |
8463 | } | |
8464 | #undef USE_BITS | |
8465 | if (used_bits != 0xffffffff) | |
8466 | { | |
8467 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8468 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8469 | return 0; | |
8470 | } | |
8471 | return 1; | |
8472 | } | |
8473 | ||
8474 | /* This routine assembles an instruction into its binary format. As a | |
8475 | side effect, it sets one of the global variables imm_reloc or | |
8476 | offset_reloc to the type of relocation to do if one of the operands | |
8477 | is an address expression. */ | |
8478 | ||
8479 | static void | |
8480 | mips_ip (str, ip) | |
8481 | char *str; | |
8482 | struct mips_cl_insn *ip; | |
8483 | { | |
8484 | char *s; | |
8485 | const char *args; | |
43841e91 | 8486 | char c = 0; |
252b5132 RH |
8487 | struct mips_opcode *insn; |
8488 | char *argsStart; | |
8489 | unsigned int regno; | |
8490 | unsigned int lastregno = 0; | |
af7ee8bf | 8491 | unsigned int lastpos = 0; |
071742cf | 8492 | unsigned int limlo, limhi; |
252b5132 RH |
8493 | char *s_reset; |
8494 | char save_c = 0; | |
252b5132 RH |
8495 | |
8496 | insn_error = NULL; | |
8497 | ||
8498 | /* If the instruction contains a '.', we first try to match an instruction | |
8499 | including the '.'. Then we try again without the '.'. */ | |
8500 | insn = NULL; | |
3882b010 | 8501 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8502 | continue; |
8503 | ||
8504 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8505 | the call to hash_find. Save the character we replaced just in case we | |
8506 | have to re-parse the instruction. */ | |
3882b010 | 8507 | if (ISSPACE (*s)) |
252b5132 RH |
8508 | { |
8509 | save_c = *s; | |
8510 | *s++ = '\0'; | |
8511 | } | |
bdaaa2e1 | 8512 | |
252b5132 RH |
8513 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8514 | ||
8515 | /* If we didn't find the instruction in the opcode table, try again, but | |
8516 | this time with just the instruction up to, but not including the | |
8517 | first '.'. */ | |
8518 | if (insn == NULL) | |
8519 | { | |
bdaaa2e1 | 8520 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8521 | if (save_c) |
8522 | *(--s) = save_c; | |
8523 | ||
8524 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8525 | for (s = str; |
8526 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8527 | ++s) | |
252b5132 RH |
8528 | continue; |
8529 | ||
8530 | /* If we did not find a '.', then we can quit now. */ | |
8531 | if (*s != '.') | |
8532 | { | |
8533 | insn_error = "unrecognized opcode"; | |
8534 | return; | |
8535 | } | |
8536 | ||
8537 | /* Lookup the instruction in the hash table. */ | |
8538 | *s++ = '\0'; | |
8539 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8540 | { | |
8541 | insn_error = "unrecognized opcode"; | |
8542 | return; | |
8543 | } | |
252b5132 RH |
8544 | } |
8545 | ||
8546 | argsStart = s; | |
8547 | for (;;) | |
8548 | { | |
b34976b6 | 8549 | bfd_boolean ok; |
252b5132 RH |
8550 | |
8551 | assert (strcmp (insn->name, str) == 0); | |
8552 | ||
1f25f5d3 CD |
8553 | if (OPCODE_IS_MEMBER (insn, |
8554 | (mips_opts.isa | |
3396de36 | 8555 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8556 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8557 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 8558 | mips_arch)) |
b34976b6 | 8559 | ok = TRUE; |
bdaaa2e1 | 8560 | else |
b34976b6 | 8561 | ok = FALSE; |
bdaaa2e1 | 8562 | |
252b5132 RH |
8563 | if (insn->pinfo != INSN_MACRO) |
8564 | { | |
ec68c924 | 8565 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8566 | ok = FALSE; |
252b5132 RH |
8567 | } |
8568 | ||
8569 | if (! ok) | |
8570 | { | |
8571 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8572 | && strcmp (insn->name, insn[1].name) == 0) | |
8573 | { | |
8574 | ++insn; | |
8575 | continue; | |
8576 | } | |
252b5132 | 8577 | else |
beae10d5 | 8578 | { |
268f6bed L |
8579 | if (!insn_error) |
8580 | { | |
8581 | static char buf[100]; | |
316f5878 RS |
8582 | if (mips_arch_info->is_isa) |
8583 | sprintf (buf, | |
8584 | _("opcode not supported at this ISA level (%s)"), | |
8585 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8586 | else | |
8587 | sprintf (buf, | |
8588 | _("opcode not supported on this processor: %s (%s)"), | |
8589 | mips_arch_info->name, | |
8590 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8591 | insn_error = buf; |
8592 | } | |
8593 | if (save_c) | |
8594 | *(--s) = save_c; | |
2bd7f1f3 | 8595 | return; |
252b5132 | 8596 | } |
252b5132 RH |
8597 | } |
8598 | ||
8599 | ip->insn_mo = insn; | |
8600 | ip->insn_opcode = insn->match; | |
268f6bed | 8601 | insn_error = NULL; |
252b5132 RH |
8602 | for (args = insn->args;; ++args) |
8603 | { | |
deec1734 CD |
8604 | int is_mdmx; |
8605 | ||
ad8d3bb3 | 8606 | s += strspn (s, " \t"); |
deec1734 | 8607 | is_mdmx = 0; |
252b5132 RH |
8608 | switch (*args) |
8609 | { | |
8610 | case '\0': /* end of args */ | |
8611 | if (*s == '\0') | |
8612 | return; | |
8613 | break; | |
8614 | ||
8615 | case ',': | |
8616 | if (*s++ == *args) | |
8617 | continue; | |
8618 | s--; | |
8619 | switch (*++args) | |
8620 | { | |
8621 | case 'r': | |
8622 | case 'v': | |
38487616 | 8623 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8624 | continue; |
8625 | ||
8626 | case 'w': | |
38487616 TS |
8627 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8628 | continue; | |
8629 | ||
252b5132 | 8630 | case 'W': |
38487616 | 8631 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8632 | continue; |
8633 | ||
8634 | case 'V': | |
38487616 | 8635 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8636 | continue; |
8637 | } | |
8638 | break; | |
8639 | ||
8640 | case '(': | |
8641 | /* Handle optional base register. | |
8642 | Either the base register is omitted or | |
bdaaa2e1 | 8643 | we must have a left paren. */ |
252b5132 RH |
8644 | /* This is dependent on the next operand specifier |
8645 | is a base register specification. */ | |
8646 | assert (args[1] == 'b' || args[1] == '5' | |
8647 | || args[1] == '-' || args[1] == '4'); | |
8648 | if (*s == '\0') | |
8649 | return; | |
8650 | ||
8651 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8652 | case '[': |
8653 | case ']': | |
252b5132 RH |
8654 | if (*s++ == *args) |
8655 | continue; | |
8656 | break; | |
8657 | ||
af7ee8bf CD |
8658 | case '+': /* Opcode extension character. */ |
8659 | switch (*++args) | |
8660 | { | |
071742cf CD |
8661 | case 'A': /* ins/ext position, becomes LSB. */ |
8662 | limlo = 0; | |
8663 | limhi = 31; | |
8664 | my_getExpression (&imm_expr, s); | |
8665 | check_absolute_expr (ip, &imm_expr); | |
8666 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8667 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8668 | { | |
8669 | as_bad (_("Improper position (%lu)"), | |
8670 | (unsigned long) imm_expr.X_add_number); | |
8671 | imm_expr.X_add_number = limlo; | |
8672 | } | |
8673 | lastpos = imm_expr.X_add_number; | |
8674 | ip->insn_opcode |= (imm_expr.X_add_number | |
8675 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8676 | imm_expr.X_op = O_absent; | |
8677 | s = expr_end; | |
8678 | continue; | |
8679 | ||
8680 | case 'B': /* ins size, becomes MSB. */ | |
8681 | limlo = 1; | |
8682 | limhi = 32; | |
8683 | my_getExpression (&imm_expr, s); | |
8684 | check_absolute_expr (ip, &imm_expr); | |
8685 | /* Check for negative input so that small negative numbers | |
8686 | will not succeed incorrectly. The checks against | |
8687 | (pos+size) transitively check "size" itself, | |
8688 | assuming that "pos" is reasonable. */ | |
8689 | if ((long) imm_expr.X_add_number < 0 | |
8690 | || ((unsigned long) imm_expr.X_add_number | |
8691 | + lastpos) < limlo | |
8692 | || ((unsigned long) imm_expr.X_add_number | |
8693 | + lastpos) > limhi) | |
8694 | { | |
8695 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8696 | (unsigned long) imm_expr.X_add_number, | |
8697 | (unsigned long) lastpos); | |
8698 | imm_expr.X_add_number = limlo - lastpos; | |
8699 | } | |
8700 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8701 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8702 | imm_expr.X_op = O_absent; | |
8703 | s = expr_end; | |
8704 | continue; | |
8705 | ||
8706 | case 'C': /* ext size, becomes MSBD. */ | |
8707 | limlo = 1; | |
8708 | limhi = 32; | |
8709 | my_getExpression (&imm_expr, s); | |
8710 | check_absolute_expr (ip, &imm_expr); | |
8711 | /* Check for negative input so that small negative numbers | |
8712 | will not succeed incorrectly. The checks against | |
8713 | (pos+size) transitively check "size" itself, | |
8714 | assuming that "pos" is reasonable. */ | |
8715 | if ((long) imm_expr.X_add_number < 0 | |
8716 | || ((unsigned long) imm_expr.X_add_number | |
8717 | + lastpos) < limlo | |
8718 | || ((unsigned long) imm_expr.X_add_number | |
8719 | + lastpos) > limhi) | |
8720 | { | |
8721 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8722 | (unsigned long) imm_expr.X_add_number, | |
8723 | (unsigned long) lastpos); | |
8724 | imm_expr.X_add_number = limlo - lastpos; | |
8725 | } | |
8726 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8727 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8728 | imm_expr.X_op = O_absent; | |
8729 | s = expr_end; | |
8730 | continue; | |
af7ee8bf | 8731 | |
bbcc0807 CD |
8732 | case 'D': |
8733 | /* +D is for disassembly only; never match. */ | |
8734 | break; | |
8735 | ||
af7ee8bf CD |
8736 | default: |
8737 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8738 | *args, insn->name, insn->args); | |
8739 | /* Further processing is fruitless. */ | |
8740 | return; | |
8741 | } | |
8742 | break; | |
8743 | ||
252b5132 RH |
8744 | case '<': /* must be at least one digit */ |
8745 | /* | |
8746 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8747 | * than 31 or less than 0, then the shift amount should be |
8748 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8749 | * We issue a warning and mask out all but the low 5 bits. |
8750 | */ | |
8751 | my_getExpression (&imm_expr, s); | |
8752 | check_absolute_expr (ip, &imm_expr); | |
8753 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8754 | { | |
793b27f4 TS |
8755 | as_warn (_("Improper shift amount (%lu)"), |
8756 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8757 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8758 | } |
38487616 | 8759 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8760 | imm_expr.X_op = O_absent; |
8761 | s = expr_end; | |
8762 | continue; | |
8763 | ||
8764 | case '>': /* shift amount minus 32 */ | |
8765 | my_getExpression (&imm_expr, s); | |
8766 | check_absolute_expr (ip, &imm_expr); | |
8767 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8768 | || (unsigned long) imm_expr.X_add_number > 63) | |
8769 | break; | |
38487616 | 8770 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8771 | imm_expr.X_op = O_absent; |
8772 | s = expr_end; | |
8773 | continue; | |
8774 | ||
252b5132 RH |
8775 | case 'k': /* cache code */ |
8776 | case 'h': /* prefx code */ | |
8777 | my_getExpression (&imm_expr, s); | |
8778 | check_absolute_expr (ip, &imm_expr); | |
8779 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8780 | { | |
8781 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8782 | ip->insn_mo->name, | |
8783 | (unsigned long) imm_expr.X_add_number); | |
8784 | imm_expr.X_add_number &= 0x1f; | |
8785 | } | |
8786 | if (*args == 'k') | |
8787 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8788 | else | |
8789 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8790 | imm_expr.X_op = O_absent; | |
8791 | s = expr_end; | |
8792 | continue; | |
8793 | ||
8794 | case 'c': /* break code */ | |
8795 | my_getExpression (&imm_expr, s); | |
8796 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8797 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8798 | { |
793b27f4 TS |
8799 | as_warn (_("Illegal break code (%lu)"), |
8800 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8801 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8802 | } |
38487616 | 8803 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8804 | imm_expr.X_op = O_absent; |
8805 | s = expr_end; | |
8806 | continue; | |
8807 | ||
8808 | case 'q': /* lower break code */ | |
8809 | my_getExpression (&imm_expr, s); | |
8810 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8811 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8812 | { |
793b27f4 TS |
8813 | as_warn (_("Illegal lower break code (%lu)"), |
8814 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8815 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8816 | } |
38487616 | 8817 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8818 | imm_expr.X_op = O_absent; |
8819 | s = expr_end; | |
8820 | continue; | |
8821 | ||
4372b673 | 8822 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8823 | my_getExpression (&imm_expr, s); |
156c2f8b | 8824 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8825 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8826 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8827 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8828 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8829 | imm_expr.X_op = O_absent; |
8830 | s = expr_end; | |
8831 | continue; | |
8832 | ||
98d3f06f | 8833 | case 'C': /* Coprocessor code */ |
beae10d5 | 8834 | my_getExpression (&imm_expr, s); |
252b5132 | 8835 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8836 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8837 | { |
793b27f4 TS |
8838 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8839 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8840 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8841 | } |
beae10d5 KH |
8842 | ip->insn_opcode |= imm_expr.X_add_number; |
8843 | imm_expr.X_op = O_absent; | |
8844 | s = expr_end; | |
8845 | continue; | |
252b5132 | 8846 | |
4372b673 NC |
8847 | case 'J': /* 19-bit wait code. */ |
8848 | my_getExpression (&imm_expr, s); | |
8849 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8850 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8851 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8852 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8853 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8854 | imm_expr.X_op = O_absent; |
8855 | s = expr_end; | |
8856 | continue; | |
8857 | ||
252b5132 | 8858 | case 'P': /* Performance register */ |
beae10d5 | 8859 | my_getExpression (&imm_expr, s); |
252b5132 | 8860 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8861 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8862 | { |
793b27f4 TS |
8863 | as_warn (_("Invalid performance register (%lu)"), |
8864 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8865 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8866 | } |
38487616 | 8867 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8868 | imm_expr.X_op = O_absent; |
8869 | s = expr_end; | |
8870 | continue; | |
252b5132 RH |
8871 | |
8872 | case 'b': /* base register */ | |
8873 | case 'd': /* destination register */ | |
8874 | case 's': /* source register */ | |
8875 | case 't': /* target register */ | |
8876 | case 'r': /* both target and source */ | |
8877 | case 'v': /* both dest and source */ | |
8878 | case 'w': /* both dest and target */ | |
8879 | case 'E': /* coprocessor target register */ | |
8880 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8881 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8882 | case 'x': /* ignore register name */ |
8883 | case 'z': /* must be zero register */ | |
4372b673 | 8884 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8885 | s_reset = s; |
8886 | if (s[0] == '$') | |
8887 | { | |
8888 | ||
3882b010 | 8889 | if (ISDIGIT (s[1])) |
252b5132 RH |
8890 | { |
8891 | ++s; | |
8892 | regno = 0; | |
8893 | do | |
8894 | { | |
8895 | regno *= 10; | |
8896 | regno += *s - '0'; | |
8897 | ++s; | |
8898 | } | |
3882b010 | 8899 | while (ISDIGIT (*s)); |
252b5132 RH |
8900 | if (regno > 31) |
8901 | as_bad (_("Invalid register number (%d)"), regno); | |
8902 | } | |
af7ee8bf | 8903 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8904 | goto notreg; |
8905 | else | |
8906 | { | |
76db943d TS |
8907 | if (s[1] == 'r' && s[2] == 'a') |
8908 | { | |
8909 | s += 3; | |
8910 | regno = RA; | |
8911 | } | |
8912 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8913 | { |
8914 | s += 3; | |
8915 | regno = FP; | |
8916 | } | |
8917 | else if (s[1] == 's' && s[2] == 'p') | |
8918 | { | |
8919 | s += 3; | |
8920 | regno = SP; | |
8921 | } | |
8922 | else if (s[1] == 'g' && s[2] == 'p') | |
8923 | { | |
8924 | s += 3; | |
8925 | regno = GP; | |
8926 | } | |
8927 | else if (s[1] == 'a' && s[2] == 't') | |
8928 | { | |
8929 | s += 3; | |
8930 | regno = AT; | |
8931 | } | |
8932 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8933 | { | |
8934 | s += 4; | |
8935 | regno = KT0; | |
8936 | } | |
8937 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8938 | { | |
8939 | s += 4; | |
8940 | regno = KT1; | |
8941 | } | |
85b51719 TS |
8942 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8943 | { | |
8944 | s += 5; | |
8945 | regno = ZERO; | |
8946 | } | |
252b5132 RH |
8947 | else if (itbl_have_entries) |
8948 | { | |
8949 | char *p, *n; | |
d7ba4a77 | 8950 | unsigned long r; |
252b5132 | 8951 | |
d7ba4a77 | 8952 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8953 | n = itbl_get_field (&p); /* n is name */ |
8954 | ||
d7ba4a77 ILT |
8955 | /* See if this is a register defined in an |
8956 | itbl entry. */ | |
8957 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8958 | { |
8959 | /* Get_field advances to the start of | |
8960 | the next field, so we need to back | |
d7ba4a77 | 8961 | rack to the end of the last field. */ |
bdaaa2e1 | 8962 | if (p) |
252b5132 | 8963 | s = p - 1; |
bdaaa2e1 | 8964 | else |
d7ba4a77 | 8965 | s = strchr (s, '\0'); |
252b5132 RH |
8966 | regno = r; |
8967 | } | |
8968 | else | |
8969 | goto notreg; | |
beae10d5 | 8970 | } |
252b5132 RH |
8971 | else |
8972 | goto notreg; | |
8973 | } | |
8974 | if (regno == AT | |
8975 | && ! mips_opts.noat | |
8976 | && *args != 'E' | |
af7ee8bf CD |
8977 | && *args != 'G' |
8978 | && *args != 'K') | |
252b5132 RH |
8979 | as_warn (_("Used $at without \".set noat\"")); |
8980 | c = *args; | |
8981 | if (*s == ' ') | |
f9419b05 | 8982 | ++s; |
252b5132 RH |
8983 | if (args[1] != *s) |
8984 | { | |
8985 | if (c == 'r' || c == 'v' || c == 'w') | |
8986 | { | |
8987 | regno = lastregno; | |
8988 | s = s_reset; | |
f9419b05 | 8989 | ++args; |
252b5132 RH |
8990 | } |
8991 | } | |
8992 | /* 'z' only matches $0. */ | |
8993 | if (c == 'z' && regno != 0) | |
8994 | break; | |
8995 | ||
bdaaa2e1 KH |
8996 | /* Now that we have assembled one operand, we use the args string |
8997 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8998 | switch (c) |
8999 | { | |
9000 | case 'r': | |
9001 | case 's': | |
9002 | case 'v': | |
9003 | case 'b': | |
38487616 | 9004 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
9005 | break; |
9006 | case 'd': | |
9007 | case 'G': | |
af7ee8bf | 9008 | case 'K': |
38487616 | 9009 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 9010 | break; |
4372b673 | 9011 | case 'U': |
38487616 TS |
9012 | ip->insn_opcode |= regno << OP_SH_RD; |
9013 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 9014 | break; |
252b5132 RH |
9015 | case 'w': |
9016 | case 't': | |
9017 | case 'E': | |
38487616 | 9018 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
9019 | break; |
9020 | case 'x': | |
9021 | /* This case exists because on the r3000 trunc | |
9022 | expands into a macro which requires a gp | |
9023 | register. On the r6000 or r4000 it is | |
9024 | assembled into a single instruction which | |
9025 | ignores the register. Thus the insn version | |
9026 | is MIPS_ISA2 and uses 'x', and the macro | |
9027 | version is MIPS_ISA1 and uses 't'. */ | |
9028 | break; | |
9029 | case 'z': | |
9030 | /* This case is for the div instruction, which | |
9031 | acts differently if the destination argument | |
9032 | is $0. This only matches $0, and is checked | |
9033 | outside the switch. */ | |
9034 | break; | |
9035 | case 'D': | |
9036 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9037 | break; | |
9038 | /* What about all other operands like 'i', which | |
9039 | can be specified in the opcode table? */ | |
9040 | } | |
9041 | lastregno = regno; | |
9042 | continue; | |
9043 | } | |
9044 | notreg: | |
9045 | switch (*args++) | |
9046 | { | |
9047 | case 'r': | |
9048 | case 'v': | |
38487616 | 9049 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
9050 | continue; |
9051 | case 'w': | |
38487616 | 9052 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
9053 | continue; |
9054 | } | |
9055 | break; | |
9056 | ||
deec1734 CD |
9057 | case 'O': /* MDMX alignment immediate constant. */ |
9058 | my_getExpression (&imm_expr, s); | |
9059 | check_absolute_expr (ip, &imm_expr); | |
9060 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
9061 | { | |
9062 | as_warn ("Improper align amount (%ld), using low bits", | |
9063 | (long) imm_expr.X_add_number); | |
9064 | imm_expr.X_add_number &= OP_MASK_ALN; | |
9065 | } | |
9066 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
9067 | imm_expr.X_op = O_absent; | |
9068 | s = expr_end; | |
9069 | continue; | |
9070 | ||
9071 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9072 | if (s[0] != '$') | |
9073 | { | |
9074 | /* MDMX Immediate. */ | |
9075 | my_getExpression (&imm_expr, s); | |
9076 | check_absolute_expr (ip, &imm_expr); | |
9077 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
9078 | { | |
9079 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
9080 | (long) imm_expr.X_add_number); | |
9081 | imm_expr.X_add_number &= OP_MASK_FT; | |
9082 | } | |
9083 | imm_expr.X_add_number &= OP_MASK_FT; | |
9084 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9085 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9086 | else | |
9087 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
9088 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
9089 | imm_expr.X_op = O_absent; | |
9090 | s = expr_end; | |
9091 | continue; | |
9092 | } | |
9093 | /* Not MDMX Immediate. Fall through. */ | |
9094 | case 'X': /* MDMX destination register. */ | |
9095 | case 'Y': /* MDMX source register. */ | |
9096 | case 'Z': /* MDMX target register. */ | |
9097 | is_mdmx = 1; | |
252b5132 RH |
9098 | case 'D': /* floating point destination register */ |
9099 | case 'S': /* floating point source register */ | |
9100 | case 'T': /* floating point target register */ | |
9101 | case 'R': /* floating point source register */ | |
9102 | case 'V': | |
9103 | case 'W': | |
9104 | s_reset = s; | |
deec1734 CD |
9105 | /* Accept $fN for FP and MDMX register numbers, and in |
9106 | addition accept $vN for MDMX register numbers. */ | |
9107 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
9108 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
9109 | && ISDIGIT (s[2]))) | |
252b5132 RH |
9110 | { |
9111 | s += 2; | |
9112 | regno = 0; | |
9113 | do | |
9114 | { | |
9115 | regno *= 10; | |
9116 | regno += *s - '0'; | |
9117 | ++s; | |
9118 | } | |
3882b010 | 9119 | while (ISDIGIT (*s)); |
252b5132 RH |
9120 | |
9121 | if (regno > 31) | |
9122 | as_bad (_("Invalid float register number (%d)"), regno); | |
9123 | ||
9124 | if ((regno & 1) != 0 | |
ca4e0257 | 9125 | && HAVE_32BIT_FPRS |
252b5132 RH |
9126 | && ! (strcmp (str, "mtc1") == 0 |
9127 | || strcmp (str, "mfc1") == 0 | |
9128 | || strcmp (str, "lwc1") == 0 | |
9129 | || strcmp (str, "swc1") == 0 | |
9130 | || strcmp (str, "l.s") == 0 | |
9131 | || strcmp (str, "s.s") == 0)) | |
9132 | as_warn (_("Float register should be even, was %d"), | |
9133 | regno); | |
9134 | ||
9135 | c = *args; | |
9136 | if (*s == ' ') | |
f9419b05 | 9137 | ++s; |
252b5132 RH |
9138 | if (args[1] != *s) |
9139 | { | |
9140 | if (c == 'V' || c == 'W') | |
9141 | { | |
9142 | regno = lastregno; | |
9143 | s = s_reset; | |
f9419b05 | 9144 | ++args; |
252b5132 RH |
9145 | } |
9146 | } | |
9147 | switch (c) | |
9148 | { | |
9149 | case 'D': | |
deec1734 | 9150 | case 'X': |
38487616 | 9151 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
9152 | break; |
9153 | case 'V': | |
9154 | case 'S': | |
deec1734 | 9155 | case 'Y': |
38487616 | 9156 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 9157 | break; |
deec1734 CD |
9158 | case 'Q': |
9159 | /* This is like 'Z', but also needs to fix the MDMX | |
9160 | vector/scalar select bits. Note that the | |
9161 | scalar immediate case is handled above. */ | |
9162 | if (*s == '[') | |
9163 | { | |
9164 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9165 | int max_el = (is_qh ? 3 : 7); | |
9166 | s++; | |
9167 | my_getExpression(&imm_expr, s); | |
9168 | check_absolute_expr (ip, &imm_expr); | |
9169 | s = expr_end; | |
9170 | if (imm_expr.X_add_number > max_el) | |
9171 | as_bad(_("Bad element selector %ld"), | |
9172 | (long) imm_expr.X_add_number); | |
9173 | imm_expr.X_add_number &= max_el; | |
9174 | ip->insn_opcode |= (imm_expr.X_add_number | |
9175 | << (OP_SH_VSEL + | |
9176 | (is_qh ? 2 : 1))); | |
9177 | if (*s != ']') | |
9178 | as_warn(_("Expecting ']' found '%s'"), s); | |
9179 | else | |
9180 | s++; | |
9181 | } | |
9182 | else | |
9183 | { | |
9184 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9185 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9186 | << OP_SH_VSEL); | |
9187 | else | |
9188 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9189 | OP_SH_VSEL); | |
9190 | } | |
9191 | /* Fall through */ | |
252b5132 RH |
9192 | case 'W': |
9193 | case 'T': | |
deec1734 | 9194 | case 'Z': |
38487616 | 9195 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
9196 | break; |
9197 | case 'R': | |
38487616 | 9198 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
9199 | break; |
9200 | } | |
9201 | lastregno = regno; | |
9202 | continue; | |
9203 | } | |
9204 | ||
252b5132 RH |
9205 | switch (*args++) |
9206 | { | |
9207 | case 'V': | |
38487616 | 9208 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
9209 | continue; |
9210 | case 'W': | |
38487616 | 9211 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
9212 | continue; |
9213 | } | |
9214 | break; | |
9215 | ||
9216 | case 'I': | |
9217 | my_getExpression (&imm_expr, s); | |
9218 | if (imm_expr.X_op != O_big | |
9219 | && imm_expr.X_op != O_constant) | |
9220 | insn_error = _("absolute expression required"); | |
9221 | s = expr_end; | |
9222 | continue; | |
9223 | ||
9224 | case 'A': | |
9225 | my_getExpression (&offset_expr, s); | |
f6688943 | 9226 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9227 | s = expr_end; |
9228 | continue; | |
9229 | ||
9230 | case 'F': | |
9231 | case 'L': | |
9232 | case 'f': | |
9233 | case 'l': | |
9234 | { | |
9235 | int f64; | |
ca4e0257 | 9236 | int using_gprs; |
252b5132 RH |
9237 | char *save_in; |
9238 | char *err; | |
9239 | unsigned char temp[8]; | |
9240 | int len; | |
9241 | unsigned int length; | |
9242 | segT seg; | |
9243 | subsegT subseg; | |
9244 | char *p; | |
9245 | ||
9246 | /* These only appear as the last operand in an | |
9247 | instruction, and every instruction that accepts | |
9248 | them in any variant accepts them in all variants. | |
9249 | This means we don't have to worry about backing out | |
9250 | any changes if the instruction does not match. | |
9251 | ||
9252 | The difference between them is the size of the | |
9253 | floating point constant and where it goes. For 'F' | |
9254 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9255 | is 32 bits. Where the constant is placed is based | |
9256 | on how the MIPS assembler does things: | |
9257 | F -- .rdata | |
9258 | L -- .lit8 | |
9259 | f -- immediate value | |
9260 | l -- .lit4 | |
9261 | ||
9262 | The .lit4 and .lit8 sections are only used if | |
9263 | permitted by the -G argument. | |
9264 | ||
9265 | When generating embedded PIC code, we use the | |
9266 | .lit8 section but not the .lit4 section (we can do | |
9267 | .lit4 inline easily; we need to put .lit8 | |
9268 | somewhere in the data segment, and using .lit8 | |
9269 | permits the linker to eventually combine identical | |
ca4e0257 RS |
9270 | .lit8 entries). |
9271 | ||
9272 | The code below needs to know whether the target register | |
9273 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9274 | 'F' are used with GPR-based instructions and 'l' and | |
9275 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9276 | |
9277 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9278 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9279 | |
9280 | save_in = input_line_pointer; | |
9281 | input_line_pointer = s; | |
9282 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9283 | length = len; | |
9284 | s = input_line_pointer; | |
9285 | input_line_pointer = save_in; | |
9286 | if (err != NULL && *err != '\0') | |
9287 | { | |
9288 | as_bad (_("Bad floating point constant: %s"), err); | |
9289 | memset (temp, '\0', sizeof temp); | |
9290 | length = f64 ? 8 : 4; | |
9291 | } | |
9292 | ||
156c2f8b | 9293 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9294 | |
9295 | if (*args == 'f' | |
9296 | || (*args == 'l' | |
9297 | && (! USE_GLOBAL_POINTER_OPT | |
9298 | || mips_pic == EMBEDDED_PIC | |
9299 | || g_switch_value < 4 | |
9300 | || (temp[0] == 0 && temp[1] == 0) | |
9301 | || (temp[2] == 0 && temp[3] == 0)))) | |
9302 | { | |
9303 | imm_expr.X_op = O_constant; | |
9304 | if (! target_big_endian) | |
9305 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9306 | else | |
9307 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9308 | } | |
9309 | else if (length > 4 | |
119d663a | 9310 | && ! mips_disable_float_construction |
ca4e0257 RS |
9311 | /* Constants can only be constructed in GPRs and |
9312 | copied to FPRs if the GPRs are at least as wide | |
9313 | as the FPRs. Force the constant into memory if | |
9314 | we are using 64-bit FPRs but the GPRs are only | |
9315 | 32 bits wide. */ | |
9316 | && (using_gprs | |
9317 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9318 | && ((temp[0] == 0 && temp[1] == 0) |
9319 | || (temp[2] == 0 && temp[3] == 0)) | |
9320 | && ((temp[4] == 0 && temp[5] == 0) | |
9321 | || (temp[6] == 0 && temp[7] == 0))) | |
9322 | { | |
ca4e0257 RS |
9323 | /* The value is simple enough to load with a couple of |
9324 | instructions. If using 32-bit registers, set | |
9325 | imm_expr to the high order 32 bits and offset_expr to | |
9326 | the low order 32 bits. Otherwise, set imm_expr to | |
9327 | the entire 64 bit constant. */ | |
9328 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9329 | { |
9330 | imm_expr.X_op = O_constant; | |
9331 | offset_expr.X_op = O_constant; | |
9332 | if (! target_big_endian) | |
9333 | { | |
9334 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9335 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9336 | } | |
9337 | else | |
9338 | { | |
9339 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9340 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9341 | } | |
9342 | if (offset_expr.X_add_number == 0) | |
9343 | offset_expr.X_op = O_absent; | |
9344 | } | |
9345 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9346 | { | |
9347 | imm_expr.X_op = O_constant; | |
9348 | if (! target_big_endian) | |
9349 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9350 | else | |
9351 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9352 | } | |
9353 | else | |
9354 | { | |
9355 | imm_expr.X_op = O_big; | |
9356 | imm_expr.X_add_number = 4; | |
9357 | if (! target_big_endian) | |
9358 | { | |
9359 | generic_bignum[0] = bfd_getl16 (temp); | |
9360 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9361 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9362 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9363 | } | |
9364 | else | |
9365 | { | |
9366 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9367 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9368 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9369 | generic_bignum[3] = bfd_getb16 (temp); | |
9370 | } | |
9371 | } | |
9372 | } | |
9373 | else | |
9374 | { | |
9375 | const char *newname; | |
9376 | segT new_seg; | |
9377 | ||
9378 | /* Switch to the right section. */ | |
9379 | seg = now_seg; | |
9380 | subseg = now_subseg; | |
9381 | switch (*args) | |
9382 | { | |
9383 | default: /* unused default case avoids warnings. */ | |
9384 | case 'L': | |
9385 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9386 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9387 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9388 | newname = ".lit8"; |
9389 | break; | |
9390 | case 'F': | |
bb2d6cd7 GK |
9391 | if (mips_pic == EMBEDDED_PIC) |
9392 | newname = ".lit8"; | |
9393 | else | |
9394 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9395 | break; |
9396 | case 'l': | |
9397 | assert (!USE_GLOBAL_POINTER_OPT | |
9398 | || g_switch_value >= 4); | |
9399 | newname = ".lit4"; | |
9400 | break; | |
9401 | } | |
9402 | new_seg = subseg_new (newname, (subsegT) 0); | |
9403 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9404 | bfd_set_section_flags (stdoutput, new_seg, | |
9405 | (SEC_ALLOC | |
9406 | | SEC_LOAD | |
9407 | | SEC_READONLY | |
9408 | | SEC_DATA)); | |
9409 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9410 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9411 | && strcmp (TARGET_OS, "elf") != 0) | |
9412 | record_alignment (new_seg, 4); | |
9413 | else | |
9414 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9415 | if (seg == now_seg) | |
9416 | as_bad (_("Can't use floating point insn in this section")); | |
9417 | ||
9418 | /* Set the argument to the current address in the | |
9419 | section. */ | |
9420 | offset_expr.X_op = O_symbol; | |
9421 | offset_expr.X_add_symbol = | |
9422 | symbol_new ("L0\001", now_seg, | |
9423 | (valueT) frag_now_fix (), frag_now); | |
9424 | offset_expr.X_add_number = 0; | |
9425 | ||
9426 | /* Put the floating point number into the section. */ | |
9427 | p = frag_more ((int) length); | |
9428 | memcpy (p, temp, length); | |
9429 | ||
9430 | /* Switch back to the original section. */ | |
9431 | subseg_set (seg, subseg); | |
9432 | } | |
9433 | } | |
9434 | continue; | |
9435 | ||
9436 | case 'i': /* 16 bit unsigned immediate */ | |
9437 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9438 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9439 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9440 | { |
9441 | int more; | |
5e0116d5 RS |
9442 | offsetT minval, maxval; |
9443 | ||
9444 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9445 | && strcmp (insn->name, insn[1].name) == 0); | |
9446 | ||
9447 | /* If the expression was written as an unsigned number, | |
9448 | only treat it as signed if there are no more | |
9449 | alternatives. */ | |
9450 | if (more | |
9451 | && *args == 'j' | |
9452 | && sizeof (imm_expr.X_add_number) <= 4 | |
9453 | && imm_expr.X_op == O_constant | |
9454 | && imm_expr.X_add_number < 0 | |
9455 | && imm_expr.X_unsigned | |
9456 | && HAVE_64BIT_GPRS) | |
9457 | break; | |
9458 | ||
9459 | /* For compatibility with older assemblers, we accept | |
9460 | 0x8000-0xffff as signed 16-bit numbers when only | |
9461 | signed numbers are allowed. */ | |
9462 | if (*args == 'i') | |
9463 | minval = 0, maxval = 0xffff; | |
9464 | else if (more) | |
9465 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9466 | else |
5e0116d5 RS |
9467 | minval = -0x8000, maxval = 0xffff; |
9468 | ||
9469 | if (imm_expr.X_op != O_constant | |
9470 | || imm_expr.X_add_number < minval | |
9471 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9472 | { |
9473 | if (more) | |
9474 | break; | |
2ae7e77b AH |
9475 | if (imm_expr.X_op == O_constant |
9476 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9477 | as_bad (_("expression out of range")); |
252b5132 RH |
9478 | } |
9479 | } | |
9480 | s = expr_end; | |
9481 | continue; | |
9482 | ||
9483 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9484 | /* Check whether there is only a single bracketed expression |
9485 | left. If so, it must be the base register and the | |
9486 | constant must be zero. */ | |
9487 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9488 | { | |
9489 | offset_expr.X_op = O_constant; | |
9490 | offset_expr.X_add_number = 0; | |
9491 | continue; | |
9492 | } | |
252b5132 RH |
9493 | |
9494 | /* If this value won't fit into a 16 bit offset, then go | |
9495 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9496 | code pattern. */ |
5e0116d5 | 9497 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9498 | && (offset_expr.X_op != O_constant |
9499 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9500 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9501 | break; |
9502 | ||
252b5132 RH |
9503 | s = expr_end; |
9504 | continue; | |
9505 | ||
9506 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9507 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9508 | my_getExpression (&offset_expr, s); |
9509 | s = expr_end; | |
9510 | continue; | |
9511 | ||
9512 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9513 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9514 | && imm_expr.X_op == O_constant | |
9515 | && (imm_expr.X_add_number < 0 | |
9516 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9517 | as_bad (_("lui expression not in range 0..65535")); |
9518 | s = expr_end; | |
9519 | continue; | |
9520 | ||
9521 | case 'a': /* 26 bit address */ | |
9522 | my_getExpression (&offset_expr, s); | |
9523 | s = expr_end; | |
f6688943 | 9524 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9525 | continue; |
9526 | ||
9527 | case 'N': /* 3 bit branch condition code */ | |
9528 | case 'M': /* 3 bit compare condition code */ | |
9529 | if (strncmp (s, "$fcc", 4) != 0) | |
9530 | break; | |
9531 | s += 4; | |
9532 | regno = 0; | |
9533 | do | |
9534 | { | |
9535 | regno *= 10; | |
9536 | regno += *s - '0'; | |
9537 | ++s; | |
9538 | } | |
3882b010 | 9539 | while (ISDIGIT (*s)); |
252b5132 RH |
9540 | if (regno > 7) |
9541 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9542 | if (*args == 'N') | |
9543 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9544 | else | |
9545 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9546 | continue; |
252b5132 | 9547 | |
156c2f8b NC |
9548 | case 'H': |
9549 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9550 | s += 2; | |
3882b010 | 9551 | if (ISDIGIT (*s)) |
156c2f8b NC |
9552 | { |
9553 | c = 0; | |
9554 | do | |
9555 | { | |
9556 | c *= 10; | |
9557 | c += *s - '0'; | |
9558 | ++s; | |
9559 | } | |
3882b010 | 9560 | while (ISDIGIT (*s)); |
156c2f8b NC |
9561 | } |
9562 | else | |
9563 | c = 8; /* Invalid sel value. */ | |
9564 | ||
9565 | if (c > 7) | |
9566 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9567 | ip->insn_opcode |= c; | |
9568 | continue; | |
9569 | ||
60b63b72 RS |
9570 | case 'e': |
9571 | /* Must be at least one digit. */ | |
9572 | my_getExpression (&imm_expr, s); | |
9573 | check_absolute_expr (ip, &imm_expr); | |
9574 | ||
9575 | if ((unsigned long) imm_expr.X_add_number | |
9576 | > (unsigned long) OP_MASK_VECBYTE) | |
9577 | { | |
9578 | as_bad (_("bad byte vector index (%ld)"), | |
9579 | (long) imm_expr.X_add_number); | |
9580 | imm_expr.X_add_number = 0; | |
9581 | } | |
9582 | ||
9583 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9584 | imm_expr.X_op = O_absent; | |
9585 | s = expr_end; | |
9586 | continue; | |
9587 | ||
9588 | case '%': | |
9589 | my_getExpression (&imm_expr, s); | |
9590 | check_absolute_expr (ip, &imm_expr); | |
9591 | ||
9592 | if ((unsigned long) imm_expr.X_add_number | |
9593 | > (unsigned long) OP_MASK_VECALIGN) | |
9594 | { | |
9595 | as_bad (_("bad byte vector index (%ld)"), | |
9596 | (long) imm_expr.X_add_number); | |
9597 | imm_expr.X_add_number = 0; | |
9598 | } | |
9599 | ||
9600 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9601 | imm_expr.X_op = O_absent; | |
9602 | s = expr_end; | |
9603 | continue; | |
9604 | ||
252b5132 RH |
9605 | default: |
9606 | as_bad (_("bad char = '%c'\n"), *args); | |
9607 | internalError (); | |
9608 | } | |
9609 | break; | |
9610 | } | |
9611 | /* Args don't match. */ | |
9612 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9613 | !strcmp (insn->name, insn[1].name)) | |
9614 | { | |
9615 | ++insn; | |
9616 | s = argsStart; | |
268f6bed | 9617 | insn_error = _("illegal operands"); |
252b5132 RH |
9618 | continue; |
9619 | } | |
268f6bed L |
9620 | if (save_c) |
9621 | *(--s) = save_c; | |
252b5132 RH |
9622 | insn_error = _("illegal operands"); |
9623 | return; | |
9624 | } | |
9625 | } | |
9626 | ||
9627 | /* This routine assembles an instruction into its binary format when | |
9628 | assembling for the mips16. As a side effect, it sets one of the | |
9629 | global variables imm_reloc or offset_reloc to the type of | |
9630 | relocation to do if one of the operands is an address expression. | |
9631 | It also sets mips16_small and mips16_ext if the user explicitly | |
9632 | requested a small or extended instruction. */ | |
9633 | ||
9634 | static void | |
9635 | mips16_ip (str, ip) | |
9636 | char *str; | |
9637 | struct mips_cl_insn *ip; | |
9638 | { | |
9639 | char *s; | |
9640 | const char *args; | |
9641 | struct mips_opcode *insn; | |
9642 | char *argsstart; | |
9643 | unsigned int regno; | |
9644 | unsigned int lastregno = 0; | |
9645 | char *s_reset; | |
9646 | ||
9647 | insn_error = NULL; | |
9648 | ||
b34976b6 AM |
9649 | mips16_small = FALSE; |
9650 | mips16_ext = FALSE; | |
252b5132 | 9651 | |
3882b010 | 9652 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9653 | ; |
9654 | switch (*s) | |
9655 | { | |
9656 | case '\0': | |
9657 | break; | |
9658 | ||
9659 | case ' ': | |
9660 | *s++ = '\0'; | |
9661 | break; | |
9662 | ||
9663 | case '.': | |
9664 | if (s[1] == 't' && s[2] == ' ') | |
9665 | { | |
9666 | *s = '\0'; | |
b34976b6 | 9667 | mips16_small = TRUE; |
252b5132 RH |
9668 | s += 3; |
9669 | break; | |
9670 | } | |
9671 | else if (s[1] == 'e' && s[2] == ' ') | |
9672 | { | |
9673 | *s = '\0'; | |
b34976b6 | 9674 | mips16_ext = TRUE; |
252b5132 RH |
9675 | s += 3; |
9676 | break; | |
9677 | } | |
9678 | /* Fall through. */ | |
9679 | default: | |
9680 | insn_error = _("unknown opcode"); | |
9681 | return; | |
9682 | } | |
9683 | ||
9684 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9685 | mips16_small = TRUE; |
252b5132 RH |
9686 | |
9687 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9688 | { | |
9689 | insn_error = _("unrecognized opcode"); | |
9690 | return; | |
9691 | } | |
9692 | ||
9693 | argsstart = s; | |
9694 | for (;;) | |
9695 | { | |
9696 | assert (strcmp (insn->name, str) == 0); | |
9697 | ||
9698 | ip->insn_mo = insn; | |
9699 | ip->insn_opcode = insn->match; | |
b34976b6 | 9700 | ip->use_extend = FALSE; |
252b5132 | 9701 | imm_expr.X_op = O_absent; |
f6688943 TS |
9702 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9703 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9704 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9705 | offset_expr.X_op = O_absent; |
f6688943 TS |
9706 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9707 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9708 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9709 | for (args = insn->args; 1; ++args) |
9710 | { | |
9711 | int c; | |
9712 | ||
9713 | if (*s == ' ') | |
9714 | ++s; | |
9715 | ||
9716 | /* In this switch statement we call break if we did not find | |
9717 | a match, continue if we did find a match, or return if we | |
9718 | are done. */ | |
9719 | ||
9720 | c = *args; | |
9721 | switch (c) | |
9722 | { | |
9723 | case '\0': | |
9724 | if (*s == '\0') | |
9725 | { | |
9726 | /* Stuff the immediate value in now, if we can. */ | |
9727 | if (imm_expr.X_op == O_constant | |
f6688943 | 9728 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9729 | && insn->pinfo != INSN_MACRO) |
9730 | { | |
c4e7957c | 9731 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9732 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9733 | mips16_ext, &ip->insn_opcode, |
9734 | &ip->use_extend, &ip->extend); | |
9735 | imm_expr.X_op = O_absent; | |
f6688943 | 9736 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9737 | } |
9738 | ||
9739 | return; | |
9740 | } | |
9741 | break; | |
9742 | ||
9743 | case ',': | |
9744 | if (*s++ == c) | |
9745 | continue; | |
9746 | s--; | |
9747 | switch (*++args) | |
9748 | { | |
9749 | case 'v': | |
9750 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9751 | continue; | |
9752 | case 'w': | |
9753 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9754 | continue; | |
9755 | } | |
9756 | break; | |
9757 | ||
9758 | case '(': | |
9759 | case ')': | |
9760 | if (*s++ == c) | |
9761 | continue; | |
9762 | break; | |
9763 | ||
9764 | case 'v': | |
9765 | case 'w': | |
9766 | if (s[0] != '$') | |
9767 | { | |
9768 | if (c == 'v') | |
9769 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9770 | else | |
9771 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9772 | ++args; | |
9773 | continue; | |
9774 | } | |
9775 | /* Fall through. */ | |
9776 | case 'x': | |
9777 | case 'y': | |
9778 | case 'z': | |
9779 | case 'Z': | |
9780 | case '0': | |
9781 | case 'S': | |
9782 | case 'R': | |
9783 | case 'X': | |
9784 | case 'Y': | |
9785 | if (s[0] != '$') | |
9786 | break; | |
9787 | s_reset = s; | |
3882b010 | 9788 | if (ISDIGIT (s[1])) |
252b5132 RH |
9789 | { |
9790 | ++s; | |
9791 | regno = 0; | |
9792 | do | |
9793 | { | |
9794 | regno *= 10; | |
9795 | regno += *s - '0'; | |
9796 | ++s; | |
9797 | } | |
3882b010 | 9798 | while (ISDIGIT (*s)); |
252b5132 RH |
9799 | if (regno > 31) |
9800 | { | |
9801 | as_bad (_("invalid register number (%d)"), regno); | |
9802 | regno = 2; | |
9803 | } | |
9804 | } | |
9805 | else | |
9806 | { | |
76db943d TS |
9807 | if (s[1] == 'r' && s[2] == 'a') |
9808 | { | |
9809 | s += 3; | |
9810 | regno = RA; | |
9811 | } | |
9812 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9813 | { |
9814 | s += 3; | |
9815 | regno = FP; | |
9816 | } | |
9817 | else if (s[1] == 's' && s[2] == 'p') | |
9818 | { | |
9819 | s += 3; | |
9820 | regno = SP; | |
9821 | } | |
9822 | else if (s[1] == 'g' && s[2] == 'p') | |
9823 | { | |
9824 | s += 3; | |
9825 | regno = GP; | |
9826 | } | |
9827 | else if (s[1] == 'a' && s[2] == 't') | |
9828 | { | |
9829 | s += 3; | |
9830 | regno = AT; | |
9831 | } | |
9832 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9833 | { | |
9834 | s += 4; | |
9835 | regno = KT0; | |
9836 | } | |
9837 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9838 | { | |
9839 | s += 4; | |
9840 | regno = KT1; | |
9841 | } | |
85b51719 TS |
9842 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9843 | { | |
9844 | s += 5; | |
9845 | regno = ZERO; | |
9846 | } | |
252b5132 RH |
9847 | else |
9848 | break; | |
9849 | } | |
9850 | ||
9851 | if (*s == ' ') | |
9852 | ++s; | |
9853 | if (args[1] != *s) | |
9854 | { | |
9855 | if (c == 'v' || c == 'w') | |
9856 | { | |
9857 | regno = mips16_to_32_reg_map[lastregno]; | |
9858 | s = s_reset; | |
f9419b05 | 9859 | ++args; |
252b5132 RH |
9860 | } |
9861 | } | |
9862 | ||
9863 | switch (c) | |
9864 | { | |
9865 | case 'x': | |
9866 | case 'y': | |
9867 | case 'z': | |
9868 | case 'v': | |
9869 | case 'w': | |
9870 | case 'Z': | |
9871 | regno = mips32_to_16_reg_map[regno]; | |
9872 | break; | |
9873 | ||
9874 | case '0': | |
9875 | if (regno != 0) | |
9876 | regno = ILLEGAL_REG; | |
9877 | break; | |
9878 | ||
9879 | case 'S': | |
9880 | if (regno != SP) | |
9881 | regno = ILLEGAL_REG; | |
9882 | break; | |
9883 | ||
9884 | case 'R': | |
9885 | if (regno != RA) | |
9886 | regno = ILLEGAL_REG; | |
9887 | break; | |
9888 | ||
9889 | case 'X': | |
9890 | case 'Y': | |
9891 | if (regno == AT && ! mips_opts.noat) | |
9892 | as_warn (_("used $at without \".set noat\"")); | |
9893 | break; | |
9894 | ||
9895 | default: | |
9896 | internalError (); | |
9897 | } | |
9898 | ||
9899 | if (regno == ILLEGAL_REG) | |
9900 | break; | |
9901 | ||
9902 | switch (c) | |
9903 | { | |
9904 | case 'x': | |
9905 | case 'v': | |
9906 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9907 | break; | |
9908 | case 'y': | |
9909 | case 'w': | |
9910 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9911 | break; | |
9912 | case 'z': | |
9913 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9914 | break; | |
9915 | case 'Z': | |
9916 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9917 | case '0': | |
9918 | case 'S': | |
9919 | case 'R': | |
9920 | break; | |
9921 | case 'X': | |
9922 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9923 | break; | |
9924 | case 'Y': | |
9925 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9926 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9927 | break; | |
9928 | default: | |
9929 | internalError (); | |
9930 | } | |
9931 | ||
9932 | lastregno = regno; | |
9933 | continue; | |
9934 | ||
9935 | case 'P': | |
9936 | if (strncmp (s, "$pc", 3) == 0) | |
9937 | { | |
9938 | s += 3; | |
9939 | continue; | |
9940 | } | |
9941 | break; | |
9942 | ||
9943 | case '<': | |
9944 | case '>': | |
9945 | case '[': | |
9946 | case ']': | |
9947 | case '4': | |
9948 | case '5': | |
9949 | case 'H': | |
9950 | case 'W': | |
9951 | case 'D': | |
9952 | case 'j': | |
9953 | case '8': | |
9954 | case 'V': | |
9955 | case 'C': | |
9956 | case 'U': | |
9957 | case 'k': | |
9958 | case 'K': | |
9959 | if (s[0] == '%' | |
9960 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9961 | { | |
9962 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9963 | and generate the appropriate reloc. If the text | |
9964 | inside %gprel is not a symbol name with an | |
9965 | optional offset, then we generate a normal reloc | |
9966 | and will probably fail later. */ | |
9967 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9968 | if (imm_expr.X_op == O_symbol) | |
9969 | { | |
b34976b6 | 9970 | mips16_ext = TRUE; |
f6688943 | 9971 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9972 | s = expr_end; |
b34976b6 | 9973 | ip->use_extend = TRUE; |
252b5132 RH |
9974 | ip->extend = 0; |
9975 | continue; | |
9976 | } | |
9977 | } | |
9978 | else | |
9979 | { | |
9980 | /* Just pick up a normal expression. */ | |
9981 | my_getExpression (&imm_expr, s); | |
9982 | } | |
9983 | ||
9984 | if (imm_expr.X_op == O_register) | |
9985 | { | |
9986 | /* What we thought was an expression turned out to | |
9987 | be a register. */ | |
9988 | ||
9989 | if (s[0] == '(' && args[1] == '(') | |
9990 | { | |
9991 | /* It looks like the expression was omitted | |
9992 | before a register indirection, which means | |
9993 | that the expression is implicitly zero. We | |
9994 | still set up imm_expr, so that we handle | |
9995 | explicit extensions correctly. */ | |
9996 | imm_expr.X_op = O_constant; | |
9997 | imm_expr.X_add_number = 0; | |
f6688943 | 9998 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9999 | continue; |
10000 | } | |
10001 | ||
10002 | break; | |
10003 | } | |
10004 | ||
10005 | /* We need to relax this instruction. */ | |
f6688943 | 10006 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10007 | s = expr_end; |
10008 | continue; | |
10009 | ||
10010 | case 'p': | |
10011 | case 'q': | |
10012 | case 'A': | |
10013 | case 'B': | |
10014 | case 'E': | |
10015 | /* We use offset_reloc rather than imm_reloc for the PC | |
10016 | relative operands. This lets macros with both | |
10017 | immediate and address operands work correctly. */ | |
10018 | my_getExpression (&offset_expr, s); | |
10019 | ||
10020 | if (offset_expr.X_op == O_register) | |
10021 | break; | |
10022 | ||
10023 | /* We need to relax this instruction. */ | |
f6688943 | 10024 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10025 | s = expr_end; |
10026 | continue; | |
10027 | ||
10028 | case '6': /* break code */ | |
10029 | my_getExpression (&imm_expr, s); | |
10030 | check_absolute_expr (ip, &imm_expr); | |
10031 | if ((unsigned long) imm_expr.X_add_number > 63) | |
10032 | { | |
10033 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10034 | ip->insn_mo->name, | |
10035 | (unsigned long) imm_expr.X_add_number); | |
10036 | imm_expr.X_add_number &= 0x3f; | |
10037 | } | |
10038 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
10039 | imm_expr.X_op = O_absent; | |
10040 | s = expr_end; | |
10041 | continue; | |
10042 | ||
10043 | case 'a': /* 26 bit address */ | |
10044 | my_getExpression (&offset_expr, s); | |
10045 | s = expr_end; | |
f6688943 | 10046 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10047 | ip->insn_opcode <<= 16; |
10048 | continue; | |
10049 | ||
10050 | case 'l': /* register list for entry macro */ | |
10051 | case 'L': /* register list for exit macro */ | |
10052 | { | |
10053 | int mask; | |
10054 | ||
10055 | if (c == 'l') | |
10056 | mask = 0; | |
10057 | else | |
10058 | mask = 7 << 3; | |
10059 | while (*s != '\0') | |
10060 | { | |
10061 | int freg, reg1, reg2; | |
10062 | ||
10063 | while (*s == ' ' || *s == ',') | |
10064 | ++s; | |
10065 | if (*s != '$') | |
10066 | { | |
10067 | as_bad (_("can't parse register list")); | |
10068 | break; | |
10069 | } | |
10070 | ++s; | |
10071 | if (*s != 'f') | |
10072 | freg = 0; | |
10073 | else | |
10074 | { | |
10075 | freg = 1; | |
10076 | ++s; | |
10077 | } | |
10078 | reg1 = 0; | |
3882b010 | 10079 | while (ISDIGIT (*s)) |
252b5132 RH |
10080 | { |
10081 | reg1 *= 10; | |
10082 | reg1 += *s - '0'; | |
10083 | ++s; | |
10084 | } | |
10085 | if (*s == ' ') | |
10086 | ++s; | |
10087 | if (*s != '-') | |
10088 | reg2 = reg1; | |
10089 | else | |
10090 | { | |
10091 | ++s; | |
10092 | if (*s != '$') | |
10093 | break; | |
10094 | ++s; | |
10095 | if (freg) | |
10096 | { | |
10097 | if (*s == 'f') | |
10098 | ++s; | |
10099 | else | |
10100 | { | |
10101 | as_bad (_("invalid register list")); | |
10102 | break; | |
10103 | } | |
10104 | } | |
10105 | reg2 = 0; | |
3882b010 | 10106 | while (ISDIGIT (*s)) |
252b5132 RH |
10107 | { |
10108 | reg2 *= 10; | |
10109 | reg2 += *s - '0'; | |
10110 | ++s; | |
10111 | } | |
10112 | } | |
10113 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10114 | { | |
10115 | mask &= ~ (7 << 3); | |
10116 | mask |= 5 << 3; | |
10117 | } | |
10118 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10119 | { | |
10120 | mask &= ~ (7 << 3); | |
10121 | mask |= 6 << 3; | |
10122 | } | |
10123 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10124 | mask |= (reg2 - 3) << 3; | |
10125 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10126 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10127 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10128 | mask |= 1; |
10129 | else | |
10130 | { | |
10131 | as_bad (_("invalid register list")); | |
10132 | break; | |
10133 | } | |
10134 | } | |
10135 | /* The mask is filled in in the opcode table for the | |
10136 | benefit of the disassembler. We remove it before | |
10137 | applying the actual mask. */ | |
10138 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10139 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10140 | } | |
10141 | continue; | |
10142 | ||
10143 | case 'e': /* extend code */ | |
10144 | my_getExpression (&imm_expr, s); | |
10145 | check_absolute_expr (ip, &imm_expr); | |
10146 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10147 | { | |
10148 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10149 | ip->insn_mo->name, | |
10150 | (unsigned long) imm_expr.X_add_number); | |
10151 | imm_expr.X_add_number &= 0x7ff; | |
10152 | } | |
10153 | ip->insn_opcode |= imm_expr.X_add_number; | |
10154 | imm_expr.X_op = O_absent; | |
10155 | s = expr_end; | |
10156 | continue; | |
10157 | ||
10158 | default: | |
10159 | internalError (); | |
10160 | } | |
10161 | break; | |
10162 | } | |
10163 | ||
10164 | /* Args don't match. */ | |
10165 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10166 | strcmp (insn->name, insn[1].name) == 0) | |
10167 | { | |
10168 | ++insn; | |
10169 | s = argsstart; | |
10170 | continue; | |
10171 | } | |
10172 | ||
10173 | insn_error = _("illegal operands"); | |
10174 | ||
10175 | return; | |
10176 | } | |
10177 | } | |
10178 | ||
10179 | /* This structure holds information we know about a mips16 immediate | |
10180 | argument type. */ | |
10181 | ||
e972090a NC |
10182 | struct mips16_immed_operand |
10183 | { | |
252b5132 RH |
10184 | /* The type code used in the argument string in the opcode table. */ |
10185 | int type; | |
10186 | /* The number of bits in the short form of the opcode. */ | |
10187 | int nbits; | |
10188 | /* The number of bits in the extended form of the opcode. */ | |
10189 | int extbits; | |
10190 | /* The amount by which the short form is shifted when it is used; | |
10191 | for example, the sw instruction has a shift count of 2. */ | |
10192 | int shift; | |
10193 | /* The amount by which the short form is shifted when it is stored | |
10194 | into the instruction code. */ | |
10195 | int op_shift; | |
10196 | /* Non-zero if the short form is unsigned. */ | |
10197 | int unsp; | |
10198 | /* Non-zero if the extended form is unsigned. */ | |
10199 | int extu; | |
10200 | /* Non-zero if the value is PC relative. */ | |
10201 | int pcrel; | |
10202 | }; | |
10203 | ||
10204 | /* The mips16 immediate operand types. */ | |
10205 | ||
10206 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10207 | { | |
10208 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10209 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10210 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10211 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10212 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10213 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10214 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10215 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10216 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10217 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10218 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10219 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10220 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10221 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10222 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10223 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10224 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10225 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10226 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10227 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10228 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10229 | }; | |
10230 | ||
10231 | #define MIPS16_NUM_IMMED \ | |
10232 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10233 | ||
10234 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10235 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10236 | whether an extended value is needed; if one is needed, it sets | |
10237 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10238 | If SMALL is true, an unextended opcode was explicitly requested. | |
10239 | If EXT is true, an extended opcode was explicitly requested. If | |
10240 | WARN is true, warn if EXT does not match reality. */ | |
10241 | ||
10242 | static void | |
10243 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
10244 | extend) | |
10245 | char *file; | |
10246 | unsigned int line; | |
10247 | int type; | |
10248 | offsetT val; | |
b34976b6 AM |
10249 | bfd_boolean warn; |
10250 | bfd_boolean small; | |
10251 | bfd_boolean ext; | |
252b5132 | 10252 | unsigned long *insn; |
b34976b6 | 10253 | bfd_boolean *use_extend; |
252b5132 RH |
10254 | unsigned short *extend; |
10255 | { | |
10256 | register const struct mips16_immed_operand *op; | |
10257 | int mintiny, maxtiny; | |
b34976b6 | 10258 | bfd_boolean needext; |
252b5132 RH |
10259 | |
10260 | op = mips16_immed_operands; | |
10261 | while (op->type != type) | |
10262 | { | |
10263 | ++op; | |
10264 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10265 | } | |
10266 | ||
10267 | if (op->unsp) | |
10268 | { | |
10269 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10270 | { | |
10271 | mintiny = 1; | |
10272 | maxtiny = 1 << op->nbits; | |
10273 | } | |
10274 | else | |
10275 | { | |
10276 | mintiny = 0; | |
10277 | maxtiny = (1 << op->nbits) - 1; | |
10278 | } | |
10279 | } | |
10280 | else | |
10281 | { | |
10282 | mintiny = - (1 << (op->nbits - 1)); | |
10283 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10284 | } | |
10285 | ||
10286 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10287 | if (type == 'p' || type == 'q') | |
10288 | val /= 2; | |
10289 | ||
10290 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10291 | || val < (mintiny << op->shift) | |
10292 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10293 | needext = TRUE; |
252b5132 | 10294 | else |
b34976b6 | 10295 | needext = FALSE; |
252b5132 RH |
10296 | |
10297 | if (warn && ext && ! needext) | |
beae10d5 KH |
10298 | as_warn_where (file, line, |
10299 | _("extended operand requested but not required")); | |
252b5132 RH |
10300 | if (small && needext) |
10301 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10302 | ||
10303 | if (small || (! ext && ! needext)) | |
10304 | { | |
10305 | int insnval; | |
10306 | ||
b34976b6 | 10307 | *use_extend = FALSE; |
252b5132 RH |
10308 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10309 | insnval <<= op->op_shift; | |
10310 | *insn |= insnval; | |
10311 | } | |
10312 | else | |
10313 | { | |
10314 | long minext, maxext; | |
10315 | int extval; | |
10316 | ||
10317 | if (op->extu) | |
10318 | { | |
10319 | minext = 0; | |
10320 | maxext = (1 << op->extbits) - 1; | |
10321 | } | |
10322 | else | |
10323 | { | |
10324 | minext = - (1 << (op->extbits - 1)); | |
10325 | maxext = (1 << (op->extbits - 1)) - 1; | |
10326 | } | |
10327 | if (val < minext || val > maxext) | |
10328 | as_bad_where (file, line, | |
10329 | _("operand value out of range for instruction")); | |
10330 | ||
b34976b6 | 10331 | *use_extend = TRUE; |
252b5132 RH |
10332 | if (op->extbits == 16) |
10333 | { | |
10334 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10335 | val &= 0x1f; | |
10336 | } | |
10337 | else if (op->extbits == 15) | |
10338 | { | |
10339 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10340 | val &= 0xf; | |
10341 | } | |
10342 | else | |
10343 | { | |
10344 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10345 | val = 0; | |
10346 | } | |
10347 | ||
10348 | *extend = (unsigned short) extval; | |
10349 | *insn |= val; | |
10350 | } | |
10351 | } | |
10352 | \f | |
5e0116d5 | 10353 | static const struct percent_op_match |
ad8d3bb3 | 10354 | { |
5e0116d5 RS |
10355 | const char *str; |
10356 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
10357 | } percent_op[] = |
10358 | { | |
5e0116d5 | 10359 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10360 | #ifdef OBJ_ELF |
5e0116d5 RS |
10361 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10362 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10363 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10364 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10365 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10366 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10367 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10368 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10369 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10370 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10371 | {"%half", BFD_RELOC_16}, | |
10372 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10373 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10374 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 10375 | #endif |
5e0116d5 | 10376 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10377 | }; |
10378 | ||
252b5132 | 10379 | |
5e0116d5 RS |
10380 | /* Return true if *STR points to a relocation operator. When returning true, |
10381 | move *STR over the operator and store its relocation code in *RELOC. | |
10382 | Leave both *STR and *RELOC alone when returning false. */ | |
10383 | ||
10384 | static bfd_boolean | |
10385 | parse_relocation (str, reloc) | |
ad8d3bb3 | 10386 | char **str; |
5e0116d5 | 10387 | bfd_reloc_code_real_type *reloc; |
252b5132 | 10388 | { |
5e0116d5 | 10389 | size_t i; |
76b3015f | 10390 | |
5e0116d5 RS |
10391 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10392 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10393 | { |
5e0116d5 RS |
10394 | *str += strlen (percent_op[i].str); |
10395 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10396 | |
5e0116d5 RS |
10397 | /* Check whether the output BFD supports this relocation. |
10398 | If not, issue an error and fall back on something safe. */ | |
10399 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10400 | { |
5e0116d5 RS |
10401 | as_bad ("relocation %s isn't supported by the current ABI", |
10402 | percent_op[i].str); | |
10403 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10404 | } |
5e0116d5 | 10405 | return TRUE; |
394f9b3a | 10406 | } |
5e0116d5 | 10407 | return FALSE; |
394f9b3a | 10408 | } |
ad8d3bb3 | 10409 | |
ad8d3bb3 | 10410 | |
5e0116d5 RS |
10411 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10412 | expression in *EP and the relocations in the array starting | |
10413 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10414 | |
5e0116d5 RS |
10415 | On exit, EXPR_END points to the first character after the expression. |
10416 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10417 | |
5e0116d5 RS |
10418 | static size_t |
10419 | my_getSmallExpression (ep, reloc, str) | |
ad8d3bb3 | 10420 | expressionS *ep; |
5e0116d5 | 10421 | bfd_reloc_code_real_type *reloc; |
ad8d3bb3 TS |
10422 | char *str; |
10423 | { | |
5e0116d5 RS |
10424 | bfd_reloc_code_real_type reversed_reloc[3]; |
10425 | size_t reloc_index, i; | |
09b8f35a RS |
10426 | int crux_depth, str_depth; |
10427 | char *crux; | |
5e0116d5 RS |
10428 | |
10429 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10430 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10431 | of the main expression and with CRUX_DEPTH containing the number | |
10432 | of open brackets at that point. */ | |
10433 | reloc_index = -1; | |
10434 | str_depth = 0; | |
10435 | do | |
fb1b3232 | 10436 | { |
09b8f35a RS |
10437 | reloc_index++; |
10438 | crux = str; | |
10439 | crux_depth = str_depth; | |
10440 | ||
10441 | /* Skip over whitespace and brackets, keeping count of the number | |
10442 | of brackets. */ | |
10443 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10444 | if (*str++ == '(') | |
10445 | str_depth++; | |
5e0116d5 | 10446 | } |
09b8f35a RS |
10447 | while (*str == '%' |
10448 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10449 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10450 | |
09b8f35a | 10451 | my_getExpression (ep, crux); |
5e0116d5 | 10452 | str = expr_end; |
394f9b3a | 10453 | |
5e0116d5 | 10454 | /* Match every open bracket. */ |
09b8f35a | 10455 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10456 | if (*str++ == ')') |
09b8f35a | 10457 | crux_depth--; |
394f9b3a | 10458 | |
09b8f35a | 10459 | if (crux_depth > 0) |
5e0116d5 | 10460 | as_bad ("unclosed '('"); |
394f9b3a | 10461 | |
5e0116d5 | 10462 | expr_end = str; |
252b5132 | 10463 | |
64bdfcaf RS |
10464 | if (reloc_index == 0) |
10465 | reloc[0] = BFD_RELOC_LO16; | |
10466 | else | |
10467 | { | |
10468 | prev_reloc_op_frag = frag_now; | |
10469 | for (i = 0; i < reloc_index; i++) | |
10470 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10471 | } | |
fb1b3232 | 10472 | |
5e0116d5 | 10473 | return reloc_index; |
252b5132 RH |
10474 | } |
10475 | ||
10476 | static void | |
10477 | my_getExpression (ep, str) | |
10478 | expressionS *ep; | |
10479 | char *str; | |
10480 | { | |
10481 | char *save_in; | |
98aa84af | 10482 | valueT val; |
252b5132 RH |
10483 | |
10484 | save_in = input_line_pointer; | |
10485 | input_line_pointer = str; | |
10486 | expression (ep); | |
10487 | expr_end = input_line_pointer; | |
10488 | input_line_pointer = save_in; | |
10489 | ||
10490 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10491 | then we bump the value of the symbol by 1 since that is how other | |
10492 | text symbols are handled. We don't bother to handle complex | |
10493 | expressions, just `.' plus or minus a constant. */ | |
10494 | if (mips_opts.mips16 | |
10495 | && ep->X_op == O_symbol | |
10496 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10497 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10498 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10499 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10500 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10501 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10502 | } |
10503 | ||
10504 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10505 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10506 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10507 | returned, or NULL on OK. */ |
10508 | ||
10509 | char * | |
10510 | md_atof (type, litP, sizeP) | |
10511 | int type; | |
10512 | char *litP; | |
10513 | int *sizeP; | |
10514 | { | |
10515 | int prec; | |
10516 | LITTLENUM_TYPE words[4]; | |
10517 | char *t; | |
10518 | int i; | |
10519 | ||
10520 | switch (type) | |
10521 | { | |
10522 | case 'f': | |
10523 | prec = 2; | |
10524 | break; | |
10525 | ||
10526 | case 'd': | |
10527 | prec = 4; | |
10528 | break; | |
10529 | ||
10530 | default: | |
10531 | *sizeP = 0; | |
10532 | return _("bad call to md_atof"); | |
10533 | } | |
10534 | ||
10535 | t = atof_ieee (input_line_pointer, type, words); | |
10536 | if (t) | |
10537 | input_line_pointer = t; | |
10538 | ||
10539 | *sizeP = prec * 2; | |
10540 | ||
10541 | if (! target_big_endian) | |
10542 | { | |
10543 | for (i = prec - 1; i >= 0; i--) | |
10544 | { | |
10545 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10546 | litP += 2; | |
10547 | } | |
10548 | } | |
10549 | else | |
10550 | { | |
10551 | for (i = 0; i < prec; i++) | |
10552 | { | |
10553 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10554 | litP += 2; | |
10555 | } | |
10556 | } | |
bdaaa2e1 | 10557 | |
252b5132 RH |
10558 | return NULL; |
10559 | } | |
10560 | ||
10561 | void | |
10562 | md_number_to_chars (buf, val, n) | |
10563 | char *buf; | |
10564 | valueT val; | |
10565 | int n; | |
10566 | { | |
10567 | if (target_big_endian) | |
10568 | number_to_chars_bigendian (buf, val, n); | |
10569 | else | |
10570 | number_to_chars_littleendian (buf, val, n); | |
10571 | } | |
10572 | \f | |
ae948b86 | 10573 | #ifdef OBJ_ELF |
e013f690 TS |
10574 | static int support_64bit_objects(void) |
10575 | { | |
10576 | const char **list, **l; | |
aa3d8fdf | 10577 | int yes; |
e013f690 TS |
10578 | |
10579 | list = bfd_target_list (); | |
10580 | for (l = list; *l != NULL; l++) | |
10581 | #ifdef TE_TMIPS | |
10582 | /* This is traditional mips */ | |
10583 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10584 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10585 | #else | |
10586 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10587 | || strcmp (*l, "elf64-littlemips") == 0) | |
10588 | #endif | |
10589 | break; | |
aa3d8fdf | 10590 | yes = (*l != NULL); |
e013f690 | 10591 | free (list); |
aa3d8fdf | 10592 | return yes; |
e013f690 | 10593 | } |
ae948b86 | 10594 | #endif /* OBJ_ELF */ |
e013f690 | 10595 | |
5a38dc70 | 10596 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10597 | |
e972090a NC |
10598 | struct option md_longopts[] = |
10599 | { | |
f9b4148d CD |
10600 | /* Options which specify architecture. */ |
10601 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10602 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10603 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10604 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10605 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10606 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10607 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10608 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10609 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10610 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10611 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10612 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10613 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10614 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10615 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10616 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10617 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10618 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10619 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10620 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10621 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10622 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
10623 | ||
10624 | /* Options which specify Application Specific Extensions (ASEs). */ | |
10625 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10) | |
10626 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) | |
10627 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10628 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10629 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10630 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10631 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10632 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10633 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10634 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10635 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10636 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10637 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10638 | ||
10639 | /* Old-style architecture options. Don't add more of these. */ | |
10640 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10641 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10642 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10643 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10644 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10645 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10646 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10647 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10648 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10649 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10650 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10651 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10652 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10653 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10654 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10655 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10656 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10657 | ||
10658 | /* Options which enable bug fixes. */ | |
10659 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10660 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10661 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10662 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10663 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10664 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10665 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10666 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10667 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10668 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10669 | ||
10670 | /* Miscellaneous options. */ | |
10671 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10672 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10673 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10674 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10675 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10676 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10677 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10678 | {"break", no_argument, NULL, OPTION_BREAK}, |
10679 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10680 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10681 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10682 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10683 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10684 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10685 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10686 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10687 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10688 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10689 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10690 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10691 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10692 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10693 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10694 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10695 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10696 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10697 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10698 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10699 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10700 | |
10701 | /* ELF-specific options. */ | |
156c2f8b | 10702 | #ifdef OBJ_ELF |
f9b4148d | 10703 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10704 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10705 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10706 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10707 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10708 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10709 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10710 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10711 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10712 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10713 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10714 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10715 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10716 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10717 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10718 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10719 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10720 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10721 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10722 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
ae948b86 | 10723 | #endif /* OBJ_ELF */ |
f9b4148d | 10724 | |
252b5132 RH |
10725 | {NULL, no_argument, NULL, 0} |
10726 | }; | |
156c2f8b | 10727 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10728 | |
316f5878 RS |
10729 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10730 | NEW_VALUE. Warn if another value was already specified. Note: | |
10731 | we have to defer parsing the -march and -mtune arguments in order | |
10732 | to handle 'from-abi' correctly, since the ABI might be specified | |
10733 | in a later argument. */ | |
10734 | ||
10735 | static void | |
10736 | mips_set_option_string (string_ptr, new_value) | |
10737 | const char **string_ptr, *new_value; | |
10738 | { | |
10739 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10740 | as_warn (_("A different %s was already specified, is now %s"), | |
10741 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10742 | new_value); | |
10743 | ||
10744 | *string_ptr = new_value; | |
10745 | } | |
10746 | ||
252b5132 RH |
10747 | int |
10748 | md_parse_option (c, arg) | |
10749 | int c; | |
10750 | char *arg; | |
10751 | { | |
10752 | switch (c) | |
10753 | { | |
119d663a NC |
10754 | case OPTION_CONSTRUCT_FLOATS: |
10755 | mips_disable_float_construction = 0; | |
10756 | break; | |
bdaaa2e1 | 10757 | |
119d663a NC |
10758 | case OPTION_NO_CONSTRUCT_FLOATS: |
10759 | mips_disable_float_construction = 1; | |
10760 | break; | |
bdaaa2e1 | 10761 | |
252b5132 RH |
10762 | case OPTION_TRAP: |
10763 | mips_trap = 1; | |
10764 | break; | |
10765 | ||
10766 | case OPTION_BREAK: | |
10767 | mips_trap = 0; | |
10768 | break; | |
10769 | ||
10770 | case OPTION_EB: | |
10771 | target_big_endian = 1; | |
10772 | break; | |
10773 | ||
10774 | case OPTION_EL: | |
10775 | target_big_endian = 0; | |
10776 | break; | |
10777 | ||
39c0a331 L |
10778 | case 'n': |
10779 | warn_nops = 1; | |
10780 | break; | |
10781 | ||
252b5132 RH |
10782 | case 'O': |
10783 | if (arg && arg[1] == '0') | |
10784 | mips_optimize = 1; | |
10785 | else | |
10786 | mips_optimize = 2; | |
10787 | break; | |
10788 | ||
10789 | case 'g': | |
10790 | if (arg == NULL) | |
10791 | mips_debug = 2; | |
10792 | else | |
10793 | mips_debug = atoi (arg); | |
10794 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10795 | optimizations which limit full symbolic debugging. We take | |
10796 | that to be equivalent to -O0. */ | |
10797 | if (mips_debug == 2) | |
10798 | mips_optimize = 1; | |
10799 | break; | |
10800 | ||
10801 | case OPTION_MIPS1: | |
316f5878 | 10802 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10803 | break; |
10804 | ||
10805 | case OPTION_MIPS2: | |
316f5878 | 10806 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10807 | break; |
10808 | ||
10809 | case OPTION_MIPS3: | |
316f5878 | 10810 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10811 | break; |
10812 | ||
10813 | case OPTION_MIPS4: | |
316f5878 | 10814 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10815 | break; |
10816 | ||
84ea6cf2 | 10817 | case OPTION_MIPS5: |
316f5878 | 10818 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10819 | break; |
10820 | ||
e7af610e | 10821 | case OPTION_MIPS32: |
316f5878 | 10822 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10823 | break; |
10824 | ||
af7ee8bf CD |
10825 | case OPTION_MIPS32R2: |
10826 | file_mips_isa = ISA_MIPS32R2; | |
10827 | break; | |
10828 | ||
84ea6cf2 | 10829 | case OPTION_MIPS64: |
316f5878 | 10830 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10831 | break; |
10832 | ||
ec68c924 | 10833 | case OPTION_MTUNE: |
316f5878 RS |
10834 | mips_set_option_string (&mips_tune_string, arg); |
10835 | break; | |
ec68c924 | 10836 | |
316f5878 RS |
10837 | case OPTION_MARCH: |
10838 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10839 | break; |
10840 | ||
10841 | case OPTION_M4650: | |
316f5878 RS |
10842 | mips_set_option_string (&mips_arch_string, "4650"); |
10843 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10844 | break; |
10845 | ||
10846 | case OPTION_NO_M4650: | |
10847 | break; | |
10848 | ||
10849 | case OPTION_M4010: | |
316f5878 RS |
10850 | mips_set_option_string (&mips_arch_string, "4010"); |
10851 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10852 | break; |
10853 | ||
10854 | case OPTION_NO_M4010: | |
10855 | break; | |
10856 | ||
10857 | case OPTION_M4100: | |
316f5878 RS |
10858 | mips_set_option_string (&mips_arch_string, "4100"); |
10859 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10860 | break; |
10861 | ||
10862 | case OPTION_NO_M4100: | |
10863 | break; | |
10864 | ||
252b5132 | 10865 | case OPTION_M3900: |
316f5878 RS |
10866 | mips_set_option_string (&mips_arch_string, "3900"); |
10867 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10868 | break; |
bdaaa2e1 | 10869 | |
252b5132 RH |
10870 | case OPTION_NO_M3900: |
10871 | break; | |
10872 | ||
deec1734 CD |
10873 | case OPTION_MDMX: |
10874 | mips_opts.ase_mdmx = 1; | |
10875 | break; | |
10876 | ||
10877 | case OPTION_NO_MDMX: | |
10878 | mips_opts.ase_mdmx = 0; | |
10879 | break; | |
10880 | ||
252b5132 RH |
10881 | case OPTION_MIPS16: |
10882 | mips_opts.mips16 = 1; | |
b34976b6 | 10883 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10884 | break; |
10885 | ||
10886 | case OPTION_NO_MIPS16: | |
10887 | mips_opts.mips16 = 0; | |
b34976b6 | 10888 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10889 | break; |
10890 | ||
1f25f5d3 CD |
10891 | case OPTION_MIPS3D: |
10892 | mips_opts.ase_mips3d = 1; | |
10893 | break; | |
10894 | ||
10895 | case OPTION_NO_MIPS3D: | |
10896 | mips_opts.ase_mips3d = 0; | |
10897 | break; | |
10898 | ||
252b5132 RH |
10899 | case OPTION_MEMBEDDED_PIC: |
10900 | mips_pic = EMBEDDED_PIC; | |
10901 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10902 | { | |
10903 | as_bad (_("-G may not be used with embedded PIC code")); | |
10904 | return 0; | |
10905 | } | |
10906 | g_switch_value = 0x7fffffff; | |
10907 | break; | |
10908 | ||
60b63b72 RS |
10909 | case OPTION_FIX_VR4122: |
10910 | mips_fix_4122_bugs = 1; | |
10911 | break; | |
10912 | ||
10913 | case OPTION_NO_FIX_VR4122: | |
10914 | mips_fix_4122_bugs = 0; | |
10915 | break; | |
10916 | ||
4a6a3df4 AO |
10917 | case OPTION_RELAX_BRANCH: |
10918 | mips_relax_branch = 1; | |
10919 | break; | |
10920 | ||
10921 | case OPTION_NO_RELAX_BRANCH: | |
10922 | mips_relax_branch = 0; | |
10923 | break; | |
10924 | ||
0f074f60 | 10925 | #ifdef OBJ_ELF |
252b5132 RH |
10926 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10927 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10928 | intended to be compatible with Irix 5. */ | |
10929 | case OPTION_CALL_SHARED: | |
10930 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10931 | { | |
10932 | as_bad (_("-call_shared is supported only for ELF format")); | |
10933 | return 0; | |
10934 | } | |
10935 | mips_pic = SVR4_PIC; | |
143d77c5 | 10936 | mips_abicalls = TRUE; |
252b5132 RH |
10937 | if (g_switch_seen && g_switch_value != 0) |
10938 | { | |
10939 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10940 | return 0; | |
10941 | } | |
10942 | g_switch_value = 0; | |
10943 | break; | |
10944 | ||
10945 | case OPTION_NON_SHARED: | |
10946 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10947 | { | |
10948 | as_bad (_("-non_shared is supported only for ELF format")); | |
10949 | return 0; | |
10950 | } | |
10951 | mips_pic = NO_PIC; | |
143d77c5 | 10952 | mips_abicalls = FALSE; |
252b5132 RH |
10953 | break; |
10954 | ||
10955 | /* The -xgot option tells the assembler to use 32 offsets when | |
10956 | accessing the got in SVR4_PIC mode. It is for Irix | |
10957 | compatibility. */ | |
10958 | case OPTION_XGOT: | |
10959 | mips_big_got = 1; | |
10960 | break; | |
0f074f60 | 10961 | #endif /* OBJ_ELF */ |
252b5132 RH |
10962 | |
10963 | case 'G': | |
10964 | if (! USE_GLOBAL_POINTER_OPT) | |
10965 | { | |
10966 | as_bad (_("-G is not supported for this configuration")); | |
10967 | return 0; | |
10968 | } | |
10969 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10970 | { | |
10971 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10972 | return 0; | |
10973 | } | |
10974 | else | |
10975 | g_switch_value = atoi (arg); | |
10976 | g_switch_seen = 1; | |
10977 | break; | |
10978 | ||
0f074f60 | 10979 | #ifdef OBJ_ELF |
34ba82a8 TS |
10980 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10981 | and -mabi=64. */ | |
252b5132 | 10982 | case OPTION_32: |
34ba82a8 TS |
10983 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10984 | { | |
10985 | as_bad (_("-32 is supported for ELF format only")); | |
10986 | return 0; | |
10987 | } | |
316f5878 | 10988 | mips_abi = O32_ABI; |
252b5132 RH |
10989 | break; |
10990 | ||
e013f690 | 10991 | case OPTION_N32: |
34ba82a8 TS |
10992 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10993 | { | |
10994 | as_bad (_("-n32 is supported for ELF format only")); | |
10995 | return 0; | |
10996 | } | |
316f5878 | 10997 | mips_abi = N32_ABI; |
e013f690 | 10998 | break; |
252b5132 | 10999 | |
e013f690 | 11000 | case OPTION_64: |
34ba82a8 TS |
11001 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11002 | { | |
11003 | as_bad (_("-64 is supported for ELF format only")); | |
11004 | return 0; | |
11005 | } | |
316f5878 | 11006 | mips_abi = N64_ABI; |
e013f690 TS |
11007 | if (! support_64bit_objects()) |
11008 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11009 | break; |
ae948b86 | 11010 | #endif /* OBJ_ELF */ |
252b5132 | 11011 | |
c97ef257 | 11012 | case OPTION_GP32: |
a325df1d | 11013 | file_mips_gp32 = 1; |
c97ef257 AH |
11014 | break; |
11015 | ||
11016 | case OPTION_GP64: | |
a325df1d | 11017 | file_mips_gp32 = 0; |
c97ef257 | 11018 | break; |
252b5132 | 11019 | |
ca4e0257 | 11020 | case OPTION_FP32: |
a325df1d | 11021 | file_mips_fp32 = 1; |
316f5878 RS |
11022 | break; |
11023 | ||
11024 | case OPTION_FP64: | |
11025 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11026 | break; |
11027 | ||
ae948b86 | 11028 | #ifdef OBJ_ELF |
252b5132 | 11029 | case OPTION_MABI: |
34ba82a8 TS |
11030 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11031 | { | |
11032 | as_bad (_("-mabi is supported for ELF format only")); | |
11033 | return 0; | |
11034 | } | |
e013f690 | 11035 | if (strcmp (arg, "32") == 0) |
316f5878 | 11036 | mips_abi = O32_ABI; |
e013f690 | 11037 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11038 | mips_abi = O64_ABI; |
e013f690 | 11039 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11040 | mips_abi = N32_ABI; |
e013f690 TS |
11041 | else if (strcmp (arg, "64") == 0) |
11042 | { | |
316f5878 | 11043 | mips_abi = N64_ABI; |
e013f690 TS |
11044 | if (! support_64bit_objects()) |
11045 | as_fatal (_("No compiled in support for 64 bit object file " | |
11046 | "format")); | |
11047 | } | |
11048 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11049 | mips_abi = EABI_ABI; |
e013f690 | 11050 | else |
da0e507f TS |
11051 | { |
11052 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11053 | return 0; | |
11054 | } | |
252b5132 | 11055 | break; |
e013f690 | 11056 | #endif /* OBJ_ELF */ |
252b5132 | 11057 | |
6b76fefe | 11058 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11059 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11060 | break; |
11061 | ||
9ee72ff1 | 11062 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11063 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11064 | break; |
11065 | ||
ecb4347a DJ |
11066 | #ifdef OBJ_ELF |
11067 | case OPTION_MDEBUG: | |
b34976b6 | 11068 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11069 | break; |
11070 | ||
11071 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11072 | mips_flag_mdebug = FALSE; |
ecb4347a DJ |
11073 | break; |
11074 | #endif /* OBJ_ELF */ | |
11075 | ||
252b5132 RH |
11076 | default: |
11077 | return 0; | |
11078 | } | |
11079 | ||
11080 | return 1; | |
11081 | } | |
316f5878 RS |
11082 | \f |
11083 | /* Set up globals to generate code for the ISA or processor | |
11084 | described by INFO. */ | |
252b5132 | 11085 | |
252b5132 | 11086 | static void |
316f5878 RS |
11087 | mips_set_architecture (info) |
11088 | const struct mips_cpu_info *info; | |
252b5132 | 11089 | { |
316f5878 | 11090 | if (info != 0) |
252b5132 | 11091 | { |
316f5878 RS |
11092 | mips_arch_info = info; |
11093 | mips_arch = info->cpu; | |
11094 | mips_opts.isa = info->isa; | |
252b5132 | 11095 | } |
252b5132 RH |
11096 | } |
11097 | ||
252b5132 | 11098 | |
316f5878 | 11099 | /* Likewise for tuning. */ |
252b5132 | 11100 | |
316f5878 RS |
11101 | static void |
11102 | mips_set_tune (info) | |
11103 | const struct mips_cpu_info *info; | |
11104 | { | |
11105 | if (info != 0) | |
11106 | { | |
11107 | mips_tune_info = info; | |
11108 | mips_tune = info->cpu; | |
11109 | } | |
11110 | } | |
80cc45a5 | 11111 | |
34ba82a8 | 11112 | |
252b5132 | 11113 | void |
e9670677 MR |
11114 | mips_after_parse_args () |
11115 | { | |
e9670677 MR |
11116 | /* GP relative stuff not working for PE */ |
11117 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
11118 | && g_switch_value != 0) | |
11119 | { | |
11120 | if (g_switch_seen) | |
11121 | as_bad (_("-G not supported in this configuration.")); | |
11122 | g_switch_value = 0; | |
11123 | } | |
11124 | ||
cac012d6 AO |
11125 | if (mips_abi == NO_ABI) |
11126 | mips_abi = MIPS_DEFAULT_ABI; | |
11127 | ||
22923709 RS |
11128 | /* The following code determines the architecture and register size. |
11129 | Similar code was added to GCC 3.3 (see override_options() in | |
11130 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11131 | as much as possible. */ | |
e9670677 | 11132 | |
316f5878 RS |
11133 | if (mips_arch_string != 0) |
11134 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); | |
e9670677 | 11135 | |
316f5878 RS |
11136 | if (mips_tune_string != 0) |
11137 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); | |
e9670677 | 11138 | |
316f5878 | 11139 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11140 | { |
316f5878 RS |
11141 | /* Handle -mipsN. At this point, file_mips_isa contains the |
11142 | ISA level specified by -mipsN, while mips_opts.isa contains | |
11143 | the -march selection (if any). */ | |
11144 | if (mips_arch_info != 0) | |
e9670677 | 11145 | { |
316f5878 RS |
11146 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11147 | There's no harm in specifying both as long as the ISA levels | |
11148 | are the same. */ | |
11149 | if (file_mips_isa != mips_opts.isa) | |
11150 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), | |
11151 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
11152 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11153 | } |
316f5878 RS |
11154 | else |
11155 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); | |
e9670677 MR |
11156 | } |
11157 | ||
316f5878 RS |
11158 | if (mips_arch_info == 0) |
11159 | mips_set_architecture (mips_parse_cpu ("default CPU", | |
11160 | MIPS_CPU_STRING_DEFAULT)); | |
e9670677 | 11161 | |
316f5878 RS |
11162 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
11163 | as_bad ("-march=%s is not compatible with the selected ABI", | |
11164 | mips_arch_info->name); | |
e9670677 | 11165 | |
316f5878 RS |
11166 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
11167 | if (mips_tune_info == 0) | |
11168 | mips_set_tune (mips_arch_info); | |
e9670677 | 11169 | |
316f5878 | 11170 | if (file_mips_gp32 >= 0) |
e9670677 | 11171 | { |
316f5878 RS |
11172 | /* The user specified the size of the integer registers. Make sure |
11173 | it agrees with the ABI and ISA. */ | |
11174 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11175 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11176 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11177 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11178 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11179 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11180 | } |
11181 | else | |
11182 | { | |
316f5878 RS |
11183 | /* Infer the integer register size from the ABI and processor. |
11184 | Restrict ourselves to 32-bit registers if that's all the | |
11185 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11186 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11187 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11188 | } |
11189 | ||
316f5878 RS |
11190 | /* ??? GAS treats single-float processors as though they had 64-bit |
11191 | float registers (although it complains when double-precision | |
11192 | instructions are used). As things stand, saying they have 32-bit | |
11193 | registers would lead to spurious "register must be even" messages. | |
11194 | So here we assume float registers are always the same size as | |
11195 | integer ones, unless the user says otherwise. */ | |
11196 | if (file_mips_fp32 < 0) | |
11197 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 11198 | |
316f5878 | 11199 | /* End of GCC-shared inference code. */ |
e9670677 | 11200 | |
316f5878 RS |
11201 | /* ??? When do we want this flag to be set? Who uses it? */ |
11202 | if (file_mips_gp32 == 1 | |
11203 | && mips_abi == NO_ABI | |
11204 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11205 | mips_32bitmode = 1; | |
e9670677 MR |
11206 | |
11207 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11208 | as_bad (_("trap exception not supported at ISA 1")); | |
11209 | ||
e9670677 MR |
11210 | /* If the selected architecture includes support for ASEs, enable |
11211 | generation of code for them. */ | |
a4672219 TS |
11212 | if (mips_opts.mips16 == -1) |
11213 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; | |
ffdefa66 | 11214 | if (mips_opts.ase_mips3d == -1) |
a4672219 | 11215 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
ffdefa66 | 11216 | if (mips_opts.ase_mdmx == -1) |
a4672219 | 11217 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
e9670677 | 11218 | |
e9670677 | 11219 | file_mips_isa = mips_opts.isa; |
a4672219 | 11220 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11221 | file_ase_mips3d = mips_opts.ase_mips3d; |
11222 | file_ase_mdmx = mips_opts.ase_mdmx; | |
11223 | mips_opts.gp32 = file_mips_gp32; | |
11224 | mips_opts.fp32 = file_mips_fp32; | |
11225 | ||
ecb4347a DJ |
11226 | if (mips_flag_mdebug < 0) |
11227 | { | |
11228 | #ifdef OBJ_MAYBE_ECOFF | |
11229 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11230 | mips_flag_mdebug = 1; | |
11231 | else | |
11232 | #endif /* OBJ_MAYBE_ECOFF */ | |
11233 | mips_flag_mdebug = 0; | |
11234 | } | |
e9670677 MR |
11235 | } |
11236 | \f | |
11237 | void | |
252b5132 RH |
11238 | mips_init_after_args () |
11239 | { | |
11240 | /* initialize opcodes */ | |
11241 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11242 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11243 | } |
11244 | ||
11245 | long | |
11246 | md_pcrel_from (fixP) | |
11247 | fixS *fixP; | |
11248 | { | |
a7ebbfdf TS |
11249 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11250 | switch (fixP->fx_r_type) | |
11251 | { | |
11252 | case BFD_RELOC_16_PCREL_S2: | |
11253 | case BFD_RELOC_MIPS_JMP: | |
11254 | /* Return the address of the delay slot. */ | |
11255 | return addr + 4; | |
11256 | default: | |
11257 | return addr; | |
11258 | } | |
252b5132 RH |
11259 | } |
11260 | ||
252b5132 RH |
11261 | /* This is called before the symbol table is processed. In order to |
11262 | work with gcc when using mips-tfile, we must keep all local labels. | |
11263 | However, in other cases, we want to discard them. If we were | |
11264 | called with -g, but we didn't see any debugging information, it may | |
11265 | mean that gcc is smuggling debugging information through to | |
11266 | mips-tfile, in which case we must generate all local labels. */ | |
11267 | ||
11268 | void | |
11269 | mips_frob_file_before_adjust () | |
11270 | { | |
11271 | #ifndef NO_ECOFF_DEBUGGING | |
11272 | if (ECOFF_DEBUGGING | |
11273 | && mips_debug != 0 | |
11274 | && ! ecoff_debugging_seen) | |
11275 | flag_keep_locals = 1; | |
11276 | #endif | |
11277 | } | |
11278 | ||
11279 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 11280 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
11281 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
11282 | explicit use of the %hi modifier. */ | |
11283 | ||
11284 | void | |
11285 | mips_frob_file () | |
11286 | { | |
11287 | struct mips_hi_fixup *l; | |
11288 | ||
11289 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11290 | { | |
11291 | segment_info_type *seginfo; | |
11292 | int pass; | |
11293 | ||
5919d012 | 11294 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11295 | |
5919d012 RS |
11296 | /* If a GOT16 relocation turns out to be against a global symbol, |
11297 | there isn't supposed to be a matching LO. */ | |
11298 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11299 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11300 | continue; | |
11301 | ||
11302 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11303 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11304 | continue; |
11305 | ||
11306 | /* Look through the fixups for this segment for a matching %lo. | |
11307 | When we find one, move the %hi just in front of it. We do | |
11308 | this in two passes. In the first pass, we try to find a | |
11309 | unique %lo. In the second pass, we permit multiple %hi | |
11310 | relocs for a single %lo (this is a GNU extension). */ | |
11311 | seginfo = seg_info (l->seg); | |
11312 | for (pass = 0; pass < 2; pass++) | |
11313 | { | |
11314 | fixS *f, *prev; | |
11315 | ||
11316 | prev = NULL; | |
11317 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
11318 | { | |
11319 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
11320 | if (f->fx_r_type == BFD_RELOC_LO16 | |
11321 | && f->fx_addsy == l->fixp->fx_addsy | |
11322 | && f->fx_offset == l->fixp->fx_offset | |
11323 | && (pass == 1 | |
11324 | || prev == NULL | |
5919d012 RS |
11325 | || !reloc_needs_lo_p (prev->fx_r_type) |
11326 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
11327 | { |
11328 | fixS **pf; | |
11329 | ||
11330 | /* Move l->fixp before f. */ | |
11331 | for (pf = &seginfo->fix_root; | |
11332 | *pf != l->fixp; | |
11333 | pf = &(*pf)->fx_next) | |
11334 | assert (*pf != NULL); | |
11335 | ||
11336 | *pf = l->fixp->fx_next; | |
11337 | ||
11338 | l->fixp->fx_next = f; | |
11339 | if (prev == NULL) | |
11340 | seginfo->fix_root = l->fixp; | |
11341 | else | |
11342 | prev->fx_next = l->fixp; | |
11343 | ||
11344 | break; | |
11345 | } | |
11346 | ||
11347 | prev = f; | |
11348 | } | |
11349 | ||
11350 | if (f != NULL) | |
11351 | break; | |
11352 | ||
11353 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
11354 | can leave a %hi without a %lo. */ | |
11355 | if (pass == 1) | |
11356 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
11357 | _("Unmatched %%hi reloc")); | |
11358 | #endif | |
11359 | } | |
11360 | } | |
11361 | } | |
11362 | ||
11363 | /* When generating embedded PIC code we need to use a special | |
11364 | relocation to represent the difference of two symbols in the .text | |
11365 | section (switch tables use a difference of this sort). See | |
11366 | include/coff/mips.h for details. This macro checks whether this | |
11367 | fixup requires the special reloc. */ | |
11368 | #define SWITCH_TABLE(fixp) \ | |
11369 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 11370 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
11371 | && (fixp)->fx_addsy != NULL \ |
11372 | && (fixp)->fx_subsy != NULL \ | |
11373 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
11374 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11375 | ||
11376 | /* When generating embedded PIC code we must keep all PC relative | |
11377 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11378 | to keep relocations for switch table entries. |
11379 | ||
11380 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11381 | We have to prevent gas from dropping them. */ | |
252b5132 | 11382 | |
252b5132 RH |
11383 | int |
11384 | mips_force_relocation (fixp) | |
11385 | fixS *fixp; | |
11386 | { | |
ae6063d4 | 11387 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11388 | return 1; |
11389 | ||
f6688943 TS |
11390 | if (HAVE_NEWABI |
11391 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11392 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11393 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11394 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11395 | return 1; | |
11396 | ||
252b5132 RH |
11397 | return (mips_pic == EMBEDDED_PIC |
11398 | && (fixp->fx_pcrel | |
11399 | || SWITCH_TABLE (fixp) | |
11400 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11401 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11402 | } | |
11403 | ||
45f8dfe8 AO |
11404 | /* This hook is called before a fix is simplified. We don't really |
11405 | decide whether to skip a fix here. Rather, we turn global symbols | |
11406 | used as branch targets into local symbols, such that they undergo | |
11407 | simplification. We can only do this if the symbol is defined and | |
11408 | it is in the same section as the branch. If this doesn't hold, we | |
11409 | emit a better error message than just saying the relocation is not | |
11410 | valid for the selected object format. | |
11411 | ||
11412 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11413 | segment in which the fix up occurs. The return value should be | |
11414 | non-zero to indicate the fix-up is valid for further | |
11415 | simplifications. */ | |
11416 | ||
11417 | int | |
11418 | mips_validate_fix (fixP, seg) | |
11419 | struct fix *fixP; | |
11420 | asection *seg; | |
11421 | { | |
11422 | /* There's a lot of discussion on whether it should be possible to | |
11423 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11424 | seems to be that it can, but gas/bfd are very broken in creating | |
11425 | RELA relocations for this, so for now we only accept branches to | |
11426 | symbols in the same section. Anything else is of dubious value, | |
11427 | since there's no guarantee that at link time the symbol would be | |
11428 | in range. Even for branches to local symbols this is arguably | |
11429 | wrong, since it we assume the symbol is not going to be | |
11430 | overridden, which should be possible per ELF library semantics, | |
11431 | but then, there isn't a dynamic relocation that could be used to | |
11432 | this effect, and the target would likely be out of range as well. | |
11433 | ||
11434 | Unfortunately, it seems that there is too much code out there | |
11435 | that relies on branches to symbols that are global to be resolved | |
11436 | as if they were local, like the IRIX tools do, so we do it as | |
11437 | well, but with a warning so that people are reminded to fix their | |
11438 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11439 | targets, this entire block should go away (and probably the | |
11440 | whole function). */ | |
11441 | ||
11442 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11443 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11444 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11445 | && mips_pic != EMBEDDED_PIC) | |
11446 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11447 | && fixP->fx_addsy) | |
11448 | { | |
11449 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11450 | { | |
11451 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11452 | _("Cannot branch to undefined symbol.")); | |
11453 | /* Avoid any further errors about this fixup. */ | |
11454 | fixP->fx_done = 1; | |
11455 | } | |
11456 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11457 | { | |
11458 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11459 | _("Cannot branch to symbol in another section.")); | |
11460 | fixP->fx_done = 1; | |
11461 | } | |
11462 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11463 | { | |
11464 | symbolS *sym = fixP->fx_addsy; | |
11465 | ||
11466 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11467 | _("Pretending global symbol used as branch target is local.")); | |
11468 | ||
11469 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11470 | S_GET_SEGMENT (sym), | |
11471 | S_GET_VALUE (sym), | |
11472 | symbol_get_frag (sym)); | |
11473 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11474 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11475 | assert (symbol_resolved_p (sym)); | |
11476 | symbol_mark_resolved (fixP->fx_addsy); | |
11477 | } | |
11478 | } | |
11479 | ||
11480 | return 1; | |
11481 | } | |
11482 | ||
add55e1f RS |
11483 | #ifdef OBJ_ELF |
11484 | static int | |
11485 | mips_need_elf_addend_fixup (fixP) | |
11486 | fixS *fixP; | |
11487 | { | |
2d2bf3e0 CD |
11488 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11489 | return 1; | |
b25a253c CD |
11490 | if (mips_pic == EMBEDDED_PIC |
11491 | && S_IS_WEAK (fixP->fx_addsy)) | |
11492 | return 1; | |
11493 | if (mips_pic != EMBEDDED_PIC | |
11494 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11495 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11496 | && !S_IS_COMMON (fixP->fx_addsy)) |
11497 | return 1; | |
9204e615 DJ |
11498 | if (((bfd_get_section_flags (stdoutput, |
11499 | S_GET_SEGMENT (fixP->fx_addsy)) | |
11500 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) | |
11501 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
11502 | ".gnu.linkonce", | |
11503 | sizeof (".gnu.linkonce") - 1)) | |
2d2bf3e0 CD |
11504 | return 1; |
11505 | return 0; | |
add55e1f RS |
11506 | } |
11507 | #endif | |
11508 | ||
252b5132 RH |
11509 | /* Apply a fixup to the object file. */ |
11510 | ||
94f592af NC |
11511 | void |
11512 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 11513 | fixS *fixP; |
98d3f06f | 11514 | valueT *valP; |
94f592af | 11515 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 11516 | { |
874e8986 | 11517 | bfd_byte *buf; |
98aa84af | 11518 | long insn; |
ed6fb7bd | 11519 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11520 | reloc_howto_type *howto; |
252b5132 | 11521 | |
a7ebbfdf TS |
11522 | /* We ignore generic BFD relocations we don't know about. */ |
11523 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11524 | if (! howto) | |
11525 | return; | |
65551fa4 | 11526 | |
252b5132 RH |
11527 | assert (fixP->fx_size == 4 |
11528 | || fixP->fx_r_type == BFD_RELOC_16 | |
11529 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11530 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11531 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11532 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11533 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11534 | |
a7ebbfdf | 11535 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 RH |
11536 | |
11537 | /* If we aren't adjusting this fixup to be against the section | |
11538 | symbol, we need to adjust the value. */ | |
11539 | #ifdef OBJ_ELF | |
11540 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11541 | { |
a7ebbfdf TS |
11542 | if (mips_need_elf_addend_fixup (fixP) |
11543 | && howto->partial_inplace | |
11544 | && fixP->fx_r_type != BFD_RELOC_GPREL16 | |
11545 | && fixP->fx_r_type != BFD_RELOC_GPREL32 | |
11546 | && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL) | |
11547 | { | |
11548 | /* In this case, the bfd_install_relocation routine will | |
11549 | incorrectly add the symbol value back in. We just want | |
11550 | the addend to appear in the object file. | |
11551 | ||
11552 | The condition above used to include | |
11553 | "&& (! fixP->fx_pcrel || howto->pcrel_offset)". | |
11554 | ||
11555 | However, howto can't be trusted here, because we | |
11556 | might change the reloc type in tc_gen_reloc. We can | |
11557 | check howto->partial_inplace because that conversion | |
11558 | happens to preserve howto->partial_inplace; but it | |
11559 | does not preserve howto->pcrel_offset. I've just | |
11560 | eliminated the check, because all MIPS PC-relative | |
11561 | relocations are marked howto->pcrel_offset. | |
11562 | ||
11563 | howto->pcrel_offset was originally added for | |
11564 | R_MIPS_PC16, which is generated for code like | |
11565 | ||
11566 | globl g1 .text | |
11567 | .text | |
11568 | .space 20 | |
11569 | g1: | |
11570 | x: | |
11571 | bal g1 | |
11572 | */ | |
11573 | *valP -= S_GET_VALUE (fixP->fx_addsy); | |
98aa84af | 11574 | } |
252b5132 | 11575 | |
bb2d6cd7 GK |
11576 | /* This code was generated using trial and error and so is |
11577 | fragile and not trustworthy. If you change it, you should | |
11578 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11579 | they still pass. */ | |
a7ebbfdf | 11580 | if (fixP->fx_pcrel) |
bb2d6cd7 | 11581 | { |
a7ebbfdf | 11582 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11583 | |
11584 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11585 | This gives the right results, but it can't possibly | |
11586 | be the way things are supposed to work. */ | |
a7ebbfdf | 11587 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11588 | } |
11589 | } | |
11590 | #endif | |
252b5132 | 11591 | |
ed6fb7bd SC |
11592 | /* We are not done if this is a composite relocation to set up gp. */ |
11593 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11594 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11595 | || (fixP->fx_r_type == BFD_RELOC_64 |
11596 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11597 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11598 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11599 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11600 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11601 | fixP->fx_done = 1; |
ed6fb7bd | 11602 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11603 | |
11604 | switch (fixP->fx_r_type) | |
11605 | { | |
11606 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11607 | case BFD_RELOC_MIPS_SHIFT5: |
11608 | case BFD_RELOC_MIPS_SHIFT6: | |
11609 | case BFD_RELOC_MIPS_GOT_DISP: | |
11610 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11611 | case BFD_RELOC_MIPS_GOT_OFST: | |
11612 | case BFD_RELOC_MIPS_SUB: | |
11613 | case BFD_RELOC_MIPS_INSERT_A: | |
11614 | case BFD_RELOC_MIPS_INSERT_B: | |
11615 | case BFD_RELOC_MIPS_DELETE: | |
11616 | case BFD_RELOC_MIPS_HIGHEST: | |
11617 | case BFD_RELOC_MIPS_HIGHER: | |
11618 | case BFD_RELOC_MIPS_SCN_DISP: | |
11619 | case BFD_RELOC_MIPS_REL16: | |
11620 | case BFD_RELOC_MIPS_RELGOT: | |
11621 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11622 | case BFD_RELOC_HI16: |
11623 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11624 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11625 | case BFD_RELOC_MIPS_LITERAL: |
11626 | case BFD_RELOC_MIPS_CALL16: | |
11627 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11628 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11629 | case BFD_RELOC_MIPS_GOT_HI16: |
11630 | case BFD_RELOC_MIPS_GOT_LO16: | |
11631 | case BFD_RELOC_MIPS_CALL_HI16: | |
11632 | case BFD_RELOC_MIPS_CALL_LO16: | |
11633 | case BFD_RELOC_MIPS16_GPREL: | |
11634 | if (fixP->fx_pcrel) | |
11635 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11636 | _("Invalid PC relative reloc")); | |
11637 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11638 | break; | |
11639 | ||
11640 | case BFD_RELOC_MIPS16_JMP: | |
11641 | /* We currently always generate a reloc against a symbol, which | |
11642 | means that we don't want an addend even if the symbol is | |
11643 | defined. */ | |
a7ebbfdf | 11644 | *valP = 0; |
252b5132 RH |
11645 | break; |
11646 | ||
11647 | case BFD_RELOC_PCREL_HI16_S: | |
11648 | /* The addend for this is tricky if it is internal, so we just | |
11649 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11650 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11651 | break; |
11652 | if (fixP->fx_addsy | |
11653 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11654 | { |
11655 | /* For an external symbol adjust by the address to make it | |
11656 | pcrel_offset. We use the address of the RELLO reloc | |
11657 | which follows this one. */ | |
a7ebbfdf | 11658 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11659 | + fixP->fx_next->fx_where); |
11660 | } | |
a7ebbfdf | 11661 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11662 | if (target_big_endian) |
11663 | buf += 2; | |
a7ebbfdf | 11664 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11665 | break; |
11666 | ||
11667 | case BFD_RELOC_PCREL_LO16: | |
11668 | /* The addend for this is tricky if it is internal, so we just | |
11669 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11670 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11671 | break; |
11672 | if (fixP->fx_addsy | |
11673 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11674 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11675 | if (target_big_endian) |
11676 | buf += 2; | |
a7ebbfdf | 11677 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11678 | break; |
11679 | ||
11680 | case BFD_RELOC_64: | |
11681 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11682 | extended value if we are only 32 bits. */ | |
11683 | if (fixP->fx_done | |
11684 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11685 | { | |
11686 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11687 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11688 | else |
11689 | { | |
a7ebbfdf | 11690 | valueT hiv; |
252b5132 | 11691 | |
a7ebbfdf | 11692 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11693 | hiv = 0xffffffff; |
11694 | else | |
11695 | hiv = 0; | |
a7ebbfdf TS |
11696 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11697 | *valP, 4); | |
11698 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11699 | hiv, 4); | |
252b5132 RH |
11700 | } |
11701 | } | |
11702 | break; | |
11703 | ||
056350c6 | 11704 | case BFD_RELOC_RVA: |
252b5132 RH |
11705 | case BFD_RELOC_32: |
11706 | /* If we are deleting this reloc entry, we must fill in the | |
11707 | value now. This can happen if we have a .word which is not | |
11708 | resolved when it appears but is later defined. We also need | |
11709 | to fill in the value if this is an embedded PIC switch table | |
11710 | entry. */ | |
11711 | if (fixP->fx_done | |
11712 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11713 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11714 | break; |
11715 | ||
11716 | case BFD_RELOC_16: | |
11717 | /* If we are deleting this reloc entry, we must fill in the | |
11718 | value now. */ | |
11719 | assert (fixP->fx_size == 2); | |
11720 | if (fixP->fx_done) | |
a7ebbfdf | 11721 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11722 | break; |
11723 | ||
11724 | case BFD_RELOC_LO16: | |
11725 | /* When handling an embedded PIC switch statement, we can wind | |
11726 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11727 | if (fixP->fx_done) | |
11728 | { | |
a7ebbfdf | 11729 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11730 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11731 | _("relocation overflow")); | |
252b5132 RH |
11732 | if (target_big_endian) |
11733 | buf += 2; | |
a7ebbfdf | 11734 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11735 | } |
11736 | break; | |
11737 | ||
11738 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11739 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11740 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11741 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11742 | |
252b5132 RH |
11743 | /* |
11744 | * We need to save the bits in the instruction since fixup_segment() | |
11745 | * might be deleting the relocation entry (i.e., a branch within | |
11746 | * the current segment). | |
11747 | */ | |
a7ebbfdf | 11748 | if (! fixP->fx_done) |
bb2d6cd7 | 11749 | break; |
252b5132 RH |
11750 | |
11751 | /* update old instruction data */ | |
252b5132 RH |
11752 | if (target_big_endian) |
11753 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11754 | else | |
11755 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11756 | ||
a7ebbfdf TS |
11757 | if (*valP + 0x20000 <= 0x3ffff) |
11758 | { | |
11759 | insn |= (*valP >> 2) & 0xffff; | |
11760 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11761 | } | |
11762 | else if (mips_pic == NO_PIC | |
11763 | && fixP->fx_done | |
11764 | && fixP->fx_frag->fr_address >= text_section->vma | |
11765 | && (fixP->fx_frag->fr_address | |
11766 | < text_section->vma + text_section->_raw_size) | |
11767 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11768 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11769 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11770 | { |
11771 | /* The branch offset is too large. If this is an | |
11772 | unconditional branch, and we are not generating PIC code, | |
11773 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11774 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11775 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11776 | else |
a7ebbfdf TS |
11777 | insn = 0x08000000; /* j */ |
11778 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11779 | fixP->fx_done = 0; | |
11780 | fixP->fx_addsy = section_symbol (text_section); | |
11781 | *valP += md_pcrel_from (fixP); | |
11782 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11783 | } | |
11784 | else | |
11785 | { | |
11786 | /* If we got here, we have branch-relaxation disabled, | |
11787 | and there's nothing we can do to fix this instruction | |
11788 | without turning it into a longer sequence. */ | |
11789 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11790 | _("Branch out of range")); | |
252b5132 | 11791 | } |
252b5132 RH |
11792 | break; |
11793 | ||
11794 | case BFD_RELOC_VTABLE_INHERIT: | |
11795 | fixP->fx_done = 0; | |
11796 | if (fixP->fx_addsy | |
11797 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11798 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11799 | S_SET_WEAK (fixP->fx_addsy); | |
11800 | break; | |
11801 | ||
11802 | case BFD_RELOC_VTABLE_ENTRY: | |
11803 | fixP->fx_done = 0; | |
11804 | break; | |
11805 | ||
11806 | default: | |
11807 | internalError (); | |
11808 | } | |
a7ebbfdf TS |
11809 | |
11810 | /* Remember value for tc_gen_reloc. */ | |
11811 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11812 | } |
11813 | ||
11814 | #if 0 | |
11815 | void | |
11816 | printInsn (oc) | |
11817 | unsigned long oc; | |
11818 | { | |
11819 | const struct mips_opcode *p; | |
11820 | int treg, sreg, dreg, shamt; | |
11821 | short imm; | |
11822 | const char *args; | |
11823 | int i; | |
11824 | ||
11825 | for (i = 0; i < NUMOPCODES; ++i) | |
11826 | { | |
11827 | p = &mips_opcodes[i]; | |
11828 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11829 | { | |
11830 | printf ("%08lx %s\t", oc, p->name); | |
11831 | treg = (oc >> 16) & 0x1f; | |
11832 | sreg = (oc >> 21) & 0x1f; | |
11833 | dreg = (oc >> 11) & 0x1f; | |
11834 | shamt = (oc >> 6) & 0x1f; | |
11835 | imm = oc; | |
11836 | for (args = p->args;; ++args) | |
11837 | { | |
11838 | switch (*args) | |
11839 | { | |
11840 | case '\0': | |
11841 | printf ("\n"); | |
11842 | break; | |
11843 | ||
11844 | case ',': | |
11845 | case '(': | |
11846 | case ')': | |
11847 | printf ("%c", *args); | |
11848 | continue; | |
11849 | ||
11850 | case 'r': | |
11851 | assert (treg == sreg); | |
11852 | printf ("$%d,$%d", treg, sreg); | |
11853 | continue; | |
11854 | ||
11855 | case 'd': | |
11856 | case 'G': | |
11857 | printf ("$%d", dreg); | |
11858 | continue; | |
11859 | ||
11860 | case 't': | |
11861 | case 'E': | |
11862 | printf ("$%d", treg); | |
11863 | continue; | |
11864 | ||
11865 | case 'k': | |
11866 | printf ("0x%x", treg); | |
11867 | continue; | |
11868 | ||
11869 | case 'b': | |
11870 | case 's': | |
11871 | printf ("$%d", sreg); | |
11872 | continue; | |
11873 | ||
11874 | case 'a': | |
11875 | printf ("0x%08lx", oc & 0x1ffffff); | |
11876 | continue; | |
11877 | ||
11878 | case 'i': | |
11879 | case 'j': | |
11880 | case 'o': | |
11881 | case 'u': | |
11882 | printf ("%d", imm); | |
11883 | continue; | |
11884 | ||
11885 | case '<': | |
11886 | case '>': | |
11887 | printf ("$%d", shamt); | |
11888 | continue; | |
11889 | ||
11890 | default: | |
11891 | internalError (); | |
11892 | } | |
11893 | break; | |
11894 | } | |
11895 | return; | |
11896 | } | |
11897 | } | |
11898 | printf (_("%08lx UNDEFINED\n"), oc); | |
11899 | } | |
11900 | #endif | |
11901 | ||
11902 | static symbolS * | |
11903 | get_symbol () | |
11904 | { | |
11905 | int c; | |
11906 | char *name; | |
11907 | symbolS *p; | |
11908 | ||
11909 | name = input_line_pointer; | |
11910 | c = get_symbol_end (); | |
11911 | p = (symbolS *) symbol_find_or_make (name); | |
11912 | *input_line_pointer = c; | |
11913 | return p; | |
11914 | } | |
11915 | ||
11916 | /* Align the current frag to a given power of two. The MIPS assembler | |
11917 | also automatically adjusts any preceding label. */ | |
11918 | ||
11919 | static void | |
11920 | mips_align (to, fill, label) | |
11921 | int to; | |
11922 | int fill; | |
11923 | symbolS *label; | |
11924 | { | |
b34976b6 | 11925 | mips_emit_delays (FALSE); |
252b5132 RH |
11926 | frag_align (to, fill, 0); |
11927 | record_alignment (now_seg, to); | |
11928 | if (label != NULL) | |
11929 | { | |
11930 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11931 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11932 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11933 | } | |
11934 | } | |
11935 | ||
11936 | /* Align to a given power of two. .align 0 turns off the automatic | |
11937 | alignment used by the data creating pseudo-ops. */ | |
11938 | ||
11939 | static void | |
11940 | s_align (x) | |
43841e91 | 11941 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11942 | { |
11943 | register int temp; | |
11944 | register long temp_fill; | |
11945 | long max_alignment = 15; | |
11946 | ||
11947 | /* | |
11948 | ||
11949 | o Note that the assembler pulls down any immediately preceeding label | |
11950 | to the aligned address. | |
11951 | o It's not documented but auto alignment is reinstated by | |
11952 | a .align pseudo instruction. | |
11953 | o Note also that after auto alignment is turned off the mips assembler | |
11954 | issues an error on attempt to assemble an improperly aligned data item. | |
11955 | We don't. | |
11956 | ||
11957 | */ | |
11958 | ||
11959 | temp = get_absolute_expression (); | |
11960 | if (temp > max_alignment) | |
11961 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11962 | else if (temp < 0) | |
11963 | { | |
11964 | as_warn (_("Alignment negative: 0 assumed.")); | |
11965 | temp = 0; | |
11966 | } | |
11967 | if (*input_line_pointer == ',') | |
11968 | { | |
f9419b05 | 11969 | ++input_line_pointer; |
252b5132 RH |
11970 | temp_fill = get_absolute_expression (); |
11971 | } | |
11972 | else | |
11973 | temp_fill = 0; | |
11974 | if (temp) | |
11975 | { | |
11976 | auto_align = 1; | |
11977 | mips_align (temp, (int) temp_fill, | |
11978 | insn_labels != NULL ? insn_labels->label : NULL); | |
11979 | } | |
11980 | else | |
11981 | { | |
11982 | auto_align = 0; | |
11983 | } | |
11984 | ||
11985 | demand_empty_rest_of_line (); | |
11986 | } | |
11987 | ||
11988 | void | |
11989 | mips_flush_pending_output () | |
11990 | { | |
b34976b6 | 11991 | mips_emit_delays (FALSE); |
252b5132 RH |
11992 | mips_clear_insn_labels (); |
11993 | } | |
11994 | ||
11995 | static void | |
11996 | s_change_sec (sec) | |
11997 | int sec; | |
11998 | { | |
11999 | segT seg; | |
12000 | ||
12001 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
12002 | .sdata and .sbss sections. We change the .data and .rdata | |
12003 | pseudo-ops to use .sdata. */ | |
12004 | if (mips_pic == EMBEDDED_PIC | |
12005 | && (sec == 'd' || sec == 'r')) | |
12006 | sec = 's'; | |
12007 | ||
12008 | #ifdef OBJ_ELF | |
12009 | /* The ELF backend needs to know that we are changing sections, so | |
12010 | that .previous works correctly. We could do something like check | |
b6ff326e | 12011 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12012 | as it would not be appropriate to use it in the section changing |
12013 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12014 | This should be cleaner, somehow. */ | |
12015 | obj_elf_section_change_hook (); | |
12016 | #endif | |
12017 | ||
b34976b6 | 12018 | mips_emit_delays (FALSE); |
252b5132 RH |
12019 | switch (sec) |
12020 | { | |
12021 | case 't': | |
12022 | s_text (0); | |
12023 | break; | |
12024 | case 'd': | |
12025 | s_data (0); | |
12026 | break; | |
12027 | case 'b': | |
12028 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12029 | demand_empty_rest_of_line (); | |
12030 | break; | |
12031 | ||
12032 | case 'r': | |
12033 | if (USE_GLOBAL_POINTER_OPT) | |
12034 | { | |
12035 | seg = subseg_new (RDATA_SECTION_NAME, | |
12036 | (subsegT) get_absolute_expression ()); | |
12037 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
12038 | { | |
12039 | bfd_set_section_flags (stdoutput, seg, | |
12040 | (SEC_ALLOC | |
12041 | | SEC_LOAD | |
12042 | | SEC_READONLY | |
12043 | | SEC_RELOC | |
12044 | | SEC_DATA)); | |
12045 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 12046 | record_alignment (seg, 4); |
252b5132 RH |
12047 | } |
12048 | demand_empty_rest_of_line (); | |
12049 | } | |
12050 | else | |
12051 | { | |
12052 | as_bad (_("No read only data section in this object file format")); | |
12053 | demand_empty_rest_of_line (); | |
12054 | return; | |
12055 | } | |
12056 | break; | |
12057 | ||
12058 | case 's': | |
12059 | if (USE_GLOBAL_POINTER_OPT) | |
12060 | { | |
12061 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
12062 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
12063 | { | |
12064 | bfd_set_section_flags (stdoutput, seg, | |
12065 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
12066 | | SEC_DATA); | |
12067 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 12068 | record_alignment (seg, 4); |
252b5132 RH |
12069 | } |
12070 | demand_empty_rest_of_line (); | |
12071 | break; | |
12072 | } | |
12073 | else | |
12074 | { | |
12075 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
12076 | demand_empty_rest_of_line (); | |
12077 | return; | |
12078 | } | |
12079 | } | |
12080 | ||
12081 | auto_align = 1; | |
12082 | } | |
b34976b6 | 12083 | |
cca86cc8 SC |
12084 | void |
12085 | s_change_section (ignore) | |
12086 | int ignore ATTRIBUTE_UNUSED; | |
12087 | { | |
7ed4a06a | 12088 | #ifdef OBJ_ELF |
cca86cc8 SC |
12089 | char *section_name; |
12090 | char c; | |
684022ea | 12091 | char next_c = 0; |
cca86cc8 SC |
12092 | int section_type; |
12093 | int section_flag; | |
12094 | int section_entry_size; | |
12095 | int section_alignment; | |
b34976b6 | 12096 | |
7ed4a06a TS |
12097 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
12098 | return; | |
12099 | ||
cca86cc8 SC |
12100 | section_name = input_line_pointer; |
12101 | c = get_symbol_end (); | |
a816d1ed AO |
12102 | if (c) |
12103 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12104 | |
4cf0dd0d TS |
12105 | /* Do we have .section Name<,"flags">? */ |
12106 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12107 | { |
4cf0dd0d TS |
12108 | /* just after name is now '\0'. */ |
12109 | *input_line_pointer = c; | |
cca86cc8 SC |
12110 | input_line_pointer = section_name; |
12111 | obj_elf_section (ignore); | |
12112 | return; | |
12113 | } | |
12114 | input_line_pointer++; | |
12115 | ||
12116 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12117 | if (c == ',') | |
12118 | section_type = get_absolute_expression (); | |
12119 | else | |
12120 | section_type = 0; | |
12121 | if (*input_line_pointer++ == ',') | |
12122 | section_flag = get_absolute_expression (); | |
12123 | else | |
12124 | section_flag = 0; | |
12125 | if (*input_line_pointer++ == ',') | |
12126 | section_entry_size = get_absolute_expression (); | |
12127 | else | |
12128 | section_entry_size = 0; | |
12129 | if (*input_line_pointer++ == ',') | |
12130 | section_alignment = get_absolute_expression (); | |
12131 | else | |
12132 | section_alignment = 0; | |
12133 | ||
a816d1ed AO |
12134 | section_name = xstrdup (section_name); |
12135 | ||
cca86cc8 SC |
12136 | obj_elf_change_section (section_name, section_type, section_flag, |
12137 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12138 | |
12139 | if (now_seg->name != section_name) | |
12140 | free (section_name); | |
7ed4a06a | 12141 | #endif /* OBJ_ELF */ |
cca86cc8 | 12142 | } |
252b5132 RH |
12143 | |
12144 | void | |
12145 | mips_enable_auto_align () | |
12146 | { | |
12147 | auto_align = 1; | |
12148 | } | |
12149 | ||
12150 | static void | |
12151 | s_cons (log_size) | |
12152 | int log_size; | |
12153 | { | |
12154 | symbolS *label; | |
12155 | ||
12156 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12157 | mips_emit_delays (FALSE); |
252b5132 RH |
12158 | if (log_size > 0 && auto_align) |
12159 | mips_align (log_size, 0, label); | |
12160 | mips_clear_insn_labels (); | |
12161 | cons (1 << log_size); | |
12162 | } | |
12163 | ||
12164 | static void | |
12165 | s_float_cons (type) | |
12166 | int type; | |
12167 | { | |
12168 | symbolS *label; | |
12169 | ||
12170 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
12171 | ||
b34976b6 | 12172 | mips_emit_delays (FALSE); |
252b5132 RH |
12173 | |
12174 | if (auto_align) | |
49309057 ILT |
12175 | { |
12176 | if (type == 'd') | |
12177 | mips_align (3, 0, label); | |
12178 | else | |
12179 | mips_align (2, 0, label); | |
12180 | } | |
252b5132 RH |
12181 | |
12182 | mips_clear_insn_labels (); | |
12183 | ||
12184 | float_cons (type); | |
12185 | } | |
12186 | ||
12187 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12188 | permitted to say | |
12189 | .globl foo .text | |
12190 | where foo is an undefined symbol, to mean that foo should be | |
12191 | considered to be the address of a function. */ | |
12192 | ||
12193 | static void | |
12194 | s_mips_globl (x) | |
43841e91 | 12195 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12196 | { |
12197 | char *name; | |
12198 | int c; | |
12199 | symbolS *symbolP; | |
12200 | flagword flag; | |
12201 | ||
12202 | name = input_line_pointer; | |
12203 | c = get_symbol_end (); | |
12204 | symbolP = symbol_find_or_make (name); | |
12205 | *input_line_pointer = c; | |
12206 | SKIP_WHITESPACE (); | |
12207 | ||
12208 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
12209 | being a function is apparently labelled as being an object. */ | |
12210 | flag = BSF_OBJECT; | |
12211 | ||
12212 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12213 | { | |
12214 | char *secname; | |
12215 | asection *sec; | |
12216 | ||
12217 | secname = input_line_pointer; | |
12218 | c = get_symbol_end (); | |
12219 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12220 | if (sec == NULL) | |
12221 | as_bad (_("%s: no such section"), secname); | |
12222 | *input_line_pointer = c; | |
12223 | ||
12224 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12225 | flag = BSF_FUNCTION; | |
12226 | } | |
12227 | ||
49309057 | 12228 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
12229 | |
12230 | S_SET_EXTERNAL (symbolP); | |
12231 | demand_empty_rest_of_line (); | |
12232 | } | |
12233 | ||
12234 | static void | |
12235 | s_option (x) | |
43841e91 | 12236 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12237 | { |
12238 | char *opt; | |
12239 | char c; | |
12240 | ||
12241 | opt = input_line_pointer; | |
12242 | c = get_symbol_end (); | |
12243 | ||
12244 | if (*opt == 'O') | |
12245 | { | |
12246 | /* FIXME: What does this mean? */ | |
12247 | } | |
12248 | else if (strncmp (opt, "pic", 3) == 0) | |
12249 | { | |
12250 | int i; | |
12251 | ||
12252 | i = atoi (opt + 3); | |
12253 | if (i == 0) | |
12254 | mips_pic = NO_PIC; | |
12255 | else if (i == 2) | |
143d77c5 | 12256 | { |
252b5132 | 12257 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12258 | mips_abicalls = TRUE; |
12259 | } | |
252b5132 RH |
12260 | else |
12261 | as_bad (_(".option pic%d not supported"), i); | |
12262 | ||
12263 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
12264 | { | |
12265 | if (g_switch_seen && g_switch_value != 0) | |
12266 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12267 | g_switch_value = 0; | |
12268 | bfd_set_gp_size (stdoutput, 0); | |
12269 | } | |
12270 | } | |
12271 | else | |
12272 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12273 | ||
12274 | *input_line_pointer = c; | |
12275 | demand_empty_rest_of_line (); | |
12276 | } | |
12277 | ||
12278 | /* This structure is used to hold a stack of .set values. */ | |
12279 | ||
e972090a NC |
12280 | struct mips_option_stack |
12281 | { | |
252b5132 RH |
12282 | struct mips_option_stack *next; |
12283 | struct mips_set_options options; | |
12284 | }; | |
12285 | ||
12286 | static struct mips_option_stack *mips_opts_stack; | |
12287 | ||
12288 | /* Handle the .set pseudo-op. */ | |
12289 | ||
12290 | static void | |
12291 | s_mipsset (x) | |
43841e91 | 12292 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12293 | { |
12294 | char *name = input_line_pointer, ch; | |
12295 | ||
12296 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12297 | ++input_line_pointer; |
252b5132 RH |
12298 | ch = *input_line_pointer; |
12299 | *input_line_pointer = '\0'; | |
12300 | ||
12301 | if (strcmp (name, "reorder") == 0) | |
12302 | { | |
12303 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
12304 | { | |
12305 | /* If we still have pending nops, we can discard them. The | |
12306 | usual nop handling will insert any that are still | |
bdaaa2e1 | 12307 | needed. */ |
252b5132 RH |
12308 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
12309 | * (mips_opts.mips16 ? 2 : 4)); | |
12310 | prev_nop_frag = NULL; | |
12311 | } | |
12312 | mips_opts.noreorder = 0; | |
12313 | } | |
12314 | else if (strcmp (name, "noreorder") == 0) | |
12315 | { | |
b34976b6 | 12316 | mips_emit_delays (TRUE); |
252b5132 RH |
12317 | mips_opts.noreorder = 1; |
12318 | mips_any_noreorder = 1; | |
12319 | } | |
12320 | else if (strcmp (name, "at") == 0) | |
12321 | { | |
12322 | mips_opts.noat = 0; | |
12323 | } | |
12324 | else if (strcmp (name, "noat") == 0) | |
12325 | { | |
12326 | mips_opts.noat = 1; | |
12327 | } | |
12328 | else if (strcmp (name, "macro") == 0) | |
12329 | { | |
12330 | mips_opts.warn_about_macros = 0; | |
12331 | } | |
12332 | else if (strcmp (name, "nomacro") == 0) | |
12333 | { | |
12334 | if (mips_opts.noreorder == 0) | |
12335 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12336 | mips_opts.warn_about_macros = 1; | |
12337 | } | |
12338 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12339 | { | |
12340 | mips_opts.nomove = 0; | |
12341 | } | |
12342 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12343 | { | |
12344 | mips_opts.nomove = 1; | |
12345 | } | |
12346 | else if (strcmp (name, "bopt") == 0) | |
12347 | { | |
12348 | mips_opts.nobopt = 0; | |
12349 | } | |
12350 | else if (strcmp (name, "nobopt") == 0) | |
12351 | { | |
12352 | mips_opts.nobopt = 1; | |
12353 | } | |
12354 | else if (strcmp (name, "mips16") == 0 | |
12355 | || strcmp (name, "MIPS-16") == 0) | |
12356 | mips_opts.mips16 = 1; | |
12357 | else if (strcmp (name, "nomips16") == 0 | |
12358 | || strcmp (name, "noMIPS-16") == 0) | |
12359 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
12360 | else if (strcmp (name, "mips3d") == 0) |
12361 | mips_opts.ase_mips3d = 1; | |
12362 | else if (strcmp (name, "nomips3d") == 0) | |
12363 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12364 | else if (strcmp (name, "mdmx") == 0) |
12365 | mips_opts.ase_mdmx = 1; | |
12366 | else if (strcmp (name, "nomdmx") == 0) | |
12367 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
12368 | else if (strncmp (name, "mips", 4) == 0) |
12369 | { | |
af7ee8bf | 12370 | int reset = 0; |
252b5132 RH |
12371 | |
12372 | /* Permit the user to change the ISA on the fly. Needless to | |
12373 | say, misuse can cause serious problems. */ | |
af7ee8bf CD |
12374 | if (strcmp (name, "mips0") == 0) |
12375 | { | |
12376 | reset = 1; | |
12377 | mips_opts.isa = file_mips_isa; | |
12378 | } | |
12379 | else if (strcmp (name, "mips1") == 0) | |
12380 | mips_opts.isa = ISA_MIPS1; | |
12381 | else if (strcmp (name, "mips2") == 0) | |
12382 | mips_opts.isa = ISA_MIPS2; | |
12383 | else if (strcmp (name, "mips3") == 0) | |
12384 | mips_opts.isa = ISA_MIPS3; | |
12385 | else if (strcmp (name, "mips4") == 0) | |
12386 | mips_opts.isa = ISA_MIPS4; | |
12387 | else if (strcmp (name, "mips5") == 0) | |
12388 | mips_opts.isa = ISA_MIPS5; | |
12389 | else if (strcmp (name, "mips32") == 0) | |
12390 | mips_opts.isa = ISA_MIPS32; | |
12391 | else if (strcmp (name, "mips32r2") == 0) | |
12392 | mips_opts.isa = ISA_MIPS32R2; | |
12393 | else if (strcmp (name, "mips64") == 0) | |
12394 | mips_opts.isa = ISA_MIPS64; | |
12395 | else | |
12396 | as_bad (_("unknown ISA level %s"), name + 4); | |
12397 | ||
12398 | switch (mips_opts.isa) | |
98d3f06f KH |
12399 | { |
12400 | case 0: | |
98d3f06f | 12401 | break; |
af7ee8bf CD |
12402 | case ISA_MIPS1: |
12403 | case ISA_MIPS2: | |
12404 | case ISA_MIPS32: | |
12405 | case ISA_MIPS32R2: | |
98d3f06f KH |
12406 | mips_opts.gp32 = 1; |
12407 | mips_opts.fp32 = 1; | |
12408 | break; | |
af7ee8bf CD |
12409 | case ISA_MIPS3: |
12410 | case ISA_MIPS4: | |
12411 | case ISA_MIPS5: | |
12412 | case ISA_MIPS64: | |
98d3f06f KH |
12413 | mips_opts.gp32 = 0; |
12414 | mips_opts.fp32 = 0; | |
12415 | break; | |
12416 | default: | |
12417 | as_bad (_("unknown ISA level %s"), name + 4); | |
12418 | break; | |
12419 | } | |
af7ee8bf | 12420 | if (reset) |
98d3f06f | 12421 | { |
af7ee8bf CD |
12422 | mips_opts.gp32 = file_mips_gp32; |
12423 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12424 | } |
252b5132 RH |
12425 | } |
12426 | else if (strcmp (name, "autoextend") == 0) | |
12427 | mips_opts.noautoextend = 0; | |
12428 | else if (strcmp (name, "noautoextend") == 0) | |
12429 | mips_opts.noautoextend = 1; | |
12430 | else if (strcmp (name, "push") == 0) | |
12431 | { | |
12432 | struct mips_option_stack *s; | |
12433 | ||
12434 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12435 | s->next = mips_opts_stack; | |
12436 | s->options = mips_opts; | |
12437 | mips_opts_stack = s; | |
12438 | } | |
12439 | else if (strcmp (name, "pop") == 0) | |
12440 | { | |
12441 | struct mips_option_stack *s; | |
12442 | ||
12443 | s = mips_opts_stack; | |
12444 | if (s == NULL) | |
12445 | as_bad (_(".set pop with no .set push")); | |
12446 | else | |
12447 | { | |
12448 | /* If we're changing the reorder mode we need to handle | |
12449 | delay slots correctly. */ | |
12450 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12451 | mips_emit_delays (TRUE); |
252b5132 RH |
12452 | else if (! s->options.noreorder && mips_opts.noreorder) |
12453 | { | |
12454 | if (prev_nop_frag != NULL) | |
12455 | { | |
12456 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12457 | * (mips_opts.mips16 ? 2 : 4)); | |
12458 | prev_nop_frag = NULL; | |
12459 | } | |
12460 | } | |
12461 | ||
12462 | mips_opts = s->options; | |
12463 | mips_opts_stack = s->next; | |
12464 | free (s); | |
12465 | } | |
12466 | } | |
12467 | else | |
12468 | { | |
12469 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12470 | } | |
12471 | *input_line_pointer = ch; | |
12472 | demand_empty_rest_of_line (); | |
12473 | } | |
12474 | ||
12475 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12476 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12477 | ||
12478 | static void | |
12479 | s_abicalls (ignore) | |
43841e91 | 12480 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12481 | { |
12482 | mips_pic = SVR4_PIC; | |
143d77c5 | 12483 | mips_abicalls = TRUE; |
252b5132 RH |
12484 | if (USE_GLOBAL_POINTER_OPT) |
12485 | { | |
12486 | if (g_switch_seen && g_switch_value != 0) | |
12487 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12488 | g_switch_value = 0; | |
12489 | } | |
12490 | bfd_set_gp_size (stdoutput, 0); | |
12491 | demand_empty_rest_of_line (); | |
12492 | } | |
12493 | ||
12494 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12495 | PIC code. It sets the $gp register for the function based on the | |
12496 | function address, which is in the register named in the argument. | |
12497 | This uses a relocation against _gp_disp, which is handled specially | |
12498 | by the linker. The result is: | |
12499 | lui $gp,%hi(_gp_disp) | |
12500 | addiu $gp,$gp,%lo(_gp_disp) | |
12501 | addu $gp,$gp,.cpload argument | |
12502 | The .cpload argument is normally $25 == $t9. */ | |
12503 | ||
12504 | static void | |
12505 | s_cpload (ignore) | |
43841e91 | 12506 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12507 | { |
12508 | expressionS ex; | |
12509 | int icnt = 0; | |
12510 | ||
6478892d TS |
12511 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12512 | .cpload is ignored. */ | |
12513 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12514 | { |
12515 | s_ignore (0); | |
12516 | return; | |
12517 | } | |
12518 | ||
d3ecfc59 | 12519 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12520 | if (mips_opts.noreorder == 0) |
12521 | as_warn (_(".cpload not in noreorder section")); | |
12522 | ||
12523 | ex.X_op = O_symbol; | |
12524 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12525 | ex.X_op_symbol = NULL; | |
12526 | ex.X_add_number = 0; | |
12527 | ||
12528 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12529 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12530 | |
c9914766 TS |
12531 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
12532 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
12533 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
12534 | |
12535 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 12536 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
12537 | |
12538 | demand_empty_rest_of_line (); | |
12539 | } | |
12540 | ||
6478892d TS |
12541 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12542 | .cpsetup $reg1, offset|$reg2, label | |
12543 | ||
12544 | If offset is given, this results in: | |
12545 | sd $gp, offset($sp) | |
956cd1d6 | 12546 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12547 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12548 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12549 | |
12550 | If $reg2 is given, this results in: | |
12551 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12552 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12553 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12554 | daddu $gp, $gp, $reg1 | |
12555 | $reg1 is normally $25 == $t9. */ | |
6478892d TS |
12556 | static void |
12557 | s_cpsetup (ignore) | |
12558 | int ignore ATTRIBUTE_UNUSED; | |
12559 | { | |
12560 | expressionS ex_off; | |
12561 | expressionS ex_sym; | |
12562 | int reg1; | |
12563 | int icnt = 0; | |
f21f8242 | 12564 | char *f; |
6478892d | 12565 | |
8586fc66 | 12566 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12567 | We also need NewABI support. */ |
12568 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12569 | { | |
12570 | s_ignore (0); | |
12571 | return; | |
12572 | } | |
12573 | ||
12574 | reg1 = tc_get_register (0); | |
12575 | SKIP_WHITESPACE (); | |
12576 | if (*input_line_pointer != ',') | |
12577 | { | |
12578 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12579 | return; | |
12580 | } | |
12581 | else | |
80245285 | 12582 | ++input_line_pointer; |
6478892d TS |
12583 | SKIP_WHITESPACE (); |
12584 | if (*input_line_pointer == '$') | |
80245285 TS |
12585 | { |
12586 | mips_cpreturn_register = tc_get_register (0); | |
12587 | mips_cpreturn_offset = -1; | |
12588 | } | |
6478892d | 12589 | else |
80245285 TS |
12590 | { |
12591 | mips_cpreturn_offset = get_absolute_expression (); | |
12592 | mips_cpreturn_register = -1; | |
12593 | } | |
6478892d TS |
12594 | SKIP_WHITESPACE (); |
12595 | if (*input_line_pointer != ',') | |
12596 | { | |
12597 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12598 | return; | |
12599 | } | |
12600 | else | |
f9419b05 | 12601 | ++input_line_pointer; |
6478892d | 12602 | SKIP_WHITESPACE (); |
f21f8242 | 12603 | expression (&ex_sym); |
6478892d TS |
12604 | |
12605 | if (mips_cpreturn_register == -1) | |
12606 | { | |
12607 | ex_off.X_op = O_constant; | |
12608 | ex_off.X_add_symbol = NULL; | |
12609 | ex_off.X_op_symbol = NULL; | |
12610 | ex_off.X_add_number = mips_cpreturn_offset; | |
12611 | ||
12612 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
815ddb50 | 12613 | mips_gp_register, (int) BFD_RELOC_LO16, SP); |
6478892d TS |
12614 | } |
12615 | else | |
12616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12617 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
12618 | ||
f21f8242 AO |
12619 | /* Ensure there's room for the next two instructions, so that `f' |
12620 | doesn't end up with an address in the wrong frag. */ | |
12621 | frag_grow (8); | |
12622 | f = frag_more (0); | |
6478892d TS |
12623 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12624 | (int) BFD_RELOC_GPREL16); | |
f21f8242 | 12625 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12626 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12627 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12628 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12629 | |
12630 | f = frag_more (0); | |
6478892d TS |
12631 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
12632 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
f21f8242 | 12633 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12634 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12635 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12636 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12637 | |
f899b4b8 TS |
12638 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
12639 | "d,v,t", mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
12640 | |
12641 | demand_empty_rest_of_line (); | |
12642 | } | |
12643 | ||
12644 | static void | |
12645 | s_cplocal (ignore) | |
12646 | int ignore ATTRIBUTE_UNUSED; | |
12647 | { | |
12648 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12649 | .cplocal is ignored. */ | |
12650 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12651 | { | |
12652 | s_ignore (0); | |
12653 | return; | |
12654 | } | |
12655 | ||
12656 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12657 | demand_empty_rest_of_line (); |
6478892d TS |
12658 | } |
12659 | ||
252b5132 RH |
12660 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12661 | offset from $sp. The offset is remembered, and after making a PIC | |
12662 | call $gp is restored from that location. */ | |
12663 | ||
12664 | static void | |
12665 | s_cprestore (ignore) | |
43841e91 | 12666 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12667 | { |
12668 | expressionS ex; | |
12669 | int icnt = 0; | |
12670 | ||
6478892d | 12671 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12672 | .cprestore is ignored. */ |
6478892d | 12673 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12674 | { |
12675 | s_ignore (0); | |
12676 | return; | |
12677 | } | |
12678 | ||
12679 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12680 | mips_cprestore_valid = 1; |
252b5132 RH |
12681 | |
12682 | ex.X_op = O_constant; | |
12683 | ex.X_add_symbol = NULL; | |
12684 | ex.X_op_symbol = NULL; | |
12685 | ex.X_add_number = mips_cprestore_offset; | |
12686 | ||
f899b4b8 | 12687 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, ADDRESS_STORE_INSN, |
815ddb50 | 12688 | mips_gp_register, SP); |
252b5132 RH |
12689 | |
12690 | demand_empty_rest_of_line (); | |
12691 | } | |
12692 | ||
6478892d TS |
12693 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12694 | was given in the preceeding .gpsetup, it results in: | |
12695 | ld $gp, offset($sp) | |
76b3015f | 12696 | |
6478892d TS |
12697 | If a register $reg2 was given there, it results in: |
12698 | daddiu $gp, $gp, $reg2 | |
12699 | */ | |
12700 | static void | |
12701 | s_cpreturn (ignore) | |
12702 | int ignore ATTRIBUTE_UNUSED; | |
12703 | { | |
12704 | expressionS ex; | |
12705 | int icnt = 0; | |
12706 | ||
12707 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12708 | We also need NewABI support. */ | |
12709 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12710 | { | |
12711 | s_ignore (0); | |
12712 | return; | |
12713 | } | |
12714 | ||
12715 | if (mips_cpreturn_register == -1) | |
12716 | { | |
12717 | ex.X_op = O_constant; | |
12718 | ex.X_add_symbol = NULL; | |
12719 | ex.X_op_symbol = NULL; | |
12720 | ex.X_add_number = mips_cpreturn_offset; | |
12721 | ||
12722 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
815ddb50 | 12723 | mips_gp_register, (int) BFD_RELOC_LO16, SP); |
6478892d TS |
12724 | } |
12725 | else | |
12726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12727 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
12728 | ||
12729 | demand_empty_rest_of_line (); | |
12730 | } | |
12731 | ||
12732 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12733 | code. It sets the offset to use in gp_rel relocations. */ | |
12734 | ||
12735 | static void | |
12736 | s_gpvalue (ignore) | |
12737 | int ignore ATTRIBUTE_UNUSED; | |
12738 | { | |
12739 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12740 | We also need NewABI support. */ | |
12741 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12742 | { | |
12743 | s_ignore (0); | |
12744 | return; | |
12745 | } | |
12746 | ||
def2e0dd | 12747 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12748 | |
12749 | demand_empty_rest_of_line (); | |
12750 | } | |
12751 | ||
252b5132 RH |
12752 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12753 | code. It generates a 32 bit GP relative reloc. */ | |
12754 | ||
12755 | static void | |
12756 | s_gpword (ignore) | |
43841e91 | 12757 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12758 | { |
12759 | symbolS *label; | |
12760 | expressionS ex; | |
12761 | char *p; | |
12762 | ||
12763 | /* When not generating PIC code, this is treated as .word. */ | |
12764 | if (mips_pic != SVR4_PIC) | |
12765 | { | |
12766 | s_cons (2); | |
12767 | return; | |
12768 | } | |
12769 | ||
12770 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12771 | mips_emit_delays (TRUE); |
252b5132 RH |
12772 | if (auto_align) |
12773 | mips_align (2, 0, label); | |
12774 | mips_clear_insn_labels (); | |
12775 | ||
12776 | expression (&ex); | |
12777 | ||
12778 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12779 | { | |
12780 | as_bad (_("Unsupported use of .gpword")); | |
12781 | ignore_rest_of_line (); | |
12782 | } | |
12783 | ||
12784 | p = frag_more (4); | |
12785 | md_number_to_chars (p, (valueT) 0, 4); | |
b34976b6 | 12786 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12787 | BFD_RELOC_GPREL32); |
252b5132 RH |
12788 | |
12789 | demand_empty_rest_of_line (); | |
12790 | } | |
12791 | ||
10181a0d AO |
12792 | static void |
12793 | s_gpdword (ignore) | |
12794 | int ignore ATTRIBUTE_UNUSED; | |
12795 | { | |
12796 | symbolS *label; | |
12797 | expressionS ex; | |
12798 | char *p; | |
12799 | ||
12800 | /* When not generating PIC code, this is treated as .dword. */ | |
12801 | if (mips_pic != SVR4_PIC) | |
12802 | { | |
12803 | s_cons (3); | |
12804 | return; | |
12805 | } | |
12806 | ||
12807 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12808 | mips_emit_delays (TRUE); |
10181a0d AO |
12809 | if (auto_align) |
12810 | mips_align (3, 0, label); | |
12811 | mips_clear_insn_labels (); | |
12812 | ||
12813 | expression (&ex); | |
12814 | ||
12815 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12816 | { | |
12817 | as_bad (_("Unsupported use of .gpdword")); | |
12818 | ignore_rest_of_line (); | |
12819 | } | |
12820 | ||
12821 | p = frag_more (8); | |
12822 | md_number_to_chars (p, (valueT) 0, 8); | |
a105a300 | 12823 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12824 | BFD_RELOC_GPREL32); |
12825 | ||
12826 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12827 | ex.X_op = O_absent; | |
12828 | ex.X_add_symbol = 0; | |
12829 | ex.X_add_number = 0; | |
b34976b6 | 12830 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12831 | BFD_RELOC_64); |
12832 | ||
12833 | demand_empty_rest_of_line (); | |
12834 | } | |
12835 | ||
252b5132 RH |
12836 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12837 | tables in SVR4 PIC code. */ | |
12838 | ||
12839 | static void | |
12840 | s_cpadd (ignore) | |
43841e91 | 12841 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12842 | { |
12843 | int icnt = 0; | |
12844 | int reg; | |
12845 | ||
10181a0d AO |
12846 | /* This is ignored when not generating SVR4 PIC code. */ |
12847 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12848 | { |
12849 | s_ignore (0); | |
12850 | return; | |
12851 | } | |
12852 | ||
12853 | /* Add $gp to the register named as an argument. */ | |
12854 | reg = tc_get_register (0); | |
f899b4b8 | 12855 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
c9914766 | 12856 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12857 | |
bdaaa2e1 | 12858 | demand_empty_rest_of_line (); |
252b5132 RH |
12859 | } |
12860 | ||
12861 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12862 | mips16 mode. This permits the linker to handle them specially, | |
12863 | such as generating jalx instructions when needed. We also make | |
12864 | them odd for the duration of the assembly, in order to generate the | |
12865 | right sort of code. We will make them even in the adjust_symtab | |
12866 | routine, while leaving them marked. This is convenient for the | |
12867 | debugger and the disassembler. The linker knows to make them odd | |
12868 | again. */ | |
12869 | ||
12870 | static void | |
12871 | s_insn (ignore) | |
43841e91 | 12872 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12873 | { |
f9419b05 | 12874 | mips16_mark_labels (); |
252b5132 RH |
12875 | |
12876 | demand_empty_rest_of_line (); | |
12877 | } | |
12878 | ||
12879 | /* Handle a .stabn directive. We need these in order to mark a label | |
12880 | as being a mips16 text label correctly. Sometimes the compiler | |
12881 | will emit a label, followed by a .stabn, and then switch sections. | |
12882 | If the label and .stabn are in mips16 mode, then the label is | |
12883 | really a mips16 text label. */ | |
12884 | ||
12885 | static void | |
12886 | s_mips_stab (type) | |
12887 | int type; | |
12888 | { | |
f9419b05 | 12889 | if (type == 'n') |
252b5132 RH |
12890 | mips16_mark_labels (); |
12891 | ||
12892 | s_stab (type); | |
12893 | } | |
12894 | ||
12895 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12896 | */ | |
12897 | ||
12898 | static void | |
12899 | s_mips_weakext (ignore) | |
43841e91 | 12900 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12901 | { |
12902 | char *name; | |
12903 | int c; | |
12904 | symbolS *symbolP; | |
12905 | expressionS exp; | |
12906 | ||
12907 | name = input_line_pointer; | |
12908 | c = get_symbol_end (); | |
12909 | symbolP = symbol_find_or_make (name); | |
12910 | S_SET_WEAK (symbolP); | |
12911 | *input_line_pointer = c; | |
12912 | ||
12913 | SKIP_WHITESPACE (); | |
12914 | ||
12915 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12916 | { | |
12917 | if (S_IS_DEFINED (symbolP)) | |
12918 | { | |
956cd1d6 | 12919 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12920 | S_GET_NAME (symbolP)); |
12921 | ignore_rest_of_line (); | |
12922 | return; | |
12923 | } | |
bdaaa2e1 | 12924 | |
252b5132 RH |
12925 | if (*input_line_pointer == ',') |
12926 | { | |
12927 | ++input_line_pointer; | |
12928 | SKIP_WHITESPACE (); | |
12929 | } | |
bdaaa2e1 | 12930 | |
252b5132 RH |
12931 | expression (&exp); |
12932 | if (exp.X_op != O_symbol) | |
12933 | { | |
12934 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12935 | ignore_rest_of_line (); |
252b5132 RH |
12936 | return; |
12937 | } | |
49309057 | 12938 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12939 | } |
12940 | ||
12941 | demand_empty_rest_of_line (); | |
12942 | } | |
12943 | ||
12944 | /* Parse a register string into a number. Called from the ECOFF code | |
12945 | to parse .frame. The argument is non-zero if this is the frame | |
12946 | register, so that we can record it in mips_frame_reg. */ | |
12947 | ||
12948 | int | |
12949 | tc_get_register (frame) | |
12950 | int frame; | |
12951 | { | |
12952 | int reg; | |
12953 | ||
12954 | SKIP_WHITESPACE (); | |
12955 | if (*input_line_pointer++ != '$') | |
12956 | { | |
12957 | as_warn (_("expected `$'")); | |
85b51719 | 12958 | reg = ZERO; |
252b5132 | 12959 | } |
3882b010 | 12960 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12961 | { |
12962 | reg = get_absolute_expression (); | |
12963 | if (reg < 0 || reg >= 32) | |
12964 | { | |
12965 | as_warn (_("Bad register number")); | |
85b51719 | 12966 | reg = ZERO; |
252b5132 RH |
12967 | } |
12968 | } | |
12969 | else | |
12970 | { | |
76db943d | 12971 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12972 | { |
12973 | reg = RA; | |
12974 | input_line_pointer += 2; | |
12975 | } | |
76db943d | 12976 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12977 | { |
12978 | reg = FP; | |
12979 | input_line_pointer += 2; | |
12980 | } | |
252b5132 | 12981 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12982 | { |
12983 | reg = SP; | |
12984 | input_line_pointer += 2; | |
12985 | } | |
252b5132 | 12986 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12987 | { |
12988 | reg = GP; | |
12989 | input_line_pointer += 2; | |
12990 | } | |
252b5132 | 12991 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12992 | { |
12993 | reg = AT; | |
12994 | input_line_pointer += 2; | |
12995 | } | |
12996 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12997 | { | |
12998 | reg = KT0; | |
12999 | input_line_pointer += 3; | |
13000 | } | |
13001 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
13002 | { | |
13003 | reg = KT1; | |
13004 | input_line_pointer += 3; | |
13005 | } | |
13006 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
13007 | { | |
13008 | reg = ZERO; | |
13009 | input_line_pointer += 4; | |
13010 | } | |
252b5132 RH |
13011 | else |
13012 | { | |
13013 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
13014 | reg = ZERO; |
13015 | while (ISALNUM(*input_line_pointer)) | |
13016 | input_line_pointer++; | |
252b5132 | 13017 | } |
252b5132 RH |
13018 | } |
13019 | if (frame) | |
7a621144 DJ |
13020 | { |
13021 | mips_frame_reg = reg != 0 ? reg : SP; | |
13022 | mips_frame_reg_valid = 1; | |
13023 | mips_cprestore_valid = 0; | |
13024 | } | |
252b5132 RH |
13025 | return reg; |
13026 | } | |
13027 | ||
13028 | valueT | |
13029 | md_section_align (seg, addr) | |
13030 | asection *seg; | |
13031 | valueT addr; | |
13032 | { | |
13033 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13034 | ||
13035 | #ifdef OBJ_ELF | |
13036 | /* We don't need to align ELF sections to the full alignment. | |
13037 | However, Irix 5 may prefer that we align them at least to a 16 | |
13038 | byte boundary. We don't bother to align the sections if we are | |
13039 | targeted for an embedded system. */ | |
13040 | if (strcmp (TARGET_OS, "elf") == 0) | |
13041 | return addr; | |
13042 | if (align > 4) | |
13043 | align = 4; | |
13044 | #endif | |
13045 | ||
13046 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13047 | } | |
13048 | ||
13049 | /* Utility routine, called from above as well. If called while the | |
13050 | input file is still being read, it's only an approximation. (For | |
13051 | example, a symbol may later become defined which appeared to be | |
13052 | undefined earlier.) */ | |
13053 | ||
13054 | static int | |
13055 | nopic_need_relax (sym, before_relaxing) | |
13056 | symbolS *sym; | |
13057 | int before_relaxing; | |
13058 | { | |
13059 | if (sym == 0) | |
13060 | return 0; | |
13061 | ||
6478892d | 13062 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
13063 | { |
13064 | const char *symname; | |
13065 | int change; | |
13066 | ||
c9914766 | 13067 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13068 | register. It can be if it is smaller than the -G size or if |
13069 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13070 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13071 | they can. */ |
13072 | symname = S_GET_NAME (sym); | |
13073 | if (symname != (const char *) NULL | |
13074 | && (strcmp (symname, "eprol") == 0 | |
13075 | || strcmp (symname, "etext") == 0 | |
13076 | || strcmp (symname, "_gp") == 0 | |
13077 | || strcmp (symname, "edata") == 0 | |
13078 | || strcmp (symname, "_fbss") == 0 | |
13079 | || strcmp (symname, "_fdata") == 0 | |
13080 | || strcmp (symname, "_ftext") == 0 | |
13081 | || strcmp (symname, "end") == 0 | |
13082 | || strcmp (symname, "_gp_disp") == 0)) | |
13083 | change = 1; | |
13084 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13085 | && (0 | |
13086 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13087 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13088 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13089 | <= g_switch_value)) | |
252b5132 RH |
13090 | #endif |
13091 | /* We must defer this decision until after the whole | |
13092 | file has been read, since there might be a .extern | |
13093 | after the first use of this symbol. */ | |
13094 | || (before_relaxing | |
13095 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13096 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13097 | #endif |
13098 | && S_GET_VALUE (sym) == 0) | |
13099 | || (S_GET_VALUE (sym) != 0 | |
13100 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13101 | change = 0; | |
13102 | else | |
13103 | { | |
13104 | const char *segname; | |
13105 | ||
13106 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13107 | assert (strcmp (segname, ".lit8") != 0 | |
13108 | && strcmp (segname, ".lit4") != 0); | |
13109 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13110 | && strcmp (segname, ".sbss") != 0 |
13111 | && strncmp (segname, ".sdata.", 7) != 0 | |
13112 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
13113 | } |
13114 | return change; | |
13115 | } | |
13116 | else | |
c9914766 | 13117 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13118 | return 1; |
13119 | } | |
13120 | ||
5919d012 RS |
13121 | |
13122 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13123 | ||
13124 | static bfd_boolean | |
13125 | pic_need_relax (sym, segtype) | |
13126 | symbolS *sym; | |
13127 | asection *segtype; | |
13128 | { | |
13129 | asection *symsec; | |
13130 | bfd_boolean linkonce; | |
13131 | ||
13132 | /* Handle the case of a symbol equated to another symbol. */ | |
13133 | while (symbol_equated_reloc_p (sym)) | |
13134 | { | |
13135 | symbolS *n; | |
13136 | ||
13137 | /* It's possible to get a loop here in a badly written | |
13138 | program. */ | |
13139 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
13140 | if (n == sym) | |
13141 | break; | |
13142 | sym = n; | |
13143 | } | |
13144 | ||
13145 | symsec = S_GET_SEGMENT (sym); | |
13146 | ||
13147 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
13148 | linkonce = FALSE; | |
13149 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
13150 | { | |
13151 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
13152 | != 0) | |
13153 | linkonce = TRUE; | |
13154 | ||
13155 | /* The GNU toolchain uses an extension for ELF: a section | |
13156 | beginning with the magic string .gnu.linkonce is a linkonce | |
13157 | section. */ | |
13158 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
13159 | sizeof ".gnu.linkonce" - 1) == 0) | |
13160 | linkonce = TRUE; | |
13161 | } | |
13162 | ||
13163 | /* This must duplicate the test in adjust_reloc_syms. */ | |
13164 | return (symsec != &bfd_und_section | |
13165 | && symsec != &bfd_abs_section | |
13166 | && ! bfd_is_com_section (symsec) | |
13167 | && !linkonce | |
13168 | #ifdef OBJ_ELF | |
13169 | /* A global or weak symbol is treated as external. */ | |
13170 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
13171 | || (! S_IS_WEAK (sym) | |
13172 | && (! S_IS_EXTERNAL (sym) | |
13173 | || mips_pic == EMBEDDED_PIC))) | |
13174 | #endif | |
13175 | ); | |
13176 | } | |
13177 | ||
13178 | ||
252b5132 RH |
13179 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13180 | extended opcode. SEC is the section the frag is in. */ | |
13181 | ||
13182 | static int | |
13183 | mips16_extended_frag (fragp, sec, stretch) | |
13184 | fragS *fragp; | |
13185 | asection *sec; | |
13186 | long stretch; | |
13187 | { | |
13188 | int type; | |
13189 | register const struct mips16_immed_operand *op; | |
13190 | offsetT val; | |
13191 | int mintiny, maxtiny; | |
13192 | segT symsec; | |
98aa84af | 13193 | fragS *sym_frag; |
252b5132 RH |
13194 | |
13195 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13196 | return 0; | |
13197 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13198 | return 1; | |
13199 | ||
13200 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13201 | op = mips16_immed_operands; | |
13202 | while (op->type != type) | |
13203 | { | |
13204 | ++op; | |
13205 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13206 | } | |
13207 | ||
13208 | if (op->unsp) | |
13209 | { | |
13210 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13211 | { | |
13212 | mintiny = 1; | |
13213 | maxtiny = 1 << op->nbits; | |
13214 | } | |
13215 | else | |
13216 | { | |
13217 | mintiny = 0; | |
13218 | maxtiny = (1 << op->nbits) - 1; | |
13219 | } | |
13220 | } | |
13221 | else | |
13222 | { | |
13223 | mintiny = - (1 << (op->nbits - 1)); | |
13224 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13225 | } | |
13226 | ||
98aa84af | 13227 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13228 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13229 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13230 | |
13231 | if (op->pcrel) | |
13232 | { | |
13233 | addressT addr; | |
13234 | ||
13235 | /* We won't have the section when we are called from | |
13236 | mips_relax_frag. However, we will always have been called | |
13237 | from md_estimate_size_before_relax first. If this is a | |
13238 | branch to a different section, we mark it as such. If SEC is | |
13239 | NULL, and the frag is not marked, then it must be a branch to | |
13240 | the same section. */ | |
13241 | if (sec == NULL) | |
13242 | { | |
13243 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13244 | return 1; | |
13245 | } | |
13246 | else | |
13247 | { | |
98aa84af | 13248 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13249 | if (symsec != sec) |
13250 | { | |
13251 | fragp->fr_subtype = | |
13252 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13253 | ||
13254 | /* FIXME: We should support this, and let the linker | |
13255 | catch branches and loads that are out of range. */ | |
13256 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13257 | _("unsupported PC relative reference to different section")); | |
13258 | ||
13259 | return 1; | |
13260 | } | |
98aa84af AM |
13261 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13262 | /* Assume non-extended on the first relaxation pass. | |
13263 | The address we have calculated will be bogus if this is | |
13264 | a forward branch to another frag, as the forward frag | |
13265 | will have fr_address == 0. */ | |
13266 | return 0; | |
252b5132 RH |
13267 | } |
13268 | ||
13269 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13270 | the same section. If the relax_marker of the symbol fragment |
13271 | differs from the relax_marker of this fragment, we have not | |
13272 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13273 | in STRETCH in order to get a better estimate of the address. |
13274 | This particularly matters because of the shift bits. */ | |
13275 | if (stretch != 0 | |
98aa84af | 13276 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13277 | { |
13278 | fragS *f; | |
13279 | ||
13280 | /* Adjust stretch for any alignment frag. Note that if have | |
13281 | been expanding the earlier code, the symbol may be | |
13282 | defined in what appears to be an earlier frag. FIXME: | |
13283 | This doesn't handle the fr_subtype field, which specifies | |
13284 | a maximum number of bytes to skip when doing an | |
13285 | alignment. */ | |
98aa84af | 13286 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13287 | { |
13288 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13289 | { | |
13290 | if (stretch < 0) | |
13291 | stretch = - ((- stretch) | |
13292 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13293 | else | |
13294 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13295 | if (stretch == 0) | |
13296 | break; | |
13297 | } | |
13298 | } | |
13299 | if (f != NULL) | |
13300 | val += stretch; | |
13301 | } | |
13302 | ||
13303 | addr = fragp->fr_address + fragp->fr_fix; | |
13304 | ||
13305 | /* The base address rules are complicated. The base address of | |
13306 | a branch is the following instruction. The base address of a | |
13307 | PC relative load or add is the instruction itself, but if it | |
13308 | is in a delay slot (in which case it can not be extended) use | |
13309 | the address of the instruction whose delay slot it is in. */ | |
13310 | if (type == 'p' || type == 'q') | |
13311 | { | |
13312 | addr += 2; | |
13313 | ||
13314 | /* If we are currently assuming that this frag should be | |
13315 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13316 | higher. */ |
252b5132 RH |
13317 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13318 | addr += 2; | |
13319 | ||
13320 | /* Ignore the low bit in the target, since it will be set | |
13321 | for a text label. */ | |
13322 | if ((val & 1) != 0) | |
13323 | --val; | |
13324 | } | |
13325 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13326 | addr -= 4; | |
13327 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13328 | addr -= 2; | |
13329 | ||
13330 | val -= addr & ~ ((1 << op->shift) - 1); | |
13331 | ||
13332 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13333 | if (type == 'p' || type == 'q') | |
13334 | val /= 2; | |
13335 | ||
13336 | /* If any of the shifted bits are set, we must use an extended | |
13337 | opcode. If the address depends on the size of this | |
13338 | instruction, this can lead to a loop, so we arrange to always | |
13339 | use an extended opcode. We only check this when we are in | |
13340 | the main relaxation loop, when SEC is NULL. */ | |
13341 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13342 | { | |
13343 | fragp->fr_subtype = | |
13344 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13345 | return 1; | |
13346 | } | |
13347 | ||
13348 | /* If we are about to mark a frag as extended because the value | |
13349 | is precisely maxtiny + 1, then there is a chance of an | |
13350 | infinite loop as in the following code: | |
13351 | la $4,foo | |
13352 | .skip 1020 | |
13353 | .align 2 | |
13354 | foo: | |
13355 | In this case when the la is extended, foo is 0x3fc bytes | |
13356 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13357 | the la must be extended. To avoid this loop, we mark the | |
13358 | frag as extended if it was small, and is about to become | |
13359 | extended with a value of maxtiny + 1. */ | |
13360 | if (val == ((maxtiny + 1) << op->shift) | |
13361 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13362 | && sec == NULL) | |
13363 | { | |
13364 | fragp->fr_subtype = | |
13365 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13366 | return 1; | |
13367 | } | |
13368 | } | |
13369 | else if (symsec != absolute_section && sec != NULL) | |
13370 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13371 | ||
13372 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13373 | || val < (mintiny << op->shift) | |
13374 | || val > (maxtiny << op->shift)) | |
13375 | return 1; | |
13376 | else | |
13377 | return 0; | |
13378 | } | |
13379 | ||
4a6a3df4 AO |
13380 | /* Compute the length of a branch sequence, and adjust the |
13381 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13382 | worst-case length is computed, with UPDATE being used to indicate | |
13383 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13384 | branch is to be computed. */ | |
13385 | static int | |
13386 | relaxed_branch_length (fragp, sec, update) | |
13387 | fragS *fragp; | |
13388 | asection *sec; | |
13389 | int update; | |
13390 | { | |
b34976b6 | 13391 | bfd_boolean toofar; |
4a6a3df4 AO |
13392 | int length; |
13393 | ||
13394 | if (fragp | |
13395 | && S_IS_DEFINED (fragp->fr_symbol) | |
13396 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13397 | { | |
13398 | addressT addr; | |
13399 | offsetT val; | |
13400 | ||
13401 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13402 | ||
13403 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13404 | ||
13405 | val -= addr; | |
13406 | ||
13407 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13408 | } | |
13409 | else if (fragp) | |
13410 | /* If the symbol is not defined or it's in a different segment, | |
13411 | assume the user knows what's going on and emit a short | |
13412 | branch. */ | |
b34976b6 | 13413 | toofar = FALSE; |
4a6a3df4 | 13414 | else |
b34976b6 | 13415 | toofar = TRUE; |
4a6a3df4 AO |
13416 | |
13417 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13418 | fragp->fr_subtype | |
af6ae2ad | 13419 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13420 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13421 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13422 | toofar); | |
13423 | ||
13424 | length = 4; | |
13425 | if (toofar) | |
13426 | { | |
13427 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13428 | length += 8; | |
13429 | ||
13430 | if (mips_pic != NO_PIC) | |
13431 | { | |
13432 | /* Additional space for PIC loading of target address. */ | |
13433 | length += 8; | |
13434 | if (mips_opts.isa == ISA_MIPS1) | |
13435 | /* Additional space for $at-stabilizing nop. */ | |
13436 | length += 4; | |
13437 | } | |
13438 | ||
13439 | /* If branch is conditional. */ | |
13440 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13441 | length += 8; | |
13442 | } | |
b34976b6 | 13443 | |
4a6a3df4 AO |
13444 | return length; |
13445 | } | |
13446 | ||
252b5132 RH |
13447 | /* Estimate the size of a frag before relaxing. Unless this is the |
13448 | mips16, we are not really relaxing here, and the final size is | |
13449 | encoded in the subtype information. For the mips16, we have to | |
13450 | decide whether we are using an extended opcode or not. */ | |
13451 | ||
252b5132 RH |
13452 | int |
13453 | md_estimate_size_before_relax (fragp, segtype) | |
13454 | fragS *fragp; | |
13455 | asection *segtype; | |
13456 | { | |
5919d012 | 13457 | int change; |
252b5132 | 13458 | |
4a6a3df4 AO |
13459 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13460 | { | |
13461 | ||
b34976b6 AM |
13462 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13463 | ||
4a6a3df4 AO |
13464 | return fragp->fr_var; |
13465 | } | |
13466 | ||
252b5132 | 13467 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13468 | /* We don't want to modify the EXTENDED bit here; it might get us |
13469 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13470 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13471 | |
13472 | if (mips_pic == NO_PIC) | |
5919d012 | 13473 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13474 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13475 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13476 | else |
13477 | abort (); | |
13478 | ||
13479 | if (change) | |
13480 | { | |
13481 | /* Record the offset to the first reloc in the fr_opcode field. | |
13482 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13483 | must be expanded. */ | |
13484 | fragp->fr_opcode = (fragp->fr_literal | |
13485 | + fragp->fr_fix | |
13486 | - RELAX_OLD (fragp->fr_subtype) | |
13487 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13488 | /* FIXME: This really needs as_warn_where. */ | |
13489 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13490 | as_warn (_("AT used after \".set noat\" or macro used after " |
13491 | "\".set nomacro\"")); | |
13492 | ||
13493 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13494 | } |
13495 | ||
9a41af64 | 13496 | return 0; |
252b5132 RH |
13497 | } |
13498 | ||
13499 | /* This is called to see whether a reloc against a defined symbol | |
13500 | should be converted into a reloc against a section. Don't adjust | |
13501 | MIPS16 jump relocations, so we don't have to worry about the format | |
13502 | of the offset in the .o file. Don't adjust relocations against | |
13503 | mips16 symbols, so that the linker can find them if it needs to set | |
13504 | up a stub. */ | |
13505 | ||
13506 | int | |
13507 | mips_fix_adjustable (fixp) | |
13508 | fixS *fixp; | |
13509 | { | |
13510 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13511 | return 0; | |
a161fe53 | 13512 | |
252b5132 RH |
13513 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13514 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13515 | return 0; | |
a161fe53 | 13516 | |
252b5132 RH |
13517 | if (fixp->fx_addsy == NULL) |
13518 | return 1; | |
a161fe53 | 13519 | |
252b5132 RH |
13520 | #ifdef OBJ_ELF |
13521 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13522 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13523 | && fixp->fx_subsy == NULL) | |
13524 | return 0; | |
13525 | #endif | |
a161fe53 | 13526 | |
252b5132 RH |
13527 | return 1; |
13528 | } | |
13529 | ||
13530 | /* Translate internal representation of relocation info to BFD target | |
13531 | format. */ | |
13532 | ||
13533 | arelent ** | |
13534 | tc_gen_reloc (section, fixp) | |
43841e91 | 13535 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
13536 | fixS *fixp; |
13537 | { | |
13538 | static arelent *retval[4]; | |
13539 | arelent *reloc; | |
13540 | bfd_reloc_code_real_type code; | |
13541 | ||
4b0cff4e TS |
13542 | memset (retval, 0, sizeof(retval)); |
13543 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13544 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13545 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13546 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13547 | ||
13548 | if (mips_pic == EMBEDDED_PIC | |
13549 | && SWITCH_TABLE (fixp)) | |
13550 | { | |
13551 | /* For a switch table entry we use a special reloc. The addend | |
13552 | is actually the difference between the reloc address and the | |
13553 | subtrahend. */ | |
13554 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13555 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13556 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13557 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13558 | } | |
13559 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13560 | { | |
4514d474 CD |
13561 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13562 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13563 | else |
4514d474 CD |
13564 | { |
13565 | /* We use a special addend for an internal RELLO reloc. */ | |
13566 | if (symbol_section_p (fixp->fx_addsy)) | |
13567 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13568 | else | |
13569 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13570 | } | |
252b5132 RH |
13571 | } |
13572 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13573 | { | |
13574 | assert (fixp->fx_next != NULL | |
13575 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13576 | |
13577 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13578 | accordingly. */ |
4514d474 CD |
13579 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13580 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13581 | else |
4514d474 CD |
13582 | { |
13583 | /* We use a special addend for an internal RELHI reloc. */ | |
13584 | if (symbol_section_p (fixp->fx_addsy)) | |
13585 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13586 | + fixp->fx_next->fx_where | |
13587 | - S_GET_VALUE (fixp->fx_subsy)); | |
13588 | else | |
13589 | reloc->addend = (fixp->fx_addnumber | |
13590 | + fixp->fx_next->fx_frag->fr_address | |
13591 | + fixp->fx_next->fx_where); | |
13592 | } | |
252b5132 | 13593 | } |
4514d474 CD |
13594 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13595 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13596 | else |
13597 | { | |
13598 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13599 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13600 | handling. */ | |
13601 | reloc->addend = reloc->address; | |
13602 | else | |
13603 | reloc->addend = -reloc->address; | |
13604 | } | |
13605 | ||
13606 | /* If this is a variant frag, we may need to adjust the existing | |
13607 | reloc and generate a new one. */ | |
13608 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13609 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13610 | && ! HAVE_NEWABI) | |
f5040a92 AO |
13611 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP |
13612 | && HAVE_NEWABI) | |
252b5132 RH |
13613 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13614 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13615 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13616 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13617 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13618 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13619 | ) |
252b5132 RH |
13620 | { |
13621 | arelent *reloc2; | |
13622 | ||
13623 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13624 | ||
13625 | /* If this is not the last reloc in this frag, then we have two | |
13626 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13627 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13628 | the second one handle all of them. */ | |
13629 | if (fixp->fx_next != NULL | |
13630 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13631 | { | |
cdf6fd85 TS |
13632 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13633 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13634 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13635 | && (fixp->fx_next->fx_r_type | |
13636 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13637 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13638 | && (fixp->fx_next->fx_r_type | |
13639 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13640 | retval[0] = NULL; | |
13641 | return retval; | |
13642 | } | |
13643 | ||
13644 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13645 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
f5040a92 | 13646 | reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 | 13647 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
49309057 ILT |
13648 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13649 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13650 | reloc2->address = (reloc->address |
13651 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13652 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
a7ebbfdf | 13653 | reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy) |
f5040a92 | 13654 | + fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 RH |
13655 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
13656 | assert (reloc2->howto != NULL); | |
13657 | ||
13658 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13659 | { | |
13660 | arelent *reloc3; | |
13661 | ||
13662 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
252b5132 RH |
13663 | *reloc3 = *reloc2; |
13664 | reloc3->address += 4; | |
13665 | } | |
13666 | ||
13667 | if (mips_pic == NO_PIC) | |
13668 | { | |
cdf6fd85 | 13669 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13670 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13671 | } | |
13672 | else if (mips_pic == SVR4_PIC) | |
13673 | { | |
13674 | switch (fixp->fx_r_type) | |
13675 | { | |
13676 | default: | |
13677 | abort (); | |
13678 | case BFD_RELOC_MIPS_GOT16: | |
13679 | break; | |
252b5132 RH |
13680 | case BFD_RELOC_MIPS_GOT_LO16: |
13681 | case BFD_RELOC_MIPS_CALL_LO16: | |
ed6fb7bd SC |
13682 | if (HAVE_NEWABI) |
13683 | { | |
ed6fb7bd SC |
13684 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; |
13685 | reloc2->howto = bfd_reloc_type_lookup | |
13686 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13687 | } | |
13688 | else | |
13689 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13690 | break; | |
f5040a92 AO |
13691 | case BFD_RELOC_MIPS_CALL16: |
13692 | case BFD_RELOC_MIPS_GOT_OFST: | |
13693 | case BFD_RELOC_MIPS_GOT_DISP: | |
13694 | if (HAVE_NEWABI) | |
13695 | { | |
13696 | /* It may seem nonsensical to relax GOT_DISP to | |
13697 | GOT_DISP, but we're actually turning a GOT_DISP | |
13698 | without offset into a GOT_DISP with an offset, | |
13699 | getting rid of the separate addition, which we can | |
13700 | do when the symbol is found to be local. */ | |
13701 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13702 | retval[1] = NULL; | |
13703 | } | |
13704 | else | |
13705 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13706 | break; | |
252b5132 RH |
13707 | } |
13708 | } | |
13709 | else | |
13710 | abort (); | |
13711 | } | |
13712 | ||
438c16b8 TS |
13713 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13714 | entry to be used in the relocation's section offset. */ | |
13715 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13716 | { |
13717 | reloc->address = reloc->addend; | |
13718 | reloc->addend = 0; | |
13719 | } | |
13720 | ||
13721 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13722 | fixup_segment converted a non-PC relative reloc into a PC | |
13723 | relative reloc. In such a case, we need to convert the reloc | |
13724 | code. */ | |
13725 | code = fixp->fx_r_type; | |
13726 | if (fixp->fx_pcrel) | |
13727 | { | |
13728 | switch (code) | |
13729 | { | |
13730 | case BFD_RELOC_8: | |
13731 | code = BFD_RELOC_8_PCREL; | |
13732 | break; | |
13733 | case BFD_RELOC_16: | |
13734 | code = BFD_RELOC_16_PCREL; | |
13735 | break; | |
13736 | case BFD_RELOC_32: | |
13737 | code = BFD_RELOC_32_PCREL; | |
13738 | break; | |
13739 | case BFD_RELOC_64: | |
13740 | code = BFD_RELOC_64_PCREL; | |
13741 | break; | |
13742 | case BFD_RELOC_8_PCREL: | |
13743 | case BFD_RELOC_16_PCREL: | |
13744 | case BFD_RELOC_32_PCREL: | |
13745 | case BFD_RELOC_64_PCREL: | |
13746 | case BFD_RELOC_16_PCREL_S2: | |
13747 | case BFD_RELOC_PCREL_HI16_S: | |
13748 | case BFD_RELOC_PCREL_LO16: | |
13749 | break; | |
13750 | default: | |
13751 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13752 | _("Cannot make %s relocation PC relative"), | |
13753 | bfd_get_reloc_code_name (code)); | |
13754 | } | |
13755 | } | |
13756 | ||
0b25d3e6 AO |
13757 | /* To support a PC relative reloc when generating embedded PIC code |
13758 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13759 | make sure that we don't let such a reloc escape normally. */ | |
13760 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13761 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13762 | && code == BFD_RELOC_16_PCREL_S2 | |
13763 | && mips_pic != EMBEDDED_PIC) | |
13764 | reloc->howto = NULL; | |
13765 | else | |
13766 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13767 | ||
252b5132 RH |
13768 | if (reloc->howto == NULL) |
13769 | { | |
13770 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13771 | _("Can not represent %s relocation in this object file format"), | |
13772 | bfd_get_reloc_code_name (code)); | |
13773 | retval[0] = NULL; | |
13774 | } | |
13775 | ||
13776 | return retval; | |
13777 | } | |
13778 | ||
13779 | /* Relax a machine dependent frag. This returns the amount by which | |
13780 | the current size of the frag should change. */ | |
13781 | ||
13782 | int | |
4a6a3df4 AO |
13783 | mips_relax_frag (sec, fragp, stretch) |
13784 | asection *sec; | |
252b5132 RH |
13785 | fragS *fragp; |
13786 | long stretch; | |
13787 | { | |
4a6a3df4 AO |
13788 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13789 | { | |
13790 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13791 | |
13792 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13793 | |
13794 | return fragp->fr_var - old_var; | |
13795 | } | |
13796 | ||
252b5132 RH |
13797 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13798 | return 0; | |
13799 | ||
c4e7957c | 13800 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13801 | { |
13802 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13803 | return 0; | |
13804 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13805 | return 2; | |
13806 | } | |
13807 | else | |
13808 | { | |
13809 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13810 | return 0; | |
13811 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13812 | return -2; | |
13813 | } | |
13814 | ||
13815 | return 0; | |
13816 | } | |
13817 | ||
13818 | /* Convert a machine dependent frag. */ | |
13819 | ||
13820 | void | |
13821 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 13822 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
13823 | segT asec; |
13824 | fragS *fragp; | |
13825 | { | |
13826 | int old, new; | |
13827 | char *fixptr; | |
13828 | ||
4a6a3df4 AO |
13829 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13830 | { | |
13831 | bfd_byte *buf; | |
13832 | unsigned long insn; | |
13833 | expressionS exp; | |
13834 | fixS *fixp; | |
b34976b6 | 13835 | |
4a6a3df4 AO |
13836 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13837 | ||
13838 | if (target_big_endian) | |
13839 | insn = bfd_getb32 (buf); | |
13840 | else | |
13841 | insn = bfd_getl32 (buf); | |
b34976b6 | 13842 | |
4a6a3df4 AO |
13843 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13844 | { | |
13845 | /* We generate a fixup instead of applying it right now | |
13846 | because, if there are linker relaxations, we're going to | |
13847 | need the relocations. */ | |
13848 | exp.X_op = O_symbol; | |
13849 | exp.X_add_symbol = fragp->fr_symbol; | |
13850 | exp.X_add_number = fragp->fr_offset; | |
13851 | ||
13852 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13853 | 4, &exp, 1, |
13854 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13855 | fixp->fx_file = fragp->fr_file; |
13856 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13857 | |
4a6a3df4 AO |
13858 | md_number_to_chars ((char *)buf, insn, 4); |
13859 | buf += 4; | |
13860 | } | |
13861 | else | |
13862 | { | |
13863 | int i; | |
13864 | ||
13865 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13866 | _("relaxed out-of-range branch into a jump")); | |
13867 | ||
13868 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13869 | goto uncond; | |
13870 | ||
13871 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13872 | { | |
13873 | /* Reverse the branch. */ | |
13874 | switch ((insn >> 28) & 0xf) | |
13875 | { | |
13876 | case 4: | |
13877 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13878 | have the condition reversed by tweaking a single | |
13879 | bit, and their opcodes all have 0x4???????. */ | |
13880 | assert ((insn & 0xf1000000) == 0x41000000); | |
13881 | insn ^= 0x00010000; | |
13882 | break; | |
13883 | ||
13884 | case 0: | |
13885 | /* bltz 0x04000000 bgez 0x04010000 | |
13886 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13887 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13888 | insn ^= 0x00010000; | |
13889 | break; | |
b34976b6 | 13890 | |
4a6a3df4 AO |
13891 | case 1: |
13892 | /* beq 0x10000000 bne 0x14000000 | |
13893 | blez 0x18000000 bgtz 0x1c000000 */ | |
13894 | insn ^= 0x04000000; | |
13895 | break; | |
13896 | ||
13897 | default: | |
13898 | abort (); | |
13899 | } | |
13900 | } | |
13901 | ||
13902 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13903 | { | |
13904 | /* Clear the and-link bit. */ | |
13905 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13906 | ||
13907 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13908 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13909 | insn &= ~0x00100000; | |
13910 | } | |
13911 | ||
13912 | /* Branch over the branch (if the branch was likely) or the | |
13913 | full jump (not likely case). Compute the offset from the | |
13914 | current instruction to branch to. */ | |
13915 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13916 | i = 16; | |
13917 | else | |
13918 | { | |
13919 | /* How many bytes in instructions we've already emitted? */ | |
13920 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13921 | /* How many bytes in instructions from here to the end? */ | |
13922 | i = fragp->fr_var - i; | |
13923 | } | |
13924 | /* Convert to instruction count. */ | |
13925 | i >>= 2; | |
13926 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13927 | i--; |
4a6a3df4 AO |
13928 | insn |= i; |
13929 | /* Branch over the jump. */ | |
13930 | md_number_to_chars ((char *)buf, insn, 4); | |
13931 | buf += 4; | |
13932 | ||
13933 | /* Nop */ | |
13934 | md_number_to_chars ((char*)buf, 0, 4); | |
13935 | buf += 4; | |
13936 | ||
13937 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13938 | { | |
13939 | /* beql $0, $0, 2f */ | |
13940 | insn = 0x50000000; | |
13941 | /* Compute the PC offset from the current instruction to | |
13942 | the end of the variable frag. */ | |
13943 | /* How many bytes in instructions we've already emitted? */ | |
13944 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13945 | /* How many bytes in instructions from here to the end? */ | |
13946 | i = fragp->fr_var - i; | |
13947 | /* Convert to instruction count. */ | |
13948 | i >>= 2; | |
13949 | /* Don't decrement i, because we want to branch over the | |
13950 | delay slot. */ | |
13951 | ||
13952 | insn |= i; | |
13953 | md_number_to_chars ((char *)buf, insn, 4); | |
13954 | buf += 4; | |
13955 | ||
13956 | md_number_to_chars ((char *)buf, 0, 4); | |
13957 | buf += 4; | |
13958 | } | |
13959 | ||
13960 | uncond: | |
13961 | if (mips_pic == NO_PIC) | |
13962 | { | |
13963 | /* j or jal. */ | |
13964 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13965 | ? 0x0c000000 : 0x08000000); | |
13966 | exp.X_op = O_symbol; | |
13967 | exp.X_add_symbol = fragp->fr_symbol; | |
13968 | exp.X_add_number = fragp->fr_offset; | |
13969 | ||
13970 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13971 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13972 | fixp->fx_file = fragp->fr_file; | |
13973 | fixp->fx_line = fragp->fr_line; | |
13974 | ||
13975 | md_number_to_chars ((char*)buf, insn, 4); | |
13976 | buf += 4; | |
13977 | } | |
13978 | else | |
13979 | { | |
13980 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13981 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13982 | exp.X_op = O_symbol; | |
13983 | exp.X_add_symbol = fragp->fr_symbol; | |
13984 | exp.X_add_number = fragp->fr_offset; | |
13985 | ||
13986 | if (fragp->fr_offset) | |
13987 | { | |
13988 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13989 | exp.X_add_number = 0; | |
13990 | } | |
13991 | ||
13992 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13993 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13994 | fixp->fx_file = fragp->fr_file; | |
13995 | fixp->fx_line = fragp->fr_line; | |
13996 | ||
13997 | md_number_to_chars ((char*)buf, insn, 4); | |
13998 | buf += 4; | |
b34976b6 | 13999 | |
4a6a3df4 AO |
14000 | if (mips_opts.isa == ISA_MIPS1) |
14001 | { | |
14002 | /* nop */ | |
14003 | md_number_to_chars ((char*)buf, 0, 4); | |
14004 | buf += 4; | |
14005 | } | |
14006 | ||
14007 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14008 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14009 | ||
14010 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
14011 | 4, &exp, 0, BFD_RELOC_LO16); | |
14012 | fixp->fx_file = fragp->fr_file; | |
14013 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14014 | |
4a6a3df4 AO |
14015 | md_number_to_chars ((char*)buf, insn, 4); |
14016 | buf += 4; | |
14017 | ||
14018 | /* j(al)r $at. */ | |
14019 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14020 | insn = 0x0020f809; | |
14021 | else | |
14022 | insn = 0x00200008; | |
14023 | ||
14024 | md_number_to_chars ((char*)buf, insn, 4); | |
14025 | buf += 4; | |
14026 | } | |
14027 | } | |
14028 | ||
14029 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14030 | + fragp->fr_fix + fragp->fr_var); | |
14031 | ||
14032 | fragp->fr_fix += fragp->fr_var; | |
14033 | ||
14034 | return; | |
14035 | } | |
14036 | ||
252b5132 RH |
14037 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14038 | { | |
14039 | int type; | |
14040 | register const struct mips16_immed_operand *op; | |
b34976b6 | 14041 | bfd_boolean small, ext; |
252b5132 RH |
14042 | offsetT val; |
14043 | bfd_byte *buf; | |
14044 | unsigned long insn; | |
b34976b6 | 14045 | bfd_boolean use_extend; |
252b5132 RH |
14046 | unsigned short extend; |
14047 | ||
14048 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14049 | op = mips16_immed_operands; | |
14050 | while (op->type != type) | |
14051 | ++op; | |
14052 | ||
14053 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14054 | { | |
b34976b6 AM |
14055 | small = FALSE; |
14056 | ext = TRUE; | |
252b5132 RH |
14057 | } |
14058 | else | |
14059 | { | |
b34976b6 AM |
14060 | small = TRUE; |
14061 | ext = FALSE; | |
252b5132 RH |
14062 | } |
14063 | ||
6386f3a7 | 14064 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14065 | val = S_GET_VALUE (fragp->fr_symbol); |
14066 | if (op->pcrel) | |
14067 | { | |
14068 | addressT addr; | |
14069 | ||
14070 | addr = fragp->fr_address + fragp->fr_fix; | |
14071 | ||
14072 | /* The rules for the base address of a PC relative reloc are | |
14073 | complicated; see mips16_extended_frag. */ | |
14074 | if (type == 'p' || type == 'q') | |
14075 | { | |
14076 | addr += 2; | |
14077 | if (ext) | |
14078 | addr += 2; | |
14079 | /* Ignore the low bit in the target, since it will be | |
14080 | set for a text label. */ | |
14081 | if ((val & 1) != 0) | |
14082 | --val; | |
14083 | } | |
14084 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14085 | addr -= 4; | |
14086 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14087 | addr -= 2; | |
14088 | ||
14089 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14090 | val -= addr; | |
14091 | ||
14092 | /* Make sure the section winds up with the alignment we have | |
14093 | assumed. */ | |
14094 | if (op->shift > 0) | |
14095 | record_alignment (asec, op->shift); | |
14096 | } | |
14097 | ||
14098 | if (ext | |
14099 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14100 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14101 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14102 | _("extended instruction in delay slot")); | |
14103 | ||
14104 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14105 | ||
14106 | if (target_big_endian) | |
14107 | insn = bfd_getb16 (buf); | |
14108 | else | |
14109 | insn = bfd_getl16 (buf); | |
14110 | ||
14111 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14112 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14113 | small, ext, &insn, &use_extend, &extend); | |
14114 | ||
14115 | if (use_extend) | |
14116 | { | |
874e8986 | 14117 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14118 | fragp->fr_fix += 2; |
14119 | buf += 2; | |
14120 | } | |
14121 | ||
874e8986 | 14122 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14123 | fragp->fr_fix += 2; |
14124 | buf += 2; | |
14125 | } | |
14126 | else | |
14127 | { | |
14128 | if (fragp->fr_opcode == NULL) | |
14129 | return; | |
14130 | ||
14131 | old = RELAX_OLD (fragp->fr_subtype); | |
14132 | new = RELAX_NEW (fragp->fr_subtype); | |
14133 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
14134 | ||
14135 | if (new > 0) | |
f5040a92 | 14136 | memmove (fixptr - old, fixptr, new); |
252b5132 RH |
14137 | |
14138 | fragp->fr_fix += new - old; | |
14139 | } | |
14140 | } | |
14141 | ||
14142 | #ifdef OBJ_ELF | |
14143 | ||
14144 | /* This function is called after the relocs have been generated. | |
14145 | We've been storing mips16 text labels as odd. Here we convert them | |
14146 | back to even for the convenience of the debugger. */ | |
14147 | ||
14148 | void | |
14149 | mips_frob_file_after_relocs () | |
14150 | { | |
14151 | asymbol **syms; | |
14152 | unsigned int count, i; | |
14153 | ||
14154 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
14155 | return; | |
14156 | ||
14157 | syms = bfd_get_outsymbols (stdoutput); | |
14158 | count = bfd_get_symcount (stdoutput); | |
14159 | for (i = 0; i < count; i++, syms++) | |
14160 | { | |
14161 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14162 | && ((*syms)->value & 1) != 0) | |
14163 | { | |
14164 | (*syms)->value &= ~1; | |
14165 | /* If the symbol has an odd size, it was probably computed | |
14166 | incorrectly, so adjust that as well. */ | |
14167 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14168 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14169 | } | |
14170 | } | |
14171 | } | |
14172 | ||
14173 | #endif | |
14174 | ||
14175 | /* This function is called whenever a label is defined. It is used | |
14176 | when handling branch delays; if a branch has a label, we assume we | |
14177 | can not move it. */ | |
14178 | ||
14179 | void | |
14180 | mips_define_label (sym) | |
14181 | symbolS *sym; | |
14182 | { | |
14183 | struct insn_label_list *l; | |
14184 | ||
14185 | if (free_insn_labels == NULL) | |
14186 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14187 | else | |
14188 | { | |
14189 | l = free_insn_labels; | |
14190 | free_insn_labels = l->next; | |
14191 | } | |
14192 | ||
14193 | l->label = sym; | |
14194 | l->next = insn_labels; | |
14195 | insn_labels = l; | |
14196 | } | |
14197 | \f | |
14198 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14199 | ||
14200 | /* Some special processing for a MIPS ELF file. */ | |
14201 | ||
14202 | void | |
14203 | mips_elf_final_processing () | |
14204 | { | |
14205 | /* Write out the register information. */ | |
316f5878 | 14206 | if (mips_abi != N64_ABI) |
252b5132 RH |
14207 | { |
14208 | Elf32_RegInfo s; | |
14209 | ||
14210 | s.ri_gprmask = mips_gprmask; | |
14211 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14212 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14213 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14214 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14215 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14216 | ||
14217 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14218 | ((Elf32_External_RegInfo *) | |
14219 | mips_regmask_frag)); | |
14220 | } | |
14221 | else | |
14222 | { | |
14223 | Elf64_Internal_RegInfo s; | |
14224 | ||
14225 | s.ri_gprmask = mips_gprmask; | |
14226 | s.ri_pad = 0; | |
14227 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14228 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14229 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14230 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14231 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14232 | ||
14233 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14234 | ((Elf64_External_RegInfo *) | |
14235 | mips_regmask_frag)); | |
14236 | } | |
14237 | ||
14238 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14239 | sort of BFD interface for this. */ | |
14240 | if (mips_any_noreorder) | |
14241 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14242 | if (mips_pic != NO_PIC) | |
143d77c5 | 14243 | { |
252b5132 | 14244 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14245 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14246 | } | |
14247 | if (mips_abicalls) | |
14248 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14249 | |
98d3f06f | 14250 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
14251 | if (file_ase_mips16) |
14252 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14253 | #if 0 /* XXX FIXME */ |
14254 | if (file_ase_mips3d) | |
14255 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14256 | #endif | |
deec1734 CD |
14257 | if (file_ase_mdmx) |
14258 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14259 | |
bdaaa2e1 | 14260 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14261 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14262 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14263 | else if (mips_abi == O64_ABI) |
252b5132 | 14264 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14265 | else if (mips_abi == EABI_ABI) |
252b5132 | 14266 | { |
316f5878 | 14267 | if (!file_mips_gp32) |
252b5132 RH |
14268 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14269 | else | |
14270 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14271 | } | |
316f5878 | 14272 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14273 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14274 | ||
c9914766 | 14275 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14276 | |
14277 | if (mips_32bitmode) | |
14278 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
14279 | } | |
14280 | ||
14281 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14282 | \f | |
beae10d5 KH |
14283 | typedef struct proc { |
14284 | symbolS *isym; | |
14285 | unsigned long reg_mask; | |
14286 | unsigned long reg_offset; | |
14287 | unsigned long fpreg_mask; | |
14288 | unsigned long fpreg_offset; | |
14289 | unsigned long frame_offset; | |
14290 | unsigned long frame_reg; | |
14291 | unsigned long pc_reg; | |
14292 | } procS; | |
252b5132 RH |
14293 | |
14294 | static procS cur_proc; | |
14295 | static procS *cur_proc_ptr; | |
14296 | static int numprocs; | |
14297 | ||
0a9ef439 | 14298 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14299 | |
0a9ef439 RH |
14300 | void |
14301 | mips_handle_align (fragp) | |
14302 | fragS *fragp; | |
a19d8eb0 | 14303 | { |
0a9ef439 RH |
14304 | if (fragp->fr_type != rs_align_code) |
14305 | return; | |
14306 | ||
14307 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14308 | { |
14309 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14310 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14311 | ||
0a9ef439 RH |
14312 | int bytes; |
14313 | char *p; | |
a19d8eb0 | 14314 | |
0a9ef439 RH |
14315 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14316 | p = fragp->fr_literal + fragp->fr_fix; | |
14317 | ||
14318 | if (bytes & 1) | |
14319 | { | |
14320 | *p++ = 0; | |
f9419b05 | 14321 | fragp->fr_fix++; |
0a9ef439 RH |
14322 | } |
14323 | ||
14324 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14325 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14326 | } |
14327 | ||
0a9ef439 | 14328 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14329 | } |
14330 | ||
252b5132 RH |
14331 | static void |
14332 | md_obj_begin () | |
14333 | { | |
14334 | } | |
14335 | ||
14336 | static void | |
14337 | md_obj_end () | |
14338 | { | |
14339 | /* check for premature end, nesting errors, etc */ | |
14340 | if (cur_proc_ptr) | |
9a41af64 | 14341 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14342 | } |
14343 | ||
14344 | static long | |
14345 | get_number () | |
14346 | { | |
14347 | int negative = 0; | |
14348 | long val = 0; | |
14349 | ||
14350 | if (*input_line_pointer == '-') | |
14351 | { | |
14352 | ++input_line_pointer; | |
14353 | negative = 1; | |
14354 | } | |
3882b010 | 14355 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14356 | as_bad (_("expected simple number")); |
252b5132 RH |
14357 | if (input_line_pointer[0] == '0') |
14358 | { | |
14359 | if (input_line_pointer[1] == 'x') | |
14360 | { | |
14361 | input_line_pointer += 2; | |
3882b010 | 14362 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14363 | { |
14364 | val <<= 4; | |
14365 | val |= hex_value (*input_line_pointer++); | |
14366 | } | |
14367 | return negative ? -val : val; | |
14368 | } | |
14369 | else | |
14370 | { | |
14371 | ++input_line_pointer; | |
3882b010 | 14372 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14373 | { |
14374 | val <<= 3; | |
14375 | val |= *input_line_pointer++ - '0'; | |
14376 | } | |
14377 | return negative ? -val : val; | |
14378 | } | |
14379 | } | |
3882b010 | 14380 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14381 | { |
14382 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14383 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14384 | as_warn (_("invalid number")); |
252b5132 RH |
14385 | return -1; |
14386 | } | |
3882b010 | 14387 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14388 | { |
14389 | val *= 10; | |
14390 | val += *input_line_pointer++ - '0'; | |
14391 | } | |
14392 | return negative ? -val : val; | |
14393 | } | |
14394 | ||
14395 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14396 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14397 | case .file implies DWARF-2. */ | |
14398 | ||
14399 | static void | |
14400 | s_mips_file (x) | |
14401 | int x ATTRIBUTE_UNUSED; | |
14402 | { | |
ecb4347a DJ |
14403 | static int first_file_directive = 0; |
14404 | ||
c5dd6aab DJ |
14405 | if (ECOFF_DEBUGGING) |
14406 | { | |
14407 | get_number (); | |
14408 | s_app_file (0); | |
14409 | } | |
14410 | else | |
ecb4347a DJ |
14411 | { |
14412 | char *filename; | |
14413 | ||
14414 | filename = dwarf2_directive_file (0); | |
14415 | ||
14416 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14417 | directive even for stabs output. Make sure that this | |
14418 | ".file" is handled. Note that you need a version of GCC | |
14419 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14420 | if (filename != NULL && ! first_file_directive) | |
14421 | { | |
14422 | (void) new_logical_line (filename, -1); | |
14423 | s_app_file_string (filename); | |
14424 | } | |
14425 | first_file_directive = 1; | |
14426 | } | |
c5dd6aab DJ |
14427 | } |
14428 | ||
14429 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14430 | |
14431 | static void | |
c5dd6aab | 14432 | s_mips_loc (x) |
43841e91 | 14433 | int x ATTRIBUTE_UNUSED; |
252b5132 | 14434 | { |
c5dd6aab DJ |
14435 | if (!ECOFF_DEBUGGING) |
14436 | dwarf2_directive_loc (0); | |
252b5132 RH |
14437 | } |
14438 | ||
252b5132 RH |
14439 | /* The .end directive. */ |
14440 | ||
14441 | static void | |
14442 | s_mips_end (x) | |
43841e91 | 14443 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
14444 | { |
14445 | symbolS *p; | |
252b5132 | 14446 | |
7a621144 DJ |
14447 | /* Following functions need their own .frame and .cprestore directives. */ |
14448 | mips_frame_reg_valid = 0; | |
14449 | mips_cprestore_valid = 0; | |
14450 | ||
252b5132 RH |
14451 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14452 | { | |
14453 | p = get_symbol (); | |
14454 | demand_empty_rest_of_line (); | |
14455 | } | |
14456 | else | |
14457 | p = NULL; | |
14458 | ||
14949570 | 14459 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14460 | as_warn (_(".end not in text section")); |
14461 | ||
14462 | if (!cur_proc_ptr) | |
14463 | { | |
14464 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14465 | demand_empty_rest_of_line (); | |
14466 | return; | |
14467 | } | |
14468 | ||
14469 | if (p != NULL) | |
14470 | { | |
14471 | assert (S_GET_NAME (p)); | |
14472 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14473 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14474 | |
14475 | if (debug_type == DEBUG_STABS) | |
14476 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14477 | S_GET_NAME (p)); | |
252b5132 RH |
14478 | } |
14479 | else | |
14480 | as_warn (_(".end directive missing or unknown symbol")); | |
14481 | ||
ecb4347a DJ |
14482 | #ifdef OBJ_ELF |
14483 | /* Generate a .pdr section. */ | |
14484 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14485 | { | |
14486 | segT saved_seg = now_seg; | |
14487 | subsegT saved_subseg = now_subseg; | |
14488 | valueT dot; | |
14489 | expressionS exp; | |
14490 | char *fragp; | |
252b5132 | 14491 | |
ecb4347a | 14492 | dot = frag_now_fix (); |
252b5132 RH |
14493 | |
14494 | #ifdef md_flush_pending_output | |
ecb4347a | 14495 | md_flush_pending_output (); |
252b5132 RH |
14496 | #endif |
14497 | ||
ecb4347a DJ |
14498 | assert (pdr_seg); |
14499 | subseg_set (pdr_seg, 0); | |
252b5132 | 14500 | |
ecb4347a DJ |
14501 | /* Write the symbol. */ |
14502 | exp.X_op = O_symbol; | |
14503 | exp.X_add_symbol = p; | |
14504 | exp.X_add_number = 0; | |
14505 | emit_expr (&exp, 4); | |
252b5132 | 14506 | |
ecb4347a | 14507 | fragp = frag_more (7 * 4); |
252b5132 | 14508 | |
ecb4347a DJ |
14509 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
14510 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
14511 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
14512 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
14513 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
14514 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
14515 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14516 | |
ecb4347a DJ |
14517 | subseg_set (saved_seg, saved_subseg); |
14518 | } | |
14519 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14520 | |
14521 | cur_proc_ptr = NULL; | |
14522 | } | |
14523 | ||
14524 | /* The .aent and .ent directives. */ | |
14525 | ||
14526 | static void | |
14527 | s_mips_ent (aent) | |
14528 | int aent; | |
14529 | { | |
252b5132 | 14530 | symbolS *symbolP; |
252b5132 RH |
14531 | |
14532 | symbolP = get_symbol (); | |
14533 | if (*input_line_pointer == ',') | |
f9419b05 | 14534 | ++input_line_pointer; |
252b5132 | 14535 | SKIP_WHITESPACE (); |
3882b010 | 14536 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14537 | || *input_line_pointer == '-') |
874e8986 | 14538 | get_number (); |
252b5132 | 14539 | |
14949570 | 14540 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14541 | as_warn (_(".ent or .aent not in text section.")); |
14542 | ||
14543 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14544 | as_warn (_("missing .end")); |
252b5132 RH |
14545 | |
14546 | if (!aent) | |
14547 | { | |
7a621144 DJ |
14548 | /* This function needs its own .frame and .cprestore directives. */ |
14549 | mips_frame_reg_valid = 0; | |
14550 | mips_cprestore_valid = 0; | |
14551 | ||
252b5132 RH |
14552 | cur_proc_ptr = &cur_proc; |
14553 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14554 | ||
14555 | cur_proc_ptr->isym = symbolP; | |
14556 | ||
49309057 | 14557 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14558 | |
f9419b05 | 14559 | ++numprocs; |
ecb4347a DJ |
14560 | |
14561 | if (debug_type == DEBUG_STABS) | |
14562 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14563 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14564 | } |
14565 | ||
14566 | demand_empty_rest_of_line (); | |
14567 | } | |
14568 | ||
14569 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14570 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14571 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14572 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14573 | symbol table (in the mdebug section). */ |
14574 | ||
14575 | static void | |
14576 | s_mips_frame (ignore) | |
2b3c5a5d | 14577 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 14578 | { |
ecb4347a DJ |
14579 | #ifdef OBJ_ELF |
14580 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14581 | { | |
14582 | long val; | |
252b5132 | 14583 | |
ecb4347a DJ |
14584 | if (cur_proc_ptr == (procS *) NULL) |
14585 | { | |
14586 | as_warn (_(".frame outside of .ent")); | |
14587 | demand_empty_rest_of_line (); | |
14588 | return; | |
14589 | } | |
252b5132 | 14590 | |
ecb4347a DJ |
14591 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14592 | ||
14593 | SKIP_WHITESPACE (); | |
14594 | if (*input_line_pointer++ != ',' | |
14595 | || get_absolute_expression_and_terminator (&val) != ',') | |
14596 | { | |
14597 | as_warn (_("Bad .frame directive")); | |
14598 | --input_line_pointer; | |
14599 | demand_empty_rest_of_line (); | |
14600 | return; | |
14601 | } | |
252b5132 | 14602 | |
ecb4347a DJ |
14603 | cur_proc_ptr->frame_offset = val; |
14604 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14605 | |
252b5132 | 14606 | demand_empty_rest_of_line (); |
252b5132 | 14607 | } |
ecb4347a DJ |
14608 | else |
14609 | #endif /* OBJ_ELF */ | |
14610 | s_ignore (ignore); | |
252b5132 RH |
14611 | } |
14612 | ||
bdaaa2e1 KH |
14613 | /* The .fmask and .mask directives. If the mdebug section is present |
14614 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14615 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14616 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14617 | make reference to the ecoff symbol table (in the mdebug section). */ |
14618 | ||
14619 | static void | |
14620 | s_mips_mask (reg_type) | |
14621 | char reg_type; | |
14622 | { | |
ecb4347a DJ |
14623 | #ifdef OBJ_ELF |
14624 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14625 | { |
ecb4347a | 14626 | long mask, off; |
252b5132 | 14627 | |
ecb4347a DJ |
14628 | if (cur_proc_ptr == (procS *) NULL) |
14629 | { | |
14630 | as_warn (_(".mask/.fmask outside of .ent")); | |
14631 | demand_empty_rest_of_line (); | |
14632 | return; | |
14633 | } | |
252b5132 | 14634 | |
ecb4347a DJ |
14635 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14636 | { | |
14637 | as_warn (_("Bad .mask/.fmask directive")); | |
14638 | --input_line_pointer; | |
14639 | demand_empty_rest_of_line (); | |
14640 | return; | |
14641 | } | |
252b5132 | 14642 | |
ecb4347a DJ |
14643 | off = get_absolute_expression (); |
14644 | ||
14645 | if (reg_type == 'F') | |
14646 | { | |
14647 | cur_proc_ptr->fpreg_mask = mask; | |
14648 | cur_proc_ptr->fpreg_offset = off; | |
14649 | } | |
14650 | else | |
14651 | { | |
14652 | cur_proc_ptr->reg_mask = mask; | |
14653 | cur_proc_ptr->reg_offset = off; | |
14654 | } | |
14655 | ||
14656 | demand_empty_rest_of_line (); | |
252b5132 RH |
14657 | } |
14658 | else | |
ecb4347a DJ |
14659 | #endif /* OBJ_ELF */ |
14660 | s_ignore (reg_type); | |
252b5132 RH |
14661 | } |
14662 | ||
14663 | /* The .loc directive. */ | |
14664 | ||
14665 | #if 0 | |
14666 | static void | |
14667 | s_loc (x) | |
14668 | int x; | |
14669 | { | |
14670 | symbolS *symbolP; | |
14671 | int lineno; | |
14672 | int addroff; | |
14673 | ||
14674 | assert (now_seg == text_section); | |
14675 | ||
14676 | lineno = get_number (); | |
14677 | addroff = frag_now_fix (); | |
14678 | ||
14679 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14680 | S_SET_TYPE (symbolP, N_SLINE); | |
14681 | S_SET_OTHER (symbolP, 0); | |
14682 | S_SET_DESC (symbolP, lineno); | |
14683 | symbolP->sy_segment = now_seg; | |
14684 | } | |
14685 | #endif | |
e7af610e | 14686 | |
316f5878 RS |
14687 | /* A table describing all the processors gas knows about. Names are |
14688 | matched in the order listed. | |
e7af610e | 14689 | |
316f5878 RS |
14690 | To ease comparison, please keep this table in the same order as |
14691 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14692 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14693 | { | |
316f5878 RS |
14694 | /* Entries for generic ISAs */ |
14695 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14696 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14697 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14698 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14699 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14700 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14701 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 RS |
14702 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
14703 | ||
14704 | /* MIPS I */ | |
14705 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14706 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14707 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14708 | ||
14709 | /* MIPS II */ | |
14710 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14711 | ||
14712 | /* MIPS III */ | |
14713 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14714 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14715 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14716 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14717 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14718 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14719 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14720 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14721 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14722 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14723 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14724 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14725 | ||
14726 | /* MIPS IV */ | |
14727 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14728 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14729 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14730 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14731 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14732 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14733 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14734 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14735 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14736 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14737 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14738 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, | |
14739 | ||
14740 | /* MIPS 32 */ | |
14741 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, | |
14742 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14743 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14744 | |
316f5878 RS |
14745 | /* MIPS 64 */ |
14746 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14747 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14748 | |
c7a23324 | 14749 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14750 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14751 | |
316f5878 RS |
14752 | /* End marker */ |
14753 | { NULL, 0, 0, 0 } | |
14754 | }; | |
e7af610e | 14755 | |
84ea6cf2 | 14756 | |
316f5878 RS |
14757 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14758 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14759 | |
316f5878 | 14760 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14761 | |
b34976b6 | 14762 | static bfd_boolean |
316f5878 RS |
14763 | mips_strict_matching_cpu_name_p (canonical, given) |
14764 | const char *canonical, *given; | |
14765 | { | |
14766 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14767 | given++, canonical++; | |
14768 | ||
14769 | return ((*given == 0 && *canonical == 0) | |
14770 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14771 | } | |
14772 | ||
14773 | ||
14774 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14775 | CPU name. We've traditionally allowed a lot of variation here. | |
14776 | ||
14777 | Note: this function is shared between GCC and GAS. */ | |
14778 | ||
b34976b6 | 14779 | static bfd_boolean |
316f5878 RS |
14780 | mips_matching_cpu_name_p (canonical, given) |
14781 | const char *canonical, *given; | |
14782 | { | |
14783 | /* First see if the name matches exactly, or with a final "000" | |
14784 | turned into "k". */ | |
14785 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14786 | return TRUE; |
316f5878 RS |
14787 | |
14788 | /* If not, try comparing based on numerical designation alone. | |
14789 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14790 | if (TOLOWER (*given) == 'r') | |
14791 | given++; | |
14792 | if (!ISDIGIT (*given)) | |
b34976b6 | 14793 | return FALSE; |
316f5878 RS |
14794 | |
14795 | /* Skip over some well-known prefixes in the canonical name, | |
14796 | hoping to find a number there too. */ | |
14797 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14798 | canonical += 2; | |
14799 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14800 | canonical += 2; | |
14801 | else if (TOLOWER (canonical[0]) == 'r') | |
14802 | canonical += 1; | |
14803 | ||
14804 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14805 | } | |
14806 | ||
14807 | ||
14808 | /* Parse an option that takes the name of a processor as its argument. | |
14809 | OPTION is the name of the option and CPU_STRING is the argument. | |
14810 | Return the corresponding processor enumeration if the CPU_STRING is | |
14811 | recognized, otherwise report an error and return null. | |
14812 | ||
14813 | A similar function exists in GCC. */ | |
e7af610e NC |
14814 | |
14815 | static const struct mips_cpu_info * | |
316f5878 RS |
14816 | mips_parse_cpu (option, cpu_string) |
14817 | const char *option, *cpu_string; | |
e7af610e | 14818 | { |
316f5878 | 14819 | const struct mips_cpu_info *p; |
e7af610e | 14820 | |
316f5878 RS |
14821 | /* 'from-abi' selects the most compatible architecture for the given |
14822 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14823 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14824 | version. Look first at the -mgp options, if given, otherwise base | |
14825 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14826 | |
316f5878 RS |
14827 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14828 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14829 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14830 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14831 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14832 | { | |
14833 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14834 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14835 | ||
14836 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14837 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14838 | ||
14839 | if (file_mips_gp32 >= 0) | |
14840 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14841 | ||
14842 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14843 | ? ISA_MIPS3 | |
14844 | : ISA_MIPS1); | |
14845 | } | |
14846 | ||
14847 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14848 | if (strcasecmp (cpu_string, "default") == 0) | |
14849 | return 0; | |
14850 | ||
14851 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14852 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14853 | return p; | |
14854 | ||
14855 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14856 | return 0; | |
e7af610e NC |
14857 | } |
14858 | ||
316f5878 RS |
14859 | /* Return the canonical processor information for ISA (a member of the |
14860 | ISA_MIPS* enumeration). */ | |
14861 | ||
e7af610e NC |
14862 | static const struct mips_cpu_info * |
14863 | mips_cpu_info_from_isa (isa) | |
14864 | int isa; | |
14865 | { | |
14866 | int i; | |
14867 | ||
14868 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14869 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14870 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14871 | return (&mips_cpu_info_table[i]); |
14872 | ||
e972090a | 14873 | return NULL; |
e7af610e | 14874 | } |
316f5878 RS |
14875 | \f |
14876 | static void | |
14877 | show (stream, string, col_p, first_p) | |
14878 | FILE *stream; | |
14879 | const char *string; | |
14880 | int *col_p; | |
14881 | int *first_p; | |
14882 | { | |
14883 | if (*first_p) | |
14884 | { | |
14885 | fprintf (stream, "%24s", ""); | |
14886 | *col_p = 24; | |
14887 | } | |
14888 | else | |
14889 | { | |
14890 | fprintf (stream, ", "); | |
14891 | *col_p += 2; | |
14892 | } | |
e7af610e | 14893 | |
316f5878 RS |
14894 | if (*col_p + strlen (string) > 72) |
14895 | { | |
14896 | fprintf (stream, "\n%24s", ""); | |
14897 | *col_p = 24; | |
14898 | } | |
14899 | ||
14900 | fprintf (stream, "%s", string); | |
14901 | *col_p += strlen (string); | |
14902 | ||
14903 | *first_p = 0; | |
14904 | } | |
14905 | ||
14906 | void | |
14907 | md_show_usage (stream) | |
14908 | FILE *stream; | |
e7af610e | 14909 | { |
316f5878 RS |
14910 | int column, first; |
14911 | size_t i; | |
14912 | ||
14913 | fprintf (stream, _("\ | |
14914 | MIPS options:\n\ | |
14915 | -membedded-pic generate embedded position independent code\n\ | |
14916 | -EB generate big endian output\n\ | |
14917 | -EL generate little endian output\n\ | |
14918 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14919 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14920 | implicitly with the gp register [default 8]\n")); | |
14921 | fprintf (stream, _("\ | |
14922 | -mips1 generate MIPS ISA I instructions\n\ | |
14923 | -mips2 generate MIPS ISA II instructions\n\ | |
14924 | -mips3 generate MIPS ISA III instructions\n\ | |
14925 | -mips4 generate MIPS ISA IV instructions\n\ | |
14926 | -mips5 generate MIPS ISA V instructions\n\ | |
14927 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14928 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 RS |
14929 | -mips64 generate MIPS64 ISA instructions\n\ |
14930 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14931 | ||
14932 | first = 1; | |
e7af610e NC |
14933 | |
14934 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14935 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14936 | show (stream, "from-abi", &column, &first); | |
14937 | fputc ('\n', stream); | |
e7af610e | 14938 | |
316f5878 RS |
14939 | fprintf (stream, _("\ |
14940 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14941 | -no-mCPU don't generate code specific to CPU.\n\ | |
14942 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14943 | ||
14944 | first = 1; | |
14945 | ||
14946 | show (stream, "3900", &column, &first); | |
14947 | show (stream, "4010", &column, &first); | |
14948 | show (stream, "4100", &column, &first); | |
14949 | show (stream, "4650", &column, &first); | |
14950 | fputc ('\n', stream); | |
14951 | ||
14952 | fprintf (stream, _("\ | |
14953 | -mips16 generate mips16 instructions\n\ | |
14954 | -no-mips16 do not generate mips16 instructions\n")); | |
14955 | fprintf (stream, _("\ | |
14956 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14957 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14958 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14959 | -O remove unneeded NOPs and swap branches\n\ | |
14960 | -n warn about NOPs generated from macros\n\ | |
14961 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14962 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14963 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14964 | #ifdef OBJ_ELF | |
14965 | fprintf (stream, _("\ | |
14966 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14967 | -non_shared do not generate position independent code\n\ | |
14968 | -xgot assume a 32 bit GOT\n\ | |
14969 | -mabi=ABI create ABI conformant object file for:\n")); | |
14970 | ||
14971 | first = 1; | |
14972 | ||
14973 | show (stream, "32", &column, &first); | |
14974 | show (stream, "o64", &column, &first); | |
14975 | show (stream, "n32", &column, &first); | |
14976 | show (stream, "64", &column, &first); | |
14977 | show (stream, "eabi", &column, &first); | |
14978 | ||
14979 | fputc ('\n', stream); | |
14980 | ||
14981 | fprintf (stream, _("\ | |
14982 | -32 create o32 ABI object file (default)\n\ | |
14983 | -n32 create n32 ABI object file\n\ | |
14984 | -64 create 64 ABI object file\n")); | |
14985 | #endif | |
e7af610e | 14986 | } |
14e777e0 KB |
14987 | |
14988 | enum dwarf2_format | |
14989 | mips_dwarf2_format () | |
14990 | { | |
14991 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14992 | { |
14993 | #ifdef TE_IRIX | |
14994 | return dwarf2_format_64bit_irix; | |
14995 | #else | |
14996 | return dwarf2_format_64bit; | |
14997 | #endif | |
14998 | } | |
14e777e0 KB |
14999 | else |
15000 | return dwarf2_format_32bit; | |
15001 | } |