Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
159 | |
160 | /* True if this instruction is complete. */ | |
161 | unsigned int complete_p : 1; | |
47e39b9d RS |
162 | }; |
163 | ||
a325df1d TS |
164 | /* The ABI to use. */ |
165 | enum mips_abi_level | |
166 | { | |
167 | NO_ABI = 0, | |
168 | O32_ABI, | |
169 | O64_ABI, | |
170 | N32_ABI, | |
171 | N64_ABI, | |
172 | EABI_ABI | |
173 | }; | |
174 | ||
175 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 176 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 177 | |
143d77c5 EC |
178 | /* Whether or not we have code that can call pic code. */ |
179 | int mips_abicalls = FALSE; | |
180 | ||
aa6975fb ILT |
181 | /* Whether or not we have code which can be put into a shared |
182 | library. */ | |
183 | static bfd_boolean mips_in_shared = TRUE; | |
184 | ||
252b5132 RH |
185 | /* This is the set of options which may be modified by the .set |
186 | pseudo-op. We use a struct so that .set push and .set pop are more | |
187 | reliable. */ | |
188 | ||
e972090a NC |
189 | struct mips_set_options |
190 | { | |
252b5132 RH |
191 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
192 | if it has not been initialized. Changed by `.set mipsN', and the | |
193 | -mipsN command line option, and the default CPU. */ | |
194 | int isa; | |
1f25f5d3 CD |
195 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
196 | if they have not been initialized. Changed by `.set <asename>', by | |
197 | command line options, and based on the default architecture. */ | |
198 | int ase_mips3d; | |
deec1734 | 199 | int ase_mdmx; |
e16bfa71 | 200 | int ase_smartmips; |
74cd071d | 201 | int ase_dsp; |
8b082fb1 | 202 | int ase_dspr2; |
ef2e4d86 | 203 | int ase_mt; |
252b5132 RH |
204 | /* Whether we are assembling for the mips16 processor. 0 if we are |
205 | not, 1 if we are, and -1 if the value has not been initialized. | |
206 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
207 | -nomips16 command line options, and the default CPU. */ | |
208 | int mips16; | |
209 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
210 | reorder' and `.set noreorder'. */ | |
211 | int noreorder; | |
741fe287 MR |
212 | /* Non-zero if we should not permit the register designated "assembler |
213 | temporary" to be used in instructions. The value is the register | |
214 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
215 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
216 | unsigned int at; | |
252b5132 RH |
217 | /* Non-zero if we should warn when a macro instruction expands into |
218 | more than one machine instruction. Changed by `.set nomacro' and | |
219 | `.set macro'. */ | |
220 | int warn_about_macros; | |
221 | /* Non-zero if we should not move instructions. Changed by `.set | |
222 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
223 | int nomove; | |
224 | /* Non-zero if we should not optimize branches by moving the target | |
225 | of the branch into the delay slot. Actually, we don't perform | |
226 | this optimization anyhow. Changed by `.set bopt' and `.set | |
227 | nobopt'. */ | |
228 | int nobopt; | |
229 | /* Non-zero if we should not autoextend mips16 instructions. | |
230 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
231 | int noautoextend; | |
a325df1d TS |
232 | /* Restrict general purpose registers and floating point registers |
233 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
234 | is passed but can changed if the assembler code uses .set mipsN. */ | |
235 | int gp32; | |
236 | int fp32; | |
fef14a42 TS |
237 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
238 | command line option, and the default CPU. */ | |
239 | int arch; | |
aed1a261 RS |
240 | /* True if ".set sym32" is in effect. */ |
241 | bfd_boolean sym32; | |
037b32b9 AN |
242 | /* True if floating-point operations are not allowed. Changed by .set |
243 | softfloat or .set hardfloat, by command line options -msoft-float or | |
244 | -mhard-float. The default is false. */ | |
245 | bfd_boolean soft_float; | |
246 | ||
247 | /* True if only single-precision floating-point operations are allowed. | |
248 | Changed by .set singlefloat or .set doublefloat, command-line options | |
249 | -msingle-float or -mdouble-float. The default is false. */ | |
250 | bfd_boolean single_float; | |
252b5132 RH |
251 | }; |
252 | ||
037b32b9 AN |
253 | /* This is the struct we use to hold the current set of options. Note |
254 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
255 | -1 to indicate that they have not been initialized. */ | |
256 | ||
a325df1d | 257 | /* True if -mgp32 was passed. */ |
a8e8e863 | 258 | static int file_mips_gp32 = -1; |
a325df1d TS |
259 | |
260 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 261 | static int file_mips_fp32 = -1; |
a325df1d | 262 | |
037b32b9 AN |
263 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
264 | static int file_mips_soft_float = 0; | |
265 | ||
266 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
267 | static int file_mips_single_float = 0; | |
252b5132 | 268 | |
e972090a NC |
269 | static struct mips_set_options mips_opts = |
270 | { | |
037b32b9 AN |
271 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
272 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
273 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
274 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
275 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
276 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 277 | }; |
252b5132 RH |
278 | |
279 | /* These variables are filled in with the masks of registers used. | |
280 | The object format code reads them and puts them in the appropriate | |
281 | place. */ | |
282 | unsigned long mips_gprmask; | |
283 | unsigned long mips_cprmask[4]; | |
284 | ||
285 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 286 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 287 | |
738f4d98 | 288 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
289 | static int file_ase_mips16; |
290 | ||
3994f87e TS |
291 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
292 | || mips_opts.isa == ISA_MIPS32R2 \ | |
293 | || mips_opts.isa == ISA_MIPS64 \ | |
294 | || mips_opts.isa == ISA_MIPS64R2) | |
295 | ||
b12dd2e4 CF |
296 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
297 | #ifdef TE_IRIX | |
1180b5a4 | 298 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 299 | #else |
1180b5a4 RS |
300 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
301 | because there's no place for any addend, the only acceptable | |
302 | expression is a bare symbol. */ | |
303 | #define MIPS_JALR_HINT_P(EXPR) \ | |
304 | (!HAVE_IN_PLACE_ADDENDS \ | |
305 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
306 | #endif |
307 | ||
1f25f5d3 CD |
308 | /* True if -mips3d was passed or implied by arguments passed on the |
309 | command line (e.g., by -march). */ | |
310 | static int file_ase_mips3d; | |
311 | ||
deec1734 CD |
312 | /* True if -mdmx was passed or implied by arguments passed on the |
313 | command line (e.g., by -march). */ | |
314 | static int file_ase_mdmx; | |
315 | ||
e16bfa71 TS |
316 | /* True if -msmartmips was passed or implied by arguments passed on the |
317 | command line (e.g., by -march). */ | |
318 | static int file_ase_smartmips; | |
319 | ||
ad3fea08 TS |
320 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
321 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 322 | |
74cd071d CF |
323 | /* True if -mdsp was passed or implied by arguments passed on the |
324 | command line (e.g., by -march). */ | |
325 | static int file_ase_dsp; | |
326 | ||
ad3fea08 TS |
327 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
328 | || mips_opts.isa == ISA_MIPS64R2) | |
329 | ||
65263ce3 TS |
330 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
331 | ||
8b082fb1 TS |
332 | /* True if -mdspr2 was passed or implied by arguments passed on the |
333 | command line (e.g., by -march). */ | |
334 | static int file_ase_dspr2; | |
335 | ||
336 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
337 | || mips_opts.isa == ISA_MIPS64R2) | |
338 | ||
ef2e4d86 CF |
339 | /* True if -mmt was passed or implied by arguments passed on the |
340 | command line (e.g., by -march). */ | |
341 | static int file_ase_mt; | |
342 | ||
ad3fea08 TS |
343 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
344 | || mips_opts.isa == ISA_MIPS64R2) | |
345 | ||
ec68c924 | 346 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 347 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 348 | static const char *mips_arch_string; |
ec68c924 EC |
349 | |
350 | /* The argument of the -mtune= flag. The architecture for which we | |
351 | are optimizing. */ | |
352 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 353 | static const char *mips_tune_string; |
ec68c924 | 354 | |
316f5878 | 355 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
356 | static int mips_32bitmode = 0; |
357 | ||
316f5878 RS |
358 | /* True if the given ABI requires 32-bit registers. */ |
359 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
360 | ||
361 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
362 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
363 | ((ABI) == N32_ABI \ | |
364 | || (ABI) == N64_ABI \ | |
316f5878 RS |
365 | || (ABI) == O64_ABI) |
366 | ||
ad3fea08 | 367 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
368 | #define ISA_HAS_64BIT_REGS(ISA) \ |
369 | ((ISA) == ISA_MIPS3 \ | |
370 | || (ISA) == ISA_MIPS4 \ | |
371 | || (ISA) == ISA_MIPS5 \ | |
372 | || (ISA) == ISA_MIPS64 \ | |
373 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 374 | |
ad3fea08 TS |
375 | /* Return true if ISA supports 64 bit wide float registers. */ |
376 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
377 | ((ISA) == ISA_MIPS3 \ | |
378 | || (ISA) == ISA_MIPS4 \ | |
379 | || (ISA) == ISA_MIPS5 \ | |
380 | || (ISA) == ISA_MIPS32R2 \ | |
381 | || (ISA) == ISA_MIPS64 \ | |
382 | || (ISA) == ISA_MIPS64R2) | |
383 | ||
af7ee8bf CD |
384 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
385 | instructions. */ | |
707bfff6 TS |
386 | #define ISA_HAS_DROR(ISA) \ |
387 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
388 | |
389 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
390 | instructions. */ | |
707bfff6 TS |
391 | #define ISA_HAS_ROR(ISA) \ |
392 | ((ISA) == ISA_MIPS32R2 \ | |
393 | || (ISA) == ISA_MIPS64R2 \ | |
394 | || mips_opts.ase_smartmips) | |
395 | ||
7455baf8 TS |
396 | /* Return true if ISA supports single-precision floats in odd registers. */ |
397 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
398 | ((ISA) == ISA_MIPS32 \ | |
399 | || (ISA) == ISA_MIPS32R2 \ | |
400 | || (ISA) == ISA_MIPS64 \ | |
401 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 402 | |
ad3fea08 TS |
403 | /* Return true if ISA supports move to/from high part of a 64-bit |
404 | floating-point register. */ | |
405 | #define ISA_HAS_MXHC1(ISA) \ | |
406 | ((ISA) == ISA_MIPS32R2 \ | |
407 | || (ISA) == ISA_MIPS64R2) | |
408 | ||
e013f690 | 409 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 410 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 411 | |
e013f690 | 412 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 413 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 414 | |
ad3fea08 TS |
415 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
416 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 417 | |
316f5878 | 418 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 419 | |
316f5878 | 420 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 421 | |
3b91255e RS |
422 | /* True if relocations are stored in-place. */ |
423 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
424 | ||
aed1a261 RS |
425 | /* The ABI-derived address size. */ |
426 | #define HAVE_64BIT_ADDRESSES \ | |
427 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
428 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 429 | |
aed1a261 RS |
430 | /* The size of symbolic constants (i.e., expressions of the form |
431 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
432 | #define HAVE_32BIT_SYMBOLS \ | |
433 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
434 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 435 | |
b7c7d6c1 TS |
436 | /* Addresses are loaded in different ways, depending on the address size |
437 | in use. The n32 ABI Documentation also mandates the use of additions | |
438 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 439 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 440 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
441 | |
442 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 443 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
444 | |
445 | #define ADDRESS_LOAD_INSN \ | |
446 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
447 | ||
448 | #define ADDRESS_STORE_INSN \ | |
449 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
450 | ||
a4672219 | 451 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
452 | #define CPU_HAS_MIPS16(cpu) \ |
453 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
454 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 455 | |
60b63b72 RS |
456 | /* True if CPU has a dror instruction. */ |
457 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
458 | ||
459 | /* True if CPU has a ror instruction. */ | |
460 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
461 | ||
dd3cbb7e NC |
462 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
463 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
464 | ||
b19e8a9b AN |
465 | /* True if CPU does not implement the all the coprocessor insns. For these |
466 | CPUs only those COP insns are accepted that are explicitly marked to be | |
467 | available on the CPU. ISA membership for COP insns is ignored. */ | |
468 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
469 | ||
c8978940 CD |
470 | /* True if mflo and mfhi can be immediately followed by instructions |
471 | which write to the HI and LO registers. | |
472 | ||
473 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
474 | (at least) two instructions between the reads of HI/LO and | |
475 | instructions which write them, and later ISAs do not. Contradicting | |
476 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
477 | the UM for the NEC Vr5000) document needing the instructions between | |
478 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
479 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
480 | earlier-ISA CPUs for which CPU documentation declares that the | |
481 | instructions are really interlocked. */ | |
482 | #define hilo_interlocks \ | |
483 | (mips_opts.isa == ISA_MIPS32 \ | |
484 | || mips_opts.isa == ISA_MIPS32R2 \ | |
485 | || mips_opts.isa == ISA_MIPS64 \ | |
486 | || mips_opts.isa == ISA_MIPS64R2 \ | |
487 | || mips_opts.arch == CPU_R4010 \ | |
488 | || mips_opts.arch == CPU_R10000 \ | |
489 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
490 | || mips_opts.arch == CPU_R14000 \ |
491 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 492 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
493 | || mips_opts.arch == CPU_VR5500 \ |
494 | ) | |
252b5132 RH |
495 | |
496 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
497 | from the GPRs after they are loaded from memory, and thus does not |
498 | require nops to be inserted. This applies to instructions marked | |
499 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
500 | level I. */ | |
252b5132 | 501 | #define gpr_interlocks \ |
e7af610e | 502 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 503 | || mips_opts.arch == CPU_R3900) |
252b5132 | 504 | |
81912461 ILT |
505 | /* Whether the processor uses hardware interlocks to avoid delays |
506 | required by coprocessor instructions, and thus does not require | |
507 | nops to be inserted. This applies to instructions marked | |
508 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
509 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
510 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
511 | levels I, II, and III. */ | |
bdaaa2e1 | 512 | /* Itbl support may require additional care here. */ |
81912461 ILT |
513 | #define cop_interlocks \ |
514 | ((mips_opts.isa != ISA_MIPS1 \ | |
515 | && mips_opts.isa != ISA_MIPS2 \ | |
516 | && mips_opts.isa != ISA_MIPS3) \ | |
517 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
518 | ) |
519 | ||
520 | /* Whether the processor uses hardware interlocks to protect reads | |
521 | from coprocessor registers after they are loaded from memory, and | |
522 | thus does not require nops to be inserted. This applies to | |
523 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
524 | requires at MIPS ISA level I. */ | |
525 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 526 | |
6b76fefe CM |
527 | /* Is this a mfhi or mflo instruction? */ |
528 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
529 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
530 | ||
531 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
532 | or writing the condition code is only possible on the coprocessors and | |
533 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 534 | condition-code flags. */ |
b19e8a9b AN |
535 | #define COP_INSN(PINFO) \ |
536 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
537 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
538 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 539 | |
252b5132 RH |
540 | /* MIPS PIC level. */ |
541 | ||
a161fe53 | 542 | enum mips_pic_level mips_pic; |
252b5132 | 543 | |
c9914766 | 544 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 545 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 546 | static int mips_big_got = 0; |
252b5132 RH |
547 | |
548 | /* 1 if trap instructions should used for overflow rather than break | |
549 | instructions. */ | |
c9914766 | 550 | static int mips_trap = 0; |
252b5132 | 551 | |
119d663a | 552 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 553 | by assembling two single width halves into two single width floating |
119d663a NC |
554 | point registers which just happen to alias the double width destination |
555 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 556 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
557 | automatically at assemble time. */ |
558 | static int mips_disable_float_construction; | |
559 | ||
252b5132 RH |
560 | /* Non-zero if any .set noreorder directives were used. */ |
561 | ||
562 | static int mips_any_noreorder; | |
563 | ||
6b76fefe CM |
564 | /* Non-zero if nops should be inserted when the register referenced in |
565 | an mfhi/mflo instruction is read in the next two instructions. */ | |
566 | static int mips_7000_hilo_fix; | |
567 | ||
02ffd3e4 | 568 | /* The size of objects in the small data section. */ |
156c2f8b | 569 | static unsigned int g_switch_value = 8; |
252b5132 RH |
570 | /* Whether the -G option was used. */ |
571 | static int g_switch_seen = 0; | |
572 | ||
573 | #define N_RMASK 0xc4 | |
574 | #define N_VFP 0xd4 | |
575 | ||
576 | /* If we can determine in advance that GP optimization won't be | |
577 | possible, we can skip the relaxation stuff that tries to produce | |
578 | GP-relative references. This makes delay slot optimization work | |
579 | better. | |
580 | ||
581 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
582 | gcc output. It needs to guess right for gcc, otherwise gcc |
583 | will put what it thinks is a GP-relative instruction in a branch | |
584 | delay slot. | |
252b5132 RH |
585 | |
586 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
587 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 588 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
589 | |
590 | /* handle of the OPCODE hash table */ | |
591 | static struct hash_control *op_hash = NULL; | |
592 | ||
593 | /* The opcode hash table we use for the mips16. */ | |
594 | static struct hash_control *mips16_op_hash = NULL; | |
595 | ||
596 | /* This array holds the chars that always start a comment. If the | |
597 | pre-processor is disabled, these aren't very useful */ | |
598 | const char comment_chars[] = "#"; | |
599 | ||
600 | /* This array holds the chars that only start a comment at the beginning of | |
601 | a line. If the line seems to have the form '# 123 filename' | |
602 | .line and .file directives will appear in the pre-processed output */ | |
603 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
604 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 605 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
606 | /* Also note that C style comments are always supported. */ |
607 | const char line_comment_chars[] = "#"; | |
608 | ||
bdaaa2e1 | 609 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 610 | const char line_separator_chars[] = ";"; |
252b5132 RH |
611 | |
612 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
613 | const char EXP_CHARS[] = "eE"; | |
614 | ||
615 | /* Chars that mean this number is a floating point constant */ | |
616 | /* As in 0f12.456 */ | |
617 | /* or 0d1.2345e12 */ | |
618 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
619 | ||
620 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
621 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
622 | but nothing is ideal around here. | |
623 | */ | |
624 | ||
625 | static char *insn_error; | |
626 | ||
627 | static int auto_align = 1; | |
628 | ||
629 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
630 | offset in the stack frame from which to restore the $gp register. | |
631 | This is set by the .cprestore pseudo-op, and saved in this | |
632 | variable. */ | |
633 | static offsetT mips_cprestore_offset = -1; | |
634 | ||
67c1ffbe | 635 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 636 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 637 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
638 | static offsetT mips_cpreturn_offset = -1; |
639 | static int mips_cpreturn_register = -1; | |
640 | static int mips_gp_register = GP; | |
def2e0dd | 641 | static int mips_gprel_offset = 0; |
6478892d | 642 | |
7a621144 DJ |
643 | /* Whether mips_cprestore_offset has been set in the current function |
644 | (or whether it has already been warned about, if not). */ | |
645 | static int mips_cprestore_valid = 0; | |
646 | ||
252b5132 RH |
647 | /* This is the register which holds the stack frame, as set by the |
648 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
649 | static int mips_frame_reg = SP; | |
650 | ||
7a621144 DJ |
651 | /* Whether mips_frame_reg has been set in the current function |
652 | (or whether it has already been warned about, if not). */ | |
653 | static int mips_frame_reg_valid = 0; | |
654 | ||
252b5132 RH |
655 | /* To output NOP instructions correctly, we need to keep information |
656 | about the previous two instructions. */ | |
657 | ||
658 | /* Whether we are optimizing. The default value of 2 means to remove | |
659 | unneeded NOPs and swap branch instructions when possible. A value | |
660 | of 1 means to not swap branches. A value of 0 means to always | |
661 | insert NOPs. */ | |
662 | static int mips_optimize = 2; | |
663 | ||
664 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
665 | equivalent to seeing no -g option at all. */ | |
666 | static int mips_debug = 0; | |
667 | ||
7d8e00cf RS |
668 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
669 | #define MAX_VR4130_NOPS 4 | |
670 | ||
671 | /* The maximum number of NOPs needed to fill delay slots. */ | |
672 | #define MAX_DELAY_NOPS 2 | |
673 | ||
674 | /* The maximum number of NOPs needed for any purpose. */ | |
675 | #define MAX_NOPS 4 | |
71400594 RS |
676 | |
677 | /* A list of previous instructions, with index 0 being the most recent. | |
678 | We need to look back MAX_NOPS instructions when filling delay slots | |
679 | or working around processor errata. We need to look back one | |
680 | instruction further if we're thinking about using history[0] to | |
681 | fill a branch delay slot. */ | |
682 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 683 | |
1e915849 RS |
684 | /* Nop instructions used by emit_nop. */ |
685 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
686 | ||
687 | /* The appropriate nop for the current mode. */ | |
688 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 689 | |
252b5132 RH |
690 | /* If this is set, it points to a frag holding nop instructions which |
691 | were inserted before the start of a noreorder section. If those | |
692 | nops turn out to be unnecessary, the size of the frag can be | |
693 | decreased. */ | |
694 | static fragS *prev_nop_frag; | |
695 | ||
696 | /* The number of nop instructions we created in prev_nop_frag. */ | |
697 | static int prev_nop_frag_holds; | |
698 | ||
699 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 700 | prev_nop_frag. */ |
252b5132 RH |
701 | static int prev_nop_frag_required; |
702 | ||
703 | /* The number of instructions we've seen since prev_nop_frag. */ | |
704 | static int prev_nop_frag_since; | |
705 | ||
706 | /* For ECOFF and ELF, relocations against symbols are done in two | |
707 | parts, with a HI relocation and a LO relocation. Each relocation | |
708 | has only 16 bits of space to store an addend. This means that in | |
709 | order for the linker to handle carries correctly, it must be able | |
710 | to locate both the HI and the LO relocation. This means that the | |
711 | relocations must appear in order in the relocation table. | |
712 | ||
713 | In order to implement this, we keep track of each unmatched HI | |
714 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 715 | corresponding LO relocation. */ |
252b5132 | 716 | |
e972090a NC |
717 | struct mips_hi_fixup |
718 | { | |
252b5132 RH |
719 | /* Next HI fixup. */ |
720 | struct mips_hi_fixup *next; | |
721 | /* This fixup. */ | |
722 | fixS *fixp; | |
723 | /* The section this fixup is in. */ | |
724 | segT seg; | |
725 | }; | |
726 | ||
727 | /* The list of unmatched HI relocs. */ | |
728 | ||
729 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
730 | ||
64bdfcaf RS |
731 | /* The frag containing the last explicit relocation operator. |
732 | Null if explicit relocations have not been used. */ | |
733 | ||
734 | static fragS *prev_reloc_op_frag; | |
735 | ||
252b5132 RH |
736 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
737 | ||
738 | #define X ILLEGAL_REG | |
e972090a NC |
739 | static const int mips32_to_16_reg_map[] = |
740 | { | |
252b5132 RH |
741 | X, X, 2, 3, 4, 5, 6, 7, |
742 | X, X, X, X, X, X, X, X, | |
743 | 0, 1, X, X, X, X, X, X, | |
744 | X, X, X, X, X, X, X, X | |
745 | }; | |
746 | #undef X | |
747 | ||
748 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
749 | ||
e972090a NC |
750 | static const unsigned int mips16_to_32_reg_map[] = |
751 | { | |
252b5132 RH |
752 | 16, 17, 2, 3, 4, 5, 6, 7 |
753 | }; | |
60b63b72 | 754 | |
71400594 RS |
755 | /* Classifies the kind of instructions we're interested in when |
756 | implementing -mfix-vr4120. */ | |
c67a084a NC |
757 | enum fix_vr4120_class |
758 | { | |
71400594 RS |
759 | FIX_VR4120_MACC, |
760 | FIX_VR4120_DMACC, | |
761 | FIX_VR4120_MULT, | |
762 | FIX_VR4120_DMULT, | |
763 | FIX_VR4120_DIV, | |
764 | FIX_VR4120_MTHILO, | |
765 | NUM_FIX_VR4120_CLASSES | |
766 | }; | |
767 | ||
c67a084a NC |
768 | /* ...likewise -mfix-loongson2f-jump. */ |
769 | static bfd_boolean mips_fix_loongson2f_jump; | |
770 | ||
771 | /* ...likewise -mfix-loongson2f-nop. */ | |
772 | static bfd_boolean mips_fix_loongson2f_nop; | |
773 | ||
774 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
775 | static bfd_boolean mips_fix_loongson2f; | |
776 | ||
71400594 RS |
777 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
778 | there must be at least one other instruction between an instruction | |
779 | of type X and an instruction of type Y. */ | |
780 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
781 | ||
782 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 783 | static int mips_fix_vr4120; |
4a6a3df4 | 784 | |
7d8e00cf RS |
785 | /* ...likewise -mfix-vr4130. */ |
786 | static int mips_fix_vr4130; | |
787 | ||
6a32d874 CM |
788 | /* ...likewise -mfix-24k. */ |
789 | static int mips_fix_24k; | |
790 | ||
d954098f DD |
791 | /* ...likewise -mfix-cn63xxp1 */ |
792 | static bfd_boolean mips_fix_cn63xxp1; | |
793 | ||
4a6a3df4 AO |
794 | /* We don't relax branches by default, since this causes us to expand |
795 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
796 | fail to compute the offset before expanding the macro to the most | |
797 | efficient expansion. */ | |
798 | ||
799 | static int mips_relax_branch; | |
252b5132 | 800 | \f |
4d7206a2 RS |
801 | /* The expansion of many macros depends on the type of symbol that |
802 | they refer to. For example, when generating position-dependent code, | |
803 | a macro that refers to a symbol may have two different expansions, | |
804 | one which uses GP-relative addresses and one which uses absolute | |
805 | addresses. When generating SVR4-style PIC, a macro may have | |
806 | different expansions for local and global symbols. | |
807 | ||
808 | We handle these situations by generating both sequences and putting | |
809 | them in variant frags. In position-dependent code, the first sequence | |
810 | will be the GP-relative one and the second sequence will be the | |
811 | absolute one. In SVR4 PIC, the first sequence will be for global | |
812 | symbols and the second will be for local symbols. | |
813 | ||
584892a6 RS |
814 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
815 | SECOND are the lengths of the two sequences in bytes. These fields | |
816 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
817 | the subtype has the following flags: | |
4d7206a2 | 818 | |
584892a6 RS |
819 | RELAX_USE_SECOND |
820 | Set if it has been decided that we should use the second | |
821 | sequence instead of the first. | |
822 | ||
823 | RELAX_SECOND_LONGER | |
824 | Set in the first variant frag if the macro's second implementation | |
825 | is longer than its first. This refers to the macro as a whole, | |
826 | not an individual relaxation. | |
827 | ||
828 | RELAX_NOMACRO | |
829 | Set in the first variant frag if the macro appeared in a .set nomacro | |
830 | block and if one alternative requires a warning but the other does not. | |
831 | ||
832 | RELAX_DELAY_SLOT | |
833 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
834 | delay slot. | |
4d7206a2 RS |
835 | |
836 | The frag's "opcode" points to the first fixup for relaxable code. | |
837 | ||
838 | Relaxable macros are generated using a sequence such as: | |
839 | ||
840 | relax_start (SYMBOL); | |
841 | ... generate first expansion ... | |
842 | relax_switch (); | |
843 | ... generate second expansion ... | |
844 | relax_end (); | |
845 | ||
846 | The code and fixups for the unwanted alternative are discarded | |
847 | by md_convert_frag. */ | |
584892a6 | 848 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 849 | |
584892a6 RS |
850 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
851 | #define RELAX_SECOND(X) ((X) & 0xff) | |
852 | #define RELAX_USE_SECOND 0x10000 | |
853 | #define RELAX_SECOND_LONGER 0x20000 | |
854 | #define RELAX_NOMACRO 0x40000 | |
855 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 856 | |
4a6a3df4 AO |
857 | /* Branch without likely bit. If label is out of range, we turn: |
858 | ||
859 | beq reg1, reg2, label | |
860 | delay slot | |
861 | ||
862 | into | |
863 | ||
864 | bne reg1, reg2, 0f | |
865 | nop | |
866 | j label | |
867 | 0: delay slot | |
868 | ||
869 | with the following opcode replacements: | |
870 | ||
871 | beq <-> bne | |
872 | blez <-> bgtz | |
873 | bltz <-> bgez | |
874 | bc1f <-> bc1t | |
875 | ||
876 | bltzal <-> bgezal (with jal label instead of j label) | |
877 | ||
878 | Even though keeping the delay slot instruction in the delay slot of | |
879 | the branch would be more efficient, it would be very tricky to do | |
880 | correctly, because we'd have to introduce a variable frag *after* | |
881 | the delay slot instruction, and expand that instead. Let's do it | |
882 | the easy way for now, even if the branch-not-taken case now costs | |
883 | one additional instruction. Out-of-range branches are not supposed | |
884 | to be common, anyway. | |
885 | ||
886 | Branch likely. If label is out of range, we turn: | |
887 | ||
888 | beql reg1, reg2, label | |
889 | delay slot (annulled if branch not taken) | |
890 | ||
891 | into | |
892 | ||
893 | beql reg1, reg2, 1f | |
894 | nop | |
895 | beql $0, $0, 2f | |
896 | nop | |
897 | 1: j[al] label | |
898 | delay slot (executed only if branch taken) | |
899 | 2: | |
900 | ||
901 | It would be possible to generate a shorter sequence by losing the | |
902 | likely bit, generating something like: | |
b34976b6 | 903 | |
4a6a3df4 AO |
904 | bne reg1, reg2, 0f |
905 | nop | |
906 | j[al] label | |
907 | delay slot (executed only if branch taken) | |
908 | 0: | |
909 | ||
910 | beql -> bne | |
911 | bnel -> beq | |
912 | blezl -> bgtz | |
913 | bgtzl -> blez | |
914 | bltzl -> bgez | |
915 | bgezl -> bltz | |
916 | bc1fl -> bc1t | |
917 | bc1tl -> bc1f | |
918 | ||
919 | bltzall -> bgezal (with jal label instead of j label) | |
920 | bgezall -> bltzal (ditto) | |
921 | ||
922 | ||
923 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
924 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
925 | ((relax_substateT) \ | |
926 | (0xc0000000 \ | |
927 | | ((at) & 0x1f) \ | |
928 | | ((toofar) ? 0x20 : 0) \ | |
929 | | ((link) ? 0x40 : 0) \ | |
930 | | ((likely) ? 0x80 : 0) \ | |
931 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 932 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
933 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
934 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
935 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
936 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
937 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 938 | |
252b5132 RH |
939 | /* For mips16 code, we use an entirely different form of relaxation. |
940 | mips16 supports two versions of most instructions which take | |
941 | immediate values: a small one which takes some small value, and a | |
942 | larger one which takes a 16 bit value. Since branches also follow | |
943 | this pattern, relaxing these values is required. | |
944 | ||
945 | We can assemble both mips16 and normal MIPS code in a single | |
946 | object. Therefore, we need to support this type of relaxation at | |
947 | the same time that we support the relaxation described above. We | |
948 | use the high bit of the subtype field to distinguish these cases. | |
949 | ||
950 | The information we store for this type of relaxation is the | |
951 | argument code found in the opcode file for this relocation, whether | |
952 | the user explicitly requested a small or extended form, and whether | |
953 | the relocation is in a jump or jal delay slot. That tells us the | |
954 | size of the value, and how it should be stored. We also store | |
955 | whether the fragment is considered to be extended or not. We also | |
956 | store whether this is known to be a branch to a different section, | |
957 | whether we have tried to relax this frag yet, and whether we have | |
958 | ever extended a PC relative fragment because of a shift count. */ | |
959 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
960 | (0x80000000 \ | |
961 | | ((type) & 0xff) \ | |
962 | | ((small) ? 0x100 : 0) \ | |
963 | | ((ext) ? 0x200 : 0) \ | |
964 | | ((dslot) ? 0x400 : 0) \ | |
965 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 966 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
967 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
968 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
969 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
970 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
971 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
972 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
973 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
974 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
975 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
976 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
977 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
978 | |
979 | /* Is the given value a sign-extended 32-bit value? */ | |
980 | #define IS_SEXT_32BIT_NUM(x) \ | |
981 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
982 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
983 | ||
984 | /* Is the given value a sign-extended 16-bit value? */ | |
985 | #define IS_SEXT_16BIT_NUM(x) \ | |
986 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
987 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
988 | ||
2051e8c4 MR |
989 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
990 | #define IS_ZEXT_32BIT_NUM(x) \ | |
991 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
992 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
993 | ||
bf12938e RS |
994 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
995 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
996 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
997 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
998 | | (((VALUE) & (MASK)) << (SHIFT))) | |
999 | ||
1000 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1001 | SHIFT places. */ | |
1002 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1003 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1004 | ||
1005 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1006 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1007 | ||
1008 | include/opcode/mips.h specifies operand fields using the macros | |
1009 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1010 | with "MIPS16OP" instead of "OP". */ | |
1011 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1012 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1013 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1014 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1015 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1016 | ||
1017 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1018 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1019 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1020 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1021 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1022 | MIPS16OP_MASK_##FIELD, \ | |
1023 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1024 | \f |
1025 | /* Global variables used when generating relaxable macros. See the | |
1026 | comment above RELAX_ENCODE for more details about how relaxation | |
1027 | is used. */ | |
1028 | static struct { | |
1029 | /* 0 if we're not emitting a relaxable macro. | |
1030 | 1 if we're emitting the first of the two relaxation alternatives. | |
1031 | 2 if we're emitting the second alternative. */ | |
1032 | int sequence; | |
1033 | ||
1034 | /* The first relaxable fixup in the current frag. (In other words, | |
1035 | the first fixup that refers to relaxable code.) */ | |
1036 | fixS *first_fixup; | |
1037 | ||
1038 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1039 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1040 | unsigned int sizes[2]; | |
1041 | ||
1042 | /* The symbol on which the choice of sequence depends. */ | |
1043 | symbolS *symbol; | |
1044 | } mips_relax; | |
252b5132 | 1045 | \f |
584892a6 RS |
1046 | /* Global variables used to decide whether a macro needs a warning. */ |
1047 | static struct { | |
1048 | /* True if the macro is in a branch delay slot. */ | |
1049 | bfd_boolean delay_slot_p; | |
1050 | ||
1051 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1052 | in bytes and sizes[1] is the length of the second alternative. | |
1053 | For non-relaxable macros, both elements give the length of the | |
1054 | macro in bytes. */ | |
1055 | unsigned int sizes[2]; | |
1056 | ||
1057 | /* The first variant frag for this macro. */ | |
1058 | fragS *first_frag; | |
1059 | } mips_macro_warning; | |
1060 | \f | |
252b5132 RH |
1061 | /* Prototypes for static functions. */ |
1062 | ||
17a2f251 | 1063 | #define internalError() \ |
252b5132 | 1064 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1065 | |
1066 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1067 | ||
b34976b6 | 1068 | static void append_insn |
c67a084a | 1069 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1070 | static void mips_no_prev_insn (void); |
c67a084a | 1071 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1072 | static void mips16_macro_build |
03ea81db | 1073 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1074 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1075 | static void macro_start (void); |
1076 | static void macro_end (void); | |
17a2f251 TS |
1077 | static void macro (struct mips_cl_insn * ip); |
1078 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1079 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1080 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1081 | static void mips16_immed |
17a2f251 TS |
1082 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1083 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1084 | static size_t my_getSmallExpression |
17a2f251 TS |
1085 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1086 | static void my_getExpression (expressionS *, char *); | |
1087 | static void s_align (int); | |
1088 | static void s_change_sec (int); | |
1089 | static void s_change_section (int); | |
1090 | static void s_cons (int); | |
1091 | static void s_float_cons (int); | |
1092 | static void s_mips_globl (int); | |
1093 | static void s_option (int); | |
1094 | static void s_mipsset (int); | |
1095 | static void s_abicalls (int); | |
1096 | static void s_cpload (int); | |
1097 | static void s_cpsetup (int); | |
1098 | static void s_cplocal (int); | |
1099 | static void s_cprestore (int); | |
1100 | static void s_cpreturn (int); | |
741d6ea8 JM |
1101 | static void s_dtprelword (int); |
1102 | static void s_dtpreldword (int); | |
17a2f251 TS |
1103 | static void s_gpvalue (int); |
1104 | static void s_gpword (int); | |
1105 | static void s_gpdword (int); | |
1106 | static void s_cpadd (int); | |
1107 | static void s_insn (int); | |
1108 | static void md_obj_begin (void); | |
1109 | static void md_obj_end (void); | |
1110 | static void s_mips_ent (int); | |
1111 | static void s_mips_end (int); | |
1112 | static void s_mips_frame (int); | |
1113 | static void s_mips_mask (int reg_type); | |
1114 | static void s_mips_stab (int); | |
1115 | static void s_mips_weakext (int); | |
1116 | static void s_mips_file (int); | |
1117 | static void s_mips_loc (int); | |
1118 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1119 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1120 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1121 | |
1122 | /* Table and functions used to map between CPU/ISA names, and | |
1123 | ISA levels, and CPU numbers. */ | |
1124 | ||
e972090a NC |
1125 | struct mips_cpu_info |
1126 | { | |
e7af610e | 1127 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1128 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1129 | int isa; /* ISA level. */ |
1130 | int cpu; /* CPU number (default CPU if ISA). */ | |
1131 | }; | |
1132 | ||
ad3fea08 TS |
1133 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1134 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1135 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1136 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1137 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1138 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1139 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1140 | |
17a2f251 TS |
1141 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1142 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1143 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1144 | \f |
1145 | /* Pseudo-op table. | |
1146 | ||
1147 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1148 | should be defined here, but are currently unsupported: .alias, | |
1149 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1150 | ||
1151 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1152 | specific to the type of debugging information being generated, and | |
1153 | should be defined by the object format: .aent, .begin, .bend, | |
1154 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1155 | .vreg. | |
1156 | ||
1157 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1158 | not MIPS CPU specific, but are also not specific to the object file | |
1159 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1160 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1161 | |
e972090a NC |
1162 | static const pseudo_typeS mips_pseudo_table[] = |
1163 | { | |
beae10d5 | 1164 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1165 | {"option", s_option, 0}, |
1166 | {"set", s_mipsset, 0}, | |
1167 | {"rdata", s_change_sec, 'r'}, | |
1168 | {"sdata", s_change_sec, 's'}, | |
1169 | {"livereg", s_ignore, 0}, | |
1170 | {"abicalls", s_abicalls, 0}, | |
1171 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1172 | {"cpsetup", s_cpsetup, 0}, |
1173 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1174 | {"cprestore", s_cprestore, 0}, |
6478892d | 1175 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1176 | {"dtprelword", s_dtprelword, 0}, |
1177 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1178 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1179 | {"gpword", s_gpword, 0}, |
10181a0d | 1180 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1181 | {"cpadd", s_cpadd, 0}, |
1182 | {"insn", s_insn, 0}, | |
1183 | ||
beae10d5 | 1184 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1185 | chips. */ |
38a57ae7 | 1186 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1187 | {"bss", s_change_sec, 'b'}, |
1188 | {"err", s_err, 0}, | |
1189 | {"half", s_cons, 1}, | |
1190 | {"dword", s_cons, 3}, | |
1191 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1192 | {"origin", s_org, 0}, |
1193 | {"repeat", s_rept, 0}, | |
252b5132 | 1194 | |
998b3c36 MR |
1195 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1196 | {"sbss", s_change_sec, 'B'}, | |
1197 | ||
beae10d5 | 1198 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1199 | here for one reason or another. */ |
1200 | {"align", s_align, 0}, | |
1201 | {"byte", s_cons, 0}, | |
1202 | {"data", s_change_sec, 'd'}, | |
1203 | {"double", s_float_cons, 'd'}, | |
1204 | {"float", s_float_cons, 'f'}, | |
1205 | {"globl", s_mips_globl, 0}, | |
1206 | {"global", s_mips_globl, 0}, | |
1207 | {"hword", s_cons, 1}, | |
1208 | {"int", s_cons, 2}, | |
1209 | {"long", s_cons, 2}, | |
1210 | {"octa", s_cons, 4}, | |
1211 | {"quad", s_cons, 3}, | |
cca86cc8 | 1212 | {"section", s_change_section, 0}, |
252b5132 RH |
1213 | {"short", s_cons, 1}, |
1214 | {"single", s_float_cons, 'f'}, | |
1215 | {"stabn", s_mips_stab, 'n'}, | |
1216 | {"text", s_change_sec, 't'}, | |
1217 | {"word", s_cons, 2}, | |
add56521 | 1218 | |
add56521 | 1219 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1220 | |
43841e91 | 1221 | { NULL, NULL, 0 }, |
252b5132 RH |
1222 | }; |
1223 | ||
e972090a NC |
1224 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1225 | { | |
beae10d5 KH |
1226 | /* These pseudo-ops should be defined by the object file format. |
1227 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1228 | {"aent", s_mips_ent, 1}, |
1229 | {"bgnb", s_ignore, 0}, | |
1230 | {"end", s_mips_end, 0}, | |
1231 | {"endb", s_ignore, 0}, | |
1232 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1233 | {"file", s_mips_file, 0}, |
252b5132 RH |
1234 | {"fmask", s_mips_mask, 'F'}, |
1235 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1236 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1237 | {"mask", s_mips_mask, 'R'}, |
1238 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1239 | { NULL, NULL, 0 }, |
252b5132 RH |
1240 | }; |
1241 | ||
3ae8dd8d MR |
1242 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1243 | purpose of the `.dc.a' internal pseudo-op. */ | |
1244 | ||
1245 | int | |
1246 | mips_address_bytes (void) | |
1247 | { | |
1248 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1249 | } | |
1250 | ||
17a2f251 | 1251 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1252 | |
1253 | void | |
17a2f251 | 1254 | mips_pop_insert (void) |
252b5132 RH |
1255 | { |
1256 | pop_insert (mips_pseudo_table); | |
1257 | if (! ECOFF_DEBUGGING) | |
1258 | pop_insert (mips_nonecoff_pseudo_table); | |
1259 | } | |
1260 | \f | |
1261 | /* Symbols labelling the current insn. */ | |
1262 | ||
e972090a NC |
1263 | struct insn_label_list |
1264 | { | |
252b5132 RH |
1265 | struct insn_label_list *next; |
1266 | symbolS *label; | |
1267 | }; | |
1268 | ||
252b5132 | 1269 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1270 | #define label_list tc_segment_info_data.labels |
252b5132 | 1271 | |
17a2f251 | 1272 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1273 | |
1274 | static inline void | |
17a2f251 | 1275 | mips_clear_insn_labels (void) |
252b5132 RH |
1276 | { |
1277 | register struct insn_label_list **pl; | |
a8dbcb85 | 1278 | segment_info_type *si; |
252b5132 | 1279 | |
a8dbcb85 TS |
1280 | if (now_seg) |
1281 | { | |
1282 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1283 | ; | |
1284 | ||
1285 | si = seg_info (now_seg); | |
1286 | *pl = si->label_list; | |
1287 | si->label_list = NULL; | |
1288 | } | |
252b5132 | 1289 | } |
a8dbcb85 | 1290 | |
252b5132 RH |
1291 | \f |
1292 | static char *expr_end; | |
1293 | ||
1294 | /* Expressions which appear in instructions. These are set by | |
1295 | mips_ip. */ | |
1296 | ||
1297 | static expressionS imm_expr; | |
5f74bc13 | 1298 | static expressionS imm2_expr; |
252b5132 RH |
1299 | static expressionS offset_expr; |
1300 | ||
1301 | /* Relocs associated with imm_expr and offset_expr. */ | |
1302 | ||
f6688943 TS |
1303 | static bfd_reloc_code_real_type imm_reloc[3] |
1304 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1305 | static bfd_reloc_code_real_type offset_reloc[3] | |
1306 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1307 | |
252b5132 RH |
1308 | /* These are set by mips16_ip if an explicit extension is used. */ |
1309 | ||
b34976b6 | 1310 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1311 | |
7ed4a06a | 1312 | #ifdef OBJ_ELF |
ecb4347a DJ |
1313 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1314 | ECOFF debugging. */ | |
252b5132 RH |
1315 | |
1316 | static segT pdr_seg; | |
7ed4a06a | 1317 | #endif |
252b5132 | 1318 | |
e013f690 TS |
1319 | /* The default target format to use. */ |
1320 | ||
aeffff67 RS |
1321 | #if defined (TE_FreeBSD) |
1322 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1323 | #elif defined (TE_TMIPS) | |
1324 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1325 | #else | |
1326 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1327 | #endif | |
1328 | ||
e013f690 | 1329 | const char * |
17a2f251 | 1330 | mips_target_format (void) |
e013f690 TS |
1331 | { |
1332 | switch (OUTPUT_FLAVOR) | |
1333 | { | |
e013f690 TS |
1334 | case bfd_target_ecoff_flavour: |
1335 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1336 | case bfd_target_coff_flavour: | |
1337 | return "pe-mips"; | |
1338 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1339 | #ifdef TE_VXWORKS |
1340 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1341 | return (target_big_endian | |
1342 | ? "elf32-bigmips-vxworks" | |
1343 | : "elf32-littlemips-vxworks"); | |
1344 | #endif | |
e013f690 | 1345 | return (target_big_endian |
cfe86eaa | 1346 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1347 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1348 | : (HAVE_NEWABI |
aeffff67 RS |
1349 | ? ELF_TARGET ("elf32-n", "big") |
1350 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1351 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1352 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1353 | : (HAVE_NEWABI |
aeffff67 RS |
1354 | ? ELF_TARGET ("elf32-n", "little") |
1355 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1356 | default: |
1357 | abort (); | |
1358 | return NULL; | |
1359 | } | |
1360 | } | |
1361 | ||
1e915849 RS |
1362 | /* Return the length of instruction INSN. */ |
1363 | ||
1364 | static inline unsigned int | |
1365 | insn_length (const struct mips_cl_insn *insn) | |
1366 | { | |
1367 | if (!mips_opts.mips16) | |
1368 | return 4; | |
1369 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1370 | } | |
1371 | ||
1372 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1373 | ||
1374 | static void | |
1375 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1376 | { | |
1377 | size_t i; | |
1378 | ||
1379 | insn->insn_mo = mo; | |
1380 | insn->use_extend = FALSE; | |
1381 | insn->extend = 0; | |
1382 | insn->insn_opcode = mo->match; | |
1383 | insn->frag = NULL; | |
1384 | insn->where = 0; | |
1385 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1386 | insn->fixp[i] = NULL; | |
1387 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1388 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1389 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1390 | insn->complete_p = 0; |
1e915849 RS |
1391 | } |
1392 | ||
742a56fe RS |
1393 | /* Record the current MIPS16 mode in now_seg. */ |
1394 | ||
1395 | static void | |
1396 | mips_record_mips16_mode (void) | |
1397 | { | |
1398 | segment_info_type *si; | |
1399 | ||
1400 | si = seg_info (now_seg); | |
1401 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1402 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1403 | } | |
1404 | ||
1e915849 RS |
1405 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1406 | ||
1407 | static void | |
1408 | install_insn (const struct mips_cl_insn *insn) | |
1409 | { | |
1410 | char *f = insn->frag->fr_literal + insn->where; | |
1411 | if (!mips_opts.mips16) | |
1412 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1413 | else if (insn->mips16_absolute_jump_p) | |
1414 | { | |
1415 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1416 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1417 | } | |
1418 | else | |
1419 | { | |
1420 | if (insn->use_extend) | |
1421 | { | |
1422 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1423 | f += 2; | |
1424 | } | |
1425 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1426 | } | |
742a56fe | 1427 | mips_record_mips16_mode (); |
1e915849 RS |
1428 | } |
1429 | ||
1430 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1431 | and install the opcode in the new location. */ | |
1432 | ||
1433 | static void | |
1434 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1435 | { | |
1436 | size_t i; | |
1437 | ||
1438 | insn->frag = frag; | |
1439 | insn->where = where; | |
1440 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1441 | if (insn->fixp[i] != NULL) | |
1442 | { | |
1443 | insn->fixp[i]->fx_frag = frag; | |
1444 | insn->fixp[i]->fx_where = where; | |
1445 | } | |
1446 | install_insn (insn); | |
1447 | } | |
1448 | ||
1449 | /* Add INSN to the end of the output. */ | |
1450 | ||
1451 | static void | |
1452 | add_fixed_insn (struct mips_cl_insn *insn) | |
1453 | { | |
1454 | char *f = frag_more (insn_length (insn)); | |
1455 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1456 | } | |
1457 | ||
1458 | /* Start a variant frag and move INSN to the start of the variant part, | |
1459 | marking it as fixed. The other arguments are as for frag_var. */ | |
1460 | ||
1461 | static void | |
1462 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1463 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1464 | { | |
1465 | frag_grow (max_chars); | |
1466 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1467 | insn->fixed_p = 1; | |
1468 | frag_var (rs_machine_dependent, max_chars, var, | |
1469 | subtype, symbol, offset, NULL); | |
1470 | } | |
1471 | ||
1472 | /* Insert N copies of INSN into the history buffer, starting at | |
1473 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1474 | ||
1475 | static void | |
1476 | insert_into_history (unsigned int first, unsigned int n, | |
1477 | const struct mips_cl_insn *insn) | |
1478 | { | |
1479 | if (mips_relax.sequence != 2) | |
1480 | { | |
1481 | unsigned int i; | |
1482 | ||
1483 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1484 | if (i >= first + n) | |
1485 | history[i] = history[i - n]; | |
1486 | else | |
1487 | history[i] = *insn; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1492 | ||
1493 | static void | |
1494 | emit_nop (void) | |
1495 | { | |
1496 | add_fixed_insn (NOP_INSN); | |
1497 | insert_into_history (0, 1, NOP_INSN); | |
1498 | } | |
1499 | ||
71400594 RS |
1500 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1501 | the idea is to make it obvious at a glance that each errata is | |
1502 | included. */ | |
1503 | ||
1504 | static void | |
1505 | init_vr4120_conflicts (void) | |
1506 | { | |
1507 | #define CONFLICT(FIRST, SECOND) \ | |
1508 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1509 | ||
1510 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1511 | CONFLICT (MACC, DIV); | |
1512 | CONFLICT (DMACC, DIV); | |
1513 | ||
1514 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1515 | CONFLICT (DMULT, DMULT); | |
1516 | CONFLICT (DMULT, DMACC); | |
1517 | CONFLICT (DMACC, DMULT); | |
1518 | CONFLICT (DMACC, DMACC); | |
1519 | ||
1520 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1521 | CONFLICT (MACC, MTHILO); | |
1522 | CONFLICT (DMACC, MTHILO); | |
1523 | ||
1524 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1525 | instruction is executed immediately after a MACC or DMACC | |
1526 | instruction, the result of [either instruction] is incorrect." */ | |
1527 | CONFLICT (MACC, MULT); | |
1528 | CONFLICT (MACC, DMULT); | |
1529 | CONFLICT (DMACC, MULT); | |
1530 | CONFLICT (DMACC, DMULT); | |
1531 | ||
1532 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1533 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1534 | DDIV or DDIVU instruction, the result of the MACC or | |
1535 | DMACC instruction is incorrect.". */ | |
1536 | CONFLICT (DMULT, MACC); | |
1537 | CONFLICT (DMULT, DMACC); | |
1538 | CONFLICT (DIV, MACC); | |
1539 | CONFLICT (DIV, DMACC); | |
1540 | ||
1541 | #undef CONFLICT | |
1542 | } | |
1543 | ||
707bfff6 TS |
1544 | struct regname { |
1545 | const char *name; | |
1546 | unsigned int num; | |
1547 | }; | |
1548 | ||
1549 | #define RTYPE_MASK 0x1ff00 | |
1550 | #define RTYPE_NUM 0x00100 | |
1551 | #define RTYPE_FPU 0x00200 | |
1552 | #define RTYPE_FCC 0x00400 | |
1553 | #define RTYPE_VEC 0x00800 | |
1554 | #define RTYPE_GP 0x01000 | |
1555 | #define RTYPE_CP0 0x02000 | |
1556 | #define RTYPE_PC 0x04000 | |
1557 | #define RTYPE_ACC 0x08000 | |
1558 | #define RTYPE_CCC 0x10000 | |
1559 | #define RNUM_MASK 0x000ff | |
1560 | #define RWARN 0x80000 | |
1561 | ||
1562 | #define GENERIC_REGISTER_NUMBERS \ | |
1563 | {"$0", RTYPE_NUM | 0}, \ | |
1564 | {"$1", RTYPE_NUM | 1}, \ | |
1565 | {"$2", RTYPE_NUM | 2}, \ | |
1566 | {"$3", RTYPE_NUM | 3}, \ | |
1567 | {"$4", RTYPE_NUM | 4}, \ | |
1568 | {"$5", RTYPE_NUM | 5}, \ | |
1569 | {"$6", RTYPE_NUM | 6}, \ | |
1570 | {"$7", RTYPE_NUM | 7}, \ | |
1571 | {"$8", RTYPE_NUM | 8}, \ | |
1572 | {"$9", RTYPE_NUM | 9}, \ | |
1573 | {"$10", RTYPE_NUM | 10}, \ | |
1574 | {"$11", RTYPE_NUM | 11}, \ | |
1575 | {"$12", RTYPE_NUM | 12}, \ | |
1576 | {"$13", RTYPE_NUM | 13}, \ | |
1577 | {"$14", RTYPE_NUM | 14}, \ | |
1578 | {"$15", RTYPE_NUM | 15}, \ | |
1579 | {"$16", RTYPE_NUM | 16}, \ | |
1580 | {"$17", RTYPE_NUM | 17}, \ | |
1581 | {"$18", RTYPE_NUM | 18}, \ | |
1582 | {"$19", RTYPE_NUM | 19}, \ | |
1583 | {"$20", RTYPE_NUM | 20}, \ | |
1584 | {"$21", RTYPE_NUM | 21}, \ | |
1585 | {"$22", RTYPE_NUM | 22}, \ | |
1586 | {"$23", RTYPE_NUM | 23}, \ | |
1587 | {"$24", RTYPE_NUM | 24}, \ | |
1588 | {"$25", RTYPE_NUM | 25}, \ | |
1589 | {"$26", RTYPE_NUM | 26}, \ | |
1590 | {"$27", RTYPE_NUM | 27}, \ | |
1591 | {"$28", RTYPE_NUM | 28}, \ | |
1592 | {"$29", RTYPE_NUM | 29}, \ | |
1593 | {"$30", RTYPE_NUM | 30}, \ | |
1594 | {"$31", RTYPE_NUM | 31} | |
1595 | ||
1596 | #define FPU_REGISTER_NAMES \ | |
1597 | {"$f0", RTYPE_FPU | 0}, \ | |
1598 | {"$f1", RTYPE_FPU | 1}, \ | |
1599 | {"$f2", RTYPE_FPU | 2}, \ | |
1600 | {"$f3", RTYPE_FPU | 3}, \ | |
1601 | {"$f4", RTYPE_FPU | 4}, \ | |
1602 | {"$f5", RTYPE_FPU | 5}, \ | |
1603 | {"$f6", RTYPE_FPU | 6}, \ | |
1604 | {"$f7", RTYPE_FPU | 7}, \ | |
1605 | {"$f8", RTYPE_FPU | 8}, \ | |
1606 | {"$f9", RTYPE_FPU | 9}, \ | |
1607 | {"$f10", RTYPE_FPU | 10}, \ | |
1608 | {"$f11", RTYPE_FPU | 11}, \ | |
1609 | {"$f12", RTYPE_FPU | 12}, \ | |
1610 | {"$f13", RTYPE_FPU | 13}, \ | |
1611 | {"$f14", RTYPE_FPU | 14}, \ | |
1612 | {"$f15", RTYPE_FPU | 15}, \ | |
1613 | {"$f16", RTYPE_FPU | 16}, \ | |
1614 | {"$f17", RTYPE_FPU | 17}, \ | |
1615 | {"$f18", RTYPE_FPU | 18}, \ | |
1616 | {"$f19", RTYPE_FPU | 19}, \ | |
1617 | {"$f20", RTYPE_FPU | 20}, \ | |
1618 | {"$f21", RTYPE_FPU | 21}, \ | |
1619 | {"$f22", RTYPE_FPU | 22}, \ | |
1620 | {"$f23", RTYPE_FPU | 23}, \ | |
1621 | {"$f24", RTYPE_FPU | 24}, \ | |
1622 | {"$f25", RTYPE_FPU | 25}, \ | |
1623 | {"$f26", RTYPE_FPU | 26}, \ | |
1624 | {"$f27", RTYPE_FPU | 27}, \ | |
1625 | {"$f28", RTYPE_FPU | 28}, \ | |
1626 | {"$f29", RTYPE_FPU | 29}, \ | |
1627 | {"$f30", RTYPE_FPU | 30}, \ | |
1628 | {"$f31", RTYPE_FPU | 31} | |
1629 | ||
1630 | #define FPU_CONDITION_CODE_NAMES \ | |
1631 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1632 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1633 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1634 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1635 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1636 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1637 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1638 | {"$fcc7", RTYPE_FCC | 7} | |
1639 | ||
1640 | #define COPROC_CONDITION_CODE_NAMES \ | |
1641 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1642 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1643 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1644 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1645 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1646 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1647 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1648 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1649 | ||
1650 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1651 | {"$a4", RTYPE_GP | 8}, \ | |
1652 | {"$a5", RTYPE_GP | 9}, \ | |
1653 | {"$a6", RTYPE_GP | 10}, \ | |
1654 | {"$a7", RTYPE_GP | 11}, \ | |
1655 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1656 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1657 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1658 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1659 | {"$t0", RTYPE_GP | 12}, \ | |
1660 | {"$t1", RTYPE_GP | 13}, \ | |
1661 | {"$t2", RTYPE_GP | 14}, \ | |
1662 | {"$t3", RTYPE_GP | 15} | |
1663 | ||
1664 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1665 | {"$t0", RTYPE_GP | 8}, \ | |
1666 | {"$t1", RTYPE_GP | 9}, \ | |
1667 | {"$t2", RTYPE_GP | 10}, \ | |
1668 | {"$t3", RTYPE_GP | 11}, \ | |
1669 | {"$t4", RTYPE_GP | 12}, \ | |
1670 | {"$t5", RTYPE_GP | 13}, \ | |
1671 | {"$t6", RTYPE_GP | 14}, \ | |
1672 | {"$t7", RTYPE_GP | 15}, \ | |
1673 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1674 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1675 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1676 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1677 | ||
1678 | /* Remaining symbolic register names */ | |
1679 | #define SYMBOLIC_REGISTER_NAMES \ | |
1680 | {"$zero", RTYPE_GP | 0}, \ | |
1681 | {"$at", RTYPE_GP | 1}, \ | |
1682 | {"$AT", RTYPE_GP | 1}, \ | |
1683 | {"$v0", RTYPE_GP | 2}, \ | |
1684 | {"$v1", RTYPE_GP | 3}, \ | |
1685 | {"$a0", RTYPE_GP | 4}, \ | |
1686 | {"$a1", RTYPE_GP | 5}, \ | |
1687 | {"$a2", RTYPE_GP | 6}, \ | |
1688 | {"$a3", RTYPE_GP | 7}, \ | |
1689 | {"$s0", RTYPE_GP | 16}, \ | |
1690 | {"$s1", RTYPE_GP | 17}, \ | |
1691 | {"$s2", RTYPE_GP | 18}, \ | |
1692 | {"$s3", RTYPE_GP | 19}, \ | |
1693 | {"$s4", RTYPE_GP | 20}, \ | |
1694 | {"$s5", RTYPE_GP | 21}, \ | |
1695 | {"$s6", RTYPE_GP | 22}, \ | |
1696 | {"$s7", RTYPE_GP | 23}, \ | |
1697 | {"$t8", RTYPE_GP | 24}, \ | |
1698 | {"$t9", RTYPE_GP | 25}, \ | |
1699 | {"$k0", RTYPE_GP | 26}, \ | |
1700 | {"$kt0", RTYPE_GP | 26}, \ | |
1701 | {"$k1", RTYPE_GP | 27}, \ | |
1702 | {"$kt1", RTYPE_GP | 27}, \ | |
1703 | {"$gp", RTYPE_GP | 28}, \ | |
1704 | {"$sp", RTYPE_GP | 29}, \ | |
1705 | {"$s8", RTYPE_GP | 30}, \ | |
1706 | {"$fp", RTYPE_GP | 30}, \ | |
1707 | {"$ra", RTYPE_GP | 31} | |
1708 | ||
1709 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1710 | {"$pc", RTYPE_PC | 0} | |
1711 | ||
1712 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1713 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1714 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1715 | {"$v2", RTYPE_VEC | 2}, \ | |
1716 | {"$v3", RTYPE_VEC | 3}, \ | |
1717 | {"$v4", RTYPE_VEC | 4}, \ | |
1718 | {"$v5", RTYPE_VEC | 5}, \ | |
1719 | {"$v6", RTYPE_VEC | 6}, \ | |
1720 | {"$v7", RTYPE_VEC | 7}, \ | |
1721 | {"$v8", RTYPE_VEC | 8}, \ | |
1722 | {"$v9", RTYPE_VEC | 9}, \ | |
1723 | {"$v10", RTYPE_VEC | 10}, \ | |
1724 | {"$v11", RTYPE_VEC | 11}, \ | |
1725 | {"$v12", RTYPE_VEC | 12}, \ | |
1726 | {"$v13", RTYPE_VEC | 13}, \ | |
1727 | {"$v14", RTYPE_VEC | 14}, \ | |
1728 | {"$v15", RTYPE_VEC | 15}, \ | |
1729 | {"$v16", RTYPE_VEC | 16}, \ | |
1730 | {"$v17", RTYPE_VEC | 17}, \ | |
1731 | {"$v18", RTYPE_VEC | 18}, \ | |
1732 | {"$v19", RTYPE_VEC | 19}, \ | |
1733 | {"$v20", RTYPE_VEC | 20}, \ | |
1734 | {"$v21", RTYPE_VEC | 21}, \ | |
1735 | {"$v22", RTYPE_VEC | 22}, \ | |
1736 | {"$v23", RTYPE_VEC | 23}, \ | |
1737 | {"$v24", RTYPE_VEC | 24}, \ | |
1738 | {"$v25", RTYPE_VEC | 25}, \ | |
1739 | {"$v26", RTYPE_VEC | 26}, \ | |
1740 | {"$v27", RTYPE_VEC | 27}, \ | |
1741 | {"$v28", RTYPE_VEC | 28}, \ | |
1742 | {"$v29", RTYPE_VEC | 29}, \ | |
1743 | {"$v30", RTYPE_VEC | 30}, \ | |
1744 | {"$v31", RTYPE_VEC | 31} | |
1745 | ||
1746 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1747 | {"$ac0", RTYPE_ACC | 0}, \ | |
1748 | {"$ac1", RTYPE_ACC | 1}, \ | |
1749 | {"$ac2", RTYPE_ACC | 2}, \ | |
1750 | {"$ac3", RTYPE_ACC | 3} | |
1751 | ||
1752 | static const struct regname reg_names[] = { | |
1753 | GENERIC_REGISTER_NUMBERS, | |
1754 | FPU_REGISTER_NAMES, | |
1755 | FPU_CONDITION_CODE_NAMES, | |
1756 | COPROC_CONDITION_CODE_NAMES, | |
1757 | ||
1758 | /* The $txx registers depends on the abi, | |
1759 | these will be added later into the symbol table from | |
1760 | one of the tables below once mips_abi is set after | |
1761 | parsing of arguments from the command line. */ | |
1762 | SYMBOLIC_REGISTER_NAMES, | |
1763 | ||
1764 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1765 | MDMX_VECTOR_REGISTER_NAMES, | |
1766 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1767 | {0, 0} | |
1768 | }; | |
1769 | ||
1770 | static const struct regname reg_names_o32[] = { | |
1771 | O32_SYMBOLIC_REGISTER_NAMES, | |
1772 | {0, 0} | |
1773 | }; | |
1774 | ||
1775 | static const struct regname reg_names_n32n64[] = { | |
1776 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1777 | {0, 0} | |
1778 | }; | |
1779 | ||
1780 | static int | |
1781 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1782 | { | |
1783 | symbolS *symbolP; | |
1784 | char *e; | |
1785 | char save_c; | |
1786 | int reg = -1; | |
1787 | ||
1788 | /* Find end of name. */ | |
1789 | e = *s; | |
1790 | if (is_name_beginner (*e)) | |
1791 | ++e; | |
1792 | while (is_part_of_name (*e)) | |
1793 | ++e; | |
1794 | ||
1795 | /* Terminate name. */ | |
1796 | save_c = *e; | |
1797 | *e = '\0'; | |
1798 | ||
1799 | /* Look for a register symbol. */ | |
1800 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1801 | { | |
1802 | int r = S_GET_VALUE (symbolP); | |
1803 | if (r & types) | |
1804 | reg = r & RNUM_MASK; | |
1805 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1806 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1807 | reg = (r & RNUM_MASK) - 2; | |
1808 | } | |
1809 | /* Else see if this is a register defined in an itbl entry. */ | |
1810 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1811 | { | |
1812 | char *n = *s; | |
1813 | unsigned long r; | |
1814 | ||
1815 | if (*n == '$') | |
1816 | ++n; | |
1817 | if (itbl_get_reg_val (n, &r)) | |
1818 | reg = r & RNUM_MASK; | |
1819 | } | |
1820 | ||
1821 | /* Advance to next token if a register was recognised. */ | |
1822 | if (reg >= 0) | |
1823 | *s = e; | |
1824 | else if (types & RWARN) | |
20203fb9 | 1825 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1826 | |
1827 | *e = save_c; | |
1828 | if (regnop) | |
1829 | *regnop = reg; | |
1830 | return reg >= 0; | |
1831 | } | |
1832 | ||
037b32b9 | 1833 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1834 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1835 | |
1836 | static bfd_boolean | |
f79e2745 | 1837 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1838 | { |
1839 | int isa = mips_opts.isa; | |
1840 | int fp_s, fp_d; | |
1841 | ||
1842 | if (mips_opts.ase_mdmx) | |
1843 | isa |= INSN_MDMX; | |
1844 | if (mips_opts.ase_dsp) | |
1845 | isa |= INSN_DSP; | |
1846 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1847 | isa |= INSN_DSP64; | |
1848 | if (mips_opts.ase_dspr2) | |
1849 | isa |= INSN_DSPR2; | |
1850 | if (mips_opts.ase_mt) | |
1851 | isa |= INSN_MT; | |
1852 | if (mips_opts.ase_mips3d) | |
1853 | isa |= INSN_MIPS3D; | |
1854 | if (mips_opts.ase_smartmips) | |
1855 | isa |= INSN_SMARTMIPS; | |
1856 | ||
b19e8a9b AN |
1857 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1858 | all the coprocessor insns. */ | |
1859 | if (NO_ISA_COP (mips_opts.arch) | |
1860 | && COP_INSN (mo->pinfo)) | |
1861 | isa = 0; | |
1862 | ||
037b32b9 AN |
1863 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1864 | return FALSE; | |
1865 | ||
1866 | /* Check whether the instruction or macro requires single-precision or | |
1867 | double-precision floating-point support. Note that this information is | |
1868 | stored differently in the opcode table for insns and macros. */ | |
1869 | if (mo->pinfo == INSN_MACRO) | |
1870 | { | |
1871 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1872 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | fp_s = mo->pinfo & FP_S; | |
1877 | fp_d = mo->pinfo & FP_D; | |
1878 | } | |
1879 | ||
1880 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1881 | return FALSE; | |
1882 | ||
1883 | if (fp_s && mips_opts.soft_float) | |
1884 | return FALSE; | |
1885 | ||
1886 | return TRUE; | |
1887 | } | |
1888 | ||
1889 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1890 | selected ISA and architecture. */ | |
1891 | ||
1892 | static bfd_boolean | |
1893 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1894 | { | |
1895 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1896 | } | |
1897 | ||
707bfff6 TS |
1898 | /* This function is called once, at assembler startup time. It should set up |
1899 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1900 | |
252b5132 | 1901 | void |
17a2f251 | 1902 | md_begin (void) |
252b5132 | 1903 | { |
3994f87e | 1904 | const char *retval = NULL; |
156c2f8b | 1905 | int i = 0; |
252b5132 | 1906 | int broken = 0; |
1f25f5d3 | 1907 | |
0a44bf69 RS |
1908 | if (mips_pic != NO_PIC) |
1909 | { | |
1910 | if (g_switch_seen && g_switch_value != 0) | |
1911 | as_bad (_("-G may not be used in position-independent code")); | |
1912 | g_switch_value = 0; | |
1913 | } | |
1914 | ||
fef14a42 | 1915 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1916 | as_warn (_("Could not set architecture and machine")); |
1917 | ||
252b5132 RH |
1918 | op_hash = hash_new (); |
1919 | ||
1920 | for (i = 0; i < NUMOPCODES;) | |
1921 | { | |
1922 | const char *name = mips_opcodes[i].name; | |
1923 | ||
17a2f251 | 1924 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1925 | if (retval != NULL) |
1926 | { | |
1927 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1928 | mips_opcodes[i].name, retval); | |
1929 | /* Probably a memory allocation problem? Give up now. */ | |
1930 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1931 | } | |
1932 | do | |
1933 | { | |
1934 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1935 | { | |
1936 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1937 | broken = 1; | |
1e915849 RS |
1938 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1939 | { | |
1940 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1941 | if (mips_fix_loongson2f_nop) |
1942 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1943 | nop_insn.fixed_p = 1; |
1944 | } | |
252b5132 RH |
1945 | } |
1946 | ++i; | |
1947 | } | |
1948 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1949 | } | |
1950 | ||
1951 | mips16_op_hash = hash_new (); | |
1952 | ||
1953 | i = 0; | |
1954 | while (i < bfd_mips16_num_opcodes) | |
1955 | { | |
1956 | const char *name = mips16_opcodes[i].name; | |
1957 | ||
17a2f251 | 1958 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1959 | if (retval != NULL) |
1960 | as_fatal (_("internal: can't hash `%s': %s"), | |
1961 | mips16_opcodes[i].name, retval); | |
1962 | do | |
1963 | { | |
1964 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1965 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1966 | != mips16_opcodes[i].match)) | |
1967 | { | |
1968 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1969 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1970 | broken = 1; | |
1971 | } | |
1e915849 RS |
1972 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1973 | { | |
1974 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1975 | mips16_nop_insn.fixed_p = 1; | |
1976 | } | |
252b5132 RH |
1977 | ++i; |
1978 | } | |
1979 | while (i < bfd_mips16_num_opcodes | |
1980 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1981 | } | |
1982 | ||
1983 | if (broken) | |
1984 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1985 | ||
1986 | /* We add all the general register names to the symbol table. This | |
1987 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1988 | for (i = 0; reg_names[i].name; i++) |
1989 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1990 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1991 | &zero_address_frag)); |
1992 | if (HAVE_NEWABI) | |
1993 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1994 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1995 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1996 | &zero_address_frag)); |
707bfff6 TS |
1997 | else |
1998 | for (i = 0; reg_names_o32[i].name; i++) | |
1999 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2000 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2001 | &zero_address_frag)); |
6047c971 | 2002 | |
7d10b47d | 2003 | mips_no_prev_insn (); |
252b5132 RH |
2004 | |
2005 | mips_gprmask = 0; | |
2006 | mips_cprmask[0] = 0; | |
2007 | mips_cprmask[1] = 0; | |
2008 | mips_cprmask[2] = 0; | |
2009 | mips_cprmask[3] = 0; | |
2010 | ||
2011 | /* set the default alignment for the text section (2**2) */ | |
2012 | record_alignment (text_section, 2); | |
2013 | ||
4d0d148d | 2014 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2015 | |
707bfff6 | 2016 | #ifdef OBJ_ELF |
f43abd2b | 2017 | if (IS_ELF) |
252b5132 | 2018 | { |
0a44bf69 RS |
2019 | /* On a native system other than VxWorks, sections must be aligned |
2020 | to 16 byte boundaries. When configured for an embedded ELF | |
2021 | target, we don't bother. */ | |
c41e87e3 CF |
2022 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2023 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2024 | { |
2025 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2026 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2027 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2028 | } | |
2029 | ||
2030 | /* Create a .reginfo section for register masks and a .mdebug | |
2031 | section for debugging information. */ | |
2032 | { | |
2033 | segT seg; | |
2034 | subsegT subseg; | |
2035 | flagword flags; | |
2036 | segT sec; | |
2037 | ||
2038 | seg = now_seg; | |
2039 | subseg = now_subseg; | |
2040 | ||
2041 | /* The ABI says this section should be loaded so that the | |
2042 | running program can access it. However, we don't load it | |
2043 | if we are configured for an embedded target */ | |
2044 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2045 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2046 | flags |= SEC_ALLOC | SEC_LOAD; |
2047 | ||
316f5878 | 2048 | if (mips_abi != N64_ABI) |
252b5132 RH |
2049 | { |
2050 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2051 | ||
195325d2 TS |
2052 | bfd_set_section_flags (stdoutput, sec, flags); |
2053 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2054 | |
252b5132 | 2055 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2056 | } |
2057 | else | |
2058 | { | |
2059 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2060 | .reginfo section. */ | |
2061 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2062 | bfd_set_section_flags (stdoutput, sec, flags); |
2063 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2064 | |
252b5132 RH |
2065 | /* Set up the option header. */ |
2066 | { | |
2067 | Elf_Internal_Options opthdr; | |
2068 | char *f; | |
2069 | ||
2070 | opthdr.kind = ODK_REGINFO; | |
2071 | opthdr.size = (sizeof (Elf_External_Options) | |
2072 | + sizeof (Elf64_External_RegInfo)); | |
2073 | opthdr.section = 0; | |
2074 | opthdr.info = 0; | |
2075 | f = frag_more (sizeof (Elf_External_Options)); | |
2076 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2077 | (Elf_External_Options *) f); | |
2078 | ||
2079 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2080 | } | |
252b5132 RH |
2081 | } |
2082 | ||
2083 | if (ECOFF_DEBUGGING) | |
2084 | { | |
2085 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2086 | (void) bfd_set_section_flags (stdoutput, sec, | |
2087 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2088 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2089 | } | |
f43abd2b | 2090 | else if (mips_flag_pdr) |
ecb4347a DJ |
2091 | { |
2092 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2093 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2094 | SEC_READONLY | SEC_RELOC | |
2095 | | SEC_DEBUGGING); | |
2096 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2097 | } | |
252b5132 RH |
2098 | |
2099 | subseg_set (seg, subseg); | |
2100 | } | |
2101 | } | |
707bfff6 | 2102 | #endif /* OBJ_ELF */ |
252b5132 RH |
2103 | |
2104 | if (! ECOFF_DEBUGGING) | |
2105 | md_obj_begin (); | |
71400594 RS |
2106 | |
2107 | if (mips_fix_vr4120) | |
2108 | init_vr4120_conflicts (); | |
252b5132 RH |
2109 | } |
2110 | ||
2111 | void | |
17a2f251 | 2112 | md_mips_end (void) |
252b5132 | 2113 | { |
02b1ab82 | 2114 | mips_emit_delays (); |
252b5132 RH |
2115 | if (! ECOFF_DEBUGGING) |
2116 | md_obj_end (); | |
2117 | } | |
2118 | ||
2119 | void | |
17a2f251 | 2120 | md_assemble (char *str) |
252b5132 RH |
2121 | { |
2122 | struct mips_cl_insn insn; | |
f6688943 TS |
2123 | bfd_reloc_code_real_type unused_reloc[3] |
2124 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2125 | |
2126 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2127 | imm2_expr.X_op = O_absent; |
252b5132 | 2128 | offset_expr.X_op = O_absent; |
f6688943 TS |
2129 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2130 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2131 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2132 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2133 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2134 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2135 | |
2136 | if (mips_opts.mips16) | |
2137 | mips16_ip (str, &insn); | |
2138 | else | |
2139 | { | |
2140 | mips_ip (str, &insn); | |
beae10d5 KH |
2141 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2142 | str, insn.insn_opcode)); | |
252b5132 RH |
2143 | } |
2144 | ||
2145 | if (insn_error) | |
2146 | { | |
2147 | as_bad ("%s `%s'", insn_error, str); | |
2148 | return; | |
2149 | } | |
2150 | ||
2151 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2152 | { | |
584892a6 | 2153 | macro_start (); |
252b5132 RH |
2154 | if (mips_opts.mips16) |
2155 | mips16_macro (&insn); | |
2156 | else | |
2157 | macro (&insn); | |
584892a6 | 2158 | macro_end (); |
252b5132 RH |
2159 | } |
2160 | else | |
2161 | { | |
2162 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2163 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2164 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2165 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2166 | else |
4d7206a2 | 2167 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2168 | } |
2169 | } | |
2170 | ||
738e5348 RS |
2171 | /* Convenience functions for abstracting away the differences between |
2172 | MIPS16 and non-MIPS16 relocations. */ | |
2173 | ||
2174 | static inline bfd_boolean | |
2175 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2176 | { | |
2177 | switch (reloc) | |
2178 | { | |
2179 | case BFD_RELOC_MIPS16_JMP: | |
2180 | case BFD_RELOC_MIPS16_GPREL: | |
2181 | case BFD_RELOC_MIPS16_GOT16: | |
2182 | case BFD_RELOC_MIPS16_CALL16: | |
2183 | case BFD_RELOC_MIPS16_HI16_S: | |
2184 | case BFD_RELOC_MIPS16_HI16: | |
2185 | case BFD_RELOC_MIPS16_LO16: | |
2186 | return TRUE; | |
2187 | ||
2188 | default: | |
2189 | return FALSE; | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | static inline bfd_boolean | |
2194 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2195 | { | |
2196 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2197 | } | |
2198 | ||
2199 | static inline bfd_boolean | |
2200 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2201 | { | |
2202 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2203 | } | |
2204 | ||
2205 | static inline bfd_boolean | |
2206 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2207 | { | |
2208 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2209 | } | |
2210 | ||
5919d012 | 2211 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2212 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2213 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2214 | |
2215 | static inline bfd_boolean | |
17a2f251 | 2216 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2217 | { |
3b91255e | 2218 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2219 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2220 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2221 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2222 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2223 | } | |
2224 | ||
2225 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2226 | reloc_needs_lo_p. */ | |
2227 | ||
2228 | static inline bfd_reloc_code_real_type | |
2229 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2230 | { | |
2231 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2232 | } |
2233 | ||
2234 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2235 | relocation. */ | |
2236 | ||
2237 | static inline bfd_boolean | |
17a2f251 | 2238 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2239 | { |
2240 | return (fixp->fx_next != NULL | |
738e5348 | 2241 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2242 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2243 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2244 | } | |
2245 | ||
252b5132 RH |
2246 | /* This function returns true if modifying a register requires a |
2247 | delay. */ | |
2248 | ||
2249 | static int | |
17a2f251 | 2250 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2251 | { |
2252 | unsigned long prev_pinfo; | |
2253 | ||
47e39b9d | 2254 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2255 | if (! mips_opts.noreorder |
81912461 ILT |
2256 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2257 | && ! gpr_interlocks) | |
2258 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2259 | && ! cop_interlocks))) | |
252b5132 | 2260 | { |
81912461 ILT |
2261 | /* A load from a coprocessor or from memory. All load delays |
2262 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2263 | /* Itbl support may require additional care here. */ |
252b5132 | 2264 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2265 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2266 | return 1; |
2267 | } | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
404a8071 RS |
2272 | /* Move all labels in insn_labels to the current insertion point. */ |
2273 | ||
2274 | static void | |
2275 | mips_move_labels (void) | |
2276 | { | |
a8dbcb85 | 2277 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2278 | struct insn_label_list *l; |
2279 | valueT val; | |
2280 | ||
a8dbcb85 | 2281 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2282 | { |
9c2799c2 | 2283 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2284 | symbol_set_frag (l->label, frag_now); |
2285 | val = (valueT) frag_now_fix (); | |
2286 | /* mips16 text labels are stored as odd. */ | |
2287 | if (mips_opts.mips16) | |
2288 | ++val; | |
2289 | S_SET_VALUE (l->label, val); | |
2290 | } | |
2291 | } | |
2292 | ||
5f0fe04b TS |
2293 | static bfd_boolean |
2294 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2295 | { | |
2296 | bfd_boolean linkonce = FALSE; | |
2297 | segT symseg = S_GET_SEGMENT (sym); | |
2298 | ||
2299 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2300 | { | |
2301 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2302 | linkonce = TRUE; | |
2303 | #ifdef OBJ_ELF | |
2304 | /* The GNU toolchain uses an extension for ELF: a section | |
2305 | beginning with the magic string .gnu.linkonce is a | |
2306 | linkonce section. */ | |
2307 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2308 | sizeof ".gnu.linkonce" - 1) == 0) | |
2309 | linkonce = TRUE; | |
2310 | #endif | |
2311 | } | |
2312 | return linkonce; | |
2313 | } | |
2314 | ||
252b5132 RH |
2315 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2316 | handle them specially, such as generating jalx instructions when | |
2317 | needed. We also make them odd for the duration of the assembly, in | |
2318 | order to generate the right sort of code. We will make them even | |
2319 | in the adjust_symtab routine, while leaving them marked. This is | |
2320 | convenient for the debugger and the disassembler. The linker knows | |
2321 | to make them odd again. */ | |
2322 | ||
2323 | static void | |
17a2f251 | 2324 | mips16_mark_labels (void) |
252b5132 | 2325 | { |
a8dbcb85 TS |
2326 | segment_info_type *si = seg_info (now_seg); |
2327 | struct insn_label_list *l; | |
252b5132 | 2328 | |
a8dbcb85 TS |
2329 | if (!mips_opts.mips16) |
2330 | return; | |
2331 | ||
2332 | for (l = si->label_list; l != NULL; l = l->next) | |
2333 | { | |
2334 | symbolS *label = l->label; | |
2335 | ||
2336 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2337 | if (IS_ELF) |
30c09090 | 2338 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2339 | #endif |
5f0fe04b TS |
2340 | if ((S_GET_VALUE (label) & 1) == 0 |
2341 | /* Don't adjust the address if the label is global or weak, or | |
2342 | in a link-once section, since we'll be emitting symbol reloc | |
2343 | references to it which will be patched up by the linker, and | |
2344 | the final value of the symbol may or may not be MIPS16. */ | |
2345 | && ! S_IS_WEAK (label) | |
2346 | && ! S_IS_EXTERNAL (label) | |
2347 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2348 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2349 | } |
2350 | } | |
2351 | ||
4d7206a2 RS |
2352 | /* End the current frag. Make it a variant frag and record the |
2353 | relaxation info. */ | |
2354 | ||
2355 | static void | |
2356 | relax_close_frag (void) | |
2357 | { | |
584892a6 | 2358 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2359 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2360 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2361 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2362 | ||
2363 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2364 | mips_relax.first_fixup = 0; | |
2365 | } | |
2366 | ||
2367 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2368 | See the comment above RELAX_ENCODE for more details. */ | |
2369 | ||
2370 | static void | |
2371 | relax_start (symbolS *symbol) | |
2372 | { | |
9c2799c2 | 2373 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2374 | mips_relax.sequence = 1; |
2375 | mips_relax.symbol = symbol; | |
2376 | } | |
2377 | ||
2378 | /* Start generating the second version of a relaxable sequence. | |
2379 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2380 | |
2381 | static void | |
4d7206a2 RS |
2382 | relax_switch (void) |
2383 | { | |
9c2799c2 | 2384 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2385 | mips_relax.sequence = 2; |
2386 | } | |
2387 | ||
2388 | /* End the current relaxable sequence. */ | |
2389 | ||
2390 | static void | |
2391 | relax_end (void) | |
2392 | { | |
9c2799c2 | 2393 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2394 | relax_close_frag (); |
2395 | mips_relax.sequence = 0; | |
2396 | } | |
2397 | ||
4c260379 RS |
2398 | /* Return the mask of core registers that IP reads. */ |
2399 | ||
2400 | static unsigned int | |
2401 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2402 | { | |
2403 | unsigned long pinfo, pinfo2; | |
2404 | unsigned int mask; | |
2405 | ||
2406 | mask = 0; | |
2407 | pinfo = ip->insn_mo->pinfo; | |
2408 | pinfo2 = ip->insn_mo->pinfo2; | |
2409 | if (mips_opts.mips16) | |
2410 | { | |
2411 | if (pinfo & MIPS16_INSN_READ_X) | |
2412 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2413 | if (pinfo & MIPS16_INSN_READ_Y) | |
2414 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2415 | if (pinfo & MIPS16_INSN_READ_T) | |
2416 | mask |= 1 << TREG; | |
2417 | if (pinfo & MIPS16_INSN_READ_SP) | |
2418 | mask |= 1 << SP; | |
2419 | if (pinfo & MIPS16_INSN_READ_31) | |
2420 | mask |= 1 << RA; | |
2421 | if (pinfo & MIPS16_INSN_READ_Z) | |
2422 | mask |= 1 << (mips16_to_32_reg_map | |
2423 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2424 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2425 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2426 | } | |
2427 | else | |
2428 | { | |
2429 | if (pinfo2 & INSN2_READ_GPR_D) | |
2430 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2431 | if (pinfo & INSN_READ_GPR_T) | |
2432 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2433 | if (pinfo & INSN_READ_GPR_S) | |
2434 | mask |= 1 << EXTRACT_OPERAND (RS, *ip); | |
2435 | if (pinfo2 & INSN2_READ_GPR_Z) | |
2436 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2437 | } | |
2438 | return mask & ~0; | |
2439 | } | |
2440 | ||
2441 | /* Return the mask of core registers that IP writes. */ | |
2442 | ||
2443 | static unsigned int | |
2444 | gpr_write_mask (const struct mips_cl_insn *ip) | |
2445 | { | |
2446 | unsigned long pinfo, pinfo2; | |
2447 | unsigned int mask; | |
2448 | ||
2449 | mask = 0; | |
2450 | pinfo = ip->insn_mo->pinfo; | |
2451 | pinfo2 = ip->insn_mo->pinfo2; | |
2452 | if (mips_opts.mips16) | |
2453 | { | |
2454 | if (pinfo & MIPS16_INSN_WRITE_X) | |
2455 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2456 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
2457 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2458 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2459 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
2460 | if (pinfo & MIPS16_INSN_WRITE_T) | |
2461 | mask |= 1 << TREG; | |
2462 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
2463 | mask |= 1 << SP; | |
2464 | if (pinfo & MIPS16_INSN_WRITE_31) | |
2465 | mask |= 1 << RA; | |
2466 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2467 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2468 | } | |
2469 | else | |
2470 | { | |
2471 | if (pinfo & INSN_WRITE_GPR_D) | |
2472 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2473 | if (pinfo & INSN_WRITE_GPR_T) | |
2474 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2475 | if (pinfo & INSN_WRITE_GPR_31) | |
2476 | mask |= 1 << RA; | |
2477 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
2478 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2479 | } | |
2480 | return mask & ~0; | |
2481 | } | |
2482 | ||
2483 | /* Return the mask of floating-point registers that IP reads. */ | |
2484 | ||
2485 | static unsigned int | |
2486 | fpr_read_mask (const struct mips_cl_insn *ip) | |
2487 | { | |
2488 | unsigned long pinfo, pinfo2; | |
2489 | unsigned int mask; | |
2490 | ||
2491 | mask = 0; | |
2492 | pinfo = ip->insn_mo->pinfo; | |
2493 | pinfo2 = ip->insn_mo->pinfo2; | |
2494 | if (!mips_opts.mips16) | |
2495 | { | |
2496 | if (pinfo & INSN_READ_FPR_S) | |
2497 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2498 | if (pinfo & INSN_READ_FPR_T) | |
2499 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2500 | if (pinfo & INSN_READ_FPR_R) | |
2501 | mask |= 1 << EXTRACT_OPERAND (FR, *ip); | |
2502 | if (pinfo2 & INSN2_READ_FPR_Z) | |
2503 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2504 | } | |
2505 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2506 | (This is overly pessimistic for things like cvt.d.s.) */ | |
2507 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2508 | mask |= mask << 1; | |
2509 | return mask; | |
2510 | } | |
2511 | ||
2512 | /* Return the mask of floating-point registers that IP writes. */ | |
2513 | ||
2514 | static unsigned int | |
2515 | fpr_write_mask (const struct mips_cl_insn *ip) | |
2516 | { | |
2517 | unsigned long pinfo, pinfo2; | |
2518 | unsigned int mask; | |
2519 | ||
2520 | mask = 0; | |
2521 | pinfo = ip->insn_mo->pinfo; | |
2522 | pinfo2 = ip->insn_mo->pinfo2; | |
2523 | if (!mips_opts.mips16) | |
2524 | { | |
2525 | if (pinfo & INSN_WRITE_FPR_D) | |
2526 | mask |= 1 << EXTRACT_OPERAND (FD, *ip); | |
2527 | if (pinfo & INSN_WRITE_FPR_S) | |
2528 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2529 | if (pinfo & INSN_WRITE_FPR_T) | |
2530 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2531 | if (pinfo2 & INSN2_WRITE_FPR_Z) | |
2532 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2533 | } | |
2534 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2535 | (This is overly pessimistic for things like cvt.s.d.) */ | |
2536 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2537 | mask |= mask << 1; | |
2538 | return mask; | |
2539 | } | |
2540 | ||
71400594 RS |
2541 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2542 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2543 | by VR4120 errata. */ | |
4d7206a2 | 2544 | |
71400594 RS |
2545 | static unsigned int |
2546 | classify_vr4120_insn (const char *name) | |
252b5132 | 2547 | { |
71400594 RS |
2548 | if (strncmp (name, "macc", 4) == 0) |
2549 | return FIX_VR4120_MACC; | |
2550 | if (strncmp (name, "dmacc", 5) == 0) | |
2551 | return FIX_VR4120_DMACC; | |
2552 | if (strncmp (name, "mult", 4) == 0) | |
2553 | return FIX_VR4120_MULT; | |
2554 | if (strncmp (name, "dmult", 5) == 0) | |
2555 | return FIX_VR4120_DMULT; | |
2556 | if (strstr (name, "div")) | |
2557 | return FIX_VR4120_DIV; | |
2558 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2559 | return FIX_VR4120_MTHILO; | |
2560 | return NUM_FIX_VR4120_CLASSES; | |
2561 | } | |
252b5132 | 2562 | |
ff239038 CM |
2563 | #define INSN_ERET 0x42000018 |
2564 | #define INSN_DERET 0x4200001f | |
2565 | ||
71400594 RS |
2566 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2567 | where INSN1 is the earlier instruction. Return the worst-case value | |
2568 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2569 | |
71400594 RS |
2570 | static unsigned int |
2571 | insns_between (const struct mips_cl_insn *insn1, | |
2572 | const struct mips_cl_insn *insn2) | |
2573 | { | |
2574 | unsigned long pinfo1, pinfo2; | |
4c260379 | 2575 | unsigned int mask; |
71400594 RS |
2576 | |
2577 | /* This function needs to know which pinfo flags are set for INSN2 | |
2578 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
2579 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
2580 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
2581 | pinfo1 = insn1->insn_mo->pinfo; |
2582 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2583 | |
4c260379 RS |
2584 | #define INSN2_USES_GPR(REG) \ |
2585 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
2586 | |
2587 | /* For most targets, write-after-read dependencies on the HI and LO | |
2588 | registers must be separated by at least two instructions. */ | |
2589 | if (!hilo_interlocks) | |
252b5132 | 2590 | { |
71400594 RS |
2591 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2592 | return 2; | |
2593 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2594 | return 2; | |
2595 | } | |
2596 | ||
2597 | /* If we're working around r7000 errata, there must be two instructions | |
2598 | between an mfhi or mflo and any instruction that uses the result. */ | |
2599 | if (mips_7000_hilo_fix | |
2600 | && MF_HILO_INSN (pinfo1) | |
4c260379 | 2601 | && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1))) |
71400594 RS |
2602 | return 2; |
2603 | ||
ff239038 CM |
2604 | /* If we're working around 24K errata, one instruction is required |
2605 | if an ERET or DERET is followed by a branch instruction. */ | |
2606 | if (mips_fix_24k) | |
2607 | { | |
2608 | if (insn1->insn_opcode == INSN_ERET | |
2609 | || insn1->insn_opcode == INSN_DERET) | |
2610 | { | |
2611 | if (insn2 == NULL | |
2612 | || insn2->insn_opcode == INSN_ERET | |
2613 | || insn2->insn_opcode == INSN_DERET | |
2614 | || (insn2->insn_mo->pinfo | |
2615 | & (INSN_UNCOND_BRANCH_DELAY | |
2616 | | INSN_COND_BRANCH_DELAY | |
2617 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2618 | return 1; | |
2619 | } | |
2620 | } | |
2621 | ||
71400594 RS |
2622 | /* If working around VR4120 errata, check for combinations that need |
2623 | a single intervening instruction. */ | |
2624 | if (mips_fix_vr4120) | |
2625 | { | |
2626 | unsigned int class1, class2; | |
252b5132 | 2627 | |
71400594 RS |
2628 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2629 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2630 | { |
71400594 RS |
2631 | if (insn2 == NULL) |
2632 | return 1; | |
2633 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2634 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2635 | return 1; | |
252b5132 | 2636 | } |
71400594 RS |
2637 | } |
2638 | ||
2639 | if (!mips_opts.mips16) | |
2640 | { | |
2641 | /* Check for GPR or coprocessor load delays. All such delays | |
2642 | are on the RT register. */ | |
2643 | /* Itbl support may require additional care here. */ | |
2644 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2645 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2646 | { |
71400594 | 2647 | know (pinfo1 & INSN_WRITE_GPR_T); |
4c260379 | 2648 | if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1))) |
71400594 RS |
2649 | return 1; |
2650 | } | |
2651 | ||
2652 | /* Check for generic coprocessor hazards. | |
2653 | ||
2654 | This case is not handled very well. There is no special | |
2655 | knowledge of CP0 handling, and the coprocessors other than | |
2656 | the floating point unit are not distinguished at all. */ | |
2657 | /* Itbl support may require additional care here. FIXME! | |
2658 | Need to modify this to include knowledge about | |
2659 | user specified delays! */ | |
2660 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2661 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2662 | { | |
2663 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2664 | register. There must be a one instruction delay before INSN2 | |
2665 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
2666 | mask = fpr_write_mask (insn1); |
2667 | if (mask != 0) | |
252b5132 | 2668 | { |
4c260379 | 2669 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 2670 | return 1; |
252b5132 RH |
2671 | } |
2672 | else | |
2673 | { | |
71400594 RS |
2674 | /* Read-after-write dependencies on the control registers |
2675 | require a two-instruction gap. */ | |
2676 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2677 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2678 | return 2; | |
2679 | ||
2680 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2681 | also a coprocessor instruction, assume there must be | |
2682 | a one instruction gap. */ | |
2683 | if (pinfo2 & INSN_COP) | |
2684 | return 1; | |
252b5132 RH |
2685 | } |
2686 | } | |
6b76fefe | 2687 | |
71400594 RS |
2688 | /* Check for read-after-write dependencies on the coprocessor |
2689 | control registers in cases where INSN1 does not need a general | |
2690 | coprocessor delay. This means that INSN1 is a floating point | |
2691 | comparison instruction. */ | |
2692 | /* Itbl support may require additional care here. */ | |
2693 | else if (!cop_interlocks | |
2694 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2695 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2696 | return 1; | |
2697 | } | |
6b76fefe | 2698 | |
4c260379 | 2699 | #undef INSN2_USES_GPR |
6b76fefe | 2700 | |
71400594 RS |
2701 | return 0; |
2702 | } | |
6b76fefe | 2703 | |
7d8e00cf RS |
2704 | /* Return the number of nops that would be needed to work around the |
2705 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
2706 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
2707 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
2708 | |
2709 | static int | |
932d1a1b | 2710 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
2711 | const struct mips_cl_insn *insn) |
2712 | { | |
4c260379 RS |
2713 | int i, j; |
2714 | unsigned int mask; | |
7d8e00cf RS |
2715 | |
2716 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2717 | are not affected by the errata. */ | |
2718 | if (insn != 0 | |
2719 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2720 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2721 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2722 | return 0; | |
2723 | ||
2724 | /* Search for the first MFLO or MFHI. */ | |
2725 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2726 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2727 | { |
2728 | /* Extract the destination register. */ | |
4c260379 | 2729 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
2730 | |
2731 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 2732 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
2733 | return 0; |
2734 | ||
2735 | /* ...or if any of the intervening instructions do. */ | |
2736 | for (j = 0; j < i; j++) | |
4c260379 | 2737 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
2738 | return 0; |
2739 | ||
932d1a1b RS |
2740 | if (i >= ignore) |
2741 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
2742 | } |
2743 | return 0; | |
2744 | } | |
2745 | ||
15be625d CM |
2746 | #define BASE_REG_EQ(INSN1, INSN2) \ |
2747 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
2748 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
2749 | ||
2750 | /* Return the minimum alignment for this store instruction. */ | |
2751 | ||
2752 | static int | |
2753 | fix_24k_align_to (const struct mips_opcode *mo) | |
2754 | { | |
2755 | if (strcmp (mo->name, "sh") == 0) | |
2756 | return 2; | |
2757 | ||
2758 | if (strcmp (mo->name, "swc1") == 0 | |
2759 | || strcmp (mo->name, "swc2") == 0 | |
2760 | || strcmp (mo->name, "sw") == 0 | |
2761 | || strcmp (mo->name, "sc") == 0 | |
2762 | || strcmp (mo->name, "s.s") == 0) | |
2763 | return 4; | |
2764 | ||
2765 | if (strcmp (mo->name, "sdc1") == 0 | |
2766 | || strcmp (mo->name, "sdc2") == 0 | |
2767 | || strcmp (mo->name, "s.d") == 0) | |
2768 | return 8; | |
2769 | ||
2770 | /* sb, swl, swr */ | |
2771 | return 1; | |
2772 | } | |
2773 | ||
2774 | struct fix_24k_store_info | |
2775 | { | |
2776 | /* Immediate offset, if any, for this store instruction. */ | |
2777 | short off; | |
2778 | /* Alignment required by this store instruction. */ | |
2779 | int align_to; | |
2780 | /* True for register offsets. */ | |
2781 | int register_offset; | |
2782 | }; | |
2783 | ||
2784 | /* Comparison function used by qsort. */ | |
2785 | ||
2786 | static int | |
2787 | fix_24k_sort (const void *a, const void *b) | |
2788 | { | |
2789 | const struct fix_24k_store_info *pos1 = a; | |
2790 | const struct fix_24k_store_info *pos2 = b; | |
2791 | ||
2792 | return (pos1->off - pos2->off); | |
2793 | } | |
2794 | ||
2795 | /* INSN is a store instruction. Try to record the store information | |
2796 | in STINFO. Return false if the information isn't known. */ | |
2797 | ||
2798 | static bfd_boolean | |
2799 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 2800 | const struct mips_cl_insn *insn) |
15be625d CM |
2801 | { |
2802 | /* The instruction must have a known offset. */ | |
2803 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
2804 | return FALSE; | |
2805 | ||
2806 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
2807 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
2808 | return TRUE; | |
2809 | } | |
2810 | ||
932d1a1b RS |
2811 | /* Return the number of nops that would be needed to work around the 24k |
2812 | "lost data on stores during refill" errata if instruction INSN | |
2813 | immediately followed the 2 instructions described by HIST. | |
2814 | Ignore hazards that are contained within the first IGNORE | |
2815 | instructions of HIST. | |
2816 | ||
2817 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
2818 | for the data cache refills and store data. The following describes | |
2819 | the scenario where the store data could be lost. | |
2820 | ||
2821 | * A data cache miss, due to either a load or a store, causing fill | |
2822 | data to be supplied by the memory subsystem | |
2823 | * The first three doublewords of fill data are returned and written | |
2824 | into the cache | |
2825 | * A sequence of four stores occurs in consecutive cycles around the | |
2826 | final doubleword of the fill: | |
2827 | * Store A | |
2828 | * Store B | |
2829 | * Store C | |
2830 | * Zero, One or more instructions | |
2831 | * Store D | |
2832 | ||
2833 | The four stores A-D must be to different doublewords of the line that | |
2834 | is being filled. The fourth instruction in the sequence above permits | |
2835 | the fill of the final doubleword to be transferred from the FSB into | |
2836 | the cache. In the sequence above, the stores may be either integer | |
2837 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
2838 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
2839 | different doublewords on the line. If the floating point unit is | |
2840 | running in 1:2 mode, it is not possible to create the sequence above | |
2841 | using only floating point store instructions. | |
15be625d CM |
2842 | |
2843 | In this case, the cache line being filled is incorrectly marked | |
2844 | invalid, thereby losing the data from any store to the line that | |
2845 | occurs between the original miss and the completion of the five | |
2846 | cycle sequence shown above. | |
2847 | ||
932d1a1b | 2848 | The workarounds are: |
15be625d | 2849 | |
932d1a1b RS |
2850 | * Run the data cache in write-through mode. |
2851 | * Insert a non-store instruction between | |
2852 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
2853 | |
2854 | static int | |
932d1a1b | 2855 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
2856 | const struct mips_cl_insn *insn) |
2857 | { | |
2858 | struct fix_24k_store_info pos[3]; | |
2859 | int align, i, base_offset; | |
2860 | ||
932d1a1b RS |
2861 | if (ignore >= 2) |
2862 | return 0; | |
2863 | ||
ab9794cf RS |
2864 | /* If the previous instruction wasn't a store, there's nothing to |
2865 | worry about. */ | |
15be625d CM |
2866 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
2867 | return 0; | |
2868 | ||
ab9794cf RS |
2869 | /* If the instructions after the previous one are unknown, we have |
2870 | to assume the worst. */ | |
2871 | if (!insn) | |
15be625d CM |
2872 | return 1; |
2873 | ||
ab9794cf RS |
2874 | /* Check whether we are dealing with three consecutive stores. */ |
2875 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
2876 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
2877 | return 0; |
2878 | ||
2879 | /* If we don't know the relationship between the store addresses, | |
2880 | assume the worst. */ | |
ab9794cf | 2881 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
2882 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
2883 | return 1; | |
2884 | ||
2885 | if (!fix_24k_record_store_info (&pos[0], insn) | |
2886 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
2887 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
2888 | return 1; | |
2889 | ||
2890 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
2891 | ||
2892 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
2893 | X bytes and such that the base register + X is known to be aligned | |
2894 | to align bytes. */ | |
2895 | ||
2896 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
2897 | align = 8; | |
2898 | else | |
2899 | { | |
2900 | align = pos[0].align_to; | |
2901 | base_offset = pos[0].off; | |
2902 | for (i = 1; i < 3; i++) | |
2903 | if (align < pos[i].align_to) | |
2904 | { | |
2905 | align = pos[i].align_to; | |
2906 | base_offset = pos[i].off; | |
2907 | } | |
2908 | for (i = 0; i < 3; i++) | |
2909 | pos[i].off -= base_offset; | |
2910 | } | |
2911 | ||
2912 | pos[0].off &= ~align + 1; | |
2913 | pos[1].off &= ~align + 1; | |
2914 | pos[2].off &= ~align + 1; | |
2915 | ||
2916 | /* If any two stores write to the same chunk, they also write to the | |
2917 | same doubleword. The offsets are still sorted at this point. */ | |
2918 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
2919 | return 0; | |
2920 | ||
2921 | /* A range of at least 9 bytes is needed for the stores to be in | |
2922 | non-overlapping doublewords. */ | |
2923 | if (pos[2].off - pos[0].off <= 8) | |
2924 | return 0; | |
2925 | ||
2926 | if (pos[2].off - pos[1].off >= 24 | |
2927 | || pos[1].off - pos[0].off >= 24 | |
2928 | || pos[2].off - pos[0].off >= 32) | |
2929 | return 0; | |
2930 | ||
2931 | return 1; | |
2932 | } | |
2933 | ||
71400594 | 2934 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 2935 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
2936 | where HIST[0] is the most recent instruction. Ignore hazards |
2937 | between INSN and the first IGNORE instructions in HIST. | |
2938 | ||
2939 | If INSN is null, return the worse-case number of nops for any | |
2940 | instruction. */ | |
bdaaa2e1 | 2941 | |
71400594 | 2942 | static int |
932d1a1b | 2943 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
2944 | const struct mips_cl_insn *insn) |
2945 | { | |
2946 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2947 | |
71400594 | 2948 | nops = 0; |
932d1a1b | 2949 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2950 | { |
91d6fa6a | 2951 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2952 | if (tmp_nops > nops) |
2953 | nops = tmp_nops; | |
2954 | } | |
7d8e00cf RS |
2955 | |
2956 | if (mips_fix_vr4130) | |
2957 | { | |
932d1a1b | 2958 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
2959 | if (tmp_nops > nops) |
2960 | nops = tmp_nops; | |
2961 | } | |
2962 | ||
15be625d CM |
2963 | if (mips_fix_24k) |
2964 | { | |
932d1a1b | 2965 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
2966 | if (tmp_nops > nops) |
2967 | nops = tmp_nops; | |
2968 | } | |
2969 | ||
71400594 RS |
2970 | return nops; |
2971 | } | |
252b5132 | 2972 | |
71400594 | 2973 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2974 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
2975 | would be needed after the extended sequence, ignoring hazards |
2976 | in the first IGNORE instructions. */ | |
252b5132 | 2977 | |
71400594 | 2978 | static int |
932d1a1b RS |
2979 | nops_for_sequence (int num_insns, int ignore, |
2980 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
2981 | { |
2982 | va_list args; | |
2983 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2984 | struct mips_cl_insn *cursor; | |
2985 | int nops; | |
2986 | ||
91d6fa6a | 2987 | va_start (args, hist); |
71400594 | 2988 | cursor = buffer + num_insns; |
91d6fa6a | 2989 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2990 | while (cursor > buffer) |
2991 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2992 | ||
932d1a1b | 2993 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
2994 | va_end (args); |
2995 | return nops; | |
2996 | } | |
252b5132 | 2997 | |
71400594 RS |
2998 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2999 | worst-case delay for the branch target. */ | |
252b5132 | 3000 | |
71400594 | 3001 | static int |
932d1a1b | 3002 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3003 | const struct mips_cl_insn *insn) |
3004 | { | |
3005 | int nops, tmp_nops; | |
60b63b72 | 3006 | |
932d1a1b | 3007 | nops = nops_for_insn (ignore, hist, insn); |
71400594 RS |
3008 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
3009 | | INSN_COND_BRANCH_DELAY | |
3010 | | INSN_COND_BRANCH_LIKELY)) | |
3011 | { | |
932d1a1b RS |
3012 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
3013 | hist, insn, NOP_INSN); | |
71400594 RS |
3014 | if (tmp_nops > nops) |
3015 | nops = tmp_nops; | |
3016 | } | |
9a2c7088 MR |
3017 | else if (mips_opts.mips16 |
3018 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3019 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 3020 | { |
932d1a1b | 3021 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3022 | if (tmp_nops > nops) |
3023 | nops = tmp_nops; | |
3024 | } | |
3025 | return nops; | |
3026 | } | |
3027 | ||
c67a084a NC |
3028 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3029 | ||
3030 | static void | |
3031 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3032 | { | |
3033 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
3034 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3035 | } | |
3036 | ||
3037 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3038 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3039 | ||
3040 | static void | |
3041 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3042 | { | |
3043 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
3044 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3045 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3046 | { | |
3047 | int sreg; | |
3048 | expressionS ep; | |
3049 | ||
3050 | if (! mips_opts.at) | |
3051 | return; | |
3052 | ||
3053 | sreg = EXTRACT_OPERAND (RS, *ip); | |
3054 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
3055 | return; | |
3056 | ||
3057 | ep.X_op = O_constant; | |
3058 | ep.X_add_number = 0xcfff0000; | |
3059 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3060 | ep.X_add_number = 0xffff; | |
3061 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3062 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3063 | } | |
3064 | } | |
3065 | ||
3066 | static void | |
3067 | fix_loongson2f (struct mips_cl_insn * ip) | |
3068 | { | |
3069 | if (mips_fix_loongson2f_nop) | |
3070 | fix_loongson2f_nop (ip); | |
3071 | ||
3072 | if (mips_fix_loongson2f_jump) | |
3073 | fix_loongson2f_jump (ip); | |
3074 | } | |
3075 | ||
ceb94aa5 RS |
3076 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3077 | Point IP->insn_mo to the new opcode's definition. */ | |
3078 | ||
3079 | static void | |
3080 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3081 | { | |
3082 | const struct mips_opcode *mo, *end; | |
3083 | ||
3084 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3085 | for (mo = ip->insn_mo; mo < end; mo++) | |
3086 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3087 | { | |
3088 | ip->insn_mo = mo; | |
3089 | return; | |
3090 | } | |
3091 | abort (); | |
3092 | } | |
3093 | ||
71400594 RS |
3094 | /* Output an instruction. IP is the instruction information. |
3095 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3096 | RELOC_TYPE. */ | |
3097 | ||
3098 | static void | |
3099 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
3100 | bfd_reloc_code_real_type *reloc_type) | |
3101 | { | |
3994f87e | 3102 | unsigned long prev_pinfo, pinfo; |
98675402 | 3103 | unsigned long prev_pinfo2, pinfo2; |
71400594 RS |
3104 | relax_stateT prev_insn_frag_type = 0; |
3105 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 3106 | segment_info_type *si = seg_info (now_seg); |
71400594 | 3107 | |
c67a084a NC |
3108 | if (mips_fix_loongson2f) |
3109 | fix_loongson2f (ip); | |
3110 | ||
71400594 RS |
3111 | /* Mark instruction labels in mips16 mode. */ |
3112 | mips16_mark_labels (); | |
3113 | ||
738f4d98 MR |
3114 | file_ase_mips16 |= mips_opts.mips16; |
3115 | ||
71400594 | 3116 | prev_pinfo = history[0].insn_mo->pinfo; |
98675402 | 3117 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 3118 | pinfo = ip->insn_mo->pinfo; |
98675402 | 3119 | pinfo2 = ip->insn_mo->pinfo2; |
71400594 | 3120 | |
15be625d CM |
3121 | if (address_expr == NULL) |
3122 | ip->complete_p = 1; | |
3123 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
3124 | && address_expr->X_op == O_constant) | |
3125 | { | |
3126 | unsigned int tmp; | |
3127 | ||
3128 | ip->complete_p = 1; | |
3129 | switch (*reloc_type) | |
3130 | { | |
3131 | case BFD_RELOC_32: | |
3132 | ip->insn_opcode |= address_expr->X_add_number; | |
3133 | break; | |
3134 | ||
3135 | case BFD_RELOC_MIPS_HIGHEST: | |
3136 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
3137 | ip->insn_opcode |= tmp & 0xffff; | |
3138 | break; | |
3139 | ||
3140 | case BFD_RELOC_MIPS_HIGHER: | |
3141 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
3142 | ip->insn_opcode |= tmp & 0xffff; | |
3143 | break; | |
3144 | ||
3145 | case BFD_RELOC_HI16_S: | |
3146 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
3147 | ip->insn_opcode |= tmp & 0xffff; | |
3148 | break; | |
3149 | ||
3150 | case BFD_RELOC_HI16: | |
3151 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3152 | break; | |
3153 | ||
3154 | case BFD_RELOC_UNUSED: | |
3155 | case BFD_RELOC_LO16: | |
3156 | case BFD_RELOC_MIPS_GOT_DISP: | |
3157 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
3158 | break; | |
3159 | ||
3160 | case BFD_RELOC_MIPS_JMP: | |
3161 | if ((address_expr->X_add_number & 3) != 0) | |
3162 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3163 | (unsigned long) address_expr->X_add_number); | |
3164 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3165 | ip->complete_p = 0; | |
3166 | break; | |
3167 | ||
3168 | case BFD_RELOC_MIPS16_JMP: | |
3169 | if ((address_expr->X_add_number & 3) != 0) | |
3170 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3171 | (unsigned long) address_expr->X_add_number); | |
3172 | ip->insn_opcode |= | |
3173 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3174 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3175 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3176 | ip->complete_p = 0; | |
3177 | break; | |
3178 | ||
3179 | case BFD_RELOC_16_PCREL_S2: | |
3180 | if ((address_expr->X_add_number & 3) != 0) | |
3181 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3182 | (unsigned long) address_expr->X_add_number); | |
9fe77896 RS |
3183 | if (!mips_relax_branch) |
3184 | { | |
3185 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3186 | as_bad (_("branch address range overflow (0x%lx)"), | |
3187 | (unsigned long) address_expr->X_add_number); | |
3188 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3189 | } | |
15be625d CM |
3190 | ip->complete_p = 0; |
3191 | break; | |
3192 | ||
3193 | default: | |
3194 | internalError (); | |
3195 | } | |
3196 | } | |
3197 | ||
71400594 RS |
3198 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
3199 | { | |
3200 | /* There are a lot of optimizations we could do that we don't. | |
3201 | In particular, we do not, in general, reorder instructions. | |
3202 | If you use gcc with optimization, it will reorder | |
3203 | instructions and generally do much more optimization then we | |
3204 | do here; repeating all that work in the assembler would only | |
3205 | benefit hand written assembly code, and does not seem worth | |
3206 | it. */ | |
3207 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
3208 | ? nops_for_insn (0, history, NULL) |
3209 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 3210 | if (nops > 0) |
252b5132 RH |
3211 | { |
3212 | fragS *old_frag; | |
3213 | unsigned long old_frag_offset; | |
3214 | int i; | |
252b5132 RH |
3215 | |
3216 | old_frag = frag_now; | |
3217 | old_frag_offset = frag_now_fix (); | |
3218 | ||
3219 | for (i = 0; i < nops; i++) | |
3220 | emit_nop (); | |
3221 | ||
3222 | if (listing) | |
3223 | { | |
3224 | listing_prev_line (); | |
3225 | /* We may be at the start of a variant frag. In case we | |
3226 | are, make sure there is enough space for the frag | |
3227 | after the frags created by listing_prev_line. The | |
3228 | argument to frag_grow here must be at least as large | |
3229 | as the argument to all other calls to frag_grow in | |
3230 | this file. We don't have to worry about being in the | |
3231 | middle of a variant frag, because the variants insert | |
3232 | all needed nop instructions themselves. */ | |
3233 | frag_grow (40); | |
3234 | } | |
3235 | ||
404a8071 | 3236 | mips_move_labels (); |
252b5132 RH |
3237 | |
3238 | #ifndef NO_ECOFF_DEBUGGING | |
3239 | if (ECOFF_DEBUGGING) | |
3240 | ecoff_fix_loc (old_frag, old_frag_offset); | |
3241 | #endif | |
3242 | } | |
71400594 RS |
3243 | } |
3244 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
3245 | { | |
932d1a1b RS |
3246 | int nops; |
3247 | ||
3248 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
3249 | ignoring hazards generated by the first prev_nop_frag_since | |
3250 | instructions. */ | |
3251 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 3252 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 3253 | |
71400594 RS |
3254 | /* Enforce NOPS as a minimum. */ |
3255 | if (nops > prev_nop_frag_required) | |
3256 | prev_nop_frag_required = nops; | |
252b5132 | 3257 | |
71400594 RS |
3258 | if (prev_nop_frag_holds == prev_nop_frag_required) |
3259 | { | |
3260 | /* Settle for the current number of nops. Update the history | |
3261 | accordingly (for the benefit of any future .set reorder code). */ | |
3262 | prev_nop_frag = NULL; | |
3263 | insert_into_history (prev_nop_frag_since, | |
3264 | prev_nop_frag_holds, NOP_INSN); | |
3265 | } | |
3266 | else | |
3267 | { | |
3268 | /* Allow this instruction to replace one of the nops that was | |
3269 | tentatively added to prev_nop_frag. */ | |
3270 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
3271 | prev_nop_frag_holds--; | |
3272 | prev_nop_frag_since++; | |
252b5132 RH |
3273 | } |
3274 | } | |
3275 | ||
58e2ea4d MR |
3276 | #ifdef OBJ_ELF |
3277 | /* The value passed to dwarf2_emit_insn is the distance between | |
3278 | the beginning of the current instruction and the address that | |
3279 | should be recorded in the debug tables. For MIPS16 debug info | |
3280 | we want to use ISA-encoded addresses, so we pass -1 for an | |
3281 | address higher by one than the current. */ | |
3282 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
3283 | #endif | |
3284 | ||
895921c9 | 3285 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
3286 | if (history[0].frag) |
3287 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 3288 | |
4d7206a2 | 3289 | if (address_expr |
0b25d3e6 | 3290 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
3291 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
3292 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
3293 | && mips_relax_branch | |
3294 | /* Don't try branch relaxation within .set nomacro, or within | |
3295 | .set noat if we use $at for PIC computations. If it turns | |
3296 | out that the branch was out-of-range, we'll get an error. */ | |
3297 | && !mips_opts.warn_about_macros | |
741fe287 | 3298 | && (mips_opts.at || mips_pic == NO_PIC) |
d455268f MR |
3299 | /* Don't relax BPOSGE32/64 as they have no complementing branches. */ |
3300 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)) | |
4a6a3df4 AO |
3301 | && !mips_opts.mips16) |
3302 | { | |
895921c9 | 3303 | relaxed_branch = TRUE; |
1e915849 RS |
3304 | add_relaxed_insn (ip, (relaxed_branch_length |
3305 | (NULL, NULL, | |
3306 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
3307 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
3308 | : 0)), 4, | |
3309 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
3310 | (AT, |
3311 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
3312 | pinfo & INSN_COND_BRANCH_LIKELY, |
3313 | pinfo & INSN_WRITE_GPR_31, | |
3314 | 0), | |
3315 | address_expr->X_add_symbol, | |
3316 | address_expr->X_add_number); | |
4a6a3df4 AO |
3317 | *reloc_type = BFD_RELOC_UNUSED; |
3318 | } | |
3319 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
3320 | { |
3321 | /* We need to set up a variant frag. */ | |
9c2799c2 | 3322 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
3323 | add_relaxed_insn (ip, 4, 0, |
3324 | RELAX_MIPS16_ENCODE | |
3325 | (*reloc_type - BFD_RELOC_UNUSED, | |
3326 | mips16_small, mips16_ext, | |
3327 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
3328 | history[0].mips16_absolute_jump_p), | |
3329 | make_expr_symbol (address_expr), 0); | |
252b5132 | 3330 | } |
252b5132 RH |
3331 | else if (mips_opts.mips16 |
3332 | && ! ip->use_extend | |
f6688943 | 3333 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 3334 | { |
b8ee1a6e DU |
3335 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
3336 | /* Make sure there is enough room to swap this instruction with | |
3337 | a following jump instruction. */ | |
3338 | frag_grow (6); | |
1e915849 | 3339 | add_fixed_insn (ip); |
252b5132 RH |
3340 | } |
3341 | else | |
3342 | { | |
3343 | if (mips_opts.mips16 | |
3344 | && mips_opts.noreorder | |
3345 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
3346 | as_warn (_("extended instruction in delay slot")); | |
3347 | ||
4d7206a2 RS |
3348 | if (mips_relax.sequence) |
3349 | { | |
3350 | /* If we've reached the end of this frag, turn it into a variant | |
3351 | frag and record the information for the instructions we've | |
3352 | written so far. */ | |
3353 | if (frag_room () < 4) | |
3354 | relax_close_frag (); | |
3355 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
3356 | } | |
3357 | ||
584892a6 RS |
3358 | if (mips_relax.sequence != 2) |
3359 | mips_macro_warning.sizes[0] += 4; | |
3360 | if (mips_relax.sequence != 1) | |
3361 | mips_macro_warning.sizes[1] += 4; | |
3362 | ||
1e915849 RS |
3363 | if (mips_opts.mips16) |
3364 | { | |
3365 | ip->fixed_p = 1; | |
3366 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
3367 | } | |
3368 | add_fixed_insn (ip); | |
252b5132 RH |
3369 | } |
3370 | ||
9fe77896 | 3371 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3372 | { |
9fe77896 RS |
3373 | reloc_howto_type *howto; |
3374 | int i; | |
34ce925e | 3375 | |
9fe77896 RS |
3376 | /* In a compound relocation, it is the final (outermost) |
3377 | operator that determines the relocated field. */ | |
3378 | for (i = 1; i < 3; i++) | |
3379 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3380 | break; | |
34ce925e | 3381 | |
9fe77896 RS |
3382 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
3383 | if (howto == NULL) | |
3384 | { | |
3385 | /* To reproduce this failure try assembling gas/testsuites/ | |
3386 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3387 | assembler. */ | |
3388 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3389 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3390 | } | |
23fce1e3 | 3391 | |
9fe77896 RS |
3392 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3393 | bfd_get_reloc_size (howto), | |
3394 | address_expr, | |
3395 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3396 | reloc_type[0]); | |
3397 | ||
3398 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
3399 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3400 | && ip->fixp[0]->fx_addsy) | |
3401 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3402 | ||
3403 | /* These relocations can have an addend that won't fit in | |
3404 | 4 octets for 64bit assembly. */ | |
3405 | if (HAVE_64BIT_GPRS | |
3406 | && ! howto->partial_inplace | |
3407 | && (reloc_type[0] == BFD_RELOC_16 | |
3408 | || reloc_type[0] == BFD_RELOC_32 | |
3409 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
3410 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
3411 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3412 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3413 | || reloc_type[0] == BFD_RELOC_64 | |
3414 | || reloc_type[0] == BFD_RELOC_CTOR | |
3415 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3416 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3417 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3418 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3419 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
3420 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
3421 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
3422 | || hi16_reloc_p (reloc_type[0]) | |
3423 | || lo16_reloc_p (reloc_type[0]))) | |
3424 | ip->fixp[0]->fx_no_overflow = 1; | |
3425 | ||
3426 | if (mips_relax.sequence) | |
3427 | { | |
3428 | if (mips_relax.first_fixup == 0) | |
3429 | mips_relax.first_fixup = ip->fixp[0]; | |
3430 | } | |
3431 | else if (reloc_needs_lo_p (*reloc_type)) | |
3432 | { | |
3433 | struct mips_hi_fixup *hi_fixup; | |
3434 | ||
3435 | /* Reuse the last entry if it already has a matching %lo. */ | |
3436 | hi_fixup = mips_hi_fixup_list; | |
3437 | if (hi_fixup == 0 | |
3438 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 3439 | { |
9fe77896 RS |
3440 | hi_fixup = ((struct mips_hi_fixup *) |
3441 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3442 | hi_fixup->next = mips_hi_fixup_list; | |
3443 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 3444 | } |
9fe77896 RS |
3445 | hi_fixup->fixp = ip->fixp[0]; |
3446 | hi_fixup->seg = now_seg; | |
3447 | } | |
252b5132 | 3448 | |
9fe77896 RS |
3449 | /* Add fixups for the second and third relocations, if given. |
3450 | Note that the ABI allows the second relocation to be | |
3451 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3452 | moment we only use RSS_UNDEF, but we could add support | |
3453 | for the others if it ever becomes necessary. */ | |
3454 | for (i = 1; i < 3; i++) | |
3455 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3456 | { | |
3457 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
3458 | ip->fixp[0]->fx_size, NULL, 0, | |
3459 | FALSE, reloc_type[i]); | |
f6688943 | 3460 | |
9fe77896 RS |
3461 | /* Use fx_tcbit to mark compound relocs. */ |
3462 | ip->fixp[0]->fx_tcbit = 1; | |
3463 | ip->fixp[i]->fx_tcbit = 1; | |
3464 | } | |
252b5132 | 3465 | } |
1e915849 | 3466 | install_insn (ip); |
252b5132 RH |
3467 | |
3468 | /* Update the register mask information. */ | |
4c260379 RS |
3469 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
3470 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 3471 | |
4d7206a2 | 3472 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3473 | { |
3474 | /* Filling the branch delay slot is more complex. We try to | |
3475 | switch the branch with the previous instruction, which we can | |
3476 | do if the previous instruction does not set up a condition | |
3477 | that the branch tests and if the branch is not itself the | |
3478 | target of any branch. */ | |
3479 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3480 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3481 | { | |
3482 | if (mips_optimize < 2 | |
3483 | /* If we have seen .set volatile or .set nomove, don't | |
3484 | optimize. */ | |
3485 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3486 | /* We can't swap if the previous instruction's position |
3487 | is fixed. */ | |
3488 | || history[0].fixed_p | |
252b5132 RH |
3489 | /* If the previous previous insn was in a .set |
3490 | noreorder, we can't swap. Actually, the MIPS | |
3491 | assembler will swap in this situation. However, gcc | |
3492 | configured -with-gnu-as will generate code like | |
3493 | .set noreorder | |
3494 | lw $4,XXX | |
3495 | .set reorder | |
3496 | INSN | |
3497 | bne $4,$0,foo | |
3498 | in which we can not swap the bne and INSN. If gcc is | |
3499 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3500 | .set pseudo-ops. */ |
47e39b9d | 3501 | || history[1].noreorder_p |
252b5132 RH |
3502 | /* If the branch is itself the target of a branch, we |
3503 | can not swap. We cheat on this; all we check for is | |
3504 | whether there is a label on this instruction. If | |
3505 | there are any branches to anything other than a | |
3506 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3507 | || si->label_list != NULL |
895921c9 MR |
3508 | /* If the previous instruction is in a variant frag |
3509 | other than this branch's one, we cannot do the swap. | |
3510 | This does not apply to the mips16, which uses variant | |
3511 | frags for different purposes. */ | |
252b5132 | 3512 | || (! mips_opts.mips16 |
895921c9 | 3513 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3514 | /* Check for conflicts between the branch and the instructions |
3515 | before the candidate delay slot. */ | |
932d1a1b | 3516 | || nops_for_insn (0, history + 1, ip) > 0 |
71400594 RS |
3517 | /* Check for conflicts between the swapped sequence and the |
3518 | target of the branch. */ | |
932d1a1b | 3519 | || nops_for_sequence (2, 0, history + 1, ip, history) > 0 |
252b5132 RH |
3520 | /* We do not swap with a trap instruction, since it |
3521 | complicates trap handlers to have the trap | |
3522 | instruction be in a delay slot. */ | |
3523 | || (prev_pinfo & INSN_TRAP) | |
3524 | /* If the branch reads a register that the previous | |
3525 | instruction sets, we can not swap. */ | |
4c260379 | 3526 | || (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0 |
252b5132 | 3527 | /* If the branch writes a register that the previous |
4c260379 RS |
3528 | instruction sets, we can not swap. */ |
3529 | || (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0 | |
252b5132 | 3530 | /* If the branch writes a register that the previous |
4c260379 RS |
3531 | instruction reads, we can not swap. */ |
3532 | || (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0 | |
252b5132 RH |
3533 | /* If one instruction sets a condition code and the |
3534 | other one uses a condition code, we can not swap. */ | |
3535 | || ((pinfo & INSN_READ_COND_CODE) | |
3536 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3537 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3538 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3539 | /* If the previous instruction uses the PC, we can not | |
3540 | swap. */ | |
3541 | || (mips_opts.mips16 | |
3542 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3543 | /* If the previous instruction had a fixup in mips16 |
3544 | mode, we can not swap. This normally means that the | |
3545 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3546 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3547 | /* If the previous instruction is a sync, sync.l, or |
3548 | sync.p, we can not swap. */ | |
6a32d874 CM |
3549 | || (prev_pinfo & INSN_SYNC) |
3550 | /* If the previous instruction is an ERET or | |
3551 | DERET, avoid the swap. */ | |
3552 | || (history[0].insn_opcode == INSN_ERET) | |
3553 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3554 | { |
29024861 DU |
3555 | if (mips_opts.mips16 |
3556 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3557 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3558 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3559 | { |
3560 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3561 | ip->insn_opcode |= 0x0080; | |
ceb94aa5 | 3562 | find_altered_mips16_opcode (ip); |
29024861 DU |
3563 | install_insn (ip); |
3564 | insert_into_history (0, 1, ip); | |
3565 | } | |
3566 | else | |
3567 | { | |
3568 | /* We could do even better for unconditional branches to | |
3569 | portions of this object file; we could pick up the | |
3570 | instruction at the destination, put it in the delay | |
3571 | slot, and bump the destination address. */ | |
3572 | insert_into_history (0, 1, ip); | |
3573 | emit_nop (); | |
3574 | } | |
3575 | ||
dd22970f ILT |
3576 | if (mips_relax.sequence) |
3577 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3578 | } |
3579 | else | |
3580 | { | |
3581 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3582 | struct mips_cl_insn delay = history[0]; |
3583 | if (mips_opts.mips16) | |
252b5132 | 3584 | { |
b8ee1a6e DU |
3585 | know (delay.frag == ip->frag); |
3586 | move_insn (ip, delay.frag, delay.where); | |
3587 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3588 | } |
3589 | else if (relaxed_branch) | |
3590 | { | |
3591 | /* Add the delay slot instruction to the end of the | |
3592 | current frag and shrink the fixed part of the | |
3593 | original frag. If the branch occupies the tail of | |
3594 | the latter, move it backwards to cover the gap. */ | |
3595 | delay.frag->fr_fix -= 4; | |
3596 | if (delay.frag == ip->frag) | |
3597 | move_insn (ip, ip->frag, ip->where - 4); | |
3598 | add_fixed_insn (&delay); | |
252b5132 RH |
3599 | } |
3600 | else | |
3601 | { | |
1e915849 RS |
3602 | move_insn (&delay, ip->frag, ip->where); |
3603 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3604 | } |
1e915849 RS |
3605 | history[0] = *ip; |
3606 | delay.fixed_p = 1; | |
3607 | insert_into_history (0, 1, &delay); | |
252b5132 | 3608 | } |
252b5132 RH |
3609 | } |
3610 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3611 | { | |
3612 | /* We don't yet optimize a branch likely. What we should do | |
3613 | is look at the target, copy the instruction found there | |
3614 | into the delay slot, and increment the branch to jump to | |
3615 | the next instruction. */ | |
1e915849 | 3616 | insert_into_history (0, 1, ip); |
252b5132 | 3617 | emit_nop (); |
252b5132 RH |
3618 | } |
3619 | else | |
1e915849 | 3620 | insert_into_history (0, 1, ip); |
252b5132 | 3621 | } |
1e915849 RS |
3622 | else |
3623 | insert_into_history (0, 1, ip); | |
252b5132 | 3624 | |
13408f1e RS |
3625 | /* If we have just completed an unconditional branch, clear the history. */ |
3626 | if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3627 | || (mips_opts.mips16 | |
3628 | && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH))) | |
3629 | mips_no_prev_insn (); | |
3630 | ||
252b5132 RH |
3631 | /* We just output an insn, so the next one doesn't have a label. */ |
3632 | mips_clear_insn_labels (); | |
252b5132 RH |
3633 | } |
3634 | ||
7d10b47d | 3635 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3636 | |
3637 | static void | |
7d10b47d | 3638 | mips_no_prev_insn (void) |
252b5132 | 3639 | { |
7d10b47d RS |
3640 | prev_nop_frag = NULL; |
3641 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3642 | mips_clear_insn_labels (); |
3643 | } | |
3644 | ||
7d10b47d RS |
3645 | /* This function must be called before we emit something other than |
3646 | instructions. It is like mips_no_prev_insn except that it inserts | |
3647 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3648 | |
7d10b47d RS |
3649 | void |
3650 | mips_emit_delays (void) | |
252b5132 RH |
3651 | { |
3652 | if (! mips_opts.noreorder) | |
3653 | { | |
932d1a1b | 3654 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
3655 | if (nops > 0) |
3656 | { | |
7d10b47d RS |
3657 | while (nops-- > 0) |
3658 | add_fixed_insn (NOP_INSN); | |
3659 | mips_move_labels (); | |
3660 | } | |
3661 | } | |
3662 | mips_no_prev_insn (); | |
3663 | } | |
3664 | ||
3665 | /* Start a (possibly nested) noreorder block. */ | |
3666 | ||
3667 | static void | |
3668 | start_noreorder (void) | |
3669 | { | |
3670 | if (mips_opts.noreorder == 0) | |
3671 | { | |
3672 | unsigned int i; | |
3673 | int nops; | |
3674 | ||
3675 | /* None of the instructions before the .set noreorder can be moved. */ | |
3676 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3677 | history[i].fixed_p = 1; | |
3678 | ||
3679 | /* Insert any nops that might be needed between the .set noreorder | |
3680 | block and the previous instructions. We will later remove any | |
3681 | nops that turn out not to be needed. */ | |
932d1a1b | 3682 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
3683 | if (nops > 0) |
3684 | { | |
3685 | if (mips_optimize != 0) | |
252b5132 RH |
3686 | { |
3687 | /* Record the frag which holds the nop instructions, so | |
3688 | that we can remove them if we don't need them. */ | |
3689 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3690 | prev_nop_frag = frag_now; | |
3691 | prev_nop_frag_holds = nops; | |
3692 | prev_nop_frag_required = 0; | |
3693 | prev_nop_frag_since = 0; | |
3694 | } | |
3695 | ||
3696 | for (; nops > 0; --nops) | |
1e915849 | 3697 | add_fixed_insn (NOP_INSN); |
252b5132 | 3698 | |
7d10b47d RS |
3699 | /* Move on to a new frag, so that it is safe to simply |
3700 | decrease the size of prev_nop_frag. */ | |
3701 | frag_wane (frag_now); | |
3702 | frag_new (0); | |
404a8071 | 3703 | mips_move_labels (); |
252b5132 | 3704 | } |
7d10b47d RS |
3705 | mips16_mark_labels (); |
3706 | mips_clear_insn_labels (); | |
252b5132 | 3707 | } |
7d10b47d RS |
3708 | mips_opts.noreorder++; |
3709 | mips_any_noreorder = 1; | |
3710 | } | |
252b5132 | 3711 | |
7d10b47d | 3712 | /* End a nested noreorder block. */ |
252b5132 | 3713 | |
7d10b47d RS |
3714 | static void |
3715 | end_noreorder (void) | |
3716 | { | |
6a32d874 | 3717 | |
7d10b47d RS |
3718 | mips_opts.noreorder--; |
3719 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3720 | { | |
3721 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3722 | handling nop insertion the .set reorder way. */ | |
3723 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3724 | * (mips_opts.mips16 ? 2 : 4)); | |
3725 | insert_into_history (prev_nop_frag_since, | |
3726 | prev_nop_frag_required, NOP_INSN); | |
3727 | prev_nop_frag = NULL; | |
3728 | } | |
252b5132 RH |
3729 | } |
3730 | ||
584892a6 RS |
3731 | /* Set up global variables for the start of a new macro. */ |
3732 | ||
3733 | static void | |
3734 | macro_start (void) | |
3735 | { | |
3736 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3737 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3738 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3739 | & (INSN_UNCOND_BRANCH_DELAY |
3740 | | INSN_COND_BRANCH_DELAY | |
3741 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3742 | } | |
3743 | ||
3744 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3745 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3746 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3747 | ||
3748 | static const char * | |
3749 | macro_warning (relax_substateT subtype) | |
3750 | { | |
3751 | if (subtype & RELAX_DELAY_SLOT) | |
3752 | return _("Macro instruction expanded into multiple instructions" | |
3753 | " in a branch delay slot"); | |
3754 | else if (subtype & RELAX_NOMACRO) | |
3755 | return _("Macro instruction expanded into multiple instructions"); | |
3756 | else | |
3757 | return 0; | |
3758 | } | |
3759 | ||
3760 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3761 | ||
3762 | static void | |
3763 | macro_end (void) | |
3764 | { | |
3765 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3766 | { | |
3767 | relax_substateT subtype; | |
3768 | ||
3769 | /* Set up the relaxation warning flags. */ | |
3770 | subtype = 0; | |
3771 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3772 | subtype |= RELAX_SECOND_LONGER; | |
3773 | if (mips_opts.warn_about_macros) | |
3774 | subtype |= RELAX_NOMACRO; | |
3775 | if (mips_macro_warning.delay_slot_p) | |
3776 | subtype |= RELAX_DELAY_SLOT; | |
3777 | ||
3778 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3779 | { | |
3780 | /* Either the macro has a single implementation or both | |
3781 | implementations are longer than 4 bytes. Emit the | |
3782 | warning now. */ | |
3783 | const char *msg = macro_warning (subtype); | |
3784 | if (msg != 0) | |
520725ea | 3785 | as_warn ("%s", msg); |
584892a6 RS |
3786 | } |
3787 | else | |
3788 | { | |
3789 | /* One implementation might need a warning but the other | |
3790 | definitely doesn't. */ | |
3791 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3792 | } | |
3793 | } | |
3794 | } | |
3795 | ||
6e1304d8 RS |
3796 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3797 | The first argument in *ARGS will be either the code for a single | |
3798 | relocation or -1 followed by the three codes that make up a | |
3799 | composite relocation. */ | |
3800 | ||
3801 | static void | |
3802 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3803 | { | |
3804 | int i, next; | |
3805 | ||
3806 | next = va_arg (*args, int); | |
3807 | if (next >= 0) | |
3808 | r[0] = (bfd_reloc_code_real_type) next; | |
3809 | else | |
3810 | for (i = 0; i < 3; i++) | |
3811 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3812 | } | |
3813 | ||
252b5132 RH |
3814 | /* Build an instruction created by a macro expansion. This is passed |
3815 | a pointer to the count of instructions created so far, an | |
3816 | expression, the name of the instruction to build, an operand format | |
3817 | string, and corresponding arguments. */ | |
3818 | ||
252b5132 | 3819 | static void |
67c0d1eb | 3820 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3821 | { |
1e915849 | 3822 | const struct mips_opcode *mo; |
252b5132 | 3823 | struct mips_cl_insn insn; |
f6688943 | 3824 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3825 | va_list args; |
252b5132 | 3826 | |
252b5132 | 3827 | va_start (args, fmt); |
252b5132 | 3828 | |
252b5132 RH |
3829 | if (mips_opts.mips16) |
3830 | { | |
03ea81db | 3831 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3832 | va_end (args); |
3833 | return; | |
3834 | } | |
3835 | ||
f6688943 TS |
3836 | r[0] = BFD_RELOC_UNUSED; |
3837 | r[1] = BFD_RELOC_UNUSED; | |
3838 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3839 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3840 | gas_assert (mo); |
3841 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3842 | |
8b082fb1 TS |
3843 | while (1) |
3844 | { | |
3845 | /* Search until we get a match for NAME. It is assumed here that | |
3846 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3847 | if (strcmp (fmt, mo->args) == 0 | |
3848 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3849 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3850 | break; |
3851 | ||
1e915849 | 3852 | ++mo; |
9c2799c2 NC |
3853 | gas_assert (mo->name); |
3854 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3855 | } |
3856 | ||
1e915849 | 3857 | create_insn (&insn, mo); |
252b5132 RH |
3858 | for (;;) |
3859 | { | |
3860 | switch (*fmt++) | |
3861 | { | |
3862 | case '\0': | |
3863 | break; | |
3864 | ||
3865 | case ',': | |
3866 | case '(': | |
3867 | case ')': | |
3868 | continue; | |
3869 | ||
5f74bc13 CD |
3870 | case '+': |
3871 | switch (*fmt++) | |
3872 | { | |
3873 | case 'A': | |
3874 | case 'E': | |
bf12938e | 3875 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3876 | continue; |
3877 | ||
3878 | case 'B': | |
3879 | case 'F': | |
3880 | /* Note that in the macro case, these arguments are already | |
3881 | in MSB form. (When handling the instruction in the | |
3882 | non-macro case, these arguments are sizes from which | |
3883 | MSB values must be calculated.) */ | |
bf12938e | 3884 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3885 | continue; |
3886 | ||
3887 | case 'C': | |
3888 | case 'G': | |
3889 | case 'H': | |
3890 | /* Note that in the macro case, these arguments are already | |
3891 | in MSBD form. (When handling the instruction in the | |
3892 | non-macro case, these arguments are sizes from which | |
3893 | MSBD values must be calculated.) */ | |
bf12938e | 3894 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3895 | continue; |
3896 | ||
dd3cbb7e NC |
3897 | case 'Q': |
3898 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3899 | continue; | |
3900 | ||
5f74bc13 CD |
3901 | default: |
3902 | internalError (); | |
3903 | } | |
3904 | continue; | |
3905 | ||
8b082fb1 TS |
3906 | case '2': |
3907 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3908 | continue; | |
3909 | ||
252b5132 RH |
3910 | case 't': |
3911 | case 'w': | |
3912 | case 'E': | |
bf12938e | 3913 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3914 | continue; |
3915 | ||
3916 | case 'c': | |
bf12938e | 3917 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3918 | continue; |
3919 | ||
252b5132 RH |
3920 | case 'T': |
3921 | case 'W': | |
bf12938e | 3922 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3923 | continue; |
3924 | ||
3925 | case 'd': | |
3926 | case 'G': | |
af7ee8bf | 3927 | case 'K': |
bf12938e | 3928 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3929 | continue; |
3930 | ||
4372b673 NC |
3931 | case 'U': |
3932 | { | |
3933 | int tmp = va_arg (args, int); | |
3934 | ||
bf12938e RS |
3935 | INSERT_OPERAND (RT, insn, tmp); |
3936 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3937 | continue; |
4372b673 NC |
3938 | } |
3939 | ||
252b5132 RH |
3940 | case 'V': |
3941 | case 'S': | |
bf12938e | 3942 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3943 | continue; |
3944 | ||
3945 | case 'z': | |
3946 | continue; | |
3947 | ||
3948 | case '<': | |
bf12938e | 3949 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3950 | continue; |
3951 | ||
3952 | case 'D': | |
bf12938e | 3953 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3954 | continue; |
3955 | ||
3956 | case 'B': | |
bf12938e | 3957 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3958 | continue; |
3959 | ||
4372b673 | 3960 | case 'J': |
bf12938e | 3961 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3962 | continue; |
3963 | ||
252b5132 | 3964 | case 'q': |
bf12938e | 3965 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3966 | continue; |
3967 | ||
3968 | case 'b': | |
3969 | case 's': | |
3970 | case 'r': | |
3971 | case 'v': | |
bf12938e | 3972 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3973 | continue; |
3974 | ||
3975 | case 'i': | |
3976 | case 'j': | |
6e1304d8 | 3977 | macro_read_relocs (&args, r); |
9c2799c2 | 3978 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
3979 | || *r == BFD_RELOC_MIPS_HIGHER |
3980 | || *r == BFD_RELOC_HI16_S | |
3981 | || *r == BFD_RELOC_LO16 | |
3982 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
3983 | continue; | |
3984 | ||
3985 | case 'o': | |
3986 | macro_read_relocs (&args, r); | |
252b5132 RH |
3987 | continue; |
3988 | ||
3989 | case 'u': | |
6e1304d8 | 3990 | macro_read_relocs (&args, r); |
9c2799c2 | 3991 | gas_assert (ep != NULL |
90ecf173 MR |
3992 | && (ep->X_op == O_constant |
3993 | || (ep->X_op == O_symbol | |
3994 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
3995 | || *r == BFD_RELOC_HI16_S | |
3996 | || *r == BFD_RELOC_HI16 | |
3997 | || *r == BFD_RELOC_GPREL16 | |
3998 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3999 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4000 | continue; |
4001 | ||
4002 | case 'p': | |
9c2799c2 | 4003 | gas_assert (ep != NULL); |
bad36eac | 4004 | |
252b5132 RH |
4005 | /* |
4006 | * This allows macro() to pass an immediate expression for | |
4007 | * creating short branches without creating a symbol. | |
bad36eac DJ |
4008 | * |
4009 | * We don't allow branch relaxation for these branches, as | |
4010 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
4011 | */ |
4012 | if (ep->X_op == O_constant) | |
4013 | { | |
bad36eac DJ |
4014 | if ((ep->X_add_number & 3) != 0) |
4015 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4016 | (unsigned long) ep->X_add_number); | |
4017 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
4018 | as_bad (_("branch address range overflow (0x%lx)"), | |
4019 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
4020 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
4021 | ep = NULL; | |
4022 | } | |
4023 | else | |
0b25d3e6 | 4024 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
4025 | continue; |
4026 | ||
4027 | case 'a': | |
9c2799c2 | 4028 | gas_assert (ep != NULL); |
f6688943 | 4029 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
4030 | continue; |
4031 | ||
4032 | case 'C': | |
a9e24354 | 4033 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
4034 | continue; |
4035 | ||
d43b4baf | 4036 | case 'k': |
a9e24354 | 4037 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
4038 | continue; |
4039 | ||
252b5132 RH |
4040 | default: |
4041 | internalError (); | |
4042 | } | |
4043 | break; | |
4044 | } | |
4045 | va_end (args); | |
9c2799c2 | 4046 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4047 | |
4d7206a2 | 4048 | append_insn (&insn, ep, r); |
252b5132 RH |
4049 | } |
4050 | ||
4051 | static void | |
67c0d1eb | 4052 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 4053 | va_list *args) |
252b5132 | 4054 | { |
1e915849 | 4055 | struct mips_opcode *mo; |
252b5132 | 4056 | struct mips_cl_insn insn; |
f6688943 TS |
4057 | bfd_reloc_code_real_type r[3] |
4058 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4059 | |
1e915849 | 4060 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
4061 | gas_assert (mo); |
4062 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 4063 | |
1e915849 | 4064 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 4065 | { |
1e915849 | 4066 | ++mo; |
9c2799c2 NC |
4067 | gas_assert (mo->name); |
4068 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
4069 | } |
4070 | ||
1e915849 | 4071 | create_insn (&insn, mo); |
252b5132 RH |
4072 | for (;;) |
4073 | { | |
4074 | int c; | |
4075 | ||
4076 | c = *fmt++; | |
4077 | switch (c) | |
4078 | { | |
4079 | case '\0': | |
4080 | break; | |
4081 | ||
4082 | case ',': | |
4083 | case '(': | |
4084 | case ')': | |
4085 | continue; | |
4086 | ||
4087 | case 'y': | |
4088 | case 'w': | |
03ea81db | 4089 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
4090 | continue; |
4091 | ||
4092 | case 'x': | |
4093 | case 'v': | |
03ea81db | 4094 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
4095 | continue; |
4096 | ||
4097 | case 'z': | |
03ea81db | 4098 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
4099 | continue; |
4100 | ||
4101 | case 'Z': | |
03ea81db | 4102 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
4103 | continue; |
4104 | ||
4105 | case '0': | |
4106 | case 'S': | |
4107 | case 'P': | |
4108 | case 'R': | |
4109 | continue; | |
4110 | ||
4111 | case 'X': | |
03ea81db | 4112 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
4113 | continue; |
4114 | ||
4115 | case 'Y': | |
4116 | { | |
4117 | int regno; | |
4118 | ||
03ea81db | 4119 | regno = va_arg (*args, int); |
252b5132 | 4120 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 4121 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
4122 | } |
4123 | continue; | |
4124 | ||
4125 | case '<': | |
4126 | case '>': | |
4127 | case '4': | |
4128 | case '5': | |
4129 | case 'H': | |
4130 | case 'W': | |
4131 | case 'D': | |
4132 | case 'j': | |
4133 | case '8': | |
4134 | case 'V': | |
4135 | case 'C': | |
4136 | case 'U': | |
4137 | case 'k': | |
4138 | case 'K': | |
4139 | case 'p': | |
4140 | case 'q': | |
4141 | { | |
9c2799c2 | 4142 | gas_assert (ep != NULL); |
252b5132 RH |
4143 | |
4144 | if (ep->X_op != O_constant) | |
874e8986 | 4145 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
4146 | else |
4147 | { | |
b34976b6 AM |
4148 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
4149 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 4150 | &insn.extend); |
252b5132 | 4151 | ep = NULL; |
f6688943 | 4152 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
4153 | } |
4154 | } | |
4155 | continue; | |
4156 | ||
4157 | case '6': | |
03ea81db | 4158 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
4159 | continue; |
4160 | } | |
4161 | ||
4162 | break; | |
4163 | } | |
4164 | ||
9c2799c2 | 4165 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4166 | |
4d7206a2 | 4167 | append_insn (&insn, ep, r); |
252b5132 RH |
4168 | } |
4169 | ||
2051e8c4 MR |
4170 | /* |
4171 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
4172 | * higher bits unset. | |
4173 | */ | |
9f872bbe | 4174 | static void |
2051e8c4 MR |
4175 | normalize_constant_expr (expressionS *ex) |
4176 | { | |
9ee2a2d4 | 4177 | if (ex->X_op == O_constant |
2051e8c4 MR |
4178 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
4179 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4180 | - 0x80000000); | |
4181 | } | |
4182 | ||
4183 | /* | |
4184 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
4185 | * all higher bits unset. | |
4186 | */ | |
4187 | static void | |
4188 | normalize_address_expr (expressionS *ex) | |
4189 | { | |
4190 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
4191 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
4192 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
4193 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4194 | - 0x80000000); | |
4195 | } | |
4196 | ||
438c16b8 TS |
4197 | /* |
4198 | * Generate a "jalr" instruction with a relocation hint to the called | |
4199 | * function. This occurs in NewABI PIC code. | |
4200 | */ | |
4201 | static void | |
67c0d1eb | 4202 | macro_build_jalr (expressionS *ep) |
438c16b8 | 4203 | { |
685736be | 4204 | char *f = NULL; |
b34976b6 | 4205 | |
1180b5a4 | 4206 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4207 | { |
cc3d92a5 | 4208 | frag_grow (8); |
f21f8242 AO |
4209 | f = frag_more (0); |
4210 | } | |
67c0d1eb | 4211 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4212 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4213 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4214 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4215 | } |
4216 | ||
252b5132 RH |
4217 | /* |
4218 | * Generate a "lui" instruction. | |
4219 | */ | |
4220 | static void | |
67c0d1eb | 4221 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4222 | { |
4223 | expressionS high_expr; | |
1e915849 | 4224 | const struct mips_opcode *mo; |
252b5132 | 4225 | struct mips_cl_insn insn; |
f6688943 TS |
4226 | bfd_reloc_code_real_type r[3] |
4227 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4228 | const char *name = "lui"; |
4229 | const char *fmt = "t,u"; | |
252b5132 | 4230 | |
9c2799c2 | 4231 | gas_assert (! mips_opts.mips16); |
252b5132 | 4232 | |
4d7206a2 | 4233 | high_expr = *ep; |
252b5132 RH |
4234 | |
4235 | if (high_expr.X_op == O_constant) | |
4236 | { | |
54f4ddb3 | 4237 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4238 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4239 | >> 16) & 0xffff; | |
f6688943 | 4240 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4241 | } |
78e1bb40 | 4242 | else |
252b5132 | 4243 | { |
9c2799c2 | 4244 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4245 | /* _gp_disp is a special case, used from s_cpload. |
4246 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4247 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4248 | || (! HAVE_NEWABI |
aa6975fb ILT |
4249 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4250 | || (! mips_in_shared | |
bbe506e8 TS |
4251 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4252 | "__gnu_local_gp") == 0)); | |
f6688943 | 4253 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4254 | } |
4255 | ||
1e915849 | 4256 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4257 | gas_assert (strcmp (name, mo->name) == 0); |
4258 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4259 | create_insn (&insn, mo); |
252b5132 | 4260 | |
bf12938e RS |
4261 | insn.insn_opcode = insn.insn_mo->match; |
4262 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4263 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4264 | { |
4265 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4266 | append_insn (&insn, NULL, r); |
252b5132 RH |
4267 | } |
4268 | else | |
4d7206a2 | 4269 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4270 | } |
4271 | ||
885add95 CD |
4272 | /* Generate a sequence of instructions to do a load or store from a constant |
4273 | offset off of a base register (breg) into/from a target register (treg), | |
4274 | using AT if necessary. */ | |
4275 | static void | |
67c0d1eb RS |
4276 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4277 | int treg, int breg, int dbl) | |
885add95 | 4278 | { |
9c2799c2 | 4279 | gas_assert (ep->X_op == O_constant); |
885add95 | 4280 | |
256ab948 | 4281 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4282 | if (!dbl) |
4283 | normalize_constant_expr (ep); | |
256ab948 | 4284 | |
67c1ffbe | 4285 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4286 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4287 | as_warn (_("operand overflow")); |
4288 | ||
4289 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4290 | { | |
4291 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4292 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4293 | } |
4294 | else | |
4295 | { | |
4296 | /* 32-bit offset, need multiple instructions and AT, like: | |
4297 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4298 | addu $tempreg,$tempreg,$breg | |
4299 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4300 | to handle the complete offset. */ | |
67c0d1eb RS |
4301 | macro_build_lui (ep, AT); |
4302 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4303 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4304 | |
741fe287 | 4305 | if (!mips_opts.at) |
8fc2e39e | 4306 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4307 | } |
4308 | } | |
4309 | ||
252b5132 RH |
4310 | /* set_at() |
4311 | * Generates code to set the $at register to true (one) | |
4312 | * if reg is less than the immediate expression. | |
4313 | */ | |
4314 | static void | |
67c0d1eb | 4315 | set_at (int reg, int unsignedp) |
252b5132 RH |
4316 | { |
4317 | if (imm_expr.X_op == O_constant | |
4318 | && imm_expr.X_add_number >= -0x8000 | |
4319 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4320 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4321 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4322 | else |
4323 | { | |
67c0d1eb RS |
4324 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4325 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4326 | } |
4327 | } | |
4328 | ||
4329 | /* Warn if an expression is not a constant. */ | |
4330 | ||
4331 | static void | |
17a2f251 | 4332 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4333 | { |
4334 | if (ex->X_op == O_big) | |
4335 | as_bad (_("unsupported large constant")); | |
4336 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4337 | as_bad (_("Instruction %s requires absolute expression"), |
4338 | ip->insn_mo->name); | |
13757d0c | 4339 | |
9ee2a2d4 MR |
4340 | if (HAVE_32BIT_GPRS) |
4341 | normalize_constant_expr (ex); | |
252b5132 RH |
4342 | } |
4343 | ||
4344 | /* Count the leading zeroes by performing a binary chop. This is a | |
4345 | bulky bit of source, but performance is a LOT better for the | |
4346 | majority of values than a simple loop to count the bits: | |
4347 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4348 | if ((v) & (1 << (31 - lcnt))) | |
4349 | break; | |
4350 | However it is not code size friendly, and the gain will drop a bit | |
4351 | on certain cached systems. | |
4352 | */ | |
4353 | #define COUNT_TOP_ZEROES(v) \ | |
4354 | (((v) & ~0xffff) == 0 \ | |
4355 | ? ((v) & ~0xff) == 0 \ | |
4356 | ? ((v) & ~0xf) == 0 \ | |
4357 | ? ((v) & ~0x3) == 0 \ | |
4358 | ? ((v) & ~0x1) == 0 \ | |
4359 | ? !(v) \ | |
4360 | ? 32 \ | |
4361 | : 31 \ | |
4362 | : 30 \ | |
4363 | : ((v) & ~0x7) == 0 \ | |
4364 | ? 29 \ | |
4365 | : 28 \ | |
4366 | : ((v) & ~0x3f) == 0 \ | |
4367 | ? ((v) & ~0x1f) == 0 \ | |
4368 | ? 27 \ | |
4369 | : 26 \ | |
4370 | : ((v) & ~0x7f) == 0 \ | |
4371 | ? 25 \ | |
4372 | : 24 \ | |
4373 | : ((v) & ~0xfff) == 0 \ | |
4374 | ? ((v) & ~0x3ff) == 0 \ | |
4375 | ? ((v) & ~0x1ff) == 0 \ | |
4376 | ? 23 \ | |
4377 | : 22 \ | |
4378 | : ((v) & ~0x7ff) == 0 \ | |
4379 | ? 21 \ | |
4380 | : 20 \ | |
4381 | : ((v) & ~0x3fff) == 0 \ | |
4382 | ? ((v) & ~0x1fff) == 0 \ | |
4383 | ? 19 \ | |
4384 | : 18 \ | |
4385 | : ((v) & ~0x7fff) == 0 \ | |
4386 | ? 17 \ | |
4387 | : 16 \ | |
4388 | : ((v) & ~0xffffff) == 0 \ | |
4389 | ? ((v) & ~0xfffff) == 0 \ | |
4390 | ? ((v) & ~0x3ffff) == 0 \ | |
4391 | ? ((v) & ~0x1ffff) == 0 \ | |
4392 | ? 15 \ | |
4393 | : 14 \ | |
4394 | : ((v) & ~0x7ffff) == 0 \ | |
4395 | ? 13 \ | |
4396 | : 12 \ | |
4397 | : ((v) & ~0x3fffff) == 0 \ | |
4398 | ? ((v) & ~0x1fffff) == 0 \ | |
4399 | ? 11 \ | |
4400 | : 10 \ | |
4401 | : ((v) & ~0x7fffff) == 0 \ | |
4402 | ? 9 \ | |
4403 | : 8 \ | |
4404 | : ((v) & ~0xfffffff) == 0 \ | |
4405 | ? ((v) & ~0x3ffffff) == 0 \ | |
4406 | ? ((v) & ~0x1ffffff) == 0 \ | |
4407 | ? 7 \ | |
4408 | : 6 \ | |
4409 | : ((v) & ~0x7ffffff) == 0 \ | |
4410 | ? 5 \ | |
4411 | : 4 \ | |
4412 | : ((v) & ~0x3fffffff) == 0 \ | |
4413 | ? ((v) & ~0x1fffffff) == 0 \ | |
4414 | ? 3 \ | |
4415 | : 2 \ | |
4416 | : ((v) & ~0x7fffffff) == 0 \ | |
4417 | ? 1 \ | |
4418 | : 0) | |
4419 | ||
4420 | /* load_register() | |
67c1ffbe | 4421 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4422 | * an absolute expression value into a register. |
4423 | */ | |
4424 | static void | |
67c0d1eb | 4425 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4426 | { |
4427 | int freg; | |
4428 | expressionS hi32, lo32; | |
4429 | ||
4430 | if (ep->X_op != O_big) | |
4431 | { | |
9c2799c2 | 4432 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4433 | |
4434 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4435 | if (!dbl) |
4436 | normalize_constant_expr (ep); | |
256ab948 TS |
4437 | |
4438 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4439 | { |
4440 | /* We can handle 16 bit signed values with an addiu to | |
4441 | $zero. No need to ever use daddiu here, since $zero and | |
4442 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4443 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4444 | return; |
4445 | } | |
4446 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4447 | { | |
4448 | /* We can handle 16 bit unsigned values with an ori to | |
4449 | $zero. */ | |
67c0d1eb | 4450 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4451 | return; |
4452 | } | |
256ab948 | 4453 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4454 | { |
4455 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4456 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4457 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4458 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4459 | return; |
4460 | } | |
4461 | } | |
4462 | ||
4463 | /* The value is larger than 32 bits. */ | |
4464 | ||
2051e8c4 | 4465 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4466 | { |
55e08f71 NC |
4467 | char value[32]; |
4468 | ||
4469 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4470 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4471 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4472 | return; |
4473 | } | |
4474 | ||
4475 | if (ep->X_op != O_big) | |
4476 | { | |
4477 | hi32 = *ep; | |
4478 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4479 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4480 | hi32.X_add_number &= 0xffffffff; | |
4481 | lo32 = *ep; | |
4482 | lo32.X_add_number &= 0xffffffff; | |
4483 | } | |
4484 | else | |
4485 | { | |
9c2799c2 | 4486 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4487 | if (ep->X_add_number == 3) |
4488 | generic_bignum[3] = 0; | |
4489 | else if (ep->X_add_number > 4) | |
4490 | as_bad (_("Number larger than 64 bits")); | |
4491 | lo32.X_op = O_constant; | |
4492 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4493 | hi32.X_op = O_constant; | |
4494 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4495 | } | |
4496 | ||
4497 | if (hi32.X_add_number == 0) | |
4498 | freg = 0; | |
4499 | else | |
4500 | { | |
4501 | int shift, bit; | |
4502 | unsigned long hi, lo; | |
4503 | ||
956cd1d6 | 4504 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4505 | { |
4506 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4507 | { | |
67c0d1eb | 4508 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4509 | return; |
4510 | } | |
4511 | if (lo32.X_add_number & 0x80000000) | |
4512 | { | |
67c0d1eb | 4513 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4514 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4515 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4516 | return; |
4517 | } | |
4518 | } | |
252b5132 RH |
4519 | |
4520 | /* Check for 16bit shifted constant. We know that hi32 is | |
4521 | non-zero, so start the mask on the first bit of the hi32 | |
4522 | value. */ | |
4523 | shift = 17; | |
4524 | do | |
beae10d5 KH |
4525 | { |
4526 | unsigned long himask, lomask; | |
4527 | ||
4528 | if (shift < 32) | |
4529 | { | |
4530 | himask = 0xffff >> (32 - shift); | |
4531 | lomask = (0xffff << shift) & 0xffffffff; | |
4532 | } | |
4533 | else | |
4534 | { | |
4535 | himask = 0xffff << (shift - 32); | |
4536 | lomask = 0; | |
4537 | } | |
4538 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4539 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4540 | { | |
4541 | expressionS tmp; | |
4542 | ||
4543 | tmp.X_op = O_constant; | |
4544 | if (shift < 32) | |
4545 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4546 | | (lo32.X_add_number >> shift)); | |
4547 | else | |
4548 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4549 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4550 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4551 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4552 | return; |
4553 | } | |
f9419b05 | 4554 | ++shift; |
beae10d5 KH |
4555 | } |
4556 | while (shift <= (64 - 16)); | |
252b5132 RH |
4557 | |
4558 | /* Find the bit number of the lowest one bit, and store the | |
4559 | shifted value in hi/lo. */ | |
4560 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4561 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4562 | if (lo != 0) | |
4563 | { | |
4564 | bit = 0; | |
4565 | while ((lo & 1) == 0) | |
4566 | { | |
4567 | lo >>= 1; | |
4568 | ++bit; | |
4569 | } | |
4570 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4571 | hi >>= bit; | |
4572 | } | |
4573 | else | |
4574 | { | |
4575 | bit = 32; | |
4576 | while ((hi & 1) == 0) | |
4577 | { | |
4578 | hi >>= 1; | |
4579 | ++bit; | |
4580 | } | |
4581 | lo = hi; | |
4582 | hi = 0; | |
4583 | } | |
4584 | ||
4585 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4586 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4587 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4588 | { |
4589 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4590 | if (shift != 0) |
beae10d5 | 4591 | { |
252b5132 RH |
4592 | expressionS tmp; |
4593 | ||
4594 | /* This instruction will set the register to be all | |
4595 | ones. */ | |
beae10d5 KH |
4596 | tmp.X_op = O_constant; |
4597 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4598 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4599 | if (bit != 0) |
4600 | { | |
4601 | bit += shift; | |
67c0d1eb RS |
4602 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4603 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4604 | } |
67c0d1eb RS |
4605 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4606 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4607 | return; |
4608 | } | |
4609 | } | |
252b5132 RH |
4610 | |
4611 | /* Sign extend hi32 before calling load_register, because we can | |
4612 | generally get better code when we load a sign extended value. */ | |
4613 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4614 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4615 | load_register (reg, &hi32, 0); |
252b5132 RH |
4616 | freg = reg; |
4617 | } | |
4618 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4619 | { | |
4620 | if (freg != 0) | |
4621 | { | |
67c0d1eb | 4622 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4623 | freg = reg; |
4624 | } | |
4625 | } | |
4626 | else | |
4627 | { | |
4628 | expressionS mid16; | |
4629 | ||
956cd1d6 | 4630 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4631 | { |
67c0d1eb RS |
4632 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4633 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4634 | return; |
4635 | } | |
252b5132 RH |
4636 | |
4637 | if (freg != 0) | |
4638 | { | |
67c0d1eb | 4639 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4640 | freg = reg; |
4641 | } | |
4642 | mid16 = lo32; | |
4643 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4644 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4645 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4646 | freg = reg; |
4647 | } | |
4648 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4649 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4650 | } |
4651 | ||
269137b2 TS |
4652 | static inline void |
4653 | load_delay_nop (void) | |
4654 | { | |
4655 | if (!gpr_interlocks) | |
4656 | macro_build (NULL, "nop", ""); | |
4657 | } | |
4658 | ||
252b5132 RH |
4659 | /* Load an address into a register. */ |
4660 | ||
4661 | static void | |
67c0d1eb | 4662 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4663 | { |
252b5132 RH |
4664 | if (ep->X_op != O_constant |
4665 | && ep->X_op != O_symbol) | |
4666 | { | |
4667 | as_bad (_("expression too complex")); | |
4668 | ep->X_op = O_constant; | |
4669 | } | |
4670 | ||
4671 | if (ep->X_op == O_constant) | |
4672 | { | |
67c0d1eb | 4673 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4674 | return; |
4675 | } | |
4676 | ||
4677 | if (mips_pic == NO_PIC) | |
4678 | { | |
4679 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4680 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4681 | Otherwise we want |
4682 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4683 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4684 | If we have an addend, we always use the latter form. |
76b3015f | 4685 | |
d6bc6245 TS |
4686 | With 64bit address space and a usable $at we want |
4687 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4688 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4689 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4690 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4691 | dsll32 $reg,0 | |
3a482fd5 | 4692 | daddu $reg,$reg,$at |
76b3015f | 4693 | |
c03099e6 | 4694 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4695 | on superscalar processors. |
4696 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4697 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4698 | dsll $reg,16 | |
4699 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4700 | dsll $reg,16 | |
4701 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4702 | |
4703 | For GP relative symbols in 64bit address space we can use | |
4704 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4705 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4706 | { |
6caf9ef4 TS |
4707 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4708 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4709 | { | |
4710 | relax_start (ep->X_add_symbol); | |
4711 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4712 | mips_gp_register, BFD_RELOC_GPREL16); | |
4713 | relax_switch (); | |
4714 | } | |
d6bc6245 | 4715 | |
741fe287 | 4716 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4717 | { |
67c0d1eb RS |
4718 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4719 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4720 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4721 | BFD_RELOC_MIPS_HIGHER); | |
4722 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4723 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4724 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4725 | *used_at = 1; |
4726 | } | |
4727 | else | |
4728 | { | |
67c0d1eb RS |
4729 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4730 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4731 | BFD_RELOC_MIPS_HIGHER); | |
4732 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4733 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4734 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4735 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4736 | } |
6caf9ef4 TS |
4737 | |
4738 | if (mips_relax.sequence) | |
4739 | relax_end (); | |
d6bc6245 | 4740 | } |
252b5132 RH |
4741 | else |
4742 | { | |
d6bc6245 | 4743 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4744 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4745 | { |
4d7206a2 | 4746 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4747 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4748 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4749 | relax_switch (); |
d6bc6245 | 4750 | } |
67c0d1eb RS |
4751 | macro_build_lui (ep, reg); |
4752 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4753 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4754 | if (mips_relax.sequence) |
4755 | relax_end (); | |
d6bc6245 | 4756 | } |
252b5132 | 4757 | } |
0a44bf69 | 4758 | else if (!mips_big_got) |
252b5132 RH |
4759 | { |
4760 | expressionS ex; | |
4761 | ||
4762 | /* If this is a reference to an external symbol, we want | |
4763 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4764 | Otherwise we want | |
4765 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4766 | nop | |
4767 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4768 | If there is a constant, it must be added in after. |
4769 | ||
ed6fb7bd | 4770 | If we have NewABI, we want |
f5040a92 AO |
4771 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4772 | unless we're referencing a global symbol with a non-zero | |
4773 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4774 | if (HAVE_NEWABI) |
4775 | { | |
f5040a92 AO |
4776 | if (ep->X_add_number) |
4777 | { | |
4d7206a2 | 4778 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4779 | ep->X_add_number = 0; |
4d7206a2 | 4780 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4781 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4782 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4783 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4784 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4785 | ex.X_op = O_constant; | |
67c0d1eb | 4786 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4787 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4788 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4789 | relax_switch (); |
f5040a92 | 4790 | } |
67c0d1eb | 4791 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4792 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4793 | if (mips_relax.sequence) |
4794 | relax_end (); | |
ed6fb7bd SC |
4795 | } |
4796 | else | |
4797 | { | |
f5040a92 AO |
4798 | ex.X_add_number = ep->X_add_number; |
4799 | ep->X_add_number = 0; | |
67c0d1eb RS |
4800 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4801 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4802 | load_delay_nop (); |
4d7206a2 RS |
4803 | relax_start (ep->X_add_symbol); |
4804 | relax_switch (); | |
67c0d1eb | 4805 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4806 | BFD_RELOC_LO16); |
4d7206a2 | 4807 | relax_end (); |
ed6fb7bd | 4808 | |
f5040a92 AO |
4809 | if (ex.X_add_number != 0) |
4810 | { | |
4811 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4812 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4813 | ex.X_op = O_constant; | |
67c0d1eb | 4814 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4815 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4816 | } |
252b5132 RH |
4817 | } |
4818 | } | |
0a44bf69 | 4819 | else if (mips_big_got) |
252b5132 RH |
4820 | { |
4821 | expressionS ex; | |
252b5132 RH |
4822 | |
4823 | /* This is the large GOT case. If this is a reference to an | |
4824 | external symbol, we want | |
4825 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4826 | addu $reg,$reg,$gp | |
4827 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4828 | |
4829 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4830 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4831 | nop | |
4832 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4833 | If there is a constant, it must be added in after. |
f5040a92 AO |
4834 | |
4835 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4836 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4837 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4838 | */ |
438c16b8 TS |
4839 | if (HAVE_NEWABI) |
4840 | { | |
4d7206a2 | 4841 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4842 | ep->X_add_number = 0; |
4d7206a2 | 4843 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4844 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4846 | reg, reg, mips_gp_register); | |
4847 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4848 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4849 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4850 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4851 | else if (ex.X_add_number) | |
4852 | { | |
4853 | ex.X_op = O_constant; | |
67c0d1eb RS |
4854 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4855 | BFD_RELOC_LO16); | |
f5040a92 AO |
4856 | } |
4857 | ||
4858 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4859 | relax_switch (); |
67c0d1eb | 4860 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4861 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4862 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4863 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4864 | relax_end (); |
438c16b8 | 4865 | } |
252b5132 | 4866 | else |
438c16b8 | 4867 | { |
f5040a92 AO |
4868 | ex.X_add_number = ep->X_add_number; |
4869 | ep->X_add_number = 0; | |
4d7206a2 | 4870 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4871 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4872 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4873 | reg, reg, mips_gp_register); | |
4874 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4875 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4876 | relax_switch (); |
4877 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4878 | { |
4879 | /* We need a nop before loading from $gp. This special | |
4880 | check is required because the lui which starts the main | |
4881 | instruction stream does not refer to $gp, and so will not | |
4882 | insert the nop which may be required. */ | |
67c0d1eb | 4883 | macro_build (NULL, "nop", ""); |
438c16b8 | 4884 | } |
67c0d1eb | 4885 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4886 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4887 | load_delay_nop (); |
67c0d1eb | 4888 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4889 | BFD_RELOC_LO16); |
4d7206a2 | 4890 | relax_end (); |
438c16b8 | 4891 | |
f5040a92 AO |
4892 | if (ex.X_add_number != 0) |
4893 | { | |
4894 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4895 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4896 | ex.X_op = O_constant; | |
67c0d1eb RS |
4897 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4898 | BFD_RELOC_LO16); | |
f5040a92 | 4899 | } |
252b5132 RH |
4900 | } |
4901 | } | |
252b5132 RH |
4902 | else |
4903 | abort (); | |
8fc2e39e | 4904 | |
741fe287 | 4905 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4906 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4907 | } |
4908 | ||
ea1fb5dc RS |
4909 | /* Move the contents of register SOURCE into register DEST. */ |
4910 | ||
4911 | static void | |
67c0d1eb | 4912 | move_register (int dest, int source) |
ea1fb5dc | 4913 | { |
67c0d1eb RS |
4914 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4915 | dest, source, 0); | |
ea1fb5dc RS |
4916 | } |
4917 | ||
4d7206a2 | 4918 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4919 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4920 | The two alternatives are: | |
4d7206a2 RS |
4921 | |
4922 | Global symbol Local sybmol | |
4923 | ------------- ------------ | |
4924 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4925 | ... ... | |
4926 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4927 | ||
4928 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4929 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4930 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4931 | |
4932 | static void | |
67c0d1eb | 4933 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4934 | { |
4935 | expressionS global; | |
4936 | ||
4937 | global = *local; | |
4938 | global.X_add_number = 0; | |
4939 | ||
4940 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4941 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4942 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4943 | relax_switch (); |
67c0d1eb RS |
4944 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4945 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4946 | relax_end (); |
4947 | } | |
4948 | ||
4949 | static void | |
67c0d1eb | 4950 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4951 | { |
4952 | expressionS global; | |
4953 | ||
4954 | global.X_op = O_constant; | |
4955 | global.X_op_symbol = NULL; | |
4956 | global.X_add_symbol = NULL; | |
4957 | global.X_add_number = local->X_add_number; | |
4958 | ||
4959 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4960 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4961 | dest, dest, BFD_RELOC_LO16); |
4962 | relax_switch (); | |
67c0d1eb | 4963 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4964 | relax_end (); |
4965 | } | |
4966 | ||
f6a22291 MR |
4967 | static void |
4968 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4969 | { | |
4970 | expressionS global; | |
4971 | int hold_mips_optimize; | |
4972 | ||
4973 | global.X_op = O_constant; | |
4974 | global.X_op_symbol = NULL; | |
4975 | global.X_add_symbol = NULL; | |
4976 | global.X_add_number = local->X_add_number; | |
4977 | ||
4978 | relax_start (local->X_add_symbol); | |
4979 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4980 | relax_switch (); | |
4981 | /* Set mips_optimize around the lui instruction to avoid | |
4982 | inserting an unnecessary nop after the lw. */ | |
4983 | hold_mips_optimize = mips_optimize; | |
4984 | mips_optimize = 2; | |
4985 | macro_build_lui (&global, tmp); | |
4986 | mips_optimize = hold_mips_optimize; | |
4987 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4988 | relax_end (); | |
4989 | ||
4990 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4991 | } | |
4992 | ||
252b5132 RH |
4993 | /* |
4994 | * Build macros | |
4995 | * This routine implements the seemingly endless macro or synthesized | |
4996 | * instructions and addressing modes in the mips assembly language. Many | |
4997 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4998 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4999 | * this verbose method. Others are not simple macros but are more like |
5000 | * optimizing code generation. | |
5001 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 5002 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
5003 | * The ensuing load upper instructions are ommited. This implies some kind |
5004 | * of global optimization. We currently only optimize within a single macro. | |
5005 | * For many of the load and store macros if the address is specified as a | |
5006 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
5007 | * first load register 'at' with zero and use it as the base register. The | |
5008 | * mips assembler simply uses register $zero. Just one tiny optimization | |
5009 | * we're missing. | |
5010 | */ | |
5011 | static void | |
17a2f251 | 5012 | macro (struct mips_cl_insn *ip) |
252b5132 | 5013 | { |
741fe287 MR |
5014 | unsigned int treg, sreg, dreg, breg; |
5015 | unsigned int tempreg; | |
252b5132 | 5016 | int mask; |
43841e91 | 5017 | int used_at = 0; |
252b5132 RH |
5018 | expressionS expr1; |
5019 | const char *s; | |
5020 | const char *s2; | |
5021 | const char *fmt; | |
5022 | int likely = 0; | |
5023 | int dbl = 0; | |
5024 | int coproc = 0; | |
5025 | int lr = 0; | |
5026 | int imm = 0; | |
1abe91b1 | 5027 | int call = 0; |
252b5132 | 5028 | int off; |
67c0d1eb | 5029 | offsetT maxnum; |
252b5132 | 5030 | bfd_reloc_code_real_type r; |
252b5132 RH |
5031 | int hold_mips_optimize; |
5032 | ||
9c2799c2 | 5033 | gas_assert (! mips_opts.mips16); |
252b5132 | 5034 | |
bbea7ebc MR |
5035 | treg = EXTRACT_OPERAND (RT, *ip); |
5036 | dreg = EXTRACT_OPERAND (RD, *ip); | |
5037 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
5038 | mask = ip->insn_mo->mask; |
5039 | ||
5040 | expr1.X_op = O_constant; | |
5041 | expr1.X_op_symbol = NULL; | |
5042 | expr1.X_add_symbol = NULL; | |
5043 | expr1.X_add_number = 1; | |
5044 | ||
5045 | switch (mask) | |
5046 | { | |
5047 | case M_DABS: | |
5048 | dbl = 1; | |
5049 | case M_ABS: | |
5050 | /* bgez $a0,.+12 | |
5051 | move v0,$a0 | |
5052 | sub v0,$zero,$a0 | |
5053 | */ | |
5054 | ||
7d10b47d | 5055 | start_noreorder (); |
252b5132 RH |
5056 | |
5057 | expr1.X_add_number = 8; | |
67c0d1eb | 5058 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 5059 | if (dreg == sreg) |
a605d2b3 | 5060 | macro_build (NULL, "nop", ""); |
252b5132 | 5061 | else |
67c0d1eb RS |
5062 | move_register (dreg, sreg); |
5063 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 5064 | |
7d10b47d | 5065 | end_noreorder (); |
8fc2e39e | 5066 | break; |
252b5132 RH |
5067 | |
5068 | case M_ADD_I: | |
5069 | s = "addi"; | |
5070 | s2 = "add"; | |
5071 | goto do_addi; | |
5072 | case M_ADDU_I: | |
5073 | s = "addiu"; | |
5074 | s2 = "addu"; | |
5075 | goto do_addi; | |
5076 | case M_DADD_I: | |
5077 | dbl = 1; | |
5078 | s = "daddi"; | |
5079 | s2 = "dadd"; | |
5080 | goto do_addi; | |
5081 | case M_DADDU_I: | |
5082 | dbl = 1; | |
5083 | s = "daddiu"; | |
5084 | s2 = "daddu"; | |
5085 | do_addi: | |
5086 | if (imm_expr.X_op == O_constant | |
5087 | && imm_expr.X_add_number >= -0x8000 | |
5088 | && imm_expr.X_add_number < 0x8000) | |
5089 | { | |
67c0d1eb | 5090 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5091 | break; |
252b5132 | 5092 | } |
8fc2e39e | 5093 | used_at = 1; |
67c0d1eb RS |
5094 | load_register (AT, &imm_expr, dbl); |
5095 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5096 | break; |
5097 | ||
5098 | case M_AND_I: | |
5099 | s = "andi"; | |
5100 | s2 = "and"; | |
5101 | goto do_bit; | |
5102 | case M_OR_I: | |
5103 | s = "ori"; | |
5104 | s2 = "or"; | |
5105 | goto do_bit; | |
5106 | case M_NOR_I: | |
5107 | s = ""; | |
5108 | s2 = "nor"; | |
5109 | goto do_bit; | |
5110 | case M_XOR_I: | |
5111 | s = "xori"; | |
5112 | s2 = "xor"; | |
5113 | do_bit: | |
5114 | if (imm_expr.X_op == O_constant | |
5115 | && imm_expr.X_add_number >= 0 | |
5116 | && imm_expr.X_add_number < 0x10000) | |
5117 | { | |
5118 | if (mask != M_NOR_I) | |
67c0d1eb | 5119 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
5120 | else |
5121 | { | |
67c0d1eb RS |
5122 | macro_build (&imm_expr, "ori", "t,r,i", |
5123 | treg, sreg, BFD_RELOC_LO16); | |
5124 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 5125 | } |
8fc2e39e | 5126 | break; |
252b5132 RH |
5127 | } |
5128 | ||
8fc2e39e | 5129 | used_at = 1; |
67c0d1eb RS |
5130 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5131 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5132 | break; |
5133 | ||
8b082fb1 TS |
5134 | case M_BALIGN: |
5135 | switch (imm_expr.X_add_number) | |
5136 | { | |
5137 | case 0: | |
5138 | macro_build (NULL, "nop", ""); | |
5139 | break; | |
5140 | case 2: | |
5141 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
5142 | break; | |
5143 | default: | |
5144 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 5145 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
5146 | break; |
5147 | } | |
5148 | break; | |
5149 | ||
252b5132 RH |
5150 | case M_BEQ_I: |
5151 | s = "beq"; | |
5152 | goto beq_i; | |
5153 | case M_BEQL_I: | |
5154 | s = "beql"; | |
5155 | likely = 1; | |
5156 | goto beq_i; | |
5157 | case M_BNE_I: | |
5158 | s = "bne"; | |
5159 | goto beq_i; | |
5160 | case M_BNEL_I: | |
5161 | s = "bnel"; | |
5162 | likely = 1; | |
5163 | beq_i: | |
5164 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5165 | { | |
c80c840e | 5166 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 5167 | break; |
252b5132 | 5168 | } |
8fc2e39e | 5169 | used_at = 1; |
67c0d1eb RS |
5170 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5171 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
5172 | break; |
5173 | ||
5174 | case M_BGEL: | |
5175 | likely = 1; | |
5176 | case M_BGE: | |
5177 | if (treg == 0) | |
5178 | { | |
67c0d1eb | 5179 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5180 | break; |
252b5132 RH |
5181 | } |
5182 | if (sreg == 0) | |
5183 | { | |
67c0d1eb | 5184 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 5185 | break; |
252b5132 | 5186 | } |
8fc2e39e | 5187 | used_at = 1; |
67c0d1eb | 5188 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5189 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5190 | break; |
5191 | ||
5192 | case M_BGTL_I: | |
5193 | likely = 1; | |
5194 | case M_BGT_I: | |
90ecf173 | 5195 | /* Check for > max integer. */ |
252b5132 | 5196 | maxnum = 0x7fffffff; |
ca4e0257 | 5197 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5198 | { |
5199 | maxnum <<= 16; | |
5200 | maxnum |= 0xffff; | |
5201 | maxnum <<= 16; | |
5202 | maxnum |= 0xffff; | |
5203 | } | |
5204 | if (imm_expr.X_op == O_constant | |
5205 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5206 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5207 | { |
5208 | do_false: | |
90ecf173 | 5209 | /* Result is always false. */ |
252b5132 | 5210 | if (! likely) |
a605d2b3 | 5211 | macro_build (NULL, "nop", ""); |
252b5132 | 5212 | else |
c80c840e | 5213 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5214 | break; |
252b5132 RH |
5215 | } |
5216 | if (imm_expr.X_op != O_constant) | |
5217 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5218 | ++imm_expr.X_add_number; |
252b5132 RH |
5219 | /* FALLTHROUGH */ |
5220 | case M_BGE_I: | |
5221 | case M_BGEL_I: | |
5222 | if (mask == M_BGEL_I) | |
5223 | likely = 1; | |
5224 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5225 | { | |
67c0d1eb | 5226 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5227 | break; |
252b5132 RH |
5228 | } |
5229 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5230 | { | |
67c0d1eb | 5231 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5232 | break; |
252b5132 RH |
5233 | } |
5234 | maxnum = 0x7fffffff; | |
ca4e0257 | 5235 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5236 | { |
5237 | maxnum <<= 16; | |
5238 | maxnum |= 0xffff; | |
5239 | maxnum <<= 16; | |
5240 | maxnum |= 0xffff; | |
5241 | } | |
5242 | maxnum = - maxnum - 1; | |
5243 | if (imm_expr.X_op == O_constant | |
5244 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5245 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5246 | { |
5247 | do_true: | |
5248 | /* result is always true */ | |
5249 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5250 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5251 | break; |
252b5132 | 5252 | } |
8fc2e39e | 5253 | used_at = 1; |
67c0d1eb | 5254 | set_at (sreg, 0); |
c80c840e | 5255 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5256 | break; |
5257 | ||
5258 | case M_BGEUL: | |
5259 | likely = 1; | |
5260 | case M_BGEU: | |
5261 | if (treg == 0) | |
5262 | goto do_true; | |
5263 | if (sreg == 0) | |
5264 | { | |
67c0d1eb | 5265 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5266 | "s,t,p", ZERO, treg); |
8fc2e39e | 5267 | break; |
252b5132 | 5268 | } |
8fc2e39e | 5269 | used_at = 1; |
67c0d1eb | 5270 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5271 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5272 | break; |
5273 | ||
5274 | case M_BGTUL_I: | |
5275 | likely = 1; | |
5276 | case M_BGTU_I: | |
5277 | if (sreg == 0 | |
ca4e0257 | 5278 | || (HAVE_32BIT_GPRS |
252b5132 | 5279 | && imm_expr.X_op == O_constant |
f01dc953 | 5280 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5281 | goto do_false; |
5282 | if (imm_expr.X_op != O_constant) | |
5283 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5284 | ++imm_expr.X_add_number; |
252b5132 RH |
5285 | /* FALLTHROUGH */ |
5286 | case M_BGEU_I: | |
5287 | case M_BGEUL_I: | |
5288 | if (mask == M_BGEUL_I) | |
5289 | likely = 1; | |
5290 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5291 | goto do_true; | |
5292 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5293 | { | |
67c0d1eb | 5294 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5295 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5296 | break; |
252b5132 | 5297 | } |
8fc2e39e | 5298 | used_at = 1; |
67c0d1eb | 5299 | set_at (sreg, 1); |
c80c840e | 5300 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5301 | break; |
5302 | ||
5303 | case M_BGTL: | |
5304 | likely = 1; | |
5305 | case M_BGT: | |
5306 | if (treg == 0) | |
5307 | { | |
67c0d1eb | 5308 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5309 | break; |
252b5132 RH |
5310 | } |
5311 | if (sreg == 0) | |
5312 | { | |
67c0d1eb | 5313 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5314 | break; |
252b5132 | 5315 | } |
8fc2e39e | 5316 | used_at = 1; |
67c0d1eb | 5317 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5318 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5319 | break; |
5320 | ||
5321 | case M_BGTUL: | |
5322 | likely = 1; | |
5323 | case M_BGTU: | |
5324 | if (treg == 0) | |
5325 | { | |
67c0d1eb | 5326 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5327 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5328 | break; |
252b5132 RH |
5329 | } |
5330 | if (sreg == 0) | |
5331 | goto do_false; | |
8fc2e39e | 5332 | used_at = 1; |
67c0d1eb | 5333 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5334 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5335 | break; |
5336 | ||
5337 | case M_BLEL: | |
5338 | likely = 1; | |
5339 | case M_BLE: | |
5340 | if (treg == 0) | |
5341 | { | |
67c0d1eb | 5342 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5343 | break; |
252b5132 RH |
5344 | } |
5345 | if (sreg == 0) | |
5346 | { | |
67c0d1eb | 5347 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5348 | break; |
252b5132 | 5349 | } |
8fc2e39e | 5350 | used_at = 1; |
67c0d1eb | 5351 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5352 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5353 | break; |
5354 | ||
5355 | case M_BLEL_I: | |
5356 | likely = 1; | |
5357 | case M_BLE_I: | |
5358 | maxnum = 0x7fffffff; | |
ca4e0257 | 5359 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5360 | { |
5361 | maxnum <<= 16; | |
5362 | maxnum |= 0xffff; | |
5363 | maxnum <<= 16; | |
5364 | maxnum |= 0xffff; | |
5365 | } | |
5366 | if (imm_expr.X_op == O_constant | |
5367 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5368 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5369 | goto do_true; |
5370 | if (imm_expr.X_op != O_constant) | |
5371 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5372 | ++imm_expr.X_add_number; |
252b5132 RH |
5373 | /* FALLTHROUGH */ |
5374 | case M_BLT_I: | |
5375 | case M_BLTL_I: | |
5376 | if (mask == M_BLTL_I) | |
5377 | likely = 1; | |
5378 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5379 | { | |
67c0d1eb | 5380 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5381 | break; |
252b5132 RH |
5382 | } |
5383 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5384 | { | |
67c0d1eb | 5385 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5386 | break; |
252b5132 | 5387 | } |
8fc2e39e | 5388 | used_at = 1; |
67c0d1eb | 5389 | set_at (sreg, 0); |
c80c840e | 5390 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5391 | break; |
5392 | ||
5393 | case M_BLEUL: | |
5394 | likely = 1; | |
5395 | case M_BLEU: | |
5396 | if (treg == 0) | |
5397 | { | |
67c0d1eb | 5398 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5399 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5400 | break; |
252b5132 RH |
5401 | } |
5402 | if (sreg == 0) | |
5403 | goto do_true; | |
8fc2e39e | 5404 | used_at = 1; |
67c0d1eb | 5405 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5406 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5407 | break; |
5408 | ||
5409 | case M_BLEUL_I: | |
5410 | likely = 1; | |
5411 | case M_BLEU_I: | |
5412 | if (sreg == 0 | |
ca4e0257 | 5413 | || (HAVE_32BIT_GPRS |
252b5132 | 5414 | && imm_expr.X_op == O_constant |
f01dc953 | 5415 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5416 | goto do_true; |
5417 | if (imm_expr.X_op != O_constant) | |
5418 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5419 | ++imm_expr.X_add_number; |
252b5132 RH |
5420 | /* FALLTHROUGH */ |
5421 | case M_BLTU_I: | |
5422 | case M_BLTUL_I: | |
5423 | if (mask == M_BLTUL_I) | |
5424 | likely = 1; | |
5425 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5426 | goto do_false; | |
5427 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5428 | { | |
67c0d1eb | 5429 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5430 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5431 | break; |
252b5132 | 5432 | } |
8fc2e39e | 5433 | used_at = 1; |
67c0d1eb | 5434 | set_at (sreg, 1); |
c80c840e | 5435 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5436 | break; |
5437 | ||
5438 | case M_BLTL: | |
5439 | likely = 1; | |
5440 | case M_BLT: | |
5441 | if (treg == 0) | |
5442 | { | |
67c0d1eb | 5443 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5444 | break; |
252b5132 RH |
5445 | } |
5446 | if (sreg == 0) | |
5447 | { | |
67c0d1eb | 5448 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5449 | break; |
252b5132 | 5450 | } |
8fc2e39e | 5451 | used_at = 1; |
67c0d1eb | 5452 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5453 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5454 | break; |
5455 | ||
5456 | case M_BLTUL: | |
5457 | likely = 1; | |
5458 | case M_BLTU: | |
5459 | if (treg == 0) | |
5460 | goto do_false; | |
5461 | if (sreg == 0) | |
5462 | { | |
67c0d1eb | 5463 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5464 | "s,t,p", ZERO, treg); |
8fc2e39e | 5465 | break; |
252b5132 | 5466 | } |
8fc2e39e | 5467 | used_at = 1; |
67c0d1eb | 5468 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5469 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5470 | break; |
5471 | ||
5f74bc13 CD |
5472 | case M_DEXT: |
5473 | { | |
d5818fca MR |
5474 | /* Use unsigned arithmetic. */ |
5475 | addressT pos; | |
5476 | addressT size; | |
5f74bc13 | 5477 | |
90ecf173 | 5478 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5479 | { |
5480 | as_bad (_("Unsupported large constant")); | |
5481 | pos = size = 1; | |
5482 | } | |
5483 | else | |
5484 | { | |
d5818fca MR |
5485 | pos = imm_expr.X_add_number; |
5486 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5487 | } |
5488 | ||
5489 | if (pos > 63) | |
5490 | { | |
d5818fca | 5491 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5492 | pos = 1; |
5493 | } | |
90ecf173 | 5494 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5495 | { |
5496 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5497 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5498 | size = 1; |
5499 | } | |
5500 | ||
5501 | if (size <= 32 && pos < 32) | |
5502 | { | |
5503 | s = "dext"; | |
5504 | fmt = "t,r,+A,+C"; | |
5505 | } | |
5506 | else if (size <= 32) | |
5507 | { | |
5508 | s = "dextu"; | |
5509 | fmt = "t,r,+E,+H"; | |
5510 | } | |
5511 | else | |
5512 | { | |
5513 | s = "dextm"; | |
5514 | fmt = "t,r,+A,+G"; | |
5515 | } | |
d5818fca MR |
5516 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5517 | (int) (size - 1)); | |
5f74bc13 | 5518 | } |
8fc2e39e | 5519 | break; |
5f74bc13 CD |
5520 | |
5521 | case M_DINS: | |
5522 | { | |
d5818fca MR |
5523 | /* Use unsigned arithmetic. */ |
5524 | addressT pos; | |
5525 | addressT size; | |
5f74bc13 | 5526 | |
90ecf173 | 5527 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5528 | { |
5529 | as_bad (_("Unsupported large constant")); | |
5530 | pos = size = 1; | |
5531 | } | |
5532 | else | |
5533 | { | |
d5818fca MR |
5534 | pos = imm_expr.X_add_number; |
5535 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5536 | } |
5537 | ||
5538 | if (pos > 63) | |
5539 | { | |
d5818fca | 5540 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5541 | pos = 1; |
5542 | } | |
90ecf173 | 5543 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5544 | { |
5545 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5546 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5547 | size = 1; |
5548 | } | |
5549 | ||
5550 | if (pos < 32 && (pos + size - 1) < 32) | |
5551 | { | |
5552 | s = "dins"; | |
5553 | fmt = "t,r,+A,+B"; | |
5554 | } | |
5555 | else if (pos >= 32) | |
5556 | { | |
5557 | s = "dinsu"; | |
5558 | fmt = "t,r,+E,+F"; | |
5559 | } | |
5560 | else | |
5561 | { | |
5562 | s = "dinsm"; | |
5563 | fmt = "t,r,+A,+F"; | |
5564 | } | |
750bdd57 AS |
5565 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5566 | (int) (pos + size - 1)); | |
5f74bc13 | 5567 | } |
8fc2e39e | 5568 | break; |
5f74bc13 | 5569 | |
252b5132 RH |
5570 | case M_DDIV_3: |
5571 | dbl = 1; | |
5572 | case M_DIV_3: | |
5573 | s = "mflo"; | |
5574 | goto do_div3; | |
5575 | case M_DREM_3: | |
5576 | dbl = 1; | |
5577 | case M_REM_3: | |
5578 | s = "mfhi"; | |
5579 | do_div3: | |
5580 | if (treg == 0) | |
5581 | { | |
5582 | as_warn (_("Divide by zero.")); | |
5583 | if (mips_trap) | |
c80c840e | 5584 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5585 | else |
67c0d1eb | 5586 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5587 | break; |
252b5132 RH |
5588 | } |
5589 | ||
7d10b47d | 5590 | start_noreorder (); |
252b5132 RH |
5591 | if (mips_trap) |
5592 | { | |
c80c840e | 5593 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5594 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5595 | } |
5596 | else | |
5597 | { | |
5598 | expr1.X_add_number = 8; | |
c80c840e | 5599 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5600 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5601 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5602 | } |
5603 | expr1.X_add_number = -1; | |
8fc2e39e | 5604 | used_at = 1; |
f6a22291 | 5605 | load_register (AT, &expr1, dbl); |
252b5132 | 5606 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5607 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5608 | if (dbl) |
5609 | { | |
5610 | expr1.X_add_number = 1; | |
f6a22291 | 5611 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5612 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5613 | } |
5614 | else | |
5615 | { | |
5616 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5617 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5618 | } |
5619 | if (mips_trap) | |
5620 | { | |
67c0d1eb | 5621 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5622 | /* We want to close the noreorder block as soon as possible, so |
5623 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5624 | end_noreorder (); |
252b5132 RH |
5625 | } |
5626 | else | |
5627 | { | |
5628 | expr1.X_add_number = 8; | |
67c0d1eb | 5629 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5630 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5631 | |
5632 | /* We want to close the noreorder block as soon as possible, so | |
5633 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5634 | end_noreorder (); |
252b5132 | 5635 | |
67c0d1eb | 5636 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5637 | } |
67c0d1eb | 5638 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5639 | break; |
5640 | ||
5641 | case M_DIV_3I: | |
5642 | s = "div"; | |
5643 | s2 = "mflo"; | |
5644 | goto do_divi; | |
5645 | case M_DIVU_3I: | |
5646 | s = "divu"; | |
5647 | s2 = "mflo"; | |
5648 | goto do_divi; | |
5649 | case M_REM_3I: | |
5650 | s = "div"; | |
5651 | s2 = "mfhi"; | |
5652 | goto do_divi; | |
5653 | case M_REMU_3I: | |
5654 | s = "divu"; | |
5655 | s2 = "mfhi"; | |
5656 | goto do_divi; | |
5657 | case M_DDIV_3I: | |
5658 | dbl = 1; | |
5659 | s = "ddiv"; | |
5660 | s2 = "mflo"; | |
5661 | goto do_divi; | |
5662 | case M_DDIVU_3I: | |
5663 | dbl = 1; | |
5664 | s = "ddivu"; | |
5665 | s2 = "mflo"; | |
5666 | goto do_divi; | |
5667 | case M_DREM_3I: | |
5668 | dbl = 1; | |
5669 | s = "ddiv"; | |
5670 | s2 = "mfhi"; | |
5671 | goto do_divi; | |
5672 | case M_DREMU_3I: | |
5673 | dbl = 1; | |
5674 | s = "ddivu"; | |
5675 | s2 = "mfhi"; | |
5676 | do_divi: | |
5677 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5678 | { | |
5679 | as_warn (_("Divide by zero.")); | |
5680 | if (mips_trap) | |
c80c840e | 5681 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5682 | else |
67c0d1eb | 5683 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5684 | break; |
252b5132 RH |
5685 | } |
5686 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5687 | { | |
5688 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5689 | move_register (dreg, sreg); |
252b5132 | 5690 | else |
c80c840e | 5691 | move_register (dreg, ZERO); |
8fc2e39e | 5692 | break; |
252b5132 RH |
5693 | } |
5694 | if (imm_expr.X_op == O_constant | |
5695 | && imm_expr.X_add_number == -1 | |
5696 | && s[strlen (s) - 1] != 'u') | |
5697 | { | |
5698 | if (strcmp (s2, "mflo") == 0) | |
5699 | { | |
67c0d1eb | 5700 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5701 | } |
5702 | else | |
c80c840e | 5703 | move_register (dreg, ZERO); |
8fc2e39e | 5704 | break; |
252b5132 RH |
5705 | } |
5706 | ||
8fc2e39e | 5707 | used_at = 1; |
67c0d1eb RS |
5708 | load_register (AT, &imm_expr, dbl); |
5709 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5710 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5711 | break; |
5712 | ||
5713 | case M_DIVU_3: | |
5714 | s = "divu"; | |
5715 | s2 = "mflo"; | |
5716 | goto do_divu3; | |
5717 | case M_REMU_3: | |
5718 | s = "divu"; | |
5719 | s2 = "mfhi"; | |
5720 | goto do_divu3; | |
5721 | case M_DDIVU_3: | |
5722 | s = "ddivu"; | |
5723 | s2 = "mflo"; | |
5724 | goto do_divu3; | |
5725 | case M_DREMU_3: | |
5726 | s = "ddivu"; | |
5727 | s2 = "mfhi"; | |
5728 | do_divu3: | |
7d10b47d | 5729 | start_noreorder (); |
252b5132 RH |
5730 | if (mips_trap) |
5731 | { | |
c80c840e | 5732 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5733 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5734 | /* We want to close the noreorder block as soon as possible, so |
5735 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5736 | end_noreorder (); |
252b5132 RH |
5737 | } |
5738 | else | |
5739 | { | |
5740 | expr1.X_add_number = 8; | |
c80c840e | 5741 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5742 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5743 | |
5744 | /* We want to close the noreorder block as soon as possible, so | |
5745 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5746 | end_noreorder (); |
67c0d1eb | 5747 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5748 | } |
67c0d1eb | 5749 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5750 | break; |
252b5132 | 5751 | |
1abe91b1 MR |
5752 | case M_DLCA_AB: |
5753 | dbl = 1; | |
5754 | case M_LCA_AB: | |
5755 | call = 1; | |
5756 | goto do_la; | |
252b5132 RH |
5757 | case M_DLA_AB: |
5758 | dbl = 1; | |
5759 | case M_LA_AB: | |
1abe91b1 | 5760 | do_la: |
252b5132 RH |
5761 | /* Load the address of a symbol into a register. If breg is not |
5762 | zero, we then add a base register to it. */ | |
5763 | ||
3bec30a8 TS |
5764 | if (dbl && HAVE_32BIT_GPRS) |
5765 | as_warn (_("dla used to load 32-bit register")); | |
5766 | ||
90ecf173 | 5767 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5768 | as_warn (_("la used to load 64-bit address")); |
5769 | ||
0c11417f MR |
5770 | if (offset_expr.X_op == O_constant |
5771 | && offset_expr.X_add_number >= -0x8000 | |
5772 | && offset_expr.X_add_number < 0x8000) | |
5773 | { | |
aed1a261 | 5774 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5775 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5776 | break; |
0c11417f MR |
5777 | } |
5778 | ||
741fe287 | 5779 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5780 | { |
5781 | tempreg = AT; | |
5782 | used_at = 1; | |
5783 | } | |
5784 | else | |
5785 | { | |
5786 | tempreg = treg; | |
afdbd6d0 CD |
5787 | } |
5788 | ||
252b5132 RH |
5789 | if (offset_expr.X_op != O_symbol |
5790 | && offset_expr.X_op != O_constant) | |
5791 | { | |
f71d0d44 | 5792 | as_bad (_("Expression too complex")); |
252b5132 RH |
5793 | offset_expr.X_op = O_constant; |
5794 | } | |
5795 | ||
252b5132 | 5796 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5797 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5798 | else if (mips_pic == NO_PIC) |
5799 | { | |
d6bc6245 | 5800 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5801 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5802 | Otherwise we want |
5803 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5804 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5805 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5806 | so we may as well always use the latter form. |
76b3015f | 5807 | |
6caf9ef4 TS |
5808 | With 64bit address space and a usable $at we want |
5809 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5810 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5811 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5812 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5813 | dsll32 $tempreg,0 | |
5814 | daddu $tempreg,$tempreg,$at | |
5815 | ||
5816 | If $at is already in use, we use a path which is suboptimal | |
5817 | on superscalar processors. | |
5818 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5819 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5820 | dsll $tempreg,16 | |
5821 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5822 | dsll $tempreg,16 | |
5823 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5824 | ||
5825 | For GP relative symbols in 64bit address space we can use | |
5826 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5827 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5828 | { |
6caf9ef4 TS |
5829 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5830 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5831 | { | |
5832 | relax_start (offset_expr.X_add_symbol); | |
5833 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5834 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5835 | relax_switch (); | |
5836 | } | |
d6bc6245 | 5837 | |
741fe287 | 5838 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5839 | { |
67c0d1eb | 5840 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5841 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5842 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5843 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5844 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5845 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5846 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5847 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5848 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5849 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5850 | used_at = 1; |
5851 | } | |
5852 | else | |
5853 | { | |
67c0d1eb | 5854 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5855 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5856 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5857 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5858 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5859 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5860 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5861 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5862 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5863 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5864 | } |
6caf9ef4 TS |
5865 | |
5866 | if (mips_relax.sequence) | |
5867 | relax_end (); | |
98d3f06f KH |
5868 | } |
5869 | else | |
5870 | { | |
5871 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5872 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5873 | { |
4d7206a2 | 5874 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5875 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5876 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5877 | relax_switch (); |
98d3f06f | 5878 | } |
6943caf0 | 5879 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5880 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5881 | macro_build_lui (&offset_expr, tempreg); |
5882 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5883 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5884 | if (mips_relax.sequence) |
5885 | relax_end (); | |
98d3f06f | 5886 | } |
252b5132 | 5887 | } |
0a44bf69 | 5888 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5889 | { |
9117d219 NC |
5890 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5891 | ||
252b5132 RH |
5892 | /* If this is a reference to an external symbol, and there |
5893 | is no constant, we want | |
5894 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5895 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5896 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5897 | For a local symbol, we want |
5898 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5899 | nop | |
5900 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5901 | ||
5902 | If we have a small constant, and this is a reference to | |
5903 | an external symbol, we want | |
5904 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5905 | nop | |
5906 | addiu $tempreg,$tempreg,<constant> | |
5907 | For a local symbol, we want the same instruction | |
5908 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5909 | addiu instruction. | |
5910 | ||
5911 | If we have a large constant, and this is a reference to | |
5912 | an external symbol, we want | |
5913 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5914 | lui $at,<hiconstant> | |
5915 | addiu $at,$at,<loconstant> | |
5916 | addu $tempreg,$tempreg,$at | |
5917 | For a local symbol, we want the same instruction | |
5918 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5919 | addiu instruction. |
ed6fb7bd SC |
5920 | */ |
5921 | ||
4d7206a2 | 5922 | if (offset_expr.X_add_number == 0) |
252b5132 | 5923 | { |
0a44bf69 RS |
5924 | if (mips_pic == SVR4_PIC |
5925 | && breg == 0 | |
5926 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5927 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5928 | ||
5929 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5930 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5931 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5932 | if (breg != 0) |
252b5132 RH |
5933 | { |
5934 | /* We're going to put in an addu instruction using | |
5935 | tempreg, so we may as well insert the nop right | |
5936 | now. */ | |
269137b2 | 5937 | load_delay_nop (); |
252b5132 | 5938 | } |
4d7206a2 | 5939 | relax_switch (); |
67c0d1eb RS |
5940 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5941 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5942 | load_delay_nop (); |
67c0d1eb RS |
5943 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5944 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5945 | relax_end (); |
252b5132 RH |
5946 | /* FIXME: If breg == 0, and the next instruction uses |
5947 | $tempreg, then if this variant case is used an extra | |
5948 | nop will be generated. */ | |
5949 | } | |
4d7206a2 RS |
5950 | else if (offset_expr.X_add_number >= -0x8000 |
5951 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5952 | { |
67c0d1eb | 5953 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5954 | load_delay_nop (); |
67c0d1eb | 5955 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5956 | } |
5957 | else | |
5958 | { | |
4d7206a2 RS |
5959 | expr1.X_add_number = offset_expr.X_add_number; |
5960 | offset_expr.X_add_number = | |
5961 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5962 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5963 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5964 | /* If we are going to add in a base register, and the |
5965 | target register and the base register are the same, | |
5966 | then we are using AT as a temporary register. Since | |
5967 | we want to load the constant into AT, we add our | |
5968 | current AT (from the global offset table) and the | |
5969 | register into the register now, and pretend we were | |
5970 | not using a base register. */ | |
67c0d1eb | 5971 | if (breg == treg) |
252b5132 | 5972 | { |
269137b2 | 5973 | load_delay_nop (); |
67c0d1eb | 5974 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5975 | treg, AT, breg); |
252b5132 RH |
5976 | breg = 0; |
5977 | tempreg = treg; | |
252b5132 | 5978 | } |
f6a22291 | 5979 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5980 | used_at = 1; |
5981 | } | |
5982 | } | |
0a44bf69 | 5983 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5984 | { |
67c0d1eb | 5985 | int add_breg_early = 0; |
f5040a92 AO |
5986 | |
5987 | /* If this is a reference to an external, and there is no | |
5988 | constant, or local symbol (*), with or without a | |
5989 | constant, we want | |
5990 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5991 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5992 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5993 | ||
5994 | If we have a small constant, and this is a reference to | |
5995 | an external symbol, we want | |
5996 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5997 | addiu $tempreg,$tempreg,<constant> | |
5998 | ||
5999 | If we have a large constant, and this is a reference to | |
6000 | an external symbol, we want | |
6001 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
6002 | lui $at,<hiconstant> | |
6003 | addiu $at,$at,<loconstant> | |
6004 | addu $tempreg,$tempreg,$at | |
6005 | ||
6006 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
6007 | local symbols, even though it introduces an additional | |
6008 | instruction. */ | |
6009 | ||
f5040a92 AO |
6010 | if (offset_expr.X_add_number) |
6011 | { | |
4d7206a2 | 6012 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6013 | offset_expr.X_add_number = 0; |
6014 | ||
4d7206a2 | 6015 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6016 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6017 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6018 | |
6019 | if (expr1.X_add_number >= -0x8000 | |
6020 | && expr1.X_add_number < 0x8000) | |
6021 | { | |
67c0d1eb RS |
6022 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
6023 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 6024 | } |
ecd13cd3 | 6025 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6026 | { |
f5040a92 AO |
6027 | /* If we are going to add in a base register, and the |
6028 | target register and the base register are the same, | |
6029 | then we are using AT as a temporary register. Since | |
6030 | we want to load the constant into AT, we add our | |
6031 | current AT (from the global offset table) and the | |
6032 | register into the register now, and pretend we were | |
6033 | not using a base register. */ | |
6034 | if (breg != treg) | |
6035 | dreg = tempreg; | |
6036 | else | |
6037 | { | |
9c2799c2 | 6038 | gas_assert (tempreg == AT); |
67c0d1eb RS |
6039 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6040 | treg, AT, breg); | |
f5040a92 | 6041 | dreg = treg; |
67c0d1eb | 6042 | add_breg_early = 1; |
f5040a92 AO |
6043 | } |
6044 | ||
f6a22291 | 6045 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6047 | dreg, dreg, AT); |
f5040a92 | 6048 | |
f5040a92 AO |
6049 | used_at = 1; |
6050 | } | |
6051 | else | |
6052 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6053 | ||
4d7206a2 | 6054 | relax_switch (); |
f5040a92 AO |
6055 | offset_expr.X_add_number = expr1.X_add_number; |
6056 | ||
67c0d1eb RS |
6057 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6058 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
6059 | if (add_breg_early) | |
f5040a92 | 6060 | { |
67c0d1eb | 6061 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 6062 | treg, tempreg, breg); |
f5040a92 AO |
6063 | breg = 0; |
6064 | tempreg = treg; | |
6065 | } | |
4d7206a2 | 6066 | relax_end (); |
f5040a92 | 6067 | } |
4d7206a2 | 6068 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 6069 | { |
4d7206a2 | 6070 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6071 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6072 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 6073 | relax_switch (); |
67c0d1eb RS |
6074 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6075 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 6076 | relax_end (); |
f5040a92 | 6077 | } |
4d7206a2 | 6078 | else |
f5040a92 | 6079 | { |
67c0d1eb RS |
6080 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6081 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6082 | } |
6083 | } | |
0a44bf69 | 6084 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6085 | { |
67c0d1eb | 6086 | int gpdelay; |
9117d219 NC |
6087 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6088 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 6089 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
6090 | |
6091 | /* This is the large GOT case. If this is a reference to an | |
6092 | external symbol, and there is no constant, we want | |
6093 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6094 | addu $tempreg,$tempreg,$gp | |
6095 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6096 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
6097 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6098 | addu $tempreg,$tempreg,$gp | |
6099 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
6100 | For a local symbol, we want |
6101 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6102 | nop | |
6103 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6104 | ||
6105 | If we have a small constant, and this is a reference to | |
6106 | an external symbol, we want | |
6107 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6108 | addu $tempreg,$tempreg,$gp | |
6109 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6110 | nop | |
6111 | addiu $tempreg,$tempreg,<constant> | |
6112 | For a local symbol, we want | |
6113 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6114 | nop | |
6115 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
6116 | ||
6117 | If we have a large constant, and this is a reference to | |
6118 | an external symbol, we want | |
6119 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6120 | addu $tempreg,$tempreg,$gp | |
6121 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6122 | lui $at,<hiconstant> | |
6123 | addiu $at,$at,<loconstant> | |
6124 | addu $tempreg,$tempreg,$at | |
6125 | For a local symbol, we want | |
6126 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6127 | lui $at,<hiconstant> | |
6128 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
6129 | addu $tempreg,$tempreg,$at | |
f5040a92 | 6130 | */ |
438c16b8 | 6131 | |
252b5132 RH |
6132 | expr1.X_add_number = offset_expr.X_add_number; |
6133 | offset_expr.X_add_number = 0; | |
4d7206a2 | 6134 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6135 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
6136 | if (expr1.X_add_number == 0 && breg == 0 |
6137 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
6138 | { |
6139 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6140 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6141 | } | |
67c0d1eb RS |
6142 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6143 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6144 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 6145 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6146 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
6147 | if (expr1.X_add_number == 0) |
6148 | { | |
67c0d1eb | 6149 | if (breg != 0) |
252b5132 RH |
6150 | { |
6151 | /* We're going to put in an addu instruction using | |
6152 | tempreg, so we may as well insert the nop right | |
6153 | now. */ | |
269137b2 | 6154 | load_delay_nop (); |
252b5132 | 6155 | } |
252b5132 RH |
6156 | } |
6157 | else if (expr1.X_add_number >= -0x8000 | |
6158 | && expr1.X_add_number < 0x8000) | |
6159 | { | |
269137b2 | 6160 | load_delay_nop (); |
67c0d1eb | 6161 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6162 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
6163 | } |
6164 | else | |
6165 | { | |
252b5132 RH |
6166 | /* If we are going to add in a base register, and the |
6167 | target register and the base register are the same, | |
6168 | then we are using AT as a temporary register. Since | |
6169 | we want to load the constant into AT, we add our | |
6170 | current AT (from the global offset table) and the | |
6171 | register into the register now, and pretend we were | |
6172 | not using a base register. */ | |
6173 | if (breg != treg) | |
67c0d1eb | 6174 | dreg = tempreg; |
252b5132 RH |
6175 | else |
6176 | { | |
9c2799c2 | 6177 | gas_assert (tempreg == AT); |
269137b2 | 6178 | load_delay_nop (); |
67c0d1eb | 6179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6180 | treg, AT, breg); |
252b5132 | 6181 | dreg = treg; |
252b5132 RH |
6182 | } |
6183 | ||
f6a22291 | 6184 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6185 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 6186 | |
252b5132 RH |
6187 | used_at = 1; |
6188 | } | |
4d7206a2 RS |
6189 | offset_expr.X_add_number = |
6190 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
6191 | relax_switch (); | |
252b5132 | 6192 | |
67c0d1eb | 6193 | if (gpdelay) |
252b5132 RH |
6194 | { |
6195 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 6196 | the first instruction on the main stream does not. */ |
67c0d1eb | 6197 | macro_build (NULL, "nop", ""); |
252b5132 | 6198 | } |
ed6fb7bd | 6199 | |
67c0d1eb RS |
6200 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6201 | local_reloc_type, mips_gp_register); | |
f5040a92 | 6202 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
6203 | && expr1.X_add_number < 0x8000) |
6204 | { | |
269137b2 | 6205 | load_delay_nop (); |
67c0d1eb RS |
6206 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6207 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6208 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6209 | register, the external symbol case ended with a load, |
6210 | so if the symbol turns out to not be external, and | |
6211 | the next instruction uses tempreg, an unnecessary nop | |
6212 | will be inserted. */ | |
252b5132 RH |
6213 | } |
6214 | else | |
6215 | { | |
6216 | if (breg == treg) | |
6217 | { | |
6218 | /* We must add in the base register now, as in the | |
f5040a92 | 6219 | external symbol case. */ |
9c2799c2 | 6220 | gas_assert (tempreg == AT); |
269137b2 | 6221 | load_delay_nop (); |
67c0d1eb | 6222 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6223 | treg, AT, breg); |
252b5132 RH |
6224 | tempreg = treg; |
6225 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6226 | it in in both cases. */ |
252b5132 RH |
6227 | breg = 0; |
6228 | } | |
6229 | ||
67c0d1eb RS |
6230 | macro_build_lui (&expr1, AT); |
6231 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6232 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6233 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6234 | tempreg, tempreg, AT); |
8fc2e39e | 6235 | used_at = 1; |
252b5132 | 6236 | } |
4d7206a2 | 6237 | relax_end (); |
252b5132 | 6238 | } |
0a44bf69 | 6239 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6240 | { |
f5040a92 AO |
6241 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6242 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6243 | int add_breg_early = 0; |
f5040a92 AO |
6244 | |
6245 | /* This is the large GOT case. If this is a reference to an | |
6246 | external symbol, and there is no constant, we want | |
6247 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6248 | add $tempreg,$tempreg,$gp | |
6249 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6250 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6251 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6252 | add $tempreg,$tempreg,$gp | |
6253 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6254 | ||
6255 | If we have a small constant, and this is a reference to | |
6256 | an external symbol, we want | |
6257 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6258 | add $tempreg,$tempreg,$gp | |
6259 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6260 | addi $tempreg,$tempreg,<constant> | |
6261 | ||
6262 | If we have a large constant, and this is a reference to | |
6263 | an external symbol, we want | |
6264 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6265 | addu $tempreg,$tempreg,$gp | |
6266 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6267 | lui $at,<hiconstant> | |
6268 | addi $at,$at,<loconstant> | |
6269 | add $tempreg,$tempreg,$at | |
6270 | ||
6271 | If we have NewABI, and we know it's a local symbol, we want | |
6272 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6273 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6274 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6275 | ||
4d7206a2 | 6276 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6277 | |
4d7206a2 | 6278 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6279 | offset_expr.X_add_number = 0; |
6280 | ||
1abe91b1 MR |
6281 | if (expr1.X_add_number == 0 && breg == 0 |
6282 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6283 | { |
6284 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6285 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6286 | } | |
67c0d1eb RS |
6287 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6288 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6289 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6290 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6291 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6292 | |
6293 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6294 | ; |
f5040a92 AO |
6295 | else if (expr1.X_add_number >= -0x8000 |
6296 | && expr1.X_add_number < 0x8000) | |
6297 | { | |
67c0d1eb | 6298 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6299 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6300 | } |
ecd13cd3 | 6301 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6302 | { |
f5040a92 AO |
6303 | /* If we are going to add in a base register, and the |
6304 | target register and the base register are the same, | |
6305 | then we are using AT as a temporary register. Since | |
6306 | we want to load the constant into AT, we add our | |
6307 | current AT (from the global offset table) and the | |
6308 | register into the register now, and pretend we were | |
6309 | not using a base register. */ | |
6310 | if (breg != treg) | |
6311 | dreg = tempreg; | |
6312 | else | |
6313 | { | |
9c2799c2 | 6314 | gas_assert (tempreg == AT); |
67c0d1eb | 6315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6316 | treg, AT, breg); |
f5040a92 | 6317 | dreg = treg; |
67c0d1eb | 6318 | add_breg_early = 1; |
f5040a92 AO |
6319 | } |
6320 | ||
f6a22291 | 6321 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6322 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6323 | |
f5040a92 AO |
6324 | used_at = 1; |
6325 | } | |
6326 | else | |
6327 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6328 | ||
4d7206a2 | 6329 | relax_switch (); |
f5040a92 | 6330 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6331 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6332 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6333 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6334 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6335 | if (add_breg_early) | |
f5040a92 | 6336 | { |
67c0d1eb | 6337 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6338 | treg, tempreg, breg); |
f5040a92 AO |
6339 | breg = 0; |
6340 | tempreg = treg; | |
6341 | } | |
4d7206a2 | 6342 | relax_end (); |
f5040a92 | 6343 | } |
252b5132 RH |
6344 | else |
6345 | abort (); | |
6346 | ||
6347 | if (breg != 0) | |
aed1a261 | 6348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6349 | break; |
6350 | ||
52b6b6b9 JM |
6351 | case M_MSGSND: |
6352 | { | |
6353 | unsigned long temp = (treg << 16) | (0x01); | |
6354 | macro_build (NULL, "c2", "C", temp); | |
6355 | } | |
c7af4273 | 6356 | break; |
52b6b6b9 JM |
6357 | |
6358 | case M_MSGLD: | |
6359 | { | |
6360 | unsigned long temp = (0x02); | |
6361 | macro_build (NULL, "c2", "C", temp); | |
6362 | } | |
c7af4273 | 6363 | break; |
52b6b6b9 JM |
6364 | |
6365 | case M_MSGLD_T: | |
6366 | { | |
6367 | unsigned long temp = (treg << 16) | (0x02); | |
6368 | macro_build (NULL, "c2", "C", temp); | |
6369 | } | |
c7af4273 | 6370 | break; |
52b6b6b9 JM |
6371 | |
6372 | case M_MSGWAIT: | |
6373 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6374 | break; |
52b6b6b9 JM |
6375 | |
6376 | case M_MSGWAIT_T: | |
6377 | { | |
6378 | unsigned long temp = (treg << 16) | 0x03; | |
6379 | macro_build (NULL, "c2", "C", temp); | |
6380 | } | |
c7af4273 | 6381 | break; |
52b6b6b9 | 6382 | |
252b5132 RH |
6383 | case M_J_A: |
6384 | /* The j instruction may not be used in PIC code, since it | |
6385 | requires an absolute address. We convert it to a b | |
6386 | instruction. */ | |
6387 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6388 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6389 | else |
67c0d1eb | 6390 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6391 | break; |
252b5132 RH |
6392 | |
6393 | /* The jal instructions must be handled as macros because when | |
6394 | generating PIC code they expand to multi-instruction | |
6395 | sequences. Normally they are simple instructions. */ | |
6396 | case M_JAL_1: | |
6397 | dreg = RA; | |
6398 | /* Fall through. */ | |
6399 | case M_JAL_2: | |
3e722fb5 | 6400 | if (mips_pic == NO_PIC) |
67c0d1eb | 6401 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6402 | else |
252b5132 RH |
6403 | { |
6404 | if (sreg != PIC_CALL_REG) | |
6405 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6406 | |
67c0d1eb | 6407 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6408 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6409 | { |
6478892d TS |
6410 | if (mips_cprestore_offset < 0) |
6411 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6412 | else | |
6413 | { | |
90ecf173 | 6414 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6415 | { |
6416 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6417 | /* Quiet this warning. */ | |
6418 | mips_frame_reg_valid = 1; | |
6419 | } | |
90ecf173 | 6420 | if (!mips_cprestore_valid) |
7a621144 DJ |
6421 | { |
6422 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6423 | /* Quiet this warning. */ | |
6424 | mips_cprestore_valid = 1; | |
6425 | } | |
d3fca0b5 MR |
6426 | if (mips_opts.noreorder) |
6427 | macro_build (NULL, "nop", ""); | |
6478892d | 6428 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6429 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6430 | mips_gp_register, |
256ab948 TS |
6431 | mips_frame_reg, |
6432 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6433 | } |
252b5132 RH |
6434 | } |
6435 | } | |
252b5132 | 6436 | |
8fc2e39e | 6437 | break; |
252b5132 RH |
6438 | |
6439 | case M_JAL_A: | |
6440 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6441 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6442 | else if (mips_pic == SVR4_PIC) |
6443 | { | |
6444 | /* If this is a reference to an external symbol, and we are | |
6445 | using a small GOT, we want | |
6446 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6447 | nop | |
f9419b05 | 6448 | jalr $ra,$25 |
252b5132 RH |
6449 | nop |
6450 | lw $gp,cprestore($sp) | |
6451 | The cprestore value is set using the .cprestore | |
6452 | pseudo-op. If we are using a big GOT, we want | |
6453 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6454 | addu $25,$25,$gp | |
6455 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6456 | nop | |
f9419b05 | 6457 | jalr $ra,$25 |
252b5132 RH |
6458 | nop |
6459 | lw $gp,cprestore($sp) | |
6460 | If the symbol is not external, we want | |
6461 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6462 | nop | |
6463 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6464 | jalr $ra,$25 |
252b5132 | 6465 | nop |
438c16b8 | 6466 | lw $gp,cprestore($sp) |
f5040a92 AO |
6467 | |
6468 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6469 | sequences above, minus nops, unless the symbol is local, | |
6470 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6471 | GOT_DISP. */ | |
438c16b8 | 6472 | if (HAVE_NEWABI) |
252b5132 | 6473 | { |
90ecf173 | 6474 | if (!mips_big_got) |
f5040a92 | 6475 | { |
4d7206a2 | 6476 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6477 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6478 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6479 | mips_gp_register); |
4d7206a2 | 6480 | relax_switch (); |
67c0d1eb RS |
6481 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6482 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6483 | mips_gp_register); |
6484 | relax_end (); | |
f5040a92 AO |
6485 | } |
6486 | else | |
6487 | { | |
4d7206a2 | 6488 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6489 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6490 | BFD_RELOC_MIPS_CALL_HI16); | |
6491 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6492 | PIC_CALL_REG, mips_gp_register); | |
6493 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6494 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6495 | PIC_CALL_REG); | |
4d7206a2 | 6496 | relax_switch (); |
67c0d1eb RS |
6497 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6498 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6499 | mips_gp_register); | |
6500 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6501 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6502 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6503 | relax_end (); |
f5040a92 | 6504 | } |
684022ea | 6505 | |
67c0d1eb | 6506 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6507 | } |
6508 | else | |
6509 | { | |
4d7206a2 | 6510 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6511 | if (!mips_big_got) |
438c16b8 | 6512 | { |
67c0d1eb RS |
6513 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6514 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6515 | mips_gp_register); |
269137b2 | 6516 | load_delay_nop (); |
4d7206a2 | 6517 | relax_switch (); |
438c16b8 | 6518 | } |
252b5132 | 6519 | else |
252b5132 | 6520 | { |
67c0d1eb RS |
6521 | int gpdelay; |
6522 | ||
6523 | gpdelay = reg_needs_delay (mips_gp_register); | |
6524 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6525 | BFD_RELOC_MIPS_CALL_HI16); | |
6526 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6527 | PIC_CALL_REG, mips_gp_register); | |
6528 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6529 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6530 | PIC_CALL_REG); | |
269137b2 | 6531 | load_delay_nop (); |
4d7206a2 | 6532 | relax_switch (); |
67c0d1eb RS |
6533 | if (gpdelay) |
6534 | macro_build (NULL, "nop", ""); | |
252b5132 | 6535 | } |
67c0d1eb RS |
6536 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6537 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6538 | mips_gp_register); |
269137b2 | 6539 | load_delay_nop (); |
67c0d1eb RS |
6540 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6541 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6542 | relax_end (); |
67c0d1eb | 6543 | macro_build_jalr (&offset_expr); |
438c16b8 | 6544 | |
6478892d TS |
6545 | if (mips_cprestore_offset < 0) |
6546 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6547 | else | |
6548 | { | |
90ecf173 | 6549 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6550 | { |
6551 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6552 | /* Quiet this warning. */ | |
6553 | mips_frame_reg_valid = 1; | |
6554 | } | |
90ecf173 | 6555 | if (!mips_cprestore_valid) |
7a621144 DJ |
6556 | { |
6557 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6558 | /* Quiet this warning. */ | |
6559 | mips_cprestore_valid = 1; | |
6560 | } | |
6478892d | 6561 | if (mips_opts.noreorder) |
67c0d1eb | 6562 | macro_build (NULL, "nop", ""); |
6478892d | 6563 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6564 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6565 | mips_gp_register, |
256ab948 TS |
6566 | mips_frame_reg, |
6567 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6568 | } |
252b5132 RH |
6569 | } |
6570 | } | |
0a44bf69 RS |
6571 | else if (mips_pic == VXWORKS_PIC) |
6572 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6573 | else |
6574 | abort (); | |
6575 | ||
8fc2e39e | 6576 | break; |
252b5132 RH |
6577 | |
6578 | case M_LB_AB: | |
6579 | s = "lb"; | |
6580 | goto ld; | |
6581 | case M_LBU_AB: | |
6582 | s = "lbu"; | |
6583 | goto ld; | |
6584 | case M_LH_AB: | |
6585 | s = "lh"; | |
6586 | goto ld; | |
6587 | case M_LHU_AB: | |
6588 | s = "lhu"; | |
6589 | goto ld; | |
6590 | case M_LW_AB: | |
6591 | s = "lw"; | |
6592 | goto ld; | |
6593 | case M_LWC0_AB: | |
6594 | s = "lwc0"; | |
bdaaa2e1 | 6595 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6596 | coproc = 1; |
6597 | goto ld; | |
6598 | case M_LWC1_AB: | |
6599 | s = "lwc1"; | |
bdaaa2e1 | 6600 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6601 | coproc = 1; |
6602 | goto ld; | |
6603 | case M_LWC2_AB: | |
6604 | s = "lwc2"; | |
bdaaa2e1 | 6605 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6606 | coproc = 1; |
6607 | goto ld; | |
6608 | case M_LWC3_AB: | |
6609 | s = "lwc3"; | |
bdaaa2e1 | 6610 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6611 | coproc = 1; |
6612 | goto ld; | |
6613 | case M_LWL_AB: | |
6614 | s = "lwl"; | |
6615 | lr = 1; | |
6616 | goto ld; | |
6617 | case M_LWR_AB: | |
6618 | s = "lwr"; | |
6619 | lr = 1; | |
6620 | goto ld; | |
6621 | case M_LDC1_AB: | |
252b5132 | 6622 | s = "ldc1"; |
bdaaa2e1 | 6623 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6624 | coproc = 1; |
6625 | goto ld; | |
6626 | case M_LDC2_AB: | |
6627 | s = "ldc2"; | |
bdaaa2e1 | 6628 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6629 | coproc = 1; |
6630 | goto ld; | |
6631 | case M_LDC3_AB: | |
6632 | s = "ldc3"; | |
bdaaa2e1 | 6633 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6634 | coproc = 1; |
6635 | goto ld; | |
6636 | case M_LDL_AB: | |
6637 | s = "ldl"; | |
6638 | lr = 1; | |
6639 | goto ld; | |
6640 | case M_LDR_AB: | |
6641 | s = "ldr"; | |
6642 | lr = 1; | |
6643 | goto ld; | |
6644 | case M_LL_AB: | |
6645 | s = "ll"; | |
6646 | goto ld; | |
6647 | case M_LLD_AB: | |
6648 | s = "lld"; | |
6649 | goto ld; | |
6650 | case M_LWU_AB: | |
6651 | s = "lwu"; | |
6652 | ld: | |
8fc2e39e | 6653 | if (breg == treg || coproc || lr) |
252b5132 RH |
6654 | { |
6655 | tempreg = AT; | |
6656 | used_at = 1; | |
6657 | } | |
6658 | else | |
6659 | { | |
6660 | tempreg = treg; | |
252b5132 RH |
6661 | } |
6662 | goto ld_st; | |
6663 | case M_SB_AB: | |
6664 | s = "sb"; | |
6665 | goto st; | |
6666 | case M_SH_AB: | |
6667 | s = "sh"; | |
6668 | goto st; | |
6669 | case M_SW_AB: | |
6670 | s = "sw"; | |
6671 | goto st; | |
6672 | case M_SWC0_AB: | |
6673 | s = "swc0"; | |
bdaaa2e1 | 6674 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6675 | coproc = 1; |
6676 | goto st; | |
6677 | case M_SWC1_AB: | |
6678 | s = "swc1"; | |
bdaaa2e1 | 6679 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6680 | coproc = 1; |
6681 | goto st; | |
6682 | case M_SWC2_AB: | |
6683 | s = "swc2"; | |
bdaaa2e1 | 6684 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6685 | coproc = 1; |
6686 | goto st; | |
6687 | case M_SWC3_AB: | |
6688 | s = "swc3"; | |
bdaaa2e1 | 6689 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6690 | coproc = 1; |
6691 | goto st; | |
6692 | case M_SWL_AB: | |
6693 | s = "swl"; | |
6694 | goto st; | |
6695 | case M_SWR_AB: | |
6696 | s = "swr"; | |
6697 | goto st; | |
6698 | case M_SC_AB: | |
6699 | s = "sc"; | |
6700 | goto st; | |
6701 | case M_SCD_AB: | |
6702 | s = "scd"; | |
6703 | goto st; | |
d43b4baf TS |
6704 | case M_CACHE_AB: |
6705 | s = "cache"; | |
6706 | goto st; | |
3eebd5eb MR |
6707 | case M_PREF_AB: |
6708 | s = "pref"; | |
6709 | goto st; | |
252b5132 | 6710 | case M_SDC1_AB: |
252b5132 RH |
6711 | s = "sdc1"; |
6712 | coproc = 1; | |
bdaaa2e1 | 6713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6714 | goto st; |
6715 | case M_SDC2_AB: | |
6716 | s = "sdc2"; | |
bdaaa2e1 | 6717 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6718 | coproc = 1; |
6719 | goto st; | |
6720 | case M_SDC3_AB: | |
6721 | s = "sdc3"; | |
bdaaa2e1 | 6722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6723 | coproc = 1; |
6724 | goto st; | |
6725 | case M_SDL_AB: | |
6726 | s = "sdl"; | |
6727 | goto st; | |
6728 | case M_SDR_AB: | |
6729 | s = "sdr"; | |
6730 | st: | |
8fc2e39e TS |
6731 | tempreg = AT; |
6732 | used_at = 1; | |
252b5132 | 6733 | ld_st: |
b19e8a9b AN |
6734 | if (coproc |
6735 | && NO_ISA_COP (mips_opts.arch) | |
6736 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6737 | { | |
f71d0d44 | 6738 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6739 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6740 | break; | |
6741 | } | |
6742 | ||
bdaaa2e1 | 6743 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6744 | if (mask == M_LWC1_AB |
6745 | || mask == M_SWC1_AB | |
6746 | || mask == M_LDC1_AB | |
6747 | || mask == M_SDC1_AB | |
6748 | || mask == M_L_DAB | |
6749 | || mask == M_S_DAB) | |
6750 | fmt = "T,o(b)"; | |
3eebd5eb | 6751 | else if (mask == M_CACHE_AB || mask == M_PREF_AB) |
d43b4baf | 6752 | fmt = "k,o(b)"; |
252b5132 RH |
6753 | else if (coproc) |
6754 | fmt = "E,o(b)"; | |
6755 | else | |
6756 | fmt = "t,o(b)"; | |
6757 | ||
6758 | if (offset_expr.X_op != O_constant | |
6759 | && offset_expr.X_op != O_symbol) | |
6760 | { | |
f71d0d44 | 6761 | as_bad (_("Expression too complex")); |
252b5132 RH |
6762 | offset_expr.X_op = O_constant; |
6763 | } | |
6764 | ||
2051e8c4 MR |
6765 | if (HAVE_32BIT_ADDRESSES |
6766 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6767 | { |
6768 | char value [32]; | |
6769 | ||
6770 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6771 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6772 | } |
2051e8c4 | 6773 | |
252b5132 RH |
6774 | /* A constant expression in PIC code can be handled just as it |
6775 | is in non PIC code. */ | |
aed1a261 RS |
6776 | if (offset_expr.X_op == O_constant) |
6777 | { | |
842f8b2a | 6778 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6779 | normalize_address_expr (&expr1); |
842f8b2a MR |
6780 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6781 | { | |
6782 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6783 | & ~(bfd_vma) 0xffff); | |
6784 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6785 | if (breg != 0) | |
6786 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6787 | tempreg, tempreg, breg); | |
6788 | breg = tempreg; | |
6789 | } | |
6790 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6791 | } |
6792 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6793 | { |
6794 | /* If this is a reference to a GP relative symbol, and there | |
6795 | is no base register, we want | |
cdf6fd85 | 6796 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6797 | Otherwise, if there is no base register, we want |
6798 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6799 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6800 | If we have a constant, we need two instructions anyhow, | |
6801 | so we always use the latter form. | |
6802 | ||
6803 | If we have a base register, and this is a reference to a | |
6804 | GP relative symbol, we want | |
6805 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6806 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6807 | Otherwise we want |
6808 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6809 | addu $tempreg,$tempreg,$breg | |
6810 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6811 | With a constant we always use the latter case. |
76b3015f | 6812 | |
d6bc6245 TS |
6813 | With 64bit address space and no base register and $at usable, |
6814 | we want | |
6815 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6816 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6817 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6818 | dsll32 $tempreg,0 | |
6819 | daddu $tempreg,$at | |
6820 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6821 | If we have a base register, we want | |
6822 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6823 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6824 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6825 | daddu $at,$breg | |
6826 | dsll32 $tempreg,0 | |
6827 | daddu $tempreg,$at | |
6828 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6829 | ||
6830 | Without $at we can't generate the optimal path for superscalar | |
6831 | processors here since this would require two temporary registers. | |
6832 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6833 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6834 | dsll $tempreg,16 | |
6835 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6836 | dsll $tempreg,16 | |
6837 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6838 | If we have a base register, we want | |
6839 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6840 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6841 | dsll $tempreg,16 | |
6842 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6843 | dsll $tempreg,16 | |
6844 | daddu $tempreg,$tempreg,$breg | |
6845 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6846 | |
6caf9ef4 | 6847 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6848 | the same sequence as in 32bit address space. */ |
6849 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6850 | { |
aed1a261 | 6851 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6852 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6853 | { | |
6854 | relax_start (offset_expr.X_add_symbol); | |
6855 | if (breg == 0) | |
6856 | { | |
6857 | macro_build (&offset_expr, s, fmt, treg, | |
6858 | BFD_RELOC_GPREL16, mips_gp_register); | |
6859 | } | |
6860 | else | |
6861 | { | |
6862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6863 | tempreg, breg, mips_gp_register); | |
6864 | macro_build (&offset_expr, s, fmt, treg, | |
6865 | BFD_RELOC_GPREL16, tempreg); | |
6866 | } | |
6867 | relax_switch (); | |
6868 | } | |
d6bc6245 | 6869 | |
741fe287 | 6870 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6871 | { |
67c0d1eb RS |
6872 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6873 | BFD_RELOC_MIPS_HIGHEST); | |
6874 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6875 | BFD_RELOC_HI16_S); | |
6876 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6877 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6878 | if (breg != 0) |
67c0d1eb RS |
6879 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6880 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6881 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6882 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6883 | tempreg); | |
d6bc6245 TS |
6884 | used_at = 1; |
6885 | } | |
6886 | else | |
6887 | { | |
67c0d1eb RS |
6888 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6889 | BFD_RELOC_MIPS_HIGHEST); | |
6890 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6891 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6892 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6893 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6894 | tempreg, BFD_RELOC_HI16_S); | |
6895 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6896 | if (breg != 0) |
67c0d1eb | 6897 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6898 | tempreg, tempreg, breg); |
67c0d1eb | 6899 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6900 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6901 | } |
6caf9ef4 TS |
6902 | |
6903 | if (mips_relax.sequence) | |
6904 | relax_end (); | |
8fc2e39e | 6905 | break; |
d6bc6245 | 6906 | } |
256ab948 | 6907 | |
252b5132 RH |
6908 | if (breg == 0) |
6909 | { | |
67c0d1eb | 6910 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6911 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6912 | { |
4d7206a2 | 6913 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6914 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6915 | mips_gp_register); | |
4d7206a2 | 6916 | relax_switch (); |
252b5132 | 6917 | } |
67c0d1eb RS |
6918 | macro_build_lui (&offset_expr, tempreg); |
6919 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6920 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6921 | if (mips_relax.sequence) |
6922 | relax_end (); | |
252b5132 RH |
6923 | } |
6924 | else | |
6925 | { | |
67c0d1eb | 6926 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6927 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6928 | { |
4d7206a2 | 6929 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6930 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6931 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6932 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6933 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6934 | relax_switch (); |
252b5132 | 6935 | } |
67c0d1eb RS |
6936 | macro_build_lui (&offset_expr, tempreg); |
6937 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6938 | tempreg, tempreg, breg); |
67c0d1eb | 6939 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6940 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6941 | if (mips_relax.sequence) |
6942 | relax_end (); | |
252b5132 RH |
6943 | } |
6944 | } | |
0a44bf69 | 6945 | else if (!mips_big_got) |
252b5132 | 6946 | { |
ed6fb7bd | 6947 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6948 | |
252b5132 RH |
6949 | /* If this is a reference to an external symbol, we want |
6950 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6951 | nop | |
6952 | <op> $treg,0($tempreg) | |
6953 | Otherwise we want | |
6954 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6955 | nop | |
6956 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6957 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6958 | |
6959 | For NewABI, we want | |
6960 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6961 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6962 | ||
252b5132 RH |
6963 | If there is a base register, we add it to $tempreg before |
6964 | the <op>. If there is a constant, we stick it in the | |
6965 | <op> instruction. We don't handle constants larger than | |
6966 | 16 bits, because we have no way to load the upper 16 bits | |
6967 | (actually, we could handle them for the subset of cases | |
6968 | in which we are not using $at). */ | |
9c2799c2 | 6969 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6970 | if (HAVE_NEWABI) |
6971 | { | |
67c0d1eb RS |
6972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6973 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6974 | if (breg != 0) |
67c0d1eb | 6975 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6976 | tempreg, tempreg, breg); |
67c0d1eb | 6977 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6978 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6979 | break; |
6980 | } | |
252b5132 RH |
6981 | expr1.X_add_number = offset_expr.X_add_number; |
6982 | offset_expr.X_add_number = 0; | |
6983 | if (expr1.X_add_number < -0x8000 | |
6984 | || expr1.X_add_number >= 0x8000) | |
6985 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6986 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6987 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6988 | load_delay_nop (); |
4d7206a2 RS |
6989 | relax_start (offset_expr.X_add_symbol); |
6990 | relax_switch (); | |
67c0d1eb RS |
6991 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6992 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6993 | relax_end (); |
252b5132 | 6994 | if (breg != 0) |
67c0d1eb | 6995 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6996 | tempreg, tempreg, breg); |
67c0d1eb | 6997 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6998 | } |
0a44bf69 | 6999 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7000 | { |
67c0d1eb | 7001 | int gpdelay; |
252b5132 RH |
7002 | |
7003 | /* If this is a reference to an external symbol, we want | |
7004 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7005 | addu $tempreg,$tempreg,$gp | |
7006 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7007 | <op> $treg,0($tempreg) | |
7008 | Otherwise we want | |
7009 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7010 | nop | |
7011 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7012 | <op> $treg,0($tempreg) | |
7013 | If there is a base register, we add it to $tempreg before | |
7014 | the <op>. If there is a constant, we stick it in the | |
7015 | <op> instruction. We don't handle constants larger than | |
7016 | 16 bits, because we have no way to load the upper 16 bits | |
7017 | (actually, we could handle them for the subset of cases | |
f5040a92 | 7018 | in which we are not using $at). */ |
9c2799c2 | 7019 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
7020 | expr1.X_add_number = offset_expr.X_add_number; |
7021 | offset_expr.X_add_number = 0; | |
7022 | if (expr1.X_add_number < -0x8000 | |
7023 | || expr1.X_add_number >= 0x8000) | |
7024 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7025 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7026 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7027 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7028 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7029 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7030 | mips_gp_register); | |
7031 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7032 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 7033 | relax_switch (); |
67c0d1eb RS |
7034 | if (gpdelay) |
7035 | macro_build (NULL, "nop", ""); | |
7036 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7037 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7038 | load_delay_nop (); |
67c0d1eb RS |
7039 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
7040 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7041 | relax_end (); |
7042 | ||
252b5132 | 7043 | if (breg != 0) |
67c0d1eb | 7044 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7045 | tempreg, tempreg, breg); |
67c0d1eb | 7046 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 7047 | } |
0a44bf69 | 7048 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7049 | { |
f5040a92 AO |
7050 | /* If this is a reference to an external symbol, we want |
7051 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7052 | add $tempreg,$tempreg,$gp | |
7053 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7054 | <op> $treg,<ofst>($tempreg) | |
7055 | Otherwise, for local symbols, we want: | |
7056 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7057 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 7058 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 7059 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7060 | offset_expr.X_add_number = 0; |
7061 | if (expr1.X_add_number < -0x8000 | |
7062 | || expr1.X_add_number >= 0x8000) | |
7063 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 7064 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7065 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7066 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7067 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7068 | mips_gp_register); | |
7069 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7070 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 7071 | if (breg != 0) |
67c0d1eb | 7072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7073 | tempreg, tempreg, breg); |
67c0d1eb | 7074 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 7075 | |
4d7206a2 | 7076 | relax_switch (); |
f5040a92 | 7077 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7078 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7079 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 7080 | if (breg != 0) |
67c0d1eb | 7081 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7082 | tempreg, tempreg, breg); |
67c0d1eb | 7083 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7084 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 7085 | relax_end (); |
f5040a92 | 7086 | } |
252b5132 RH |
7087 | else |
7088 | abort (); | |
7089 | ||
252b5132 RH |
7090 | break; |
7091 | ||
7092 | case M_LI: | |
7093 | case M_LI_S: | |
67c0d1eb | 7094 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 7095 | break; |
252b5132 RH |
7096 | |
7097 | case M_DLI: | |
67c0d1eb | 7098 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 7099 | break; |
252b5132 RH |
7100 | |
7101 | case M_LI_SS: | |
7102 | if (imm_expr.X_op == O_constant) | |
7103 | { | |
8fc2e39e | 7104 | used_at = 1; |
67c0d1eb RS |
7105 | load_register (AT, &imm_expr, 0); |
7106 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7107 | break; |
7108 | } | |
7109 | else | |
7110 | { | |
9c2799c2 | 7111 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
7112 | && strcmp (segment_name (S_GET_SEGMENT |
7113 | (offset_expr.X_add_symbol)), | |
7114 | ".lit4") == 0 | |
7115 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 7116 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 7117 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7118 | break; |
252b5132 RH |
7119 | } |
7120 | ||
7121 | case M_LI_D: | |
ca4e0257 RS |
7122 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
7123 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
7124 | order 32 bits of the value and the low order 32 bits are either | |
7125 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
7126 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7127 | { | |
ca4e0257 | 7128 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 7129 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
7130 | else |
7131 | { | |
7132 | int hreg, lreg; | |
7133 | ||
7134 | if (target_big_endian) | |
7135 | { | |
7136 | hreg = treg; | |
7137 | lreg = treg + 1; | |
7138 | } | |
7139 | else | |
7140 | { | |
7141 | hreg = treg + 1; | |
7142 | lreg = treg; | |
7143 | } | |
7144 | ||
7145 | if (hreg <= 31) | |
67c0d1eb | 7146 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
7147 | if (lreg <= 31) |
7148 | { | |
7149 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 7150 | move_register (lreg, 0); |
252b5132 RH |
7151 | else |
7152 | { | |
9c2799c2 | 7153 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 7154 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
7155 | } |
7156 | } | |
7157 | } | |
8fc2e39e | 7158 | break; |
252b5132 RH |
7159 | } |
7160 | ||
7161 | /* We know that sym is in the .rdata section. First we get the | |
7162 | upper 16 bits of the address. */ | |
7163 | if (mips_pic == NO_PIC) | |
7164 | { | |
67c0d1eb | 7165 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 7166 | used_at = 1; |
252b5132 | 7167 | } |
0a44bf69 | 7168 | else |
252b5132 | 7169 | { |
67c0d1eb RS |
7170 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7171 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 7172 | used_at = 1; |
252b5132 | 7173 | } |
bdaaa2e1 | 7174 | |
252b5132 | 7175 | /* Now we load the register(s). */ |
ca4e0257 | 7176 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
7177 | { |
7178 | used_at = 1; | |
7179 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
7180 | } | |
252b5132 RH |
7181 | else |
7182 | { | |
8fc2e39e | 7183 | used_at = 1; |
67c0d1eb | 7184 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 7185 | if (treg != RA) |
252b5132 RH |
7186 | { |
7187 | /* FIXME: How in the world do we deal with the possible | |
7188 | overflow here? */ | |
7189 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7190 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 7191 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
7192 | } |
7193 | } | |
252b5132 RH |
7194 | break; |
7195 | ||
7196 | case M_LI_DD: | |
ca4e0257 RS |
7197 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
7198 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
7199 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
7200 | the value and the low order 32 bits are either zero or in | |
7201 | OFFSET_EXPR. */ | |
252b5132 RH |
7202 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7203 | { | |
8fc2e39e | 7204 | used_at = 1; |
67c0d1eb | 7205 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
7206 | if (HAVE_64BIT_FPRS) |
7207 | { | |
9c2799c2 | 7208 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7209 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7210 | } |
252b5132 RH |
7211 | else |
7212 | { | |
67c0d1eb | 7213 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7214 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7215 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7216 | else |
7217 | { | |
9c2799c2 | 7218 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7219 | load_register (AT, &offset_expr, 0); |
7220 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7221 | } |
7222 | } | |
7223 | break; | |
7224 | } | |
7225 | ||
9c2799c2 | 7226 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7227 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7228 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7229 | if (strcmp (s, ".lit8") == 0) | |
7230 | { | |
e7af610e | 7231 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7232 | { |
67c0d1eb | 7233 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7234 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7235 | break; |
252b5132 | 7236 | } |
c9914766 | 7237 | breg = mips_gp_register; |
252b5132 RH |
7238 | r = BFD_RELOC_MIPS_LITERAL; |
7239 | goto dob; | |
7240 | } | |
7241 | else | |
7242 | { | |
9c2799c2 | 7243 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7244 | used_at = 1; |
0a44bf69 | 7245 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7246 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7247 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7248 | else |
7249 | { | |
7250 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7251 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7252 | } |
bdaaa2e1 | 7253 | |
e7af610e | 7254 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7255 | { |
67c0d1eb RS |
7256 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7257 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7258 | break; |
7259 | } | |
7260 | breg = AT; | |
7261 | r = BFD_RELOC_LO16; | |
7262 | goto dob; | |
7263 | } | |
7264 | ||
7265 | case M_L_DOB: | |
252b5132 RH |
7266 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7267 | to adjust when loading from memory. */ | |
7268 | r = BFD_RELOC_LO16; | |
7269 | dob: | |
9c2799c2 | 7270 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7271 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7272 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7273 | /* FIXME: A possible overflow which I don't know how to deal |
7274 | with. */ | |
7275 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7276 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7277 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7278 | break; |
7279 | ||
c4a68bea MR |
7280 | case M_S_DOB: |
7281 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7282 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7283 | to adjust when storing to memory. */ | |
7284 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7285 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7286 | offset_expr.X_add_number += 4; | |
7287 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7288 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7289 | break; | |
7290 | ||
252b5132 RH |
7291 | case M_L_DAB: |
7292 | /* | |
7293 | * The MIPS assembler seems to check for X_add_number not | |
7294 | * being double aligned and generating: | |
7295 | * lui at,%hi(foo+1) | |
7296 | * addu at,at,v1 | |
7297 | * addiu at,at,%lo(foo+1) | |
7298 | * lwc1 f2,0(at) | |
7299 | * lwc1 f3,4(at) | |
7300 | * But, the resulting address is the same after relocation so why | |
7301 | * generate the extra instruction? | |
7302 | */ | |
bdaaa2e1 | 7303 | /* Itbl support may require additional care here. */ |
252b5132 | 7304 | coproc = 1; |
e7af610e | 7305 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7306 | { |
7307 | s = "ldc1"; | |
7308 | goto ld; | |
7309 | } | |
7310 | ||
7311 | s = "lwc1"; | |
7312 | fmt = "T,o(b)"; | |
7313 | goto ldd_std; | |
7314 | ||
7315 | case M_S_DAB: | |
e7af610e | 7316 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7317 | { |
7318 | s = "sdc1"; | |
7319 | goto st; | |
7320 | } | |
7321 | ||
7322 | s = "swc1"; | |
7323 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7324 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7325 | coproc = 1; |
7326 | goto ldd_std; | |
7327 | ||
7328 | case M_LD_AB: | |
ca4e0257 | 7329 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7330 | { |
7331 | s = "ld"; | |
7332 | goto ld; | |
7333 | } | |
7334 | ||
7335 | s = "lw"; | |
7336 | fmt = "t,o(b)"; | |
7337 | goto ldd_std; | |
7338 | ||
7339 | case M_SD_AB: | |
ca4e0257 | 7340 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7341 | { |
7342 | s = "sd"; | |
7343 | goto st; | |
7344 | } | |
7345 | ||
7346 | s = "sw"; | |
7347 | fmt = "t,o(b)"; | |
7348 | ||
7349 | ldd_std: | |
7350 | if (offset_expr.X_op != O_symbol | |
7351 | && offset_expr.X_op != O_constant) | |
7352 | { | |
f71d0d44 | 7353 | as_bad (_("Expression too complex")); |
252b5132 RH |
7354 | offset_expr.X_op = O_constant; |
7355 | } | |
7356 | ||
2051e8c4 MR |
7357 | if (HAVE_32BIT_ADDRESSES |
7358 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7359 | { |
7360 | char value [32]; | |
7361 | ||
7362 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7363 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7364 | } |
2051e8c4 | 7365 | |
252b5132 RH |
7366 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7367 | to adjust when loading from memory. We set coproc if we must | |
7368 | load $fn+1 first. */ | |
bdaaa2e1 | 7369 | /* Itbl support may require additional care here. */ |
90ecf173 | 7370 | if (!target_big_endian) |
252b5132 RH |
7371 | coproc = 0; |
7372 | ||
90ecf173 | 7373 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7374 | { |
7375 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7376 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7377 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7378 | If we have a base register, we use this |
7379 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7380 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7381 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7382 | If this is not a GP relative symbol, we want |
7383 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7384 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7385 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7386 | If there is a base register, we add it to $at after the | |
7387 | lui instruction. If there is a constant, we always use | |
7388 | the last case. */ | |
39a59cf8 MR |
7389 | if (offset_expr.X_op == O_symbol |
7390 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7391 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7392 | { |
4d7206a2 | 7393 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7394 | if (breg == 0) |
7395 | { | |
c9914766 | 7396 | tempreg = mips_gp_register; |
252b5132 RH |
7397 | } |
7398 | else | |
7399 | { | |
67c0d1eb | 7400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7401 | AT, breg, mips_gp_register); |
252b5132 | 7402 | tempreg = AT; |
252b5132 RH |
7403 | used_at = 1; |
7404 | } | |
7405 | ||
beae10d5 | 7406 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7407 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7408 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7409 | offset_expr.X_add_number += 4; |
7410 | ||
7411 | /* Set mips_optimize to 2 to avoid inserting an | |
7412 | undesired nop. */ | |
7413 | hold_mips_optimize = mips_optimize; | |
7414 | mips_optimize = 2; | |
beae10d5 | 7415 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7416 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7417 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7418 | mips_optimize = hold_mips_optimize; |
7419 | ||
4d7206a2 | 7420 | relax_switch (); |
252b5132 | 7421 | |
0970e49e | 7422 | offset_expr.X_add_number -= 4; |
252b5132 | 7423 | } |
8fc2e39e | 7424 | used_at = 1; |
67c0d1eb | 7425 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7426 | if (breg != 0) |
67c0d1eb | 7427 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7428 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7429 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7430 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7431 | /* FIXME: How do we handle overflow here? */ |
7432 | offset_expr.X_add_number += 4; | |
beae10d5 | 7433 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7434 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7435 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7436 | if (mips_relax.sequence) |
7437 | relax_end (); | |
bdaaa2e1 | 7438 | } |
0a44bf69 | 7439 | else if (!mips_big_got) |
252b5132 | 7440 | { |
252b5132 RH |
7441 | /* If this is a reference to an external symbol, we want |
7442 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7443 | nop | |
7444 | <op> $treg,0($at) | |
7445 | <op> $treg+1,4($at) | |
7446 | Otherwise we want | |
7447 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7448 | nop | |
7449 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7450 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7451 | If there is a base register we add it to $at before the | |
7452 | lwc1 instructions. If there is a constant we include it | |
7453 | in the lwc1 instructions. */ | |
7454 | used_at = 1; | |
7455 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7456 | if (expr1.X_add_number < -0x8000 |
7457 | || expr1.X_add_number >= 0x8000 - 4) | |
7458 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7459 | load_got_offset (AT, &offset_expr); |
269137b2 | 7460 | load_delay_nop (); |
252b5132 | 7461 | if (breg != 0) |
67c0d1eb | 7462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7463 | |
7464 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7465 | nop. */ | |
7466 | hold_mips_optimize = mips_optimize; | |
7467 | mips_optimize = 2; | |
4d7206a2 | 7468 | |
beae10d5 | 7469 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7470 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7471 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7472 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7473 | expr1.X_add_number += 4; |
67c0d1eb RS |
7474 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7475 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7476 | relax_switch (); |
67c0d1eb RS |
7477 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7478 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7479 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7480 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7481 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7482 | relax_end (); |
252b5132 | 7483 | |
4d7206a2 | 7484 | mips_optimize = hold_mips_optimize; |
252b5132 | 7485 | } |
0a44bf69 | 7486 | else if (mips_big_got) |
252b5132 | 7487 | { |
67c0d1eb | 7488 | int gpdelay; |
252b5132 RH |
7489 | |
7490 | /* If this is a reference to an external symbol, we want | |
7491 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7492 | addu $at,$at,$gp | |
7493 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7494 | nop | |
7495 | <op> $treg,0($at) | |
7496 | <op> $treg+1,4($at) | |
7497 | Otherwise we want | |
7498 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7499 | nop | |
7500 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7501 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7502 | If there is a base register we add it to $at before the | |
7503 | lwc1 instructions. If there is a constant we include it | |
7504 | in the lwc1 instructions. */ | |
7505 | used_at = 1; | |
7506 | expr1.X_add_number = offset_expr.X_add_number; | |
7507 | offset_expr.X_add_number = 0; | |
7508 | if (expr1.X_add_number < -0x8000 | |
7509 | || expr1.X_add_number >= 0x8000 - 4) | |
7510 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7511 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7512 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7513 | macro_build (&offset_expr, "lui", "t,u", |
7514 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7515 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7516 | AT, AT, mips_gp_register); |
67c0d1eb | 7517 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7518 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7519 | load_delay_nop (); |
252b5132 | 7520 | if (breg != 0) |
67c0d1eb | 7521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7522 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7523 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7524 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7525 | expr1.X_add_number += 4; |
7526 | ||
7527 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7528 | nop. */ | |
7529 | hold_mips_optimize = mips_optimize; | |
7530 | mips_optimize = 2; | |
beae10d5 | 7531 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7532 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7533 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7534 | mips_optimize = hold_mips_optimize; |
7535 | expr1.X_add_number -= 4; | |
7536 | ||
4d7206a2 RS |
7537 | relax_switch (); |
7538 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7539 | if (gpdelay) |
7540 | macro_build (NULL, "nop", ""); | |
7541 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7542 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7543 | load_delay_nop (); |
252b5132 | 7544 | if (breg != 0) |
67c0d1eb | 7545 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7546 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7547 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7548 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7549 | offset_expr.X_add_number += 4; |
252b5132 RH |
7550 | |
7551 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7552 | nop. */ | |
7553 | hold_mips_optimize = mips_optimize; | |
7554 | mips_optimize = 2; | |
beae10d5 | 7555 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7556 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7557 | BFD_RELOC_LO16, AT); | |
252b5132 | 7558 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7559 | relax_end (); |
252b5132 | 7560 | } |
252b5132 RH |
7561 | else |
7562 | abort (); | |
7563 | ||
252b5132 RH |
7564 | break; |
7565 | ||
7566 | case M_LD_OB: | |
704897fb | 7567 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7568 | goto sd_ob; |
7569 | case M_SD_OB: | |
704897fb | 7570 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7571 | sd_ob: |
4614d845 MR |
7572 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7573 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7574 | breg); | |
704897fb MR |
7575 | if (!HAVE_64BIT_GPRS) |
7576 | { | |
7577 | offset_expr.X_add_number += 4; | |
7578 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7579 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7580 | breg); | |
704897fb | 7581 | } |
8fc2e39e | 7582 | break; |
252b5132 RH |
7583 | |
7584 | /* New code added to support COPZ instructions. | |
7585 | This code builds table entries out of the macros in mip_opcodes. | |
7586 | R4000 uses interlocks to handle coproc delays. | |
7587 | Other chips (like the R3000) require nops to be inserted for delays. | |
7588 | ||
f72c8c98 | 7589 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7590 | In order to fill delay slots for non-interlocked chips, |
7591 | we must have a way to specify delays based on the coprocessor. | |
7592 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7593 | What are the side-effects of the cop instruction? | |
7594 | What cache support might we have and what are its effects? | |
7595 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7596 | What registers are read/set/modified? |
252b5132 RH |
7597 | |
7598 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7599 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7600 | |
7601 | case M_COP0: | |
7602 | s = "c0"; | |
7603 | goto copz; | |
7604 | case M_COP1: | |
7605 | s = "c1"; | |
7606 | goto copz; | |
7607 | case M_COP2: | |
7608 | s = "c2"; | |
7609 | goto copz; | |
7610 | case M_COP3: | |
7611 | s = "c3"; | |
7612 | copz: | |
b19e8a9b AN |
7613 | if (NO_ISA_COP (mips_opts.arch) |
7614 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7615 | { | |
7616 | as_bad (_("opcode not supported on this processor: %s"), | |
7617 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7618 | break; | |
7619 | } | |
7620 | ||
252b5132 RH |
7621 | /* For now we just do C (same as Cz). The parameter will be |
7622 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7623 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7624 | break; |
252b5132 | 7625 | |
ea1fb5dc | 7626 | case M_MOVE: |
67c0d1eb | 7627 | move_register (dreg, sreg); |
8fc2e39e | 7628 | break; |
ea1fb5dc | 7629 | |
252b5132 RH |
7630 | case M_DMUL: |
7631 | dbl = 1; | |
7632 | case M_MUL: | |
67c0d1eb RS |
7633 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7634 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7635 | break; |
252b5132 RH |
7636 | |
7637 | case M_DMUL_I: | |
7638 | dbl = 1; | |
7639 | case M_MUL_I: | |
7640 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7641 | not trying to be that fancy. GCC should do this for us | |
7642 | anyway. */ | |
8fc2e39e | 7643 | used_at = 1; |
67c0d1eb RS |
7644 | load_register (AT, &imm_expr, dbl); |
7645 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7646 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7647 | break; |
7648 | ||
7649 | case M_DMULO_I: | |
7650 | dbl = 1; | |
7651 | case M_MULO_I: | |
7652 | imm = 1; | |
7653 | goto do_mulo; | |
7654 | ||
7655 | case M_DMULO: | |
7656 | dbl = 1; | |
7657 | case M_MULO: | |
7658 | do_mulo: | |
7d10b47d | 7659 | start_noreorder (); |
8fc2e39e | 7660 | used_at = 1; |
252b5132 | 7661 | if (imm) |
67c0d1eb RS |
7662 | load_register (AT, &imm_expr, dbl); |
7663 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7664 | macro_build (NULL, "mflo", "d", dreg); | |
7665 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7666 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7667 | if (mips_trap) |
67c0d1eb | 7668 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7669 | else |
7670 | { | |
7671 | expr1.X_add_number = 8; | |
67c0d1eb | 7672 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7673 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7674 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7675 | } |
7d10b47d | 7676 | end_noreorder (); |
67c0d1eb | 7677 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7678 | break; |
7679 | ||
7680 | case M_DMULOU_I: | |
7681 | dbl = 1; | |
7682 | case M_MULOU_I: | |
7683 | imm = 1; | |
7684 | goto do_mulou; | |
7685 | ||
7686 | case M_DMULOU: | |
7687 | dbl = 1; | |
7688 | case M_MULOU: | |
7689 | do_mulou: | |
7d10b47d | 7690 | start_noreorder (); |
8fc2e39e | 7691 | used_at = 1; |
252b5132 | 7692 | if (imm) |
67c0d1eb RS |
7693 | load_register (AT, &imm_expr, dbl); |
7694 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7695 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7696 | macro_build (NULL, "mfhi", "d", AT); |
7697 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7698 | if (mips_trap) |
c80c840e | 7699 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7700 | else |
7701 | { | |
7702 | expr1.X_add_number = 8; | |
c80c840e | 7703 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7704 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7705 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7706 | } |
7d10b47d | 7707 | end_noreorder (); |
252b5132 RH |
7708 | break; |
7709 | ||
771c7ce4 | 7710 | case M_DROL: |
fef14a42 | 7711 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7712 | { |
7713 | if (dreg == sreg) | |
7714 | { | |
7715 | tempreg = AT; | |
7716 | used_at = 1; | |
7717 | } | |
7718 | else | |
7719 | { | |
7720 | tempreg = dreg; | |
82dd0097 | 7721 | } |
67c0d1eb RS |
7722 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7723 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7724 | break; |
82dd0097 | 7725 | } |
8fc2e39e | 7726 | used_at = 1; |
c80c840e | 7727 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7728 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7729 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7730 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7731 | break; |
7732 | ||
252b5132 | 7733 | case M_ROL: |
fef14a42 | 7734 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7735 | { |
7736 | if (dreg == sreg) | |
7737 | { | |
7738 | tempreg = AT; | |
7739 | used_at = 1; | |
7740 | } | |
7741 | else | |
7742 | { | |
7743 | tempreg = dreg; | |
82dd0097 | 7744 | } |
67c0d1eb RS |
7745 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7746 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7747 | break; |
82dd0097 | 7748 | } |
8fc2e39e | 7749 | used_at = 1; |
c80c840e | 7750 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7751 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7752 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7753 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7754 | break; |
7755 | ||
771c7ce4 TS |
7756 | case M_DROL_I: |
7757 | { | |
7758 | unsigned int rot; | |
91d6fa6a NC |
7759 | char *l; |
7760 | char *rr; | |
771c7ce4 TS |
7761 | |
7762 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7763 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7764 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7765 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7766 | { |
7767 | rot = (64 - rot) & 0x3f; | |
7768 | if (rot >= 32) | |
67c0d1eb | 7769 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7770 | else |
67c0d1eb | 7771 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7772 | break; |
60b63b72 | 7773 | } |
483fc7cd | 7774 | if (rot == 0) |
483fc7cd | 7775 | { |
67c0d1eb | 7776 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7777 | break; |
483fc7cd | 7778 | } |
82dd0097 | 7779 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7780 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7781 | rot &= 0x1f; |
8fc2e39e | 7782 | used_at = 1; |
67c0d1eb | 7783 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7784 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7785 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7786 | } |
7787 | break; | |
7788 | ||
252b5132 | 7789 | case M_ROL_I: |
771c7ce4 TS |
7790 | { |
7791 | unsigned int rot; | |
7792 | ||
7793 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7794 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7795 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7796 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7797 | { |
67c0d1eb | 7798 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7799 | break; |
60b63b72 | 7800 | } |
483fc7cd | 7801 | if (rot == 0) |
483fc7cd | 7802 | { |
67c0d1eb | 7803 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7804 | break; |
483fc7cd | 7805 | } |
8fc2e39e | 7806 | used_at = 1; |
67c0d1eb RS |
7807 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7808 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7809 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7810 | } |
7811 | break; | |
7812 | ||
7813 | case M_DROR: | |
fef14a42 | 7814 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7815 | { |
67c0d1eb | 7816 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7817 | break; |
82dd0097 | 7818 | } |
8fc2e39e | 7819 | used_at = 1; |
c80c840e | 7820 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7821 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7822 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7823 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7824 | break; |
7825 | ||
7826 | case M_ROR: | |
fef14a42 | 7827 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7828 | { |
67c0d1eb | 7829 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7830 | break; |
82dd0097 | 7831 | } |
8fc2e39e | 7832 | used_at = 1; |
c80c840e | 7833 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7834 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7835 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7836 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7837 | break; |
7838 | ||
771c7ce4 TS |
7839 | case M_DROR_I: |
7840 | { | |
7841 | unsigned int rot; | |
91d6fa6a NC |
7842 | char *l; |
7843 | char *rr; | |
771c7ce4 TS |
7844 | |
7845 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7846 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7847 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7848 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7849 | { |
7850 | if (rot >= 32) | |
67c0d1eb | 7851 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7852 | else |
67c0d1eb | 7853 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7854 | break; |
82dd0097 | 7855 | } |
483fc7cd | 7856 | if (rot == 0) |
483fc7cd | 7857 | { |
67c0d1eb | 7858 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7859 | break; |
483fc7cd | 7860 | } |
91d6fa6a | 7861 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7862 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7863 | rot &= 0x1f; | |
8fc2e39e | 7864 | used_at = 1; |
91d6fa6a | 7865 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7866 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7867 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7868 | } |
7869 | break; | |
7870 | ||
252b5132 | 7871 | case M_ROR_I: |
771c7ce4 TS |
7872 | { |
7873 | unsigned int rot; | |
7874 | ||
7875 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7876 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7877 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7878 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7879 | { |
67c0d1eb | 7880 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7881 | break; |
82dd0097 | 7882 | } |
483fc7cd | 7883 | if (rot == 0) |
483fc7cd | 7884 | { |
67c0d1eb | 7885 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7886 | break; |
483fc7cd | 7887 | } |
8fc2e39e | 7888 | used_at = 1; |
67c0d1eb RS |
7889 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7890 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7891 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7892 | } |
252b5132 RH |
7893 | break; |
7894 | ||
252b5132 RH |
7895 | case M_SEQ: |
7896 | if (sreg == 0) | |
67c0d1eb | 7897 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7898 | else if (treg == 0) |
67c0d1eb | 7899 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7900 | else |
7901 | { | |
67c0d1eb RS |
7902 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7903 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7904 | } |
8fc2e39e | 7905 | break; |
252b5132 RH |
7906 | |
7907 | case M_SEQ_I: | |
7908 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7909 | { | |
67c0d1eb | 7910 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7911 | break; |
252b5132 RH |
7912 | } |
7913 | if (sreg == 0) | |
7914 | { | |
7915 | as_warn (_("Instruction %s: result is always false"), | |
7916 | ip->insn_mo->name); | |
67c0d1eb | 7917 | move_register (dreg, 0); |
8fc2e39e | 7918 | break; |
252b5132 | 7919 | } |
dd3cbb7e NC |
7920 | if (CPU_HAS_SEQ (mips_opts.arch) |
7921 | && -512 <= imm_expr.X_add_number | |
7922 | && imm_expr.X_add_number < 512) | |
7923 | { | |
7924 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7925 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7926 | break; |
7927 | } | |
252b5132 RH |
7928 | if (imm_expr.X_op == O_constant |
7929 | && imm_expr.X_add_number >= 0 | |
7930 | && imm_expr.X_add_number < 0x10000) | |
7931 | { | |
67c0d1eb | 7932 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7933 | } |
7934 | else if (imm_expr.X_op == O_constant | |
7935 | && imm_expr.X_add_number > -0x8000 | |
7936 | && imm_expr.X_add_number < 0) | |
7937 | { | |
7938 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7939 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7940 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7941 | } |
dd3cbb7e NC |
7942 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7943 | { | |
7944 | used_at = 1; | |
7945 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7946 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7947 | break; | |
7948 | } | |
252b5132 RH |
7949 | else |
7950 | { | |
67c0d1eb RS |
7951 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7952 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7953 | used_at = 1; |
7954 | } | |
67c0d1eb | 7955 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7956 | break; |
252b5132 RH |
7957 | |
7958 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7959 | s = "slt"; | |
7960 | goto sge; | |
7961 | case M_SGEU: | |
7962 | s = "sltu"; | |
7963 | sge: | |
67c0d1eb RS |
7964 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7965 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7966 | break; |
252b5132 RH |
7967 | |
7968 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7969 | case M_SGEU_I: | |
7970 | if (imm_expr.X_op == O_constant | |
7971 | && imm_expr.X_add_number >= -0x8000 | |
7972 | && imm_expr.X_add_number < 0x8000) | |
7973 | { | |
67c0d1eb RS |
7974 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7975 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7976 | } |
7977 | else | |
7978 | { | |
67c0d1eb RS |
7979 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7980 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7981 | dreg, sreg, AT); | |
252b5132 RH |
7982 | used_at = 1; |
7983 | } | |
67c0d1eb | 7984 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7985 | break; |
252b5132 RH |
7986 | |
7987 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7988 | s = "slt"; | |
7989 | goto sgt; | |
7990 | case M_SGTU: | |
7991 | s = "sltu"; | |
7992 | sgt: | |
67c0d1eb | 7993 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7994 | break; |
252b5132 RH |
7995 | |
7996 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7997 | s = "slt"; | |
7998 | goto sgti; | |
7999 | case M_SGTU_I: | |
8000 | s = "sltu"; | |
8001 | sgti: | |
8fc2e39e | 8002 | used_at = 1; |
67c0d1eb RS |
8003 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8004 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
8005 | break; |
8006 | ||
2396cfb9 | 8007 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
8008 | s = "slt"; |
8009 | goto sle; | |
8010 | case M_SLEU: | |
8011 | s = "sltu"; | |
8012 | sle: | |
67c0d1eb RS |
8013 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8014 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 8015 | break; |
252b5132 | 8016 | |
2396cfb9 | 8017 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
8018 | s = "slt"; |
8019 | goto slei; | |
8020 | case M_SLEU_I: | |
8021 | s = "sltu"; | |
8022 | slei: | |
8fc2e39e | 8023 | used_at = 1; |
67c0d1eb RS |
8024 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8025 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
8026 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
8027 | break; |
8028 | ||
8029 | case M_SLT_I: | |
8030 | if (imm_expr.X_op == O_constant | |
8031 | && imm_expr.X_add_number >= -0x8000 | |
8032 | && imm_expr.X_add_number < 0x8000) | |
8033 | { | |
67c0d1eb | 8034 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 8035 | break; |
252b5132 | 8036 | } |
8fc2e39e | 8037 | used_at = 1; |
67c0d1eb RS |
8038 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8039 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8040 | break; |
8041 | ||
8042 | case M_SLTU_I: | |
8043 | if (imm_expr.X_op == O_constant | |
8044 | && imm_expr.X_add_number >= -0x8000 | |
8045 | && imm_expr.X_add_number < 0x8000) | |
8046 | { | |
67c0d1eb | 8047 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 8048 | BFD_RELOC_LO16); |
8fc2e39e | 8049 | break; |
252b5132 | 8050 | } |
8fc2e39e | 8051 | used_at = 1; |
67c0d1eb RS |
8052 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8053 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8054 | break; |
8055 | ||
8056 | case M_SNE: | |
8057 | if (sreg == 0) | |
67c0d1eb | 8058 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 8059 | else if (treg == 0) |
67c0d1eb | 8060 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
8061 | else |
8062 | { | |
67c0d1eb RS |
8063 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
8064 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 8065 | } |
8fc2e39e | 8066 | break; |
252b5132 RH |
8067 | |
8068 | case M_SNE_I: | |
8069 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
8070 | { | |
67c0d1eb | 8071 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 8072 | break; |
252b5132 RH |
8073 | } |
8074 | if (sreg == 0) | |
8075 | { | |
8076 | as_warn (_("Instruction %s: result is always true"), | |
8077 | ip->insn_mo->name); | |
67c0d1eb RS |
8078 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
8079 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 8080 | break; |
252b5132 | 8081 | } |
dd3cbb7e NC |
8082 | if (CPU_HAS_SEQ (mips_opts.arch) |
8083 | && -512 <= imm_expr.X_add_number | |
8084 | && imm_expr.X_add_number < 512) | |
8085 | { | |
8086 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 8087 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
8088 | break; |
8089 | } | |
252b5132 RH |
8090 | if (imm_expr.X_op == O_constant |
8091 | && imm_expr.X_add_number >= 0 | |
8092 | && imm_expr.X_add_number < 0x10000) | |
8093 | { | |
67c0d1eb | 8094 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
8095 | } |
8096 | else if (imm_expr.X_op == O_constant | |
8097 | && imm_expr.X_add_number > -0x8000 | |
8098 | && imm_expr.X_add_number < 0) | |
8099 | { | |
8100 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8101 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 8102 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 8103 | } |
dd3cbb7e NC |
8104 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
8105 | { | |
8106 | used_at = 1; | |
8107 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
8108 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
8109 | break; | |
8110 | } | |
252b5132 RH |
8111 | else |
8112 | { | |
67c0d1eb RS |
8113 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8114 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8115 | used_at = 1; |
8116 | } | |
67c0d1eb | 8117 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 8118 | break; |
252b5132 RH |
8119 | |
8120 | case M_DSUB_I: | |
8121 | dbl = 1; | |
8122 | case M_SUB_I: | |
8123 | if (imm_expr.X_op == O_constant | |
8124 | && imm_expr.X_add_number > -0x8000 | |
8125 | && imm_expr.X_add_number <= 0x8000) | |
8126 | { | |
8127 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8128 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
8129 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8130 | break; |
252b5132 | 8131 | } |
8fc2e39e | 8132 | used_at = 1; |
67c0d1eb RS |
8133 | load_register (AT, &imm_expr, dbl); |
8134 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8135 | break; |
8136 | ||
8137 | case M_DSUBU_I: | |
8138 | dbl = 1; | |
8139 | case M_SUBU_I: | |
8140 | if (imm_expr.X_op == O_constant | |
8141 | && imm_expr.X_add_number > -0x8000 | |
8142 | && imm_expr.X_add_number <= 0x8000) | |
8143 | { | |
8144 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8145 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
8146 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8147 | break; |
252b5132 | 8148 | } |
8fc2e39e | 8149 | used_at = 1; |
67c0d1eb RS |
8150 | load_register (AT, &imm_expr, dbl); |
8151 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8152 | break; |
8153 | ||
8154 | case M_TEQ_I: | |
8155 | s = "teq"; | |
8156 | goto trap; | |
8157 | case M_TGE_I: | |
8158 | s = "tge"; | |
8159 | goto trap; | |
8160 | case M_TGEU_I: | |
8161 | s = "tgeu"; | |
8162 | goto trap; | |
8163 | case M_TLT_I: | |
8164 | s = "tlt"; | |
8165 | goto trap; | |
8166 | case M_TLTU_I: | |
8167 | s = "tltu"; | |
8168 | goto trap; | |
8169 | case M_TNE_I: | |
8170 | s = "tne"; | |
8171 | trap: | |
8fc2e39e | 8172 | used_at = 1; |
67c0d1eb RS |
8173 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8174 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
8175 | break; |
8176 | ||
252b5132 | 8177 | case M_TRUNCWS: |
43841e91 | 8178 | case M_TRUNCWD: |
9c2799c2 | 8179 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8180 | used_at = 1; |
252b5132 RH |
8181 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8182 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8183 | ||
8184 | /* | |
8185 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8186 | * or is there a reason for it? | |
8187 | */ | |
7d10b47d | 8188 | start_noreorder (); |
67c0d1eb RS |
8189 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8190 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8191 | macro_build (NULL, "nop", ""); | |
252b5132 | 8192 | expr1.X_add_number = 3; |
67c0d1eb | 8193 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8194 | expr1.X_add_number = 2; |
67c0d1eb RS |
8195 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8196 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8197 | macro_build (NULL, "nop", ""); | |
8198 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8199 | dreg, sreg); | |
8200 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8201 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8202 | end_noreorder (); |
252b5132 RH |
8203 | break; |
8204 | ||
8205 | case M_ULH: | |
8206 | s = "lb"; | |
8207 | goto ulh; | |
8208 | case M_ULHU: | |
8209 | s = "lbu"; | |
8210 | ulh: | |
8fc2e39e | 8211 | used_at = 1; |
252b5132 | 8212 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8213 | as_bad (_("Operand overflow")); |
90ecf173 | 8214 | if (!target_big_endian) |
f9419b05 | 8215 | ++offset_expr.X_add_number; |
67c0d1eb | 8216 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8217 | if (!target_big_endian) |
f9419b05 | 8218 | --offset_expr.X_add_number; |
252b5132 | 8219 | else |
f9419b05 | 8220 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8221 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8222 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8223 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8224 | break; |
8225 | ||
8226 | case M_ULD: | |
8227 | s = "ldl"; | |
8228 | s2 = "ldr"; | |
8229 | off = 7; | |
8230 | goto ulw; | |
8231 | case M_ULW: | |
8232 | s = "lwl"; | |
8233 | s2 = "lwr"; | |
8234 | off = 3; | |
8235 | ulw: | |
8236 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8237 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8238 | if (treg != breg) |
8239 | tempreg = treg; | |
8240 | else | |
8fc2e39e TS |
8241 | { |
8242 | used_at = 1; | |
8243 | tempreg = AT; | |
8244 | } | |
90ecf173 | 8245 | if (!target_big_endian) |
252b5132 | 8246 | offset_expr.X_add_number += off; |
67c0d1eb | 8247 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8248 | if (!target_big_endian) |
252b5132 RH |
8249 | offset_expr.X_add_number -= off; |
8250 | else | |
8251 | offset_expr.X_add_number += off; | |
67c0d1eb | 8252 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8253 | |
90ecf173 | 8254 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8255 | if (treg == tempreg) |
8fc2e39e | 8256 | break; |
af22f5b2 | 8257 | /* Protect second load's delay slot. */ |
017315e4 | 8258 | load_delay_nop (); |
67c0d1eb | 8259 | move_register (treg, tempreg); |
af22f5b2 | 8260 | break; |
252b5132 RH |
8261 | |
8262 | case M_ULD_A: | |
8263 | s = "ldl"; | |
8264 | s2 = "ldr"; | |
8265 | off = 7; | |
8266 | goto ulwa; | |
8267 | case M_ULW_A: | |
8268 | s = "lwl"; | |
8269 | s2 = "lwr"; | |
8270 | off = 3; | |
8271 | ulwa: | |
d6bc6245 | 8272 | used_at = 1; |
67c0d1eb | 8273 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8274 | if (breg != 0) |
67c0d1eb | 8275 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8276 | if (!target_big_endian) |
252b5132 RH |
8277 | expr1.X_add_number = off; |
8278 | else | |
8279 | expr1.X_add_number = 0; | |
67c0d1eb | 8280 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8281 | if (!target_big_endian) |
252b5132 RH |
8282 | expr1.X_add_number = 0; |
8283 | else | |
8284 | expr1.X_add_number = off; | |
67c0d1eb | 8285 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8286 | break; |
8287 | ||
8288 | case M_ULH_A: | |
8289 | case M_ULHU_A: | |
d6bc6245 | 8290 | used_at = 1; |
67c0d1eb | 8291 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8292 | if (breg != 0) |
67c0d1eb | 8293 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8294 | if (target_big_endian) |
8295 | expr1.X_add_number = 0; | |
67c0d1eb | 8296 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8297 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8298 | if (target_big_endian) |
8299 | expr1.X_add_number = 1; | |
8300 | else | |
8301 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8302 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8303 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8304 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8305 | break; |
8306 | ||
8307 | case M_USH: | |
8fc2e39e | 8308 | used_at = 1; |
252b5132 | 8309 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8310 | as_bad (_("Operand overflow")); |
252b5132 | 8311 | if (target_big_endian) |
f9419b05 | 8312 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8313 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8314 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8315 | if (target_big_endian) |
f9419b05 | 8316 | --offset_expr.X_add_number; |
252b5132 | 8317 | else |
f9419b05 | 8318 | ++offset_expr.X_add_number; |
67c0d1eb | 8319 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8320 | break; |
8321 | ||
8322 | case M_USD: | |
8323 | s = "sdl"; | |
8324 | s2 = "sdr"; | |
8325 | off = 7; | |
8326 | goto usw; | |
8327 | case M_USW: | |
8328 | s = "swl"; | |
8329 | s2 = "swr"; | |
8330 | off = 3; | |
8331 | usw: | |
8332 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8333 | as_bad (_("Operand overflow")); |
90ecf173 | 8334 | if (!target_big_endian) |
252b5132 | 8335 | offset_expr.X_add_number += off; |
67c0d1eb | 8336 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8337 | if (!target_big_endian) |
252b5132 RH |
8338 | offset_expr.X_add_number -= off; |
8339 | else | |
8340 | offset_expr.X_add_number += off; | |
67c0d1eb | 8341 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8342 | break; |
252b5132 RH |
8343 | |
8344 | case M_USD_A: | |
8345 | s = "sdl"; | |
8346 | s2 = "sdr"; | |
8347 | off = 7; | |
8348 | goto uswa; | |
8349 | case M_USW_A: | |
8350 | s = "swl"; | |
8351 | s2 = "swr"; | |
8352 | off = 3; | |
8353 | uswa: | |
d6bc6245 | 8354 | used_at = 1; |
67c0d1eb | 8355 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8356 | if (breg != 0) |
67c0d1eb | 8357 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8358 | if (!target_big_endian) |
252b5132 RH |
8359 | expr1.X_add_number = off; |
8360 | else | |
8361 | expr1.X_add_number = 0; | |
67c0d1eb | 8362 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8363 | if (!target_big_endian) |
252b5132 RH |
8364 | expr1.X_add_number = 0; |
8365 | else | |
8366 | expr1.X_add_number = off; | |
67c0d1eb | 8367 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8368 | break; |
8369 | ||
8370 | case M_USH_A: | |
d6bc6245 | 8371 | used_at = 1; |
67c0d1eb | 8372 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8373 | if (breg != 0) |
67c0d1eb | 8374 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8375 | if (!target_big_endian) |
252b5132 | 8376 | expr1.X_add_number = 0; |
67c0d1eb RS |
8377 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8378 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8379 | if (!target_big_endian) |
252b5132 RH |
8380 | expr1.X_add_number = 1; |
8381 | else | |
8382 | expr1.X_add_number = 0; | |
67c0d1eb | 8383 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8384 | if (!target_big_endian) |
252b5132 RH |
8385 | expr1.X_add_number = 0; |
8386 | else | |
8387 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8388 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8389 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8390 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8391 | break; |
8392 | ||
8393 | default: | |
8394 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8395 | are added dynamically. */ |
252b5132 RH |
8396 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8397 | break; | |
8398 | } | |
741fe287 | 8399 | if (!mips_opts.at && used_at) |
8fc2e39e | 8400 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8401 | } |
8402 | ||
8403 | /* Implement macros in mips16 mode. */ | |
8404 | ||
8405 | static void | |
17a2f251 | 8406 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8407 | { |
8408 | int mask; | |
8409 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8410 | expressionS expr1; |
8411 | int dbl; | |
8412 | const char *s, *s2, *s3; | |
8413 | ||
8414 | mask = ip->insn_mo->mask; | |
8415 | ||
bf12938e RS |
8416 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8417 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8418 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8419 | |
252b5132 RH |
8420 | expr1.X_op = O_constant; |
8421 | expr1.X_op_symbol = NULL; | |
8422 | expr1.X_add_symbol = NULL; | |
8423 | expr1.X_add_number = 1; | |
8424 | ||
8425 | dbl = 0; | |
8426 | ||
8427 | switch (mask) | |
8428 | { | |
8429 | default: | |
8430 | internalError (); | |
8431 | ||
8432 | case M_DDIV_3: | |
8433 | dbl = 1; | |
8434 | case M_DIV_3: | |
8435 | s = "mflo"; | |
8436 | goto do_div3; | |
8437 | case M_DREM_3: | |
8438 | dbl = 1; | |
8439 | case M_REM_3: | |
8440 | s = "mfhi"; | |
8441 | do_div3: | |
7d10b47d | 8442 | start_noreorder (); |
67c0d1eb | 8443 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8444 | expr1.X_add_number = 2; |
67c0d1eb RS |
8445 | macro_build (&expr1, "bnez", "x,p", yreg); |
8446 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8447 | |
252b5132 RH |
8448 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8449 | since that causes an overflow. We should do that as well, | |
8450 | but I don't see how to do the comparisons without a temporary | |
8451 | register. */ | |
7d10b47d | 8452 | end_noreorder (); |
67c0d1eb | 8453 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8454 | break; |
8455 | ||
8456 | case M_DIVU_3: | |
8457 | s = "divu"; | |
8458 | s2 = "mflo"; | |
8459 | goto do_divu3; | |
8460 | case M_REMU_3: | |
8461 | s = "divu"; | |
8462 | s2 = "mfhi"; | |
8463 | goto do_divu3; | |
8464 | case M_DDIVU_3: | |
8465 | s = "ddivu"; | |
8466 | s2 = "mflo"; | |
8467 | goto do_divu3; | |
8468 | case M_DREMU_3: | |
8469 | s = "ddivu"; | |
8470 | s2 = "mfhi"; | |
8471 | do_divu3: | |
7d10b47d | 8472 | start_noreorder (); |
67c0d1eb | 8473 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8474 | expr1.X_add_number = 2; |
67c0d1eb RS |
8475 | macro_build (&expr1, "bnez", "x,p", yreg); |
8476 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8477 | end_noreorder (); |
67c0d1eb | 8478 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8479 | break; |
8480 | ||
8481 | case M_DMUL: | |
8482 | dbl = 1; | |
8483 | case M_MUL: | |
67c0d1eb RS |
8484 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8485 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8486 | break; |
252b5132 RH |
8487 | |
8488 | case M_DSUBU_I: | |
8489 | dbl = 1; | |
8490 | goto do_subu; | |
8491 | case M_SUBU_I: | |
8492 | do_subu: | |
8493 | if (imm_expr.X_op != O_constant) | |
8494 | as_bad (_("Unsupported large constant")); | |
8495 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8496 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8497 | break; |
8498 | ||
8499 | case M_SUBU_I_2: | |
8500 | if (imm_expr.X_op != O_constant) | |
8501 | as_bad (_("Unsupported large constant")); | |
8502 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8503 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8504 | break; |
8505 | ||
8506 | case M_DSUBU_I_2: | |
8507 | if (imm_expr.X_op != O_constant) | |
8508 | as_bad (_("Unsupported large constant")); | |
8509 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8510 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8511 | break; |
8512 | ||
8513 | case M_BEQ: | |
8514 | s = "cmp"; | |
8515 | s2 = "bteqz"; | |
8516 | goto do_branch; | |
8517 | case M_BNE: | |
8518 | s = "cmp"; | |
8519 | s2 = "btnez"; | |
8520 | goto do_branch; | |
8521 | case M_BLT: | |
8522 | s = "slt"; | |
8523 | s2 = "btnez"; | |
8524 | goto do_branch; | |
8525 | case M_BLTU: | |
8526 | s = "sltu"; | |
8527 | s2 = "btnez"; | |
8528 | goto do_branch; | |
8529 | case M_BLE: | |
8530 | s = "slt"; | |
8531 | s2 = "bteqz"; | |
8532 | goto do_reverse_branch; | |
8533 | case M_BLEU: | |
8534 | s = "sltu"; | |
8535 | s2 = "bteqz"; | |
8536 | goto do_reverse_branch; | |
8537 | case M_BGE: | |
8538 | s = "slt"; | |
8539 | s2 = "bteqz"; | |
8540 | goto do_branch; | |
8541 | case M_BGEU: | |
8542 | s = "sltu"; | |
8543 | s2 = "bteqz"; | |
8544 | goto do_branch; | |
8545 | case M_BGT: | |
8546 | s = "slt"; | |
8547 | s2 = "btnez"; | |
8548 | goto do_reverse_branch; | |
8549 | case M_BGTU: | |
8550 | s = "sltu"; | |
8551 | s2 = "btnez"; | |
8552 | ||
8553 | do_reverse_branch: | |
8554 | tmp = xreg; | |
8555 | xreg = yreg; | |
8556 | yreg = tmp; | |
8557 | ||
8558 | do_branch: | |
67c0d1eb RS |
8559 | macro_build (NULL, s, "x,y", xreg, yreg); |
8560 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8561 | break; |
8562 | ||
8563 | case M_BEQ_I: | |
8564 | s = "cmpi"; | |
8565 | s2 = "bteqz"; | |
8566 | s3 = "x,U"; | |
8567 | goto do_branch_i; | |
8568 | case M_BNE_I: | |
8569 | s = "cmpi"; | |
8570 | s2 = "btnez"; | |
8571 | s3 = "x,U"; | |
8572 | goto do_branch_i; | |
8573 | case M_BLT_I: | |
8574 | s = "slti"; | |
8575 | s2 = "btnez"; | |
8576 | s3 = "x,8"; | |
8577 | goto do_branch_i; | |
8578 | case M_BLTU_I: | |
8579 | s = "sltiu"; | |
8580 | s2 = "btnez"; | |
8581 | s3 = "x,8"; | |
8582 | goto do_branch_i; | |
8583 | case M_BLE_I: | |
8584 | s = "slti"; | |
8585 | s2 = "btnez"; | |
8586 | s3 = "x,8"; | |
8587 | goto do_addone_branch_i; | |
8588 | case M_BLEU_I: | |
8589 | s = "sltiu"; | |
8590 | s2 = "btnez"; | |
8591 | s3 = "x,8"; | |
8592 | goto do_addone_branch_i; | |
8593 | case M_BGE_I: | |
8594 | s = "slti"; | |
8595 | s2 = "bteqz"; | |
8596 | s3 = "x,8"; | |
8597 | goto do_branch_i; | |
8598 | case M_BGEU_I: | |
8599 | s = "sltiu"; | |
8600 | s2 = "bteqz"; | |
8601 | s3 = "x,8"; | |
8602 | goto do_branch_i; | |
8603 | case M_BGT_I: | |
8604 | s = "slti"; | |
8605 | s2 = "bteqz"; | |
8606 | s3 = "x,8"; | |
8607 | goto do_addone_branch_i; | |
8608 | case M_BGTU_I: | |
8609 | s = "sltiu"; | |
8610 | s2 = "bteqz"; | |
8611 | s3 = "x,8"; | |
8612 | ||
8613 | do_addone_branch_i: | |
8614 | if (imm_expr.X_op != O_constant) | |
8615 | as_bad (_("Unsupported large constant")); | |
8616 | ++imm_expr.X_add_number; | |
8617 | ||
8618 | do_branch_i: | |
67c0d1eb RS |
8619 | macro_build (&imm_expr, s, s3, xreg); |
8620 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8621 | break; |
8622 | ||
8623 | case M_ABS: | |
8624 | expr1.X_add_number = 0; | |
67c0d1eb | 8625 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8626 | if (xreg != yreg) |
67c0d1eb | 8627 | move_register (xreg, yreg); |
252b5132 | 8628 | expr1.X_add_number = 2; |
67c0d1eb RS |
8629 | macro_build (&expr1, "bteqz", "p"); |
8630 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8631 | } |
8632 | } | |
8633 | ||
8634 | /* For consistency checking, verify that all bits are specified either | |
8635 | by the match/mask part of the instruction definition, or by the | |
8636 | operand list. */ | |
8637 | static int | |
17a2f251 | 8638 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8639 | { |
8640 | const char *p = opc->args; | |
8641 | char c; | |
8642 | unsigned long used_bits = opc->mask; | |
8643 | ||
8644 | if ((used_bits & opc->match) != opc->match) | |
8645 | { | |
8646 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8647 | opc->name, opc->args); | |
8648 | return 0; | |
8649 | } | |
8650 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8651 | while (*p) | |
8652 | switch (c = *p++) | |
8653 | { | |
8654 | case ',': break; | |
8655 | case '(': break; | |
8656 | case ')': break; | |
af7ee8bf CD |
8657 | case '+': |
8658 | switch (c = *p++) | |
8659 | { | |
9bcd4f99 TS |
8660 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8661 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8662 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8663 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8664 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8665 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8666 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8667 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8668 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8669 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8670 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8671 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8672 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8673 | case 'I': break; | |
ef2e4d86 CF |
8674 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8675 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8676 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8677 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8678 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8679 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8680 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8681 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8682 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8683 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
8684 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
8685 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
8686 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
8687 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
8688 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 8689 | |
af7ee8bf CD |
8690 | default: |
8691 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8692 | c, opc->name, opc->args); | |
8693 | return 0; | |
8694 | } | |
8695 | break; | |
252b5132 RH |
8696 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8697 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8698 | case 'A': break; | |
4372b673 | 8699 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8700 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8701 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8702 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8703 | case 'F': break; | |
8704 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8705 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8706 | case 'I': break; |
e972090a | 8707 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8708 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8709 | case 'L': break; |
8710 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8711 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8712 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8713 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8714 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8715 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8716 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8717 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8718 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8719 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8720 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8721 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8722 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8723 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8724 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8725 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8726 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8727 | case 'f': break; | |
8728 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8729 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8730 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8731 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8732 | case 'l': break; | |
8733 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8734 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8735 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8736 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8737 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8738 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8739 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8740 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8741 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8742 | case 'x': break; | |
8743 | case 'z': break; | |
8744 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8745 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8746 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8747 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8748 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8749 | case '[': break; | |
8750 | case ']': break; | |
620edafd | 8751 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8752 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8753 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8754 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8755 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8756 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8757 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8758 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8759 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8760 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8761 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8762 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8763 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8764 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8765 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8766 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8767 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8768 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8769 | default: |
8770 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8771 | c, opc->name, opc->args); | |
8772 | return 0; | |
8773 | } | |
8774 | #undef USE_BITS | |
8775 | if (used_bits != 0xffffffff) | |
8776 | { | |
8777 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8778 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8779 | return 0; | |
8780 | } | |
8781 | return 1; | |
8782 | } | |
8783 | ||
9bcd4f99 TS |
8784 | /* UDI immediates. */ |
8785 | struct mips_immed { | |
8786 | char type; | |
8787 | unsigned int shift; | |
8788 | unsigned long mask; | |
8789 | const char * desc; | |
8790 | }; | |
8791 | ||
8792 | static const struct mips_immed mips_immed[] = { | |
8793 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8794 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8795 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8796 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8797 | { 0,0,0,0 } | |
8798 | }; | |
8799 | ||
7455baf8 TS |
8800 | /* Check whether an odd floating-point register is allowed. */ |
8801 | static int | |
8802 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8803 | { | |
8804 | const char *s = insn->name; | |
8805 | ||
8806 | if (insn->pinfo == INSN_MACRO) | |
8807 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8808 | return 1; | |
8809 | ||
8810 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8811 | { | |
8812 | /* Allow odd registers for single-precision ops. */ | |
8813 | switch (insn->pinfo & (FP_S | FP_D)) | |
8814 | { | |
8815 | case FP_S: | |
8816 | case 0: | |
8817 | return 1; /* both single precision - ok */ | |
8818 | case FP_D: | |
8819 | return 0; /* both double precision - fail */ | |
8820 | default: | |
8821 | break; | |
8822 | } | |
8823 | ||
8824 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8825 | s = strchr (insn->name, '.'); | |
8826 | if (argnum == 2) | |
8827 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8828 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8829 | } | |
8830 | ||
8831 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8832 | if ((insn->pinfo & FP_S) | |
8833 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8834 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8835 | return 1; | |
8836 | ||
8837 | return 0; | |
8838 | } | |
8839 | ||
252b5132 RH |
8840 | /* This routine assembles an instruction into its binary format. As a |
8841 | side effect, it sets one of the global variables imm_reloc or | |
8842 | offset_reloc to the type of relocation to do if one of the operands | |
8843 | is an address expression. */ | |
8844 | ||
8845 | static void | |
17a2f251 | 8846 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8847 | { |
8848 | char *s; | |
8849 | const char *args; | |
43841e91 | 8850 | char c = 0; |
252b5132 RH |
8851 | struct mips_opcode *insn; |
8852 | char *argsStart; | |
8853 | unsigned int regno; | |
34224acf | 8854 | unsigned int lastregno; |
af7ee8bf | 8855 | unsigned int lastpos = 0; |
071742cf | 8856 | unsigned int limlo, limhi; |
252b5132 RH |
8857 | char *s_reset; |
8858 | char save_c = 0; | |
74cd071d | 8859 | offsetT min_range, max_range; |
707bfff6 TS |
8860 | int argnum; |
8861 | unsigned int rtype; | |
252b5132 RH |
8862 | |
8863 | insn_error = NULL; | |
8864 | ||
8865 | /* If the instruction contains a '.', we first try to match an instruction | |
8866 | including the '.'. Then we try again without the '.'. */ | |
8867 | insn = NULL; | |
3882b010 | 8868 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8869 | continue; |
8870 | ||
8871 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8872 | the call to hash_find. Save the character we replaced just in case we | |
8873 | have to re-parse the instruction. */ | |
3882b010 | 8874 | if (ISSPACE (*s)) |
252b5132 RH |
8875 | { |
8876 | save_c = *s; | |
8877 | *s++ = '\0'; | |
8878 | } | |
bdaaa2e1 | 8879 | |
252b5132 RH |
8880 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8881 | ||
8882 | /* If we didn't find the instruction in the opcode table, try again, but | |
8883 | this time with just the instruction up to, but not including the | |
8884 | first '.'. */ | |
8885 | if (insn == NULL) | |
8886 | { | |
bdaaa2e1 | 8887 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8888 | if (save_c) |
8889 | *(--s) = save_c; | |
8890 | ||
8891 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8892 | for (s = str; |
8893 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8894 | ++s) | |
252b5132 RH |
8895 | continue; |
8896 | ||
8897 | /* If we did not find a '.', then we can quit now. */ | |
8898 | if (*s != '.') | |
8899 | { | |
f71d0d44 | 8900 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8901 | return; |
8902 | } | |
8903 | ||
8904 | /* Lookup the instruction in the hash table. */ | |
8905 | *s++ = '\0'; | |
8906 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8907 | { | |
f71d0d44 | 8908 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8909 | return; |
8910 | } | |
252b5132 RH |
8911 | } |
8912 | ||
8913 | argsStart = s; | |
8914 | for (;;) | |
8915 | { | |
b34976b6 | 8916 | bfd_boolean ok; |
252b5132 | 8917 | |
9c2799c2 | 8918 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8919 | |
f79e2745 | 8920 | ok = is_opcode_valid (insn); |
252b5132 RH |
8921 | if (! ok) |
8922 | { | |
8923 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8924 | && strcmp (insn->name, insn[1].name) == 0) | |
8925 | { | |
8926 | ++insn; | |
8927 | continue; | |
8928 | } | |
252b5132 | 8929 | else |
beae10d5 | 8930 | { |
268f6bed L |
8931 | if (!insn_error) |
8932 | { | |
8933 | static char buf[100]; | |
fef14a42 TS |
8934 | sprintf (buf, |
8935 | _("opcode not supported on this processor: %s (%s)"), | |
8936 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8937 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8938 | insn_error = buf; |
8939 | } | |
8940 | if (save_c) | |
8941 | *(--s) = save_c; | |
2bd7f1f3 | 8942 | return; |
252b5132 | 8943 | } |
252b5132 RH |
8944 | } |
8945 | ||
1e915849 | 8946 | create_insn (ip, insn); |
268f6bed | 8947 | insn_error = NULL; |
707bfff6 | 8948 | argnum = 1; |
24864476 | 8949 | lastregno = 0xffffffff; |
252b5132 RH |
8950 | for (args = insn->args;; ++args) |
8951 | { | |
deec1734 CD |
8952 | int is_mdmx; |
8953 | ||
ad8d3bb3 | 8954 | s += strspn (s, " \t"); |
deec1734 | 8955 | is_mdmx = 0; |
252b5132 RH |
8956 | switch (*args) |
8957 | { | |
8958 | case '\0': /* end of args */ | |
8959 | if (*s == '\0') | |
8960 | return; | |
8961 | break; | |
8962 | ||
90ecf173 | 8963 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
8964 | my_getExpression (&imm_expr, s); |
8965 | check_absolute_expr (ip, &imm_expr); | |
8966 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8967 | && (unsigned long) imm_expr.X_add_number != 3) | |
8968 | { | |
8969 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8970 | (unsigned long) imm_expr.X_add_number); | |
8971 | } | |
8972 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8973 | imm_expr.X_op = O_absent; | |
8974 | s = expr_end; | |
8975 | continue; | |
8976 | ||
90ecf173 | 8977 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8978 | my_getExpression (&imm_expr, s); |
8979 | check_absolute_expr (ip, &imm_expr); | |
8980 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8981 | { | |
a9e24354 TS |
8982 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8983 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8984 | } |
a9e24354 | 8985 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8986 | imm_expr.X_op = O_absent; |
8987 | s = expr_end; | |
8988 | continue; | |
8989 | ||
90ecf173 | 8990 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8991 | my_getExpression (&imm_expr, s); |
8992 | check_absolute_expr (ip, &imm_expr); | |
8993 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8994 | { | |
a9e24354 TS |
8995 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8996 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8997 | } |
a9e24354 | 8998 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8999 | imm_expr.X_op = O_absent; |
9000 | s = expr_end; | |
9001 | continue; | |
9002 | ||
90ecf173 | 9003 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
9004 | my_getExpression (&imm_expr, s); |
9005 | check_absolute_expr (ip, &imm_expr); | |
9006 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
9007 | { | |
a9e24354 TS |
9008 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9009 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9010 | } |
a9e24354 | 9011 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
9012 | imm_expr.X_op = O_absent; |
9013 | s = expr_end; | |
9014 | continue; | |
9015 | ||
90ecf173 | 9016 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
9017 | my_getExpression (&imm_expr, s); |
9018 | check_absolute_expr (ip, &imm_expr); | |
9019 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
9020 | { | |
a9e24354 TS |
9021 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9022 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9023 | } |
a9e24354 | 9024 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
9025 | imm_expr.X_op = O_absent; |
9026 | s = expr_end; | |
9027 | continue; | |
9028 | ||
90ecf173 | 9029 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
9030 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9031 | s[3] >= '0' && s[3] <= '3') | |
9032 | { | |
9033 | regno = s[3] - '0'; | |
9034 | s += 4; | |
a9e24354 | 9035 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
9036 | continue; |
9037 | } | |
9038 | else | |
9039 | as_bad (_("Invalid dsp acc register")); | |
9040 | break; | |
9041 | ||
90ecf173 | 9042 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
9043 | my_getExpression (&imm_expr, s); |
9044 | check_absolute_expr (ip, &imm_expr); | |
9045 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
9046 | { | |
a9e24354 TS |
9047 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9048 | OP_MASK_WRDSP, | |
9049 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9050 | } |
a9e24354 | 9051 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9052 | imm_expr.X_op = O_absent; |
9053 | s = expr_end; | |
9054 | continue; | |
9055 | ||
90ecf173 | 9056 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
9057 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9058 | s[3] >= '0' && s[3] <= '3') | |
9059 | { | |
9060 | regno = s[3] - '0'; | |
9061 | s += 4; | |
a9e24354 | 9062 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
9063 | continue; |
9064 | } | |
9065 | else | |
9066 | as_bad (_("Invalid dsp acc register")); | |
9067 | break; | |
9068 | ||
90ecf173 | 9069 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
9070 | my_getExpression (&imm_expr, s); |
9071 | check_absolute_expr (ip, &imm_expr); | |
9072 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
9073 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
9074 | if (imm_expr.X_add_number < min_range || | |
9075 | imm_expr.X_add_number > max_range) | |
9076 | { | |
a9e24354 TS |
9077 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9078 | (long) min_range, (long) max_range, | |
9079 | (long) imm_expr.X_add_number); | |
74cd071d | 9080 | } |
a9e24354 | 9081 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
9082 | imm_expr.X_op = O_absent; |
9083 | s = expr_end; | |
9084 | continue; | |
9085 | ||
90ecf173 | 9086 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
9087 | my_getExpression (&imm_expr, s); |
9088 | check_absolute_expr (ip, &imm_expr); | |
9089 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
9090 | { | |
a9e24354 TS |
9091 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9092 | OP_MASK_RDDSP, | |
9093 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9094 | } |
a9e24354 | 9095 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9096 | imm_expr.X_op = O_absent; |
9097 | s = expr_end; | |
9098 | continue; | |
9099 | ||
90ecf173 | 9100 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
9101 | my_getExpression (&imm_expr, s); |
9102 | check_absolute_expr (ip, &imm_expr); | |
9103 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
9104 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
9105 | if (imm_expr.X_add_number < min_range || | |
9106 | imm_expr.X_add_number > max_range) | |
9107 | { | |
a9e24354 TS |
9108 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9109 | (long) min_range, (long) max_range, | |
9110 | (long) imm_expr.X_add_number); | |
74cd071d | 9111 | } |
a9e24354 | 9112 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
9113 | imm_expr.X_op = O_absent; |
9114 | s = expr_end; | |
9115 | continue; | |
9116 | ||
90ecf173 | 9117 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
9118 | my_getExpression (&imm_expr, s); |
9119 | check_absolute_expr (ip, &imm_expr); | |
9120 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
9121 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
9122 | if (imm_expr.X_add_number < min_range || | |
9123 | imm_expr.X_add_number > max_range) | |
9124 | { | |
a9e24354 TS |
9125 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9126 | (long) min_range, (long) max_range, | |
9127 | (long) imm_expr.X_add_number); | |
74cd071d | 9128 | } |
a9e24354 | 9129 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
9130 | imm_expr.X_op = O_absent; |
9131 | s = expr_end; | |
9132 | continue; | |
9133 | ||
a9e24354 | 9134 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
9135 | my_getExpression (&imm_expr, s); |
9136 | check_absolute_expr (ip, &imm_expr); | |
9137 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
9138 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
9139 | (unsigned long) imm_expr.X_add_number); | |
9140 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9141 | imm_expr.X_op = O_absent; |
9142 | s = expr_end; | |
9143 | continue; | |
9144 | ||
a9e24354 | 9145 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
9146 | my_getExpression (&imm_expr, s); |
9147 | check_absolute_expr (ip, &imm_expr); | |
9148 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
9149 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
9150 | (unsigned long) imm_expr.X_add_number); | |
9151 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9152 | imm_expr.X_op = O_absent; |
9153 | s = expr_end; | |
9154 | continue; | |
9155 | ||
90ecf173 | 9156 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
9157 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9158 | s[3] >= '0' && s[3] <= '3') | |
9159 | { | |
9160 | regno = s[3] - '0'; | |
9161 | s += 4; | |
a9e24354 | 9162 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
9163 | continue; |
9164 | } | |
9165 | else | |
9166 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9167 | break; | |
9168 | ||
90ecf173 | 9169 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
9170 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9171 | s[3] >= '0' && s[3] <= '3') | |
9172 | { | |
9173 | regno = s[3] - '0'; | |
9174 | s += 4; | |
a9e24354 | 9175 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9176 | continue; |
9177 | } | |
9178 | else | |
9179 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9180 | break; | |
9181 | ||
252b5132 | 9182 | case ',': |
a339155f | 9183 | ++argnum; |
252b5132 RH |
9184 | if (*s++ == *args) |
9185 | continue; | |
9186 | s--; | |
9187 | switch (*++args) | |
9188 | { | |
9189 | case 'r': | |
9190 | case 'v': | |
bf12938e | 9191 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9192 | continue; |
9193 | ||
9194 | case 'w': | |
bf12938e | 9195 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9196 | continue; |
9197 | ||
252b5132 | 9198 | case 'W': |
bf12938e | 9199 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9200 | continue; |
9201 | ||
9202 | case 'V': | |
bf12938e | 9203 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9204 | continue; |
9205 | } | |
9206 | break; | |
9207 | ||
9208 | case '(': | |
9209 | /* Handle optional base register. | |
9210 | Either the base register is omitted or | |
bdaaa2e1 | 9211 | we must have a left paren. */ |
252b5132 RH |
9212 | /* This is dependent on the next operand specifier |
9213 | is a base register specification. */ | |
f9bbfb18 | 9214 | gas_assert (args[1] == 'b'); |
252b5132 RH |
9215 | if (*s == '\0') |
9216 | return; | |
9217 | ||
90ecf173 | 9218 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9219 | case '[': |
9220 | case ']': | |
252b5132 RH |
9221 | if (*s++ == *args) |
9222 | continue; | |
9223 | break; | |
9224 | ||
af7ee8bf CD |
9225 | case '+': /* Opcode extension character. */ |
9226 | switch (*++args) | |
9227 | { | |
9bcd4f99 TS |
9228 | case '1': /* UDI immediates. */ |
9229 | case '2': | |
9230 | case '3': | |
9231 | case '4': | |
9232 | { | |
9233 | const struct mips_immed *imm = mips_immed; | |
9234 | ||
9235 | while (imm->type && imm->type != *args) | |
9236 | ++imm; | |
9237 | if (! imm->type) | |
9238 | internalError (); | |
9239 | my_getExpression (&imm_expr, s); | |
9240 | check_absolute_expr (ip, &imm_expr); | |
9241 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9242 | { | |
9243 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9244 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9245 | (unsigned long) imm_expr.X_add_number, | |
9246 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9247 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9248 | } |
9249 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9250 | << imm->shift); | |
9251 | imm_expr.X_op = O_absent; | |
9252 | s = expr_end; | |
9253 | } | |
9254 | continue; | |
90ecf173 | 9255 | |
071742cf CD |
9256 | case 'A': /* ins/ext position, becomes LSB. */ |
9257 | limlo = 0; | |
9258 | limhi = 31; | |
5f74bc13 CD |
9259 | goto do_lsb; |
9260 | case 'E': | |
9261 | limlo = 32; | |
9262 | limhi = 63; | |
9263 | goto do_lsb; | |
90ecf173 | 9264 | do_lsb: |
071742cf CD |
9265 | my_getExpression (&imm_expr, s); |
9266 | check_absolute_expr (ip, &imm_expr); | |
9267 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9268 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9269 | { | |
9270 | as_bad (_("Improper position (%lu)"), | |
9271 | (unsigned long) imm_expr.X_add_number); | |
9272 | imm_expr.X_add_number = limlo; | |
9273 | } | |
9274 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9275 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9276 | imm_expr.X_op = O_absent; |
9277 | s = expr_end; | |
9278 | continue; | |
9279 | ||
9280 | case 'B': /* ins size, becomes MSB. */ | |
9281 | limlo = 1; | |
9282 | limhi = 32; | |
5f74bc13 CD |
9283 | goto do_msb; |
9284 | case 'F': | |
9285 | limlo = 33; | |
9286 | limhi = 64; | |
9287 | goto do_msb; | |
90ecf173 | 9288 | do_msb: |
071742cf CD |
9289 | my_getExpression (&imm_expr, s); |
9290 | check_absolute_expr (ip, &imm_expr); | |
9291 | /* Check for negative input so that small negative numbers | |
9292 | will not succeed incorrectly. The checks against | |
9293 | (pos+size) transitively check "size" itself, | |
9294 | assuming that "pos" is reasonable. */ | |
9295 | if ((long) imm_expr.X_add_number < 0 | |
9296 | || ((unsigned long) imm_expr.X_add_number | |
9297 | + lastpos) < limlo | |
9298 | || ((unsigned long) imm_expr.X_add_number | |
9299 | + lastpos) > limhi) | |
9300 | { | |
9301 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9302 | (unsigned long) imm_expr.X_add_number, | |
9303 | (unsigned long) lastpos); | |
9304 | imm_expr.X_add_number = limlo - lastpos; | |
9305 | } | |
bf12938e RS |
9306 | INSERT_OPERAND (INSMSB, *ip, |
9307 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9308 | imm_expr.X_op = O_absent; |
9309 | s = expr_end; | |
9310 | continue; | |
9311 | ||
9312 | case 'C': /* ext size, becomes MSBD. */ | |
9313 | limlo = 1; | |
9314 | limhi = 32; | |
5f74bc13 CD |
9315 | goto do_msbd; |
9316 | case 'G': | |
9317 | limlo = 33; | |
9318 | limhi = 64; | |
9319 | goto do_msbd; | |
9320 | case 'H': | |
9321 | limlo = 33; | |
9322 | limhi = 64; | |
9323 | goto do_msbd; | |
90ecf173 | 9324 | do_msbd: |
071742cf CD |
9325 | my_getExpression (&imm_expr, s); |
9326 | check_absolute_expr (ip, &imm_expr); | |
9327 | /* Check for negative input so that small negative numbers | |
9328 | will not succeed incorrectly. The checks against | |
9329 | (pos+size) transitively check "size" itself, | |
9330 | assuming that "pos" is reasonable. */ | |
9331 | if ((long) imm_expr.X_add_number < 0 | |
9332 | || ((unsigned long) imm_expr.X_add_number | |
9333 | + lastpos) < limlo | |
9334 | || ((unsigned long) imm_expr.X_add_number | |
9335 | + lastpos) > limhi) | |
9336 | { | |
9337 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9338 | (unsigned long) imm_expr.X_add_number, | |
9339 | (unsigned long) lastpos); | |
9340 | imm_expr.X_add_number = limlo - lastpos; | |
9341 | } | |
bf12938e | 9342 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9343 | imm_expr.X_op = O_absent; |
9344 | s = expr_end; | |
9345 | continue; | |
af7ee8bf | 9346 | |
bbcc0807 CD |
9347 | case 'D': |
9348 | /* +D is for disassembly only; never match. */ | |
9349 | break; | |
9350 | ||
5f74bc13 CD |
9351 | case 'I': |
9352 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9353 | my_getExpression (&imm2_expr, s); | |
9354 | if (imm2_expr.X_op != O_big | |
9355 | && imm2_expr.X_op != O_constant) | |
9356 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9357 | if (HAVE_32BIT_GPRS) |
9358 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9359 | s = expr_end; |
9360 | continue; | |
9361 | ||
707bfff6 | 9362 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9363 | /* +T is for disassembly only; never match. */ |
9364 | break; | |
9365 | ||
707bfff6 | 9366 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9367 | if (s[0] == '$' && ISDIGIT (s[1])) |
9368 | { | |
9369 | ++s; | |
9370 | regno = 0; | |
9371 | do | |
9372 | { | |
9373 | regno *= 10; | |
9374 | regno += *s - '0'; | |
9375 | ++s; | |
9376 | } | |
9377 | while (ISDIGIT (*s)); | |
9378 | if (regno > 31) | |
9379 | as_bad (_("Invalid register number (%d)"), regno); | |
9380 | else | |
9381 | { | |
a9e24354 | 9382 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9383 | continue; |
9384 | } | |
9385 | } | |
9386 | else | |
9387 | as_bad (_("Invalid coprocessor 0 register number")); | |
9388 | break; | |
9389 | ||
bb35fb24 NC |
9390 | case 'x': |
9391 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9392 | is not in the valid range. */ | |
9393 | my_getExpression (&imm_expr, s); | |
9394 | check_absolute_expr (ip, &imm_expr); | |
9395 | if ((unsigned) imm_expr.X_add_number > 31) | |
9396 | { | |
9397 | as_bad (_("Improper bit index (%lu)"), | |
9398 | (unsigned long) imm_expr.X_add_number); | |
9399 | imm_expr.X_add_number = 0; | |
9400 | } | |
9401 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9402 | imm_expr.X_op = O_absent; | |
9403 | s = expr_end; | |
9404 | continue; | |
9405 | ||
9406 | case 'X': | |
9407 | /* bbit[01] bit index when bbit is used but we generate | |
9408 | bbit[01]32 because the index is over 32. Move to the | |
9409 | next candidate if index is not in the valid range. */ | |
9410 | my_getExpression (&imm_expr, s); | |
9411 | check_absolute_expr (ip, &imm_expr); | |
9412 | if ((unsigned) imm_expr.X_add_number < 32 | |
9413 | || (unsigned) imm_expr.X_add_number > 63) | |
9414 | break; | |
9415 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9416 | imm_expr.X_op = O_absent; | |
9417 | s = expr_end; | |
9418 | continue; | |
9419 | ||
9420 | case 'p': | |
9421 | /* cins, cins32, exts and exts32 position field. Give error | |
9422 | if it's not in the valid range. */ | |
9423 | my_getExpression (&imm_expr, s); | |
9424 | check_absolute_expr (ip, &imm_expr); | |
9425 | if ((unsigned) imm_expr.X_add_number > 31) | |
9426 | { | |
9427 | as_bad (_("Improper position (%lu)"), | |
9428 | (unsigned long) imm_expr.X_add_number); | |
9429 | imm_expr.X_add_number = 0; | |
9430 | } | |
9431 | /* Make the pos explicit to simplify +S. */ | |
9432 | lastpos = imm_expr.X_add_number + 32; | |
9433 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9434 | imm_expr.X_op = O_absent; | |
9435 | s = expr_end; | |
9436 | continue; | |
9437 | ||
9438 | case 'P': | |
9439 | /* cins, cins32, exts and exts32 position field. Move to | |
9440 | the next candidate if it's not in the valid range. */ | |
9441 | my_getExpression (&imm_expr, s); | |
9442 | check_absolute_expr (ip, &imm_expr); | |
9443 | if ((unsigned) imm_expr.X_add_number < 32 | |
9444 | || (unsigned) imm_expr.X_add_number > 63) | |
9445 | break; | |
9446 | lastpos = imm_expr.X_add_number; | |
9447 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9448 | imm_expr.X_op = O_absent; | |
9449 | s = expr_end; | |
9450 | continue; | |
9451 | ||
9452 | case 's': | |
9453 | /* cins and exts length-minus-one field. */ | |
9454 | my_getExpression (&imm_expr, s); | |
9455 | check_absolute_expr (ip, &imm_expr); | |
9456 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9457 | { | |
9458 | as_bad (_("Improper size (%lu)"), | |
9459 | (unsigned long) imm_expr.X_add_number); | |
9460 | imm_expr.X_add_number = 0; | |
9461 | } | |
9462 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9463 | imm_expr.X_op = O_absent; | |
9464 | s = expr_end; | |
9465 | continue; | |
9466 | ||
9467 | case 'S': | |
9468 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9469 | length-minus-one field. */ | |
9470 | my_getExpression (&imm_expr, s); | |
9471 | check_absolute_expr (ip, &imm_expr); | |
9472 | if ((long) imm_expr.X_add_number < 0 | |
9473 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9474 | { | |
9475 | as_bad (_("Improper size (%lu)"), | |
9476 | (unsigned long) imm_expr.X_add_number); | |
9477 | imm_expr.X_add_number = 0; | |
9478 | } | |
9479 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9480 | imm_expr.X_op = O_absent; | |
9481 | s = expr_end; | |
9482 | continue; | |
9483 | ||
dd3cbb7e NC |
9484 | case 'Q': |
9485 | /* seqi/snei immediate field. */ | |
9486 | my_getExpression (&imm_expr, s); | |
9487 | check_absolute_expr (ip, &imm_expr); | |
9488 | if ((long) imm_expr.X_add_number < -512 | |
9489 | || (long) imm_expr.X_add_number >= 512) | |
9490 | { | |
9491 | as_bad (_("Improper immediate (%ld)"), | |
9492 | (long) imm_expr.X_add_number); | |
9493 | imm_expr.X_add_number = 0; | |
9494 | } | |
9495 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9496 | imm_expr.X_op = O_absent; | |
9497 | s = expr_end; | |
9498 | continue; | |
9499 | ||
98675402 RS |
9500 | case 'a': /* 8-bit signed offset in bit 6 */ |
9501 | my_getExpression (&imm_expr, s); | |
9502 | check_absolute_expr (ip, &imm_expr); | |
9503 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
9504 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
9505 | if (imm_expr.X_add_number < min_range | |
9506 | || imm_expr.X_add_number > max_range) | |
9507 | { | |
c95354ed | 9508 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9509 | (long) min_range, (long) max_range, |
9510 | (long) imm_expr.X_add_number); | |
9511 | } | |
9512 | INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number); | |
9513 | imm_expr.X_op = O_absent; | |
9514 | s = expr_end; | |
9515 | continue; | |
9516 | ||
9517 | case 'b': /* 8-bit signed offset in bit 3 */ | |
9518 | my_getExpression (&imm_expr, s); | |
9519 | check_absolute_expr (ip, &imm_expr); | |
9520 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
9521 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
9522 | if (imm_expr.X_add_number < min_range | |
9523 | || imm_expr.X_add_number > max_range) | |
9524 | { | |
c95354ed | 9525 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9526 | (long) min_range, (long) max_range, |
9527 | (long) imm_expr.X_add_number); | |
9528 | } | |
9529 | INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number); | |
9530 | imm_expr.X_op = O_absent; | |
9531 | s = expr_end; | |
9532 | continue; | |
9533 | ||
9534 | case 'c': /* 9-bit signed offset in bit 6 */ | |
9535 | my_getExpression (&imm_expr, s); | |
9536 | check_absolute_expr (ip, &imm_expr); | |
9537 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
9538 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
9539 | /* We check the offset range before adjusted. */ |
9540 | min_range <<= 4; | |
9541 | max_range <<= 4; | |
98675402 RS |
9542 | if (imm_expr.X_add_number < min_range |
9543 | || imm_expr.X_add_number > max_range) | |
9544 | { | |
c95354ed | 9545 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9546 | (long) min_range, (long) max_range, |
9547 | (long) imm_expr.X_add_number); | |
9548 | } | |
c95354ed MX |
9549 | if (imm_expr.X_add_number & 0xf) |
9550 | { | |
9551 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
9552 | (long) imm_expr.X_add_number); | |
9553 | } | |
9554 | /* Right shift 4 bits to adjust the offset operand. */ | |
9555 | INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4); | |
98675402 RS |
9556 | imm_expr.X_op = O_absent; |
9557 | s = expr_end; | |
9558 | continue; | |
9559 | ||
9560 | case 'z': | |
9561 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
9562 | break; | |
9563 | if (regno == AT && mips_opts.at) | |
9564 | { | |
9565 | if (mips_opts.at == ATREG) | |
9566 | as_warn (_("used $at without \".set noat\"")); | |
9567 | else | |
9568 | as_warn (_("used $%u with \".set at=$%u\""), | |
9569 | regno, mips_opts.at); | |
9570 | } | |
9571 | INSERT_OPERAND (RZ, *ip, regno); | |
9572 | continue; | |
9573 | ||
9574 | case 'Z': | |
9575 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) | |
9576 | break; | |
9577 | INSERT_OPERAND (FZ, *ip, regno); | |
9578 | continue; | |
9579 | ||
af7ee8bf | 9580 | default: |
f71d0d44 | 9581 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9582 | "(unknown extension operand type `+%c'): %s %s"), |
9583 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9584 | /* Further processing is fruitless. */ |
9585 | return; | |
9586 | } | |
9587 | break; | |
9588 | ||
252b5132 RH |
9589 | case '<': /* must be at least one digit */ |
9590 | /* | |
9591 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9592 | * than 31 or less than 0, then the shift amount should be |
9593 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9594 | * We issue a warning and mask out all but the low 5 bits. |
9595 | */ | |
9596 | my_getExpression (&imm_expr, s); | |
9597 | check_absolute_expr (ip, &imm_expr); | |
9598 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9599 | as_warn (_("Improper shift amount (%lu)"), |
9600 | (unsigned long) imm_expr.X_add_number); | |
9601 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9602 | imm_expr.X_op = O_absent; |
9603 | s = expr_end; | |
9604 | continue; | |
9605 | ||
9606 | case '>': /* shift amount minus 32 */ | |
9607 | my_getExpression (&imm_expr, s); | |
9608 | check_absolute_expr (ip, &imm_expr); | |
9609 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9610 | || (unsigned long) imm_expr.X_add_number > 63) | |
9611 | break; | |
bf12938e | 9612 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9613 | imm_expr.X_op = O_absent; |
9614 | s = expr_end; | |
9615 | continue; | |
9616 | ||
90ecf173 MR |
9617 | case 'k': /* CACHE code. */ |
9618 | case 'h': /* PREFX code. */ | |
9619 | case '1': /* SYNC type. */ | |
252b5132 RH |
9620 | my_getExpression (&imm_expr, s); |
9621 | check_absolute_expr (ip, &imm_expr); | |
9622 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9623 | as_warn (_("Invalid value for `%s' (%lu)"), |
9624 | ip->insn_mo->name, | |
9625 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9626 | if (*args == 'k') |
d954098f DD |
9627 | { |
9628 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9629 | switch (imm_expr.X_add_number) | |
9630 | { | |
9631 | case 5: | |
9632 | case 25: | |
9633 | case 26: | |
9634 | case 27: | |
9635 | case 28: | |
9636 | case 29: | |
9637 | case 30: | |
9638 | case 31: /* These are ok. */ | |
9639 | break; | |
9640 | ||
9641 | default: /* The rest must be changed to 28. */ | |
9642 | imm_expr.X_add_number = 28; | |
9643 | break; | |
9644 | } | |
9645 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9646 | } | |
620edafd | 9647 | else if (*args == 'h') |
bf12938e | 9648 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9649 | else |
9650 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9651 | imm_expr.X_op = O_absent; |
9652 | s = expr_end; | |
9653 | continue; | |
9654 | ||
90ecf173 | 9655 | case 'c': /* BREAK code. */ |
252b5132 RH |
9656 | my_getExpression (&imm_expr, s); |
9657 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9658 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9659 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9660 | ip->insn_mo->name, | |
bf12938e RS |
9661 | (unsigned long) imm_expr.X_add_number); |
9662 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9663 | imm_expr.X_op = O_absent; |
9664 | s = expr_end; | |
9665 | continue; | |
9666 | ||
90ecf173 | 9667 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9668 | my_getExpression (&imm_expr, s); |
9669 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9670 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9671 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9672 | ip->insn_mo->name, | |
bf12938e RS |
9673 | (unsigned long) imm_expr.X_add_number); |
9674 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9675 | imm_expr.X_op = O_absent; |
9676 | s = expr_end; | |
9677 | continue; | |
9678 | ||
90ecf173 | 9679 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9680 | my_getExpression (&imm_expr, s); |
156c2f8b | 9681 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9682 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9683 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9684 | ip->insn_mo->name, | |
793b27f4 | 9685 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9686 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9687 | imm_expr.X_op = O_absent; |
9688 | s = expr_end; | |
9689 | continue; | |
9690 | ||
90ecf173 | 9691 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9692 | my_getExpression (&imm_expr, s); |
252b5132 | 9693 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9694 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9695 | { |
793b27f4 TS |
9696 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9697 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9698 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9699 | } |
a9e24354 | 9700 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9701 | imm_expr.X_op = O_absent; |
9702 | s = expr_end; | |
9703 | continue; | |
252b5132 | 9704 | |
90ecf173 | 9705 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9706 | my_getExpression (&imm_expr, s); |
9707 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9708 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9709 | { |
9710 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9711 | (unsigned long) imm_expr.X_add_number); | |
9712 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9713 | } | |
bf12938e | 9714 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9715 | imm_expr.X_op = O_absent; |
9716 | s = expr_end; | |
9717 | continue; | |
9718 | ||
707bfff6 | 9719 | case 'P': /* Performance register. */ |
beae10d5 | 9720 | my_getExpression (&imm_expr, s); |
252b5132 | 9721 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9722 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9723 | as_warn (_("Invalid performance register (%lu)"), |
9724 | (unsigned long) imm_expr.X_add_number); | |
9725 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9726 | imm_expr.X_op = O_absent; |
9727 | s = expr_end; | |
9728 | continue; | |
252b5132 | 9729 | |
707bfff6 TS |
9730 | case 'G': /* Coprocessor destination register. */ |
9731 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9732 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9733 | else | |
9734 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9735 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9736 | if (ok) |
9737 | { | |
9738 | lastregno = regno; | |
9739 | continue; | |
9740 | } | |
9741 | else | |
9742 | break; | |
9743 | ||
90ecf173 MR |
9744 | case 'b': /* Base register. */ |
9745 | case 'd': /* Destination register. */ | |
9746 | case 's': /* Source register. */ | |
9747 | case 't': /* Target register. */ | |
9748 | case 'r': /* Both target and source. */ | |
9749 | case 'v': /* Both dest and source. */ | |
9750 | case 'w': /* Both dest and target. */ | |
9751 | case 'E': /* Coprocessor target register. */ | |
9752 | case 'K': /* RDHWR destination register. */ | |
9753 | case 'x': /* Ignore register name. */ | |
9754 | case 'z': /* Must be zero register. */ | |
9755 | case 'U': /* Destination register (CLO/CLZ). */ | |
9756 | case 'g': /* Coprocessor destination register. */ | |
9757 | s_reset = s; | |
707bfff6 TS |
9758 | if (*args == 'E' || *args == 'K') |
9759 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9760 | else | |
9761 | { | |
9762 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9763 | if (regno == AT && mips_opts.at) |
9764 | { | |
9765 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9766 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9767 | else |
f71d0d44 | 9768 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9769 | regno, mips_opts.at); |
9770 | } | |
707bfff6 TS |
9771 | } |
9772 | if (ok) | |
252b5132 | 9773 | { |
252b5132 RH |
9774 | c = *args; |
9775 | if (*s == ' ') | |
f9419b05 | 9776 | ++s; |
252b5132 RH |
9777 | if (args[1] != *s) |
9778 | { | |
9779 | if (c == 'r' || c == 'v' || c == 'w') | |
9780 | { | |
9781 | regno = lastregno; | |
9782 | s = s_reset; | |
f9419b05 | 9783 | ++args; |
252b5132 RH |
9784 | } |
9785 | } | |
9786 | /* 'z' only matches $0. */ | |
9787 | if (c == 'z' && regno != 0) | |
9788 | break; | |
9789 | ||
24864476 | 9790 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9791 | { |
9792 | if (regno == lastregno) | |
90ecf173 MR |
9793 | { |
9794 | insn_error | |
f71d0d44 | 9795 | = _("Source and destination must be different"); |
e7c604dd | 9796 | continue; |
90ecf173 | 9797 | } |
24864476 | 9798 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9799 | { |
9800 | insn_error | |
f71d0d44 | 9801 | = _("A destination register must be supplied"); |
e7c604dd | 9802 | continue; |
90ecf173 | 9803 | } |
e7c604dd | 9804 | } |
90ecf173 MR |
9805 | /* Now that we have assembled one operand, we use the args |
9806 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9807 | switch (c) |
9808 | { | |
9809 | case 'r': | |
9810 | case 's': | |
9811 | case 'v': | |
9812 | case 'b': | |
bf12938e | 9813 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9814 | break; |
9815 | case 'd': | |
af7ee8bf | 9816 | case 'K': |
ef2e4d86 | 9817 | case 'g': |
bf12938e | 9818 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9819 | break; |
4372b673 | 9820 | case 'U': |
bf12938e RS |
9821 | INSERT_OPERAND (RD, *ip, regno); |
9822 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9823 | break; |
252b5132 RH |
9824 | case 'w': |
9825 | case 't': | |
9826 | case 'E': | |
bf12938e | 9827 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9828 | break; |
9829 | case 'x': | |
9830 | /* This case exists because on the r3000 trunc | |
9831 | expands into a macro which requires a gp | |
9832 | register. On the r6000 or r4000 it is | |
9833 | assembled into a single instruction which | |
9834 | ignores the register. Thus the insn version | |
9835 | is MIPS_ISA2 and uses 'x', and the macro | |
9836 | version is MIPS_ISA1 and uses 't'. */ | |
9837 | break; | |
9838 | case 'z': | |
9839 | /* This case is for the div instruction, which | |
9840 | acts differently if the destination argument | |
9841 | is $0. This only matches $0, and is checked | |
9842 | outside the switch. */ | |
9843 | break; | |
252b5132 RH |
9844 | } |
9845 | lastregno = regno; | |
9846 | continue; | |
9847 | } | |
252b5132 RH |
9848 | switch (*args++) |
9849 | { | |
9850 | case 'r': | |
9851 | case 'v': | |
bf12938e | 9852 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9853 | continue; |
9854 | case 'w': | |
bf12938e | 9855 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9856 | continue; |
9857 | } | |
9858 | break; | |
9859 | ||
deec1734 CD |
9860 | case 'O': /* MDMX alignment immediate constant. */ |
9861 | my_getExpression (&imm_expr, s); | |
9862 | check_absolute_expr (ip, &imm_expr); | |
9863 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9864 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9865 | (long) imm_expr.X_add_number); |
9866 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9867 | imm_expr.X_op = O_absent; |
9868 | s = expr_end; | |
9869 | continue; | |
9870 | ||
9871 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9872 | if (s[0] != '$') | |
9873 | { | |
9874 | /* MDMX Immediate. */ | |
9875 | my_getExpression (&imm_expr, s); | |
9876 | check_absolute_expr (ip, &imm_expr); | |
9877 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9878 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9879 | (long) imm_expr.X_add_number); | |
9880 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9881 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9882 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9883 | else | |
9884 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9885 | imm_expr.X_op = O_absent; |
9886 | s = expr_end; | |
9887 | continue; | |
9888 | } | |
9889 | /* Not MDMX Immediate. Fall through. */ | |
9890 | case 'X': /* MDMX destination register. */ | |
9891 | case 'Y': /* MDMX source register. */ | |
9892 | case 'Z': /* MDMX target register. */ | |
9893 | is_mdmx = 1; | |
90ecf173 MR |
9894 | case 'D': /* Floating point destination register. */ |
9895 | case 'S': /* Floating point source register. */ | |
9896 | case 'T': /* Floating point target register. */ | |
9897 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9898 | case 'V': |
9899 | case 'W': | |
707bfff6 TS |
9900 | rtype = RTYPE_FPU; |
9901 | if (is_mdmx | |
9902 | || (mips_opts.ase_mdmx | |
9903 | && (ip->insn_mo->pinfo & FP_D) | |
9904 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9905 | | INSN_COPROC_MEMORY_DELAY | |
9906 | | INSN_LOAD_COPROC_DELAY | |
9907 | | INSN_LOAD_MEMORY_DELAY | |
9908 | | INSN_STORE_MEMORY)))) | |
9909 | rtype |= RTYPE_VEC; | |
252b5132 | 9910 | s_reset = s; |
707bfff6 | 9911 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9912 | { |
252b5132 | 9913 | if ((regno & 1) != 0 |
ca4e0257 | 9914 | && HAVE_32BIT_FPRS |
90ecf173 | 9915 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9916 | as_warn (_("Float register should be even, was %d"), |
9917 | regno); | |
9918 | ||
9919 | c = *args; | |
9920 | if (*s == ' ') | |
f9419b05 | 9921 | ++s; |
252b5132 RH |
9922 | if (args[1] != *s) |
9923 | { | |
9924 | if (c == 'V' || c == 'W') | |
9925 | { | |
9926 | regno = lastregno; | |
9927 | s = s_reset; | |
f9419b05 | 9928 | ++args; |
252b5132 RH |
9929 | } |
9930 | } | |
9931 | switch (c) | |
9932 | { | |
9933 | case 'D': | |
deec1734 | 9934 | case 'X': |
bf12938e | 9935 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9936 | break; |
9937 | case 'V': | |
9938 | case 'S': | |
deec1734 | 9939 | case 'Y': |
bf12938e | 9940 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9941 | break; |
deec1734 CD |
9942 | case 'Q': |
9943 | /* This is like 'Z', but also needs to fix the MDMX | |
9944 | vector/scalar select bits. Note that the | |
9945 | scalar immediate case is handled above. */ | |
9946 | if (*s == '[') | |
9947 | { | |
9948 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9949 | int max_el = (is_qh ? 3 : 7); | |
9950 | s++; | |
9951 | my_getExpression(&imm_expr, s); | |
9952 | check_absolute_expr (ip, &imm_expr); | |
9953 | s = expr_end; | |
9954 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9955 | as_bad (_("Bad element selector %ld"), |
9956 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9957 | imm_expr.X_add_number &= max_el; |
9958 | ip->insn_opcode |= (imm_expr.X_add_number | |
9959 | << (OP_SH_VSEL + | |
9960 | (is_qh ? 2 : 1))); | |
01a3f561 | 9961 | imm_expr.X_op = O_absent; |
deec1734 | 9962 | if (*s != ']') |
20203fb9 | 9963 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9964 | else |
9965 | s++; | |
9966 | } | |
9967 | else | |
9968 | { | |
9969 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9970 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9971 | << OP_SH_VSEL); | |
9972 | else | |
9973 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9974 | OP_SH_VSEL); | |
9975 | } | |
90ecf173 | 9976 | /* Fall through. */ |
252b5132 RH |
9977 | case 'W': |
9978 | case 'T': | |
deec1734 | 9979 | case 'Z': |
bf12938e | 9980 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9981 | break; |
9982 | case 'R': | |
bf12938e | 9983 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9984 | break; |
9985 | } | |
9986 | lastregno = regno; | |
9987 | continue; | |
9988 | } | |
9989 | ||
252b5132 RH |
9990 | switch (*args++) |
9991 | { | |
9992 | case 'V': | |
bf12938e | 9993 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9994 | continue; |
9995 | case 'W': | |
bf12938e | 9996 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9997 | continue; |
9998 | } | |
9999 | break; | |
10000 | ||
10001 | case 'I': | |
10002 | my_getExpression (&imm_expr, s); | |
10003 | if (imm_expr.X_op != O_big | |
10004 | && imm_expr.X_op != O_constant) | |
10005 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
10006 | if (HAVE_32BIT_GPRS) |
10007 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
10008 | s = expr_end; |
10009 | continue; | |
10010 | ||
10011 | case 'A': | |
10012 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 10013 | normalize_address_expr (&offset_expr); |
f6688943 | 10014 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
10015 | s = expr_end; |
10016 | continue; | |
10017 | ||
10018 | case 'F': | |
10019 | case 'L': | |
10020 | case 'f': | |
10021 | case 'l': | |
10022 | { | |
10023 | int f64; | |
ca4e0257 | 10024 | int using_gprs; |
252b5132 RH |
10025 | char *save_in; |
10026 | char *err; | |
10027 | unsigned char temp[8]; | |
10028 | int len; | |
10029 | unsigned int length; | |
10030 | segT seg; | |
10031 | subsegT subseg; | |
10032 | char *p; | |
10033 | ||
10034 | /* These only appear as the last operand in an | |
10035 | instruction, and every instruction that accepts | |
10036 | them in any variant accepts them in all variants. | |
10037 | This means we don't have to worry about backing out | |
10038 | any changes if the instruction does not match. | |
10039 | ||
10040 | The difference between them is the size of the | |
10041 | floating point constant and where it goes. For 'F' | |
10042 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
10043 | is 32 bits. Where the constant is placed is based | |
10044 | on how the MIPS assembler does things: | |
10045 | F -- .rdata | |
10046 | L -- .lit8 | |
10047 | f -- immediate value | |
10048 | l -- .lit4 | |
10049 | ||
10050 | The .lit4 and .lit8 sections are only used if | |
10051 | permitted by the -G argument. | |
10052 | ||
ca4e0257 RS |
10053 | The code below needs to know whether the target register |
10054 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
10055 | 'F' are used with GPR-based instructions and 'l' and | |
10056 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
10057 | |
10058 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 10059 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
10060 | |
10061 | save_in = input_line_pointer; | |
10062 | input_line_pointer = s; | |
10063 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
10064 | length = len; | |
10065 | s = input_line_pointer; | |
10066 | input_line_pointer = save_in; | |
10067 | if (err != NULL && *err != '\0') | |
10068 | { | |
10069 | as_bad (_("Bad floating point constant: %s"), err); | |
10070 | memset (temp, '\0', sizeof temp); | |
10071 | length = f64 ? 8 : 4; | |
10072 | } | |
10073 | ||
9c2799c2 | 10074 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
10075 | |
10076 | if (*args == 'f' | |
10077 | || (*args == 'l' | |
3e722fb5 | 10078 | && (g_switch_value < 4 |
252b5132 RH |
10079 | || (temp[0] == 0 && temp[1] == 0) |
10080 | || (temp[2] == 0 && temp[3] == 0)))) | |
10081 | { | |
10082 | imm_expr.X_op = O_constant; | |
90ecf173 | 10083 | if (!target_big_endian) |
252b5132 RH |
10084 | imm_expr.X_add_number = bfd_getl32 (temp); |
10085 | else | |
10086 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10087 | } | |
10088 | else if (length > 4 | |
90ecf173 | 10089 | && !mips_disable_float_construction |
ca4e0257 RS |
10090 | /* Constants can only be constructed in GPRs and |
10091 | copied to FPRs if the GPRs are at least as wide | |
10092 | as the FPRs. Force the constant into memory if | |
10093 | we are using 64-bit FPRs but the GPRs are only | |
10094 | 32 bits wide. */ | |
10095 | && (using_gprs | |
90ecf173 | 10096 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
10097 | && ((temp[0] == 0 && temp[1] == 0) |
10098 | || (temp[2] == 0 && temp[3] == 0)) | |
10099 | && ((temp[4] == 0 && temp[5] == 0) | |
10100 | || (temp[6] == 0 && temp[7] == 0))) | |
10101 | { | |
ca4e0257 | 10102 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
10103 | instructions. If using 32-bit registers, set |
10104 | imm_expr to the high order 32 bits and offset_expr to | |
10105 | the low order 32 bits. Otherwise, set imm_expr to | |
10106 | the entire 64 bit constant. */ | |
ca4e0257 | 10107 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
10108 | { |
10109 | imm_expr.X_op = O_constant; | |
10110 | offset_expr.X_op = O_constant; | |
90ecf173 | 10111 | if (!target_big_endian) |
252b5132 RH |
10112 | { |
10113 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
10114 | offset_expr.X_add_number = bfd_getl32 (temp); | |
10115 | } | |
10116 | else | |
10117 | { | |
10118 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10119 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
10120 | } | |
10121 | if (offset_expr.X_add_number == 0) | |
10122 | offset_expr.X_op = O_absent; | |
10123 | } | |
10124 | else if (sizeof (imm_expr.X_add_number) > 4) | |
10125 | { | |
10126 | imm_expr.X_op = O_constant; | |
90ecf173 | 10127 | if (!target_big_endian) |
252b5132 RH |
10128 | imm_expr.X_add_number = bfd_getl64 (temp); |
10129 | else | |
10130 | imm_expr.X_add_number = bfd_getb64 (temp); | |
10131 | } | |
10132 | else | |
10133 | { | |
10134 | imm_expr.X_op = O_big; | |
10135 | imm_expr.X_add_number = 4; | |
90ecf173 | 10136 | if (!target_big_endian) |
252b5132 RH |
10137 | { |
10138 | generic_bignum[0] = bfd_getl16 (temp); | |
10139 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
10140 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
10141 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
10142 | } | |
10143 | else | |
10144 | { | |
10145 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
10146 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
10147 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
10148 | generic_bignum[3] = bfd_getb16 (temp); | |
10149 | } | |
10150 | } | |
10151 | } | |
10152 | else | |
10153 | { | |
10154 | const char *newname; | |
10155 | segT new_seg; | |
10156 | ||
10157 | /* Switch to the right section. */ | |
10158 | seg = now_seg; | |
10159 | subseg = now_subseg; | |
10160 | switch (*args) | |
10161 | { | |
10162 | default: /* unused default case avoids warnings. */ | |
10163 | case 'L': | |
10164 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 10165 | if (g_switch_value >= 8) |
252b5132 RH |
10166 | newname = ".lit8"; |
10167 | break; | |
10168 | case 'F': | |
3e722fb5 | 10169 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
10170 | break; |
10171 | case 'l': | |
9c2799c2 | 10172 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
10173 | newname = ".lit4"; |
10174 | break; | |
10175 | } | |
10176 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 10177 | if (IS_ELF) |
252b5132 RH |
10178 | bfd_set_section_flags (stdoutput, new_seg, |
10179 | (SEC_ALLOC | |
10180 | | SEC_LOAD | |
10181 | | SEC_READONLY | |
10182 | | SEC_DATA)); | |
10183 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 10184 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
10185 | record_alignment (new_seg, 4); |
10186 | else | |
10187 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
10188 | if (seg == now_seg) | |
10189 | as_bad (_("Can't use floating point insn in this section")); | |
10190 | ||
10191 | /* Set the argument to the current address in the | |
10192 | section. */ | |
10193 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 10194 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
10195 | offset_expr.X_add_number = 0; |
10196 | ||
10197 | /* Put the floating point number into the section. */ | |
10198 | p = frag_more ((int) length); | |
10199 | memcpy (p, temp, length); | |
10200 | ||
10201 | /* Switch back to the original section. */ | |
10202 | subseg_set (seg, subseg); | |
10203 | } | |
10204 | } | |
10205 | continue; | |
10206 | ||
90ecf173 MR |
10207 | case 'i': /* 16-bit unsigned immediate. */ |
10208 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 10209 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 10210 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
10211 | { |
10212 | int more; | |
5e0116d5 RS |
10213 | offsetT minval, maxval; |
10214 | ||
10215 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10216 | && strcmp (insn->name, insn[1].name) == 0); | |
10217 | ||
10218 | /* If the expression was written as an unsigned number, | |
10219 | only treat it as signed if there are no more | |
10220 | alternatives. */ | |
10221 | if (more | |
10222 | && *args == 'j' | |
10223 | && sizeof (imm_expr.X_add_number) <= 4 | |
10224 | && imm_expr.X_op == O_constant | |
10225 | && imm_expr.X_add_number < 0 | |
10226 | && imm_expr.X_unsigned | |
10227 | && HAVE_64BIT_GPRS) | |
10228 | break; | |
10229 | ||
10230 | /* For compatibility with older assemblers, we accept | |
10231 | 0x8000-0xffff as signed 16-bit numbers when only | |
10232 | signed numbers are allowed. */ | |
10233 | if (*args == 'i') | |
10234 | minval = 0, maxval = 0xffff; | |
10235 | else if (more) | |
10236 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10237 | else |
5e0116d5 RS |
10238 | minval = -0x8000, maxval = 0xffff; |
10239 | ||
10240 | if (imm_expr.X_op != O_constant | |
10241 | || imm_expr.X_add_number < minval | |
10242 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10243 | { |
10244 | if (more) | |
10245 | break; | |
2ae7e77b AH |
10246 | if (imm_expr.X_op == O_constant |
10247 | || imm_expr.X_op == O_big) | |
f71d0d44 | 10248 | as_bad (_("Expression out of range")); |
252b5132 RH |
10249 | } |
10250 | } | |
10251 | s = expr_end; | |
10252 | continue; | |
10253 | ||
90ecf173 | 10254 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
10255 | offset_reloc[0] = BFD_RELOC_LO16; |
10256 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10257 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
10258 | ||
5e0116d5 RS |
10259 | /* Check whether there is only a single bracketed expression |
10260 | left. If so, it must be the base register and the | |
10261 | constant must be zero. */ | |
10262 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10263 | { | |
10264 | offset_expr.X_op = O_constant; | |
10265 | offset_expr.X_add_number = 0; | |
10266 | continue; | |
10267 | } | |
252b5132 RH |
10268 | |
10269 | /* If this value won't fit into a 16 bit offset, then go | |
10270 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10271 | code pattern. */ |
5e0116d5 | 10272 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10273 | && (offset_expr.X_op != O_constant |
10274 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10275 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10276 | break; |
10277 | ||
252b5132 RH |
10278 | s = expr_end; |
10279 | continue; | |
10280 | ||
90ecf173 | 10281 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 10282 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10283 | my_getExpression (&offset_expr, s); |
10284 | s = expr_end; | |
10285 | continue; | |
10286 | ||
90ecf173 | 10287 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10288 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10289 | && imm_expr.X_op == O_constant | |
10290 | && (imm_expr.X_add_number < 0 | |
10291 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10292 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10293 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10294 | s = expr_end; |
10295 | continue; | |
10296 | ||
90ecf173 | 10297 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10298 | my_getExpression (&offset_expr, s); |
10299 | s = expr_end; | |
f6688943 | 10300 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10301 | continue; |
10302 | ||
90ecf173 MR |
10303 | case 'N': /* 3-bit branch condition code. */ |
10304 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10305 | rtype = RTYPE_CCC; |
90ecf173 | 10306 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10307 | rtype |= RTYPE_FCC; |
10308 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10309 | break; |
90ecf173 MR |
10310 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10311 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10312 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10313 | && (regno & 1) != 0) |
90ecf173 MR |
10314 | as_warn (_("Condition code register should be even for %s, " |
10315 | "was %d"), | |
20203fb9 | 10316 | str, regno); |
90ecf173 MR |
10317 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10318 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10319 | && (regno & 3) != 0) |
90ecf173 MR |
10320 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10321 | "was %d"), | |
20203fb9 | 10322 | str, regno); |
252b5132 | 10323 | if (*args == 'N') |
bf12938e | 10324 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10325 | else |
bf12938e | 10326 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10327 | continue; |
252b5132 | 10328 | |
156c2f8b NC |
10329 | case 'H': |
10330 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10331 | s += 2; | |
3882b010 | 10332 | if (ISDIGIT (*s)) |
156c2f8b NC |
10333 | { |
10334 | c = 0; | |
10335 | do | |
10336 | { | |
10337 | c *= 10; | |
10338 | c += *s - '0'; | |
10339 | ++s; | |
10340 | } | |
3882b010 | 10341 | while (ISDIGIT (*s)); |
156c2f8b NC |
10342 | } |
10343 | else | |
10344 | c = 8; /* Invalid sel value. */ | |
10345 | ||
10346 | if (c > 7) | |
f71d0d44 | 10347 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10348 | ip->insn_opcode |= c; |
10349 | continue; | |
10350 | ||
60b63b72 RS |
10351 | case 'e': |
10352 | /* Must be at least one digit. */ | |
10353 | my_getExpression (&imm_expr, s); | |
10354 | check_absolute_expr (ip, &imm_expr); | |
10355 | ||
10356 | if ((unsigned long) imm_expr.X_add_number | |
10357 | > (unsigned long) OP_MASK_VECBYTE) | |
10358 | { | |
10359 | as_bad (_("bad byte vector index (%ld)"), | |
10360 | (long) imm_expr.X_add_number); | |
10361 | imm_expr.X_add_number = 0; | |
10362 | } | |
10363 | ||
bf12938e | 10364 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10365 | imm_expr.X_op = O_absent; |
10366 | s = expr_end; | |
10367 | continue; | |
10368 | ||
10369 | case '%': | |
10370 | my_getExpression (&imm_expr, s); | |
10371 | check_absolute_expr (ip, &imm_expr); | |
10372 | ||
10373 | if ((unsigned long) imm_expr.X_add_number | |
10374 | > (unsigned long) OP_MASK_VECALIGN) | |
10375 | { | |
10376 | as_bad (_("bad byte vector index (%ld)"), | |
10377 | (long) imm_expr.X_add_number); | |
10378 | imm_expr.X_add_number = 0; | |
10379 | } | |
10380 | ||
bf12938e | 10381 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10382 | imm_expr.X_op = O_absent; |
10383 | s = expr_end; | |
10384 | continue; | |
10385 | ||
252b5132 | 10386 | default: |
f71d0d44 | 10387 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10388 | internalError (); |
10389 | } | |
10390 | break; | |
10391 | } | |
10392 | /* Args don't match. */ | |
10393 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10394 | !strcmp (insn->name, insn[1].name)) | |
10395 | { | |
10396 | ++insn; | |
10397 | s = argsStart; | |
f71d0d44 | 10398 | insn_error = _("Illegal operands"); |
252b5132 RH |
10399 | continue; |
10400 | } | |
268f6bed | 10401 | if (save_c) |
570de991 | 10402 | *(--argsStart) = save_c; |
f71d0d44 | 10403 | insn_error = _("Illegal operands"); |
252b5132 RH |
10404 | return; |
10405 | } | |
10406 | } | |
10407 | ||
0499d65b TS |
10408 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10409 | ||
252b5132 RH |
10410 | /* This routine assembles an instruction into its binary format when |
10411 | assembling for the mips16. As a side effect, it sets one of the | |
10412 | global variables imm_reloc or offset_reloc to the type of | |
10413 | relocation to do if one of the operands is an address expression. | |
10414 | It also sets mips16_small and mips16_ext if the user explicitly | |
10415 | requested a small or extended instruction. */ | |
10416 | ||
10417 | static void | |
17a2f251 | 10418 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10419 | { |
10420 | char *s; | |
10421 | const char *args; | |
10422 | struct mips_opcode *insn; | |
10423 | char *argsstart; | |
10424 | unsigned int regno; | |
10425 | unsigned int lastregno = 0; | |
10426 | char *s_reset; | |
d6f16593 | 10427 | size_t i; |
252b5132 RH |
10428 | |
10429 | insn_error = NULL; | |
10430 | ||
b34976b6 AM |
10431 | mips16_small = FALSE; |
10432 | mips16_ext = FALSE; | |
252b5132 | 10433 | |
3882b010 | 10434 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10435 | ; |
10436 | switch (*s) | |
10437 | { | |
10438 | case '\0': | |
10439 | break; | |
10440 | ||
10441 | case ' ': | |
10442 | *s++ = '\0'; | |
10443 | break; | |
10444 | ||
10445 | case '.': | |
10446 | if (s[1] == 't' && s[2] == ' ') | |
10447 | { | |
10448 | *s = '\0'; | |
b34976b6 | 10449 | mips16_small = TRUE; |
252b5132 RH |
10450 | s += 3; |
10451 | break; | |
10452 | } | |
10453 | else if (s[1] == 'e' && s[2] == ' ') | |
10454 | { | |
10455 | *s = '\0'; | |
b34976b6 | 10456 | mips16_ext = TRUE; |
252b5132 RH |
10457 | s += 3; |
10458 | break; | |
10459 | } | |
10460 | /* Fall through. */ | |
10461 | default: | |
10462 | insn_error = _("unknown opcode"); | |
10463 | return; | |
10464 | } | |
10465 | ||
10466 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10467 | mips16_small = TRUE; |
252b5132 RH |
10468 | |
10469 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10470 | { | |
10471 | insn_error = _("unrecognized opcode"); | |
10472 | return; | |
10473 | } | |
10474 | ||
10475 | argsstart = s; | |
10476 | for (;;) | |
10477 | { | |
9b3f89ee TS |
10478 | bfd_boolean ok; |
10479 | ||
9c2799c2 | 10480 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10481 | |
037b32b9 | 10482 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10483 | if (! ok) |
10484 | { | |
10485 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10486 | && strcmp (insn->name, insn[1].name) == 0) | |
10487 | { | |
10488 | ++insn; | |
10489 | continue; | |
10490 | } | |
10491 | else | |
10492 | { | |
10493 | if (!insn_error) | |
10494 | { | |
10495 | static char buf[100]; | |
10496 | sprintf (buf, | |
10497 | _("opcode not supported on this processor: %s (%s)"), | |
10498 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10499 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10500 | insn_error = buf; | |
10501 | } | |
10502 | return; | |
10503 | } | |
10504 | } | |
10505 | ||
1e915849 | 10506 | create_insn (ip, insn); |
252b5132 | 10507 | imm_expr.X_op = O_absent; |
f6688943 TS |
10508 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10509 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10510 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10511 | imm2_expr.X_op = O_absent; |
252b5132 | 10512 | offset_expr.X_op = O_absent; |
f6688943 TS |
10513 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10514 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10515 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10516 | for (args = insn->args; 1; ++args) |
10517 | { | |
10518 | int c; | |
10519 | ||
10520 | if (*s == ' ') | |
10521 | ++s; | |
10522 | ||
10523 | /* In this switch statement we call break if we did not find | |
10524 | a match, continue if we did find a match, or return if we | |
10525 | are done. */ | |
10526 | ||
10527 | c = *args; | |
10528 | switch (c) | |
10529 | { | |
10530 | case '\0': | |
10531 | if (*s == '\0') | |
10532 | { | |
10533 | /* Stuff the immediate value in now, if we can. */ | |
10534 | if (imm_expr.X_op == O_constant | |
f6688943 | 10535 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10536 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10537 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10538 | && insn->pinfo != INSN_MACRO) |
10539 | { | |
d6f16593 MR |
10540 | valueT tmp; |
10541 | ||
10542 | switch (*offset_reloc) | |
10543 | { | |
10544 | case BFD_RELOC_MIPS16_HI16_S: | |
10545 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10546 | break; | |
10547 | ||
10548 | case BFD_RELOC_MIPS16_HI16: | |
10549 | tmp = imm_expr.X_add_number >> 16; | |
10550 | break; | |
10551 | ||
10552 | case BFD_RELOC_MIPS16_LO16: | |
10553 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10554 | - 0x8000; | |
10555 | break; | |
10556 | ||
10557 | case BFD_RELOC_UNUSED: | |
10558 | tmp = imm_expr.X_add_number; | |
10559 | break; | |
10560 | ||
10561 | default: | |
10562 | internalError (); | |
10563 | } | |
10564 | *offset_reloc = BFD_RELOC_UNUSED; | |
10565 | ||
c4e7957c | 10566 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10567 | tmp, TRUE, mips16_small, |
252b5132 RH |
10568 | mips16_ext, &ip->insn_opcode, |
10569 | &ip->use_extend, &ip->extend); | |
10570 | imm_expr.X_op = O_absent; | |
f6688943 | 10571 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10572 | } |
10573 | ||
10574 | return; | |
10575 | } | |
10576 | break; | |
10577 | ||
10578 | case ',': | |
10579 | if (*s++ == c) | |
10580 | continue; | |
10581 | s--; | |
10582 | switch (*++args) | |
10583 | { | |
10584 | case 'v': | |
bf12938e | 10585 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10586 | continue; |
10587 | case 'w': | |
bf12938e | 10588 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10589 | continue; |
10590 | } | |
10591 | break; | |
10592 | ||
10593 | case '(': | |
10594 | case ')': | |
10595 | if (*s++ == c) | |
10596 | continue; | |
10597 | break; | |
10598 | ||
10599 | case 'v': | |
10600 | case 'w': | |
10601 | if (s[0] != '$') | |
10602 | { | |
10603 | if (c == 'v') | |
bf12938e | 10604 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10605 | else |
bf12938e | 10606 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10607 | ++args; |
10608 | continue; | |
10609 | } | |
10610 | /* Fall through. */ | |
10611 | case 'x': | |
10612 | case 'y': | |
10613 | case 'z': | |
10614 | case 'Z': | |
10615 | case '0': | |
10616 | case 'S': | |
10617 | case 'R': | |
10618 | case 'X': | |
10619 | case 'Y': | |
707bfff6 TS |
10620 | s_reset = s; |
10621 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10622 | { |
707bfff6 | 10623 | if (c == 'v' || c == 'w') |
85b51719 | 10624 | { |
707bfff6 | 10625 | if (c == 'v') |
a9e24354 | 10626 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10627 | else |
a9e24354 | 10628 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10629 | ++args; |
10630 | continue; | |
85b51719 | 10631 | } |
707bfff6 | 10632 | break; |
252b5132 RH |
10633 | } |
10634 | ||
10635 | if (*s == ' ') | |
10636 | ++s; | |
10637 | if (args[1] != *s) | |
10638 | { | |
10639 | if (c == 'v' || c == 'w') | |
10640 | { | |
10641 | regno = mips16_to_32_reg_map[lastregno]; | |
10642 | s = s_reset; | |
f9419b05 | 10643 | ++args; |
252b5132 RH |
10644 | } |
10645 | } | |
10646 | ||
10647 | switch (c) | |
10648 | { | |
10649 | case 'x': | |
10650 | case 'y': | |
10651 | case 'z': | |
10652 | case 'v': | |
10653 | case 'w': | |
10654 | case 'Z': | |
10655 | regno = mips32_to_16_reg_map[regno]; | |
10656 | break; | |
10657 | ||
10658 | case '0': | |
10659 | if (regno != 0) | |
10660 | regno = ILLEGAL_REG; | |
10661 | break; | |
10662 | ||
10663 | case 'S': | |
10664 | if (regno != SP) | |
10665 | regno = ILLEGAL_REG; | |
10666 | break; | |
10667 | ||
10668 | case 'R': | |
10669 | if (regno != RA) | |
10670 | regno = ILLEGAL_REG; | |
10671 | break; | |
10672 | ||
10673 | case 'X': | |
10674 | case 'Y': | |
741fe287 MR |
10675 | if (regno == AT && mips_opts.at) |
10676 | { | |
10677 | if (mips_opts.at == ATREG) | |
10678 | as_warn (_("used $at without \".set noat\"")); | |
10679 | else | |
10680 | as_warn (_("used $%u with \".set at=$%u\""), | |
10681 | regno, mips_opts.at); | |
10682 | } | |
252b5132 RH |
10683 | break; |
10684 | ||
10685 | default: | |
10686 | internalError (); | |
10687 | } | |
10688 | ||
10689 | if (regno == ILLEGAL_REG) | |
10690 | break; | |
10691 | ||
10692 | switch (c) | |
10693 | { | |
10694 | case 'x': | |
10695 | case 'v': | |
bf12938e | 10696 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10697 | break; |
10698 | case 'y': | |
10699 | case 'w': | |
bf12938e | 10700 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10701 | break; |
10702 | case 'z': | |
bf12938e | 10703 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10704 | break; |
10705 | case 'Z': | |
bf12938e | 10706 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10707 | case '0': |
10708 | case 'S': | |
10709 | case 'R': | |
10710 | break; | |
10711 | case 'X': | |
bf12938e | 10712 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10713 | break; |
10714 | case 'Y': | |
10715 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10716 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10717 | break; |
10718 | default: | |
10719 | internalError (); | |
10720 | } | |
10721 | ||
10722 | lastregno = regno; | |
10723 | continue; | |
10724 | ||
10725 | case 'P': | |
10726 | if (strncmp (s, "$pc", 3) == 0) | |
10727 | { | |
10728 | s += 3; | |
10729 | continue; | |
10730 | } | |
10731 | break; | |
10732 | ||
252b5132 RH |
10733 | case '5': |
10734 | case 'H': | |
10735 | case 'W': | |
10736 | case 'D': | |
10737 | case 'j': | |
252b5132 RH |
10738 | case 'V': |
10739 | case 'C': | |
10740 | case 'U': | |
10741 | case 'k': | |
10742 | case 'K': | |
d6f16593 MR |
10743 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10744 | if (i > 0) | |
252b5132 | 10745 | { |
d6f16593 | 10746 | if (imm_expr.X_op != O_constant) |
252b5132 | 10747 | { |
b34976b6 | 10748 | mips16_ext = TRUE; |
b34976b6 | 10749 | ip->use_extend = TRUE; |
252b5132 | 10750 | ip->extend = 0; |
252b5132 | 10751 | } |
d6f16593 MR |
10752 | else |
10753 | { | |
10754 | /* We need to relax this instruction. */ | |
10755 | *offset_reloc = *imm_reloc; | |
10756 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10757 | } | |
10758 | s = expr_end; | |
10759 | continue; | |
252b5132 | 10760 | } |
d6f16593 MR |
10761 | *imm_reloc = BFD_RELOC_UNUSED; |
10762 | /* Fall through. */ | |
10763 | case '<': | |
10764 | case '>': | |
10765 | case '[': | |
10766 | case ']': | |
10767 | case '4': | |
10768 | case '8': | |
10769 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10770 | if (imm_expr.X_op == O_register) |
10771 | { | |
10772 | /* What we thought was an expression turned out to | |
10773 | be a register. */ | |
10774 | ||
10775 | if (s[0] == '(' && args[1] == '(') | |
10776 | { | |
10777 | /* It looks like the expression was omitted | |
10778 | before a register indirection, which means | |
10779 | that the expression is implicitly zero. We | |
10780 | still set up imm_expr, so that we handle | |
10781 | explicit extensions correctly. */ | |
10782 | imm_expr.X_op = O_constant; | |
10783 | imm_expr.X_add_number = 0; | |
f6688943 | 10784 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10785 | continue; |
10786 | } | |
10787 | ||
10788 | break; | |
10789 | } | |
10790 | ||
10791 | /* We need to relax this instruction. */ | |
f6688943 | 10792 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10793 | s = expr_end; |
10794 | continue; | |
10795 | ||
10796 | case 'p': | |
10797 | case 'q': | |
10798 | case 'A': | |
10799 | case 'B': | |
10800 | case 'E': | |
10801 | /* We use offset_reloc rather than imm_reloc for the PC | |
10802 | relative operands. This lets macros with both | |
10803 | immediate and address operands work correctly. */ | |
10804 | my_getExpression (&offset_expr, s); | |
10805 | ||
10806 | if (offset_expr.X_op == O_register) | |
10807 | break; | |
10808 | ||
10809 | /* We need to relax this instruction. */ | |
f6688943 | 10810 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10811 | s = expr_end; |
10812 | continue; | |
10813 | ||
10814 | case '6': /* break code */ | |
10815 | my_getExpression (&imm_expr, s); | |
10816 | check_absolute_expr (ip, &imm_expr); | |
10817 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10818 | as_warn (_("Invalid value for `%s' (%lu)"), |
10819 | ip->insn_mo->name, | |
10820 | (unsigned long) imm_expr.X_add_number); | |
10821 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10822 | imm_expr.X_op = O_absent; |
10823 | s = expr_end; | |
10824 | continue; | |
10825 | ||
10826 | case 'a': /* 26 bit address */ | |
10827 | my_getExpression (&offset_expr, s); | |
10828 | s = expr_end; | |
f6688943 | 10829 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10830 | ip->insn_opcode <<= 16; |
10831 | continue; | |
10832 | ||
10833 | case 'l': /* register list for entry macro */ | |
10834 | case 'L': /* register list for exit macro */ | |
10835 | { | |
10836 | int mask; | |
10837 | ||
10838 | if (c == 'l') | |
10839 | mask = 0; | |
10840 | else | |
10841 | mask = 7 << 3; | |
10842 | while (*s != '\0') | |
10843 | { | |
707bfff6 | 10844 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10845 | |
10846 | while (*s == ' ' || *s == ',') | |
10847 | ++s; | |
707bfff6 | 10848 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10849 | freg = 0; |
707bfff6 TS |
10850 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10851 | freg = 1; | |
252b5132 RH |
10852 | else |
10853 | { | |
707bfff6 TS |
10854 | as_bad (_("can't parse register list")); |
10855 | break; | |
252b5132 RH |
10856 | } |
10857 | if (*s == ' ') | |
10858 | ++s; | |
10859 | if (*s != '-') | |
10860 | reg2 = reg1; | |
10861 | else | |
10862 | { | |
10863 | ++s; | |
707bfff6 TS |
10864 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10865 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10866 | { |
707bfff6 TS |
10867 | as_bad (_("invalid register list")); |
10868 | break; | |
252b5132 RH |
10869 | } |
10870 | } | |
10871 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10872 | { | |
10873 | mask &= ~ (7 << 3); | |
10874 | mask |= 5 << 3; | |
10875 | } | |
10876 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10877 | { | |
10878 | mask &= ~ (7 << 3); | |
10879 | mask |= 6 << 3; | |
10880 | } | |
10881 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10882 | mask |= (reg2 - 3) << 3; | |
10883 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10884 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10885 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10886 | mask |= 1; |
10887 | else | |
10888 | { | |
10889 | as_bad (_("invalid register list")); | |
10890 | break; | |
10891 | } | |
10892 | } | |
10893 | /* The mask is filled in in the opcode table for the | |
10894 | benefit of the disassembler. We remove it before | |
10895 | applying the actual mask. */ | |
10896 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10897 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10898 | } | |
10899 | continue; | |
10900 | ||
0499d65b TS |
10901 | case 'm': /* Register list for save insn. */ |
10902 | case 'M': /* Register list for restore insn. */ | |
10903 | { | |
10904 | int opcode = 0; | |
10905 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10906 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10907 | |
10908 | while (*s != '\0') | |
10909 | { | |
10910 | unsigned int reg1, reg2; | |
10911 | ||
10912 | SKIP_SPACE_TABS (s); | |
10913 | while (*s == ',') | |
10914 | ++s; | |
10915 | SKIP_SPACE_TABS (s); | |
10916 | ||
10917 | my_getExpression (&imm_expr, s); | |
10918 | if (imm_expr.X_op == O_constant) | |
10919 | { | |
10920 | /* Handle the frame size. */ | |
10921 | if (seen_framesz) | |
10922 | { | |
10923 | as_bad (_("more than one frame size in list")); | |
10924 | break; | |
10925 | } | |
10926 | seen_framesz = 1; | |
10927 | framesz = imm_expr.X_add_number; | |
10928 | imm_expr.X_op = O_absent; | |
10929 | s = expr_end; | |
10930 | continue; | |
10931 | } | |
10932 | ||
707bfff6 | 10933 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10934 | { |
10935 | as_bad (_("can't parse register list")); | |
10936 | break; | |
10937 | } | |
0499d65b | 10938 | |
707bfff6 TS |
10939 | while (*s == ' ') |
10940 | ++s; | |
10941 | ||
0499d65b TS |
10942 | if (*s != '-') |
10943 | reg2 = reg1; | |
10944 | else | |
10945 | { | |
10946 | ++s; | |
707bfff6 TS |
10947 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10948 | || reg2 < reg1) | |
0499d65b TS |
10949 | { |
10950 | as_bad (_("can't parse register list")); | |
10951 | break; | |
10952 | } | |
0499d65b TS |
10953 | } |
10954 | ||
10955 | while (reg1 <= reg2) | |
10956 | { | |
10957 | if (reg1 >= 4 && reg1 <= 7) | |
10958 | { | |
3a93f742 | 10959 | if (!seen_framesz) |
0499d65b | 10960 | /* args $a0-$a3 */ |
91d6fa6a | 10961 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10962 | else |
10963 | /* statics $a0-$a3 */ | |
10964 | statics |= 1 << (reg1 - 4); | |
10965 | } | |
10966 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10967 | { | |
10968 | /* $s0-$s8 */ | |
10969 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10970 | } | |
10971 | else if (reg1 == 31) | |
10972 | { | |
10973 | /* Add $ra to insn. */ | |
10974 | opcode |= 0x40; | |
10975 | } | |
10976 | else | |
10977 | { | |
10978 | as_bad (_("unexpected register in list")); | |
10979 | break; | |
10980 | } | |
10981 | if (++reg1 == 24) | |
10982 | reg1 = 30; | |
10983 | } | |
10984 | } | |
10985 | ||
10986 | /* Encode args/statics combination. */ | |
91d6fa6a | 10987 | if (nargs & statics) |
0499d65b | 10988 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10989 | else if (nargs == 0xf) |
0499d65b TS |
10990 | /* All $a0-$a3 are args. */ |
10991 | opcode |= MIPS16_ALL_ARGS << 16; | |
10992 | else if (statics == 0xf) | |
10993 | /* All $a0-$a3 are statics. */ | |
10994 | opcode |= MIPS16_ALL_STATICS << 16; | |
10995 | else | |
10996 | { | |
10997 | int narg = 0, nstat = 0; | |
10998 | ||
10999 | /* Count arg registers. */ | |
91d6fa6a | 11000 | while (nargs & 0x1) |
0499d65b | 11001 | { |
91d6fa6a | 11002 | nargs >>= 1; |
0499d65b TS |
11003 | narg++; |
11004 | } | |
91d6fa6a | 11005 | if (nargs != 0) |
0499d65b TS |
11006 | as_bad (_("invalid arg register list")); |
11007 | ||
11008 | /* Count static registers. */ | |
11009 | while (statics & 0x8) | |
11010 | { | |
11011 | statics = (statics << 1) & 0xf; | |
11012 | nstat++; | |
11013 | } | |
11014 | if (statics != 0) | |
11015 | as_bad (_("invalid static register list")); | |
11016 | ||
11017 | /* Encode args/statics. */ | |
11018 | opcode |= ((narg << 2) | nstat) << 16; | |
11019 | } | |
11020 | ||
11021 | /* Encode $s0/$s1. */ | |
11022 | if (sregs & (1 << 0)) /* $s0 */ | |
11023 | opcode |= 0x20; | |
11024 | if (sregs & (1 << 1)) /* $s1 */ | |
11025 | opcode |= 0x10; | |
11026 | sregs >>= 2; | |
11027 | ||
11028 | if (sregs != 0) | |
11029 | { | |
11030 | /* Count regs $s2-$s8. */ | |
11031 | int nsreg = 0; | |
11032 | while (sregs & 1) | |
11033 | { | |
11034 | sregs >>= 1; | |
11035 | nsreg++; | |
11036 | } | |
11037 | if (sregs != 0) | |
11038 | as_bad (_("invalid static register list")); | |
11039 | /* Encode $s2-$s8. */ | |
11040 | opcode |= nsreg << 24; | |
11041 | } | |
11042 | ||
11043 | /* Encode frame size. */ | |
11044 | if (!seen_framesz) | |
11045 | as_bad (_("missing frame size")); | |
11046 | else if ((framesz & 7) != 0 || framesz < 0 | |
11047 | || framesz > 0xff * 8) | |
11048 | as_bad (_("invalid frame size")); | |
11049 | else if (framesz != 128 || (opcode >> 16) != 0) | |
11050 | { | |
11051 | framesz /= 8; | |
11052 | opcode |= (((framesz & 0xf0) << 16) | |
11053 | | (framesz & 0x0f)); | |
11054 | } | |
11055 | ||
11056 | /* Finally build the instruction. */ | |
11057 | if ((opcode >> 16) != 0 || framesz == 0) | |
11058 | { | |
11059 | ip->use_extend = TRUE; | |
11060 | ip->extend = opcode >> 16; | |
11061 | } | |
11062 | ip->insn_opcode |= opcode & 0x7f; | |
11063 | } | |
11064 | continue; | |
11065 | ||
252b5132 RH |
11066 | case 'e': /* extend code */ |
11067 | my_getExpression (&imm_expr, s); | |
11068 | check_absolute_expr (ip, &imm_expr); | |
11069 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
11070 | { | |
11071 | as_warn (_("Invalid value for `%s' (%lu)"), | |
11072 | ip->insn_mo->name, | |
11073 | (unsigned long) imm_expr.X_add_number); | |
11074 | imm_expr.X_add_number &= 0x7ff; | |
11075 | } | |
11076 | ip->insn_opcode |= imm_expr.X_add_number; | |
11077 | imm_expr.X_op = O_absent; | |
11078 | s = expr_end; | |
11079 | continue; | |
11080 | ||
11081 | default: | |
11082 | internalError (); | |
11083 | } | |
11084 | break; | |
11085 | } | |
11086 | ||
11087 | /* Args don't match. */ | |
11088 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
11089 | strcmp (insn->name, insn[1].name) == 0) | |
11090 | { | |
11091 | ++insn; | |
11092 | s = argsstart; | |
11093 | continue; | |
11094 | } | |
11095 | ||
11096 | insn_error = _("illegal operands"); | |
11097 | ||
11098 | return; | |
11099 | } | |
11100 | } | |
11101 | ||
11102 | /* This structure holds information we know about a mips16 immediate | |
11103 | argument type. */ | |
11104 | ||
e972090a NC |
11105 | struct mips16_immed_operand |
11106 | { | |
252b5132 RH |
11107 | /* The type code used in the argument string in the opcode table. */ |
11108 | int type; | |
11109 | /* The number of bits in the short form of the opcode. */ | |
11110 | int nbits; | |
11111 | /* The number of bits in the extended form of the opcode. */ | |
11112 | int extbits; | |
11113 | /* The amount by which the short form is shifted when it is used; | |
11114 | for example, the sw instruction has a shift count of 2. */ | |
11115 | int shift; | |
11116 | /* The amount by which the short form is shifted when it is stored | |
11117 | into the instruction code. */ | |
11118 | int op_shift; | |
11119 | /* Non-zero if the short form is unsigned. */ | |
11120 | int unsp; | |
11121 | /* Non-zero if the extended form is unsigned. */ | |
11122 | int extu; | |
11123 | /* Non-zero if the value is PC relative. */ | |
11124 | int pcrel; | |
11125 | }; | |
11126 | ||
11127 | /* The mips16 immediate operand types. */ | |
11128 | ||
11129 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
11130 | { | |
11131 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11132 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11133 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11134 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11135 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
11136 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11137 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11138 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11139 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11140 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
11141 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11142 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11143 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11144 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
11145 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11146 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11147 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11148 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11149 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
11150 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
11151 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
11152 | }; | |
11153 | ||
11154 | #define MIPS16_NUM_IMMED \ | |
11155 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
11156 | ||
11157 | /* Handle a mips16 instruction with an immediate value. This or's the | |
11158 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
11159 | whether an extended value is needed; if one is needed, it sets | |
11160 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
11161 | If SMALL is true, an unextended opcode was explicitly requested. | |
11162 | If EXT is true, an extended opcode was explicitly requested. If | |
11163 | WARN is true, warn if EXT does not match reality. */ | |
11164 | ||
11165 | static void | |
17a2f251 TS |
11166 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
11167 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
11168 | unsigned long *insn, bfd_boolean *use_extend, | |
11169 | unsigned short *extend) | |
252b5132 | 11170 | { |
3994f87e | 11171 | const struct mips16_immed_operand *op; |
252b5132 | 11172 | int mintiny, maxtiny; |
b34976b6 | 11173 | bfd_boolean needext; |
252b5132 RH |
11174 | |
11175 | op = mips16_immed_operands; | |
11176 | while (op->type != type) | |
11177 | { | |
11178 | ++op; | |
9c2799c2 | 11179 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
11180 | } |
11181 | ||
11182 | if (op->unsp) | |
11183 | { | |
11184 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11185 | { | |
11186 | mintiny = 1; | |
11187 | maxtiny = 1 << op->nbits; | |
11188 | } | |
11189 | else | |
11190 | { | |
11191 | mintiny = 0; | |
11192 | maxtiny = (1 << op->nbits) - 1; | |
11193 | } | |
11194 | } | |
11195 | else | |
11196 | { | |
11197 | mintiny = - (1 << (op->nbits - 1)); | |
11198 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11199 | } | |
11200 | ||
11201 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11202 | if (type == 'p' || type == 'q') | |
11203 | val /= 2; | |
11204 | ||
11205 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11206 | || val < (mintiny << op->shift) | |
11207 | || val > (maxtiny << op->shift)) | |
b34976b6 | 11208 | needext = TRUE; |
252b5132 | 11209 | else |
b34976b6 | 11210 | needext = FALSE; |
252b5132 RH |
11211 | |
11212 | if (warn && ext && ! needext) | |
beae10d5 KH |
11213 | as_warn_where (file, line, |
11214 | _("extended operand requested but not required")); | |
252b5132 RH |
11215 | if (small && needext) |
11216 | as_bad_where (file, line, _("invalid unextended operand value")); | |
11217 | ||
11218 | if (small || (! ext && ! needext)) | |
11219 | { | |
11220 | int insnval; | |
11221 | ||
b34976b6 | 11222 | *use_extend = FALSE; |
252b5132 RH |
11223 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11224 | insnval <<= op->op_shift; | |
11225 | *insn |= insnval; | |
11226 | } | |
11227 | else | |
11228 | { | |
11229 | long minext, maxext; | |
11230 | int extval; | |
11231 | ||
11232 | if (op->extu) | |
11233 | { | |
11234 | minext = 0; | |
11235 | maxext = (1 << op->extbits) - 1; | |
11236 | } | |
11237 | else | |
11238 | { | |
11239 | minext = - (1 << (op->extbits - 1)); | |
11240 | maxext = (1 << (op->extbits - 1)) - 1; | |
11241 | } | |
11242 | if (val < minext || val > maxext) | |
11243 | as_bad_where (file, line, | |
11244 | _("operand value out of range for instruction")); | |
11245 | ||
b34976b6 | 11246 | *use_extend = TRUE; |
252b5132 RH |
11247 | if (op->extbits == 16) |
11248 | { | |
11249 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11250 | val &= 0x1f; | |
11251 | } | |
11252 | else if (op->extbits == 15) | |
11253 | { | |
11254 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11255 | val &= 0xf; | |
11256 | } | |
11257 | else | |
11258 | { | |
11259 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11260 | val = 0; | |
11261 | } | |
11262 | ||
11263 | *extend = (unsigned short) extval; | |
11264 | *insn |= val; | |
11265 | } | |
11266 | } | |
11267 | \f | |
d6f16593 | 11268 | struct percent_op_match |
ad8d3bb3 | 11269 | { |
5e0116d5 RS |
11270 | const char *str; |
11271 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11272 | }; |
11273 | ||
11274 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11275 | { |
5e0116d5 | 11276 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11277 | #ifdef OBJ_ELF |
5e0116d5 RS |
11278 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11279 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11280 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11281 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11282 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11283 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11284 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11285 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11286 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11287 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11288 | {"%half", BFD_RELOC_16}, | |
11289 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11290 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11291 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11292 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11293 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11294 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11295 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11296 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11297 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11298 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11299 | #endif |
5e0116d5 | 11300 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11301 | }; |
11302 | ||
d6f16593 MR |
11303 | static const struct percent_op_match mips16_percent_op[] = |
11304 | { | |
11305 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11306 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11307 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11308 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11309 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11310 | }; | |
11311 | ||
252b5132 | 11312 | |
5e0116d5 RS |
11313 | /* Return true if *STR points to a relocation operator. When returning true, |
11314 | move *STR over the operator and store its relocation code in *RELOC. | |
11315 | Leave both *STR and *RELOC alone when returning false. */ | |
11316 | ||
11317 | static bfd_boolean | |
17a2f251 | 11318 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11319 | { |
d6f16593 MR |
11320 | const struct percent_op_match *percent_op; |
11321 | size_t limit, i; | |
11322 | ||
11323 | if (mips_opts.mips16) | |
11324 | { | |
11325 | percent_op = mips16_percent_op; | |
11326 | limit = ARRAY_SIZE (mips16_percent_op); | |
11327 | } | |
11328 | else | |
11329 | { | |
11330 | percent_op = mips_percent_op; | |
11331 | limit = ARRAY_SIZE (mips_percent_op); | |
11332 | } | |
76b3015f | 11333 | |
d6f16593 | 11334 | for (i = 0; i < limit; i++) |
5e0116d5 | 11335 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11336 | { |
3f98094e DJ |
11337 | int len = strlen (percent_op[i].str); |
11338 | ||
11339 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11340 | continue; | |
11341 | ||
5e0116d5 RS |
11342 | *str += strlen (percent_op[i].str); |
11343 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11344 | |
5e0116d5 RS |
11345 | /* Check whether the output BFD supports this relocation. |
11346 | If not, issue an error and fall back on something safe. */ | |
11347 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11348 | { |
20203fb9 | 11349 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11350 | percent_op[i].str); |
01a3f561 | 11351 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11352 | } |
5e0116d5 | 11353 | return TRUE; |
394f9b3a | 11354 | } |
5e0116d5 | 11355 | return FALSE; |
394f9b3a | 11356 | } |
ad8d3bb3 | 11357 | |
ad8d3bb3 | 11358 | |
5e0116d5 RS |
11359 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11360 | expression in *EP and the relocations in the array starting | |
11361 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11362 | |
01a3f561 | 11363 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11364 | |
5e0116d5 | 11365 | static size_t |
17a2f251 TS |
11366 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11367 | char *str) | |
ad8d3bb3 | 11368 | { |
5e0116d5 RS |
11369 | bfd_reloc_code_real_type reversed_reloc[3]; |
11370 | size_t reloc_index, i; | |
09b8f35a RS |
11371 | int crux_depth, str_depth; |
11372 | char *crux; | |
5e0116d5 RS |
11373 | |
11374 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11375 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11376 | of the main expression and with CRUX_DEPTH containing the number | |
11377 | of open brackets at that point. */ | |
11378 | reloc_index = -1; | |
11379 | str_depth = 0; | |
11380 | do | |
fb1b3232 | 11381 | { |
09b8f35a RS |
11382 | reloc_index++; |
11383 | crux = str; | |
11384 | crux_depth = str_depth; | |
11385 | ||
11386 | /* Skip over whitespace and brackets, keeping count of the number | |
11387 | of brackets. */ | |
11388 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11389 | if (*str++ == '(') | |
11390 | str_depth++; | |
5e0116d5 | 11391 | } |
09b8f35a RS |
11392 | while (*str == '%' |
11393 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11394 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11395 | |
09b8f35a | 11396 | my_getExpression (ep, crux); |
5e0116d5 | 11397 | str = expr_end; |
394f9b3a | 11398 | |
5e0116d5 | 11399 | /* Match every open bracket. */ |
09b8f35a | 11400 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11401 | if (*str++ == ')') |
09b8f35a | 11402 | crux_depth--; |
394f9b3a | 11403 | |
09b8f35a | 11404 | if (crux_depth > 0) |
20203fb9 | 11405 | as_bad (_("unclosed '('")); |
394f9b3a | 11406 | |
5e0116d5 | 11407 | expr_end = str; |
252b5132 | 11408 | |
01a3f561 | 11409 | if (reloc_index != 0) |
64bdfcaf RS |
11410 | { |
11411 | prev_reloc_op_frag = frag_now; | |
11412 | for (i = 0; i < reloc_index; i++) | |
11413 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11414 | } | |
fb1b3232 | 11415 | |
5e0116d5 | 11416 | return reloc_index; |
252b5132 RH |
11417 | } |
11418 | ||
11419 | static void | |
17a2f251 | 11420 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11421 | { |
11422 | char *save_in; | |
11423 | ||
11424 | save_in = input_line_pointer; | |
11425 | input_line_pointer = str; | |
11426 | expression (ep); | |
11427 | expr_end = input_line_pointer; | |
11428 | input_line_pointer = save_in; | |
252b5132 RH |
11429 | } |
11430 | ||
252b5132 | 11431 | char * |
17a2f251 | 11432 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11433 | { |
499ac353 | 11434 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11435 | } |
11436 | ||
11437 | void | |
17a2f251 | 11438 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11439 | { |
11440 | if (target_big_endian) | |
11441 | number_to_chars_bigendian (buf, val, n); | |
11442 | else | |
11443 | number_to_chars_littleendian (buf, val, n); | |
11444 | } | |
11445 | \f | |
ae948b86 | 11446 | #ifdef OBJ_ELF |
e013f690 TS |
11447 | static int support_64bit_objects(void) |
11448 | { | |
11449 | const char **list, **l; | |
aa3d8fdf | 11450 | int yes; |
e013f690 TS |
11451 | |
11452 | list = bfd_target_list (); | |
11453 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
11454 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
11455 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 11456 | break; |
aa3d8fdf | 11457 | yes = (*l != NULL); |
e013f690 | 11458 | free (list); |
aa3d8fdf | 11459 | return yes; |
e013f690 | 11460 | } |
ae948b86 | 11461 | #endif /* OBJ_ELF */ |
e013f690 | 11462 | |
78849248 | 11463 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11464 | |
23fce1e3 NC |
11465 | enum options |
11466 | { | |
11467 | OPTION_MARCH = OPTION_MD_BASE, | |
11468 | OPTION_MTUNE, | |
11469 | OPTION_MIPS1, | |
11470 | OPTION_MIPS2, | |
11471 | OPTION_MIPS3, | |
11472 | OPTION_MIPS4, | |
11473 | OPTION_MIPS5, | |
11474 | OPTION_MIPS32, | |
11475 | OPTION_MIPS64, | |
11476 | OPTION_MIPS32R2, | |
11477 | OPTION_MIPS64R2, | |
11478 | OPTION_MIPS16, | |
11479 | OPTION_NO_MIPS16, | |
11480 | OPTION_MIPS3D, | |
11481 | OPTION_NO_MIPS3D, | |
11482 | OPTION_MDMX, | |
11483 | OPTION_NO_MDMX, | |
11484 | OPTION_DSP, | |
11485 | OPTION_NO_DSP, | |
11486 | OPTION_MT, | |
11487 | OPTION_NO_MT, | |
11488 | OPTION_SMARTMIPS, | |
11489 | OPTION_NO_SMARTMIPS, | |
11490 | OPTION_DSPR2, | |
11491 | OPTION_NO_DSPR2, | |
11492 | OPTION_COMPAT_ARCH_BASE, | |
11493 | OPTION_M4650, | |
11494 | OPTION_NO_M4650, | |
11495 | OPTION_M4010, | |
11496 | OPTION_NO_M4010, | |
11497 | OPTION_M4100, | |
11498 | OPTION_NO_M4100, | |
11499 | OPTION_M3900, | |
11500 | OPTION_NO_M3900, | |
11501 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11502 | OPTION_MNO_7000_HILO_FIX, |
11503 | OPTION_FIX_24K, | |
11504 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11505 | OPTION_FIX_LOONGSON2F_JUMP, |
11506 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11507 | OPTION_FIX_LOONGSON2F_NOP, | |
11508 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11509 | OPTION_FIX_VR4120, |
11510 | OPTION_NO_FIX_VR4120, | |
11511 | OPTION_FIX_VR4130, | |
11512 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11513 | OPTION_FIX_CN63XXP1, |
11514 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11515 | OPTION_TRAP, |
11516 | OPTION_BREAK, | |
11517 | OPTION_EB, | |
11518 | OPTION_EL, | |
11519 | OPTION_FP32, | |
11520 | OPTION_GP32, | |
11521 | OPTION_CONSTRUCT_FLOATS, | |
11522 | OPTION_NO_CONSTRUCT_FLOATS, | |
11523 | OPTION_FP64, | |
11524 | OPTION_GP64, | |
11525 | OPTION_RELAX_BRANCH, | |
11526 | OPTION_NO_RELAX_BRANCH, | |
11527 | OPTION_MSHARED, | |
11528 | OPTION_MNO_SHARED, | |
11529 | OPTION_MSYM32, | |
11530 | OPTION_MNO_SYM32, | |
11531 | OPTION_SOFT_FLOAT, | |
11532 | OPTION_HARD_FLOAT, | |
11533 | OPTION_SINGLE_FLOAT, | |
11534 | OPTION_DOUBLE_FLOAT, | |
11535 | OPTION_32, | |
11536 | #ifdef OBJ_ELF | |
11537 | OPTION_CALL_SHARED, | |
11538 | OPTION_CALL_NONPIC, | |
11539 | OPTION_NON_SHARED, | |
11540 | OPTION_XGOT, | |
11541 | OPTION_MABI, | |
11542 | OPTION_N32, | |
11543 | OPTION_64, | |
11544 | OPTION_MDEBUG, | |
11545 | OPTION_NO_MDEBUG, | |
11546 | OPTION_PDR, | |
11547 | OPTION_NO_PDR, | |
11548 | OPTION_MVXWORKS_PIC, | |
11549 | #endif /* OBJ_ELF */ | |
11550 | OPTION_END_OF_ENUM | |
11551 | }; | |
11552 | ||
e972090a NC |
11553 | struct option md_longopts[] = |
11554 | { | |
f9b4148d | 11555 | /* Options which specify architecture. */ |
f9b4148d | 11556 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11557 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11558 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11559 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11560 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11561 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11562 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11563 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11564 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11565 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11566 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11567 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11568 | |
11569 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11570 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11571 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11572 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11573 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11574 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11575 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11576 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11577 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11578 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11579 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11580 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11581 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11582 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11583 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11584 | |
11585 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11586 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11587 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11588 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11589 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11590 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11591 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11592 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11593 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11594 | ||
11595 | /* Options which enable bug fixes. */ | |
f9b4148d | 11596 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11597 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11598 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11599 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11600 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11601 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11602 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11603 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11604 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11605 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11606 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11607 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11608 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11609 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11610 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11611 | |
11612 | /* Miscellaneous options. */ | |
252b5132 RH |
11613 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11614 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11615 | {"break", no_argument, NULL, OPTION_BREAK}, |
11616 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11617 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11618 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11619 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11620 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11621 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11622 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11623 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11624 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11625 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11626 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11627 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11628 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11629 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11630 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11631 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11632 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11633 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11634 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11635 | |
11636 | /* Strictly speaking this next option is ELF specific, | |
11637 | but we allow it for other ports as well in order to | |
11638 | make testing easier. */ | |
11639 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11640 | |
f9b4148d | 11641 | /* ELF-specific options. */ |
156c2f8b | 11642 | #ifdef OBJ_ELF |
156c2f8b NC |
11643 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11644 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11645 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11646 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11647 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11648 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11649 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11650 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11651 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11652 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11653 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11654 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11655 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11656 | #endif /* OBJ_ELF */ |
f9b4148d | 11657 | |
252b5132 RH |
11658 | {NULL, no_argument, NULL, 0} |
11659 | }; | |
156c2f8b | 11660 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11661 | |
316f5878 RS |
11662 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11663 | NEW_VALUE. Warn if another value was already specified. Note: | |
11664 | we have to defer parsing the -march and -mtune arguments in order | |
11665 | to handle 'from-abi' correctly, since the ABI might be specified | |
11666 | in a later argument. */ | |
11667 | ||
11668 | static void | |
17a2f251 | 11669 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11670 | { |
11671 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11672 | as_warn (_("A different %s was already specified, is now %s"), | |
11673 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11674 | new_value); | |
11675 | ||
11676 | *string_ptr = new_value; | |
11677 | } | |
11678 | ||
252b5132 | 11679 | int |
17a2f251 | 11680 | md_parse_option (int c, char *arg) |
252b5132 RH |
11681 | { |
11682 | switch (c) | |
11683 | { | |
119d663a NC |
11684 | case OPTION_CONSTRUCT_FLOATS: |
11685 | mips_disable_float_construction = 0; | |
11686 | break; | |
bdaaa2e1 | 11687 | |
119d663a NC |
11688 | case OPTION_NO_CONSTRUCT_FLOATS: |
11689 | mips_disable_float_construction = 1; | |
11690 | break; | |
bdaaa2e1 | 11691 | |
252b5132 RH |
11692 | case OPTION_TRAP: |
11693 | mips_trap = 1; | |
11694 | break; | |
11695 | ||
11696 | case OPTION_BREAK: | |
11697 | mips_trap = 0; | |
11698 | break; | |
11699 | ||
11700 | case OPTION_EB: | |
11701 | target_big_endian = 1; | |
11702 | break; | |
11703 | ||
11704 | case OPTION_EL: | |
11705 | target_big_endian = 0; | |
11706 | break; | |
11707 | ||
11708 | case 'O': | |
4ffff32f TS |
11709 | if (arg == NULL) |
11710 | mips_optimize = 1; | |
11711 | else if (arg[0] == '0') | |
11712 | mips_optimize = 0; | |
11713 | else if (arg[0] == '1') | |
252b5132 RH |
11714 | mips_optimize = 1; |
11715 | else | |
11716 | mips_optimize = 2; | |
11717 | break; | |
11718 | ||
11719 | case 'g': | |
11720 | if (arg == NULL) | |
11721 | mips_debug = 2; | |
11722 | else | |
11723 | mips_debug = atoi (arg); | |
252b5132 RH |
11724 | break; |
11725 | ||
11726 | case OPTION_MIPS1: | |
316f5878 | 11727 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11728 | break; |
11729 | ||
11730 | case OPTION_MIPS2: | |
316f5878 | 11731 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11732 | break; |
11733 | ||
11734 | case OPTION_MIPS3: | |
316f5878 | 11735 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11736 | break; |
11737 | ||
11738 | case OPTION_MIPS4: | |
316f5878 | 11739 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11740 | break; |
11741 | ||
84ea6cf2 | 11742 | case OPTION_MIPS5: |
316f5878 | 11743 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11744 | break; |
11745 | ||
e7af610e | 11746 | case OPTION_MIPS32: |
316f5878 | 11747 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11748 | break; |
11749 | ||
af7ee8bf CD |
11750 | case OPTION_MIPS32R2: |
11751 | file_mips_isa = ISA_MIPS32R2; | |
11752 | break; | |
11753 | ||
5f74bc13 CD |
11754 | case OPTION_MIPS64R2: |
11755 | file_mips_isa = ISA_MIPS64R2; | |
11756 | break; | |
11757 | ||
84ea6cf2 | 11758 | case OPTION_MIPS64: |
316f5878 | 11759 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11760 | break; |
11761 | ||
ec68c924 | 11762 | case OPTION_MTUNE: |
316f5878 RS |
11763 | mips_set_option_string (&mips_tune_string, arg); |
11764 | break; | |
ec68c924 | 11765 | |
316f5878 RS |
11766 | case OPTION_MARCH: |
11767 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11768 | break; |
11769 | ||
11770 | case OPTION_M4650: | |
316f5878 RS |
11771 | mips_set_option_string (&mips_arch_string, "4650"); |
11772 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11773 | break; |
11774 | ||
11775 | case OPTION_NO_M4650: | |
11776 | break; | |
11777 | ||
11778 | case OPTION_M4010: | |
316f5878 RS |
11779 | mips_set_option_string (&mips_arch_string, "4010"); |
11780 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11781 | break; |
11782 | ||
11783 | case OPTION_NO_M4010: | |
11784 | break; | |
11785 | ||
11786 | case OPTION_M4100: | |
316f5878 RS |
11787 | mips_set_option_string (&mips_arch_string, "4100"); |
11788 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11789 | break; |
11790 | ||
11791 | case OPTION_NO_M4100: | |
11792 | break; | |
11793 | ||
252b5132 | 11794 | case OPTION_M3900: |
316f5878 RS |
11795 | mips_set_option_string (&mips_arch_string, "3900"); |
11796 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11797 | break; |
bdaaa2e1 | 11798 | |
252b5132 RH |
11799 | case OPTION_NO_M3900: |
11800 | break; | |
11801 | ||
deec1734 CD |
11802 | case OPTION_MDMX: |
11803 | mips_opts.ase_mdmx = 1; | |
11804 | break; | |
11805 | ||
11806 | case OPTION_NO_MDMX: | |
11807 | mips_opts.ase_mdmx = 0; | |
11808 | break; | |
11809 | ||
74cd071d CF |
11810 | case OPTION_DSP: |
11811 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11812 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11813 | break; |
11814 | ||
11815 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11816 | mips_opts.ase_dsp = 0; |
11817 | mips_opts.ase_dspr2 = 0; | |
11818 | break; | |
11819 | ||
11820 | case OPTION_DSPR2: | |
11821 | mips_opts.ase_dspr2 = 1; | |
11822 | mips_opts.ase_dsp = 1; | |
11823 | break; | |
11824 | ||
11825 | case OPTION_NO_DSPR2: | |
11826 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11827 | mips_opts.ase_dsp = 0; |
11828 | break; | |
11829 | ||
ef2e4d86 CF |
11830 | case OPTION_MT: |
11831 | mips_opts.ase_mt = 1; | |
11832 | break; | |
11833 | ||
11834 | case OPTION_NO_MT: | |
11835 | mips_opts.ase_mt = 0; | |
11836 | break; | |
11837 | ||
252b5132 RH |
11838 | case OPTION_MIPS16: |
11839 | mips_opts.mips16 = 1; | |
7d10b47d | 11840 | mips_no_prev_insn (); |
252b5132 RH |
11841 | break; |
11842 | ||
11843 | case OPTION_NO_MIPS16: | |
11844 | mips_opts.mips16 = 0; | |
7d10b47d | 11845 | mips_no_prev_insn (); |
252b5132 RH |
11846 | break; |
11847 | ||
1f25f5d3 CD |
11848 | case OPTION_MIPS3D: |
11849 | mips_opts.ase_mips3d = 1; | |
11850 | break; | |
11851 | ||
11852 | case OPTION_NO_MIPS3D: | |
11853 | mips_opts.ase_mips3d = 0; | |
11854 | break; | |
11855 | ||
e16bfa71 TS |
11856 | case OPTION_SMARTMIPS: |
11857 | mips_opts.ase_smartmips = 1; | |
11858 | break; | |
11859 | ||
11860 | case OPTION_NO_SMARTMIPS: | |
11861 | mips_opts.ase_smartmips = 0; | |
11862 | break; | |
11863 | ||
6a32d874 CM |
11864 | case OPTION_FIX_24K: |
11865 | mips_fix_24k = 1; | |
11866 | break; | |
11867 | ||
11868 | case OPTION_NO_FIX_24K: | |
11869 | mips_fix_24k = 0; | |
11870 | break; | |
11871 | ||
c67a084a NC |
11872 | case OPTION_FIX_LOONGSON2F_JUMP: |
11873 | mips_fix_loongson2f_jump = TRUE; | |
11874 | break; | |
11875 | ||
11876 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11877 | mips_fix_loongson2f_jump = FALSE; | |
11878 | break; | |
11879 | ||
11880 | case OPTION_FIX_LOONGSON2F_NOP: | |
11881 | mips_fix_loongson2f_nop = TRUE; | |
11882 | break; | |
11883 | ||
11884 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11885 | mips_fix_loongson2f_nop = FALSE; | |
11886 | break; | |
11887 | ||
d766e8ec RS |
11888 | case OPTION_FIX_VR4120: |
11889 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11890 | break; |
11891 | ||
d766e8ec RS |
11892 | case OPTION_NO_FIX_VR4120: |
11893 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11894 | break; |
11895 | ||
7d8e00cf RS |
11896 | case OPTION_FIX_VR4130: |
11897 | mips_fix_vr4130 = 1; | |
11898 | break; | |
11899 | ||
11900 | case OPTION_NO_FIX_VR4130: | |
11901 | mips_fix_vr4130 = 0; | |
11902 | break; | |
11903 | ||
d954098f DD |
11904 | case OPTION_FIX_CN63XXP1: |
11905 | mips_fix_cn63xxp1 = TRUE; | |
11906 | break; | |
11907 | ||
11908 | case OPTION_NO_FIX_CN63XXP1: | |
11909 | mips_fix_cn63xxp1 = FALSE; | |
11910 | break; | |
11911 | ||
4a6a3df4 AO |
11912 | case OPTION_RELAX_BRANCH: |
11913 | mips_relax_branch = 1; | |
11914 | break; | |
11915 | ||
11916 | case OPTION_NO_RELAX_BRANCH: | |
11917 | mips_relax_branch = 0; | |
11918 | break; | |
11919 | ||
aa6975fb ILT |
11920 | case OPTION_MSHARED: |
11921 | mips_in_shared = TRUE; | |
11922 | break; | |
11923 | ||
11924 | case OPTION_MNO_SHARED: | |
11925 | mips_in_shared = FALSE; | |
11926 | break; | |
11927 | ||
aed1a261 RS |
11928 | case OPTION_MSYM32: |
11929 | mips_opts.sym32 = TRUE; | |
11930 | break; | |
11931 | ||
11932 | case OPTION_MNO_SYM32: | |
11933 | mips_opts.sym32 = FALSE; | |
11934 | break; | |
11935 | ||
0f074f60 | 11936 | #ifdef OBJ_ELF |
252b5132 RH |
11937 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11938 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11939 | intended to be compatible with Irix 5. */ | |
11940 | case OPTION_CALL_SHARED: | |
f43abd2b | 11941 | if (!IS_ELF) |
252b5132 RH |
11942 | { |
11943 | as_bad (_("-call_shared is supported only for ELF format")); | |
11944 | return 0; | |
11945 | } | |
11946 | mips_pic = SVR4_PIC; | |
143d77c5 | 11947 | mips_abicalls = TRUE; |
252b5132 RH |
11948 | break; |
11949 | ||
861fb55a DJ |
11950 | case OPTION_CALL_NONPIC: |
11951 | if (!IS_ELF) | |
11952 | { | |
11953 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11954 | return 0; | |
11955 | } | |
11956 | mips_pic = NO_PIC; | |
11957 | mips_abicalls = TRUE; | |
11958 | break; | |
11959 | ||
252b5132 | 11960 | case OPTION_NON_SHARED: |
f43abd2b | 11961 | if (!IS_ELF) |
252b5132 RH |
11962 | { |
11963 | as_bad (_("-non_shared is supported only for ELF format")); | |
11964 | return 0; | |
11965 | } | |
11966 | mips_pic = NO_PIC; | |
143d77c5 | 11967 | mips_abicalls = FALSE; |
252b5132 RH |
11968 | break; |
11969 | ||
44075ae2 TS |
11970 | /* The -xgot option tells the assembler to use 32 bit offsets |
11971 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11972 | compatibility. */ |
11973 | case OPTION_XGOT: | |
11974 | mips_big_got = 1; | |
11975 | break; | |
0f074f60 | 11976 | #endif /* OBJ_ELF */ |
252b5132 RH |
11977 | |
11978 | case 'G': | |
6caf9ef4 TS |
11979 | g_switch_value = atoi (arg); |
11980 | g_switch_seen = 1; | |
252b5132 RH |
11981 | break; |
11982 | ||
34ba82a8 TS |
11983 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11984 | and -mabi=64. */ | |
252b5132 | 11985 | case OPTION_32: |
23fce1e3 NC |
11986 | if (IS_ELF) |
11987 | mips_abi = O32_ABI; | |
11988 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11989 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11990 | break; |
11991 | ||
23fce1e3 | 11992 | #ifdef OBJ_ELF |
e013f690 | 11993 | case OPTION_N32: |
f43abd2b | 11994 | if (!IS_ELF) |
34ba82a8 TS |
11995 | { |
11996 | as_bad (_("-n32 is supported for ELF format only")); | |
11997 | return 0; | |
11998 | } | |
316f5878 | 11999 | mips_abi = N32_ABI; |
e013f690 | 12000 | break; |
252b5132 | 12001 | |
e013f690 | 12002 | case OPTION_64: |
f43abd2b | 12003 | if (!IS_ELF) |
34ba82a8 TS |
12004 | { |
12005 | as_bad (_("-64 is supported for ELF format only")); | |
12006 | return 0; | |
12007 | } | |
316f5878 | 12008 | mips_abi = N64_ABI; |
f43abd2b | 12009 | if (!support_64bit_objects()) |
e013f690 | 12010 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 12011 | break; |
ae948b86 | 12012 | #endif /* OBJ_ELF */ |
252b5132 | 12013 | |
c97ef257 | 12014 | case OPTION_GP32: |
a325df1d | 12015 | file_mips_gp32 = 1; |
c97ef257 AH |
12016 | break; |
12017 | ||
12018 | case OPTION_GP64: | |
a325df1d | 12019 | file_mips_gp32 = 0; |
c97ef257 | 12020 | break; |
252b5132 | 12021 | |
ca4e0257 | 12022 | case OPTION_FP32: |
a325df1d | 12023 | file_mips_fp32 = 1; |
316f5878 RS |
12024 | break; |
12025 | ||
12026 | case OPTION_FP64: | |
12027 | file_mips_fp32 = 0; | |
ca4e0257 RS |
12028 | break; |
12029 | ||
037b32b9 AN |
12030 | case OPTION_SINGLE_FLOAT: |
12031 | file_mips_single_float = 1; | |
12032 | break; | |
12033 | ||
12034 | case OPTION_DOUBLE_FLOAT: | |
12035 | file_mips_single_float = 0; | |
12036 | break; | |
12037 | ||
12038 | case OPTION_SOFT_FLOAT: | |
12039 | file_mips_soft_float = 1; | |
12040 | break; | |
12041 | ||
12042 | case OPTION_HARD_FLOAT: | |
12043 | file_mips_soft_float = 0; | |
12044 | break; | |
12045 | ||
ae948b86 | 12046 | #ifdef OBJ_ELF |
252b5132 | 12047 | case OPTION_MABI: |
f43abd2b | 12048 | if (!IS_ELF) |
34ba82a8 TS |
12049 | { |
12050 | as_bad (_("-mabi is supported for ELF format only")); | |
12051 | return 0; | |
12052 | } | |
e013f690 | 12053 | if (strcmp (arg, "32") == 0) |
316f5878 | 12054 | mips_abi = O32_ABI; |
e013f690 | 12055 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 12056 | mips_abi = O64_ABI; |
e013f690 | 12057 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 12058 | mips_abi = N32_ABI; |
e013f690 TS |
12059 | else if (strcmp (arg, "64") == 0) |
12060 | { | |
316f5878 | 12061 | mips_abi = N64_ABI; |
e013f690 TS |
12062 | if (! support_64bit_objects()) |
12063 | as_fatal (_("No compiled in support for 64 bit object file " | |
12064 | "format")); | |
12065 | } | |
12066 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 12067 | mips_abi = EABI_ABI; |
e013f690 | 12068 | else |
da0e507f TS |
12069 | { |
12070 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
12071 | return 0; | |
12072 | } | |
252b5132 | 12073 | break; |
e013f690 | 12074 | #endif /* OBJ_ELF */ |
252b5132 | 12075 | |
6b76fefe | 12076 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 12077 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
12078 | break; |
12079 | ||
9ee72ff1 | 12080 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 12081 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
12082 | break; |
12083 | ||
ecb4347a DJ |
12084 | #ifdef OBJ_ELF |
12085 | case OPTION_MDEBUG: | |
b34976b6 | 12086 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
12087 | break; |
12088 | ||
12089 | case OPTION_NO_MDEBUG: | |
b34976b6 | 12090 | mips_flag_mdebug = FALSE; |
ecb4347a | 12091 | break; |
dcd410fe RO |
12092 | |
12093 | case OPTION_PDR: | |
12094 | mips_flag_pdr = TRUE; | |
12095 | break; | |
12096 | ||
12097 | case OPTION_NO_PDR: | |
12098 | mips_flag_pdr = FALSE; | |
12099 | break; | |
0a44bf69 RS |
12100 | |
12101 | case OPTION_MVXWORKS_PIC: | |
12102 | mips_pic = VXWORKS_PIC; | |
12103 | break; | |
ecb4347a DJ |
12104 | #endif /* OBJ_ELF */ |
12105 | ||
252b5132 RH |
12106 | default: |
12107 | return 0; | |
12108 | } | |
12109 | ||
c67a084a NC |
12110 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
12111 | ||
252b5132 RH |
12112 | return 1; |
12113 | } | |
316f5878 RS |
12114 | \f |
12115 | /* Set up globals to generate code for the ISA or processor | |
12116 | described by INFO. */ | |
252b5132 | 12117 | |
252b5132 | 12118 | static void |
17a2f251 | 12119 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 12120 | { |
316f5878 | 12121 | if (info != 0) |
252b5132 | 12122 | { |
fef14a42 TS |
12123 | file_mips_arch = info->cpu; |
12124 | mips_opts.arch = info->cpu; | |
316f5878 | 12125 | mips_opts.isa = info->isa; |
252b5132 | 12126 | } |
252b5132 RH |
12127 | } |
12128 | ||
252b5132 | 12129 | |
316f5878 | 12130 | /* Likewise for tuning. */ |
252b5132 | 12131 | |
316f5878 | 12132 | static void |
17a2f251 | 12133 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
12134 | { |
12135 | if (info != 0) | |
fef14a42 | 12136 | mips_tune = info->cpu; |
316f5878 | 12137 | } |
80cc45a5 | 12138 | |
34ba82a8 | 12139 | |
252b5132 | 12140 | void |
17a2f251 | 12141 | mips_after_parse_args (void) |
e9670677 | 12142 | { |
fef14a42 TS |
12143 | const struct mips_cpu_info *arch_info = 0; |
12144 | const struct mips_cpu_info *tune_info = 0; | |
12145 | ||
e9670677 | 12146 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 12147 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 12148 | { |
6caf9ef4 | 12149 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
12150 | as_bad (_("-G not supported in this configuration.")); |
12151 | g_switch_value = 0; | |
12152 | } | |
12153 | ||
cac012d6 AO |
12154 | if (mips_abi == NO_ABI) |
12155 | mips_abi = MIPS_DEFAULT_ABI; | |
12156 | ||
22923709 RS |
12157 | /* The following code determines the architecture and register size. |
12158 | Similar code was added to GCC 3.3 (see override_options() in | |
12159 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
12160 | as much as possible. */ | |
e9670677 | 12161 | |
316f5878 | 12162 | if (mips_arch_string != 0) |
fef14a42 | 12163 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 12164 | |
316f5878 | 12165 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 12166 | { |
316f5878 | 12167 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 12168 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 12169 | the -march selection (if any). */ |
fef14a42 | 12170 | if (arch_info != 0) |
e9670677 | 12171 | { |
316f5878 RS |
12172 | /* -march takes precedence over -mipsN, since it is more descriptive. |
12173 | There's no harm in specifying both as long as the ISA levels | |
12174 | are the same. */ | |
fef14a42 | 12175 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
12176 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
12177 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 12178 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 12179 | } |
316f5878 | 12180 | else |
fef14a42 | 12181 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
12182 | } |
12183 | ||
fef14a42 TS |
12184 | if (arch_info == 0) |
12185 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 12186 | |
fef14a42 | 12187 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 12188 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
12189 | arch_info->name); |
12190 | ||
12191 | mips_set_architecture (arch_info); | |
12192 | ||
12193 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
12194 | if (mips_tune_string != 0) | |
12195 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 12196 | |
fef14a42 TS |
12197 | if (tune_info == 0) |
12198 | mips_set_tune (arch_info); | |
12199 | else | |
12200 | mips_set_tune (tune_info); | |
e9670677 | 12201 | |
316f5878 | 12202 | if (file_mips_gp32 >= 0) |
e9670677 | 12203 | { |
316f5878 RS |
12204 | /* The user specified the size of the integer registers. Make sure |
12205 | it agrees with the ABI and ISA. */ | |
12206 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12207 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12208 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12209 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12210 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12211 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12212 | } |
12213 | else | |
12214 | { | |
316f5878 RS |
12215 | /* Infer the integer register size from the ABI and processor. |
12216 | Restrict ourselves to 32-bit registers if that's all the | |
12217 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12218 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12219 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12220 | } |
12221 | ||
ad3fea08 TS |
12222 | switch (file_mips_fp32) |
12223 | { | |
12224 | default: | |
12225 | case -1: | |
12226 | /* No user specified float register size. | |
12227 | ??? GAS treats single-float processors as though they had 64-bit | |
12228 | float registers (although it complains when double-precision | |
12229 | instructions are used). As things stand, saying they have 32-bit | |
12230 | registers would lead to spurious "register must be even" messages. | |
12231 | So here we assume float registers are never smaller than the | |
12232 | integer ones. */ | |
12233 | if (file_mips_gp32 == 0) | |
12234 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12235 | file_mips_fp32 = 0; | |
12236 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12237 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12238 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12239 | file_mips_fp32 = 0; | |
12240 | else | |
12241 | /* 32-bit float registers. */ | |
12242 | file_mips_fp32 = 1; | |
12243 | break; | |
12244 | ||
12245 | /* The user specified the size of the float registers. Check if it | |
12246 | agrees with the ABI and ISA. */ | |
12247 | case 0: | |
12248 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12249 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12250 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12251 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12252 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12253 | break; | |
12254 | case 1: | |
12255 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12256 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12257 | break; | |
12258 | } | |
e9670677 | 12259 | |
316f5878 | 12260 | /* End of GCC-shared inference code. */ |
e9670677 | 12261 | |
17a2f251 TS |
12262 | /* This flag is set when we have a 64-bit capable CPU but use only |
12263 | 32-bit wide registers. Note that EABI does not use it. */ | |
12264 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12265 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12266 | || mips_abi == O32_ABI)) | |
316f5878 | 12267 | mips_32bitmode = 1; |
e9670677 MR |
12268 | |
12269 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12270 | as_bad (_("trap exception not supported at ISA 1")); | |
12271 | ||
e9670677 MR |
12272 | /* If the selected architecture includes support for ASEs, enable |
12273 | generation of code for them. */ | |
a4672219 | 12274 | if (mips_opts.mips16 == -1) |
fef14a42 | 12275 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12276 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12277 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12278 | && file_mips_fp32 == 0) ? 1 : 0; |
12279 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12280 | as_bad (_("-mfp32 used with -mips3d")); | |
12281 | ||
ffdefa66 | 12282 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12283 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12284 | && file_mips_fp32 == 0) ? 1 : 0; |
12285 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12286 | as_bad (_("-mfp32 used with -mdmx")); | |
12287 | ||
12288 | if (mips_opts.ase_smartmips == -1) | |
12289 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12290 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12291 | as_warn (_("%s ISA does not support SmartMIPS"), |
12292 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12293 | |
74cd071d | 12294 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12295 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12296 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12297 | as_warn (_("%s ISA does not support DSP ASE"), |
12298 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12299 | |
8b082fb1 TS |
12300 | if (mips_opts.ase_dspr2 == -1) |
12301 | { | |
12302 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12303 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12304 | } | |
12305 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12306 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12307 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12308 | |
ef2e4d86 | 12309 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12310 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12311 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12312 | as_warn (_("%s ISA does not support MT ASE"), |
12313 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12314 | |
e9670677 | 12315 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
12316 | file_ase_mips3d = mips_opts.ase_mips3d; |
12317 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12318 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12319 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12320 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12321 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12322 | mips_opts.gp32 = file_mips_gp32; |
12323 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12324 | mips_opts.soft_float = file_mips_soft_float; |
12325 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12326 | |
ecb4347a DJ |
12327 | if (mips_flag_mdebug < 0) |
12328 | { | |
12329 | #ifdef OBJ_MAYBE_ECOFF | |
12330 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12331 | mips_flag_mdebug = 1; | |
12332 | else | |
12333 | #endif /* OBJ_MAYBE_ECOFF */ | |
12334 | mips_flag_mdebug = 0; | |
12335 | } | |
e9670677 MR |
12336 | } |
12337 | \f | |
12338 | void | |
17a2f251 | 12339 | mips_init_after_args (void) |
252b5132 RH |
12340 | { |
12341 | /* initialize opcodes */ | |
12342 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12343 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12344 | } |
12345 | ||
12346 | long | |
17a2f251 | 12347 | md_pcrel_from (fixS *fixP) |
252b5132 | 12348 | { |
a7ebbfdf TS |
12349 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12350 | switch (fixP->fx_r_type) | |
12351 | { | |
12352 | case BFD_RELOC_16_PCREL_S2: | |
12353 | case BFD_RELOC_MIPS_JMP: | |
12354 | /* Return the address of the delay slot. */ | |
12355 | return addr + 4; | |
12356 | default: | |
58ea3d6a | 12357 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12358 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12359 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12360 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12361 | return addr; |
12362 | } | |
252b5132 RH |
12363 | } |
12364 | ||
252b5132 RH |
12365 | /* This is called before the symbol table is processed. In order to |
12366 | work with gcc when using mips-tfile, we must keep all local labels. | |
12367 | However, in other cases, we want to discard them. If we were | |
12368 | called with -g, but we didn't see any debugging information, it may | |
12369 | mean that gcc is smuggling debugging information through to | |
12370 | mips-tfile, in which case we must generate all local labels. */ | |
12371 | ||
12372 | void | |
17a2f251 | 12373 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12374 | { |
12375 | #ifndef NO_ECOFF_DEBUGGING | |
12376 | if (ECOFF_DEBUGGING | |
12377 | && mips_debug != 0 | |
12378 | && ! ecoff_debugging_seen) | |
12379 | flag_keep_locals = 1; | |
12380 | #endif | |
12381 | } | |
12382 | ||
3b91255e | 12383 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12384 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12385 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12386 | relocation operators. | |
12387 | ||
12388 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12389 | expression if: | |
12390 | ||
12391 | (a) it refers to the same symbol; and | |
12392 | (b) the offset applied in the %lo() expression is no lower than | |
12393 | the offset applied in the %got() or %hi(). | |
12394 | ||
12395 | (b) allows us to cope with code like: | |
12396 | ||
12397 | lui $4,%hi(foo) | |
12398 | lh $4,%lo(foo+2)($4) | |
12399 | ||
12400 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12401 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12402 | the high 16 bits. | |
12403 | ||
12404 | When several %lo()s match a particular %got() or %hi(), we use the | |
12405 | following rules to distinguish them: | |
12406 | ||
12407 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12408 | higher offsets. | |
12409 | ||
12410 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12411 | that already have a matching %got() or %hi(). | |
12412 | ||
12413 | (3) later %lo()s are better than earlier %lo()s. | |
12414 | ||
12415 | These rules are applied in order. | |
12416 | ||
12417 | (1) means, among other things, that %lo()s with identical offsets are | |
12418 | chosen if they exist. | |
12419 | ||
12420 | (2) means that we won't associate several high-part relocations with | |
12421 | the same low-part relocation unless there's no alternative. Having | |
12422 | several high parts for the same low part is a GNU extension; this rule | |
12423 | allows careful users to avoid it. | |
12424 | ||
12425 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12426 | with the last high-part relocation being at the front of the list. | |
12427 | It therefore makes sense to choose the last matching low-part | |
12428 | relocation, all other things being equal. It's also easier | |
12429 | to code that way. */ | |
252b5132 RH |
12430 | |
12431 | void | |
17a2f251 | 12432 | mips_frob_file (void) |
252b5132 RH |
12433 | { |
12434 | struct mips_hi_fixup *l; | |
35903be0 | 12435 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12436 | |
12437 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12438 | { | |
12439 | segment_info_type *seginfo; | |
3b91255e RS |
12440 | bfd_boolean matched_lo_p; |
12441 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12442 | |
9c2799c2 | 12443 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12444 | |
5919d012 RS |
12445 | /* If a GOT16 relocation turns out to be against a global symbol, |
12446 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12447 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12448 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12449 | continue; | |
12450 | ||
12451 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12452 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12453 | continue; |
12454 | ||
252b5132 | 12455 | seginfo = seg_info (l->seg); |
252b5132 | 12456 | |
3b91255e RS |
12457 | /* Set HI_POS to the position of this relocation in the chain. |
12458 | Set LO_POS to the position of the chosen low-part relocation. | |
12459 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12460 | relocation that matches an immediately-preceding high-part | |
12461 | relocation. */ | |
12462 | hi_pos = NULL; | |
12463 | lo_pos = NULL; | |
12464 | matched_lo_p = FALSE; | |
738e5348 | 12465 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12466 | |
3b91255e RS |
12467 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12468 | { | |
12469 | if (*pos == l->fixp) | |
12470 | hi_pos = pos; | |
12471 | ||
35903be0 | 12472 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12473 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12474 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12475 | && (lo_pos == NULL | |
12476 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12477 | || (!matched_lo_p | |
12478 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12479 | lo_pos = pos; | |
12480 | ||
12481 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12482 | && fixup_has_matching_lo_p (*pos)); | |
12483 | } | |
12484 | ||
12485 | /* If we found a match, remove the high-part relocation from its | |
12486 | current position and insert it before the low-part relocation. | |
12487 | Make the offsets match so that fixup_has_matching_lo_p() | |
12488 | will return true. | |
12489 | ||
12490 | We don't warn about unmatched high-part relocations since some | |
12491 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12492 | instructions. */ | |
12493 | if (lo_pos != NULL) | |
12494 | { | |
12495 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12496 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12497 | { |
3b91255e RS |
12498 | *hi_pos = l->fixp->fx_next; |
12499 | l->fixp->fx_next = *lo_pos; | |
12500 | *lo_pos = l->fixp; | |
252b5132 | 12501 | } |
252b5132 RH |
12502 | } |
12503 | } | |
12504 | } | |
12505 | ||
3e722fb5 | 12506 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12507 | We have to prevent gas from dropping them. */ |
252b5132 | 12508 | |
252b5132 | 12509 | int |
17a2f251 | 12510 | mips_force_relocation (fixS *fixp) |
252b5132 | 12511 | { |
ae6063d4 | 12512 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12513 | return 1; |
12514 | ||
f6688943 TS |
12515 | if (HAVE_NEWABI |
12516 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12517 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12518 | || hi16_reloc_p (fixp->fx_r_type) |
12519 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12520 | return 1; |
12521 | ||
3e722fb5 | 12522 | return 0; |
252b5132 RH |
12523 | } |
12524 | ||
12525 | /* Apply a fixup to the object file. */ | |
12526 | ||
94f592af | 12527 | void |
55cf6793 | 12528 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12529 | { |
874e8986 | 12530 | bfd_byte *buf; |
98aa84af | 12531 | long insn; |
a7ebbfdf | 12532 | reloc_howto_type *howto; |
252b5132 | 12533 | |
a7ebbfdf TS |
12534 | /* We ignore generic BFD relocations we don't know about. */ |
12535 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12536 | if (! howto) | |
12537 | return; | |
65551fa4 | 12538 | |
9c2799c2 | 12539 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12540 | || fixP->fx_r_type == BFD_RELOC_16 |
12541 | || fixP->fx_r_type == BFD_RELOC_64 | |
12542 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12543 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12544 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12545 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12546 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12547 | |
a7ebbfdf | 12548 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12549 | |
9c2799c2 | 12550 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12551 | |
12552 | /* Don't treat parts of a composite relocation as done. There are two | |
12553 | reasons for this: | |
12554 | ||
12555 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12556 | should nevertheless be emitted if the first part is. | |
12557 | ||
12558 | (2) In normal usage, composite relocations are never assembly-time | |
12559 | constants. The easiest way of dealing with the pathological | |
12560 | exceptions is to generate a relocation against STN_UNDEF and | |
12561 | leave everything up to the linker. */ | |
3994f87e | 12562 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12563 | fixP->fx_done = 1; |
12564 | ||
12565 | switch (fixP->fx_r_type) | |
12566 | { | |
3f98094e DJ |
12567 | case BFD_RELOC_MIPS_TLS_GD: |
12568 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12569 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12570 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12571 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12572 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12573 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12574 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12575 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12576 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12577 | /* fall through */ | |
12578 | ||
252b5132 | 12579 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12580 | case BFD_RELOC_MIPS_SHIFT5: |
12581 | case BFD_RELOC_MIPS_SHIFT6: | |
12582 | case BFD_RELOC_MIPS_GOT_DISP: | |
12583 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12584 | case BFD_RELOC_MIPS_GOT_OFST: | |
12585 | case BFD_RELOC_MIPS_SUB: | |
12586 | case BFD_RELOC_MIPS_INSERT_A: | |
12587 | case BFD_RELOC_MIPS_INSERT_B: | |
12588 | case BFD_RELOC_MIPS_DELETE: | |
12589 | case BFD_RELOC_MIPS_HIGHEST: | |
12590 | case BFD_RELOC_MIPS_HIGHER: | |
12591 | case BFD_RELOC_MIPS_SCN_DISP: | |
12592 | case BFD_RELOC_MIPS_REL16: | |
12593 | case BFD_RELOC_MIPS_RELGOT: | |
12594 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12595 | case BFD_RELOC_HI16: |
12596 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12597 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12598 | case BFD_RELOC_MIPS_LITERAL: |
12599 | case BFD_RELOC_MIPS_CALL16: | |
12600 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12601 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12602 | case BFD_RELOC_MIPS_GOT_HI16: |
12603 | case BFD_RELOC_MIPS_GOT_LO16: | |
12604 | case BFD_RELOC_MIPS_CALL_HI16: | |
12605 | case BFD_RELOC_MIPS_CALL_LO16: | |
12606 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12607 | case BFD_RELOC_MIPS16_GOT16: |
12608 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12609 | case BFD_RELOC_MIPS16_HI16: |
12610 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12611 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12612 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12613 | break; |
12614 | ||
252b5132 RH |
12615 | case BFD_RELOC_64: |
12616 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12617 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12618 | if (fixP->fx_done) |
252b5132 RH |
12619 | { |
12620 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12621 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12622 | else |
12623 | { | |
a7ebbfdf | 12624 | valueT hiv; |
252b5132 | 12625 | |
a7ebbfdf | 12626 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12627 | hiv = 0xffffffff; |
12628 | else | |
12629 | hiv = 0; | |
b215186b | 12630 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12631 | *valP, 4); |
b215186b | 12632 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12633 | hiv, 4); |
252b5132 RH |
12634 | } |
12635 | } | |
12636 | break; | |
12637 | ||
056350c6 | 12638 | case BFD_RELOC_RVA: |
252b5132 | 12639 | case BFD_RELOC_32: |
252b5132 RH |
12640 | case BFD_RELOC_16: |
12641 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12642 | value now. This can happen if we have a .word which is not |
12643 | resolved when it appears but is later defined. */ | |
252b5132 | 12644 | if (fixP->fx_done) |
54f4ddb3 | 12645 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12646 | break; |
12647 | ||
12648 | case BFD_RELOC_LO16: | |
d6f16593 | 12649 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12650 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12651 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12652 | /* When handling an embedded PIC switch statement, we can wind |
12653 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12654 | if (fixP->fx_done) | |
12655 | { | |
a7ebbfdf | 12656 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12657 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12658 | _("relocation overflow")); | |
252b5132 RH |
12659 | if (target_big_endian) |
12660 | buf += 2; | |
2132e3a3 | 12661 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12662 | } |
12663 | break; | |
12664 | ||
12665 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12666 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12667 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12668 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12669 | |
54f4ddb3 TS |
12670 | /* We need to save the bits in the instruction since fixup_segment() |
12671 | might be deleting the relocation entry (i.e., a branch within | |
12672 | the current segment). */ | |
a7ebbfdf | 12673 | if (! fixP->fx_done) |
bb2d6cd7 | 12674 | break; |
252b5132 | 12675 | |
54f4ddb3 | 12676 | /* Update old instruction data. */ |
252b5132 RH |
12677 | if (target_big_endian) |
12678 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12679 | else | |
12680 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12681 | ||
a7ebbfdf TS |
12682 | if (*valP + 0x20000 <= 0x3ffff) |
12683 | { | |
12684 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12685 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12686 | } |
12687 | else if (mips_pic == NO_PIC | |
12688 | && fixP->fx_done | |
12689 | && fixP->fx_frag->fr_address >= text_section->vma | |
12690 | && (fixP->fx_frag->fr_address | |
587aac4e | 12691 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12692 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12693 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12694 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12695 | { |
12696 | /* The branch offset is too large. If this is an | |
12697 | unconditional branch, and we are not generating PIC code, | |
12698 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12699 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12700 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12701 | else |
a7ebbfdf TS |
12702 | insn = 0x08000000; /* j */ |
12703 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12704 | fixP->fx_done = 0; | |
12705 | fixP->fx_addsy = section_symbol (text_section); | |
12706 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12707 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12708 | } |
12709 | else | |
12710 | { | |
12711 | /* If we got here, we have branch-relaxation disabled, | |
12712 | and there's nothing we can do to fix this instruction | |
12713 | without turning it into a longer sequence. */ | |
12714 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12715 | _("Branch out of range")); | |
252b5132 | 12716 | } |
252b5132 RH |
12717 | break; |
12718 | ||
12719 | case BFD_RELOC_VTABLE_INHERIT: | |
12720 | fixP->fx_done = 0; | |
12721 | if (fixP->fx_addsy | |
12722 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12723 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12724 | S_SET_WEAK (fixP->fx_addsy); | |
12725 | break; | |
12726 | ||
12727 | case BFD_RELOC_VTABLE_ENTRY: | |
12728 | fixP->fx_done = 0; | |
12729 | break; | |
12730 | ||
12731 | default: | |
12732 | internalError (); | |
12733 | } | |
a7ebbfdf TS |
12734 | |
12735 | /* Remember value for tc_gen_reloc. */ | |
12736 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12737 | } |
12738 | ||
252b5132 | 12739 | static symbolS * |
17a2f251 | 12740 | get_symbol (void) |
252b5132 RH |
12741 | { |
12742 | int c; | |
12743 | char *name; | |
12744 | symbolS *p; | |
12745 | ||
12746 | name = input_line_pointer; | |
12747 | c = get_symbol_end (); | |
12748 | p = (symbolS *) symbol_find_or_make (name); | |
12749 | *input_line_pointer = c; | |
12750 | return p; | |
12751 | } | |
12752 | ||
742a56fe RS |
12753 | /* Align the current frag to a given power of two. If a particular |
12754 | fill byte should be used, FILL points to an integer that contains | |
12755 | that byte, otherwise FILL is null. | |
12756 | ||
12757 | The MIPS assembler also automatically adjusts any preceding | |
12758 | label. */ | |
252b5132 RH |
12759 | |
12760 | static void | |
742a56fe | 12761 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12762 | { |
7d10b47d | 12763 | mips_emit_delays (); |
742a56fe RS |
12764 | mips_record_mips16_mode (); |
12765 | if (fill == NULL && subseg_text_p (now_seg)) | |
12766 | frag_align_code (to, 0); | |
12767 | else | |
12768 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12769 | record_alignment (now_seg, to); |
12770 | if (label != NULL) | |
12771 | { | |
9c2799c2 | 12772 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12773 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12774 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12775 | } | |
12776 | } | |
12777 | ||
12778 | /* Align to a given power of two. .align 0 turns off the automatic | |
12779 | alignment used by the data creating pseudo-ops. */ | |
12780 | ||
12781 | static void | |
17a2f251 | 12782 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12783 | { |
742a56fe | 12784 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12785 | long max_alignment = 28; |
252b5132 | 12786 | |
54f4ddb3 | 12787 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12788 | to the aligned address. |
54f4ddb3 | 12789 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12790 | a .align pseudo instruction. |
54f4ddb3 | 12791 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12792 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12793 | We don't. */ |
252b5132 RH |
12794 | |
12795 | temp = get_absolute_expression (); | |
12796 | if (temp > max_alignment) | |
12797 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12798 | else if (temp < 0) | |
12799 | { | |
12800 | as_warn (_("Alignment negative: 0 assumed.")); | |
12801 | temp = 0; | |
12802 | } | |
12803 | if (*input_line_pointer == ',') | |
12804 | { | |
f9419b05 | 12805 | ++input_line_pointer; |
742a56fe RS |
12806 | fill_value = get_absolute_expression (); |
12807 | fill_ptr = &fill_value; | |
252b5132 RH |
12808 | } |
12809 | else | |
742a56fe | 12810 | fill_ptr = 0; |
252b5132 RH |
12811 | if (temp) |
12812 | { | |
a8dbcb85 TS |
12813 | segment_info_type *si = seg_info (now_seg); |
12814 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12815 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12816 | auto_align = 1; |
742a56fe | 12817 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12818 | } |
12819 | else | |
12820 | { | |
12821 | auto_align = 0; | |
12822 | } | |
12823 | ||
12824 | demand_empty_rest_of_line (); | |
12825 | } | |
12826 | ||
252b5132 | 12827 | static void |
17a2f251 | 12828 | s_change_sec (int sec) |
252b5132 RH |
12829 | { |
12830 | segT seg; | |
12831 | ||
252b5132 RH |
12832 | #ifdef OBJ_ELF |
12833 | /* The ELF backend needs to know that we are changing sections, so | |
12834 | that .previous works correctly. We could do something like check | |
b6ff326e | 12835 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12836 | as it would not be appropriate to use it in the section changing |
12837 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12838 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12839 | if (IS_ELF) |
12840 | obj_elf_section_change_hook (); | |
252b5132 RH |
12841 | #endif |
12842 | ||
7d10b47d | 12843 | mips_emit_delays (); |
6a32d874 | 12844 | |
252b5132 RH |
12845 | switch (sec) |
12846 | { | |
12847 | case 't': | |
12848 | s_text (0); | |
12849 | break; | |
12850 | case 'd': | |
12851 | s_data (0); | |
12852 | break; | |
12853 | case 'b': | |
12854 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12855 | demand_empty_rest_of_line (); | |
12856 | break; | |
12857 | ||
12858 | case 'r': | |
4d0d148d TS |
12859 | seg = subseg_new (RDATA_SECTION_NAME, |
12860 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12861 | if (IS_ELF) |
252b5132 | 12862 | { |
4d0d148d TS |
12863 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12864 | | SEC_READONLY | SEC_RELOC | |
12865 | | SEC_DATA)); | |
c41e87e3 | 12866 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12867 | record_alignment (seg, 4); |
252b5132 | 12868 | } |
4d0d148d | 12869 | demand_empty_rest_of_line (); |
252b5132 RH |
12870 | break; |
12871 | ||
12872 | case 's': | |
4d0d148d | 12873 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12874 | if (IS_ELF) |
252b5132 | 12875 | { |
4d0d148d TS |
12876 | bfd_set_section_flags (stdoutput, seg, |
12877 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12878 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12879 | record_alignment (seg, 4); |
252b5132 | 12880 | } |
4d0d148d TS |
12881 | demand_empty_rest_of_line (); |
12882 | break; | |
998b3c36 MR |
12883 | |
12884 | case 'B': | |
12885 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12886 | if (IS_ELF) | |
12887 | { | |
12888 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12889 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12890 | record_alignment (seg, 4); | |
12891 | } | |
12892 | demand_empty_rest_of_line (); | |
12893 | break; | |
252b5132 RH |
12894 | } |
12895 | ||
12896 | auto_align = 1; | |
12897 | } | |
b34976b6 | 12898 | |
cca86cc8 | 12899 | void |
17a2f251 | 12900 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12901 | { |
7ed4a06a | 12902 | #ifdef OBJ_ELF |
cca86cc8 SC |
12903 | char *section_name; |
12904 | char c; | |
684022ea | 12905 | char next_c = 0; |
cca86cc8 SC |
12906 | int section_type; |
12907 | int section_flag; | |
12908 | int section_entry_size; | |
12909 | int section_alignment; | |
b34976b6 | 12910 | |
f43abd2b | 12911 | if (!IS_ELF) |
7ed4a06a TS |
12912 | return; |
12913 | ||
cca86cc8 SC |
12914 | section_name = input_line_pointer; |
12915 | c = get_symbol_end (); | |
a816d1ed AO |
12916 | if (c) |
12917 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12918 | |
4cf0dd0d TS |
12919 | /* Do we have .section Name<,"flags">? */ |
12920 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12921 | { |
4cf0dd0d TS |
12922 | /* just after name is now '\0'. */ |
12923 | *input_line_pointer = c; | |
cca86cc8 SC |
12924 | input_line_pointer = section_name; |
12925 | obj_elf_section (ignore); | |
12926 | return; | |
12927 | } | |
12928 | input_line_pointer++; | |
12929 | ||
12930 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12931 | if (c == ',') | |
12932 | section_type = get_absolute_expression (); | |
12933 | else | |
12934 | section_type = 0; | |
12935 | if (*input_line_pointer++ == ',') | |
12936 | section_flag = get_absolute_expression (); | |
12937 | else | |
12938 | section_flag = 0; | |
12939 | if (*input_line_pointer++ == ',') | |
12940 | section_entry_size = get_absolute_expression (); | |
12941 | else | |
12942 | section_entry_size = 0; | |
12943 | if (*input_line_pointer++ == ',') | |
12944 | section_alignment = get_absolute_expression (); | |
12945 | else | |
12946 | section_alignment = 0; | |
87975d2a AM |
12947 | /* FIXME: really ignore? */ |
12948 | (void) section_alignment; | |
cca86cc8 | 12949 | |
a816d1ed AO |
12950 | section_name = xstrdup (section_name); |
12951 | ||
8ab8a5c8 RS |
12952 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12953 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12954 | traditionally had to fall back on the more common @progbits instead. | |
12955 | ||
12956 | There's nothing really harmful in this, since bfd will correct | |
12957 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12958 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12959 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12960 | ||
12961 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12962 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12963 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12964 | generic type-checking code. */ | |
12965 | if (section_type == SHT_MIPS_DWARF) | |
12966 | section_type = SHT_PROGBITS; | |
12967 | ||
cca86cc8 SC |
12968 | obj_elf_change_section (section_name, section_type, section_flag, |
12969 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12970 | |
12971 | if (now_seg->name != section_name) | |
12972 | free (section_name); | |
7ed4a06a | 12973 | #endif /* OBJ_ELF */ |
cca86cc8 | 12974 | } |
252b5132 RH |
12975 | |
12976 | void | |
17a2f251 | 12977 | mips_enable_auto_align (void) |
252b5132 RH |
12978 | { |
12979 | auto_align = 1; | |
12980 | } | |
12981 | ||
12982 | static void | |
17a2f251 | 12983 | s_cons (int log_size) |
252b5132 | 12984 | { |
a8dbcb85 TS |
12985 | segment_info_type *si = seg_info (now_seg); |
12986 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12987 | symbolS *label; |
12988 | ||
a8dbcb85 | 12989 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12990 | mips_emit_delays (); |
252b5132 RH |
12991 | if (log_size > 0 && auto_align) |
12992 | mips_align (log_size, 0, label); | |
252b5132 | 12993 | cons (1 << log_size); |
a1facbec | 12994 | mips_clear_insn_labels (); |
252b5132 RH |
12995 | } |
12996 | ||
12997 | static void | |
17a2f251 | 12998 | s_float_cons (int type) |
252b5132 | 12999 | { |
a8dbcb85 TS |
13000 | segment_info_type *si = seg_info (now_seg); |
13001 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
13002 | symbolS *label; |
13003 | ||
a8dbcb85 | 13004 | label = l != NULL ? l->label : NULL; |
252b5132 | 13005 | |
7d10b47d | 13006 | mips_emit_delays (); |
252b5132 RH |
13007 | |
13008 | if (auto_align) | |
49309057 ILT |
13009 | { |
13010 | if (type == 'd') | |
13011 | mips_align (3, 0, label); | |
13012 | else | |
13013 | mips_align (2, 0, label); | |
13014 | } | |
252b5132 | 13015 | |
252b5132 | 13016 | float_cons (type); |
a1facbec | 13017 | mips_clear_insn_labels (); |
252b5132 RH |
13018 | } |
13019 | ||
13020 | /* Handle .globl. We need to override it because on Irix 5 you are | |
13021 | permitted to say | |
13022 | .globl foo .text | |
13023 | where foo is an undefined symbol, to mean that foo should be | |
13024 | considered to be the address of a function. */ | |
13025 | ||
13026 | static void | |
17a2f251 | 13027 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13028 | { |
13029 | char *name; | |
13030 | int c; | |
13031 | symbolS *symbolP; | |
13032 | flagword flag; | |
13033 | ||
8a06b769 | 13034 | do |
252b5132 | 13035 | { |
8a06b769 | 13036 | name = input_line_pointer; |
252b5132 | 13037 | c = get_symbol_end (); |
8a06b769 TS |
13038 | symbolP = symbol_find_or_make (name); |
13039 | S_SET_EXTERNAL (symbolP); | |
13040 | ||
252b5132 | 13041 | *input_line_pointer = c; |
8a06b769 | 13042 | SKIP_WHITESPACE (); |
252b5132 | 13043 | |
8a06b769 TS |
13044 | /* On Irix 5, every global symbol that is not explicitly labelled as |
13045 | being a function is apparently labelled as being an object. */ | |
13046 | flag = BSF_OBJECT; | |
252b5132 | 13047 | |
8a06b769 TS |
13048 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
13049 | && (*input_line_pointer != ',')) | |
13050 | { | |
13051 | char *secname; | |
13052 | asection *sec; | |
13053 | ||
13054 | secname = input_line_pointer; | |
13055 | c = get_symbol_end (); | |
13056 | sec = bfd_get_section_by_name (stdoutput, secname); | |
13057 | if (sec == NULL) | |
13058 | as_bad (_("%s: no such section"), secname); | |
13059 | *input_line_pointer = c; | |
13060 | ||
13061 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
13062 | flag = BSF_FUNCTION; | |
13063 | } | |
13064 | ||
13065 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
13066 | ||
13067 | c = *input_line_pointer; | |
13068 | if (c == ',') | |
13069 | { | |
13070 | input_line_pointer++; | |
13071 | SKIP_WHITESPACE (); | |
13072 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
13073 | c = '\n'; | |
13074 | } | |
13075 | } | |
13076 | while (c == ','); | |
252b5132 | 13077 | |
252b5132 RH |
13078 | demand_empty_rest_of_line (); |
13079 | } | |
13080 | ||
13081 | static void | |
17a2f251 | 13082 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13083 | { |
13084 | char *opt; | |
13085 | char c; | |
13086 | ||
13087 | opt = input_line_pointer; | |
13088 | c = get_symbol_end (); | |
13089 | ||
13090 | if (*opt == 'O') | |
13091 | { | |
13092 | /* FIXME: What does this mean? */ | |
13093 | } | |
13094 | else if (strncmp (opt, "pic", 3) == 0) | |
13095 | { | |
13096 | int i; | |
13097 | ||
13098 | i = atoi (opt + 3); | |
13099 | if (i == 0) | |
13100 | mips_pic = NO_PIC; | |
13101 | else if (i == 2) | |
143d77c5 | 13102 | { |
252b5132 | 13103 | mips_pic = SVR4_PIC; |
143d77c5 EC |
13104 | mips_abicalls = TRUE; |
13105 | } | |
252b5132 RH |
13106 | else |
13107 | as_bad (_(".option pic%d not supported"), i); | |
13108 | ||
4d0d148d | 13109 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
13110 | { |
13111 | if (g_switch_seen && g_switch_value != 0) | |
13112 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13113 | g_switch_value = 0; | |
13114 | bfd_set_gp_size (stdoutput, 0); | |
13115 | } | |
13116 | } | |
13117 | else | |
13118 | as_warn (_("Unrecognized option \"%s\""), opt); | |
13119 | ||
13120 | *input_line_pointer = c; | |
13121 | demand_empty_rest_of_line (); | |
13122 | } | |
13123 | ||
13124 | /* This structure is used to hold a stack of .set values. */ | |
13125 | ||
e972090a NC |
13126 | struct mips_option_stack |
13127 | { | |
252b5132 RH |
13128 | struct mips_option_stack *next; |
13129 | struct mips_set_options options; | |
13130 | }; | |
13131 | ||
13132 | static struct mips_option_stack *mips_opts_stack; | |
13133 | ||
13134 | /* Handle the .set pseudo-op. */ | |
13135 | ||
13136 | static void | |
17a2f251 | 13137 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13138 | { |
13139 | char *name = input_line_pointer, ch; | |
13140 | ||
13141 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 13142 | ++input_line_pointer; |
252b5132 RH |
13143 | ch = *input_line_pointer; |
13144 | *input_line_pointer = '\0'; | |
13145 | ||
13146 | if (strcmp (name, "reorder") == 0) | |
13147 | { | |
7d10b47d RS |
13148 | if (mips_opts.noreorder) |
13149 | end_noreorder (); | |
252b5132 RH |
13150 | } |
13151 | else if (strcmp (name, "noreorder") == 0) | |
13152 | { | |
7d10b47d RS |
13153 | if (!mips_opts.noreorder) |
13154 | start_noreorder (); | |
252b5132 | 13155 | } |
741fe287 MR |
13156 | else if (strncmp (name, "at=", 3) == 0) |
13157 | { | |
13158 | char *s = name + 3; | |
13159 | ||
13160 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
13161 | as_bad (_("Unrecognized register name `%s'"), s); | |
13162 | } | |
252b5132 RH |
13163 | else if (strcmp (name, "at") == 0) |
13164 | { | |
741fe287 | 13165 | mips_opts.at = ATREG; |
252b5132 RH |
13166 | } |
13167 | else if (strcmp (name, "noat") == 0) | |
13168 | { | |
741fe287 | 13169 | mips_opts.at = ZERO; |
252b5132 RH |
13170 | } |
13171 | else if (strcmp (name, "macro") == 0) | |
13172 | { | |
13173 | mips_opts.warn_about_macros = 0; | |
13174 | } | |
13175 | else if (strcmp (name, "nomacro") == 0) | |
13176 | { | |
13177 | if (mips_opts.noreorder == 0) | |
13178 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
13179 | mips_opts.warn_about_macros = 1; | |
13180 | } | |
13181 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
13182 | { | |
13183 | mips_opts.nomove = 0; | |
13184 | } | |
13185 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
13186 | { | |
13187 | mips_opts.nomove = 1; | |
13188 | } | |
13189 | else if (strcmp (name, "bopt") == 0) | |
13190 | { | |
13191 | mips_opts.nobopt = 0; | |
13192 | } | |
13193 | else if (strcmp (name, "nobopt") == 0) | |
13194 | { | |
13195 | mips_opts.nobopt = 1; | |
13196 | } | |
ad3fea08 TS |
13197 | else if (strcmp (name, "gp=default") == 0) |
13198 | mips_opts.gp32 = file_mips_gp32; | |
13199 | else if (strcmp (name, "gp=32") == 0) | |
13200 | mips_opts.gp32 = 1; | |
13201 | else if (strcmp (name, "gp=64") == 0) | |
13202 | { | |
13203 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 13204 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
13205 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13206 | mips_opts.gp32 = 0; | |
13207 | } | |
13208 | else if (strcmp (name, "fp=default") == 0) | |
13209 | mips_opts.fp32 = file_mips_fp32; | |
13210 | else if (strcmp (name, "fp=32") == 0) | |
13211 | mips_opts.fp32 = 1; | |
13212 | else if (strcmp (name, "fp=64") == 0) | |
13213 | { | |
13214 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13215 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13216 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13217 | mips_opts.fp32 = 0; | |
13218 | } | |
037b32b9 AN |
13219 | else if (strcmp (name, "softfloat") == 0) |
13220 | mips_opts.soft_float = 1; | |
13221 | else if (strcmp (name, "hardfloat") == 0) | |
13222 | mips_opts.soft_float = 0; | |
13223 | else if (strcmp (name, "singlefloat") == 0) | |
13224 | mips_opts.single_float = 1; | |
13225 | else if (strcmp (name, "doublefloat") == 0) | |
13226 | mips_opts.single_float = 0; | |
252b5132 RH |
13227 | else if (strcmp (name, "mips16") == 0 |
13228 | || strcmp (name, "MIPS-16") == 0) | |
13229 | mips_opts.mips16 = 1; | |
13230 | else if (strcmp (name, "nomips16") == 0 | |
13231 | || strcmp (name, "noMIPS-16") == 0) | |
13232 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13233 | else if (strcmp (name, "smartmips") == 0) |
13234 | { | |
ad3fea08 | 13235 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13236 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13237 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13238 | mips_opts.ase_smartmips = 1; | |
13239 | } | |
13240 | else if (strcmp (name, "nosmartmips") == 0) | |
13241 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13242 | else if (strcmp (name, "mips3d") == 0) |
13243 | mips_opts.ase_mips3d = 1; | |
13244 | else if (strcmp (name, "nomips3d") == 0) | |
13245 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13246 | else if (strcmp (name, "mdmx") == 0) |
13247 | mips_opts.ase_mdmx = 1; | |
13248 | else if (strcmp (name, "nomdmx") == 0) | |
13249 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13250 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13251 | { |
13252 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13253 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13254 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13255 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13256 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13257 | } |
74cd071d | 13258 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13259 | { |
13260 | mips_opts.ase_dsp = 0; | |
13261 | mips_opts.ase_dspr2 = 0; | |
13262 | } | |
13263 | else if (strcmp (name, "dspr2") == 0) | |
13264 | { | |
13265 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13266 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13267 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13268 | mips_opts.ase_dspr2 = 1; | |
13269 | mips_opts.ase_dsp = 1; | |
13270 | } | |
13271 | else if (strcmp (name, "nodspr2") == 0) | |
13272 | { | |
13273 | mips_opts.ase_dspr2 = 0; | |
13274 | mips_opts.ase_dsp = 0; | |
13275 | } | |
ef2e4d86 | 13276 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13277 | { |
13278 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13279 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13280 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13281 | mips_opts.ase_mt = 1; | |
13282 | } | |
ef2e4d86 CF |
13283 | else if (strcmp (name, "nomt") == 0) |
13284 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13285 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13286 | { |
af7ee8bf | 13287 | int reset = 0; |
252b5132 | 13288 | |
1a2c1fad CD |
13289 | /* Permit the user to change the ISA and architecture on the fly. |
13290 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13291 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13292 | { |
13293 | reset = 1; | |
13294 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13295 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13296 | } |
13297 | else if (strncmp (name, "arch=", 5) == 0) | |
13298 | { | |
13299 | const struct mips_cpu_info *p; | |
13300 | ||
13301 | p = mips_parse_cpu("internal use", name + 5); | |
13302 | if (!p) | |
13303 | as_bad (_("unknown architecture %s"), name + 5); | |
13304 | else | |
13305 | { | |
13306 | mips_opts.arch = p->cpu; | |
13307 | mips_opts.isa = p->isa; | |
13308 | } | |
13309 | } | |
81a21e38 TS |
13310 | else if (strncmp (name, "mips", 4) == 0) |
13311 | { | |
13312 | const struct mips_cpu_info *p; | |
13313 | ||
13314 | p = mips_parse_cpu("internal use", name); | |
13315 | if (!p) | |
13316 | as_bad (_("unknown ISA level %s"), name + 4); | |
13317 | else | |
13318 | { | |
13319 | mips_opts.arch = p->cpu; | |
13320 | mips_opts.isa = p->isa; | |
13321 | } | |
13322 | } | |
af7ee8bf | 13323 | else |
81a21e38 | 13324 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13325 | |
13326 | switch (mips_opts.isa) | |
98d3f06f KH |
13327 | { |
13328 | case 0: | |
98d3f06f | 13329 | break; |
af7ee8bf CD |
13330 | case ISA_MIPS1: |
13331 | case ISA_MIPS2: | |
13332 | case ISA_MIPS32: | |
13333 | case ISA_MIPS32R2: | |
98d3f06f KH |
13334 | mips_opts.gp32 = 1; |
13335 | mips_opts.fp32 = 1; | |
13336 | break; | |
af7ee8bf CD |
13337 | case ISA_MIPS3: |
13338 | case ISA_MIPS4: | |
13339 | case ISA_MIPS5: | |
13340 | case ISA_MIPS64: | |
5f74bc13 | 13341 | case ISA_MIPS64R2: |
98d3f06f KH |
13342 | mips_opts.gp32 = 0; |
13343 | mips_opts.fp32 = 0; | |
13344 | break; | |
13345 | default: | |
13346 | as_bad (_("unknown ISA level %s"), name + 4); | |
13347 | break; | |
13348 | } | |
af7ee8bf | 13349 | if (reset) |
98d3f06f | 13350 | { |
af7ee8bf CD |
13351 | mips_opts.gp32 = file_mips_gp32; |
13352 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13353 | } |
252b5132 RH |
13354 | } |
13355 | else if (strcmp (name, "autoextend") == 0) | |
13356 | mips_opts.noautoextend = 0; | |
13357 | else if (strcmp (name, "noautoextend") == 0) | |
13358 | mips_opts.noautoextend = 1; | |
13359 | else if (strcmp (name, "push") == 0) | |
13360 | { | |
13361 | struct mips_option_stack *s; | |
13362 | ||
13363 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13364 | s->next = mips_opts_stack; | |
13365 | s->options = mips_opts; | |
13366 | mips_opts_stack = s; | |
13367 | } | |
13368 | else if (strcmp (name, "pop") == 0) | |
13369 | { | |
13370 | struct mips_option_stack *s; | |
13371 | ||
13372 | s = mips_opts_stack; | |
13373 | if (s == NULL) | |
13374 | as_bad (_(".set pop with no .set push")); | |
13375 | else | |
13376 | { | |
13377 | /* If we're changing the reorder mode we need to handle | |
13378 | delay slots correctly. */ | |
13379 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13380 | start_noreorder (); |
252b5132 | 13381 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13382 | end_noreorder (); |
252b5132 RH |
13383 | |
13384 | mips_opts = s->options; | |
13385 | mips_opts_stack = s->next; | |
13386 | free (s); | |
13387 | } | |
13388 | } | |
aed1a261 RS |
13389 | else if (strcmp (name, "sym32") == 0) |
13390 | mips_opts.sym32 = TRUE; | |
13391 | else if (strcmp (name, "nosym32") == 0) | |
13392 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13393 | else if (strchr (name, ',')) |
13394 | { | |
13395 | /* Generic ".set" directive; use the generic handler. */ | |
13396 | *input_line_pointer = ch; | |
13397 | input_line_pointer = name; | |
13398 | s_set (0); | |
13399 | return; | |
13400 | } | |
252b5132 RH |
13401 | else |
13402 | { | |
13403 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13404 | } | |
13405 | *input_line_pointer = ch; | |
13406 | demand_empty_rest_of_line (); | |
13407 | } | |
13408 | ||
13409 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13410 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13411 | ||
13412 | static void | |
17a2f251 | 13413 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13414 | { |
13415 | mips_pic = SVR4_PIC; | |
143d77c5 | 13416 | mips_abicalls = TRUE; |
4d0d148d TS |
13417 | |
13418 | if (g_switch_seen && g_switch_value != 0) | |
13419 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13420 | g_switch_value = 0; | |
13421 | ||
252b5132 RH |
13422 | bfd_set_gp_size (stdoutput, 0); |
13423 | demand_empty_rest_of_line (); | |
13424 | } | |
13425 | ||
13426 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13427 | PIC code. It sets the $gp register for the function based on the | |
13428 | function address, which is in the register named in the argument. | |
13429 | This uses a relocation against _gp_disp, which is handled specially | |
13430 | by the linker. The result is: | |
13431 | lui $gp,%hi(_gp_disp) | |
13432 | addiu $gp,$gp,%lo(_gp_disp) | |
13433 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13434 | The .cpload argument is normally $25 == $t9. |
13435 | ||
13436 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13437 | lui $gp,%hi(__gnu_local_gp) |
13438 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13439 | and the argument is ignored. This saves an instruction, but the |
13440 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13441 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13442 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13443 | |
13444 | static void | |
17a2f251 | 13445 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13446 | { |
13447 | expressionS ex; | |
aa6975fb ILT |
13448 | int reg; |
13449 | int in_shared; | |
252b5132 | 13450 | |
6478892d TS |
13451 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13452 | .cpload is ignored. */ | |
13453 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13454 | { |
13455 | s_ignore (0); | |
13456 | return; | |
13457 | } | |
13458 | ||
d3ecfc59 | 13459 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13460 | if (mips_opts.noreorder == 0) |
13461 | as_warn (_(".cpload not in noreorder section")); | |
13462 | ||
aa6975fb ILT |
13463 | reg = tc_get_register (0); |
13464 | ||
13465 | /* If we need to produce a 64-bit address, we are better off using | |
13466 | the default instruction sequence. */ | |
aed1a261 | 13467 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13468 | |
252b5132 | 13469 | ex.X_op = O_symbol; |
bbe506e8 TS |
13470 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13471 | "__gnu_local_gp"); | |
252b5132 RH |
13472 | ex.X_op_symbol = NULL; |
13473 | ex.X_add_number = 0; | |
13474 | ||
13475 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13476 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13477 | |
584892a6 | 13478 | macro_start (); |
67c0d1eb RS |
13479 | macro_build_lui (&ex, mips_gp_register); |
13480 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13481 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13482 | if (in_shared) |
13483 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13484 | mips_gp_register, reg); | |
584892a6 | 13485 | macro_end (); |
252b5132 RH |
13486 | |
13487 | demand_empty_rest_of_line (); | |
13488 | } | |
13489 | ||
6478892d TS |
13490 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13491 | .cpsetup $reg1, offset|$reg2, label | |
13492 | ||
13493 | If offset is given, this results in: | |
13494 | sd $gp, offset($sp) | |
956cd1d6 | 13495 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13496 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13497 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13498 | |
13499 | If $reg2 is given, this results in: | |
13500 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13501 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13502 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13503 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13504 | $reg1 is normally $25 == $t9. |
13505 | ||
13506 | The -mno-shared option replaces the last three instructions with | |
13507 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13508 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13509 | |
6478892d | 13510 | static void |
17a2f251 | 13511 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13512 | { |
13513 | expressionS ex_off; | |
13514 | expressionS ex_sym; | |
13515 | int reg1; | |
6478892d | 13516 | |
8586fc66 | 13517 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13518 | We also need NewABI support. */ |
13519 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13520 | { | |
13521 | s_ignore (0); | |
13522 | return; | |
13523 | } | |
13524 | ||
13525 | reg1 = tc_get_register (0); | |
13526 | SKIP_WHITESPACE (); | |
13527 | if (*input_line_pointer != ',') | |
13528 | { | |
13529 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13530 | return; | |
13531 | } | |
13532 | else | |
80245285 | 13533 | ++input_line_pointer; |
6478892d TS |
13534 | SKIP_WHITESPACE (); |
13535 | if (*input_line_pointer == '$') | |
80245285 TS |
13536 | { |
13537 | mips_cpreturn_register = tc_get_register (0); | |
13538 | mips_cpreturn_offset = -1; | |
13539 | } | |
6478892d | 13540 | else |
80245285 TS |
13541 | { |
13542 | mips_cpreturn_offset = get_absolute_expression (); | |
13543 | mips_cpreturn_register = -1; | |
13544 | } | |
6478892d TS |
13545 | SKIP_WHITESPACE (); |
13546 | if (*input_line_pointer != ',') | |
13547 | { | |
13548 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13549 | return; | |
13550 | } | |
13551 | else | |
f9419b05 | 13552 | ++input_line_pointer; |
6478892d | 13553 | SKIP_WHITESPACE (); |
f21f8242 | 13554 | expression (&ex_sym); |
6478892d | 13555 | |
584892a6 | 13556 | macro_start (); |
6478892d TS |
13557 | if (mips_cpreturn_register == -1) |
13558 | { | |
13559 | ex_off.X_op = O_constant; | |
13560 | ex_off.X_add_symbol = NULL; | |
13561 | ex_off.X_op_symbol = NULL; | |
13562 | ex_off.X_add_number = mips_cpreturn_offset; | |
13563 | ||
67c0d1eb | 13564 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13565 | BFD_RELOC_LO16, SP); |
6478892d TS |
13566 | } |
13567 | else | |
67c0d1eb | 13568 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13569 | mips_gp_register, 0); |
6478892d | 13570 | |
aed1a261 | 13571 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13572 | { |
13573 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13574 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13575 | BFD_RELOC_HI16_S); | |
13576 | ||
13577 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13578 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13579 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13580 | ||
13581 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13582 | mips_gp_register, reg1); | |
13583 | } | |
13584 | else | |
13585 | { | |
13586 | expressionS ex; | |
13587 | ||
13588 | ex.X_op = O_symbol; | |
4184909a | 13589 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13590 | ex.X_op_symbol = NULL; |
13591 | ex.X_add_number = 0; | |
6e1304d8 | 13592 | |
aa6975fb ILT |
13593 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13594 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13595 | ||
13596 | macro_build_lui (&ex, mips_gp_register); | |
13597 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13598 | mips_gp_register, BFD_RELOC_LO16); | |
13599 | } | |
f21f8242 | 13600 | |
584892a6 | 13601 | macro_end (); |
6478892d TS |
13602 | |
13603 | demand_empty_rest_of_line (); | |
13604 | } | |
13605 | ||
13606 | static void | |
17a2f251 | 13607 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13608 | { |
13609 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13610 | .cplocal is ignored. */ |
6478892d TS |
13611 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13612 | { | |
13613 | s_ignore (0); | |
13614 | return; | |
13615 | } | |
13616 | ||
13617 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13618 | demand_empty_rest_of_line (); |
6478892d TS |
13619 | } |
13620 | ||
252b5132 RH |
13621 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13622 | offset from $sp. The offset is remembered, and after making a PIC | |
13623 | call $gp is restored from that location. */ | |
13624 | ||
13625 | static void | |
17a2f251 | 13626 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13627 | { |
13628 | expressionS ex; | |
252b5132 | 13629 | |
6478892d | 13630 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13631 | .cprestore is ignored. */ |
6478892d | 13632 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13633 | { |
13634 | s_ignore (0); | |
13635 | return; | |
13636 | } | |
13637 | ||
13638 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13639 | mips_cprestore_valid = 1; |
252b5132 RH |
13640 | |
13641 | ex.X_op = O_constant; | |
13642 | ex.X_add_symbol = NULL; | |
13643 | ex.X_op_symbol = NULL; | |
13644 | ex.X_add_number = mips_cprestore_offset; | |
13645 | ||
584892a6 | 13646 | macro_start (); |
67c0d1eb RS |
13647 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13648 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13649 | macro_end (); |
252b5132 RH |
13650 | |
13651 | demand_empty_rest_of_line (); | |
13652 | } | |
13653 | ||
6478892d | 13654 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13655 | was given in the preceding .cpsetup, it results in: |
6478892d | 13656 | ld $gp, offset($sp) |
76b3015f | 13657 | |
6478892d | 13658 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13659 | daddu $gp, $reg2, $0 */ |
13660 | ||
6478892d | 13661 | static void |
17a2f251 | 13662 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13663 | { |
13664 | expressionS ex; | |
6478892d TS |
13665 | |
13666 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13667 | We also need NewABI support. */ | |
13668 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13669 | { | |
13670 | s_ignore (0); | |
13671 | return; | |
13672 | } | |
13673 | ||
584892a6 | 13674 | macro_start (); |
6478892d TS |
13675 | if (mips_cpreturn_register == -1) |
13676 | { | |
13677 | ex.X_op = O_constant; | |
13678 | ex.X_add_symbol = NULL; | |
13679 | ex.X_op_symbol = NULL; | |
13680 | ex.X_add_number = mips_cpreturn_offset; | |
13681 | ||
67c0d1eb | 13682 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13683 | } |
13684 | else | |
67c0d1eb | 13685 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13686 | mips_cpreturn_register, 0); |
584892a6 | 13687 | macro_end (); |
6478892d TS |
13688 | |
13689 | demand_empty_rest_of_line (); | |
13690 | } | |
13691 | ||
741d6ea8 JM |
13692 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13693 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13694 | use in DWARF debug information. */ | |
13695 | ||
13696 | static void | |
13697 | s_dtprel_internal (size_t bytes) | |
13698 | { | |
13699 | expressionS ex; | |
13700 | char *p; | |
13701 | ||
13702 | expression (&ex); | |
13703 | ||
13704 | if (ex.X_op != O_symbol) | |
13705 | { | |
13706 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13707 | ? ".dtpreldword" | |
13708 | : ".dtprelword")); | |
13709 | ignore_rest_of_line (); | |
13710 | } | |
13711 | ||
13712 | p = frag_more (bytes); | |
13713 | md_number_to_chars (p, 0, bytes); | |
13714 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13715 | (bytes == 8 | |
13716 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13717 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13718 | ||
13719 | demand_empty_rest_of_line (); | |
13720 | } | |
13721 | ||
13722 | /* Handle .dtprelword. */ | |
13723 | ||
13724 | static void | |
13725 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13726 | { | |
13727 | s_dtprel_internal (4); | |
13728 | } | |
13729 | ||
13730 | /* Handle .dtpreldword. */ | |
13731 | ||
13732 | static void | |
13733 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13734 | { | |
13735 | s_dtprel_internal (8); | |
13736 | } | |
13737 | ||
6478892d TS |
13738 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13739 | code. It sets the offset to use in gp_rel relocations. */ | |
13740 | ||
13741 | static void | |
17a2f251 | 13742 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13743 | { |
13744 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13745 | We also need NewABI support. */ | |
13746 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13747 | { | |
13748 | s_ignore (0); | |
13749 | return; | |
13750 | } | |
13751 | ||
def2e0dd | 13752 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13753 | |
13754 | demand_empty_rest_of_line (); | |
13755 | } | |
13756 | ||
252b5132 RH |
13757 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13758 | code. It generates a 32 bit GP relative reloc. */ | |
13759 | ||
13760 | static void | |
17a2f251 | 13761 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13762 | { |
a8dbcb85 TS |
13763 | segment_info_type *si; |
13764 | struct insn_label_list *l; | |
252b5132 RH |
13765 | symbolS *label; |
13766 | expressionS ex; | |
13767 | char *p; | |
13768 | ||
13769 | /* When not generating PIC code, this is treated as .word. */ | |
13770 | if (mips_pic != SVR4_PIC) | |
13771 | { | |
13772 | s_cons (2); | |
13773 | return; | |
13774 | } | |
13775 | ||
a8dbcb85 TS |
13776 | si = seg_info (now_seg); |
13777 | l = si->label_list; | |
13778 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13779 | mips_emit_delays (); |
252b5132 RH |
13780 | if (auto_align) |
13781 | mips_align (2, 0, label); | |
252b5132 RH |
13782 | |
13783 | expression (&ex); | |
a1facbec | 13784 | mips_clear_insn_labels (); |
252b5132 RH |
13785 | |
13786 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13787 | { | |
13788 | as_bad (_("Unsupported use of .gpword")); | |
13789 | ignore_rest_of_line (); | |
13790 | } | |
13791 | ||
13792 | p = frag_more (4); | |
17a2f251 | 13793 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13794 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13795 | BFD_RELOC_GPREL32); |
252b5132 RH |
13796 | |
13797 | demand_empty_rest_of_line (); | |
13798 | } | |
13799 | ||
10181a0d | 13800 | static void |
17a2f251 | 13801 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13802 | { |
a8dbcb85 TS |
13803 | segment_info_type *si; |
13804 | struct insn_label_list *l; | |
10181a0d AO |
13805 | symbolS *label; |
13806 | expressionS ex; | |
13807 | char *p; | |
13808 | ||
13809 | /* When not generating PIC code, this is treated as .dword. */ | |
13810 | if (mips_pic != SVR4_PIC) | |
13811 | { | |
13812 | s_cons (3); | |
13813 | return; | |
13814 | } | |
13815 | ||
a8dbcb85 TS |
13816 | si = seg_info (now_seg); |
13817 | l = si->label_list; | |
13818 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13819 | mips_emit_delays (); |
10181a0d AO |
13820 | if (auto_align) |
13821 | mips_align (3, 0, label); | |
10181a0d AO |
13822 | |
13823 | expression (&ex); | |
a1facbec | 13824 | mips_clear_insn_labels (); |
10181a0d AO |
13825 | |
13826 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13827 | { | |
13828 | as_bad (_("Unsupported use of .gpdword")); | |
13829 | ignore_rest_of_line (); | |
13830 | } | |
13831 | ||
13832 | p = frag_more (8); | |
17a2f251 | 13833 | md_number_to_chars (p, 0, 8); |
a105a300 | 13834 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13835 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13836 | |
13837 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13838 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13839 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13840 | |
13841 | demand_empty_rest_of_line (); | |
13842 | } | |
13843 | ||
252b5132 RH |
13844 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13845 | tables in SVR4 PIC code. */ | |
13846 | ||
13847 | static void | |
17a2f251 | 13848 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13849 | { |
252b5132 RH |
13850 | int reg; |
13851 | ||
10181a0d AO |
13852 | /* This is ignored when not generating SVR4 PIC code. */ |
13853 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13854 | { |
13855 | s_ignore (0); | |
13856 | return; | |
13857 | } | |
13858 | ||
13859 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13860 | macro_start (); |
252b5132 | 13861 | reg = tc_get_register (0); |
67c0d1eb | 13862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13863 | macro_end (); |
252b5132 | 13864 | |
bdaaa2e1 | 13865 | demand_empty_rest_of_line (); |
252b5132 RH |
13866 | } |
13867 | ||
13868 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13869 | mips16 mode. This permits the linker to handle them specially, | |
13870 | such as generating jalx instructions when needed. We also make | |
13871 | them odd for the duration of the assembly, in order to generate the | |
13872 | right sort of code. We will make them even in the adjust_symtab | |
13873 | routine, while leaving them marked. This is convenient for the | |
13874 | debugger and the disassembler. The linker knows to make them odd | |
13875 | again. */ | |
13876 | ||
13877 | static void | |
17a2f251 | 13878 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13879 | { |
f9419b05 | 13880 | mips16_mark_labels (); |
252b5132 RH |
13881 | |
13882 | demand_empty_rest_of_line (); | |
13883 | } | |
13884 | ||
13885 | /* Handle a .stabn directive. We need these in order to mark a label | |
13886 | as being a mips16 text label correctly. Sometimes the compiler | |
13887 | will emit a label, followed by a .stabn, and then switch sections. | |
13888 | If the label and .stabn are in mips16 mode, then the label is | |
13889 | really a mips16 text label. */ | |
13890 | ||
13891 | static void | |
17a2f251 | 13892 | s_mips_stab (int type) |
252b5132 | 13893 | { |
f9419b05 | 13894 | if (type == 'n') |
252b5132 RH |
13895 | mips16_mark_labels (); |
13896 | ||
13897 | s_stab (type); | |
13898 | } | |
13899 | ||
54f4ddb3 | 13900 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13901 | |
13902 | static void | |
17a2f251 | 13903 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13904 | { |
13905 | char *name; | |
13906 | int c; | |
13907 | symbolS *symbolP; | |
13908 | expressionS exp; | |
13909 | ||
13910 | name = input_line_pointer; | |
13911 | c = get_symbol_end (); | |
13912 | symbolP = symbol_find_or_make (name); | |
13913 | S_SET_WEAK (symbolP); | |
13914 | *input_line_pointer = c; | |
13915 | ||
13916 | SKIP_WHITESPACE (); | |
13917 | ||
13918 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13919 | { | |
13920 | if (S_IS_DEFINED (symbolP)) | |
13921 | { | |
20203fb9 | 13922 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13923 | S_GET_NAME (symbolP)); |
13924 | ignore_rest_of_line (); | |
13925 | return; | |
13926 | } | |
bdaaa2e1 | 13927 | |
252b5132 RH |
13928 | if (*input_line_pointer == ',') |
13929 | { | |
13930 | ++input_line_pointer; | |
13931 | SKIP_WHITESPACE (); | |
13932 | } | |
bdaaa2e1 | 13933 | |
252b5132 RH |
13934 | expression (&exp); |
13935 | if (exp.X_op != O_symbol) | |
13936 | { | |
20203fb9 | 13937 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13938 | ignore_rest_of_line (); |
252b5132 RH |
13939 | return; |
13940 | } | |
49309057 | 13941 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13942 | } |
13943 | ||
13944 | demand_empty_rest_of_line (); | |
13945 | } | |
13946 | ||
13947 | /* Parse a register string into a number. Called from the ECOFF code | |
13948 | to parse .frame. The argument is non-zero if this is the frame | |
13949 | register, so that we can record it in mips_frame_reg. */ | |
13950 | ||
13951 | int | |
17a2f251 | 13952 | tc_get_register (int frame) |
252b5132 | 13953 | { |
707bfff6 | 13954 | unsigned int reg; |
252b5132 RH |
13955 | |
13956 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13957 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13958 | reg = 0; | |
252b5132 | 13959 | if (frame) |
7a621144 DJ |
13960 | { |
13961 | mips_frame_reg = reg != 0 ? reg : SP; | |
13962 | mips_frame_reg_valid = 1; | |
13963 | mips_cprestore_valid = 0; | |
13964 | } | |
252b5132 RH |
13965 | return reg; |
13966 | } | |
13967 | ||
13968 | valueT | |
17a2f251 | 13969 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13970 | { |
13971 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13972 | ||
b4c71f56 TS |
13973 | if (IS_ELF) |
13974 | { | |
13975 | /* We don't need to align ELF sections to the full alignment. | |
13976 | However, Irix 5 may prefer that we align them at least to a 16 | |
13977 | byte boundary. We don't bother to align the sections if we | |
13978 | are targeted for an embedded system. */ | |
c41e87e3 | 13979 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13980 | return addr; |
13981 | if (align > 4) | |
13982 | align = 4; | |
13983 | } | |
252b5132 RH |
13984 | |
13985 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13986 | } | |
13987 | ||
13988 | /* Utility routine, called from above as well. If called while the | |
13989 | input file is still being read, it's only an approximation. (For | |
13990 | example, a symbol may later become defined which appeared to be | |
13991 | undefined earlier.) */ | |
13992 | ||
13993 | static int | |
17a2f251 | 13994 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13995 | { |
13996 | if (sym == 0) | |
13997 | return 0; | |
13998 | ||
4d0d148d | 13999 | if (g_switch_value > 0) |
252b5132 RH |
14000 | { |
14001 | const char *symname; | |
14002 | int change; | |
14003 | ||
c9914766 | 14004 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
14005 | register. It can be if it is smaller than the -G size or if |
14006 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 14007 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
14008 | they can. */ |
14009 | symname = S_GET_NAME (sym); | |
14010 | if (symname != (const char *) NULL | |
14011 | && (strcmp (symname, "eprol") == 0 | |
14012 | || strcmp (symname, "etext") == 0 | |
14013 | || strcmp (symname, "_gp") == 0 | |
14014 | || strcmp (symname, "edata") == 0 | |
14015 | || strcmp (symname, "_fbss") == 0 | |
14016 | || strcmp (symname, "_fdata") == 0 | |
14017 | || strcmp (symname, "_ftext") == 0 | |
14018 | || strcmp (symname, "end") == 0 | |
14019 | || strcmp (symname, "_gp_disp") == 0)) | |
14020 | change = 1; | |
14021 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
14022 | && (0 | |
14023 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
14024 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
14025 | && (symbol_get_obj (sym)->ecoff_extern_size | |
14026 | <= g_switch_value)) | |
252b5132 RH |
14027 | #endif |
14028 | /* We must defer this decision until after the whole | |
14029 | file has been read, since there might be a .extern | |
14030 | after the first use of this symbol. */ | |
14031 | || (before_relaxing | |
14032 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 14033 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
14034 | #endif |
14035 | && S_GET_VALUE (sym) == 0) | |
14036 | || (S_GET_VALUE (sym) != 0 | |
14037 | && S_GET_VALUE (sym) <= g_switch_value))) | |
14038 | change = 0; | |
14039 | else | |
14040 | { | |
14041 | const char *segname; | |
14042 | ||
14043 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 14044 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
14045 | && strcmp (segname, ".lit4") != 0); |
14046 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
14047 | && strcmp (segname, ".sbss") != 0 |
14048 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
14049 | && strncmp (segname, ".sbss.", 6) != 0 |
14050 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 14051 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
14052 | } |
14053 | return change; | |
14054 | } | |
14055 | else | |
c9914766 | 14056 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
14057 | return 1; |
14058 | } | |
14059 | ||
5919d012 RS |
14060 | |
14061 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
14062 | ||
14063 | static bfd_boolean | |
17a2f251 | 14064 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
14065 | { |
14066 | asection *symsec; | |
5919d012 RS |
14067 | |
14068 | /* Handle the case of a symbol equated to another symbol. */ | |
14069 | while (symbol_equated_reloc_p (sym)) | |
14070 | { | |
14071 | symbolS *n; | |
14072 | ||
5f0fe04b | 14073 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
14074 | n = symbol_get_value_expression (sym)->X_add_symbol; |
14075 | if (n == sym) | |
14076 | break; | |
14077 | sym = n; | |
14078 | } | |
14079 | ||
df1f3cda DD |
14080 | if (symbol_section_p (sym)) |
14081 | return TRUE; | |
14082 | ||
5919d012 RS |
14083 | symsec = S_GET_SEGMENT (sym); |
14084 | ||
5919d012 RS |
14085 | /* This must duplicate the test in adjust_reloc_syms. */ |
14086 | return (symsec != &bfd_und_section | |
14087 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
14088 | && !bfd_is_com_section (symsec) |
14089 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
14090 | #ifdef OBJ_ELF |
14091 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 14092 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
14093 | #endif |
14094 | ); | |
14095 | } | |
14096 | ||
14097 | ||
252b5132 RH |
14098 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
14099 | extended opcode. SEC is the section the frag is in. */ | |
14100 | ||
14101 | static int | |
17a2f251 | 14102 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
14103 | { |
14104 | int type; | |
3994f87e | 14105 | const struct mips16_immed_operand *op; |
252b5132 RH |
14106 | offsetT val; |
14107 | int mintiny, maxtiny; | |
14108 | segT symsec; | |
98aa84af | 14109 | fragS *sym_frag; |
252b5132 RH |
14110 | |
14111 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
14112 | return 0; | |
14113 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
14114 | return 1; | |
14115 | ||
14116 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14117 | op = mips16_immed_operands; | |
14118 | while (op->type != type) | |
14119 | { | |
14120 | ++op; | |
9c2799c2 | 14121 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14122 | } |
14123 | ||
14124 | if (op->unsp) | |
14125 | { | |
14126 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14127 | { | |
14128 | mintiny = 1; | |
14129 | maxtiny = 1 << op->nbits; | |
14130 | } | |
14131 | else | |
14132 | { | |
14133 | mintiny = 0; | |
14134 | maxtiny = (1 << op->nbits) - 1; | |
14135 | } | |
14136 | } | |
14137 | else | |
14138 | { | |
14139 | mintiny = - (1 << (op->nbits - 1)); | |
14140 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
14141 | } | |
14142 | ||
98aa84af | 14143 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 14144 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 14145 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
14146 | |
14147 | if (op->pcrel) | |
14148 | { | |
14149 | addressT addr; | |
14150 | ||
14151 | /* We won't have the section when we are called from | |
14152 | mips_relax_frag. However, we will always have been called | |
14153 | from md_estimate_size_before_relax first. If this is a | |
14154 | branch to a different section, we mark it as such. If SEC is | |
14155 | NULL, and the frag is not marked, then it must be a branch to | |
14156 | the same section. */ | |
14157 | if (sec == NULL) | |
14158 | { | |
14159 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
14160 | return 1; | |
14161 | } | |
14162 | else | |
14163 | { | |
98aa84af | 14164 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
14165 | if (symsec != sec) |
14166 | { | |
14167 | fragp->fr_subtype = | |
14168 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14169 | ||
14170 | /* FIXME: We should support this, and let the linker | |
14171 | catch branches and loads that are out of range. */ | |
14172 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
14173 | _("unsupported PC relative reference to different section")); | |
14174 | ||
14175 | return 1; | |
14176 | } | |
98aa84af AM |
14177 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
14178 | /* Assume non-extended on the first relaxation pass. | |
14179 | The address we have calculated will be bogus if this is | |
14180 | a forward branch to another frag, as the forward frag | |
14181 | will have fr_address == 0. */ | |
14182 | return 0; | |
252b5132 RH |
14183 | } |
14184 | ||
14185 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
14186 | the same section. If the relax_marker of the symbol fragment |
14187 | differs from the relax_marker of this fragment, we have not | |
14188 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
14189 | in STRETCH in order to get a better estimate of the address. |
14190 | This particularly matters because of the shift bits. */ | |
14191 | if (stretch != 0 | |
98aa84af | 14192 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
14193 | { |
14194 | fragS *f; | |
14195 | ||
14196 | /* Adjust stretch for any alignment frag. Note that if have | |
14197 | been expanding the earlier code, the symbol may be | |
14198 | defined in what appears to be an earlier frag. FIXME: | |
14199 | This doesn't handle the fr_subtype field, which specifies | |
14200 | a maximum number of bytes to skip when doing an | |
14201 | alignment. */ | |
98aa84af | 14202 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
14203 | { |
14204 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
14205 | { | |
14206 | if (stretch < 0) | |
14207 | stretch = - ((- stretch) | |
14208 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
14209 | else | |
14210 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
14211 | if (stretch == 0) | |
14212 | break; | |
14213 | } | |
14214 | } | |
14215 | if (f != NULL) | |
14216 | val += stretch; | |
14217 | } | |
14218 | ||
14219 | addr = fragp->fr_address + fragp->fr_fix; | |
14220 | ||
14221 | /* The base address rules are complicated. The base address of | |
14222 | a branch is the following instruction. The base address of a | |
14223 | PC relative load or add is the instruction itself, but if it | |
14224 | is in a delay slot (in which case it can not be extended) use | |
14225 | the address of the instruction whose delay slot it is in. */ | |
14226 | if (type == 'p' || type == 'q') | |
14227 | { | |
14228 | addr += 2; | |
14229 | ||
14230 | /* If we are currently assuming that this frag should be | |
14231 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14232 | higher. */ |
252b5132 RH |
14233 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14234 | addr += 2; | |
14235 | ||
14236 | /* Ignore the low bit in the target, since it will be set | |
14237 | for a text label. */ | |
14238 | if ((val & 1) != 0) | |
14239 | --val; | |
14240 | } | |
14241 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14242 | addr -= 4; | |
14243 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14244 | addr -= 2; | |
14245 | ||
14246 | val -= addr & ~ ((1 << op->shift) - 1); | |
14247 | ||
14248 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14249 | if (type == 'p' || type == 'q') | |
14250 | val /= 2; | |
14251 | ||
14252 | /* If any of the shifted bits are set, we must use an extended | |
14253 | opcode. If the address depends on the size of this | |
14254 | instruction, this can lead to a loop, so we arrange to always | |
14255 | use an extended opcode. We only check this when we are in | |
14256 | the main relaxation loop, when SEC is NULL. */ | |
14257 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14258 | { | |
14259 | fragp->fr_subtype = | |
14260 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14261 | return 1; | |
14262 | } | |
14263 | ||
14264 | /* If we are about to mark a frag as extended because the value | |
14265 | is precisely maxtiny + 1, then there is a chance of an | |
14266 | infinite loop as in the following code: | |
14267 | la $4,foo | |
14268 | .skip 1020 | |
14269 | .align 2 | |
14270 | foo: | |
14271 | In this case when the la is extended, foo is 0x3fc bytes | |
14272 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14273 | the la must be extended. To avoid this loop, we mark the | |
14274 | frag as extended if it was small, and is about to become | |
14275 | extended with a value of maxtiny + 1. */ | |
14276 | if (val == ((maxtiny + 1) << op->shift) | |
14277 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14278 | && sec == NULL) | |
14279 | { | |
14280 | fragp->fr_subtype = | |
14281 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14282 | return 1; | |
14283 | } | |
14284 | } | |
14285 | else if (symsec != absolute_section && sec != NULL) | |
14286 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14287 | ||
14288 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14289 | || val < (mintiny << op->shift) | |
14290 | || val > (maxtiny << op->shift)) | |
14291 | return 1; | |
14292 | else | |
14293 | return 0; | |
14294 | } | |
14295 | ||
4a6a3df4 AO |
14296 | /* Compute the length of a branch sequence, and adjust the |
14297 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14298 | worst-case length is computed, with UPDATE being used to indicate | |
14299 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14300 | branch is to be computed. */ | |
14301 | static int | |
17a2f251 | 14302 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14303 | { |
b34976b6 | 14304 | bfd_boolean toofar; |
4a6a3df4 AO |
14305 | int length; |
14306 | ||
14307 | if (fragp | |
14308 | && S_IS_DEFINED (fragp->fr_symbol) | |
14309 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14310 | { | |
14311 | addressT addr; | |
14312 | offsetT val; | |
14313 | ||
14314 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14315 | ||
14316 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14317 | ||
14318 | val -= addr; | |
14319 | ||
14320 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14321 | } | |
14322 | else if (fragp) | |
14323 | /* If the symbol is not defined or it's in a different segment, | |
14324 | assume the user knows what's going on and emit a short | |
14325 | branch. */ | |
b34976b6 | 14326 | toofar = FALSE; |
4a6a3df4 | 14327 | else |
b34976b6 | 14328 | toofar = TRUE; |
4a6a3df4 AO |
14329 | |
14330 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14331 | fragp->fr_subtype | |
66b3e8da MR |
14332 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
14333 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
14334 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14335 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14336 | toofar); | |
14337 | ||
14338 | length = 4; | |
14339 | if (toofar) | |
14340 | { | |
14341 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14342 | length += 8; | |
14343 | ||
14344 | if (mips_pic != NO_PIC) | |
14345 | { | |
14346 | /* Additional space for PIC loading of target address. */ | |
14347 | length += 8; | |
14348 | if (mips_opts.isa == ISA_MIPS1) | |
14349 | /* Additional space for $at-stabilizing nop. */ | |
14350 | length += 4; | |
14351 | } | |
14352 | ||
14353 | /* If branch is conditional. */ | |
14354 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14355 | length += 8; | |
14356 | } | |
b34976b6 | 14357 | |
4a6a3df4 AO |
14358 | return length; |
14359 | } | |
14360 | ||
252b5132 RH |
14361 | /* Estimate the size of a frag before relaxing. Unless this is the |
14362 | mips16, we are not really relaxing here, and the final size is | |
14363 | encoded in the subtype information. For the mips16, we have to | |
14364 | decide whether we are using an extended opcode or not. */ | |
14365 | ||
252b5132 | 14366 | int |
17a2f251 | 14367 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14368 | { |
5919d012 | 14369 | int change; |
252b5132 | 14370 | |
4a6a3df4 AO |
14371 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14372 | { | |
14373 | ||
b34976b6 AM |
14374 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14375 | ||
4a6a3df4 AO |
14376 | return fragp->fr_var; |
14377 | } | |
14378 | ||
252b5132 | 14379 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14380 | /* We don't want to modify the EXTENDED bit here; it might get us |
14381 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14382 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14383 | |
14384 | if (mips_pic == NO_PIC) | |
5919d012 | 14385 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14386 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14387 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14388 | else if (mips_pic == VXWORKS_PIC) |
14389 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14390 | change = 0; | |
252b5132 RH |
14391 | else |
14392 | abort (); | |
14393 | ||
14394 | if (change) | |
14395 | { | |
4d7206a2 | 14396 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14397 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14398 | } |
4d7206a2 RS |
14399 | else |
14400 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14401 | } |
14402 | ||
14403 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14404 | should be converted into a reloc against a section. */ |
252b5132 RH |
14405 | |
14406 | int | |
17a2f251 | 14407 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14408 | { |
252b5132 RH |
14409 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14410 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14411 | return 0; | |
a161fe53 | 14412 | |
252b5132 RH |
14413 | if (fixp->fx_addsy == NULL) |
14414 | return 1; | |
a161fe53 | 14415 | |
de7e6852 RS |
14416 | /* If symbol SYM is in a mergeable section, relocations of the form |
14417 | SYM + 0 can usually be made section-relative. The mergeable data | |
14418 | is then identified by the section offset rather than by the symbol. | |
14419 | ||
14420 | However, if we're generating REL LO16 relocations, the offset is split | |
14421 | between the LO16 and parterning high part relocation. The linker will | |
14422 | need to recalculate the complete offset in order to correctly identify | |
14423 | the merge data. | |
14424 | ||
14425 | The linker has traditionally not looked for the parterning high part | |
14426 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14427 | placed anywhere. Rather than break backwards compatibility by changing | |
14428 | this, it seems better not to force the issue, and instead keep the | |
14429 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14430 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14431 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14432 | && HAVE_IN_PLACE_ADDENDS |
14433 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14434 | return 0; | |
14435 | ||
ce70d90a MR |
14436 | /* There is no place to store an in-place offset for JALR relocations. |
14437 | Likewise an in-range offset of PC-relative relocations may overflow | |
14438 | the in-place relocatable field if recalculated against the start | |
14439 | address of the symbol's containing section. */ | |
14440 | if (HAVE_IN_PLACE_ADDENDS | |
14441 | && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR)) | |
1180b5a4 RS |
14442 | return 0; |
14443 | ||
252b5132 | 14444 | #ifdef OBJ_ELF |
b314ec0e RS |
14445 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14446 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14447 | relocations against MIPS16 functions; in this case, the stub becomes | |
14448 | the function's canonical address. | |
14449 | ||
14450 | Floating-point stubs are stored in unique .mips16.call.* or | |
14451 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14452 | the first relocation in section S must be against F; this is how the | |
14453 | linker determines the target function. All relocations that might | |
14454 | resolve to T must also be against F. We therefore have the following | |
14455 | restrictions, which are given in an intentionally-redundant way: | |
14456 | ||
14457 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14458 | symbols. | |
14459 | ||
14460 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14461 | if that stub might be used. | |
14462 | ||
14463 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14464 | symbols. | |
14465 | ||
14466 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14467 | that stub might be used. | |
14468 | ||
14469 | There is a further restriction: | |
14470 | ||
14471 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14472 | on targets with in-place addends; the relocation field cannot | |
14473 | encode the low bit. | |
14474 | ||
14475 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14476 | against a MIPS16 symbol. | |
14477 | ||
14478 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14479 | relocation against some symbol R, no relocation against R may be | |
14480 | reduced. (Note that this deals with (2) as well as (1) because | |
14481 | relocations against global symbols will never be reduced on ELF | |
14482 | targets.) This approach is a little simpler than trying to detect | |
14483 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14484 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14485 | if (IS_ELF |
b314ec0e | 14486 | && fixp->fx_subsy == NULL |
30c09090 | 14487 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14488 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14489 | return 0; |
14490 | #endif | |
a161fe53 | 14491 | |
252b5132 RH |
14492 | return 1; |
14493 | } | |
14494 | ||
14495 | /* Translate internal representation of relocation info to BFD target | |
14496 | format. */ | |
14497 | ||
14498 | arelent ** | |
17a2f251 | 14499 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14500 | { |
14501 | static arelent *retval[4]; | |
14502 | arelent *reloc; | |
14503 | bfd_reloc_code_real_type code; | |
14504 | ||
4b0cff4e TS |
14505 | memset (retval, 0, sizeof(retval)); |
14506 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14507 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14508 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14509 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14510 | ||
bad36eac DJ |
14511 | if (fixp->fx_pcrel) |
14512 | { | |
9c2799c2 | 14513 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14514 | |
14515 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14516 | Relocations want only the symbol offset. */ | |
14517 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14518 | if (!IS_ELF) |
bad36eac DJ |
14519 | { |
14520 | /* A gruesome hack which is a result of the gruesome gas | |
14521 | reloc handling. What's worse, for COFF (as opposed to | |
14522 | ECOFF), we might need yet another copy of reloc->address. | |
14523 | See bfd_install_relocation. */ | |
14524 | reloc->addend += reloc->address; | |
14525 | } | |
14526 | } | |
14527 | else | |
14528 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14529 | |
438c16b8 TS |
14530 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14531 | entry to be used in the relocation's section offset. */ | |
14532 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14533 | { |
14534 | reloc->address = reloc->addend; | |
14535 | reloc->addend = 0; | |
14536 | } | |
14537 | ||
252b5132 | 14538 | code = fixp->fx_r_type; |
252b5132 | 14539 | |
bad36eac | 14540 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14541 | if (reloc->howto == NULL) |
14542 | { | |
14543 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14544 | _("Can not represent %s relocation in this object file format"), | |
14545 | bfd_get_reloc_code_name (code)); | |
14546 | retval[0] = NULL; | |
14547 | } | |
14548 | ||
14549 | return retval; | |
14550 | } | |
14551 | ||
14552 | /* Relax a machine dependent frag. This returns the amount by which | |
14553 | the current size of the frag should change. */ | |
14554 | ||
14555 | int | |
17a2f251 | 14556 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14557 | { |
4a6a3df4 AO |
14558 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14559 | { | |
14560 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14561 | |
14562 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14563 | |
14564 | return fragp->fr_var - old_var; | |
14565 | } | |
14566 | ||
252b5132 RH |
14567 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14568 | return 0; | |
14569 | ||
c4e7957c | 14570 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14571 | { |
14572 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14573 | return 0; | |
14574 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14575 | return 2; | |
14576 | } | |
14577 | else | |
14578 | { | |
14579 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14580 | return 0; | |
14581 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14582 | return -2; | |
14583 | } | |
14584 | ||
14585 | return 0; | |
14586 | } | |
14587 | ||
14588 | /* Convert a machine dependent frag. */ | |
14589 | ||
14590 | void | |
17a2f251 | 14591 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14592 | { |
4a6a3df4 AO |
14593 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14594 | { | |
14595 | bfd_byte *buf; | |
14596 | unsigned long insn; | |
14597 | expressionS exp; | |
14598 | fixS *fixp; | |
b34976b6 | 14599 | |
4a6a3df4 AO |
14600 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14601 | ||
14602 | if (target_big_endian) | |
14603 | insn = bfd_getb32 (buf); | |
14604 | else | |
14605 | insn = bfd_getl32 (buf); | |
b34976b6 | 14606 | |
4a6a3df4 AO |
14607 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14608 | { | |
14609 | /* We generate a fixup instead of applying it right now | |
14610 | because, if there are linker relaxations, we're going to | |
14611 | need the relocations. */ | |
14612 | exp.X_op = O_symbol; | |
14613 | exp.X_add_symbol = fragp->fr_symbol; | |
14614 | exp.X_add_number = fragp->fr_offset; | |
14615 | ||
14616 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14617 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14618 | fixp->fx_file = fragp->fr_file; |
14619 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14620 | |
2132e3a3 | 14621 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14622 | buf += 4; |
14623 | } | |
14624 | else | |
14625 | { | |
14626 | int i; | |
14627 | ||
14628 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 14629 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
14630 | |
14631 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14632 | goto uncond; | |
14633 | ||
14634 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14635 | { | |
14636 | /* Reverse the branch. */ | |
14637 | switch ((insn >> 28) & 0xf) | |
14638 | { | |
14639 | case 4: | |
14640 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14641 | have the condition reversed by tweaking a single | |
14642 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14643 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14644 | insn ^= 0x00010000; |
14645 | break; | |
14646 | ||
14647 | case 0: | |
14648 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14649 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14650 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14651 | insn ^= 0x00010000; |
14652 | break; | |
b34976b6 | 14653 | |
4a6a3df4 AO |
14654 | case 1: |
14655 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14656 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14657 | insn ^= 0x04000000; |
14658 | break; | |
14659 | ||
14660 | default: | |
14661 | abort (); | |
14662 | } | |
14663 | } | |
14664 | ||
14665 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14666 | { | |
14667 | /* Clear the and-link bit. */ | |
9c2799c2 | 14668 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14669 | |
54f4ddb3 TS |
14670 | /* bltzal 0x04100000 bgezal 0x04110000 |
14671 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14672 | insn &= ~0x00100000; |
14673 | } | |
14674 | ||
14675 | /* Branch over the branch (if the branch was likely) or the | |
14676 | full jump (not likely case). Compute the offset from the | |
14677 | current instruction to branch to. */ | |
14678 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14679 | i = 16; | |
14680 | else | |
14681 | { | |
14682 | /* How many bytes in instructions we've already emitted? */ | |
14683 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14684 | /* How many bytes in instructions from here to the end? */ | |
14685 | i = fragp->fr_var - i; | |
14686 | } | |
14687 | /* Convert to instruction count. */ | |
14688 | i >>= 2; | |
14689 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14690 | i--; |
4a6a3df4 AO |
14691 | insn |= i; |
14692 | /* Branch over the jump. */ | |
2132e3a3 | 14693 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14694 | buf += 4; |
14695 | ||
54f4ddb3 | 14696 | /* nop */ |
2132e3a3 | 14697 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14698 | buf += 4; |
14699 | ||
14700 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14701 | { | |
14702 | /* beql $0, $0, 2f */ | |
14703 | insn = 0x50000000; | |
14704 | /* Compute the PC offset from the current instruction to | |
14705 | the end of the variable frag. */ | |
14706 | /* How many bytes in instructions we've already emitted? */ | |
14707 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14708 | /* How many bytes in instructions from here to the end? */ | |
14709 | i = fragp->fr_var - i; | |
14710 | /* Convert to instruction count. */ | |
14711 | i >>= 2; | |
14712 | /* Don't decrement i, because we want to branch over the | |
14713 | delay slot. */ | |
14714 | ||
14715 | insn |= i; | |
2132e3a3 | 14716 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14717 | buf += 4; |
14718 | ||
2132e3a3 | 14719 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14720 | buf += 4; |
14721 | } | |
14722 | ||
14723 | uncond: | |
14724 | if (mips_pic == NO_PIC) | |
14725 | { | |
14726 | /* j or jal. */ | |
14727 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14728 | ? 0x0c000000 : 0x08000000); | |
14729 | exp.X_op = O_symbol; | |
14730 | exp.X_add_symbol = fragp->fr_symbol; | |
14731 | exp.X_add_number = fragp->fr_offset; | |
14732 | ||
14733 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14734 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14735 | fixp->fx_file = fragp->fr_file; |
14736 | fixp->fx_line = fragp->fr_line; | |
14737 | ||
2132e3a3 | 14738 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14739 | buf += 4; |
14740 | } | |
14741 | else | |
14742 | { | |
66b3e8da MR |
14743 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
14744 | ||
4a6a3df4 | 14745 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
14746 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
14747 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
14748 | exp.X_op = O_symbol; |
14749 | exp.X_add_symbol = fragp->fr_symbol; | |
14750 | exp.X_add_number = fragp->fr_offset; | |
14751 | ||
14752 | if (fragp->fr_offset) | |
14753 | { | |
14754 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14755 | exp.X_add_number = 0; | |
14756 | } | |
14757 | ||
14758 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14759 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14760 | fixp->fx_file = fragp->fr_file; |
14761 | fixp->fx_line = fragp->fr_line; | |
14762 | ||
2132e3a3 | 14763 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14764 | buf += 4; |
b34976b6 | 14765 | |
4a6a3df4 AO |
14766 | if (mips_opts.isa == ISA_MIPS1) |
14767 | { | |
14768 | /* nop */ | |
2132e3a3 | 14769 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14770 | buf += 4; |
14771 | } | |
14772 | ||
14773 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
14774 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
14775 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
14776 | |
14777 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14778 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14779 | fixp->fx_file = fragp->fr_file; |
14780 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14781 | |
2132e3a3 | 14782 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14783 | buf += 4; |
14784 | ||
14785 | /* j(al)r $at. */ | |
14786 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 14787 | insn = 0x0000f809; |
4a6a3df4 | 14788 | else |
66b3e8da MR |
14789 | insn = 0x00000008; |
14790 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 14791 | |
2132e3a3 | 14792 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14793 | buf += 4; |
14794 | } | |
14795 | } | |
14796 | ||
9c2799c2 | 14797 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14798 | + fragp->fr_fix + fragp->fr_var); |
14799 | ||
14800 | fragp->fr_fix += fragp->fr_var; | |
14801 | ||
14802 | return; | |
14803 | } | |
14804 | ||
252b5132 RH |
14805 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14806 | { | |
14807 | int type; | |
3994f87e | 14808 | const struct mips16_immed_operand *op; |
b34976b6 | 14809 | bfd_boolean small, ext; |
252b5132 RH |
14810 | offsetT val; |
14811 | bfd_byte *buf; | |
14812 | unsigned long insn; | |
b34976b6 | 14813 | bfd_boolean use_extend; |
252b5132 RH |
14814 | unsigned short extend; |
14815 | ||
14816 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14817 | op = mips16_immed_operands; | |
14818 | while (op->type != type) | |
14819 | ++op; | |
14820 | ||
14821 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14822 | { | |
b34976b6 AM |
14823 | small = FALSE; |
14824 | ext = TRUE; | |
252b5132 RH |
14825 | } |
14826 | else | |
14827 | { | |
b34976b6 AM |
14828 | small = TRUE; |
14829 | ext = FALSE; | |
252b5132 RH |
14830 | } |
14831 | ||
5f5f22c0 | 14832 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14833 | if (op->pcrel) |
14834 | { | |
14835 | addressT addr; | |
14836 | ||
14837 | addr = fragp->fr_address + fragp->fr_fix; | |
14838 | ||
14839 | /* The rules for the base address of a PC relative reloc are | |
14840 | complicated; see mips16_extended_frag. */ | |
14841 | if (type == 'p' || type == 'q') | |
14842 | { | |
14843 | addr += 2; | |
14844 | if (ext) | |
14845 | addr += 2; | |
14846 | /* Ignore the low bit in the target, since it will be | |
14847 | set for a text label. */ | |
14848 | if ((val & 1) != 0) | |
14849 | --val; | |
14850 | } | |
14851 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14852 | addr -= 4; | |
14853 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14854 | addr -= 2; | |
14855 | ||
14856 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14857 | val -= addr; | |
14858 | ||
14859 | /* Make sure the section winds up with the alignment we have | |
14860 | assumed. */ | |
14861 | if (op->shift > 0) | |
14862 | record_alignment (asec, op->shift); | |
14863 | } | |
14864 | ||
14865 | if (ext | |
14866 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14867 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14868 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14869 | _("extended instruction in delay slot")); | |
14870 | ||
14871 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14872 | ||
14873 | if (target_big_endian) | |
14874 | insn = bfd_getb16 (buf); | |
14875 | else | |
14876 | insn = bfd_getl16 (buf); | |
14877 | ||
14878 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14879 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14880 | small, ext, &insn, &use_extend, &extend); | |
14881 | ||
14882 | if (use_extend) | |
14883 | { | |
2132e3a3 | 14884 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14885 | fragp->fr_fix += 2; |
14886 | buf += 2; | |
14887 | } | |
14888 | ||
2132e3a3 | 14889 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14890 | fragp->fr_fix += 2; |
14891 | buf += 2; | |
14892 | } | |
14893 | else | |
14894 | { | |
4d7206a2 RS |
14895 | int first, second; |
14896 | fixS *fixp; | |
252b5132 | 14897 | |
4d7206a2 RS |
14898 | first = RELAX_FIRST (fragp->fr_subtype); |
14899 | second = RELAX_SECOND (fragp->fr_subtype); | |
14900 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14901 | |
584892a6 RS |
14902 | /* Possibly emit a warning if we've chosen the longer option. */ |
14903 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14904 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14905 | { | |
14906 | const char *msg = macro_warning (fragp->fr_subtype); | |
14907 | if (msg != 0) | |
520725ea | 14908 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14909 | } |
14910 | ||
4d7206a2 RS |
14911 | /* Go through all the fixups for the first sequence. Disable them |
14912 | (by marking them as done) if we're going to use the second | |
14913 | sequence instead. */ | |
14914 | while (fixp | |
14915 | && fixp->fx_frag == fragp | |
14916 | && fixp->fx_where < fragp->fr_fix - second) | |
14917 | { | |
14918 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14919 | fixp->fx_done = 1; | |
14920 | fixp = fixp->fx_next; | |
14921 | } | |
252b5132 | 14922 | |
4d7206a2 RS |
14923 | /* Go through the fixups for the second sequence. Disable them if |
14924 | we're going to use the first sequence, otherwise adjust their | |
14925 | addresses to account for the relaxation. */ | |
14926 | while (fixp && fixp->fx_frag == fragp) | |
14927 | { | |
14928 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14929 | fixp->fx_where -= first; | |
14930 | else | |
14931 | fixp->fx_done = 1; | |
14932 | fixp = fixp->fx_next; | |
14933 | } | |
14934 | ||
14935 | /* Now modify the frag contents. */ | |
14936 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14937 | { | |
14938 | char *start; | |
14939 | ||
14940 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14941 | memmove (start, start + first, second); | |
14942 | fragp->fr_fix -= first; | |
14943 | } | |
14944 | else | |
14945 | fragp->fr_fix -= second; | |
252b5132 RH |
14946 | } |
14947 | } | |
14948 | ||
14949 | #ifdef OBJ_ELF | |
14950 | ||
14951 | /* This function is called after the relocs have been generated. | |
14952 | We've been storing mips16 text labels as odd. Here we convert them | |
14953 | back to even for the convenience of the debugger. */ | |
14954 | ||
14955 | void | |
17a2f251 | 14956 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14957 | { |
14958 | asymbol **syms; | |
14959 | unsigned int count, i; | |
14960 | ||
f43abd2b | 14961 | if (!IS_ELF) |
252b5132 RH |
14962 | return; |
14963 | ||
14964 | syms = bfd_get_outsymbols (stdoutput); | |
14965 | count = bfd_get_symcount (stdoutput); | |
14966 | for (i = 0; i < count; i++, syms++) | |
14967 | { | |
30c09090 | 14968 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14969 | && ((*syms)->value & 1) != 0) |
14970 | { | |
14971 | (*syms)->value &= ~1; | |
14972 | /* If the symbol has an odd size, it was probably computed | |
14973 | incorrectly, so adjust that as well. */ | |
14974 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14975 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14976 | } | |
14977 | } | |
14978 | } | |
14979 | ||
14980 | #endif | |
14981 | ||
a1facbec MR |
14982 | /* This function is called whenever a label is defined, including fake |
14983 | labels instantiated off the dot special symbol. It is used when | |
14984 | handling branch delays; if a branch has a label, we assume we cannot | |
14985 | move it. This also bumps the value of the symbol by 1 in compressed | |
14986 | code. */ | |
252b5132 RH |
14987 | |
14988 | void | |
a1facbec | 14989 | mips_record_label (symbolS *sym) |
252b5132 | 14990 | { |
a8dbcb85 | 14991 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14992 | struct insn_label_list *l; |
14993 | ||
14994 | if (free_insn_labels == NULL) | |
14995 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14996 | else | |
14997 | { | |
14998 | l = free_insn_labels; | |
14999 | free_insn_labels = l->next; | |
15000 | } | |
15001 | ||
15002 | l->label = sym; | |
a8dbcb85 TS |
15003 | l->next = si->label_list; |
15004 | si->label_list = l; | |
a1facbec | 15005 | } |
07a53e5c | 15006 | |
a1facbec MR |
15007 | /* This function is called as tc_frob_label() whenever a label is defined |
15008 | and adds a DWARF-2 record we only want for true labels. */ | |
15009 | ||
15010 | void | |
15011 | mips_define_label (symbolS *sym) | |
15012 | { | |
15013 | mips_record_label (sym); | |
07a53e5c RH |
15014 | #ifdef OBJ_ELF |
15015 | dwarf2_emit_label (sym); | |
15016 | #endif | |
252b5132 RH |
15017 | } |
15018 | \f | |
15019 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15020 | ||
15021 | /* Some special processing for a MIPS ELF file. */ | |
15022 | ||
15023 | void | |
17a2f251 | 15024 | mips_elf_final_processing (void) |
252b5132 RH |
15025 | { |
15026 | /* Write out the register information. */ | |
316f5878 | 15027 | if (mips_abi != N64_ABI) |
252b5132 RH |
15028 | { |
15029 | Elf32_RegInfo s; | |
15030 | ||
15031 | s.ri_gprmask = mips_gprmask; | |
15032 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15033 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15034 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15035 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15036 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15037 | ||
15038 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
15039 | ((Elf32_External_RegInfo *) | |
15040 | mips_regmask_frag)); | |
15041 | } | |
15042 | else | |
15043 | { | |
15044 | Elf64_Internal_RegInfo s; | |
15045 | ||
15046 | s.ri_gprmask = mips_gprmask; | |
15047 | s.ri_pad = 0; | |
15048 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15049 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15050 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15051 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15052 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15053 | ||
15054 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
15055 | ((Elf64_External_RegInfo *) | |
15056 | mips_regmask_frag)); | |
15057 | } | |
15058 | ||
15059 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
15060 | sort of BFD interface for this. */ | |
15061 | if (mips_any_noreorder) | |
15062 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
15063 | if (mips_pic != NO_PIC) | |
143d77c5 | 15064 | { |
252b5132 | 15065 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
15066 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
15067 | } | |
15068 | if (mips_abicalls) | |
15069 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 15070 | |
98d3f06f | 15071 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
15072 | /* We may need to define a new flag for DSP ASE, and set this flag when |
15073 | file_ase_dsp is true. */ | |
8b082fb1 | 15074 | /* Same for DSP R2. */ |
ef2e4d86 CF |
15075 | /* We may need to define a new flag for MT ASE, and set this flag when |
15076 | file_ase_mt is true. */ | |
a4672219 TS |
15077 | if (file_ase_mips16) |
15078 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
15079 | #if 0 /* XXX FIXME */ |
15080 | if (file_ase_mips3d) | |
15081 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15082 | #endif | |
deec1734 CD |
15083 | if (file_ase_mdmx) |
15084 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 15085 | |
bdaaa2e1 | 15086 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 15087 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 15088 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 15089 | else if (mips_abi == O64_ABI) |
252b5132 | 15090 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 15091 | else if (mips_abi == EABI_ABI) |
252b5132 | 15092 | { |
316f5878 | 15093 | if (!file_mips_gp32) |
252b5132 RH |
15094 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
15095 | else | |
15096 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
15097 | } | |
316f5878 | 15098 | else if (mips_abi == N32_ABI) |
be00bddd TS |
15099 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
15100 | ||
c9914766 | 15101 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
15102 | |
15103 | if (mips_32bitmode) | |
15104 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
15105 | |
15106 | #if 0 /* XXX FIXME */ | |
15107 | /* 32 bit code with 64 bit FP registers. */ | |
15108 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15109 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15110 | #endif | |
252b5132 RH |
15111 | } |
15112 | ||
15113 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
15114 | \f | |
beae10d5 | 15115 | typedef struct proc { |
9b2f1d35 EC |
15116 | symbolS *func_sym; |
15117 | symbolS *func_end_sym; | |
beae10d5 KH |
15118 | unsigned long reg_mask; |
15119 | unsigned long reg_offset; | |
15120 | unsigned long fpreg_mask; | |
15121 | unsigned long fpreg_offset; | |
15122 | unsigned long frame_offset; | |
15123 | unsigned long frame_reg; | |
15124 | unsigned long pc_reg; | |
15125 | } procS; | |
252b5132 RH |
15126 | |
15127 | static procS cur_proc; | |
15128 | static procS *cur_proc_ptr; | |
15129 | static int numprocs; | |
15130 | ||
742a56fe RS |
15131 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
15132 | nop as "0". */ | |
15133 | ||
15134 | char | |
15135 | mips_nop_opcode (void) | |
15136 | { | |
15137 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
15138 | } | |
15139 | ||
15140 | /* Fill in an rs_align_code fragment. This only needs to do something | |
15141 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 15142 | |
0a9ef439 | 15143 | void |
17a2f251 | 15144 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 15145 | { |
742a56fe | 15146 | char *p; |
c67a084a NC |
15147 | int bytes, size, excess; |
15148 | valueT opcode; | |
742a56fe | 15149 | |
0a9ef439 RH |
15150 | if (fragp->fr_type != rs_align_code) |
15151 | return; | |
15152 | ||
742a56fe RS |
15153 | p = fragp->fr_literal + fragp->fr_fix; |
15154 | if (*p) | |
a19d8eb0 | 15155 | { |
c67a084a NC |
15156 | opcode = mips16_nop_insn.insn_opcode; |
15157 | size = 2; | |
15158 | } | |
15159 | else | |
15160 | { | |
15161 | opcode = nop_insn.insn_opcode; | |
15162 | size = 4; | |
15163 | } | |
a19d8eb0 | 15164 | |
c67a084a NC |
15165 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
15166 | excess = bytes % size; | |
15167 | if (excess != 0) | |
15168 | { | |
15169 | /* If we're not inserting a whole number of instructions, | |
15170 | pad the end of the fixed part of the frag with zeros. */ | |
15171 | memset (p, 0, excess); | |
15172 | p += excess; | |
15173 | fragp->fr_fix += excess; | |
a19d8eb0 | 15174 | } |
c67a084a NC |
15175 | |
15176 | md_number_to_chars (p, opcode, size); | |
15177 | fragp->fr_var = size; | |
a19d8eb0 CP |
15178 | } |
15179 | ||
252b5132 | 15180 | static void |
17a2f251 | 15181 | md_obj_begin (void) |
252b5132 RH |
15182 | { |
15183 | } | |
15184 | ||
15185 | static void | |
17a2f251 | 15186 | md_obj_end (void) |
252b5132 | 15187 | { |
54f4ddb3 | 15188 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 15189 | if (cur_proc_ptr) |
9a41af64 | 15190 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
15191 | } |
15192 | ||
15193 | static long | |
17a2f251 | 15194 | get_number (void) |
252b5132 RH |
15195 | { |
15196 | int negative = 0; | |
15197 | long val = 0; | |
15198 | ||
15199 | if (*input_line_pointer == '-') | |
15200 | { | |
15201 | ++input_line_pointer; | |
15202 | negative = 1; | |
15203 | } | |
3882b010 | 15204 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 15205 | as_bad (_("expected simple number")); |
252b5132 RH |
15206 | if (input_line_pointer[0] == '0') |
15207 | { | |
15208 | if (input_line_pointer[1] == 'x') | |
15209 | { | |
15210 | input_line_pointer += 2; | |
3882b010 | 15211 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
15212 | { |
15213 | val <<= 4; | |
15214 | val |= hex_value (*input_line_pointer++); | |
15215 | } | |
15216 | return negative ? -val : val; | |
15217 | } | |
15218 | else | |
15219 | { | |
15220 | ++input_line_pointer; | |
3882b010 | 15221 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15222 | { |
15223 | val <<= 3; | |
15224 | val |= *input_line_pointer++ - '0'; | |
15225 | } | |
15226 | return negative ? -val : val; | |
15227 | } | |
15228 | } | |
3882b010 | 15229 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15230 | { |
15231 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15232 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15233 | as_warn (_("invalid number")); |
252b5132 RH |
15234 | return -1; |
15235 | } | |
3882b010 | 15236 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15237 | { |
15238 | val *= 10; | |
15239 | val += *input_line_pointer++ - '0'; | |
15240 | } | |
15241 | return negative ? -val : val; | |
15242 | } | |
15243 | ||
15244 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15245 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15246 | case .file implies DWARF-2. */ | |
15247 | ||
15248 | static void | |
17a2f251 | 15249 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15250 | { |
ecb4347a DJ |
15251 | static int first_file_directive = 0; |
15252 | ||
c5dd6aab DJ |
15253 | if (ECOFF_DEBUGGING) |
15254 | { | |
15255 | get_number (); | |
15256 | s_app_file (0); | |
15257 | } | |
15258 | else | |
ecb4347a DJ |
15259 | { |
15260 | char *filename; | |
15261 | ||
15262 | filename = dwarf2_directive_file (0); | |
15263 | ||
15264 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15265 | directive even for stabs output. Make sure that this | |
15266 | ".file" is handled. Note that you need a version of GCC | |
15267 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15268 | if (filename != NULL && ! first_file_directive) | |
15269 | { | |
15270 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15271 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15272 | } |
15273 | first_file_directive = 1; | |
15274 | } | |
c5dd6aab DJ |
15275 | } |
15276 | ||
15277 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15278 | |
15279 | static void | |
17a2f251 | 15280 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15281 | { |
c5dd6aab DJ |
15282 | if (!ECOFF_DEBUGGING) |
15283 | dwarf2_directive_loc (0); | |
252b5132 RH |
15284 | } |
15285 | ||
252b5132 RH |
15286 | /* The .end directive. */ |
15287 | ||
15288 | static void | |
17a2f251 | 15289 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15290 | { |
15291 | symbolS *p; | |
252b5132 | 15292 | |
7a621144 DJ |
15293 | /* Following functions need their own .frame and .cprestore directives. */ |
15294 | mips_frame_reg_valid = 0; | |
15295 | mips_cprestore_valid = 0; | |
15296 | ||
252b5132 RH |
15297 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15298 | { | |
15299 | p = get_symbol (); | |
15300 | demand_empty_rest_of_line (); | |
15301 | } | |
15302 | else | |
15303 | p = NULL; | |
15304 | ||
14949570 | 15305 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15306 | as_warn (_(".end not in text section")); |
15307 | ||
15308 | if (!cur_proc_ptr) | |
15309 | { | |
15310 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15311 | demand_empty_rest_of_line (); | |
15312 | return; | |
15313 | } | |
15314 | ||
15315 | if (p != NULL) | |
15316 | { | |
9c2799c2 | 15317 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15318 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15319 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15320 | |
15321 | if (debug_type == DEBUG_STABS) | |
15322 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15323 | S_GET_NAME (p)); | |
252b5132 RH |
15324 | } |
15325 | else | |
15326 | as_warn (_(".end directive missing or unknown symbol")); | |
15327 | ||
2132e3a3 | 15328 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15329 | /* Create an expression to calculate the size of the function. */ |
15330 | if (p && cur_proc_ptr) | |
15331 | { | |
15332 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15333 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15334 | ||
15335 | obj->size = exp; | |
15336 | exp->X_op = O_subtract; | |
15337 | exp->X_add_symbol = symbol_temp_new_now (); | |
15338 | exp->X_op_symbol = p; | |
15339 | exp->X_add_number = 0; | |
15340 | ||
15341 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15342 | } | |
15343 | ||
ecb4347a | 15344 | /* Generate a .pdr section. */ |
f43abd2b | 15345 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15346 | { |
15347 | segT saved_seg = now_seg; | |
15348 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15349 | expressionS exp; |
15350 | char *fragp; | |
252b5132 | 15351 | |
252b5132 | 15352 | #ifdef md_flush_pending_output |
ecb4347a | 15353 | md_flush_pending_output (); |
252b5132 RH |
15354 | #endif |
15355 | ||
9c2799c2 | 15356 | gas_assert (pdr_seg); |
ecb4347a | 15357 | subseg_set (pdr_seg, 0); |
252b5132 | 15358 | |
ecb4347a DJ |
15359 | /* Write the symbol. */ |
15360 | exp.X_op = O_symbol; | |
15361 | exp.X_add_symbol = p; | |
15362 | exp.X_add_number = 0; | |
15363 | emit_expr (&exp, 4); | |
252b5132 | 15364 | |
ecb4347a | 15365 | fragp = frag_more (7 * 4); |
252b5132 | 15366 | |
17a2f251 TS |
15367 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15368 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15369 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15370 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15371 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15372 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15373 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15374 | |
ecb4347a DJ |
15375 | subseg_set (saved_seg, saved_subseg); |
15376 | } | |
15377 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15378 | |
15379 | cur_proc_ptr = NULL; | |
15380 | } | |
15381 | ||
15382 | /* The .aent and .ent directives. */ | |
15383 | ||
15384 | static void | |
17a2f251 | 15385 | s_mips_ent (int aent) |
252b5132 | 15386 | { |
252b5132 | 15387 | symbolS *symbolP; |
252b5132 RH |
15388 | |
15389 | symbolP = get_symbol (); | |
15390 | if (*input_line_pointer == ',') | |
f9419b05 | 15391 | ++input_line_pointer; |
252b5132 | 15392 | SKIP_WHITESPACE (); |
3882b010 | 15393 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15394 | || *input_line_pointer == '-') |
874e8986 | 15395 | get_number (); |
252b5132 | 15396 | |
14949570 | 15397 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15398 | as_warn (_(".ent or .aent not in text section.")); |
15399 | ||
15400 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15401 | as_warn (_("missing .end")); |
252b5132 RH |
15402 | |
15403 | if (!aent) | |
15404 | { | |
7a621144 DJ |
15405 | /* This function needs its own .frame and .cprestore directives. */ |
15406 | mips_frame_reg_valid = 0; | |
15407 | mips_cprestore_valid = 0; | |
15408 | ||
252b5132 RH |
15409 | cur_proc_ptr = &cur_proc; |
15410 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15411 | ||
9b2f1d35 | 15412 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15413 | |
f9419b05 | 15414 | ++numprocs; |
ecb4347a DJ |
15415 | |
15416 | if (debug_type == DEBUG_STABS) | |
15417 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15418 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15419 | } |
15420 | ||
7c0fc524 MR |
15421 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15422 | ||
252b5132 RH |
15423 | demand_empty_rest_of_line (); |
15424 | } | |
15425 | ||
15426 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15427 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15428 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15429 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15430 | symbol table (in the mdebug section). */ |
15431 | ||
15432 | static void | |
17a2f251 | 15433 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15434 | { |
ecb4347a | 15435 | #ifdef OBJ_ELF |
f43abd2b | 15436 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15437 | { |
15438 | long val; | |
252b5132 | 15439 | |
ecb4347a DJ |
15440 | if (cur_proc_ptr == (procS *) NULL) |
15441 | { | |
15442 | as_warn (_(".frame outside of .ent")); | |
15443 | demand_empty_rest_of_line (); | |
15444 | return; | |
15445 | } | |
252b5132 | 15446 | |
ecb4347a DJ |
15447 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15448 | ||
15449 | SKIP_WHITESPACE (); | |
15450 | if (*input_line_pointer++ != ',' | |
15451 | || get_absolute_expression_and_terminator (&val) != ',') | |
15452 | { | |
15453 | as_warn (_("Bad .frame directive")); | |
15454 | --input_line_pointer; | |
15455 | demand_empty_rest_of_line (); | |
15456 | return; | |
15457 | } | |
252b5132 | 15458 | |
ecb4347a DJ |
15459 | cur_proc_ptr->frame_offset = val; |
15460 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15461 | |
252b5132 | 15462 | demand_empty_rest_of_line (); |
252b5132 | 15463 | } |
ecb4347a DJ |
15464 | else |
15465 | #endif /* OBJ_ELF */ | |
15466 | s_ignore (ignore); | |
252b5132 RH |
15467 | } |
15468 | ||
bdaaa2e1 KH |
15469 | /* The .fmask and .mask directives. If the mdebug section is present |
15470 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15471 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15472 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15473 | make reference to the ecoff symbol table (in the mdebug section). */ |
15474 | ||
15475 | static void | |
17a2f251 | 15476 | s_mips_mask (int reg_type) |
252b5132 | 15477 | { |
ecb4347a | 15478 | #ifdef OBJ_ELF |
f43abd2b | 15479 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15480 | { |
ecb4347a | 15481 | long mask, off; |
252b5132 | 15482 | |
ecb4347a DJ |
15483 | if (cur_proc_ptr == (procS *) NULL) |
15484 | { | |
15485 | as_warn (_(".mask/.fmask outside of .ent")); | |
15486 | demand_empty_rest_of_line (); | |
15487 | return; | |
15488 | } | |
252b5132 | 15489 | |
ecb4347a DJ |
15490 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15491 | { | |
15492 | as_warn (_("Bad .mask/.fmask directive")); | |
15493 | --input_line_pointer; | |
15494 | demand_empty_rest_of_line (); | |
15495 | return; | |
15496 | } | |
252b5132 | 15497 | |
ecb4347a DJ |
15498 | off = get_absolute_expression (); |
15499 | ||
15500 | if (reg_type == 'F') | |
15501 | { | |
15502 | cur_proc_ptr->fpreg_mask = mask; | |
15503 | cur_proc_ptr->fpreg_offset = off; | |
15504 | } | |
15505 | else | |
15506 | { | |
15507 | cur_proc_ptr->reg_mask = mask; | |
15508 | cur_proc_ptr->reg_offset = off; | |
15509 | } | |
15510 | ||
15511 | demand_empty_rest_of_line (); | |
252b5132 RH |
15512 | } |
15513 | else | |
ecb4347a DJ |
15514 | #endif /* OBJ_ELF */ |
15515 | s_ignore (reg_type); | |
252b5132 RH |
15516 | } |
15517 | ||
316f5878 RS |
15518 | /* A table describing all the processors gas knows about. Names are |
15519 | matched in the order listed. | |
e7af610e | 15520 | |
316f5878 RS |
15521 | To ease comparison, please keep this table in the same order as |
15522 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15523 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15524 | { | |
316f5878 | 15525 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15526 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15527 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15528 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15529 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15530 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15531 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15532 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15533 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15534 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15535 | |
15536 | /* MIPS I */ | |
ad3fea08 TS |
15537 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15538 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15539 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15540 | |
15541 | /* MIPS II */ | |
ad3fea08 | 15542 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15543 | |
15544 | /* MIPS III */ | |
ad3fea08 TS |
15545 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15546 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15547 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15548 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15549 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15550 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15551 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15552 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15553 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15554 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15555 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15556 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15557 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15558 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15559 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15560 | |
15561 | /* MIPS IV */ | |
ad3fea08 TS |
15562 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15563 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15564 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15565 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15566 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15567 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15568 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15569 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15570 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15571 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15572 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15573 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15574 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15575 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15576 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15577 | |
15578 | /* MIPS 32 */ | |
ad3fea08 TS |
15579 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15580 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15581 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15582 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15583 | ||
15584 | /* MIPS 32 Release 2 */ | |
15585 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15586 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15587 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15588 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15589 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15590 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15591 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15592 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15593 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15594 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15595 | /* Deprecated forms of the above. */ | |
15596 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15597 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15598 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15599 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15600 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15601 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15602 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15603 | /* Deprecated forms of the above. */ | |
15604 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15605 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15606 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15607 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15608 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15609 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15610 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15611 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15612 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15613 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15614 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15615 | /* Deprecated forms of the above. */ | |
15616 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15617 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15618 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15619 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15620 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15621 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15622 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15623 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15624 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15625 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15626 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15627 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15628 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15629 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15630 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15631 | /* Deprecated forms of the above. */ | |
15632 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15633 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15634 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15635 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15636 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15637 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15638 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15639 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15640 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15641 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15642 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15643 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15644 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15645 | |
316f5878 | 15646 | /* MIPS 64 */ |
ad3fea08 TS |
15647 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15648 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15649 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15650 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15651 | |
c7a23324 | 15652 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15653 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15654 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15655 | /* Broadcom SB-1A CPU core */ |
15656 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15657 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15658 | |
15659 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15660 | |
ed163775 MR |
15661 | /* MIPS 64 Release 2 */ |
15662 | ||
967344c6 AN |
15663 | /* Cavium Networks Octeon CPU core */ |
15664 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15665 | ||
52b6b6b9 JM |
15666 | /* RMI Xlr */ |
15667 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15668 | ||
316f5878 RS |
15669 | /* End marker */ |
15670 | { NULL, 0, 0, 0 } | |
15671 | }; | |
e7af610e | 15672 | |
84ea6cf2 | 15673 | |
316f5878 RS |
15674 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15675 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15676 | |
316f5878 | 15677 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15678 | |
b34976b6 | 15679 | static bfd_boolean |
17a2f251 | 15680 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15681 | { |
15682 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15683 | given++, canonical++; | |
15684 | ||
15685 | return ((*given == 0 && *canonical == 0) | |
15686 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15687 | } | |
15688 | ||
15689 | ||
15690 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15691 | CPU name. We've traditionally allowed a lot of variation here. | |
15692 | ||
15693 | Note: this function is shared between GCC and GAS. */ | |
15694 | ||
b34976b6 | 15695 | static bfd_boolean |
17a2f251 | 15696 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15697 | { |
15698 | /* First see if the name matches exactly, or with a final "000" | |
15699 | turned into "k". */ | |
15700 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15701 | return TRUE; |
316f5878 RS |
15702 | |
15703 | /* If not, try comparing based on numerical designation alone. | |
15704 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15705 | if (TOLOWER (*given) == 'r') | |
15706 | given++; | |
15707 | if (!ISDIGIT (*given)) | |
b34976b6 | 15708 | return FALSE; |
316f5878 RS |
15709 | |
15710 | /* Skip over some well-known prefixes in the canonical name, | |
15711 | hoping to find a number there too. */ | |
15712 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15713 | canonical += 2; | |
15714 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15715 | canonical += 2; | |
15716 | else if (TOLOWER (canonical[0]) == 'r') | |
15717 | canonical += 1; | |
15718 | ||
15719 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15720 | } | |
15721 | ||
15722 | ||
15723 | /* Parse an option that takes the name of a processor as its argument. | |
15724 | OPTION is the name of the option and CPU_STRING is the argument. | |
15725 | Return the corresponding processor enumeration if the CPU_STRING is | |
15726 | recognized, otherwise report an error and return null. | |
15727 | ||
15728 | A similar function exists in GCC. */ | |
e7af610e NC |
15729 | |
15730 | static const struct mips_cpu_info * | |
17a2f251 | 15731 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15732 | { |
316f5878 | 15733 | const struct mips_cpu_info *p; |
e7af610e | 15734 | |
316f5878 RS |
15735 | /* 'from-abi' selects the most compatible architecture for the given |
15736 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15737 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15738 | version. Look first at the -mgp options, if given, otherwise base | |
15739 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15740 | |
316f5878 RS |
15741 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15742 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15743 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15744 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15745 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15746 | { | |
15747 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15748 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15749 | ||
15750 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15751 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15752 | ||
15753 | if (file_mips_gp32 >= 0) | |
15754 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15755 | ||
15756 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15757 | ? ISA_MIPS3 | |
15758 | : ISA_MIPS1); | |
15759 | } | |
15760 | ||
15761 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15762 | if (strcasecmp (cpu_string, "default") == 0) | |
15763 | return 0; | |
15764 | ||
15765 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15766 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15767 | return p; | |
15768 | ||
20203fb9 | 15769 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15770 | return 0; |
e7af610e NC |
15771 | } |
15772 | ||
316f5878 RS |
15773 | /* Return the canonical processor information for ISA (a member of the |
15774 | ISA_MIPS* enumeration). */ | |
15775 | ||
e7af610e | 15776 | static const struct mips_cpu_info * |
17a2f251 | 15777 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15778 | { |
15779 | int i; | |
15780 | ||
15781 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15782 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15783 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15784 | return (&mips_cpu_info_table[i]); |
15785 | ||
e972090a | 15786 | return NULL; |
e7af610e | 15787 | } |
fef14a42 TS |
15788 | |
15789 | static const struct mips_cpu_info * | |
17a2f251 | 15790 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15791 | { |
15792 | int i; | |
15793 | ||
15794 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15795 | if (arch == mips_cpu_info_table[i].cpu) | |
15796 | return (&mips_cpu_info_table[i]); | |
15797 | ||
15798 | return NULL; | |
15799 | } | |
316f5878 RS |
15800 | \f |
15801 | static void | |
17a2f251 | 15802 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15803 | { |
15804 | if (*first_p) | |
15805 | { | |
15806 | fprintf (stream, "%24s", ""); | |
15807 | *col_p = 24; | |
15808 | } | |
15809 | else | |
15810 | { | |
15811 | fprintf (stream, ", "); | |
15812 | *col_p += 2; | |
15813 | } | |
e7af610e | 15814 | |
316f5878 RS |
15815 | if (*col_p + strlen (string) > 72) |
15816 | { | |
15817 | fprintf (stream, "\n%24s", ""); | |
15818 | *col_p = 24; | |
15819 | } | |
15820 | ||
15821 | fprintf (stream, "%s", string); | |
15822 | *col_p += strlen (string); | |
15823 | ||
15824 | *first_p = 0; | |
15825 | } | |
15826 | ||
15827 | void | |
17a2f251 | 15828 | md_show_usage (FILE *stream) |
e7af610e | 15829 | { |
316f5878 RS |
15830 | int column, first; |
15831 | size_t i; | |
15832 | ||
15833 | fprintf (stream, _("\ | |
15834 | MIPS options:\n\ | |
316f5878 RS |
15835 | -EB generate big endian output\n\ |
15836 | -EL generate little endian output\n\ | |
15837 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15838 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15839 | implicitly with the gp register [default 8]\n")); | |
15840 | fprintf (stream, _("\ | |
15841 | -mips1 generate MIPS ISA I instructions\n\ | |
15842 | -mips2 generate MIPS ISA II instructions\n\ | |
15843 | -mips3 generate MIPS ISA III instructions\n\ | |
15844 | -mips4 generate MIPS ISA IV instructions\n\ | |
15845 | -mips5 generate MIPS ISA V instructions\n\ | |
15846 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15847 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15848 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15849 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15850 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15851 | ||
15852 | first = 1; | |
e7af610e NC |
15853 | |
15854 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15855 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15856 | show (stream, "from-abi", &column, &first); | |
15857 | fputc ('\n', stream); | |
e7af610e | 15858 | |
316f5878 RS |
15859 | fprintf (stream, _("\ |
15860 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15861 | -no-mCPU don't generate code specific to CPU.\n\ | |
15862 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15863 | ||
15864 | first = 1; | |
15865 | ||
15866 | show (stream, "3900", &column, &first); | |
15867 | show (stream, "4010", &column, &first); | |
15868 | show (stream, "4100", &column, &first); | |
15869 | show (stream, "4650", &column, &first); | |
15870 | fputc ('\n', stream); | |
15871 | ||
15872 | fprintf (stream, _("\ | |
15873 | -mips16 generate mips16 instructions\n\ | |
15874 | -no-mips16 do not generate mips16 instructions\n")); | |
15875 | fprintf (stream, _("\ | |
e16bfa71 TS |
15876 | -msmartmips generate smartmips instructions\n\ |
15877 | -mno-smartmips do not generate smartmips instructions\n")); | |
15878 | fprintf (stream, _("\ | |
74cd071d CF |
15879 | -mdsp generate DSP instructions\n\ |
15880 | -mno-dsp do not generate DSP instructions\n")); | |
15881 | fprintf (stream, _("\ | |
8b082fb1 TS |
15882 | -mdspr2 generate DSP R2 instructions\n\ |
15883 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15884 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15885 | -mmt generate MT instructions\n\ |
15886 | -mno-mt do not generate MT instructions\n")); | |
15887 | fprintf (stream, _("\ | |
c67a084a NC |
15888 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15889 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15890 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15891 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15892 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15893 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15894 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15895 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15896 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15897 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15898 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15899 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15900 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15901 | fprintf (stream, _("\ |
15902 | -mhard-float allow floating-point instructions\n\ | |
15903 | -msoft-float do not allow floating-point instructions\n\ | |
15904 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15905 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15906 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15907 | )); | |
316f5878 RS |
15908 | #ifdef OBJ_ELF |
15909 | fprintf (stream, _("\ | |
15910 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15911 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15912 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15913 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15914 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15915 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15916 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15917 | position dependent (non shared) code\n\ |
316f5878 RS |
15918 | -mabi=ABI create ABI conformant object file for:\n")); |
15919 | ||
15920 | first = 1; | |
15921 | ||
15922 | show (stream, "32", &column, &first); | |
15923 | show (stream, "o64", &column, &first); | |
15924 | show (stream, "n32", &column, &first); | |
15925 | show (stream, "64", &column, &first); | |
15926 | show (stream, "eabi", &column, &first); | |
15927 | ||
15928 | fputc ('\n', stream); | |
15929 | ||
15930 | fprintf (stream, _("\ | |
15931 | -32 create o32 ABI object file (default)\n\ | |
15932 | -n32 create n32 ABI object file\n\ | |
15933 | -64 create 64 ABI object file\n")); | |
15934 | #endif | |
e7af610e | 15935 | } |
14e777e0 | 15936 | |
1575952e | 15937 | #ifdef TE_IRIX |
14e777e0 | 15938 | enum dwarf2_format |
413a266c | 15939 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15940 | { |
369943fe | 15941 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15942 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15943 | else |
15944 | return dwarf2_format_32bit; | |
15945 | } | |
1575952e | 15946 | #endif |
73369e65 EC |
15947 | |
15948 | int | |
15949 | mips_dwarf2_addr_size (void) | |
15950 | { | |
6b6b3450 | 15951 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15952 | return 8; |
73369e65 EC |
15953 | else |
15954 | return 4; | |
15955 | } | |
5862107c EC |
15956 | |
15957 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15958 | void | |
15959 | mips_cfi_frame_initial_instructions (void) | |
15960 | { | |
15961 | cfi_add_CFA_def_cfa_register (SP); | |
15962 | } | |
15963 | ||
707bfff6 TS |
15964 | int |
15965 | tc_mips_regname_to_dw2regnum (char *regname) | |
15966 | { | |
15967 | unsigned int regnum = -1; | |
15968 | unsigned int reg; | |
15969 | ||
15970 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15971 | regnum = reg; | |
15972 | ||
15973 | return regnum; | |
15974 | } |