Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
f2a663d3 | 71 | #include "elf/mips.h" |
1dc1e798 | 72 | #endif |
f2a663d3 | 73 | |
739708fa | 74 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 75 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
76 | #define ECOFF_DEBUGGING 0 |
77 | #endif | |
78 | ||
22ba90ce ILT |
79 | #include "ecoff.h" |
80 | ||
a8aed9dd | 81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 82 | static char *mips_regmask_frag; |
a8aed9dd | 83 | #endif |
f2a663d3 | 84 | |
3d3c5039 | 85 | #define AT 1 |
cc5703cd | 86 | #define TREG 24 |
9226253a | 87 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
88 | #define KT0 26 |
89 | #define KT1 27 | |
670a50eb | 90 | #define GP 28 |
9226253a ILT |
91 | #define SP 29 |
92 | #define FP 30 | |
3d3c5039 ILT |
93 | #define RA 31 |
94 | ||
cc5703cd ILT |
95 | #define ILLEGAL_REG (32) |
96 | ||
af942793 SS |
97 | /* Allow override of standard little-endian ECOFF format. */ |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
1dc1e798 | 103 | extern int target_big_endian; |
88225433 | 104 | |
7f9880e5 ILT |
105 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
106 | 32 bit ABI. This has no meaning for ECOFF. */ | |
107 | static int mips_64; | |
108 | ||
04cb3372 | 109 | /* The default target format to use. */ |
1dc1e798 KR |
110 | const char * |
111 | mips_target_format () | |
112 | { | |
113 | switch (OUTPUT_FLAVOR) | |
114 | { | |
115 | case bfd_target_aout_flavour: | |
116 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
117 | case bfd_target_ecoff_flavour: | |
af942793 | 118 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 119 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
120 | return (target_big_endian |
121 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
122 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
123 | default: |
124 | abort (); | |
125 | } | |
126 | } | |
04cb3372 | 127 | |
d2c71068 | 128 | /* The name of the readonly data section. */ |
1dc1e798 KR |
129 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
130 | ? ".data" \ | |
131 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
132 | ? ".rdata" \ | |
133 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
134 | ? ".rodata" \ | |
135 | : (abort (), "")) | |
d2c71068 | 136 | |
1aa6938e ILT |
137 | /* These variables are filled in with the masks of registers used. |
138 | The object format code reads them and puts them in the appropriate | |
139 | place. */ | |
140 | unsigned long mips_gprmask; | |
141 | unsigned long mips_cprmask[4]; | |
142 | ||
1051c97f ILT |
143 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
144 | temporarily using .set mipsN). */ | |
8358c818 ILT |
145 | static int mips_isa = -1; |
146 | ||
1051c97f ILT |
147 | /* MIPS ISA we are using for this output file. */ |
148 | static int file_mips_isa; | |
149 | ||
cc5703cd ILT |
150 | /* Whether we are assembling for the mips16 processor. */ |
151 | static int mips16 = -1; | |
152 | ||
8c63448a | 153 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 154 | static int mips_cpu = -1; |
8c63448a | 155 | |
b2b8c24e ILT |
156 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
157 | static int mips_4650 = -1; | |
158 | ||
e532b44c ILT |
159 | /* Whether the 4010 instructions are permitted. */ |
160 | static int mips_4010 = -1; | |
161 | ||
c625fc23 JSC |
162 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
163 | static int mips_4100 = -1; | |
164 | ||
276c2d7d GRK |
165 | /* start-sanitize-r5900 */ |
166 | /* Whether Toshiba r5900 instructions are permitted. */ | |
167 | static int mips_5900 = -1; | |
168 | /* end-sanitize-r5900 */ | |
169 | ||
e532b44c ILT |
170 | /* Whether the processor uses hardware interlocks, and thus does not |
171 | require nops to be inserted. */ | |
172 | static int interlocks = -1; | |
173 | ||
344a8d61 JSC |
174 | /* As with "interlocks" this is used by hardware that has FP |
175 | (co-processor) interlocks. */ | |
efec4a28 | 176 | /* Itbl support may require additional care here. */ |
344a8d61 JSC |
177 | static int cop_interlocks = -1; |
178 | ||
d9aba805 ILT |
179 | /* MIPS PIC level. */ |
180 | ||
181 | enum mips_pic_level | |
182 | { | |
183 | /* Do not generate PIC code. */ | |
184 | NO_PIC, | |
185 | ||
186 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
187 | not sure what it is supposed to do. */ | |
188 | IRIX4_PIC, | |
189 | ||
190 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
191 | SVR4_PIC, | |
192 | ||
193 | /* Generate PIC code without using a global offset table: the data | |
194 | segment has a maximum size of 64K, all data references are off | |
195 | the $gp register, and all text references are PC relative. This | |
196 | is used on some embedded systems. */ | |
197 | EMBEDDED_PIC | |
198 | }; | |
199 | ||
200 | static enum mips_pic_level mips_pic; | |
9226253a | 201 | |
fb251650 ILT |
202 | /* 1 if we should generate 32 bit offsets from the GP register in |
203 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
204 | static int mips_big_got; | |
205 | ||
8ea7f4e8 ILT |
206 | /* 1 if trap instructions should used for overflow rather than break |
207 | instructions. */ | |
208 | static int mips_trap; | |
209 | ||
cc5703cd ILT |
210 | /* 1 if we should autoextend mips16 instructions. */ |
211 | static int mips16_autoextend = 1; | |
212 | ||
3d3c5039 ILT |
213 | static int mips_warn_about_macros; |
214 | static int mips_noreorder; | |
0dd2d296 | 215 | static int mips_any_noreorder; |
3d3c5039 ILT |
216 | static int mips_nomove; |
217 | static int mips_noat; | |
218 | static int mips_nobopt; | |
219 | ||
670a50eb ILT |
220 | /* The size of the small data section. */ |
221 | static int g_switch_value = 8; | |
42562568 ILT |
222 | /* Whether the -G option was used. */ |
223 | static int g_switch_seen = 0; | |
670a50eb | 224 | |
3d3c5039 ILT |
225 | #define N_RMASK 0xc4 |
226 | #define N_VFP 0xd4 | |
227 | ||
d8a1c247 KR |
228 | /* If we can determine in advance that GP optimization won't be |
229 | possible, we can skip the relaxation stuff that tries to produce | |
230 | GP-relative references. This makes delay slot optimization work | |
231 | better. | |
232 | ||
233 | This function can only provide a guess, but it seems to work for | |
234 | gcc output. If it guesses wrong, the only loss should be in | |
235 | efficiency; it shouldn't introduce any bugs. | |
236 | ||
237 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
238 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
239 | static int nopic_need_relax PARAMS ((symbolS *)); | |
240 | ||
3d3c5039 ILT |
241 | /* handle of the OPCODE hash table */ |
242 | static struct hash_control *op_hash = NULL; | |
243 | ||
cc5703cd ILT |
244 | /* The opcode hash table we use for the mips16. */ |
245 | static struct hash_control *mips16_op_hash = NULL; | |
246 | ||
3d3c5039 ILT |
247 | /* This array holds the chars that always start a comment. If the |
248 | pre-processor is disabled, these aren't very useful */ | |
249 | const char comment_chars[] = "#"; | |
250 | ||
251 | /* This array holds the chars that only start a comment at the beginning of | |
252 | a line. If the line seems to have the form '# 123 filename' | |
253 | .line and .file directives will appear in the pre-processed output */ | |
254 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
255 | first line of the input file. This is because the compiler outputs | |
256 | #NO_APP at the beginning of its output. */ | |
257 | /* Also note that C style comments are always supported. */ | |
258 | const char line_comment_chars[] = "#"; | |
259 | ||
260 | /* This array holds machine specific line separator characters. */ | |
261 | const char line_separator_chars[] = ""; | |
262 | ||
263 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
264 | const char EXP_CHARS[] = "eE"; | |
265 | ||
266 | /* Chars that mean this number is a floating point constant */ | |
267 | /* As in 0f12.456 */ | |
268 | /* or 0d1.2345e12 */ | |
269 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
270 | ||
271 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
272 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
273 | but nothing is ideal around here. | |
274 | */ | |
275 | ||
670a50eb | 276 | static char *insn_error; |
3d3c5039 | 277 | |
3d3c5039 | 278 | static int auto_align = 1; |
becfe05e | 279 | |
9226253a ILT |
280 | /* When outputting SVR4 PIC code, the assembler needs to know the |
281 | offset in the stack frame from which to restore the $gp register. | |
282 | This is set by the .cprestore pseudo-op, and saved in this | |
283 | variable. */ | |
0dd2d296 ILT |
284 | static offsetT mips_cprestore_offset = -1; |
285 | ||
286 | /* This is the register which holds the stack frame, as set by the | |
287 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
288 | static int mips_frame_reg = SP; | |
9226253a | 289 | |
becfe05e ILT |
290 | /* To output NOP instructions correctly, we need to keep information |
291 | about the previous two instructions. */ | |
292 | ||
0aa07269 ILT |
293 | /* Whether we are optimizing. The default value of 2 means to remove |
294 | unneeded NOPs and swap branch instructions when possible. A value | |
295 | of 1 means to not swap branches. A value of 0 means to always | |
296 | insert NOPs. */ | |
297 | static int mips_optimize = 2; | |
4e95866e | 298 | |
22ba90ce ILT |
299 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
300 | equivalent to seeing no -g option at all. */ | |
301 | static int mips_debug = 0; | |
302 | ||
becfe05e ILT |
303 | /* The previous instruction. */ |
304 | static struct mips_cl_insn prev_insn; | |
305 | ||
306 | /* The instruction before prev_insn. */ | |
307 | static struct mips_cl_insn prev_prev_insn; | |
308 | ||
309 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
310 | point the insn_mo field at this dummy integer. */ | |
311 | static const struct mips_opcode dummy_opcode = { 0 }; | |
312 | ||
313 | /* Non-zero if prev_insn is valid. */ | |
314 | static int prev_insn_valid; | |
315 | ||
316 | /* The frag for the previous instruction. */ | |
317 | static struct frag *prev_insn_frag; | |
318 | ||
319 | /* The offset into prev_insn_frag for the previous instruction. */ | |
320 | static long prev_insn_where; | |
321 | ||
a677feeb ILT |
322 | /* The reloc type for the previous instruction, if any. */ |
323 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
324 | ||
becfe05e ILT |
325 | /* The reloc for the previous instruction, if any. */ |
326 | static fixS *prev_insn_fixp; | |
327 | ||
328 | /* Non-zero if the previous instruction was in a delay slot. */ | |
329 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
330 | |
331 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
332 | static int prev_insn_unreordered; | |
333 | ||
cc5703cd ILT |
334 | /* Non-zero if the previous instruction uses an extend opcode (if |
335 | mips16). */ | |
336 | static int prev_insn_extended; | |
337 | ||
4e95866e ILT |
338 | /* Non-zero if the previous previous instruction was in a .set |
339 | noreorder. */ | |
340 | static int prev_prev_insn_unreordered; | |
867a58b3 | 341 | |
4a1cb507 ILT |
342 | /* If this is set, it points to a frag holding nop instructions which |
343 | were inserted before the start of a noreorder section. If those | |
344 | nops turn out to be unnecessary, the size of the frag can be | |
345 | decreased. */ | |
346 | static fragS *prev_nop_frag; | |
347 | ||
348 | /* The number of nop instructions we created in prev_nop_frag. */ | |
349 | static int prev_nop_frag_holds; | |
350 | ||
351 | /* The number of nop instructions that we know we need in | |
352 | prev_nop_frag. */ | |
353 | static int prev_nop_frag_required; | |
354 | ||
355 | /* The number of instructions we've seen since prev_nop_frag. */ | |
356 | static int prev_nop_frag_since; | |
357 | ||
867a58b3 ILT |
358 | /* For ECOFF and ELF, relocations against symbols are done in two |
359 | parts, with a HI relocation and a LO relocation. Each relocation | |
360 | has only 16 bits of space to store an addend. This means that in | |
361 | order for the linker to handle carries correctly, it must be able | |
362 | to locate both the HI and the LO relocation. This means that the | |
363 | relocations must appear in order in the relocation table. | |
364 | ||
365 | In order to implement this, we keep track of each unmatched HI | |
366 | relocation. We then sort them so that they immediately precede the | |
367 | corresponding LO relocation. */ | |
368 | ||
369 | struct mips_hi_fixup | |
370 | { | |
371 | /* Next HI fixup. */ | |
372 | struct mips_hi_fixup *next; | |
373 | /* This fixup. */ | |
374 | fixS *fixp; | |
375 | /* The section this fixup is in. */ | |
376 | segT seg; | |
377 | }; | |
378 | ||
379 | /* The list of unmatched HI relocs. */ | |
380 | ||
381 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
382 | |
383 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
384 | ||
385 | #define X ILLEGAL_REG | |
386 | static const int mips32_to_16_reg_map[] = | |
387 | { | |
388 | X, X, 2, 3, 4, 5, 6, 7, | |
389 | X, X, X, X, X, X, X, X, | |
390 | 0, 1, X, X, X, X, X, X, | |
391 | X, X, X, X, X, X, X, X | |
392 | }; | |
393 | #undef X | |
394 | ||
395 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
396 | ||
397 | static const int mips16_to_32_reg_map[] = | |
398 | { | |
399 | 16, 17, 2, 3, 4, 5, 6, 7 | |
400 | }; | |
3d3c5039 | 401 | \f |
0dd2d296 ILT |
402 | /* Since the MIPS does not have multiple forms of PC relative |
403 | instructions, we do not have to do relaxing as is done on other | |
404 | platforms. However, we do have to handle GP relative addressing | |
405 | correctly, which turns out to be a similar problem. | |
406 | ||
407 | Every macro that refers to a symbol can occur in (at least) two | |
408 | forms, one with GP relative addressing and one without. For | |
409 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 410 | a macro instruction like this: |
0dd2d296 ILT |
411 | lw $4,i |
412 | If i can be addressed off the GP register (this is true if it is in | |
413 | the .sbss or .sdata section, or if it is known to be smaller than | |
414 | the -G argument) this will generate the following instruction: | |
415 | lw $4,i($gp) | |
416 | This instruction will use a GPREL reloc. If i can not be addressed | |
417 | off the GP register, the following instruction sequence will be used: | |
418 | lui $at,i | |
419 | lw $4,i($at) | |
420 | In this case the first instruction will have a HI16 reloc, and the | |
421 | second reloc will have a LO16 reloc. Both relocs will be against | |
422 | the symbol i. | |
423 | ||
424 | The issue here is that we may not know whether i is GP addressable | |
425 | until after we see the instruction that uses it. Therefore, we | |
426 | want to be able to choose the final instruction sequence only at | |
427 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 428 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
429 | end of assembly. |
430 | ||
431 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
432 | addressing in quite the same way, but the issue still arises as |
433 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
434 | |
435 | We handle these issues by actually generating both possible | |
436 | instruction sequences. The longer one is put in a frag_var with | |
437 | type rs_machine_dependent. We encode what to do with the frag in | |
438 | the subtype field. We encode (1) the number of existing bytes to | |
439 | replace, (2) the number of new bytes to use, (3) the offset from | |
440 | the start of the existing bytes to the first reloc we must generate | |
441 | (that is, the offset is applied from the start of the existing | |
442 | bytes after they are replaced by the new bytes, if any), (4) the | |
443 | offset from the start of the existing bytes to the second reloc, | |
444 | (5) whether a third reloc is needed (the third reloc is always four | |
445 | bytes after the second reloc), and (6) whether to warn if this | |
446 | variant is used (this is sometimes needed if .set nomacro or .set | |
447 | noat is in effect). All these numbers are reasonably small. | |
448 | ||
449 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
450 | ensure that delay slots are handled correctly. Fortunately, there |
451 | are a limited number of cases. When the second instruction | |
452 | sequence is generated, append_insn is directed to maintain the | |
453 | existing delay slot information, so it continues to apply to any | |
454 | code after the second instruction sequence. This means that the | |
455 | second instruction sequence must not impose any requirements not | |
456 | required by the first instruction sequence. | |
0dd2d296 ILT |
457 | |
458 | These variant frags are then handled in functions called by the | |
459 | machine independent code. md_estimate_size_before_relax returns | |
460 | the final size of the frag. md_convert_frag sets up the final form | |
461 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
462 | one if needed. */ | |
463 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
464 | ((relax_substateT) \ | |
cc5703cd | 465 | (((old) << 23) \ |
0dd2d296 ILT |
466 | | ((new) << 16) \ |
467 | | (((reloc1) + 64) << 9) \ | |
468 | | (((reloc2) + 64) << 2) \ | |
469 | | ((reloc3) ? (1 << 1) : 0) \ | |
470 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
471 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
472 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
473 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
474 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
475 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
476 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
477 | |
478 | /* For mips16 code, we use an entirely different form of relaxation. | |
479 | mips16 supports two versions of most instructions which take | |
480 | immediate values: a small one which takes some small value, and a | |
481 | larger one which takes a 16 bit value. Since branches also follow | |
482 | this pattern, relaxing these values is required. | |
483 | ||
484 | We can assemble both mips16 and normal MIPS code in a single | |
485 | object. Therefore, we need to support this type of relaxation at | |
486 | the same time that we support the relaxation described above. We | |
487 | use the high bit of the subtype field to distinguish these cases. | |
488 | ||
a677feeb ILT |
489 | The information we store for this type of relaxation is the |
490 | argument code found in the opcode file for this relocation, whether | |
491 | the user explicitly requested a small or extended form, and whether | |
492 | the relocation is in a jump or jal delay slot. That tells us the | |
493 | size of the value, and how it should be stored. We also store | |
494 | whether the fragment is considered to be extended or not. We also | |
495 | store whether this is known to be a branch to a different section, | |
496 | whether we have tried to relax this frag yet, and whether we have | |
497 | ever extended a PC relative fragment because of a shift count. */ | |
498 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
499 | (0x80000000 \ | |
500 | | ((type) & 0xff) \ | |
501 | | ((small) ? 0x100 : 0) \ | |
502 | | ((ext) ? 0x200 : 0) \ | |
503 | | ((dslot) ? 0x400 : 0) \ | |
504 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
505 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
506 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
507 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
508 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
509 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
510 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
511 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
512 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
513 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
514 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
515 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
516 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 517 | \f |
3d3c5039 ILT |
518 | /* Prototypes for static functions. */ |
519 | ||
520 | #ifdef __STDC__ | |
521 | #define internalError() \ | |
522 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
523 | #else | |
524 | #define internalError() as_fatal ("MIPS internal Error"); | |
525 | #endif | |
526 | ||
cc5703cd ILT |
527 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
528 | ||
becfe05e | 529 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 530 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 531 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
532 | static void append_insn PARAMS ((char *place, |
533 | struct mips_cl_insn * ip, | |
670a50eb | 534 | expressionS * p, |
867a58b3 ILT |
535 | bfd_reloc_code_real_type r, |
536 | boolean)); | |
4a1cb507 | 537 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 538 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 539 | #ifdef USE_STDARG |
0dd2d296 | 540 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
541 | const char *name, const char *fmt, |
542 | ...)); | |
c625fc23 JSC |
543 | #else |
544 | static void macro_build (); | |
545 | #endif | |
cc5703cd ILT |
546 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
547 | const char *, const char *, | |
548 | va_list)); | |
0dd2d296 ILT |
549 | static void macro_build_lui PARAMS ((char *place, int *counter, |
550 | expressionS * ep, int regnum)); | |
6e8dda9c | 551 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 552 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 553 | expressionS *)); |
d8a1c247 | 554 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 555 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 556 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 557 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
558 | #ifdef LOSING_COMPILER |
559 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
560 | #endif | |
670a50eb | 561 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 562 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
563 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
564 | boolean, boolean, unsigned long *, | |
565 | boolean *, unsigned short *)); | |
670a50eb ILT |
566 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
567 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 568 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 569 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
570 | static void s_align PARAMS ((int)); |
571 | static void s_change_sec PARAMS ((int)); | |
572 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 573 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 574 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
575 | static void s_option PARAMS ((int)); |
576 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
577 | static void s_abicalls PARAMS ((int)); |
578 | static void s_cpload PARAMS ((int)); | |
579 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
580 | static void s_gpword PARAMS ((int)); |
581 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 582 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
583 | static void md_obj_begin PARAMS ((void)); |
584 | static void md_obj_end PARAMS ((void)); | |
585 | static long get_number PARAMS ((void)); | |
586 | static void s_ent PARAMS ((int)); | |
587 | static void s_mipsend PARAMS ((int)); | |
588 | static void s_file PARAMS ((int)); | |
cc5703cd | 589 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
590 | \f |
591 | /* Pseudo-op table. | |
592 | ||
593 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
594 | should be defined here, but are currently unsupported: .alias, | |
595 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
596 | ||
597 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
598 | specific to the type of debugging information being generated, and | |
599 | should be defined by the object format: .aent, .begin, .bend, | |
600 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
601 | .vreg. | |
602 | ||
603 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
604 | not MIPS CPU specific, but are also not specific to the object file | |
605 | format. This file is probably the best place to define them, but | |
606 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
607 | .struct, .weakext. */ | |
608 | ||
739708fa | 609 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 610 | { |
670a50eb ILT |
611 | /* MIPS specific pseudo-ops. */ |
612 | {"option", s_option, 0}, | |
613 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
614 | {"rdata", s_change_sec, 'r'}, |
615 | {"sdata", s_change_sec, 's'}, | |
616 | {"livereg", s_ignore, 0}, | |
739708fa KR |
617 | {"abicalls", s_abicalls, 0}, |
618 | {"cpload", s_cpload, 0}, | |
619 | {"cprestore", s_cprestore, 0}, | |
620 | {"gpword", s_gpword, 0}, | |
621 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 622 | {"insn", s_insn, 0}, |
3d3c5039 | 623 | |
670a50eb | 624 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 625 | chips. */ |
739708fa | 626 | {"asciiz", stringer, 1}, |
670a50eb ILT |
627 | {"bss", s_change_sec, 'b'}, |
628 | {"err", s_err, 0}, | |
629 | {"half", s_cons, 1}, | |
52aa70b5 | 630 | {"dword", s_cons, 3}, |
3d3c5039 | 631 | |
670a50eb | 632 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 633 | here for one reason or another. */ |
670a50eb ILT |
634 | {"align", s_align, 0}, |
635 | {"byte", s_cons, 0}, | |
636 | {"data", s_change_sec, 'd'}, | |
becfe05e | 637 | {"double", s_float_cons, 'd'}, |
becfe05e | 638 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
639 | {"globl", s_mips_globl, 0}, |
640 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
641 | {"hword", s_cons, 1}, |
642 | {"int", s_cons, 2}, | |
643 | {"long", s_cons, 2}, | |
644 | {"octa", s_cons, 4}, | |
645 | {"quad", s_cons, 3}, | |
646 | {"short", s_cons, 1}, | |
647 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
648 | {"text", s_change_sec, 't'}, |
649 | {"word", s_cons, 2}, | |
739708fa KR |
650 | { 0 }, |
651 | }; | |
3d3c5039 | 652 | |
739708fa | 653 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 654 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 655 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 656 | {"aent", s_ent, 1}, |
9226253a | 657 | {"bgnb", s_ignore, 0}, |
670a50eb | 658 | {"end", s_mipsend, 0}, |
9226253a | 659 | {"endb", s_ignore, 0}, |
670a50eb ILT |
660 | {"ent", s_ent, 0}, |
661 | {"file", s_file, 0}, | |
662 | {"fmask", s_ignore, 'F'}, | |
663 | {"frame", s_ignore, 0}, | |
664 | {"loc", s_ignore, 0}, | |
665 | {"mask", s_ignore, 'R'}, | |
666 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
667 | { 0 }, |
668 | }; | |
61420a20 | 669 | |
739708fa KR |
670 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
671 | ||
672 | void | |
673 | mips_pop_insert () | |
674 | { | |
675 | pop_insert (mips_pseudo_table); | |
676 | if (! ECOFF_DEBUGGING) | |
677 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 678 | } |
3d3c5039 | 679 | \f |
fbcfacb7 ILT |
680 | /* Symbols labelling the current insn. */ |
681 | ||
682 | struct insn_label_list | |
683 | { | |
684 | struct insn_label_list *next; | |
685 | symbolS *label; | |
686 | }; | |
687 | ||
688 | static struct insn_label_list *insn_labels; | |
689 | static struct insn_label_list *free_insn_labels; | |
690 | ||
691 | static void mips_clear_insn_labels PARAMS ((void)); | |
692 | ||
693 | static inline void | |
694 | mips_clear_insn_labels () | |
695 | { | |
696 | register struct insn_label_list **pl; | |
697 | ||
698 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
699 | ; | |
700 | *pl = insn_labels; | |
701 | insn_labels = NULL; | |
702 | } | |
703 | \f | |
3d3c5039 ILT |
704 | static char *expr_end; |
705 | ||
867a58b3 ILT |
706 | /* Expressions which appear in instructions. These are set by |
707 | mips_ip. */ | |
708 | ||
3d3c5039 ILT |
709 | static expressionS imm_expr; |
710 | static expressionS offset_expr; | |
867a58b3 ILT |
711 | |
712 | /* Relocs associated with imm_expr and offset_expr. */ | |
713 | ||
3d3c5039 ILT |
714 | static bfd_reloc_code_real_type imm_reloc; |
715 | static bfd_reloc_code_real_type offset_reloc; | |
716 | ||
867a58b3 ILT |
717 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
718 | ||
719 | static boolean imm_unmatched_hi; | |
720 | ||
8728fa92 ILT |
721 | /* These are set by mips16_ip if an explicit extension is used. */ |
722 | ||
723 | static boolean mips16_small, mips16_ext; | |
724 | ||
3d3c5039 ILT |
725 | /* |
726 | * This function is called once, at assembler startup time. It should | |
727 | * set up all the tables, etc. that the MD part of the assembler will need. | |
728 | */ | |
729 | void | |
670a50eb | 730 | md_begin () |
3d3c5039 | 731 | { |
0dd2d296 | 732 | boolean ok = false; |
604633ae | 733 | register const char *retval = NULL; |
670a50eb | 734 | register unsigned int i = 0; |
3d3c5039 | 735 | |
8358c818 ILT |
736 | if (mips_isa == -1) |
737 | { | |
8c63448a ILT |
738 | const char *cpu; |
739 | char *a = NULL; | |
740 | ||
741 | cpu = TARGET_CPU; | |
742 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
743 | { | |
744 | a = xmalloc (sizeof TARGET_CPU); | |
745 | strcpy (a, TARGET_CPU); | |
746 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
747 | cpu = a; | |
748 | } | |
749 | ||
750 | if (strcmp (cpu, "mips") == 0) | |
751 | { | |
752 | mips_isa = 1; | |
4bb0cc41 ILT |
753 | if (mips_cpu == -1) |
754 | mips_cpu = 3000; | |
8c63448a ILT |
755 | } |
756 | else if (strcmp (cpu, "r6000") == 0 | |
757 | || strcmp (cpu, "mips2") == 0) | |
758 | { | |
759 | mips_isa = 2; | |
4bb0cc41 ILT |
760 | if (mips_cpu == -1) |
761 | mips_cpu = 6000; | |
8c63448a ILT |
762 | } |
763 | else if (strcmp (cpu, "mips64") == 0 | |
764 | || strcmp (cpu, "r4000") == 0 | |
765 | || strcmp (cpu, "mips3") == 0) | |
766 | { | |
767 | mips_isa = 3; | |
4bb0cc41 ILT |
768 | if (mips_cpu == -1) |
769 | mips_cpu = 4000; | |
8c63448a ILT |
770 | } |
771 | else if (strcmp (cpu, "r4400") == 0) | |
772 | { | |
773 | mips_isa = 3; | |
4bb0cc41 ILT |
774 | if (mips_cpu == -1) |
775 | mips_cpu = 4400; | |
8c63448a ILT |
776 | } |
777 | else if (strcmp (cpu, "mips64orion") == 0 | |
778 | || strcmp (cpu, "r4600") == 0) | |
779 | { | |
780 | mips_isa = 3; | |
4bb0cc41 ILT |
781 | if (mips_cpu == -1) |
782 | mips_cpu = 4600; | |
8c63448a | 783 | } |
b2b8c24e ILT |
784 | else if (strcmp (cpu, "r4650") == 0) |
785 | { | |
786 | mips_isa = 3; | |
787 | if (mips_cpu == -1) | |
788 | mips_cpu = 4650; | |
789 | if (mips_4650 == -1) | |
790 | mips_4650 = 1; | |
791 | } | |
c625fc23 JSC |
792 | else if (strcmp (cpu, "mips64vr4300") == 0) |
793 | { | |
794 | mips_isa = 3; | |
795 | if (mips_cpu == -1) | |
796 | mips_cpu = 4300; | |
797 | } | |
798 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
799 | { | |
800 | mips_isa = 3; | |
801 | if (mips_cpu == -1) | |
802 | mips_cpu = 4100; | |
803 | if (mips_4100 == -1) | |
804 | mips_4100 = 1; | |
805 | } | |
e532b44c ILT |
806 | else if (strcmp (cpu, "r4010") == 0) |
807 | { | |
808 | mips_isa = 2; | |
809 | if (mips_cpu == -1) | |
810 | mips_cpu = 4010; | |
811 | if (mips_4010 == -1) | |
812 | mips_4010 = 1; | |
813 | } | |
517078c1 ILT |
814 | else if (strcmp (cpu, "r5000") == 0 |
815 | || strcmp (cpu, "mips64vr5000") == 0) | |
816 | { | |
817 | mips_isa = 4; | |
818 | if (mips_cpu == -1) | |
819 | mips_cpu = 5000; | |
820 | } | |
276c2d7d GRK |
821 | /* start-sanitize-r5900 */ |
822 | else if (strcmp (cpu, "r5900") == 0 | |
823 | || strcmp (cpu, "mips64vr5900") == 0 | |
824 | || strcmp (cpu, "mips64vr5900el") == 0) | |
825 | { | |
826 | mips_isa = 3; | |
827 | if (mips_cpu == -1) | |
828 | mips_cpu = 5900; | |
16262668 | 829 | if (mips_5900 == -1) |
276c2d7d GRK |
830 | mips_5900 = 1; |
831 | } | |
832 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
833 | else if (strcmp (cpu, "r8000") == 0 |
834 | || strcmp (cpu, "mips4") == 0) | |
835 | { | |
836 | mips_isa = 4; | |
837 | if (mips_cpu == -1) | |
838 | mips_cpu = 8000; | |
839 | } | |
840 | else if (strcmp (cpu, "r10000") == 0) | |
841 | { | |
842 | mips_isa = 4; | |
843 | if (mips_cpu == -1) | |
844 | mips_cpu = 10000; | |
845 | } | |
cc5703cd ILT |
846 | else if (strcmp (cpu, "mips16") == 0) |
847 | { | |
848 | mips_isa = 3; | |
849 | if (mips_cpu == -1) | |
850 | mips_cpu = 0; /* FIXME */ | |
851 | } | |
8358c818 | 852 | else |
8c63448a ILT |
853 | { |
854 | mips_isa = 1; | |
4bb0cc41 ILT |
855 | if (mips_cpu == -1) |
856 | mips_cpu = 3000; | |
8c63448a ILT |
857 | } |
858 | ||
859 | if (a != NULL) | |
860 | free (a); | |
8358c818 ILT |
861 | } |
862 | ||
cc5703cd ILT |
863 | if (mips16 < 0) |
864 | { | |
865 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
866 | mips16 = 1; | |
867 | else | |
868 | mips16 = 0; | |
869 | } | |
870 | ||
b2b8c24e ILT |
871 | if (mips_4650 < 0) |
872 | mips_4650 = 0; | |
873 | ||
e532b44c ILT |
874 | if (mips_4010 < 0) |
875 | mips_4010 = 0; | |
876 | ||
c625fc23 JSC |
877 | if (mips_4100 < 0) |
878 | mips_4100 = 0; | |
879 | ||
276c2d7d GRK |
880 | /* start-sanitize-r5900 */ |
881 | if (mips_5900 < 0) | |
882 | mips_5900 = 0; | |
883 | /* end-sanitize-r5900 */ | |
884 | ||
c36a90ef | 885 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
886 | interlocks = 1; |
887 | else | |
888 | interlocks = 0; | |
889 | ||
efec4a28 | 890 | /* Itbl support may require additional care here. */ |
ca296aab | 891 | if (mips_cpu == 4300) |
344a8d61 JSC |
892 | cop_interlocks = 1; |
893 | else | |
894 | cop_interlocks = 0; | |
895 | ||
8ea7f4e8 ILT |
896 | if (mips_isa < 2 && mips_trap) |
897 | as_bad ("trap exception not supported at ISA 1"); | |
898 | ||
97f99d11 ILT |
899 | switch (mips_isa) |
900 | { | |
901 | case 1: | |
902 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
903 | break; | |
904 | case 2: | |
905 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
906 | break; | |
907 | case 3: | |
908 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
909 | break; | |
d8a1c247 KR |
910 | case 4: |
911 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
912 | break; | |
97f99d11 ILT |
913 | } |
914 | if (! ok) | |
915 | as_warn ("Could not set architecture and machine"); | |
916 | ||
1051c97f ILT |
917 | file_mips_isa = mips_isa; |
918 | ||
13fe1379 ILT |
919 | op_hash = hash_new (); |
920 | ||
670a50eb ILT |
921 | for (i = 0; i < NUMOPCODES;) |
922 | { | |
923 | const char *name = mips_opcodes[i].name; | |
924 | ||
604633ae | 925 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 926 | if (retval != NULL) |
670a50eb ILT |
927 | { |
928 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
929 | mips_opcodes[i].name, retval); | |
930 | as_fatal ("Broken assembler. No assembly attempted."); | |
931 | } | |
932 | do | |
933 | { | |
8358c818 ILT |
934 | if (mips_opcodes[i].pinfo != INSN_MACRO |
935 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
936 | != mips_opcodes[i].match)) | |
670a50eb ILT |
937 | { |
938 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
939 | mips_opcodes[i].name, mips_opcodes[i].args); | |
940 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 941 | } |
670a50eb ILT |
942 | ++i; |
943 | } | |
944 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
945 | } |
946 | ||
cc5703cd ILT |
947 | mips16_op_hash = hash_new (); |
948 | ||
949 | i = 0; | |
950 | while (i < bfd_mips16_num_opcodes) | |
951 | { | |
952 | const char *name = mips16_opcodes[i].name; | |
953 | ||
954 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
955 | if (retval != NULL) | |
956 | as_fatal ("internal error: can't hash `%s': %s\n", | |
957 | mips16_opcodes[i].name, retval); | |
958 | do | |
959 | { | |
960 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
961 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
962 | != mips16_opcodes[i].match)) | |
963 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
964 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
965 | ++i; | |
966 | } | |
967 | while (i < bfd_mips16_num_opcodes | |
968 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
969 | } | |
970 | ||
ebf28372 ILT |
971 | /* We add all the general register names to the symbol table. This |
972 | helps us detect invalid uses of them. */ | |
973 | for (i = 0; i < 32; i++) | |
974 | { | |
975 | char buf[5]; | |
976 | ||
977 | sprintf (buf, "$%d", i); | |
978 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
979 | &zero_address_frag)); | |
980 | } | |
981 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
982 | &zero_address_frag)); | |
983 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
984 | &zero_address_frag)); | |
985 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
986 | &zero_address_frag)); | |
987 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
988 | &zero_address_frag)); | |
989 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
990 | &zero_address_frag)); | |
991 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
992 | &zero_address_frag)); | |
993 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
994 | &zero_address_frag)); | |
995 | ||
4a1cb507 | 996 | mips_no_prev_insn (false); |
becfe05e | 997 | |
1aa6938e ILT |
998 | mips_gprmask = 0; |
999 | mips_cprmask[0] = 0; | |
1000 | mips_cprmask[1] = 0; | |
1001 | mips_cprmask[2] = 0; | |
1002 | mips_cprmask[3] = 0; | |
1003 | ||
8358c818 | 1004 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1005 | record_alignment (text_section, 2); |
8358c818 | 1006 | |
1dc1e798 KR |
1007 | if (USE_GLOBAL_POINTER_OPT) |
1008 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1009 | |
1dc1e798 KR |
1010 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1011 | { | |
08e17202 ILT |
1012 | /* On a native system, sections must be aligned to 16 byte |
1013 | boundaries. When configured for an embedded ELF target, we | |
1014 | don't bother. */ | |
1015 | if (strcmp (TARGET_OS, "elf") != 0) | |
1016 | { | |
1017 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1018 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1019 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1020 | } | |
1dc1e798 KR |
1021 | |
1022 | /* Create a .reginfo section for register masks and a .mdebug | |
1023 | section for debugging information. */ | |
1024 | { | |
1025 | segT seg; | |
1026 | subsegT subseg; | |
b3a64736 | 1027 | flagword flags; |
1dc1e798 KR |
1028 | segT sec; |
1029 | ||
1030 | seg = now_seg; | |
1031 | subseg = now_subseg; | |
1dc1e798 | 1032 | |
b3a64736 ILT |
1033 | /* The ABI says this section should be loaded so that the |
1034 | running program can access it. However, we don't load it | |
1035 | if we are configured for an embedded target */ | |
1036 | flags = SEC_READONLY | SEC_DATA; | |
1037 | if (strcmp (TARGET_OS, "elf") != 0) | |
1038 | flags |= SEC_ALLOC | SEC_LOAD; | |
1039 | ||
87178180 ILT |
1040 | if (! mips_64) |
1041 | { | |
1042 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1043 | |
b3a64736 ILT |
1044 | |
1045 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1046 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1047 | ||
f2a663d3 | 1048 | #ifdef OBJ_ELF |
87178180 | 1049 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1050 | #endif |
87178180 ILT |
1051 | } |
1052 | else | |
1053 | { | |
1054 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1055 | .reginfo section. */ | |
1056 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1057 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1058 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1059 | ||
1060 | #ifdef OBJ_ELF | |
1061 | /* Set up the option header. */ | |
1062 | { | |
1063 | Elf_Internal_Options opthdr; | |
1064 | char *f; | |
1065 | ||
1066 | opthdr.kind = ODK_REGINFO; | |
1067 | opthdr.size = (sizeof (Elf_External_Options) | |
1068 | + sizeof (Elf64_External_RegInfo)); | |
1069 | opthdr.section = 0; | |
1070 | opthdr.info = 0; | |
1071 | f = frag_more (sizeof (Elf_External_Options)); | |
1072 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1073 | (Elf_External_Options *) f); | |
1074 | ||
1075 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1076 | } | |
1077 | #endif | |
1078 | } | |
f2a663d3 | 1079 | |
739708fa KR |
1080 | if (ECOFF_DEBUGGING) |
1081 | { | |
1082 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1083 | (void) bfd_set_section_flags (stdoutput, sec, | |
1084 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1085 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1086 | } | |
0dd2d296 | 1087 | |
1dc1e798 KR |
1088 | subseg_set (seg, subseg); |
1089 | } | |
1090 | } | |
f2a663d3 | 1091 | |
739708fa KR |
1092 | if (! ECOFF_DEBUGGING) |
1093 | md_obj_begin (); | |
3d3c5039 ILT |
1094 | } |
1095 | ||
1096 | void | |
13fe1379 | 1097 | md_mips_end () |
3d3c5039 | 1098 | { |
739708fa KR |
1099 | if (! ECOFF_DEBUGGING) |
1100 | md_obj_end (); | |
3d3c5039 ILT |
1101 | } |
1102 | ||
1103 | void | |
670a50eb ILT |
1104 | md_assemble (str) |
1105 | char *str; | |
3d3c5039 | 1106 | { |
670a50eb | 1107 | struct mips_cl_insn insn; |
3d3c5039 | 1108 | |
5ac34ac3 | 1109 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1110 | imm_reloc = BFD_RELOC_UNUSED; |
1111 | imm_unmatched_hi = false; | |
5ac34ac3 | 1112 | offset_expr.X_op = O_absent; |
867a58b3 | 1113 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1114 | |
cc5703cd ILT |
1115 | if (mips16) |
1116 | mips16_ip (str, &insn); | |
1117 | else | |
efec4a28 | 1118 | { |
9218cee0 | 1119 | mips_ip (str, &insn); |
efec4a28 DP |
1120 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1121 | str, insn.insn_opcode)); | |
1122 | } | |
cc5703cd | 1123 | |
670a50eb ILT |
1124 | if (insn_error) |
1125 | { | |
1126 | as_bad ("%s `%s'", insn_error, str); | |
1127 | return; | |
1128 | } | |
cc5703cd | 1129 | |
670a50eb ILT |
1130 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1131 | { | |
cc5703cd ILT |
1132 | if (mips16) |
1133 | mips16_macro (&insn); | |
1134 | else | |
1135 | macro (&insn); | |
3d3c5039 | 1136 | } |
670a50eb ILT |
1137 | else |
1138 | { | |
5ac34ac3 | 1139 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1140 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1141 | imm_unmatched_hi); | |
5ac34ac3 | 1142 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1143 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1144 | else |
867a58b3 | 1145 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1146 | } |
1147 | } | |
1148 | ||
cc5703cd ILT |
1149 | /* See whether instruction IP reads register REG. CLASS is the type |
1150 | of register. */ | |
becfe05e ILT |
1151 | |
1152 | static int | |
cc5703cd | 1153 | insn_uses_reg (ip, reg, class) |
becfe05e | 1154 | struct mips_cl_insn *ip; |
604633ae | 1155 | unsigned int reg; |
cc5703cd | 1156 | enum mips_regclass class; |
becfe05e | 1157 | { |
cc5703cd ILT |
1158 | if (class == MIPS16_REG) |
1159 | { | |
1160 | assert (mips16); | |
1161 | reg = mips16_to_32_reg_map[reg]; | |
1162 | class = MIPS_GR_REG; | |
1163 | } | |
1164 | ||
becfe05e | 1165 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1166 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1167 | return 0; |
1168 | ||
cc5703cd | 1169 | if (class == MIPS_FP_REG) |
becfe05e | 1170 | { |
cc5703cd | 1171 | assert (! mips16); |
becfe05e ILT |
1172 | /* If we are called with either $f0 or $f1, we must check $f0. |
1173 | This is not optimal, because it will introduce an unnecessary | |
1174 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1175 | need to distinguish reading both $f0 and $f1 or just one of | |
1176 | them. Note that we don't have to check the other way, | |
1177 | because there is no instruction that sets both $f0 and $f1 | |
1178 | and requires a delay. */ | |
1179 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1180 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1181 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1182 | return 1; |
1183 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1184 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1185 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1186 | return 1; |
1187 | } | |
cc5703cd | 1188 | else if (! mips16) |
becfe05e ILT |
1189 | { |
1190 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1191 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1192 | return 1; | |
1193 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1194 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1195 | return 1; | |
1196 | } | |
cc5703cd ILT |
1197 | else |
1198 | { | |
1199 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1200 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1201 | & MIPS16OP_MASK_RX)] | |
1202 | == reg)) | |
cc5703cd ILT |
1203 | return 1; |
1204 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1205 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1206 | & MIPS16OP_MASK_RY)] | |
1207 | == reg)) | |
cc5703cd ILT |
1208 | return 1; |
1209 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1210 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1211 | & MIPS16OP_MASK_MOVE32Z)] | |
1212 | == reg)) | |
cc5703cd ILT |
1213 | return 1; |
1214 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1215 | return 1; | |
1216 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1217 | return 1; | |
1218 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1219 | return 1; | |
1220 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1221 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1222 | & MIPS16OP_MASK_REGR32) == reg) | |
1223 | return 1; | |
1224 | } | |
becfe05e ILT |
1225 | |
1226 | return 0; | |
1227 | } | |
1228 | ||
fb251650 ILT |
1229 | /* This function returns true if modifying a register requires a |
1230 | delay. */ | |
1231 | ||
1232 | static int | |
1233 | reg_needs_delay (reg) | |
1234 | int reg; | |
1235 | { | |
1236 | unsigned long prev_pinfo; | |
1237 | ||
1238 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1239 | if (! mips_noreorder | |
1240 | && mips_isa < 4 | |
1241 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1242 | || (mips_isa < 2 | |
1243 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1244 | { | |
1245 | /* A load from a coprocessor or from memory. All load | |
1246 | delays delay the use of general register rt for one | |
1247 | instruction on the r3000. The r6000 and r4000 use | |
1248 | interlocks. */ | |
efec4a28 | 1249 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1250 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1251 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1252 | return 1; | |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
0dd2d296 ILT |
1258 | /* Output an instruction. PLACE is where to put the instruction; if |
1259 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1260 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1261 | used with RELOC_TYPE. */ | |
3d3c5039 | 1262 | |
3d3c5039 | 1263 | static void |
867a58b3 | 1264 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1265 | char *place; |
670a50eb ILT |
1266 | struct mips_cl_insn *ip; |
1267 | expressionS *address_expr; | |
1268 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1269 | boolean unmatched_hi; |
3d3c5039 | 1270 | { |
1aa6938e | 1271 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1272 | char *f; |
becfe05e ILT |
1273 | fixS *fixp; |
1274 | int nops = 0; | |
3d3c5039 | 1275 | |
fbcfacb7 ILT |
1276 | /* Mark instruction labels in mips16 mode. This permits the linker |
1277 | to handle them specially, such as generating jalx instructions | |
1278 | when needed. We also make them odd for the duration of the | |
1279 | assembly, in order to generate the right sort of code. We will | |
1280 | make them even in the adjust_symtab routine, while leaving them | |
1281 | marked. This is convenient for the debugger and the | |
1282 | disassembler. The linker knows to make them odd again. */ | |
1283 | if (mips16) | |
1284 | { | |
1285 | struct insn_label_list *l; | |
1286 | ||
1287 | for (l = insn_labels; l != NULL; l = l->next) | |
1288 | { | |
1289 | #ifdef S_SET_OTHER | |
1290 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1291 | S_SET_OTHER (l->label, STO_MIPS16); | |
1292 | #endif | |
1293 | ++l->label->sy_value.X_add_number; | |
1294 | } | |
1295 | } | |
1296 | ||
1aa6938e ILT |
1297 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1298 | pinfo = ip->insn_mo->pinfo; | |
1299 | ||
4a1cb507 | 1300 | if (place == NULL && (! mips_noreorder || prev_nop_frag != NULL)) |
becfe05e | 1301 | { |
4a1cb507 ILT |
1302 | int prev_prev_nop; |
1303 | ||
becfe05e | 1304 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1305 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1306 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1307 | (1) a load from memory delay |
1308 | (2) a load from a coprocessor delay | |
1309 | (3) an unconditional branch delay | |
1310 | (4) a conditional branch delay | |
1311 | (5) a move to coprocessor register delay | |
1312 | (6) a load coprocessor register from memory delay | |
1313 | (7) a coprocessor condition code delay | |
1314 | (8) a HI/LO special register delay | |
becfe05e ILT |
1315 | |
1316 | There are a lot of optimizations we could do that we don't. | |
1317 | In particular, we do not, in general, reorder instructions. | |
1318 | If you use gcc with optimization, it will reorder | |
1319 | instructions and generally do much more optimization then we | |
1320 | do here; repeating all that work in the assembler would only | |
1321 | benefit hand written assembly code, and does not seem worth | |
1322 | it. */ | |
1323 | ||
1324 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1325 | #define emit_nop() \ |
1326 | (mips16 \ | |
1327 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1328 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1329 | |
1330 | /* The previous insn might require a delay slot, depending upon | |
1331 | the contents of the current insn. */ | |
cc5703cd ILT |
1332 | if (! mips16 |
1333 | && mips_isa < 4 | |
5af96dce ILT |
1334 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1335 | && ! cop_interlocks) | |
d8a1c247 KR |
1336 | || (mips_isa < 2 |
1337 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1338 | { |
1339 | /* A load from a coprocessor or from memory. All load | |
1340 | delays delay the use of general register rt for one | |
1341 | instruction on the r3000. The r6000 and r4000 use | |
1342 | interlocks. */ | |
efec4a28 | 1343 | /* Itbl support may require additional care here. */ |
1aa6938e | 1344 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1345 | if (mips_optimize == 0 |
1346 | || insn_uses_reg (ip, | |
1347 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1348 | & OP_MASK_RT), | |
cc5703cd | 1349 | MIPS_GR_REG)) |
becfe05e ILT |
1350 | ++nops; |
1351 | } | |
cc5703cd ILT |
1352 | else if (! mips16 |
1353 | && mips_isa < 4 | |
5af96dce ILT |
1354 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1355 | && ! cop_interlocks) | |
d8a1c247 KR |
1356 | || (mips_isa < 2 |
1357 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1358 | { |
1359 | /* A generic coprocessor delay. The previous instruction | |
1360 | modified a coprocessor general or control register. If | |
1361 | it modified a control register, we need to avoid any | |
1362 | coprocessor instruction (this is probably not always | |
1363 | required, but it sometimes is). If it modified a general | |
1364 | register, we avoid using that register. | |
1365 | ||
8358c818 ILT |
1366 | On the r6000 and r4000 loading a coprocessor register |
1367 | from memory is interlocked, and does not require a delay. | |
1368 | ||
becfe05e ILT |
1369 | This case is not handled very well. There is no special |
1370 | knowledge of CP0 handling, and the coprocessors other | |
1371 | than the floating point unit are not distinguished at | |
1372 | all. */ | |
efec4a28 DP |
1373 | /* Itbl support may require additional care here. FIXME! |
1374 | Need to modify this to include knowledge about | |
1375 | user specified delays! */ | |
1aa6938e | 1376 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1377 | { |
0aa07269 ILT |
1378 | if (mips_optimize == 0 |
1379 | || insn_uses_reg (ip, | |
8358c818 ILT |
1380 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1381 | & OP_MASK_FT), | |
cc5703cd | 1382 | MIPS_FP_REG)) |
becfe05e ILT |
1383 | ++nops; |
1384 | } | |
1aa6938e | 1385 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1386 | { |
0aa07269 ILT |
1387 | if (mips_optimize == 0 |
1388 | || insn_uses_reg (ip, | |
8358c818 ILT |
1389 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1390 | & OP_MASK_FS), | |
cc5703cd | 1391 | MIPS_FP_REG)) |
becfe05e ILT |
1392 | ++nops; |
1393 | } | |
1394 | else | |
1395 | { | |
1396 | /* We don't know exactly what the previous instruction | |
1397 | does. If the current instruction uses a coprocessor | |
1398 | register, we must insert a NOP. If previous | |
1399 | instruction may set the condition codes, and the | |
1400 | current instruction uses them, we must insert two | |
1401 | NOPS. */ | |
efec4a28 | 1402 | /* Itbl support may require additional care here. */ |
0aa07269 | 1403 | if (mips_optimize == 0 |
1aa6938e ILT |
1404 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1405 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1406 | nops += 2; |
1aa6938e | 1407 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1408 | ++nops; |
1409 | } | |
1410 | } | |
cc5703cd ILT |
1411 | else if (! mips16 |
1412 | && mips_isa < 4 | |
344a8d61 JSC |
1413 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1414 | && ! cop_interlocks) | |
becfe05e ILT |
1415 | { |
1416 | /* The previous instruction sets the coprocessor condition | |
1417 | codes, but does not require a general coprocessor delay | |
1418 | (this means it is a floating point comparison | |
1419 | instruction). If this instruction uses the condition | |
1420 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1421 | /* Itbl support may require additional care here. */ |
0aa07269 | 1422 | if (mips_optimize == 0 |
1aa6938e | 1423 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1424 | ++nops; |
1425 | } | |
1aa6938e | 1426 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1427 | { |
1428 | /* The previous instruction reads the LO register; if the | |
1429 | current instruction writes to the LO register, we must | |
517078c1 | 1430 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1431 | if (! interlocks |
b2b8c24e ILT |
1432 | && (mips_optimize == 0 |
1433 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1434 | nops += 2; |
1435 | } | |
1436 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1437 | { | |
1438 | /* The previous instruction reads the HI register; if the | |
1439 | current instruction writes to the HI register, we must | |
517078c1 | 1440 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1441 | if (! interlocks |
b2b8c24e ILT |
1442 | && (mips_optimize == 0 |
1443 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1444 | nops += 2; |
1445 | } | |
1446 | ||
4a1cb507 ILT |
1447 | /* If the previous instruction was in a noreorder section, then |
1448 | we don't want to insert the nop after all. */ | |
efec4a28 | 1449 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1450 | if (prev_insn_unreordered) |
1451 | nops = 0; | |
1452 | ||
becfe05e ILT |
1453 | /* There are two cases which require two intervening |
1454 | instructions: 1) setting the condition codes using a move to | |
1455 | coprocessor instruction which requires a general coprocessor | |
1456 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1457 | or LO register and then writing to it (except on processors |
1458 | which have interlocks). If we are not already emitting a NOP | |
1459 | instruction, we must check for these cases compared to the | |
1460 | instruction previous to the previous instruction. */ | |
4a1cb507 ILT |
1461 | if ((! mips16 |
1462 | && mips_isa < 4 | |
1463 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) | |
1464 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1465 | && (pinfo & INSN_READ_COND_CODE) | |
1466 | && ! cop_interlocks) | |
1467 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1468 | && (pinfo & INSN_WRITE_LO) | |
1469 | && ! interlocks) | |
1470 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1471 | && (pinfo & INSN_WRITE_HI) | |
1472 | && ! interlocks)) | |
1473 | prev_prev_nop = 1; | |
1474 | else | |
1475 | prev_prev_nop = 0; | |
1476 | ||
1477 | if (prev_prev_insn_unreordered) | |
1478 | prev_prev_nop = 0; | |
1479 | ||
1480 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1481 | ++nops; |
1482 | ||
0dd2d296 ILT |
1483 | /* If we are being given a nop instruction, don't bother with |
1484 | one of the nops we would otherwise output. This will only | |
1485 | happen when a nop instruction is used with mips_optimize set | |
1486 | to 0. */ | |
4a1cb507 ILT |
1487 | if (nops > 0 |
1488 | && ! mips_noreorder | |
1489 | && ip->insn_opcode == (mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1490 | --nops; |
1491 | ||
becfe05e | 1492 | /* Now emit the right number of NOP instructions. */ |
4a1cb507 | 1493 | if (nops > 0 && ! mips_noreorder) |
becfe05e | 1494 | { |
5af96dce ILT |
1495 | fragS *old_frag; |
1496 | unsigned long old_frag_offset; | |
8c63448a | 1497 | int i; |
fbcfacb7 | 1498 | struct insn_label_list *l; |
8c63448a | 1499 | |
5af96dce ILT |
1500 | old_frag = frag_now; |
1501 | old_frag_offset = frag_now_fix (); | |
1502 | ||
8c63448a | 1503 | for (i = 0; i < nops; i++) |
becfe05e | 1504 | emit_nop (); |
5af96dce | 1505 | |
af255ca0 | 1506 | if (listing) |
546f5536 ILT |
1507 | { |
1508 | listing_prev_line (); | |
1509 | /* We may be at the start of a variant frag. In case we | |
1510 | are, make sure there is enough space for the frag | |
1511 | after the frags created by listing_prev_line. The | |
1512 | argument to frag_grow here must be at least as large | |
1513 | as the argument to all other calls to frag_grow in | |
1514 | this file. We don't have to worry about being in the | |
1515 | middle of a variant frag, because the variants insert | |
1516 | all needed nop instructions themselves. */ | |
1517 | frag_grow (40); | |
1518 | } | |
5af96dce | 1519 | |
fbcfacb7 | 1520 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1521 | { |
fbcfacb7 ILT |
1522 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1523 | l->label->sy_frag = frag_now; | |
1524 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1525 | /* mips16 text labels are stored as odd. */ | |
1526 | if (mips16) | |
1527 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1528 | } |
5af96dce ILT |
1529 | |
1530 | #ifndef NO_ECOFF_DEBUGGING | |
1531 | if (ECOFF_DEBUGGING) | |
1532 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1533 | #endif | |
becfe05e | 1534 | } |
4a1cb507 ILT |
1535 | else if (prev_nop_frag != NULL) |
1536 | { | |
1537 | /* We have a frag holding nops we may be able to remove. If | |
1538 | we don't need any nops, we can decrease the size of | |
1539 | prev_nop_frag by the size of one instruction. If we do | |
1540 | need some nops, we count them in prev_nops_required. */ | |
1541 | if (prev_nop_frag_since == 0) | |
1542 | { | |
1543 | if (nops == 0) | |
1544 | { | |
1545 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1546 | --prev_nop_frag_holds; | |
1547 | } | |
1548 | else | |
1549 | prev_nop_frag_required += nops; | |
1550 | } | |
1551 | else | |
1552 | { | |
1553 | if (prev_prev_nop == 0) | |
1554 | { | |
1555 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1556 | --prev_nop_frag_holds; | |
1557 | } | |
1558 | else | |
1559 | ++prev_nop_frag_required; | |
1560 | } | |
1561 | ||
1562 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1563 | prev_nop_frag = NULL; | |
1564 | ||
1565 | ++prev_nop_frag_since; | |
1566 | ||
1567 | /* Sanity check: by the time we reach the second instruction | |
1568 | after prev_nop_frag, we should have used up all the nops | |
1569 | one way or another. */ | |
1570 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1571 | } | |
becfe05e | 1572 | } |
4a1cb507 | 1573 | |
cc5703cd ILT |
1574 | if (reloc_type > BFD_RELOC_UNUSED) |
1575 | { | |
1576 | /* We need to set up a variant frag. */ | |
1577 | assert (mips16 && address_expr != NULL); | |
1578 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1579 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1580 | mips16_small, mips16_ext, |
1581 | (prev_pinfo | |
1582 | & INSN_UNCOND_BRANCH_DELAY), | |
1583 | (prev_insn_reloc_type | |
1584 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1585 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1586 | (char *) NULL); |
1587 | } | |
1588 | else if (place != NULL) | |
0dd2d296 | 1589 | f = place; |
cc5703cd | 1590 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1591 | { |
1592 | /* Make sure there is enough room to swap this instruction with | |
1593 | a following jump instruction. */ | |
1594 | frag_grow (6); | |
1595 | f = frag_more (2); | |
1596 | } | |
cc5703cd | 1597 | else |
035936da ILT |
1598 | { |
1599 | if (mips16 | |
1600 | && mips_noreorder | |
1601 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1602 | as_warn ("extended instruction in delay slot"); | |
1603 | ||
1604 | f = frag_more (4); | |
1605 | } | |
1606 | ||
becfe05e | 1607 | fixp = NULL; |
cc5703cd | 1608 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1609 | { |
5ac34ac3 | 1610 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1611 | { |
1612 | switch (reloc_type) | |
1613 | { | |
3d3c5039 | 1614 | case BFD_RELOC_32: |
670a50eb ILT |
1615 | ip->insn_opcode |= address_expr->X_add_number; |
1616 | break; | |
3d3c5039 ILT |
1617 | |
1618 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1619 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1620 | break; | |
3d3c5039 ILT |
1621 | |
1622 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1623 | if ((address_expr->X_add_number & 3) != 0) |
1624 | as_bad ("jump to misaligned address (0x%lx)", | |
1625 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1626 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1627 | break; | |
1628 | ||
cc5703cd | 1629 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1630 | if ((address_expr->X_add_number & 3) != 0) |
1631 | as_bad ("jump to misaligned address (0x%lx)", | |
1632 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1633 | ip->insn_opcode |= |
1634 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1635 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1636 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1637 | break; | |
1638 | ||
3d3c5039 | 1639 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1640 | goto need_reloc; |
3d3c5039 ILT |
1641 | |
1642 | default: | |
670a50eb | 1643 | internalError (); |
3d3c5039 | 1644 | } |
670a50eb ILT |
1645 | } |
1646 | else | |
1647 | { | |
3d3c5039 | 1648 | need_reloc: |
0dd2d296 ILT |
1649 | /* Don't generate a reloc if we are writing into a variant |
1650 | frag. */ | |
1651 | if (place == NULL) | |
867a58b3 ILT |
1652 | { |
1653 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1654 | address_expr, | |
1655 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1656 | reloc_type); | |
1657 | if (unmatched_hi) | |
1658 | { | |
1659 | struct mips_hi_fixup *hi_fixup; | |
1660 | ||
1661 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1662 | hi_fixup = ((struct mips_hi_fixup *) | |
1663 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1664 | hi_fixup->fixp = fixp; | |
1665 | hi_fixup->seg = now_seg; | |
1666 | hi_fixup->next = mips_hi_fixup_list; | |
1667 | mips_hi_fixup_list = hi_fixup; | |
1668 | } | |
1669 | } | |
3d3c5039 ILT |
1670 | } |
1671 | } | |
becfe05e | 1672 | |
16262668 | 1673 | if (! mips16) |
cc5703cd | 1674 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1675 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1676 | { | |
1677 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1678 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1679 | } | |
cc5703cd ILT |
1680 | else |
1681 | { | |
1682 | if (ip->use_extend) | |
1683 | { | |
1684 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1685 | f += 2; | |
1686 | } | |
1687 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1688 | } | |
670a50eb | 1689 | |
1aa6938e | 1690 | /* Update the register mask information. */ |
cc5703cd ILT |
1691 | if (! mips16) |
1692 | { | |
1693 | if (pinfo & INSN_WRITE_GPR_D) | |
1694 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1695 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1696 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1697 | if (pinfo & INSN_READ_GPR_S) | |
1698 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1699 | if (pinfo & INSN_WRITE_GPR_31) | |
1700 | mips_gprmask |= 1 << 31; | |
1701 | if (pinfo & INSN_WRITE_FPR_D) | |
1702 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1703 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1704 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1705 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1706 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1707 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1708 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1709 | if (pinfo & INSN_COP) | |
1710 | { | |
efec4a28 DP |
1711 | /* We don't keep enough information to sort these cases out. |
1712 | The itbl support does keep this information however, although | |
1713 | we currently don't support itbl fprmats as part of the cop | |
1714 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1715 | } |
1716 | /* Never set the bit for $0, which is always zero. */ | |
1717 | mips_gprmask &=~ 1 << 0; | |
1718 | } | |
1719 | else | |
1aa6938e | 1720 | { |
cc5703cd ILT |
1721 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1722 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1723 | & MIPS16OP_MASK_RX); | |
1724 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1725 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1726 | & MIPS16OP_MASK_RY); | |
1727 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1728 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1729 | & MIPS16OP_MASK_RZ); | |
1730 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1731 | mips_gprmask |= 1 << TREG; | |
1732 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1733 | mips_gprmask |= 1 << SP; | |
1734 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1735 | mips_gprmask |= 1 << RA; | |
1736 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1737 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1738 | if (pinfo & MIPS16_INSN_READ_Z) | |
1739 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1740 | & MIPS16OP_MASK_MOVE32Z); | |
1741 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1742 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1743 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1744 | } |
1aa6938e | 1745 | |
0dd2d296 | 1746 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1747 | { |
becfe05e ILT |
1748 | /* Filling the branch delay slot is more complex. We try to |
1749 | switch the branch with the previous instruction, which we can | |
1750 | do if the previous instruction does not set up a condition | |
1751 | that the branch tests and if the branch is not itself the | |
1752 | target of any branch. */ | |
1aa6938e ILT |
1753 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1754 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1755 | { |
0aa07269 | 1756 | if (mips_optimize < 2 |
19ed8960 ILT |
1757 | /* If we have seen .set volatile or .set nomove, don't |
1758 | optimize. */ | |
1759 | || mips_nomove != 0 | |
4e95866e ILT |
1760 | /* If we had to emit any NOP instructions, then we |
1761 | already know we can not swap. */ | |
1762 | || nops != 0 | |
becfe05e ILT |
1763 | /* If we don't even know the previous insn, we can not |
1764 | swap. */ | |
1765 | || ! prev_insn_valid | |
1766 | /* If the previous insn is already in a branch delay | |
1767 | slot, then we can not swap. */ | |
1768 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1769 | /* If the previous previous insn was in a .set |
1770 | noreorder, we can't swap. Actually, the MIPS | |
1771 | assembler will swap in this situation. However, gcc | |
1772 | configured -with-gnu-as will generate code like | |
1773 | .set noreorder | |
1774 | lw $4,XXX | |
1775 | .set reorder | |
1776 | INSN | |
1777 | bne $4,$0,foo | |
1778 | in which we can not swap the bne and INSN. If gcc is | |
1779 | not configured -with-gnu-as, it does not output the | |
1780 | .set pseudo-ops. We don't have to check | |
1781 | prev_insn_unreordered, because prev_insn_valid will | |
1782 | be 0 in that case. We don't want to use | |
1783 | prev_prev_insn_valid, because we do want to be able | |
1784 | to swap at the start of a function. */ | |
1785 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1786 | /* If the branch is itself the target of a branch, we |
1787 | can not swap. We cheat on this; all we check for is | |
1788 | whether there is a label on this instruction. If | |
1789 | there are any branches to anything other than a | |
1790 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1791 | || insn_labels != NULL |
777ad64d | 1792 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1793 | can not do the swap. This does not apply to the |
1794 | mips16, which uses variant frags for different | |
1795 | purposes. */ | |
1796 | || (! mips16 | |
1797 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1798 | /* If the branch reads the condition codes, we don't |
1799 | even try to swap, because in the sequence | |
1800 | ctc1 $X,$31 | |
1801 | INSN | |
1802 | INSN | |
1803 | bc1t LABEL | |
1804 | we can not swap, and I don't feel like handling that | |
1805 | case. */ | |
cc5703cd ILT |
1806 | || (! mips16 |
1807 | && mips_isa < 4 | |
d8a1c247 | 1808 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1809 | /* We can not swap with an instruction that requires a |
1810 | delay slot, becase the target of the branch might | |
1811 | interfere with that instruction. */ | |
cc5703cd ILT |
1812 | || (! mips16 |
1813 | && mips_isa < 4 | |
d8a1c247 | 1814 | && (prev_pinfo |
efec4a28 | 1815 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1816 | & (INSN_LOAD_COPROC_DELAY |
1817 | | INSN_COPROC_MOVE_DELAY | |
1818 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1819 | || (! interlocks |
b2b8c24e ILT |
1820 | && (prev_pinfo |
1821 | & (INSN_READ_LO | |
1822 | | INSN_READ_HI))) | |
cc5703cd ILT |
1823 | || (! mips16 |
1824 | && mips_isa < 2 | |
1aa6938e | 1825 | && (prev_pinfo |
8358c818 | 1826 | & (INSN_LOAD_MEMORY_DELAY |
efec4a28 | 1827 | /* Itbl support may require additional care here. */ |
8358c818 | 1828 | | INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 1829 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1830 | || (prev_pinfo |
6e8dda9c ILT |
1831 | & (INSN_UNCOND_BRANCH_DELAY |
1832 | | INSN_COND_BRANCH_DELAY | |
1833 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1834 | /* We do not swap with a trap instruction, since it |
1835 | complicates trap handlers to have the trap | |
1836 | instruction be in a delay slot. */ | |
1aa6938e | 1837 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1838 | /* If the branch reads a register that the previous |
1839 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1840 | || (! mips16 |
1841 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1842 | && insn_uses_reg (ip, |
1843 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1844 | & OP_MASK_RT), | |
cc5703cd ILT |
1845 | MIPS_GR_REG)) |
1846 | || (! mips16 | |
1847 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1848 | && insn_uses_reg (ip, |
1849 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1850 | & OP_MASK_RD), | |
cc5703cd ILT |
1851 | MIPS_GR_REG)) |
1852 | || (mips16 | |
1853 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1854 | && insn_uses_reg (ip, | |
1855 | ((prev_insn.insn_opcode | |
1856 | >> MIPS16OP_SH_RX) | |
1857 | & MIPS16OP_MASK_RX), | |
1858 | MIPS16_REG)) | |
1859 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1860 | && insn_uses_reg (ip, | |
1861 | ((prev_insn.insn_opcode | |
1862 | >> MIPS16OP_SH_RY) | |
1863 | & MIPS16OP_MASK_RY), | |
1864 | MIPS16_REG)) | |
1865 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1866 | && insn_uses_reg (ip, | |
1867 | ((prev_insn.insn_opcode | |
1868 | >> MIPS16OP_SH_RZ) | |
1869 | & MIPS16OP_MASK_RZ), | |
1870 | MIPS16_REG)) | |
1871 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1872 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1873 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1874 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1875 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1876 | && insn_uses_reg (ip, | |
1877 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1878 | insn_opcode), | |
1879 | MIPS_GR_REG)))) | |
1849d646 ILT |
1880 | /* If the branch writes a register that the previous |
1881 | instruction sets, we can not swap (we know that | |
1882 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1883 | || (! mips16 |
1884 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1885 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1886 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1887 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1888 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1889 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1890 | & OP_MASK_RT) | |
1891 | == 31)))) | |
cc5703cd ILT |
1892 | || (! mips16 |
1893 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1894 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1895 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1896 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1897 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1898 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1899 | & OP_MASK_RD) | |
1900 | == 31)))) | |
cc5703cd ILT |
1901 | || (mips16 |
1902 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1903 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1904 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1905 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1906 | == RA)))) | |
becfe05e ILT |
1907 | /* If the branch writes a register that the previous |
1908 | instruction reads, we can not swap (we know that | |
1909 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1910 | || (! mips16 |
1911 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1912 | && insn_uses_reg (&prev_insn, |
1913 | ((ip->insn_opcode >> OP_SH_RD) | |
1914 | & OP_MASK_RD), | |
cc5703cd ILT |
1915 | MIPS_GR_REG)) |
1916 | || (! mips16 | |
1917 | && (pinfo & INSN_WRITE_GPR_31) | |
1918 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1919 | || (mips16 | |
1920 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1921 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1922 | /* If we are generating embedded PIC code, the branch |
1923 | might be expanded into a sequence which uses $at, so | |
1924 | we can't swap with an instruction which reads it. */ | |
1925 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1926 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1927 | /* If the previous previous instruction has a load |
1928 | delay, and sets a register that the branch reads, we | |
1929 | can not swap. */ | |
cc5703cd ILT |
1930 | || (! mips16 |
1931 | && mips_isa < 4 | |
efec4a28 | 1932 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1933 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1934 | || (mips_isa < 2 | |
1935 | && (prev_prev_insn.insn_mo->pinfo | |
1936 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1937 | && insn_uses_reg (ip, |
1938 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1939 | & OP_MASK_RT), | |
cc5703cd | 1940 | MIPS_GR_REG)) |
d31a3f5e ILT |
1941 | /* If one instruction sets a condition code and the |
1942 | other one uses a condition code, we can not swap. */ | |
1943 | || ((pinfo & INSN_READ_COND_CODE) | |
1944 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1945 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1946 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1947 | /* If the previous instruction uses the PC, we can not | |
1948 | swap. */ | |
1949 | || (mips16 | |
1950 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1951 | /* If the previous instruction was extended, we can not | |
1952 | swap. */ | |
1953 | || (mips16 && prev_insn_extended) | |
1954 | /* If the previous instruction had a fixup in mips16 | |
1955 | mode, we can not swap. This normally means that the | |
1956 | previous instruction was a 4 byte branch anyhow. */ | |
1957 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1958 | { |
1959 | /* We could do even better for unconditional branches to | |
1960 | portions of this object file; we could pick up the | |
1961 | instruction at the destination, put it in the delay | |
1962 | slot, and bump the destination address. */ | |
1963 | emit_nop (); | |
1964 | /* Update the previous insn information. */ | |
1965 | prev_prev_insn = *ip; | |
1966 | prev_insn.insn_mo = &dummy_opcode; | |
1967 | } | |
1968 | else | |
1969 | { | |
becfe05e | 1970 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1971 | if (! mips16) |
1972 | { | |
1973 | char *prev_f; | |
1974 | char temp[4]; | |
1975 | ||
1976 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1977 | memcpy (temp, prev_f, 4); | |
1978 | memcpy (prev_f, f, 4); | |
1979 | memcpy (f, temp, 4); | |
1980 | if (prev_insn_fixp) | |
1981 | { | |
1982 | prev_insn_fixp->fx_frag = frag_now; | |
1983 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1984 | } | |
1985 | if (fixp) | |
1986 | { | |
1987 | fixp->fx_frag = prev_insn_frag; | |
1988 | fixp->fx_where = prev_insn_where; | |
1989 | } | |
1990 | } | |
cc5703cd | 1991 | else |
becfe05e | 1992 | { |
cc5703cd ILT |
1993 | char *prev_f; |
1994 | char temp[2]; | |
1995 | ||
1996 | assert (prev_insn_fixp == NULL); | |
1997 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1998 | memcpy (temp, prev_f, 2); | |
1999 | memcpy (prev_f, f, 2); | |
2000 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2001 | { |
2002 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2003 | memcpy (f, temp, 2); | |
2004 | } | |
cc5703cd ILT |
2005 | else |
2006 | { | |
2007 | memcpy (f, f + 2, 2); | |
2008 | memcpy (f + 2, temp, 2); | |
2009 | } | |
2010 | if (fixp) | |
2011 | { | |
2012 | fixp->fx_frag = prev_insn_frag; | |
2013 | fixp->fx_where = prev_insn_where; | |
2014 | } | |
becfe05e | 2015 | } |
cc5703cd | 2016 | |
becfe05e ILT |
2017 | /* Update the previous insn information; leave prev_insn |
2018 | unchanged. */ | |
2019 | prev_prev_insn = *ip; | |
2020 | } | |
2021 | prev_insn_is_delay_slot = 1; | |
2022 | ||
2023 | /* If that was an unconditional branch, forget the previous | |
2024 | insn information. */ | |
1aa6938e | 2025 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2026 | { |
2027 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2028 | prev_insn.insn_mo = &dummy_opcode; | |
2029 | } | |
a677feeb ILT |
2030 | |
2031 | prev_insn_fixp = NULL; | |
2032 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2033 | prev_insn_extended = 0; | |
becfe05e | 2034 | } |
1aa6938e | 2035 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2036 | { |
2037 | /* We don't yet optimize a branch likely. What we should do | |
2038 | is look at the target, copy the instruction found there | |
2039 | into the delay slot, and increment the branch to jump to | |
2040 | the next instruction. */ | |
2041 | emit_nop (); | |
2042 | /* Update the previous insn information. */ | |
2043 | prev_prev_insn = *ip; | |
2044 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2045 | prev_insn_fixp = NULL; |
2046 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2047 | prev_insn_extended = 0; | |
8358c818 | 2048 | } |
becfe05e | 2049 | else |
670a50eb | 2050 | { |
becfe05e ILT |
2051 | /* Update the previous insn information. */ |
2052 | if (nops > 0) | |
2053 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2054 | else | |
2055 | prev_prev_insn = prev_insn; | |
2056 | prev_insn = *ip; | |
2057 | ||
2058 | /* Any time we see a branch, we always fill the delay slot | |
2059 | immediately; since this insn is not a branch, we know it | |
2060 | is not in a delay slot. */ | |
2061 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2062 | |
2063 | prev_insn_fixp = fixp; | |
2064 | prev_insn_reloc_type = reloc_type; | |
2065 | if (mips16) | |
2066 | prev_insn_extended = (ip->use_extend | |
2067 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2068 | } |
2069 | ||
4e95866e ILT |
2070 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2071 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2072 | prev_insn_frag = frag_now; |
2073 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2074 | prev_insn_valid = 1; |
2075 | } | |
fbcfacb7 | 2076 | else if (place == NULL) |
a677feeb | 2077 | { |
fbcfacb7 | 2078 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2079 | reordering, in order to determine the base address for mips16 |
2080 | PC relative relocs. */ | |
4a1cb507 | 2081 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2082 | prev_insn = *ip; |
2083 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2084 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2085 | prev_insn_unreordered = 1; | |
a677feeb | 2086 | } |
3d3c5039 | 2087 | |
becfe05e | 2088 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2089 | mips_clear_insn_labels (); |
becfe05e ILT |
2090 | } |
2091 | ||
2092 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2093 | label. If PRESERVE is non-zero, it remembers enough information to |
2094 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2095 | |
2096 | static void | |
4a1cb507 ILT |
2097 | mips_no_prev_insn (preserve) |
2098 | int preserve; | |
becfe05e | 2099 | { |
4a1cb507 ILT |
2100 | if (! preserve) |
2101 | { | |
2102 | prev_insn.insn_mo = &dummy_opcode; | |
2103 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2104 | prev_nop_frag = NULL; | |
2105 | prev_nop_frag_holds = 0; | |
2106 | prev_nop_frag_required = 0; | |
2107 | prev_nop_frag_since = 0; | |
2108 | } | |
becfe05e ILT |
2109 | prev_insn_valid = 0; |
2110 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2111 | prev_insn_unreordered = 0; |
cc5703cd | 2112 | prev_insn_extended = 0; |
a677feeb | 2113 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2114 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2115 | mips_clear_insn_labels (); |
becfe05e ILT |
2116 | } |
2117 | ||
2118 | /* This function must be called whenever we turn on noreorder or emit | |
2119 | something other than instructions. It inserts any NOPS which might | |
2120 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2121 | kept for the previous instructions. The INSNS parameter is true if |
2122 | instructions are to follow. */ | |
becfe05e ILT |
2123 | |
2124 | static void | |
fbcfacb7 ILT |
2125 | mips_emit_delays (insns) |
2126 | boolean insns; | |
becfe05e ILT |
2127 | { |
2128 | if (! mips_noreorder) | |
2129 | { | |
4a1cb507 | 2130 | int nops; |
becfe05e | 2131 | |
4a1cb507 | 2132 | nops = 0; |
cc5703cd ILT |
2133 | if ((! mips16 |
2134 | && mips_isa < 4 | |
344a8d61 JSC |
2135 | && (! cop_interlocks |
2136 | && (prev_insn.insn_mo->pinfo | |
2137 | & (INSN_LOAD_COPROC_DELAY | |
2138 | | INSN_COPROC_MOVE_DELAY | |
2139 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 2140 | || (! interlocks |
b2b8c24e ILT |
2141 | && (prev_insn.insn_mo->pinfo |
2142 | & (INSN_READ_LO | |
2143 | | INSN_READ_HI))) | |
cc5703cd ILT |
2144 | || (! mips16 |
2145 | && mips_isa < 2 | |
8358c818 ILT |
2146 | && (prev_insn.insn_mo->pinfo |
2147 | & (INSN_LOAD_MEMORY_DELAY | |
2148 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e | 2149 | { |
efec4a28 | 2150 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2151 | ++nops; |
cc5703cd ILT |
2152 | if ((! mips16 |
2153 | && mips_isa < 4 | |
344a8d61 JSC |
2154 | && (! cop_interlocks |
2155 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2156 | || (! interlocks |
b2b8c24e ILT |
2157 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2158 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2159 | ++nops; |
2160 | ||
2161 | if (prev_insn_unreordered) | |
2162 | nops = 0; | |
becfe05e | 2163 | } |
cc5703cd ILT |
2164 | else if ((! mips16 |
2165 | && mips_isa < 4 | |
344a8d61 JSC |
2166 | && (! cop_interlocks |
2167 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2168 | || (! interlocks |
b2b8c24e ILT |
2169 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2170 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2171 | { |
efec4a28 | 2172 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2173 | if (! prev_prev_insn_unreordered) |
2174 | ++nops; | |
2175 | } | |
2176 | ||
2177 | if (nops > 0) | |
670a50eb | 2178 | { |
fbcfacb7 ILT |
2179 | struct insn_label_list *l; |
2180 | ||
4a1cb507 ILT |
2181 | if (insns) |
2182 | { | |
2183 | /* Record the frag which holds the nop instructions, so | |
2184 | that we can remove them if we don't need them. */ | |
2185 | frag_grow (mips16 ? nops * 2 : nops * 4); | |
2186 | prev_nop_frag = frag_now; | |
2187 | prev_nop_frag_holds = nops; | |
2188 | prev_nop_frag_required = 0; | |
2189 | prev_nop_frag_since = 0; | |
2190 | } | |
2191 | ||
2192 | for (; nops > 0; --nops) | |
2193 | emit_nop (); | |
2194 | ||
2195 | if (insns) | |
2196 | { | |
2197 | /* Move on to a new frag, so that it is safe to simply | |
2198 | decrease the size of prev_nop_frag. */ | |
2199 | frag_wane (frag_now); | |
2200 | frag_new (0); | |
2201 | } | |
2202 | ||
fbcfacb7 | 2203 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2204 | { |
fbcfacb7 ILT |
2205 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2206 | l->label->sy_frag = frag_now; | |
2207 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2208 | /* mips16 text labels are stored as odd. */ | |
2209 | if (mips16) | |
2210 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2211 | } |
3d3c5039 ILT |
2212 | } |
2213 | } | |
0221ddf7 | 2214 | |
fbcfacb7 ILT |
2215 | /* Mark instruction labels in mips16 mode. This permits the linker |
2216 | to handle them specially, such as generating jalx instructions | |
2217 | when needed. We also make them odd for the duration of the | |
2218 | assembly, in order to generate the right sort of code. We will | |
2219 | make them even in the adjust_symtab routine, while leaving them | |
2220 | marked. This is convenient for the debugger and the | |
2221 | disassembler. The linker knows to make them odd again. */ | |
2222 | if (mips16 && insns) | |
2223 | { | |
2224 | struct insn_label_list *l; | |
2225 | ||
2226 | for (l = insn_labels; l != NULL; l = l->next) | |
2227 | { | |
2228 | #ifdef S_SET_OTHER | |
2229 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2230 | S_SET_OTHER (l->label, STO_MIPS16); | |
2231 | #endif | |
2232 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2233 | ++l->label->sy_value.X_add_number; | |
2234 | } | |
2235 | } | |
2236 | ||
4a1cb507 | 2237 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2238 | } |
2239 | ||
670a50eb ILT |
2240 | /* Build an instruction created by a macro expansion. This is passed |
2241 | a pointer to the count of instructions created so far, an | |
2242 | expression, the name of the instruction to build, an operand format | |
2243 | string, and corresponding arguments. */ | |
2244 | ||
1dc1e798 | 2245 | #ifdef USE_STDARG |
3d3c5039 | 2246 | static void |
0dd2d296 ILT |
2247 | macro_build (char *place, |
2248 | int *counter, | |
670a50eb | 2249 | expressionS * ep, |
3d3c5039 ILT |
2250 | const char *name, |
2251 | const char *fmt, | |
2252 | ...) | |
1dc1e798 | 2253 | #else |
3d3c5039 | 2254 | static void |
0dd2d296 ILT |
2255 | macro_build (place, counter, ep, name, fmt, va_alist) |
2256 | char *place; | |
3d3c5039 ILT |
2257 | int *counter; |
2258 | expressionS *ep; | |
2259 | const char *name; | |
2260 | const char *fmt; | |
2261 | va_dcl | |
1dc1e798 | 2262 | #endif |
3d3c5039 | 2263 | { |
670a50eb ILT |
2264 | struct mips_cl_insn insn; |
2265 | bfd_reloc_code_real_type r; | |
2266 | va_list args; | |
3d3c5039 | 2267 | |
1dc1e798 | 2268 | #ifdef USE_STDARG |
670a50eb | 2269 | va_start (args, fmt); |
3d3c5039 | 2270 | #else |
670a50eb | 2271 | va_start (args); |
3d3c5039 ILT |
2272 | #endif |
2273 | ||
670a50eb ILT |
2274 | /* |
2275 | * If the macro is about to expand into a second instruction, | |
2276 | * print a warning if needed. We need to pass ip as a parameter | |
2277 | * to generate a better warning message here... | |
2278 | */ | |
0dd2d296 | 2279 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2280 | as_warn ("Macro instruction expanded into multiple instructions"); |
2281 | ||
0dd2d296 ILT |
2282 | if (place == NULL) |
2283 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2284 | |
cc5703cd ILT |
2285 | if (mips16) |
2286 | { | |
2287 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2288 | va_end (args); | |
2289 | return; | |
2290 | } | |
2291 | ||
670a50eb ILT |
2292 | r = BFD_RELOC_UNUSED; |
2293 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2294 | assert (insn.insn_mo); | |
2295 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2296 | ||
9226253a | 2297 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2298 | || insn.insn_mo->pinfo == INSN_MACRO |
2299 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2300 | && mips_isa < 2) | |
2301 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2302 | && mips_isa < 3) | |
2303 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2304 | && mips_isa < 4) | |
2305 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2306 | && ! mips_4650) | |
2307 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2308 | && ! mips_4010) | |
2309 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2310 | && ! mips_4100) |
2311 | /* start-sanitize-r5900 */ | |
2312 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2313 | && ! mips_5900) | |
2314 | /* end-sanitize-r5900 */ | |
2315 | ) | |
670a50eb ILT |
2316 | { |
2317 | ++insn.insn_mo; | |
2318 | assert (insn.insn_mo->name); | |
2319 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2320 | } |
670a50eb ILT |
2321 | insn.insn_opcode = insn.insn_mo->match; |
2322 | for (;;) | |
2323 | { | |
2324 | switch (*fmt++) | |
2325 | { | |
3d3c5039 | 2326 | case '\0': |
670a50eb | 2327 | break; |
3d3c5039 ILT |
2328 | |
2329 | case ',': | |
2330 | case '(': | |
2331 | case ')': | |
670a50eb | 2332 | continue; |
3d3c5039 ILT |
2333 | |
2334 | case 't': | |
2335 | case 'w': | |
918692a5 | 2336 | case 'E': |
670a50eb ILT |
2337 | insn.insn_opcode |= va_arg (args, int) << 16; |
2338 | continue; | |
3d3c5039 ILT |
2339 | |
2340 | case 'c': | |
2341 | case 'T': | |
2342 | case 'W': | |
670a50eb ILT |
2343 | insn.insn_opcode |= va_arg (args, int) << 16; |
2344 | continue; | |
3d3c5039 ILT |
2345 | |
2346 | case 'd': | |
918692a5 | 2347 | case 'G': |
670a50eb ILT |
2348 | insn.insn_opcode |= va_arg (args, int) << 11; |
2349 | continue; | |
3d3c5039 ILT |
2350 | |
2351 | case 'V': | |
2352 | case 'S': | |
670a50eb ILT |
2353 | insn.insn_opcode |= va_arg (args, int) << 11; |
2354 | continue; | |
3d3c5039 | 2355 | |
ff3a5c18 ILT |
2356 | case 'z': |
2357 | continue; | |
2358 | ||
3d3c5039 | 2359 | case '<': |
670a50eb ILT |
2360 | insn.insn_opcode |= va_arg (args, int) << 6; |
2361 | continue; | |
3d3c5039 ILT |
2362 | |
2363 | case 'D': | |
670a50eb ILT |
2364 | insn.insn_opcode |= va_arg (args, int) << 6; |
2365 | continue; | |
3d3c5039 | 2366 | |
918692a5 ILT |
2367 | case 'B': |
2368 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2369 | continue; | |
2370 | ||
3d3c5039 ILT |
2371 | case 'b': |
2372 | case 's': | |
2373 | case 'r': | |
2374 | case 'v': | |
670a50eb ILT |
2375 | insn.insn_opcode |= va_arg (args, int) << 21; |
2376 | continue; | |
3d3c5039 ILT |
2377 | |
2378 | case 'i': | |
2379 | case 'j': | |
2380 | case 'o': | |
9226253a | 2381 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2382 | assert (r == BFD_RELOC_MIPS_GPREL |
2383 | || r == BFD_RELOC_MIPS_LITERAL | |
2384 | || r == BFD_RELOC_LO16 | |
2385 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2386 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2387 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2388 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2389 | || (ep->X_op == O_subtract |
2390 | && now_seg == text_section | |
ecd4ca1c | 2391 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2392 | continue; |
3d3c5039 | 2393 | |
6e8dda9c | 2394 | case 'u': |
ecd4ca1c ILT |
2395 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2396 | assert (ep != NULL | |
2397 | && (ep->X_op == O_constant | |
2398 | || (ep->X_op == O_symbol | |
2399 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2400 | || r == BFD_RELOC_HI16 |
2401 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2402 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2403 | || (ep->X_op == O_subtract |
2404 | && now_seg == text_section | |
ecd4ca1c ILT |
2405 | && r == BFD_RELOC_PCREL_HI16_S))); |
2406 | if (ep->X_op == O_constant) | |
2407 | { | |
2408 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2409 | ep = NULL; | |
2410 | r = BFD_RELOC_UNUSED; | |
2411 | } | |
6e8dda9c ILT |
2412 | continue; |
2413 | ||
3d3c5039 | 2414 | case 'p': |
670a50eb ILT |
2415 | assert (ep != NULL); |
2416 | /* | |
2417 | * This allows macro() to pass an immediate expression for | |
2418 | * creating short branches without creating a symbol. | |
2419 | * Note that the expression still might come from the assembly | |
2420 | * input, in which case the value is not checked for range nor | |
2421 | * is a relocation entry generated (yuck). | |
2422 | */ | |
5ac34ac3 | 2423 | if (ep->X_op == O_constant) |
670a50eb ILT |
2424 | { |
2425 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2426 | ep = NULL; | |
2427 | } | |
2428 | else | |
2429 | r = BFD_RELOC_16_PCREL_S2; | |
2430 | continue; | |
3d3c5039 | 2431 | |
9226253a ILT |
2432 | case 'a': |
2433 | assert (ep != NULL); | |
2434 | r = BFD_RELOC_MIPS_JMP; | |
2435 | continue; | |
2436 | ||
3d3c5039 | 2437 | default: |
670a50eb | 2438 | internalError (); |
3d3c5039 | 2439 | } |
670a50eb | 2440 | break; |
3d3c5039 | 2441 | } |
670a50eb ILT |
2442 | va_end (args); |
2443 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2444 | ||
867a58b3 | 2445 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2446 | } |
2447 | ||
cc5703cd ILT |
2448 | static void |
2449 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2450 | char *place; | |
2451 | int *counter; | |
2452 | expressionS *ep; | |
2453 | const char *name; | |
2454 | const char *fmt; | |
2455 | va_list args; | |
2456 | { | |
2457 | struct mips_cl_insn insn; | |
2458 | bfd_reloc_code_real_type r; | |
2459 | ||
2460 | r = BFD_RELOC_UNUSED; | |
2461 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2462 | assert (insn.insn_mo); | |
2463 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2464 | ||
2465 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2466 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2467 | { | |
2468 | ++insn.insn_mo; | |
2469 | assert (insn.insn_mo->name); | |
2470 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2471 | } | |
2472 | ||
2473 | insn.insn_opcode = insn.insn_mo->match; | |
2474 | insn.use_extend = false; | |
2475 | ||
2476 | for (;;) | |
2477 | { | |
2478 | int c; | |
2479 | ||
2480 | c = *fmt++; | |
2481 | switch (c) | |
2482 | { | |
2483 | case '\0': | |
2484 | break; | |
2485 | ||
2486 | case ',': | |
2487 | case '(': | |
2488 | case ')': | |
2489 | continue; | |
2490 | ||
2491 | case 'y': | |
2492 | case 'w': | |
2493 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2494 | continue; | |
2495 | ||
2496 | case 'x': | |
2497 | case 'v': | |
2498 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2499 | continue; | |
2500 | ||
2501 | case 'z': | |
2502 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2503 | continue; | |
2504 | ||
2505 | case 'Z': | |
2506 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2507 | continue; | |
2508 | ||
2509 | case '0': | |
2510 | case 'S': | |
2511 | case 'P': | |
2512 | case 'R': | |
2513 | continue; | |
2514 | ||
2515 | case 'X': | |
2516 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2517 | continue; | |
2518 | ||
2519 | case 'Y': | |
2520 | { | |
2521 | int regno; | |
2522 | ||
2523 | regno = va_arg (args, int); | |
2524 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2525 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2526 | } | |
2527 | continue; | |
2528 | ||
2529 | case '<': | |
2530 | case '>': | |
2531 | case '4': | |
2532 | case '5': | |
2533 | case 'H': | |
2534 | case 'W': | |
2535 | case 'D': | |
2536 | case 'j': | |
2537 | case '8': | |
2538 | case 'V': | |
2539 | case 'C': | |
2540 | case 'U': | |
2541 | case 'k': | |
2542 | case 'K': | |
2543 | case 'p': | |
2544 | case 'q': | |
2545 | { | |
2546 | assert (ep != NULL); | |
2547 | ||
2548 | if (ep->X_op != O_constant) | |
2549 | r = BFD_RELOC_UNUSED + c; | |
2550 | else | |
2551 | { | |
15e69f98 ILT |
2552 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2553 | false, false, &insn.insn_opcode, | |
2554 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2555 | ep = NULL; |
2556 | r = BFD_RELOC_UNUSED; | |
2557 | } | |
2558 | } | |
2559 | continue; | |
2560 | ||
2561 | case '6': | |
2562 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2563 | continue; | |
2564 | } | |
2565 | ||
2566 | break; | |
2567 | } | |
2568 | ||
2569 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2570 | ||
2571 | append_insn (place, &insn, ep, r, false); | |
2572 | } | |
2573 | ||
3d3c5039 ILT |
2574 | /* |
2575 | * Generate a "lui" instruction. | |
2576 | */ | |
2577 | static void | |
0dd2d296 ILT |
2578 | macro_build_lui (place, counter, ep, regnum) |
2579 | char *place; | |
3d3c5039 ILT |
2580 | int *counter; |
2581 | expressionS *ep; | |
2582 | int regnum; | |
2583 | { | |
670a50eb ILT |
2584 | expressionS high_expr; |
2585 | struct mips_cl_insn insn; | |
2586 | bfd_reloc_code_real_type r; | |
2587 | CONST char *name = "lui"; | |
2588 | CONST char *fmt = "t,u"; | |
2589 | ||
cc5703cd ILT |
2590 | assert (! mips16); |
2591 | ||
0dd2d296 ILT |
2592 | if (place == NULL) |
2593 | high_expr = *ep; | |
2594 | else | |
2595 | { | |
2596 | high_expr.X_op = O_constant; | |
fb251650 | 2597 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2598 | } |
670a50eb | 2599 | |
5ac34ac3 | 2600 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2601 | { |
2602 | /* we can compute the instruction now without a relocation entry */ | |
2603 | if (high_expr.X_add_number & 0x8000) | |
2604 | high_expr.X_add_number += 0x10000; | |
2605 | high_expr.X_add_number = | |
2606 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2607 | r = BFD_RELOC_UNUSED; | |
2608 | } | |
2609 | else | |
0dd2d296 ILT |
2610 | { |
2611 | assert (ep->X_op == O_symbol); | |
2612 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2613 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2614 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2615 | r = BFD_RELOC_HI16_S; | |
2616 | } | |
670a50eb ILT |
2617 | |
2618 | /* | |
2619 | * If the macro is about to expand into a second instruction, | |
2620 | * print a warning if needed. We need to pass ip as a parameter | |
2621 | * to generate a better warning message here... | |
2622 | */ | |
0dd2d296 | 2623 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2624 | as_warn ("Macro instruction expanded into multiple instructions"); |
2625 | ||
0dd2d296 ILT |
2626 | if (place == NULL) |
2627 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2628 | |
2629 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2630 | assert (insn.insn_mo); | |
2631 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2632 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2633 | ||
0dd2d296 | 2634 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2635 | if (r == BFD_RELOC_UNUSED) |
2636 | { | |
2637 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2638 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2639 | } |
2640 | else | |
867a58b3 | 2641 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2642 | } |
2643 | ||
2644 | /* set_at() | |
2645 | * Generates code to set the $at register to true (one) | |
2646 | * if reg is less than the immediate expression. | |
2647 | */ | |
2648 | static void | |
6e8dda9c | 2649 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2650 | int *counter; |
2651 | int reg; | |
6e8dda9c | 2652 | int unsignedp; |
3d3c5039 | 2653 | { |
6e8dda9c | 2654 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2655 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2656 | unsignedp ? "sltiu" : "slti", |
9226253a | 2657 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2658 | else |
670a50eb | 2659 | { |
d8a1c247 | 2660 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2661 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2662 | unsignedp ? "sltu" : "slt", |
2663 | "d,v,t", AT, reg, AT); | |
670a50eb | 2664 | } |
3d3c5039 ILT |
2665 | } |
2666 | ||
6e8dda9c | 2667 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2668 | |
2669 | static void | |
19ed8960 | 2670 | check_absolute_expr (ip, ex) |
3d3c5039 | 2671 | struct mips_cl_insn *ip; |
19ed8960 | 2672 | expressionS *ex; |
3d3c5039 | 2673 | { |
19ed8960 | 2674 | if (ex->X_op != O_constant) |
670a50eb | 2675 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2676 | } |
2677 | ||
ff8716f5 JSC |
2678 | /* Count the leading zeroes by performing a binary chop. This is a |
2679 | bulky bit of source, but performance is a LOT better for the | |
2680 | majority of values than a simple loop to count the bits: | |
2681 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2682 | if ((v) & (1 << (31 - lcnt))) | |
2683 | break; | |
2684 | However it is not code size friendly, and the gain will drop a bit | |
2685 | on certain cached systems. | |
2686 | */ | |
2687 | #define COUNT_TOP_ZEROES(v) \ | |
2688 | (((v) & ~0xffff) == 0 \ | |
2689 | ? ((v) & ~0xff) == 0 \ | |
2690 | ? ((v) & ~0xf) == 0 \ | |
2691 | ? ((v) & ~0x3) == 0 \ | |
2692 | ? ((v) & ~0x1) == 0 \ | |
2693 | ? !(v) \ | |
2694 | ? 32 \ | |
2695 | : 31 \ | |
2696 | : 30 \ | |
2697 | : ((v) & ~0x7) == 0 \ | |
2698 | ? 29 \ | |
2699 | : 28 \ | |
2700 | : ((v) & ~0x3f) == 0 \ | |
2701 | ? ((v) & ~0x1f) == 0 \ | |
2702 | ? 27 \ | |
2703 | : 26 \ | |
2704 | : ((v) & ~0x7f) == 0 \ | |
2705 | ? 25 \ | |
2706 | : 24 \ | |
2707 | : ((v) & ~0xfff) == 0 \ | |
2708 | ? ((v) & ~0x3ff) == 0 \ | |
2709 | ? ((v) & ~0x1ff) == 0 \ | |
2710 | ? 23 \ | |
2711 | : 22 \ | |
2712 | : ((v) & ~0x7ff) == 0 \ | |
2713 | ? 21 \ | |
2714 | : 20 \ | |
2715 | : ((v) & ~0x3fff) == 0 \ | |
2716 | ? ((v) & ~0x1fff) == 0 \ | |
2717 | ? 19 \ | |
2718 | : 18 \ | |
2719 | : ((v) & ~0x7fff) == 0 \ | |
2720 | ? 17 \ | |
2721 | : 16 \ | |
2722 | : ((v) & ~0xffffff) == 0 \ | |
2723 | ? ((v) & ~0xfffff) == 0 \ | |
2724 | ? ((v) & ~0x3ffff) == 0 \ | |
2725 | ? ((v) & ~0x1ffff) == 0 \ | |
2726 | ? 15 \ | |
2727 | : 14 \ | |
2728 | : ((v) & ~0x7ffff) == 0 \ | |
2729 | ? 13 \ | |
2730 | : 12 \ | |
2731 | : ((v) & ~0x3fffff) == 0 \ | |
2732 | ? ((v) & ~0x1fffff) == 0 \ | |
2733 | ? 11 \ | |
2734 | : 10 \ | |
2735 | : ((v) & ~0x7fffff) == 0 \ | |
2736 | ? 9 \ | |
2737 | : 8 \ | |
2738 | : ((v) & ~0xfffffff) == 0 \ | |
2739 | ? ((v) & ~0x3ffffff) == 0 \ | |
2740 | ? ((v) & ~0x1ffffff) == 0 \ | |
2741 | ? 7 \ | |
2742 | : 6 \ | |
2743 | : ((v) & ~0x7ffffff) == 0 \ | |
2744 | ? 5 \ | |
2745 | : 4 \ | |
2746 | : ((v) & ~0x3fffffff) == 0 \ | |
2747 | ? ((v) & ~0x1fffffff) == 0 \ | |
2748 | ? 3 \ | |
2749 | : 2 \ | |
2750 | : ((v) & ~0x7fffffff) == 0 \ | |
2751 | ? 1 \ | |
2752 | : 0) | |
2753 | ||
3d3c5039 ILT |
2754 | /* load_register() |
2755 | * This routine generates the least number of instructions neccessary to load | |
2756 | * an absolute expression value into a register. | |
2757 | */ | |
2758 | static void | |
d8a1c247 | 2759 | load_register (counter, reg, ep, dbl) |
670a50eb | 2760 | int *counter; |
670a50eb ILT |
2761 | int reg; |
2762 | expressionS *ep; | |
d8a1c247 | 2763 | int dbl; |
3d3c5039 | 2764 | { |
c36a90ef ILT |
2765 | int freg; |
2766 | expressionS hi32, lo32; | |
847a01cd ILT |
2767 | |
2768 | if (ep->X_op != O_big) | |
6e8dda9c | 2769 | { |
847a01cd | 2770 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2771 | if (ep->X_add_number < 0x8000 |
2772 | && (ep->X_add_number >= 0 | |
2773 | || (ep->X_add_number >= -0x8000 | |
2774 | && (! dbl | |
2775 | || ! ep->X_unsigned | |
2776 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2777 | { |
2778 | /* We can handle 16 bit signed values with an addiu to | |
2779 | $zero. No need to ever use daddiu here, since $zero and | |
2780 | the result are always correct in 32 bit mode. */ | |
2781 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2782 | (int) BFD_RELOC_LO16); | |
2783 | return; | |
2784 | } | |
2785 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2786 | { | |
2787 | /* We can handle 16 bit unsigned values with an ori to | |
2788 | $zero. */ | |
2789 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2790 | (int) BFD_RELOC_LO16); | |
2791 | return; | |
2792 | } | |
98bfd087 ILT |
2793 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2794 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2795 | == ~ (offsetT) 0x7fffffff)) | |
2796 | && (! dbl | |
2797 | || ! ep->X_unsigned | |
2798 | || sizeof (ep->X_add_number) > 4 | |
2799 | || (ep->X_add_number & 0x80000000) == 0)) | |
f59fb6ca ILT |
2800 | || ((mips_isa < 3 || ! dbl) |
2801 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) | |
2802 | || (mips_isa < 3 | |
2803 | && ! dbl | |
2804 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
2805 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
2806 | { |
2807 | /* 32 bit values require an lui. */ | |
2808 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2809 | (int) BFD_RELOC_HI16); | |
2810 | if ((ep->X_add_number & 0xffff) != 0) | |
2811 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2812 | (int) BFD_RELOC_LO16); | |
2813 | return; | |
2814 | } | |
6e8dda9c | 2815 | } |
847a01cd ILT |
2816 | |
2817 | /* The value is larger than 32 bits. */ | |
2818 | ||
2819 | if (mips_isa < 3) | |
670a50eb | 2820 | { |
6e8dda9c | 2821 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2822 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2823 | (int) BFD_RELOC_LO16); |
847a01cd | 2824 | return; |
6e8dda9c | 2825 | } |
6e8dda9c | 2826 | |
847a01cd ILT |
2827 | if (ep->X_op != O_big) |
2828 | { | |
6e8dda9c | 2829 | hi32 = *ep; |
c36a90ef ILT |
2830 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2831 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2832 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2833 | lo32 = *ep; |
2834 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2835 | } |
847a01cd ILT |
2836 | else |
2837 | { | |
2838 | assert (ep->X_add_number > 2); | |
2839 | if (ep->X_add_number == 3) | |
2840 | generic_bignum[3] = 0; | |
2841 | else if (ep->X_add_number > 4) | |
2842 | as_bad ("Number larger than 64 bits"); | |
2843 | lo32.X_op = O_constant; | |
2844 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2845 | hi32.X_op = O_constant; | |
2846 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2847 | } | |
2848 | ||
d8a1c247 KR |
2849 | if (hi32.X_add_number == 0) |
2850 | freg = 0; | |
2851 | else | |
2852 | { | |
c36a90ef ILT |
2853 | int shift, bit; |
2854 | unsigned long hi, lo; | |
2855 | ||
fb251650 ILT |
2856 | if (hi32.X_add_number == 0xffffffff) |
2857 | { | |
2858 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2859 | { | |
c36a90ef ILT |
2860 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2861 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2862 | return; |
2863 | } | |
2864 | if (lo32.X_add_number & 0x80000000) | |
2865 | { | |
2866 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2867 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2868 | if (lo32.X_add_number & 0xffff) |
2869 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2870 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2871 | return; |
2872 | } | |
2873 | } | |
ff8716f5 | 2874 | |
c36a90ef ILT |
2875 | /* Check for 16bit shifted constant. We know that hi32 is |
2876 | non-zero, so start the mask on the first bit of the hi32 | |
2877 | value. */ | |
ff8716f5 JSC |
2878 | shift = 17; |
2879 | do | |
2880 | { | |
c36a90ef ILT |
2881 | unsigned long himask, lomask; |
2882 | ||
2883 | if (shift < 32) | |
2884 | { | |
2885 | himask = 0xffff >> (32 - shift); | |
2886 | lomask = (0xffff << shift) & 0xffffffff; | |
2887 | } | |
2888 | else | |
2889 | { | |
2890 | himask = 0xffff << (shift - 32); | |
2891 | lomask = 0; | |
2892 | } | |
2893 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2894 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2895 | { | |
2896 | expressionS tmp; | |
2897 | ||
2898 | tmp.X_op = O_constant; | |
2899 | if (shift < 32) | |
2900 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2901 | | (lo32.X_add_number >> shift)); | |
2902 | else | |
2903 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2904 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2905 | (int) BFD_RELOC_LO16); | |
2906 | macro_build ((char *) NULL, counter, NULL, | |
2907 | (shift >= 32) ? "dsll32" : "dsll", | |
2908 | "d,w,<", reg, reg, | |
2909 | (shift >= 32) ? shift - 32 : shift); | |
2910 | return; | |
2911 | } | |
ff8716f5 JSC |
2912 | shift++; |
2913 | } while (shift <= (64 - 16)); | |
2914 | ||
c36a90ef ILT |
2915 | /* Find the bit number of the lowest one bit, and store the |
2916 | shifted value in hi/lo. */ | |
2917 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2918 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2919 | if (lo != 0) | |
2920 | { | |
2921 | bit = 0; | |
2922 | while ((lo & 1) == 0) | |
2923 | { | |
2924 | lo >>= 1; | |
2925 | ++bit; | |
2926 | } | |
2927 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2928 | hi >>= bit; | |
2929 | } | |
2930 | else | |
2931 | { | |
2932 | bit = 32; | |
2933 | while ((hi & 1) == 0) | |
2934 | { | |
2935 | hi >>= 1; | |
2936 | ++bit; | |
2937 | } | |
2938 | lo = hi; | |
2939 | hi = 0; | |
2940 | } | |
2941 | ||
2942 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2943 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2944 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2945 | { |
c36a90ef | 2946 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2947 | if (shift != 0) |
2948 | { | |
c36a90ef ILT |
2949 | expressionS tmp; |
2950 | ||
2951 | /* This instruction will set the register to be all | |
2952 | ones. */ | |
ff8716f5 | 2953 | tmp.X_op = O_constant; |
c36a90ef ILT |
2954 | tmp.X_add_number = (offsetT) -1; |
2955 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2956 | reg, 0, (int) BFD_RELOC_LO16); | |
2957 | if (bit != 0) | |
ff8716f5 | 2958 | { |
c36a90ef | 2959 | bit += shift; |
ff8716f5 | 2960 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2961 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2962 | "d,w,<", reg, reg, |
c36a90ef | 2963 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2964 | } |
c36a90ef ILT |
2965 | macro_build ((char *) NULL, counter, NULL, |
2966 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2967 | "d,w,<", reg, reg, | |
2968 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2969 | return; |
2970 | } | |
2971 | } | |
c36a90ef ILT |
2972 | |
2973 | /* Sign extend hi32 before calling load_register, because we can | |
2974 | generally get better code when we load a sign extended value. */ | |
2975 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2976 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2977 | load_register (counter, reg, &hi32, 0); |
2978 | freg = reg; | |
2979 | } | |
847a01cd | 2980 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2981 | { |
2982 | if (freg != 0) | |
2983 | { | |
2984 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2985 | freg, 0); | |
2986 | freg = reg; | |
2987 | } | |
2988 | } | |
847a01cd ILT |
2989 | else |
2990 | { | |
2991 | expressionS mid16; | |
2992 | ||
fb251650 ILT |
2993 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2994 | { | |
2995 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2996 | (int) BFD_RELOC_HI16); | |
2997 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2998 | reg, 0); |
fb251650 ILT |
2999 | return; |
3000 | } | |
3001 | ||
d8a1c247 KR |
3002 | if (freg != 0) |
3003 | { | |
3004 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3005 | freg, 16); | |
3006 | freg = reg; | |
3007 | } | |
847a01cd ILT |
3008 | mid16 = lo32; |
3009 | mid16.X_add_number >>= 16; | |
3010 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3011 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3012 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3013 | reg, 16); | |
d8a1c247 | 3014 | freg = reg; |
847a01cd ILT |
3015 | } |
3016 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3017 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3018 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3019 | } |
3020 | ||
0dd2d296 ILT |
3021 | /* Load an address into a register. */ |
3022 | ||
3023 | static void | |
3024 | load_address (counter, reg, ep) | |
3025 | int *counter; | |
3026 | int reg; | |
3027 | expressionS *ep; | |
3028 | { | |
3029 | char *p; | |
3030 | ||
3031 | if (ep->X_op != O_constant | |
3032 | && ep->X_op != O_symbol) | |
3033 | { | |
3034 | as_bad ("expression too complex"); | |
3035 | ep->X_op = O_constant; | |
3036 | } | |
3037 | ||
3038 | if (ep->X_op == O_constant) | |
d9aba805 | 3039 | { |
d8a1c247 | 3040 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3041 | return; |
3042 | } | |
3043 | ||
3044 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3045 | { |
3046 | /* If this is a reference to a GP relative symbol, we want | |
3047 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3048 | Otherwise we want | |
04cb3372 | 3049 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3050 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3051 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
3052 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
3053 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
3054 | p = NULL; |
3055 | else | |
3056 | { | |
8ea7f4e8 | 3057 | frag_grow (20); |
0dd2d296 ILT |
3058 | macro_build ((char *) NULL, counter, ep, |
3059 | mips_isa < 3 ? "addiu" : "daddiu", | |
3060 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3061 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 3062 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
f59fb6ca | 3063 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3064 | } |
3065 | macro_build_lui (p, counter, ep, reg); | |
3066 | if (p != NULL) | |
3067 | p += 4; | |
3068 | macro_build (p, counter, ep, | |
3069 | mips_isa < 3 ? "addiu" : "daddiu", | |
3070 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3071 | } | |
fb251650 | 3072 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3073 | { |
3074 | expressionS ex; | |
3075 | ||
3076 | /* If this is a reference to an external symbol, we want | |
3077 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3078 | Otherwise we want | |
3079 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3080 | nop | |
3081 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3082 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3083 | ex.X_add_number = ep->X_add_number; |
3084 | ep->X_add_number = 0; | |
8ea7f4e8 | 3085 | frag_grow (20); |
0dd2d296 ILT |
3086 | macro_build ((char *) NULL, counter, ep, |
3087 | mips_isa < 3 ? "lw" : "ld", | |
3088 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3089 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3090 | p = frag_var (rs_machine_dependent, 4, 0, | |
3091 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
f59fb6ca | 3092 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3093 | macro_build (p, counter, ep, |
3094 | mips_isa < 3 ? "addiu" : "daddiu", | |
3095 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3096 | if (ex.X_add_number != 0) | |
3097 | { | |
3098 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3099 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3100 | ex.X_op = O_constant; | |
fb251650 ILT |
3101 | macro_build ((char *) NULL, counter, &ex, |
3102 | mips_isa < 3 ? "addiu" : "daddiu", | |
3103 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3104 | } | |
3105 | } | |
3106 | else if (mips_pic == SVR4_PIC) | |
3107 | { | |
3108 | expressionS ex; | |
3109 | int off; | |
3110 | ||
3111 | /* This is the large GOT case. If this is a reference to an | |
3112 | external symbol, we want | |
3113 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3114 | addu $reg,$reg,$gp | |
3115 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3116 | Otherwise, for a reference to a local symbol, we want | |
3117 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3118 | nop | |
3119 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3120 | If there is a constant, it must be added in after. */ | |
3121 | ex.X_add_number = ep->X_add_number; | |
3122 | ep->X_add_number = 0; | |
3123 | if (reg_needs_delay (GP)) | |
3124 | off = 4; | |
3125 | else | |
3126 | off = 0; | |
3127 | frag_grow (32); | |
3128 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3129 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3130 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3131 | mips_isa < 3 ? "addu" : "daddu", | |
3132 | "d,v,t", reg, reg, GP); | |
3133 | macro_build ((char *) NULL, counter, ep, | |
3134 | mips_isa < 3 ? "lw" : "ld", | |
3135 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3136 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3137 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3138 | mips_warn_about_macros), | |
f59fb6ca | 3139 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3140 | if (off > 0) |
3141 | { | |
3142 | /* We need a nop before loading from $gp. This special | |
3143 | check is required because the lui which starts the main | |
3144 | instruction stream does not refer to $gp, and so will not | |
3145 | insert the nop which may be required. */ | |
3146 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3147 | p += 4; | |
3148 | } | |
3149 | macro_build (p, counter, ep, | |
3150 | mips_isa < 3 ? "lw" : "ld", | |
3151 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3152 | p += 4; | |
3153 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3154 | p += 4; | |
3155 | macro_build (p, counter, ep, | |
3156 | mips_isa < 3 ? "addiu" : "daddiu", | |
3157 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3158 | if (ex.X_add_number != 0) | |
3159 | { | |
3160 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3161 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3162 | ex.X_op = O_constant; | |
3163 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
3164 | mips_isa < 3 ? "addiu" : "daddiu", |
3165 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3166 | } | |
d9aba805 ILT |
3167 | } |
3168 | else if (mips_pic == EMBEDDED_PIC) | |
3169 | { | |
3170 | /* We always do | |
3171 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3172 | */ | |
3173 | macro_build ((char *) NULL, counter, ep, | |
3174 | mips_isa < 3 ? "addiu" : "daddiu", | |
3175 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3176 | } | |
3177 | else | |
3178 | abort (); | |
0dd2d296 ILT |
3179 | } |
3180 | ||
3d3c5039 ILT |
3181 | /* |
3182 | * Build macros | |
3183 | * This routine implements the seemingly endless macro or synthesized | |
3184 | * instructions and addressing modes in the mips assembly language. Many | |
3185 | * of these macros are simple and are similar to each other. These could | |
3186 | * probably be handled by some kind of table or grammer aproach instead of | |
3187 | * this verbose method. Others are not simple macros but are more like | |
3188 | * optimizing code generation. | |
3189 | * One interesting optimization is when several store macros appear | |
3190 | * consecutivly that would load AT with the upper half of the same address. | |
3191 | * The ensuing load upper instructions are ommited. This implies some kind | |
3192 | * of global optimization. We currently only optimize within a single macro. | |
3193 | * For many of the load and store macros if the address is specified as a | |
3194 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3195 | * first load register 'at' with zero and use it as the base register. The | |
3196 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3197 | * we're missing. | |
3198 | */ | |
3199 | static void | |
3200 | macro (ip) | |
3201 | struct mips_cl_insn *ip; | |
3202 | { | |
670a50eb ILT |
3203 | register int treg, sreg, dreg, breg; |
3204 | int tempreg; | |
3205 | int mask; | |
3206 | int icnt = 0; | |
3207 | int used_at; | |
670a50eb ILT |
3208 | expressionS expr1; |
3209 | const char *s; | |
8358c818 | 3210 | const char *s2; |
670a50eb | 3211 | const char *fmt; |
8358c818 ILT |
3212 | int likely = 0; |
3213 | int dbl = 0; | |
3214 | int coproc = 0; | |
b2b8c24e | 3215 | int lr = 0; |
6e8dda9c | 3216 | offsetT maxnum; |
adcf2b9d | 3217 | int off; |
9226253a | 3218 | bfd_reloc_code_real_type r; |
0dd2d296 | 3219 | char *p; |
55933a58 | 3220 | int hold_mips_optimize; |
670a50eb | 3221 | |
cc5703cd ILT |
3222 | assert (! mips16); |
3223 | ||
670a50eb ILT |
3224 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3225 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3226 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3227 | mask = ip->insn_mo->mask; | |
3228 | ||
5ac34ac3 ILT |
3229 | expr1.X_op = O_constant; |
3230 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3231 | expr1.X_add_symbol = NULL; |
3232 | expr1.X_add_number = 1; | |
3233 | ||
3234 | switch (mask) | |
3235 | { | |
6e8dda9c ILT |
3236 | case M_DABS: |
3237 | dbl = 1; | |
3d3c5039 | 3238 | case M_ABS: |
6e8dda9c ILT |
3239 | /* bgez $a0,.+12 |
3240 | move v0,$a0 | |
3241 | sub v0,$zero,$a0 | |
3242 | */ | |
3d3c5039 | 3243 | |
fbcfacb7 | 3244 | mips_emit_delays (true); |
becfe05e | 3245 | ++mips_noreorder; |
0dd2d296 | 3246 | mips_any_noreorder = 1; |
3d3c5039 | 3247 | |
670a50eb | 3248 | expr1.X_add_number = 8; |
0dd2d296 | 3249 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3250 | if (dreg == sreg) |
0dd2d296 | 3251 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3252 | else |
0dd2d296 ILT |
3253 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3254 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3255 | dbl ? "dsub" : "sub", |
3256 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3257 | |
becfe05e | 3258 | --mips_noreorder; |
670a50eb | 3259 | return; |
3d3c5039 ILT |
3260 | |
3261 | case M_ADD_I: | |
8358c818 ILT |
3262 | s = "addi"; |
3263 | s2 = "add"; | |
3264 | goto do_addi; | |
3d3c5039 | 3265 | case M_ADDU_I: |
8358c818 ILT |
3266 | s = "addiu"; |
3267 | s2 = "addu"; | |
3268 | goto do_addi; | |
3269 | case M_DADD_I: | |
6e8dda9c | 3270 | dbl = 1; |
8358c818 ILT |
3271 | s = "daddi"; |
3272 | s2 = "dadd"; | |
3273 | goto do_addi; | |
3274 | case M_DADDU_I: | |
6e8dda9c | 3275 | dbl = 1; |
8358c818 ILT |
3276 | s = "daddiu"; |
3277 | s2 = "daddu"; | |
3278 | do_addi: | |
6e8dda9c | 3279 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3280 | { |
0dd2d296 | 3281 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3282 | (int) BFD_RELOC_LO16); |
670a50eb | 3283 | return; |
3d3c5039 | 3284 | } |
d8a1c247 | 3285 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3286 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3287 | break; |
3d3c5039 ILT |
3288 | |
3289 | case M_AND_I: | |
6e8dda9c ILT |
3290 | s = "andi"; |
3291 | s2 = "and"; | |
3292 | goto do_bit; | |
3d3c5039 | 3293 | case M_OR_I: |
6e8dda9c ILT |
3294 | s = "ori"; |
3295 | s2 = "or"; | |
3296 | goto do_bit; | |
3d3c5039 | 3297 | case M_NOR_I: |
6e8dda9c ILT |
3298 | s = ""; |
3299 | s2 = "nor"; | |
3300 | goto do_bit; | |
3d3c5039 | 3301 | case M_XOR_I: |
6e8dda9c ILT |
3302 | s = "xori"; |
3303 | s2 = "xor"; | |
3304 | do_bit: | |
3305 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3306 | { |
6e8dda9c | 3307 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3308 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3309 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3310 | else |
670a50eb | 3311 | { |
0dd2d296 ILT |
3312 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3313 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3314 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3315 | treg, treg, 0); |
3d3c5039 | 3316 | } |
6e8dda9c | 3317 | return; |
3d3c5039 | 3318 | } |
6e8dda9c | 3319 | |
d8a1c247 | 3320 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3321 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3322 | break; |
3d3c5039 ILT |
3323 | |
3324 | case M_BEQ_I: | |
8358c818 ILT |
3325 | s = "beq"; |
3326 | goto beq_i; | |
3327 | case M_BEQL_I: | |
3328 | s = "beql"; | |
3329 | likely = 1; | |
3330 | goto beq_i; | |
3d3c5039 | 3331 | case M_BNE_I: |
8358c818 ILT |
3332 | s = "bne"; |
3333 | goto beq_i; | |
3334 | case M_BNEL_I: | |
3335 | s = "bnel"; | |
3336 | likely = 1; | |
3337 | beq_i: | |
670a50eb ILT |
3338 | if (imm_expr.X_add_number == 0) |
3339 | { | |
0dd2d296 ILT |
3340 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3341 | 0); | |
670a50eb ILT |
3342 | return; |
3343 | } | |
d8a1c247 | 3344 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3345 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3346 | break; |
3d3c5039 | 3347 | |
8358c818 ILT |
3348 | case M_BGEL: |
3349 | likely = 1; | |
3d3c5039 | 3350 | case M_BGE: |
670a50eb ILT |
3351 | if (treg == 0) |
3352 | { | |
0dd2d296 | 3353 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3354 | likely ? "bgezl" : "bgez", |
3355 | "s,p", sreg); | |
670a50eb | 3356 | return; |
3d3c5039 | 3357 | } |
9a7d824a ILT |
3358 | if (sreg == 0) |
3359 | { | |
0dd2d296 | 3360 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3361 | likely ? "blezl" : "blez", |
3362 | "s,p", treg); | |
9a7d824a ILT |
3363 | return; |
3364 | } | |
0dd2d296 ILT |
3365 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3366 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3367 | likely ? "beql" : "beq", |
3368 | "s,t,p", AT, 0); | |
670a50eb | 3369 | break; |
3d3c5039 | 3370 | |
8358c818 ILT |
3371 | case M_BGTL_I: |
3372 | likely = 1; | |
3d3c5039 | 3373 | case M_BGT_I: |
9a7d824a | 3374 | /* check for > max integer */ |
6e8dda9c ILT |
3375 | maxnum = 0x7fffffff; |
3376 | if (mips_isa >= 3) | |
3377 | { | |
3378 | maxnum <<= 16; | |
3379 | maxnum |= 0xffff; | |
3380 | maxnum <<= 16; | |
3381 | maxnum |= 0xffff; | |
3382 | } | |
7b777690 ILT |
3383 | if (imm_expr.X_add_number >= maxnum |
3384 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3385 | { |
3386 | do_false: | |
3387 | /* result is always false */ | |
8358c818 ILT |
3388 | if (! likely) |
3389 | { | |
3390 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3391 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3392 | } |
3393 | else | |
3394 | { | |
3395 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3396 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3397 | "s,t,p", 0, 0); | |
8358c818 | 3398 | } |
9a7d824a ILT |
3399 | return; |
3400 | } | |
670a50eb ILT |
3401 | imm_expr.X_add_number++; |
3402 | /* FALLTHROUGH */ | |
3d3c5039 | 3403 | case M_BGE_I: |
8358c818 ILT |
3404 | case M_BGEL_I: |
3405 | if (mask == M_BGEL_I) | |
3406 | likely = 1; | |
670a50eb ILT |
3407 | if (imm_expr.X_add_number == 0) |
3408 | { | |
0dd2d296 | 3409 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3410 | likely ? "bgezl" : "bgez", |
3411 | "s,p", sreg); | |
670a50eb | 3412 | return; |
3d3c5039 | 3413 | } |
670a50eb ILT |
3414 | if (imm_expr.X_add_number == 1) |
3415 | { | |
0dd2d296 | 3416 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3417 | likely ? "bgtzl" : "bgtz", |
3418 | "s,p", sreg); | |
670a50eb | 3419 | return; |
3d3c5039 | 3420 | } |
6e8dda9c ILT |
3421 | maxnum = 0x7fffffff; |
3422 | if (mips_isa >= 3) | |
3423 | { | |
3424 | maxnum <<= 16; | |
3425 | maxnum |= 0xffff; | |
3426 | maxnum <<= 16; | |
3427 | maxnum |= 0xffff; | |
3428 | } | |
3429 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3430 | if (imm_expr.X_add_number <= maxnum |
3431 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3432 | { |
3433 | do_true: | |
3434 | /* result is always true */ | |
3435 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3436 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3437 | return; |
3438 | } | |
6e8dda9c | 3439 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3440 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3441 | likely ? "beql" : "beq", |
3442 | "s,t,p", AT, 0); | |
670a50eb | 3443 | break; |
3d3c5039 | 3444 | |
8358c818 ILT |
3445 | case M_BGEUL: |
3446 | likely = 1; | |
3d3c5039 | 3447 | case M_BGEU: |
670a50eb | 3448 | if (treg == 0) |
9a7d824a ILT |
3449 | goto do_true; |
3450 | if (sreg == 0) | |
670a50eb | 3451 | { |
0dd2d296 | 3452 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3453 | likely ? "beql" : "beq", |
3454 | "s,t,p", 0, treg); | |
670a50eb | 3455 | return; |
3d3c5039 | 3456 | } |
0dd2d296 ILT |
3457 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3458 | treg); | |
3459 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3460 | likely ? "beql" : "beq", |
3461 | "s,t,p", AT, 0); | |
670a50eb | 3462 | break; |
3d3c5039 | 3463 | |
8358c818 ILT |
3464 | case M_BGTUL_I: |
3465 | likely = 1; | |
9a7d824a | 3466 | case M_BGTU_I: |
6e8dda9c | 3467 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3468 | goto do_false; |
3469 | imm_expr.X_add_number++; | |
3470 | /* FALLTHROUGH */ | |
3d3c5039 | 3471 | case M_BGEU_I: |
8358c818 ILT |
3472 | case M_BGEUL_I: |
3473 | if (mask == M_BGEUL_I) | |
3474 | likely = 1; | |
670a50eb | 3475 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3476 | goto do_true; |
670a50eb ILT |
3477 | if (imm_expr.X_add_number == 1) |
3478 | { | |
0dd2d296 | 3479 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3480 | likely ? "bnel" : "bne", |
3481 | "s,t,p", sreg, 0); | |
670a50eb | 3482 | return; |
3d3c5039 | 3483 | } |
6e8dda9c | 3484 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3485 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3486 | likely ? "beql" : "beq", |
3487 | "s,t,p", AT, 0); | |
670a50eb | 3488 | break; |
3d3c5039 | 3489 | |
8358c818 ILT |
3490 | case M_BGTL: |
3491 | likely = 1; | |
3d3c5039 | 3492 | case M_BGT: |
670a50eb ILT |
3493 | if (treg == 0) |
3494 | { | |
0dd2d296 | 3495 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3496 | likely ? "bgtzl" : "bgtz", |
3497 | "s,p", sreg); | |
670a50eb | 3498 | return; |
3d3c5039 | 3499 | } |
9a7d824a ILT |
3500 | if (sreg == 0) |
3501 | { | |
0dd2d296 | 3502 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3503 | likely ? "bltzl" : "bltz", |
3504 | "s,p", treg); | |
9a7d824a ILT |
3505 | return; |
3506 | } | |
0dd2d296 ILT |
3507 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3508 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3509 | likely ? "bnel" : "bne", |
3510 | "s,t,p", AT, 0); | |
670a50eb | 3511 | break; |
3d3c5039 | 3512 | |
8358c818 ILT |
3513 | case M_BGTUL: |
3514 | likely = 1; | |
3d3c5039 | 3515 | case M_BGTU: |
670a50eb ILT |
3516 | if (treg == 0) |
3517 | { | |
0dd2d296 | 3518 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3519 | likely ? "bnel" : "bne", |
3520 | "s,t,p", sreg, 0); | |
670a50eb | 3521 | return; |
3d3c5039 | 3522 | } |
9a7d824a ILT |
3523 | if (sreg == 0) |
3524 | goto do_false; | |
0dd2d296 ILT |
3525 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3526 | sreg); | |
3527 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3528 | likely ? "bnel" : "bne", |
3529 | "s,t,p", AT, 0); | |
670a50eb | 3530 | break; |
3d3c5039 | 3531 | |
8358c818 ILT |
3532 | case M_BLEL: |
3533 | likely = 1; | |
3d3c5039 | 3534 | case M_BLE: |
670a50eb ILT |
3535 | if (treg == 0) |
3536 | { | |
0dd2d296 | 3537 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3538 | likely ? "blezl" : "blez", |
3539 | "s,p", sreg); | |
670a50eb ILT |
3540 | return; |
3541 | } | |
9a7d824a ILT |
3542 | if (sreg == 0) |
3543 | { | |
0dd2d296 | 3544 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3545 | likely ? "bgezl" : "bgez", |
3546 | "s,p", treg); | |
9a7d824a ILT |
3547 | return; |
3548 | } | |
0dd2d296 ILT |
3549 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3550 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3551 | likely ? "beql" : "beq", |
3552 | "s,t,p", AT, 0); | |
670a50eb | 3553 | break; |
3d3c5039 | 3554 | |
8358c818 ILT |
3555 | case M_BLEL_I: |
3556 | likely = 1; | |
3d3c5039 | 3557 | case M_BLE_I: |
6e8dda9c ILT |
3558 | maxnum = 0x7fffffff; |
3559 | if (mips_isa >= 3) | |
3560 | { | |
3561 | maxnum <<= 16; | |
3562 | maxnum |= 0xffff; | |
3563 | maxnum <<= 16; | |
3564 | maxnum |= 0xffff; | |
3565 | } | |
7b777690 ILT |
3566 | if (imm_expr.X_add_number >= maxnum |
3567 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3568 | goto do_true; |
3569 | imm_expr.X_add_number++; | |
3570 | /* FALLTHROUGH */ | |
9a7d824a | 3571 | case M_BLT_I: |
8358c818 ILT |
3572 | case M_BLTL_I: |
3573 | if (mask == M_BLTL_I) | |
3574 | likely = 1; | |
670a50eb ILT |
3575 | if (imm_expr.X_add_number == 0) |
3576 | { | |
0dd2d296 | 3577 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3578 | likely ? "bltzl" : "bltz", |
3579 | "s,p", sreg); | |
670a50eb ILT |
3580 | return; |
3581 | } | |
9a7d824a | 3582 | if (imm_expr.X_add_number == 1) |
670a50eb | 3583 | { |
0dd2d296 | 3584 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3585 | likely ? "blezl" : "blez", |
3586 | "s,p", sreg); | |
670a50eb ILT |
3587 | return; |
3588 | } | |
6e8dda9c | 3589 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3590 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3591 | likely ? "bnel" : "bne", |
3592 | "s,t,p", AT, 0); | |
670a50eb | 3593 | break; |
3d3c5039 | 3594 | |
8358c818 ILT |
3595 | case M_BLEUL: |
3596 | likely = 1; | |
3d3c5039 | 3597 | case M_BLEU: |
670a50eb ILT |
3598 | if (treg == 0) |
3599 | { | |
0dd2d296 | 3600 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3601 | likely ? "beql" : "beq", |
3602 | "s,t,p", sreg, 0); | |
670a50eb | 3603 | return; |
3d3c5039 | 3604 | } |
9a7d824a ILT |
3605 | if (sreg == 0) |
3606 | goto do_true; | |
0dd2d296 ILT |
3607 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3608 | sreg); | |
3609 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3610 | likely ? "beql" : "beq", |
3611 | "s,t,p", AT, 0); | |
670a50eb | 3612 | break; |
3d3c5039 | 3613 | |
8358c818 ILT |
3614 | case M_BLEUL_I: |
3615 | likely = 1; | |
3d3c5039 | 3616 | case M_BLEU_I: |
6e8dda9c | 3617 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3618 | goto do_true; |
3619 | imm_expr.X_add_number++; | |
3620 | /* FALLTHROUGH */ | |
9a7d824a | 3621 | case M_BLTU_I: |
8358c818 ILT |
3622 | case M_BLTUL_I: |
3623 | if (mask == M_BLTUL_I) | |
3624 | likely = 1; | |
670a50eb | 3625 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3626 | goto do_false; |
3627 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3628 | { |
0dd2d296 | 3629 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3630 | likely ? "beql" : "beq", |
3631 | "s,t,p", sreg, 0); | |
670a50eb | 3632 | return; |
3d3c5039 | 3633 | } |
6e8dda9c | 3634 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3635 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3636 | likely ? "bnel" : "bne", |
3637 | "s,t,p", AT, 0); | |
670a50eb | 3638 | break; |
3d3c5039 | 3639 | |
8358c818 ILT |
3640 | case M_BLTL: |
3641 | likely = 1; | |
3d3c5039 | 3642 | case M_BLT: |
670a50eb ILT |
3643 | if (treg == 0) |
3644 | { | |
0dd2d296 | 3645 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3646 | likely ? "bltzl" : "bltz", |
3647 | "s,p", sreg); | |
670a50eb | 3648 | return; |
3d3c5039 | 3649 | } |
9a7d824a | 3650 | if (sreg == 0) |
670a50eb | 3651 | { |
0dd2d296 | 3652 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3653 | likely ? "bgtzl" : "bgtz", |
3654 | "s,p", treg); | |
670a50eb | 3655 | return; |
3d3c5039 | 3656 | } |
0dd2d296 ILT |
3657 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3658 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3659 | likely ? "bnel" : "bne", |
3660 | "s,t,p", AT, 0); | |
670a50eb | 3661 | break; |
3d3c5039 | 3662 | |
8358c818 ILT |
3663 | case M_BLTUL: |
3664 | likely = 1; | |
3d3c5039 | 3665 | case M_BLTU: |
670a50eb | 3666 | if (treg == 0) |
9a7d824a ILT |
3667 | goto do_false; |
3668 | if (sreg == 0) | |
670a50eb | 3669 | { |
0dd2d296 | 3670 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3671 | likely ? "bnel" : "bne", |
3672 | "s,t,p", 0, treg); | |
670a50eb ILT |
3673 | return; |
3674 | } | |
0dd2d296 ILT |
3675 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3676 | treg); | |
3677 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3678 | likely ? "bnel" : "bne", |
3679 | "s,t,p", AT, 0); | |
670a50eb | 3680 | break; |
3d3c5039 | 3681 | |
8358c818 ILT |
3682 | case M_DDIV_3: |
3683 | dbl = 1; | |
3d3c5039 | 3684 | case M_DIV_3: |
8358c818 ILT |
3685 | s = "mflo"; |
3686 | goto do_div3; | |
3687 | case M_DREM_3: | |
3688 | dbl = 1; | |
3d3c5039 | 3689 | case M_REM_3: |
8358c818 ILT |
3690 | s = "mfhi"; |
3691 | do_div3: | |
670a50eb ILT |
3692 | if (treg == 0) |
3693 | { | |
3694 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3695 | if (mips_trap) |
3696 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3697 | else | |
3698 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3699 | return; |
3700 | } | |
3701 | ||
fbcfacb7 | 3702 | mips_emit_delays (true); |
becfe05e | 3703 | ++mips_noreorder; |
0dd2d296 ILT |
3704 | mips_any_noreorder = 1; |
3705 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3706 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3707 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3708 | if (mips_trap) |
3709 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3710 | else | |
3711 | { | |
3712 | expr1.X_add_number = 8; | |
3713 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3714 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3715 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3716 | } | |
670a50eb | 3717 | expr1.X_add_number = -1; |
0dd2d296 | 3718 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3719 | dbl ? "daddiu" : "addiu", |
9226253a | 3720 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3721 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3722 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3723 | if (dbl) |
3724 | { | |
3725 | expr1.X_add_number = 1; | |
0dd2d296 | 3726 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3727 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3728 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3729 | 31); | |
8358c818 ILT |
3730 | } |
3731 | else | |
3732 | { | |
3733 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3734 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3735 | (int) BFD_RELOC_HI16); | |
8358c818 | 3736 | } |
8ea7f4e8 ILT |
3737 | if (mips_trap) |
3738 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3739 | else | |
3740 | { | |
3741 | expr1.X_add_number = 8; | |
3742 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3743 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3744 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3745 | } | |
becfe05e | 3746 | --mips_noreorder; |
0dd2d296 | 3747 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3748 | break; |
3d3c5039 ILT |
3749 | |
3750 | case M_DIV_3I: | |
8358c818 ILT |
3751 | s = "div"; |
3752 | s2 = "mflo"; | |
3753 | goto do_divi; | |
3d3c5039 | 3754 | case M_DIVU_3I: |
8358c818 ILT |
3755 | s = "divu"; |
3756 | s2 = "mflo"; | |
3757 | goto do_divi; | |
3d3c5039 | 3758 | case M_REM_3I: |
8358c818 ILT |
3759 | s = "div"; |
3760 | s2 = "mfhi"; | |
3761 | goto do_divi; | |
3d3c5039 | 3762 | case M_REMU_3I: |
8358c818 ILT |
3763 | s = "divu"; |
3764 | s2 = "mfhi"; | |
3765 | goto do_divi; | |
3766 | case M_DDIV_3I: | |
3767 | dbl = 1; | |
3768 | s = "ddiv"; | |
3769 | s2 = "mflo"; | |
3770 | goto do_divi; | |
3771 | case M_DDIVU_3I: | |
3772 | dbl = 1; | |
3773 | s = "ddivu"; | |
3774 | s2 = "mflo"; | |
3775 | goto do_divi; | |
3776 | case M_DREM_3I: | |
3777 | dbl = 1; | |
3778 | s = "ddiv"; | |
3779 | s2 = "mfhi"; | |
3780 | goto do_divi; | |
3781 | case M_DREMU_3I: | |
3782 | dbl = 1; | |
3783 | s = "ddivu"; | |
3784 | s2 = "mfhi"; | |
3785 | do_divi: | |
670a50eb ILT |
3786 | if (imm_expr.X_add_number == 0) |
3787 | { | |
3788 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3789 | if (mips_trap) |
3790 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3791 | else | |
3792 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3793 | return; |
3794 | } | |
3795 | if (imm_expr.X_add_number == 1) | |
3796 | { | |
8358c818 | 3797 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3798 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3799 | sreg); | |
3d3c5039 | 3800 | else |
0dd2d296 | 3801 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3802 | return; |
3803 | } | |
8358c818 ILT |
3804 | if (imm_expr.X_add_number == -1 |
3805 | && s[strlen (s) - 1] != 'u') | |
3806 | { | |
3807 | if (strcmp (s2, "mflo") == 0) | |
3808 | { | |
3809 | if (dbl) | |
0dd2d296 ILT |
3810 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3811 | sreg); | |
8358c818 | 3812 | else |
0dd2d296 ILT |
3813 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3814 | sreg); | |
8358c818 ILT |
3815 | } |
3816 | else | |
0dd2d296 | 3817 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3818 | return; |
3819 | } | |
3d3c5039 | 3820 | |
d8a1c247 | 3821 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3822 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3823 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3824 | break; |
3825 | ||
3826 | case M_DIVU_3: | |
8358c818 ILT |
3827 | s = "divu"; |
3828 | s2 = "mflo"; | |
3829 | goto do_divu3; | |
670a50eb | 3830 | case M_REMU_3: |
8358c818 ILT |
3831 | s = "divu"; |
3832 | s2 = "mfhi"; | |
3833 | goto do_divu3; | |
3834 | case M_DDIVU_3: | |
3835 | s = "ddivu"; | |
3836 | s2 = "mflo"; | |
3837 | goto do_divu3; | |
3838 | case M_DREMU_3: | |
3839 | s = "ddivu"; | |
3840 | s2 = "mfhi"; | |
3841 | do_divu3: | |
fbcfacb7 | 3842 | mips_emit_delays (true); |
becfe05e | 3843 | ++mips_noreorder; |
0dd2d296 ILT |
3844 | mips_any_noreorder = 1; |
3845 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3846 | if (mips_trap) |
3847 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3848 | else | |
3849 | { | |
3850 | expr1.X_add_number = 8; | |
3851 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3852 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3853 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3854 | } | |
becfe05e | 3855 | --mips_noreorder; |
0dd2d296 | 3856 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3857 | return; |
3d3c5039 | 3858 | |
d8a1c247 KR |
3859 | case M_DLA_AB: |
3860 | dbl = 1; | |
0dd2d296 | 3861 | case M_LA_AB: |
d9aba805 ILT |
3862 | /* Load the address of a symbol into a register. If breg is not |
3863 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3864 | |
3865 | /* When generating embedded PIC code, we permit expressions of | |
3866 | the form | |
3867 | la $4,foo-bar | |
3868 | where bar is an address in the .text section. These are used | |
3869 | when getting the addresses of functions. We don't permit | |
3870 | X_add_number to be non-zero, because if the symbol is | |
3871 | external the relaxing code needs to know that any addend is | |
3872 | purely the offset to X_op_symbol. */ | |
3873 | if (mips_pic == EMBEDDED_PIC | |
3874 | && offset_expr.X_op == O_subtract | |
3875 | && now_seg == text_section | |
847a01cd ILT |
3876 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3877 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3878 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3879 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3880 | ->sy_value.X_add_symbol) | |
3881 | == text_section))) | |
ecd4ca1c ILT |
3882 | && breg == 0 |
3883 | && offset_expr.X_add_number == 0) | |
3884 | { | |
3885 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3886 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3887 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3888 | mips_isa < 3 ? "addiu" : "daddiu", | |
3889 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3890 | return; | |
3891 | } | |
3892 | ||
0dd2d296 ILT |
3893 | if (offset_expr.X_op != O_symbol |
3894 | && offset_expr.X_op != O_constant) | |
670a50eb | 3895 | { |
0dd2d296 ILT |
3896 | as_bad ("expression too complex"); |
3897 | offset_expr.X_op = O_constant; | |
3898 | } | |
3899 | ||
3900 | if (treg == breg) | |
3901 | { | |
3902 | tempreg = AT; | |
3903 | used_at = 1; | |
3d3c5039 | 3904 | } |
670a50eb ILT |
3905 | else |
3906 | { | |
0dd2d296 ILT |
3907 | tempreg = treg; |
3908 | used_at = 0; | |
670a50eb | 3909 | } |
3d3c5039 | 3910 | |
5ac34ac3 | 3911 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3912 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3913 | else if (mips_pic == NO_PIC) |
670a50eb | 3914 | { |
0dd2d296 ILT |
3915 | /* If this is a reference to an GP relative symbol, we want |
3916 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3917 | Otherwise we want | |
3918 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3919 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3920 | If we have a constant, we need two instructions anyhow, | |
3921 | so we may as well always use the latter form. */ | |
7a15a226 | 3922 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3923 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3924 | p = NULL; |
3925 | else | |
3926 | { | |
8ea7f4e8 | 3927 | frag_grow (20); |
0dd2d296 ILT |
3928 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3929 | mips_isa < 3 ? "addiu" : "daddiu", | |
3930 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3931 | p = frag_var (rs_machine_dependent, 8, 0, | |
3932 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3933 | mips_warn_about_macros), | |
f59fb6ca | 3934 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
3935 | (char *) NULL); |
3936 | } | |
3937 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3938 | if (p != NULL) | |
3939 | p += 4; | |
3940 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3941 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3942 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3943 | } | |
fb251650 | 3944 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3945 | { |
3946 | /* If this is a reference to an external symbol, and there | |
3947 | is no constant, we want | |
3948 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3949 | For a local symbol, we want | |
3950 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3951 | nop | |
3952 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3953 | ||
3954 | If we have a small constant, and this is a reference to | |
3955 | an external symbol, we want | |
3956 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3957 | nop | |
3958 | addiu $tempreg,$tempreg,<constant> | |
3959 | For a local symbol, we want the same instruction | |
3960 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3961 | addiu instruction. | |
3962 | ||
3963 | If we have a large constant, and this is a reference to | |
3964 | an external symbol, we want | |
3965 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3966 | lui $at,<hiconstant> | |
3967 | addiu $at,$at,<loconstant> | |
3968 | addu $tempreg,$tempreg,$at | |
3969 | For a local symbol, we want the same instruction | |
3970 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3971 | addiu instruction. */ | |
3972 | expr1.X_add_number = offset_expr.X_add_number; | |
3973 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3974 | frag_grow (32); |
0dd2d296 | 3975 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3976 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3977 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3978 | if (expr1.X_add_number == 0) | |
3979 | { | |
3980 | int off; | |
3981 | ||
3982 | if (breg == 0) | |
3983 | off = 0; | |
3984 | else | |
3985 | { | |
3986 | /* We're going to put in an addu instruction using | |
3987 | tempreg, so we may as well insert the nop right | |
3988 | now. */ | |
3989 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3990 | "nop", ""); | |
3991 | off = 4; | |
3992 | } | |
3993 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3994 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3995 | (breg == 0 | |
3996 | ? mips_warn_about_macros | |
3997 | : 0)), | |
f59fb6ca | 3998 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
3999 | (char *) NULL); |
4000 | if (breg == 0) | |
4001 | { | |
4002 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4003 | p += 4; | |
4004 | } | |
4005 | macro_build (p, &icnt, &expr1, | |
4006 | mips_isa < 3 ? "addiu" : "daddiu", | |
4007 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4008 | /* FIXME: If breg == 0, and the next instruction uses | |
4009 | $tempreg, then if this variant case is used an extra | |
4010 | nop will be generated. */ | |
4011 | } | |
4012 | else if (expr1.X_add_number >= -0x8000 | |
4013 | && expr1.X_add_number < 0x8000) | |
4014 | { | |
4015 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4016 | "nop", ""); | |
4017 | macro_build ((char *) NULL, &icnt, &expr1, | |
4018 | mips_isa < 3 ? "addiu" : "daddiu", | |
4019 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4020 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4021 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4022 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4023 | (char *) NULL); |
4024 | } | |
4025 | else | |
4026 | { | |
4027 | int off1; | |
4028 | ||
4029 | /* If we are going to add in a base register, and the | |
4030 | target register and the base register are the same, | |
4031 | then we are using AT as a temporary register. Since | |
4032 | we want to load the constant into AT, we add our | |
4033 | current AT (from the global offset table) and the | |
4034 | register into the register now, and pretend we were | |
4035 | not using a base register. */ | |
4036 | if (breg != treg) | |
4037 | off1 = 0; | |
4038 | else | |
4039 | { | |
4040 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4041 | "nop", ""); | |
4042 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4043 | mips_isa < 3 ? "addu" : "daddu", | |
4044 | "d,v,t", treg, AT, breg); | |
4045 | breg = 0; | |
4046 | tempreg = treg; | |
4047 | off1 = -8; | |
4048 | } | |
4049 | ||
55933a58 ILT |
4050 | /* Set mips_optimize around the lui instruction to avoid |
4051 | inserting an unnecessary nop after the lw. */ | |
4052 | hold_mips_optimize = mips_optimize; | |
4053 | mips_optimize = 2; | |
0dd2d296 | 4054 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4055 | mips_optimize = hold_mips_optimize; |
4056 | ||
0dd2d296 ILT |
4057 | macro_build ((char *) NULL, &icnt, &expr1, |
4058 | mips_isa < 3 ? "addiu" : "daddiu", | |
4059 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4060 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4061 | mips_isa < 3 ? "addu" : "daddu", | |
4062 | "d,v,t", tempreg, tempreg, AT); | |
4063 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4064 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4065 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4066 | (char *) NULL); |
4067 | used_at = 1; | |
4068 | } | |
670a50eb | 4069 | } |
fb251650 ILT |
4070 | else if (mips_pic == SVR4_PIC) |
4071 | { | |
4072 | int gpdel; | |
4073 | ||
4074 | /* This is the large GOT case. If this is a reference to an | |
4075 | external symbol, and there is no constant, we want | |
4076 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4077 | addu $tempreg,$tempreg,$gp | |
4078 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4079 | For a local symbol, we want | |
4080 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4081 | nop | |
4082 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4083 | ||
4084 | If we have a small constant, and this is a reference to | |
4085 | an external symbol, we want | |
4086 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4087 | addu $tempreg,$tempreg,$gp | |
4088 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4089 | nop | |
4090 | addiu $tempreg,$tempreg,<constant> | |
4091 | For a local symbol, we want | |
4092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4093 | nop | |
4094 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4095 | ||
4096 | If we have a large constant, and this is a reference to | |
4097 | an external symbol, we want | |
4098 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4099 | addu $tempreg,$tempreg,$gp | |
4100 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4101 | lui $at,<hiconstant> | |
4102 | addiu $at,$at,<loconstant> | |
4103 | addu $tempreg,$tempreg,$at | |
4104 | For a local symbol, we want | |
4105 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4106 | lui $at,<hiconstant> | |
4107 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4108 | addu $tempreg,$tempreg,$at | |
4109 | */ | |
4110 | expr1.X_add_number = offset_expr.X_add_number; | |
4111 | offset_expr.X_add_number = 0; | |
4112 | frag_grow (52); | |
4113 | if (reg_needs_delay (GP)) | |
4114 | gpdel = 4; | |
4115 | else | |
4116 | gpdel = 0; | |
4117 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4118 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4119 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4120 | mips_isa < 3 ? "addu" : "daddu", | |
4121 | "d,v,t", tempreg, tempreg, GP); | |
4122 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4123 | dbl ? "ld" : "lw", | |
4124 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4125 | tempreg); | |
4126 | if (expr1.X_add_number == 0) | |
4127 | { | |
4128 | int off; | |
4129 | ||
4130 | if (breg == 0) | |
4131 | off = 0; | |
4132 | else | |
4133 | { | |
4134 | /* We're going to put in an addu instruction using | |
4135 | tempreg, so we may as well insert the nop right | |
4136 | now. */ | |
4137 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4138 | "nop", ""); | |
4139 | off = 4; | |
4140 | } | |
4141 | ||
4142 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4143 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4144 | 8 + gpdel, 0, | |
4145 | (breg == 0 | |
4146 | ? mips_warn_about_macros | |
4147 | : 0)), | |
f59fb6ca | 4148 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4149 | (char *) NULL); |
4150 | } | |
4151 | else if (expr1.X_add_number >= -0x8000 | |
4152 | && expr1.X_add_number < 0x8000) | |
4153 | { | |
4154 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4155 | "nop", ""); | |
4156 | macro_build ((char *) NULL, &icnt, &expr1, | |
4157 | mips_isa < 3 ? "addiu" : "daddiu", | |
4158 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4159 | ||
4160 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4161 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4162 | (breg == 0 | |
4163 | ? mips_warn_about_macros | |
4164 | : 0)), | |
f59fb6ca | 4165 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4166 | (char *) NULL); |
4167 | } | |
4168 | else | |
4169 | { | |
4170 | int adj, dreg; | |
4171 | ||
4172 | /* If we are going to add in a base register, and the | |
4173 | target register and the base register are the same, | |
4174 | then we are using AT as a temporary register. Since | |
4175 | we want to load the constant into AT, we add our | |
4176 | current AT (from the global offset table) and the | |
4177 | register into the register now, and pretend we were | |
4178 | not using a base register. */ | |
4179 | if (breg != treg) | |
4180 | { | |
4181 | adj = 0; | |
4182 | dreg = tempreg; | |
4183 | } | |
4184 | else | |
4185 | { | |
4186 | assert (tempreg == AT); | |
4187 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4188 | "nop", ""); | |
4189 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4190 | mips_isa < 3 ? "addu" : "daddu", | |
4191 | "d,v,t", treg, AT, breg); | |
4192 | dreg = treg; | |
4193 | adj = 8; | |
4194 | } | |
4195 | ||
4196 | /* Set mips_optimize around the lui instruction to avoid | |
4197 | inserting an unnecessary nop after the lw. */ | |
4198 | hold_mips_optimize = mips_optimize; | |
4199 | mips_optimize = 2; | |
4200 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4201 | mips_optimize = hold_mips_optimize; | |
4202 | ||
4203 | macro_build ((char *) NULL, &icnt, &expr1, | |
4204 | mips_isa < 3 ? "addiu" : "daddiu", | |
4205 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4206 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4207 | mips_isa < 3 ? "addu" : "daddu", | |
4208 | "d,v,t", dreg, dreg, AT); | |
4209 | ||
4210 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4211 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4212 | 8 + gpdel, 0, | |
4213 | (breg == 0 | |
4214 | ? mips_warn_about_macros | |
4215 | : 0)), | |
f59fb6ca | 4216 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4217 | (char *) NULL); |
4218 | ||
4219 | used_at = 1; | |
4220 | } | |
4221 | ||
4222 | if (gpdel > 0) | |
4223 | { | |
4224 | /* This is needed because this instruction uses $gp, but | |
4225 | the first instruction on the main stream does not. */ | |
4226 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4227 | p += 4; | |
4228 | } | |
4229 | macro_build (p, &icnt, &offset_expr, | |
4230 | dbl ? "ld" : "lw", | |
4231 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4232 | p += 4; | |
4233 | if (expr1.X_add_number >= -0x8000 | |
4234 | && expr1.X_add_number < 0x8000) | |
4235 | { | |
4236 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4237 | p += 4; | |
4238 | macro_build (p, &icnt, &expr1, | |
4239 | mips_isa < 3 ? "addiu" : "daddiu", | |
4240 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4241 | /* FIXME: If add_number is 0, and there was no base | |
4242 | register, the external symbol case ended with a load, | |
4243 | so if the symbol turns out to not be external, and | |
4244 | the next instruction uses tempreg, an unnecessary nop | |
4245 | will be inserted. */ | |
4246 | } | |
4247 | else | |
4248 | { | |
4249 | if (breg == treg) | |
4250 | { | |
4251 | /* We must add in the base register now, as in the | |
4252 | external symbol case. */ | |
4253 | assert (tempreg == AT); | |
4254 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4255 | p += 4; | |
4256 | macro_build (p, &icnt, (expressionS *) NULL, | |
4257 | mips_isa < 3 ? "addu" : "daddu", | |
4258 | "d,v,t", treg, AT, breg); | |
4259 | p += 4; | |
4260 | tempreg = treg; | |
4261 | /* We set breg to 0 because we have arranged to add | |
4262 | it in in both cases. */ | |
4263 | breg = 0; | |
4264 | } | |
4265 | ||
4266 | macro_build_lui (p, &icnt, &expr1, AT); | |
4267 | p += 4; | |
4268 | macro_build (p, &icnt, &expr1, | |
4269 | mips_isa < 3 ? "addiu" : "daddiu", | |
4270 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4271 | p += 4; | |
4272 | macro_build (p, &icnt, (expressionS *) NULL, | |
4273 | mips_isa < 3 ? "addu" : "daddu", | |
4274 | "d,v,t", tempreg, tempreg, AT); | |
4275 | p += 4; | |
4276 | } | |
4277 | } | |
d9aba805 ILT |
4278 | else if (mips_pic == EMBEDDED_PIC) |
4279 | { | |
4280 | /* We use | |
4281 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4282 | */ | |
4283 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4284 | mips_isa < 3 ? "addiu" : "daddiu", | |
4285 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4286 | } | |
4287 | else | |
4288 | abort (); | |
0dd2d296 | 4289 | |
670a50eb | 4290 | if (breg != 0) |
0dd2d296 ILT |
4291 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4292 | mips_isa < 3 ? "addu" : "daddu", | |
4293 | "d,v,t", treg, tempreg, breg); | |
4294 | ||
4295 | if (! used_at) | |
4296 | return; | |
4297 | ||
4298 | break; | |
4299 | ||
4300 | case M_J_A: | |
4301 | /* The j instruction may not be used in PIC code, since it | |
4302 | requires an absolute address. We convert it to a b | |
4303 | instruction. */ | |
d9aba805 | 4304 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4305 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4306 | else | |
4307 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4308 | return; |
3d3c5039 | 4309 | |
9226253a ILT |
4310 | /* The jal instructions must be handled as macros because when |
4311 | generating PIC code they expand to multi-instruction | |
4312 | sequences. Normally they are simple instructions. */ | |
4313 | case M_JAL_1: | |
4314 | dreg = RA; | |
4315 | /* Fall through. */ | |
4316 | case M_JAL_2: | |
d9aba805 ILT |
4317 | if (mips_pic == NO_PIC |
4318 | || mips_pic == EMBEDDED_PIC) | |
4319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4320 | "d,s", dreg, sreg); | |
4321 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4322 | { |
d9aba805 ILT |
4323 | if (sreg != PIC_CALL_REG) |
4324 | as_warn ("MIPS PIC call to register other than $25"); | |
4325 | ||
0dd2d296 ILT |
4326 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4327 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4328 | if (mips_cprestore_offset < 0) |
4329 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4330 | else | |
4331 | { | |
4332 | expr1.X_add_number = mips_cprestore_offset; | |
4333 | macro_build ((char *) NULL, &icnt, &expr1, | |
4334 | mips_isa < 3 ? "lw" : "ld", | |
4335 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4336 | } | |
9226253a | 4337 | } |
0dd2d296 | 4338 | else |
d9aba805 ILT |
4339 | abort (); |
4340 | ||
9226253a ILT |
4341 | return; |
4342 | ||
4343 | case M_JAL_A: | |
d9aba805 ILT |
4344 | if (mips_pic == NO_PIC) |
4345 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4346 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4347 | { |
fb251650 ILT |
4348 | /* If this is a reference to an external symbol, and we are |
4349 | using a small GOT, we want | |
d9aba805 ILT |
4350 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4351 | nop | |
4352 | jalr $25 | |
4353 | nop | |
4354 | lw $gp,cprestore($sp) | |
4355 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4356 | pseudo-op. If we are using a big GOT, we want |
4357 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4358 | addu $25,$25,$gp | |
4359 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4360 | nop | |
4361 | jalr $25 | |
4362 | nop | |
4363 | lw $gp,cprestore($sp) | |
4364 | If the symbol is not external, we want | |
d9aba805 ILT |
4365 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4366 | nop | |
4367 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4368 | jalr $25 | |
4369 | nop | |
fb251650 ILT |
4370 | lw $gp,cprestore($sp) */ |
4371 | frag_grow (40); | |
4372 | if (! mips_big_got) | |
4373 | { | |
4374 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4375 | mips_isa < 3 ? "lw" : "ld", | |
4376 | "t,o(b)", PIC_CALL_REG, | |
4377 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4378 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4379 | "nop", ""); | |
4380 | p = frag_var (rs_machine_dependent, 4, 0, | |
4381 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4382 | offset_expr.X_add_symbol, (offsetT) 0, |
4383 | (char *) NULL); | |
fb251650 ILT |
4384 | } |
4385 | else | |
4386 | { | |
4387 | int gpdel; | |
4388 | ||
4389 | if (reg_needs_delay (GP)) | |
4390 | gpdel = 4; | |
4391 | else | |
4392 | gpdel = 0; | |
4393 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4394 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4395 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4396 | mips_isa < 3 ? "addu" : "daddu", | |
4397 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4398 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4399 | mips_isa < 3 ? "lw" : "ld", | |
4400 | "t,o(b)", PIC_CALL_REG, | |
4401 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4402 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4403 | "nop", ""); | |
4404 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4405 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4406 | 0, 0), | |
f59fb6ca ILT |
4407 | offset_expr.X_add_symbol, (offsetT) 0, |
4408 | (char *) NULL); | |
fb251650 ILT |
4409 | if (gpdel > 0) |
4410 | { | |
4411 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4412 | p += 4; | |
4413 | } | |
4414 | macro_build (p, &icnt, &offset_expr, | |
4415 | mips_isa < 3 ? "lw" : "ld", | |
4416 | "t,o(b)", PIC_CALL_REG, | |
4417 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4418 | p += 4; | |
4419 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4420 | p += 4; | |
4421 | } | |
d9aba805 ILT |
4422 | macro_build (p, &icnt, &offset_expr, |
4423 | mips_isa < 3 ? "addiu" : "daddiu", | |
4424 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4425 | (int) BFD_RELOC_LO16); | |
4426 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4427 | "jalr", "s", PIC_CALL_REG); | |
4428 | if (mips_cprestore_offset < 0) | |
4429 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4430 | else | |
4431 | { | |
4432 | if (mips_noreorder) | |
4433 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4434 | "nop", ""); | |
4435 | expr1.X_add_number = mips_cprestore_offset; | |
4436 | macro_build ((char *) NULL, &icnt, &expr1, | |
4437 | mips_isa < 3 ? "lw" : "ld", | |
4438 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4439 | mips_frame_reg); | |
4440 | } | |
0dd2d296 | 4441 | } |
d9aba805 | 4442 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4443 | { |
4444 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4445 | /* The linker may expand the call to a longer sequence which | |
4446 | uses $at, so we must break rather than return. */ | |
4447 | break; | |
4448 | } | |
d9aba805 ILT |
4449 | else |
4450 | abort (); | |
4451 | ||
9226253a ILT |
4452 | return; |
4453 | ||
3d3c5039 | 4454 | case M_LB_AB: |
670a50eb ILT |
4455 | s = "lb"; |
4456 | goto ld; | |
3d3c5039 | 4457 | case M_LBU_AB: |
670a50eb ILT |
4458 | s = "lbu"; |
4459 | goto ld; | |
3d3c5039 | 4460 | case M_LH_AB: |
670a50eb ILT |
4461 | s = "lh"; |
4462 | goto ld; | |
3d3c5039 | 4463 | case M_LHU_AB: |
670a50eb ILT |
4464 | s = "lhu"; |
4465 | goto ld; | |
3d3c5039 | 4466 | case M_LW_AB: |
670a50eb ILT |
4467 | s = "lw"; |
4468 | goto ld; | |
3d3c5039 | 4469 | case M_LWC0_AB: |
670a50eb | 4470 | s = "lwc0"; |
efec4a28 | 4471 | /* Itbl support may require additional care here. */ |
8358c818 | 4472 | coproc = 1; |
670a50eb | 4473 | goto ld; |
3d3c5039 | 4474 | case M_LWC1_AB: |
670a50eb | 4475 | s = "lwc1"; |
efec4a28 | 4476 | /* Itbl support may require additional care here. */ |
8358c818 | 4477 | coproc = 1; |
670a50eb | 4478 | goto ld; |
3d3c5039 | 4479 | case M_LWC2_AB: |
670a50eb | 4480 | s = "lwc2"; |
efec4a28 | 4481 | /* Itbl support may require additional care here. */ |
8358c818 | 4482 | coproc = 1; |
670a50eb | 4483 | goto ld; |
3d3c5039 | 4484 | case M_LWC3_AB: |
670a50eb | 4485 | s = "lwc3"; |
efec4a28 | 4486 | /* Itbl support may require additional care here. */ |
8358c818 | 4487 | coproc = 1; |
670a50eb | 4488 | goto ld; |
3d3c5039 | 4489 | case M_LWL_AB: |
670a50eb | 4490 | s = "lwl"; |
b2b8c24e | 4491 | lr = 1; |
670a50eb | 4492 | goto ld; |
3d3c5039 | 4493 | case M_LWR_AB: |
670a50eb | 4494 | s = "lwr"; |
b2b8c24e | 4495 | lr = 1; |
8358c818 ILT |
4496 | goto ld; |
4497 | case M_LDC1_AB: | |
4498 | s = "ldc1"; | |
efec4a28 | 4499 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4500 | coproc = 1; |
4501 | goto ld; | |
4502 | case M_LDC2_AB: | |
4503 | s = "ldc2"; | |
efec4a28 | 4504 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4505 | coproc = 1; |
4506 | goto ld; | |
4507 | case M_LDC3_AB: | |
4508 | s = "ldc3"; | |
efec4a28 | 4509 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4510 | coproc = 1; |
4511 | goto ld; | |
4512 | case M_LDL_AB: | |
4513 | s = "ldl"; | |
b2b8c24e | 4514 | lr = 1; |
8358c818 ILT |
4515 | goto ld; |
4516 | case M_LDR_AB: | |
4517 | s = "ldr"; | |
b2b8c24e | 4518 | lr = 1; |
8358c818 ILT |
4519 | goto ld; |
4520 | case M_LL_AB: | |
4521 | s = "ll"; | |
4522 | goto ld; | |
4523 | case M_LLD_AB: | |
4524 | s = "lld"; | |
4525 | goto ld; | |
4526 | case M_LWU_AB: | |
4527 | s = "lwu"; | |
3d3c5039 | 4528 | ld: |
b2b8c24e | 4529 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4530 | { |
4531 | tempreg = AT; | |
4532 | used_at = 1; | |
4533 | } | |
4534 | else | |
4535 | { | |
4536 | tempreg = treg; | |
4537 | used_at = 0; | |
4538 | } | |
4539 | goto ld_st; | |
3d3c5039 | 4540 | case M_SB_AB: |
670a50eb ILT |
4541 | s = "sb"; |
4542 | goto st; | |
3d3c5039 | 4543 | case M_SH_AB: |
670a50eb ILT |
4544 | s = "sh"; |
4545 | goto st; | |
3d3c5039 | 4546 | case M_SW_AB: |
670a50eb ILT |
4547 | s = "sw"; |
4548 | goto st; | |
3d3c5039 | 4549 | case M_SWC0_AB: |
670a50eb | 4550 | s = "swc0"; |
efec4a28 | 4551 | /* Itbl support may require additional care here. */ |
8358c818 | 4552 | coproc = 1; |
670a50eb | 4553 | goto st; |
3d3c5039 | 4554 | case M_SWC1_AB: |
670a50eb | 4555 | s = "swc1"; |
efec4a28 | 4556 | /* Itbl support may require additional care here. */ |
8358c818 | 4557 | coproc = 1; |
670a50eb | 4558 | goto st; |
3d3c5039 | 4559 | case M_SWC2_AB: |
670a50eb | 4560 | s = "swc2"; |
efec4a28 | 4561 | /* Itbl support may require additional care here. */ |
8358c818 | 4562 | coproc = 1; |
670a50eb | 4563 | goto st; |
3d3c5039 | 4564 | case M_SWC3_AB: |
670a50eb | 4565 | s = "swc3"; |
efec4a28 | 4566 | /* Itbl support may require additional care here. */ |
8358c818 | 4567 | coproc = 1; |
670a50eb | 4568 | goto st; |
3d3c5039 | 4569 | case M_SWL_AB: |
670a50eb ILT |
4570 | s = "swl"; |
4571 | goto st; | |
3d3c5039 | 4572 | case M_SWR_AB: |
670a50eb | 4573 | s = "swr"; |
8358c818 ILT |
4574 | goto st; |
4575 | case M_SC_AB: | |
4576 | s = "sc"; | |
4577 | goto st; | |
4578 | case M_SCD_AB: | |
4579 | s = "scd"; | |
4580 | goto st; | |
4581 | case M_SDC1_AB: | |
4582 | s = "sdc1"; | |
4583 | coproc = 1; | |
efec4a28 | 4584 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4585 | goto st; |
4586 | case M_SDC2_AB: | |
4587 | s = "sdc2"; | |
efec4a28 | 4588 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4589 | coproc = 1; |
4590 | goto st; | |
4591 | case M_SDC3_AB: | |
4592 | s = "sdc3"; | |
efec4a28 | 4593 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4594 | coproc = 1; |
4595 | goto st; | |
4596 | case M_SDL_AB: | |
4597 | s = "sdl"; | |
4598 | goto st; | |
4599 | case M_SDR_AB: | |
4600 | s = "sdr"; | |
3d3c5039 | 4601 | st: |
670a50eb ILT |
4602 | tempreg = AT; |
4603 | used_at = 1; | |
3d3c5039 | 4604 | ld_st: |
efec4a28 | 4605 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4606 | if (mask == M_LWC1_AB |
4607 | || mask == M_SWC1_AB | |
8358c818 | 4608 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4609 | || mask == M_SDC1_AB |
4610 | || mask == M_L_DAB | |
4611 | || mask == M_S_DAB) | |
670a50eb | 4612 | fmt = "T,o(b)"; |
8358c818 | 4613 | else if (coproc) |
19ed8960 | 4614 | fmt = "E,o(b)"; |
670a50eb ILT |
4615 | else |
4616 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4617 | |
4618 | if (offset_expr.X_op != O_constant | |
4619 | && offset_expr.X_op != O_symbol) | |
4620 | { | |
4621 | as_bad ("expression too complex"); | |
4622 | offset_expr.X_op = O_constant; | |
4623 | } | |
4624 | ||
4625 | /* A constant expression in PIC code can be handled just as it | |
4626 | is in non PIC code. */ | |
d9aba805 | 4627 | if (mips_pic == NO_PIC |
0dd2d296 | 4628 | || offset_expr.X_op == O_constant) |
670a50eb | 4629 | { |
0dd2d296 ILT |
4630 | /* If this is a reference to a GP relative symbol, and there |
4631 | is no base register, we want | |
4632 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4633 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4634 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4635 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4636 | If we have a constant, we need two instructions anyhow, | |
4637 | so we always use the latter form. | |
4638 | ||
4639 | If we have a base register, and this is a reference to a | |
4640 | GP relative symbol, we want | |
4641 | addu $tempreg,$breg,$gp | |
4642 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4643 | Otherwise we want | |
4644 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4645 | addu $tempreg,$tempreg,$breg | |
4646 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4647 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4648 | if (breg == 0) |
4649 | { | |
7a15a226 | 4650 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4651 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4652 | p = NULL; |
4653 | else | |
4654 | { | |
8ea7f4e8 | 4655 | frag_grow (20); |
0dd2d296 ILT |
4656 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4657 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4658 | p = frag_var (rs_machine_dependent, 8, 0, | |
4659 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4660 | (mips_warn_about_macros |
4661 | || (used_at && mips_noat))), | |
f59fb6ca | 4662 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4663 | (char *) NULL); |
8197b589 | 4664 | used_at = 0; |
0dd2d296 ILT |
4665 | } |
4666 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4667 | if (p != NULL) | |
4668 | p += 4; | |
4669 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4670 | (int) BFD_RELOC_LO16, tempreg); | |
4671 | } | |
4672 | else | |
4673 | { | |
7a15a226 | 4674 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4675 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4676 | p = NULL; |
4677 | else | |
4678 | { | |
8ea7f4e8 | 4679 | frag_grow (28); |
0dd2d296 ILT |
4680 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4681 | mips_isa < 3 ? "addu" : "daddu", | |
4682 | "d,v,t", tempreg, breg, GP); | |
4683 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4684 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4685 | p = frag_var (rs_machine_dependent, 12, 0, | |
4686 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4687 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4688 | (char *) NULL); |
4689 | } | |
4690 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4691 | if (p != NULL) | |
4692 | p += 4; | |
4693 | macro_build (p, &icnt, (expressionS *) NULL, | |
4694 | mips_isa < 3 ? "addu" : "daddu", | |
4695 | "d,v,t", tempreg, tempreg, breg); | |
4696 | if (p != NULL) | |
4697 | p += 4; | |
4698 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4699 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4700 | } |
670a50eb | 4701 | } |
fb251650 | 4702 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4703 | { |
0dd2d296 ILT |
4704 | /* If this is a reference to an external symbol, we want |
4705 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4706 | nop | |
4707 | <op> $treg,0($tempreg) | |
4708 | Otherwise we want | |
4709 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4710 | nop | |
4711 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4712 | <op> $treg,0($tempreg) | |
4713 | If there is a base register, we add it to $tempreg before | |
4714 | the <op>. If there is a constant, we stick it in the | |
4715 | <op> instruction. We don't handle constants larger than | |
4716 | 16 bits, because we have no way to load the upper 16 bits | |
4717 | (actually, we could handle them for the subset of cases | |
4718 | in which we are not using $at). */ | |
4719 | assert (offset_expr.X_op == O_symbol); | |
4720 | expr1.X_add_number = offset_expr.X_add_number; | |
4721 | offset_expr.X_add_number = 0; | |
4722 | if (expr1.X_add_number < -0x8000 | |
4723 | || expr1.X_add_number >= 0x8000) | |
4724 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4725 | frag_grow (20); |
0dd2d296 ILT |
4726 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4727 | mips_isa < 3 ? "lw" : "ld", | |
4728 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4730 | p = frag_var (rs_machine_dependent, 4, 0, | |
4731 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 4732 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4733 | (char *) NULL); |
4734 | macro_build (p, &icnt, &offset_expr, | |
4735 | mips_isa < 3 ? "addiu" : "daddiu", | |
4736 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4737 | if (breg != 0) |
0dd2d296 | 4738 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4739 | mips_isa < 3 ? "addu" : "daddu", |
4740 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4741 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4742 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4743 | } |
fb251650 ILT |
4744 | else if (mips_pic == SVR4_PIC) |
4745 | { | |
4746 | int gpdel; | |
4747 | ||
4748 | /* If this is a reference to an external symbol, we want | |
4749 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4750 | addu $tempreg,$tempreg,$gp | |
4751 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4752 | <op> $treg,0($tempreg) | |
4753 | Otherwise we want | |
4754 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4755 | nop | |
4756 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4757 | <op> $treg,0($tempreg) | |
4758 | If there is a base register, we add it to $tempreg before | |
4759 | the <op>. If there is a constant, we stick it in the | |
4760 | <op> instruction. We don't handle constants larger than | |
4761 | 16 bits, because we have no way to load the upper 16 bits | |
4762 | (actually, we could handle them for the subset of cases | |
4763 | in which we are not using $at). */ | |
4764 | assert (offset_expr.X_op == O_symbol); | |
4765 | expr1.X_add_number = offset_expr.X_add_number; | |
4766 | offset_expr.X_add_number = 0; | |
4767 | if (expr1.X_add_number < -0x8000 | |
4768 | || expr1.X_add_number >= 0x8000) | |
4769 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4770 | if (reg_needs_delay (GP)) | |
4771 | gpdel = 4; | |
4772 | else | |
4773 | gpdel = 0; | |
4774 | frag_grow (36); | |
4775 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4776 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4778 | mips_isa < 3 ? "addu" : "daddu", | |
4779 | "d,v,t", tempreg, tempreg, GP); | |
4780 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4781 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4782 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4783 | tempreg); | |
fb251650 ILT |
4784 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4785 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 4786 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
4787 | if (gpdel > 0) |
4788 | { | |
4789 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4790 | p += 4; | |
4791 | } | |
4792 | macro_build (p, &icnt, &offset_expr, | |
4793 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4794 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4795 | p += 4; |
4796 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4797 | p += 4; | |
4798 | macro_build (p, &icnt, &offset_expr, | |
4799 | mips_isa < 3 ? "addiu" : "daddiu", | |
4800 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4801 | if (breg != 0) | |
4802 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4803 | mips_isa < 3 ? "addu" : "daddu", | |
4804 | "d,v,t", tempreg, tempreg, breg); | |
4805 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4806 | (int) BFD_RELOC_LO16, tempreg); | |
4807 | } | |
d9aba805 ILT |
4808 | else if (mips_pic == EMBEDDED_PIC) |
4809 | { | |
4810 | /* If there is no base register, we want | |
4811 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4812 | If there is a base register, we want | |
4813 | addu $tempreg,$breg,$gp | |
4814 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4815 | */ | |
4816 | assert (offset_expr.X_op == O_symbol); | |
4817 | if (breg == 0) | |
4818 | { | |
4819 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4820 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4821 | used_at = 0; | |
4822 | } | |
4823 | else | |
4824 | { | |
4825 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4826 | mips_isa < 3 ? "addu" : "daddu", | |
4827 | "d,v,t", tempreg, breg, GP); | |
4828 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4829 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4830 | } | |
4831 | } | |
4832 | else | |
4833 | abort (); | |
0dd2d296 ILT |
4834 | |
4835 | if (! used_at) | |
4836 | return; | |
4837 | ||
4838 | break; | |
3d3c5039 ILT |
4839 | |
4840 | case M_LI: | |
19ed8960 | 4841 | case M_LI_S: |
d8a1c247 KR |
4842 | load_register (&icnt, treg, &imm_expr, 0); |
4843 | return; | |
4844 | ||
4845 | case M_DLI: | |
4846 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4847 | return; |
3d3c5039 | 4848 | |
0dd2d296 | 4849 | case M_LI_SS: |
55933a58 | 4850 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4851 | { |
d8a1c247 | 4852 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4853 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4854 | "mtc1", "t,G", AT, treg); | |
4855 | break; | |
0dd2d296 | 4856 | } |
d9aba805 | 4857 | else |
d2c71068 | 4858 | { |
55933a58 ILT |
4859 | assert (offset_expr.X_op == O_symbol |
4860 | && strcmp (segment_name (S_GET_SEGMENT | |
4861 | (offset_expr.X_add_symbol)), | |
4862 | ".lit4") == 0 | |
4863 | && offset_expr.X_add_number == 0); | |
4864 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4865 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4866 | return; |
4867 | } | |
0dd2d296 | 4868 | |
3d3c5039 | 4869 | case M_LI_D: |
d9aba805 ILT |
4870 | /* We know that sym is in the .rdata section. First we get the |
4871 | upper 16 bits of the address. */ | |
4872 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4873 | { |
4874 | /* FIXME: This won't work for a 64 bit address. */ | |
4875 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4876 | } | |
d9aba805 | 4877 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4878 | { |
4879 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4880 | mips_isa < 3 ? "lw" : "ld", | |
4881 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4882 | } | |
d9aba805 ILT |
4883 | else if (mips_pic == EMBEDDED_PIC) |
4884 | { | |
4885 | /* For embedded PIC we pick up the entire address off $gp in | |
4886 | a single instruction. */ | |
4887 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4888 | mips_isa < 3 ? "addiu" : "daddiu", | |
4889 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4890 | offset_expr.X_op = O_constant; | |
4891 | offset_expr.X_add_number = 0; | |
4892 | } | |
4893 | else | |
4894 | abort (); | |
4895 | ||
0dd2d296 | 4896 | /* Now we load the register(s). */ |
8358c818 | 4897 | if (mips_isa >= 3) |
0dd2d296 ILT |
4898 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4899 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4900 | else |
4901 | { | |
0dd2d296 ILT |
4902 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4903 | treg, (int) BFD_RELOC_LO16, AT); | |
4904 | if (treg != 31) | |
4905 | { | |
4906 | /* FIXME: How in the world do we deal with the possible | |
4907 | overflow here? */ | |
4908 | offset_expr.X_add_number += 4; | |
4909 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4910 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4911 | } | |
8358c818 | 4912 | } |
d2c71068 ILT |
4913 | |
4914 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4915 | does not become a variant frag. */ | |
4916 | frag_wane (frag_now); | |
4917 | frag_new (0); | |
4918 | ||
670a50eb | 4919 | break; |
3d3c5039 ILT |
4920 | |
4921 | case M_LI_DD: | |
55933a58 ILT |
4922 | assert (offset_expr.X_op == O_symbol |
4923 | && offset_expr.X_add_number == 0); | |
4924 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4925 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4926 | { |
0dd2d296 ILT |
4927 | if (mips_isa >= 2) |
4928 | { | |
4929 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4930 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4931 | return; | |
4932 | } | |
4933 | breg = GP; | |
4934 | r = BFD_RELOC_MIPS_LITERAL; | |
4935 | goto dob; | |
4936 | } | |
55933a58 | 4937 | else |
0dd2d296 | 4938 | { |
55933a58 ILT |
4939 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4940 | if (mips_pic == SVR4_PIC) | |
4941 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4942 | mips_isa < 3 ? "lw" : "ld", | |
4943 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4944 | else | |
4945 | { | |
4946 | /* FIXME: This won't work for a 64 bit address. */ | |
4947 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4948 | } | |
4949 | ||
0dd2d296 ILT |
4950 | if (mips_isa >= 2) |
4951 | { | |
4952 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4953 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4954 | |
4955 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4956 | that this does not become a variant frag. */ | |
4957 | frag_wane (frag_now); | |
4958 | frag_new (0); | |
4959 | ||
0dd2d296 ILT |
4960 | break; |
4961 | } | |
4962 | breg = AT; | |
4963 | r = BFD_RELOC_LO16; | |
4964 | goto dob; | |
8358c818 | 4965 | } |
9226253a | 4966 | |
3d3c5039 | 4967 | case M_L_DOB: |
9a7d824a ILT |
4968 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4969 | to adjust when loading from memory. */ | |
9226253a ILT |
4970 | r = BFD_RELOC_LO16; |
4971 | dob: | |
8358c818 | 4972 | assert (mips_isa < 2); |
0dd2d296 | 4973 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4974 | target_big_endian ? treg + 1 : treg, |
9226253a | 4975 | (int) r, breg); |
0dd2d296 ILT |
4976 | /* FIXME: A possible overflow which I don't know how to deal |
4977 | with. */ | |
670a50eb | 4978 | offset_expr.X_add_number += 4; |
0dd2d296 | 4979 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4980 | target_big_endian ? treg : treg + 1, |
9226253a | 4981 | (int) r, breg); |
d2c71068 ILT |
4982 | |
4983 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4984 | does not become a variant frag. */ | |
4985 | frag_wane (frag_now); | |
4986 | frag_new (0); | |
4987 | ||
0dd2d296 ILT |
4988 | if (breg != AT) |
4989 | return; | |
4990 | break; | |
3d3c5039 ILT |
4991 | |
4992 | case M_L_DAB: | |
670a50eb ILT |
4993 | /* |
4994 | * The MIPS assembler seems to check for X_add_number not | |
4995 | * being double aligned and generating: | |
4996 | * lui at,%hi(foo+1) | |
4997 | * addu at,at,v1 | |
4998 | * addiu at,at,%lo(foo+1) | |
4999 | * lwc1 f2,0(at) | |
5000 | * lwc1 f3,4(at) | |
5001 | * But, the resulting address is the same after relocation so why | |
5002 | * generate the extra instruction? | |
5003 | */ | |
efec4a28 | 5004 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5005 | coproc = 1; |
0dd2d296 | 5006 | if (mips_isa >= 2) |
670a50eb | 5007 | { |
0dd2d296 ILT |
5008 | s = "ldc1"; |
5009 | goto ld; | |
670a50eb | 5010 | } |
0dd2d296 ILT |
5011 | |
5012 | s = "lwc1"; | |
5013 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5014 | goto ldd_std; |
5015 | ||
5016 | case M_S_DAB: | |
8358c818 | 5017 | if (mips_isa >= 2) |
8358c818 | 5018 | { |
0dd2d296 ILT |
5019 | s = "sdc1"; |
5020 | goto st; | |
8358c818 | 5021 | } |
3d3c5039 | 5022 | |
0dd2d296 ILT |
5023 | s = "swc1"; |
5024 | fmt = "T,o(b)"; | |
efec4a28 | 5025 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5026 | coproc = 1; |
5027 | goto ldd_std; | |
3d3c5039 ILT |
5028 | |
5029 | case M_LD_AB: | |
0dd2d296 | 5030 | if (mips_isa >= 3) |
670a50eb | 5031 | { |
0dd2d296 ILT |
5032 | s = "ld"; |
5033 | goto ld; | |
670a50eb | 5034 | } |
0dd2d296 ILT |
5035 | |
5036 | s = "lw"; | |
5037 | fmt = "t,o(b)"; | |
5038 | goto ldd_std; | |
5039 | ||
5040 | case M_SD_AB: | |
5041 | if (mips_isa >= 3) | |
670a50eb | 5042 | { |
0dd2d296 ILT |
5043 | s = "sd"; |
5044 | goto st; | |
670a50eb | 5045 | } |
0dd2d296 | 5046 | |
670a50eb | 5047 | s = "sw"; |
0dd2d296 ILT |
5048 | fmt = "t,o(b)"; |
5049 | ||
5050 | ldd_std: | |
5051 | if (offset_expr.X_op != O_symbol | |
5052 | && offset_expr.X_op != O_constant) | |
670a50eb | 5053 | { |
0dd2d296 ILT |
5054 | as_bad ("expression too complex"); |
5055 | offset_expr.X_op = O_constant; | |
5056 | } | |
5057 | ||
5058 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5059 | to adjust when loading from memory. We set coproc if we must | |
5060 | load $fn+1 first. */ | |
efec4a28 | 5061 | /* Itbl support may require additional care here. */ |
b9129c6f | 5062 | if (! target_big_endian) |
0dd2d296 ILT |
5063 | coproc = 0; |
5064 | ||
d9aba805 | 5065 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5066 | || offset_expr.X_op == O_constant) |
5067 | { | |
5068 | /* If this is a reference to a GP relative symbol, we want | |
5069 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5070 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5071 | If we have a base register, we use this | |
5072 | addu $at,$breg,$gp | |
5073 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5074 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5075 | If this is not a GP relative symbol, we want | |
5076 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5077 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5078 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5079 | If there is a base register, we add it to $at after the | |
5080 | lui instruction. If there is a constant, we always use | |
5081 | the last case. */ | |
7a15a226 | 5082 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 5083 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 5084 | { |
0dd2d296 ILT |
5085 | p = NULL; |
5086 | used_at = 1; | |
670a50eb ILT |
5087 | } |
5088 | else | |
0dd2d296 ILT |
5089 | { |
5090 | int off; | |
5091 | ||
5092 | if (breg == 0) | |
5093 | { | |
8ea7f4e8 | 5094 | frag_grow (28); |
0dd2d296 ILT |
5095 | tempreg = GP; |
5096 | off = 0; | |
5097 | used_at = 0; | |
5098 | } | |
5099 | else | |
5100 | { | |
8ea7f4e8 | 5101 | frag_grow (36); |
0dd2d296 ILT |
5102 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5103 | mips_isa < 3 ? "addu" : "daddu", | |
5104 | "d,v,t", AT, breg, GP); | |
5105 | tempreg = AT; | |
5106 | off = 4; | |
5107 | used_at = 1; | |
5108 | } | |
5109 | ||
efec4a28 | 5110 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5111 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5112 | coproc ? treg + 1 : treg, | |
5113 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5114 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5115 | |
5116 | /* Set mips_optimize to 2 to avoid inserting an | |
5117 | undesired nop. */ | |
5118 | hold_mips_optimize = mips_optimize; | |
5119 | mips_optimize = 2; | |
efec4a28 | 5120 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5121 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5122 | coproc ? treg : treg + 1, | |
5123 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5124 | mips_optimize = hold_mips_optimize; |
5125 | ||
0dd2d296 ILT |
5126 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5127 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 5128 | used_at && mips_noat), |
f59fb6ca | 5129 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5130 | (char *) NULL); |
777ad64d ILT |
5131 | |
5132 | /* We just generated two relocs. When tc_gen_reloc | |
5133 | handles this case, it will skip the first reloc and | |
5134 | handle the second. The second reloc already has an | |
5135 | extra addend of 4, which we added above. We must | |
5136 | subtract it out, and then subtract another 4 to make | |
5137 | the first reloc come out right. The second reloc | |
5138 | will come out right because we are going to add 4 to | |
5139 | offset_expr when we build its instruction below. */ | |
5140 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
5141 | offset_expr.X_op = O_constant; |
5142 | } | |
5143 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5144 | if (p != NULL) | |
5145 | p += 4; | |
5146 | if (breg != 0) | |
5147 | { | |
5148 | macro_build (p, &icnt, (expressionS *) NULL, | |
5149 | mips_isa < 3 ? "addu" : "daddu", | |
5150 | "d,v,t", AT, breg, AT); | |
5151 | if (p != NULL) | |
5152 | p += 4; | |
5153 | } | |
efec4a28 | 5154 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5155 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5156 | coproc ? treg + 1 : treg, | |
5157 | (int) BFD_RELOC_LO16, AT); | |
5158 | if (p != NULL) | |
5159 | p += 4; | |
5160 | /* FIXME: How do we handle overflow here? */ | |
5161 | offset_expr.X_add_number += 4; | |
efec4a28 | 5162 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5163 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5164 | coproc ? treg : treg + 1, | |
5165 | (int) BFD_RELOC_LO16, AT); | |
5166 | } | |
fb251650 | 5167 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5168 | { |
0dd2d296 ILT |
5169 | int off; |
5170 | ||
5171 | /* If this is a reference to an external symbol, we want | |
5172 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5173 | nop | |
5174 | <op> $treg,0($at) | |
5175 | <op> $treg+1,4($at) | |
5176 | Otherwise we want | |
5177 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5178 | nop | |
5179 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5180 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5181 | If there is a base register we add it to $at before the | |
5182 | lwc1 instructions. If there is a constant we include it | |
5183 | in the lwc1 instructions. */ | |
5184 | used_at = 1; | |
5185 | expr1.X_add_number = offset_expr.X_add_number; | |
5186 | offset_expr.X_add_number = 0; | |
5187 | if (expr1.X_add_number < -0x8000 | |
5188 | || expr1.X_add_number >= 0x8000 - 4) | |
5189 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5190 | if (breg == 0) | |
5191 | off = 0; | |
5192 | else | |
5193 | off = 4; | |
8ea7f4e8 | 5194 | frag_grow (24 + off); |
0dd2d296 ILT |
5195 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5196 | mips_isa < 3 ? "lw" : "ld", | |
5197 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5198 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5199 | if (breg != 0) |
0dd2d296 | 5200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 5201 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5202 | "d,v,t", AT, breg, AT); |
efec4a28 | 5203 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5204 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5205 | coproc ? treg + 1 : treg, | |
5206 | (int) BFD_RELOC_LO16, AT); | |
5207 | expr1.X_add_number += 4; | |
55933a58 ILT |
5208 | |
5209 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5210 | nop. */ | |
5211 | hold_mips_optimize = mips_optimize; | |
5212 | mips_optimize = 2; | |
efec4a28 | 5213 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5214 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5215 | coproc ? treg : treg + 1, | |
5216 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5217 | mips_optimize = hold_mips_optimize; |
5218 | ||
0dd2d296 ILT |
5219 | (void) frag_var (rs_machine_dependent, 0, 0, |
5220 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5221 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5222 | (char *) NULL); |
8358c818 | 5223 | } |
fb251650 ILT |
5224 | else if (mips_pic == SVR4_PIC) |
5225 | { | |
5226 | int gpdel, off; | |
5227 | ||
5228 | /* If this is a reference to an external symbol, we want | |
5229 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5230 | addu $at,$at,$gp | |
5231 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5232 | nop | |
5233 | <op> $treg,0($at) | |
5234 | <op> $treg+1,4($at) | |
5235 | Otherwise we want | |
5236 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5237 | nop | |
5238 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5239 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5240 | If there is a base register we add it to $at before the | |
5241 | lwc1 instructions. If there is a constant we include it | |
5242 | in the lwc1 instructions. */ | |
5243 | used_at = 1; | |
5244 | expr1.X_add_number = offset_expr.X_add_number; | |
5245 | offset_expr.X_add_number = 0; | |
5246 | if (expr1.X_add_number < -0x8000 | |
5247 | || expr1.X_add_number >= 0x8000 - 4) | |
5248 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5249 | if (reg_needs_delay (GP)) | |
5250 | gpdel = 4; | |
5251 | else | |
5252 | gpdel = 0; | |
5253 | if (breg == 0) | |
5254 | off = 0; | |
5255 | else | |
5256 | off = 4; | |
5257 | frag_grow (56); | |
5258 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5259 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5260 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5261 | mips_isa < 3 ? "addu" : "daddu", | |
5262 | "d,v,t", AT, AT, GP); | |
5263 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5264 | mips_isa < 3 ? "lw" : "ld", | |
5265 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5266 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5267 | if (breg != 0) | |
5268 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5269 | mips_isa < 3 ? "addu" : "daddu", | |
5270 | "d,v,t", AT, breg, AT); | |
efec4a28 | 5271 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5272 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5273 | coproc ? treg + 1 : treg, | |
5274 | (int) BFD_RELOC_LO16, AT); | |
5275 | expr1.X_add_number += 4; | |
5276 | ||
5277 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5278 | nop. */ | |
5279 | hold_mips_optimize = mips_optimize; | |
5280 | mips_optimize = 2; | |
efec4a28 | 5281 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5282 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5283 | coproc ? treg : treg + 1, | |
5284 | (int) BFD_RELOC_LO16, AT); | |
5285 | mips_optimize = hold_mips_optimize; | |
5286 | expr1.X_add_number -= 4; | |
5287 | ||
5288 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5289 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5290 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5291 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5292 | (char *) NULL); |
5293 | if (gpdel > 0) | |
5294 | { | |
5295 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5296 | p += 4; | |
5297 | } | |
5298 | macro_build (p, &icnt, &offset_expr, | |
5299 | mips_isa < 3 ? "lw" : "ld", | |
5300 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5301 | p += 4; | |
5302 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5303 | p += 4; | |
5304 | if (breg != 0) | |
5305 | { | |
5306 | macro_build (p, &icnt, (expressionS *) NULL, | |
5307 | mips_isa < 3 ? "addu" : "daddu", | |
5308 | "d,v,t", AT, breg, AT); | |
5309 | p += 4; | |
5310 | } | |
efec4a28 | 5311 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5312 | macro_build (p, &icnt, &expr1, s, fmt, |
5313 | coproc ? treg + 1 : treg, | |
5314 | (int) BFD_RELOC_LO16, AT); | |
5315 | p += 4; | |
5316 | expr1.X_add_number += 4; | |
5317 | ||
5318 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5319 | nop. */ | |
5320 | hold_mips_optimize = mips_optimize; | |
5321 | mips_optimize = 2; | |
efec4a28 | 5322 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5323 | macro_build (p, &icnt, &expr1, s, fmt, |
5324 | coproc ? treg : treg + 1, | |
5325 | (int) BFD_RELOC_LO16, AT); | |
5326 | mips_optimize = hold_mips_optimize; | |
5327 | } | |
d9aba805 ILT |
5328 | else if (mips_pic == EMBEDDED_PIC) |
5329 | { | |
5330 | /* If there is no base register, we use | |
5331 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5332 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5333 | If we have a base register, we use | |
5334 | addu $at,$breg,$gp | |
5335 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5336 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5337 | */ | |
5338 | if (breg == 0) | |
5339 | { | |
5340 | tempreg = GP; | |
5341 | used_at = 0; | |
5342 | } | |
5343 | else | |
5344 | { | |
5345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5346 | mips_isa < 3 ? "addu" : "daddu", | |
5347 | "d,v,t", AT, breg, GP); | |
5348 | tempreg = AT; | |
5349 | used_at = 1; | |
5350 | } | |
5351 | ||
efec4a28 | 5352 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5353 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5354 | coproc ? treg + 1 : treg, | |
5355 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5356 | offset_expr.X_add_number += 4; | |
efec4a28 | 5357 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5358 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5359 | coproc ? treg : treg + 1, | |
5360 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5361 | } | |
5362 | else | |
5363 | abort (); | |
0dd2d296 ILT |
5364 | |
5365 | if (! used_at) | |
5366 | return; | |
5367 | ||
5368 | break; | |
5369 | ||
5370 | case M_LD_OB: | |
5371 | s = "lw"; | |
5372 | goto sd_ob; | |
5373 | case M_SD_OB: | |
5374 | s = "sw"; | |
5375 | sd_ob: | |
5376 | assert (mips_isa < 3); | |
5377 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5378 | (int) BFD_RELOC_LO16, breg); | |
5379 | offset_expr.X_add_number += 4; | |
5380 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5381 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5382 | return; |
efec4a28 DP |
5383 | |
5384 | /* New code added to support COPZ instructions. | |
5385 | This code builds table entries out of the macros in mip_opcodes. | |
5386 | R4000 uses interlocks to handle coproc delays. | |
5387 | Other chips (like the R3000) require nops to be inserted for delays. | |
5388 | ||
5389 | FIXME: Currently, we require that the user handle delays. | |
5390 | In order to fill delay slots for non-interlocked chips, | |
5391 | we must have a way to specify delays based on the coprocessor. | |
5392 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5393 | What are the side-effects of the cop instruction? | |
5394 | What cache support might we have and what are its effects? | |
5395 | Both coprocessor & memory require delays. how long??? | |
5396 | What registers are read/set/modified? | |
5397 | ||
5398 | If an itbl is provided to interpret cop instructions, | |
5399 | this knowledge can be encoded in the itbl spec. */ | |
5400 | ||
5401 | case M_COP0: | |
5402 | s = "cop0"; | |
5403 | goto copz; | |
5404 | case M_COP1: | |
5405 | s = "cop1"; | |
5406 | goto copz; | |
5407 | case M_COP2: | |
5408 | s = "cop2"; | |
5409 | goto copz; | |
5410 | case M_COP3: | |
5411 | s = "cop3"; | |
5412 | copz: | |
5413 | /* For now we just do C (same as Cz). */ | |
9218cee0 | 5414 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); |
efec4a28 DP |
5415 | return; |
5416 | ||
917fae09 SS |
5417 | #ifdef LOSING_COMPILER |
5418 | default: | |
efec4a28 DP |
5419 | /* Try and see if this is a new itbl instruction. |
5420 | This code builds table entries out of the macros in mip_opcodes. | |
5421 | FIXME: For now we just assemble the expression and pass it's | |
5422 | value along as a 32-bit immediate. | |
5423 | We may want to have the assembler assemble this value, | |
5424 | so that we gain the assembler's knowledge of delay slots, | |
5425 | symbols, etc. | |
5426 | Would it be more efficient to use mask (id) here? */ | |
5427 | if (itbl_have_entries | |
9218cee0 | 5428 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5429 | { |
5430 | s = ip->insn_mo->name; | |
5431 | s2 = "cop3"; | |
9218cee0 | 5432 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5433 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5434 | return; | |
5435 | } | |
917fae09 SS |
5436 | macro2 (ip); |
5437 | return; | |
5438 | } | |
5439 | if (mips_noat) | |
5440 | as_warn ("Macro used $at after \".set noat\""); | |
5441 | } | |
5442 | ||
5443 | static void | |
5444 | macro2 (ip) | |
5445 | struct mips_cl_insn *ip; | |
5446 | { | |
5447 | register int treg, sreg, dreg, breg; | |
5448 | int tempreg; | |
5449 | int mask; | |
5450 | int icnt = 0; | |
5451 | int used_at; | |
5452 | expressionS expr1; | |
5453 | const char *s; | |
5454 | const char *s2; | |
5455 | const char *fmt; | |
5456 | int likely = 0; | |
5457 | int dbl = 0; | |
5458 | int coproc = 0; | |
adcf2b9d ILT |
5459 | int lr = 0; |
5460 | int off; | |
917fae09 SS |
5461 | offsetT maxnum; |
5462 | bfd_reloc_code_real_type r; | |
5463 | char *p; | |
5464 | ||
5465 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5466 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5467 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5468 | mask = ip->insn_mo->mask; | |
5469 | ||
5470 | expr1.X_op = O_constant; | |
5471 | expr1.X_op_symbol = NULL; | |
5472 | expr1.X_add_symbol = NULL; | |
5473 | expr1.X_add_number = 1; | |
5474 | ||
5475 | switch (mask) | |
5476 | { | |
5477 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5478 | |
8358c818 ILT |
5479 | case M_DMUL: |
5480 | dbl = 1; | |
3d3c5039 | 5481 | case M_MUL: |
0dd2d296 | 5482 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5483 | dbl ? "dmultu" : "multu", |
5484 | "s,t", sreg, treg); | |
0dd2d296 | 5485 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5486 | return; |
3d3c5039 | 5487 | |
8358c818 ILT |
5488 | case M_DMUL_I: |
5489 | dbl = 1; | |
3d3c5039 | 5490 | case M_MUL_I: |
8358c818 ILT |
5491 | /* The MIPS assembler some times generates shifts and adds. I'm |
5492 | not trying to be that fancy. GCC should do this for us | |
5493 | anyway. */ | |
d8a1c247 | 5494 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5495 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5496 | dbl ? "dmult" : "mult", |
5497 | "s,t", sreg, AT); | |
0dd2d296 | 5498 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5499 | break; |
3d3c5039 | 5500 | |
8358c818 ILT |
5501 | case M_DMULO: |
5502 | dbl = 1; | |
5503 | case M_MULO: | |
fbcfacb7 | 5504 | mips_emit_delays (true); |
8358c818 | 5505 | ++mips_noreorder; |
0dd2d296 ILT |
5506 | mips_any_noreorder = 1; |
5507 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5508 | dbl ? "dmult" : "mult", |
5509 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5510 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5511 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5512 | dbl ? "dsra32" : "sra", |
5513 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5514 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5515 | if (mips_trap) |
5516 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5517 | else | |
5518 | { | |
5519 | expr1.X_add_number = 8; | |
5520 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5521 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5522 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5523 | } | |
8358c818 | 5524 | --mips_noreorder; |
0dd2d296 | 5525 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5526 | break; |
5527 | ||
5528 | case M_DMULOU: | |
5529 | dbl = 1; | |
5530 | case M_MULOU: | |
fbcfacb7 | 5531 | mips_emit_delays (true); |
8358c818 | 5532 | ++mips_noreorder; |
0dd2d296 ILT |
5533 | mips_any_noreorder = 1; |
5534 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5535 | dbl ? "dmultu" : "multu", |
5536 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5537 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5538 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5539 | if (mips_trap) |
5540 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5541 | else | |
5542 | { | |
5543 | expr1.X_add_number = 8; | |
5544 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5545 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5546 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5547 | } | |
8358c818 ILT |
5548 | --mips_noreorder; |
5549 | break; | |
5550 | ||
3d3c5039 | 5551 | case M_ROL: |
0dd2d296 ILT |
5552 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5553 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5554 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5555 | treg); | |
5556 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5557 | break; |
3d3c5039 ILT |
5558 | |
5559 | case M_ROL_I: | |
0dd2d296 | 5560 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5561 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5562 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5563 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5564 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5565 | break; |
3d3c5039 ILT |
5566 | |
5567 | case M_ROR: | |
0dd2d296 ILT |
5568 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5569 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5570 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5571 | treg); | |
5572 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5573 | break; |
3d3c5039 ILT |
5574 | |
5575 | case M_ROR_I: | |
0dd2d296 | 5576 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5577 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5578 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5579 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5580 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5581 | break; |
3d3c5039 ILT |
5582 | |
5583 | case M_S_DOB: | |
8358c818 | 5584 | assert (mips_isa < 2); |
9a7d824a ILT |
5585 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5586 | to adjust when storing to memory. */ | |
0dd2d296 | 5587 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5588 | target_big_endian ? treg + 1 : treg, |
9226253a | 5589 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5590 | offset_expr.X_add_number += 4; |
0dd2d296 | 5591 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5592 | target_big_endian ? treg : treg + 1, |
9226253a | 5593 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5594 | return; |
3d3c5039 | 5595 | |
3d3c5039 | 5596 | case M_SEQ: |
670a50eb | 5597 | if (sreg == 0) |
0dd2d296 ILT |
5598 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5599 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5600 | else if (treg == 0) |
0dd2d296 ILT |
5601 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5602 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5603 | else |
5604 | { | |
0dd2d296 ILT |
5605 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5606 | sreg, treg); | |
5607 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5608 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5609 | } |
670a50eb | 5610 | return; |
3d3c5039 ILT |
5611 | |
5612 | case M_SEQ_I: | |
670a50eb ILT |
5613 | if (imm_expr.X_add_number == 0) |
5614 | { | |
0dd2d296 ILT |
5615 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5616 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5617 | return; |
3d3c5039 | 5618 | } |
670a50eb ILT |
5619 | if (sreg == 0) |
5620 | { | |
9a7d824a | 5621 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5622 | ip->insn_mo->name); |
0dd2d296 | 5623 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5624 | return; |
3d3c5039 | 5625 | } |
6e8dda9c | 5626 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5627 | { |
0dd2d296 ILT |
5628 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5629 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5630 | used_at = 0; |
6e8dda9c ILT |
5631 | } |
5632 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5633 | { | |
5634 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5635 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5636 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5637 | "t,r,j", dreg, sreg, |
5638 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5639 | used_at = 0; |
5640 | } | |
5641 | else | |
5642 | { | |
d8a1c247 | 5643 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5644 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5645 | sreg, AT); | |
670a50eb ILT |
5646 | used_at = 1; |
5647 | } | |
0dd2d296 | 5648 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5649 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5650 | if (used_at) |
5651 | break; | |
5652 | return; | |
3d3c5039 ILT |
5653 | |
5654 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5655 | s = "slt"; |
5656 | goto sge; | |
3d3c5039 | 5657 | case M_SGEU: |
670a50eb | 5658 | s = "sltu"; |
3d3c5039 | 5659 | sge: |
0dd2d296 ILT |
5660 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5661 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5662 | (int) BFD_RELOC_LO16); |
670a50eb | 5663 | return; |
3d3c5039 | 5664 | |
670a50eb | 5665 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5666 | case M_SGEU_I: |
6e8dda9c | 5667 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5668 | { |
0dd2d296 | 5669 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5670 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5671 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5672 | used_at = 0; |
5673 | } | |
5674 | else | |
5675 | { | |
d8a1c247 | 5676 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5677 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5678 | mask == M_SGE_I ? "slt" : "sltu", |
5679 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5680 | used_at = 1; |
5681 | } | |
0dd2d296 | 5682 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5683 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5684 | if (used_at) |
5685 | break; | |
5686 | return; | |
3d3c5039 ILT |
5687 | |
5688 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5689 | s = "slt"; |
5690 | goto sgt; | |
3d3c5039 | 5691 | case M_SGTU: |
670a50eb | 5692 | s = "sltu"; |
3d3c5039 | 5693 | sgt: |
0dd2d296 | 5694 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5695 | return; |
3d3c5039 | 5696 | |
670a50eb ILT |
5697 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5698 | s = "slt"; | |
5699 | goto sgti; | |
3d3c5039 | 5700 | case M_SGTU_I: |
670a50eb | 5701 | s = "sltu"; |
3d3c5039 | 5702 | sgti: |
d8a1c247 | 5703 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5704 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5705 | break; |
3d3c5039 | 5706 | |
670a50eb ILT |
5707 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5708 | s = "slt"; | |
5709 | goto sle; | |
3d3c5039 | 5710 | case M_SLEU: |
670a50eb | 5711 | s = "sltu"; |
3d3c5039 | 5712 | sle: |
0dd2d296 ILT |
5713 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5714 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5715 | (int) BFD_RELOC_LO16); |
670a50eb | 5716 | return; |
3d3c5039 | 5717 | |
670a50eb ILT |
5718 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5719 | s = "slt"; | |
5720 | goto slei; | |
3d3c5039 | 5721 | case M_SLEU_I: |
670a50eb | 5722 | s = "sltu"; |
3d3c5039 | 5723 | slei: |
d8a1c247 | 5724 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5725 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5726 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5727 | (int) BFD_RELOC_LO16); |
670a50eb | 5728 | break; |
3d3c5039 ILT |
5729 | |
5730 | case M_SLT_I: | |
6e8dda9c | 5731 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5732 | { |
0dd2d296 ILT |
5733 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5734 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5735 | return; |
3d3c5039 | 5736 | } |
d8a1c247 | 5737 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5738 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5739 | break; |
3d3c5039 ILT |
5740 | |
5741 | case M_SLTU_I: | |
6e8dda9c | 5742 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5743 | { |
0dd2d296 ILT |
5744 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5745 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5746 | return; |
3d3c5039 | 5747 | } |
d8a1c247 | 5748 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5749 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5750 | AT); | |
670a50eb | 5751 | break; |
3d3c5039 ILT |
5752 | |
5753 | case M_SNE: | |
670a50eb | 5754 | if (sreg == 0) |
0dd2d296 ILT |
5755 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5756 | treg); | |
670a50eb | 5757 | else if (treg == 0) |
0dd2d296 ILT |
5758 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5759 | sreg); | |
670a50eb ILT |
5760 | else |
5761 | { | |
0dd2d296 ILT |
5762 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5763 | sreg, treg); | |
5764 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5765 | dreg); | |
3d3c5039 | 5766 | } |
670a50eb | 5767 | return; |
3d3c5039 ILT |
5768 | |
5769 | case M_SNE_I: | |
670a50eb ILT |
5770 | if (imm_expr.X_add_number == 0) |
5771 | { | |
0dd2d296 ILT |
5772 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5773 | sreg); | |
670a50eb | 5774 | return; |
3d3c5039 | 5775 | } |
670a50eb ILT |
5776 | if (sreg == 0) |
5777 | { | |
9a7d824a | 5778 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5779 | ip->insn_mo->name); |
0dd2d296 | 5780 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5781 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5782 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5783 | return; |
3d3c5039 | 5784 | } |
6e8dda9c | 5785 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5786 | { |
0dd2d296 ILT |
5787 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5788 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5789 | used_at = 0; |
6e8dda9c ILT |
5790 | } |
5791 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5792 | { | |
5793 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5794 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5795 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5796 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5797 | used_at = 0; |
5798 | } | |
5799 | else | |
5800 | { | |
d8a1c247 | 5801 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5802 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5803 | sreg, AT); | |
670a50eb ILT |
5804 | used_at = 1; |
5805 | } | |
0dd2d296 | 5806 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5807 | if (used_at) |
5808 | break; | |
5809 | return; | |
3d3c5039 | 5810 | |
8358c818 ILT |
5811 | case M_DSUB_I: |
5812 | dbl = 1; | |
3d3c5039 | 5813 | case M_SUB_I: |
6e8dda9c | 5814 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5815 | { |
5816 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5817 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5818 | dbl ? "daddi" : "addi", |
9226253a | 5819 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5820 | return; |
3d3c5039 | 5821 | } |
d8a1c247 | 5822 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5823 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5824 | dbl ? "dsub" : "sub", |
5825 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5826 | break; |
3d3c5039 | 5827 | |
8358c818 ILT |
5828 | case M_DSUBU_I: |
5829 | dbl = 1; | |
3d3c5039 | 5830 | case M_SUBU_I: |
6e8dda9c | 5831 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5832 | { |
5833 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5834 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5835 | dbl ? "daddiu" : "addiu", |
9226253a | 5836 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5837 | return; |
3d3c5039 | 5838 | } |
d8a1c247 | 5839 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5840 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5841 | dbl ? "dsubu" : "subu", |
5842 | "d,v,t", dreg, sreg, AT); | |
5843 | break; | |
5844 | ||
5845 | case M_TEQ_I: | |
5846 | s = "teq"; | |
5847 | goto trap; | |
5848 | case M_TGE_I: | |
5849 | s = "tge"; | |
5850 | goto trap; | |
5851 | case M_TGEU_I: | |
5852 | s = "tgeu"; | |
5853 | goto trap; | |
5854 | case M_TLT_I: | |
5855 | s = "tlt"; | |
5856 | goto trap; | |
5857 | case M_TLTU_I: | |
5858 | s = "tltu"; | |
5859 | goto trap; | |
5860 | case M_TNE_I: | |
5861 | s = "tne"; | |
5862 | trap: | |
d8a1c247 | 5863 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5864 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5865 | break; |
3d3c5039 ILT |
5866 | |
5867 | case M_TRUNCWD: | |
5868 | case M_TRUNCWS: | |
8358c818 | 5869 | assert (mips_isa < 2); |
670a50eb ILT |
5870 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5871 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5872 | ||
5873 | /* | |
5874 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5875 | * or is there a reason for it? | |
5876 | */ | |
fbcfacb7 | 5877 | mips_emit_delays (true); |
becfe05e | 5878 | ++mips_noreorder; |
0dd2d296 ILT |
5879 | mips_any_noreorder = 1; |
5880 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5881 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5882 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5883 | expr1.X_add_number = 3; |
0dd2d296 | 5884 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5885 | (int) BFD_RELOC_LO16); |
670a50eb | 5886 | expr1.X_add_number = 2; |
0dd2d296 | 5887 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5888 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5889 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5890 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5891 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5892 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5893 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5894 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5895 | --mips_noreorder; |
670a50eb | 5896 | break; |
3d3c5039 ILT |
5897 | |
5898 | case M_ULH: | |
670a50eb ILT |
5899 | s = "lb"; |
5900 | goto ulh; | |
3d3c5039 | 5901 | case M_ULHU: |
670a50eb | 5902 | s = "lbu"; |
3d3c5039 | 5903 | ulh: |
8ea7f4e8 ILT |
5904 | if (offset_expr.X_add_number >= 0x7fff) |
5905 | as_bad ("operand overflow"); | |
670a50eb | 5906 | /* avoid load delay */ |
b9129c6f | 5907 | if (! target_big_endian) |
8ea7f4e8 | 5908 | offset_expr.X_add_number += 1; |
0dd2d296 | 5909 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5910 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5911 | if (! target_big_endian) |
8ea7f4e8 ILT |
5912 | offset_expr.X_add_number -= 1; |
5913 | else | |
5914 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5915 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5916 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5917 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5918 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5919 | break; |
3d3c5039 | 5920 | |
adcf2b9d ILT |
5921 | case M_ULD: |
5922 | s = "ldl"; | |
5923 | s2 = "ldr"; | |
5924 | off = 7; | |
5925 | goto ulw; | |
3d3c5039 | 5926 | case M_ULW: |
adcf2b9d ILT |
5927 | s = "lwl"; |
5928 | s2 = "lwr"; | |
5929 | off = 3; | |
5930 | ulw: | |
5931 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5932 | as_bad ("operand overflow"); |
b9129c6f | 5933 | if (! target_big_endian) |
adcf2b9d ILT |
5934 | offset_expr.X_add_number += off; |
5935 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5936 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5937 | if (! target_big_endian) |
adcf2b9d | 5938 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5939 | else |
adcf2b9d ILT |
5940 | offset_expr.X_add_number += off; |
5941 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5942 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5943 | return; |
3d3c5039 | 5944 | |
adcf2b9d ILT |
5945 | case M_ULD_A: |
5946 | s = "ldl"; | |
5947 | s2 = "ldr"; | |
5948 | off = 7; | |
5949 | goto ulwa; | |
5950 | case M_ULW_A: | |
5951 | s = "lwl"; | |
5952 | s2 = "lwr"; | |
5953 | off = 3; | |
5954 | ulwa: | |
5955 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5956 | if (breg != 0) |
5957 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5958 | mips_isa < 3 ? "addu" : "daddu", | |
5959 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5960 | if (! target_big_endian) |
adcf2b9d ILT |
5961 | expr1.X_add_number = off; |
5962 | else | |
5963 | expr1.X_add_number = 0; | |
5964 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5965 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5966 | if (! target_big_endian) |
adcf2b9d ILT |
5967 | expr1.X_add_number = 0; |
5968 | else | |
5969 | expr1.X_add_number = off; | |
5970 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5971 | (int) BFD_RELOC_LO16, AT); | |
5972 | break; | |
5973 | ||
3d3c5039 ILT |
5974 | case M_ULH_A: |
5975 | case M_ULHU_A: | |
0dd2d296 | 5976 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5977 | if (breg != 0) |
5978 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5979 | mips_isa < 3 ? "addu" : "daddu", | |
5980 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5981 | if (target_big_endian) |
adcf2b9d ILT |
5982 | expr1.X_add_number = 0; |
5983 | macro_build ((char *) NULL, &icnt, &expr1, | |
5984 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5985 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5986 | if (target_big_endian) |
adcf2b9d | 5987 | expr1.X_add_number = 1; |
670a50eb | 5988 | else |
adcf2b9d ILT |
5989 | expr1.X_add_number = 0; |
5990 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5991 | (int) BFD_RELOC_LO16, AT); | |
5992 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5993 | treg, 8); | |
5994 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5995 | treg, AT); | |
670a50eb | 5996 | break; |
3d3c5039 ILT |
5997 | |
5998 | case M_USH: | |
8ea7f4e8 ILT |
5999 | if (offset_expr.X_add_number >= 0x7fff) |
6000 | as_bad ("operand overflow"); | |
b9129c6f | 6001 | if (target_big_endian) |
8ea7f4e8 | 6002 | offset_expr.X_add_number += 1; |
0dd2d296 | 6003 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6004 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6005 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6006 | if (target_big_endian) |
8ea7f4e8 ILT |
6007 | offset_expr.X_add_number -= 1; |
6008 | else | |
6009 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6010 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6011 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6012 | break; |
3d3c5039 | 6013 | |
adcf2b9d ILT |
6014 | case M_USD: |
6015 | s = "sdl"; | |
6016 | s2 = "sdr"; | |
6017 | off = 7; | |
6018 | goto usw; | |
3d3c5039 | 6019 | case M_USW: |
adcf2b9d ILT |
6020 | s = "swl"; |
6021 | s2 = "swr"; | |
6022 | off = 3; | |
6023 | usw: | |
6024 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6025 | as_bad ("operand overflow"); |
b9129c6f | 6026 | if (! target_big_endian) |
adcf2b9d ILT |
6027 | offset_expr.X_add_number += off; |
6028 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6029 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6030 | if (! target_big_endian) |
adcf2b9d | 6031 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6032 | else |
adcf2b9d ILT |
6033 | offset_expr.X_add_number += off; |
6034 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6035 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6036 | return; |
3d3c5039 | 6037 | |
adcf2b9d ILT |
6038 | case M_USD_A: |
6039 | s = "sdl"; | |
6040 | s2 = "sdr"; | |
6041 | off = 7; | |
6042 | goto uswa; | |
3d3c5039 | 6043 | case M_USW_A: |
adcf2b9d ILT |
6044 | s = "swl"; |
6045 | s2 = "swr"; | |
6046 | off = 3; | |
6047 | uswa: | |
0dd2d296 | 6048 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6049 | if (breg != 0) |
6050 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6051 | mips_isa < 3 ? "addu" : "daddu", | |
6052 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6053 | if (! target_big_endian) |
adcf2b9d | 6054 | expr1.X_add_number = off; |
670a50eb | 6055 | else |
adcf2b9d ILT |
6056 | expr1.X_add_number = 0; |
6057 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6058 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6059 | if (! target_big_endian) |
adcf2b9d ILT |
6060 | expr1.X_add_number = 0; |
6061 | else | |
6062 | expr1.X_add_number = off; | |
6063 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6064 | (int) BFD_RELOC_LO16, AT); | |
6065 | break; | |
6066 | ||
6067 | case M_USH_A: | |
6068 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6069 | if (breg != 0) |
6070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6071 | mips_isa < 3 ? "addu" : "daddu", | |
6072 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6073 | if (! target_big_endian) |
adcf2b9d ILT |
6074 | expr1.X_add_number = 0; |
6075 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6076 | (int) BFD_RELOC_LO16, AT); | |
6077 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6078 | treg, 8); | |
b9129c6f | 6079 | if (! target_big_endian) |
adcf2b9d ILT |
6080 | expr1.X_add_number = 1; |
6081 | else | |
6082 | expr1.X_add_number = 0; | |
6083 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6084 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6085 | if (! target_big_endian) |
adcf2b9d ILT |
6086 | expr1.X_add_number = 0; |
6087 | else | |
6088 | expr1.X_add_number = 1; | |
6089 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6090 | (int) BFD_RELOC_LO16, AT); | |
6091 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6092 | treg, 8); | |
6093 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6094 | treg, AT); | |
670a50eb | 6095 | break; |
3d3c5039 ILT |
6096 | |
6097 | default: | |
9218cee0 ILT |
6098 | /* FIXME: Check if this is one of the itbl macros, since they |
6099 | are added dynamically. */ | |
670a50eb | 6100 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6101 | break; |
3d3c5039 | 6102 | } |
670a50eb ILT |
6103 | if (mips_noat) |
6104 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
6105 | } |
6106 | ||
cc5703cd | 6107 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6108 | |
3d3c5039 | 6109 | static void |
cc5703cd | 6110 | mips16_macro (ip) |
3d3c5039 ILT |
6111 | struct mips_cl_insn *ip; |
6112 | { | |
cc5703cd ILT |
6113 | int mask; |
6114 | int xreg, yreg, zreg, tmp; | |
6115 | int icnt; | |
6116 | expressionS expr1; | |
6117 | int dbl; | |
6118 | const char *s, *s2, *s3; | |
3d3c5039 | 6119 | |
cc5703cd | 6120 | mask = ip->insn_mo->mask; |
3d3c5039 | 6121 | |
cc5703cd ILT |
6122 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6123 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6124 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6125 | |
cc5703cd | 6126 | icnt = 0; |
8358c818 | 6127 | |
cc5703cd ILT |
6128 | expr1.X_op = O_constant; |
6129 | expr1.X_op_symbol = NULL; | |
6130 | expr1.X_add_symbol = NULL; | |
6131 | expr1.X_add_number = 1; | |
8358c818 | 6132 | |
cc5703cd | 6133 | dbl = 0; |
517078c1 | 6134 | |
cc5703cd ILT |
6135 | switch (mask) |
6136 | { | |
6137 | default: | |
6138 | internalError (); | |
6139 | ||
6140 | case M_DDIV_3: | |
6141 | dbl = 1; | |
6142 | case M_DIV_3: | |
6143 | s = "mflo"; | |
6144 | goto do_div3; | |
6145 | case M_DREM_3: | |
6146 | dbl = 1; | |
6147 | case M_REM_3: | |
6148 | s = "mfhi"; | |
6149 | do_div3: | |
fbcfacb7 | 6150 | mips_emit_delays (true); |
cc5703cd ILT |
6151 | ++mips_noreorder; |
6152 | mips_any_noreorder = 1; | |
6153 | macro_build ((char *) NULL, &icnt, NULL, | |
6154 | dbl ? "ddiv" : "div", | |
6155 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6156 | expr1.X_add_number = 2; |
cc5703cd | 6157 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6158 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6159 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6160 | since that causes an overflow. We should do that as well, | |
6161 | but I don't see how to do the comparisons without a temporary | |
6162 | register. */ | |
6163 | --mips_noreorder; | |
6164 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6165 | break; | |
6166 | ||
6167 | case M_DIVU_3: | |
6168 | s = "divu"; | |
6169 | s2 = "mflo"; | |
6170 | goto do_divu3; | |
6171 | case M_REMU_3: | |
6172 | s = "divu"; | |
6173 | s2 = "mfhi"; | |
6174 | goto do_divu3; | |
6175 | case M_DDIVU_3: | |
6176 | s = "ddivu"; | |
6177 | s2 = "mflo"; | |
6178 | goto do_divu3; | |
6179 | case M_DREMU_3: | |
6180 | s = "ddivu"; | |
6181 | s2 = "mfhi"; | |
6182 | do_divu3: | |
fbcfacb7 | 6183 | mips_emit_delays (true); |
cc5703cd ILT |
6184 | ++mips_noreorder; |
6185 | mips_any_noreorder = 1; | |
6186 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6187 | expr1.X_add_number = 2; |
cc5703cd | 6188 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6189 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6190 | --mips_noreorder; | |
6191 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6192 | break; | |
6193 | ||
6194 | case M_DSUBU_I: | |
6195 | dbl = 1; | |
6196 | goto do_subu; | |
6197 | case M_SUBU_I: | |
6198 | do_subu: | |
6199 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6200 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6201 | dbl ? "daddiu" : "addiu", | |
6202 | "y,x,4", yreg, xreg); | |
6203 | break; | |
6204 | ||
6205 | case M_SUBU_I_2: | |
6206 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6207 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6208 | "x,k", xreg); | |
6209 | break; | |
6210 | ||
6211 | case M_DSUBU_I_2: | |
6212 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6213 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6214 | "y,j", yreg); | |
6215 | break; | |
6216 | ||
6217 | case M_BEQ: | |
6218 | s = "cmp"; | |
6219 | s2 = "bteqz"; | |
6220 | goto do_branch; | |
6221 | case M_BNE: | |
6222 | s = "cmp"; | |
6223 | s2 = "btnez"; | |
6224 | goto do_branch; | |
6225 | case M_BLT: | |
6226 | s = "slt"; | |
6227 | s2 = "btnez"; | |
6228 | goto do_branch; | |
6229 | case M_BLTU: | |
6230 | s = "sltu"; | |
6231 | s2 = "btnez"; | |
6232 | goto do_branch; | |
6233 | case M_BLE: | |
6234 | s = "slt"; | |
6235 | s2 = "bteqz"; | |
6236 | goto do_reverse_branch; | |
6237 | case M_BLEU: | |
6238 | s = "sltu"; | |
6239 | s2 = "bteqz"; | |
6240 | goto do_reverse_branch; | |
6241 | case M_BGE: | |
6242 | s = "slt"; | |
6243 | s2 = "bteqz"; | |
6244 | goto do_branch; | |
6245 | case M_BGEU: | |
6246 | s = "sltu"; | |
6247 | s2 = "bteqz"; | |
6248 | goto do_branch; | |
6249 | case M_BGT: | |
6250 | s = "slt"; | |
6251 | s2 = "btnez"; | |
6252 | goto do_reverse_branch; | |
6253 | case M_BGTU: | |
6254 | s = "sltu"; | |
6255 | s2 = "btnez"; | |
6256 | ||
6257 | do_reverse_branch: | |
6258 | tmp = xreg; | |
6259 | xreg = yreg; | |
6260 | yreg = tmp; | |
6261 | ||
6262 | do_branch: | |
6263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6264 | xreg, yreg); | |
6265 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6266 | break; | |
6267 | ||
6268 | case M_BEQ_I: | |
6269 | s = "cmpi"; | |
6270 | s2 = "bteqz"; | |
6271 | s3 = "x,U"; | |
6272 | goto do_branch_i; | |
6273 | case M_BNE_I: | |
6274 | s = "cmpi"; | |
6275 | s2 = "btnez"; | |
6276 | s3 = "x,U"; | |
6277 | goto do_branch_i; | |
6278 | case M_BLT_I: | |
6279 | s = "slti"; | |
6280 | s2 = "btnez"; | |
6281 | s3 = "x,8"; | |
6282 | goto do_branch_i; | |
6283 | case M_BLTU_I: | |
6284 | s = "sltiu"; | |
6285 | s2 = "btnez"; | |
6286 | s3 = "x,8"; | |
6287 | goto do_branch_i; | |
6288 | case M_BLE_I: | |
6289 | s = "slti"; | |
6290 | s2 = "btnez"; | |
6291 | s3 = "x,8"; | |
6292 | goto do_addone_branch_i; | |
6293 | case M_BLEU_I: | |
6294 | s = "sltiu"; | |
6295 | s2 = "btnez"; | |
6296 | s3 = "x,8"; | |
6297 | goto do_addone_branch_i; | |
6298 | case M_BGE_I: | |
6299 | s = "slti"; | |
6300 | s2 = "bteqz"; | |
6301 | s3 = "x,8"; | |
6302 | goto do_branch_i; | |
6303 | case M_BGEU_I: | |
6304 | s = "sltiu"; | |
6305 | s2 = "bteqz"; | |
6306 | s3 = "x,8"; | |
6307 | goto do_branch_i; | |
6308 | case M_BGT_I: | |
6309 | s = "slti"; | |
6310 | s2 = "bteqz"; | |
6311 | s3 = "x,8"; | |
6312 | goto do_addone_branch_i; | |
6313 | case M_BGTU_I: | |
6314 | s = "sltiu"; | |
6315 | s2 = "bteqz"; | |
6316 | s3 = "x,8"; | |
6317 | ||
6318 | do_addone_branch_i: | |
6319 | ++imm_expr.X_add_number; | |
6320 | ||
6321 | do_branch_i: | |
6322 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6323 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6324 | break; | |
18e0764d ILT |
6325 | |
6326 | case M_ABS: | |
6327 | expr1.X_add_number = 0; | |
6328 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6329 | if (xreg != yreg) | |
6330 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6331 | "move", "y,X", xreg, yreg); | |
6332 | expr1.X_add_number = 2; | |
6333 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6334 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6335 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6336 | } |
6337 | } | |
6338 | ||
6339 | /* This routine assembles an instruction into its binary format. As a | |
6340 | side effect, it sets one of the global variables imm_reloc or | |
6341 | offset_reloc to the type of relocation to do if one of the operands | |
6342 | is an address expression. */ | |
6343 | ||
6344 | static void | |
6345 | mips_ip (str, ip) | |
6346 | char *str; | |
6347 | struct mips_cl_insn *ip; | |
6348 | { | |
6349 | char *s; | |
6350 | const char *args; | |
6351 | char c; | |
6352 | struct mips_opcode *insn; | |
6353 | char *argsStart; | |
6354 | unsigned int regno; | |
6355 | unsigned int lastregno = 0; | |
6356 | char *s_reset; | |
6357 | ||
6358 | insn_error = NULL; | |
6359 | ||
e2e5acfa | 6360 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6361 | continue; |
1857d1e6 | 6362 | if (isspace (*s)) |
e2e5acfa | 6363 | *s++ = '\0'; |
1857d1e6 | 6364 | |
cc5703cd ILT |
6365 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6366 | { | |
6367 | insn_error = "unrecognized opcode"; | |
6368 | return; | |
6369 | } | |
6370 | argsStart = s; | |
6371 | for (;;) | |
6372 | { | |
6373 | int insn_isa; | |
6374 | ||
6375 | assert (strcmp (insn->name, str) == 0); | |
6376 | ||
6377 | if (insn->pinfo == INSN_MACRO) | |
6378 | insn_isa = insn->match; | |
6379 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6380 | insn_isa = 2; | |
6381 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6382 | insn_isa = 3; | |
6383 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6384 | insn_isa = 4; | |
6385 | else | |
6386 | insn_isa = 1; | |
6387 | ||
6388 | if (insn_isa > mips_isa | |
16262668 ILT |
6389 | || (insn->pinfo != INSN_MACRO |
6390 | && (((insn->pinfo & INSN_ISA) == INSN_4650 | |
6391 | && ! mips_4650) | |
6392 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6393 | && ! mips_4010) | |
6394 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6395 | && ! mips_4100) | |
6396 | /* start-sanitize-r5900 */ | |
6397 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6398 | && ! mips_5900) | |
6399 | /* end-sanitize-r5900 */ | |
6400 | ))) | |
cc5703cd ILT |
6401 | { |
6402 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6403 | && strcmp (insn->name, insn[1].name) == 0) | |
6404 | { | |
6405 | ++insn; | |
6406 | continue; | |
6407 | } | |
6408 | if (insn_isa <= mips_isa) | |
6409 | insn_error = "opcode not supported on this processor"; | |
6410 | else | |
6411 | { | |
6412 | static char buf[100]; | |
6413 | ||
6414 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6415 | insn_error = buf; | |
6416 | } | |
6417 | return; | |
6418 | } | |
8358c818 | 6419 | |
670a50eb ILT |
6420 | ip->insn_mo = insn; |
6421 | ip->insn_opcode = insn->match; | |
6422 | for (args = insn->args;; ++args) | |
6423 | { | |
6424 | if (*s == ' ') | |
6425 | ++s; | |
6426 | switch (*args) | |
6427 | { | |
6428 | case '\0': /* end of args */ | |
6429 | if (*s == '\0') | |
6430 | return; | |
6431 | break; | |
3d3c5039 ILT |
6432 | |
6433 | case ',': | |
670a50eb ILT |
6434 | if (*s++ == *args) |
6435 | continue; | |
6436 | s--; | |
6437 | switch (*++args) | |
6438 | { | |
3d3c5039 ILT |
6439 | case 'r': |
6440 | case 'v': | |
670a50eb ILT |
6441 | ip->insn_opcode |= lastregno << 21; |
6442 | continue; | |
3d3c5039 ILT |
6443 | |
6444 | case 'w': | |
6445 | case 'W': | |
670a50eb ILT |
6446 | ip->insn_opcode |= lastregno << 16; |
6447 | continue; | |
3d3c5039 ILT |
6448 | |
6449 | case 'V': | |
670a50eb ILT |
6450 | ip->insn_opcode |= lastregno << 11; |
6451 | continue; | |
3d3c5039 | 6452 | } |
670a50eb | 6453 | break; |
3d3c5039 ILT |
6454 | |
6455 | case '(': | |
670a50eb ILT |
6456 | /* handle optional base register. |
6457 | Either the base register is omitted or | |
6458 | we must have a left paren. */ | |
6459 | /* this is dependent on the next operand specifier | |
6460 | is a 'b' for base register */ | |
6461 | assert (args[1] == 'b'); | |
6462 | if (*s == '\0') | |
6463 | return; | |
3d3c5039 | 6464 | |
670a50eb ILT |
6465 | case ')': /* these must match exactly */ |
6466 | if (*s++ == *args) | |
3d3c5039 | 6467 | continue; |
670a50eb ILT |
6468 | break; |
6469 | ||
6470 | case '<': /* must be at least one digit */ | |
6471 | /* | |
6472 | * According to the manual, if the shift amount is greater | |
6473 | * than 31 or less than 0 the the shift amount should be | |
6474 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6475 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6476 | */ |
6477 | my_getExpression (&imm_expr, s); | |
6478 | check_absolute_expr (ip, &imm_expr); | |
6479 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6480 | { | |
58d4951d ILT |
6481 | as_warn ("Improper shift amount (%ld)", |
6482 | (long) imm_expr.X_add_number); | |
9226253a | 6483 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6484 | } |
6485 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6486 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6487 | s = expr_end; |
6488 | continue; | |
6489 | ||
56c96faa ILT |
6490 | case '>': /* shift amount minus 32 */ |
6491 | my_getExpression (&imm_expr, s); | |
6492 | check_absolute_expr (ip, &imm_expr); | |
6493 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6494 | || (unsigned long) imm_expr.X_add_number > 63) | |
6495 | break; | |
6496 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6497 | imm_expr.X_op = O_absent; | |
6498 | s = expr_end; | |
6499 | continue; | |
6500 | ||
9226253a | 6501 | case 'k': /* cache code */ |
d8a1c247 | 6502 | case 'h': /* prefx code */ |
9226253a ILT |
6503 | my_getExpression (&imm_expr, s); |
6504 | check_absolute_expr (ip, &imm_expr); | |
6505 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6506 | { | |
d8a1c247 KR |
6507 | as_warn ("Invalid value for `%s' (%lu)", |
6508 | ip->insn_mo->name, | |
9226253a ILT |
6509 | (unsigned long) imm_expr.X_add_number); |
6510 | imm_expr.X_add_number &= 0x1f; | |
6511 | } | |
d8a1c247 KR |
6512 | if (*args == 'k') |
6513 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6514 | else | |
6515 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6516 | imm_expr.X_op = O_absent; |
6517 | s = expr_end; | |
6518 | continue; | |
6519 | ||
670a50eb ILT |
6520 | case 'c': /* break code */ |
6521 | my_getExpression (&imm_expr, s); | |
6522 | check_absolute_expr (ip, &imm_expr); | |
6523 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6524 | as_warn ("Illegal break code (%ld)", |
6525 | (long) imm_expr.X_add_number); | |
670a50eb | 6526 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6527 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6528 | s = expr_end; |
6529 | continue; | |
6530 | ||
918692a5 ILT |
6531 | case 'B': /* syscall code */ |
6532 | my_getExpression (&imm_expr, s); | |
6533 | check_absolute_expr (ip, &imm_expr); | |
6534 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6535 | as_warn ("Illegal syscall code (%ld)", |
6536 | (long) imm_expr.X_add_number); | |
918692a5 | 6537 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6538 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6539 | s = expr_end; |
6540 | continue; | |
6541 | ||
0aa07269 ILT |
6542 | case 'C': /* Coprocessor code */ |
6543 | my_getExpression (&imm_expr, s); | |
6544 | check_absolute_expr (ip, &imm_expr); | |
6545 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6546 | { | |
58d4951d ILT |
6547 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6548 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6549 | imm_expr.X_add_number &= ((1<<25) - 1); |
6550 | } | |
6551 | ip->insn_opcode |= imm_expr.X_add_number; | |
6552 | imm_expr.X_op = O_absent; | |
6553 | s = expr_end; | |
6554 | continue; | |
6555 | ||
670a50eb ILT |
6556 | case 'b': /* base register */ |
6557 | case 'd': /* destination register */ | |
6558 | case 's': /* source register */ | |
6559 | case 't': /* target register */ | |
6560 | case 'r': /* both target and source */ | |
6561 | case 'v': /* both dest and source */ | |
6562 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6563 | case 'E': /* coprocessor target register */ |
6564 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6565 | case 'x': /* ignore register name */ |
ff3a5c18 | 6566 | case 'z': /* must be zero register */ |
670a50eb ILT |
6567 | s_reset = s; |
6568 | if (s[0] == '$') | |
6569 | { | |
6570 | if (isdigit (s[1])) | |
6571 | { | |
6572 | ++s; | |
6573 | regno = 0; | |
6574 | do | |
6575 | { | |
6576 | regno *= 10; | |
6577 | regno += *s - '0'; | |
6578 | ++s; | |
6579 | } | |
6580 | while (isdigit (*s)); | |
0aa07269 ILT |
6581 | if (regno > 31) |
6582 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6583 | } |
0dd2d296 ILT |
6584 | else if (*args == 'E' || *args == 'G') |
6585 | goto notreg; | |
6586 | else | |
670a50eb | 6587 | { |
0aa07269 ILT |
6588 | if (s[1] == 'f' && s[2] == 'p') |
6589 | { | |
6590 | s += 3; | |
9226253a | 6591 | regno = FP; |
0aa07269 ILT |
6592 | } |
6593 | else if (s[1] == 's' && s[2] == 'p') | |
6594 | { | |
6595 | s += 3; | |
9226253a | 6596 | regno = SP; |
0aa07269 ILT |
6597 | } |
6598 | else if (s[1] == 'g' && s[2] == 'p') | |
6599 | { | |
6600 | s += 3; | |
9226253a | 6601 | regno = GP; |
0aa07269 ILT |
6602 | } |
6603 | else if (s[1] == 'a' && s[2] == 't') | |
6604 | { | |
6605 | s += 3; | |
9226253a | 6606 | regno = AT; |
0aa07269 | 6607 | } |
b2b8c24e ILT |
6608 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6609 | { | |
6610 | s += 4; | |
6611 | regno = KT0; | |
6612 | } | |
6613 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6614 | { | |
6615 | s += 4; | |
6616 | regno = KT1; | |
6617 | } | |
efec4a28 DP |
6618 | else if (itbl_have_entries) |
6619 | { | |
6620 | char *p, *n; | |
6621 | int r; | |
6622 | ||
6623 | p = s+1; /* advance past '$' */ | |
9218cee0 | 6624 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
6625 | |
6626 | /* See if this is a register defined in an | |
6627 | itbl entry */ | |
9218cee0 ILT |
6628 | r = itbl_get_reg_val (n); |
6629 | if (r) | |
efec4a28 | 6630 | { |
9218cee0 ILT |
6631 | /* Get_field advances to the start of |
6632 | the next field, so we need to back | |
6633 | rack to the end of the last field. */ | |
efec4a28 | 6634 | if (p) |
9218cee0 | 6635 | s = p - 1; |
efec4a28 | 6636 | else |
9218cee0 | 6637 | s = strchr (s,'\0'); |
efec4a28 DP |
6638 | regno = r; |
6639 | } | |
6640 | else | |
6641 | goto notreg; | |
6642 | } | |
0aa07269 ILT |
6643 | else |
6644 | goto notreg; | |
670a50eb | 6645 | } |
9753202d ILT |
6646 | if (regno == AT |
6647 | && ! mips_noat | |
6648 | && *args != 'E' | |
6649 | && *args != 'G') | |
13fe1379 | 6650 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6651 | c = *args; |
6652 | if (*s == ' ') | |
6653 | s++; | |
6654 | if (args[1] != *s) | |
6655 | { | |
6656 | if (c == 'r' || c == 'v' || c == 'w') | |
6657 | { | |
6658 | regno = lastregno; | |
6659 | s = s_reset; | |
6660 | args++; | |
6661 | } | |
6662 | } | |
ff3a5c18 ILT |
6663 | /* 'z' only matches $0. */ |
6664 | if (c == 'z' && regno != 0) | |
6665 | break; | |
efec4a28 DP |
6666 | |
6667 | /* Now that we have assembled one operand, we use the args string | |
6668 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
6669 | switch (c) |
6670 | { | |
3d3c5039 ILT |
6671 | case 'r': |
6672 | case 's': | |
6673 | case 'v': | |
6674 | case 'b': | |
670a50eb ILT |
6675 | ip->insn_opcode |= regno << 21; |
6676 | break; | |
3d3c5039 | 6677 | case 'd': |
918692a5 | 6678 | case 'G': |
670a50eb ILT |
6679 | ip->insn_opcode |= regno << 11; |
6680 | break; | |
3d3c5039 ILT |
6681 | case 'w': |
6682 | case 't': | |
918692a5 | 6683 | case 'E': |
670a50eb | 6684 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6685 | break; |
6686 | case 'x': | |
6687 | /* This case exists because on the r3000 trunc | |
6688 | expands into a macro which requires a gp | |
6689 | register. On the r6000 or r4000 it is | |
6690 | assembled into a single instruction which | |
6691 | ignores the register. Thus the insn version | |
6692 | is MIPS_ISA2 and uses 'x', and the macro | |
6693 | version is MIPS_ISA1 and uses 't'. */ | |
6694 | break; | |
ff3a5c18 ILT |
6695 | case 'z': |
6696 | /* This case is for the div instruction, which | |
6697 | acts differently if the destination argument | |
6698 | is $0. This only matches $0, and is checked | |
6699 | outside the switch. */ | |
6700 | break; | |
efec4a28 DP |
6701 | case 'D': |
6702 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
6703 | break; | |
9218cee0 ILT |
6704 | /* What about all other operands like 'i', which |
6705 | can be specified in the opcode table? */ | |
3d3c5039 | 6706 | } |
670a50eb ILT |
6707 | lastregno = regno; |
6708 | continue; | |
3d3c5039 ILT |
6709 | } |
6710 | notreg: | |
670a50eb ILT |
6711 | switch (*args++) |
6712 | { | |
3d3c5039 ILT |
6713 | case 'r': |
6714 | case 'v': | |
670a50eb ILT |
6715 | ip->insn_opcode |= lastregno << 21; |
6716 | continue; | |
3d3c5039 | 6717 | case 'w': |
670a50eb ILT |
6718 | ip->insn_opcode |= lastregno << 16; |
6719 | continue; | |
3d3c5039 | 6720 | } |
670a50eb | 6721 | break; |
3d3c5039 | 6722 | |
670a50eb ILT |
6723 | case 'D': /* floating point destination register */ |
6724 | case 'S': /* floating point source register */ | |
6725 | case 'T': /* floating point target register */ | |
d8a1c247 | 6726 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6727 | case 'V': |
6728 | case 'W': | |
670a50eb ILT |
6729 | s_reset = s; |
6730 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6731 | { | |
6732 | s += 2; | |
6733 | regno = 0; | |
6734 | do | |
6735 | { | |
6736 | regno *= 10; | |
6737 | regno += *s - '0'; | |
6738 | ++s; | |
6739 | } | |
6740 | while (isdigit (*s)); | |
6741 | ||
6742 | if (regno > 31) | |
6743 | as_bad ("Invalid float register number (%d)", regno); | |
6744 | ||
9226253a ILT |
6745 | if ((regno & 1) != 0 |
6746 | && mips_isa < 3 | |
538034cf ILT |
6747 | && ! (strcmp (str, "mtc1") == 0 |
6748 | || strcmp (str, "mfc1") == 0 | |
6749 | || strcmp (str, "lwc1") == 0 | |
6750 | || strcmp (str, "swc1") == 0 | |
6751 | || strcmp (str, "l.s") == 0 | |
6752 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6753 | as_warn ("Float register should be even, was %d", |
6754 | regno); | |
6755 | ||
6756 | c = *args; | |
6757 | if (*s == ' ') | |
6758 | s++; | |
6759 | if (args[1] != *s) | |
6760 | { | |
6761 | if (c == 'V' || c == 'W') | |
6762 | { | |
6763 | regno = lastregno; | |
6764 | s = s_reset; | |
6765 | args++; | |
3d3c5039 ILT |
6766 | } |
6767 | } | |
670a50eb ILT |
6768 | switch (c) |
6769 | { | |
3d3c5039 | 6770 | case 'D': |
670a50eb ILT |
6771 | ip->insn_opcode |= regno << 6; |
6772 | break; | |
3d3c5039 ILT |
6773 | case 'V': |
6774 | case 'S': | |
670a50eb ILT |
6775 | ip->insn_opcode |= regno << 11; |
6776 | break; | |
3d3c5039 ILT |
6777 | case 'W': |
6778 | case 'T': | |
670a50eb | 6779 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6780 | break; |
6781 | case 'R': | |
6782 | ip->insn_opcode |= regno << 21; | |
6783 | break; | |
3d3c5039 | 6784 | } |
670a50eb ILT |
6785 | lastregno = regno; |
6786 | continue; | |
3d3c5039 | 6787 | } |
670a50eb ILT |
6788 | switch (*args++) |
6789 | { | |
3d3c5039 | 6790 | case 'V': |
670a50eb ILT |
6791 | ip->insn_opcode |= lastregno << 11; |
6792 | continue; | |
3d3c5039 | 6793 | case 'W': |
670a50eb ILT |
6794 | ip->insn_opcode |= lastregno << 16; |
6795 | continue; | |
3d3c5039 | 6796 | } |
670a50eb | 6797 | break; |
3d3c5039 ILT |
6798 | |
6799 | case 'I': | |
670a50eb | 6800 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6801 | if (imm_expr.X_op != O_big |
6802 | && imm_expr.X_op != O_constant) | |
6803 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6804 | s = expr_end; |
6805 | continue; | |
3d3c5039 ILT |
6806 | |
6807 | case 'A': | |
670a50eb ILT |
6808 | my_getExpression (&offset_expr, s); |
6809 | imm_reloc = BFD_RELOC_32; | |
6810 | s = expr_end; | |
6811 | continue; | |
3d3c5039 ILT |
6812 | |
6813 | case 'F': | |
19ed8960 ILT |
6814 | case 'L': |
6815 | case 'f': | |
6816 | case 'l': | |
6817 | { | |
6818 | int f64; | |
6819 | char *save_in; | |
6820 | char *err; | |
6821 | unsigned char temp[8]; | |
604633ae ILT |
6822 | int len; |
6823 | unsigned int length; | |
19ed8960 ILT |
6824 | segT seg; |
6825 | subsegT subseg; | |
6826 | char *p; | |
6827 | ||
6828 | /* These only appear as the last operand in an | |
6829 | instruction, and every instruction that accepts | |
6830 | them in any variant accepts them in all variants. | |
6831 | This means we don't have to worry about backing out | |
6832 | any changes if the instruction does not match. | |
6833 | ||
6834 | The difference between them is the size of the | |
6835 | floating point constant and where it goes. For 'F' | |
6836 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6837 | is 32 bits. Where the constant is placed is based | |
6838 | on how the MIPS assembler does things: | |
6839 | F -- .rdata | |
6840 | L -- .lit8 | |
6841 | f -- immediate value | |
6842 | l -- .lit4 | |
0dd2d296 | 6843 | |
55933a58 ILT |
6844 | The .lit4 and .lit8 sections are only used if |
6845 | permitted by the -G argument. | |
6846 | ||
6847 | When generating embedded PIC code, we use the | |
6848 | .lit8 section but not the .lit4 section (we can do | |
6849 | .lit4 inline easily; we need to put .lit8 | |
6850 | somewhere in the data segment, and using .lit8 | |
6851 | permits the linker to eventually combine identical | |
6852 | .lit8 entries). */ | |
19ed8960 ILT |
6853 | |
6854 | f64 = *args == 'F' || *args == 'L'; | |
6855 | ||
6856 | save_in = input_line_pointer; | |
6857 | input_line_pointer = s; | |
604633ae ILT |
6858 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6859 | length = len; | |
19ed8960 ILT |
6860 | s = input_line_pointer; |
6861 | input_line_pointer = save_in; | |
6862 | if (err != NULL && *err != '\0') | |
6863 | { | |
6864 | as_bad ("Bad floating point constant: %s", err); | |
6865 | memset (temp, '\0', sizeof temp); | |
6866 | length = f64 ? 8 : 4; | |
6867 | } | |
6868 | ||
6869 | assert (length == (f64 ? 8 : 4)); | |
6870 | ||
0dd2d296 | 6871 | if (*args == 'f' |
55933a58 | 6872 | || (*args == 'l' |
1dc1e798 KR |
6873 | && (! USE_GLOBAL_POINTER_OPT |
6874 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6875 | || g_switch_value < 4) |
1113140a | 6876 | )) |
19ed8960 ILT |
6877 | { |
6878 | imm_expr.X_op = O_constant; | |
b9129c6f | 6879 | if (! target_big_endian) |
19ed8960 ILT |
6880 | imm_expr.X_add_number = |
6881 | (((((((int) temp[3] << 8) | |
6882 | | temp[2]) << 8) | |
6883 | | temp[1]) << 8) | |
6884 | | temp[0]); | |
6885 | else | |
6886 | imm_expr.X_add_number = | |
6887 | (((((((int) temp[0] << 8) | |
6888 | | temp[1]) << 8) | |
6889 | | temp[2]) << 8) | |
6890 | | temp[3]); | |
6891 | } | |
6892 | else | |
6893 | { | |
0dd2d296 ILT |
6894 | const char *newname; |
6895 | segT new_seg; | |
6896 | ||
19ed8960 ILT |
6897 | /* Switch to the right section. */ |
6898 | seg = now_seg; | |
6899 | subseg = now_subseg; | |
6900 | switch (*args) | |
6901 | { | |
0dd2d296 | 6902 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6903 | case 'L': |
1113140a | 6904 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6905 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6906 | newname = ".lit8"; |
0dd2d296 ILT |
6907 | break; |
6908 | case 'F': | |
d2c71068 | 6909 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6910 | break; |
6911 | case 'l': | |
1dc1e798 KR |
6912 | assert (!USE_GLOBAL_POINTER_OPT |
6913 | || g_switch_value >= 4); | |
0dd2d296 | 6914 | newname = ".lit4"; |
19ed8960 ILT |
6915 | break; |
6916 | } | |
0dd2d296 | 6917 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6918 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6919 | bfd_set_section_flags (stdoutput, new_seg, | |
6920 | (SEC_ALLOC | |
6921 | | SEC_LOAD | |
6922 | | SEC_READONLY | |
6923 | | SEC_DATA)); | |
e2e5acfa JW |
6924 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
6925 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
6926 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
6927 | record_alignment (new_seg, 4); |
6928 | else | |
6929 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6930 | if (seg == now_seg) |
6931 | as_bad ("Can't use floating point insn in this section"); | |
6932 | ||
6933 | /* Set the argument to the current address in the | |
6e8dda9c | 6934 | section. */ |
19ed8960 ILT |
6935 | offset_expr.X_op = O_symbol; |
6936 | offset_expr.X_add_symbol = | |
6937 | symbol_new ("L0\001", now_seg, | |
6938 | (valueT) frag_now_fix (), frag_now); | |
6939 | offset_expr.X_add_number = 0; | |
6940 | ||
6941 | /* Put the floating point number into the section. */ | |
604633ae | 6942 | p = frag_more ((int) length); |
19ed8960 ILT |
6943 | memcpy (p, temp, length); |
6944 | ||
6945 | /* Switch back to the original section. */ | |
6946 | subseg_set (seg, subseg); | |
6947 | } | |
6948 | } | |
670a50eb ILT |
6949 | continue; |
6950 | ||
6951 | case 'i': /* 16 bit unsigned immediate */ | |
6952 | case 'j': /* 16 bit signed immediate */ | |
6953 | imm_reloc = BFD_RELOC_LO16; | |
6954 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6955 | if (c != '\0') |
670a50eb ILT |
6956 | { |
6957 | if (c != 'l') | |
6958 | { | |
5ac34ac3 | 6959 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6960 | imm_expr.X_add_number = |
6961 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6962 | else if (c == 'h') | |
867a58b3 ILT |
6963 | { |
6964 | imm_reloc = BFD_RELOC_HI16_S; | |
6965 | imm_unmatched_hi = true; | |
6966 | } | |
670a50eb ILT |
6967 | else |
6968 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6969 | } |
670a50eb | 6970 | } |
670a50eb ILT |
6971 | if (*args == 'i') |
6972 | { | |
344a8d61 | 6973 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6974 | || ((imm_expr.X_add_number < 0 |
6975 | || imm_expr.X_add_number >= 0x10000) | |
6976 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6977 | { |
6978 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6979 | !strcmp (insn->name, insn[1].name)) | |
6980 | break; | |
9753202d ILT |
6981 | if (imm_expr.X_op != O_constant |
6982 | && imm_expr.X_op != O_big) | |
6983 | insn_error = "absolute expression required"; | |
6984 | else | |
6985 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6986 | } |
670a50eb ILT |
6987 | } |
6988 | else | |
6989 | { | |
d9aba805 ILT |
6990 | int more; |
6991 | offsetT max; | |
6992 | ||
be22008b ILT |
6993 | /* The upper bound should be 0x8000, but |
6994 | unfortunately the MIPS assembler accepts numbers | |
6995 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6996 | we want to be compatible. We only permit this |
6997 | extended range for an instruction which does not | |
6998 | provide any further alternates, since those | |
6999 | alternates may handle other cases. People should | |
7000 | use the numbers they mean, rather than relying on | |
7001 | a mysterious sign extension. */ | |
7002 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7003 | strcmp (insn->name, insn[1].name) == 0); | |
7004 | if (more) | |
7005 | max = 0x8000; | |
7006 | else | |
7007 | max = 0x10000; | |
344a8d61 | 7008 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7009 | || ((imm_expr.X_add_number < -0x8000 |
7010 | || imm_expr.X_add_number >= max) | |
7011 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7012 | || (more |
7013 | && imm_expr.X_add_number < 0 | |
7014 | && mips_isa >= 3 | |
7015 | && imm_expr.X_unsigned | |
7016 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7017 | { |
d9aba805 | 7018 | if (more) |
99c24539 | 7019 | break; |
9753202d ILT |
7020 | if (imm_expr.X_op != O_constant |
7021 | && imm_expr.X_op != O_big) | |
7022 | insn_error = "absolute expression required"; | |
7023 | else | |
7024 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7025 | } |
3d3c5039 | 7026 | } |
670a50eb ILT |
7027 | s = expr_end; |
7028 | continue; | |
7029 | ||
7030 | case 'o': /* 16 bit offset */ | |
7031 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7032 | |
7033 | /* If this value won't fit into a 16 bit offset, then go | |
7034 | find a macro that will generate the 32 bit offset | |
7035 | code pattern. As a special hack, we accept the | |
7036 | difference of two local symbols as a constant. This | |
7037 | is required to suppose embedded PIC switches, which | |
7038 | use an instruction which looks like | |
7039 | lw $4,$L12-$LS12($4) | |
7040 | The problem with handling this in a more general | |
7041 | fashion is that the macro function doesn't expect to | |
7042 | see anything which can be handled in a single | |
7043 | constant instruction. */ | |
6f0b87c3 SS |
7044 | if (c == 0 |
7045 | && (offset_expr.X_op != O_constant | |
7046 | || offset_expr.X_add_number >= 0x8000 | |
7047 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7048 | && (mips_pic != EMBEDDED_PIC |
7049 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7050 | || now_seg != text_section |
7051 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7052 | != text_section))) | |
670a50eb | 7053 | break; |
3d3c5039 | 7054 | |
670a50eb ILT |
7055 | offset_reloc = BFD_RELOC_LO16; |
7056 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7057 | { |
7058 | assert (offset_expr.X_op == O_constant); | |
7059 | offset_expr.X_add_number = | |
7060 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7061 | } | |
cc5703cd ILT |
7062 | s = expr_end; |
7063 | continue; | |
7064 | ||
7065 | case 'p': /* pc relative offset */ | |
7066 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7067 | my_getExpression (&offset_expr, s); | |
7068 | s = expr_end; | |
7069 | continue; | |
7070 | ||
7071 | case 'u': /* upper 16 bits */ | |
7072 | c = my_getSmallExpression (&imm_expr, s); | |
7073 | if (imm_expr.X_op == O_constant | |
7074 | && (imm_expr.X_add_number < 0 | |
7075 | || imm_expr.X_add_number >= 0x10000)) | |
7076 | as_bad ("lui expression not in range 0..65535"); | |
7077 | imm_reloc = BFD_RELOC_LO16; | |
7078 | if (c) | |
7079 | { | |
7080 | if (c != 'l') | |
7081 | { | |
7082 | if (imm_expr.X_op == O_constant) | |
7083 | imm_expr.X_add_number = | |
7084 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7085 | else if (c == 'h') | |
7086 | { | |
7087 | imm_reloc = BFD_RELOC_HI16_S; | |
7088 | imm_unmatched_hi = true; | |
7089 | } | |
7090 | else | |
7091 | imm_reloc = BFD_RELOC_HI16; | |
7092 | } | |
7093 | } | |
7094 | s = expr_end; | |
7095 | continue; | |
7096 | ||
7097 | case 'a': /* 26 bit address */ | |
7098 | my_getExpression (&offset_expr, s); | |
7099 | s = expr_end; | |
7100 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7101 | continue; | |
7102 | ||
7103 | case 'N': /* 3 bit branch condition code */ | |
7104 | case 'M': /* 3 bit compare condition code */ | |
7105 | if (strncmp (s, "$fcc", 4) != 0) | |
7106 | break; | |
7107 | s += 4; | |
7108 | regno = 0; | |
7109 | do | |
7110 | { | |
7111 | regno *= 10; | |
7112 | regno += *s - '0'; | |
7113 | ++s; | |
7114 | } | |
7115 | while (isdigit (*s)); | |
7116 | if (regno > 7) | |
7117 | as_bad ("invalid condition code register $fcc%d", regno); | |
7118 | if (*args == 'N') | |
7119 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7120 | else | |
7121 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7122 | continue; | |
7123 | ||
7124 | default: | |
7125 | fprintf (stderr, "bad char = '%c'\n", *args); | |
7126 | internalError (); | |
7127 | } | |
7128 | break; | |
7129 | } | |
7130 | /* Args don't match. */ | |
7131 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7132 | !strcmp (insn->name, insn[1].name)) | |
7133 | { | |
7134 | ++insn; | |
7135 | s = argsStart; | |
7136 | continue; | |
7137 | } | |
7138 | insn_error = "illegal operands"; | |
7139 | return; | |
7140 | } | |
7141 | } | |
7142 | ||
7143 | /* This routine assembles an instruction into its binary format when | |
7144 | assembling for the mips16. As a side effect, it sets one of the | |
7145 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7146 | relocation to do if one of the operands is an address expression. |
7147 | It also sets mips16_small and mips16_ext if the user explicitly | |
7148 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7149 | |
7150 | static void | |
7151 | mips16_ip (str, ip) | |
7152 | char *str; | |
7153 | struct mips_cl_insn *ip; | |
7154 | { | |
7155 | char *s; | |
cc5703cd ILT |
7156 | const char *args; |
7157 | struct mips_opcode *insn; | |
7158 | char *argsstart; | |
7159 | unsigned int regno; | |
7160 | unsigned int lastregno = 0; | |
7161 | char *s_reset; | |
7162 | ||
7163 | insn_error = NULL; | |
7164 | ||
8728fa92 ILT |
7165 | mips16_small = false; |
7166 | mips16_ext = false; | |
cc5703cd ILT |
7167 | |
7168 | for (s = str; islower (*s); ++s) | |
7169 | ; | |
7170 | switch (*s) | |
7171 | { | |
7172 | case '\0': | |
7173 | break; | |
7174 | ||
7175 | case ' ': | |
7176 | *s++ = '\0'; | |
7177 | break; | |
7178 | ||
7179 | case '.': | |
7180 | if (s[1] == 't' && s[2] == ' ') | |
7181 | { | |
7182 | *s = '\0'; | |
8728fa92 | 7183 | mips16_small = true; |
cc5703cd ILT |
7184 | s += 3; |
7185 | break; | |
7186 | } | |
7187 | else if (s[1] == 'e' && s[2] == ' ') | |
7188 | { | |
7189 | *s = '\0'; | |
8728fa92 | 7190 | mips16_ext = true; |
cc5703cd ILT |
7191 | s += 3; |
7192 | break; | |
7193 | } | |
7194 | /* Fall through. */ | |
7195 | default: | |
7196 | insn_error = "unknown opcode"; | |
7197 | return; | |
7198 | } | |
7199 | ||
8728fa92 ILT |
7200 | if (! mips16_autoextend && ! mips16_ext) |
7201 | mips16_small = true; | |
7202 | ||
cc5703cd ILT |
7203 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7204 | { | |
7205 | insn_error = "unrecognized opcode"; | |
7206 | return; | |
7207 | } | |
7208 | ||
7209 | argsstart = s; | |
7210 | for (;;) | |
7211 | { | |
7212 | assert (strcmp (insn->name, str) == 0); | |
7213 | ||
7214 | ip->insn_mo = insn; | |
7215 | ip->insn_opcode = insn->match; | |
7216 | ip->use_extend = false; | |
7217 | imm_expr.X_op = O_absent; | |
7218 | imm_reloc = BFD_RELOC_UNUSED; | |
7219 | offset_expr.X_op = O_absent; | |
7220 | offset_reloc = BFD_RELOC_UNUSED; | |
7221 | for (args = insn->args; 1; ++args) | |
7222 | { | |
7223 | int c; | |
7224 | ||
7225 | if (*s == ' ') | |
7226 | ++s; | |
7227 | ||
7228 | /* In this switch statement we call break if we did not find | |
7229 | a match, continue if we did find a match, or return if we | |
7230 | are done. */ | |
7231 | ||
7232 | c = *args; | |
7233 | switch (c) | |
7234 | { | |
7235 | case '\0': | |
7236 | if (*s == '\0') | |
7237 | { | |
7238 | /* Stuff the immediate value in now, if we can. */ | |
7239 | if (imm_expr.X_op == O_constant | |
7240 | && imm_reloc > BFD_RELOC_UNUSED | |
7241 | && insn->pinfo != INSN_MACRO) | |
7242 | { | |
15e69f98 ILT |
7243 | mips16_immed ((char *) NULL, 0, |
7244 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7245 | imm_expr.X_add_number, true, mips16_small, |
7246 | mips16_ext, &ip->insn_opcode, | |
7247 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7248 | imm_expr.X_op = O_absent; |
7249 | imm_reloc = BFD_RELOC_UNUSED; | |
7250 | } | |
7251 | ||
7252 | return; | |
7253 | } | |
7254 | break; | |
7255 | ||
7256 | case ',': | |
7257 | if (*s++ == c) | |
7258 | continue; | |
7259 | s--; | |
7260 | switch (*++args) | |
7261 | { | |
7262 | case 'v': | |
7263 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7264 | continue; | |
7265 | case 'w': | |
7266 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7267 | continue; | |
7268 | } | |
7269 | break; | |
7270 | ||
7271 | case '(': | |
7272 | case ')': | |
7273 | if (*s++ == c) | |
7274 | continue; | |
7275 | break; | |
7276 | ||
7277 | case 'v': | |
7278 | case 'w': | |
7279 | if (s[0] != '$') | |
7280 | { | |
7281 | if (c == 'v') | |
7282 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7283 | else | |
7284 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7285 | ++args; | |
7286 | continue; | |
7287 | } | |
7288 | /* Fall through. */ | |
7289 | case 'x': | |
7290 | case 'y': | |
7291 | case 'z': | |
7292 | case 'Z': | |
7293 | case '0': | |
7294 | case 'S': | |
7295 | case 'R': | |
7296 | case 'X': | |
7297 | case 'Y': | |
7298 | if (s[0] != '$') | |
7299 | break; | |
7300 | s_reset = s; | |
7301 | if (isdigit (s[1])) | |
7302 | { | |
7303 | ++s; | |
7304 | regno = 0; | |
7305 | do | |
7306 | { | |
7307 | regno *= 10; | |
7308 | regno += *s - '0'; | |
7309 | ++s; | |
7310 | } | |
7311 | while (isdigit (*s)); | |
7312 | if (regno > 31) | |
7313 | { | |
7314 | as_bad ("invalid register number (%d)", regno); | |
7315 | regno = 2; | |
7316 | } | |
7317 | } | |
7318 | else | |
7319 | { | |
7320 | if (s[1] == 'f' && s[2] == 'p') | |
7321 | { | |
7322 | s += 3; | |
7323 | regno = FP; | |
7324 | } | |
7325 | else if (s[1] == 's' && s[2] == 'p') | |
7326 | { | |
7327 | s += 3; | |
7328 | regno = SP; | |
7329 | } | |
7330 | else if (s[1] == 'g' && s[2] == 'p') | |
7331 | { | |
7332 | s += 3; | |
7333 | regno = GP; | |
7334 | } | |
7335 | else if (s[1] == 'a' && s[2] == 't') | |
7336 | { | |
7337 | s += 3; | |
7338 | regno = AT; | |
7339 | } | |
7340 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7341 | { | |
7342 | s += 4; | |
7343 | regno = KT0; | |
7344 | } | |
7345 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7346 | { | |
7347 | s += 4; | |
7348 | regno = KT1; | |
7349 | } | |
7350 | else | |
7351 | break; | |
7352 | } | |
7353 | ||
7354 | if (*s == ' ') | |
7355 | ++s; | |
7356 | if (args[1] != *s) | |
7357 | { | |
7358 | if (c == 'v' || c == 'w') | |
7359 | { | |
7360 | regno = mips16_to_32_reg_map[lastregno]; | |
7361 | s = s_reset; | |
7362 | args++; | |
7363 | } | |
7364 | } | |
7365 | ||
7366 | switch (c) | |
7367 | { | |
7368 | case 'x': | |
7369 | case 'y': | |
7370 | case 'z': | |
7371 | case 'v': | |
7372 | case 'w': | |
7373 | case 'Z': | |
7374 | regno = mips32_to_16_reg_map[regno]; | |
7375 | break; | |
7376 | ||
7377 | case '0': | |
7378 | if (regno != 0) | |
7379 | regno = ILLEGAL_REG; | |
7380 | break; | |
7381 | ||
7382 | case 'S': | |
7383 | if (regno != SP) | |
7384 | regno = ILLEGAL_REG; | |
7385 | break; | |
7386 | ||
7387 | case 'R': | |
7388 | if (regno != RA) | |
7389 | regno = ILLEGAL_REG; | |
7390 | break; | |
7391 | ||
7392 | case 'X': | |
7393 | case 'Y': | |
7394 | if (regno == AT && ! mips_noat) | |
7395 | as_warn ("used $at without \".set noat\""); | |
7396 | break; | |
7397 | ||
7398 | default: | |
7399 | internalError (); | |
7400 | } | |
7401 | ||
7402 | if (regno == ILLEGAL_REG) | |
7403 | break; | |
7404 | ||
7405 | switch (c) | |
7406 | { | |
7407 | case 'x': | |
7408 | case 'v': | |
7409 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7410 | break; | |
7411 | case 'y': | |
7412 | case 'w': | |
7413 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7414 | break; | |
7415 | case 'z': | |
7416 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7417 | break; | |
7418 | case 'Z': | |
7419 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7420 | case '0': | |
7421 | case 'S': | |
7422 | case 'R': | |
7423 | break; | |
7424 | case 'X': | |
7425 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7426 | break; | |
7427 | case 'Y': | |
7428 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7429 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7430 | break; | |
7431 | default: | |
7432 | internalError (); | |
7433 | } | |
7434 | ||
7435 | lastregno = regno; | |
7436 | continue; | |
7437 | ||
7438 | case 'P': | |
7439 | if (strncmp (s, "$pc", 3) == 0) | |
7440 | { | |
7441 | s += 3; | |
7442 | continue; | |
7443 | } | |
7444 | break; | |
7445 | ||
7446 | case '<': | |
7447 | case '>': | |
7448 | case '[': | |
7449 | case ']': | |
7450 | case '4': | |
7451 | case '5': | |
7452 | case 'H': | |
7453 | case 'W': | |
7454 | case 'D': | |
7455 | case 'j': | |
7456 | case '8': | |
7457 | case 'V': | |
7458 | case 'C': | |
7459 | case 'U': | |
7460 | case 'k': | |
7461 | case 'K': | |
16262668 ILT |
7462 | if (s[0] == '%' |
7463 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7464 | { | |
7465 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7466 | and generate the appropriate reloc. If the text | |
7467 | inside %gprel is not a symbol name with an | |
7468 | optional offset, then we generate a normal reloc | |
7469 | and will probably fail later. */ | |
7470 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7471 | if (imm_expr.X_op == O_symbol) | |
7472 | { | |
7473 | mips16_ext = true; | |
7474 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7475 | s = expr_end; | |
7476 | ip->use_extend = true; | |
7477 | ip->extend = 0; | |
7478 | continue; | |
7479 | } | |
7480 | } | |
7481 | else | |
7482 | { | |
7483 | /* Just pick up a normal expression. */ | |
7484 | my_getExpression (&imm_expr, s); | |
7485 | } | |
7486 | ||
ebf28372 ILT |
7487 | if (imm_expr.X_op == O_register) |
7488 | { | |
7489 | /* What we thought was an expression turned out to | |
7490 | be a register. */ | |
7491 | ||
7492 | if (s[0] == '(' && args[1] == '(') | |
7493 | { | |
7494 | /* It looks like the expression was omitted | |
7495 | before a register indirection, which means | |
7496 | that the expression is implicitly zero. We | |
7497 | still set up imm_expr, so that we handle | |
7498 | explicit extensions correctly. */ | |
7499 | imm_expr.X_op = O_constant; | |
7500 | imm_expr.X_add_number = 0; | |
7501 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7502 | continue; | |
7503 | } | |
7504 | ||
7505 | break; | |
7506 | } | |
7507 | ||
cc5703cd ILT |
7508 | /* We need to relax this instruction. */ |
7509 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7510 | s = expr_end; | |
7511 | continue; | |
7512 | ||
7513 | case 'p': | |
7514 | case 'q': | |
7515 | case 'A': | |
7516 | case 'B': | |
7517 | case 'E': | |
7518 | /* We use offset_reloc rather than imm_reloc for the PC | |
7519 | relative operands. This lets macros with both | |
7520 | immediate and address operands work correctly. */ | |
670a50eb | 7521 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7522 | |
7523 | if (offset_expr.X_op == O_register) | |
7524 | break; | |
7525 | ||
cc5703cd ILT |
7526 | /* We need to relax this instruction. */ |
7527 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7528 | s = expr_end; |
7529 | continue; | |
7530 | ||
cc5703cd ILT |
7531 | case '6': /* break code */ |
7532 | my_getExpression (&imm_expr, s); | |
7533 | check_absolute_expr (ip, &imm_expr); | |
7534 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7535 | { |
cc5703cd ILT |
7536 | as_warn ("Invalid value for `%s' (%lu)", |
7537 | ip->insn_mo->name, | |
7538 | (unsigned long) imm_expr.X_add_number); | |
7539 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7540 | } |
cc5703cd ILT |
7541 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7542 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7543 | s = expr_end; |
7544 | continue; | |
3d3c5039 | 7545 | |
670a50eb ILT |
7546 | case 'a': /* 26 bit address */ |
7547 | my_getExpression (&offset_expr, s); | |
7548 | s = expr_end; | |
cc5703cd ILT |
7549 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7550 | ip->insn_opcode <<= 16; | |
670a50eb | 7551 | continue; |
3d3c5039 | 7552 | |
cc5703cd ILT |
7553 | case 'l': /* register list for entry macro */ |
7554 | case 'L': /* register list for exit macro */ | |
7555 | { | |
7556 | int mask; | |
7557 | ||
7558 | if (c == 'l') | |
7559 | mask = 0; | |
7560 | else | |
7561 | mask = 7 << 3; | |
7562 | while (*s != '\0') | |
7563 | { | |
c9167640 | 7564 | int freg, reg1, reg2; |
cc5703cd ILT |
7565 | |
7566 | while (*s == ' ' || *s == ',') | |
7567 | ++s; | |
7568 | if (*s != '$') | |
7569 | { | |
7570 | as_bad ("can't parse register list"); | |
7571 | break; | |
7572 | } | |
7573 | ++s; | |
c9167640 ILT |
7574 | if (*s != 'f') |
7575 | freg = 0; | |
7576 | else | |
7577 | { | |
7578 | freg = 1; | |
7579 | ++s; | |
7580 | } | |
cc5703cd ILT |
7581 | reg1 = 0; |
7582 | while (isdigit (*s)) | |
7583 | { | |
7584 | reg1 *= 10; | |
7585 | reg1 += *s - '0'; | |
7586 | ++s; | |
7587 | } | |
7588 | if (*s == ' ') | |
7589 | ++s; | |
7590 | if (*s != '-') | |
7591 | reg2 = reg1; | |
7592 | else | |
7593 | { | |
7594 | ++s; | |
7595 | if (*s != '$') | |
7596 | break; | |
7597 | ++s; | |
c9167640 ILT |
7598 | if (freg) |
7599 | { | |
7600 | if (*s == 'f') | |
7601 | ++s; | |
7602 | else | |
7603 | { | |
7604 | as_bad ("invalid register list"); | |
7605 | break; | |
7606 | } | |
7607 | } | |
cc5703cd ILT |
7608 | reg2 = 0; |
7609 | while (isdigit (*s)) | |
7610 | { | |
7611 | reg2 *= 10; | |
7612 | reg2 += *s - '0'; | |
7613 | ++s; | |
7614 | } | |
7615 | } | |
c9167640 ILT |
7616 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7617 | { | |
7618 | mask &= ~ (7 << 3); | |
7619 | mask |= 5 << 3; | |
7620 | } | |
7621 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7622 | { | |
7623 | mask &= ~ (7 << 3); | |
7624 | mask |= 6 << 3; | |
7625 | } | |
7626 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7627 | mask |= (reg2 - 3) << 3; |
7628 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7629 | mask |= (reg2 - 15) << 1; | |
7630 | else if (reg1 == 31 && reg2 == 31) | |
7631 | mask |= 1; | |
7632 | else | |
c9167640 ILT |
7633 | { |
7634 | as_bad ("invalid register list"); | |
7635 | break; | |
7636 | } | |
cc5703cd | 7637 | } |
c9167640 ILT |
7638 | /* The mask is filled in in the opcode table for the |
7639 | benefit of the disassembler. We remove it before | |
7640 | applying the actual mask. */ | |
7641 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7642 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7643 | } | |
7644 | continue; | |
d8a1c247 | 7645 | |
56bb6eee ILT |
7646 | case 'e': /* extend code */ |
7647 | my_getExpression (&imm_expr, s); | |
7648 | check_absolute_expr (ip, &imm_expr); | |
7649 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
7650 | { | |
7651 | as_warn ("Invalid value for `%s' (%lu)", | |
7652 | ip->insn_mo->name, | |
7653 | (unsigned long) imm_expr.X_add_number); | |
7654 | imm_expr.X_add_number &= 0x7ff; | |
7655 | } | |
7656 | ip->insn_opcode |= imm_expr.X_add_number; | |
7657 | imm_expr.X_op = O_absent; | |
7658 | s = expr_end; | |
7659 | continue; | |
7660 | ||
3d3c5039 | 7661 | default: |
670a50eb | 7662 | internalError (); |
3d3c5039 | 7663 | } |
670a50eb | 7664 | break; |
3d3c5039 | 7665 | } |
cc5703cd | 7666 | |
670a50eb | 7667 | /* Args don't match. */ |
cc5703cd ILT |
7668 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7669 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7670 | { |
7671 | ++insn; | |
cc5703cd | 7672 | s = argsstart; |
670a50eb | 7673 | continue; |
3d3c5039 | 7674 | } |
cc5703cd | 7675 | |
9753202d | 7676 | insn_error = "illegal operands"; |
cc5703cd | 7677 | |
670a50eb | 7678 | return; |
3d3c5039 ILT |
7679 | } |
7680 | } | |
7681 | ||
cc5703cd ILT |
7682 | /* This structure holds information we know about a mips16 immediate |
7683 | argument type. */ | |
7684 | ||
7685 | struct mips16_immed_operand | |
7686 | { | |
7687 | /* The type code used in the argument string in the opcode table. */ | |
7688 | int type; | |
7689 | /* The number of bits in the short form of the opcode. */ | |
7690 | int nbits; | |
7691 | /* The number of bits in the extended form of the opcode. */ | |
7692 | int extbits; | |
7693 | /* The amount by which the short form is shifted when it is used; | |
7694 | for example, the sw instruction has a shift count of 2. */ | |
7695 | int shift; | |
7696 | /* The amount by which the short form is shifted when it is stored | |
7697 | into the instruction code. */ | |
7698 | int op_shift; | |
7699 | /* Non-zero if the short form is unsigned. */ | |
7700 | int unsp; | |
7701 | /* Non-zero if the extended form is unsigned. */ | |
7702 | int extu; | |
7703 | /* Non-zero if the value is PC relative. */ | |
7704 | int pcrel; | |
7705 | }; | |
7706 | ||
7707 | /* The mips16 immediate operand types. */ | |
7708 | ||
7709 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7710 | { | |
7711 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7712 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7713 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7714 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7715 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7716 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7717 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7718 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7719 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7720 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7721 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7722 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7723 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7724 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7725 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7726 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7727 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7728 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7729 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7730 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7731 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7732 | }; | |
7733 | ||
7734 | #define MIPS16_NUM_IMMED \ | |
7735 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7736 | ||
7737 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7738 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7739 | whether an extended value is needed; if one is needed, it sets | |
7740 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7741 | If SMALL is true, an unextended opcode was explicitly requested. | |
7742 | If EXT is true, an extended opcode was explicitly requested. If | |
7743 | WARN is true, warn if EXT does not match reality. */ | |
7744 | ||
7745 | static void | |
15e69f98 ILT |
7746 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7747 | extend) | |
7748 | char *file; | |
7749 | unsigned int line; | |
cc5703cd ILT |
7750 | int type; |
7751 | offsetT val; | |
7752 | boolean warn; | |
7753 | boolean small; | |
7754 | boolean ext; | |
7755 | unsigned long *insn; | |
7756 | boolean *use_extend; | |
7757 | unsigned short *extend; | |
7758 | { | |
7759 | register const struct mips16_immed_operand *op; | |
7760 | int mintiny, maxtiny; | |
7761 | boolean needext; | |
7762 | ||
7763 | op = mips16_immed_operands; | |
7764 | while (op->type != type) | |
7765 | { | |
7766 | ++op; | |
7767 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7768 | } | |
7769 | ||
7770 | if (op->unsp) | |
7771 | { | |
7772 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7773 | { | |
7774 | mintiny = 1; | |
7775 | maxtiny = 1 << op->nbits; | |
7776 | } | |
7777 | else | |
7778 | { | |
7779 | mintiny = 0; | |
7780 | maxtiny = (1 << op->nbits) - 1; | |
7781 | } | |
7782 | } | |
7783 | else | |
7784 | { | |
7785 | mintiny = - (1 << (op->nbits - 1)); | |
7786 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7787 | } | |
7788 | ||
7789 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7790 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7791 | val /= 2; |
cc5703cd ILT |
7792 | |
7793 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7794 | || val < (mintiny << op->shift) | |
7795 | || val > (maxtiny << op->shift)) | |
7796 | needext = true; | |
7797 | else | |
7798 | needext = false; | |
7799 | ||
7800 | if (warn && ext && ! needext) | |
15e69f98 | 7801 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7802 | if (small && needext) |
15e69f98 | 7803 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7804 | |
7805 | if (small || (! ext && ! needext)) | |
7806 | { | |
7807 | int insnval; | |
7808 | ||
7809 | *use_extend = false; | |
7810 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7811 | insnval <<= op->op_shift; | |
7812 | *insn |= insnval; | |
7813 | } | |
7814 | else | |
7815 | { | |
7816 | long minext, maxext; | |
7817 | int extval; | |
7818 | ||
7819 | if (op->extu) | |
7820 | { | |
7821 | minext = 0; | |
7822 | maxext = (1 << op->extbits) - 1; | |
7823 | } | |
7824 | else | |
7825 | { | |
7826 | minext = - (1 << (op->extbits - 1)); | |
7827 | maxext = (1 << (op->extbits - 1)) - 1; | |
7828 | } | |
7829 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7830 | as_bad_where (file, line, |
7831 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7832 | |
7833 | *use_extend = true; | |
7834 | if (op->extbits == 16) | |
7835 | { | |
7836 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7837 | val &= 0x1f; | |
7838 | } | |
7839 | else if (op->extbits == 15) | |
7840 | { | |
7841 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7842 | val &= 0xf; | |
7843 | } | |
7844 | else | |
7845 | { | |
7846 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7847 | val = 0; | |
7848 | } | |
7849 | ||
7850 | *extend = (unsigned short) extval; | |
7851 | *insn |= val; | |
7852 | } | |
7853 | } | |
7854 | \f | |
3d3c5039 ILT |
7855 | #define LP '(' |
7856 | #define RP ')' | |
7857 | ||
7858 | static int | |
7859 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7860 | expressionS *ep; |
7861 | char *str; | |
3d3c5039 | 7862 | { |
670a50eb ILT |
7863 | char *sp; |
7864 | int c = 0; | |
7865 | ||
7866 | if (*str == ' ') | |
7867 | str++; | |
7868 | if (*str == LP | |
7869 | || (*str == '%' && | |
7870 | ((str[1] == 'h' && str[2] == 'i') | |
7871 | || (str[1] == 'H' && str[2] == 'I') | |
7872 | || (str[1] == 'l' && str[2] == 'o')) | |
7873 | && str[3] == LP)) | |
7874 | { | |
7875 | if (*str == LP) | |
7876 | c = 0; | |
7877 | else | |
7878 | { | |
7879 | c = str[1]; | |
7880 | str += 3; | |
7881 | } | |
7882 | ||
7883 | /* | |
7884 | * A small expression may be followed by a base register. | |
7885 | * Scan to the end of this operand, and then back over a possible | |
7886 | * base register. Then scan the small expression up to that | |
7887 | * point. (Based on code in sparc.c...) | |
7888 | */ | |
7889 | for (sp = str; *sp && *sp != ','; sp++) | |
7890 | ; | |
7891 | if (sp - 4 >= str && sp[-1] == RP) | |
7892 | { | |
7893 | if (isdigit (sp[-2])) | |
7894 | { | |
7895 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7896 | ; | |
7897 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7898 | { | |
7899 | sp--; | |
7900 | goto do_it; | |
3d3c5039 | 7901 | } |
670a50eb ILT |
7902 | } |
7903 | else if (sp - 5 >= str | |
7904 | && sp[-5] == LP | |
7905 | && sp[-4] == '$' | |
7906 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7907 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7908 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7909 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7910 | { | |
7911 | sp -= 5; | |
3d3c5039 | 7912 | do_it: |
670a50eb ILT |
7913 | if (sp == str) |
7914 | { | |
7915 | /* no expression means zero offset */ | |
7916 | if (c) | |
7917 | { | |
7918 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7919 | ep->X_op = O_absent; |
670a50eb | 7920 | expr_end = str - 3; |
3d3c5039 | 7921 | } |
670a50eb ILT |
7922 | else |
7923 | { | |
52aa70b5 | 7924 | ep->X_op = O_constant; |
670a50eb ILT |
7925 | expr_end = sp; |
7926 | } | |
7927 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7928 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7929 | ep->X_add_number = 0; |
7930 | } | |
7931 | else | |
7932 | { | |
7933 | *sp = '\0'; | |
7934 | my_getExpression (ep, str); | |
7935 | *sp = LP; | |
3d3c5039 | 7936 | } |
670a50eb | 7937 | return c; |
3d3c5039 ILT |
7938 | } |
7939 | } | |
7940 | } | |
670a50eb ILT |
7941 | my_getExpression (ep, str); |
7942 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7943 | } |
7944 | ||
7945 | static void | |
7946 | my_getExpression (ep, str) | |
670a50eb ILT |
7947 | expressionS *ep; |
7948 | char *str; | |
3d3c5039 | 7949 | { |
670a50eb | 7950 | char *save_in; |
670a50eb ILT |
7951 | |
7952 | save_in = input_line_pointer; | |
7953 | input_line_pointer = str; | |
5ac34ac3 | 7954 | expression (ep); |
670a50eb ILT |
7955 | expr_end = input_line_pointer; |
7956 | input_line_pointer = save_in; | |
eb17f56c ILT |
7957 | |
7958 | /* If we are in mips16 mode, and this is an expression based on `.', | |
7959 | then we bump the value of the symbol by 1 since that is how other | |
7960 | text symbols are handled. We don't bother to handle complex | |
7961 | expressions, just `.' plus or minus a constant. */ | |
7962 | if (mips16 | |
7963 | && ep->X_op == O_symbol | |
7964 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
7965 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
7966 | && ep->X_add_symbol->sy_frag == frag_now | |
7967 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
7968 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
7969 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
7970 | } |
7971 | ||
becfe05e ILT |
7972 | /* Turn a string in input_line_pointer into a floating point constant |
7973 | of type type, and store the appropriate bytes in *litP. The number | |
7974 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7975 | returned, or NULL on OK. */ | |
7976 | ||
3d3c5039 | 7977 | char * |
670a50eb | 7978 | md_atof (type, litP, sizeP) |
becfe05e | 7979 | int type; |
3d3c5039 ILT |
7980 | char *litP; |
7981 | int *sizeP; | |
7982 | { | |
becfe05e ILT |
7983 | int prec; |
7984 | LITTLENUM_TYPE words[4]; | |
7985 | char *t; | |
7986 | int i; | |
7987 | ||
7988 | switch (type) | |
7989 | { | |
7990 | case 'f': | |
7991 | prec = 2; | |
7992 | break; | |
7993 | ||
7994 | case 'd': | |
7995 | prec = 4; | |
7996 | break; | |
7997 | ||
7998 | default: | |
7999 | *sizeP = 0; | |
8000 | return "bad call to md_atof"; | |
8001 | } | |
8002 | ||
8003 | t = atof_ieee (input_line_pointer, type, words); | |
8004 | if (t) | |
8005 | input_line_pointer = t; | |
8006 | ||
8007 | *sizeP = prec * 2; | |
8008 | ||
b9129c6f | 8009 | if (! target_big_endian) |
becfe05e ILT |
8010 | { |
8011 | for (i = prec - 1; i >= 0; i--) | |
8012 | { | |
8013 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8014 | litP += 2; | |
8015 | } | |
8016 | } | |
8017 | else | |
8018 | { | |
8019 | for (i = 0; i < prec; i++) | |
8020 | { | |
8021 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8022 | litP += 2; | |
8023 | } | |
8024 | } | |
8025 | ||
670a50eb | 8026 | return NULL; |
3d3c5039 ILT |
8027 | } |
8028 | ||
8029 | void | |
8030 | md_number_to_chars (buf, val, n) | |
8031 | char *buf; | |
918692a5 | 8032 | valueT val; |
3d3c5039 ILT |
8033 | int n; |
8034 | { | |
b9129c6f ILT |
8035 | if (target_big_endian) |
8036 | number_to_chars_bigendian (buf, val, n); | |
8037 | else | |
8038 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8039 | } |
f3d817d8 | 8040 | \f |
e8d4d475 | 8041 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8042 | |
f3d817d8 DM |
8043 | struct option md_longopts[] = { |
8044 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8045 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8046 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8047 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8048 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8049 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8050 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8051 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8052 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8053 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8054 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8055 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8056 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8057 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8058 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8059 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8060 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8061 | {"break", no_argument, NULL, OPTION_BREAK}, |
8062 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8063 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8064 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8065 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8066 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8067 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8068 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8069 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8070 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8071 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8072 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8073 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8074 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8075 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8076 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8077 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8078 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8079 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8080 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8081 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8082 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8083 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8084 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8085 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8086 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8087 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8088 | /* end-sanitize-r5900 */ |
f3d817d8 | 8089 | |
d8a1c247 | 8090 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8091 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8092 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8093 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8094 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8095 | #ifdef OBJ_ELF |
f3d817d8 | 8096 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8097 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8098 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8099 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8100 | {"32", no_argument, NULL, OPTION_32}, |
8101 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8102 | #endif |
8103 | ||
8104 | {NULL, no_argument, NULL, 0} | |
8105 | }; | |
8106 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8107 | |
8108 | int | |
f3d817d8 DM |
8109 | md_parse_option (c, arg) |
8110 | int c; | |
8111 | char *arg; | |
3d3c5039 | 8112 | { |
f3d817d8 | 8113 | switch (c) |
670a50eb | 8114 | { |
f3d817d8 DM |
8115 | case OPTION_TRAP: |
8116 | mips_trap = 1; | |
8117 | break; | |
670a50eb | 8118 | |
f3d817d8 DM |
8119 | case OPTION_BREAK: |
8120 | mips_trap = 0; | |
8121 | break; | |
8122 | ||
e8d4d475 | 8123 | case OPTION_EB: |
1dc1e798 | 8124 | target_big_endian = 1; |
e8d4d475 | 8125 | break; |
04cb3372 | 8126 | |
e8d4d475 | 8127 | case OPTION_EL: |
1dc1e798 | 8128 | target_big_endian = 0; |
f3d817d8 | 8129 | break; |
670a50eb | 8130 | |
f3d817d8 DM |
8131 | case 'O': |
8132 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8133 | mips_optimize = 1; |
8134 | else | |
8135 | mips_optimize = 2; | |
f3d817d8 | 8136 | break; |
0aa07269 | 8137 | |
f3d817d8 | 8138 | case 'g': |
22ba90ce ILT |
8139 | if (arg == NULL) |
8140 | mips_debug = 2; | |
8141 | else | |
8142 | mips_debug = atoi (arg); | |
8143 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8144 | optimizations which limit full symbolic debugging. We take | |
8145 | that to be equivalent to -O0. */ | |
8146 | if (mips_debug == 2) | |
05874c2e | 8147 | mips_optimize = 1; |
f3d817d8 | 8148 | break; |
4e95866e | 8149 | |
f3d817d8 DM |
8150 | case OPTION_MIPS1: |
8151 | mips_isa = 1; | |
4bb0cc41 ILT |
8152 | if (mips_cpu == -1) |
8153 | mips_cpu = 3000; | |
f3d817d8 | 8154 | break; |
8358c818 | 8155 | |
f3d817d8 DM |
8156 | case OPTION_MIPS2: |
8157 | mips_isa = 2; | |
4bb0cc41 ILT |
8158 | if (mips_cpu == -1) |
8159 | mips_cpu = 6000; | |
f3d817d8 | 8160 | break; |
8358c818 | 8161 | |
f3d817d8 DM |
8162 | case OPTION_MIPS3: |
8163 | mips_isa = 3; | |
4bb0cc41 ILT |
8164 | if (mips_cpu == -1) |
8165 | mips_cpu = 4000; | |
f3d817d8 | 8166 | break; |
8358c818 | 8167 | |
d8a1c247 KR |
8168 | case OPTION_MIPS4: |
8169 | mips_isa = 4; | |
8170 | if (mips_cpu == -1) | |
8171 | mips_cpu = 8000; | |
8172 | break; | |
8173 | ||
f3d817d8 DM |
8174 | case OPTION_MCPU: |
8175 | { | |
8176 | char *p; | |
8177 | ||
8178 | /* Identify the processor type */ | |
8179 | p = arg; | |
8180 | if (strcmp (p, "default") == 0 | |
8181 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8182 | mips_cpu = -1; |
f3d817d8 DM |
8183 | else |
8184 | { | |
c625fc23 JSC |
8185 | int sv = 0; |
8186 | ||
8187 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8188 | processor. */ | |
8189 | if (*p == 'v' || *p == 'V') | |
8190 | { | |
8191 | sv = 1; | |
8192 | p++; | |
8193 | } | |
8194 | ||
f3d817d8 DM |
8195 | if (*p == 'r' || *p == 'R') |
8196 | p++; | |
8358c818 | 8197 | |
4bb0cc41 | 8198 | mips_cpu = -1; |
f3d817d8 DM |
8199 | switch (*p) |
8200 | { | |
d8a1c247 KR |
8201 | case '1': |
8202 | if (strcmp (p, "10000") == 0 | |
8203 | || strcmp (p, "10k") == 0 | |
8204 | || strcmp (p, "10K") == 0) | |
8205 | mips_cpu = 10000; | |
8206 | break; | |
8207 | ||
f3d817d8 DM |
8208 | case '2': |
8209 | if (strcmp (p, "2000") == 0 | |
8210 | || strcmp (p, "2k") == 0 | |
8211 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8212 | mips_cpu = 2000; |
f3d817d8 | 8213 | break; |
8358c818 | 8214 | |
f3d817d8 DM |
8215 | case '3': |
8216 | if (strcmp (p, "3000") == 0 | |
8217 | || strcmp (p, "3k") == 0 | |
8218 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8219 | mips_cpu = 3000; |
f3d817d8 | 8220 | break; |
8358c818 | 8221 | |
f3d817d8 DM |
8222 | case '4': |
8223 | if (strcmp (p, "4000") == 0 | |
8224 | || strcmp (p, "4k") == 0 | |
8c63448a | 8225 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8226 | mips_cpu = 4000; |
c625fc23 JSC |
8227 | else if (strcmp (p, "4100") == 0) |
8228 | { | |
8229 | mips_cpu = 4100; | |
8230 | if (mips_4100 < 0) | |
8231 | mips_4100 = 1; | |
8232 | } | |
8233 | else if (strcmp (p, "4300") == 0) | |
8234 | mips_cpu = 4300; | |
8c63448a | 8235 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8236 | mips_cpu = 4400; |
8c63448a | 8237 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8238 | mips_cpu = 4600; |
b2b8c24e ILT |
8239 | else if (strcmp (p, "4650") == 0) |
8240 | { | |
8241 | mips_cpu = 4650; | |
8242 | if (mips_4650 < 0) | |
8243 | mips_4650 = 1; | |
8244 | } | |
e532b44c ILT |
8245 | else if (strcmp (p, "4010") == 0) |
8246 | { | |
8247 | mips_cpu = 4010; | |
8248 | if (mips_4010 < 0) | |
8249 | mips_4010 = 1; | |
8250 | } | |
f3d817d8 | 8251 | break; |
8358c818 | 8252 | |
517078c1 ILT |
8253 | case '5': |
8254 | if (strcmp (p, "5000") == 0 | |
8255 | || strcmp (p, "5k") == 0 | |
8256 | || strcmp (p, "5K") == 0) | |
8257 | mips_cpu = 5000; | |
276c2d7d GRK |
8258 | /* start-sanitize-r5900 */ |
8259 | else if (strcmp (p, "5900") == 0) | |
8260 | mips_cpu = 5900; | |
8261 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8262 | break; |
8263 | ||
f3d817d8 DM |
8264 | case '6': |
8265 | if (strcmp (p, "6000") == 0 | |
8266 | || strcmp (p, "6k") == 0 | |
8267 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8268 | mips_cpu = 6000; |
f3d817d8 | 8269 | break; |
55933a58 | 8270 | |
d8a1c247 KR |
8271 | case '8': |
8272 | if (strcmp (p, "8000") == 0 | |
8273 | || strcmp (p, "8k") == 0 | |
8274 | || strcmp (p, "8K") == 0) | |
8275 | mips_cpu = 8000; | |
8276 | break; | |
8277 | ||
55933a58 ILT |
8278 | case 'o': |
8279 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8280 | mips_cpu = 4600; |
55933a58 | 8281 | break; |
f3d817d8 | 8282 | } |
8358c818 | 8283 | |
517078c1 | 8284 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8285 | { |
8286 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8287 | return 0; | |
8288 | } | |
8289 | ||
4bb0cc41 | 8290 | if (mips_cpu == -1) |
f3d817d8 DM |
8291 | { |
8292 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8293 | return 0; | |
8294 | } | |
8295 | } | |
8296 | } | |
8297 | break; | |
8358c818 | 8298 | |
b2b8c24e ILT |
8299 | case OPTION_M4650: |
8300 | mips_4650 = 1; | |
8301 | break; | |
8302 | ||
8303 | case OPTION_NO_M4650: | |
8304 | mips_4650 = 0; | |
8305 | break; | |
8306 | ||
e532b44c ILT |
8307 | case OPTION_M4010: |
8308 | mips_4010 = 1; | |
8309 | break; | |
8310 | ||
8311 | case OPTION_NO_M4010: | |
8312 | mips_4010 = 0; | |
8313 | break; | |
8314 | ||
c625fc23 JSC |
8315 | case OPTION_M4100: |
8316 | mips_4100 = 1; | |
8317 | break; | |
8318 | ||
8319 | case OPTION_NO_M4100: | |
8320 | mips_4100 = 0; | |
8321 | break; | |
8322 | ||
276c2d7d GRK |
8323 | /* start-sanitize-r5900 */ |
8324 | case OPTION_M5900: | |
8325 | mips_5900 = 1; | |
8326 | break; | |
8327 | ||
8328 | case OPTION_NO_M5900: | |
8329 | mips_5900 = 0; | |
8330 | break; | |
8331 | /* end-sanitize-r5900 */ | |
8332 | ||
cc5703cd ILT |
8333 | case OPTION_MIPS16: |
8334 | mips16 = 1; | |
4a1cb507 | 8335 | mips_no_prev_insn (false); |
cc5703cd ILT |
8336 | break; |
8337 | ||
8338 | case OPTION_NO_MIPS16: | |
8339 | mips16 = 0; | |
4a1cb507 | 8340 | mips_no_prev_insn (false); |
cc5703cd ILT |
8341 | break; |
8342 | ||
f3d817d8 | 8343 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8344 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8345 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8346 | { |
8347 | as_bad ("-G may not be used with embedded PIC code"); | |
8348 | return 0; | |
8349 | } | |
5b63f465 | 8350 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8351 | break; |
d9aba805 | 8352 | |
fb251650 ILT |
8353 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8354 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8355 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8356 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8357 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8358 | { | |
8359 | as_bad ("-call_shared is supported only for ELF format"); | |
8360 | return 0; | |
8361 | } | |
d9aba805 ILT |
8362 | mips_pic = SVR4_PIC; |
8363 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8364 | { |
8365 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8366 | return 0; | |
8367 | } | |
d9aba805 | 8368 | g_switch_value = 0; |
f3d817d8 DM |
8369 | break; |
8370 | ||
8371 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8372 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8373 | { | |
8374 | as_bad ("-non_shared is supported only for ELF format"); | |
8375 | return 0; | |
8376 | } | |
d9aba805 | 8377 | mips_pic = NO_PIC; |
f3d817d8 | 8378 | break; |
8358c818 | 8379 | |
fb251650 ILT |
8380 | /* The -xgot option tells the assembler to use 32 offsets when |
8381 | accessing the got in SVR4_PIC mode. It is for Irix | |
8382 | compatibility. */ | |
8383 | case OPTION_XGOT: | |
8384 | mips_big_got = 1; | |
8385 | break; | |
8386 | ||
f3d817d8 | 8387 | case 'G': |
1dc1e798 KR |
8388 | if (! USE_GLOBAL_POINTER_OPT) |
8389 | { | |
8390 | as_bad ("-G is not supported for this configuration"); | |
8391 | return 0; | |
8392 | } | |
8393 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8394 | { |
f3d817d8 DM |
8395 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8396 | return 0; | |
670a50eb ILT |
8397 | } |
8398 | else | |
f3d817d8 | 8399 | g_switch_value = atoi (arg); |
42562568 | 8400 | g_switch_seen = 1; |
f3d817d8 | 8401 | break; |
4e95866e | 8402 | |
7f9880e5 ILT |
8403 | /* The -32 and -64 options tell the assembler to output the 32 |
8404 | bit or the 64 bit MIPS ELF format. */ | |
8405 | case OPTION_32: | |
8406 | mips_64 = 0; | |
8407 | break; | |
8408 | ||
8409 | case OPTION_64: | |
9c44af60 ILT |
8410 | { |
8411 | const char **list, **l; | |
8412 | ||
8413 | list = bfd_target_list (); | |
8414 | for (l = list; *l != NULL; l++) | |
8415 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8416 | || strcmp (*l, "elf64-littlemips") == 0) | |
8417 | break; | |
8418 | if (*l == NULL) | |
8419 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8420 | free (list); | |
8421 | mips_64 = 1; | |
8422 | } | |
7f9880e5 ILT |
8423 | break; |
8424 | ||
f3d817d8 DM |
8425 | default: |
8426 | return 0; | |
8ea7f4e8 ILT |
8427 | } |
8428 | ||
f3d817d8 | 8429 | return 1; |
8ea7f4e8 ILT |
8430 | } |
8431 | ||
f3d817d8 DM |
8432 | void |
8433 | md_show_usage (stream) | |
8434 | FILE *stream; | |
8435 | { | |
8436 | fprintf(stream, "\ | |
8437 | MIPS options:\n\ | |
8438 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8439 | -EB generate big endian output\n\ |
8440 | -EL generate little endian output\n\ | |
8441 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8442 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8443 | implicitly with the gp register [default 8]\n"); |
8444 | fprintf(stream, "\ | |
f3d817d8 DM |
8445 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8446 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8447 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8448 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8449 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8450 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8451 | -m4650 permit R4650 instructions\n\ |
8452 | -no-m4650 do not permit R4650 instructions\n\ | |
8453 | -m4010 permit R4010 instructions\n\ | |
8454 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8455 | -m4100 permit VR4100 instructions\n\ |
8456 | -no-m4100 do not permit VR4100 instructions\n"); | |
8457 | fprintf(stream, "\ | |
cc5703cd ILT |
8458 | -mips16 generate mips16 instructions\n\ |
8459 | -no-mips16 do not generate mips16 instructions\n"); | |
8460 | fprintf(stream, "\ | |
f3d817d8 DM |
8461 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8462 | -O remove unneeded NOPs and swap branches\n\ | |
8463 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8464 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8465 | #ifdef OBJ_ELF | |
8466 | fprintf(stream, "\ | |
8467 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8468 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8469 | -xgot assume a 32 bit GOT\n\ |
8470 | -32 create 32 bit object file (default)\n\ | |
8471 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8472 | #endif |
8473 | } | |
8474 | \f | |
efec4a28 DP |
8475 | void |
8476 | mips_init_after_args () | |
8477 | { | |
af942793 SS |
8478 | /* initialize opcodes */ |
8479 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
8480 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
8481 | } |
8482 | ||
3d3c5039 ILT |
8483 | long |
8484 | md_pcrel_from (fixP) | |
8485 | fixS *fixP; | |
8486 | { | |
1dc1e798 KR |
8487 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8488 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8489 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8490 | { | |
8491 | /* This makes a branch to an undefined symbol be a branch to the | |
8492 | current location. */ | |
8493 | return 4; | |
8494 | } | |
5b63f465 | 8495 | |
670a50eb ILT |
8496 | /* return the address of the delay slot */ |
8497 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8498 | } |
8499 | ||
abdad6bc ILT |
8500 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8501 | reloc for a cons. We could use the definition there, except that | |
8502 | we want to handle 64 bit relocs specially. */ | |
8503 | ||
8504 | void | |
8505 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8506 | fragS *frag; | |
8507 | int where; | |
8508 | unsigned int nbytes; | |
8509 | expressionS *exp; | |
8510 | { | |
bf39474f | 8511 | #ifndef OBJ_ELF |
abdad6bc | 8512 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8513 | 4 byte reloc. */ |
8514 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8515 | { |
b9129c6f | 8516 | if (target_big_endian) |
abdad6bc ILT |
8517 | where += 4; |
8518 | nbytes = 4; | |
8519 | } | |
bf39474f | 8520 | #endif |
abdad6bc | 8521 | |
7f9880e5 | 8522 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8523 | as_bad ("Unsupported reloc size %d", nbytes); |
8524 | ||
8525 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8526 | (nbytes == 2 |
8527 | ? BFD_RELOC_16 | |
8528 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8529 | } |
8530 | ||
23604921 ILT |
8531 | /* This is called before the symbol table is processed. In order to |
8532 | work with gcc when using mips-tfile, we must keep all local labels. | |
8533 | However, in other cases, we want to discard them. If we were | |
8534 | called with -g, but we didn't see any debugging information, it may | |
8535 | mean that gcc is smuggling debugging information through to | |
8536 | mips-tfile, in which case we must generate all local labels. */ | |
8537 | ||
8538 | void | |
8539 | mips_frob_file_before_adjust () | |
8540 | { | |
8541 | #ifndef NO_ECOFF_DEBUGGING | |
8542 | if (ECOFF_DEBUGGING | |
8543 | && mips_debug != 0 | |
8544 | && ! ecoff_debugging_seen) | |
8545 | flag_keep_locals = 1; | |
8546 | #endif | |
8547 | } | |
8548 | ||
867a58b3 ILT |
8549 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8550 | the corresponding LO reloc. This is called before md_apply_fix and | |
8551 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8552 | explicit use of the %hi modifier. */ | |
8553 | ||
8554 | void | |
8555 | mips_frob_file () | |
8556 | { | |
8557 | struct mips_hi_fixup *l; | |
8558 | ||
8559 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8560 | { | |
8561 | segment_info_type *seginfo; | |
9b61d62b | 8562 | int pass; |
867a58b3 ILT |
8563 | |
8564 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8565 | ||
8566 | /* Check quickly whether the next fixup happens to be a matching | |
8567 | %lo. */ | |
8568 | if (l->fixp->fx_next != NULL | |
8569 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8570 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8571 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8572 | continue; | |
8573 | ||
8574 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8575 | When we find one, move the %hi just in front of it. We do |
8576 | this in two passes. In the first pass, we try to find a | |
8577 | unique %lo. In the second pass, we permit multiple %hi | |
8578 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8579 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8580 | for (pass = 0; pass < 2; pass++) |
8581 | { | |
8582 | fixS *f, *prev; | |
8583 | ||
8584 | prev = NULL; | |
8585 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8586 | { |
9b61d62b ILT |
8587 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8588 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8589 | && f->fx_addsy == l->fixp->fx_addsy | |
8590 | && f->fx_offset == l->fixp->fx_offset | |
8591 | && (pass == 1 | |
8592 | || prev == NULL | |
8593 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8594 | || prev->fx_addsy != f->fx_addsy | |
8595 | || prev->fx_offset != f->fx_offset)) | |
8596 | { | |
8597 | fixS **pf; | |
867a58b3 | 8598 | |
9b61d62b ILT |
8599 | /* Move l->fixp before f. */ |
8600 | for (pf = &seginfo->fix_root; | |
8601 | *pf != l->fixp; | |
8602 | pf = &(*pf)->fx_next) | |
8603 | assert (*pf != NULL); | |
867a58b3 | 8604 | |
9b61d62b | 8605 | *pf = l->fixp->fx_next; |
867a58b3 | 8606 | |
9b61d62b ILT |
8607 | l->fixp->fx_next = f; |
8608 | if (prev == NULL) | |
8609 | seginfo->fix_root = l->fixp; | |
8610 | else | |
8611 | prev->fx_next = l->fixp; | |
867a58b3 | 8612 | |
9b61d62b ILT |
8613 | break; |
8614 | } | |
8615 | ||
8616 | prev = f; | |
867a58b3 ILT |
8617 | } |
8618 | ||
9b61d62b ILT |
8619 | if (f != NULL) |
8620 | break; | |
867a58b3 | 8621 | |
9b61d62b ILT |
8622 | if (pass == 1) |
8623 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8624 | "Unmatched %%hi reloc"); | |
8625 | } | |
867a58b3 ILT |
8626 | } |
8627 | } | |
8628 | ||
1c803e52 ILT |
8629 | /* When generating embedded PIC code we need to use a special |
8630 | relocation to represent the difference of two symbols in the .text | |
8631 | section (switch tables use a difference of this sort). See | |
8632 | include/coff/mips.h for details. This macro checks whether this | |
8633 | fixup requires the special reloc. */ | |
8634 | #define SWITCH_TABLE(fixp) \ | |
8635 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8636 | && (fixp)->fx_addsy != NULL \ | |
8637 | && (fixp)->fx_subsy != NULL \ | |
8638 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8639 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8640 | ||
5b63f465 | 8641 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8642 | relocations, in case the linker has to relax a call. We also need |
8643 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8644 | |
8645 | /*ARGSUSED*/ | |
8646 | int | |
8647 | mips_force_relocation (fixp) | |
8648 | fixS *fixp; | |
8649 | { | |
1c803e52 | 8650 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8651 | && (fixp->fx_pcrel |
8652 | || SWITCH_TABLE (fixp) | |
8653 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8654 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8655 | } |
8656 | ||
8657 | /* Apply a fixup to the object file. */ | |
8658 | ||
3d3c5039 ILT |
8659 | int |
8660 | md_apply_fix (fixP, valueP) | |
8661 | fixS *fixP; | |
918692a5 | 8662 | valueT *valueP; |
3d3c5039 | 8663 | { |
670a50eb ILT |
8664 | unsigned char *buf; |
8665 | long insn, value; | |
3d3c5039 | 8666 | |
bf39474f ILT |
8667 | assert (fixP->fx_size == 4 |
8668 | || fixP->fx_r_type == BFD_RELOC_16 | |
8669 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8670 | |
670a50eb | 8671 | value = *valueP; |
1748b9d8 ILT |
8672 | |
8673 | /* If we aren't adjusting this fixup to be against the section | |
8674 | symbol, we need to adjust the value. */ | |
8675 | #ifdef S_GET_OTHER | |
8676 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8677 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8678 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8679 | { | |
8680 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8681 | if (value != 0 && ! fixP->fx_pcrel) | |
8682 | { | |
8683 | /* In this case, the bfd_install_relocation routine will | |
8684 | incorrectly add the symbol value back in. We just want | |
8685 | the addend to appear in the object file. */ | |
8686 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8687 | } | |
8688 | } | |
8689 | #endif | |
8690 | ||
670a50eb | 8691 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8692 | |
5b63f465 ILT |
8693 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8694 | fixP->fx_done = 1; | |
8695 | ||
670a50eb ILT |
8696 | switch (fixP->fx_r_type) |
8697 | { | |
3d3c5039 ILT |
8698 | case BFD_RELOC_MIPS_JMP: |
8699 | case BFD_RELOC_HI16: | |
8700 | case BFD_RELOC_HI16_S: | |
670a50eb | 8701 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8702 | case BFD_RELOC_MIPS_LITERAL: |
8703 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8704 | case BFD_RELOC_MIPS_GOT16: |
8705 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8706 | case BFD_RELOC_MIPS_GOT_HI16: |
8707 | case BFD_RELOC_MIPS_GOT_LO16: | |
8708 | case BFD_RELOC_MIPS_CALL_HI16: | |
8709 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8710 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8711 | if (fixP->fx_pcrel) |
7b777690 ILT |
8712 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8713 | "Invalid PC relative reloc"); | |
670a50eb | 8714 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8715 | break; |
3d3c5039 | 8716 | |
cc5703cd ILT |
8717 | case BFD_RELOC_MIPS16_JMP: |
8718 | /* We currently always generate a reloc against a symbol, which | |
8719 | means that we don't want an addend even if the symbol is | |
8720 | defined. */ | |
8721 | fixP->fx_addnumber = 0; | |
8722 | break; | |
8723 | ||
ecd4ca1c ILT |
8724 | case BFD_RELOC_PCREL_HI16_S: |
8725 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8726 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8727 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8728 | { | |
8729 | /* For an external symbol adjust by the address to make it | |
8730 | pcrel_offset. We use the address of the RELLO reloc | |
8731 | which follows this one. */ | |
8732 | value += (fixP->fx_next->fx_frag->fr_address | |
8733 | + fixP->fx_next->fx_where); | |
8734 | } | |
8735 | if (value & 0x8000) | |
8736 | value += 0x10000; | |
8737 | value >>= 16; | |
0221ddf7 | 8738 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8739 | if (target_big_endian) |
ecd4ca1c ILT |
8740 | buf += 2; |
8741 | md_number_to_chars (buf, value, 2); | |
8742 | break; | |
8743 | ||
8744 | case BFD_RELOC_PCREL_LO16: | |
8745 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8746 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8747 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8748 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8749 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8750 | if (target_big_endian) |
ecd4ca1c ILT |
8751 | buf += 2; |
8752 | md_number_to_chars (buf, value, 2); | |
8753 | break; | |
8754 | ||
bf39474f ILT |
8755 | case BFD_RELOC_64: |
8756 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8757 | extended value if we are only 32 bits. */ | |
8758 | if (fixP->fx_done | |
8759 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8760 | { | |
8761 | if (8 <= sizeof (valueT)) | |
8762 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8763 | value, 8); | |
8764 | else | |
8765 | { | |
8766 | long w1, w2; | |
8767 | long hiv; | |
8768 | ||
8769 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8770 | if (target_big_endian) |
bf39474f ILT |
8771 | w1 += 4; |
8772 | else | |
8773 | w2 += 4; | |
8774 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8775 | if ((value & 0x80000000) != 0) | |
8776 | hiv = 0xffffffff; | |
8777 | else | |
8778 | hiv = 0; | |
8779 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8780 | } | |
8781 | } | |
8782 | break; | |
8783 | ||
f3645945 ILT |
8784 | case BFD_RELOC_32: |
8785 | /* If we are deleting this reloc entry, we must fill in the | |
8786 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8787 | resolved when it appears but is later defined. We also need |
8788 | to fill in the value if this is an embedded PIC switch table | |
8789 | entry. */ | |
8790 | if (fixP->fx_done | |
8791 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8792 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8793 | value, 4); | |
8794 | break; | |
8795 | ||
49ad0c4c ILT |
8796 | case BFD_RELOC_16: |
8797 | /* If we are deleting this reloc entry, we must fill in the | |
8798 | value now. */ | |
8799 | assert (fixP->fx_size == 2); | |
8800 | if (fixP->fx_done) | |
8801 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8802 | value, 2); | |
8803 | break; | |
8804 | ||
f3645945 ILT |
8805 | case BFD_RELOC_LO16: |
8806 | /* When handling an embedded PIC switch statement, we can wind | |
8807 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8808 | if (fixP->fx_done) | |
8809 | { | |
8810 | if (value < -0x8000 || value > 0x7fff) | |
8811 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8812 | "relocation overflow"); | |
0221ddf7 | 8813 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8814 | if (target_big_endian) |
f3645945 ILT |
8815 | buf += 2; |
8816 | md_number_to_chars (buf, value, 2); | |
8817 | } | |
8818 | break; | |
8819 | ||
3d3c5039 | 8820 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8821 | /* |
8822 | * We need to save the bits in the instruction since fixup_segment() | |
8823 | * might be deleting the relocation entry (i.e., a branch within | |
8824 | * the current segment). | |
8825 | */ | |
fbcfacb7 | 8826 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8827 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8828 | "Branch to odd address (%lx)", value); | |
670a50eb | 8829 | value >>= 2; |
670a50eb ILT |
8830 | |
8831 | /* update old instruction data */ | |
8832 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8833 | if (target_big_endian) |
8834 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8835 | else | |
8836 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8837 | |
8838 | if (value >= -0x8000 && value < 0x8000) | |
8839 | insn |= value & 0xffff; | |
8840 | else | |
8841 | { | |
8842 | /* The branch offset is too large. If this is an | |
8843 | unconditional branch, and we are not generating PIC code, | |
8844 | we can convert it to an absolute jump instruction. */ | |
8845 | if (mips_pic == NO_PIC | |
8846 | && fixP->fx_done | |
8847 | && fixP->fx_frag->fr_address >= text_section->vma | |
8848 | && (fixP->fx_frag->fr_address | |
8849 | < text_section->vma + text_section->_raw_size) | |
8850 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8851 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8852 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8853 | { | |
8854 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8855 | insn = 0x0c000000; /* jal */ | |
8856 | else | |
8857 | insn = 0x08000000; /* j */ | |
8858 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8859 | fixP->fx_done = 0; | |
8860 | fixP->fx_addsy = section_symbol (text_section); | |
8861 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8862 | } | |
8863 | else | |
8864 | { | |
8865 | /* FIXME. It would be possible in principle to handle | |
8866 | conditional branches which overflow. They could be | |
8867 | transformed into a branch around a jump. This would | |
8868 | require setting up variant frags for each different | |
8869 | branch type. The native MIPS assembler attempts to | |
8870 | handle these cases, but it appears to do it | |
8871 | incorrectly. */ | |
8872 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 8873 | "Branch out of range"); |
9da4c5d1 ILT |
8874 | } |
8875 | } | |
8876 | ||
604633ae | 8877 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8878 | break; |
3d3c5039 ILT |
8879 | |
8880 | default: | |
670a50eb | 8881 | internalError (); |
3d3c5039 | 8882 | } |
5b63f465 | 8883 | |
670a50eb | 8884 | return 1; |
3d3c5039 ILT |
8885 | } |
8886 | ||
8887 | #if 0 | |
8888 | void | |
670a50eb ILT |
8889 | printInsn (oc) |
8890 | unsigned long oc; | |
3d3c5039 | 8891 | { |
670a50eb ILT |
8892 | const struct mips_opcode *p; |
8893 | int treg, sreg, dreg, shamt; | |
8894 | short imm; | |
8895 | const char *args; | |
8896 | int i; | |
3d3c5039 | 8897 | |
670a50eb ILT |
8898 | for (i = 0; i < NUMOPCODES; ++i) |
8899 | { | |
8900 | p = &mips_opcodes[i]; | |
8901 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8902 | { | |
8903 | printf ("%08lx %s\t", oc, p->name); | |
8904 | treg = (oc >> 16) & 0x1f; | |
8905 | sreg = (oc >> 21) & 0x1f; | |
8906 | dreg = (oc >> 11) & 0x1f; | |
8907 | shamt = (oc >> 6) & 0x1f; | |
8908 | imm = oc; | |
8909 | for (args = p->args;; ++args) | |
8910 | { | |
8911 | switch (*args) | |
8912 | { | |
3d3c5039 | 8913 | case '\0': |
670a50eb ILT |
8914 | printf ("\n"); |
8915 | break; | |
3d3c5039 ILT |
8916 | |
8917 | case ',': | |
8918 | case '(': | |
8919 | case ')': | |
670a50eb ILT |
8920 | printf ("%c", *args); |
8921 | continue; | |
3d3c5039 ILT |
8922 | |
8923 | case 'r': | |
670a50eb ILT |
8924 | assert (treg == sreg); |
8925 | printf ("$%d,$%d", treg, sreg); | |
8926 | continue; | |
3d3c5039 ILT |
8927 | |
8928 | case 'd': | |
918692a5 | 8929 | case 'G': |
670a50eb ILT |
8930 | printf ("$%d", dreg); |
8931 | continue; | |
3d3c5039 ILT |
8932 | |
8933 | case 't': | |
918692a5 | 8934 | case 'E': |
670a50eb ILT |
8935 | printf ("$%d", treg); |
8936 | continue; | |
3d3c5039 | 8937 | |
9226253a ILT |
8938 | case 'k': |
8939 | printf ("0x%x", treg); | |
8940 | continue; | |
8941 | ||
3d3c5039 ILT |
8942 | case 'b': |
8943 | case 's': | |
670a50eb ILT |
8944 | printf ("$%d", sreg); |
8945 | continue; | |
3d3c5039 ILT |
8946 | |
8947 | case 'a': | |
670a50eb ILT |
8948 | printf ("0x%08lx", oc & 0x1ffffff); |
8949 | continue; | |
3d3c5039 ILT |
8950 | |
8951 | case 'i': | |
8952 | case 'j': | |
8953 | case 'o': | |
8954 | case 'u': | |
670a50eb ILT |
8955 | printf ("%d", imm); |
8956 | continue; | |
3d3c5039 ILT |
8957 | |
8958 | case '<': | |
56c96faa | 8959 | case '>': |
670a50eb ILT |
8960 | printf ("$%d", shamt); |
8961 | continue; | |
3d3c5039 ILT |
8962 | |
8963 | default: | |
670a50eb | 8964 | internalError (); |
3d3c5039 | 8965 | } |
670a50eb | 8966 | break; |
3d3c5039 | 8967 | } |
670a50eb | 8968 | return; |
3d3c5039 ILT |
8969 | } |
8970 | } | |
670a50eb | 8971 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8972 | } |
8973 | #endif | |
8974 | ||
8975 | static symbolS * | |
8976 | get_symbol () | |
8977 | { | |
670a50eb ILT |
8978 | int c; |
8979 | char *name; | |
8980 | symbolS *p; | |
8981 | ||
8982 | name = input_line_pointer; | |
8983 | c = get_symbol_end (); | |
8984 | p = (symbolS *) symbol_find_or_make (name); | |
8985 | *input_line_pointer = c; | |
8986 | return p; | |
3d3c5039 ILT |
8987 | } |
8988 | ||
becfe05e ILT |
8989 | /* Align the current frag to a given power of two. The MIPS assembler |
8990 | also automatically adjusts any preceding label. */ | |
8991 | ||
8992 | static void | |
23dc1ae3 | 8993 | mips_align (to, fill, label) |
becfe05e ILT |
8994 | int to; |
8995 | int fill; | |
23dc1ae3 | 8996 | symbolS *label; |
becfe05e | 8997 | { |
fbcfacb7 | 8998 | mips_emit_delays (false); |
e2e5acfa | 8999 | frag_align (to, fill, 0); |
becfe05e | 9000 | record_alignment (now_seg, to); |
23dc1ae3 | 9001 | if (label != NULL) |
becfe05e | 9002 | { |
23dc1ae3 ILT |
9003 | assert (S_GET_SEGMENT (label) == now_seg); |
9004 | label->sy_frag = frag_now; | |
9005 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9006 | } |
9007 | } | |
9008 | ||
9009 | /* Align to a given power of two. .align 0 turns off the automatic | |
9010 | alignment used by the data creating pseudo-ops. */ | |
9011 | ||
3d3c5039 ILT |
9012 | static void |
9013 | s_align (x) | |
9014 | int x; | |
9015 | { | |
670a50eb ILT |
9016 | register int temp; |
9017 | register long temp_fill; | |
9018 | long max_alignment = 15; | |
3d3c5039 | 9019 | |
670a50eb | 9020 | /* |
3d3c5039 ILT |
9021 | |
9022 | o Note that the assembler pulls down any immediately preceeding label | |
9023 | to the aligned address. | |
9024 | o It's not documented but auto alignment is reinstated by | |
9025 | a .align pseudo instruction. | |
9026 | o Note also that after auto alignment is turned off the mips assembler | |
9027 | issues an error on attempt to assemble an improperly aligned data item. | |
9028 | We don't. | |
9029 | ||
9030 | */ | |
9031 | ||
670a50eb ILT |
9032 | temp = get_absolute_expression (); |
9033 | if (temp > max_alignment) | |
9034 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9035 | else if (temp < 0) | |
9036 | { | |
9037 | as_warn ("Alignment negative: 0 assumed."); | |
9038 | temp = 0; | |
9039 | } | |
9040 | if (*input_line_pointer == ',') | |
9041 | { | |
9042 | input_line_pointer++; | |
9043 | temp_fill = get_absolute_expression (); | |
9044 | } | |
9045 | else | |
9046 | temp_fill = 0; | |
9047 | if (temp) | |
9048 | { | |
9049 | auto_align = 1; | |
fbcfacb7 ILT |
9050 | mips_align (temp, (int) temp_fill, |
9051 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9052 | } |
670a50eb ILT |
9053 | else |
9054 | { | |
9055 | auto_align = 0; | |
3d3c5039 ILT |
9056 | } |
9057 | ||
670a50eb | 9058 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9059 | } |
9060 | ||
739708fa KR |
9061 | void |
9062 | mips_flush_pending_output () | |
becfe05e | 9063 | { |
fbcfacb7 ILT |
9064 | mips_emit_delays (false); |
9065 | mips_clear_insn_labels (); | |
becfe05e ILT |
9066 | } |
9067 | ||
3d3c5039 ILT |
9068 | static void |
9069 | s_change_sec (sec) | |
9070 | int sec; | |
9071 | { | |
88225433 | 9072 | segT seg; |
becfe05e | 9073 | |
5b63f465 ILT |
9074 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9075 | .sdata and .sbss sections. We change the .data and .rdata | |
9076 | pseudo-ops to use .sdata. */ | |
9077 | if (mips_pic == EMBEDDED_PIC | |
9078 | && (sec == 'd' || sec == 'r')) | |
9079 | sec = 's'; | |
9080 | ||
acdc7ce3 ILT |
9081 | #ifdef OBJ_ELF |
9082 | /* The ELF backend needs to know that we are changing sections, so | |
9083 | that .previous works correctly. We could do something like check | |
9084 | for a obj_section_change_hook macro, but that might be confusing | |
9085 | as it would not be appropriate to use it in the section changing | |
9086 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9087 | This should be cleaner, somehow. */ | |
9088 | obj_elf_section_change_hook (); | |
9089 | #endif | |
9090 | ||
fbcfacb7 | 9091 | mips_emit_delays (false); |
670a50eb ILT |
9092 | switch (sec) |
9093 | { | |
3d3c5039 | 9094 | case 't': |
604633ae | 9095 | s_text (0); |
670a50eb | 9096 | break; |
3d3c5039 | 9097 | case 'd': |
604633ae | 9098 | s_data (0); |
670a50eb | 9099 | break; |
3d3c5039 | 9100 | case 'b': |
670a50eb | 9101 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9102 | demand_empty_rest_of_line (); |
9103 | break; | |
88225433 ILT |
9104 | |
9105 | case 'r': | |
1dc1e798 KR |
9106 | if (USE_GLOBAL_POINTER_OPT) |
9107 | { | |
9108 | seg = subseg_new (RDATA_SECTION_NAME, | |
9109 | (subsegT) get_absolute_expression ()); | |
9110 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9111 | { | |
9112 | bfd_set_section_flags (stdoutput, seg, | |
9113 | (SEC_ALLOC | |
9114 | | SEC_LOAD | |
9115 | | SEC_READONLY | |
9116 | | SEC_RELOC | |
9117 | | SEC_DATA)); | |
08e17202 ILT |
9118 | if (strcmp (TARGET_OS, "elf") != 0) |
9119 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9120 | } |
9121 | demand_empty_rest_of_line (); | |
9122 | } | |
9123 | else | |
9124 | { | |
9125 | as_bad ("No read only data section in this object file format"); | |
9126 | demand_empty_rest_of_line (); | |
9127 | return; | |
9128 | } | |
88225433 | 9129 | break; |
88225433 ILT |
9130 | |
9131 | case 's': | |
1dc1e798 KR |
9132 | if (USE_GLOBAL_POINTER_OPT) |
9133 | { | |
9134 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9135 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9136 | { | |
9137 | bfd_set_section_flags (stdoutput, seg, | |
9138 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9139 | | SEC_DATA); | |
08e17202 ILT |
9140 | if (strcmp (TARGET_OS, "elf") != 0) |
9141 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9142 | } |
9143 | demand_empty_rest_of_line (); | |
9144 | break; | |
9145 | } | |
9146 | else | |
9147 | { | |
9148 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9149 | demand_empty_rest_of_line (); | |
9150 | return; | |
9151 | } | |
3d3c5039 | 9152 | } |
88225433 | 9153 | |
670a50eb | 9154 | auto_align = 1; |
3d3c5039 ILT |
9155 | } |
9156 | ||
739708fa KR |
9157 | void |
9158 | mips_enable_auto_align () | |
9da4c5d1 | 9159 | { |
9da4c5d1 ILT |
9160 | auto_align = 1; |
9161 | } | |
9162 | ||
3d3c5039 ILT |
9163 | static void |
9164 | s_cons (log_size) | |
9165 | int log_size; | |
9166 | { | |
23dc1ae3 ILT |
9167 | symbolS *label; |
9168 | ||
fbcfacb7 ILT |
9169 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9170 | mips_emit_delays (false); | |
670a50eb | 9171 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9172 | mips_align (log_size, 0, label); |
fbcfacb7 | 9173 | mips_clear_insn_labels (); |
670a50eb | 9174 | cons (1 << log_size); |
3d3c5039 ILT |
9175 | } |
9176 | ||
3d3c5039 | 9177 | static void |
becfe05e ILT |
9178 | s_float_cons (type) |
9179 | int type; | |
3d3c5039 | 9180 | { |
23dc1ae3 ILT |
9181 | symbolS *label; |
9182 | ||
fbcfacb7 | 9183 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9184 | |
fbcfacb7 | 9185 | mips_emit_delays (false); |
670a50eb ILT |
9186 | |
9187 | if (auto_align) | |
becfe05e | 9188 | if (type == 'd') |
23dc1ae3 | 9189 | mips_align (3, 0, label); |
670a50eb | 9190 | else |
23dc1ae3 | 9191 | mips_align (2, 0, label); |
670a50eb | 9192 | |
fbcfacb7 | 9193 | mips_clear_insn_labels (); |
1849d646 | 9194 | |
becfe05e | 9195 | float_cons (type); |
3d3c5039 ILT |
9196 | } |
9197 | ||
c1444ec4 ILT |
9198 | /* Handle .globl. We need to override it because on Irix 5 you are |
9199 | permitted to say | |
9200 | .globl foo .text | |
9201 | where foo is an undefined symbol, to mean that foo should be | |
9202 | considered to be the address of a function. */ | |
9203 | ||
9204 | static void | |
9205 | s_mips_globl (x) | |
9206 | int x; | |
9207 | { | |
9208 | char *name; | |
9209 | int c; | |
9210 | symbolS *symbolP; | |
fb251650 | 9211 | flagword flag; |
c1444ec4 ILT |
9212 | |
9213 | name = input_line_pointer; | |
9214 | c = get_symbol_end (); | |
9215 | symbolP = symbol_find_or_make (name); | |
9216 | *input_line_pointer = c; | |
9217 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9218 | |
9219 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9220 | being a function is apparently labelled as being an object. */ | |
9221 | flag = BSF_OBJECT; | |
9222 | ||
c1444ec4 ILT |
9223 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9224 | { | |
9225 | char *secname; | |
9226 | asection *sec; | |
9227 | ||
9228 | secname = input_line_pointer; | |
9229 | c = get_symbol_end (); | |
9230 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9231 | if (sec == NULL) | |
9232 | as_bad ("%s: no such section", secname); | |
9233 | *input_line_pointer = c; | |
9234 | ||
9235 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9236 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9237 | } |
9238 | ||
fb251650 ILT |
9239 | symbolP->bsym->flags |= flag; |
9240 | ||
c1444ec4 ILT |
9241 | S_SET_EXTERNAL (symbolP); |
9242 | demand_empty_rest_of_line (); | |
9243 | } | |
9244 | ||
3d3c5039 ILT |
9245 | static void |
9246 | s_option (x) | |
9247 | int x; | |
9248 | { | |
dd3f1f76 ILT |
9249 | char *opt; |
9250 | char c; | |
9251 | ||
9252 | opt = input_line_pointer; | |
9253 | c = get_symbol_end (); | |
9254 | ||
dd3f1f76 | 9255 | if (*opt == 'O') |
9226253a ILT |
9256 | { |
9257 | /* FIXME: What does this mean? */ | |
9258 | } | |
dd3f1f76 | 9259 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9260 | { |
d9aba805 | 9261 | int i; |
42562568 | 9262 | |
d9aba805 ILT |
9263 | i = atoi (opt + 3); |
9264 | if (i == 0) | |
9265 | mips_pic = NO_PIC; | |
9266 | else if (i == 2) | |
9267 | mips_pic = SVR4_PIC; | |
9268 | else | |
9269 | as_bad (".option pic%d not supported", i); | |
9270 | ||
1dc1e798 | 9271 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9272 | { |
9273 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9274 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9275 | g_switch_value = 0; |
9276 | bfd_set_gp_size (stdoutput, 0); | |
9277 | } | |
9226253a | 9278 | } |
dd3f1f76 ILT |
9279 | else |
9280 | as_warn ("Unrecognized option \"%s\"", opt); | |
9281 | ||
9282 | *input_line_pointer = c; | |
670a50eb | 9283 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9284 | } |
9285 | ||
9286 | static void | |
9287 | s_mipsset (x) | |
9288 | int x; | |
9289 | { | |
670a50eb ILT |
9290 | char *name = input_line_pointer, ch; |
9291 | ||
9292 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9293 | input_line_pointer++; | |
9294 | ch = *input_line_pointer; | |
9295 | *input_line_pointer = '\0'; | |
9296 | ||
9297 | if (strcmp (name, "reorder") == 0) | |
9298 | { | |
4a1cb507 | 9299 | if (mips_noreorder && prev_nop_frag != NULL) |
4e95866e | 9300 | { |
4a1cb507 ILT |
9301 | /* If we still have pending nops, we can discard them. The |
9302 | usual nop handling will insert any that are still | |
9303 | needed. */ | |
9304 | prev_nop_frag->fr_fix -= prev_nop_frag_holds * (mips16 ? 2 : 4); | |
9305 | prev_nop_frag = NULL; | |
4e95866e | 9306 | } |
670a50eb ILT |
9307 | mips_noreorder = 0; |
9308 | } | |
9309 | else if (strcmp (name, "noreorder") == 0) | |
9310 | { | |
fbcfacb7 | 9311 | mips_emit_delays (true); |
670a50eb | 9312 | mips_noreorder = 1; |
0dd2d296 | 9313 | mips_any_noreorder = 1; |
670a50eb ILT |
9314 | } |
9315 | else if (strcmp (name, "at") == 0) | |
9316 | { | |
9317 | mips_noat = 0; | |
9318 | } | |
9319 | else if (strcmp (name, "noat") == 0) | |
9320 | { | |
9321 | mips_noat = 1; | |
3d3c5039 | 9322 | } |
670a50eb ILT |
9323 | else if (strcmp (name, "macro") == 0) |
9324 | { | |
9325 | mips_warn_about_macros = 0; | |
9326 | } | |
9327 | else if (strcmp (name, "nomacro") == 0) | |
9328 | { | |
9329 | if (mips_noreorder == 0) | |
9330 | as_bad ("`noreorder' must be set before `nomacro'"); | |
9331 | mips_warn_about_macros = 1; | |
9332 | } | |
9333 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9334 | { | |
9335 | mips_nomove = 0; | |
9336 | } | |
9337 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9338 | { | |
9339 | mips_nomove = 1; | |
9340 | } | |
9341 | else if (strcmp (name, "bopt") == 0) | |
9342 | { | |
9343 | mips_nobopt = 0; | |
9344 | } | |
9345 | else if (strcmp (name, "nobopt") == 0) | |
9346 | { | |
9347 | mips_nobopt = 1; | |
9348 | } | |
943321c0 ILT |
9349 | else if (strcmp (name, "mips16") == 0 |
9350 | || strcmp (name, "MIPS-16") == 0) | |
9351 | mips16 = 1; | |
9352 | else if (strcmp (name, "nomips16") == 0 | |
9353 | || strcmp (name, "noMIPS-16") == 0) | |
9354 | mips16 = 0; | |
1051c97f ILT |
9355 | else if (strncmp (name, "mips", 4) == 0) |
9356 | { | |
9357 | int isa; | |
9358 | ||
9359 | /* Permit the user to change the ISA on the fly. Needless to | |
9360 | say, misuse can cause serious problems. */ | |
9361 | isa = atoi (name + 4); | |
9362 | if (isa == 0) | |
9363 | mips_isa = file_mips_isa; | |
d8a1c247 | 9364 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9365 | as_bad ("unknown ISA level"); |
9366 | else | |
9367 | mips_isa = isa; | |
9368 | } | |
cc5703cd ILT |
9369 | else if (strcmp (name, "autoextend") == 0) |
9370 | mips16_autoextend = 1; | |
9371 | else if (strcmp (name, "noautoextend") == 0) | |
9372 | mips16_autoextend = 0; | |
670a50eb ILT |
9373 | else |
9374 | { | |
9375 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9376 | } | |
9377 | *input_line_pointer = ch; | |
9378 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9379 | } |
9380 | ||
9226253a ILT |
9381 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9382 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9383 | ||
9384 | static void | |
9385 | s_abicalls (ignore) | |
9386 | int ignore; | |
9387 | { | |
d9aba805 | 9388 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9389 | if (USE_GLOBAL_POINTER_OPT) |
9390 | { | |
9391 | if (g_switch_seen && g_switch_value != 0) | |
9392 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9393 | g_switch_value = 0; | |
9394 | } | |
d9aba805 | 9395 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9396 | demand_empty_rest_of_line (); |
9397 | } | |
9398 | ||
9399 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9400 | PIC code. It sets the $gp register for the function based on the | |
9401 | function address, which is in the register named in the argument. | |
9402 | This uses a relocation against _gp_disp, which is handled specially | |
9403 | by the linker. The result is: | |
9404 | lui $gp,%hi(_gp_disp) | |
9405 | addiu $gp,$gp,%lo(_gp_disp) | |
9406 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9407 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9408 | |
9409 | static void | |
9410 | s_cpload (ignore) | |
9411 | int ignore; | |
9412 | { | |
9413 | expressionS ex; | |
9414 | int icnt = 0; | |
9415 | ||
d9aba805 ILT |
9416 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9417 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9418 | { |
9419 | s_ignore (0); | |
9420 | return; | |
9421 | } | |
9422 | ||
9423 | /* .cpload should be a in .set noreorder section. */ | |
9424 | if (mips_noreorder == 0) | |
9425 | as_warn (".cpload not in noreorder section"); | |
9426 | ||
9226253a ILT |
9427 | ex.X_op = O_symbol; |
9428 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9429 | ex.X_op_symbol = NULL; | |
9430 | ex.X_add_number = 0; | |
9431 | ||
fb251650 ILT |
9432 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9433 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9434 | ||
0dd2d296 ILT |
9435 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9436 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9437 | (int) BFD_RELOC_LO16); |
9438 | ||
0dd2d296 ILT |
9439 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9440 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9441 | |
9442 | demand_empty_rest_of_line (); | |
9443 | } | |
9444 | ||
9445 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9446 | offset from $sp. The offset is remembered, and after making a PIC | |
9447 | call $gp is restored from that location. */ | |
9448 | ||
9449 | static void | |
9450 | s_cprestore (ignore) | |
9451 | int ignore; | |
9452 | { | |
9453 | expressionS ex; | |
9454 | int icnt = 0; | |
9455 | ||
d9aba805 ILT |
9456 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9457 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9458 | { |
9459 | s_ignore (0); | |
9460 | return; | |
9461 | } | |
9462 | ||
9226253a ILT |
9463 | mips_cprestore_offset = get_absolute_expression (); |
9464 | ||
9465 | ex.X_op = O_constant; | |
9466 | ex.X_add_symbol = NULL; | |
9467 | ex.X_op_symbol = NULL; | |
9468 | ex.X_add_number = mips_cprestore_offset; | |
9469 | ||
0dd2d296 | 9470 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9471 | mips_isa < 3 ? "sw" : "sd", |
9472 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9473 | ||
9474 | demand_empty_rest_of_line (); | |
9475 | } | |
9476 | ||
0dd2d296 ILT |
9477 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9478 | code. It generates a 32 bit GP relative reloc. */ | |
9479 | ||
9480 | static void | |
9481 | s_gpword (ignore) | |
9482 | int ignore; | |
9483 | { | |
23dc1ae3 | 9484 | symbolS *label; |
0dd2d296 ILT |
9485 | expressionS ex; |
9486 | char *p; | |
9487 | ||
9488 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9489 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9490 | { |
9491 | s_cons (2); | |
9492 | return; | |
9493 | } | |
9494 | ||
fbcfacb7 ILT |
9495 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9496 | mips_emit_delays (true); | |
0dd2d296 | 9497 | if (auto_align) |
23dc1ae3 | 9498 | mips_align (2, 0, label); |
fbcfacb7 | 9499 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9500 | |
9501 | expression (&ex); | |
9502 | ||
9503 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9504 | { | |
9505 | as_bad ("Unsupported use of .gpword"); | |
9506 | ignore_rest_of_line (); | |
9507 | } | |
9508 | ||
9509 | p = frag_more (4); | |
9510 | md_number_to_chars (p, (valueT) 0, 4); | |
9511 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9512 | BFD_RELOC_MIPS_GPREL32); | |
9513 | ||
9514 | demand_empty_rest_of_line (); | |
9515 | } | |
9516 | ||
9517 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9518 | tables in SVR4 PIC code. */ | |
9519 | ||
9520 | static void | |
9521 | s_cpadd (ignore) | |
9522 | int ignore; | |
9523 | { | |
9524 | int icnt = 0; | |
9525 | int reg; | |
9526 | ||
9527 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9528 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9529 | { |
9530 | s_ignore (0); | |
9531 | return; | |
9532 | } | |
9533 | ||
9534 | /* Add $gp to the register named as an argument. */ | |
9535 | reg = tc_get_register (0); | |
9536 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9537 | mips_isa < 3 ? "addu" : "daddu", | |
9538 | "d,v,t", reg, reg, GP); | |
9539 | ||
9540 | demand_empty_rest_of_line (); | |
9541 | } | |
9542 | ||
ed3eb786 ILT |
9543 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9544 | mips16 mode. This permits the linker to handle them specially, | |
9545 | such as generating jalx instructions when needed. We also make | |
9546 | them odd for the duration of the assembly, in order to generate the | |
9547 | right sort of code. We will make them even in the adjust_symtab | |
9548 | routine, while leaving them marked. This is convenient for the | |
9549 | debugger and the disassembler. The linker knows to make them odd | |
9550 | again. */ | |
9551 | ||
9552 | static void | |
9553 | s_insn (ignore) | |
9554 | int ignore; | |
9555 | { | |
9556 | if (mips16) | |
9557 | { | |
9558 | struct insn_label_list *l; | |
9559 | ||
9560 | for (l = insn_labels; l != NULL; l = l->next) | |
9561 | { | |
9562 | #ifdef S_SET_OTHER | |
9563 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9564 | S_SET_OTHER (l->label, STO_MIPS16); | |
9565 | #endif | |
9566 | ++l->label->sy_value.X_add_number; | |
9567 | } | |
9568 | ||
9569 | mips_clear_insn_labels (); | |
9570 | } | |
9571 | ||
9572 | demand_empty_rest_of_line (); | |
9573 | } | |
9574 | ||
9226253a | 9575 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9576 | to parse .frame. The argument is non-zero if this is the frame |
9577 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9578 | |
3d3c5039 | 9579 | int |
0dd2d296 ILT |
9580 | tc_get_register (frame) |
9581 | int frame; | |
3d3c5039 ILT |
9582 | { |
9583 | int reg; | |
9584 | ||
9585 | SKIP_WHITESPACE (); | |
9586 | if (*input_line_pointer++ != '$') | |
9587 | { | |
9588 | as_warn ("expected `$'"); | |
0dd2d296 | 9589 | reg = 0; |
3d3c5039 | 9590 | } |
0dd2d296 | 9591 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9592 | { |
9593 | reg = get_absolute_expression (); | |
9594 | if (reg < 0 || reg >= 32) | |
9595 | { | |
9596 | as_warn ("Bad register number"); | |
9597 | reg = 0; | |
9598 | } | |
9599 | } | |
9600 | else | |
9601 | { | |
9602 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9603 | reg = FP; |
3d3c5039 | 9604 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9605 | reg = SP; |
3d3c5039 | 9606 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9607 | reg = GP; |
3d3c5039 | 9608 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9609 | reg = AT; |
3d3c5039 ILT |
9610 | else |
9611 | { | |
9612 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9613 | reg = 0; |
3d3c5039 ILT |
9614 | } |
9615 | input_line_pointer += 2; | |
9616 | } | |
0dd2d296 ILT |
9617 | if (frame) |
9618 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9619 | return reg; |
9620 | } | |
9621 | ||
0dd2d296 ILT |
9622 | valueT |
9623 | md_section_align (seg, addr) | |
9624 | asection *seg; | |
9625 | valueT addr; | |
9626 | { | |
9627 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9628 | ||
cf32394d ILT |
9629 | #ifdef OBJ_ELF |
9630 | /* We don't need to align ELF sections to the full alignment. | |
9631 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9632 | byte boundary. We don't bother to align the sections if we are |
9633 | targeted for an embedded system. */ | |
9634 | if (strcmp (TARGET_OS, "elf") == 0) | |
9635 | return addr; | |
943321c0 ILT |
9636 | if (align > 4) |
9637 | align = 4; | |
10a14e36 | 9638 | #endif |
cf32394d ILT |
9639 | |
9640 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9641 | } |
9642 | ||
d8a1c247 KR |
9643 | /* Utility routine, called from above as well. If called while the |
9644 | input file is still being read, it's only an approximation. (For | |
9645 | example, a symbol may later become defined which appeared to be | |
9646 | undefined earlier.) */ | |
22ba90ce ILT |
9647 | |
9648 | static int | |
9649 | nopic_need_relax (sym) | |
d8a1c247 KR |
9650 | symbolS *sym; |
9651 | { | |
9652 | if (sym == 0) | |
9653 | return 0; | |
9654 | ||
1dc1e798 KR |
9655 | if (USE_GLOBAL_POINTER_OPT) |
9656 | { | |
9657 | const char *symname; | |
9658 | int change; | |
9659 | ||
9660 | /* Find out whether this symbol can be referenced off the GP | |
9661 | register. It can be if it is smaller than the -G size or if | |
9662 | it is in the .sdata or .sbss section. Certain symbols can | |
9663 | not be referenced off the GP, although it appears as though | |
9664 | they can. */ | |
9665 | symname = S_GET_NAME (sym); | |
9666 | if (symname != (const char *) NULL | |
9667 | && (strcmp (symname, "eprol") == 0 | |
9668 | || strcmp (symname, "etext") == 0 | |
9669 | || strcmp (symname, "_gp") == 0 | |
9670 | || strcmp (symname, "edata") == 0 | |
9671 | || strcmp (symname, "_fbss") == 0 | |
9672 | || strcmp (symname, "_fdata") == 0 | |
9673 | || strcmp (symname, "_ftext") == 0 | |
9674 | || strcmp (symname, "end") == 0 | |
9675 | || strcmp (symname, "_gp_disp") == 0)) | |
9676 | change = 1; | |
23ac3ca1 | 9677 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
9678 | && (0 |
9679 | #ifndef NO_ECOFF_DEBUGGING | |
9680 | || (sym->ecoff_extern_size != 0 | |
9681 | && sym->ecoff_extern_size <= g_switch_value) | |
9682 | #endif | |
1dc1e798 KR |
9683 | || (S_GET_VALUE (sym) != 0 |
9684 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9685 | change = 0; | |
9686 | else | |
9687 | { | |
9688 | const char *segname; | |
d8a1c247 | 9689 | |
1dc1e798 KR |
9690 | segname = segment_name (S_GET_SEGMENT (sym)); |
9691 | assert (strcmp (segname, ".lit8") != 0 | |
9692 | && strcmp (segname, ".lit4") != 0); | |
9693 | change = (strcmp (segname, ".sdata") != 0 | |
9694 | && strcmp (segname, ".sbss") != 0); | |
9695 | } | |
9696 | return change; | |
9697 | } | |
9698 | else | |
9699 | /* We are not optimizing for the GP register. */ | |
9700 | return 1; | |
d8a1c247 KR |
9701 | } |
9702 | ||
cc5703cd ILT |
9703 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9704 | extended opcode. SEC is the section the frag is in. */ | |
9705 | ||
9706 | static int | |
9707 | mips16_extended_frag (fragp, sec, stretch) | |
9708 | fragS *fragp; | |
9709 | asection *sec; | |
9710 | long stretch; | |
9711 | { | |
9712 | int type; | |
9713 | register const struct mips16_immed_operand *op; | |
9714 | offsetT val; | |
9715 | int mintiny, maxtiny; | |
f74ba7a3 | 9716 | segT symsec; |
cc5703cd | 9717 | |
8728fa92 ILT |
9718 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9719 | return 0; | |
9720 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9721 | return 1; | |
9722 | ||
cc5703cd ILT |
9723 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9724 | op = mips16_immed_operands; | |
9725 | while (op->type != type) | |
9726 | { | |
9727 | ++op; | |
9728 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9729 | } | |
9730 | ||
9731 | if (op->unsp) | |
9732 | { | |
9733 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9734 | { | |
9735 | mintiny = 1; | |
9736 | maxtiny = 1 << op->nbits; | |
9737 | } | |
9738 | else | |
9739 | { | |
9740 | mintiny = 0; | |
9741 | maxtiny = (1 << op->nbits) - 1; | |
9742 | } | |
9743 | } | |
9744 | else | |
9745 | { | |
9746 | mintiny = - (1 << (op->nbits - 1)); | |
9747 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9748 | } | |
9749 | ||
f74ba7a3 ILT |
9750 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9751 | a particular frag address. */ | |
9752 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9753 | { | |
9754 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9755 | + fragp->fr_symbol->sy_frag->fr_address); | |
9756 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9757 | } | |
9758 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9759 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9760 | == O_constant)) | |
9761 | { | |
9762 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9763 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9764 | + fragp->fr_symbol->sy_value.X_add_number | |
9765 | + fragp->fr_symbol->sy_frag->fr_address); | |
9766 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9767 | } | |
9768 | else | |
9769 | return 1; | |
cc5703cd ILT |
9770 | |
9771 | if (op->pcrel) | |
9772 | { | |
9773 | addressT addr; | |
9774 | ||
9775 | /* We won't have the section when we are called from | |
9776 | mips_relax_frag. However, we will always have been called | |
9777 | from md_estimate_size_before_relax first. If this is a | |
9778 | branch to a different section, we mark it as such. If SEC is | |
9779 | NULL, and the frag is not marked, then it must be a branch to | |
9780 | the same section. */ | |
9781 | if (sec == NULL) | |
9782 | { | |
9783 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9784 | return 1; | |
9785 | } | |
9786 | else | |
9787 | { | |
f74ba7a3 | 9788 | if (symsec != sec) |
cc5703cd ILT |
9789 | { |
9790 | fragp->fr_subtype = | |
9791 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9792 | ||
9793 | /* FIXME: We should support this, and let the linker | |
9794 | catch branches and loads that are out of range. */ | |
9795 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9796 | "unsupported PC relative reference to different section"); | |
9797 | ||
9798 | return 1; | |
9799 | } | |
9800 | } | |
9801 | ||
9802 | /* In this case, we know for sure that the symbol fragment is in | |
9803 | the same section. If the fr_address of the symbol fragment | |
9804 | is greater then the address of this fragment we want to add | |
9805 | in STRETCH in order to get a better estimate of the address. | |
9806 | This particularly matters because of the shift bits. */ | |
9807 | if (stretch != 0 | |
9808 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9809 | { | |
9810 | fragS *f; | |
9811 | ||
a941619c ILT |
9812 | /* Adjust stretch for any alignment frag. Note that if have |
9813 | been expanding the earlier code, the symbol may be | |
9814 | defined in what appears to be an earlier frag. FIXME: | |
9815 | This doesn't handle the fr_subtype field, which specifies | |
9816 | a maximum number of bytes to skip when doing an | |
9817 | alignment. */ | |
9818 | for (f = fragp; | |
9819 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
9820 | f = f->fr_next) | |
cc5703cd | 9821 | { |
cc5703cd ILT |
9822 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
9823 | { | |
9824 | if (stretch < 0) | |
9825 | stretch = - ((- stretch) | |
9826 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9827 | else | |
9828 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9829 | if (stretch == 0) | |
9830 | break; | |
9831 | } | |
9832 | } | |
a941619c ILT |
9833 | if (f != NULL) |
9834 | val += stretch; | |
cc5703cd ILT |
9835 | } |
9836 | ||
a677feeb ILT |
9837 | addr = fragp->fr_address + fragp->fr_fix; |
9838 | ||
9839 | /* The base address rules are complicated. The base address of | |
9840 | a branch is the following instruction. The base address of a | |
9841 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
9842 | is in a delay slot (in which case it can not be extended) use |
9843 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 9844 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
9845 | { |
9846 | addr += 2; | |
319305a7 ILT |
9847 | |
9848 | /* If we are currently assuming that this frag should be | |
9849 | extended, then, the current address is two bytes | |
9850 | higher. */ | |
9851 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9852 | addr += 2; | |
9853 | ||
fbcfacb7 ILT |
9854 | /* Ignore the low bit in the target, since it will be set |
9855 | for a text label. */ | |
9856 | if ((val & 1) != 0) | |
9857 | --val; | |
9858 | } | |
a677feeb ILT |
9859 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9860 | addr -= 4; | |
9861 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9862 | addr -= 2; | |
cc5703cd | 9863 | |
cc5703cd ILT |
9864 | val -= addr & ~ ((1 << op->shift) - 1); |
9865 | ||
9866 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9867 | if (type == 'p' || type == 'q') | |
9868 | val /= 2; | |
9869 | ||
9870 | /* If any of the shifted bits are set, we must use an extended | |
9871 | opcode. If the address depends on the size of this | |
9872 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9873 | use an extended opcode. We only check this when we are in |
9874 | the main relaxation loop, when SEC is NULL. */ | |
9875 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9876 | { | |
9877 | fragp->fr_subtype = | |
9878 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9879 | return 1; | |
9880 | } | |
9881 | ||
9882 | /* If we are about to mark a frag as extended because the value | |
9883 | is precisely maxtiny + 1, then there is a chance of an | |
9884 | infinite loop as in the following code: | |
9885 | la $4,foo | |
9886 | .skip 1020 | |
9887 | .align 2 | |
9888 | foo: | |
9889 | In this case when the la is extended, foo is 0x3fc bytes | |
9890 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9891 | the la must be extended. To avoid this loop, we mark the | |
9892 | frag as extended if it was small, and is about to become | |
9893 | extended with a value of maxtiny + 1. */ | |
9894 | if (val == ((maxtiny + 1) << op->shift) | |
9895 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9896 | && sec == NULL) | |
cc5703cd ILT |
9897 | { |
9898 | fragp->fr_subtype = | |
9899 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9900 | return 1; | |
9901 | } | |
9902 | } | |
41a0ed22 ILT |
9903 | else if (symsec != absolute_section && sec != NULL) |
9904 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9905 | |
9906 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9907 | || val < (mintiny << op->shift) | |
9908 | || val > (maxtiny << op->shift)) | |
9909 | return 1; | |
9910 | else | |
9911 | return 0; | |
9912 | } | |
9913 | ||
9914 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9915 | mips16, we are not really relaxing here, and the final size is | |
9916 | encoded in the subtype information. For the mips16, we have to | |
9917 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9918 | |
0dd2d296 ILT |
9919 | /*ARGSUSED*/ |
9920 | int | |
9921 | md_estimate_size_before_relax (fragp, segtype) | |
9922 | fragS *fragp; | |
9923 | asection *segtype; | |
9924 | { | |
9925 | int change; | |
9926 | ||
cc5703cd ILT |
9927 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9928 | { | |
9929 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9930 | { | |
9931 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9932 | return 4; | |
9933 | } | |
9934 | else | |
9935 | { | |
9936 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9937 | return 2; | |
9938 | } | |
9939 | } | |
9940 | ||
d9aba805 | 9941 | if (mips_pic == NO_PIC) |
0dd2d296 | 9942 | { |
d8a1c247 | 9943 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9944 | } |
d9aba805 | 9945 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9946 | { |
46a92fde ILT |
9947 | symbolS *sym; |
9948 | asection *symsec; | |
9949 | ||
9950 | sym = fragp->fr_symbol; | |
9951 | ||
9952 | /* Handle the case of a symbol equated to another symbol. */ | |
9953 | while (sym->sy_value.X_op == O_symbol | |
9954 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
9955 | { | |
9956 | symbolS *n; | |
9957 | ||
9958 | /* It's possible to get a loop here in a badly written | |
9959 | program. */ | |
9960 | n = sym->sy_value.X_add_symbol; | |
9961 | if (n == sym) | |
9962 | break; | |
9963 | sym = n; | |
9964 | } | |
9965 | ||
9966 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
9967 | |
9968 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9969 | change = (symsec != &bfd_und_section | |
9970 | && symsec != &bfd_abs_section | |
9971 | && ! bfd_is_com_section (symsec)); | |
9972 | } | |
d9aba805 ILT |
9973 | else |
9974 | abort (); | |
0dd2d296 ILT |
9975 | |
9976 | if (change) | |
9977 | { | |
9978 | /* Record the offset to the first reloc in the fr_opcode field. | |
9979 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9980 | must be expanded. */ | |
9981 | fragp->fr_opcode = (fragp->fr_literal | |
9982 | + fragp->fr_fix | |
9983 | - RELAX_OLD (fragp->fr_subtype) | |
9984 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9985 | /* FIXME: This really needs as_warn_where. */ | |
9986 | if (RELAX_WARN (fragp->fr_subtype)) | |
9987 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9988 | } | |
9989 | ||
9990 | if (! change) | |
9991 | return 0; | |
9992 | else | |
9993 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9994 | } | |
9995 | ||
0d7f9025 ILT |
9996 | /* This is called to see whether a reloc against a defined symbol |
9997 | should be converted into a reloc against a section. Don't adjust | |
9998 | MIPS16 jump relocations, so we don't have to worry about the format | |
9999 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10000 | mips16 symbols, so that the linker can find them if it needs to set |
10001 | up a stub. */ | |
0d7f9025 ILT |
10002 | |
10003 | int | |
10004 | mips_fix_adjustable (fixp) | |
10005 | fixS *fixp; | |
10006 | { | |
10007 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10008 | return 0; | |
10009 | if (fixp->fx_addsy == NULL) | |
10010 | return 1; | |
0d7f9025 ILT |
10011 | #ifdef S_GET_OTHER |
10012 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
46a92fde ILT |
10013 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10014 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10015 | return 0; |
10016 | #endif | |
10017 | return 1; | |
10018 | } | |
10019 | ||
0dd2d296 ILT |
10020 | /* Translate internal representation of relocation info to BFD target |
10021 | format. */ | |
10022 | ||
10023 | arelent ** | |
3d3c5039 ILT |
10024 | tc_gen_reloc (section, fixp) |
10025 | asection *section; | |
10026 | fixS *fixp; | |
10027 | { | |
0dd2d296 | 10028 | static arelent *retval[4]; |
3d3c5039 | 10029 | arelent *reloc; |
a8aed9dd | 10030 | bfd_reloc_code_real_type code; |
3d3c5039 | 10031 | |
0dd2d296 ILT |
10032 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10033 | retval[1] = NULL; | |
3d3c5039 ILT |
10034 | |
10035 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10036 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10037 | |
10038 | if (mips_pic == EMBEDDED_PIC | |
10039 | && SWITCH_TABLE (fixp)) | |
10040 | { | |
10041 | /* For a switch table entry we use a special reloc. The addend | |
10042 | is actually the difference between the reloc address and the | |
10043 | subtrahend. */ | |
10044 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10045 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10046 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10047 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10048 | } | |
ecd4ca1c ILT |
10049 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10050 | { | |
10051 | /* We use a special addend for an internal RELLO reloc. */ | |
10052 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10053 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10054 | else | |
10055 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10056 | } | |
10057 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10058 | { | |
10059 | assert (fixp->fx_next != NULL | |
10060 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10061 | /* We use a special addend for an internal RELHI reloc. The | |
10062 | reloc is relative to the RELLO; adjust the addend | |
10063 | accordingly. */ | |
10064 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10065 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10066 | + fixp->fx_next->fx_where | |
10067 | - S_GET_VALUE (fixp->fx_subsy)); | |
10068 | else | |
10069 | reloc->addend = (fixp->fx_addnumber | |
10070 | + fixp->fx_next->fx_frag->fr_address | |
10071 | + fixp->fx_next->fx_where); | |
10072 | } | |
1c803e52 | 10073 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10074 | reloc->addend = fixp->fx_addnumber; |
10075 | else | |
5b63f465 | 10076 | { |
1dc1e798 KR |
10077 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10078 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10079 | handling. */ | |
10080 | reloc->addend = reloc->address; | |
10081 | else | |
10082 | reloc->addend = -reloc->address; | |
5b63f465 | 10083 | } |
0dd2d296 ILT |
10084 | |
10085 | /* If this is a variant frag, we may need to adjust the existing | |
10086 | reloc and generate a new one. */ | |
10087 | if (fixp->fx_frag->fr_opcode != NULL | |
10088 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10089 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10090 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10091 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10092 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10093 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10094 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10095 | { |
10096 | arelent *reloc2; | |
10097 | ||
cc5703cd ILT |
10098 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10099 | ||
0dd2d296 | 10100 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10101 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10102 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10103 | the second one handle all of them. */ | |
0dd2d296 ILT |
10104 | if (fixp->fx_next != NULL |
10105 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10106 | { | |
fb251650 ILT |
10107 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10108 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10109 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10110 | && (fixp->fx_next->fx_r_type | |
10111 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10112 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10113 | && (fixp->fx_next->fx_r_type | |
10114 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10115 | retval[0] = NULL; |
10116 | return retval; | |
10117 | } | |
10118 | ||
10119 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10120 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10121 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10122 | retval[2] = NULL; | |
10123 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10124 | reloc2->address = (reloc->address | |
10125 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10126 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10127 | reloc2->addend = fixp->fx_addnumber; | |
10128 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10129 | assert (reloc2->howto != NULL); | |
10130 | ||
10131 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10132 | { | |
10133 | arelent *reloc3; | |
10134 | ||
10135 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10136 | retval[3] = NULL; | |
10137 | *reloc3 = *reloc2; | |
10138 | reloc3->address += 4; | |
10139 | } | |
10140 | ||
d9aba805 | 10141 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10142 | { |
10143 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10144 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10145 | } | |
d9aba805 | 10146 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10147 | { |
fb251650 | 10148 | switch (fixp->fx_r_type) |
0dd2d296 | 10149 | { |
fb251650 ILT |
10150 | default: |
10151 | abort (); | |
10152 | case BFD_RELOC_MIPS_GOT16: | |
10153 | break; | |
10154 | case BFD_RELOC_MIPS_CALL16: | |
10155 | case BFD_RELOC_MIPS_GOT_LO16: | |
10156 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10157 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10158 | break; |
0dd2d296 ILT |
10159 | } |
10160 | } | |
d9aba805 ILT |
10161 | else |
10162 | abort (); | |
0dd2d296 ILT |
10163 | } |
10164 | ||
a8aed9dd ILT |
10165 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10166 | fixup_segment converted a non-PC relative reloc into a PC | |
10167 | relative reloc. In such a case, we need to convert the reloc | |
10168 | code. */ | |
10169 | code = fixp->fx_r_type; | |
10170 | if (fixp->fx_pcrel) | |
10171 | { | |
10172 | switch (code) | |
10173 | { | |
10174 | case BFD_RELOC_8: | |
10175 | code = BFD_RELOC_8_PCREL; | |
10176 | break; | |
10177 | case BFD_RELOC_16: | |
10178 | code = BFD_RELOC_16_PCREL; | |
10179 | break; | |
10180 | case BFD_RELOC_32: | |
10181 | code = BFD_RELOC_32_PCREL; | |
10182 | break; | |
bf39474f ILT |
10183 | case BFD_RELOC_64: |
10184 | code = BFD_RELOC_64_PCREL; | |
10185 | break; | |
a8aed9dd ILT |
10186 | case BFD_RELOC_8_PCREL: |
10187 | case BFD_RELOC_16_PCREL: | |
10188 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10189 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10190 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10191 | case BFD_RELOC_PCREL_HI16_S: |
10192 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10193 | break; |
10194 | default: | |
10195 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10196 | "Cannot make %s relocation PC relative", | |
10197 | bfd_get_reloc_code_name (code)); | |
10198 | } | |
10199 | } | |
10200 | ||
d9aba805 ILT |
10201 | /* To support a PC relative reloc when generating embedded PIC code |
10202 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10203 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10204 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10205 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10206 | && mips_pic != EMBEDDED_PIC) |
10207 | reloc->howto = NULL; | |
10208 | else | |
a8aed9dd | 10209 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10210 | |
52aa70b5 JW |
10211 | if (reloc->howto == NULL) |
10212 | { | |
10213 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10214 | "Can not represent %s relocation in this object file format", |
10215 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10216 | retval[0] = NULL; |
52aa70b5 | 10217 | } |
3d3c5039 | 10218 | |
0dd2d296 | 10219 | return retval; |
3d3c5039 ILT |
10220 | } |
10221 | ||
cc5703cd ILT |
10222 | /* Relax a machine dependent frag. This returns the amount by which |
10223 | the current size of the frag should change. */ | |
10224 | ||
10225 | int | |
10226 | mips_relax_frag (fragp, stretch) | |
10227 | fragS *fragp; | |
10228 | long stretch; | |
10229 | { | |
10230 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10231 | return 0; | |
10232 | ||
10233 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10234 | { | |
10235 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10236 | return 0; | |
10237 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10238 | return 2; | |
10239 | } | |
10240 | else | |
10241 | { | |
10242 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10243 | return 0; | |
10244 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10245 | return -2; | |
10246 | } | |
10247 | ||
10248 | return 0; | |
10249 | } | |
10250 | ||
0dd2d296 ILT |
10251 | /* Convert a machine dependent frag. */ |
10252 | ||
10253 | void | |
10254 | md_convert_frag (abfd, asec, fragp) | |
10255 | bfd *abfd; | |
10256 | segT asec; | |
10257 | fragS *fragp; | |
3d3c5039 | 10258 | { |
0dd2d296 ILT |
10259 | int old, new; |
10260 | char *fixptr; | |
3d3c5039 | 10261 | |
cc5703cd ILT |
10262 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10263 | { | |
10264 | int type; | |
10265 | register const struct mips16_immed_operand *op; | |
10266 | boolean small, ext; | |
10267 | offsetT val; | |
10268 | bfd_byte *buf; | |
10269 | unsigned long insn; | |
10270 | boolean use_extend; | |
10271 | unsigned short extend; | |
10272 | ||
10273 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10274 | op = mips16_immed_operands; | |
10275 | while (op->type != type) | |
10276 | ++op; | |
10277 | ||
10278 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10279 | { | |
10280 | small = false; | |
10281 | ext = true; | |
10282 | } | |
10283 | else | |
10284 | { | |
10285 | small = true; | |
10286 | ext = false; | |
10287 | } | |
10288 | ||
f74ba7a3 | 10289 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 10290 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10291 | if (op->pcrel) |
10292 | { | |
10293 | addressT addr; | |
10294 | ||
a677feeb ILT |
10295 | addr = fragp->fr_address + fragp->fr_fix; |
10296 | ||
10297 | /* The rules for the base address of a PC relative reloc are | |
10298 | complicated; see mips16_extended_frag. */ | |
10299 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10300 | { |
10301 | addr += 2; | |
319305a7 ILT |
10302 | if (ext) |
10303 | addr += 2; | |
fbcfacb7 ILT |
10304 | /* Ignore the low bit in the target, since it will be |
10305 | set for a text label. */ | |
10306 | if ((val & 1) != 0) | |
10307 | --val; | |
10308 | } | |
a677feeb ILT |
10309 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10310 | addr -= 4; | |
10311 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10312 | addr -= 2; | |
10313 | ||
cc5703cd ILT |
10314 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10315 | val -= addr; | |
a677feeb ILT |
10316 | |
10317 | /* Make sure the section winds up with the alignment we have | |
10318 | assumed. */ | |
10319 | if (op->shift > 0) | |
10320 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10321 | } |
10322 | ||
035936da ILT |
10323 | if (ext |
10324 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10325 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10326 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10327 | "extended instruction in delay slot"); | |
10328 | ||
cc5703cd ILT |
10329 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10330 | ||
b9129c6f ILT |
10331 | if (target_big_endian) |
10332 | insn = bfd_getb16 (buf); | |
10333 | else | |
10334 | insn = bfd_getl16 (buf); | |
cc5703cd | 10335 | |
31a2c6ff ILT |
10336 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10337 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10338 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10339 | |
10340 | if (use_extend) | |
10341 | { | |
10342 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10343 | fragp->fr_fix += 2; | |
10344 | buf += 2; | |
10345 | } | |
3d3c5039 | 10346 | |
cc5703cd ILT |
10347 | md_number_to_chars (buf, insn, 2); |
10348 | fragp->fr_fix += 2; | |
10349 | buf += 2; | |
10350 | } | |
10351 | else | |
10352 | { | |
10353 | if (fragp->fr_opcode == NULL) | |
10354 | return; | |
0dd2d296 | 10355 | |
cc5703cd ILT |
10356 | old = RELAX_OLD (fragp->fr_subtype); |
10357 | new = RELAX_NEW (fragp->fr_subtype); | |
10358 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10359 | |
cc5703cd ILT |
10360 | if (new > 0) |
10361 | memcpy (fixptr - old, fixptr, new); | |
10362 | ||
10363 | fragp->fr_fix += new - old; | |
10364 | } | |
0dd2d296 | 10365 | } |
becfe05e | 10366 | |
fbcfacb7 ILT |
10367 | #ifdef OBJ_ELF |
10368 | ||
10369 | /* This function is called after the relocs have been generated. | |
10370 | We've been storing mips16 text labels as odd. Here we convert them | |
10371 | back to even for the convenience of the debugger. */ | |
10372 | ||
10373 | void | |
10374 | mips_frob_file_after_relocs () | |
10375 | { | |
10376 | asymbol **syms; | |
10377 | unsigned int count, i; | |
10378 | ||
10379 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10380 | return; | |
10381 | ||
10382 | syms = bfd_get_outsymbols (stdoutput); | |
10383 | count = bfd_get_symcount (stdoutput); | |
10384 | for (i = 0; i < count; i++, syms++) | |
10385 | { | |
10386 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10387 | && ((*syms)->value & 1) != 0) | |
10388 | { | |
10389 | (*syms)->value &= ~1; | |
10390 | /* If the symbol has an odd size, it was probably computed | |
10391 | incorrectly, so adjust that as well. */ | |
10392 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10393 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10394 | } | |
10395 | } | |
10396 | } | |
10397 | ||
10398 | #endif | |
10399 | ||
becfe05e ILT |
10400 | /* This function is called whenever a label is defined. It is used |
10401 | when handling branch delays; if a branch has a label, we assume we | |
10402 | can not move it. */ | |
10403 | ||
10404 | void | |
10405 | mips_define_label (sym) | |
10406 | symbolS *sym; | |
10407 | { | |
fbcfacb7 ILT |
10408 | struct insn_label_list *l; |
10409 | ||
10410 | if (free_insn_labels == NULL) | |
10411 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10412 | else | |
10413 | { | |
10414 | l = free_insn_labels; | |
10415 | free_insn_labels = l->next; | |
10416 | } | |
10417 | ||
10418 | l->label = sym; | |
10419 | l->next = insn_labels; | |
10420 | insn_labels = l; | |
becfe05e | 10421 | } |
3d3c5039 | 10422 | \f |
739708fa | 10423 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10424 | |
0dd2d296 | 10425 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10426 | |
10427 | void | |
10428 | mips_elf_final_processing () | |
10429 | { | |
87178180 ILT |
10430 | /* Write out the register information. */ |
10431 | if (! mips_64) | |
10432 | { | |
10433 | Elf32_RegInfo s; | |
10434 | ||
10435 | s.ri_gprmask = mips_gprmask; | |
10436 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10437 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10438 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10439 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10440 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10441 | ||
10442 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10443 | ((Elf32_External_RegInfo *) | |
10444 | mips_regmask_frag)); | |
10445 | } | |
10446 | else | |
10447 | { | |
10448 | Elf64_Internal_RegInfo s; | |
10449 | ||
10450 | s.ri_gprmask = mips_gprmask; | |
10451 | s.ri_pad = 0; | |
10452 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10453 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10454 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10455 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10456 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10457 | ||
10458 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10459 | ((Elf64_External_RegInfo *) | |
10460 | mips_regmask_frag)); | |
10461 | } | |
0dd2d296 ILT |
10462 | |
10463 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10464 | sort of BFD interface for this. */ | |
10465 | if (mips_any_noreorder) | |
10466 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10467 | if (mips_pic != NO_PIC) |
0dd2d296 | 10468 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10469 | } |
10470 | ||
739708fa | 10471 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10472 | \f |
3d3c5039 ILT |
10473 | /* These functions should really be defined by the object file format, |
10474 | since they are related to debugging information. However, this | |
10475 | code has to work for the a.out format, which does not define them, | |
10476 | so we provide simple versions here. These don't actually generate | |
10477 | any debugging information, but they do simple checking and someday | |
10478 | somebody may make them useful. */ | |
10479 | ||
670a50eb ILT |
10480 | typedef struct loc |
10481 | { | |
10482 | struct loc *loc_next; | |
10483 | unsigned long loc_fileno; | |
10484 | unsigned long loc_lineno; | |
10485 | unsigned long loc_offset; | |
10486 | unsigned short loc_delta; | |
10487 | unsigned short loc_count; | |
3d3c5039 | 10488 | #if 0 |
670a50eb | 10489 | fragS *loc_frag; |
3d3c5039 | 10490 | #endif |
670a50eb ILT |
10491 | } |
10492 | locS; | |
3d3c5039 | 10493 | |
670a50eb ILT |
10494 | typedef struct proc |
10495 | { | |
3d3c5039 ILT |
10496 | struct proc *proc_next; |
10497 | struct symbol *proc_isym; | |
10498 | struct symbol *proc_end; | |
10499 | unsigned long proc_reg_mask; | |
10500 | unsigned long proc_reg_offset; | |
10501 | unsigned long proc_fpreg_mask; | |
10502 | unsigned long proc_fpreg_offset; | |
10503 | unsigned long proc_frameoffset; | |
10504 | unsigned long proc_framereg; | |
10505 | unsigned long proc_pcreg; | |
10506 | locS *proc_iline; | |
10507 | struct file *proc_file; | |
10508 | int proc_index; | |
670a50eb ILT |
10509 | } |
10510 | procS; | |
3d3c5039 | 10511 | |
670a50eb ILT |
10512 | typedef struct file |
10513 | { | |
3d3c5039 ILT |
10514 | struct file *file_next; |
10515 | unsigned long file_fileno; | |
10516 | struct symbol *file_symbol; | |
10517 | struct symbol *file_end; | |
10518 | struct proc *file_proc; | |
10519 | int file_numprocs; | |
670a50eb ILT |
10520 | } |
10521 | fileS; | |
3d3c5039 ILT |
10522 | |
10523 | static struct obstack proc_frags; | |
10524 | static procS *proc_lastP; | |
10525 | static procS *proc_rootP; | |
10526 | static int numprocs; | |
10527 | ||
10528 | static void | |
10529 | md_obj_begin () | |
10530 | { | |
670a50eb | 10531 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10532 | } |
10533 | ||
10534 | static void | |
10535 | md_obj_end () | |
10536 | { | |
10537 | /* check for premature end, nesting errors, etc */ | |
10538 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10539 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10540 | } |
10541 | ||
3d3c5039 ILT |
10542 | static long |
10543 | get_number () | |
10544 | { | |
670a50eb ILT |
10545 | int negative = 0; |
10546 | long val = 0; | |
3d3c5039 | 10547 | |
670a50eb ILT |
10548 | if (*input_line_pointer == '-') |
10549 | { | |
10550 | ++input_line_pointer; | |
10551 | negative = 1; | |
3d3c5039 | 10552 | } |
670a50eb ILT |
10553 | if (!isdigit (*input_line_pointer)) |
10554 | as_bad ("Expected simple number."); | |
10555 | if (input_line_pointer[0] == '0') | |
10556 | { | |
10557 | if (input_line_pointer[1] == 'x') | |
10558 | { | |
10559 | input_line_pointer += 2; | |
10560 | while (isxdigit (*input_line_pointer)) | |
10561 | { | |
10562 | val <<= 4; | |
3a762a0b | 10563 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10564 | } |
670a50eb ILT |
10565 | return negative ? -val : val; |
10566 | } | |
10567 | else | |
10568 | { | |
10569 | ++input_line_pointer; | |
10570 | while (isdigit (*input_line_pointer)) | |
10571 | { | |
10572 | val <<= 3; | |
10573 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10574 | } |
670a50eb | 10575 | return negative ? -val : val; |
3d3c5039 ILT |
10576 | } |
10577 | } | |
670a50eb ILT |
10578 | if (!isdigit (*input_line_pointer)) |
10579 | { | |
10580 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10581 | *input_line_pointer, *input_line_pointer); | |
10582 | as_warn ("Invalid number"); | |
10583 | return -1; | |
3d3c5039 | 10584 | } |
670a50eb ILT |
10585 | while (isdigit (*input_line_pointer)) |
10586 | { | |
10587 | val *= 10; | |
10588 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10589 | } |
670a50eb | 10590 | return negative ? -val : val; |
3d3c5039 ILT |
10591 | } |
10592 | ||
10593 | /* The .file directive; just like the usual .file directive, but there | |
10594 | is an initial number which is the ECOFF file index. */ | |
10595 | ||
10596 | static void | |
10597 | s_file (x) | |
10598 | int x; | |
10599 | { | |
670a50eb | 10600 | int line; |
3d3c5039 | 10601 | |
670a50eb | 10602 | line = get_number (); |
9a7d824a | 10603 | s_app_file (0); |
3d3c5039 ILT |
10604 | } |
10605 | ||
10606 | ||
10607 | /* The .end directive. */ | |
10608 | ||
10609 | static void | |
10610 | s_mipsend (x) | |
10611 | int x; | |
10612 | { | |
670a50eb ILT |
10613 | symbolS *p; |
10614 | ||
10615 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10616 | { | |
10617 | p = get_symbol (); | |
10618 | demand_empty_rest_of_line (); | |
10619 | } | |
10620 | else | |
10621 | p = NULL; | |
10622 | if (now_seg != text_section) | |
10623 | as_warn (".end not in text section"); | |
10624 | if (!proc_lastP) | |
10625 | { | |
10626 | as_warn (".end and no .ent seen yet."); | |
10627 | return; | |
3d3c5039 ILT |
10628 | } |
10629 | ||
670a50eb ILT |
10630 | if (p != NULL) |
10631 | { | |
10632 | assert (S_GET_NAME (p)); | |
10633 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10634 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10635 | } |
10636 | ||
670a50eb | 10637 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10638 | } |
10639 | ||
10640 | /* The .aent and .ent directives. */ | |
10641 | ||
10642 | static void | |
10643 | s_ent (aent) | |
10644 | int aent; | |
10645 | { | |
670a50eb ILT |
10646 | int number = 0; |
10647 | procS *procP; | |
10648 | symbolS *symbolP; | |
10649 | ||
10650 | symbolP = get_symbol (); | |
10651 | if (*input_line_pointer == ',') | |
10652 | input_line_pointer++; | |
dd3f1f76 | 10653 | SKIP_WHITESPACE (); |
670a50eb ILT |
10654 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10655 | number = get_number (); | |
10656 | if (now_seg != text_section) | |
10657 | as_warn (".ent or .aent not in text section."); | |
10658 | ||
10659 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10660 | as_warn ("missing `.end'"); | |
10661 | ||
10662 | if (!aent) | |
10663 | { | |
10664 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10665 | procP->proc_isym = symbolP; | |
10666 | procP->proc_reg_mask = 0; | |
10667 | procP->proc_reg_offset = 0; | |
10668 | procP->proc_fpreg_mask = 0; | |
10669 | procP->proc_fpreg_offset = 0; | |
10670 | procP->proc_frameoffset = 0; | |
10671 | procP->proc_framereg = 0; | |
10672 | procP->proc_pcreg = 0; | |
10673 | procP->proc_end = NULL; | |
10674 | procP->proc_next = NULL; | |
10675 | if (proc_lastP) | |
10676 | proc_lastP->proc_next = procP; | |
10677 | else | |
10678 | proc_rootP = procP; | |
10679 | proc_lastP = procP; | |
10680 | numprocs++; | |
3d3c5039 | 10681 | } |
670a50eb | 10682 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10683 | } |
10684 | ||
10685 | /* The .frame directive. */ | |
10686 | ||
88225433 | 10687 | #if 0 |
3d3c5039 ILT |
10688 | static void |
10689 | s_frame (x) | |
670a50eb | 10690 | int x; |
3d3c5039 | 10691 | { |
670a50eb ILT |
10692 | char str[100]; |
10693 | symbolS *symP; | |
10694 | int frame_reg; | |
10695 | int frame_off; | |
10696 | int pcreg; | |
10697 | ||
0dd2d296 | 10698 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10699 | if (*input_line_pointer == ',') |
10700 | input_line_pointer++; | |
5ac34ac3 | 10701 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10702 | if (*input_line_pointer == ',') |
10703 | input_line_pointer++; | |
0dd2d296 | 10704 | pcreg = tc_get_register (0); |
670a50eb ILT |
10705 | |
10706 | /* bob third eye */ | |
10707 | assert (proc_rootP); | |
10708 | proc_rootP->proc_framereg = frame_reg; | |
10709 | proc_rootP->proc_frameoffset = frame_off; | |
10710 | proc_rootP->proc_pcreg = pcreg; | |
10711 | /* bob macho .frame */ | |
10712 | ||
10713 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10714 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10715 | { |
10716 | if (!proc_lastP) | |
10717 | as_warn ("No .ent for .frame to use."); | |
10718 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10719 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10720 | S_SET_TYPE (symP, N_RMASK); | |
10721 | S_SET_OTHER (symP, 0); | |
10722 | S_SET_DESC (symP, 0); | |
10723 | symP->sy_forward = proc_lastP->proc_isym; | |
10724 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10725 | } |
670a50eb | 10726 | demand_empty_rest_of_line (); |
3d3c5039 | 10727 | } |
88225433 | 10728 | #endif |
3d3c5039 ILT |
10729 | |
10730 | /* The .fmask and .mask directives. */ | |
10731 | ||
88225433 | 10732 | #if 0 |
3d3c5039 ILT |
10733 | static void |
10734 | s_mask (reg_type) | |
10735 | char reg_type; | |
10736 | { | |
670a50eb ILT |
10737 | char str[100], *strP; |
10738 | symbolS *symP; | |
10739 | int i; | |
10740 | unsigned int mask; | |
10741 | int off; | |
10742 | ||
10743 | mask = get_number (); | |
10744 | if (*input_line_pointer == ',') | |
10745 | input_line_pointer++; | |
10746 | off = get_absolute_expression (); | |
10747 | ||
10748 | /* bob only for coff */ | |
10749 | assert (proc_rootP); | |
10750 | if (reg_type == 'F') | |
10751 | { | |
10752 | proc_rootP->proc_fpreg_mask = mask; | |
10753 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10754 | } |
670a50eb ILT |
10755 | else |
10756 | { | |
10757 | proc_rootP->proc_reg_mask = mask; | |
10758 | proc_rootP->proc_reg_offset = off; | |
10759 | } | |
10760 | ||
10761 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10762 | |
670a50eb ILT |
10763 | /* We don't have to write out a mask stab if no saved regs. */ |
10764 | if (!(mask == 0)) | |
10765 | { | |
10766 | if (!proc_lastP) | |
10767 | as_warn ("No .ent for .mask to use."); | |
10768 | strP = str; | |
10769 | for (i = 0; i < 32; i++) | |
10770 | { | |
10771 | if (mask % 2) | |
10772 | { | |
10773 | sprintf (strP, "%c%d,", reg_type, i); | |
10774 | strP += strlen (strP); | |
10775 | } | |
3d3c5039 | 10776 | mask /= 2; |
670a50eb ILT |
10777 | } |
10778 | sprintf (strP, ";%d,", off); | |
10779 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10780 | S_SET_TYPE (symP, N_RMASK); | |
10781 | S_SET_OTHER (symP, 0); | |
10782 | S_SET_DESC (symP, 0); | |
10783 | symP->sy_forward = proc_lastP->proc_isym; | |
10784 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10785 | } |
3d3c5039 | 10786 | } |
88225433 | 10787 | #endif |
3d3c5039 ILT |
10788 | |
10789 | /* The .loc directive. */ | |
10790 | ||
88225433 | 10791 | #if 0 |
3d3c5039 ILT |
10792 | static void |
10793 | s_loc (x) | |
10794 | int x; | |
10795 | { | |
670a50eb ILT |
10796 | symbolS *symbolP; |
10797 | int lineno; | |
10798 | int addroff; | |
3d3c5039 | 10799 | |
670a50eb | 10800 | assert (now_seg == text_section); |
3d3c5039 | 10801 | |
670a50eb | 10802 | lineno = get_number (); |
87e48495 | 10803 | addroff = frag_now_fix (); |
3d3c5039 | 10804 | |
670a50eb ILT |
10805 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10806 | S_SET_TYPE (symbolP, N_SLINE); | |
10807 | S_SET_OTHER (symbolP, 0); | |
10808 | S_SET_DESC (symbolP, lineno); | |
10809 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10810 | } |
88225433 | 10811 | #endif |