Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
e532b44c ILT |
151 | /* Whether the processor uses hardware interlocks, and thus does not |
152 | require nops to be inserted. */ | |
153 | static int interlocks = -1; | |
154 | ||
344a8d61 JSC |
155 | /* As with "interlocks" this is used by hardware that has FP |
156 | (co-processor) interlocks. */ | |
157 | static int cop_interlocks = -1; | |
158 | ||
d9aba805 ILT |
159 | /* MIPS PIC level. */ |
160 | ||
161 | enum mips_pic_level | |
162 | { | |
163 | /* Do not generate PIC code. */ | |
164 | NO_PIC, | |
165 | ||
166 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
167 | not sure what it is supposed to do. */ | |
168 | IRIX4_PIC, | |
169 | ||
170 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
171 | SVR4_PIC, | |
172 | ||
173 | /* Generate PIC code without using a global offset table: the data | |
174 | segment has a maximum size of 64K, all data references are off | |
175 | the $gp register, and all text references are PC relative. This | |
176 | is used on some embedded systems. */ | |
177 | EMBEDDED_PIC | |
178 | }; | |
179 | ||
180 | static enum mips_pic_level mips_pic; | |
9226253a | 181 | |
fb251650 ILT |
182 | /* 1 if we should generate 32 bit offsets from the GP register in |
183 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
184 | static int mips_big_got; | |
185 | ||
8ea7f4e8 ILT |
186 | /* 1 if trap instructions should used for overflow rather than break |
187 | instructions. */ | |
188 | static int mips_trap; | |
189 | ||
cc5703cd ILT |
190 | /* 1 if we should autoextend mips16 instructions. */ |
191 | static int mips16_autoextend = 1; | |
192 | ||
3d3c5039 ILT |
193 | static int mips_warn_about_macros; |
194 | static int mips_noreorder; | |
0dd2d296 | 195 | static int mips_any_noreorder; |
3d3c5039 ILT |
196 | static int mips_nomove; |
197 | static int mips_noat; | |
198 | static int mips_nobopt; | |
199 | ||
670a50eb ILT |
200 | /* The size of the small data section. */ |
201 | static int g_switch_value = 8; | |
42562568 ILT |
202 | /* Whether the -G option was used. */ |
203 | static int g_switch_seen = 0; | |
670a50eb | 204 | |
3d3c5039 ILT |
205 | #define N_RMASK 0xc4 |
206 | #define N_VFP 0xd4 | |
207 | ||
d8a1c247 KR |
208 | /* If we can determine in advance that GP optimization won't be |
209 | possible, we can skip the relaxation stuff that tries to produce | |
210 | GP-relative references. This makes delay slot optimization work | |
211 | better. | |
212 | ||
213 | This function can only provide a guess, but it seems to work for | |
214 | gcc output. If it guesses wrong, the only loss should be in | |
215 | efficiency; it shouldn't introduce any bugs. | |
216 | ||
217 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
218 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
219 | static int nopic_need_relax PARAMS ((symbolS *)); | |
220 | ||
3d3c5039 ILT |
221 | /* handle of the OPCODE hash table */ |
222 | static struct hash_control *op_hash = NULL; | |
223 | ||
cc5703cd ILT |
224 | /* The opcode hash table we use for the mips16. */ |
225 | static struct hash_control *mips16_op_hash = NULL; | |
226 | ||
3d3c5039 ILT |
227 | /* This array holds the chars that always start a comment. If the |
228 | pre-processor is disabled, these aren't very useful */ | |
229 | const char comment_chars[] = "#"; | |
230 | ||
231 | /* This array holds the chars that only start a comment at the beginning of | |
232 | a line. If the line seems to have the form '# 123 filename' | |
233 | .line and .file directives will appear in the pre-processed output */ | |
234 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
235 | first line of the input file. This is because the compiler outputs | |
236 | #NO_APP at the beginning of its output. */ | |
237 | /* Also note that C style comments are always supported. */ | |
238 | const char line_comment_chars[] = "#"; | |
239 | ||
240 | /* This array holds machine specific line separator characters. */ | |
241 | const char line_separator_chars[] = ""; | |
242 | ||
243 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
244 | const char EXP_CHARS[] = "eE"; | |
245 | ||
246 | /* Chars that mean this number is a floating point constant */ | |
247 | /* As in 0f12.456 */ | |
248 | /* or 0d1.2345e12 */ | |
249 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
250 | ||
251 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
252 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
253 | but nothing is ideal around here. | |
254 | */ | |
255 | ||
670a50eb | 256 | static char *insn_error; |
3d3c5039 | 257 | |
3d3c5039 | 258 | static int auto_align = 1; |
becfe05e | 259 | |
9226253a ILT |
260 | /* When outputting SVR4 PIC code, the assembler needs to know the |
261 | offset in the stack frame from which to restore the $gp register. | |
262 | This is set by the .cprestore pseudo-op, and saved in this | |
263 | variable. */ | |
0dd2d296 ILT |
264 | static offsetT mips_cprestore_offset = -1; |
265 | ||
266 | /* This is the register which holds the stack frame, as set by the | |
267 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
268 | static int mips_frame_reg = SP; | |
9226253a | 269 | |
becfe05e ILT |
270 | /* To output NOP instructions correctly, we need to keep information |
271 | about the previous two instructions. */ | |
272 | ||
0aa07269 ILT |
273 | /* Whether we are optimizing. The default value of 2 means to remove |
274 | unneeded NOPs and swap branch instructions when possible. A value | |
275 | of 1 means to not swap branches. A value of 0 means to always | |
276 | insert NOPs. */ | |
277 | static int mips_optimize = 2; | |
4e95866e | 278 | |
22ba90ce ILT |
279 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
280 | equivalent to seeing no -g option at all. */ | |
281 | static int mips_debug = 0; | |
282 | ||
becfe05e ILT |
283 | /* The previous instruction. */ |
284 | static struct mips_cl_insn prev_insn; | |
285 | ||
286 | /* The instruction before prev_insn. */ | |
287 | static struct mips_cl_insn prev_prev_insn; | |
288 | ||
289 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
290 | point the insn_mo field at this dummy integer. */ | |
291 | static const struct mips_opcode dummy_opcode = { 0 }; | |
292 | ||
293 | /* Non-zero if prev_insn is valid. */ | |
294 | static int prev_insn_valid; | |
295 | ||
296 | /* The frag for the previous instruction. */ | |
297 | static struct frag *prev_insn_frag; | |
298 | ||
299 | /* The offset into prev_insn_frag for the previous instruction. */ | |
300 | static long prev_insn_where; | |
301 | ||
a677feeb ILT |
302 | /* The reloc type for the previous instruction, if any. */ |
303 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
304 | ||
becfe05e ILT |
305 | /* The reloc for the previous instruction, if any. */ |
306 | static fixS *prev_insn_fixp; | |
307 | ||
308 | /* Non-zero if the previous instruction was in a delay slot. */ | |
309 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
310 | |
311 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
312 | static int prev_insn_unreordered; | |
313 | ||
cc5703cd ILT |
314 | /* Non-zero if the previous instruction uses an extend opcode (if |
315 | mips16). */ | |
316 | static int prev_insn_extended; | |
317 | ||
4e95866e ILT |
318 | /* Non-zero if the previous previous instruction was in a .set |
319 | noreorder. */ | |
320 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
321 | |
322 | /* For ECOFF and ELF, relocations against symbols are done in two | |
323 | parts, with a HI relocation and a LO relocation. Each relocation | |
324 | has only 16 bits of space to store an addend. This means that in | |
325 | order for the linker to handle carries correctly, it must be able | |
326 | to locate both the HI and the LO relocation. This means that the | |
327 | relocations must appear in order in the relocation table. | |
328 | ||
329 | In order to implement this, we keep track of each unmatched HI | |
330 | relocation. We then sort them so that they immediately precede the | |
331 | corresponding LO relocation. */ | |
332 | ||
333 | struct mips_hi_fixup | |
334 | { | |
335 | /* Next HI fixup. */ | |
336 | struct mips_hi_fixup *next; | |
337 | /* This fixup. */ | |
338 | fixS *fixp; | |
339 | /* The section this fixup is in. */ | |
340 | segT seg; | |
341 | }; | |
342 | ||
343 | /* The list of unmatched HI relocs. */ | |
344 | ||
345 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
346 | |
347 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
348 | ||
349 | #define X ILLEGAL_REG | |
350 | static const int mips32_to_16_reg_map[] = | |
351 | { | |
352 | X, X, 2, 3, 4, 5, 6, 7, | |
353 | X, X, X, X, X, X, X, X, | |
354 | 0, 1, X, X, X, X, X, X, | |
355 | X, X, X, X, X, X, X, X | |
356 | }; | |
357 | #undef X | |
358 | ||
359 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
360 | ||
361 | static const int mips16_to_32_reg_map[] = | |
362 | { | |
363 | 16, 17, 2, 3, 4, 5, 6, 7 | |
364 | }; | |
3d3c5039 | 365 | \f |
0dd2d296 ILT |
366 | /* Since the MIPS does not have multiple forms of PC relative |
367 | instructions, we do not have to do relaxing as is done on other | |
368 | platforms. However, we do have to handle GP relative addressing | |
369 | correctly, which turns out to be a similar problem. | |
370 | ||
371 | Every macro that refers to a symbol can occur in (at least) two | |
372 | forms, one with GP relative addressing and one without. For | |
373 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 374 | a macro instruction like this: |
0dd2d296 ILT |
375 | lw $4,i |
376 | If i can be addressed off the GP register (this is true if it is in | |
377 | the .sbss or .sdata section, or if it is known to be smaller than | |
378 | the -G argument) this will generate the following instruction: | |
379 | lw $4,i($gp) | |
380 | This instruction will use a GPREL reloc. If i can not be addressed | |
381 | off the GP register, the following instruction sequence will be used: | |
382 | lui $at,i | |
383 | lw $4,i($at) | |
384 | In this case the first instruction will have a HI16 reloc, and the | |
385 | second reloc will have a LO16 reloc. Both relocs will be against | |
386 | the symbol i. | |
387 | ||
388 | The issue here is that we may not know whether i is GP addressable | |
389 | until after we see the instruction that uses it. Therefore, we | |
390 | want to be able to choose the final instruction sequence only at | |
391 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 392 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
393 | end of assembly. |
394 | ||
395 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
396 | addressing in quite the same way, but the issue still arises as |
397 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
398 | |
399 | We handle these issues by actually generating both possible | |
400 | instruction sequences. The longer one is put in a frag_var with | |
401 | type rs_machine_dependent. We encode what to do with the frag in | |
402 | the subtype field. We encode (1) the number of existing bytes to | |
403 | replace, (2) the number of new bytes to use, (3) the offset from | |
404 | the start of the existing bytes to the first reloc we must generate | |
405 | (that is, the offset is applied from the start of the existing | |
406 | bytes after they are replaced by the new bytes, if any), (4) the | |
407 | offset from the start of the existing bytes to the second reloc, | |
408 | (5) whether a third reloc is needed (the third reloc is always four | |
409 | bytes after the second reloc), and (6) whether to warn if this | |
410 | variant is used (this is sometimes needed if .set nomacro or .set | |
411 | noat is in effect). All these numbers are reasonably small. | |
412 | ||
413 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
414 | ensure that delay slots are handled correctly. Fortunately, there |
415 | are a limited number of cases. When the second instruction | |
416 | sequence is generated, append_insn is directed to maintain the | |
417 | existing delay slot information, so it continues to apply to any | |
418 | code after the second instruction sequence. This means that the | |
419 | second instruction sequence must not impose any requirements not | |
420 | required by the first instruction sequence. | |
0dd2d296 ILT |
421 | |
422 | These variant frags are then handled in functions called by the | |
423 | machine independent code. md_estimate_size_before_relax returns | |
424 | the final size of the frag. md_convert_frag sets up the final form | |
425 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
426 | one if needed. */ | |
427 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
428 | ((relax_substateT) \ | |
cc5703cd | 429 | (((old) << 23) \ |
0dd2d296 ILT |
430 | | ((new) << 16) \ |
431 | | (((reloc1) + 64) << 9) \ | |
432 | | (((reloc2) + 64) << 2) \ | |
433 | | ((reloc3) ? (1 << 1) : 0) \ | |
434 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
435 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
436 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
437 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
438 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
439 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
440 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
441 | |
442 | /* For mips16 code, we use an entirely different form of relaxation. | |
443 | mips16 supports two versions of most instructions which take | |
444 | immediate values: a small one which takes some small value, and a | |
445 | larger one which takes a 16 bit value. Since branches also follow | |
446 | this pattern, relaxing these values is required. | |
447 | ||
448 | We can assemble both mips16 and normal MIPS code in a single | |
449 | object. Therefore, we need to support this type of relaxation at | |
450 | the same time that we support the relaxation described above. We | |
451 | use the high bit of the subtype field to distinguish these cases. | |
452 | ||
a677feeb ILT |
453 | The information we store for this type of relaxation is the |
454 | argument code found in the opcode file for this relocation, whether | |
455 | the user explicitly requested a small or extended form, and whether | |
456 | the relocation is in a jump or jal delay slot. That tells us the | |
457 | size of the value, and how it should be stored. We also store | |
458 | whether the fragment is considered to be extended or not. We also | |
459 | store whether this is known to be a branch to a different section, | |
460 | whether we have tried to relax this frag yet, and whether we have | |
461 | ever extended a PC relative fragment because of a shift count. */ | |
462 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
463 | (0x80000000 \ | |
464 | | ((type) & 0xff) \ | |
465 | | ((small) ? 0x100 : 0) \ | |
466 | | ((ext) ? 0x200 : 0) \ | |
467 | | ((dslot) ? 0x400 : 0) \ | |
468 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
469 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
470 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
471 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
472 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
473 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
474 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
475 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
476 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
477 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
478 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
479 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
480 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 481 | \f |
3d3c5039 ILT |
482 | /* Prototypes for static functions. */ |
483 | ||
484 | #ifdef __STDC__ | |
485 | #define internalError() \ | |
486 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
487 | #else | |
488 | #define internalError() as_fatal ("MIPS internal Error"); | |
489 | #endif | |
490 | ||
cc5703cd ILT |
491 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
492 | ||
becfe05e | 493 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 494 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 495 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
496 | static void append_insn PARAMS ((char *place, |
497 | struct mips_cl_insn * ip, | |
670a50eb | 498 | expressionS * p, |
867a58b3 ILT |
499 | bfd_reloc_code_real_type r, |
500 | boolean)); | |
becfe05e | 501 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 502 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 503 | #ifdef USE_STDARG |
0dd2d296 | 504 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
505 | const char *name, const char *fmt, |
506 | ...)); | |
c625fc23 JSC |
507 | #else |
508 | static void macro_build (); | |
509 | #endif | |
cc5703cd ILT |
510 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
511 | const char *, const char *, | |
512 | va_list)); | |
0dd2d296 ILT |
513 | static void macro_build_lui PARAMS ((char *place, int *counter, |
514 | expressionS * ep, int regnum)); | |
6e8dda9c | 515 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 516 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 517 | expressionS *)); |
d8a1c247 | 518 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 519 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 520 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 521 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
522 | #ifdef LOSING_COMPILER |
523 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
524 | #endif | |
670a50eb | 525 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 526 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
527 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
528 | boolean, boolean, unsigned long *, | |
529 | boolean *, unsigned short *)); | |
670a50eb ILT |
530 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
531 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 532 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 533 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
534 | static void s_align PARAMS ((int)); |
535 | static void s_change_sec PARAMS ((int)); | |
536 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 537 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 538 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
539 | static void s_option PARAMS ((int)); |
540 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
541 | static void s_abicalls PARAMS ((int)); |
542 | static void s_cpload PARAMS ((int)); | |
543 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
544 | static void s_gpword PARAMS ((int)); |
545 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
546 | static void md_obj_begin PARAMS ((void)); |
547 | static void md_obj_end PARAMS ((void)); | |
548 | static long get_number PARAMS ((void)); | |
549 | static void s_ent PARAMS ((int)); | |
550 | static void s_mipsend PARAMS ((int)); | |
551 | static void s_file PARAMS ((int)); | |
cc5703cd | 552 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
553 | \f |
554 | /* Pseudo-op table. | |
555 | ||
556 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
557 | should be defined here, but are currently unsupported: .alias, | |
558 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
559 | ||
560 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
561 | specific to the type of debugging information being generated, and | |
562 | should be defined by the object format: .aent, .begin, .bend, | |
563 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
564 | .vreg. | |
565 | ||
566 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
567 | not MIPS CPU specific, but are also not specific to the object file | |
568 | format. This file is probably the best place to define them, but | |
569 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
570 | .struct, .weakext. */ | |
571 | ||
739708fa | 572 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 573 | { |
670a50eb ILT |
574 | /* MIPS specific pseudo-ops. */ |
575 | {"option", s_option, 0}, | |
576 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
577 | {"rdata", s_change_sec, 'r'}, |
578 | {"sdata", s_change_sec, 's'}, | |
579 | {"livereg", s_ignore, 0}, | |
739708fa KR |
580 | {"abicalls", s_abicalls, 0}, |
581 | {"cpload", s_cpload, 0}, | |
582 | {"cprestore", s_cprestore, 0}, | |
583 | {"gpword", s_gpword, 0}, | |
584 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 585 | |
670a50eb | 586 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 587 | chips. */ |
739708fa | 588 | {"asciiz", stringer, 1}, |
670a50eb ILT |
589 | {"bss", s_change_sec, 'b'}, |
590 | {"err", s_err, 0}, | |
591 | {"half", s_cons, 1}, | |
52aa70b5 | 592 | {"dword", s_cons, 3}, |
3d3c5039 | 593 | |
670a50eb | 594 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 595 | here for one reason or another. */ |
670a50eb ILT |
596 | {"align", s_align, 0}, |
597 | {"byte", s_cons, 0}, | |
598 | {"data", s_change_sec, 'd'}, | |
becfe05e | 599 | {"double", s_float_cons, 'd'}, |
becfe05e | 600 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
601 | {"globl", s_mips_globl, 0}, |
602 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
603 | {"hword", s_cons, 1}, |
604 | {"int", s_cons, 2}, | |
605 | {"long", s_cons, 2}, | |
606 | {"octa", s_cons, 4}, | |
607 | {"quad", s_cons, 3}, | |
608 | {"short", s_cons, 1}, | |
609 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
610 | {"text", s_change_sec, 't'}, |
611 | {"word", s_cons, 2}, | |
739708fa KR |
612 | { 0 }, |
613 | }; | |
3d3c5039 | 614 | |
739708fa | 615 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 616 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 617 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 618 | {"aent", s_ent, 1}, |
9226253a | 619 | {"bgnb", s_ignore, 0}, |
670a50eb | 620 | {"end", s_mipsend, 0}, |
9226253a | 621 | {"endb", s_ignore, 0}, |
670a50eb ILT |
622 | {"ent", s_ent, 0}, |
623 | {"file", s_file, 0}, | |
624 | {"fmask", s_ignore, 'F'}, | |
625 | {"frame", s_ignore, 0}, | |
626 | {"loc", s_ignore, 0}, | |
627 | {"mask", s_ignore, 'R'}, | |
628 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
629 | { 0 }, |
630 | }; | |
61420a20 | 631 | |
739708fa KR |
632 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
633 | ||
634 | void | |
635 | mips_pop_insert () | |
636 | { | |
637 | pop_insert (mips_pseudo_table); | |
638 | if (! ECOFF_DEBUGGING) | |
639 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 640 | } |
3d3c5039 | 641 | \f |
fbcfacb7 ILT |
642 | /* Symbols labelling the current insn. */ |
643 | ||
644 | struct insn_label_list | |
645 | { | |
646 | struct insn_label_list *next; | |
647 | symbolS *label; | |
648 | }; | |
649 | ||
650 | static struct insn_label_list *insn_labels; | |
651 | static struct insn_label_list *free_insn_labels; | |
652 | ||
653 | static void mips_clear_insn_labels PARAMS ((void)); | |
654 | ||
655 | static inline void | |
656 | mips_clear_insn_labels () | |
657 | { | |
658 | register struct insn_label_list **pl; | |
659 | ||
660 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
661 | ; | |
662 | *pl = insn_labels; | |
663 | insn_labels = NULL; | |
664 | } | |
665 | \f | |
3d3c5039 ILT |
666 | static char *expr_end; |
667 | ||
867a58b3 ILT |
668 | /* Expressions which appear in instructions. These are set by |
669 | mips_ip. */ | |
670 | ||
3d3c5039 ILT |
671 | static expressionS imm_expr; |
672 | static expressionS offset_expr; | |
867a58b3 ILT |
673 | |
674 | /* Relocs associated with imm_expr and offset_expr. */ | |
675 | ||
3d3c5039 ILT |
676 | static bfd_reloc_code_real_type imm_reloc; |
677 | static bfd_reloc_code_real_type offset_reloc; | |
678 | ||
867a58b3 ILT |
679 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
680 | ||
681 | static boolean imm_unmatched_hi; | |
682 | ||
8728fa92 ILT |
683 | /* These are set by mips16_ip if an explicit extension is used. */ |
684 | ||
685 | static boolean mips16_small, mips16_ext; | |
686 | ||
3d3c5039 ILT |
687 | /* |
688 | * This function is called once, at assembler startup time. It should | |
689 | * set up all the tables, etc. that the MD part of the assembler will need. | |
690 | */ | |
691 | void | |
670a50eb | 692 | md_begin () |
3d3c5039 | 693 | { |
0dd2d296 | 694 | boolean ok = false; |
604633ae | 695 | register const char *retval = NULL; |
670a50eb | 696 | register unsigned int i = 0; |
3d3c5039 | 697 | |
8358c818 ILT |
698 | if (mips_isa == -1) |
699 | { | |
8c63448a ILT |
700 | const char *cpu; |
701 | char *a = NULL; | |
702 | ||
703 | cpu = TARGET_CPU; | |
704 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
705 | { | |
706 | a = xmalloc (sizeof TARGET_CPU); | |
707 | strcpy (a, TARGET_CPU); | |
708 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
709 | cpu = a; | |
710 | } | |
711 | ||
712 | if (strcmp (cpu, "mips") == 0) | |
713 | { | |
714 | mips_isa = 1; | |
4bb0cc41 ILT |
715 | if (mips_cpu == -1) |
716 | mips_cpu = 3000; | |
8c63448a ILT |
717 | } |
718 | else if (strcmp (cpu, "r6000") == 0 | |
719 | || strcmp (cpu, "mips2") == 0) | |
720 | { | |
721 | mips_isa = 2; | |
4bb0cc41 ILT |
722 | if (mips_cpu == -1) |
723 | mips_cpu = 6000; | |
8c63448a ILT |
724 | } |
725 | else if (strcmp (cpu, "mips64") == 0 | |
726 | || strcmp (cpu, "r4000") == 0 | |
727 | || strcmp (cpu, "mips3") == 0) | |
728 | { | |
729 | mips_isa = 3; | |
4bb0cc41 ILT |
730 | if (mips_cpu == -1) |
731 | mips_cpu = 4000; | |
8c63448a ILT |
732 | } |
733 | else if (strcmp (cpu, "r4400") == 0) | |
734 | { | |
735 | mips_isa = 3; | |
4bb0cc41 ILT |
736 | if (mips_cpu == -1) |
737 | mips_cpu = 4400; | |
8c63448a ILT |
738 | } |
739 | else if (strcmp (cpu, "mips64orion") == 0 | |
740 | || strcmp (cpu, "r4600") == 0) | |
741 | { | |
742 | mips_isa = 3; | |
4bb0cc41 ILT |
743 | if (mips_cpu == -1) |
744 | mips_cpu = 4600; | |
8c63448a | 745 | } |
b2b8c24e ILT |
746 | else if (strcmp (cpu, "r4650") == 0) |
747 | { | |
748 | mips_isa = 3; | |
749 | if (mips_cpu == -1) | |
750 | mips_cpu = 4650; | |
751 | if (mips_4650 == -1) | |
752 | mips_4650 = 1; | |
753 | } | |
c625fc23 JSC |
754 | else if (strcmp (cpu, "mips64vr4300") == 0) |
755 | { | |
756 | mips_isa = 3; | |
757 | if (mips_cpu == -1) | |
758 | mips_cpu = 4300; | |
759 | } | |
760 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
761 | { | |
762 | mips_isa = 3; | |
763 | if (mips_cpu == -1) | |
764 | mips_cpu = 4100; | |
765 | if (mips_4100 == -1) | |
766 | mips_4100 = 1; | |
767 | } | |
e532b44c ILT |
768 | else if (strcmp (cpu, "r4010") == 0) |
769 | { | |
770 | mips_isa = 2; | |
771 | if (mips_cpu == -1) | |
772 | mips_cpu = 4010; | |
773 | if (mips_4010 == -1) | |
774 | mips_4010 = 1; | |
775 | } | |
517078c1 ILT |
776 | else if (strcmp (cpu, "r5000") == 0 |
777 | || strcmp (cpu, "mips64vr5000") == 0) | |
778 | { | |
779 | mips_isa = 4; | |
780 | if (mips_cpu == -1) | |
781 | mips_cpu = 5000; | |
782 | } | |
d8a1c247 KR |
783 | else if (strcmp (cpu, "r8000") == 0 |
784 | || strcmp (cpu, "mips4") == 0) | |
785 | { | |
786 | mips_isa = 4; | |
787 | if (mips_cpu == -1) | |
788 | mips_cpu = 8000; | |
789 | } | |
790 | else if (strcmp (cpu, "r10000") == 0) | |
791 | { | |
792 | mips_isa = 4; | |
793 | if (mips_cpu == -1) | |
794 | mips_cpu = 10000; | |
795 | } | |
cc5703cd ILT |
796 | else if (strcmp (cpu, "mips16") == 0) |
797 | { | |
798 | mips_isa = 3; | |
799 | if (mips_cpu == -1) | |
800 | mips_cpu = 0; /* FIXME */ | |
801 | } | |
8358c818 | 802 | else |
8c63448a ILT |
803 | { |
804 | mips_isa = 1; | |
4bb0cc41 ILT |
805 | if (mips_cpu == -1) |
806 | mips_cpu = 3000; | |
8c63448a ILT |
807 | } |
808 | ||
809 | if (a != NULL) | |
810 | free (a); | |
8358c818 ILT |
811 | } |
812 | ||
cc5703cd ILT |
813 | if (mips16 < 0) |
814 | { | |
815 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
816 | mips16 = 1; | |
817 | else | |
818 | mips16 = 0; | |
819 | } | |
820 | ||
b2b8c24e ILT |
821 | if (mips_4650 < 0) |
822 | mips_4650 = 0; | |
823 | ||
e532b44c ILT |
824 | if (mips_4010 < 0) |
825 | mips_4010 = 0; | |
826 | ||
c625fc23 JSC |
827 | if (mips_4100 < 0) |
828 | mips_4100 = 0; | |
829 | ||
c36a90ef | 830 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
831 | interlocks = 1; |
832 | else | |
833 | interlocks = 0; | |
834 | ||
ca296aab | 835 | if (mips_cpu == 4300) |
344a8d61 JSC |
836 | cop_interlocks = 1; |
837 | else | |
838 | cop_interlocks = 0; | |
839 | ||
8ea7f4e8 ILT |
840 | if (mips_isa < 2 && mips_trap) |
841 | as_bad ("trap exception not supported at ISA 1"); | |
842 | ||
97f99d11 ILT |
843 | switch (mips_isa) |
844 | { | |
845 | case 1: | |
846 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
847 | break; | |
848 | case 2: | |
849 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
850 | break; | |
851 | case 3: | |
852 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
853 | break; | |
d8a1c247 KR |
854 | case 4: |
855 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
856 | break; | |
97f99d11 ILT |
857 | } |
858 | if (! ok) | |
859 | as_warn ("Could not set architecture and machine"); | |
860 | ||
1051c97f ILT |
861 | file_mips_isa = mips_isa; |
862 | ||
13fe1379 ILT |
863 | op_hash = hash_new (); |
864 | ||
670a50eb ILT |
865 | for (i = 0; i < NUMOPCODES;) |
866 | { | |
867 | const char *name = mips_opcodes[i].name; | |
868 | ||
604633ae | 869 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 870 | if (retval != NULL) |
670a50eb ILT |
871 | { |
872 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
873 | mips_opcodes[i].name, retval); | |
874 | as_fatal ("Broken assembler. No assembly attempted."); | |
875 | } | |
876 | do | |
877 | { | |
8358c818 ILT |
878 | if (mips_opcodes[i].pinfo != INSN_MACRO |
879 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
880 | != mips_opcodes[i].match)) | |
670a50eb ILT |
881 | { |
882 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
883 | mips_opcodes[i].name, mips_opcodes[i].args); | |
884 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 885 | } |
670a50eb ILT |
886 | ++i; |
887 | } | |
888 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
889 | } |
890 | ||
cc5703cd ILT |
891 | mips16_op_hash = hash_new (); |
892 | ||
893 | i = 0; | |
894 | while (i < bfd_mips16_num_opcodes) | |
895 | { | |
896 | const char *name = mips16_opcodes[i].name; | |
897 | ||
898 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
899 | if (retval != NULL) | |
900 | as_fatal ("internal error: can't hash `%s': %s\n", | |
901 | mips16_opcodes[i].name, retval); | |
902 | do | |
903 | { | |
904 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
905 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
906 | != mips16_opcodes[i].match)) | |
907 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
908 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
909 | ++i; | |
910 | } | |
911 | while (i < bfd_mips16_num_opcodes | |
912 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
913 | } | |
914 | ||
becfe05e ILT |
915 | mips_no_prev_insn (); |
916 | ||
1aa6938e ILT |
917 | mips_gprmask = 0; |
918 | mips_cprmask[0] = 0; | |
919 | mips_cprmask[1] = 0; | |
920 | mips_cprmask[2] = 0; | |
921 | mips_cprmask[3] = 0; | |
922 | ||
8358c818 | 923 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 924 | record_alignment (text_section, 2); |
8358c818 | 925 | |
1dc1e798 KR |
926 | if (USE_GLOBAL_POINTER_OPT) |
927 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 928 | |
1dc1e798 KR |
929 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
930 | { | |
08e17202 ILT |
931 | /* On a native system, sections must be aligned to 16 byte |
932 | boundaries. When configured for an embedded ELF target, we | |
933 | don't bother. */ | |
934 | if (strcmp (TARGET_OS, "elf") != 0) | |
935 | { | |
936 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
937 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
938 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
939 | } | |
1dc1e798 KR |
940 | |
941 | /* Create a .reginfo section for register masks and a .mdebug | |
942 | section for debugging information. */ | |
943 | { | |
944 | segT seg; | |
945 | subsegT subseg; | |
946 | segT sec; | |
947 | ||
948 | seg = now_seg; | |
949 | subseg = now_subseg; | |
1dc1e798 | 950 | |
87178180 ILT |
951 | if (! mips_64) |
952 | { | |
953 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 954 | |
87178180 ILT |
955 | /* The ABI says this section should be loaded so that the |
956 | running program can access it. */ | |
957 | (void) bfd_set_section_flags (stdoutput, sec, | |
958 | (SEC_ALLOC | SEC_LOAD | |
959 | | SEC_READONLY | SEC_DATA)); | |
960 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
961 | ||
f2a663d3 | 962 | #ifdef OBJ_ELF |
87178180 | 963 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 964 | #endif |
87178180 ILT |
965 | } |
966 | else | |
967 | { | |
968 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
969 | .reginfo section. */ | |
970 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
971 | (void) bfd_set_section_flags (stdoutput, sec, | |
972 | (SEC_ALLOC | SEC_LOAD | |
973 | | SEC_READONLY | SEC_DATA)); | |
974 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
975 | ||
976 | #ifdef OBJ_ELF | |
977 | /* Set up the option header. */ | |
978 | { | |
979 | Elf_Internal_Options opthdr; | |
980 | char *f; | |
981 | ||
982 | opthdr.kind = ODK_REGINFO; | |
983 | opthdr.size = (sizeof (Elf_External_Options) | |
984 | + sizeof (Elf64_External_RegInfo)); | |
985 | opthdr.section = 0; | |
986 | opthdr.info = 0; | |
987 | f = frag_more (sizeof (Elf_External_Options)); | |
988 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
989 | (Elf_External_Options *) f); | |
990 | ||
991 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
992 | } | |
993 | #endif | |
994 | } | |
f2a663d3 | 995 | |
739708fa KR |
996 | if (ECOFF_DEBUGGING) |
997 | { | |
998 | sec = subseg_new (".mdebug", (subsegT) 0); | |
999 | (void) bfd_set_section_flags (stdoutput, sec, | |
1000 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1001 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1002 | } | |
0dd2d296 | 1003 | |
1dc1e798 KR |
1004 | subseg_set (seg, subseg); |
1005 | } | |
1006 | } | |
f2a663d3 | 1007 | |
739708fa KR |
1008 | if (! ECOFF_DEBUGGING) |
1009 | md_obj_begin (); | |
3d3c5039 ILT |
1010 | } |
1011 | ||
1012 | void | |
13fe1379 | 1013 | md_mips_end () |
3d3c5039 | 1014 | { |
739708fa KR |
1015 | if (! ECOFF_DEBUGGING) |
1016 | md_obj_end (); | |
3d3c5039 ILT |
1017 | } |
1018 | ||
1019 | void | |
670a50eb ILT |
1020 | md_assemble (str) |
1021 | char *str; | |
3d3c5039 | 1022 | { |
670a50eb | 1023 | struct mips_cl_insn insn; |
3d3c5039 | 1024 | |
5ac34ac3 | 1025 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1026 | imm_reloc = BFD_RELOC_UNUSED; |
1027 | imm_unmatched_hi = false; | |
5ac34ac3 | 1028 | offset_expr.X_op = O_absent; |
867a58b3 | 1029 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1030 | |
cc5703cd ILT |
1031 | if (mips16) |
1032 | mips16_ip (str, &insn); | |
1033 | else | |
1034 | mips_ip (str, &insn); | |
1035 | ||
670a50eb ILT |
1036 | if (insn_error) |
1037 | { | |
1038 | as_bad ("%s `%s'", insn_error, str); | |
1039 | return; | |
1040 | } | |
cc5703cd | 1041 | |
670a50eb ILT |
1042 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1043 | { | |
cc5703cd ILT |
1044 | if (mips16) |
1045 | mips16_macro (&insn); | |
1046 | else | |
1047 | macro (&insn); | |
3d3c5039 | 1048 | } |
670a50eb ILT |
1049 | else |
1050 | { | |
5ac34ac3 | 1051 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1052 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1053 | imm_unmatched_hi); | |
5ac34ac3 | 1054 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1055 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1056 | else |
867a58b3 | 1057 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1058 | } |
1059 | } | |
1060 | ||
cc5703cd ILT |
1061 | /* See whether instruction IP reads register REG. CLASS is the type |
1062 | of register. */ | |
becfe05e ILT |
1063 | |
1064 | static int | |
cc5703cd | 1065 | insn_uses_reg (ip, reg, class) |
becfe05e | 1066 | struct mips_cl_insn *ip; |
604633ae | 1067 | unsigned int reg; |
cc5703cd | 1068 | enum mips_regclass class; |
becfe05e | 1069 | { |
cc5703cd ILT |
1070 | if (class == MIPS16_REG) |
1071 | { | |
1072 | assert (mips16); | |
1073 | reg = mips16_to_32_reg_map[reg]; | |
1074 | class = MIPS_GR_REG; | |
1075 | } | |
1076 | ||
becfe05e | 1077 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1078 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1079 | return 0; |
1080 | ||
cc5703cd | 1081 | if (class == MIPS_FP_REG) |
becfe05e | 1082 | { |
cc5703cd | 1083 | assert (! mips16); |
becfe05e ILT |
1084 | /* If we are called with either $f0 or $f1, we must check $f0. |
1085 | This is not optimal, because it will introduce an unnecessary | |
1086 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1087 | need to distinguish reading both $f0 and $f1 or just one of | |
1088 | them. Note that we don't have to check the other way, | |
1089 | because there is no instruction that sets both $f0 and $f1 | |
1090 | and requires a delay. */ | |
1091 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1092 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1093 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1094 | return 1; |
1095 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1096 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1097 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1098 | return 1; |
1099 | } | |
cc5703cd | 1100 | else if (! mips16) |
becfe05e ILT |
1101 | { |
1102 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1103 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1104 | return 1; | |
1105 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1106 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1107 | return 1; | |
1108 | } | |
cc5703cd ILT |
1109 | else |
1110 | { | |
1111 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1112 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1113 | return 1; | |
1114 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1115 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1116 | return 1; | |
1117 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1118 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1119 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1120 | return 1; | |
1121 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1122 | return 1; | |
1123 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1124 | return 1; | |
1125 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1126 | return 1; | |
1127 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1128 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1129 | & MIPS16OP_MASK_REGR32) == reg) | |
1130 | return 1; | |
1131 | } | |
becfe05e ILT |
1132 | |
1133 | return 0; | |
1134 | } | |
1135 | ||
fb251650 ILT |
1136 | /* This function returns true if modifying a register requires a |
1137 | delay. */ | |
1138 | ||
1139 | static int | |
1140 | reg_needs_delay (reg) | |
1141 | int reg; | |
1142 | { | |
1143 | unsigned long prev_pinfo; | |
1144 | ||
1145 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1146 | if (! mips_noreorder | |
1147 | && mips_isa < 4 | |
1148 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1149 | || (mips_isa < 2 | |
1150 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1151 | { | |
1152 | /* A load from a coprocessor or from memory. All load | |
1153 | delays delay the use of general register rt for one | |
1154 | instruction on the r3000. The r6000 and r4000 use | |
1155 | interlocks. */ | |
1156 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1157 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1158 | return 1; | |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
0dd2d296 ILT |
1164 | /* Output an instruction. PLACE is where to put the instruction; if |
1165 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1166 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1167 | used with RELOC_TYPE. */ | |
3d3c5039 | 1168 | |
3d3c5039 | 1169 | static void |
867a58b3 | 1170 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1171 | char *place; |
670a50eb ILT |
1172 | struct mips_cl_insn *ip; |
1173 | expressionS *address_expr; | |
1174 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1175 | boolean unmatched_hi; |
3d3c5039 | 1176 | { |
1aa6938e | 1177 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1178 | char *f; |
becfe05e ILT |
1179 | fixS *fixp; |
1180 | int nops = 0; | |
3d3c5039 | 1181 | |
fbcfacb7 ILT |
1182 | /* Mark instruction labels in mips16 mode. This permits the linker |
1183 | to handle them specially, such as generating jalx instructions | |
1184 | when needed. We also make them odd for the duration of the | |
1185 | assembly, in order to generate the right sort of code. We will | |
1186 | make them even in the adjust_symtab routine, while leaving them | |
1187 | marked. This is convenient for the debugger and the | |
1188 | disassembler. The linker knows to make them odd again. */ | |
1189 | if (mips16) | |
1190 | { | |
1191 | struct insn_label_list *l; | |
1192 | ||
1193 | for (l = insn_labels; l != NULL; l = l->next) | |
1194 | { | |
1195 | #ifdef S_SET_OTHER | |
1196 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1197 | S_SET_OTHER (l->label, STO_MIPS16); | |
1198 | #endif | |
1199 | ++l->label->sy_value.X_add_number; | |
1200 | } | |
1201 | } | |
1202 | ||
1aa6938e ILT |
1203 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1204 | pinfo = ip->insn_mo->pinfo; | |
1205 | ||
0dd2d296 | 1206 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1207 | { |
1208 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1209 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1210 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1211 | (1) a load from memory delay |
1212 | (2) a load from a coprocessor delay | |
1213 | (3) an unconditional branch delay | |
1214 | (4) a conditional branch delay | |
1215 | (5) a move to coprocessor register delay | |
1216 | (6) a load coprocessor register from memory delay | |
1217 | (7) a coprocessor condition code delay | |
1218 | (8) a HI/LO special register delay | |
becfe05e ILT |
1219 | |
1220 | There are a lot of optimizations we could do that we don't. | |
1221 | In particular, we do not, in general, reorder instructions. | |
1222 | If you use gcc with optimization, it will reorder | |
1223 | instructions and generally do much more optimization then we | |
1224 | do here; repeating all that work in the assembler would only | |
1225 | benefit hand written assembly code, and does not seem worth | |
1226 | it. */ | |
1227 | ||
1228 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1229 | #define emit_nop() \ |
1230 | (mips16 \ | |
1231 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1232 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1233 | |
1234 | /* The previous insn might require a delay slot, depending upon | |
1235 | the contents of the current insn. */ | |
cc5703cd ILT |
1236 | if (! mips16 |
1237 | && mips_isa < 4 | |
5af96dce ILT |
1238 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1239 | && ! cop_interlocks) | |
d8a1c247 KR |
1240 | || (mips_isa < 2 |
1241 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1242 | { |
1243 | /* A load from a coprocessor or from memory. All load | |
1244 | delays delay the use of general register rt for one | |
1245 | instruction on the r3000. The r6000 and r4000 use | |
1246 | interlocks. */ | |
1aa6938e | 1247 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1248 | if (mips_optimize == 0 |
1249 | || insn_uses_reg (ip, | |
1250 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1251 | & OP_MASK_RT), | |
cc5703cd | 1252 | MIPS_GR_REG)) |
becfe05e ILT |
1253 | ++nops; |
1254 | } | |
cc5703cd ILT |
1255 | else if (! mips16 |
1256 | && mips_isa < 4 | |
5af96dce ILT |
1257 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1258 | && ! cop_interlocks) | |
d8a1c247 KR |
1259 | || (mips_isa < 2 |
1260 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1261 | { |
1262 | /* A generic coprocessor delay. The previous instruction | |
1263 | modified a coprocessor general or control register. If | |
1264 | it modified a control register, we need to avoid any | |
1265 | coprocessor instruction (this is probably not always | |
1266 | required, but it sometimes is). If it modified a general | |
1267 | register, we avoid using that register. | |
1268 | ||
8358c818 ILT |
1269 | On the r6000 and r4000 loading a coprocessor register |
1270 | from memory is interlocked, and does not require a delay. | |
1271 | ||
becfe05e ILT |
1272 | This case is not handled very well. There is no special |
1273 | knowledge of CP0 handling, and the coprocessors other | |
1274 | than the floating point unit are not distinguished at | |
1275 | all. */ | |
1aa6938e | 1276 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1277 | { |
0aa07269 ILT |
1278 | if (mips_optimize == 0 |
1279 | || insn_uses_reg (ip, | |
8358c818 ILT |
1280 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1281 | & OP_MASK_FT), | |
cc5703cd | 1282 | MIPS_FP_REG)) |
becfe05e ILT |
1283 | ++nops; |
1284 | } | |
1aa6938e | 1285 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1286 | { |
0aa07269 ILT |
1287 | if (mips_optimize == 0 |
1288 | || insn_uses_reg (ip, | |
8358c818 ILT |
1289 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1290 | & OP_MASK_FS), | |
cc5703cd | 1291 | MIPS_FP_REG)) |
becfe05e ILT |
1292 | ++nops; |
1293 | } | |
1294 | else | |
1295 | { | |
1296 | /* We don't know exactly what the previous instruction | |
1297 | does. If the current instruction uses a coprocessor | |
1298 | register, we must insert a NOP. If previous | |
1299 | instruction may set the condition codes, and the | |
1300 | current instruction uses them, we must insert two | |
1301 | NOPS. */ | |
0aa07269 | 1302 | if (mips_optimize == 0 |
1aa6938e ILT |
1303 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1304 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1305 | nops += 2; |
1aa6938e | 1306 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1307 | ++nops; |
1308 | } | |
1309 | } | |
cc5703cd ILT |
1310 | else if (! mips16 |
1311 | && mips_isa < 4 | |
344a8d61 JSC |
1312 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1313 | && ! cop_interlocks) | |
becfe05e ILT |
1314 | { |
1315 | /* The previous instruction sets the coprocessor condition | |
1316 | codes, but does not require a general coprocessor delay | |
1317 | (this means it is a floating point comparison | |
1318 | instruction). If this instruction uses the condition | |
1319 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1320 | if (mips_optimize == 0 |
1aa6938e | 1321 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1322 | ++nops; |
1323 | } | |
1aa6938e | 1324 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1325 | { |
1326 | /* The previous instruction reads the LO register; if the | |
1327 | current instruction writes to the LO register, we must | |
517078c1 | 1328 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1329 | if (! interlocks |
b2b8c24e ILT |
1330 | && (mips_optimize == 0 |
1331 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1332 | nops += 2; |
1333 | } | |
1334 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1335 | { | |
1336 | /* The previous instruction reads the HI register; if the | |
1337 | current instruction writes to the HI register, we must | |
517078c1 | 1338 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1339 | if (! interlocks |
b2b8c24e ILT |
1340 | && (mips_optimize == 0 |
1341 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1342 | nops += 2; |
1343 | } | |
1344 | ||
1345 | /* There are two cases which require two intervening | |
1346 | instructions: 1) setting the condition codes using a move to | |
1347 | coprocessor instruction which requires a general coprocessor | |
1348 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1349 | or LO register and then writing to it (except on processors |
1350 | which have interlocks). If we are not already emitting a NOP | |
1351 | instruction, we must check for these cases compared to the | |
1352 | instruction previous to the previous instruction. */ | |
becfe05e | 1353 | if (nops == 0 |
cc5703cd ILT |
1354 | && ((! mips16 |
1355 | && mips_isa < 4 | |
d8a1c247 | 1356 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1357 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1358 | && (pinfo & INSN_READ_COND_CODE) |
1359 | && ! cop_interlocks) | |
becfe05e | 1360 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1361 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1362 | && ! interlocks) |
becfe05e | 1363 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1364 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1365 | && ! interlocks))) |
becfe05e ILT |
1366 | ++nops; |
1367 | ||
0dd2d296 ILT |
1368 | /* If we are being given a nop instruction, don't bother with |
1369 | one of the nops we would otherwise output. This will only | |
1370 | happen when a nop instruction is used with mips_optimize set | |
1371 | to 0. */ | |
cc5703cd | 1372 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1373 | --nops; |
1374 | ||
becfe05e ILT |
1375 | /* Now emit the right number of NOP instructions. */ |
1376 | if (nops > 0) | |
1377 | { | |
5af96dce ILT |
1378 | fragS *old_frag; |
1379 | unsigned long old_frag_offset; | |
8c63448a | 1380 | int i; |
fbcfacb7 | 1381 | struct insn_label_list *l; |
8c63448a | 1382 | |
5af96dce ILT |
1383 | old_frag = frag_now; |
1384 | old_frag_offset = frag_now_fix (); | |
1385 | ||
8c63448a | 1386 | for (i = 0; i < nops; i++) |
becfe05e | 1387 | emit_nop (); |
5af96dce | 1388 | |
af255ca0 | 1389 | if (listing) |
546f5536 ILT |
1390 | { |
1391 | listing_prev_line (); | |
1392 | /* We may be at the start of a variant frag. In case we | |
1393 | are, make sure there is enough space for the frag | |
1394 | after the frags created by listing_prev_line. The | |
1395 | argument to frag_grow here must be at least as large | |
1396 | as the argument to all other calls to frag_grow in | |
1397 | this file. We don't have to worry about being in the | |
1398 | middle of a variant frag, because the variants insert | |
1399 | all needed nop instructions themselves. */ | |
1400 | frag_grow (40); | |
1401 | } | |
5af96dce | 1402 | |
fbcfacb7 | 1403 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1404 | { |
fbcfacb7 ILT |
1405 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1406 | l->label->sy_frag = frag_now; | |
1407 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1408 | /* mips16 text labels are stored as odd. */ | |
1409 | if (mips16) | |
1410 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1411 | } |
5af96dce ILT |
1412 | |
1413 | #ifndef NO_ECOFF_DEBUGGING | |
1414 | if (ECOFF_DEBUGGING) | |
1415 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1416 | #endif | |
becfe05e ILT |
1417 | } |
1418 | } | |
1419 | ||
cc5703cd ILT |
1420 | if (reloc_type > BFD_RELOC_UNUSED) |
1421 | { | |
1422 | /* We need to set up a variant frag. */ | |
1423 | assert (mips16 && address_expr != NULL); | |
1424 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1425 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1426 | mips16_small, mips16_ext, |
1427 | (prev_pinfo | |
1428 | & INSN_UNCOND_BRANCH_DELAY), | |
1429 | (prev_insn_reloc_type | |
1430 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1431 | make_expr_symbol (address_expr), (long) 0, |
1432 | (char *) NULL); | |
1433 | } | |
1434 | else if (place != NULL) | |
0dd2d296 | 1435 | f = place; |
cc5703cd | 1436 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1437 | { |
1438 | /* Make sure there is enough room to swap this instruction with | |
1439 | a following jump instruction. */ | |
1440 | frag_grow (6); | |
1441 | f = frag_more (2); | |
1442 | } | |
cc5703cd ILT |
1443 | else |
1444 | f = frag_more (4); | |
becfe05e | 1445 | fixp = NULL; |
cc5703cd | 1446 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1447 | { |
5ac34ac3 | 1448 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1449 | { |
1450 | switch (reloc_type) | |
1451 | { | |
3d3c5039 | 1452 | case BFD_RELOC_32: |
670a50eb ILT |
1453 | ip->insn_opcode |= address_expr->X_add_number; |
1454 | break; | |
3d3c5039 ILT |
1455 | |
1456 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1457 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1458 | break; | |
3d3c5039 ILT |
1459 | |
1460 | case BFD_RELOC_MIPS_JMP: | |
5e1e8f23 ILT |
1461 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1462 | break; | |
1463 | ||
cc5703cd ILT |
1464 | case BFD_RELOC_MIPS16_JMP: |
1465 | ip->insn_opcode |= | |
1466 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1467 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1468 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1469 | break; | |
1470 | ||
3d3c5039 | 1471 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1472 | goto need_reloc; |
3d3c5039 ILT |
1473 | |
1474 | default: | |
670a50eb | 1475 | internalError (); |
3d3c5039 | 1476 | } |
670a50eb ILT |
1477 | } |
1478 | else | |
1479 | { | |
3d3c5039 | 1480 | need_reloc: |
0dd2d296 ILT |
1481 | /* Don't generate a reloc if we are writing into a variant |
1482 | frag. */ | |
1483 | if (place == NULL) | |
867a58b3 ILT |
1484 | { |
1485 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1486 | address_expr, | |
1487 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1488 | reloc_type); | |
1489 | if (unmatched_hi) | |
1490 | { | |
1491 | struct mips_hi_fixup *hi_fixup; | |
1492 | ||
1493 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1494 | hi_fixup = ((struct mips_hi_fixup *) | |
1495 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1496 | hi_fixup->fixp = fixp; | |
1497 | hi_fixup->seg = now_seg; | |
1498 | hi_fixup->next = mips_hi_fixup_list; | |
1499 | mips_hi_fixup_list = hi_fixup; | |
1500 | } | |
1501 | } | |
3d3c5039 ILT |
1502 | } |
1503 | } | |
becfe05e | 1504 | |
cc5703cd ILT |
1505 | if (! mips16 || reloc_type == BFD_RELOC_MIPS16_JMP) |
1506 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1507 | else | |
1508 | { | |
1509 | if (ip->use_extend) | |
1510 | { | |
1511 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1512 | f += 2; | |
1513 | } | |
1514 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1515 | } | |
670a50eb | 1516 | |
1aa6938e | 1517 | /* Update the register mask information. */ |
cc5703cd ILT |
1518 | if (! mips16) |
1519 | { | |
1520 | if (pinfo & INSN_WRITE_GPR_D) | |
1521 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1522 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1523 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1524 | if (pinfo & INSN_READ_GPR_S) | |
1525 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1526 | if (pinfo & INSN_WRITE_GPR_31) | |
1527 | mips_gprmask |= 1 << 31; | |
1528 | if (pinfo & INSN_WRITE_FPR_D) | |
1529 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1530 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1531 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1532 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1533 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1534 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1535 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1536 | if (pinfo & INSN_COP) | |
1537 | { | |
1538 | /* We don't keep enough information to sort these cases out. */ | |
1539 | } | |
1540 | /* Never set the bit for $0, which is always zero. */ | |
1541 | mips_gprmask &=~ 1 << 0; | |
1542 | } | |
1543 | else | |
1aa6938e | 1544 | { |
cc5703cd ILT |
1545 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1546 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1547 | & MIPS16OP_MASK_RX); | |
1548 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1549 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1550 | & MIPS16OP_MASK_RY); | |
1551 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1552 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1553 | & MIPS16OP_MASK_RZ); | |
1554 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1555 | mips_gprmask |= 1 << TREG; | |
1556 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1557 | mips_gprmask |= 1 << SP; | |
1558 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1559 | mips_gprmask |= 1 << RA; | |
1560 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1561 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1562 | if (pinfo & MIPS16_INSN_READ_Z) | |
1563 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1564 | & MIPS16OP_MASK_MOVE32Z); | |
1565 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1566 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1567 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1568 | } |
1aa6938e | 1569 | |
0dd2d296 | 1570 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1571 | { |
becfe05e ILT |
1572 | /* Filling the branch delay slot is more complex. We try to |
1573 | switch the branch with the previous instruction, which we can | |
1574 | do if the previous instruction does not set up a condition | |
1575 | that the branch tests and if the branch is not itself the | |
1576 | target of any branch. */ | |
1aa6938e ILT |
1577 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1578 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1579 | { |
0aa07269 | 1580 | if (mips_optimize < 2 |
19ed8960 ILT |
1581 | /* If we have seen .set volatile or .set nomove, don't |
1582 | optimize. */ | |
1583 | || mips_nomove != 0 | |
4e95866e ILT |
1584 | /* If we had to emit any NOP instructions, then we |
1585 | already know we can not swap. */ | |
1586 | || nops != 0 | |
becfe05e ILT |
1587 | /* If we don't even know the previous insn, we can not |
1588 | swap. */ | |
1589 | || ! prev_insn_valid | |
1590 | /* If the previous insn is already in a branch delay | |
1591 | slot, then we can not swap. */ | |
1592 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1593 | /* If the previous previous insn was in a .set |
1594 | noreorder, we can't swap. Actually, the MIPS | |
1595 | assembler will swap in this situation. However, gcc | |
1596 | configured -with-gnu-as will generate code like | |
1597 | .set noreorder | |
1598 | lw $4,XXX | |
1599 | .set reorder | |
1600 | INSN | |
1601 | bne $4,$0,foo | |
1602 | in which we can not swap the bne and INSN. If gcc is | |
1603 | not configured -with-gnu-as, it does not output the | |
1604 | .set pseudo-ops. We don't have to check | |
1605 | prev_insn_unreordered, because prev_insn_valid will | |
1606 | be 0 in that case. We don't want to use | |
1607 | prev_prev_insn_valid, because we do want to be able | |
1608 | to swap at the start of a function. */ | |
1609 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1610 | /* If the branch is itself the target of a branch, we |
1611 | can not swap. We cheat on this; all we check for is | |
1612 | whether there is a label on this instruction. If | |
1613 | there are any branches to anything other than a | |
1614 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1615 | || insn_labels != NULL |
777ad64d | 1616 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1617 | can not do the swap. This does not apply to the |
1618 | mips16, which uses variant frags for different | |
1619 | purposes. */ | |
1620 | || (! mips16 | |
1621 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1622 | /* If the branch reads the condition codes, we don't |
1623 | even try to swap, because in the sequence | |
1624 | ctc1 $X,$31 | |
1625 | INSN | |
1626 | INSN | |
1627 | bc1t LABEL | |
1628 | we can not swap, and I don't feel like handling that | |
1629 | case. */ | |
cc5703cd ILT |
1630 | || (! mips16 |
1631 | && mips_isa < 4 | |
d8a1c247 | 1632 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1633 | /* We can not swap with an instruction that requires a |
1634 | delay slot, becase the target of the branch might | |
1635 | interfere with that instruction. */ | |
cc5703cd ILT |
1636 | || (! mips16 |
1637 | && mips_isa < 4 | |
d8a1c247 KR |
1638 | && (prev_pinfo |
1639 | & (INSN_LOAD_COPROC_DELAY | |
1640 | | INSN_COPROC_MOVE_DELAY | |
1641 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1642 | || (! interlocks |
b2b8c24e ILT |
1643 | && (prev_pinfo |
1644 | & (INSN_READ_LO | |
1645 | | INSN_READ_HI))) | |
cc5703cd ILT |
1646 | || (! mips16 |
1647 | && mips_isa < 2 | |
1aa6938e | 1648 | && (prev_pinfo |
8358c818 ILT |
1649 | & (INSN_LOAD_MEMORY_DELAY |
1650 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1651 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1652 | || (prev_pinfo |
6e8dda9c ILT |
1653 | & (INSN_UNCOND_BRANCH_DELAY |
1654 | | INSN_COND_BRANCH_DELAY | |
1655 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1656 | /* We do not swap with a trap instruction, since it |
1657 | complicates trap handlers to have the trap | |
1658 | instruction be in a delay slot. */ | |
1aa6938e | 1659 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1660 | /* If the branch reads a register that the previous |
1661 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1662 | || (! mips16 |
1663 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1664 | && insn_uses_reg (ip, |
1665 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1666 | & OP_MASK_RT), | |
cc5703cd ILT |
1667 | MIPS_GR_REG)) |
1668 | || (! mips16 | |
1669 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1670 | && insn_uses_reg (ip, |
1671 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1672 | & OP_MASK_RD), | |
cc5703cd ILT |
1673 | MIPS_GR_REG)) |
1674 | || (mips16 | |
1675 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1676 | && insn_uses_reg (ip, | |
1677 | ((prev_insn.insn_opcode | |
1678 | >> MIPS16OP_SH_RX) | |
1679 | & MIPS16OP_MASK_RX), | |
1680 | MIPS16_REG)) | |
1681 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1682 | && insn_uses_reg (ip, | |
1683 | ((prev_insn.insn_opcode | |
1684 | >> MIPS16OP_SH_RY) | |
1685 | & MIPS16OP_MASK_RY), | |
1686 | MIPS16_REG)) | |
1687 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1688 | && insn_uses_reg (ip, | |
1689 | ((prev_insn.insn_opcode | |
1690 | >> MIPS16OP_SH_RZ) | |
1691 | & MIPS16OP_MASK_RZ), | |
1692 | MIPS16_REG)) | |
1693 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1694 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1695 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1696 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1697 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1698 | && insn_uses_reg (ip, | |
1699 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1700 | insn_opcode), | |
1701 | MIPS_GR_REG)))) | |
1849d646 ILT |
1702 | /* If the branch writes a register that the previous |
1703 | instruction sets, we can not swap (we know that | |
1704 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1705 | || (! mips16 |
1706 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1707 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1708 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1709 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1710 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1711 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1712 | & OP_MASK_RT) | |
1713 | == 31)))) | |
cc5703cd ILT |
1714 | || (! mips16 |
1715 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1716 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1717 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1718 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1719 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1720 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1721 | & OP_MASK_RD) | |
1722 | == 31)))) | |
cc5703cd ILT |
1723 | || (mips16 |
1724 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1725 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1726 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1727 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1728 | == RA)))) | |
becfe05e ILT |
1729 | /* If the branch writes a register that the previous |
1730 | instruction reads, we can not swap (we know that | |
1731 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1732 | || (! mips16 |
1733 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1734 | && insn_uses_reg (&prev_insn, |
1735 | ((ip->insn_opcode >> OP_SH_RD) | |
1736 | & OP_MASK_RD), | |
cc5703cd ILT |
1737 | MIPS_GR_REG)) |
1738 | || (! mips16 | |
1739 | && (pinfo & INSN_WRITE_GPR_31) | |
1740 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1741 | || (mips16 | |
1742 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1743 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1744 | /* If we are generating embedded PIC code, the branch |
1745 | might be expanded into a sequence which uses $at, so | |
1746 | we can't swap with an instruction which reads it. */ | |
1747 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1748 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1749 | /* If the previous previous instruction has a load |
1750 | delay, and sets a register that the branch reads, we | |
1751 | can not swap. */ | |
cc5703cd ILT |
1752 | || (! mips16 |
1753 | && mips_isa < 4 | |
d8a1c247 KR |
1754 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1755 | || (mips_isa < 2 | |
1756 | && (prev_prev_insn.insn_mo->pinfo | |
1757 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1758 | && insn_uses_reg (ip, |
1759 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1760 | & OP_MASK_RT), | |
cc5703cd | 1761 | MIPS_GR_REG)) |
d31a3f5e ILT |
1762 | /* If one instruction sets a condition code and the |
1763 | other one uses a condition code, we can not swap. */ | |
1764 | || ((pinfo & INSN_READ_COND_CODE) | |
1765 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1766 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1767 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1768 | /* If the previous instruction uses the PC, we can not | |
1769 | swap. */ | |
1770 | || (mips16 | |
1771 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1772 | /* If the previous instruction was extended, we can not | |
1773 | swap. */ | |
1774 | || (mips16 && prev_insn_extended) | |
1775 | /* If the previous instruction had a fixup in mips16 | |
1776 | mode, we can not swap. This normally means that the | |
1777 | previous instruction was a 4 byte branch anyhow. */ | |
1778 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1779 | { |
1780 | /* We could do even better for unconditional branches to | |
1781 | portions of this object file; we could pick up the | |
1782 | instruction at the destination, put it in the delay | |
1783 | slot, and bump the destination address. */ | |
1784 | emit_nop (); | |
1785 | /* Update the previous insn information. */ | |
1786 | prev_prev_insn = *ip; | |
1787 | prev_insn.insn_mo = &dummy_opcode; | |
1788 | } | |
1789 | else | |
1790 | { | |
becfe05e | 1791 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1792 | if (! mips16) |
1793 | { | |
1794 | char *prev_f; | |
1795 | char temp[4]; | |
1796 | ||
1797 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1798 | memcpy (temp, prev_f, 4); | |
1799 | memcpy (prev_f, f, 4); | |
1800 | memcpy (f, temp, 4); | |
1801 | if (prev_insn_fixp) | |
1802 | { | |
1803 | prev_insn_fixp->fx_frag = frag_now; | |
1804 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1805 | } | |
1806 | if (fixp) | |
1807 | { | |
1808 | fixp->fx_frag = prev_insn_frag; | |
1809 | fixp->fx_where = prev_insn_where; | |
1810 | } | |
1811 | } | |
1812 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1813 | { |
cc5703cd ILT |
1814 | char *prev_f; |
1815 | char temp[2]; | |
1816 | ||
1817 | /* We are in mips16 mode, and we have just created a | |
1818 | variant frag. We need to extract the old | |
1819 | instruction from the end of the previous frag, | |
1820 | and add it to a new frag. */ | |
1821 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1822 | memcpy (temp, prev_f, 2); | |
1823 | prev_insn_frag->fr_fix -= 2; | |
1824 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1825 | { | |
1826 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1827 | memcpy (prev_f, prev_f + 2, 2); | |
1828 | } | |
1829 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1830 | } |
cc5703cd | 1831 | else |
becfe05e | 1832 | { |
cc5703cd ILT |
1833 | char *prev_f; |
1834 | char temp[2]; | |
1835 | ||
1836 | assert (prev_insn_fixp == NULL); | |
1837 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1838 | memcpy (temp, prev_f, 2); | |
1839 | memcpy (prev_f, f, 2); | |
1840 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1841 | memcpy (f, temp, 2); | |
1842 | else | |
1843 | { | |
1844 | memcpy (f, f + 2, 2); | |
1845 | memcpy (f + 2, temp, 2); | |
1846 | } | |
1847 | if (fixp) | |
1848 | { | |
1849 | fixp->fx_frag = prev_insn_frag; | |
1850 | fixp->fx_where = prev_insn_where; | |
1851 | } | |
becfe05e | 1852 | } |
cc5703cd | 1853 | |
becfe05e ILT |
1854 | /* Update the previous insn information; leave prev_insn |
1855 | unchanged. */ | |
1856 | prev_prev_insn = *ip; | |
1857 | } | |
1858 | prev_insn_is_delay_slot = 1; | |
1859 | ||
1860 | /* If that was an unconditional branch, forget the previous | |
1861 | insn information. */ | |
1aa6938e | 1862 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1863 | { |
1864 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1865 | prev_insn.insn_mo = &dummy_opcode; | |
1866 | } | |
a677feeb ILT |
1867 | |
1868 | prev_insn_fixp = NULL; | |
1869 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1870 | prev_insn_extended = 0; | |
becfe05e | 1871 | } |
1aa6938e | 1872 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1873 | { |
1874 | /* We don't yet optimize a branch likely. What we should do | |
1875 | is look at the target, copy the instruction found there | |
1876 | into the delay slot, and increment the branch to jump to | |
1877 | the next instruction. */ | |
1878 | emit_nop (); | |
1879 | /* Update the previous insn information. */ | |
1880 | prev_prev_insn = *ip; | |
1881 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1882 | prev_insn_fixp = NULL; |
1883 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1884 | prev_insn_extended = 0; | |
8358c818 | 1885 | } |
becfe05e | 1886 | else |
670a50eb | 1887 | { |
becfe05e ILT |
1888 | /* Update the previous insn information. */ |
1889 | if (nops > 0) | |
1890 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1891 | else | |
1892 | prev_prev_insn = prev_insn; | |
1893 | prev_insn = *ip; | |
1894 | ||
1895 | /* Any time we see a branch, we always fill the delay slot | |
1896 | immediately; since this insn is not a branch, we know it | |
1897 | is not in a delay slot. */ | |
1898 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1899 | |
1900 | prev_insn_fixp = fixp; | |
1901 | prev_insn_reloc_type = reloc_type; | |
1902 | if (mips16) | |
1903 | prev_insn_extended = (ip->use_extend | |
1904 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1905 | } |
1906 | ||
4e95866e ILT |
1907 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1908 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1909 | prev_insn_frag = frag_now; |
1910 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1911 | prev_insn_valid = 1; |
1912 | } | |
fbcfacb7 | 1913 | else if (place == NULL) |
a677feeb | 1914 | { |
fbcfacb7 | 1915 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1916 | reordering, in order to determine the base address for mips16 |
1917 | PC relative relocs. */ | |
1918 | prev_insn = *ip; | |
1919 | prev_insn_reloc_type = reloc_type; | |
1920 | } | |
3d3c5039 | 1921 | |
becfe05e | 1922 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1923 | mips_clear_insn_labels (); |
becfe05e ILT |
1924 | } |
1925 | ||
1926 | /* This function forgets that there was any previous instruction or | |
1927 | label. */ | |
1928 | ||
1929 | static void | |
1930 | mips_no_prev_insn () | |
1931 | { | |
1932 | prev_insn.insn_mo = &dummy_opcode; | |
1933 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1934 | prev_insn_valid = 0; | |
1935 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1936 | prev_insn_unreordered = 0; |
cc5703cd | 1937 | prev_insn_extended = 0; |
a677feeb | 1938 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 1939 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 1940 | mips_clear_insn_labels (); |
becfe05e ILT |
1941 | } |
1942 | ||
1943 | /* This function must be called whenever we turn on noreorder or emit | |
1944 | something other than instructions. It inserts any NOPS which might | |
1945 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
1946 | kept for the previous instructions. The INSNS parameter is true if |
1947 | instructions are to follow. */ | |
becfe05e ILT |
1948 | |
1949 | static void | |
fbcfacb7 ILT |
1950 | mips_emit_delays (insns) |
1951 | boolean insns; | |
becfe05e ILT |
1952 | { |
1953 | if (! mips_noreorder) | |
1954 | { | |
1955 | int nop; | |
1956 | ||
1957 | nop = 0; | |
cc5703cd ILT |
1958 | if ((! mips16 |
1959 | && mips_isa < 4 | |
344a8d61 JSC |
1960 | && (! cop_interlocks |
1961 | && (prev_insn.insn_mo->pinfo | |
1962 | & (INSN_LOAD_COPROC_DELAY | |
1963 | | INSN_COPROC_MOVE_DELAY | |
1964 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1965 | || (! interlocks |
b2b8c24e ILT |
1966 | && (prev_insn.insn_mo->pinfo |
1967 | & (INSN_READ_LO | |
1968 | | INSN_READ_HI))) | |
cc5703cd ILT |
1969 | || (! mips16 |
1970 | && mips_isa < 2 | |
8358c818 ILT |
1971 | && (prev_insn.insn_mo->pinfo |
1972 | & (INSN_LOAD_MEMORY_DELAY | |
1973 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1974 | { |
1975 | nop = 1; | |
cc5703cd ILT |
1976 | if ((! mips16 |
1977 | && mips_isa < 4 | |
344a8d61 JSC |
1978 | && (! cop_interlocks |
1979 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1980 | || (! interlocks |
b2b8c24e ILT |
1981 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1982 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1983 | emit_nop (); |
1984 | } | |
cc5703cd ILT |
1985 | else if ((! mips16 |
1986 | && mips_isa < 4 | |
344a8d61 JSC |
1987 | && (! cop_interlocks |
1988 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1989 | || (! interlocks |
b2b8c24e ILT |
1990 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1991 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1992 | nop = 1; |
1993 | if (nop) | |
670a50eb | 1994 | { |
fbcfacb7 ILT |
1995 | struct insn_label_list *l; |
1996 | ||
becfe05e | 1997 | emit_nop (); |
fbcfacb7 | 1998 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1999 | { |
fbcfacb7 ILT |
2000 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2001 | l->label->sy_frag = frag_now; | |
2002 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2003 | /* mips16 text labels are stored as odd. */ | |
2004 | if (mips16) | |
2005 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2006 | } |
3d3c5039 ILT |
2007 | } |
2008 | } | |
0221ddf7 | 2009 | |
fbcfacb7 ILT |
2010 | /* Mark instruction labels in mips16 mode. This permits the linker |
2011 | to handle them specially, such as generating jalx instructions | |
2012 | when needed. We also make them odd for the duration of the | |
2013 | assembly, in order to generate the right sort of code. We will | |
2014 | make them even in the adjust_symtab routine, while leaving them | |
2015 | marked. This is convenient for the debugger and the | |
2016 | disassembler. The linker knows to make them odd again. */ | |
2017 | if (mips16 && insns) | |
2018 | { | |
2019 | struct insn_label_list *l; | |
2020 | ||
2021 | for (l = insn_labels; l != NULL; l = l->next) | |
2022 | { | |
2023 | #ifdef S_SET_OTHER | |
2024 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2025 | S_SET_OTHER (l->label, STO_MIPS16); | |
2026 | #endif | |
2027 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2028 | ++l->label->sy_value.X_add_number; | |
2029 | } | |
2030 | } | |
2031 | ||
0221ddf7 | 2032 | mips_no_prev_insn (); |
3d3c5039 ILT |
2033 | } |
2034 | ||
670a50eb ILT |
2035 | /* Build an instruction created by a macro expansion. This is passed |
2036 | a pointer to the count of instructions created so far, an | |
2037 | expression, the name of the instruction to build, an operand format | |
2038 | string, and corresponding arguments. */ | |
2039 | ||
1dc1e798 | 2040 | #ifdef USE_STDARG |
3d3c5039 | 2041 | static void |
0dd2d296 ILT |
2042 | macro_build (char *place, |
2043 | int *counter, | |
670a50eb | 2044 | expressionS * ep, |
3d3c5039 ILT |
2045 | const char *name, |
2046 | const char *fmt, | |
2047 | ...) | |
1dc1e798 | 2048 | #else |
3d3c5039 | 2049 | static void |
0dd2d296 ILT |
2050 | macro_build (place, counter, ep, name, fmt, va_alist) |
2051 | char *place; | |
3d3c5039 ILT |
2052 | int *counter; |
2053 | expressionS *ep; | |
2054 | const char *name; | |
2055 | const char *fmt; | |
2056 | va_dcl | |
1dc1e798 | 2057 | #endif |
3d3c5039 | 2058 | { |
670a50eb ILT |
2059 | struct mips_cl_insn insn; |
2060 | bfd_reloc_code_real_type r; | |
2061 | va_list args; | |
3d3c5039 | 2062 | |
1dc1e798 | 2063 | #ifdef USE_STDARG |
670a50eb | 2064 | va_start (args, fmt); |
3d3c5039 | 2065 | #else |
670a50eb | 2066 | va_start (args); |
3d3c5039 ILT |
2067 | #endif |
2068 | ||
670a50eb ILT |
2069 | /* |
2070 | * If the macro is about to expand into a second instruction, | |
2071 | * print a warning if needed. We need to pass ip as a parameter | |
2072 | * to generate a better warning message here... | |
2073 | */ | |
0dd2d296 | 2074 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2075 | as_warn ("Macro instruction expanded into multiple instructions"); |
2076 | ||
0dd2d296 ILT |
2077 | if (place == NULL) |
2078 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2079 | |
cc5703cd ILT |
2080 | if (mips16) |
2081 | { | |
2082 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2083 | va_end (args); | |
2084 | return; | |
2085 | } | |
2086 | ||
670a50eb ILT |
2087 | r = BFD_RELOC_UNUSED; |
2088 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2089 | assert (insn.insn_mo); | |
2090 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2091 | ||
9226253a | 2092 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2093 | || insn.insn_mo->pinfo == INSN_MACRO |
2094 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2095 | && mips_isa < 2) | |
2096 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2097 | && mips_isa < 3) | |
2098 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2099 | && mips_isa < 4) | |
2100 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2101 | && ! mips_4650) | |
2102 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2103 | && ! mips_4010) | |
2104 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
2105 | && ! mips_4100)) | |
670a50eb ILT |
2106 | { |
2107 | ++insn.insn_mo; | |
2108 | assert (insn.insn_mo->name); | |
2109 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2110 | } |
670a50eb ILT |
2111 | insn.insn_opcode = insn.insn_mo->match; |
2112 | for (;;) | |
2113 | { | |
2114 | switch (*fmt++) | |
2115 | { | |
3d3c5039 | 2116 | case '\0': |
670a50eb | 2117 | break; |
3d3c5039 ILT |
2118 | |
2119 | case ',': | |
2120 | case '(': | |
2121 | case ')': | |
670a50eb | 2122 | continue; |
3d3c5039 ILT |
2123 | |
2124 | case 't': | |
2125 | case 'w': | |
918692a5 | 2126 | case 'E': |
670a50eb ILT |
2127 | insn.insn_opcode |= va_arg (args, int) << 16; |
2128 | continue; | |
3d3c5039 ILT |
2129 | |
2130 | case 'c': | |
2131 | case 'T': | |
2132 | case 'W': | |
670a50eb ILT |
2133 | insn.insn_opcode |= va_arg (args, int) << 16; |
2134 | continue; | |
3d3c5039 ILT |
2135 | |
2136 | case 'd': | |
918692a5 | 2137 | case 'G': |
670a50eb ILT |
2138 | insn.insn_opcode |= va_arg (args, int) << 11; |
2139 | continue; | |
3d3c5039 ILT |
2140 | |
2141 | case 'V': | |
2142 | case 'S': | |
670a50eb ILT |
2143 | insn.insn_opcode |= va_arg (args, int) << 11; |
2144 | continue; | |
3d3c5039 | 2145 | |
ff3a5c18 ILT |
2146 | case 'z': |
2147 | continue; | |
2148 | ||
3d3c5039 | 2149 | case '<': |
670a50eb ILT |
2150 | insn.insn_opcode |= va_arg (args, int) << 6; |
2151 | continue; | |
3d3c5039 ILT |
2152 | |
2153 | case 'D': | |
670a50eb ILT |
2154 | insn.insn_opcode |= va_arg (args, int) << 6; |
2155 | continue; | |
3d3c5039 | 2156 | |
918692a5 ILT |
2157 | case 'B': |
2158 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2159 | continue; | |
2160 | ||
3d3c5039 ILT |
2161 | case 'b': |
2162 | case 's': | |
2163 | case 'r': | |
2164 | case 'v': | |
670a50eb ILT |
2165 | insn.insn_opcode |= va_arg (args, int) << 21; |
2166 | continue; | |
3d3c5039 ILT |
2167 | |
2168 | case 'i': | |
2169 | case 'j': | |
2170 | case 'o': | |
9226253a | 2171 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2172 | assert (r == BFD_RELOC_MIPS_GPREL |
2173 | || r == BFD_RELOC_MIPS_LITERAL | |
2174 | || r == BFD_RELOC_LO16 | |
2175 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2176 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2177 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2178 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2179 | || (ep->X_op == O_subtract |
2180 | && now_seg == text_section | |
ecd4ca1c | 2181 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2182 | continue; |
3d3c5039 | 2183 | |
6e8dda9c | 2184 | case 'u': |
ecd4ca1c ILT |
2185 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2186 | assert (ep != NULL | |
2187 | && (ep->X_op == O_constant | |
2188 | || (ep->X_op == O_symbol | |
2189 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2190 | || r == BFD_RELOC_HI16 |
2191 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2192 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2193 | || (ep->X_op == O_subtract |
2194 | && now_seg == text_section | |
ecd4ca1c ILT |
2195 | && r == BFD_RELOC_PCREL_HI16_S))); |
2196 | if (ep->X_op == O_constant) | |
2197 | { | |
2198 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2199 | ep = NULL; | |
2200 | r = BFD_RELOC_UNUSED; | |
2201 | } | |
6e8dda9c ILT |
2202 | continue; |
2203 | ||
3d3c5039 | 2204 | case 'p': |
670a50eb ILT |
2205 | assert (ep != NULL); |
2206 | /* | |
2207 | * This allows macro() to pass an immediate expression for | |
2208 | * creating short branches without creating a symbol. | |
2209 | * Note that the expression still might come from the assembly | |
2210 | * input, in which case the value is not checked for range nor | |
2211 | * is a relocation entry generated (yuck). | |
2212 | */ | |
5ac34ac3 | 2213 | if (ep->X_op == O_constant) |
670a50eb ILT |
2214 | { |
2215 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2216 | ep = NULL; | |
2217 | } | |
2218 | else | |
2219 | r = BFD_RELOC_16_PCREL_S2; | |
2220 | continue; | |
3d3c5039 | 2221 | |
9226253a ILT |
2222 | case 'a': |
2223 | assert (ep != NULL); | |
2224 | r = BFD_RELOC_MIPS_JMP; | |
2225 | continue; | |
2226 | ||
3d3c5039 | 2227 | default: |
670a50eb | 2228 | internalError (); |
3d3c5039 | 2229 | } |
670a50eb | 2230 | break; |
3d3c5039 | 2231 | } |
670a50eb ILT |
2232 | va_end (args); |
2233 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2234 | ||
867a58b3 | 2235 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2236 | } |
2237 | ||
cc5703cd ILT |
2238 | static void |
2239 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2240 | char *place; | |
2241 | int *counter; | |
2242 | expressionS *ep; | |
2243 | const char *name; | |
2244 | const char *fmt; | |
2245 | va_list args; | |
2246 | { | |
2247 | struct mips_cl_insn insn; | |
2248 | bfd_reloc_code_real_type r; | |
2249 | ||
2250 | r = BFD_RELOC_UNUSED; | |
2251 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2252 | assert (insn.insn_mo); | |
2253 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2254 | ||
2255 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2256 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2257 | { | |
2258 | ++insn.insn_mo; | |
2259 | assert (insn.insn_mo->name); | |
2260 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2261 | } | |
2262 | ||
2263 | insn.insn_opcode = insn.insn_mo->match; | |
2264 | insn.use_extend = false; | |
2265 | ||
2266 | for (;;) | |
2267 | { | |
2268 | int c; | |
2269 | ||
2270 | c = *fmt++; | |
2271 | switch (c) | |
2272 | { | |
2273 | case '\0': | |
2274 | break; | |
2275 | ||
2276 | case ',': | |
2277 | case '(': | |
2278 | case ')': | |
2279 | continue; | |
2280 | ||
2281 | case 'y': | |
2282 | case 'w': | |
2283 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2284 | continue; | |
2285 | ||
2286 | case 'x': | |
2287 | case 'v': | |
2288 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2289 | continue; | |
2290 | ||
2291 | case 'z': | |
2292 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2293 | continue; | |
2294 | ||
2295 | case 'Z': | |
2296 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2297 | continue; | |
2298 | ||
2299 | case '0': | |
2300 | case 'S': | |
2301 | case 'P': | |
2302 | case 'R': | |
2303 | continue; | |
2304 | ||
2305 | case 'X': | |
2306 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2307 | continue; | |
2308 | ||
2309 | case 'Y': | |
2310 | { | |
2311 | int regno; | |
2312 | ||
2313 | regno = va_arg (args, int); | |
2314 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2315 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2316 | } | |
2317 | continue; | |
2318 | ||
2319 | case '<': | |
2320 | case '>': | |
2321 | case '4': | |
2322 | case '5': | |
2323 | case 'H': | |
2324 | case 'W': | |
2325 | case 'D': | |
2326 | case 'j': | |
2327 | case '8': | |
2328 | case 'V': | |
2329 | case 'C': | |
2330 | case 'U': | |
2331 | case 'k': | |
2332 | case 'K': | |
2333 | case 'p': | |
2334 | case 'q': | |
2335 | { | |
2336 | assert (ep != NULL); | |
2337 | ||
2338 | if (ep->X_op != O_constant) | |
2339 | r = BFD_RELOC_UNUSED + c; | |
2340 | else | |
2341 | { | |
15e69f98 ILT |
2342 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2343 | false, false, &insn.insn_opcode, | |
2344 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2345 | ep = NULL; |
2346 | r = BFD_RELOC_UNUSED; | |
2347 | } | |
2348 | } | |
2349 | continue; | |
2350 | ||
2351 | case '6': | |
2352 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2353 | continue; | |
2354 | } | |
2355 | ||
2356 | break; | |
2357 | } | |
2358 | ||
2359 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2360 | ||
2361 | append_insn (place, &insn, ep, r, false); | |
2362 | } | |
2363 | ||
3d3c5039 ILT |
2364 | /* |
2365 | * Generate a "lui" instruction. | |
2366 | */ | |
2367 | static void | |
0dd2d296 ILT |
2368 | macro_build_lui (place, counter, ep, regnum) |
2369 | char *place; | |
3d3c5039 ILT |
2370 | int *counter; |
2371 | expressionS *ep; | |
2372 | int regnum; | |
2373 | { | |
670a50eb ILT |
2374 | expressionS high_expr; |
2375 | struct mips_cl_insn insn; | |
2376 | bfd_reloc_code_real_type r; | |
2377 | CONST char *name = "lui"; | |
2378 | CONST char *fmt = "t,u"; | |
2379 | ||
cc5703cd ILT |
2380 | assert (! mips16); |
2381 | ||
0dd2d296 ILT |
2382 | if (place == NULL) |
2383 | high_expr = *ep; | |
2384 | else | |
2385 | { | |
2386 | high_expr.X_op = O_constant; | |
fb251650 | 2387 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2388 | } |
670a50eb | 2389 | |
5ac34ac3 | 2390 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2391 | { |
2392 | /* we can compute the instruction now without a relocation entry */ | |
2393 | if (high_expr.X_add_number & 0x8000) | |
2394 | high_expr.X_add_number += 0x10000; | |
2395 | high_expr.X_add_number = | |
2396 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2397 | r = BFD_RELOC_UNUSED; | |
2398 | } | |
2399 | else | |
0dd2d296 ILT |
2400 | { |
2401 | assert (ep->X_op == O_symbol); | |
2402 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2403 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2404 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2405 | r = BFD_RELOC_HI16_S; | |
2406 | } | |
670a50eb ILT |
2407 | |
2408 | /* | |
2409 | * If the macro is about to expand into a second instruction, | |
2410 | * print a warning if needed. We need to pass ip as a parameter | |
2411 | * to generate a better warning message here... | |
2412 | */ | |
0dd2d296 | 2413 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2414 | as_warn ("Macro instruction expanded into multiple instructions"); |
2415 | ||
0dd2d296 ILT |
2416 | if (place == NULL) |
2417 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2418 | |
2419 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2420 | assert (insn.insn_mo); | |
2421 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2422 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2423 | ||
0dd2d296 | 2424 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2425 | if (r == BFD_RELOC_UNUSED) |
2426 | { | |
2427 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2428 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2429 | } |
2430 | else | |
867a58b3 | 2431 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2432 | } |
2433 | ||
2434 | /* set_at() | |
2435 | * Generates code to set the $at register to true (one) | |
2436 | * if reg is less than the immediate expression. | |
2437 | */ | |
2438 | static void | |
6e8dda9c | 2439 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2440 | int *counter; |
2441 | int reg; | |
6e8dda9c | 2442 | int unsignedp; |
3d3c5039 | 2443 | { |
6e8dda9c | 2444 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2445 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2446 | unsignedp ? "sltiu" : "slti", |
9226253a | 2447 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2448 | else |
670a50eb | 2449 | { |
d8a1c247 | 2450 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2451 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2452 | unsignedp ? "sltu" : "slt", |
2453 | "d,v,t", AT, reg, AT); | |
670a50eb | 2454 | } |
3d3c5039 ILT |
2455 | } |
2456 | ||
6e8dda9c | 2457 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2458 | |
2459 | static void | |
19ed8960 | 2460 | check_absolute_expr (ip, ex) |
3d3c5039 | 2461 | struct mips_cl_insn *ip; |
19ed8960 | 2462 | expressionS *ex; |
3d3c5039 | 2463 | { |
19ed8960 | 2464 | if (ex->X_op != O_constant) |
670a50eb | 2465 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2466 | } |
2467 | ||
ff8716f5 JSC |
2468 | /* Count the leading zeroes by performing a binary chop. This is a |
2469 | bulky bit of source, but performance is a LOT better for the | |
2470 | majority of values than a simple loop to count the bits: | |
2471 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2472 | if ((v) & (1 << (31 - lcnt))) | |
2473 | break; | |
2474 | However it is not code size friendly, and the gain will drop a bit | |
2475 | on certain cached systems. | |
2476 | */ | |
2477 | #define COUNT_TOP_ZEROES(v) \ | |
2478 | (((v) & ~0xffff) == 0 \ | |
2479 | ? ((v) & ~0xff) == 0 \ | |
2480 | ? ((v) & ~0xf) == 0 \ | |
2481 | ? ((v) & ~0x3) == 0 \ | |
2482 | ? ((v) & ~0x1) == 0 \ | |
2483 | ? !(v) \ | |
2484 | ? 32 \ | |
2485 | : 31 \ | |
2486 | : 30 \ | |
2487 | : ((v) & ~0x7) == 0 \ | |
2488 | ? 29 \ | |
2489 | : 28 \ | |
2490 | : ((v) & ~0x3f) == 0 \ | |
2491 | ? ((v) & ~0x1f) == 0 \ | |
2492 | ? 27 \ | |
2493 | : 26 \ | |
2494 | : ((v) & ~0x7f) == 0 \ | |
2495 | ? 25 \ | |
2496 | : 24 \ | |
2497 | : ((v) & ~0xfff) == 0 \ | |
2498 | ? ((v) & ~0x3ff) == 0 \ | |
2499 | ? ((v) & ~0x1ff) == 0 \ | |
2500 | ? 23 \ | |
2501 | : 22 \ | |
2502 | : ((v) & ~0x7ff) == 0 \ | |
2503 | ? 21 \ | |
2504 | : 20 \ | |
2505 | : ((v) & ~0x3fff) == 0 \ | |
2506 | ? ((v) & ~0x1fff) == 0 \ | |
2507 | ? 19 \ | |
2508 | : 18 \ | |
2509 | : ((v) & ~0x7fff) == 0 \ | |
2510 | ? 17 \ | |
2511 | : 16 \ | |
2512 | : ((v) & ~0xffffff) == 0 \ | |
2513 | ? ((v) & ~0xfffff) == 0 \ | |
2514 | ? ((v) & ~0x3ffff) == 0 \ | |
2515 | ? ((v) & ~0x1ffff) == 0 \ | |
2516 | ? 15 \ | |
2517 | : 14 \ | |
2518 | : ((v) & ~0x7ffff) == 0 \ | |
2519 | ? 13 \ | |
2520 | : 12 \ | |
2521 | : ((v) & ~0x3fffff) == 0 \ | |
2522 | ? ((v) & ~0x1fffff) == 0 \ | |
2523 | ? 11 \ | |
2524 | : 10 \ | |
2525 | : ((v) & ~0x7fffff) == 0 \ | |
2526 | ? 9 \ | |
2527 | : 8 \ | |
2528 | : ((v) & ~0xfffffff) == 0 \ | |
2529 | ? ((v) & ~0x3ffffff) == 0 \ | |
2530 | ? ((v) & ~0x1ffffff) == 0 \ | |
2531 | ? 7 \ | |
2532 | : 6 \ | |
2533 | : ((v) & ~0x7ffffff) == 0 \ | |
2534 | ? 5 \ | |
2535 | : 4 \ | |
2536 | : ((v) & ~0x3fffffff) == 0 \ | |
2537 | ? ((v) & ~0x1fffffff) == 0 \ | |
2538 | ? 3 \ | |
2539 | : 2 \ | |
2540 | : ((v) & ~0x7fffffff) == 0 \ | |
2541 | ? 1 \ | |
2542 | : 0) | |
2543 | ||
3d3c5039 ILT |
2544 | /* load_register() |
2545 | * This routine generates the least number of instructions neccessary to load | |
2546 | * an absolute expression value into a register. | |
2547 | */ | |
2548 | static void | |
d8a1c247 | 2549 | load_register (counter, reg, ep, dbl) |
670a50eb | 2550 | int *counter; |
670a50eb ILT |
2551 | int reg; |
2552 | expressionS *ep; | |
d8a1c247 | 2553 | int dbl; |
3d3c5039 | 2554 | { |
c36a90ef ILT |
2555 | int freg; |
2556 | expressionS hi32, lo32; | |
847a01cd ILT |
2557 | |
2558 | if (ep->X_op != O_big) | |
6e8dda9c | 2559 | { |
847a01cd | 2560 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2561 | if (ep->X_add_number < 0x8000 |
2562 | && (ep->X_add_number >= 0 | |
2563 | || (ep->X_add_number >= -0x8000 | |
2564 | && (! dbl | |
2565 | || ! ep->X_unsigned | |
2566 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2567 | { |
2568 | /* We can handle 16 bit signed values with an addiu to | |
2569 | $zero. No need to ever use daddiu here, since $zero and | |
2570 | the result are always correct in 32 bit mode. */ | |
2571 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2572 | (int) BFD_RELOC_LO16); | |
2573 | return; | |
2574 | } | |
2575 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2576 | { | |
2577 | /* We can handle 16 bit unsigned values with an ori to | |
2578 | $zero. */ | |
2579 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2580 | (int) BFD_RELOC_LO16); | |
2581 | return; | |
2582 | } | |
98bfd087 ILT |
2583 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2584 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2585 | == ~ (offsetT) 0x7fffffff)) | |
2586 | && (! dbl | |
2587 | || ! ep->X_unsigned | |
2588 | || sizeof (ep->X_add_number) > 4 | |
2589 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2590 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2591 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2592 | { |
2593 | /* 32 bit values require an lui. */ | |
2594 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2595 | (int) BFD_RELOC_HI16); | |
2596 | if ((ep->X_add_number & 0xffff) != 0) | |
2597 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2598 | (int) BFD_RELOC_LO16); | |
2599 | return; | |
2600 | } | |
6e8dda9c | 2601 | } |
847a01cd ILT |
2602 | |
2603 | /* The value is larger than 32 bits. */ | |
2604 | ||
2605 | if (mips_isa < 3) | |
670a50eb | 2606 | { |
6e8dda9c | 2607 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2608 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2609 | (int) BFD_RELOC_LO16); |
847a01cd | 2610 | return; |
6e8dda9c | 2611 | } |
6e8dda9c | 2612 | |
847a01cd ILT |
2613 | if (ep->X_op != O_big) |
2614 | { | |
6e8dda9c | 2615 | hi32 = *ep; |
c36a90ef ILT |
2616 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2617 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2618 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2619 | lo32 = *ep; |
2620 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2621 | } |
847a01cd ILT |
2622 | else |
2623 | { | |
2624 | assert (ep->X_add_number > 2); | |
2625 | if (ep->X_add_number == 3) | |
2626 | generic_bignum[3] = 0; | |
2627 | else if (ep->X_add_number > 4) | |
2628 | as_bad ("Number larger than 64 bits"); | |
2629 | lo32.X_op = O_constant; | |
2630 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2631 | hi32.X_op = O_constant; | |
2632 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2633 | } | |
2634 | ||
d8a1c247 KR |
2635 | if (hi32.X_add_number == 0) |
2636 | freg = 0; | |
2637 | else | |
2638 | { | |
c36a90ef ILT |
2639 | int shift, bit; |
2640 | unsigned long hi, lo; | |
2641 | ||
fb251650 ILT |
2642 | if (hi32.X_add_number == 0xffffffff) |
2643 | { | |
2644 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2645 | { | |
c36a90ef ILT |
2646 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2647 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2648 | return; |
2649 | } | |
2650 | if (lo32.X_add_number & 0x80000000) | |
2651 | { | |
2652 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2653 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2654 | if (lo32.X_add_number & 0xffff) |
2655 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2656 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2657 | return; |
2658 | } | |
2659 | } | |
ff8716f5 | 2660 | |
c36a90ef ILT |
2661 | /* Check for 16bit shifted constant. We know that hi32 is |
2662 | non-zero, so start the mask on the first bit of the hi32 | |
2663 | value. */ | |
ff8716f5 JSC |
2664 | shift = 17; |
2665 | do | |
2666 | { | |
c36a90ef ILT |
2667 | unsigned long himask, lomask; |
2668 | ||
2669 | if (shift < 32) | |
2670 | { | |
2671 | himask = 0xffff >> (32 - shift); | |
2672 | lomask = (0xffff << shift) & 0xffffffff; | |
2673 | } | |
2674 | else | |
2675 | { | |
2676 | himask = 0xffff << (shift - 32); | |
2677 | lomask = 0; | |
2678 | } | |
2679 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2680 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2681 | { | |
2682 | expressionS tmp; | |
2683 | ||
2684 | tmp.X_op = O_constant; | |
2685 | if (shift < 32) | |
2686 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2687 | | (lo32.X_add_number >> shift)); | |
2688 | else | |
2689 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2690 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2691 | (int) BFD_RELOC_LO16); | |
2692 | macro_build ((char *) NULL, counter, NULL, | |
2693 | (shift >= 32) ? "dsll32" : "dsll", | |
2694 | "d,w,<", reg, reg, | |
2695 | (shift >= 32) ? shift - 32 : shift); | |
2696 | return; | |
2697 | } | |
ff8716f5 JSC |
2698 | shift++; |
2699 | } while (shift <= (64 - 16)); | |
2700 | ||
c36a90ef ILT |
2701 | /* Find the bit number of the lowest one bit, and store the |
2702 | shifted value in hi/lo. */ | |
2703 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2704 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2705 | if (lo != 0) | |
2706 | { | |
2707 | bit = 0; | |
2708 | while ((lo & 1) == 0) | |
2709 | { | |
2710 | lo >>= 1; | |
2711 | ++bit; | |
2712 | } | |
2713 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2714 | hi >>= bit; | |
2715 | } | |
2716 | else | |
2717 | { | |
2718 | bit = 32; | |
2719 | while ((hi & 1) == 0) | |
2720 | { | |
2721 | hi >>= 1; | |
2722 | ++bit; | |
2723 | } | |
2724 | lo = hi; | |
2725 | hi = 0; | |
2726 | } | |
2727 | ||
2728 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2729 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2730 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2731 | { |
c36a90ef | 2732 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2733 | if (shift != 0) |
2734 | { | |
c36a90ef ILT |
2735 | expressionS tmp; |
2736 | ||
2737 | /* This instruction will set the register to be all | |
2738 | ones. */ | |
ff8716f5 | 2739 | tmp.X_op = O_constant; |
c36a90ef ILT |
2740 | tmp.X_add_number = (offsetT) -1; |
2741 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2742 | reg, 0, (int) BFD_RELOC_LO16); | |
2743 | if (bit != 0) | |
ff8716f5 | 2744 | { |
c36a90ef | 2745 | bit += shift; |
ff8716f5 | 2746 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2747 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2748 | "d,w,<", reg, reg, |
c36a90ef | 2749 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2750 | } |
c36a90ef ILT |
2751 | macro_build ((char *) NULL, counter, NULL, |
2752 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2753 | "d,w,<", reg, reg, | |
2754 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2755 | return; |
2756 | } | |
2757 | } | |
c36a90ef ILT |
2758 | |
2759 | /* Sign extend hi32 before calling load_register, because we can | |
2760 | generally get better code when we load a sign extended value. */ | |
2761 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2762 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2763 | load_register (counter, reg, &hi32, 0); |
2764 | freg = reg; | |
2765 | } | |
847a01cd | 2766 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2767 | { |
2768 | if (freg != 0) | |
2769 | { | |
2770 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2771 | freg, 0); | |
2772 | freg = reg; | |
2773 | } | |
2774 | } | |
847a01cd ILT |
2775 | else |
2776 | { | |
2777 | expressionS mid16; | |
2778 | ||
fb251650 ILT |
2779 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2780 | { | |
2781 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2782 | (int) BFD_RELOC_HI16); | |
2783 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2784 | reg, 0); |
fb251650 ILT |
2785 | return; |
2786 | } | |
2787 | ||
d8a1c247 KR |
2788 | if (freg != 0) |
2789 | { | |
2790 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2791 | freg, 16); | |
2792 | freg = reg; | |
2793 | } | |
847a01cd ILT |
2794 | mid16 = lo32; |
2795 | mid16.X_add_number >>= 16; | |
2796 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2797 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2798 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2799 | reg, 16); | |
d8a1c247 | 2800 | freg = reg; |
847a01cd ILT |
2801 | } |
2802 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2803 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2804 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2805 | } |
2806 | ||
0dd2d296 ILT |
2807 | /* Load an address into a register. */ |
2808 | ||
2809 | static void | |
2810 | load_address (counter, reg, ep) | |
2811 | int *counter; | |
2812 | int reg; | |
2813 | expressionS *ep; | |
2814 | { | |
2815 | char *p; | |
2816 | ||
2817 | if (ep->X_op != O_constant | |
2818 | && ep->X_op != O_symbol) | |
2819 | { | |
2820 | as_bad ("expression too complex"); | |
2821 | ep->X_op = O_constant; | |
2822 | } | |
2823 | ||
2824 | if (ep->X_op == O_constant) | |
d9aba805 | 2825 | { |
d8a1c247 | 2826 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2827 | return; |
2828 | } | |
2829 | ||
2830 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2831 | { |
2832 | /* If this is a reference to a GP relative symbol, we want | |
2833 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2834 | Otherwise we want | |
04cb3372 | 2835 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2836 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2837 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2838 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2839 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2840 | p = NULL; |
2841 | else | |
2842 | { | |
8ea7f4e8 | 2843 | frag_grow (20); |
0dd2d296 ILT |
2844 | macro_build ((char *) NULL, counter, ep, |
2845 | mips_isa < 3 ? "addiu" : "daddiu", | |
2846 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2847 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2848 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2849 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2850 | } | |
2851 | macro_build_lui (p, counter, ep, reg); | |
2852 | if (p != NULL) | |
2853 | p += 4; | |
2854 | macro_build (p, counter, ep, | |
2855 | mips_isa < 3 ? "addiu" : "daddiu", | |
2856 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2857 | } | |
fb251650 | 2858 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2859 | { |
2860 | expressionS ex; | |
2861 | ||
2862 | /* If this is a reference to an external symbol, we want | |
2863 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2864 | Otherwise we want | |
2865 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2866 | nop | |
2867 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2868 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2869 | ex.X_add_number = ep->X_add_number; |
2870 | ep->X_add_number = 0; | |
8ea7f4e8 | 2871 | frag_grow (20); |
0dd2d296 ILT |
2872 | macro_build ((char *) NULL, counter, ep, |
2873 | mips_isa < 3 ? "lw" : "ld", | |
2874 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2875 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2876 | p = frag_var (rs_machine_dependent, 4, 0, | |
2877 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2878 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2879 | macro_build (p, counter, ep, | |
2880 | mips_isa < 3 ? "addiu" : "daddiu", | |
2881 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2882 | if (ex.X_add_number != 0) | |
2883 | { | |
2884 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2885 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2886 | ex.X_op = O_constant; | |
fb251650 ILT |
2887 | macro_build ((char *) NULL, counter, &ex, |
2888 | mips_isa < 3 ? "addiu" : "daddiu", | |
2889 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2890 | } | |
2891 | } | |
2892 | else if (mips_pic == SVR4_PIC) | |
2893 | { | |
2894 | expressionS ex; | |
2895 | int off; | |
2896 | ||
2897 | /* This is the large GOT case. If this is a reference to an | |
2898 | external symbol, we want | |
2899 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2900 | addu $reg,$reg,$gp | |
2901 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2902 | Otherwise, for a reference to a local symbol, we want | |
2903 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2904 | nop | |
2905 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2906 | If there is a constant, it must be added in after. */ | |
2907 | ex.X_add_number = ep->X_add_number; | |
2908 | ep->X_add_number = 0; | |
2909 | if (reg_needs_delay (GP)) | |
2910 | off = 4; | |
2911 | else | |
2912 | off = 0; | |
2913 | frag_grow (32); | |
2914 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2915 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2916 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2917 | mips_isa < 3 ? "addu" : "daddu", | |
2918 | "d,v,t", reg, reg, GP); | |
2919 | macro_build ((char *) NULL, counter, ep, | |
2920 | mips_isa < 3 ? "lw" : "ld", | |
2921 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2922 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2923 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2924 | mips_warn_about_macros), | |
2925 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2926 | if (off > 0) | |
2927 | { | |
2928 | /* We need a nop before loading from $gp. This special | |
2929 | check is required because the lui which starts the main | |
2930 | instruction stream does not refer to $gp, and so will not | |
2931 | insert the nop which may be required. */ | |
2932 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2933 | p += 4; | |
2934 | } | |
2935 | macro_build (p, counter, ep, | |
2936 | mips_isa < 3 ? "lw" : "ld", | |
2937 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2938 | p += 4; | |
2939 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2940 | p += 4; | |
2941 | macro_build (p, counter, ep, | |
2942 | mips_isa < 3 ? "addiu" : "daddiu", | |
2943 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2944 | if (ex.X_add_number != 0) | |
2945 | { | |
2946 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2947 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2948 | ex.X_op = O_constant; | |
2949 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2950 | mips_isa < 3 ? "addiu" : "daddiu", |
2951 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2952 | } | |
d9aba805 ILT |
2953 | } |
2954 | else if (mips_pic == EMBEDDED_PIC) | |
2955 | { | |
2956 | /* We always do | |
2957 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2958 | */ | |
2959 | macro_build ((char *) NULL, counter, ep, | |
2960 | mips_isa < 3 ? "addiu" : "daddiu", | |
2961 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2962 | } | |
2963 | else | |
2964 | abort (); | |
0dd2d296 ILT |
2965 | } |
2966 | ||
3d3c5039 ILT |
2967 | /* |
2968 | * Build macros | |
2969 | * This routine implements the seemingly endless macro or synthesized | |
2970 | * instructions and addressing modes in the mips assembly language. Many | |
2971 | * of these macros are simple and are similar to each other. These could | |
2972 | * probably be handled by some kind of table or grammer aproach instead of | |
2973 | * this verbose method. Others are not simple macros but are more like | |
2974 | * optimizing code generation. | |
2975 | * One interesting optimization is when several store macros appear | |
2976 | * consecutivly that would load AT with the upper half of the same address. | |
2977 | * The ensuing load upper instructions are ommited. This implies some kind | |
2978 | * of global optimization. We currently only optimize within a single macro. | |
2979 | * For many of the load and store macros if the address is specified as a | |
2980 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2981 | * first load register 'at' with zero and use it as the base register. The | |
2982 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2983 | * we're missing. | |
2984 | */ | |
2985 | static void | |
2986 | macro (ip) | |
2987 | struct mips_cl_insn *ip; | |
2988 | { | |
670a50eb ILT |
2989 | register int treg, sreg, dreg, breg; |
2990 | int tempreg; | |
2991 | int mask; | |
2992 | int icnt = 0; | |
2993 | int used_at; | |
670a50eb ILT |
2994 | expressionS expr1; |
2995 | const char *s; | |
8358c818 | 2996 | const char *s2; |
670a50eb | 2997 | const char *fmt; |
8358c818 ILT |
2998 | int likely = 0; |
2999 | int dbl = 0; | |
3000 | int coproc = 0; | |
b2b8c24e | 3001 | int lr = 0; |
6e8dda9c | 3002 | offsetT maxnum; |
adcf2b9d | 3003 | int off; |
9226253a | 3004 | bfd_reloc_code_real_type r; |
0dd2d296 | 3005 | char *p; |
55933a58 | 3006 | int hold_mips_optimize; |
670a50eb | 3007 | |
cc5703cd ILT |
3008 | assert (! mips16); |
3009 | ||
670a50eb ILT |
3010 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3011 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3012 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3013 | mask = ip->insn_mo->mask; | |
3014 | ||
5ac34ac3 ILT |
3015 | expr1.X_op = O_constant; |
3016 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3017 | expr1.X_add_symbol = NULL; |
3018 | expr1.X_add_number = 1; | |
3019 | ||
3020 | switch (mask) | |
3021 | { | |
6e8dda9c ILT |
3022 | case M_DABS: |
3023 | dbl = 1; | |
3d3c5039 | 3024 | case M_ABS: |
6e8dda9c ILT |
3025 | /* bgez $a0,.+12 |
3026 | move v0,$a0 | |
3027 | sub v0,$zero,$a0 | |
3028 | */ | |
3d3c5039 | 3029 | |
fbcfacb7 | 3030 | mips_emit_delays (true); |
becfe05e | 3031 | ++mips_noreorder; |
0dd2d296 | 3032 | mips_any_noreorder = 1; |
3d3c5039 | 3033 | |
670a50eb | 3034 | expr1.X_add_number = 8; |
0dd2d296 | 3035 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3036 | if (dreg == sreg) |
0dd2d296 | 3037 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3038 | else |
0dd2d296 ILT |
3039 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3040 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3041 | dbl ? "dsub" : "sub", |
3042 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3043 | |
becfe05e | 3044 | --mips_noreorder; |
670a50eb | 3045 | return; |
3d3c5039 ILT |
3046 | |
3047 | case M_ADD_I: | |
8358c818 ILT |
3048 | s = "addi"; |
3049 | s2 = "add"; | |
3050 | goto do_addi; | |
3d3c5039 | 3051 | case M_ADDU_I: |
8358c818 ILT |
3052 | s = "addiu"; |
3053 | s2 = "addu"; | |
3054 | goto do_addi; | |
3055 | case M_DADD_I: | |
6e8dda9c | 3056 | dbl = 1; |
8358c818 ILT |
3057 | s = "daddi"; |
3058 | s2 = "dadd"; | |
3059 | goto do_addi; | |
3060 | case M_DADDU_I: | |
6e8dda9c | 3061 | dbl = 1; |
8358c818 ILT |
3062 | s = "daddiu"; |
3063 | s2 = "daddu"; | |
3064 | do_addi: | |
6e8dda9c | 3065 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3066 | { |
0dd2d296 | 3067 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3068 | (int) BFD_RELOC_LO16); |
670a50eb | 3069 | return; |
3d3c5039 | 3070 | } |
d8a1c247 | 3071 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3072 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3073 | break; |
3d3c5039 ILT |
3074 | |
3075 | case M_AND_I: | |
6e8dda9c ILT |
3076 | s = "andi"; |
3077 | s2 = "and"; | |
3078 | goto do_bit; | |
3d3c5039 | 3079 | case M_OR_I: |
6e8dda9c ILT |
3080 | s = "ori"; |
3081 | s2 = "or"; | |
3082 | goto do_bit; | |
3d3c5039 | 3083 | case M_NOR_I: |
6e8dda9c ILT |
3084 | s = ""; |
3085 | s2 = "nor"; | |
3086 | goto do_bit; | |
3d3c5039 | 3087 | case M_XOR_I: |
6e8dda9c ILT |
3088 | s = "xori"; |
3089 | s2 = "xor"; | |
3090 | do_bit: | |
3091 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3092 | { |
6e8dda9c | 3093 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3094 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3095 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3096 | else |
670a50eb | 3097 | { |
0dd2d296 ILT |
3098 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3099 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3100 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3101 | treg, treg, 0); |
3d3c5039 | 3102 | } |
6e8dda9c | 3103 | return; |
3d3c5039 | 3104 | } |
6e8dda9c | 3105 | |
d8a1c247 | 3106 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3107 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3108 | break; |
3d3c5039 ILT |
3109 | |
3110 | case M_BEQ_I: | |
8358c818 ILT |
3111 | s = "beq"; |
3112 | goto beq_i; | |
3113 | case M_BEQL_I: | |
3114 | s = "beql"; | |
3115 | likely = 1; | |
3116 | goto beq_i; | |
3d3c5039 | 3117 | case M_BNE_I: |
8358c818 ILT |
3118 | s = "bne"; |
3119 | goto beq_i; | |
3120 | case M_BNEL_I: | |
3121 | s = "bnel"; | |
3122 | likely = 1; | |
3123 | beq_i: | |
670a50eb ILT |
3124 | if (imm_expr.X_add_number == 0) |
3125 | { | |
0dd2d296 ILT |
3126 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3127 | 0); | |
670a50eb ILT |
3128 | return; |
3129 | } | |
d8a1c247 | 3130 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3131 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3132 | break; |
3d3c5039 | 3133 | |
8358c818 ILT |
3134 | case M_BGEL: |
3135 | likely = 1; | |
3d3c5039 | 3136 | case M_BGE: |
670a50eb ILT |
3137 | if (treg == 0) |
3138 | { | |
0dd2d296 | 3139 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3140 | likely ? "bgezl" : "bgez", |
3141 | "s,p", sreg); | |
670a50eb | 3142 | return; |
3d3c5039 | 3143 | } |
9a7d824a ILT |
3144 | if (sreg == 0) |
3145 | { | |
0dd2d296 | 3146 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3147 | likely ? "blezl" : "blez", |
3148 | "s,p", treg); | |
9a7d824a ILT |
3149 | return; |
3150 | } | |
0dd2d296 ILT |
3151 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3152 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3153 | likely ? "beql" : "beq", |
3154 | "s,t,p", AT, 0); | |
670a50eb | 3155 | break; |
3d3c5039 | 3156 | |
8358c818 ILT |
3157 | case M_BGTL_I: |
3158 | likely = 1; | |
3d3c5039 | 3159 | case M_BGT_I: |
9a7d824a | 3160 | /* check for > max integer */ |
6e8dda9c ILT |
3161 | maxnum = 0x7fffffff; |
3162 | if (mips_isa >= 3) | |
3163 | { | |
3164 | maxnum <<= 16; | |
3165 | maxnum |= 0xffff; | |
3166 | maxnum <<= 16; | |
3167 | maxnum |= 0xffff; | |
3168 | } | |
7b777690 ILT |
3169 | if (imm_expr.X_add_number >= maxnum |
3170 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3171 | { |
3172 | do_false: | |
3173 | /* result is always false */ | |
8358c818 ILT |
3174 | if (! likely) |
3175 | { | |
3176 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3177 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3178 | } |
3179 | else | |
3180 | { | |
3181 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3182 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3183 | "s,t,p", 0, 0); | |
8358c818 | 3184 | } |
9a7d824a ILT |
3185 | return; |
3186 | } | |
670a50eb ILT |
3187 | imm_expr.X_add_number++; |
3188 | /* FALLTHROUGH */ | |
3d3c5039 | 3189 | case M_BGE_I: |
8358c818 ILT |
3190 | case M_BGEL_I: |
3191 | if (mask == M_BGEL_I) | |
3192 | likely = 1; | |
670a50eb ILT |
3193 | if (imm_expr.X_add_number == 0) |
3194 | { | |
0dd2d296 | 3195 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3196 | likely ? "bgezl" : "bgez", |
3197 | "s,p", sreg); | |
670a50eb | 3198 | return; |
3d3c5039 | 3199 | } |
670a50eb ILT |
3200 | if (imm_expr.X_add_number == 1) |
3201 | { | |
0dd2d296 | 3202 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3203 | likely ? "bgtzl" : "bgtz", |
3204 | "s,p", sreg); | |
670a50eb | 3205 | return; |
3d3c5039 | 3206 | } |
6e8dda9c ILT |
3207 | maxnum = 0x7fffffff; |
3208 | if (mips_isa >= 3) | |
3209 | { | |
3210 | maxnum <<= 16; | |
3211 | maxnum |= 0xffff; | |
3212 | maxnum <<= 16; | |
3213 | maxnum |= 0xffff; | |
3214 | } | |
3215 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3216 | if (imm_expr.X_add_number <= maxnum |
3217 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3218 | { |
3219 | do_true: | |
3220 | /* result is always true */ | |
3221 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3222 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3223 | return; |
3224 | } | |
6e8dda9c | 3225 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3226 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3227 | likely ? "beql" : "beq", |
3228 | "s,t,p", AT, 0); | |
670a50eb | 3229 | break; |
3d3c5039 | 3230 | |
8358c818 ILT |
3231 | case M_BGEUL: |
3232 | likely = 1; | |
3d3c5039 | 3233 | case M_BGEU: |
670a50eb | 3234 | if (treg == 0) |
9a7d824a ILT |
3235 | goto do_true; |
3236 | if (sreg == 0) | |
670a50eb | 3237 | { |
0dd2d296 | 3238 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3239 | likely ? "beql" : "beq", |
3240 | "s,t,p", 0, treg); | |
670a50eb | 3241 | return; |
3d3c5039 | 3242 | } |
0dd2d296 ILT |
3243 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3244 | treg); | |
3245 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3246 | likely ? "beql" : "beq", |
3247 | "s,t,p", AT, 0); | |
670a50eb | 3248 | break; |
3d3c5039 | 3249 | |
8358c818 ILT |
3250 | case M_BGTUL_I: |
3251 | likely = 1; | |
9a7d824a | 3252 | case M_BGTU_I: |
6e8dda9c | 3253 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3254 | goto do_false; |
3255 | imm_expr.X_add_number++; | |
3256 | /* FALLTHROUGH */ | |
3d3c5039 | 3257 | case M_BGEU_I: |
8358c818 ILT |
3258 | case M_BGEUL_I: |
3259 | if (mask == M_BGEUL_I) | |
3260 | likely = 1; | |
670a50eb | 3261 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3262 | goto do_true; |
670a50eb ILT |
3263 | if (imm_expr.X_add_number == 1) |
3264 | { | |
0dd2d296 | 3265 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3266 | likely ? "bnel" : "bne", |
3267 | "s,t,p", sreg, 0); | |
670a50eb | 3268 | return; |
3d3c5039 | 3269 | } |
6e8dda9c | 3270 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3271 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3272 | likely ? "beql" : "beq", |
3273 | "s,t,p", AT, 0); | |
670a50eb | 3274 | break; |
3d3c5039 | 3275 | |
8358c818 ILT |
3276 | case M_BGTL: |
3277 | likely = 1; | |
3d3c5039 | 3278 | case M_BGT: |
670a50eb ILT |
3279 | if (treg == 0) |
3280 | { | |
0dd2d296 | 3281 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3282 | likely ? "bgtzl" : "bgtz", |
3283 | "s,p", sreg); | |
670a50eb | 3284 | return; |
3d3c5039 | 3285 | } |
9a7d824a ILT |
3286 | if (sreg == 0) |
3287 | { | |
0dd2d296 | 3288 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3289 | likely ? "bltzl" : "bltz", |
3290 | "s,p", treg); | |
9a7d824a ILT |
3291 | return; |
3292 | } | |
0dd2d296 ILT |
3293 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3294 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3295 | likely ? "bnel" : "bne", |
3296 | "s,t,p", AT, 0); | |
670a50eb | 3297 | break; |
3d3c5039 | 3298 | |
8358c818 ILT |
3299 | case M_BGTUL: |
3300 | likely = 1; | |
3d3c5039 | 3301 | case M_BGTU: |
670a50eb ILT |
3302 | if (treg == 0) |
3303 | { | |
0dd2d296 | 3304 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3305 | likely ? "bnel" : "bne", |
3306 | "s,t,p", sreg, 0); | |
670a50eb | 3307 | return; |
3d3c5039 | 3308 | } |
9a7d824a ILT |
3309 | if (sreg == 0) |
3310 | goto do_false; | |
0dd2d296 ILT |
3311 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3312 | sreg); | |
3313 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3314 | likely ? "bnel" : "bne", |
3315 | "s,t,p", AT, 0); | |
670a50eb | 3316 | break; |
3d3c5039 | 3317 | |
8358c818 ILT |
3318 | case M_BLEL: |
3319 | likely = 1; | |
3d3c5039 | 3320 | case M_BLE: |
670a50eb ILT |
3321 | if (treg == 0) |
3322 | { | |
0dd2d296 | 3323 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3324 | likely ? "blezl" : "blez", |
3325 | "s,p", sreg); | |
670a50eb ILT |
3326 | return; |
3327 | } | |
9a7d824a ILT |
3328 | if (sreg == 0) |
3329 | { | |
0dd2d296 | 3330 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3331 | likely ? "bgezl" : "bgez", |
3332 | "s,p", treg); | |
9a7d824a ILT |
3333 | return; |
3334 | } | |
0dd2d296 ILT |
3335 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3336 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3337 | likely ? "beql" : "beq", |
3338 | "s,t,p", AT, 0); | |
670a50eb | 3339 | break; |
3d3c5039 | 3340 | |
8358c818 ILT |
3341 | case M_BLEL_I: |
3342 | likely = 1; | |
3d3c5039 | 3343 | case M_BLE_I: |
6e8dda9c ILT |
3344 | maxnum = 0x7fffffff; |
3345 | if (mips_isa >= 3) | |
3346 | { | |
3347 | maxnum <<= 16; | |
3348 | maxnum |= 0xffff; | |
3349 | maxnum <<= 16; | |
3350 | maxnum |= 0xffff; | |
3351 | } | |
7b777690 ILT |
3352 | if (imm_expr.X_add_number >= maxnum |
3353 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3354 | goto do_true; |
3355 | imm_expr.X_add_number++; | |
3356 | /* FALLTHROUGH */ | |
9a7d824a | 3357 | case M_BLT_I: |
8358c818 ILT |
3358 | case M_BLTL_I: |
3359 | if (mask == M_BLTL_I) | |
3360 | likely = 1; | |
670a50eb ILT |
3361 | if (imm_expr.X_add_number == 0) |
3362 | { | |
0dd2d296 | 3363 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3364 | likely ? "bltzl" : "bltz", |
3365 | "s,p", sreg); | |
670a50eb ILT |
3366 | return; |
3367 | } | |
9a7d824a | 3368 | if (imm_expr.X_add_number == 1) |
670a50eb | 3369 | { |
0dd2d296 | 3370 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3371 | likely ? "blezl" : "blez", |
3372 | "s,p", sreg); | |
670a50eb ILT |
3373 | return; |
3374 | } | |
6e8dda9c | 3375 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3376 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3377 | likely ? "bnel" : "bne", |
3378 | "s,t,p", AT, 0); | |
670a50eb | 3379 | break; |
3d3c5039 | 3380 | |
8358c818 ILT |
3381 | case M_BLEUL: |
3382 | likely = 1; | |
3d3c5039 | 3383 | case M_BLEU: |
670a50eb ILT |
3384 | if (treg == 0) |
3385 | { | |
0dd2d296 | 3386 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3387 | likely ? "beql" : "beq", |
3388 | "s,t,p", sreg, 0); | |
670a50eb | 3389 | return; |
3d3c5039 | 3390 | } |
9a7d824a ILT |
3391 | if (sreg == 0) |
3392 | goto do_true; | |
0dd2d296 ILT |
3393 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3394 | sreg); | |
3395 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3396 | likely ? "beql" : "beq", |
3397 | "s,t,p", AT, 0); | |
670a50eb | 3398 | break; |
3d3c5039 | 3399 | |
8358c818 ILT |
3400 | case M_BLEUL_I: |
3401 | likely = 1; | |
3d3c5039 | 3402 | case M_BLEU_I: |
6e8dda9c | 3403 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3404 | goto do_true; |
3405 | imm_expr.X_add_number++; | |
3406 | /* FALLTHROUGH */ | |
9a7d824a | 3407 | case M_BLTU_I: |
8358c818 ILT |
3408 | case M_BLTUL_I: |
3409 | if (mask == M_BLTUL_I) | |
3410 | likely = 1; | |
670a50eb | 3411 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3412 | goto do_false; |
3413 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3414 | { |
0dd2d296 | 3415 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3416 | likely ? "beql" : "beq", |
3417 | "s,t,p", sreg, 0); | |
670a50eb | 3418 | return; |
3d3c5039 | 3419 | } |
6e8dda9c | 3420 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3421 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3422 | likely ? "bnel" : "bne", |
3423 | "s,t,p", AT, 0); | |
670a50eb | 3424 | break; |
3d3c5039 | 3425 | |
8358c818 ILT |
3426 | case M_BLTL: |
3427 | likely = 1; | |
3d3c5039 | 3428 | case M_BLT: |
670a50eb ILT |
3429 | if (treg == 0) |
3430 | { | |
0dd2d296 | 3431 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3432 | likely ? "bltzl" : "bltz", |
3433 | "s,p", sreg); | |
670a50eb | 3434 | return; |
3d3c5039 | 3435 | } |
9a7d824a | 3436 | if (sreg == 0) |
670a50eb | 3437 | { |
0dd2d296 | 3438 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3439 | likely ? "bgtzl" : "bgtz", |
3440 | "s,p", treg); | |
670a50eb | 3441 | return; |
3d3c5039 | 3442 | } |
0dd2d296 ILT |
3443 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3444 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3445 | likely ? "bnel" : "bne", |
3446 | "s,t,p", AT, 0); | |
670a50eb | 3447 | break; |
3d3c5039 | 3448 | |
8358c818 ILT |
3449 | case M_BLTUL: |
3450 | likely = 1; | |
3d3c5039 | 3451 | case M_BLTU: |
670a50eb | 3452 | if (treg == 0) |
9a7d824a ILT |
3453 | goto do_false; |
3454 | if (sreg == 0) | |
670a50eb | 3455 | { |
0dd2d296 | 3456 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3457 | likely ? "bnel" : "bne", |
3458 | "s,t,p", 0, treg); | |
670a50eb ILT |
3459 | return; |
3460 | } | |
0dd2d296 ILT |
3461 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3462 | treg); | |
3463 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3464 | likely ? "bnel" : "bne", |
3465 | "s,t,p", AT, 0); | |
670a50eb | 3466 | break; |
3d3c5039 | 3467 | |
8358c818 ILT |
3468 | case M_DDIV_3: |
3469 | dbl = 1; | |
3d3c5039 | 3470 | case M_DIV_3: |
8358c818 ILT |
3471 | s = "mflo"; |
3472 | goto do_div3; | |
3473 | case M_DREM_3: | |
3474 | dbl = 1; | |
3d3c5039 | 3475 | case M_REM_3: |
8358c818 ILT |
3476 | s = "mfhi"; |
3477 | do_div3: | |
670a50eb ILT |
3478 | if (treg == 0) |
3479 | { | |
3480 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3481 | if (mips_trap) |
3482 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3483 | else | |
3484 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3485 | return; |
3486 | } | |
3487 | ||
fbcfacb7 | 3488 | mips_emit_delays (true); |
becfe05e | 3489 | ++mips_noreorder; |
0dd2d296 ILT |
3490 | mips_any_noreorder = 1; |
3491 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3492 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3493 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3494 | if (mips_trap) |
3495 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3496 | else | |
3497 | { | |
3498 | expr1.X_add_number = 8; | |
3499 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3500 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3501 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3502 | } | |
670a50eb | 3503 | expr1.X_add_number = -1; |
0dd2d296 | 3504 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3505 | dbl ? "daddiu" : "addiu", |
9226253a | 3506 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3507 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3508 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3509 | if (dbl) |
3510 | { | |
3511 | expr1.X_add_number = 1; | |
0dd2d296 | 3512 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3513 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3514 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3515 | 31); | |
8358c818 ILT |
3516 | } |
3517 | else | |
3518 | { | |
3519 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3520 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3521 | (int) BFD_RELOC_HI16); | |
8358c818 | 3522 | } |
8ea7f4e8 ILT |
3523 | if (mips_trap) |
3524 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3525 | else | |
3526 | { | |
3527 | expr1.X_add_number = 8; | |
3528 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3529 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3530 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3531 | } | |
becfe05e | 3532 | --mips_noreorder; |
0dd2d296 | 3533 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3534 | break; |
3d3c5039 ILT |
3535 | |
3536 | case M_DIV_3I: | |
8358c818 ILT |
3537 | s = "div"; |
3538 | s2 = "mflo"; | |
3539 | goto do_divi; | |
3d3c5039 | 3540 | case M_DIVU_3I: |
8358c818 ILT |
3541 | s = "divu"; |
3542 | s2 = "mflo"; | |
3543 | goto do_divi; | |
3d3c5039 | 3544 | case M_REM_3I: |
8358c818 ILT |
3545 | s = "div"; |
3546 | s2 = "mfhi"; | |
3547 | goto do_divi; | |
3d3c5039 | 3548 | case M_REMU_3I: |
8358c818 ILT |
3549 | s = "divu"; |
3550 | s2 = "mfhi"; | |
3551 | goto do_divi; | |
3552 | case M_DDIV_3I: | |
3553 | dbl = 1; | |
3554 | s = "ddiv"; | |
3555 | s2 = "mflo"; | |
3556 | goto do_divi; | |
3557 | case M_DDIVU_3I: | |
3558 | dbl = 1; | |
3559 | s = "ddivu"; | |
3560 | s2 = "mflo"; | |
3561 | goto do_divi; | |
3562 | case M_DREM_3I: | |
3563 | dbl = 1; | |
3564 | s = "ddiv"; | |
3565 | s2 = "mfhi"; | |
3566 | goto do_divi; | |
3567 | case M_DREMU_3I: | |
3568 | dbl = 1; | |
3569 | s = "ddivu"; | |
3570 | s2 = "mfhi"; | |
3571 | do_divi: | |
670a50eb ILT |
3572 | if (imm_expr.X_add_number == 0) |
3573 | { | |
3574 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3575 | if (mips_trap) |
3576 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3577 | else | |
3578 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3579 | return; |
3580 | } | |
3581 | if (imm_expr.X_add_number == 1) | |
3582 | { | |
8358c818 | 3583 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3584 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3585 | sreg); | |
3d3c5039 | 3586 | else |
0dd2d296 | 3587 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3588 | return; |
3589 | } | |
8358c818 ILT |
3590 | if (imm_expr.X_add_number == -1 |
3591 | && s[strlen (s) - 1] != 'u') | |
3592 | { | |
3593 | if (strcmp (s2, "mflo") == 0) | |
3594 | { | |
3595 | if (dbl) | |
0dd2d296 ILT |
3596 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3597 | sreg); | |
8358c818 | 3598 | else |
0dd2d296 ILT |
3599 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3600 | sreg); | |
8358c818 ILT |
3601 | } |
3602 | else | |
0dd2d296 | 3603 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3604 | return; |
3605 | } | |
3d3c5039 | 3606 | |
d8a1c247 | 3607 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3608 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3609 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3610 | break; |
3611 | ||
3612 | case M_DIVU_3: | |
8358c818 ILT |
3613 | s = "divu"; |
3614 | s2 = "mflo"; | |
3615 | goto do_divu3; | |
670a50eb | 3616 | case M_REMU_3: |
8358c818 ILT |
3617 | s = "divu"; |
3618 | s2 = "mfhi"; | |
3619 | goto do_divu3; | |
3620 | case M_DDIVU_3: | |
3621 | s = "ddivu"; | |
3622 | s2 = "mflo"; | |
3623 | goto do_divu3; | |
3624 | case M_DREMU_3: | |
3625 | s = "ddivu"; | |
3626 | s2 = "mfhi"; | |
3627 | do_divu3: | |
fbcfacb7 | 3628 | mips_emit_delays (true); |
becfe05e | 3629 | ++mips_noreorder; |
0dd2d296 ILT |
3630 | mips_any_noreorder = 1; |
3631 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3632 | if (mips_trap) |
3633 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3634 | else | |
3635 | { | |
3636 | expr1.X_add_number = 8; | |
3637 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3638 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3639 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3640 | } | |
becfe05e | 3641 | --mips_noreorder; |
0dd2d296 | 3642 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3643 | return; |
3d3c5039 | 3644 | |
d8a1c247 KR |
3645 | case M_DLA_AB: |
3646 | dbl = 1; | |
0dd2d296 | 3647 | case M_LA_AB: |
d9aba805 ILT |
3648 | /* Load the address of a symbol into a register. If breg is not |
3649 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3650 | |
3651 | /* When generating embedded PIC code, we permit expressions of | |
3652 | the form | |
3653 | la $4,foo-bar | |
3654 | where bar is an address in the .text section. These are used | |
3655 | when getting the addresses of functions. We don't permit | |
3656 | X_add_number to be non-zero, because if the symbol is | |
3657 | external the relaxing code needs to know that any addend is | |
3658 | purely the offset to X_op_symbol. */ | |
3659 | if (mips_pic == EMBEDDED_PIC | |
3660 | && offset_expr.X_op == O_subtract | |
3661 | && now_seg == text_section | |
847a01cd ILT |
3662 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3663 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3664 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3665 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3666 | ->sy_value.X_add_symbol) | |
3667 | == text_section))) | |
ecd4ca1c ILT |
3668 | && breg == 0 |
3669 | && offset_expr.X_add_number == 0) | |
3670 | { | |
3671 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3672 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3673 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3674 | mips_isa < 3 ? "addiu" : "daddiu", | |
3675 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3676 | return; | |
3677 | } | |
3678 | ||
0dd2d296 ILT |
3679 | if (offset_expr.X_op != O_symbol |
3680 | && offset_expr.X_op != O_constant) | |
670a50eb | 3681 | { |
0dd2d296 ILT |
3682 | as_bad ("expression too complex"); |
3683 | offset_expr.X_op = O_constant; | |
3684 | } | |
3685 | ||
3686 | if (treg == breg) | |
3687 | { | |
3688 | tempreg = AT; | |
3689 | used_at = 1; | |
3d3c5039 | 3690 | } |
670a50eb ILT |
3691 | else |
3692 | { | |
0dd2d296 ILT |
3693 | tempreg = treg; |
3694 | used_at = 0; | |
670a50eb | 3695 | } |
3d3c5039 | 3696 | |
5ac34ac3 | 3697 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3698 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3699 | else if (mips_pic == NO_PIC) |
670a50eb | 3700 | { |
0dd2d296 ILT |
3701 | /* If this is a reference to an GP relative symbol, we want |
3702 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3703 | Otherwise we want | |
3704 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3705 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3706 | If we have a constant, we need two instructions anyhow, | |
3707 | so we may as well always use the latter form. */ | |
7a15a226 | 3708 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3709 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3710 | p = NULL; |
3711 | else | |
3712 | { | |
8ea7f4e8 | 3713 | frag_grow (20); |
0dd2d296 ILT |
3714 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3715 | mips_isa < 3 ? "addiu" : "daddiu", | |
3716 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3717 | p = frag_var (rs_machine_dependent, 8, 0, | |
3718 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3719 | mips_warn_about_macros), | |
3720 | offset_expr.X_add_symbol, (long) 0, | |
3721 | (char *) NULL); | |
3722 | } | |
3723 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3724 | if (p != NULL) | |
3725 | p += 4; | |
3726 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3727 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3728 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3729 | } | |
fb251650 | 3730 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3731 | { |
3732 | /* If this is a reference to an external symbol, and there | |
3733 | is no constant, we want | |
3734 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3735 | For a local symbol, we want | |
3736 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3737 | nop | |
3738 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3739 | ||
3740 | If we have a small constant, and this is a reference to | |
3741 | an external symbol, we want | |
3742 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3743 | nop | |
3744 | addiu $tempreg,$tempreg,<constant> | |
3745 | For a local symbol, we want the same instruction | |
3746 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3747 | addiu instruction. | |
3748 | ||
3749 | If we have a large constant, and this is a reference to | |
3750 | an external symbol, we want | |
3751 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3752 | lui $at,<hiconstant> | |
3753 | addiu $at,$at,<loconstant> | |
3754 | addu $tempreg,$tempreg,$at | |
3755 | For a local symbol, we want the same instruction | |
3756 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3757 | addiu instruction. */ | |
3758 | expr1.X_add_number = offset_expr.X_add_number; | |
3759 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3760 | frag_grow (32); |
0dd2d296 | 3761 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3762 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3763 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3764 | if (expr1.X_add_number == 0) | |
3765 | { | |
3766 | int off; | |
3767 | ||
3768 | if (breg == 0) | |
3769 | off = 0; | |
3770 | else | |
3771 | { | |
3772 | /* We're going to put in an addu instruction using | |
3773 | tempreg, so we may as well insert the nop right | |
3774 | now. */ | |
3775 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3776 | "nop", ""); | |
3777 | off = 4; | |
3778 | } | |
3779 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3780 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3781 | (breg == 0 | |
3782 | ? mips_warn_about_macros | |
3783 | : 0)), | |
3784 | offset_expr.X_add_symbol, (long) 0, | |
3785 | (char *) NULL); | |
3786 | if (breg == 0) | |
3787 | { | |
3788 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3789 | p += 4; | |
3790 | } | |
3791 | macro_build (p, &icnt, &expr1, | |
3792 | mips_isa < 3 ? "addiu" : "daddiu", | |
3793 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3794 | /* FIXME: If breg == 0, and the next instruction uses | |
3795 | $tempreg, then if this variant case is used an extra | |
3796 | nop will be generated. */ | |
3797 | } | |
3798 | else if (expr1.X_add_number >= -0x8000 | |
3799 | && expr1.X_add_number < 0x8000) | |
3800 | { | |
3801 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3802 | "nop", ""); | |
3803 | macro_build ((char *) NULL, &icnt, &expr1, | |
3804 | mips_isa < 3 ? "addiu" : "daddiu", | |
3805 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3806 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3807 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3808 | offset_expr.X_add_symbol, (long) 0, | |
3809 | (char *) NULL); | |
3810 | } | |
3811 | else | |
3812 | { | |
3813 | int off1; | |
3814 | ||
3815 | /* If we are going to add in a base register, and the | |
3816 | target register and the base register are the same, | |
3817 | then we are using AT as a temporary register. Since | |
3818 | we want to load the constant into AT, we add our | |
3819 | current AT (from the global offset table) and the | |
3820 | register into the register now, and pretend we were | |
3821 | not using a base register. */ | |
3822 | if (breg != treg) | |
3823 | off1 = 0; | |
3824 | else | |
3825 | { | |
3826 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3827 | "nop", ""); | |
3828 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3829 | mips_isa < 3 ? "addu" : "daddu", | |
3830 | "d,v,t", treg, AT, breg); | |
3831 | breg = 0; | |
3832 | tempreg = treg; | |
3833 | off1 = -8; | |
3834 | } | |
3835 | ||
55933a58 ILT |
3836 | /* Set mips_optimize around the lui instruction to avoid |
3837 | inserting an unnecessary nop after the lw. */ | |
3838 | hold_mips_optimize = mips_optimize; | |
3839 | mips_optimize = 2; | |
0dd2d296 | 3840 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3841 | mips_optimize = hold_mips_optimize; |
3842 | ||
0dd2d296 ILT |
3843 | macro_build ((char *) NULL, &icnt, &expr1, |
3844 | mips_isa < 3 ? "addiu" : "daddiu", | |
3845 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3847 | mips_isa < 3 ? "addu" : "daddu", | |
3848 | "d,v,t", tempreg, tempreg, AT); | |
3849 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3850 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3851 | offset_expr.X_add_symbol, (long) 0, | |
3852 | (char *) NULL); | |
3853 | used_at = 1; | |
3854 | } | |
670a50eb | 3855 | } |
fb251650 ILT |
3856 | else if (mips_pic == SVR4_PIC) |
3857 | { | |
3858 | int gpdel; | |
3859 | ||
3860 | /* This is the large GOT case. If this is a reference to an | |
3861 | external symbol, and there is no constant, we want | |
3862 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3863 | addu $tempreg,$tempreg,$gp | |
3864 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3865 | For a local symbol, we want | |
3866 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3867 | nop | |
3868 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3869 | ||
3870 | If we have a small constant, and this is a reference to | |
3871 | an external symbol, we want | |
3872 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3873 | addu $tempreg,$tempreg,$gp | |
3874 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3875 | nop | |
3876 | addiu $tempreg,$tempreg,<constant> | |
3877 | For a local symbol, we want | |
3878 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3879 | nop | |
3880 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3881 | ||
3882 | If we have a large constant, and this is a reference to | |
3883 | an external symbol, we want | |
3884 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3885 | addu $tempreg,$tempreg,$gp | |
3886 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3887 | lui $at,<hiconstant> | |
3888 | addiu $at,$at,<loconstant> | |
3889 | addu $tempreg,$tempreg,$at | |
3890 | For a local symbol, we want | |
3891 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3892 | lui $at,<hiconstant> | |
3893 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3894 | addu $tempreg,$tempreg,$at | |
3895 | */ | |
3896 | expr1.X_add_number = offset_expr.X_add_number; | |
3897 | offset_expr.X_add_number = 0; | |
3898 | frag_grow (52); | |
3899 | if (reg_needs_delay (GP)) | |
3900 | gpdel = 4; | |
3901 | else | |
3902 | gpdel = 0; | |
3903 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3904 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3905 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3906 | mips_isa < 3 ? "addu" : "daddu", | |
3907 | "d,v,t", tempreg, tempreg, GP); | |
3908 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3909 | dbl ? "ld" : "lw", | |
3910 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3911 | tempreg); | |
3912 | if (expr1.X_add_number == 0) | |
3913 | { | |
3914 | int off; | |
3915 | ||
3916 | if (breg == 0) | |
3917 | off = 0; | |
3918 | else | |
3919 | { | |
3920 | /* We're going to put in an addu instruction using | |
3921 | tempreg, so we may as well insert the nop right | |
3922 | now. */ | |
3923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3924 | "nop", ""); | |
3925 | off = 4; | |
3926 | } | |
3927 | ||
3928 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3929 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3930 | 8 + gpdel, 0, | |
3931 | (breg == 0 | |
3932 | ? mips_warn_about_macros | |
3933 | : 0)), | |
3934 | offset_expr.X_add_symbol, (long) 0, | |
3935 | (char *) NULL); | |
3936 | } | |
3937 | else if (expr1.X_add_number >= -0x8000 | |
3938 | && expr1.X_add_number < 0x8000) | |
3939 | { | |
3940 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3941 | "nop", ""); | |
3942 | macro_build ((char *) NULL, &icnt, &expr1, | |
3943 | mips_isa < 3 ? "addiu" : "daddiu", | |
3944 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3945 | ||
3946 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3947 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3948 | (breg == 0 | |
3949 | ? mips_warn_about_macros | |
3950 | : 0)), | |
3951 | offset_expr.X_add_symbol, (long) 0, | |
3952 | (char *) NULL); | |
3953 | } | |
3954 | else | |
3955 | { | |
3956 | int adj, dreg; | |
3957 | ||
3958 | /* If we are going to add in a base register, and the | |
3959 | target register and the base register are the same, | |
3960 | then we are using AT as a temporary register. Since | |
3961 | we want to load the constant into AT, we add our | |
3962 | current AT (from the global offset table) and the | |
3963 | register into the register now, and pretend we were | |
3964 | not using a base register. */ | |
3965 | if (breg != treg) | |
3966 | { | |
3967 | adj = 0; | |
3968 | dreg = tempreg; | |
3969 | } | |
3970 | else | |
3971 | { | |
3972 | assert (tempreg == AT); | |
3973 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3974 | "nop", ""); | |
3975 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3976 | mips_isa < 3 ? "addu" : "daddu", | |
3977 | "d,v,t", treg, AT, breg); | |
3978 | dreg = treg; | |
3979 | adj = 8; | |
3980 | } | |
3981 | ||
3982 | /* Set mips_optimize around the lui instruction to avoid | |
3983 | inserting an unnecessary nop after the lw. */ | |
3984 | hold_mips_optimize = mips_optimize; | |
3985 | mips_optimize = 2; | |
3986 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3987 | mips_optimize = hold_mips_optimize; | |
3988 | ||
3989 | macro_build ((char *) NULL, &icnt, &expr1, | |
3990 | mips_isa < 3 ? "addiu" : "daddiu", | |
3991 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3992 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3993 | mips_isa < 3 ? "addu" : "daddu", | |
3994 | "d,v,t", dreg, dreg, AT); | |
3995 | ||
3996 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
3997 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
3998 | 8 + gpdel, 0, | |
3999 | (breg == 0 | |
4000 | ? mips_warn_about_macros | |
4001 | : 0)), | |
4002 | offset_expr.X_add_symbol, (long) 0, | |
4003 | (char *) NULL); | |
4004 | ||
4005 | used_at = 1; | |
4006 | } | |
4007 | ||
4008 | if (gpdel > 0) | |
4009 | { | |
4010 | /* This is needed because this instruction uses $gp, but | |
4011 | the first instruction on the main stream does not. */ | |
4012 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4013 | p += 4; | |
4014 | } | |
4015 | macro_build (p, &icnt, &offset_expr, | |
4016 | dbl ? "ld" : "lw", | |
4017 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4018 | p += 4; | |
4019 | if (expr1.X_add_number >= -0x8000 | |
4020 | && expr1.X_add_number < 0x8000) | |
4021 | { | |
4022 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4023 | p += 4; | |
4024 | macro_build (p, &icnt, &expr1, | |
4025 | mips_isa < 3 ? "addiu" : "daddiu", | |
4026 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4027 | /* FIXME: If add_number is 0, and there was no base | |
4028 | register, the external symbol case ended with a load, | |
4029 | so if the symbol turns out to not be external, and | |
4030 | the next instruction uses tempreg, an unnecessary nop | |
4031 | will be inserted. */ | |
4032 | } | |
4033 | else | |
4034 | { | |
4035 | if (breg == treg) | |
4036 | { | |
4037 | /* We must add in the base register now, as in the | |
4038 | external symbol case. */ | |
4039 | assert (tempreg == AT); | |
4040 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4041 | p += 4; | |
4042 | macro_build (p, &icnt, (expressionS *) NULL, | |
4043 | mips_isa < 3 ? "addu" : "daddu", | |
4044 | "d,v,t", treg, AT, breg); | |
4045 | p += 4; | |
4046 | tempreg = treg; | |
4047 | /* We set breg to 0 because we have arranged to add | |
4048 | it in in both cases. */ | |
4049 | breg = 0; | |
4050 | } | |
4051 | ||
4052 | macro_build_lui (p, &icnt, &expr1, AT); | |
4053 | p += 4; | |
4054 | macro_build (p, &icnt, &expr1, | |
4055 | mips_isa < 3 ? "addiu" : "daddiu", | |
4056 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4057 | p += 4; | |
4058 | macro_build (p, &icnt, (expressionS *) NULL, | |
4059 | mips_isa < 3 ? "addu" : "daddu", | |
4060 | "d,v,t", tempreg, tempreg, AT); | |
4061 | p += 4; | |
4062 | } | |
4063 | } | |
d9aba805 ILT |
4064 | else if (mips_pic == EMBEDDED_PIC) |
4065 | { | |
4066 | /* We use | |
4067 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4068 | */ | |
4069 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4070 | mips_isa < 3 ? "addiu" : "daddiu", | |
4071 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4072 | } | |
4073 | else | |
4074 | abort (); | |
0dd2d296 | 4075 | |
670a50eb | 4076 | if (breg != 0) |
0dd2d296 ILT |
4077 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4078 | mips_isa < 3 ? "addu" : "daddu", | |
4079 | "d,v,t", treg, tempreg, breg); | |
4080 | ||
4081 | if (! used_at) | |
4082 | return; | |
4083 | ||
4084 | break; | |
4085 | ||
4086 | case M_J_A: | |
4087 | /* The j instruction may not be used in PIC code, since it | |
4088 | requires an absolute address. We convert it to a b | |
4089 | instruction. */ | |
d9aba805 | 4090 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4091 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4092 | else | |
4093 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4094 | return; |
3d3c5039 | 4095 | |
9226253a ILT |
4096 | /* The jal instructions must be handled as macros because when |
4097 | generating PIC code they expand to multi-instruction | |
4098 | sequences. Normally they are simple instructions. */ | |
4099 | case M_JAL_1: | |
4100 | dreg = RA; | |
4101 | /* Fall through. */ | |
4102 | case M_JAL_2: | |
d9aba805 ILT |
4103 | if (mips_pic == NO_PIC |
4104 | || mips_pic == EMBEDDED_PIC) | |
4105 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4106 | "d,s", dreg, sreg); | |
4107 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4108 | { |
d9aba805 ILT |
4109 | if (sreg != PIC_CALL_REG) |
4110 | as_warn ("MIPS PIC call to register other than $25"); | |
4111 | ||
0dd2d296 ILT |
4112 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4113 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4114 | if (mips_cprestore_offset < 0) |
4115 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4116 | else | |
4117 | { | |
4118 | expr1.X_add_number = mips_cprestore_offset; | |
4119 | macro_build ((char *) NULL, &icnt, &expr1, | |
4120 | mips_isa < 3 ? "lw" : "ld", | |
4121 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4122 | } | |
9226253a | 4123 | } |
0dd2d296 | 4124 | else |
d9aba805 ILT |
4125 | abort (); |
4126 | ||
9226253a ILT |
4127 | return; |
4128 | ||
4129 | case M_JAL_A: | |
d9aba805 ILT |
4130 | if (mips_pic == NO_PIC) |
4131 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4132 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4133 | { |
fb251650 ILT |
4134 | /* If this is a reference to an external symbol, and we are |
4135 | using a small GOT, we want | |
d9aba805 ILT |
4136 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4137 | nop | |
4138 | jalr $25 | |
4139 | nop | |
4140 | lw $gp,cprestore($sp) | |
4141 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4142 | pseudo-op. If we are using a big GOT, we want |
4143 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4144 | addu $25,$25,$gp | |
4145 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4146 | nop | |
4147 | jalr $25 | |
4148 | nop | |
4149 | lw $gp,cprestore($sp) | |
4150 | If the symbol is not external, we want | |
d9aba805 ILT |
4151 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4152 | nop | |
4153 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4154 | jalr $25 | |
4155 | nop | |
fb251650 ILT |
4156 | lw $gp,cprestore($sp) */ |
4157 | frag_grow (40); | |
4158 | if (! mips_big_got) | |
4159 | { | |
4160 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4161 | mips_isa < 3 ? "lw" : "ld", | |
4162 | "t,o(b)", PIC_CALL_REG, | |
4163 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4164 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4165 | "nop", ""); | |
4166 | p = frag_var (rs_machine_dependent, 4, 0, | |
4167 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4168 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4169 | } | |
4170 | else | |
4171 | { | |
4172 | int gpdel; | |
4173 | ||
4174 | if (reg_needs_delay (GP)) | |
4175 | gpdel = 4; | |
4176 | else | |
4177 | gpdel = 0; | |
4178 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4179 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4180 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4181 | mips_isa < 3 ? "addu" : "daddu", | |
4182 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4183 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4184 | mips_isa < 3 ? "lw" : "ld", | |
4185 | "t,o(b)", PIC_CALL_REG, | |
4186 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4187 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4188 | "nop", ""); | |
4189 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4190 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4191 | 0, 0), | |
4192 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4193 | if (gpdel > 0) | |
4194 | { | |
4195 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4196 | p += 4; | |
4197 | } | |
4198 | macro_build (p, &icnt, &offset_expr, | |
4199 | mips_isa < 3 ? "lw" : "ld", | |
4200 | "t,o(b)", PIC_CALL_REG, | |
4201 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4202 | p += 4; | |
4203 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4204 | p += 4; | |
4205 | } | |
d9aba805 ILT |
4206 | macro_build (p, &icnt, &offset_expr, |
4207 | mips_isa < 3 ? "addiu" : "daddiu", | |
4208 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4209 | (int) BFD_RELOC_LO16); | |
4210 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4211 | "jalr", "s", PIC_CALL_REG); | |
4212 | if (mips_cprestore_offset < 0) | |
4213 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4214 | else | |
4215 | { | |
4216 | if (mips_noreorder) | |
4217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4218 | "nop", ""); | |
4219 | expr1.X_add_number = mips_cprestore_offset; | |
4220 | macro_build ((char *) NULL, &icnt, &expr1, | |
4221 | mips_isa < 3 ? "lw" : "ld", | |
4222 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4223 | mips_frame_reg); | |
4224 | } | |
0dd2d296 | 4225 | } |
d9aba805 | 4226 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4227 | { |
4228 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4229 | /* The linker may expand the call to a longer sequence which | |
4230 | uses $at, so we must break rather than return. */ | |
4231 | break; | |
4232 | } | |
d9aba805 ILT |
4233 | else |
4234 | abort (); | |
4235 | ||
9226253a ILT |
4236 | return; |
4237 | ||
3d3c5039 | 4238 | case M_LB_AB: |
670a50eb ILT |
4239 | s = "lb"; |
4240 | goto ld; | |
3d3c5039 | 4241 | case M_LBU_AB: |
670a50eb ILT |
4242 | s = "lbu"; |
4243 | goto ld; | |
3d3c5039 | 4244 | case M_LH_AB: |
670a50eb ILT |
4245 | s = "lh"; |
4246 | goto ld; | |
3d3c5039 | 4247 | case M_LHU_AB: |
670a50eb ILT |
4248 | s = "lhu"; |
4249 | goto ld; | |
3d3c5039 | 4250 | case M_LW_AB: |
670a50eb ILT |
4251 | s = "lw"; |
4252 | goto ld; | |
3d3c5039 | 4253 | case M_LWC0_AB: |
670a50eb | 4254 | s = "lwc0"; |
8358c818 | 4255 | coproc = 1; |
670a50eb | 4256 | goto ld; |
3d3c5039 | 4257 | case M_LWC1_AB: |
670a50eb | 4258 | s = "lwc1"; |
8358c818 | 4259 | coproc = 1; |
670a50eb | 4260 | goto ld; |
3d3c5039 | 4261 | case M_LWC2_AB: |
670a50eb | 4262 | s = "lwc2"; |
8358c818 | 4263 | coproc = 1; |
670a50eb | 4264 | goto ld; |
3d3c5039 | 4265 | case M_LWC3_AB: |
670a50eb | 4266 | s = "lwc3"; |
8358c818 | 4267 | coproc = 1; |
670a50eb | 4268 | goto ld; |
3d3c5039 | 4269 | case M_LWL_AB: |
670a50eb | 4270 | s = "lwl"; |
b2b8c24e | 4271 | lr = 1; |
670a50eb | 4272 | goto ld; |
3d3c5039 | 4273 | case M_LWR_AB: |
670a50eb | 4274 | s = "lwr"; |
b2b8c24e | 4275 | lr = 1; |
8358c818 ILT |
4276 | goto ld; |
4277 | case M_LDC1_AB: | |
4278 | s = "ldc1"; | |
4279 | coproc = 1; | |
4280 | goto ld; | |
4281 | case M_LDC2_AB: | |
4282 | s = "ldc2"; | |
4283 | coproc = 1; | |
4284 | goto ld; | |
4285 | case M_LDC3_AB: | |
4286 | s = "ldc3"; | |
4287 | coproc = 1; | |
4288 | goto ld; | |
4289 | case M_LDL_AB: | |
4290 | s = "ldl"; | |
b2b8c24e | 4291 | lr = 1; |
8358c818 ILT |
4292 | goto ld; |
4293 | case M_LDR_AB: | |
4294 | s = "ldr"; | |
b2b8c24e | 4295 | lr = 1; |
8358c818 ILT |
4296 | goto ld; |
4297 | case M_LL_AB: | |
4298 | s = "ll"; | |
4299 | goto ld; | |
4300 | case M_LLD_AB: | |
4301 | s = "lld"; | |
4302 | goto ld; | |
4303 | case M_LWU_AB: | |
4304 | s = "lwu"; | |
3d3c5039 | 4305 | ld: |
b2b8c24e | 4306 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4307 | { |
4308 | tempreg = AT; | |
4309 | used_at = 1; | |
4310 | } | |
4311 | else | |
4312 | { | |
4313 | tempreg = treg; | |
4314 | used_at = 0; | |
4315 | } | |
4316 | goto ld_st; | |
3d3c5039 | 4317 | case M_SB_AB: |
670a50eb ILT |
4318 | s = "sb"; |
4319 | goto st; | |
3d3c5039 | 4320 | case M_SH_AB: |
670a50eb ILT |
4321 | s = "sh"; |
4322 | goto st; | |
3d3c5039 | 4323 | case M_SW_AB: |
670a50eb ILT |
4324 | s = "sw"; |
4325 | goto st; | |
3d3c5039 | 4326 | case M_SWC0_AB: |
670a50eb | 4327 | s = "swc0"; |
8358c818 | 4328 | coproc = 1; |
670a50eb | 4329 | goto st; |
3d3c5039 | 4330 | case M_SWC1_AB: |
670a50eb | 4331 | s = "swc1"; |
8358c818 | 4332 | coproc = 1; |
670a50eb | 4333 | goto st; |
3d3c5039 | 4334 | case M_SWC2_AB: |
670a50eb | 4335 | s = "swc2"; |
8358c818 | 4336 | coproc = 1; |
670a50eb | 4337 | goto st; |
3d3c5039 | 4338 | case M_SWC3_AB: |
670a50eb | 4339 | s = "swc3"; |
8358c818 | 4340 | coproc = 1; |
670a50eb | 4341 | goto st; |
3d3c5039 | 4342 | case M_SWL_AB: |
670a50eb ILT |
4343 | s = "swl"; |
4344 | goto st; | |
3d3c5039 | 4345 | case M_SWR_AB: |
670a50eb | 4346 | s = "swr"; |
8358c818 ILT |
4347 | goto st; |
4348 | case M_SC_AB: | |
4349 | s = "sc"; | |
4350 | goto st; | |
4351 | case M_SCD_AB: | |
4352 | s = "scd"; | |
4353 | goto st; | |
4354 | case M_SDC1_AB: | |
4355 | s = "sdc1"; | |
4356 | coproc = 1; | |
4357 | goto st; | |
4358 | case M_SDC2_AB: | |
4359 | s = "sdc2"; | |
4360 | coproc = 1; | |
4361 | goto st; | |
4362 | case M_SDC3_AB: | |
4363 | s = "sdc3"; | |
4364 | coproc = 1; | |
4365 | goto st; | |
4366 | case M_SDL_AB: | |
4367 | s = "sdl"; | |
4368 | goto st; | |
4369 | case M_SDR_AB: | |
4370 | s = "sdr"; | |
3d3c5039 | 4371 | st: |
670a50eb ILT |
4372 | tempreg = AT; |
4373 | used_at = 1; | |
3d3c5039 | 4374 | ld_st: |
8358c818 ILT |
4375 | if (mask == M_LWC1_AB |
4376 | || mask == M_SWC1_AB | |
8358c818 | 4377 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4378 | || mask == M_SDC1_AB |
4379 | || mask == M_L_DAB | |
4380 | || mask == M_S_DAB) | |
670a50eb | 4381 | fmt = "T,o(b)"; |
8358c818 | 4382 | else if (coproc) |
19ed8960 | 4383 | fmt = "E,o(b)"; |
670a50eb ILT |
4384 | else |
4385 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4386 | |
4387 | if (offset_expr.X_op != O_constant | |
4388 | && offset_expr.X_op != O_symbol) | |
4389 | { | |
4390 | as_bad ("expression too complex"); | |
4391 | offset_expr.X_op = O_constant; | |
4392 | } | |
4393 | ||
4394 | /* A constant expression in PIC code can be handled just as it | |
4395 | is in non PIC code. */ | |
d9aba805 | 4396 | if (mips_pic == NO_PIC |
0dd2d296 | 4397 | || offset_expr.X_op == O_constant) |
670a50eb | 4398 | { |
0dd2d296 ILT |
4399 | /* If this is a reference to a GP relative symbol, and there |
4400 | is no base register, we want | |
4401 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4402 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4403 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4404 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4405 | If we have a constant, we need two instructions anyhow, | |
4406 | so we always use the latter form. | |
4407 | ||
4408 | If we have a base register, and this is a reference to a | |
4409 | GP relative symbol, we want | |
4410 | addu $tempreg,$breg,$gp | |
4411 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4412 | Otherwise we want | |
4413 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4414 | addu $tempreg,$tempreg,$breg | |
4415 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4416 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4417 | if (breg == 0) |
4418 | { | |
7a15a226 | 4419 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4420 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4421 | p = NULL; |
4422 | else | |
4423 | { | |
8ea7f4e8 | 4424 | frag_grow (20); |
0dd2d296 ILT |
4425 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4426 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4427 | p = frag_var (rs_machine_dependent, 8, 0, | |
4428 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4429 | (mips_warn_about_macros |
4430 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4431 | offset_expr.X_add_symbol, (long) 0, |
4432 | (char *) NULL); | |
8197b589 | 4433 | used_at = 0; |
0dd2d296 ILT |
4434 | } |
4435 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4436 | if (p != NULL) | |
4437 | p += 4; | |
4438 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4439 | (int) BFD_RELOC_LO16, tempreg); | |
4440 | } | |
4441 | else | |
4442 | { | |
7a15a226 | 4443 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4444 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4445 | p = NULL; |
4446 | else | |
4447 | { | |
8ea7f4e8 | 4448 | frag_grow (28); |
0dd2d296 ILT |
4449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4450 | mips_isa < 3 ? "addu" : "daddu", | |
4451 | "d,v,t", tempreg, breg, GP); | |
4452 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4453 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4454 | p = frag_var (rs_machine_dependent, 12, 0, | |
4455 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4456 | offset_expr.X_add_symbol, (long) 0, | |
4457 | (char *) NULL); | |
4458 | } | |
4459 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4460 | if (p != NULL) | |
4461 | p += 4; | |
4462 | macro_build (p, &icnt, (expressionS *) NULL, | |
4463 | mips_isa < 3 ? "addu" : "daddu", | |
4464 | "d,v,t", tempreg, tempreg, breg); | |
4465 | if (p != NULL) | |
4466 | p += 4; | |
4467 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4468 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4469 | } |
670a50eb | 4470 | } |
fb251650 | 4471 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4472 | { |
0dd2d296 ILT |
4473 | /* If this is a reference to an external symbol, we want |
4474 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4475 | nop | |
4476 | <op> $treg,0($tempreg) | |
4477 | Otherwise we want | |
4478 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4479 | nop | |
4480 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4481 | <op> $treg,0($tempreg) | |
4482 | If there is a base register, we add it to $tempreg before | |
4483 | the <op>. If there is a constant, we stick it in the | |
4484 | <op> instruction. We don't handle constants larger than | |
4485 | 16 bits, because we have no way to load the upper 16 bits | |
4486 | (actually, we could handle them for the subset of cases | |
4487 | in which we are not using $at). */ | |
4488 | assert (offset_expr.X_op == O_symbol); | |
4489 | expr1.X_add_number = offset_expr.X_add_number; | |
4490 | offset_expr.X_add_number = 0; | |
4491 | if (expr1.X_add_number < -0x8000 | |
4492 | || expr1.X_add_number >= 0x8000) | |
4493 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4494 | frag_grow (20); |
0dd2d296 ILT |
4495 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4496 | mips_isa < 3 ? "lw" : "ld", | |
4497 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4498 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4499 | p = frag_var (rs_machine_dependent, 4, 0, | |
4500 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4501 | offset_expr.X_add_symbol, (long) 0, | |
4502 | (char *) NULL); | |
4503 | macro_build (p, &icnt, &offset_expr, | |
4504 | mips_isa < 3 ? "addiu" : "daddiu", | |
4505 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4506 | if (breg != 0) |
0dd2d296 | 4507 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4508 | mips_isa < 3 ? "addu" : "daddu", |
4509 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4510 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4511 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4512 | } |
fb251650 ILT |
4513 | else if (mips_pic == SVR4_PIC) |
4514 | { | |
4515 | int gpdel; | |
4516 | ||
4517 | /* If this is a reference to an external symbol, we want | |
4518 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4519 | addu $tempreg,$tempreg,$gp | |
4520 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4521 | <op> $treg,0($tempreg) | |
4522 | Otherwise we want | |
4523 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4524 | nop | |
4525 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4526 | <op> $treg,0($tempreg) | |
4527 | If there is a base register, we add it to $tempreg before | |
4528 | the <op>. If there is a constant, we stick it in the | |
4529 | <op> instruction. We don't handle constants larger than | |
4530 | 16 bits, because we have no way to load the upper 16 bits | |
4531 | (actually, we could handle them for the subset of cases | |
4532 | in which we are not using $at). */ | |
4533 | assert (offset_expr.X_op == O_symbol); | |
4534 | expr1.X_add_number = offset_expr.X_add_number; | |
4535 | offset_expr.X_add_number = 0; | |
4536 | if (expr1.X_add_number < -0x8000 | |
4537 | || expr1.X_add_number >= 0x8000) | |
4538 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4539 | if (reg_needs_delay (GP)) | |
4540 | gpdel = 4; | |
4541 | else | |
4542 | gpdel = 0; | |
4543 | frag_grow (36); | |
4544 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4545 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4546 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4547 | mips_isa < 3 ? "addu" : "daddu", | |
4548 | "d,v,t", tempreg, tempreg, GP); | |
4549 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4550 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4551 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4552 | tempreg); | |
fb251650 ILT |
4553 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4554 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4555 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4556 | if (gpdel > 0) | |
4557 | { | |
4558 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4559 | p += 4; | |
4560 | } | |
4561 | macro_build (p, &icnt, &offset_expr, | |
4562 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4563 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4564 | p += 4; |
4565 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4566 | p += 4; | |
4567 | macro_build (p, &icnt, &offset_expr, | |
4568 | mips_isa < 3 ? "addiu" : "daddiu", | |
4569 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4570 | if (breg != 0) | |
4571 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4572 | mips_isa < 3 ? "addu" : "daddu", | |
4573 | "d,v,t", tempreg, tempreg, breg); | |
4574 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4575 | (int) BFD_RELOC_LO16, tempreg); | |
4576 | } | |
d9aba805 ILT |
4577 | else if (mips_pic == EMBEDDED_PIC) |
4578 | { | |
4579 | /* If there is no base register, we want | |
4580 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4581 | If there is a base register, we want | |
4582 | addu $tempreg,$breg,$gp | |
4583 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4584 | */ | |
4585 | assert (offset_expr.X_op == O_symbol); | |
4586 | if (breg == 0) | |
4587 | { | |
4588 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4589 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4590 | used_at = 0; | |
4591 | } | |
4592 | else | |
4593 | { | |
4594 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4595 | mips_isa < 3 ? "addu" : "daddu", | |
4596 | "d,v,t", tempreg, breg, GP); | |
4597 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4598 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4599 | } | |
4600 | } | |
4601 | else | |
4602 | abort (); | |
0dd2d296 ILT |
4603 | |
4604 | if (! used_at) | |
4605 | return; | |
4606 | ||
4607 | break; | |
3d3c5039 ILT |
4608 | |
4609 | case M_LI: | |
19ed8960 | 4610 | case M_LI_S: |
d8a1c247 KR |
4611 | load_register (&icnt, treg, &imm_expr, 0); |
4612 | return; | |
4613 | ||
4614 | case M_DLI: | |
4615 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4616 | return; |
3d3c5039 | 4617 | |
0dd2d296 | 4618 | case M_LI_SS: |
55933a58 | 4619 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4620 | { |
d8a1c247 | 4621 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4622 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4623 | "mtc1", "t,G", AT, treg); | |
4624 | break; | |
0dd2d296 | 4625 | } |
d9aba805 | 4626 | else |
d2c71068 | 4627 | { |
55933a58 ILT |
4628 | assert (offset_expr.X_op == O_symbol |
4629 | && strcmp (segment_name (S_GET_SEGMENT | |
4630 | (offset_expr.X_add_symbol)), | |
4631 | ".lit4") == 0 | |
4632 | && offset_expr.X_add_number == 0); | |
4633 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4634 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4635 | return; |
4636 | } | |
0dd2d296 | 4637 | |
3d3c5039 | 4638 | case M_LI_D: |
d9aba805 ILT |
4639 | /* We know that sym is in the .rdata section. First we get the |
4640 | upper 16 bits of the address. */ | |
4641 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4642 | { |
4643 | /* FIXME: This won't work for a 64 bit address. */ | |
4644 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4645 | } | |
d9aba805 | 4646 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4647 | { |
4648 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4649 | mips_isa < 3 ? "lw" : "ld", | |
4650 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4651 | } | |
d9aba805 ILT |
4652 | else if (mips_pic == EMBEDDED_PIC) |
4653 | { | |
4654 | /* For embedded PIC we pick up the entire address off $gp in | |
4655 | a single instruction. */ | |
4656 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4657 | mips_isa < 3 ? "addiu" : "daddiu", | |
4658 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4659 | offset_expr.X_op = O_constant; | |
4660 | offset_expr.X_add_number = 0; | |
4661 | } | |
4662 | else | |
4663 | abort (); | |
4664 | ||
0dd2d296 | 4665 | /* Now we load the register(s). */ |
8358c818 | 4666 | if (mips_isa >= 3) |
0dd2d296 ILT |
4667 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4668 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4669 | else |
4670 | { | |
0dd2d296 ILT |
4671 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4672 | treg, (int) BFD_RELOC_LO16, AT); | |
4673 | if (treg != 31) | |
4674 | { | |
4675 | /* FIXME: How in the world do we deal with the possible | |
4676 | overflow here? */ | |
4677 | offset_expr.X_add_number += 4; | |
4678 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4679 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4680 | } | |
8358c818 | 4681 | } |
d2c71068 ILT |
4682 | |
4683 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4684 | does not become a variant frag. */ | |
4685 | frag_wane (frag_now); | |
4686 | frag_new (0); | |
4687 | ||
670a50eb | 4688 | break; |
3d3c5039 ILT |
4689 | |
4690 | case M_LI_DD: | |
55933a58 ILT |
4691 | assert (offset_expr.X_op == O_symbol |
4692 | && offset_expr.X_add_number == 0); | |
4693 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4694 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4695 | { |
0dd2d296 ILT |
4696 | if (mips_isa >= 2) |
4697 | { | |
4698 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4699 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4700 | return; | |
4701 | } | |
4702 | breg = GP; | |
4703 | r = BFD_RELOC_MIPS_LITERAL; | |
4704 | goto dob; | |
4705 | } | |
55933a58 | 4706 | else |
0dd2d296 | 4707 | { |
55933a58 ILT |
4708 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4709 | if (mips_pic == SVR4_PIC) | |
4710 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4711 | mips_isa < 3 ? "lw" : "ld", | |
4712 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4713 | else | |
4714 | { | |
4715 | /* FIXME: This won't work for a 64 bit address. */ | |
4716 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4717 | } | |
4718 | ||
0dd2d296 ILT |
4719 | if (mips_isa >= 2) |
4720 | { | |
4721 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4722 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4723 | |
4724 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4725 | that this does not become a variant frag. */ | |
4726 | frag_wane (frag_now); | |
4727 | frag_new (0); | |
4728 | ||
0dd2d296 ILT |
4729 | break; |
4730 | } | |
4731 | breg = AT; | |
4732 | r = BFD_RELOC_LO16; | |
4733 | goto dob; | |
8358c818 | 4734 | } |
9226253a | 4735 | |
3d3c5039 | 4736 | case M_L_DOB: |
9a7d824a ILT |
4737 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4738 | to adjust when loading from memory. */ | |
9226253a ILT |
4739 | r = BFD_RELOC_LO16; |
4740 | dob: | |
8358c818 | 4741 | assert (mips_isa < 2); |
0dd2d296 | 4742 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4743 | target_big_endian ? treg + 1 : treg, |
9226253a | 4744 | (int) r, breg); |
0dd2d296 ILT |
4745 | /* FIXME: A possible overflow which I don't know how to deal |
4746 | with. */ | |
670a50eb | 4747 | offset_expr.X_add_number += 4; |
0dd2d296 | 4748 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4749 | target_big_endian ? treg : treg + 1, |
9226253a | 4750 | (int) r, breg); |
d2c71068 ILT |
4751 | |
4752 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4753 | does not become a variant frag. */ | |
4754 | frag_wane (frag_now); | |
4755 | frag_new (0); | |
4756 | ||
0dd2d296 ILT |
4757 | if (breg != AT) |
4758 | return; | |
4759 | break; | |
3d3c5039 ILT |
4760 | |
4761 | case M_L_DAB: | |
670a50eb ILT |
4762 | /* |
4763 | * The MIPS assembler seems to check for X_add_number not | |
4764 | * being double aligned and generating: | |
4765 | * lui at,%hi(foo+1) | |
4766 | * addu at,at,v1 | |
4767 | * addiu at,at,%lo(foo+1) | |
4768 | * lwc1 f2,0(at) | |
4769 | * lwc1 f3,4(at) | |
4770 | * But, the resulting address is the same after relocation so why | |
4771 | * generate the extra instruction? | |
4772 | */ | |
4032d3f0 | 4773 | coproc = 1; |
0dd2d296 | 4774 | if (mips_isa >= 2) |
670a50eb | 4775 | { |
0dd2d296 ILT |
4776 | s = "ldc1"; |
4777 | goto ld; | |
670a50eb | 4778 | } |
0dd2d296 ILT |
4779 | |
4780 | s = "lwc1"; | |
4781 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4782 | goto ldd_std; |
4783 | ||
4784 | case M_S_DAB: | |
8358c818 | 4785 | if (mips_isa >= 2) |
8358c818 | 4786 | { |
0dd2d296 ILT |
4787 | s = "sdc1"; |
4788 | goto st; | |
8358c818 | 4789 | } |
3d3c5039 | 4790 | |
0dd2d296 ILT |
4791 | s = "swc1"; |
4792 | fmt = "T,o(b)"; | |
4793 | coproc = 1; | |
4794 | goto ldd_std; | |
3d3c5039 ILT |
4795 | |
4796 | case M_LD_AB: | |
0dd2d296 | 4797 | if (mips_isa >= 3) |
670a50eb | 4798 | { |
0dd2d296 ILT |
4799 | s = "ld"; |
4800 | goto ld; | |
670a50eb | 4801 | } |
0dd2d296 ILT |
4802 | |
4803 | s = "lw"; | |
4804 | fmt = "t,o(b)"; | |
4805 | goto ldd_std; | |
4806 | ||
4807 | case M_SD_AB: | |
4808 | if (mips_isa >= 3) | |
670a50eb | 4809 | { |
0dd2d296 ILT |
4810 | s = "sd"; |
4811 | goto st; | |
670a50eb | 4812 | } |
0dd2d296 | 4813 | |
670a50eb | 4814 | s = "sw"; |
0dd2d296 ILT |
4815 | fmt = "t,o(b)"; |
4816 | ||
4817 | ldd_std: | |
4818 | if (offset_expr.X_op != O_symbol | |
4819 | && offset_expr.X_op != O_constant) | |
670a50eb | 4820 | { |
0dd2d296 ILT |
4821 | as_bad ("expression too complex"); |
4822 | offset_expr.X_op = O_constant; | |
4823 | } | |
4824 | ||
4825 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4826 | to adjust when loading from memory. We set coproc if we must | |
4827 | load $fn+1 first. */ | |
b9129c6f | 4828 | if (! target_big_endian) |
0dd2d296 ILT |
4829 | coproc = 0; |
4830 | ||
d9aba805 | 4831 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4832 | || offset_expr.X_op == O_constant) |
4833 | { | |
4834 | /* If this is a reference to a GP relative symbol, we want | |
4835 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4836 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4837 | If we have a base register, we use this | |
4838 | addu $at,$breg,$gp | |
4839 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4840 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4841 | If this is not a GP relative symbol, we want | |
4842 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4843 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4844 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4845 | If there is a base register, we add it to $at after the | |
4846 | lui instruction. If there is a constant, we always use | |
4847 | the last case. */ | |
7a15a226 | 4848 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4849 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4850 | { |
0dd2d296 ILT |
4851 | p = NULL; |
4852 | used_at = 1; | |
670a50eb ILT |
4853 | } |
4854 | else | |
0dd2d296 ILT |
4855 | { |
4856 | int off; | |
4857 | ||
4858 | if (breg == 0) | |
4859 | { | |
8ea7f4e8 | 4860 | frag_grow (28); |
0dd2d296 ILT |
4861 | tempreg = GP; |
4862 | off = 0; | |
4863 | used_at = 0; | |
4864 | } | |
4865 | else | |
4866 | { | |
8ea7f4e8 | 4867 | frag_grow (36); |
0dd2d296 ILT |
4868 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4869 | mips_isa < 3 ? "addu" : "daddu", | |
4870 | "d,v,t", AT, breg, GP); | |
4871 | tempreg = AT; | |
4872 | off = 4; | |
4873 | used_at = 1; | |
4874 | } | |
4875 | ||
4876 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4877 | coproc ? treg + 1 : treg, | |
4878 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4879 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4880 | |
4881 | /* Set mips_optimize to 2 to avoid inserting an | |
4882 | undesired nop. */ | |
4883 | hold_mips_optimize = mips_optimize; | |
4884 | mips_optimize = 2; | |
0dd2d296 ILT |
4885 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4886 | coproc ? treg : treg + 1, | |
4887 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4888 | mips_optimize = hold_mips_optimize; |
4889 | ||
0dd2d296 ILT |
4890 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4891 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4892 | used_at && mips_noat), |
0dd2d296 ILT |
4893 | offset_expr.X_add_symbol, (long) 0, |
4894 | (char *) NULL); | |
777ad64d ILT |
4895 | |
4896 | /* We just generated two relocs. When tc_gen_reloc | |
4897 | handles this case, it will skip the first reloc and | |
4898 | handle the second. The second reloc already has an | |
4899 | extra addend of 4, which we added above. We must | |
4900 | subtract it out, and then subtract another 4 to make | |
4901 | the first reloc come out right. The second reloc | |
4902 | will come out right because we are going to add 4 to | |
4903 | offset_expr when we build its instruction below. */ | |
4904 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4905 | offset_expr.X_op = O_constant; |
4906 | } | |
4907 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4908 | if (p != NULL) | |
4909 | p += 4; | |
4910 | if (breg != 0) | |
4911 | { | |
4912 | macro_build (p, &icnt, (expressionS *) NULL, | |
4913 | mips_isa < 3 ? "addu" : "daddu", | |
4914 | "d,v,t", AT, breg, AT); | |
4915 | if (p != NULL) | |
4916 | p += 4; | |
4917 | } | |
4918 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4919 | coproc ? treg + 1 : treg, | |
4920 | (int) BFD_RELOC_LO16, AT); | |
4921 | if (p != NULL) | |
4922 | p += 4; | |
4923 | /* FIXME: How do we handle overflow here? */ | |
4924 | offset_expr.X_add_number += 4; | |
4925 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4926 | coproc ? treg : treg + 1, | |
4927 | (int) BFD_RELOC_LO16, AT); | |
4928 | } | |
fb251650 | 4929 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4930 | { |
0dd2d296 ILT |
4931 | int off; |
4932 | ||
4933 | /* If this is a reference to an external symbol, we want | |
4934 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4935 | nop | |
4936 | <op> $treg,0($at) | |
4937 | <op> $treg+1,4($at) | |
4938 | Otherwise we want | |
4939 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4940 | nop | |
4941 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4942 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4943 | If there is a base register we add it to $at before the | |
4944 | lwc1 instructions. If there is a constant we include it | |
4945 | in the lwc1 instructions. */ | |
4946 | used_at = 1; | |
4947 | expr1.X_add_number = offset_expr.X_add_number; | |
4948 | offset_expr.X_add_number = 0; | |
4949 | if (expr1.X_add_number < -0x8000 | |
4950 | || expr1.X_add_number >= 0x8000 - 4) | |
4951 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4952 | if (breg == 0) | |
4953 | off = 0; | |
4954 | else | |
4955 | off = 4; | |
8ea7f4e8 | 4956 | frag_grow (24 + off); |
0dd2d296 ILT |
4957 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4958 | mips_isa < 3 ? "lw" : "ld", | |
4959 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4960 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4961 | if (breg != 0) |
0dd2d296 | 4962 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4963 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4964 | "d,v,t", AT, breg, AT); |
4965 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4966 | coproc ? treg + 1 : treg, | |
4967 | (int) BFD_RELOC_LO16, AT); | |
4968 | expr1.X_add_number += 4; | |
55933a58 ILT |
4969 | |
4970 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4971 | nop. */ | |
4972 | hold_mips_optimize = mips_optimize; | |
4973 | mips_optimize = 2; | |
0dd2d296 ILT |
4974 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4975 | coproc ? treg : treg + 1, | |
4976 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4977 | mips_optimize = hold_mips_optimize; |
4978 | ||
0dd2d296 ILT |
4979 | (void) frag_var (rs_machine_dependent, 0, 0, |
4980 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4981 | offset_expr.X_add_symbol, (long) 0, | |
4982 | (char *) NULL); | |
8358c818 | 4983 | } |
fb251650 ILT |
4984 | else if (mips_pic == SVR4_PIC) |
4985 | { | |
4986 | int gpdel, off; | |
4987 | ||
4988 | /* If this is a reference to an external symbol, we want | |
4989 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4990 | addu $at,$at,$gp | |
4991 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4992 | nop | |
4993 | <op> $treg,0($at) | |
4994 | <op> $treg+1,4($at) | |
4995 | Otherwise we want | |
4996 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4997 | nop | |
4998 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4999 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5000 | If there is a base register we add it to $at before the | |
5001 | lwc1 instructions. If there is a constant we include it | |
5002 | in the lwc1 instructions. */ | |
5003 | used_at = 1; | |
5004 | expr1.X_add_number = offset_expr.X_add_number; | |
5005 | offset_expr.X_add_number = 0; | |
5006 | if (expr1.X_add_number < -0x8000 | |
5007 | || expr1.X_add_number >= 0x8000 - 4) | |
5008 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5009 | if (reg_needs_delay (GP)) | |
5010 | gpdel = 4; | |
5011 | else | |
5012 | gpdel = 0; | |
5013 | if (breg == 0) | |
5014 | off = 0; | |
5015 | else | |
5016 | off = 4; | |
5017 | frag_grow (56); | |
5018 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5019 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5020 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5021 | mips_isa < 3 ? "addu" : "daddu", | |
5022 | "d,v,t", AT, AT, GP); | |
5023 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5024 | mips_isa < 3 ? "lw" : "ld", | |
5025 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5027 | if (breg != 0) | |
5028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5029 | mips_isa < 3 ? "addu" : "daddu", | |
5030 | "d,v,t", AT, breg, AT); | |
5031 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5032 | coproc ? treg + 1 : treg, | |
5033 | (int) BFD_RELOC_LO16, AT); | |
5034 | expr1.X_add_number += 4; | |
5035 | ||
5036 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5037 | nop. */ | |
5038 | hold_mips_optimize = mips_optimize; | |
5039 | mips_optimize = 2; | |
5040 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5041 | coproc ? treg : treg + 1, | |
5042 | (int) BFD_RELOC_LO16, AT); | |
5043 | mips_optimize = hold_mips_optimize; | |
5044 | expr1.X_add_number -= 4; | |
5045 | ||
5046 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5047 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5048 | 8 + gpdel + off, 1, 0), | |
5049 | offset_expr.X_add_symbol, (long) 0, | |
5050 | (char *) NULL); | |
5051 | if (gpdel > 0) | |
5052 | { | |
5053 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5054 | p += 4; | |
5055 | } | |
5056 | macro_build (p, &icnt, &offset_expr, | |
5057 | mips_isa < 3 ? "lw" : "ld", | |
5058 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5059 | p += 4; | |
5060 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5061 | p += 4; | |
5062 | if (breg != 0) | |
5063 | { | |
5064 | macro_build (p, &icnt, (expressionS *) NULL, | |
5065 | mips_isa < 3 ? "addu" : "daddu", | |
5066 | "d,v,t", AT, breg, AT); | |
5067 | p += 4; | |
5068 | } | |
5069 | macro_build (p, &icnt, &expr1, s, fmt, | |
5070 | coproc ? treg + 1 : treg, | |
5071 | (int) BFD_RELOC_LO16, AT); | |
5072 | p += 4; | |
5073 | expr1.X_add_number += 4; | |
5074 | ||
5075 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5076 | nop. */ | |
5077 | hold_mips_optimize = mips_optimize; | |
5078 | mips_optimize = 2; | |
5079 | macro_build (p, &icnt, &expr1, s, fmt, | |
5080 | coproc ? treg : treg + 1, | |
5081 | (int) BFD_RELOC_LO16, AT); | |
5082 | mips_optimize = hold_mips_optimize; | |
5083 | } | |
d9aba805 ILT |
5084 | else if (mips_pic == EMBEDDED_PIC) |
5085 | { | |
5086 | /* If there is no base register, we use | |
5087 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5088 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5089 | If we have a base register, we use | |
5090 | addu $at,$breg,$gp | |
5091 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5092 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5093 | */ | |
5094 | if (breg == 0) | |
5095 | { | |
5096 | tempreg = GP; | |
5097 | used_at = 0; | |
5098 | } | |
5099 | else | |
5100 | { | |
5101 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5102 | mips_isa < 3 ? "addu" : "daddu", | |
5103 | "d,v,t", AT, breg, GP); | |
5104 | tempreg = AT; | |
5105 | used_at = 1; | |
5106 | } | |
5107 | ||
5108 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5109 | coproc ? treg + 1 : treg, | |
5110 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5111 | offset_expr.X_add_number += 4; | |
5112 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5113 | coproc ? treg : treg + 1, | |
5114 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5115 | } | |
5116 | else | |
5117 | abort (); | |
0dd2d296 ILT |
5118 | |
5119 | if (! used_at) | |
5120 | return; | |
5121 | ||
5122 | break; | |
5123 | ||
5124 | case M_LD_OB: | |
5125 | s = "lw"; | |
5126 | goto sd_ob; | |
5127 | case M_SD_OB: | |
5128 | s = "sw"; | |
5129 | sd_ob: | |
5130 | assert (mips_isa < 3); | |
5131 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5132 | (int) BFD_RELOC_LO16, breg); | |
5133 | offset_expr.X_add_number += 4; | |
5134 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5135 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5136 | return; |
917fae09 SS |
5137 | #ifdef LOSING_COMPILER |
5138 | default: | |
5139 | macro2 (ip); | |
5140 | return; | |
5141 | } | |
5142 | if (mips_noat) | |
5143 | as_warn ("Macro used $at after \".set noat\""); | |
5144 | } | |
5145 | ||
5146 | static void | |
5147 | macro2 (ip) | |
5148 | struct mips_cl_insn *ip; | |
5149 | { | |
5150 | register int treg, sreg, dreg, breg; | |
5151 | int tempreg; | |
5152 | int mask; | |
5153 | int icnt = 0; | |
5154 | int used_at; | |
5155 | expressionS expr1; | |
5156 | const char *s; | |
5157 | const char *s2; | |
5158 | const char *fmt; | |
5159 | int likely = 0; | |
5160 | int dbl = 0; | |
5161 | int coproc = 0; | |
adcf2b9d ILT |
5162 | int lr = 0; |
5163 | int off; | |
917fae09 SS |
5164 | offsetT maxnum; |
5165 | bfd_reloc_code_real_type r; | |
5166 | char *p; | |
5167 | ||
5168 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5169 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5170 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5171 | mask = ip->insn_mo->mask; | |
5172 | ||
5173 | expr1.X_op = O_constant; | |
5174 | expr1.X_op_symbol = NULL; | |
5175 | expr1.X_add_symbol = NULL; | |
5176 | expr1.X_add_number = 1; | |
5177 | ||
5178 | switch (mask) | |
5179 | { | |
5180 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5181 | |
8358c818 ILT |
5182 | case M_DMUL: |
5183 | dbl = 1; | |
3d3c5039 | 5184 | case M_MUL: |
0dd2d296 | 5185 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5186 | dbl ? "dmultu" : "multu", |
5187 | "s,t", sreg, treg); | |
0dd2d296 | 5188 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5189 | return; |
3d3c5039 | 5190 | |
8358c818 ILT |
5191 | case M_DMUL_I: |
5192 | dbl = 1; | |
3d3c5039 | 5193 | case M_MUL_I: |
8358c818 ILT |
5194 | /* The MIPS assembler some times generates shifts and adds. I'm |
5195 | not trying to be that fancy. GCC should do this for us | |
5196 | anyway. */ | |
d8a1c247 | 5197 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5198 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5199 | dbl ? "dmult" : "mult", |
5200 | "s,t", sreg, AT); | |
0dd2d296 | 5201 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5202 | break; |
3d3c5039 | 5203 | |
8358c818 ILT |
5204 | case M_DMULO: |
5205 | dbl = 1; | |
5206 | case M_MULO: | |
fbcfacb7 | 5207 | mips_emit_delays (true); |
8358c818 | 5208 | ++mips_noreorder; |
0dd2d296 ILT |
5209 | mips_any_noreorder = 1; |
5210 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5211 | dbl ? "dmult" : "mult", |
5212 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5213 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5214 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5215 | dbl ? "dsra32" : "sra", |
5216 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5217 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5218 | if (mips_trap) |
5219 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5220 | else | |
5221 | { | |
5222 | expr1.X_add_number = 8; | |
5223 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5224 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5225 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5226 | } | |
8358c818 | 5227 | --mips_noreorder; |
0dd2d296 | 5228 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5229 | break; |
5230 | ||
5231 | case M_DMULOU: | |
5232 | dbl = 1; | |
5233 | case M_MULOU: | |
fbcfacb7 | 5234 | mips_emit_delays (true); |
8358c818 | 5235 | ++mips_noreorder; |
0dd2d296 ILT |
5236 | mips_any_noreorder = 1; |
5237 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5238 | dbl ? "dmultu" : "multu", |
5239 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5240 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5241 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5242 | if (mips_trap) |
5243 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5244 | else | |
5245 | { | |
5246 | expr1.X_add_number = 8; | |
5247 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5248 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5249 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5250 | } | |
8358c818 ILT |
5251 | --mips_noreorder; |
5252 | break; | |
5253 | ||
3d3c5039 | 5254 | case M_ROL: |
0dd2d296 ILT |
5255 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5256 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5257 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5258 | treg); | |
5259 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5260 | break; |
3d3c5039 ILT |
5261 | |
5262 | case M_ROL_I: | |
0dd2d296 | 5263 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5264 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5265 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5266 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5267 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5268 | break; |
3d3c5039 ILT |
5269 | |
5270 | case M_ROR: | |
0dd2d296 ILT |
5271 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5272 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5273 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5274 | treg); | |
5275 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5276 | break; |
3d3c5039 ILT |
5277 | |
5278 | case M_ROR_I: | |
0dd2d296 | 5279 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5280 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5281 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5282 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5283 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5284 | break; |
3d3c5039 ILT |
5285 | |
5286 | case M_S_DOB: | |
8358c818 | 5287 | assert (mips_isa < 2); |
9a7d824a ILT |
5288 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5289 | to adjust when storing to memory. */ | |
0dd2d296 | 5290 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5291 | target_big_endian ? treg + 1 : treg, |
9226253a | 5292 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5293 | offset_expr.X_add_number += 4; |
0dd2d296 | 5294 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5295 | target_big_endian ? treg : treg + 1, |
9226253a | 5296 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5297 | return; |
3d3c5039 | 5298 | |
3d3c5039 | 5299 | case M_SEQ: |
670a50eb | 5300 | if (sreg == 0) |
0dd2d296 ILT |
5301 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5302 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5303 | else if (treg == 0) |
0dd2d296 ILT |
5304 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5305 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5306 | else |
5307 | { | |
0dd2d296 ILT |
5308 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5309 | sreg, treg); | |
5310 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5311 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5312 | } |
670a50eb | 5313 | return; |
3d3c5039 ILT |
5314 | |
5315 | case M_SEQ_I: | |
670a50eb ILT |
5316 | if (imm_expr.X_add_number == 0) |
5317 | { | |
0dd2d296 ILT |
5318 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5319 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5320 | return; |
3d3c5039 | 5321 | } |
670a50eb ILT |
5322 | if (sreg == 0) |
5323 | { | |
9a7d824a | 5324 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5325 | ip->insn_mo->name); |
0dd2d296 | 5326 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5327 | return; |
3d3c5039 | 5328 | } |
6e8dda9c | 5329 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5330 | { |
0dd2d296 ILT |
5331 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5332 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5333 | used_at = 0; |
6e8dda9c ILT |
5334 | } |
5335 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5336 | { | |
5337 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5338 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5339 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5340 | "t,r,j", dreg, sreg, |
5341 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5342 | used_at = 0; |
5343 | } | |
5344 | else | |
5345 | { | |
d8a1c247 | 5346 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5347 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5348 | sreg, AT); | |
670a50eb ILT |
5349 | used_at = 1; |
5350 | } | |
0dd2d296 | 5351 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5352 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5353 | if (used_at) |
5354 | break; | |
5355 | return; | |
3d3c5039 ILT |
5356 | |
5357 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5358 | s = "slt"; |
5359 | goto sge; | |
3d3c5039 | 5360 | case M_SGEU: |
670a50eb | 5361 | s = "sltu"; |
3d3c5039 | 5362 | sge: |
0dd2d296 ILT |
5363 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5364 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5365 | (int) BFD_RELOC_LO16); |
670a50eb | 5366 | return; |
3d3c5039 | 5367 | |
670a50eb | 5368 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5369 | case M_SGEU_I: |
6e8dda9c | 5370 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5371 | { |
0dd2d296 | 5372 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5373 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5374 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5375 | used_at = 0; |
5376 | } | |
5377 | else | |
5378 | { | |
d8a1c247 | 5379 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5380 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5381 | mask == M_SGE_I ? "slt" : "sltu", |
5382 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5383 | used_at = 1; |
5384 | } | |
0dd2d296 | 5385 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5386 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5387 | if (used_at) |
5388 | break; | |
5389 | return; | |
3d3c5039 ILT |
5390 | |
5391 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5392 | s = "slt"; |
5393 | goto sgt; | |
3d3c5039 | 5394 | case M_SGTU: |
670a50eb | 5395 | s = "sltu"; |
3d3c5039 | 5396 | sgt: |
0dd2d296 | 5397 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5398 | return; |
3d3c5039 | 5399 | |
670a50eb ILT |
5400 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5401 | s = "slt"; | |
5402 | goto sgti; | |
3d3c5039 | 5403 | case M_SGTU_I: |
670a50eb | 5404 | s = "sltu"; |
3d3c5039 | 5405 | sgti: |
d8a1c247 | 5406 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5407 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5408 | break; |
3d3c5039 | 5409 | |
670a50eb ILT |
5410 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5411 | s = "slt"; | |
5412 | goto sle; | |
3d3c5039 | 5413 | case M_SLEU: |
670a50eb | 5414 | s = "sltu"; |
3d3c5039 | 5415 | sle: |
0dd2d296 ILT |
5416 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5417 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5418 | (int) BFD_RELOC_LO16); |
670a50eb | 5419 | return; |
3d3c5039 | 5420 | |
670a50eb ILT |
5421 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5422 | s = "slt"; | |
5423 | goto slei; | |
3d3c5039 | 5424 | case M_SLEU_I: |
670a50eb | 5425 | s = "sltu"; |
3d3c5039 | 5426 | slei: |
d8a1c247 | 5427 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5428 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5429 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5430 | (int) BFD_RELOC_LO16); |
670a50eb | 5431 | break; |
3d3c5039 ILT |
5432 | |
5433 | case M_SLT_I: | |
6e8dda9c | 5434 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5435 | { |
0dd2d296 ILT |
5436 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5437 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5438 | return; |
3d3c5039 | 5439 | } |
d8a1c247 | 5440 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5441 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5442 | break; |
3d3c5039 ILT |
5443 | |
5444 | case M_SLTU_I: | |
6e8dda9c | 5445 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5446 | { |
0dd2d296 ILT |
5447 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5448 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5449 | return; |
3d3c5039 | 5450 | } |
d8a1c247 | 5451 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5452 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5453 | AT); | |
670a50eb | 5454 | break; |
3d3c5039 ILT |
5455 | |
5456 | case M_SNE: | |
670a50eb | 5457 | if (sreg == 0) |
0dd2d296 ILT |
5458 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5459 | treg); | |
670a50eb | 5460 | else if (treg == 0) |
0dd2d296 ILT |
5461 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5462 | sreg); | |
670a50eb ILT |
5463 | else |
5464 | { | |
0dd2d296 ILT |
5465 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5466 | sreg, treg); | |
5467 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5468 | dreg); | |
3d3c5039 | 5469 | } |
670a50eb | 5470 | return; |
3d3c5039 ILT |
5471 | |
5472 | case M_SNE_I: | |
670a50eb ILT |
5473 | if (imm_expr.X_add_number == 0) |
5474 | { | |
0dd2d296 ILT |
5475 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5476 | sreg); | |
670a50eb | 5477 | return; |
3d3c5039 | 5478 | } |
670a50eb ILT |
5479 | if (sreg == 0) |
5480 | { | |
9a7d824a | 5481 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5482 | ip->insn_mo->name); |
0dd2d296 | 5483 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5484 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5485 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5486 | return; |
3d3c5039 | 5487 | } |
6e8dda9c | 5488 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5489 | { |
0dd2d296 ILT |
5490 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5491 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5492 | used_at = 0; |
6e8dda9c ILT |
5493 | } |
5494 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5495 | { | |
5496 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5497 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5498 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5499 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5500 | used_at = 0; |
5501 | } | |
5502 | else | |
5503 | { | |
d8a1c247 | 5504 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5505 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5506 | sreg, AT); | |
670a50eb ILT |
5507 | used_at = 1; |
5508 | } | |
0dd2d296 | 5509 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5510 | if (used_at) |
5511 | break; | |
5512 | return; | |
3d3c5039 | 5513 | |
8358c818 ILT |
5514 | case M_DSUB_I: |
5515 | dbl = 1; | |
3d3c5039 | 5516 | case M_SUB_I: |
6e8dda9c | 5517 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5518 | { |
5519 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5520 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5521 | dbl ? "daddi" : "addi", |
9226253a | 5522 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5523 | return; |
3d3c5039 | 5524 | } |
d8a1c247 | 5525 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5526 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5527 | dbl ? "dsub" : "sub", |
5528 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5529 | break; |
3d3c5039 | 5530 | |
8358c818 ILT |
5531 | case M_DSUBU_I: |
5532 | dbl = 1; | |
3d3c5039 | 5533 | case M_SUBU_I: |
6e8dda9c | 5534 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5535 | { |
5536 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5537 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5538 | dbl ? "daddiu" : "addiu", |
9226253a | 5539 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5540 | return; |
3d3c5039 | 5541 | } |
d8a1c247 | 5542 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5543 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5544 | dbl ? "dsubu" : "subu", |
5545 | "d,v,t", dreg, sreg, AT); | |
5546 | break; | |
5547 | ||
5548 | case M_TEQ_I: | |
5549 | s = "teq"; | |
5550 | goto trap; | |
5551 | case M_TGE_I: | |
5552 | s = "tge"; | |
5553 | goto trap; | |
5554 | case M_TGEU_I: | |
5555 | s = "tgeu"; | |
5556 | goto trap; | |
5557 | case M_TLT_I: | |
5558 | s = "tlt"; | |
5559 | goto trap; | |
5560 | case M_TLTU_I: | |
5561 | s = "tltu"; | |
5562 | goto trap; | |
5563 | case M_TNE_I: | |
5564 | s = "tne"; | |
5565 | trap: | |
d8a1c247 | 5566 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5567 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5568 | break; |
3d3c5039 ILT |
5569 | |
5570 | case M_TRUNCWD: | |
5571 | case M_TRUNCWS: | |
8358c818 | 5572 | assert (mips_isa < 2); |
670a50eb ILT |
5573 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5574 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5575 | ||
5576 | /* | |
5577 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5578 | * or is there a reason for it? | |
5579 | */ | |
fbcfacb7 | 5580 | mips_emit_delays (true); |
becfe05e | 5581 | ++mips_noreorder; |
0dd2d296 ILT |
5582 | mips_any_noreorder = 1; |
5583 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5584 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5585 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5586 | expr1.X_add_number = 3; |
0dd2d296 | 5587 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5588 | (int) BFD_RELOC_LO16); |
670a50eb | 5589 | expr1.X_add_number = 2; |
0dd2d296 | 5590 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5591 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5592 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5593 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5594 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5595 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5596 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5597 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5598 | --mips_noreorder; |
670a50eb | 5599 | break; |
3d3c5039 ILT |
5600 | |
5601 | case M_ULH: | |
670a50eb ILT |
5602 | s = "lb"; |
5603 | goto ulh; | |
3d3c5039 | 5604 | case M_ULHU: |
670a50eb | 5605 | s = "lbu"; |
3d3c5039 | 5606 | ulh: |
8ea7f4e8 ILT |
5607 | if (offset_expr.X_add_number >= 0x7fff) |
5608 | as_bad ("operand overflow"); | |
670a50eb | 5609 | /* avoid load delay */ |
b9129c6f | 5610 | if (! target_big_endian) |
8ea7f4e8 | 5611 | offset_expr.X_add_number += 1; |
0dd2d296 | 5612 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5613 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5614 | if (! target_big_endian) |
8ea7f4e8 ILT |
5615 | offset_expr.X_add_number -= 1; |
5616 | else | |
5617 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5618 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5619 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5620 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5621 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5622 | break; |
3d3c5039 | 5623 | |
adcf2b9d ILT |
5624 | case M_ULD: |
5625 | s = "ldl"; | |
5626 | s2 = "ldr"; | |
5627 | off = 7; | |
5628 | goto ulw; | |
3d3c5039 | 5629 | case M_ULW: |
adcf2b9d ILT |
5630 | s = "lwl"; |
5631 | s2 = "lwr"; | |
5632 | off = 3; | |
5633 | ulw: | |
5634 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5635 | as_bad ("operand overflow"); |
b9129c6f | 5636 | if (! target_big_endian) |
adcf2b9d ILT |
5637 | offset_expr.X_add_number += off; |
5638 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5639 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5640 | if (! target_big_endian) |
adcf2b9d | 5641 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5642 | else |
adcf2b9d ILT |
5643 | offset_expr.X_add_number += off; |
5644 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5645 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5646 | return; |
3d3c5039 | 5647 | |
adcf2b9d ILT |
5648 | case M_ULD_A: |
5649 | s = "ldl"; | |
5650 | s2 = "ldr"; | |
5651 | off = 7; | |
5652 | goto ulwa; | |
5653 | case M_ULW_A: | |
5654 | s = "lwl"; | |
5655 | s2 = "lwr"; | |
5656 | off = 3; | |
5657 | ulwa: | |
5658 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5659 | if (breg != 0) |
5660 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5661 | mips_isa < 3 ? "addu" : "daddu", | |
5662 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5663 | if (! target_big_endian) |
adcf2b9d ILT |
5664 | expr1.X_add_number = off; |
5665 | else | |
5666 | expr1.X_add_number = 0; | |
5667 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5668 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5669 | if (! target_big_endian) |
adcf2b9d ILT |
5670 | expr1.X_add_number = 0; |
5671 | else | |
5672 | expr1.X_add_number = off; | |
5673 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5674 | (int) BFD_RELOC_LO16, AT); | |
5675 | break; | |
5676 | ||
3d3c5039 ILT |
5677 | case M_ULH_A: |
5678 | case M_ULHU_A: | |
0dd2d296 | 5679 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5680 | if (breg != 0) |
5681 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5682 | mips_isa < 3 ? "addu" : "daddu", | |
5683 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5684 | if (target_big_endian) |
adcf2b9d ILT |
5685 | expr1.X_add_number = 0; |
5686 | macro_build ((char *) NULL, &icnt, &expr1, | |
5687 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5688 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5689 | if (target_big_endian) |
adcf2b9d | 5690 | expr1.X_add_number = 1; |
670a50eb | 5691 | else |
adcf2b9d ILT |
5692 | expr1.X_add_number = 0; |
5693 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5694 | (int) BFD_RELOC_LO16, AT); | |
5695 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5696 | treg, 8); | |
5697 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5698 | treg, AT); | |
670a50eb | 5699 | break; |
3d3c5039 ILT |
5700 | |
5701 | case M_USH: | |
8ea7f4e8 ILT |
5702 | if (offset_expr.X_add_number >= 0x7fff) |
5703 | as_bad ("operand overflow"); | |
b9129c6f | 5704 | if (target_big_endian) |
8ea7f4e8 | 5705 | offset_expr.X_add_number += 1; |
0dd2d296 | 5706 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5707 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5708 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5709 | if (target_big_endian) |
8ea7f4e8 ILT |
5710 | offset_expr.X_add_number -= 1; |
5711 | else | |
5712 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5713 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5714 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5715 | break; |
3d3c5039 | 5716 | |
adcf2b9d ILT |
5717 | case M_USD: |
5718 | s = "sdl"; | |
5719 | s2 = "sdr"; | |
5720 | off = 7; | |
5721 | goto usw; | |
3d3c5039 | 5722 | case M_USW: |
adcf2b9d ILT |
5723 | s = "swl"; |
5724 | s2 = "swr"; | |
5725 | off = 3; | |
5726 | usw: | |
5727 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5728 | as_bad ("operand overflow"); |
b9129c6f | 5729 | if (! target_big_endian) |
adcf2b9d ILT |
5730 | offset_expr.X_add_number += off; |
5731 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5732 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5733 | if (! target_big_endian) |
adcf2b9d | 5734 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5735 | else |
adcf2b9d ILT |
5736 | offset_expr.X_add_number += off; |
5737 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5738 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5739 | return; |
3d3c5039 | 5740 | |
adcf2b9d ILT |
5741 | case M_USD_A: |
5742 | s = "sdl"; | |
5743 | s2 = "sdr"; | |
5744 | off = 7; | |
5745 | goto uswa; | |
3d3c5039 | 5746 | case M_USW_A: |
adcf2b9d ILT |
5747 | s = "swl"; |
5748 | s2 = "swr"; | |
5749 | off = 3; | |
5750 | uswa: | |
0dd2d296 | 5751 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5752 | if (breg != 0) |
5753 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5754 | mips_isa < 3 ? "addu" : "daddu", | |
5755 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5756 | if (! target_big_endian) |
adcf2b9d | 5757 | expr1.X_add_number = off; |
670a50eb | 5758 | else |
adcf2b9d ILT |
5759 | expr1.X_add_number = 0; |
5760 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5761 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5762 | if (! target_big_endian) |
adcf2b9d ILT |
5763 | expr1.X_add_number = 0; |
5764 | else | |
5765 | expr1.X_add_number = off; | |
5766 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5767 | (int) BFD_RELOC_LO16, AT); | |
5768 | break; | |
5769 | ||
5770 | case M_USH_A: | |
5771 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5772 | if (breg != 0) |
5773 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5774 | mips_isa < 3 ? "addu" : "daddu", | |
5775 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5776 | if (! target_big_endian) |
adcf2b9d ILT |
5777 | expr1.X_add_number = 0; |
5778 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5779 | (int) BFD_RELOC_LO16, AT); | |
5780 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5781 | treg, 8); | |
b9129c6f | 5782 | if (! target_big_endian) |
adcf2b9d ILT |
5783 | expr1.X_add_number = 1; |
5784 | else | |
5785 | expr1.X_add_number = 0; | |
5786 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5787 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5788 | if (! target_big_endian) |
adcf2b9d ILT |
5789 | expr1.X_add_number = 0; |
5790 | else | |
5791 | expr1.X_add_number = 1; | |
5792 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5793 | (int) BFD_RELOC_LO16, AT); | |
5794 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5795 | treg, 8); | |
5796 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5797 | treg, AT); | |
670a50eb | 5798 | break; |
3d3c5039 ILT |
5799 | |
5800 | default: | |
670a50eb | 5801 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5802 | break; |
3d3c5039 | 5803 | } |
670a50eb ILT |
5804 | if (mips_noat) |
5805 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5806 | } |
5807 | ||
cc5703cd | 5808 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5809 | |
3d3c5039 | 5810 | static void |
cc5703cd | 5811 | mips16_macro (ip) |
3d3c5039 ILT |
5812 | struct mips_cl_insn *ip; |
5813 | { | |
cc5703cd ILT |
5814 | int mask; |
5815 | int xreg, yreg, zreg, tmp; | |
5816 | int icnt; | |
5817 | expressionS expr1; | |
5818 | int dbl; | |
5819 | const char *s, *s2, *s3; | |
3d3c5039 | 5820 | |
cc5703cd | 5821 | mask = ip->insn_mo->mask; |
3d3c5039 | 5822 | |
cc5703cd ILT |
5823 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5824 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5825 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5826 | |
cc5703cd | 5827 | icnt = 0; |
8358c818 | 5828 | |
cc5703cd ILT |
5829 | expr1.X_op = O_constant; |
5830 | expr1.X_op_symbol = NULL; | |
5831 | expr1.X_add_symbol = NULL; | |
5832 | expr1.X_add_number = 1; | |
8358c818 | 5833 | |
cc5703cd | 5834 | dbl = 0; |
517078c1 | 5835 | |
cc5703cd ILT |
5836 | switch (mask) |
5837 | { | |
5838 | default: | |
5839 | internalError (); | |
5840 | ||
5841 | case M_DDIV_3: | |
5842 | dbl = 1; | |
5843 | case M_DIV_3: | |
5844 | s = "mflo"; | |
5845 | goto do_div3; | |
5846 | case M_DREM_3: | |
5847 | dbl = 1; | |
5848 | case M_REM_3: | |
5849 | s = "mfhi"; | |
5850 | do_div3: | |
fbcfacb7 | 5851 | mips_emit_delays (true); |
cc5703cd ILT |
5852 | ++mips_noreorder; |
5853 | mips_any_noreorder = 1; | |
5854 | macro_build ((char *) NULL, &icnt, NULL, | |
5855 | dbl ? "ddiv" : "div", | |
5856 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5857 | expr1.X_add_number = 2; |
cc5703cd | 5858 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5859 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5860 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5861 | since that causes an overflow. We should do that as well, | |
5862 | but I don't see how to do the comparisons without a temporary | |
5863 | register. */ | |
5864 | --mips_noreorder; | |
5865 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5866 | break; | |
5867 | ||
5868 | case M_DIVU_3: | |
5869 | s = "divu"; | |
5870 | s2 = "mflo"; | |
5871 | goto do_divu3; | |
5872 | case M_REMU_3: | |
5873 | s = "divu"; | |
5874 | s2 = "mfhi"; | |
5875 | goto do_divu3; | |
5876 | case M_DDIVU_3: | |
5877 | s = "ddivu"; | |
5878 | s2 = "mflo"; | |
5879 | goto do_divu3; | |
5880 | case M_DREMU_3: | |
5881 | s = "ddivu"; | |
5882 | s2 = "mfhi"; | |
5883 | do_divu3: | |
fbcfacb7 | 5884 | mips_emit_delays (true); |
cc5703cd ILT |
5885 | ++mips_noreorder; |
5886 | mips_any_noreorder = 1; | |
5887 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5888 | expr1.X_add_number = 2; |
cc5703cd | 5889 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5890 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5891 | --mips_noreorder; | |
5892 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5893 | break; | |
5894 | ||
5895 | case M_DSUBU_I: | |
5896 | dbl = 1; | |
5897 | goto do_subu; | |
5898 | case M_SUBU_I: | |
5899 | do_subu: | |
5900 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5901 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5902 | dbl ? "daddiu" : "addiu", | |
5903 | "y,x,4", yreg, xreg); | |
5904 | break; | |
5905 | ||
5906 | case M_SUBU_I_2: | |
5907 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5908 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5909 | "x,k", xreg); | |
5910 | break; | |
5911 | ||
5912 | case M_DSUBU_I_2: | |
5913 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5914 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5915 | "y,j", yreg); | |
5916 | break; | |
5917 | ||
5918 | case M_BEQ: | |
5919 | s = "cmp"; | |
5920 | s2 = "bteqz"; | |
5921 | goto do_branch; | |
5922 | case M_BNE: | |
5923 | s = "cmp"; | |
5924 | s2 = "btnez"; | |
5925 | goto do_branch; | |
5926 | case M_BLT: | |
5927 | s = "slt"; | |
5928 | s2 = "btnez"; | |
5929 | goto do_branch; | |
5930 | case M_BLTU: | |
5931 | s = "sltu"; | |
5932 | s2 = "btnez"; | |
5933 | goto do_branch; | |
5934 | case M_BLE: | |
5935 | s = "slt"; | |
5936 | s2 = "bteqz"; | |
5937 | goto do_reverse_branch; | |
5938 | case M_BLEU: | |
5939 | s = "sltu"; | |
5940 | s2 = "bteqz"; | |
5941 | goto do_reverse_branch; | |
5942 | case M_BGE: | |
5943 | s = "slt"; | |
5944 | s2 = "bteqz"; | |
5945 | goto do_branch; | |
5946 | case M_BGEU: | |
5947 | s = "sltu"; | |
5948 | s2 = "bteqz"; | |
5949 | goto do_branch; | |
5950 | case M_BGT: | |
5951 | s = "slt"; | |
5952 | s2 = "btnez"; | |
5953 | goto do_reverse_branch; | |
5954 | case M_BGTU: | |
5955 | s = "sltu"; | |
5956 | s2 = "btnez"; | |
5957 | ||
5958 | do_reverse_branch: | |
5959 | tmp = xreg; | |
5960 | xreg = yreg; | |
5961 | yreg = tmp; | |
5962 | ||
5963 | do_branch: | |
5964 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
5965 | xreg, yreg); | |
5966 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5967 | break; | |
5968 | ||
5969 | case M_BEQ_I: | |
5970 | s = "cmpi"; | |
5971 | s2 = "bteqz"; | |
5972 | s3 = "x,U"; | |
5973 | goto do_branch_i; | |
5974 | case M_BNE_I: | |
5975 | s = "cmpi"; | |
5976 | s2 = "btnez"; | |
5977 | s3 = "x,U"; | |
5978 | goto do_branch_i; | |
5979 | case M_BLT_I: | |
5980 | s = "slti"; | |
5981 | s2 = "btnez"; | |
5982 | s3 = "x,8"; | |
5983 | goto do_branch_i; | |
5984 | case M_BLTU_I: | |
5985 | s = "sltiu"; | |
5986 | s2 = "btnez"; | |
5987 | s3 = "x,8"; | |
5988 | goto do_branch_i; | |
5989 | case M_BLE_I: | |
5990 | s = "slti"; | |
5991 | s2 = "btnez"; | |
5992 | s3 = "x,8"; | |
5993 | goto do_addone_branch_i; | |
5994 | case M_BLEU_I: | |
5995 | s = "sltiu"; | |
5996 | s2 = "btnez"; | |
5997 | s3 = "x,8"; | |
5998 | goto do_addone_branch_i; | |
5999 | case M_BGE_I: | |
6000 | s = "slti"; | |
6001 | s2 = "bteqz"; | |
6002 | s3 = "x,8"; | |
6003 | goto do_branch_i; | |
6004 | case M_BGEU_I: | |
6005 | s = "sltiu"; | |
6006 | s2 = "bteqz"; | |
6007 | s3 = "x,8"; | |
6008 | goto do_branch_i; | |
6009 | case M_BGT_I: | |
6010 | s = "slti"; | |
6011 | s2 = "bteqz"; | |
6012 | s3 = "x,8"; | |
6013 | goto do_addone_branch_i; | |
6014 | case M_BGTU_I: | |
6015 | s = "sltiu"; | |
6016 | s2 = "bteqz"; | |
6017 | s3 = "x,8"; | |
6018 | ||
6019 | do_addone_branch_i: | |
6020 | ++imm_expr.X_add_number; | |
6021 | ||
6022 | do_branch_i: | |
6023 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6024 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6025 | break; | |
18e0764d ILT |
6026 | |
6027 | case M_ABS: | |
6028 | expr1.X_add_number = 0; | |
6029 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6030 | if (xreg != yreg) | |
6031 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6032 | "move", "y,X", xreg, yreg); | |
6033 | expr1.X_add_number = 2; | |
6034 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6035 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6036 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6037 | } |
6038 | } | |
6039 | ||
6040 | /* This routine assembles an instruction into its binary format. As a | |
6041 | side effect, it sets one of the global variables imm_reloc or | |
6042 | offset_reloc to the type of relocation to do if one of the operands | |
6043 | is an address expression. */ | |
6044 | ||
6045 | static void | |
6046 | mips_ip (str, ip) | |
6047 | char *str; | |
6048 | struct mips_cl_insn *ip; | |
6049 | { | |
6050 | char *s; | |
6051 | const char *args; | |
6052 | char c; | |
6053 | struct mips_opcode *insn; | |
6054 | char *argsStart; | |
6055 | unsigned int regno; | |
6056 | unsigned int lastregno = 0; | |
6057 | char *s_reset; | |
6058 | ||
6059 | insn_error = NULL; | |
6060 | ||
6061 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6062 | continue; | |
6063 | switch (*s) | |
6064 | { | |
6065 | case '\0': | |
6066 | break; | |
6067 | ||
6068 | case ' ': | |
6069 | *s++ = '\0'; | |
6070 | break; | |
6071 | ||
6072 | default: | |
6073 | as_fatal ("Unknown opcode: `%s'", str); | |
6074 | } | |
6075 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6076 | { | |
6077 | insn_error = "unrecognized opcode"; | |
6078 | return; | |
6079 | } | |
6080 | argsStart = s; | |
6081 | for (;;) | |
6082 | { | |
6083 | int insn_isa; | |
6084 | ||
6085 | assert (strcmp (insn->name, str) == 0); | |
6086 | ||
6087 | if (insn->pinfo == INSN_MACRO) | |
6088 | insn_isa = insn->match; | |
6089 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6090 | insn_isa = 2; | |
6091 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6092 | insn_isa = 3; | |
6093 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6094 | insn_isa = 4; | |
6095 | else | |
6096 | insn_isa = 1; | |
6097 | ||
6098 | if (insn_isa > mips_isa | |
6099 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
6100 | && ! mips_4650) | |
6101 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6102 | && ! mips_4010) | |
6103 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6104 | && ! mips_4100)) | |
6105 | { | |
6106 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6107 | && strcmp (insn->name, insn[1].name) == 0) | |
6108 | { | |
6109 | ++insn; | |
6110 | continue; | |
6111 | } | |
6112 | if (insn_isa <= mips_isa) | |
6113 | insn_error = "opcode not supported on this processor"; | |
6114 | else | |
6115 | { | |
6116 | static char buf[100]; | |
6117 | ||
6118 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6119 | insn_error = buf; | |
6120 | } | |
6121 | return; | |
6122 | } | |
8358c818 | 6123 | |
670a50eb ILT |
6124 | ip->insn_mo = insn; |
6125 | ip->insn_opcode = insn->match; | |
6126 | for (args = insn->args;; ++args) | |
6127 | { | |
6128 | if (*s == ' ') | |
6129 | ++s; | |
6130 | switch (*args) | |
6131 | { | |
6132 | case '\0': /* end of args */ | |
6133 | if (*s == '\0') | |
6134 | return; | |
6135 | break; | |
3d3c5039 ILT |
6136 | |
6137 | case ',': | |
670a50eb ILT |
6138 | if (*s++ == *args) |
6139 | continue; | |
6140 | s--; | |
6141 | switch (*++args) | |
6142 | { | |
3d3c5039 ILT |
6143 | case 'r': |
6144 | case 'v': | |
670a50eb ILT |
6145 | ip->insn_opcode |= lastregno << 21; |
6146 | continue; | |
3d3c5039 ILT |
6147 | |
6148 | case 'w': | |
6149 | case 'W': | |
670a50eb ILT |
6150 | ip->insn_opcode |= lastregno << 16; |
6151 | continue; | |
3d3c5039 ILT |
6152 | |
6153 | case 'V': | |
670a50eb ILT |
6154 | ip->insn_opcode |= lastregno << 11; |
6155 | continue; | |
3d3c5039 | 6156 | } |
670a50eb | 6157 | break; |
3d3c5039 ILT |
6158 | |
6159 | case '(': | |
670a50eb ILT |
6160 | /* handle optional base register. |
6161 | Either the base register is omitted or | |
6162 | we must have a left paren. */ | |
6163 | /* this is dependent on the next operand specifier | |
6164 | is a 'b' for base register */ | |
6165 | assert (args[1] == 'b'); | |
6166 | if (*s == '\0') | |
6167 | return; | |
3d3c5039 | 6168 | |
670a50eb ILT |
6169 | case ')': /* these must match exactly */ |
6170 | if (*s++ == *args) | |
3d3c5039 | 6171 | continue; |
670a50eb ILT |
6172 | break; |
6173 | ||
6174 | case '<': /* must be at least one digit */ | |
6175 | /* | |
6176 | * According to the manual, if the shift amount is greater | |
6177 | * than 31 or less than 0 the the shift amount should be | |
6178 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6179 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6180 | */ |
6181 | my_getExpression (&imm_expr, s); | |
6182 | check_absolute_expr (ip, &imm_expr); | |
6183 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6184 | { | |
58d4951d ILT |
6185 | as_warn ("Improper shift amount (%ld)", |
6186 | (long) imm_expr.X_add_number); | |
9226253a | 6187 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6188 | } |
6189 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6190 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6191 | s = expr_end; |
6192 | continue; | |
6193 | ||
56c96faa ILT |
6194 | case '>': /* shift amount minus 32 */ |
6195 | my_getExpression (&imm_expr, s); | |
6196 | check_absolute_expr (ip, &imm_expr); | |
6197 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6198 | || (unsigned long) imm_expr.X_add_number > 63) | |
6199 | break; | |
6200 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6201 | imm_expr.X_op = O_absent; | |
6202 | s = expr_end; | |
6203 | continue; | |
6204 | ||
9226253a | 6205 | case 'k': /* cache code */ |
d8a1c247 | 6206 | case 'h': /* prefx code */ |
9226253a ILT |
6207 | my_getExpression (&imm_expr, s); |
6208 | check_absolute_expr (ip, &imm_expr); | |
6209 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6210 | { | |
d8a1c247 KR |
6211 | as_warn ("Invalid value for `%s' (%lu)", |
6212 | ip->insn_mo->name, | |
9226253a ILT |
6213 | (unsigned long) imm_expr.X_add_number); |
6214 | imm_expr.X_add_number &= 0x1f; | |
6215 | } | |
d8a1c247 KR |
6216 | if (*args == 'k') |
6217 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6218 | else | |
6219 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6220 | imm_expr.X_op = O_absent; |
6221 | s = expr_end; | |
6222 | continue; | |
6223 | ||
670a50eb ILT |
6224 | case 'c': /* break code */ |
6225 | my_getExpression (&imm_expr, s); | |
6226 | check_absolute_expr (ip, &imm_expr); | |
6227 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6228 | as_warn ("Illegal break code (%ld)", |
6229 | (long) imm_expr.X_add_number); | |
670a50eb | 6230 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6231 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6232 | s = expr_end; |
6233 | continue; | |
6234 | ||
918692a5 ILT |
6235 | case 'B': /* syscall code */ |
6236 | my_getExpression (&imm_expr, s); | |
6237 | check_absolute_expr (ip, &imm_expr); | |
6238 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6239 | as_warn ("Illegal syscall code (%ld)", |
6240 | (long) imm_expr.X_add_number); | |
918692a5 | 6241 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6242 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6243 | s = expr_end; |
6244 | continue; | |
6245 | ||
0aa07269 ILT |
6246 | case 'C': /* Coprocessor code */ |
6247 | my_getExpression (&imm_expr, s); | |
6248 | check_absolute_expr (ip, &imm_expr); | |
6249 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6250 | { | |
58d4951d ILT |
6251 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6252 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6253 | imm_expr.X_add_number &= ((1<<25) - 1); |
6254 | } | |
6255 | ip->insn_opcode |= imm_expr.X_add_number; | |
6256 | imm_expr.X_op = O_absent; | |
6257 | s = expr_end; | |
6258 | continue; | |
6259 | ||
670a50eb ILT |
6260 | case 'b': /* base register */ |
6261 | case 'd': /* destination register */ | |
6262 | case 's': /* source register */ | |
6263 | case 't': /* target register */ | |
6264 | case 'r': /* both target and source */ | |
6265 | case 'v': /* both dest and source */ | |
6266 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6267 | case 'E': /* coprocessor target register */ |
6268 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6269 | case 'x': /* ignore register name */ |
ff3a5c18 | 6270 | case 'z': /* must be zero register */ |
670a50eb ILT |
6271 | s_reset = s; |
6272 | if (s[0] == '$') | |
6273 | { | |
6274 | if (isdigit (s[1])) | |
6275 | { | |
6276 | ++s; | |
6277 | regno = 0; | |
6278 | do | |
6279 | { | |
6280 | regno *= 10; | |
6281 | regno += *s - '0'; | |
6282 | ++s; | |
6283 | } | |
6284 | while (isdigit (*s)); | |
0aa07269 ILT |
6285 | if (regno > 31) |
6286 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6287 | } |
0dd2d296 ILT |
6288 | else if (*args == 'E' || *args == 'G') |
6289 | goto notreg; | |
6290 | else | |
670a50eb | 6291 | { |
0aa07269 ILT |
6292 | if (s[1] == 'f' && s[2] == 'p') |
6293 | { | |
6294 | s += 3; | |
9226253a | 6295 | regno = FP; |
0aa07269 ILT |
6296 | } |
6297 | else if (s[1] == 's' && s[2] == 'p') | |
6298 | { | |
6299 | s += 3; | |
9226253a | 6300 | regno = SP; |
0aa07269 ILT |
6301 | } |
6302 | else if (s[1] == 'g' && s[2] == 'p') | |
6303 | { | |
6304 | s += 3; | |
9226253a | 6305 | regno = GP; |
0aa07269 ILT |
6306 | } |
6307 | else if (s[1] == 'a' && s[2] == 't') | |
6308 | { | |
6309 | s += 3; | |
9226253a | 6310 | regno = AT; |
0aa07269 | 6311 | } |
b2b8c24e ILT |
6312 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6313 | { | |
6314 | s += 4; | |
6315 | regno = KT0; | |
6316 | } | |
6317 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6318 | { | |
6319 | s += 4; | |
6320 | regno = KT1; | |
6321 | } | |
0aa07269 ILT |
6322 | else |
6323 | goto notreg; | |
670a50eb | 6324 | } |
9753202d ILT |
6325 | if (regno == AT |
6326 | && ! mips_noat | |
6327 | && *args != 'E' | |
6328 | && *args != 'G') | |
13fe1379 | 6329 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6330 | c = *args; |
6331 | if (*s == ' ') | |
6332 | s++; | |
6333 | if (args[1] != *s) | |
6334 | { | |
6335 | if (c == 'r' || c == 'v' || c == 'w') | |
6336 | { | |
6337 | regno = lastregno; | |
6338 | s = s_reset; | |
6339 | args++; | |
6340 | } | |
6341 | } | |
ff3a5c18 ILT |
6342 | /* 'z' only matches $0. */ |
6343 | if (c == 'z' && regno != 0) | |
6344 | break; | |
670a50eb ILT |
6345 | switch (c) |
6346 | { | |
3d3c5039 ILT |
6347 | case 'r': |
6348 | case 's': | |
6349 | case 'v': | |
6350 | case 'b': | |
670a50eb ILT |
6351 | ip->insn_opcode |= regno << 21; |
6352 | break; | |
3d3c5039 | 6353 | case 'd': |
918692a5 | 6354 | case 'G': |
670a50eb ILT |
6355 | ip->insn_opcode |= regno << 11; |
6356 | break; | |
3d3c5039 ILT |
6357 | case 'w': |
6358 | case 't': | |
918692a5 | 6359 | case 'E': |
670a50eb | 6360 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6361 | break; |
6362 | case 'x': | |
6363 | /* This case exists because on the r3000 trunc | |
6364 | expands into a macro which requires a gp | |
6365 | register. On the r6000 or r4000 it is | |
6366 | assembled into a single instruction which | |
6367 | ignores the register. Thus the insn version | |
6368 | is MIPS_ISA2 and uses 'x', and the macro | |
6369 | version is MIPS_ISA1 and uses 't'. */ | |
6370 | break; | |
ff3a5c18 ILT |
6371 | case 'z': |
6372 | /* This case is for the div instruction, which | |
6373 | acts differently if the destination argument | |
6374 | is $0. This only matches $0, and is checked | |
6375 | outside the switch. */ | |
6376 | break; | |
3d3c5039 | 6377 | } |
670a50eb ILT |
6378 | lastregno = regno; |
6379 | continue; | |
3d3c5039 ILT |
6380 | } |
6381 | notreg: | |
670a50eb ILT |
6382 | switch (*args++) |
6383 | { | |
3d3c5039 ILT |
6384 | case 'r': |
6385 | case 'v': | |
670a50eb ILT |
6386 | ip->insn_opcode |= lastregno << 21; |
6387 | continue; | |
3d3c5039 | 6388 | case 'w': |
670a50eb ILT |
6389 | ip->insn_opcode |= lastregno << 16; |
6390 | continue; | |
3d3c5039 | 6391 | } |
670a50eb | 6392 | break; |
3d3c5039 | 6393 | |
670a50eb ILT |
6394 | case 'D': /* floating point destination register */ |
6395 | case 'S': /* floating point source register */ | |
6396 | case 'T': /* floating point target register */ | |
d8a1c247 | 6397 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6398 | case 'V': |
6399 | case 'W': | |
670a50eb ILT |
6400 | s_reset = s; |
6401 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6402 | { | |
6403 | s += 2; | |
6404 | regno = 0; | |
6405 | do | |
6406 | { | |
6407 | regno *= 10; | |
6408 | regno += *s - '0'; | |
6409 | ++s; | |
6410 | } | |
6411 | while (isdigit (*s)); | |
6412 | ||
6413 | if (regno > 31) | |
6414 | as_bad ("Invalid float register number (%d)", regno); | |
6415 | ||
9226253a ILT |
6416 | if ((regno & 1) != 0 |
6417 | && mips_isa < 3 | |
538034cf ILT |
6418 | && ! (strcmp (str, "mtc1") == 0 |
6419 | || strcmp (str, "mfc1") == 0 | |
6420 | || strcmp (str, "lwc1") == 0 | |
6421 | || strcmp (str, "swc1") == 0 | |
6422 | || strcmp (str, "l.s") == 0 | |
6423 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6424 | as_warn ("Float register should be even, was %d", |
6425 | regno); | |
6426 | ||
6427 | c = *args; | |
6428 | if (*s == ' ') | |
6429 | s++; | |
6430 | if (args[1] != *s) | |
6431 | { | |
6432 | if (c == 'V' || c == 'W') | |
6433 | { | |
6434 | regno = lastregno; | |
6435 | s = s_reset; | |
6436 | args++; | |
3d3c5039 ILT |
6437 | } |
6438 | } | |
670a50eb ILT |
6439 | switch (c) |
6440 | { | |
3d3c5039 | 6441 | case 'D': |
670a50eb ILT |
6442 | ip->insn_opcode |= regno << 6; |
6443 | break; | |
3d3c5039 ILT |
6444 | case 'V': |
6445 | case 'S': | |
670a50eb ILT |
6446 | ip->insn_opcode |= regno << 11; |
6447 | break; | |
3d3c5039 ILT |
6448 | case 'W': |
6449 | case 'T': | |
670a50eb | 6450 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6451 | break; |
6452 | case 'R': | |
6453 | ip->insn_opcode |= regno << 21; | |
6454 | break; | |
3d3c5039 | 6455 | } |
670a50eb ILT |
6456 | lastregno = regno; |
6457 | continue; | |
3d3c5039 | 6458 | } |
670a50eb ILT |
6459 | switch (*args++) |
6460 | { | |
3d3c5039 | 6461 | case 'V': |
670a50eb ILT |
6462 | ip->insn_opcode |= lastregno << 11; |
6463 | continue; | |
3d3c5039 | 6464 | case 'W': |
670a50eb ILT |
6465 | ip->insn_opcode |= lastregno << 16; |
6466 | continue; | |
3d3c5039 | 6467 | } |
670a50eb | 6468 | break; |
3d3c5039 ILT |
6469 | |
6470 | case 'I': | |
670a50eb | 6471 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6472 | if (imm_expr.X_op != O_big |
6473 | && imm_expr.X_op != O_constant) | |
6474 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6475 | s = expr_end; |
6476 | continue; | |
3d3c5039 ILT |
6477 | |
6478 | case 'A': | |
670a50eb ILT |
6479 | my_getExpression (&offset_expr, s); |
6480 | imm_reloc = BFD_RELOC_32; | |
6481 | s = expr_end; | |
6482 | continue; | |
3d3c5039 ILT |
6483 | |
6484 | case 'F': | |
19ed8960 ILT |
6485 | case 'L': |
6486 | case 'f': | |
6487 | case 'l': | |
6488 | { | |
6489 | int f64; | |
6490 | char *save_in; | |
6491 | char *err; | |
6492 | unsigned char temp[8]; | |
604633ae ILT |
6493 | int len; |
6494 | unsigned int length; | |
19ed8960 ILT |
6495 | segT seg; |
6496 | subsegT subseg; | |
6497 | char *p; | |
6498 | ||
6499 | /* These only appear as the last operand in an | |
6500 | instruction, and every instruction that accepts | |
6501 | them in any variant accepts them in all variants. | |
6502 | This means we don't have to worry about backing out | |
6503 | any changes if the instruction does not match. | |
6504 | ||
6505 | The difference between them is the size of the | |
6506 | floating point constant and where it goes. For 'F' | |
6507 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6508 | is 32 bits. Where the constant is placed is based | |
6509 | on how the MIPS assembler does things: | |
6510 | F -- .rdata | |
6511 | L -- .lit8 | |
6512 | f -- immediate value | |
6513 | l -- .lit4 | |
0dd2d296 | 6514 | |
55933a58 ILT |
6515 | The .lit4 and .lit8 sections are only used if |
6516 | permitted by the -G argument. | |
6517 | ||
6518 | When generating embedded PIC code, we use the | |
6519 | .lit8 section but not the .lit4 section (we can do | |
6520 | .lit4 inline easily; we need to put .lit8 | |
6521 | somewhere in the data segment, and using .lit8 | |
6522 | permits the linker to eventually combine identical | |
6523 | .lit8 entries). */ | |
19ed8960 ILT |
6524 | |
6525 | f64 = *args == 'F' || *args == 'L'; | |
6526 | ||
6527 | save_in = input_line_pointer; | |
6528 | input_line_pointer = s; | |
604633ae ILT |
6529 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6530 | length = len; | |
19ed8960 ILT |
6531 | s = input_line_pointer; |
6532 | input_line_pointer = save_in; | |
6533 | if (err != NULL && *err != '\0') | |
6534 | { | |
6535 | as_bad ("Bad floating point constant: %s", err); | |
6536 | memset (temp, '\0', sizeof temp); | |
6537 | length = f64 ? 8 : 4; | |
6538 | } | |
6539 | ||
6540 | assert (length == (f64 ? 8 : 4)); | |
6541 | ||
0dd2d296 | 6542 | if (*args == 'f' |
55933a58 | 6543 | || (*args == 'l' |
1dc1e798 KR |
6544 | && (! USE_GLOBAL_POINTER_OPT |
6545 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6546 | || g_switch_value < 4) |
1113140a | 6547 | )) |
19ed8960 ILT |
6548 | { |
6549 | imm_expr.X_op = O_constant; | |
b9129c6f | 6550 | if (! target_big_endian) |
19ed8960 ILT |
6551 | imm_expr.X_add_number = |
6552 | (((((((int) temp[3] << 8) | |
6553 | | temp[2]) << 8) | |
6554 | | temp[1]) << 8) | |
6555 | | temp[0]); | |
6556 | else | |
6557 | imm_expr.X_add_number = | |
6558 | (((((((int) temp[0] << 8) | |
6559 | | temp[1]) << 8) | |
6560 | | temp[2]) << 8) | |
6561 | | temp[3]); | |
6562 | } | |
6563 | else | |
6564 | { | |
0dd2d296 ILT |
6565 | const char *newname; |
6566 | segT new_seg; | |
6567 | ||
19ed8960 ILT |
6568 | /* Switch to the right section. */ |
6569 | seg = now_seg; | |
6570 | subseg = now_subseg; | |
6571 | switch (*args) | |
6572 | { | |
0dd2d296 | 6573 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6574 | case 'L': |
1113140a | 6575 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6576 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6577 | newname = ".lit8"; |
0dd2d296 ILT |
6578 | break; |
6579 | case 'F': | |
d2c71068 | 6580 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6581 | break; |
6582 | case 'l': | |
1dc1e798 KR |
6583 | assert (!USE_GLOBAL_POINTER_OPT |
6584 | || g_switch_value >= 4); | |
0dd2d296 | 6585 | newname = ".lit4"; |
19ed8960 ILT |
6586 | break; |
6587 | } | |
0dd2d296 | 6588 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6589 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6590 | bfd_set_section_flags (stdoutput, new_seg, | |
6591 | (SEC_ALLOC | |
6592 | | SEC_LOAD | |
6593 | | SEC_READONLY | |
6594 | | SEC_DATA)); | |
0221ddf7 | 6595 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6596 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6597 | record_alignment (new_seg, 4); | |
6598 | else | |
6599 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6600 | if (seg == now_seg) |
6601 | as_bad ("Can't use floating point insn in this section"); | |
6602 | ||
6603 | /* Set the argument to the current address in the | |
6e8dda9c | 6604 | section. */ |
19ed8960 ILT |
6605 | offset_expr.X_op = O_symbol; |
6606 | offset_expr.X_add_symbol = | |
6607 | symbol_new ("L0\001", now_seg, | |
6608 | (valueT) frag_now_fix (), frag_now); | |
6609 | offset_expr.X_add_number = 0; | |
6610 | ||
6611 | /* Put the floating point number into the section. */ | |
604633ae | 6612 | p = frag_more ((int) length); |
19ed8960 ILT |
6613 | memcpy (p, temp, length); |
6614 | ||
6615 | /* Switch back to the original section. */ | |
6616 | subseg_set (seg, subseg); | |
6617 | } | |
6618 | } | |
670a50eb ILT |
6619 | continue; |
6620 | ||
6621 | case 'i': /* 16 bit unsigned immediate */ | |
6622 | case 'j': /* 16 bit signed immediate */ | |
6623 | imm_reloc = BFD_RELOC_LO16; | |
6624 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6625 | if (c != '\0') |
670a50eb ILT |
6626 | { |
6627 | if (c != 'l') | |
6628 | { | |
5ac34ac3 | 6629 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6630 | imm_expr.X_add_number = |
6631 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6632 | else if (c == 'h') | |
867a58b3 ILT |
6633 | { |
6634 | imm_reloc = BFD_RELOC_HI16_S; | |
6635 | imm_unmatched_hi = true; | |
6636 | } | |
670a50eb ILT |
6637 | else |
6638 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6639 | } |
670a50eb | 6640 | } |
670a50eb ILT |
6641 | if (*args == 'i') |
6642 | { | |
344a8d61 | 6643 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6644 | || ((imm_expr.X_add_number < 0 |
6645 | || imm_expr.X_add_number >= 0x10000) | |
6646 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6647 | { |
6648 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6649 | !strcmp (insn->name, insn[1].name)) | |
6650 | break; | |
9753202d ILT |
6651 | if (imm_expr.X_op != O_constant |
6652 | && imm_expr.X_op != O_big) | |
6653 | insn_error = "absolute expression required"; | |
6654 | else | |
6655 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6656 | } |
670a50eb ILT |
6657 | } |
6658 | else | |
6659 | { | |
d9aba805 ILT |
6660 | int more; |
6661 | offsetT max; | |
6662 | ||
be22008b ILT |
6663 | /* The upper bound should be 0x8000, but |
6664 | unfortunately the MIPS assembler accepts numbers | |
6665 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6666 | we want to be compatible. We only permit this |
6667 | extended range for an instruction which does not | |
6668 | provide any further alternates, since those | |
6669 | alternates may handle other cases. People should | |
6670 | use the numbers they mean, rather than relying on | |
6671 | a mysterious sign extension. */ | |
6672 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6673 | strcmp (insn->name, insn[1].name) == 0); | |
6674 | if (more) | |
6675 | max = 0x8000; | |
6676 | else | |
6677 | max = 0x10000; | |
344a8d61 | 6678 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6679 | || ((imm_expr.X_add_number < -0x8000 |
6680 | || imm_expr.X_add_number >= max) | |
6681 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6682 | || (more |
6683 | && imm_expr.X_add_number < 0 | |
6684 | && mips_isa >= 3 | |
6685 | && imm_expr.X_unsigned | |
6686 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6687 | { |
d9aba805 | 6688 | if (more) |
99c24539 | 6689 | break; |
9753202d ILT |
6690 | if (imm_expr.X_op != O_constant |
6691 | && imm_expr.X_op != O_big) | |
6692 | insn_error = "absolute expression required"; | |
6693 | else | |
6694 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6695 | } |
3d3c5039 | 6696 | } |
670a50eb ILT |
6697 | s = expr_end; |
6698 | continue; | |
6699 | ||
6700 | case 'o': /* 16 bit offset */ | |
6701 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6702 | |
6703 | /* If this value won't fit into a 16 bit offset, then go | |
6704 | find a macro that will generate the 32 bit offset | |
6705 | code pattern. As a special hack, we accept the | |
6706 | difference of two local symbols as a constant. This | |
6707 | is required to suppose embedded PIC switches, which | |
6708 | use an instruction which looks like | |
6709 | lw $4,$L12-$LS12($4) | |
6710 | The problem with handling this in a more general | |
6711 | fashion is that the macro function doesn't expect to | |
6712 | see anything which can be handled in a single | |
6713 | constant instruction. */ | |
6f0b87c3 SS |
6714 | if (c == 0 |
6715 | && (offset_expr.X_op != O_constant | |
6716 | || offset_expr.X_add_number >= 0x8000 | |
6717 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6718 | && (mips_pic != EMBEDDED_PIC |
6719 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6720 | || now_seg != text_section |
6721 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6722 | != text_section))) | |
670a50eb | 6723 | break; |
3d3c5039 | 6724 | |
670a50eb ILT |
6725 | offset_reloc = BFD_RELOC_LO16; |
6726 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6727 | { |
6728 | assert (offset_expr.X_op == O_constant); | |
6729 | offset_expr.X_add_number = | |
6730 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6731 | } | |
cc5703cd ILT |
6732 | s = expr_end; |
6733 | continue; | |
6734 | ||
6735 | case 'p': /* pc relative offset */ | |
6736 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6737 | my_getExpression (&offset_expr, s); | |
6738 | s = expr_end; | |
6739 | continue; | |
6740 | ||
6741 | case 'u': /* upper 16 bits */ | |
6742 | c = my_getSmallExpression (&imm_expr, s); | |
6743 | if (imm_expr.X_op == O_constant | |
6744 | && (imm_expr.X_add_number < 0 | |
6745 | || imm_expr.X_add_number >= 0x10000)) | |
6746 | as_bad ("lui expression not in range 0..65535"); | |
6747 | imm_reloc = BFD_RELOC_LO16; | |
6748 | if (c) | |
6749 | { | |
6750 | if (c != 'l') | |
6751 | { | |
6752 | if (imm_expr.X_op == O_constant) | |
6753 | imm_expr.X_add_number = | |
6754 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6755 | else if (c == 'h') | |
6756 | { | |
6757 | imm_reloc = BFD_RELOC_HI16_S; | |
6758 | imm_unmatched_hi = true; | |
6759 | } | |
6760 | else | |
6761 | imm_reloc = BFD_RELOC_HI16; | |
6762 | } | |
6763 | } | |
6764 | s = expr_end; | |
6765 | continue; | |
6766 | ||
6767 | case 'a': /* 26 bit address */ | |
6768 | my_getExpression (&offset_expr, s); | |
6769 | s = expr_end; | |
6770 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6771 | continue; | |
6772 | ||
6773 | case 'N': /* 3 bit branch condition code */ | |
6774 | case 'M': /* 3 bit compare condition code */ | |
6775 | if (strncmp (s, "$fcc", 4) != 0) | |
6776 | break; | |
6777 | s += 4; | |
6778 | regno = 0; | |
6779 | do | |
6780 | { | |
6781 | regno *= 10; | |
6782 | regno += *s - '0'; | |
6783 | ++s; | |
6784 | } | |
6785 | while (isdigit (*s)); | |
6786 | if (regno > 7) | |
6787 | as_bad ("invalid condition code register $fcc%d", regno); | |
6788 | if (*args == 'N') | |
6789 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6790 | else | |
6791 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6792 | continue; | |
6793 | ||
6794 | default: | |
6795 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6796 | internalError (); | |
6797 | } | |
6798 | break; | |
6799 | } | |
6800 | /* Args don't match. */ | |
6801 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6802 | !strcmp (insn->name, insn[1].name)) | |
6803 | { | |
6804 | ++insn; | |
6805 | s = argsStart; | |
6806 | continue; | |
6807 | } | |
6808 | insn_error = "illegal operands"; | |
6809 | return; | |
6810 | } | |
6811 | } | |
6812 | ||
6813 | /* This routine assembles an instruction into its binary format when | |
6814 | assembling for the mips16. As a side effect, it sets one of the | |
6815 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6816 | relocation to do if one of the operands is an address expression. |
6817 | It also sets mips16_small and mips16_ext if the user explicitly | |
6818 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6819 | |
6820 | static void | |
6821 | mips16_ip (str, ip) | |
6822 | char *str; | |
6823 | struct mips_cl_insn *ip; | |
6824 | { | |
6825 | char *s; | |
cc5703cd ILT |
6826 | const char *args; |
6827 | struct mips_opcode *insn; | |
6828 | char *argsstart; | |
6829 | unsigned int regno; | |
6830 | unsigned int lastregno = 0; | |
6831 | char *s_reset; | |
6832 | ||
6833 | insn_error = NULL; | |
6834 | ||
8728fa92 ILT |
6835 | mips16_small = false; |
6836 | mips16_ext = false; | |
cc5703cd ILT |
6837 | |
6838 | for (s = str; islower (*s); ++s) | |
6839 | ; | |
6840 | switch (*s) | |
6841 | { | |
6842 | case '\0': | |
6843 | break; | |
6844 | ||
6845 | case ' ': | |
6846 | *s++ = '\0'; | |
6847 | break; | |
6848 | ||
6849 | case '.': | |
6850 | if (s[1] == 't' && s[2] == ' ') | |
6851 | { | |
6852 | *s = '\0'; | |
8728fa92 | 6853 | mips16_small = true; |
cc5703cd ILT |
6854 | s += 3; |
6855 | break; | |
6856 | } | |
6857 | else if (s[1] == 'e' && s[2] == ' ') | |
6858 | { | |
6859 | *s = '\0'; | |
8728fa92 | 6860 | mips16_ext = true; |
cc5703cd ILT |
6861 | s += 3; |
6862 | break; | |
6863 | } | |
6864 | /* Fall through. */ | |
6865 | default: | |
6866 | insn_error = "unknown opcode"; | |
6867 | return; | |
6868 | } | |
6869 | ||
8728fa92 ILT |
6870 | if (! mips16_autoextend && ! mips16_ext) |
6871 | mips16_small = true; | |
6872 | ||
cc5703cd ILT |
6873 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6874 | { | |
6875 | insn_error = "unrecognized opcode"; | |
6876 | return; | |
6877 | } | |
6878 | ||
6879 | argsstart = s; | |
6880 | for (;;) | |
6881 | { | |
6882 | assert (strcmp (insn->name, str) == 0); | |
6883 | ||
6884 | ip->insn_mo = insn; | |
6885 | ip->insn_opcode = insn->match; | |
6886 | ip->use_extend = false; | |
6887 | imm_expr.X_op = O_absent; | |
6888 | imm_reloc = BFD_RELOC_UNUSED; | |
6889 | offset_expr.X_op = O_absent; | |
6890 | offset_reloc = BFD_RELOC_UNUSED; | |
6891 | for (args = insn->args; 1; ++args) | |
6892 | { | |
6893 | int c; | |
6894 | ||
6895 | if (*s == ' ') | |
6896 | ++s; | |
6897 | ||
6898 | /* In this switch statement we call break if we did not find | |
6899 | a match, continue if we did find a match, or return if we | |
6900 | are done. */ | |
6901 | ||
6902 | c = *args; | |
6903 | switch (c) | |
6904 | { | |
6905 | case '\0': | |
6906 | if (*s == '\0') | |
6907 | { | |
6908 | /* Stuff the immediate value in now, if we can. */ | |
6909 | if (imm_expr.X_op == O_constant | |
6910 | && imm_reloc > BFD_RELOC_UNUSED | |
6911 | && insn->pinfo != INSN_MACRO) | |
6912 | { | |
15e69f98 ILT |
6913 | mips16_immed ((char *) NULL, 0, |
6914 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6915 | imm_expr.X_add_number, true, mips16_small, |
6916 | mips16_ext, &ip->insn_opcode, | |
6917 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
6918 | imm_expr.X_op = O_absent; |
6919 | imm_reloc = BFD_RELOC_UNUSED; | |
6920 | } | |
6921 | ||
6922 | return; | |
6923 | } | |
6924 | break; | |
6925 | ||
6926 | case ',': | |
6927 | if (*s++ == c) | |
6928 | continue; | |
6929 | s--; | |
6930 | switch (*++args) | |
6931 | { | |
6932 | case 'v': | |
6933 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6934 | continue; | |
6935 | case 'w': | |
6936 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6937 | continue; | |
6938 | } | |
6939 | break; | |
6940 | ||
6941 | case '(': | |
6942 | case ')': | |
6943 | if (*s++ == c) | |
6944 | continue; | |
6945 | break; | |
6946 | ||
6947 | case 'v': | |
6948 | case 'w': | |
6949 | if (s[0] != '$') | |
6950 | { | |
6951 | if (c == 'v') | |
6952 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6953 | else | |
6954 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6955 | ++args; | |
6956 | continue; | |
6957 | } | |
6958 | /* Fall through. */ | |
6959 | case 'x': | |
6960 | case 'y': | |
6961 | case 'z': | |
6962 | case 'Z': | |
6963 | case '0': | |
6964 | case 'S': | |
6965 | case 'R': | |
6966 | case 'X': | |
6967 | case 'Y': | |
6968 | if (s[0] != '$') | |
6969 | break; | |
6970 | s_reset = s; | |
6971 | if (isdigit (s[1])) | |
6972 | { | |
6973 | ++s; | |
6974 | regno = 0; | |
6975 | do | |
6976 | { | |
6977 | regno *= 10; | |
6978 | regno += *s - '0'; | |
6979 | ++s; | |
6980 | } | |
6981 | while (isdigit (*s)); | |
6982 | if (regno > 31) | |
6983 | { | |
6984 | as_bad ("invalid register number (%d)", regno); | |
6985 | regno = 2; | |
6986 | } | |
6987 | } | |
6988 | else | |
6989 | { | |
6990 | if (s[1] == 'f' && s[2] == 'p') | |
6991 | { | |
6992 | s += 3; | |
6993 | regno = FP; | |
6994 | } | |
6995 | else if (s[1] == 's' && s[2] == 'p') | |
6996 | { | |
6997 | s += 3; | |
6998 | regno = SP; | |
6999 | } | |
7000 | else if (s[1] == 'g' && s[2] == 'p') | |
7001 | { | |
7002 | s += 3; | |
7003 | regno = GP; | |
7004 | } | |
7005 | else if (s[1] == 'a' && s[2] == 't') | |
7006 | { | |
7007 | s += 3; | |
7008 | regno = AT; | |
7009 | } | |
7010 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7011 | { | |
7012 | s += 4; | |
7013 | regno = KT0; | |
7014 | } | |
7015 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7016 | { | |
7017 | s += 4; | |
7018 | regno = KT1; | |
7019 | } | |
7020 | else | |
7021 | break; | |
7022 | } | |
7023 | ||
7024 | if (*s == ' ') | |
7025 | ++s; | |
7026 | if (args[1] != *s) | |
7027 | { | |
7028 | if (c == 'v' || c == 'w') | |
7029 | { | |
7030 | regno = mips16_to_32_reg_map[lastregno]; | |
7031 | s = s_reset; | |
7032 | args++; | |
7033 | } | |
7034 | } | |
7035 | ||
7036 | switch (c) | |
7037 | { | |
7038 | case 'x': | |
7039 | case 'y': | |
7040 | case 'z': | |
7041 | case 'v': | |
7042 | case 'w': | |
7043 | case 'Z': | |
7044 | regno = mips32_to_16_reg_map[regno]; | |
7045 | break; | |
7046 | ||
7047 | case '0': | |
7048 | if (regno != 0) | |
7049 | regno = ILLEGAL_REG; | |
7050 | break; | |
7051 | ||
7052 | case 'S': | |
7053 | if (regno != SP) | |
7054 | regno = ILLEGAL_REG; | |
7055 | break; | |
7056 | ||
7057 | case 'R': | |
7058 | if (regno != RA) | |
7059 | regno = ILLEGAL_REG; | |
7060 | break; | |
7061 | ||
7062 | case 'X': | |
7063 | case 'Y': | |
7064 | if (regno == AT && ! mips_noat) | |
7065 | as_warn ("used $at without \".set noat\""); | |
7066 | break; | |
7067 | ||
7068 | default: | |
7069 | internalError (); | |
7070 | } | |
7071 | ||
7072 | if (regno == ILLEGAL_REG) | |
7073 | break; | |
7074 | ||
7075 | switch (c) | |
7076 | { | |
7077 | case 'x': | |
7078 | case 'v': | |
7079 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7080 | break; | |
7081 | case 'y': | |
7082 | case 'w': | |
7083 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7084 | break; | |
7085 | case 'z': | |
7086 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7087 | break; | |
7088 | case 'Z': | |
7089 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7090 | case '0': | |
7091 | case 'S': | |
7092 | case 'R': | |
7093 | break; | |
7094 | case 'X': | |
7095 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7096 | break; | |
7097 | case 'Y': | |
7098 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7099 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7100 | break; | |
7101 | default: | |
7102 | internalError (); | |
7103 | } | |
7104 | ||
7105 | lastregno = regno; | |
7106 | continue; | |
7107 | ||
7108 | case 'P': | |
7109 | if (strncmp (s, "$pc", 3) == 0) | |
7110 | { | |
7111 | s += 3; | |
7112 | continue; | |
7113 | } | |
7114 | break; | |
7115 | ||
7116 | case '<': | |
7117 | case '>': | |
7118 | case '[': | |
7119 | case ']': | |
7120 | case '4': | |
7121 | case '5': | |
7122 | case 'H': | |
7123 | case 'W': | |
7124 | case 'D': | |
7125 | case 'j': | |
7126 | case '8': | |
7127 | case 'V': | |
7128 | case 'C': | |
7129 | case 'U': | |
7130 | case 'k': | |
7131 | case 'K': | |
7132 | if (s[0] == '$' && isdigit (s[1])) | |
7133 | { | |
7134 | /* Looks like a register name. */ | |
7135 | break; | |
7136 | } | |
c0dea495 ILT |
7137 | |
7138 | if (s[0] == '(' | |
7139 | && args[1] == '(' | |
7140 | && s[1] == '$') | |
7141 | { | |
7142 | /* It looks like the expression was omitted before a | |
7143 | register indirection, which means that the | |
7144 | expression is implicitly zero. */ | |
7145 | continue; | |
7146 | } | |
7147 | ||
cc5703cd ILT |
7148 | my_getExpression (&imm_expr, s); |
7149 | /* We need to relax this instruction. */ | |
7150 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7151 | s = expr_end; | |
7152 | continue; | |
7153 | ||
7154 | case 'p': | |
7155 | case 'q': | |
7156 | case 'A': | |
7157 | case 'B': | |
7158 | case 'E': | |
7159 | /* We use offset_reloc rather than imm_reloc for the PC | |
7160 | relative operands. This lets macros with both | |
7161 | immediate and address operands work correctly. */ | |
7162 | if (s[0] == '$' && isdigit (s[1])) | |
7163 | { | |
7164 | /* Looks like a register name. */ | |
7165 | break; | |
7166 | } | |
670a50eb | 7167 | my_getExpression (&offset_expr, s); |
cc5703cd ILT |
7168 | /* We need to relax this instruction. */ |
7169 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7170 | s = expr_end; |
7171 | continue; | |
7172 | ||
cc5703cd ILT |
7173 | case '6': /* break code */ |
7174 | my_getExpression (&imm_expr, s); | |
7175 | check_absolute_expr (ip, &imm_expr); | |
7176 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7177 | { |
cc5703cd ILT |
7178 | as_warn ("Invalid value for `%s' (%lu)", |
7179 | ip->insn_mo->name, | |
7180 | (unsigned long) imm_expr.X_add_number); | |
7181 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7182 | } |
cc5703cd ILT |
7183 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7184 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7185 | s = expr_end; |
7186 | continue; | |
3d3c5039 | 7187 | |
670a50eb ILT |
7188 | case 'a': /* 26 bit address */ |
7189 | my_getExpression (&offset_expr, s); | |
7190 | s = expr_end; | |
cc5703cd ILT |
7191 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7192 | ip->insn_opcode <<= 16; | |
670a50eb | 7193 | continue; |
3d3c5039 | 7194 | |
cc5703cd ILT |
7195 | case 'l': /* register list for entry macro */ |
7196 | case 'L': /* register list for exit macro */ | |
7197 | { | |
7198 | int mask; | |
7199 | ||
7200 | if (c == 'l') | |
7201 | mask = 0; | |
7202 | else | |
7203 | mask = 7 << 3; | |
7204 | while (*s != '\0') | |
7205 | { | |
7206 | int reg1, reg2; | |
7207 | ||
7208 | while (*s == ' ' || *s == ',') | |
7209 | ++s; | |
7210 | if (*s != '$') | |
7211 | { | |
7212 | as_bad ("can't parse register list"); | |
7213 | break; | |
7214 | } | |
7215 | ++s; | |
7216 | reg1 = 0; | |
7217 | while (isdigit (*s)) | |
7218 | { | |
7219 | reg1 *= 10; | |
7220 | reg1 += *s - '0'; | |
7221 | ++s; | |
7222 | } | |
7223 | if (*s == ' ') | |
7224 | ++s; | |
7225 | if (*s != '-') | |
7226 | reg2 = reg1; | |
7227 | else | |
7228 | { | |
7229 | ++s; | |
7230 | if (*s != '$') | |
7231 | break; | |
7232 | ++s; | |
7233 | reg2 = 0; | |
7234 | while (isdigit (*s)) | |
7235 | { | |
7236 | reg2 *= 10; | |
7237 | reg2 += *s - '0'; | |
7238 | ++s; | |
7239 | } | |
7240 | } | |
7241 | if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
7242 | mask |= (reg2 - 3) << 3; | |
7243 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7244 | mask |= (reg2 - 15) << 1; | |
7245 | else if (reg1 == 31 && reg2 == 31) | |
7246 | mask |= 1; | |
7247 | else | |
7248 | as_bad ("invalid register list"); | |
7249 | } | |
7250 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
7251 | } | |
7252 | continue; | |
d8a1c247 | 7253 | |
3d3c5039 | 7254 | default: |
670a50eb | 7255 | internalError (); |
3d3c5039 | 7256 | } |
670a50eb | 7257 | break; |
3d3c5039 | 7258 | } |
cc5703cd | 7259 | |
670a50eb | 7260 | /* Args don't match. */ |
cc5703cd ILT |
7261 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7262 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7263 | { |
7264 | ++insn; | |
cc5703cd | 7265 | s = argsstart; |
670a50eb | 7266 | continue; |
3d3c5039 | 7267 | } |
cc5703cd | 7268 | |
9753202d | 7269 | insn_error = "illegal operands"; |
cc5703cd | 7270 | |
670a50eb | 7271 | return; |
3d3c5039 ILT |
7272 | } |
7273 | } | |
7274 | ||
cc5703cd ILT |
7275 | /* This structure holds information we know about a mips16 immediate |
7276 | argument type. */ | |
7277 | ||
7278 | struct mips16_immed_operand | |
7279 | { | |
7280 | /* The type code used in the argument string in the opcode table. */ | |
7281 | int type; | |
7282 | /* The number of bits in the short form of the opcode. */ | |
7283 | int nbits; | |
7284 | /* The number of bits in the extended form of the opcode. */ | |
7285 | int extbits; | |
7286 | /* The amount by which the short form is shifted when it is used; | |
7287 | for example, the sw instruction has a shift count of 2. */ | |
7288 | int shift; | |
7289 | /* The amount by which the short form is shifted when it is stored | |
7290 | into the instruction code. */ | |
7291 | int op_shift; | |
7292 | /* Non-zero if the short form is unsigned. */ | |
7293 | int unsp; | |
7294 | /* Non-zero if the extended form is unsigned. */ | |
7295 | int extu; | |
7296 | /* Non-zero if the value is PC relative. */ | |
7297 | int pcrel; | |
7298 | }; | |
7299 | ||
7300 | /* The mips16 immediate operand types. */ | |
7301 | ||
7302 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7303 | { | |
7304 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7305 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7306 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7307 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7308 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7309 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7310 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7311 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7312 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7313 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7314 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7315 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7316 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7317 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7318 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7319 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7320 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7321 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7322 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7323 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7324 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7325 | }; | |
7326 | ||
7327 | #define MIPS16_NUM_IMMED \ | |
7328 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7329 | ||
7330 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7331 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7332 | whether an extended value is needed; if one is needed, it sets | |
7333 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7334 | If SMALL is true, an unextended opcode was explicitly requested. | |
7335 | If EXT is true, an extended opcode was explicitly requested. If | |
7336 | WARN is true, warn if EXT does not match reality. */ | |
7337 | ||
7338 | static void | |
15e69f98 ILT |
7339 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7340 | extend) | |
7341 | char *file; | |
7342 | unsigned int line; | |
cc5703cd ILT |
7343 | int type; |
7344 | offsetT val; | |
7345 | boolean warn; | |
7346 | boolean small; | |
7347 | boolean ext; | |
7348 | unsigned long *insn; | |
7349 | boolean *use_extend; | |
7350 | unsigned short *extend; | |
7351 | { | |
7352 | register const struct mips16_immed_operand *op; | |
7353 | int mintiny, maxtiny; | |
7354 | boolean needext; | |
7355 | ||
7356 | op = mips16_immed_operands; | |
7357 | while (op->type != type) | |
7358 | { | |
7359 | ++op; | |
7360 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7361 | } | |
7362 | ||
7363 | if (op->unsp) | |
7364 | { | |
7365 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7366 | { | |
7367 | mintiny = 1; | |
7368 | maxtiny = 1 << op->nbits; | |
7369 | } | |
7370 | else | |
7371 | { | |
7372 | mintiny = 0; | |
7373 | maxtiny = (1 << op->nbits) - 1; | |
7374 | } | |
7375 | } | |
7376 | else | |
7377 | { | |
7378 | mintiny = - (1 << (op->nbits - 1)); | |
7379 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7380 | } | |
7381 | ||
7382 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7383 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7384 | val /= 2; |
cc5703cd ILT |
7385 | |
7386 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7387 | || val < (mintiny << op->shift) | |
7388 | || val > (maxtiny << op->shift)) | |
7389 | needext = true; | |
7390 | else | |
7391 | needext = false; | |
7392 | ||
7393 | if (warn && ext && ! needext) | |
15e69f98 | 7394 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7395 | if (small && needext) |
15e69f98 | 7396 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7397 | |
7398 | if (small || (! ext && ! needext)) | |
7399 | { | |
7400 | int insnval; | |
7401 | ||
7402 | *use_extend = false; | |
7403 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7404 | insnval <<= op->op_shift; | |
7405 | *insn |= insnval; | |
7406 | } | |
7407 | else | |
7408 | { | |
7409 | long minext, maxext; | |
7410 | int extval; | |
7411 | ||
7412 | if (op->extu) | |
7413 | { | |
7414 | minext = 0; | |
7415 | maxext = (1 << op->extbits) - 1; | |
7416 | } | |
7417 | else | |
7418 | { | |
7419 | minext = - (1 << (op->extbits - 1)); | |
7420 | maxext = (1 << (op->extbits - 1)) - 1; | |
7421 | } | |
7422 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7423 | as_bad_where (file, line, |
7424 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7425 | |
7426 | *use_extend = true; | |
7427 | if (op->extbits == 16) | |
7428 | { | |
7429 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7430 | val &= 0x1f; | |
7431 | } | |
7432 | else if (op->extbits == 15) | |
7433 | { | |
7434 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7435 | val &= 0xf; | |
7436 | } | |
7437 | else | |
7438 | { | |
7439 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7440 | val = 0; | |
7441 | } | |
7442 | ||
7443 | *extend = (unsigned short) extval; | |
7444 | *insn |= val; | |
7445 | } | |
7446 | } | |
7447 | \f | |
3d3c5039 ILT |
7448 | #define LP '(' |
7449 | #define RP ')' | |
7450 | ||
7451 | static int | |
7452 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7453 | expressionS *ep; |
7454 | char *str; | |
3d3c5039 | 7455 | { |
670a50eb ILT |
7456 | char *sp; |
7457 | int c = 0; | |
7458 | ||
7459 | if (*str == ' ') | |
7460 | str++; | |
7461 | if (*str == LP | |
7462 | || (*str == '%' && | |
7463 | ((str[1] == 'h' && str[2] == 'i') | |
7464 | || (str[1] == 'H' && str[2] == 'I') | |
7465 | || (str[1] == 'l' && str[2] == 'o')) | |
7466 | && str[3] == LP)) | |
7467 | { | |
7468 | if (*str == LP) | |
7469 | c = 0; | |
7470 | else | |
7471 | { | |
7472 | c = str[1]; | |
7473 | str += 3; | |
7474 | } | |
7475 | ||
7476 | /* | |
7477 | * A small expression may be followed by a base register. | |
7478 | * Scan to the end of this operand, and then back over a possible | |
7479 | * base register. Then scan the small expression up to that | |
7480 | * point. (Based on code in sparc.c...) | |
7481 | */ | |
7482 | for (sp = str; *sp && *sp != ','; sp++) | |
7483 | ; | |
7484 | if (sp - 4 >= str && sp[-1] == RP) | |
7485 | { | |
7486 | if (isdigit (sp[-2])) | |
7487 | { | |
7488 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7489 | ; | |
7490 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7491 | { | |
7492 | sp--; | |
7493 | goto do_it; | |
3d3c5039 | 7494 | } |
670a50eb ILT |
7495 | } |
7496 | else if (sp - 5 >= str | |
7497 | && sp[-5] == LP | |
7498 | && sp[-4] == '$' | |
7499 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7500 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7501 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7502 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7503 | { | |
7504 | sp -= 5; | |
3d3c5039 | 7505 | do_it: |
670a50eb ILT |
7506 | if (sp == str) |
7507 | { | |
7508 | /* no expression means zero offset */ | |
7509 | if (c) | |
7510 | { | |
7511 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7512 | ep->X_op = O_absent; |
670a50eb | 7513 | expr_end = str - 3; |
3d3c5039 | 7514 | } |
670a50eb ILT |
7515 | else |
7516 | { | |
52aa70b5 | 7517 | ep->X_op = O_constant; |
670a50eb ILT |
7518 | expr_end = sp; |
7519 | } | |
7520 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7521 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7522 | ep->X_add_number = 0; |
7523 | } | |
7524 | else | |
7525 | { | |
7526 | *sp = '\0'; | |
7527 | my_getExpression (ep, str); | |
7528 | *sp = LP; | |
3d3c5039 | 7529 | } |
670a50eb | 7530 | return c; |
3d3c5039 ILT |
7531 | } |
7532 | } | |
7533 | } | |
670a50eb ILT |
7534 | my_getExpression (ep, str); |
7535 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7536 | } |
7537 | ||
7538 | static void | |
7539 | my_getExpression (ep, str) | |
670a50eb ILT |
7540 | expressionS *ep; |
7541 | char *str; | |
3d3c5039 | 7542 | { |
670a50eb | 7543 | char *save_in; |
670a50eb ILT |
7544 | |
7545 | save_in = input_line_pointer; | |
7546 | input_line_pointer = str; | |
5ac34ac3 | 7547 | expression (ep); |
670a50eb ILT |
7548 | expr_end = input_line_pointer; |
7549 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7550 | } |
7551 | ||
becfe05e ILT |
7552 | /* Turn a string in input_line_pointer into a floating point constant |
7553 | of type type, and store the appropriate bytes in *litP. The number | |
7554 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7555 | returned, or NULL on OK. */ | |
7556 | ||
3d3c5039 | 7557 | char * |
670a50eb | 7558 | md_atof (type, litP, sizeP) |
becfe05e | 7559 | int type; |
3d3c5039 ILT |
7560 | char *litP; |
7561 | int *sizeP; | |
7562 | { | |
becfe05e ILT |
7563 | int prec; |
7564 | LITTLENUM_TYPE words[4]; | |
7565 | char *t; | |
7566 | int i; | |
7567 | ||
7568 | switch (type) | |
7569 | { | |
7570 | case 'f': | |
7571 | prec = 2; | |
7572 | break; | |
7573 | ||
7574 | case 'd': | |
7575 | prec = 4; | |
7576 | break; | |
7577 | ||
7578 | default: | |
7579 | *sizeP = 0; | |
7580 | return "bad call to md_atof"; | |
7581 | } | |
7582 | ||
7583 | t = atof_ieee (input_line_pointer, type, words); | |
7584 | if (t) | |
7585 | input_line_pointer = t; | |
7586 | ||
7587 | *sizeP = prec * 2; | |
7588 | ||
b9129c6f | 7589 | if (! target_big_endian) |
becfe05e ILT |
7590 | { |
7591 | for (i = prec - 1; i >= 0; i--) | |
7592 | { | |
7593 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7594 | litP += 2; | |
7595 | } | |
7596 | } | |
7597 | else | |
7598 | { | |
7599 | for (i = 0; i < prec; i++) | |
7600 | { | |
7601 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7602 | litP += 2; | |
7603 | } | |
7604 | } | |
7605 | ||
670a50eb | 7606 | return NULL; |
3d3c5039 ILT |
7607 | } |
7608 | ||
7609 | void | |
7610 | md_number_to_chars (buf, val, n) | |
7611 | char *buf; | |
918692a5 | 7612 | valueT val; |
3d3c5039 ILT |
7613 | int n; |
7614 | { | |
b9129c6f ILT |
7615 | if (target_big_endian) |
7616 | number_to_chars_bigendian (buf, val, n); | |
7617 | else | |
7618 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 7619 | } |
f3d817d8 | 7620 | \f |
e8d4d475 | 7621 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7622 | |
f3d817d8 DM |
7623 | struct option md_longopts[] = { |
7624 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7625 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7626 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7627 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7628 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7629 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7630 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7631 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7632 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7633 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7634 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7635 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7636 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7637 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7638 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7639 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7640 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7641 | {"break", no_argument, NULL, OPTION_BREAK}, |
7642 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7643 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7644 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7645 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7646 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7647 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7648 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7649 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7650 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7651 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7652 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7653 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7654 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7655 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7656 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7657 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7658 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7659 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7660 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7661 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7662 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f3d817d8 | 7663 | |
d8a1c247 | 7664 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7665 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7666 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7667 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7668 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7669 | #ifdef OBJ_ELF |
f3d817d8 | 7670 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7671 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7672 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7673 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7674 | {"32", no_argument, NULL, OPTION_32}, |
7675 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7676 | #endif |
7677 | ||
7678 | {NULL, no_argument, NULL, 0} | |
7679 | }; | |
7680 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7681 | |
7682 | int | |
f3d817d8 DM |
7683 | md_parse_option (c, arg) |
7684 | int c; | |
7685 | char *arg; | |
3d3c5039 | 7686 | { |
f3d817d8 | 7687 | switch (c) |
670a50eb | 7688 | { |
f3d817d8 DM |
7689 | case OPTION_TRAP: |
7690 | mips_trap = 1; | |
7691 | break; | |
670a50eb | 7692 | |
f3d817d8 DM |
7693 | case OPTION_BREAK: |
7694 | mips_trap = 0; | |
7695 | break; | |
7696 | ||
e8d4d475 | 7697 | case OPTION_EB: |
1dc1e798 | 7698 | target_big_endian = 1; |
e8d4d475 | 7699 | break; |
04cb3372 | 7700 | |
e8d4d475 | 7701 | case OPTION_EL: |
1dc1e798 | 7702 | target_big_endian = 0; |
f3d817d8 | 7703 | break; |
670a50eb | 7704 | |
f3d817d8 DM |
7705 | case 'O': |
7706 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7707 | mips_optimize = 1; |
7708 | else | |
7709 | mips_optimize = 2; | |
f3d817d8 | 7710 | break; |
0aa07269 | 7711 | |
f3d817d8 | 7712 | case 'g': |
22ba90ce ILT |
7713 | if (arg == NULL) |
7714 | mips_debug = 2; | |
7715 | else | |
7716 | mips_debug = atoi (arg); | |
7717 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7718 | optimizations which limit full symbolic debugging. We take | |
7719 | that to be equivalent to -O0. */ | |
7720 | if (mips_debug == 2) | |
0aa07269 | 7721 | mips_optimize = 0; |
f3d817d8 | 7722 | break; |
4e95866e | 7723 | |
f3d817d8 DM |
7724 | case OPTION_MIPS1: |
7725 | mips_isa = 1; | |
4bb0cc41 ILT |
7726 | if (mips_cpu == -1) |
7727 | mips_cpu = 3000; | |
f3d817d8 | 7728 | break; |
8358c818 | 7729 | |
f3d817d8 DM |
7730 | case OPTION_MIPS2: |
7731 | mips_isa = 2; | |
4bb0cc41 ILT |
7732 | if (mips_cpu == -1) |
7733 | mips_cpu = 6000; | |
f3d817d8 | 7734 | break; |
8358c818 | 7735 | |
f3d817d8 DM |
7736 | case OPTION_MIPS3: |
7737 | mips_isa = 3; | |
4bb0cc41 ILT |
7738 | if (mips_cpu == -1) |
7739 | mips_cpu = 4000; | |
f3d817d8 | 7740 | break; |
8358c818 | 7741 | |
d8a1c247 KR |
7742 | case OPTION_MIPS4: |
7743 | mips_isa = 4; | |
7744 | if (mips_cpu == -1) | |
7745 | mips_cpu = 8000; | |
7746 | break; | |
7747 | ||
f3d817d8 DM |
7748 | case OPTION_MCPU: |
7749 | { | |
7750 | char *p; | |
7751 | ||
7752 | /* Identify the processor type */ | |
7753 | p = arg; | |
7754 | if (strcmp (p, "default") == 0 | |
7755 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7756 | mips_cpu = -1; |
f3d817d8 DM |
7757 | else |
7758 | { | |
c625fc23 JSC |
7759 | int sv = 0; |
7760 | ||
7761 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7762 | processor. */ | |
7763 | if (*p == 'v' || *p == 'V') | |
7764 | { | |
7765 | sv = 1; | |
7766 | p++; | |
7767 | } | |
7768 | ||
f3d817d8 DM |
7769 | if (*p == 'r' || *p == 'R') |
7770 | p++; | |
8358c818 | 7771 | |
4bb0cc41 | 7772 | mips_cpu = -1; |
f3d817d8 DM |
7773 | switch (*p) |
7774 | { | |
d8a1c247 KR |
7775 | case '1': |
7776 | if (strcmp (p, "10000") == 0 | |
7777 | || strcmp (p, "10k") == 0 | |
7778 | || strcmp (p, "10K") == 0) | |
7779 | mips_cpu = 10000; | |
7780 | break; | |
7781 | ||
f3d817d8 DM |
7782 | case '2': |
7783 | if (strcmp (p, "2000") == 0 | |
7784 | || strcmp (p, "2k") == 0 | |
7785 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7786 | mips_cpu = 2000; |
f3d817d8 | 7787 | break; |
8358c818 | 7788 | |
f3d817d8 DM |
7789 | case '3': |
7790 | if (strcmp (p, "3000") == 0 | |
7791 | || strcmp (p, "3k") == 0 | |
7792 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7793 | mips_cpu = 3000; |
f3d817d8 | 7794 | break; |
8358c818 | 7795 | |
f3d817d8 DM |
7796 | case '4': |
7797 | if (strcmp (p, "4000") == 0 | |
7798 | || strcmp (p, "4k") == 0 | |
8c63448a | 7799 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7800 | mips_cpu = 4000; |
c625fc23 JSC |
7801 | else if (strcmp (p, "4100") == 0) |
7802 | { | |
7803 | mips_cpu = 4100; | |
7804 | if (mips_4100 < 0) | |
7805 | mips_4100 = 1; | |
7806 | } | |
7807 | else if (strcmp (p, "4300") == 0) | |
7808 | mips_cpu = 4300; | |
8c63448a | 7809 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7810 | mips_cpu = 4400; |
8c63448a | 7811 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7812 | mips_cpu = 4600; |
b2b8c24e ILT |
7813 | else if (strcmp (p, "4650") == 0) |
7814 | { | |
7815 | mips_cpu = 4650; | |
7816 | if (mips_4650 < 0) | |
7817 | mips_4650 = 1; | |
7818 | } | |
e532b44c ILT |
7819 | else if (strcmp (p, "4010") == 0) |
7820 | { | |
7821 | mips_cpu = 4010; | |
7822 | if (mips_4010 < 0) | |
7823 | mips_4010 = 1; | |
7824 | } | |
f3d817d8 | 7825 | break; |
8358c818 | 7826 | |
517078c1 ILT |
7827 | case '5': |
7828 | if (strcmp (p, "5000") == 0 | |
7829 | || strcmp (p, "5k") == 0 | |
7830 | || strcmp (p, "5K") == 0) | |
7831 | mips_cpu = 5000; | |
7832 | break; | |
7833 | ||
f3d817d8 DM |
7834 | case '6': |
7835 | if (strcmp (p, "6000") == 0 | |
7836 | || strcmp (p, "6k") == 0 | |
7837 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7838 | mips_cpu = 6000; |
f3d817d8 | 7839 | break; |
55933a58 | 7840 | |
d8a1c247 KR |
7841 | case '8': |
7842 | if (strcmp (p, "8000") == 0 | |
7843 | || strcmp (p, "8k") == 0 | |
7844 | || strcmp (p, "8K") == 0) | |
7845 | mips_cpu = 8000; | |
7846 | break; | |
7847 | ||
55933a58 ILT |
7848 | case 'o': |
7849 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7850 | mips_cpu = 4600; |
55933a58 | 7851 | break; |
f3d817d8 | 7852 | } |
8358c818 | 7853 | |
517078c1 | 7854 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7855 | { |
7856 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
7857 | return 0; | |
7858 | } | |
7859 | ||
4bb0cc41 | 7860 | if (mips_cpu == -1) |
f3d817d8 DM |
7861 | { |
7862 | as_bad ("invalid architecture -mcpu=%s", arg); | |
7863 | return 0; | |
7864 | } | |
7865 | } | |
7866 | } | |
7867 | break; | |
8358c818 | 7868 | |
b2b8c24e ILT |
7869 | case OPTION_M4650: |
7870 | mips_4650 = 1; | |
7871 | break; | |
7872 | ||
7873 | case OPTION_NO_M4650: | |
7874 | mips_4650 = 0; | |
7875 | break; | |
7876 | ||
e532b44c ILT |
7877 | case OPTION_M4010: |
7878 | mips_4010 = 1; | |
7879 | break; | |
7880 | ||
7881 | case OPTION_NO_M4010: | |
7882 | mips_4010 = 0; | |
7883 | break; | |
7884 | ||
c625fc23 JSC |
7885 | case OPTION_M4100: |
7886 | mips_4100 = 1; | |
7887 | break; | |
7888 | ||
7889 | case OPTION_NO_M4100: | |
7890 | mips_4100 = 0; | |
7891 | break; | |
7892 | ||
cc5703cd ILT |
7893 | case OPTION_MIPS16: |
7894 | mips16 = 1; | |
7895 | mips_no_prev_insn (); | |
7896 | break; | |
7897 | ||
7898 | case OPTION_NO_MIPS16: | |
7899 | mips16 = 0; | |
7900 | mips_no_prev_insn (); | |
7901 | break; | |
7902 | ||
f3d817d8 | 7903 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 7904 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 7905 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
7906 | { |
7907 | as_bad ("-G may not be used with embedded PIC code"); | |
7908 | return 0; | |
7909 | } | |
5b63f465 | 7910 | g_switch_value = 0x7fffffff; |
f3d817d8 | 7911 | break; |
d9aba805 | 7912 | |
fb251650 ILT |
7913 | /* When generating ELF code, we permit -KPIC and -call_shared to |
7914 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
7915 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 7916 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
7917 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7918 | { | |
7919 | as_bad ("-call_shared is supported only for ELF format"); | |
7920 | return 0; | |
7921 | } | |
d9aba805 ILT |
7922 | mips_pic = SVR4_PIC; |
7923 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
7924 | { |
7925 | as_bad ("-G may not be used with SVR4 PIC code"); | |
7926 | return 0; | |
7927 | } | |
d9aba805 | 7928 | g_switch_value = 0; |
f3d817d8 DM |
7929 | break; |
7930 | ||
7931 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
7932 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7933 | { | |
7934 | as_bad ("-non_shared is supported only for ELF format"); | |
7935 | return 0; | |
7936 | } | |
d9aba805 | 7937 | mips_pic = NO_PIC; |
f3d817d8 | 7938 | break; |
8358c818 | 7939 | |
fb251650 ILT |
7940 | /* The -xgot option tells the assembler to use 32 offsets when |
7941 | accessing the got in SVR4_PIC mode. It is for Irix | |
7942 | compatibility. */ | |
7943 | case OPTION_XGOT: | |
7944 | mips_big_got = 1; | |
7945 | break; | |
7946 | ||
f3d817d8 | 7947 | case 'G': |
1dc1e798 KR |
7948 | if (! USE_GLOBAL_POINTER_OPT) |
7949 | { | |
7950 | as_bad ("-G is not supported for this configuration"); | |
7951 | return 0; | |
7952 | } | |
7953 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 7954 | { |
f3d817d8 DM |
7955 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
7956 | return 0; | |
670a50eb ILT |
7957 | } |
7958 | else | |
f3d817d8 | 7959 | g_switch_value = atoi (arg); |
42562568 | 7960 | g_switch_seen = 1; |
f3d817d8 | 7961 | break; |
4e95866e | 7962 | |
7f9880e5 ILT |
7963 | /* The -32 and -64 options tell the assembler to output the 32 |
7964 | bit or the 64 bit MIPS ELF format. */ | |
7965 | case OPTION_32: | |
7966 | mips_64 = 0; | |
7967 | break; | |
7968 | ||
7969 | case OPTION_64: | |
9c44af60 ILT |
7970 | { |
7971 | const char **list, **l; | |
7972 | ||
7973 | list = bfd_target_list (); | |
7974 | for (l = list; *l != NULL; l++) | |
7975 | if (strcmp (*l, "elf64-bigmips") == 0 | |
7976 | || strcmp (*l, "elf64-littlemips") == 0) | |
7977 | break; | |
7978 | if (*l == NULL) | |
7979 | as_fatal ("No compiled in support for 64 bit object file format"); | |
7980 | free (list); | |
7981 | mips_64 = 1; | |
7982 | } | |
7f9880e5 ILT |
7983 | break; |
7984 | ||
f3d817d8 DM |
7985 | default: |
7986 | return 0; | |
8ea7f4e8 ILT |
7987 | } |
7988 | ||
f3d817d8 | 7989 | return 1; |
8ea7f4e8 ILT |
7990 | } |
7991 | ||
f3d817d8 DM |
7992 | void |
7993 | md_show_usage (stream) | |
7994 | FILE *stream; | |
7995 | { | |
7996 | fprintf(stream, "\ | |
7997 | MIPS options:\n\ | |
7998 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
7999 | -EB generate big endian output\n\ |
8000 | -EL generate little endian output\n\ | |
8001 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8002 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8003 | implicitly with the gp register [default 8]\n"); |
8004 | fprintf(stream, "\ | |
f3d817d8 DM |
8005 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8006 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8007 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8008 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8009 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8010 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8011 | -m4650 permit R4650 instructions\n\ |
8012 | -no-m4650 do not permit R4650 instructions\n\ | |
8013 | -m4010 permit R4010 instructions\n\ | |
8014 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8015 | -m4100 permit VR4100 instructions\n\ |
8016 | -no-m4100 do not permit VR4100 instructions\n"); | |
8017 | fprintf(stream, "\ | |
cc5703cd ILT |
8018 | -mips16 generate mips16 instructions\n\ |
8019 | -no-mips16 do not generate mips16 instructions\n"); | |
8020 | fprintf(stream, "\ | |
f3d817d8 DM |
8021 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8022 | -O remove unneeded NOPs and swap branches\n\ | |
8023 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8024 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8025 | #ifdef OBJ_ELF | |
8026 | fprintf(stream, "\ | |
8027 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8028 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8029 | -xgot assume a 32 bit GOT\n\ |
8030 | -32 create 32 bit object file (default)\n\ | |
8031 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8032 | #endif |
8033 | } | |
8034 | \f | |
3d3c5039 ILT |
8035 | long |
8036 | md_pcrel_from (fixP) | |
8037 | fixS *fixP; | |
8038 | { | |
1dc1e798 KR |
8039 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8040 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8041 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8042 | { | |
8043 | /* This makes a branch to an undefined symbol be a branch to the | |
8044 | current location. */ | |
8045 | return 4; | |
8046 | } | |
5b63f465 | 8047 | |
670a50eb ILT |
8048 | /* return the address of the delay slot */ |
8049 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8050 | } |
8051 | ||
abdad6bc ILT |
8052 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8053 | reloc for a cons. We could use the definition there, except that | |
8054 | we want to handle 64 bit relocs specially. */ | |
8055 | ||
8056 | void | |
8057 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8058 | fragS *frag; | |
8059 | int where; | |
8060 | unsigned int nbytes; | |
8061 | expressionS *exp; | |
8062 | { | |
bf39474f | 8063 | #ifndef OBJ_ELF |
abdad6bc | 8064 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8065 | 4 byte reloc. */ |
8066 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8067 | { |
b9129c6f | 8068 | if (target_big_endian) |
abdad6bc ILT |
8069 | where += 4; |
8070 | nbytes = 4; | |
8071 | } | |
bf39474f | 8072 | #endif |
abdad6bc | 8073 | |
7f9880e5 | 8074 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8075 | as_bad ("Unsupported reloc size %d", nbytes); |
8076 | ||
8077 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8078 | (nbytes == 2 |
8079 | ? BFD_RELOC_16 | |
8080 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8081 | } |
8082 | ||
867a58b3 ILT |
8083 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8084 | the corresponding LO reloc. This is called before md_apply_fix and | |
8085 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8086 | explicit use of the %hi modifier. */ | |
8087 | ||
8088 | void | |
8089 | mips_frob_file () | |
8090 | { | |
8091 | struct mips_hi_fixup *l; | |
8092 | ||
8093 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8094 | { | |
8095 | segment_info_type *seginfo; | |
9b61d62b | 8096 | int pass; |
867a58b3 ILT |
8097 | |
8098 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8099 | ||
8100 | /* Check quickly whether the next fixup happens to be a matching | |
8101 | %lo. */ | |
8102 | if (l->fixp->fx_next != NULL | |
8103 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8104 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8105 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8106 | continue; | |
8107 | ||
8108 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8109 | When we find one, move the %hi just in front of it. We do |
8110 | this in two passes. In the first pass, we try to find a | |
8111 | unique %lo. In the second pass, we permit multiple %hi | |
8112 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8113 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8114 | for (pass = 0; pass < 2; pass++) |
8115 | { | |
8116 | fixS *f, *prev; | |
8117 | ||
8118 | prev = NULL; | |
8119 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8120 | { |
9b61d62b ILT |
8121 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8122 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8123 | && f->fx_addsy == l->fixp->fx_addsy | |
8124 | && f->fx_offset == l->fixp->fx_offset | |
8125 | && (pass == 1 | |
8126 | || prev == NULL | |
8127 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8128 | || prev->fx_addsy != f->fx_addsy | |
8129 | || prev->fx_offset != f->fx_offset)) | |
8130 | { | |
8131 | fixS **pf; | |
867a58b3 | 8132 | |
9b61d62b ILT |
8133 | /* Move l->fixp before f. */ |
8134 | for (pf = &seginfo->fix_root; | |
8135 | *pf != l->fixp; | |
8136 | pf = &(*pf)->fx_next) | |
8137 | assert (*pf != NULL); | |
867a58b3 | 8138 | |
9b61d62b | 8139 | *pf = l->fixp->fx_next; |
867a58b3 | 8140 | |
9b61d62b ILT |
8141 | l->fixp->fx_next = f; |
8142 | if (prev == NULL) | |
8143 | seginfo->fix_root = l->fixp; | |
8144 | else | |
8145 | prev->fx_next = l->fixp; | |
867a58b3 | 8146 | |
9b61d62b ILT |
8147 | break; |
8148 | } | |
8149 | ||
8150 | prev = f; | |
867a58b3 ILT |
8151 | } |
8152 | ||
9b61d62b ILT |
8153 | if (f != NULL) |
8154 | break; | |
867a58b3 | 8155 | |
9b61d62b ILT |
8156 | if (pass == 1) |
8157 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8158 | "Unmatched %%hi reloc"); | |
8159 | } | |
867a58b3 ILT |
8160 | } |
8161 | } | |
8162 | ||
1c803e52 ILT |
8163 | /* When generating embedded PIC code we need to use a special |
8164 | relocation to represent the difference of two symbols in the .text | |
8165 | section (switch tables use a difference of this sort). See | |
8166 | include/coff/mips.h for details. This macro checks whether this | |
8167 | fixup requires the special reloc. */ | |
8168 | #define SWITCH_TABLE(fixp) \ | |
8169 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8170 | && (fixp)->fx_addsy != NULL \ | |
8171 | && (fixp)->fx_subsy != NULL \ | |
8172 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8173 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8174 | ||
5b63f465 | 8175 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8176 | relocations, in case the linker has to relax a call. We also need |
8177 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8178 | |
8179 | /*ARGSUSED*/ | |
8180 | int | |
8181 | mips_force_relocation (fixp) | |
8182 | fixS *fixp; | |
8183 | { | |
1c803e52 | 8184 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8185 | && (fixp->fx_pcrel |
8186 | || SWITCH_TABLE (fixp) | |
8187 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8188 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8189 | } |
8190 | ||
8191 | /* Apply a fixup to the object file. */ | |
8192 | ||
3d3c5039 ILT |
8193 | int |
8194 | md_apply_fix (fixP, valueP) | |
8195 | fixS *fixP; | |
918692a5 | 8196 | valueT *valueP; |
3d3c5039 | 8197 | { |
670a50eb ILT |
8198 | unsigned char *buf; |
8199 | long insn, value; | |
3d3c5039 | 8200 | |
bf39474f ILT |
8201 | assert (fixP->fx_size == 4 |
8202 | || fixP->fx_r_type == BFD_RELOC_16 | |
8203 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8204 | |
670a50eb ILT |
8205 | value = *valueP; |
8206 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 8207 | |
5b63f465 ILT |
8208 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8209 | fixP->fx_done = 1; | |
8210 | ||
670a50eb ILT |
8211 | switch (fixP->fx_r_type) |
8212 | { | |
3d3c5039 ILT |
8213 | case BFD_RELOC_MIPS_JMP: |
8214 | case BFD_RELOC_HI16: | |
8215 | case BFD_RELOC_HI16_S: | |
670a50eb | 8216 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8217 | case BFD_RELOC_MIPS_LITERAL: |
8218 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8219 | case BFD_RELOC_MIPS_GOT16: |
8220 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8221 | case BFD_RELOC_MIPS_GOT_HI16: |
8222 | case BFD_RELOC_MIPS_GOT_LO16: | |
8223 | case BFD_RELOC_MIPS_CALL_HI16: | |
8224 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 8225 | if (fixP->fx_pcrel) |
7b777690 ILT |
8226 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8227 | "Invalid PC relative reloc"); | |
670a50eb | 8228 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8229 | break; |
3d3c5039 | 8230 | |
cc5703cd ILT |
8231 | case BFD_RELOC_MIPS16_JMP: |
8232 | /* We currently always generate a reloc against a symbol, which | |
8233 | means that we don't want an addend even if the symbol is | |
8234 | defined. */ | |
8235 | fixP->fx_addnumber = 0; | |
8236 | break; | |
8237 | ||
ecd4ca1c ILT |
8238 | case BFD_RELOC_PCREL_HI16_S: |
8239 | /* The addend for this is tricky if it is internal, so we just | |
8240 | do everything here rather than in bfd_perform_relocation. */ | |
8241 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8242 | { | |
8243 | /* For an external symbol adjust by the address to make it | |
8244 | pcrel_offset. We use the address of the RELLO reloc | |
8245 | which follows this one. */ | |
8246 | value += (fixP->fx_next->fx_frag->fr_address | |
8247 | + fixP->fx_next->fx_where); | |
8248 | } | |
8249 | if (value & 0x8000) | |
8250 | value += 0x10000; | |
8251 | value >>= 16; | |
0221ddf7 | 8252 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8253 | if (target_big_endian) |
ecd4ca1c ILT |
8254 | buf += 2; |
8255 | md_number_to_chars (buf, value, 2); | |
8256 | break; | |
8257 | ||
8258 | case BFD_RELOC_PCREL_LO16: | |
8259 | /* The addend for this is tricky if it is internal, so we just | |
8260 | do everything here rather than in bfd_perform_relocation. */ | |
8261 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8262 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8263 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8264 | if (target_big_endian) |
ecd4ca1c ILT |
8265 | buf += 2; |
8266 | md_number_to_chars (buf, value, 2); | |
8267 | break; | |
8268 | ||
bf39474f ILT |
8269 | case BFD_RELOC_64: |
8270 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8271 | extended value if we are only 32 bits. */ | |
8272 | if (fixP->fx_done | |
8273 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8274 | { | |
8275 | if (8 <= sizeof (valueT)) | |
8276 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8277 | value, 8); | |
8278 | else | |
8279 | { | |
8280 | long w1, w2; | |
8281 | long hiv; | |
8282 | ||
8283 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8284 | if (target_big_endian) |
bf39474f ILT |
8285 | w1 += 4; |
8286 | else | |
8287 | w2 += 4; | |
8288 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8289 | if ((value & 0x80000000) != 0) | |
8290 | hiv = 0xffffffff; | |
8291 | else | |
8292 | hiv = 0; | |
8293 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8294 | } | |
8295 | } | |
8296 | break; | |
8297 | ||
f3645945 ILT |
8298 | case BFD_RELOC_32: |
8299 | /* If we are deleting this reloc entry, we must fill in the | |
8300 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8301 | resolved when it appears but is later defined. We also need |
8302 | to fill in the value if this is an embedded PIC switch table | |
8303 | entry. */ | |
8304 | if (fixP->fx_done | |
8305 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8306 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8307 | value, 4); | |
8308 | break; | |
8309 | ||
49ad0c4c ILT |
8310 | case BFD_RELOC_16: |
8311 | /* If we are deleting this reloc entry, we must fill in the | |
8312 | value now. */ | |
8313 | assert (fixP->fx_size == 2); | |
8314 | if (fixP->fx_done) | |
8315 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8316 | value, 2); | |
8317 | break; | |
8318 | ||
f3645945 ILT |
8319 | case BFD_RELOC_LO16: |
8320 | /* When handling an embedded PIC switch statement, we can wind | |
8321 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8322 | if (fixP->fx_done) | |
8323 | { | |
8324 | if (value < -0x8000 || value > 0x7fff) | |
8325 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8326 | "relocation overflow"); | |
0221ddf7 | 8327 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8328 | if (target_big_endian) |
f3645945 ILT |
8329 | buf += 2; |
8330 | md_number_to_chars (buf, value, 2); | |
8331 | } | |
8332 | break; | |
8333 | ||
3d3c5039 | 8334 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8335 | /* |
8336 | * We need to save the bits in the instruction since fixup_segment() | |
8337 | * might be deleting the relocation entry (i.e., a branch within | |
8338 | * the current segment). | |
8339 | */ | |
fbcfacb7 | 8340 | if ((value & 0x3) != 0) |
7b777690 ILT |
8341 | as_warn_where (fixP->fx_file, fixP->fx_line, |
8342 | "Branch to odd address (%lx)", value); | |
670a50eb | 8343 | value >>= 2; |
670a50eb ILT |
8344 | |
8345 | /* update old instruction data */ | |
8346 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8347 | if (target_big_endian) |
8348 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8349 | else | |
8350 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8351 | |
8352 | if (value >= -0x8000 && value < 0x8000) | |
8353 | insn |= value & 0xffff; | |
8354 | else | |
8355 | { | |
8356 | /* The branch offset is too large. If this is an | |
8357 | unconditional branch, and we are not generating PIC code, | |
8358 | we can convert it to an absolute jump instruction. */ | |
8359 | if (mips_pic == NO_PIC | |
8360 | && fixP->fx_done | |
8361 | && fixP->fx_frag->fr_address >= text_section->vma | |
8362 | && (fixP->fx_frag->fr_address | |
8363 | < text_section->vma + text_section->_raw_size) | |
8364 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8365 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8366 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8367 | { | |
8368 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8369 | insn = 0x0c000000; /* jal */ | |
8370 | else | |
8371 | insn = 0x08000000; /* j */ | |
8372 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8373 | fixP->fx_done = 0; | |
8374 | fixP->fx_addsy = section_symbol (text_section); | |
8375 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8376 | } | |
8377 | else | |
8378 | { | |
8379 | /* FIXME. It would be possible in principle to handle | |
8380 | conditional branches which overflow. They could be | |
8381 | transformed into a branch around a jump. This would | |
8382 | require setting up variant frags for each different | |
8383 | branch type. The native MIPS assembler attempts to | |
8384 | handle these cases, but it appears to do it | |
8385 | incorrectly. */ | |
8386 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8387 | "Relocation overflow"); | |
8388 | } | |
8389 | } | |
8390 | ||
604633ae | 8391 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8392 | break; |
3d3c5039 ILT |
8393 | |
8394 | default: | |
670a50eb | 8395 | internalError (); |
3d3c5039 | 8396 | } |
5b63f465 | 8397 | |
670a50eb | 8398 | return 1; |
3d3c5039 ILT |
8399 | } |
8400 | ||
8401 | #if 0 | |
8402 | void | |
670a50eb ILT |
8403 | printInsn (oc) |
8404 | unsigned long oc; | |
3d3c5039 | 8405 | { |
670a50eb ILT |
8406 | const struct mips_opcode *p; |
8407 | int treg, sreg, dreg, shamt; | |
8408 | short imm; | |
8409 | const char *args; | |
8410 | int i; | |
3d3c5039 | 8411 | |
670a50eb ILT |
8412 | for (i = 0; i < NUMOPCODES; ++i) |
8413 | { | |
8414 | p = &mips_opcodes[i]; | |
8415 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8416 | { | |
8417 | printf ("%08lx %s\t", oc, p->name); | |
8418 | treg = (oc >> 16) & 0x1f; | |
8419 | sreg = (oc >> 21) & 0x1f; | |
8420 | dreg = (oc >> 11) & 0x1f; | |
8421 | shamt = (oc >> 6) & 0x1f; | |
8422 | imm = oc; | |
8423 | for (args = p->args;; ++args) | |
8424 | { | |
8425 | switch (*args) | |
8426 | { | |
3d3c5039 | 8427 | case '\0': |
670a50eb ILT |
8428 | printf ("\n"); |
8429 | break; | |
3d3c5039 ILT |
8430 | |
8431 | case ',': | |
8432 | case '(': | |
8433 | case ')': | |
670a50eb ILT |
8434 | printf ("%c", *args); |
8435 | continue; | |
3d3c5039 ILT |
8436 | |
8437 | case 'r': | |
670a50eb ILT |
8438 | assert (treg == sreg); |
8439 | printf ("$%d,$%d", treg, sreg); | |
8440 | continue; | |
3d3c5039 ILT |
8441 | |
8442 | case 'd': | |
918692a5 | 8443 | case 'G': |
670a50eb ILT |
8444 | printf ("$%d", dreg); |
8445 | continue; | |
3d3c5039 ILT |
8446 | |
8447 | case 't': | |
918692a5 | 8448 | case 'E': |
670a50eb ILT |
8449 | printf ("$%d", treg); |
8450 | continue; | |
3d3c5039 | 8451 | |
9226253a ILT |
8452 | case 'k': |
8453 | printf ("0x%x", treg); | |
8454 | continue; | |
8455 | ||
3d3c5039 ILT |
8456 | case 'b': |
8457 | case 's': | |
670a50eb ILT |
8458 | printf ("$%d", sreg); |
8459 | continue; | |
3d3c5039 ILT |
8460 | |
8461 | case 'a': | |
670a50eb ILT |
8462 | printf ("0x%08lx", oc & 0x1ffffff); |
8463 | continue; | |
3d3c5039 ILT |
8464 | |
8465 | case 'i': | |
8466 | case 'j': | |
8467 | case 'o': | |
8468 | case 'u': | |
670a50eb ILT |
8469 | printf ("%d", imm); |
8470 | continue; | |
3d3c5039 ILT |
8471 | |
8472 | case '<': | |
56c96faa | 8473 | case '>': |
670a50eb ILT |
8474 | printf ("$%d", shamt); |
8475 | continue; | |
3d3c5039 ILT |
8476 | |
8477 | default: | |
670a50eb | 8478 | internalError (); |
3d3c5039 | 8479 | } |
670a50eb | 8480 | break; |
3d3c5039 | 8481 | } |
670a50eb | 8482 | return; |
3d3c5039 ILT |
8483 | } |
8484 | } | |
670a50eb | 8485 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8486 | } |
8487 | #endif | |
8488 | ||
8489 | static symbolS * | |
8490 | get_symbol () | |
8491 | { | |
670a50eb ILT |
8492 | int c; |
8493 | char *name; | |
8494 | symbolS *p; | |
8495 | ||
8496 | name = input_line_pointer; | |
8497 | c = get_symbol_end (); | |
8498 | p = (symbolS *) symbol_find_or_make (name); | |
8499 | *input_line_pointer = c; | |
8500 | return p; | |
3d3c5039 ILT |
8501 | } |
8502 | ||
becfe05e ILT |
8503 | /* Align the current frag to a given power of two. The MIPS assembler |
8504 | also automatically adjusts any preceding label. */ | |
8505 | ||
8506 | static void | |
23dc1ae3 | 8507 | mips_align (to, fill, label) |
becfe05e ILT |
8508 | int to; |
8509 | int fill; | |
23dc1ae3 | 8510 | symbolS *label; |
becfe05e | 8511 | { |
fbcfacb7 | 8512 | mips_emit_delays (false); |
becfe05e ILT |
8513 | frag_align (to, fill); |
8514 | record_alignment (now_seg, to); | |
23dc1ae3 | 8515 | if (label != NULL) |
becfe05e | 8516 | { |
23dc1ae3 ILT |
8517 | assert (S_GET_SEGMENT (label) == now_seg); |
8518 | label->sy_frag = frag_now; | |
8519 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8520 | } |
8521 | } | |
8522 | ||
8523 | /* Align to a given power of two. .align 0 turns off the automatic | |
8524 | alignment used by the data creating pseudo-ops. */ | |
8525 | ||
3d3c5039 ILT |
8526 | static void |
8527 | s_align (x) | |
8528 | int x; | |
8529 | { | |
670a50eb ILT |
8530 | register int temp; |
8531 | register long temp_fill; | |
8532 | long max_alignment = 15; | |
3d3c5039 | 8533 | |
670a50eb | 8534 | /* |
3d3c5039 ILT |
8535 | |
8536 | o Note that the assembler pulls down any immediately preceeding label | |
8537 | to the aligned address. | |
8538 | o It's not documented but auto alignment is reinstated by | |
8539 | a .align pseudo instruction. | |
8540 | o Note also that after auto alignment is turned off the mips assembler | |
8541 | issues an error on attempt to assemble an improperly aligned data item. | |
8542 | We don't. | |
8543 | ||
8544 | */ | |
8545 | ||
670a50eb ILT |
8546 | temp = get_absolute_expression (); |
8547 | if (temp > max_alignment) | |
8548 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8549 | else if (temp < 0) | |
8550 | { | |
8551 | as_warn ("Alignment negative: 0 assumed."); | |
8552 | temp = 0; | |
8553 | } | |
8554 | if (*input_line_pointer == ',') | |
8555 | { | |
8556 | input_line_pointer++; | |
8557 | temp_fill = get_absolute_expression (); | |
8558 | } | |
8559 | else | |
8560 | temp_fill = 0; | |
8561 | if (temp) | |
8562 | { | |
8563 | auto_align = 1; | |
fbcfacb7 ILT |
8564 | mips_align (temp, (int) temp_fill, |
8565 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8566 | } |
670a50eb ILT |
8567 | else |
8568 | { | |
8569 | auto_align = 0; | |
3d3c5039 ILT |
8570 | } |
8571 | ||
670a50eb | 8572 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8573 | } |
8574 | ||
739708fa KR |
8575 | void |
8576 | mips_flush_pending_output () | |
becfe05e | 8577 | { |
fbcfacb7 ILT |
8578 | mips_emit_delays (false); |
8579 | mips_clear_insn_labels (); | |
becfe05e ILT |
8580 | } |
8581 | ||
3d3c5039 ILT |
8582 | static void |
8583 | s_change_sec (sec) | |
8584 | int sec; | |
8585 | { | |
88225433 | 8586 | segT seg; |
becfe05e | 8587 | |
5b63f465 ILT |
8588 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8589 | .sdata and .sbss sections. We change the .data and .rdata | |
8590 | pseudo-ops to use .sdata. */ | |
8591 | if (mips_pic == EMBEDDED_PIC | |
8592 | && (sec == 'd' || sec == 'r')) | |
8593 | sec = 's'; | |
8594 | ||
fbcfacb7 | 8595 | mips_emit_delays (false); |
670a50eb ILT |
8596 | switch (sec) |
8597 | { | |
3d3c5039 | 8598 | case 't': |
604633ae | 8599 | s_text (0); |
670a50eb | 8600 | break; |
3d3c5039 | 8601 | case 'd': |
604633ae | 8602 | s_data (0); |
670a50eb | 8603 | break; |
3d3c5039 | 8604 | case 'b': |
670a50eb | 8605 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8606 | demand_empty_rest_of_line (); |
8607 | break; | |
88225433 ILT |
8608 | |
8609 | case 'r': | |
1dc1e798 KR |
8610 | if (USE_GLOBAL_POINTER_OPT) |
8611 | { | |
8612 | seg = subseg_new (RDATA_SECTION_NAME, | |
8613 | (subsegT) get_absolute_expression ()); | |
8614 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8615 | { | |
8616 | bfd_set_section_flags (stdoutput, seg, | |
8617 | (SEC_ALLOC | |
8618 | | SEC_LOAD | |
8619 | | SEC_READONLY | |
8620 | | SEC_RELOC | |
8621 | | SEC_DATA)); | |
08e17202 ILT |
8622 | if (strcmp (TARGET_OS, "elf") != 0) |
8623 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8624 | } |
8625 | demand_empty_rest_of_line (); | |
8626 | } | |
8627 | else | |
8628 | { | |
8629 | as_bad ("No read only data section in this object file format"); | |
8630 | demand_empty_rest_of_line (); | |
8631 | return; | |
8632 | } | |
88225433 | 8633 | break; |
88225433 ILT |
8634 | |
8635 | case 's': | |
1dc1e798 KR |
8636 | if (USE_GLOBAL_POINTER_OPT) |
8637 | { | |
8638 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8639 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8640 | { | |
8641 | bfd_set_section_flags (stdoutput, seg, | |
8642 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8643 | | SEC_DATA); | |
08e17202 ILT |
8644 | if (strcmp (TARGET_OS, "elf") != 0) |
8645 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8646 | } |
8647 | demand_empty_rest_of_line (); | |
8648 | break; | |
8649 | } | |
8650 | else | |
8651 | { | |
8652 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8653 | demand_empty_rest_of_line (); | |
8654 | return; | |
8655 | } | |
3d3c5039 | 8656 | } |
88225433 | 8657 | |
670a50eb | 8658 | auto_align = 1; |
3d3c5039 ILT |
8659 | } |
8660 | ||
739708fa KR |
8661 | void |
8662 | mips_enable_auto_align () | |
9da4c5d1 | 8663 | { |
9da4c5d1 ILT |
8664 | auto_align = 1; |
8665 | } | |
8666 | ||
3d3c5039 ILT |
8667 | static void |
8668 | s_cons (log_size) | |
8669 | int log_size; | |
8670 | { | |
23dc1ae3 ILT |
8671 | symbolS *label; |
8672 | ||
fbcfacb7 ILT |
8673 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8674 | mips_emit_delays (false); | |
670a50eb | 8675 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8676 | mips_align (log_size, 0, label); |
fbcfacb7 | 8677 | mips_clear_insn_labels (); |
670a50eb | 8678 | cons (1 << log_size); |
3d3c5039 ILT |
8679 | } |
8680 | ||
3d3c5039 | 8681 | static void |
becfe05e ILT |
8682 | s_float_cons (type) |
8683 | int type; | |
3d3c5039 | 8684 | { |
23dc1ae3 ILT |
8685 | symbolS *label; |
8686 | ||
fbcfacb7 | 8687 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8688 | |
fbcfacb7 | 8689 | mips_emit_delays (false); |
670a50eb ILT |
8690 | |
8691 | if (auto_align) | |
becfe05e | 8692 | if (type == 'd') |
23dc1ae3 | 8693 | mips_align (3, 0, label); |
670a50eb | 8694 | else |
23dc1ae3 | 8695 | mips_align (2, 0, label); |
670a50eb | 8696 | |
fbcfacb7 | 8697 | mips_clear_insn_labels (); |
1849d646 | 8698 | |
becfe05e | 8699 | float_cons (type); |
3d3c5039 ILT |
8700 | } |
8701 | ||
c1444ec4 ILT |
8702 | /* Handle .globl. We need to override it because on Irix 5 you are |
8703 | permitted to say | |
8704 | .globl foo .text | |
8705 | where foo is an undefined symbol, to mean that foo should be | |
8706 | considered to be the address of a function. */ | |
8707 | ||
8708 | static void | |
8709 | s_mips_globl (x) | |
8710 | int x; | |
8711 | { | |
8712 | char *name; | |
8713 | int c; | |
8714 | symbolS *symbolP; | |
fb251650 | 8715 | flagword flag; |
c1444ec4 ILT |
8716 | |
8717 | name = input_line_pointer; | |
8718 | c = get_symbol_end (); | |
8719 | symbolP = symbol_find_or_make (name); | |
8720 | *input_line_pointer = c; | |
8721 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8722 | |
8723 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8724 | being a function is apparently labelled as being an object. */ | |
8725 | flag = BSF_OBJECT; | |
8726 | ||
c1444ec4 ILT |
8727 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8728 | { | |
8729 | char *secname; | |
8730 | asection *sec; | |
8731 | ||
8732 | secname = input_line_pointer; | |
8733 | c = get_symbol_end (); | |
8734 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8735 | if (sec == NULL) | |
8736 | as_bad ("%s: no such section", secname); | |
8737 | *input_line_pointer = c; | |
8738 | ||
8739 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8740 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8741 | } |
8742 | ||
fb251650 ILT |
8743 | symbolP->bsym->flags |= flag; |
8744 | ||
c1444ec4 ILT |
8745 | S_SET_EXTERNAL (symbolP); |
8746 | demand_empty_rest_of_line (); | |
8747 | } | |
8748 | ||
3d3c5039 ILT |
8749 | static void |
8750 | s_option (x) | |
8751 | int x; | |
8752 | { | |
dd3f1f76 ILT |
8753 | char *opt; |
8754 | char c; | |
8755 | ||
8756 | opt = input_line_pointer; | |
8757 | c = get_symbol_end (); | |
8758 | ||
dd3f1f76 | 8759 | if (*opt == 'O') |
9226253a ILT |
8760 | { |
8761 | /* FIXME: What does this mean? */ | |
8762 | } | |
dd3f1f76 | 8763 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8764 | { |
d9aba805 | 8765 | int i; |
42562568 | 8766 | |
d9aba805 ILT |
8767 | i = atoi (opt + 3); |
8768 | if (i == 0) | |
8769 | mips_pic = NO_PIC; | |
8770 | else if (i == 2) | |
8771 | mips_pic = SVR4_PIC; | |
8772 | else | |
8773 | as_bad (".option pic%d not supported", i); | |
8774 | ||
1dc1e798 | 8775 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8776 | { |
8777 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8778 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8779 | g_switch_value = 0; |
8780 | bfd_set_gp_size (stdoutput, 0); | |
8781 | } | |
9226253a | 8782 | } |
dd3f1f76 ILT |
8783 | else |
8784 | as_warn ("Unrecognized option \"%s\"", opt); | |
8785 | ||
8786 | *input_line_pointer = c; | |
670a50eb | 8787 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8788 | } |
8789 | ||
8790 | static void | |
8791 | s_mipsset (x) | |
8792 | int x; | |
8793 | { | |
670a50eb ILT |
8794 | char *name = input_line_pointer, ch; |
8795 | ||
8796 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8797 | input_line_pointer++; | |
8798 | ch = *input_line_pointer; | |
8799 | *input_line_pointer = '\0'; | |
8800 | ||
8801 | if (strcmp (name, "reorder") == 0) | |
8802 | { | |
4e95866e ILT |
8803 | if (mips_noreorder) |
8804 | { | |
8805 | prev_insn_unreordered = 1; | |
8806 | prev_prev_insn_unreordered = 1; | |
8807 | } | |
670a50eb ILT |
8808 | mips_noreorder = 0; |
8809 | } | |
8810 | else if (strcmp (name, "noreorder") == 0) | |
8811 | { | |
fbcfacb7 | 8812 | mips_emit_delays (true); |
670a50eb | 8813 | mips_noreorder = 1; |
0dd2d296 | 8814 | mips_any_noreorder = 1; |
670a50eb ILT |
8815 | } |
8816 | else if (strcmp (name, "at") == 0) | |
8817 | { | |
8818 | mips_noat = 0; | |
8819 | } | |
8820 | else if (strcmp (name, "noat") == 0) | |
8821 | { | |
8822 | mips_noat = 1; | |
3d3c5039 | 8823 | } |
670a50eb ILT |
8824 | else if (strcmp (name, "macro") == 0) |
8825 | { | |
8826 | mips_warn_about_macros = 0; | |
8827 | } | |
8828 | else if (strcmp (name, "nomacro") == 0) | |
8829 | { | |
8830 | if (mips_noreorder == 0) | |
8831 | as_bad ("`noreorder' must be set before `nomacro'"); | |
8832 | mips_warn_about_macros = 1; | |
8833 | } | |
8834 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
8835 | { | |
8836 | mips_nomove = 0; | |
8837 | } | |
8838 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
8839 | { | |
8840 | mips_nomove = 1; | |
8841 | } | |
8842 | else if (strcmp (name, "bopt") == 0) | |
8843 | { | |
8844 | mips_nobopt = 0; | |
8845 | } | |
8846 | else if (strcmp (name, "nobopt") == 0) | |
8847 | { | |
8848 | mips_nobopt = 1; | |
8849 | } | |
943321c0 ILT |
8850 | else if (strcmp (name, "mips16") == 0 |
8851 | || strcmp (name, "MIPS-16") == 0) | |
8852 | mips16 = 1; | |
8853 | else if (strcmp (name, "nomips16") == 0 | |
8854 | || strcmp (name, "noMIPS-16") == 0) | |
8855 | mips16 = 0; | |
1051c97f ILT |
8856 | else if (strncmp (name, "mips", 4) == 0) |
8857 | { | |
8858 | int isa; | |
8859 | ||
8860 | /* Permit the user to change the ISA on the fly. Needless to | |
8861 | say, misuse can cause serious problems. */ | |
8862 | isa = atoi (name + 4); | |
8863 | if (isa == 0) | |
8864 | mips_isa = file_mips_isa; | |
d8a1c247 | 8865 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
8866 | as_bad ("unknown ISA level"); |
8867 | else | |
8868 | mips_isa = isa; | |
8869 | } | |
cc5703cd ILT |
8870 | else if (strcmp (name, "autoextend") == 0) |
8871 | mips16_autoextend = 1; | |
8872 | else if (strcmp (name, "noautoextend") == 0) | |
8873 | mips16_autoextend = 0; | |
670a50eb ILT |
8874 | else |
8875 | { | |
8876 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
8877 | } | |
8878 | *input_line_pointer = ch; | |
8879 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
8880 | } |
8881 | ||
9226253a ILT |
8882 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
8883 | .option pic2. It means to generate SVR4 PIC calls. */ | |
8884 | ||
8885 | static void | |
8886 | s_abicalls (ignore) | |
8887 | int ignore; | |
8888 | { | |
d9aba805 | 8889 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
8890 | if (USE_GLOBAL_POINTER_OPT) |
8891 | { | |
8892 | if (g_switch_seen && g_switch_value != 0) | |
8893 | as_warn ("-G may not be used with SVR4 PIC code"); | |
8894 | g_switch_value = 0; | |
8895 | } | |
d9aba805 | 8896 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
8897 | demand_empty_rest_of_line (); |
8898 | } | |
8899 | ||
8900 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
8901 | PIC code. It sets the $gp register for the function based on the | |
8902 | function address, which is in the register named in the argument. | |
8903 | This uses a relocation against _gp_disp, which is handled specially | |
8904 | by the linker. The result is: | |
8905 | lui $gp,%hi(_gp_disp) | |
8906 | addiu $gp,$gp,%lo(_gp_disp) | |
8907 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 8908 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
8909 | |
8910 | static void | |
8911 | s_cpload (ignore) | |
8912 | int ignore; | |
8913 | { | |
8914 | expressionS ex; | |
8915 | int icnt = 0; | |
8916 | ||
d9aba805 ILT |
8917 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
8918 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8919 | { |
8920 | s_ignore (0); | |
8921 | return; | |
8922 | } | |
8923 | ||
8924 | /* .cpload should be a in .set noreorder section. */ | |
8925 | if (mips_noreorder == 0) | |
8926 | as_warn (".cpload not in noreorder section"); | |
8927 | ||
9226253a ILT |
8928 | ex.X_op = O_symbol; |
8929 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
8930 | ex.X_op_symbol = NULL; | |
8931 | ex.X_add_number = 0; | |
8932 | ||
fb251650 ILT |
8933 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
8934 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
8935 | ||
0dd2d296 ILT |
8936 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
8937 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
8938 | (int) BFD_RELOC_LO16); |
8939 | ||
0dd2d296 ILT |
8940 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
8941 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
8942 | |
8943 | demand_empty_rest_of_line (); | |
8944 | } | |
8945 | ||
8946 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
8947 | offset from $sp. The offset is remembered, and after making a PIC | |
8948 | call $gp is restored from that location. */ | |
8949 | ||
8950 | static void | |
8951 | s_cprestore (ignore) | |
8952 | int ignore; | |
8953 | { | |
8954 | expressionS ex; | |
8955 | int icnt = 0; | |
8956 | ||
d9aba805 ILT |
8957 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
8958 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8959 | { |
8960 | s_ignore (0); | |
8961 | return; | |
8962 | } | |
8963 | ||
9226253a ILT |
8964 | mips_cprestore_offset = get_absolute_expression (); |
8965 | ||
8966 | ex.X_op = O_constant; | |
8967 | ex.X_add_symbol = NULL; | |
8968 | ex.X_op_symbol = NULL; | |
8969 | ex.X_add_number = mips_cprestore_offset; | |
8970 | ||
0dd2d296 | 8971 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
8972 | mips_isa < 3 ? "sw" : "sd", |
8973 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
8974 | ||
8975 | demand_empty_rest_of_line (); | |
8976 | } | |
8977 | ||
0dd2d296 ILT |
8978 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
8979 | code. It generates a 32 bit GP relative reloc. */ | |
8980 | ||
8981 | static void | |
8982 | s_gpword (ignore) | |
8983 | int ignore; | |
8984 | { | |
23dc1ae3 | 8985 | symbolS *label; |
0dd2d296 ILT |
8986 | expressionS ex; |
8987 | char *p; | |
8988 | ||
8989 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 8990 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
8991 | { |
8992 | s_cons (2); | |
8993 | return; | |
8994 | } | |
8995 | ||
fbcfacb7 ILT |
8996 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8997 | mips_emit_delays (true); | |
0dd2d296 | 8998 | if (auto_align) |
23dc1ae3 | 8999 | mips_align (2, 0, label); |
fbcfacb7 | 9000 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9001 | |
9002 | expression (&ex); | |
9003 | ||
9004 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9005 | { | |
9006 | as_bad ("Unsupported use of .gpword"); | |
9007 | ignore_rest_of_line (); | |
9008 | } | |
9009 | ||
9010 | p = frag_more (4); | |
9011 | md_number_to_chars (p, (valueT) 0, 4); | |
9012 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9013 | BFD_RELOC_MIPS_GPREL32); | |
9014 | ||
9015 | demand_empty_rest_of_line (); | |
9016 | } | |
9017 | ||
9018 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9019 | tables in SVR4 PIC code. */ | |
9020 | ||
9021 | static void | |
9022 | s_cpadd (ignore) | |
9023 | int ignore; | |
9024 | { | |
9025 | int icnt = 0; | |
9026 | int reg; | |
9027 | ||
9028 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9029 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9030 | { |
9031 | s_ignore (0); | |
9032 | return; | |
9033 | } | |
9034 | ||
9035 | /* Add $gp to the register named as an argument. */ | |
9036 | reg = tc_get_register (0); | |
9037 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9038 | mips_isa < 3 ? "addu" : "daddu", | |
9039 | "d,v,t", reg, reg, GP); | |
9040 | ||
9041 | demand_empty_rest_of_line (); | |
9042 | } | |
9043 | ||
9226253a | 9044 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9045 | to parse .frame. The argument is non-zero if this is the frame |
9046 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9047 | |
3d3c5039 | 9048 | int |
0dd2d296 ILT |
9049 | tc_get_register (frame) |
9050 | int frame; | |
3d3c5039 ILT |
9051 | { |
9052 | int reg; | |
9053 | ||
9054 | SKIP_WHITESPACE (); | |
9055 | if (*input_line_pointer++ != '$') | |
9056 | { | |
9057 | as_warn ("expected `$'"); | |
0dd2d296 | 9058 | reg = 0; |
3d3c5039 | 9059 | } |
0dd2d296 | 9060 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9061 | { |
9062 | reg = get_absolute_expression (); | |
9063 | if (reg < 0 || reg >= 32) | |
9064 | { | |
9065 | as_warn ("Bad register number"); | |
9066 | reg = 0; | |
9067 | } | |
9068 | } | |
9069 | else | |
9070 | { | |
9071 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9072 | reg = FP; |
3d3c5039 | 9073 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9074 | reg = SP; |
3d3c5039 | 9075 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9076 | reg = GP; |
3d3c5039 | 9077 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9078 | reg = AT; |
3d3c5039 ILT |
9079 | else |
9080 | { | |
9081 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9082 | reg = 0; |
3d3c5039 ILT |
9083 | } |
9084 | input_line_pointer += 2; | |
9085 | } | |
0dd2d296 ILT |
9086 | if (frame) |
9087 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9088 | return reg; |
9089 | } | |
9090 | ||
0dd2d296 ILT |
9091 | valueT |
9092 | md_section_align (seg, addr) | |
9093 | asection *seg; | |
9094 | valueT addr; | |
9095 | { | |
9096 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9097 | ||
cf32394d ILT |
9098 | #ifdef OBJ_ELF |
9099 | /* We don't need to align ELF sections to the full alignment. | |
9100 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9101 | byte boundary. We don't bother to align the sections if we are |
9102 | targeted for an embedded system. */ | |
9103 | if (strcmp (TARGET_OS, "elf") == 0) | |
9104 | return addr; | |
943321c0 ILT |
9105 | if (align > 4) |
9106 | align = 4; | |
10a14e36 | 9107 | #endif |
cf32394d ILT |
9108 | |
9109 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9110 | } |
9111 | ||
d8a1c247 KR |
9112 | /* Utility routine, called from above as well. If called while the |
9113 | input file is still being read, it's only an approximation. (For | |
9114 | example, a symbol may later become defined which appeared to be | |
9115 | undefined earlier.) */ | |
22ba90ce ILT |
9116 | |
9117 | static int | |
9118 | nopic_need_relax (sym) | |
d8a1c247 KR |
9119 | symbolS *sym; |
9120 | { | |
9121 | if (sym == 0) | |
9122 | return 0; | |
9123 | ||
1dc1e798 KR |
9124 | if (USE_GLOBAL_POINTER_OPT) |
9125 | { | |
9126 | const char *symname; | |
9127 | int change; | |
9128 | ||
9129 | /* Find out whether this symbol can be referenced off the GP | |
9130 | register. It can be if it is smaller than the -G size or if | |
9131 | it is in the .sdata or .sbss section. Certain symbols can | |
9132 | not be referenced off the GP, although it appears as though | |
9133 | they can. */ | |
9134 | symname = S_GET_NAME (sym); | |
9135 | if (symname != (const char *) NULL | |
9136 | && (strcmp (symname, "eprol") == 0 | |
9137 | || strcmp (symname, "etext") == 0 | |
9138 | || strcmp (symname, "_gp") == 0 | |
9139 | || strcmp (symname, "edata") == 0 | |
9140 | || strcmp (symname, "_fbss") == 0 | |
9141 | || strcmp (symname, "_fdata") == 0 | |
9142 | || strcmp (symname, "_ftext") == 0 | |
9143 | || strcmp (symname, "end") == 0 | |
9144 | || strcmp (symname, "_gp_disp") == 0)) | |
9145 | change = 1; | |
9146 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9147 | && (0 |
9148 | #ifndef NO_ECOFF_DEBUGGING | |
9149 | || (sym->ecoff_extern_size != 0 | |
9150 | && sym->ecoff_extern_size <= g_switch_value) | |
9151 | #endif | |
1dc1e798 KR |
9152 | || (S_GET_VALUE (sym) != 0 |
9153 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9154 | change = 0; | |
9155 | else | |
9156 | { | |
9157 | const char *segname; | |
d8a1c247 | 9158 | |
1dc1e798 KR |
9159 | segname = segment_name (S_GET_SEGMENT (sym)); |
9160 | assert (strcmp (segname, ".lit8") != 0 | |
9161 | && strcmp (segname, ".lit4") != 0); | |
9162 | change = (strcmp (segname, ".sdata") != 0 | |
9163 | && strcmp (segname, ".sbss") != 0); | |
9164 | } | |
9165 | return change; | |
9166 | } | |
9167 | else | |
9168 | /* We are not optimizing for the GP register. */ | |
9169 | return 1; | |
d8a1c247 KR |
9170 | } |
9171 | ||
cc5703cd ILT |
9172 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9173 | extended opcode. SEC is the section the frag is in. */ | |
9174 | ||
9175 | static int | |
9176 | mips16_extended_frag (fragp, sec, stretch) | |
9177 | fragS *fragp; | |
9178 | asection *sec; | |
9179 | long stretch; | |
9180 | { | |
9181 | int type; | |
9182 | register const struct mips16_immed_operand *op; | |
9183 | offsetT val; | |
9184 | int mintiny, maxtiny; | |
f74ba7a3 | 9185 | segT symsec; |
cc5703cd | 9186 | |
8728fa92 ILT |
9187 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9188 | return 0; | |
9189 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9190 | return 1; | |
9191 | ||
cc5703cd ILT |
9192 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9193 | op = mips16_immed_operands; | |
9194 | while (op->type != type) | |
9195 | { | |
9196 | ++op; | |
9197 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9198 | } | |
9199 | ||
9200 | if (op->unsp) | |
9201 | { | |
9202 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9203 | { | |
9204 | mintiny = 1; | |
9205 | maxtiny = 1 << op->nbits; | |
9206 | } | |
9207 | else | |
9208 | { | |
9209 | mintiny = 0; | |
9210 | maxtiny = (1 << op->nbits) - 1; | |
9211 | } | |
9212 | } | |
9213 | else | |
9214 | { | |
9215 | mintiny = - (1 << (op->nbits - 1)); | |
9216 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9217 | } | |
9218 | ||
f74ba7a3 ILT |
9219 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9220 | a particular frag address. */ | |
9221 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9222 | { | |
9223 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9224 | + fragp->fr_symbol->sy_frag->fr_address); | |
9225 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9226 | } | |
9227 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9228 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9229 | == O_constant)) | |
9230 | { | |
9231 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9232 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9233 | + fragp->fr_symbol->sy_value.X_add_number | |
9234 | + fragp->fr_symbol->sy_frag->fr_address); | |
9235 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9236 | } | |
9237 | else | |
9238 | return 1; | |
cc5703cd ILT |
9239 | |
9240 | if (op->pcrel) | |
9241 | { | |
9242 | addressT addr; | |
9243 | ||
9244 | /* We won't have the section when we are called from | |
9245 | mips_relax_frag. However, we will always have been called | |
9246 | from md_estimate_size_before_relax first. If this is a | |
9247 | branch to a different section, we mark it as such. If SEC is | |
9248 | NULL, and the frag is not marked, then it must be a branch to | |
9249 | the same section. */ | |
9250 | if (sec == NULL) | |
9251 | { | |
9252 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9253 | return 1; | |
9254 | } | |
9255 | else | |
9256 | { | |
f74ba7a3 | 9257 | if (symsec != sec) |
cc5703cd ILT |
9258 | { |
9259 | fragp->fr_subtype = | |
9260 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9261 | ||
9262 | /* FIXME: We should support this, and let the linker | |
9263 | catch branches and loads that are out of range. */ | |
9264 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9265 | "unsupported PC relative reference to different section"); | |
9266 | ||
9267 | return 1; | |
9268 | } | |
9269 | } | |
9270 | ||
9271 | /* In this case, we know for sure that the symbol fragment is in | |
9272 | the same section. If the fr_address of the symbol fragment | |
9273 | is greater then the address of this fragment we want to add | |
9274 | in STRETCH in order to get a better estimate of the address. | |
9275 | This particularly matters because of the shift bits. */ | |
9276 | if (stretch != 0 | |
9277 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9278 | { | |
9279 | fragS *f; | |
9280 | ||
9281 | /* Adjust stretch for any alignment frag. */ | |
9282 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9283 | { | |
9284 | assert (f != NULL); | |
9285 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9286 | { | |
9287 | if (stretch < 0) | |
9288 | stretch = - ((- stretch) | |
9289 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9290 | else | |
9291 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9292 | if (stretch == 0) | |
9293 | break; | |
9294 | } | |
9295 | } | |
9296 | val += stretch; | |
9297 | } | |
9298 | ||
a677feeb ILT |
9299 | addr = fragp->fr_address + fragp->fr_fix; |
9300 | ||
9301 | /* The base address rules are complicated. The base address of | |
9302 | a branch is the following instruction. The base address of a | |
9303 | PC relative load or add is the instruction itself, but if it | |
9304 | is extended add 2, and if it is in a delay slot (in which | |
9305 | case it can not be extended) use the address of the | |
9306 | instruction whose delay slot it is in. */ | |
9307 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9308 | { |
9309 | addr += 2; | |
9310 | /* Ignore the low bit in the target, since it will be set | |
9311 | for a text label. */ | |
9312 | if ((val & 1) != 0) | |
9313 | --val; | |
9314 | } | |
a677feeb ILT |
9315 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9316 | addr -= 4; | |
9317 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9318 | addr -= 2; | |
cc5703cd ILT |
9319 | |
9320 | /* If we are currently assuming that this frag should be | |
9321 | extended, then the current address is two bytes higher. */ | |
9322 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9323 | addr += 2; | |
9324 | ||
9325 | val -= addr & ~ ((1 << op->shift) - 1); | |
9326 | ||
9327 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9328 | if (type == 'p' || type == 'q') | |
9329 | val /= 2; | |
9330 | ||
9331 | /* If any of the shifted bits are set, we must use an extended | |
9332 | opcode. If the address depends on the size of this | |
9333 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9334 | use an extended opcode. We only check this when we are in |
9335 | the main relaxation loop, when SEC is NULL. */ | |
9336 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9337 | { | |
9338 | fragp->fr_subtype = | |
9339 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9340 | return 1; | |
9341 | } | |
9342 | ||
9343 | /* If we are about to mark a frag as extended because the value | |
9344 | is precisely maxtiny + 1, then there is a chance of an | |
9345 | infinite loop as in the following code: | |
9346 | la $4,foo | |
9347 | .skip 1020 | |
9348 | .align 2 | |
9349 | foo: | |
9350 | In this case when the la is extended, foo is 0x3fc bytes | |
9351 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9352 | the la must be extended. To avoid this loop, we mark the | |
9353 | frag as extended if it was small, and is about to become | |
9354 | extended with a value of maxtiny + 1. */ | |
9355 | if (val == ((maxtiny + 1) << op->shift) | |
9356 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9357 | && sec == NULL) | |
cc5703cd ILT |
9358 | { |
9359 | fragp->fr_subtype = | |
9360 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9361 | return 1; | |
9362 | } | |
9363 | } | |
41a0ed22 ILT |
9364 | else if (symsec != absolute_section && sec != NULL) |
9365 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9366 | |
9367 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9368 | || val < (mintiny << op->shift) | |
9369 | || val > (maxtiny << op->shift)) | |
9370 | return 1; | |
9371 | else | |
9372 | return 0; | |
9373 | } | |
9374 | ||
9375 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9376 | mips16, we are not really relaxing here, and the final size is | |
9377 | encoded in the subtype information. For the mips16, we have to | |
9378 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9379 | |
0dd2d296 ILT |
9380 | /*ARGSUSED*/ |
9381 | int | |
9382 | md_estimate_size_before_relax (fragp, segtype) | |
9383 | fragS *fragp; | |
9384 | asection *segtype; | |
9385 | { | |
9386 | int change; | |
9387 | ||
cc5703cd ILT |
9388 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9389 | { | |
9390 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9391 | { | |
9392 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9393 | return 4; | |
9394 | } | |
9395 | else | |
9396 | { | |
9397 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9398 | return 2; | |
9399 | } | |
9400 | } | |
9401 | ||
d9aba805 | 9402 | if (mips_pic == NO_PIC) |
0dd2d296 | 9403 | { |
d8a1c247 | 9404 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9405 | } |
d9aba805 | 9406 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9407 | { |
9408 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9409 | ||
9410 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9411 | change = (symsec != &bfd_und_section | |
9412 | && symsec != &bfd_abs_section | |
9413 | && ! bfd_is_com_section (symsec)); | |
9414 | } | |
d9aba805 ILT |
9415 | else |
9416 | abort (); | |
0dd2d296 ILT |
9417 | |
9418 | if (change) | |
9419 | { | |
9420 | /* Record the offset to the first reloc in the fr_opcode field. | |
9421 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9422 | must be expanded. */ | |
9423 | fragp->fr_opcode = (fragp->fr_literal | |
9424 | + fragp->fr_fix | |
9425 | - RELAX_OLD (fragp->fr_subtype) | |
9426 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9427 | /* FIXME: This really needs as_warn_where. */ | |
9428 | if (RELAX_WARN (fragp->fr_subtype)) | |
9429 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9430 | } | |
9431 | ||
9432 | if (! change) | |
9433 | return 0; | |
9434 | else | |
9435 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9436 | } | |
9437 | ||
9438 | /* Translate internal representation of relocation info to BFD target | |
9439 | format. */ | |
9440 | ||
9441 | arelent ** | |
3d3c5039 ILT |
9442 | tc_gen_reloc (section, fixp) |
9443 | asection *section; | |
9444 | fixS *fixp; | |
9445 | { | |
0dd2d296 | 9446 | static arelent *retval[4]; |
3d3c5039 | 9447 | arelent *reloc; |
a8aed9dd | 9448 | bfd_reloc_code_real_type code; |
3d3c5039 | 9449 | |
0dd2d296 ILT |
9450 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9451 | retval[1] = NULL; | |
3d3c5039 ILT |
9452 | |
9453 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9454 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9455 | |
9456 | if (mips_pic == EMBEDDED_PIC | |
9457 | && SWITCH_TABLE (fixp)) | |
9458 | { | |
9459 | /* For a switch table entry we use a special reloc. The addend | |
9460 | is actually the difference between the reloc address and the | |
9461 | subtrahend. */ | |
9462 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9463 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9464 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9465 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9466 | } | |
ecd4ca1c ILT |
9467 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9468 | { | |
9469 | /* We use a special addend for an internal RELLO reloc. */ | |
9470 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9471 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9472 | else | |
9473 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9474 | } | |
9475 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9476 | { | |
9477 | assert (fixp->fx_next != NULL | |
9478 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9479 | /* We use a special addend for an internal RELHI reloc. The | |
9480 | reloc is relative to the RELLO; adjust the addend | |
9481 | accordingly. */ | |
9482 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9483 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9484 | + fixp->fx_next->fx_where | |
9485 | - S_GET_VALUE (fixp->fx_subsy)); | |
9486 | else | |
9487 | reloc->addend = (fixp->fx_addnumber | |
9488 | + fixp->fx_next->fx_frag->fr_address | |
9489 | + fixp->fx_next->fx_where); | |
9490 | } | |
1c803e52 | 9491 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9492 | reloc->addend = fixp->fx_addnumber; |
9493 | else | |
5b63f465 | 9494 | { |
1dc1e798 KR |
9495 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9496 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9497 | handling. */ | |
9498 | reloc->addend = reloc->address; | |
9499 | else | |
9500 | reloc->addend = -reloc->address; | |
5b63f465 | 9501 | } |
0dd2d296 ILT |
9502 | |
9503 | /* If this is a variant frag, we may need to adjust the existing | |
9504 | reloc and generate a new one. */ | |
9505 | if (fixp->fx_frag->fr_opcode != NULL | |
9506 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9507 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9508 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9509 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9510 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9511 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9512 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9513 | { |
9514 | arelent *reloc2; | |
9515 | ||
cc5703cd ILT |
9516 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9517 | ||
0dd2d296 | 9518 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9519 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9520 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9521 | the second one handle all of them. */ | |
0dd2d296 ILT |
9522 | if (fixp->fx_next != NULL |
9523 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9524 | { | |
fb251650 ILT |
9525 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9526 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9527 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9528 | && (fixp->fx_next->fx_r_type | |
9529 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9530 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9531 | && (fixp->fx_next->fx_r_type | |
9532 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9533 | retval[0] = NULL; |
9534 | return retval; | |
9535 | } | |
9536 | ||
9537 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9538 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9539 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9540 | retval[2] = NULL; | |
9541 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9542 | reloc2->address = (reloc->address | |
9543 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9544 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9545 | reloc2->addend = fixp->fx_addnumber; | |
9546 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9547 | assert (reloc2->howto != NULL); | |
9548 | ||
9549 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9550 | { | |
9551 | arelent *reloc3; | |
9552 | ||
9553 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9554 | retval[3] = NULL; | |
9555 | *reloc3 = *reloc2; | |
9556 | reloc3->address += 4; | |
9557 | } | |
9558 | ||
d9aba805 | 9559 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9560 | { |
9561 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9562 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9563 | } | |
d9aba805 | 9564 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9565 | { |
fb251650 | 9566 | switch (fixp->fx_r_type) |
0dd2d296 | 9567 | { |
fb251650 ILT |
9568 | default: |
9569 | abort (); | |
9570 | case BFD_RELOC_MIPS_GOT16: | |
9571 | break; | |
9572 | case BFD_RELOC_MIPS_CALL16: | |
9573 | case BFD_RELOC_MIPS_GOT_LO16: | |
9574 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9575 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9576 | break; |
0dd2d296 ILT |
9577 | } |
9578 | } | |
d9aba805 ILT |
9579 | else |
9580 | abort (); | |
0dd2d296 ILT |
9581 | } |
9582 | ||
a8aed9dd ILT |
9583 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9584 | fixup_segment converted a non-PC relative reloc into a PC | |
9585 | relative reloc. In such a case, we need to convert the reloc | |
9586 | code. */ | |
9587 | code = fixp->fx_r_type; | |
9588 | if (fixp->fx_pcrel) | |
9589 | { | |
9590 | switch (code) | |
9591 | { | |
9592 | case BFD_RELOC_8: | |
9593 | code = BFD_RELOC_8_PCREL; | |
9594 | break; | |
9595 | case BFD_RELOC_16: | |
9596 | code = BFD_RELOC_16_PCREL; | |
9597 | break; | |
9598 | case BFD_RELOC_32: | |
9599 | code = BFD_RELOC_32_PCREL; | |
9600 | break; | |
bf39474f ILT |
9601 | case BFD_RELOC_64: |
9602 | code = BFD_RELOC_64_PCREL; | |
9603 | break; | |
a8aed9dd ILT |
9604 | case BFD_RELOC_8_PCREL: |
9605 | case BFD_RELOC_16_PCREL: | |
9606 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9607 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9608 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9609 | case BFD_RELOC_PCREL_HI16_S: |
9610 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9611 | break; |
9612 | default: | |
9613 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9614 | "Cannot make %s relocation PC relative", | |
9615 | bfd_get_reloc_code_name (code)); | |
9616 | } | |
9617 | } | |
9618 | ||
d9aba805 ILT |
9619 | /* To support a PC relative reloc when generating embedded PIC code |
9620 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9621 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9622 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9623 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9624 | && mips_pic != EMBEDDED_PIC) |
9625 | reloc->howto = NULL; | |
9626 | else | |
a8aed9dd | 9627 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9628 | |
52aa70b5 JW |
9629 | if (reloc->howto == NULL) |
9630 | { | |
9631 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9632 | "Can not represent %s relocation in this object file format", |
9633 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9634 | retval[0] = NULL; |
52aa70b5 | 9635 | } |
3d3c5039 | 9636 | |
0dd2d296 | 9637 | return retval; |
3d3c5039 ILT |
9638 | } |
9639 | ||
cc5703cd ILT |
9640 | /* Relax a machine dependent frag. This returns the amount by which |
9641 | the current size of the frag should change. */ | |
9642 | ||
9643 | int | |
9644 | mips_relax_frag (fragp, stretch) | |
9645 | fragS *fragp; | |
9646 | long stretch; | |
9647 | { | |
9648 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9649 | return 0; | |
9650 | ||
9651 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9652 | { | |
9653 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9654 | return 0; | |
9655 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9656 | return 2; | |
9657 | } | |
9658 | else | |
9659 | { | |
9660 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9661 | return 0; | |
9662 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9663 | return -2; | |
9664 | } | |
9665 | ||
9666 | return 0; | |
9667 | } | |
9668 | ||
0dd2d296 ILT |
9669 | /* Convert a machine dependent frag. */ |
9670 | ||
9671 | void | |
9672 | md_convert_frag (abfd, asec, fragp) | |
9673 | bfd *abfd; | |
9674 | segT asec; | |
9675 | fragS *fragp; | |
3d3c5039 | 9676 | { |
0dd2d296 ILT |
9677 | int old, new; |
9678 | char *fixptr; | |
3d3c5039 | 9679 | |
cc5703cd ILT |
9680 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9681 | { | |
9682 | int type; | |
9683 | register const struct mips16_immed_operand *op; | |
9684 | boolean small, ext; | |
9685 | offsetT val; | |
9686 | bfd_byte *buf; | |
9687 | unsigned long insn; | |
9688 | boolean use_extend; | |
9689 | unsigned short extend; | |
9690 | ||
9691 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9692 | op = mips16_immed_operands; | |
9693 | while (op->type != type) | |
9694 | ++op; | |
9695 | ||
9696 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9697 | { | |
9698 | small = false; | |
9699 | ext = true; | |
9700 | } | |
9701 | else | |
9702 | { | |
9703 | small = true; | |
9704 | ext = false; | |
9705 | } | |
9706 | ||
f74ba7a3 | 9707 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9708 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9709 | if (op->pcrel) |
9710 | { | |
9711 | addressT addr; | |
9712 | ||
a677feeb ILT |
9713 | addr = fragp->fr_address + fragp->fr_fix; |
9714 | ||
9715 | /* The rules for the base address of a PC relative reloc are | |
9716 | complicated; see mips16_extended_frag. */ | |
9717 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9718 | { |
9719 | addr += 2; | |
9720 | /* Ignore the low bit in the target, since it will be | |
9721 | set for a text label. */ | |
9722 | if ((val & 1) != 0) | |
9723 | --val; | |
9724 | } | |
a677feeb ILT |
9725 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9726 | addr -= 4; | |
9727 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9728 | addr -= 2; | |
9729 | ||
cc5703cd ILT |
9730 | if (ext) |
9731 | addr += 2; | |
9732 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9733 | val -= addr; | |
a677feeb ILT |
9734 | |
9735 | /* Make sure the section winds up with the alignment we have | |
9736 | assumed. */ | |
9737 | if (op->shift > 0) | |
9738 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9739 | } |
9740 | ||
9741 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9742 | ||
b9129c6f ILT |
9743 | if (target_big_endian) |
9744 | insn = bfd_getb16 (buf); | |
9745 | else | |
9746 | insn = bfd_getl16 (buf); | |
cc5703cd | 9747 | |
15e69f98 ILT |
9748 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, false, small, |
9749 | ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9750 | |
9751 | if (use_extend) | |
9752 | { | |
9753 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9754 | fragp->fr_fix += 2; | |
9755 | buf += 2; | |
9756 | } | |
3d3c5039 | 9757 | |
cc5703cd ILT |
9758 | md_number_to_chars (buf, insn, 2); |
9759 | fragp->fr_fix += 2; | |
9760 | buf += 2; | |
9761 | } | |
9762 | else | |
9763 | { | |
9764 | if (fragp->fr_opcode == NULL) | |
9765 | return; | |
0dd2d296 | 9766 | |
cc5703cd ILT |
9767 | old = RELAX_OLD (fragp->fr_subtype); |
9768 | new = RELAX_NEW (fragp->fr_subtype); | |
9769 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9770 | |
cc5703cd ILT |
9771 | if (new > 0) |
9772 | memcpy (fixptr - old, fixptr, new); | |
9773 | ||
9774 | fragp->fr_fix += new - old; | |
9775 | } | |
0dd2d296 | 9776 | } |
becfe05e | 9777 | |
fbcfacb7 ILT |
9778 | #ifdef OBJ_ELF |
9779 | ||
9780 | /* This function is called after the relocs have been generated. | |
9781 | We've been storing mips16 text labels as odd. Here we convert them | |
9782 | back to even for the convenience of the debugger. */ | |
9783 | ||
9784 | void | |
9785 | mips_frob_file_after_relocs () | |
9786 | { | |
9787 | asymbol **syms; | |
9788 | unsigned int count, i; | |
9789 | ||
9790 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9791 | return; | |
9792 | ||
9793 | syms = bfd_get_outsymbols (stdoutput); | |
9794 | count = bfd_get_symcount (stdoutput); | |
9795 | for (i = 0; i < count; i++, syms++) | |
9796 | { | |
9797 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
9798 | && ((*syms)->value & 1) != 0) | |
9799 | { | |
9800 | (*syms)->value &= ~1; | |
9801 | /* If the symbol has an odd size, it was probably computed | |
9802 | incorrectly, so adjust that as well. */ | |
9803 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
9804 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
9805 | } | |
9806 | } | |
9807 | } | |
9808 | ||
9809 | #endif | |
9810 | ||
becfe05e ILT |
9811 | /* This function is called whenever a label is defined. It is used |
9812 | when handling branch delays; if a branch has a label, we assume we | |
9813 | can not move it. */ | |
9814 | ||
9815 | void | |
9816 | mips_define_label (sym) | |
9817 | symbolS *sym; | |
9818 | { | |
fbcfacb7 ILT |
9819 | struct insn_label_list *l; |
9820 | ||
9821 | if (free_insn_labels == NULL) | |
9822 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
9823 | else | |
9824 | { | |
9825 | l = free_insn_labels; | |
9826 | free_insn_labels = l->next; | |
9827 | } | |
9828 | ||
9829 | l->label = sym; | |
9830 | l->next = insn_labels; | |
9831 | insn_labels = l; | |
becfe05e | 9832 | } |
22ba90ce ILT |
9833 | |
9834 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
9835 | In order to work with gcc when using mips-tfile, we must keep all | |
9836 | local labels. However, in other cases, we want to discard them, | |
9837 | since they are useless. */ | |
9838 | ||
9839 | int | |
9840 | mips_local_label (name) | |
9841 | const char *name; | |
9842 | { | |
c625fc23 | 9843 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
9844 | if (ECOFF_DEBUGGING |
9845 | && mips_debug != 0 | |
9846 | && ! ecoff_debugging_seen) | |
9847 | { | |
9848 | /* We were called with -g, but we didn't see any debugging | |
9849 | information. That may mean that gcc is smuggling debugging | |
9850 | information through to mips-tfile, in which case we must | |
9851 | generate all local labels. */ | |
9852 | return 0; | |
9853 | } | |
c625fc23 | 9854 | #endif |
22ba90ce ILT |
9855 | |
9856 | /* Here it's OK to discard local labels. */ | |
9857 | ||
3af584b4 | 9858 | return name[0] == '$'; |
22ba90ce | 9859 | } |
3d3c5039 | 9860 | \f |
739708fa | 9861 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 9862 | |
0dd2d296 | 9863 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
9864 | |
9865 | void | |
9866 | mips_elf_final_processing () | |
9867 | { | |
87178180 ILT |
9868 | /* Write out the register information. */ |
9869 | if (! mips_64) | |
9870 | { | |
9871 | Elf32_RegInfo s; | |
9872 | ||
9873 | s.ri_gprmask = mips_gprmask; | |
9874 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9875 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9876 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9877 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9878 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9879 | ||
9880 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
9881 | ((Elf32_External_RegInfo *) | |
9882 | mips_regmask_frag)); | |
9883 | } | |
9884 | else | |
9885 | { | |
9886 | Elf64_Internal_RegInfo s; | |
9887 | ||
9888 | s.ri_gprmask = mips_gprmask; | |
9889 | s.ri_pad = 0; | |
9890 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9891 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9892 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9893 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9894 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9895 | ||
9896 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
9897 | ((Elf64_External_RegInfo *) | |
9898 | mips_regmask_frag)); | |
9899 | } | |
0dd2d296 ILT |
9900 | |
9901 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
9902 | sort of BFD interface for this. */ | |
9903 | if (mips_any_noreorder) | |
9904 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 9905 | if (mips_pic != NO_PIC) |
0dd2d296 | 9906 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
9907 | } |
9908 | ||
739708fa | 9909 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 9910 | \f |
3d3c5039 ILT |
9911 | /* These functions should really be defined by the object file format, |
9912 | since they are related to debugging information. However, this | |
9913 | code has to work for the a.out format, which does not define them, | |
9914 | so we provide simple versions here. These don't actually generate | |
9915 | any debugging information, but they do simple checking and someday | |
9916 | somebody may make them useful. */ | |
9917 | ||
670a50eb ILT |
9918 | typedef struct loc |
9919 | { | |
9920 | struct loc *loc_next; | |
9921 | unsigned long loc_fileno; | |
9922 | unsigned long loc_lineno; | |
9923 | unsigned long loc_offset; | |
9924 | unsigned short loc_delta; | |
9925 | unsigned short loc_count; | |
3d3c5039 | 9926 | #if 0 |
670a50eb | 9927 | fragS *loc_frag; |
3d3c5039 | 9928 | #endif |
670a50eb ILT |
9929 | } |
9930 | locS; | |
3d3c5039 | 9931 | |
670a50eb ILT |
9932 | typedef struct proc |
9933 | { | |
3d3c5039 ILT |
9934 | struct proc *proc_next; |
9935 | struct symbol *proc_isym; | |
9936 | struct symbol *proc_end; | |
9937 | unsigned long proc_reg_mask; | |
9938 | unsigned long proc_reg_offset; | |
9939 | unsigned long proc_fpreg_mask; | |
9940 | unsigned long proc_fpreg_offset; | |
9941 | unsigned long proc_frameoffset; | |
9942 | unsigned long proc_framereg; | |
9943 | unsigned long proc_pcreg; | |
9944 | locS *proc_iline; | |
9945 | struct file *proc_file; | |
9946 | int proc_index; | |
670a50eb ILT |
9947 | } |
9948 | procS; | |
3d3c5039 | 9949 | |
670a50eb ILT |
9950 | typedef struct file |
9951 | { | |
3d3c5039 ILT |
9952 | struct file *file_next; |
9953 | unsigned long file_fileno; | |
9954 | struct symbol *file_symbol; | |
9955 | struct symbol *file_end; | |
9956 | struct proc *file_proc; | |
9957 | int file_numprocs; | |
670a50eb ILT |
9958 | } |
9959 | fileS; | |
3d3c5039 ILT |
9960 | |
9961 | static struct obstack proc_frags; | |
9962 | static procS *proc_lastP; | |
9963 | static procS *proc_rootP; | |
9964 | static int numprocs; | |
9965 | ||
9966 | static void | |
9967 | md_obj_begin () | |
9968 | { | |
670a50eb | 9969 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
9970 | } |
9971 | ||
9972 | static void | |
9973 | md_obj_end () | |
9974 | { | |
9975 | /* check for premature end, nesting errors, etc */ | |
9976 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 9977 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
9978 | } |
9979 | ||
3d3c5039 ILT |
9980 | static long |
9981 | get_number () | |
9982 | { | |
670a50eb ILT |
9983 | int negative = 0; |
9984 | long val = 0; | |
3d3c5039 | 9985 | |
670a50eb ILT |
9986 | if (*input_line_pointer == '-') |
9987 | { | |
9988 | ++input_line_pointer; | |
9989 | negative = 1; | |
3d3c5039 | 9990 | } |
670a50eb ILT |
9991 | if (!isdigit (*input_line_pointer)) |
9992 | as_bad ("Expected simple number."); | |
9993 | if (input_line_pointer[0] == '0') | |
9994 | { | |
9995 | if (input_line_pointer[1] == 'x') | |
9996 | { | |
9997 | input_line_pointer += 2; | |
9998 | while (isxdigit (*input_line_pointer)) | |
9999 | { | |
10000 | val <<= 4; | |
3a762a0b | 10001 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10002 | } |
670a50eb ILT |
10003 | return negative ? -val : val; |
10004 | } | |
10005 | else | |
10006 | { | |
10007 | ++input_line_pointer; | |
10008 | while (isdigit (*input_line_pointer)) | |
10009 | { | |
10010 | val <<= 3; | |
10011 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10012 | } |
670a50eb | 10013 | return negative ? -val : val; |
3d3c5039 ILT |
10014 | } |
10015 | } | |
670a50eb ILT |
10016 | if (!isdigit (*input_line_pointer)) |
10017 | { | |
10018 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10019 | *input_line_pointer, *input_line_pointer); | |
10020 | as_warn ("Invalid number"); | |
10021 | return -1; | |
3d3c5039 | 10022 | } |
670a50eb ILT |
10023 | while (isdigit (*input_line_pointer)) |
10024 | { | |
10025 | val *= 10; | |
10026 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10027 | } |
670a50eb | 10028 | return negative ? -val : val; |
3d3c5039 ILT |
10029 | } |
10030 | ||
10031 | /* The .file directive; just like the usual .file directive, but there | |
10032 | is an initial number which is the ECOFF file index. */ | |
10033 | ||
10034 | static void | |
10035 | s_file (x) | |
10036 | int x; | |
10037 | { | |
670a50eb | 10038 | int line; |
3d3c5039 | 10039 | |
670a50eb | 10040 | line = get_number (); |
9a7d824a | 10041 | s_app_file (0); |
3d3c5039 ILT |
10042 | } |
10043 | ||
10044 | ||
10045 | /* The .end directive. */ | |
10046 | ||
10047 | static void | |
10048 | s_mipsend (x) | |
10049 | int x; | |
10050 | { | |
670a50eb ILT |
10051 | symbolS *p; |
10052 | ||
10053 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10054 | { | |
10055 | p = get_symbol (); | |
10056 | demand_empty_rest_of_line (); | |
10057 | } | |
10058 | else | |
10059 | p = NULL; | |
10060 | if (now_seg != text_section) | |
10061 | as_warn (".end not in text section"); | |
10062 | if (!proc_lastP) | |
10063 | { | |
10064 | as_warn (".end and no .ent seen yet."); | |
10065 | return; | |
3d3c5039 ILT |
10066 | } |
10067 | ||
670a50eb ILT |
10068 | if (p != NULL) |
10069 | { | |
10070 | assert (S_GET_NAME (p)); | |
10071 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10072 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10073 | } |
10074 | ||
670a50eb | 10075 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10076 | } |
10077 | ||
10078 | /* The .aent and .ent directives. */ | |
10079 | ||
10080 | static void | |
10081 | s_ent (aent) | |
10082 | int aent; | |
10083 | { | |
670a50eb ILT |
10084 | int number = 0; |
10085 | procS *procP; | |
10086 | symbolS *symbolP; | |
10087 | ||
10088 | symbolP = get_symbol (); | |
10089 | if (*input_line_pointer == ',') | |
10090 | input_line_pointer++; | |
dd3f1f76 | 10091 | SKIP_WHITESPACE (); |
670a50eb ILT |
10092 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10093 | number = get_number (); | |
10094 | if (now_seg != text_section) | |
10095 | as_warn (".ent or .aent not in text section."); | |
10096 | ||
10097 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10098 | as_warn ("missing `.end'"); | |
10099 | ||
10100 | if (!aent) | |
10101 | { | |
10102 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10103 | procP->proc_isym = symbolP; | |
10104 | procP->proc_reg_mask = 0; | |
10105 | procP->proc_reg_offset = 0; | |
10106 | procP->proc_fpreg_mask = 0; | |
10107 | procP->proc_fpreg_offset = 0; | |
10108 | procP->proc_frameoffset = 0; | |
10109 | procP->proc_framereg = 0; | |
10110 | procP->proc_pcreg = 0; | |
10111 | procP->proc_end = NULL; | |
10112 | procP->proc_next = NULL; | |
10113 | if (proc_lastP) | |
10114 | proc_lastP->proc_next = procP; | |
10115 | else | |
10116 | proc_rootP = procP; | |
10117 | proc_lastP = procP; | |
10118 | numprocs++; | |
3d3c5039 | 10119 | } |
670a50eb | 10120 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10121 | } |
10122 | ||
10123 | /* The .frame directive. */ | |
10124 | ||
88225433 | 10125 | #if 0 |
3d3c5039 ILT |
10126 | static void |
10127 | s_frame (x) | |
670a50eb | 10128 | int x; |
3d3c5039 | 10129 | { |
670a50eb ILT |
10130 | char str[100]; |
10131 | symbolS *symP; | |
10132 | int frame_reg; | |
10133 | int frame_off; | |
10134 | int pcreg; | |
10135 | ||
0dd2d296 | 10136 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10137 | if (*input_line_pointer == ',') |
10138 | input_line_pointer++; | |
5ac34ac3 | 10139 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10140 | if (*input_line_pointer == ',') |
10141 | input_line_pointer++; | |
0dd2d296 | 10142 | pcreg = tc_get_register (0); |
670a50eb ILT |
10143 | |
10144 | /* bob third eye */ | |
10145 | assert (proc_rootP); | |
10146 | proc_rootP->proc_framereg = frame_reg; | |
10147 | proc_rootP->proc_frameoffset = frame_off; | |
10148 | proc_rootP->proc_pcreg = pcreg; | |
10149 | /* bob macho .frame */ | |
10150 | ||
10151 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10152 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10153 | { |
10154 | if (!proc_lastP) | |
10155 | as_warn ("No .ent for .frame to use."); | |
10156 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10157 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10158 | S_SET_TYPE (symP, N_RMASK); | |
10159 | S_SET_OTHER (symP, 0); | |
10160 | S_SET_DESC (symP, 0); | |
10161 | symP->sy_forward = proc_lastP->proc_isym; | |
10162 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10163 | } |
670a50eb | 10164 | demand_empty_rest_of_line (); |
3d3c5039 | 10165 | } |
88225433 | 10166 | #endif |
3d3c5039 ILT |
10167 | |
10168 | /* The .fmask and .mask directives. */ | |
10169 | ||
88225433 | 10170 | #if 0 |
3d3c5039 ILT |
10171 | static void |
10172 | s_mask (reg_type) | |
10173 | char reg_type; | |
10174 | { | |
670a50eb ILT |
10175 | char str[100], *strP; |
10176 | symbolS *symP; | |
10177 | int i; | |
10178 | unsigned int mask; | |
10179 | int off; | |
10180 | ||
10181 | mask = get_number (); | |
10182 | if (*input_line_pointer == ',') | |
10183 | input_line_pointer++; | |
10184 | off = get_absolute_expression (); | |
10185 | ||
10186 | /* bob only for coff */ | |
10187 | assert (proc_rootP); | |
10188 | if (reg_type == 'F') | |
10189 | { | |
10190 | proc_rootP->proc_fpreg_mask = mask; | |
10191 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10192 | } |
670a50eb ILT |
10193 | else |
10194 | { | |
10195 | proc_rootP->proc_reg_mask = mask; | |
10196 | proc_rootP->proc_reg_offset = off; | |
10197 | } | |
10198 | ||
10199 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10200 | |
670a50eb ILT |
10201 | /* We don't have to write out a mask stab if no saved regs. */ |
10202 | if (!(mask == 0)) | |
10203 | { | |
10204 | if (!proc_lastP) | |
10205 | as_warn ("No .ent for .mask to use."); | |
10206 | strP = str; | |
10207 | for (i = 0; i < 32; i++) | |
10208 | { | |
10209 | if (mask % 2) | |
10210 | { | |
10211 | sprintf (strP, "%c%d,", reg_type, i); | |
10212 | strP += strlen (strP); | |
10213 | } | |
3d3c5039 | 10214 | mask /= 2; |
670a50eb ILT |
10215 | } |
10216 | sprintf (strP, ";%d,", off); | |
10217 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10218 | S_SET_TYPE (symP, N_RMASK); | |
10219 | S_SET_OTHER (symP, 0); | |
10220 | S_SET_DESC (symP, 0); | |
10221 | symP->sy_forward = proc_lastP->proc_isym; | |
10222 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10223 | } |
3d3c5039 | 10224 | } |
88225433 | 10225 | #endif |
3d3c5039 ILT |
10226 | |
10227 | /* The .loc directive. */ | |
10228 | ||
88225433 | 10229 | #if 0 |
3d3c5039 ILT |
10230 | static void |
10231 | s_loc (x) | |
10232 | int x; | |
10233 | { | |
670a50eb ILT |
10234 | symbolS *symbolP; |
10235 | int lineno; | |
10236 | int addroff; | |
3d3c5039 | 10237 | |
670a50eb | 10238 | assert (now_seg == text_section); |
3d3c5039 | 10239 | |
670a50eb | 10240 | lineno = get_number (); |
87e48495 | 10241 | addroff = frag_now_fix (); |
3d3c5039 | 10242 | |
670a50eb ILT |
10243 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10244 | S_SET_TYPE (symbolP, N_SLINE); | |
10245 | S_SET_OTHER (symbolP, 0); | |
10246 | S_SET_DESC (symbolP, lineno); | |
10247 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10248 | } |
88225433 | 10249 | #endif |