Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
ef2e4d86 | 219 | int ase_mt; |
dec0624d | 220 | int ase_mcu; |
b015e599 | 221 | int ase_virt; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
b015e599 AP |
296 | /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1, |
297 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
298 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
299 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
300 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 301 | }; |
252b5132 RH |
302 | |
303 | /* These variables are filled in with the masks of registers used. | |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
309 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 310 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 311 | |
738f4d98 | 312 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
313 | static int file_ase_mips16; |
314 | ||
3994f87e TS |
315 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
316 | || mips_opts.isa == ISA_MIPS32R2 \ | |
317 | || mips_opts.isa == ISA_MIPS64 \ | |
318 | || mips_opts.isa == ISA_MIPS64R2) | |
319 | ||
df58fc94 RS |
320 | /* True if any microMIPS code was produced. */ |
321 | static int file_ase_micromips; | |
322 | ||
b12dd2e4 CF |
323 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
324 | #ifdef TE_IRIX | |
1180b5a4 | 325 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 326 | #else |
1180b5a4 RS |
327 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
328 | because there's no place for any addend, the only acceptable | |
329 | expression is a bare symbol. */ | |
330 | #define MIPS_JALR_HINT_P(EXPR) \ | |
331 | (!HAVE_IN_PLACE_ADDENDS \ | |
332 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
333 | #endif |
334 | ||
1f25f5d3 CD |
335 | /* True if -mips3d was passed or implied by arguments passed on the |
336 | command line (e.g., by -march). */ | |
337 | static int file_ase_mips3d; | |
338 | ||
deec1734 CD |
339 | /* True if -mdmx was passed or implied by arguments passed on the |
340 | command line (e.g., by -march). */ | |
341 | static int file_ase_mdmx; | |
342 | ||
e16bfa71 TS |
343 | /* True if -msmartmips was passed or implied by arguments passed on the |
344 | command line (e.g., by -march). */ | |
345 | static int file_ase_smartmips; | |
346 | ||
ad3fea08 TS |
347 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
348 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 349 | |
74cd071d CF |
350 | /* True if -mdsp was passed or implied by arguments passed on the |
351 | command line (e.g., by -march). */ | |
352 | static int file_ase_dsp; | |
353 | ||
ad3fea08 | 354 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
355 | || mips_opts.isa == ISA_MIPS64R2 \ |
356 | || mips_opts.micromips) | |
ad3fea08 | 357 | |
65263ce3 TS |
358 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
359 | ||
8b082fb1 TS |
360 | /* True if -mdspr2 was passed or implied by arguments passed on the |
361 | command line (e.g., by -march). */ | |
362 | static int file_ase_dspr2; | |
363 | ||
364 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
365 | || mips_opts.isa == ISA_MIPS64R2 \ |
366 | || mips_opts.micromips) | |
8b082fb1 | 367 | |
ef2e4d86 CF |
368 | /* True if -mmt was passed or implied by arguments passed on the |
369 | command line (e.g., by -march). */ | |
370 | static int file_ase_mt; | |
371 | ||
ad3fea08 TS |
372 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
373 | || mips_opts.isa == ISA_MIPS64R2) | |
374 | ||
dec0624d | 375 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
376 | || mips_opts.isa == ISA_MIPS64R2 \ |
377 | || mips_opts.micromips) | |
dec0624d | 378 | |
b015e599 AP |
379 | /* True if -mvirt was passed or implied by arguments passed on the |
380 | command line (e.g., by -march). */ | |
381 | static int file_ase_virt; | |
382 | ||
383 | #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
384 | || mips_opts.isa == ISA_MIPS64R2) | |
385 | ||
386 | #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2) | |
387 | ||
ec68c924 | 388 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 389 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 390 | static const char *mips_arch_string; |
ec68c924 EC |
391 | |
392 | /* The argument of the -mtune= flag. The architecture for which we | |
393 | are optimizing. */ | |
394 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 395 | static const char *mips_tune_string; |
ec68c924 | 396 | |
316f5878 | 397 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
398 | static int mips_32bitmode = 0; |
399 | ||
316f5878 RS |
400 | /* True if the given ABI requires 32-bit registers. */ |
401 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
402 | ||
403 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
404 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
405 | ((ABI) == N32_ABI \ | |
406 | || (ABI) == N64_ABI \ | |
316f5878 RS |
407 | || (ABI) == O64_ABI) |
408 | ||
ad3fea08 | 409 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
410 | #define ISA_HAS_64BIT_REGS(ISA) \ |
411 | ((ISA) == ISA_MIPS3 \ | |
412 | || (ISA) == ISA_MIPS4 \ | |
413 | || (ISA) == ISA_MIPS5 \ | |
414 | || (ISA) == ISA_MIPS64 \ | |
415 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 416 | |
ad3fea08 TS |
417 | /* Return true if ISA supports 64 bit wide float registers. */ |
418 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
419 | ((ISA) == ISA_MIPS3 \ | |
420 | || (ISA) == ISA_MIPS4 \ | |
421 | || (ISA) == ISA_MIPS5 \ | |
422 | || (ISA) == ISA_MIPS32R2 \ | |
423 | || (ISA) == ISA_MIPS64 \ | |
424 | || (ISA) == ISA_MIPS64R2) | |
425 | ||
af7ee8bf CD |
426 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
427 | instructions. */ | |
707bfff6 | 428 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
429 | ((ISA) == ISA_MIPS64R2 \ |
430 | || (mips_opts.micromips \ | |
431 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
432 | ) | |
af7ee8bf CD |
433 | |
434 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
435 | instructions. */ | |
707bfff6 TS |
436 | #define ISA_HAS_ROR(ISA) \ |
437 | ((ISA) == ISA_MIPS32R2 \ | |
438 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
439 | || mips_opts.ase_smartmips \ |
440 | || mips_opts.micromips \ | |
441 | ) | |
707bfff6 | 442 | |
7455baf8 TS |
443 | /* Return true if ISA supports single-precision floats in odd registers. */ |
444 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
445 | ((ISA) == ISA_MIPS32 \ | |
446 | || (ISA) == ISA_MIPS32R2 \ | |
447 | || (ISA) == ISA_MIPS64 \ | |
448 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 449 | |
ad3fea08 TS |
450 | /* Return true if ISA supports move to/from high part of a 64-bit |
451 | floating-point register. */ | |
452 | #define ISA_HAS_MXHC1(ISA) \ | |
453 | ((ISA) == ISA_MIPS32R2 \ | |
454 | || (ISA) == ISA_MIPS64R2) | |
455 | ||
e013f690 | 456 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 457 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 458 | |
e013f690 | 459 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 460 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 461 | |
ad3fea08 TS |
462 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
463 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
474 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
432233b3 | 513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 514 | |
dd3cbb7e | 515 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 516 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 517 | |
0aa27725 RS |
518 | /* True, if CPU has support for ldc1 and sdc1. */ |
519 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
520 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
521 | ||
c8978940 CD |
522 | /* True if mflo and mfhi can be immediately followed by instructions |
523 | which write to the HI and LO registers. | |
524 | ||
525 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
526 | (at least) two instructions between the reads of HI/LO and | |
527 | instructions which write them, and later ISAs do not. Contradicting | |
528 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
529 | the UM for the NEC Vr5000) document needing the instructions between | |
530 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
531 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
532 | earlier-ISA CPUs for which CPU documentation declares that the | |
533 | instructions are really interlocked. */ | |
534 | #define hilo_interlocks \ | |
535 | (mips_opts.isa == ISA_MIPS32 \ | |
536 | || mips_opts.isa == ISA_MIPS32R2 \ | |
537 | || mips_opts.isa == ISA_MIPS64 \ | |
538 | || mips_opts.isa == ISA_MIPS64R2 \ | |
539 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 540 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
541 | || mips_opts.arch == CPU_R10000 \ |
542 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
543 | || mips_opts.arch == CPU_R14000 \ |
544 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 545 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 546 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 547 | || mips_opts.micromips \ |
c8978940 | 548 | ) |
252b5132 RH |
549 | |
550 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
551 | from the GPRs after they are loaded from memory, and thus does not |
552 | require nops to be inserted. This applies to instructions marked | |
553 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
554 | level I and microMIPS mode instructions are always interlocked. */ |
555 | #define gpr_interlocks \ | |
556 | (mips_opts.isa != ISA_MIPS1 \ | |
557 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 558 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
559 | || mips_opts.micromips \ |
560 | ) | |
252b5132 | 561 | |
81912461 ILT |
562 | /* Whether the processor uses hardware interlocks to avoid delays |
563 | required by coprocessor instructions, and thus does not require | |
564 | nops to be inserted. This applies to instructions marked | |
565 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
566 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
567 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
568 | levels I, II, and III and microMIPS mode instructions are always |
569 | interlocked. */ | |
bdaaa2e1 | 570 | /* Itbl support may require additional care here. */ |
81912461 ILT |
571 | #define cop_interlocks \ |
572 | ((mips_opts.isa != ISA_MIPS1 \ | |
573 | && mips_opts.isa != ISA_MIPS2 \ | |
574 | && mips_opts.isa != ISA_MIPS3) \ | |
575 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 576 | || mips_opts.micromips \ |
81912461 ILT |
577 | ) |
578 | ||
579 | /* Whether the processor uses hardware interlocks to protect reads | |
580 | from coprocessor registers after they are loaded from memory, and | |
581 | thus does not require nops to be inserted. This applies to | |
582 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
583 | requires at MIPS ISA level I and microMIPS mode instructions are |
584 | always interlocked. */ | |
585 | #define cop_mem_interlocks \ | |
586 | (mips_opts.isa != ISA_MIPS1 \ | |
587 | || mips_opts.micromips \ | |
588 | ) | |
252b5132 | 589 | |
6b76fefe CM |
590 | /* Is this a mfhi or mflo instruction? */ |
591 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
592 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
593 | ||
df58fc94 RS |
594 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
595 | has been selected. This implies, in particular, that addresses of text | |
596 | labels have their LSB set. */ | |
597 | #define HAVE_CODE_COMPRESSION \ | |
598 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
599 | ||
252b5132 RH |
600 | /* MIPS PIC level. */ |
601 | ||
a161fe53 | 602 | enum mips_pic_level mips_pic; |
252b5132 | 603 | |
c9914766 | 604 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 605 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 606 | static int mips_big_got = 0; |
252b5132 RH |
607 | |
608 | /* 1 if trap instructions should used for overflow rather than break | |
609 | instructions. */ | |
c9914766 | 610 | static int mips_trap = 0; |
252b5132 | 611 | |
119d663a | 612 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 613 | by assembling two single width halves into two single width floating |
119d663a NC |
614 | point registers which just happen to alias the double width destination |
615 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 616 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
617 | automatically at assemble time. */ |
618 | static int mips_disable_float_construction; | |
619 | ||
252b5132 RH |
620 | /* Non-zero if any .set noreorder directives were used. */ |
621 | ||
622 | static int mips_any_noreorder; | |
623 | ||
6b76fefe CM |
624 | /* Non-zero if nops should be inserted when the register referenced in |
625 | an mfhi/mflo instruction is read in the next two instructions. */ | |
626 | static int mips_7000_hilo_fix; | |
627 | ||
02ffd3e4 | 628 | /* The size of objects in the small data section. */ |
156c2f8b | 629 | static unsigned int g_switch_value = 8; |
252b5132 RH |
630 | /* Whether the -G option was used. */ |
631 | static int g_switch_seen = 0; | |
632 | ||
633 | #define N_RMASK 0xc4 | |
634 | #define N_VFP 0xd4 | |
635 | ||
636 | /* If we can determine in advance that GP optimization won't be | |
637 | possible, we can skip the relaxation stuff that tries to produce | |
638 | GP-relative references. This makes delay slot optimization work | |
639 | better. | |
640 | ||
641 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
642 | gcc output. It needs to guess right for gcc, otherwise gcc |
643 | will put what it thinks is a GP-relative instruction in a branch | |
644 | delay slot. | |
252b5132 RH |
645 | |
646 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
647 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 648 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
649 | |
650 | /* handle of the OPCODE hash table */ | |
651 | static struct hash_control *op_hash = NULL; | |
652 | ||
653 | /* The opcode hash table we use for the mips16. */ | |
654 | static struct hash_control *mips16_op_hash = NULL; | |
655 | ||
df58fc94 RS |
656 | /* The opcode hash table we use for the microMIPS ASE. */ |
657 | static struct hash_control *micromips_op_hash = NULL; | |
658 | ||
252b5132 RH |
659 | /* This array holds the chars that always start a comment. If the |
660 | pre-processor is disabled, these aren't very useful */ | |
661 | const char comment_chars[] = "#"; | |
662 | ||
663 | /* This array holds the chars that only start a comment at the beginning of | |
664 | a line. If the line seems to have the form '# 123 filename' | |
665 | .line and .file directives will appear in the pre-processed output */ | |
666 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
667 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 668 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
669 | /* Also note that C style comments are always supported. */ |
670 | const char line_comment_chars[] = "#"; | |
671 | ||
bdaaa2e1 | 672 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 673 | const char line_separator_chars[] = ";"; |
252b5132 RH |
674 | |
675 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
676 | const char EXP_CHARS[] = "eE"; | |
677 | ||
678 | /* Chars that mean this number is a floating point constant */ | |
679 | /* As in 0f12.456 */ | |
680 | /* or 0d1.2345e12 */ | |
681 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
682 | ||
683 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
684 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
685 | but nothing is ideal around here. | |
686 | */ | |
687 | ||
688 | static char *insn_error; | |
689 | ||
690 | static int auto_align = 1; | |
691 | ||
692 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
693 | offset in the stack frame from which to restore the $gp register. | |
694 | This is set by the .cprestore pseudo-op, and saved in this | |
695 | variable. */ | |
696 | static offsetT mips_cprestore_offset = -1; | |
697 | ||
67c1ffbe | 698 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 699 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 700 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
701 | static offsetT mips_cpreturn_offset = -1; |
702 | static int mips_cpreturn_register = -1; | |
703 | static int mips_gp_register = GP; | |
def2e0dd | 704 | static int mips_gprel_offset = 0; |
6478892d | 705 | |
7a621144 DJ |
706 | /* Whether mips_cprestore_offset has been set in the current function |
707 | (or whether it has already been warned about, if not). */ | |
708 | static int mips_cprestore_valid = 0; | |
709 | ||
252b5132 RH |
710 | /* This is the register which holds the stack frame, as set by the |
711 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
712 | static int mips_frame_reg = SP; | |
713 | ||
7a621144 DJ |
714 | /* Whether mips_frame_reg has been set in the current function |
715 | (or whether it has already been warned about, if not). */ | |
716 | static int mips_frame_reg_valid = 0; | |
717 | ||
252b5132 RH |
718 | /* To output NOP instructions correctly, we need to keep information |
719 | about the previous two instructions. */ | |
720 | ||
721 | /* Whether we are optimizing. The default value of 2 means to remove | |
722 | unneeded NOPs and swap branch instructions when possible. A value | |
723 | of 1 means to not swap branches. A value of 0 means to always | |
724 | insert NOPs. */ | |
725 | static int mips_optimize = 2; | |
726 | ||
727 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
728 | equivalent to seeing no -g option at all. */ | |
729 | static int mips_debug = 0; | |
730 | ||
7d8e00cf RS |
731 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
732 | #define MAX_VR4130_NOPS 4 | |
733 | ||
734 | /* The maximum number of NOPs needed to fill delay slots. */ | |
735 | #define MAX_DELAY_NOPS 2 | |
736 | ||
737 | /* The maximum number of NOPs needed for any purpose. */ | |
738 | #define MAX_NOPS 4 | |
71400594 RS |
739 | |
740 | /* A list of previous instructions, with index 0 being the most recent. | |
741 | We need to look back MAX_NOPS instructions when filling delay slots | |
742 | or working around processor errata. We need to look back one | |
743 | instruction further if we're thinking about using history[0] to | |
744 | fill a branch delay slot. */ | |
745 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 746 | |
1e915849 | 747 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
748 | static struct mips_cl_insn nop_insn; |
749 | static struct mips_cl_insn mips16_nop_insn; | |
750 | static struct mips_cl_insn micromips_nop16_insn; | |
751 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
752 | |
753 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
754 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
755 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
756 | ||
757 | /* The size of NOP_INSN in bytes. */ | |
758 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 759 | |
252b5132 RH |
760 | /* If this is set, it points to a frag holding nop instructions which |
761 | were inserted before the start of a noreorder section. If those | |
762 | nops turn out to be unnecessary, the size of the frag can be | |
763 | decreased. */ | |
764 | static fragS *prev_nop_frag; | |
765 | ||
766 | /* The number of nop instructions we created in prev_nop_frag. */ | |
767 | static int prev_nop_frag_holds; | |
768 | ||
769 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 770 | prev_nop_frag. */ |
252b5132 RH |
771 | static int prev_nop_frag_required; |
772 | ||
773 | /* The number of instructions we've seen since prev_nop_frag. */ | |
774 | static int prev_nop_frag_since; | |
775 | ||
776 | /* For ECOFF and ELF, relocations against symbols are done in two | |
777 | parts, with a HI relocation and a LO relocation. Each relocation | |
778 | has only 16 bits of space to store an addend. This means that in | |
779 | order for the linker to handle carries correctly, it must be able | |
780 | to locate both the HI and the LO relocation. This means that the | |
781 | relocations must appear in order in the relocation table. | |
782 | ||
783 | In order to implement this, we keep track of each unmatched HI | |
784 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 785 | corresponding LO relocation. */ |
252b5132 | 786 | |
e972090a NC |
787 | struct mips_hi_fixup |
788 | { | |
252b5132 RH |
789 | /* Next HI fixup. */ |
790 | struct mips_hi_fixup *next; | |
791 | /* This fixup. */ | |
792 | fixS *fixp; | |
793 | /* The section this fixup is in. */ | |
794 | segT seg; | |
795 | }; | |
796 | ||
797 | /* The list of unmatched HI relocs. */ | |
798 | ||
799 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
800 | ||
64bdfcaf RS |
801 | /* The frag containing the last explicit relocation operator. |
802 | Null if explicit relocations have not been used. */ | |
803 | ||
804 | static fragS *prev_reloc_op_frag; | |
805 | ||
252b5132 RH |
806 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
807 | ||
808 | #define X ILLEGAL_REG | |
e972090a NC |
809 | static const int mips32_to_16_reg_map[] = |
810 | { | |
252b5132 RH |
811 | X, X, 2, 3, 4, 5, 6, 7, |
812 | X, X, X, X, X, X, X, X, | |
813 | 0, 1, X, X, X, X, X, X, | |
814 | X, X, X, X, X, X, X, X | |
815 | }; | |
816 | #undef X | |
817 | ||
818 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
819 | ||
e972090a NC |
820 | static const unsigned int mips16_to_32_reg_map[] = |
821 | { | |
252b5132 RH |
822 | 16, 17, 2, 3, 4, 5, 6, 7 |
823 | }; | |
60b63b72 | 824 | |
df58fc94 RS |
825 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
826 | ||
827 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
828 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
829 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
830 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
831 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
832 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
833 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
834 | ||
835 | #define X ILLEGAL_REG | |
836 | /* reg type h: 4, 5, 6. */ | |
837 | static const int mips32_to_micromips_reg_h_map[] = | |
838 | { | |
839 | X, X, X, X, 4, 5, 6, X, | |
840 | X, X, X, X, X, X, X, X, | |
841 | X, X, X, X, X, X, X, X, | |
842 | X, X, X, X, X, X, X, X | |
843 | }; | |
844 | ||
845 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
846 | static const int mips32_to_micromips_reg_m_map[] = | |
847 | { | |
848 | 0, X, 2, 3, X, X, X, X, | |
849 | X, X, X, X, X, X, X, X, | |
850 | 4, 1, 5, 6, 7, X, X, X, | |
851 | X, X, X, X, X, X, X, X | |
852 | }; | |
853 | ||
854 | /* reg type q: 0, 2-7. 17. */ | |
855 | static const int mips32_to_micromips_reg_q_map[] = | |
856 | { | |
857 | 0, X, 2, 3, 4, 5, 6, 7, | |
858 | X, X, X, X, X, X, X, X, | |
859 | X, 1, X, X, X, X, X, X, | |
860 | X, X, X, X, X, X, X, X | |
861 | }; | |
862 | ||
863 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
864 | #undef X | |
865 | ||
866 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
867 | ||
868 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
869 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
870 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
871 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
872 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
873 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
874 | ||
875 | /* The microMIPS registers with type h. */ | |
876 | static const unsigned int micromips_to_32_reg_h_map[] = | |
877 | { | |
878 | 5, 5, 6, 4, 4, 4, 4, 4 | |
879 | }; | |
880 | ||
881 | /* The microMIPS registers with type i. */ | |
882 | static const unsigned int micromips_to_32_reg_i_map[] = | |
883 | { | |
884 | 6, 7, 7, 21, 22, 5, 6, 7 | |
885 | }; | |
886 | ||
887 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
888 | ||
889 | /* The microMIPS registers with type m. */ | |
890 | static const unsigned int micromips_to_32_reg_m_map[] = | |
891 | { | |
892 | 0, 17, 2, 3, 16, 18, 19, 20 | |
893 | }; | |
894 | ||
895 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
896 | ||
897 | /* The microMIPS registers with type q. */ | |
898 | static const unsigned int micromips_to_32_reg_q_map[] = | |
899 | { | |
900 | 0, 17, 2, 3, 4, 5, 6, 7 | |
901 | }; | |
902 | ||
903 | /* microMIPS imm type B. */ | |
904 | static const int micromips_imm_b_map[] = | |
905 | { | |
906 | 1, 4, 8, 12, 16, 20, 24, -1 | |
907 | }; | |
908 | ||
909 | /* microMIPS imm type C. */ | |
910 | static const int micromips_imm_c_map[] = | |
911 | { | |
912 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
913 | }; | |
914 | ||
71400594 RS |
915 | /* Classifies the kind of instructions we're interested in when |
916 | implementing -mfix-vr4120. */ | |
c67a084a NC |
917 | enum fix_vr4120_class |
918 | { | |
71400594 RS |
919 | FIX_VR4120_MACC, |
920 | FIX_VR4120_DMACC, | |
921 | FIX_VR4120_MULT, | |
922 | FIX_VR4120_DMULT, | |
923 | FIX_VR4120_DIV, | |
924 | FIX_VR4120_MTHILO, | |
925 | NUM_FIX_VR4120_CLASSES | |
926 | }; | |
927 | ||
c67a084a NC |
928 | /* ...likewise -mfix-loongson2f-jump. */ |
929 | static bfd_boolean mips_fix_loongson2f_jump; | |
930 | ||
931 | /* ...likewise -mfix-loongson2f-nop. */ | |
932 | static bfd_boolean mips_fix_loongson2f_nop; | |
933 | ||
934 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
935 | static bfd_boolean mips_fix_loongson2f; | |
936 | ||
71400594 RS |
937 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
938 | there must be at least one other instruction between an instruction | |
939 | of type X and an instruction of type Y. */ | |
940 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
941 | ||
942 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 943 | static int mips_fix_vr4120; |
4a6a3df4 | 944 | |
7d8e00cf RS |
945 | /* ...likewise -mfix-vr4130. */ |
946 | static int mips_fix_vr4130; | |
947 | ||
6a32d874 CM |
948 | /* ...likewise -mfix-24k. */ |
949 | static int mips_fix_24k; | |
950 | ||
d954098f DD |
951 | /* ...likewise -mfix-cn63xxp1 */ |
952 | static bfd_boolean mips_fix_cn63xxp1; | |
953 | ||
4a6a3df4 AO |
954 | /* We don't relax branches by default, since this causes us to expand |
955 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
956 | fail to compute the offset before expanding the macro to the most | |
957 | efficient expansion. */ | |
958 | ||
959 | static int mips_relax_branch; | |
252b5132 | 960 | \f |
4d7206a2 RS |
961 | /* The expansion of many macros depends on the type of symbol that |
962 | they refer to. For example, when generating position-dependent code, | |
963 | a macro that refers to a symbol may have two different expansions, | |
964 | one which uses GP-relative addresses and one which uses absolute | |
965 | addresses. When generating SVR4-style PIC, a macro may have | |
966 | different expansions for local and global symbols. | |
967 | ||
968 | We handle these situations by generating both sequences and putting | |
969 | them in variant frags. In position-dependent code, the first sequence | |
970 | will be the GP-relative one and the second sequence will be the | |
971 | absolute one. In SVR4 PIC, the first sequence will be for global | |
972 | symbols and the second will be for local symbols. | |
973 | ||
584892a6 RS |
974 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
975 | SECOND are the lengths of the two sequences in bytes. These fields | |
976 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
977 | the subtype has the following flags: | |
4d7206a2 | 978 | |
584892a6 RS |
979 | RELAX_USE_SECOND |
980 | Set if it has been decided that we should use the second | |
981 | sequence instead of the first. | |
982 | ||
983 | RELAX_SECOND_LONGER | |
984 | Set in the first variant frag if the macro's second implementation | |
985 | is longer than its first. This refers to the macro as a whole, | |
986 | not an individual relaxation. | |
987 | ||
988 | RELAX_NOMACRO | |
989 | Set in the first variant frag if the macro appeared in a .set nomacro | |
990 | block and if one alternative requires a warning but the other does not. | |
991 | ||
992 | RELAX_DELAY_SLOT | |
993 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
994 | delay slot. | |
4d7206a2 | 995 | |
df58fc94 RS |
996 | RELAX_DELAY_SLOT_16BIT |
997 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
998 | 16-bit instruction. | |
999 | ||
1000 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1001 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1002 | the macro is of the wrong size for the branch delay slot. | |
1003 | ||
1004 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1005 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1006 | the macro is of the wrong size for the branch delay slot. | |
1007 | ||
4d7206a2 RS |
1008 | The frag's "opcode" points to the first fixup for relaxable code. |
1009 | ||
1010 | Relaxable macros are generated using a sequence such as: | |
1011 | ||
1012 | relax_start (SYMBOL); | |
1013 | ... generate first expansion ... | |
1014 | relax_switch (); | |
1015 | ... generate second expansion ... | |
1016 | relax_end (); | |
1017 | ||
1018 | The code and fixups for the unwanted alternative are discarded | |
1019 | by md_convert_frag. */ | |
584892a6 | 1020 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1021 | |
584892a6 RS |
1022 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1023 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1024 | #define RELAX_USE_SECOND 0x10000 | |
1025 | #define RELAX_SECOND_LONGER 0x20000 | |
1026 | #define RELAX_NOMACRO 0x40000 | |
1027 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1028 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1029 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1030 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1031 | |
4a6a3df4 AO |
1032 | /* Branch without likely bit. If label is out of range, we turn: |
1033 | ||
1034 | beq reg1, reg2, label | |
1035 | delay slot | |
1036 | ||
1037 | into | |
1038 | ||
1039 | bne reg1, reg2, 0f | |
1040 | nop | |
1041 | j label | |
1042 | 0: delay slot | |
1043 | ||
1044 | with the following opcode replacements: | |
1045 | ||
1046 | beq <-> bne | |
1047 | blez <-> bgtz | |
1048 | bltz <-> bgez | |
1049 | bc1f <-> bc1t | |
1050 | ||
1051 | bltzal <-> bgezal (with jal label instead of j label) | |
1052 | ||
1053 | Even though keeping the delay slot instruction in the delay slot of | |
1054 | the branch would be more efficient, it would be very tricky to do | |
1055 | correctly, because we'd have to introduce a variable frag *after* | |
1056 | the delay slot instruction, and expand that instead. Let's do it | |
1057 | the easy way for now, even if the branch-not-taken case now costs | |
1058 | one additional instruction. Out-of-range branches are not supposed | |
1059 | to be common, anyway. | |
1060 | ||
1061 | Branch likely. If label is out of range, we turn: | |
1062 | ||
1063 | beql reg1, reg2, label | |
1064 | delay slot (annulled if branch not taken) | |
1065 | ||
1066 | into | |
1067 | ||
1068 | beql reg1, reg2, 1f | |
1069 | nop | |
1070 | beql $0, $0, 2f | |
1071 | nop | |
1072 | 1: j[al] label | |
1073 | delay slot (executed only if branch taken) | |
1074 | 2: | |
1075 | ||
1076 | It would be possible to generate a shorter sequence by losing the | |
1077 | likely bit, generating something like: | |
b34976b6 | 1078 | |
4a6a3df4 AO |
1079 | bne reg1, reg2, 0f |
1080 | nop | |
1081 | j[al] label | |
1082 | delay slot (executed only if branch taken) | |
1083 | 0: | |
1084 | ||
1085 | beql -> bne | |
1086 | bnel -> beq | |
1087 | blezl -> bgtz | |
1088 | bgtzl -> blez | |
1089 | bltzl -> bgez | |
1090 | bgezl -> bltz | |
1091 | bc1fl -> bc1t | |
1092 | bc1tl -> bc1f | |
1093 | ||
1094 | bltzall -> bgezal (with jal label instead of j label) | |
1095 | bgezall -> bltzal (ditto) | |
1096 | ||
1097 | ||
1098 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1099 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1100 | ((relax_substateT) \ | |
1101 | (0xc0000000 \ | |
1102 | | ((at) & 0x1f) \ | |
1103 | | ((toofar) ? 0x20 : 0) \ | |
1104 | | ((link) ? 0x40 : 0) \ | |
1105 | | ((likely) ? 0x80 : 0) \ | |
1106 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1107 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1108 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1109 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1110 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1111 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1112 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1113 | |
252b5132 RH |
1114 | /* For mips16 code, we use an entirely different form of relaxation. |
1115 | mips16 supports two versions of most instructions which take | |
1116 | immediate values: a small one which takes some small value, and a | |
1117 | larger one which takes a 16 bit value. Since branches also follow | |
1118 | this pattern, relaxing these values is required. | |
1119 | ||
1120 | We can assemble both mips16 and normal MIPS code in a single | |
1121 | object. Therefore, we need to support this type of relaxation at | |
1122 | the same time that we support the relaxation described above. We | |
1123 | use the high bit of the subtype field to distinguish these cases. | |
1124 | ||
1125 | The information we store for this type of relaxation is the | |
1126 | argument code found in the opcode file for this relocation, whether | |
1127 | the user explicitly requested a small or extended form, and whether | |
1128 | the relocation is in a jump or jal delay slot. That tells us the | |
1129 | size of the value, and how it should be stored. We also store | |
1130 | whether the fragment is considered to be extended or not. We also | |
1131 | store whether this is known to be a branch to a different section, | |
1132 | whether we have tried to relax this frag yet, and whether we have | |
1133 | ever extended a PC relative fragment because of a shift count. */ | |
1134 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1135 | (0x80000000 \ | |
1136 | | ((type) & 0xff) \ | |
1137 | | ((small) ? 0x100 : 0) \ | |
1138 | | ((ext) ? 0x200 : 0) \ | |
1139 | | ((dslot) ? 0x400 : 0) \ | |
1140 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1141 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1142 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1143 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1144 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1145 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1146 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1147 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1148 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1149 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1150 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1151 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1152 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1153 | |
df58fc94 RS |
1154 | /* For microMIPS code, we use relaxation similar to one we use for |
1155 | MIPS16 code. Some instructions that take immediate values support | |
1156 | two encodings: a small one which takes some small value, and a | |
1157 | larger one which takes a 16 bit value. As some branches also follow | |
1158 | this pattern, relaxing these values is required. | |
1159 | ||
1160 | We can assemble both microMIPS and normal MIPS code in a single | |
1161 | object. Therefore, we need to support this type of relaxation at | |
1162 | the same time that we support the relaxation described above. We | |
1163 | use one of the high bits of the subtype field to distinguish these | |
1164 | cases. | |
1165 | ||
1166 | The information we store for this type of relaxation is the argument | |
1167 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1168 | selected as the assembler temporary, whether the branch is |
1169 | unconditional, whether it is compact, whether it stores the link | |
1170 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1171 | branches to a sequence of instructions is enabled, and whether the | |
1172 | displacement of a branch is too large to fit as an immediate argument | |
1173 | of a 16-bit and a 32-bit branch, respectively. */ | |
1174 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1175 | relax32, toofar16, toofar32) \ | |
1176 | (0x40000000 \ | |
1177 | | ((type) & 0xff) \ | |
1178 | | (((at) & 0x1f) << 8) \ | |
1179 | | ((uncond) ? 0x2000 : 0) \ | |
1180 | | ((compact) ? 0x4000 : 0) \ | |
1181 | | ((link) ? 0x8000 : 0) \ | |
1182 | | ((relax32) ? 0x10000 : 0) \ | |
1183 | | ((toofar16) ? 0x20000 : 0) \ | |
1184 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1185 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1186 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1187 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1188 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1189 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1190 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1191 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1192 | ||
1193 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1194 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1195 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1196 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1197 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1198 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1199 | |
43c0598f RS |
1200 | /* Sign-extend 16-bit value X. */ |
1201 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1202 | ||
885add95 CD |
1203 | /* Is the given value a sign-extended 32-bit value? */ |
1204 | #define IS_SEXT_32BIT_NUM(x) \ | |
1205 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1206 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1207 | ||
1208 | /* Is the given value a sign-extended 16-bit value? */ | |
1209 | #define IS_SEXT_16BIT_NUM(x) \ | |
1210 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1211 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1212 | ||
df58fc94 RS |
1213 | /* Is the given value a sign-extended 12-bit value? */ |
1214 | #define IS_SEXT_12BIT_NUM(x) \ | |
1215 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1216 | ||
2051e8c4 MR |
1217 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1218 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1219 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1220 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1221 | ||
bf12938e RS |
1222 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1223 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1224 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1225 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1226 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1227 | ||
1228 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1229 | SHIFT places. */ | |
1230 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1231 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1232 | ||
1233 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1234 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1235 | ||
1236 | include/opcode/mips.h specifies operand fields using the macros | |
1237 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1238 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1239 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1240 | do \ | |
1241 | if (!(MICROMIPS)) \ | |
1242 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1243 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1244 | else \ | |
1245 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1246 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1247 | while (0) | |
bf12938e RS |
1248 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1249 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1250 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1251 | ||
1252 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1253 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1254 | (!(MICROMIPS) \ | |
1255 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1256 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1257 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1258 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1259 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1260 | MIPS16OP_MASK_##FIELD, \ | |
1261 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1262 | |
1263 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1264 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1265 | \f |
df58fc94 RS |
1266 | /* Whether or not we are emitting a branch-likely macro. */ |
1267 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1268 | ||
4d7206a2 RS |
1269 | /* Global variables used when generating relaxable macros. See the |
1270 | comment above RELAX_ENCODE for more details about how relaxation | |
1271 | is used. */ | |
1272 | static struct { | |
1273 | /* 0 if we're not emitting a relaxable macro. | |
1274 | 1 if we're emitting the first of the two relaxation alternatives. | |
1275 | 2 if we're emitting the second alternative. */ | |
1276 | int sequence; | |
1277 | ||
1278 | /* The first relaxable fixup in the current frag. (In other words, | |
1279 | the first fixup that refers to relaxable code.) */ | |
1280 | fixS *first_fixup; | |
1281 | ||
1282 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1283 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1284 | unsigned int sizes[2]; | |
1285 | ||
1286 | /* The symbol on which the choice of sequence depends. */ | |
1287 | symbolS *symbol; | |
1288 | } mips_relax; | |
252b5132 | 1289 | \f |
584892a6 RS |
1290 | /* Global variables used to decide whether a macro needs a warning. */ |
1291 | static struct { | |
1292 | /* True if the macro is in a branch delay slot. */ | |
1293 | bfd_boolean delay_slot_p; | |
1294 | ||
df58fc94 RS |
1295 | /* Set to the length in bytes required if the macro is in a delay slot |
1296 | that requires a specific length of instruction, otherwise zero. */ | |
1297 | unsigned int delay_slot_length; | |
1298 | ||
584892a6 RS |
1299 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1300 | in bytes and sizes[1] is the length of the second alternative. | |
1301 | For non-relaxable macros, both elements give the length of the | |
1302 | macro in bytes. */ | |
1303 | unsigned int sizes[2]; | |
1304 | ||
df58fc94 RS |
1305 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1306 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1307 | is the length of the first instruction of the second alternative. | |
1308 | For non-relaxable macros, both elements give the length of the first | |
1309 | instruction in bytes. | |
1310 | ||
1311 | Set to zero if we haven't yet seen the first instruction. */ | |
1312 | unsigned int first_insn_sizes[2]; | |
1313 | ||
1314 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1315 | first alternative and insns[1] is the number of instructions for the | |
1316 | second alternative. | |
1317 | ||
1318 | For non-relaxable macros, both elements give the number of | |
1319 | instructions for the macro. */ | |
1320 | unsigned int insns[2]; | |
1321 | ||
584892a6 RS |
1322 | /* The first variant frag for this macro. */ |
1323 | fragS *first_frag; | |
1324 | } mips_macro_warning; | |
1325 | \f | |
252b5132 RH |
1326 | /* Prototypes for static functions. */ |
1327 | ||
252b5132 RH |
1328 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1329 | ||
b34976b6 | 1330 | static void append_insn |
df58fc94 RS |
1331 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1332 | bfd_boolean expansionp); | |
7d10b47d | 1333 | static void mips_no_prev_insn (void); |
c67a084a | 1334 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1335 | static void mips16_macro_build |
03ea81db | 1336 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1337 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1338 | static void macro_start (void); |
1339 | static void macro_end (void); | |
17a2f251 TS |
1340 | static void macro (struct mips_cl_insn * ip); |
1341 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1342 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1343 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1344 | static void mips16_immed |
43c0598f RS |
1345 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1346 | unsigned int, unsigned long *); | |
5e0116d5 | 1347 | static size_t my_getSmallExpression |
17a2f251 TS |
1348 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1349 | static void my_getExpression (expressionS *, char *); | |
1350 | static void s_align (int); | |
1351 | static void s_change_sec (int); | |
1352 | static void s_change_section (int); | |
1353 | static void s_cons (int); | |
1354 | static void s_float_cons (int); | |
1355 | static void s_mips_globl (int); | |
1356 | static void s_option (int); | |
1357 | static void s_mipsset (int); | |
1358 | static void s_abicalls (int); | |
1359 | static void s_cpload (int); | |
1360 | static void s_cpsetup (int); | |
1361 | static void s_cplocal (int); | |
1362 | static void s_cprestore (int); | |
1363 | static void s_cpreturn (int); | |
741d6ea8 JM |
1364 | static void s_dtprelword (int); |
1365 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1366 | static void s_tprelword (int); |
1367 | static void s_tpreldword (int); | |
17a2f251 TS |
1368 | static void s_gpvalue (int); |
1369 | static void s_gpword (int); | |
1370 | static void s_gpdword (int); | |
1371 | static void s_cpadd (int); | |
1372 | static void s_insn (int); | |
1373 | static void md_obj_begin (void); | |
1374 | static void md_obj_end (void); | |
1375 | static void s_mips_ent (int); | |
1376 | static void s_mips_end (int); | |
1377 | static void s_mips_frame (int); | |
1378 | static void s_mips_mask (int reg_type); | |
1379 | static void s_mips_stab (int); | |
1380 | static void s_mips_weakext (int); | |
1381 | static void s_mips_file (int); | |
1382 | static void s_mips_loc (int); | |
1383 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1384 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1385 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1386 | static int validate_micromips_insn (const struct mips_opcode *); |
1387 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1388 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1389 | |
1390 | /* Table and functions used to map between CPU/ISA names, and | |
1391 | ISA levels, and CPU numbers. */ | |
1392 | ||
e972090a NC |
1393 | struct mips_cpu_info |
1394 | { | |
e7af610e | 1395 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1396 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1397 | int isa; /* ISA level. */ |
1398 | int cpu; /* CPU number (default CPU if ISA). */ | |
1399 | }; | |
1400 | ||
ad3fea08 TS |
1401 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1402 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1403 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1404 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1405 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1406 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1407 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1408 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
b015e599 | 1409 | #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */ |
ad3fea08 | 1410 | |
17a2f251 TS |
1411 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1412 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1413 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1414 | \f |
1415 | /* Pseudo-op table. | |
1416 | ||
1417 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1418 | should be defined here, but are currently unsupported: .alias, | |
1419 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1420 | ||
1421 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1422 | specific to the type of debugging information being generated, and | |
1423 | should be defined by the object format: .aent, .begin, .bend, | |
1424 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1425 | .vreg. | |
1426 | ||
1427 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1428 | not MIPS CPU specific, but are also not specific to the object file | |
1429 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1430 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1431 | |
e972090a NC |
1432 | static const pseudo_typeS mips_pseudo_table[] = |
1433 | { | |
beae10d5 | 1434 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1435 | {"option", s_option, 0}, |
1436 | {"set", s_mipsset, 0}, | |
1437 | {"rdata", s_change_sec, 'r'}, | |
1438 | {"sdata", s_change_sec, 's'}, | |
1439 | {"livereg", s_ignore, 0}, | |
1440 | {"abicalls", s_abicalls, 0}, | |
1441 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1442 | {"cpsetup", s_cpsetup, 0}, |
1443 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1444 | {"cprestore", s_cprestore, 0}, |
6478892d | 1445 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1446 | {"dtprelword", s_dtprelword, 0}, |
1447 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1448 | {"tprelword", s_tprelword, 0}, |
1449 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1450 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1451 | {"gpword", s_gpword, 0}, |
10181a0d | 1452 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1453 | {"cpadd", s_cpadd, 0}, |
1454 | {"insn", s_insn, 0}, | |
1455 | ||
beae10d5 | 1456 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1457 | chips. */ |
38a57ae7 | 1458 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1459 | {"bss", s_change_sec, 'b'}, |
1460 | {"err", s_err, 0}, | |
1461 | {"half", s_cons, 1}, | |
1462 | {"dword", s_cons, 3}, | |
1463 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1464 | {"origin", s_org, 0}, |
1465 | {"repeat", s_rept, 0}, | |
252b5132 | 1466 | |
998b3c36 MR |
1467 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1468 | {"sbss", s_change_sec, 'B'}, | |
1469 | ||
beae10d5 | 1470 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1471 | here for one reason or another. */ |
1472 | {"align", s_align, 0}, | |
1473 | {"byte", s_cons, 0}, | |
1474 | {"data", s_change_sec, 'd'}, | |
1475 | {"double", s_float_cons, 'd'}, | |
1476 | {"float", s_float_cons, 'f'}, | |
1477 | {"globl", s_mips_globl, 0}, | |
1478 | {"global", s_mips_globl, 0}, | |
1479 | {"hword", s_cons, 1}, | |
1480 | {"int", s_cons, 2}, | |
1481 | {"long", s_cons, 2}, | |
1482 | {"octa", s_cons, 4}, | |
1483 | {"quad", s_cons, 3}, | |
cca86cc8 | 1484 | {"section", s_change_section, 0}, |
252b5132 RH |
1485 | {"short", s_cons, 1}, |
1486 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1487 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1488 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1489 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1490 | {"text", s_change_sec, 't'}, |
1491 | {"word", s_cons, 2}, | |
add56521 | 1492 | |
add56521 | 1493 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1494 | |
43841e91 | 1495 | { NULL, NULL, 0 }, |
252b5132 RH |
1496 | }; |
1497 | ||
e972090a NC |
1498 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1499 | { | |
beae10d5 KH |
1500 | /* These pseudo-ops should be defined by the object file format. |
1501 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1502 | {"aent", s_mips_ent, 1}, |
1503 | {"bgnb", s_ignore, 0}, | |
1504 | {"end", s_mips_end, 0}, | |
1505 | {"endb", s_ignore, 0}, | |
1506 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1507 | {"file", s_mips_file, 0}, |
252b5132 RH |
1508 | {"fmask", s_mips_mask, 'F'}, |
1509 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1510 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1511 | {"mask", s_mips_mask, 'R'}, |
1512 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1513 | { NULL, NULL, 0 }, |
252b5132 RH |
1514 | }; |
1515 | ||
3ae8dd8d MR |
1516 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1517 | purpose of the `.dc.a' internal pseudo-op. */ | |
1518 | ||
1519 | int | |
1520 | mips_address_bytes (void) | |
1521 | { | |
1522 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1523 | } | |
1524 | ||
17a2f251 | 1525 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1526 | |
1527 | void | |
17a2f251 | 1528 | mips_pop_insert (void) |
252b5132 RH |
1529 | { |
1530 | pop_insert (mips_pseudo_table); | |
1531 | if (! ECOFF_DEBUGGING) | |
1532 | pop_insert (mips_nonecoff_pseudo_table); | |
1533 | } | |
1534 | \f | |
1535 | /* Symbols labelling the current insn. */ | |
1536 | ||
e972090a NC |
1537 | struct insn_label_list |
1538 | { | |
252b5132 RH |
1539 | struct insn_label_list *next; |
1540 | symbolS *label; | |
1541 | }; | |
1542 | ||
252b5132 | 1543 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1544 | #define label_list tc_segment_info_data.labels |
252b5132 | 1545 | |
17a2f251 | 1546 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1547 | static void mips_mark_labels (void); |
1548 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1549 | |
1550 | static inline void | |
17a2f251 | 1551 | mips_clear_insn_labels (void) |
252b5132 RH |
1552 | { |
1553 | register struct insn_label_list **pl; | |
a8dbcb85 | 1554 | segment_info_type *si; |
252b5132 | 1555 | |
a8dbcb85 TS |
1556 | if (now_seg) |
1557 | { | |
1558 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1559 | ; | |
1560 | ||
1561 | si = seg_info (now_seg); | |
1562 | *pl = si->label_list; | |
1563 | si->label_list = NULL; | |
1564 | } | |
252b5132 | 1565 | } |
a8dbcb85 | 1566 | |
df58fc94 RS |
1567 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1568 | ||
1569 | static inline void | |
1570 | mips_mark_labels (void) | |
1571 | { | |
1572 | if (HAVE_CODE_COMPRESSION) | |
1573 | mips_compressed_mark_labels (); | |
1574 | } | |
252b5132 RH |
1575 | \f |
1576 | static char *expr_end; | |
1577 | ||
1578 | /* Expressions which appear in instructions. These are set by | |
1579 | mips_ip. */ | |
1580 | ||
1581 | static expressionS imm_expr; | |
5f74bc13 | 1582 | static expressionS imm2_expr; |
252b5132 RH |
1583 | static expressionS offset_expr; |
1584 | ||
1585 | /* Relocs associated with imm_expr and offset_expr. */ | |
1586 | ||
f6688943 TS |
1587 | static bfd_reloc_code_real_type imm_reloc[3] |
1588 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1589 | static bfd_reloc_code_real_type offset_reloc[3] | |
1590 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1591 | |
df58fc94 RS |
1592 | /* This is set to the resulting size of the instruction to be produced |
1593 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1594 | explicit size is supplied. */ | |
252b5132 | 1595 | |
df58fc94 | 1596 | static unsigned int forced_insn_length; |
252b5132 | 1597 | |
e1b47bd5 RS |
1598 | /* True if we are assembling an instruction. All dot symbols defined during |
1599 | this time should be treated as code labels. */ | |
1600 | ||
1601 | static bfd_boolean mips_assembling_insn; | |
1602 | ||
7ed4a06a | 1603 | #ifdef OBJ_ELF |
ecb4347a DJ |
1604 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1605 | ECOFF debugging. */ | |
252b5132 RH |
1606 | |
1607 | static segT pdr_seg; | |
7ed4a06a | 1608 | #endif |
252b5132 | 1609 | |
e013f690 TS |
1610 | /* The default target format to use. */ |
1611 | ||
aeffff67 RS |
1612 | #if defined (TE_FreeBSD) |
1613 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1614 | #elif defined (TE_TMIPS) | |
1615 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1616 | #else | |
1617 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1618 | #endif | |
1619 | ||
e013f690 | 1620 | const char * |
17a2f251 | 1621 | mips_target_format (void) |
e013f690 TS |
1622 | { |
1623 | switch (OUTPUT_FLAVOR) | |
1624 | { | |
e013f690 TS |
1625 | case bfd_target_ecoff_flavour: |
1626 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1627 | case bfd_target_coff_flavour: | |
1628 | return "pe-mips"; | |
1629 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1630 | #ifdef TE_VXWORKS |
1631 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1632 | return (target_big_endian | |
1633 | ? "elf32-bigmips-vxworks" | |
1634 | : "elf32-littlemips-vxworks"); | |
1635 | #endif | |
e013f690 | 1636 | return (target_big_endian |
cfe86eaa | 1637 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1638 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1639 | : (HAVE_NEWABI |
aeffff67 RS |
1640 | ? ELF_TARGET ("elf32-n", "big") |
1641 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1642 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1643 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1644 | : (HAVE_NEWABI |
aeffff67 RS |
1645 | ? ELF_TARGET ("elf32-n", "little") |
1646 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1647 | default: |
1648 | abort (); | |
1649 | return NULL; | |
1650 | } | |
1651 | } | |
1652 | ||
df58fc94 RS |
1653 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1654 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1655 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1656 | major opcode) will require further modifications to the opcode | |
1657 | table. */ | |
1658 | ||
1659 | static inline unsigned int | |
1660 | micromips_insn_length (const struct mips_opcode *mo) | |
1661 | { | |
1662 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1663 | } | |
1664 | ||
5c04167a RS |
1665 | /* Return the length of MIPS16 instruction OPCODE. */ |
1666 | ||
1667 | static inline unsigned int | |
1668 | mips16_opcode_length (unsigned long opcode) | |
1669 | { | |
1670 | return (opcode >> 16) == 0 ? 2 : 4; | |
1671 | } | |
1672 | ||
1e915849 RS |
1673 | /* Return the length of instruction INSN. */ |
1674 | ||
1675 | static inline unsigned int | |
1676 | insn_length (const struct mips_cl_insn *insn) | |
1677 | { | |
df58fc94 RS |
1678 | if (mips_opts.micromips) |
1679 | return micromips_insn_length (insn->insn_mo); | |
1680 | else if (mips_opts.mips16) | |
5c04167a | 1681 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1682 | else |
1e915849 | 1683 | return 4; |
1e915849 RS |
1684 | } |
1685 | ||
1686 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1687 | ||
1688 | static void | |
1689 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1690 | { | |
1691 | size_t i; | |
1692 | ||
1693 | insn->insn_mo = mo; | |
1e915849 RS |
1694 | insn->insn_opcode = mo->match; |
1695 | insn->frag = NULL; | |
1696 | insn->where = 0; | |
1697 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1698 | insn->fixp[i] = NULL; | |
1699 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1700 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1701 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1702 | insn->complete_p = 0; |
e407c74b | 1703 | insn->cleared_p = 0; |
1e915849 RS |
1704 | } |
1705 | ||
df58fc94 | 1706 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1707 | |
1708 | static void | |
df58fc94 | 1709 | mips_record_compressed_mode (void) |
742a56fe RS |
1710 | { |
1711 | segment_info_type *si; | |
1712 | ||
1713 | si = seg_info (now_seg); | |
1714 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1715 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1716 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1717 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1718 | } |
1719 | ||
4d68580a RS |
1720 | /* Read a standard MIPS instruction from BUF. */ |
1721 | ||
1722 | static unsigned long | |
1723 | read_insn (char *buf) | |
1724 | { | |
1725 | if (target_big_endian) | |
1726 | return bfd_getb32 ((bfd_byte *) buf); | |
1727 | else | |
1728 | return bfd_getl32 ((bfd_byte *) buf); | |
1729 | } | |
1730 | ||
1731 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1732 | the next byte. */ | |
1733 | ||
1734 | static char * | |
1735 | write_insn (char *buf, unsigned int insn) | |
1736 | { | |
1737 | md_number_to_chars (buf, insn, 4); | |
1738 | return buf + 4; | |
1739 | } | |
1740 | ||
1741 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1742 | has length LENGTH. */ | |
1743 | ||
1744 | static unsigned long | |
1745 | read_compressed_insn (char *buf, unsigned int length) | |
1746 | { | |
1747 | unsigned long insn; | |
1748 | unsigned int i; | |
1749 | ||
1750 | insn = 0; | |
1751 | for (i = 0; i < length; i += 2) | |
1752 | { | |
1753 | insn <<= 16; | |
1754 | if (target_big_endian) | |
1755 | insn |= bfd_getb16 ((char *) buf); | |
1756 | else | |
1757 | insn |= bfd_getl16 ((char *) buf); | |
1758 | buf += 2; | |
1759 | } | |
1760 | return insn; | |
1761 | } | |
1762 | ||
5c04167a RS |
1763 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1764 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1765 | ||
1766 | static char * | |
1767 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1768 | { | |
1769 | unsigned int i; | |
1770 | ||
1771 | for (i = 0; i < length; i += 2) | |
1772 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1773 | return buf + length; | |
1774 | } | |
1775 | ||
1e915849 RS |
1776 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1777 | ||
1778 | static void | |
1779 | install_insn (const struct mips_cl_insn *insn) | |
1780 | { | |
1781 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1782 | if (HAVE_CODE_COMPRESSION) |
1783 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1784 | else |
4d68580a | 1785 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1786 | mips_record_compressed_mode (); |
1e915849 RS |
1787 | } |
1788 | ||
1789 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1790 | and install the opcode in the new location. */ | |
1791 | ||
1792 | static void | |
1793 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1794 | { | |
1795 | size_t i; | |
1796 | ||
1797 | insn->frag = frag; | |
1798 | insn->where = where; | |
1799 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1800 | if (insn->fixp[i] != NULL) | |
1801 | { | |
1802 | insn->fixp[i]->fx_frag = frag; | |
1803 | insn->fixp[i]->fx_where = where; | |
1804 | } | |
1805 | install_insn (insn); | |
1806 | } | |
1807 | ||
1808 | /* Add INSN to the end of the output. */ | |
1809 | ||
1810 | static void | |
1811 | add_fixed_insn (struct mips_cl_insn *insn) | |
1812 | { | |
1813 | char *f = frag_more (insn_length (insn)); | |
1814 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1815 | } | |
1816 | ||
1817 | /* Start a variant frag and move INSN to the start of the variant part, | |
1818 | marking it as fixed. The other arguments are as for frag_var. */ | |
1819 | ||
1820 | static void | |
1821 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1822 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1823 | { | |
1824 | frag_grow (max_chars); | |
1825 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1826 | insn->fixed_p = 1; | |
1827 | frag_var (rs_machine_dependent, max_chars, var, | |
1828 | subtype, symbol, offset, NULL); | |
1829 | } | |
1830 | ||
1831 | /* Insert N copies of INSN into the history buffer, starting at | |
1832 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1833 | ||
1834 | static void | |
1835 | insert_into_history (unsigned int first, unsigned int n, | |
1836 | const struct mips_cl_insn *insn) | |
1837 | { | |
1838 | if (mips_relax.sequence != 2) | |
1839 | { | |
1840 | unsigned int i; | |
1841 | ||
1842 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1843 | if (i >= first + n) | |
1844 | history[i] = history[i - n]; | |
1845 | else | |
1846 | history[i] = *insn; | |
1847 | } | |
1848 | } | |
1849 | ||
71400594 RS |
1850 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1851 | the idea is to make it obvious at a glance that each errata is | |
1852 | included. */ | |
1853 | ||
1854 | static void | |
1855 | init_vr4120_conflicts (void) | |
1856 | { | |
1857 | #define CONFLICT(FIRST, SECOND) \ | |
1858 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1859 | ||
1860 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1861 | CONFLICT (MACC, DIV); | |
1862 | CONFLICT (DMACC, DIV); | |
1863 | ||
1864 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1865 | CONFLICT (DMULT, DMULT); | |
1866 | CONFLICT (DMULT, DMACC); | |
1867 | CONFLICT (DMACC, DMULT); | |
1868 | CONFLICT (DMACC, DMACC); | |
1869 | ||
1870 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1871 | CONFLICT (MACC, MTHILO); | |
1872 | CONFLICT (DMACC, MTHILO); | |
1873 | ||
1874 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1875 | instruction is executed immediately after a MACC or DMACC | |
1876 | instruction, the result of [either instruction] is incorrect." */ | |
1877 | CONFLICT (MACC, MULT); | |
1878 | CONFLICT (MACC, DMULT); | |
1879 | CONFLICT (DMACC, MULT); | |
1880 | CONFLICT (DMACC, DMULT); | |
1881 | ||
1882 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1883 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1884 | DDIV or DDIVU instruction, the result of the MACC or | |
1885 | DMACC instruction is incorrect.". */ | |
1886 | CONFLICT (DMULT, MACC); | |
1887 | CONFLICT (DMULT, DMACC); | |
1888 | CONFLICT (DIV, MACC); | |
1889 | CONFLICT (DIV, DMACC); | |
1890 | ||
1891 | #undef CONFLICT | |
1892 | } | |
1893 | ||
707bfff6 TS |
1894 | struct regname { |
1895 | const char *name; | |
1896 | unsigned int num; | |
1897 | }; | |
1898 | ||
1899 | #define RTYPE_MASK 0x1ff00 | |
1900 | #define RTYPE_NUM 0x00100 | |
1901 | #define RTYPE_FPU 0x00200 | |
1902 | #define RTYPE_FCC 0x00400 | |
1903 | #define RTYPE_VEC 0x00800 | |
1904 | #define RTYPE_GP 0x01000 | |
1905 | #define RTYPE_CP0 0x02000 | |
1906 | #define RTYPE_PC 0x04000 | |
1907 | #define RTYPE_ACC 0x08000 | |
1908 | #define RTYPE_CCC 0x10000 | |
1909 | #define RNUM_MASK 0x000ff | |
1910 | #define RWARN 0x80000 | |
1911 | ||
1912 | #define GENERIC_REGISTER_NUMBERS \ | |
1913 | {"$0", RTYPE_NUM | 0}, \ | |
1914 | {"$1", RTYPE_NUM | 1}, \ | |
1915 | {"$2", RTYPE_NUM | 2}, \ | |
1916 | {"$3", RTYPE_NUM | 3}, \ | |
1917 | {"$4", RTYPE_NUM | 4}, \ | |
1918 | {"$5", RTYPE_NUM | 5}, \ | |
1919 | {"$6", RTYPE_NUM | 6}, \ | |
1920 | {"$7", RTYPE_NUM | 7}, \ | |
1921 | {"$8", RTYPE_NUM | 8}, \ | |
1922 | {"$9", RTYPE_NUM | 9}, \ | |
1923 | {"$10", RTYPE_NUM | 10}, \ | |
1924 | {"$11", RTYPE_NUM | 11}, \ | |
1925 | {"$12", RTYPE_NUM | 12}, \ | |
1926 | {"$13", RTYPE_NUM | 13}, \ | |
1927 | {"$14", RTYPE_NUM | 14}, \ | |
1928 | {"$15", RTYPE_NUM | 15}, \ | |
1929 | {"$16", RTYPE_NUM | 16}, \ | |
1930 | {"$17", RTYPE_NUM | 17}, \ | |
1931 | {"$18", RTYPE_NUM | 18}, \ | |
1932 | {"$19", RTYPE_NUM | 19}, \ | |
1933 | {"$20", RTYPE_NUM | 20}, \ | |
1934 | {"$21", RTYPE_NUM | 21}, \ | |
1935 | {"$22", RTYPE_NUM | 22}, \ | |
1936 | {"$23", RTYPE_NUM | 23}, \ | |
1937 | {"$24", RTYPE_NUM | 24}, \ | |
1938 | {"$25", RTYPE_NUM | 25}, \ | |
1939 | {"$26", RTYPE_NUM | 26}, \ | |
1940 | {"$27", RTYPE_NUM | 27}, \ | |
1941 | {"$28", RTYPE_NUM | 28}, \ | |
1942 | {"$29", RTYPE_NUM | 29}, \ | |
1943 | {"$30", RTYPE_NUM | 30}, \ | |
1944 | {"$31", RTYPE_NUM | 31} | |
1945 | ||
1946 | #define FPU_REGISTER_NAMES \ | |
1947 | {"$f0", RTYPE_FPU | 0}, \ | |
1948 | {"$f1", RTYPE_FPU | 1}, \ | |
1949 | {"$f2", RTYPE_FPU | 2}, \ | |
1950 | {"$f3", RTYPE_FPU | 3}, \ | |
1951 | {"$f4", RTYPE_FPU | 4}, \ | |
1952 | {"$f5", RTYPE_FPU | 5}, \ | |
1953 | {"$f6", RTYPE_FPU | 6}, \ | |
1954 | {"$f7", RTYPE_FPU | 7}, \ | |
1955 | {"$f8", RTYPE_FPU | 8}, \ | |
1956 | {"$f9", RTYPE_FPU | 9}, \ | |
1957 | {"$f10", RTYPE_FPU | 10}, \ | |
1958 | {"$f11", RTYPE_FPU | 11}, \ | |
1959 | {"$f12", RTYPE_FPU | 12}, \ | |
1960 | {"$f13", RTYPE_FPU | 13}, \ | |
1961 | {"$f14", RTYPE_FPU | 14}, \ | |
1962 | {"$f15", RTYPE_FPU | 15}, \ | |
1963 | {"$f16", RTYPE_FPU | 16}, \ | |
1964 | {"$f17", RTYPE_FPU | 17}, \ | |
1965 | {"$f18", RTYPE_FPU | 18}, \ | |
1966 | {"$f19", RTYPE_FPU | 19}, \ | |
1967 | {"$f20", RTYPE_FPU | 20}, \ | |
1968 | {"$f21", RTYPE_FPU | 21}, \ | |
1969 | {"$f22", RTYPE_FPU | 22}, \ | |
1970 | {"$f23", RTYPE_FPU | 23}, \ | |
1971 | {"$f24", RTYPE_FPU | 24}, \ | |
1972 | {"$f25", RTYPE_FPU | 25}, \ | |
1973 | {"$f26", RTYPE_FPU | 26}, \ | |
1974 | {"$f27", RTYPE_FPU | 27}, \ | |
1975 | {"$f28", RTYPE_FPU | 28}, \ | |
1976 | {"$f29", RTYPE_FPU | 29}, \ | |
1977 | {"$f30", RTYPE_FPU | 30}, \ | |
1978 | {"$f31", RTYPE_FPU | 31} | |
1979 | ||
1980 | #define FPU_CONDITION_CODE_NAMES \ | |
1981 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1982 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1983 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1984 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1985 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1986 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1987 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1988 | {"$fcc7", RTYPE_FCC | 7} | |
1989 | ||
1990 | #define COPROC_CONDITION_CODE_NAMES \ | |
1991 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1992 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1993 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1994 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1995 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1996 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1997 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1998 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1999 | ||
2000 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2001 | {"$a4", RTYPE_GP | 8}, \ | |
2002 | {"$a5", RTYPE_GP | 9}, \ | |
2003 | {"$a6", RTYPE_GP | 10}, \ | |
2004 | {"$a7", RTYPE_GP | 11}, \ | |
2005 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2006 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2007 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2008 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2009 | {"$t0", RTYPE_GP | 12}, \ | |
2010 | {"$t1", RTYPE_GP | 13}, \ | |
2011 | {"$t2", RTYPE_GP | 14}, \ | |
2012 | {"$t3", RTYPE_GP | 15} | |
2013 | ||
2014 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2015 | {"$t0", RTYPE_GP | 8}, \ | |
2016 | {"$t1", RTYPE_GP | 9}, \ | |
2017 | {"$t2", RTYPE_GP | 10}, \ | |
2018 | {"$t3", RTYPE_GP | 11}, \ | |
2019 | {"$t4", RTYPE_GP | 12}, \ | |
2020 | {"$t5", RTYPE_GP | 13}, \ | |
2021 | {"$t6", RTYPE_GP | 14}, \ | |
2022 | {"$t7", RTYPE_GP | 15}, \ | |
2023 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2024 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2025 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2026 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2027 | ||
2028 | /* Remaining symbolic register names */ | |
2029 | #define SYMBOLIC_REGISTER_NAMES \ | |
2030 | {"$zero", RTYPE_GP | 0}, \ | |
2031 | {"$at", RTYPE_GP | 1}, \ | |
2032 | {"$AT", RTYPE_GP | 1}, \ | |
2033 | {"$v0", RTYPE_GP | 2}, \ | |
2034 | {"$v1", RTYPE_GP | 3}, \ | |
2035 | {"$a0", RTYPE_GP | 4}, \ | |
2036 | {"$a1", RTYPE_GP | 5}, \ | |
2037 | {"$a2", RTYPE_GP | 6}, \ | |
2038 | {"$a3", RTYPE_GP | 7}, \ | |
2039 | {"$s0", RTYPE_GP | 16}, \ | |
2040 | {"$s1", RTYPE_GP | 17}, \ | |
2041 | {"$s2", RTYPE_GP | 18}, \ | |
2042 | {"$s3", RTYPE_GP | 19}, \ | |
2043 | {"$s4", RTYPE_GP | 20}, \ | |
2044 | {"$s5", RTYPE_GP | 21}, \ | |
2045 | {"$s6", RTYPE_GP | 22}, \ | |
2046 | {"$s7", RTYPE_GP | 23}, \ | |
2047 | {"$t8", RTYPE_GP | 24}, \ | |
2048 | {"$t9", RTYPE_GP | 25}, \ | |
2049 | {"$k0", RTYPE_GP | 26}, \ | |
2050 | {"$kt0", RTYPE_GP | 26}, \ | |
2051 | {"$k1", RTYPE_GP | 27}, \ | |
2052 | {"$kt1", RTYPE_GP | 27}, \ | |
2053 | {"$gp", RTYPE_GP | 28}, \ | |
2054 | {"$sp", RTYPE_GP | 29}, \ | |
2055 | {"$s8", RTYPE_GP | 30}, \ | |
2056 | {"$fp", RTYPE_GP | 30}, \ | |
2057 | {"$ra", RTYPE_GP | 31} | |
2058 | ||
2059 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2060 | {"$pc", RTYPE_PC | 0} | |
2061 | ||
2062 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2063 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2064 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2065 | {"$v2", RTYPE_VEC | 2}, \ | |
2066 | {"$v3", RTYPE_VEC | 3}, \ | |
2067 | {"$v4", RTYPE_VEC | 4}, \ | |
2068 | {"$v5", RTYPE_VEC | 5}, \ | |
2069 | {"$v6", RTYPE_VEC | 6}, \ | |
2070 | {"$v7", RTYPE_VEC | 7}, \ | |
2071 | {"$v8", RTYPE_VEC | 8}, \ | |
2072 | {"$v9", RTYPE_VEC | 9}, \ | |
2073 | {"$v10", RTYPE_VEC | 10}, \ | |
2074 | {"$v11", RTYPE_VEC | 11}, \ | |
2075 | {"$v12", RTYPE_VEC | 12}, \ | |
2076 | {"$v13", RTYPE_VEC | 13}, \ | |
2077 | {"$v14", RTYPE_VEC | 14}, \ | |
2078 | {"$v15", RTYPE_VEC | 15}, \ | |
2079 | {"$v16", RTYPE_VEC | 16}, \ | |
2080 | {"$v17", RTYPE_VEC | 17}, \ | |
2081 | {"$v18", RTYPE_VEC | 18}, \ | |
2082 | {"$v19", RTYPE_VEC | 19}, \ | |
2083 | {"$v20", RTYPE_VEC | 20}, \ | |
2084 | {"$v21", RTYPE_VEC | 21}, \ | |
2085 | {"$v22", RTYPE_VEC | 22}, \ | |
2086 | {"$v23", RTYPE_VEC | 23}, \ | |
2087 | {"$v24", RTYPE_VEC | 24}, \ | |
2088 | {"$v25", RTYPE_VEC | 25}, \ | |
2089 | {"$v26", RTYPE_VEC | 26}, \ | |
2090 | {"$v27", RTYPE_VEC | 27}, \ | |
2091 | {"$v28", RTYPE_VEC | 28}, \ | |
2092 | {"$v29", RTYPE_VEC | 29}, \ | |
2093 | {"$v30", RTYPE_VEC | 30}, \ | |
2094 | {"$v31", RTYPE_VEC | 31} | |
2095 | ||
2096 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2097 | {"$ac0", RTYPE_ACC | 0}, \ | |
2098 | {"$ac1", RTYPE_ACC | 1}, \ | |
2099 | {"$ac2", RTYPE_ACC | 2}, \ | |
2100 | {"$ac3", RTYPE_ACC | 3} | |
2101 | ||
2102 | static const struct regname reg_names[] = { | |
2103 | GENERIC_REGISTER_NUMBERS, | |
2104 | FPU_REGISTER_NAMES, | |
2105 | FPU_CONDITION_CODE_NAMES, | |
2106 | COPROC_CONDITION_CODE_NAMES, | |
2107 | ||
2108 | /* The $txx registers depends on the abi, | |
2109 | these will be added later into the symbol table from | |
2110 | one of the tables below once mips_abi is set after | |
2111 | parsing of arguments from the command line. */ | |
2112 | SYMBOLIC_REGISTER_NAMES, | |
2113 | ||
2114 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2115 | MDMX_VECTOR_REGISTER_NAMES, | |
2116 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2117 | {0, 0} | |
2118 | }; | |
2119 | ||
2120 | static const struct regname reg_names_o32[] = { | |
2121 | O32_SYMBOLIC_REGISTER_NAMES, | |
2122 | {0, 0} | |
2123 | }; | |
2124 | ||
2125 | static const struct regname reg_names_n32n64[] = { | |
2126 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2127 | {0, 0} | |
2128 | }; | |
2129 | ||
df58fc94 RS |
2130 | /* Check if S points at a valid register specifier according to TYPES. |
2131 | If so, then return 1, advance S to consume the specifier and store | |
2132 | the register's number in REGNOP, otherwise return 0. */ | |
2133 | ||
707bfff6 TS |
2134 | static int |
2135 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2136 | { | |
2137 | symbolS *symbolP; | |
2138 | char *e; | |
2139 | char save_c; | |
2140 | int reg = -1; | |
2141 | ||
2142 | /* Find end of name. */ | |
2143 | e = *s; | |
2144 | if (is_name_beginner (*e)) | |
2145 | ++e; | |
2146 | while (is_part_of_name (*e)) | |
2147 | ++e; | |
2148 | ||
2149 | /* Terminate name. */ | |
2150 | save_c = *e; | |
2151 | *e = '\0'; | |
2152 | ||
2153 | /* Look for a register symbol. */ | |
2154 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2155 | { | |
2156 | int r = S_GET_VALUE (symbolP); | |
2157 | if (r & types) | |
2158 | reg = r & RNUM_MASK; | |
2159 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2160 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2161 | reg = (r & RNUM_MASK) - 2; | |
2162 | } | |
2163 | /* Else see if this is a register defined in an itbl entry. */ | |
2164 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2165 | { | |
2166 | char *n = *s; | |
2167 | unsigned long r; | |
2168 | ||
2169 | if (*n == '$') | |
2170 | ++n; | |
2171 | if (itbl_get_reg_val (n, &r)) | |
2172 | reg = r & RNUM_MASK; | |
2173 | } | |
2174 | ||
2175 | /* Advance to next token if a register was recognised. */ | |
2176 | if (reg >= 0) | |
2177 | *s = e; | |
2178 | else if (types & RWARN) | |
20203fb9 | 2179 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2180 | |
2181 | *e = save_c; | |
2182 | if (regnop) | |
2183 | *regnop = reg; | |
2184 | return reg >= 0; | |
2185 | } | |
2186 | ||
df58fc94 RS |
2187 | /* Check if S points at a valid register list according to TYPES. |
2188 | If so, then return 1, advance S to consume the list and store | |
2189 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2190 | otherwise return 0. A valid list comprises a comma-separated | |
2191 | enumeration of valid single registers and/or dash-separated | |
2192 | contiguous register ranges as determined by their numbers. | |
2193 | ||
2194 | As a special exception if one of s0-s7 registers is specified as | |
2195 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2196 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2197 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2198 | |
2199 | static int | |
2200 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2201 | { | |
2202 | unsigned int reglist = 0; | |
2203 | unsigned int lastregno; | |
2204 | bfd_boolean ok = TRUE; | |
2205 | unsigned int regmask; | |
2309ddf2 | 2206 | char *s_endlist = *s; |
df58fc94 | 2207 | char *s_reset = *s; |
2309ddf2 | 2208 | unsigned int regno; |
df58fc94 RS |
2209 | |
2210 | while (reg_lookup (s, types, ®no)) | |
2211 | { | |
2212 | lastregno = regno; | |
2213 | if (**s == '-') | |
2214 | { | |
2215 | (*s)++; | |
2216 | ok = reg_lookup (s, types, &lastregno); | |
2217 | if (ok && lastregno < regno) | |
2218 | ok = FALSE; | |
2219 | if (!ok) | |
2220 | break; | |
2221 | } | |
2222 | ||
2223 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2224 | { | |
2225 | lastregno = S7; | |
2226 | reglist |= 1 << FP; | |
2227 | } | |
2228 | regmask = 1 << lastregno; | |
2229 | regmask = (regmask << 1) - 1; | |
2230 | regmask ^= (1 << regno) - 1; | |
2231 | reglist |= regmask; | |
2232 | ||
2309ddf2 | 2233 | s_endlist = *s; |
df58fc94 RS |
2234 | if (**s != ',') |
2235 | break; | |
2236 | (*s)++; | |
2237 | } | |
2238 | ||
2239 | if (ok) | |
2309ddf2 | 2240 | *s = s_endlist; |
df58fc94 RS |
2241 | else |
2242 | *s = s_reset; | |
2243 | if (reglistp) | |
2244 | *reglistp = reglist; | |
2245 | return ok && reglist != 0; | |
2246 | } | |
2247 | ||
037b32b9 | 2248 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2249 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2250 | |
2251 | static bfd_boolean | |
f79e2745 | 2252 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2253 | { |
2254 | int isa = mips_opts.isa; | |
2255 | int fp_s, fp_d; | |
2256 | ||
2257 | if (mips_opts.ase_mdmx) | |
2258 | isa |= INSN_MDMX; | |
2259 | if (mips_opts.ase_dsp) | |
2260 | isa |= INSN_DSP; | |
2261 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2262 | isa |= INSN_DSP64; | |
2263 | if (mips_opts.ase_dspr2) | |
2264 | isa |= INSN_DSPR2; | |
2265 | if (mips_opts.ase_mt) | |
2266 | isa |= INSN_MT; | |
2267 | if (mips_opts.ase_mips3d) | |
2268 | isa |= INSN_MIPS3D; | |
2269 | if (mips_opts.ase_smartmips) | |
2270 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2271 | if (mips_opts.ase_mcu) |
2272 | isa |= INSN_MCU; | |
b015e599 AP |
2273 | if (mips_opts.ase_virt) |
2274 | isa |= INSN_VIRT; | |
2275 | if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE) | |
2276 | isa |= INSN_VIRT64; | |
037b32b9 | 2277 | |
35d0a169 | 2278 | if (!opcode_is_member (mo, isa, mips_opts.arch)) |
037b32b9 AN |
2279 | return FALSE; |
2280 | ||
2281 | /* Check whether the instruction or macro requires single-precision or | |
2282 | double-precision floating-point support. Note that this information is | |
2283 | stored differently in the opcode table for insns and macros. */ | |
2284 | if (mo->pinfo == INSN_MACRO) | |
2285 | { | |
2286 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2287 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2288 | } | |
2289 | else | |
2290 | { | |
2291 | fp_s = mo->pinfo & FP_S; | |
2292 | fp_d = mo->pinfo & FP_D; | |
2293 | } | |
2294 | ||
2295 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2296 | return FALSE; | |
2297 | ||
2298 | if (fp_s && mips_opts.soft_float) | |
2299 | return FALSE; | |
2300 | ||
2301 | return TRUE; | |
2302 | } | |
2303 | ||
2304 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2305 | selected ISA and architecture. */ | |
2306 | ||
2307 | static bfd_boolean | |
2308 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2309 | { | |
35d0a169 | 2310 | return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); |
037b32b9 AN |
2311 | } |
2312 | ||
df58fc94 RS |
2313 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2314 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2315 | ||
2316 | static bfd_boolean | |
2317 | is_size_valid (const struct mips_opcode *mo) | |
2318 | { | |
2319 | if (!mips_opts.micromips) | |
2320 | return TRUE; | |
2321 | ||
2322 | if (!forced_insn_length) | |
2323 | return TRUE; | |
2324 | if (mo->pinfo == INSN_MACRO) | |
2325 | return FALSE; | |
2326 | return forced_insn_length == micromips_insn_length (mo); | |
2327 | } | |
2328 | ||
2329 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2330 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2331 | ||
2332 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2333 | a macro expansion fails because it relies on a preceding 32-bit real | |
2334 | instruction to have matched and does not handle the operands correctly. | |
2335 | The only macros that may expand to 16-bit instructions are JAL that | |
2336 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2337 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2338 | a NOP. In all these cases the macros precede any corresponding real | |
2339 | instruction definitions in the opcode table, so they will match in the | |
2340 | second pass where the size of the delay slot is ignored and therefore | |
2341 | produce correct code. */ | |
df58fc94 RS |
2342 | |
2343 | static bfd_boolean | |
2344 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2345 | { | |
2346 | if (!mips_opts.micromips) | |
2347 | return TRUE; | |
2348 | ||
2349 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2350 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2351 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2352 | && micromips_insn_length (mo) != 4) | |
2353 | return FALSE; | |
2354 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2355 | && micromips_insn_length (mo) != 2) | |
2356 | return FALSE; | |
2357 | ||
2358 | return TRUE; | |
2359 | } | |
2360 | ||
707bfff6 TS |
2361 | /* This function is called once, at assembler startup time. It should set up |
2362 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2363 | |
252b5132 | 2364 | void |
17a2f251 | 2365 | md_begin (void) |
252b5132 | 2366 | { |
3994f87e | 2367 | const char *retval = NULL; |
156c2f8b | 2368 | int i = 0; |
252b5132 | 2369 | int broken = 0; |
1f25f5d3 | 2370 | |
0a44bf69 RS |
2371 | if (mips_pic != NO_PIC) |
2372 | { | |
2373 | if (g_switch_seen && g_switch_value != 0) | |
2374 | as_bad (_("-G may not be used in position-independent code")); | |
2375 | g_switch_value = 0; | |
2376 | } | |
2377 | ||
fef14a42 | 2378 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2379 | as_warn (_("Could not set architecture and machine")); |
2380 | ||
252b5132 RH |
2381 | op_hash = hash_new (); |
2382 | ||
2383 | for (i = 0; i < NUMOPCODES;) | |
2384 | { | |
2385 | const char *name = mips_opcodes[i].name; | |
2386 | ||
17a2f251 | 2387 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2388 | if (retval != NULL) |
2389 | { | |
2390 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2391 | mips_opcodes[i].name, retval); | |
2392 | /* Probably a memory allocation problem? Give up now. */ | |
2393 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2394 | } | |
2395 | do | |
2396 | { | |
2397 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2398 | { | |
2399 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2400 | broken = 1; | |
1e915849 RS |
2401 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2402 | { | |
2403 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2404 | if (mips_fix_loongson2f_nop) |
2405 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2406 | nop_insn.fixed_p = 1; |
2407 | } | |
252b5132 RH |
2408 | } |
2409 | ++i; | |
2410 | } | |
2411 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2412 | } | |
2413 | ||
2414 | mips16_op_hash = hash_new (); | |
2415 | ||
2416 | i = 0; | |
2417 | while (i < bfd_mips16_num_opcodes) | |
2418 | { | |
2419 | const char *name = mips16_opcodes[i].name; | |
2420 | ||
17a2f251 | 2421 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2422 | if (retval != NULL) |
2423 | as_fatal (_("internal: can't hash `%s': %s"), | |
2424 | mips16_opcodes[i].name, retval); | |
2425 | do | |
2426 | { | |
2427 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2428 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2429 | != mips16_opcodes[i].match)) | |
2430 | { | |
2431 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2432 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2433 | broken = 1; | |
2434 | } | |
1e915849 RS |
2435 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2436 | { | |
2437 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2438 | mips16_nop_insn.fixed_p = 1; | |
2439 | } | |
252b5132 RH |
2440 | ++i; |
2441 | } | |
2442 | while (i < bfd_mips16_num_opcodes | |
2443 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2444 | } | |
2445 | ||
df58fc94 RS |
2446 | micromips_op_hash = hash_new (); |
2447 | ||
2448 | i = 0; | |
2449 | while (i < bfd_micromips_num_opcodes) | |
2450 | { | |
2451 | const char *name = micromips_opcodes[i].name; | |
2452 | ||
2453 | retval = hash_insert (micromips_op_hash, name, | |
2454 | (void *) µmips_opcodes[i]); | |
2455 | if (retval != NULL) | |
2456 | as_fatal (_("internal: can't hash `%s': %s"), | |
2457 | micromips_opcodes[i].name, retval); | |
2458 | do | |
2459 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2460 | { | |
2461 | struct mips_cl_insn *micromips_nop_insn; | |
2462 | ||
2463 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2464 | broken = 1; | |
2465 | ||
2466 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2467 | micromips_nop_insn = µmips_nop16_insn; | |
2468 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2469 | micromips_nop_insn = µmips_nop32_insn; | |
2470 | else | |
2471 | continue; | |
2472 | ||
2473 | if (micromips_nop_insn->insn_mo == NULL | |
2474 | && strcmp (name, "nop") == 0) | |
2475 | { | |
2476 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2477 | micromips_nop_insn->fixed_p = 1; | |
2478 | } | |
2479 | } | |
2480 | while (++i < bfd_micromips_num_opcodes | |
2481 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2482 | } | |
2483 | ||
252b5132 RH |
2484 | if (broken) |
2485 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2486 | ||
2487 | /* We add all the general register names to the symbol table. This | |
2488 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2489 | for (i = 0; reg_names[i].name; i++) |
2490 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2491 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2492 | &zero_address_frag)); |
2493 | if (HAVE_NEWABI) | |
2494 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2495 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2496 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2497 | &zero_address_frag)); |
707bfff6 TS |
2498 | else |
2499 | for (i = 0; reg_names_o32[i].name; i++) | |
2500 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2501 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2502 | &zero_address_frag)); |
6047c971 | 2503 | |
7d10b47d | 2504 | mips_no_prev_insn (); |
252b5132 RH |
2505 | |
2506 | mips_gprmask = 0; | |
2507 | mips_cprmask[0] = 0; | |
2508 | mips_cprmask[1] = 0; | |
2509 | mips_cprmask[2] = 0; | |
2510 | mips_cprmask[3] = 0; | |
2511 | ||
2512 | /* set the default alignment for the text section (2**2) */ | |
2513 | record_alignment (text_section, 2); | |
2514 | ||
4d0d148d | 2515 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2516 | |
707bfff6 | 2517 | #ifdef OBJ_ELF |
f43abd2b | 2518 | if (IS_ELF) |
252b5132 | 2519 | { |
0a44bf69 RS |
2520 | /* On a native system other than VxWorks, sections must be aligned |
2521 | to 16 byte boundaries. When configured for an embedded ELF | |
2522 | target, we don't bother. */ | |
c41e87e3 CF |
2523 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2524 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2525 | { |
2526 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2527 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2528 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2529 | } | |
2530 | ||
2531 | /* Create a .reginfo section for register masks and a .mdebug | |
2532 | section for debugging information. */ | |
2533 | { | |
2534 | segT seg; | |
2535 | subsegT subseg; | |
2536 | flagword flags; | |
2537 | segT sec; | |
2538 | ||
2539 | seg = now_seg; | |
2540 | subseg = now_subseg; | |
2541 | ||
2542 | /* The ABI says this section should be loaded so that the | |
2543 | running program can access it. However, we don't load it | |
2544 | if we are configured for an embedded target */ | |
2545 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2546 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2547 | flags |= SEC_ALLOC | SEC_LOAD; |
2548 | ||
316f5878 | 2549 | if (mips_abi != N64_ABI) |
252b5132 RH |
2550 | { |
2551 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2552 | ||
195325d2 TS |
2553 | bfd_set_section_flags (stdoutput, sec, flags); |
2554 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2555 | |
252b5132 | 2556 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2557 | } |
2558 | else | |
2559 | { | |
2560 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2561 | .reginfo section. */ | |
2562 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2563 | bfd_set_section_flags (stdoutput, sec, flags); |
2564 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2565 | |
252b5132 RH |
2566 | /* Set up the option header. */ |
2567 | { | |
2568 | Elf_Internal_Options opthdr; | |
2569 | char *f; | |
2570 | ||
2571 | opthdr.kind = ODK_REGINFO; | |
2572 | opthdr.size = (sizeof (Elf_External_Options) | |
2573 | + sizeof (Elf64_External_RegInfo)); | |
2574 | opthdr.section = 0; | |
2575 | opthdr.info = 0; | |
2576 | f = frag_more (sizeof (Elf_External_Options)); | |
2577 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2578 | (Elf_External_Options *) f); | |
2579 | ||
2580 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2581 | } | |
252b5132 RH |
2582 | } |
2583 | ||
2584 | if (ECOFF_DEBUGGING) | |
2585 | { | |
2586 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2587 | (void) bfd_set_section_flags (stdoutput, sec, | |
2588 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2589 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2590 | } | |
f43abd2b | 2591 | else if (mips_flag_pdr) |
ecb4347a DJ |
2592 | { |
2593 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2594 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2595 | SEC_READONLY | SEC_RELOC | |
2596 | | SEC_DEBUGGING); | |
2597 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2598 | } | |
252b5132 RH |
2599 | |
2600 | subseg_set (seg, subseg); | |
2601 | } | |
2602 | } | |
707bfff6 | 2603 | #endif /* OBJ_ELF */ |
252b5132 RH |
2604 | |
2605 | if (! ECOFF_DEBUGGING) | |
2606 | md_obj_begin (); | |
71400594 RS |
2607 | |
2608 | if (mips_fix_vr4120) | |
2609 | init_vr4120_conflicts (); | |
252b5132 RH |
2610 | } |
2611 | ||
2612 | void | |
17a2f251 | 2613 | md_mips_end (void) |
252b5132 | 2614 | { |
02b1ab82 | 2615 | mips_emit_delays (); |
252b5132 RH |
2616 | if (! ECOFF_DEBUGGING) |
2617 | md_obj_end (); | |
2618 | } | |
2619 | ||
2620 | void | |
17a2f251 | 2621 | md_assemble (char *str) |
252b5132 RH |
2622 | { |
2623 | struct mips_cl_insn insn; | |
f6688943 TS |
2624 | bfd_reloc_code_real_type unused_reloc[3] |
2625 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2626 | |
2627 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2628 | imm2_expr.X_op = O_absent; |
252b5132 | 2629 | offset_expr.X_op = O_absent; |
f6688943 TS |
2630 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2631 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2632 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2633 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2634 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2635 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2636 | |
e1b47bd5 RS |
2637 | mips_mark_labels (); |
2638 | mips_assembling_insn = TRUE; | |
2639 | ||
252b5132 RH |
2640 | if (mips_opts.mips16) |
2641 | mips16_ip (str, &insn); | |
2642 | else | |
2643 | { | |
2644 | mips_ip (str, &insn); | |
beae10d5 KH |
2645 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2646 | str, insn.insn_opcode)); | |
252b5132 RH |
2647 | } |
2648 | ||
2649 | if (insn_error) | |
e1b47bd5 RS |
2650 | as_bad ("%s `%s'", insn_error, str); |
2651 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2652 | { |
584892a6 | 2653 | macro_start (); |
252b5132 RH |
2654 | if (mips_opts.mips16) |
2655 | mips16_macro (&insn); | |
2656 | else | |
2657 | macro (&insn); | |
584892a6 | 2658 | macro_end (); |
252b5132 RH |
2659 | } |
2660 | else | |
2661 | { | |
2662 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2663 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2664 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2665 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2666 | else |
df58fc94 | 2667 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2668 | } |
e1b47bd5 RS |
2669 | |
2670 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2671 | } |
2672 | ||
738e5348 RS |
2673 | /* Convenience functions for abstracting away the differences between |
2674 | MIPS16 and non-MIPS16 relocations. */ | |
2675 | ||
2676 | static inline bfd_boolean | |
2677 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2678 | { | |
2679 | switch (reloc) | |
2680 | { | |
2681 | case BFD_RELOC_MIPS16_JMP: | |
2682 | case BFD_RELOC_MIPS16_GPREL: | |
2683 | case BFD_RELOC_MIPS16_GOT16: | |
2684 | case BFD_RELOC_MIPS16_CALL16: | |
2685 | case BFD_RELOC_MIPS16_HI16_S: | |
2686 | case BFD_RELOC_MIPS16_HI16: | |
2687 | case BFD_RELOC_MIPS16_LO16: | |
2688 | return TRUE; | |
2689 | ||
2690 | default: | |
2691 | return FALSE; | |
2692 | } | |
2693 | } | |
2694 | ||
df58fc94 RS |
2695 | static inline bfd_boolean |
2696 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2697 | { | |
2698 | switch (reloc) | |
2699 | { | |
2700 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2701 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2702 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2703 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2704 | case BFD_RELOC_MICROMIPS_JMP: | |
2705 | case BFD_RELOC_MICROMIPS_HI16: | |
2706 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2707 | case BFD_RELOC_MICROMIPS_LO16: | |
2708 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2709 | case BFD_RELOC_MICROMIPS_GOT16: | |
2710 | case BFD_RELOC_MICROMIPS_CALL16: | |
2711 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2712 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2713 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2714 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2715 | case BFD_RELOC_MICROMIPS_SUB: | |
2716 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2717 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2718 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2719 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2720 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2721 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2722 | case BFD_RELOC_MICROMIPS_JALR: | |
2723 | return TRUE; | |
2724 | ||
2725 | default: | |
2726 | return FALSE; | |
2727 | } | |
2728 | } | |
2729 | ||
2309ddf2 MR |
2730 | static inline bfd_boolean |
2731 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2732 | { | |
2733 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2734 | } | |
2735 | ||
738e5348 RS |
2736 | static inline bfd_boolean |
2737 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2738 | { | |
2309ddf2 | 2739 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2740 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2741 | } |
2742 | ||
2743 | static inline bfd_boolean | |
2744 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2745 | { | |
2309ddf2 | 2746 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2747 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2748 | } |
2749 | ||
2750 | static inline bfd_boolean | |
2751 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2752 | { | |
2309ddf2 | 2753 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2754 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2755 | } | |
2756 | ||
df58fc94 RS |
2757 | static inline bfd_boolean |
2758 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2759 | { | |
2309ddf2 | 2760 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2761 | } |
2762 | ||
2de39019 CM |
2763 | /* Return true if RELOC is a PC-relative relocation that does not have |
2764 | full address range. */ | |
2765 | ||
2766 | static inline bfd_boolean | |
2767 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2768 | { | |
2769 | switch (reloc) | |
2770 | { | |
2771 | case BFD_RELOC_16_PCREL_S2: | |
2772 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2773 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2774 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2775 | return TRUE; | |
2776 | ||
b47468a6 CM |
2777 | case BFD_RELOC_32_PCREL: |
2778 | return HAVE_64BIT_ADDRESSES; | |
2779 | ||
2de39019 CM |
2780 | default: |
2781 | return FALSE; | |
2782 | } | |
2783 | } | |
b47468a6 | 2784 | |
5919d012 | 2785 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2786 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2787 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2788 | |
2789 | static inline bfd_boolean | |
17a2f251 | 2790 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2791 | { |
3b91255e | 2792 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2793 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2794 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2795 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2796 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2797 | } | |
2798 | ||
2799 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2800 | reloc_needs_lo_p. */ | |
2801 | ||
2802 | static inline bfd_reloc_code_real_type | |
2803 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2804 | { | |
df58fc94 RS |
2805 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2806 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2807 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2808 | } |
2809 | ||
2810 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2811 | relocation. */ | |
2812 | ||
2813 | static inline bfd_boolean | |
17a2f251 | 2814 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2815 | { |
2816 | return (fixp->fx_next != NULL | |
738e5348 | 2817 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2818 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2819 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2820 | } | |
2821 | ||
252b5132 RH |
2822 | /* This function returns true if modifying a register requires a |
2823 | delay. */ | |
2824 | ||
2825 | static int | |
17a2f251 | 2826 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2827 | { |
2828 | unsigned long prev_pinfo; | |
2829 | ||
47e39b9d | 2830 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2831 | if (! mips_opts.noreorder |
81912461 ILT |
2832 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2833 | && ! gpr_interlocks) | |
2834 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2835 | && ! cop_interlocks))) | |
252b5132 | 2836 | { |
81912461 ILT |
2837 | /* A load from a coprocessor or from memory. All load delays |
2838 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2839 | /* Itbl support may require additional care here. */ |
252b5132 | 2840 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2841 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2842 | return 1; |
2843 | } | |
2844 | ||
2845 | return 0; | |
2846 | } | |
2847 | ||
462427c4 RS |
2848 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2849 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2850 | |
2851 | static void | |
462427c4 | 2852 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2853 | { |
2854 | struct insn_label_list *l; | |
2855 | valueT val; | |
2856 | ||
462427c4 | 2857 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2858 | { |
9c2799c2 | 2859 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2860 | symbol_set_frag (l->label, frag_now); |
2861 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2862 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2863 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2864 | ++val; |
2865 | S_SET_VALUE (l->label, val); | |
2866 | } | |
2867 | } | |
2868 | ||
462427c4 RS |
2869 | /* Move all labels in insn_labels to the current insertion point |
2870 | and treat them as text labels. */ | |
2871 | ||
2872 | static void | |
2873 | mips_move_text_labels (void) | |
2874 | { | |
2875 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2876 | } | |
2877 | ||
5f0fe04b TS |
2878 | static bfd_boolean |
2879 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2880 | { | |
2881 | bfd_boolean linkonce = FALSE; | |
2882 | segT symseg = S_GET_SEGMENT (sym); | |
2883 | ||
2884 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2885 | { | |
2886 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2887 | linkonce = TRUE; | |
2888 | #ifdef OBJ_ELF | |
2889 | /* The GNU toolchain uses an extension for ELF: a section | |
2890 | beginning with the magic string .gnu.linkonce is a | |
2891 | linkonce section. */ | |
2892 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2893 | sizeof ".gnu.linkonce" - 1) == 0) | |
2894 | linkonce = TRUE; | |
2895 | #endif | |
2896 | } | |
2897 | return linkonce; | |
2898 | } | |
2899 | ||
e1b47bd5 | 2900 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2901 | linker to handle them specially, such as generating jalx instructions |
2902 | when needed. We also make them odd for the duration of the assembly, | |
2903 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2904 | in the adjust_symtab routine, while leaving them marked. This is |
2905 | convenient for the debugger and the disassembler. The linker knows | |
2906 | to make them odd again. */ | |
2907 | ||
2908 | static void | |
e1b47bd5 | 2909 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2910 | { |
df58fc94 | 2911 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2912 | |
a8dbcb85 | 2913 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2914 | if (IS_ELF) |
2915 | { | |
2916 | if (mips_opts.mips16) | |
2917 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2918 | else | |
2919 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2920 | } |
e1b47bd5 RS |
2921 | #endif |
2922 | if ((S_GET_VALUE (label) & 1) == 0 | |
2923 | /* Don't adjust the address if the label is global or weak, or | |
2924 | in a link-once section, since we'll be emitting symbol reloc | |
2925 | references to it which will be patched up by the linker, and | |
2926 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2927 | && !S_IS_WEAK (label) | |
2928 | && !S_IS_EXTERNAL (label) | |
2929 | && !s_is_linkonce (label, now_seg)) | |
2930 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2931 | } | |
2932 | ||
2933 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2934 | ||
2935 | static void | |
2936 | mips_compressed_mark_labels (void) | |
2937 | { | |
2938 | struct insn_label_list *l; | |
2939 | ||
2940 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2941 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2942 | } |
2943 | ||
4d7206a2 RS |
2944 | /* End the current frag. Make it a variant frag and record the |
2945 | relaxation info. */ | |
2946 | ||
2947 | static void | |
2948 | relax_close_frag (void) | |
2949 | { | |
584892a6 | 2950 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2951 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2952 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2953 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2954 | ||
2955 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2956 | mips_relax.first_fixup = 0; | |
2957 | } | |
2958 | ||
2959 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2960 | See the comment above RELAX_ENCODE for more details. */ | |
2961 | ||
2962 | static void | |
2963 | relax_start (symbolS *symbol) | |
2964 | { | |
9c2799c2 | 2965 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2966 | mips_relax.sequence = 1; |
2967 | mips_relax.symbol = symbol; | |
2968 | } | |
2969 | ||
2970 | /* Start generating the second version of a relaxable sequence. | |
2971 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2972 | |
2973 | static void | |
4d7206a2 RS |
2974 | relax_switch (void) |
2975 | { | |
9c2799c2 | 2976 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2977 | mips_relax.sequence = 2; |
2978 | } | |
2979 | ||
2980 | /* End the current relaxable sequence. */ | |
2981 | ||
2982 | static void | |
2983 | relax_end (void) | |
2984 | { | |
9c2799c2 | 2985 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2986 | relax_close_frag (); |
2987 | mips_relax.sequence = 0; | |
2988 | } | |
2989 | ||
11625dd8 RS |
2990 | /* Return true if IP is a delayed branch or jump. */ |
2991 | ||
2992 | static inline bfd_boolean | |
2993 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2994 | { | |
2995 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2996 | | INSN_COND_BRANCH_DELAY | |
2997 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2998 | } | |
2999 | ||
3000 | /* Return true if IP is a compact branch or jump. */ | |
3001 | ||
3002 | static inline bfd_boolean | |
3003 | compact_branch_p (const struct mips_cl_insn *ip) | |
3004 | { | |
3005 | if (mips_opts.mips16) | |
3006 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3007 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3008 | else | |
3009 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3010 | | INSN2_COND_BRANCH)) != 0; | |
3011 | } | |
3012 | ||
3013 | /* Return true if IP is an unconditional branch or jump. */ | |
3014 | ||
3015 | static inline bfd_boolean | |
3016 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3017 | { | |
3018 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3019 | || (mips_opts.mips16 | |
3020 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3021 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3022 | } | |
3023 | ||
3024 | /* Return true if IP is a branch-likely instruction. */ | |
3025 | ||
3026 | static inline bfd_boolean | |
3027 | branch_likely_p (const struct mips_cl_insn *ip) | |
3028 | { | |
3029 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3030 | } | |
3031 | ||
14fe068b RS |
3032 | /* Return the type of nop that should be used to fill the delay slot |
3033 | of delayed branch IP. */ | |
3034 | ||
3035 | static struct mips_cl_insn * | |
3036 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3037 | { | |
3038 | if (mips_opts.micromips | |
3039 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3040 | return µmips_nop32_insn; | |
3041 | return NOP_INSN; | |
3042 | } | |
3043 | ||
2309ddf2 | 3044 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3045 | |
3046 | static unsigned int | |
3047 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3048 | { | |
2309ddf2 | 3049 | unsigned long pinfo2; |
df58fc94 RS |
3050 | unsigned int mask; |
3051 | ||
3052 | mask = 0; | |
df58fc94 RS |
3053 | pinfo2 = ip->insn_mo->pinfo2; |
3054 | if (mips_opts.micromips) | |
3055 | { | |
df58fc94 RS |
3056 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3057 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3058 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3059 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3060 | if (pinfo2 & INSN2_MOD_SP) |
3061 | mask |= 1 << SP; | |
3062 | } | |
3063 | return mask; | |
3064 | } | |
3065 | ||
4c260379 RS |
3066 | /* Return the mask of core registers that IP reads. */ |
3067 | ||
3068 | static unsigned int | |
3069 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3070 | { | |
3071 | unsigned long pinfo, pinfo2; | |
3072 | unsigned int mask; | |
3073 | ||
df58fc94 | 3074 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3075 | pinfo = ip->insn_mo->pinfo; |
3076 | pinfo2 = ip->insn_mo->pinfo2; | |
3077 | if (mips_opts.mips16) | |
3078 | { | |
3079 | if (pinfo & MIPS16_INSN_READ_X) | |
3080 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3081 | if (pinfo & MIPS16_INSN_READ_Y) | |
3082 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3083 | if (pinfo & MIPS16_INSN_READ_T) | |
3084 | mask |= 1 << TREG; | |
3085 | if (pinfo & MIPS16_INSN_READ_SP) | |
3086 | mask |= 1 << SP; | |
3087 | if (pinfo & MIPS16_INSN_READ_31) | |
3088 | mask |= 1 << RA; | |
3089 | if (pinfo & MIPS16_INSN_READ_Z) | |
3090 | mask |= 1 << (mips16_to_32_reg_map | |
3091 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3092 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3093 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3094 | } | |
3095 | else | |
3096 | { | |
3097 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3098 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3099 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3100 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3101 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3102 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3103 | if (pinfo2 & INSN2_READ_GP) | |
3104 | mask |= 1 << GP; | |
3105 | if (pinfo2 & INSN2_READ_GPR_31) | |
3106 | mask |= 1 << RA; | |
4c260379 | 3107 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3108 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3109 | } |
2b0c8b40 MR |
3110 | if (mips_opts.micromips) |
3111 | { | |
3112 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3113 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3114 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3115 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3116 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3117 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3118 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3119 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3120 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3121 | { | |
3122 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3123 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3124 | } | |
3125 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3126 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3127 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3128 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3129 | } | |
fe35f09f RS |
3130 | /* Don't include register 0. */ |
3131 | return mask & ~1; | |
4c260379 RS |
3132 | } |
3133 | ||
3134 | /* Return the mask of core registers that IP writes. */ | |
3135 | ||
3136 | static unsigned int | |
3137 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3138 | { | |
3139 | unsigned long pinfo, pinfo2; | |
3140 | unsigned int mask; | |
3141 | ||
df58fc94 | 3142 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3143 | pinfo = ip->insn_mo->pinfo; |
3144 | pinfo2 = ip->insn_mo->pinfo2; | |
3145 | if (mips_opts.mips16) | |
3146 | { | |
3147 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3148 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3149 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3150 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3151 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3152 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3153 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3154 | mask |= 1 << TREG; | |
3155 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3156 | mask |= 1 << SP; | |
3157 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3158 | mask |= 1 << RA; | |
3159 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3160 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3161 | } | |
3162 | else | |
3163 | { | |
3164 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3165 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3166 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3167 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3168 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3169 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3170 | if (pinfo & INSN_WRITE_GPR_31) |
3171 | mask |= 1 << RA; | |
3172 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3173 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3174 | } |
2b0c8b40 MR |
3175 | if (mips_opts.micromips) |
3176 | { | |
3177 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3178 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3179 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3180 | { | |
3181 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3182 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3183 | } | |
3184 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3185 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3186 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3187 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3188 | } | |
fe35f09f RS |
3189 | /* Don't include register 0. */ |
3190 | return mask & ~1; | |
4c260379 RS |
3191 | } |
3192 | ||
3193 | /* Return the mask of floating-point registers that IP reads. */ | |
3194 | ||
3195 | static unsigned int | |
3196 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3197 | { | |
3198 | unsigned long pinfo, pinfo2; | |
3199 | unsigned int mask; | |
3200 | ||
3201 | mask = 0; | |
3202 | pinfo = ip->insn_mo->pinfo; | |
3203 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3204 | if (!mips_opts.mips16) |
df58fc94 RS |
3205 | { |
3206 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3207 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3208 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3209 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3210 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3211 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3212 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3213 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3214 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3215 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3216 | } |
3217 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3218 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3219 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3220 | mask |= mask << 1; | |
3221 | return mask; | |
3222 | } | |
3223 | ||
3224 | /* Return the mask of floating-point registers that IP writes. */ | |
3225 | ||
3226 | static unsigned int | |
3227 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3228 | { | |
3229 | unsigned long pinfo, pinfo2; | |
3230 | unsigned int mask; | |
3231 | ||
3232 | mask = 0; | |
3233 | pinfo = ip->insn_mo->pinfo; | |
3234 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3235 | if (!mips_opts.mips16) |
4c260379 RS |
3236 | { |
3237 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3238 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3239 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3240 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3241 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3242 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3243 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3244 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3245 | } |
3246 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3247 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3248 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3249 | mask |= mask << 1; | |
3250 | return mask; | |
3251 | } | |
3252 | ||
71400594 RS |
3253 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3254 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3255 | by VR4120 errata. */ | |
4d7206a2 | 3256 | |
71400594 RS |
3257 | static unsigned int |
3258 | classify_vr4120_insn (const char *name) | |
252b5132 | 3259 | { |
71400594 RS |
3260 | if (strncmp (name, "macc", 4) == 0) |
3261 | return FIX_VR4120_MACC; | |
3262 | if (strncmp (name, "dmacc", 5) == 0) | |
3263 | return FIX_VR4120_DMACC; | |
3264 | if (strncmp (name, "mult", 4) == 0) | |
3265 | return FIX_VR4120_MULT; | |
3266 | if (strncmp (name, "dmult", 5) == 0) | |
3267 | return FIX_VR4120_DMULT; | |
3268 | if (strstr (name, "div")) | |
3269 | return FIX_VR4120_DIV; | |
3270 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3271 | return FIX_VR4120_MTHILO; | |
3272 | return NUM_FIX_VR4120_CLASSES; | |
3273 | } | |
252b5132 | 3274 | |
ff239038 CM |
3275 | #define INSN_ERET 0x42000018 |
3276 | #define INSN_DERET 0x4200001f | |
3277 | ||
71400594 RS |
3278 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3279 | where INSN1 is the earlier instruction. Return the worst-case value | |
3280 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3281 | |
71400594 RS |
3282 | static unsigned int |
3283 | insns_between (const struct mips_cl_insn *insn1, | |
3284 | const struct mips_cl_insn *insn2) | |
3285 | { | |
3286 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3287 | unsigned int mask; |
71400594 RS |
3288 | |
3289 | /* This function needs to know which pinfo flags are set for INSN2 | |
3290 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3291 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3292 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3293 | pinfo1 = insn1->insn_mo->pinfo; |
3294 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3295 | |
4c260379 RS |
3296 | #define INSN2_USES_GPR(REG) \ |
3297 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3298 | |
3299 | /* For most targets, write-after-read dependencies on the HI and LO | |
3300 | registers must be separated by at least two instructions. */ | |
3301 | if (!hilo_interlocks) | |
252b5132 | 3302 | { |
71400594 RS |
3303 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3304 | return 2; | |
3305 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3306 | return 2; | |
3307 | } | |
3308 | ||
3309 | /* If we're working around r7000 errata, there must be two instructions | |
3310 | between an mfhi or mflo and any instruction that uses the result. */ | |
3311 | if (mips_7000_hilo_fix | |
df58fc94 | 3312 | && !mips_opts.micromips |
71400594 | 3313 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3314 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3315 | return 2; |
3316 | ||
ff239038 CM |
3317 | /* If we're working around 24K errata, one instruction is required |
3318 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3319 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3320 | { |
3321 | if (insn1->insn_opcode == INSN_ERET | |
3322 | || insn1->insn_opcode == INSN_DERET) | |
3323 | { | |
3324 | if (insn2 == NULL | |
3325 | || insn2->insn_opcode == INSN_ERET | |
3326 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3327 | || delayed_branch_p (insn2)) |
ff239038 CM |
3328 | return 1; |
3329 | } | |
3330 | } | |
3331 | ||
71400594 RS |
3332 | /* If working around VR4120 errata, check for combinations that need |
3333 | a single intervening instruction. */ | |
df58fc94 | 3334 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3335 | { |
3336 | unsigned int class1, class2; | |
252b5132 | 3337 | |
71400594 RS |
3338 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3339 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3340 | { |
71400594 RS |
3341 | if (insn2 == NULL) |
3342 | return 1; | |
3343 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3344 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3345 | return 1; | |
252b5132 | 3346 | } |
71400594 RS |
3347 | } |
3348 | ||
df58fc94 | 3349 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3350 | { |
3351 | /* Check for GPR or coprocessor load delays. All such delays | |
3352 | are on the RT register. */ | |
3353 | /* Itbl support may require additional care here. */ | |
3354 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3355 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3356 | { |
71400594 | 3357 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3358 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3359 | return 1; |
3360 | } | |
3361 | ||
3362 | /* Check for generic coprocessor hazards. | |
3363 | ||
3364 | This case is not handled very well. There is no special | |
3365 | knowledge of CP0 handling, and the coprocessors other than | |
3366 | the floating point unit are not distinguished at all. */ | |
3367 | /* Itbl support may require additional care here. FIXME! | |
3368 | Need to modify this to include knowledge about | |
3369 | user specified delays! */ | |
3370 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3371 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3372 | { | |
3373 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3374 | register. There must be a one instruction delay before INSN2 | |
3375 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3376 | mask = fpr_write_mask (insn1); |
3377 | if (mask != 0) | |
252b5132 | 3378 | { |
4c260379 | 3379 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3380 | return 1; |
252b5132 RH |
3381 | } |
3382 | else | |
3383 | { | |
71400594 RS |
3384 | /* Read-after-write dependencies on the control registers |
3385 | require a two-instruction gap. */ | |
3386 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3387 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3388 | return 2; | |
3389 | ||
3390 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3391 | also a coprocessor instruction, assume there must be | |
3392 | a one instruction gap. */ | |
3393 | if (pinfo2 & INSN_COP) | |
3394 | return 1; | |
252b5132 RH |
3395 | } |
3396 | } | |
6b76fefe | 3397 | |
71400594 RS |
3398 | /* Check for read-after-write dependencies on the coprocessor |
3399 | control registers in cases where INSN1 does not need a general | |
3400 | coprocessor delay. This means that INSN1 is a floating point | |
3401 | comparison instruction. */ | |
3402 | /* Itbl support may require additional care here. */ | |
3403 | else if (!cop_interlocks | |
3404 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3405 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3406 | return 1; | |
3407 | } | |
6b76fefe | 3408 | |
4c260379 | 3409 | #undef INSN2_USES_GPR |
6b76fefe | 3410 | |
71400594 RS |
3411 | return 0; |
3412 | } | |
6b76fefe | 3413 | |
7d8e00cf RS |
3414 | /* Return the number of nops that would be needed to work around the |
3415 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3416 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3417 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3418 | |
3419 | static int | |
932d1a1b | 3420 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3421 | const struct mips_cl_insn *insn) |
3422 | { | |
4c260379 RS |
3423 | int i, j; |
3424 | unsigned int mask; | |
7d8e00cf RS |
3425 | |
3426 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3427 | are not affected by the errata. */ | |
3428 | if (insn != 0 | |
3429 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3430 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3431 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3432 | return 0; | |
3433 | ||
3434 | /* Search for the first MFLO or MFHI. */ | |
3435 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3436 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3437 | { |
3438 | /* Extract the destination register. */ | |
4c260379 | 3439 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3440 | |
3441 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3442 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3443 | return 0; |
3444 | ||
3445 | /* ...or if any of the intervening instructions do. */ | |
3446 | for (j = 0; j < i; j++) | |
4c260379 | 3447 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3448 | return 0; |
3449 | ||
932d1a1b RS |
3450 | if (i >= ignore) |
3451 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3452 | } |
3453 | return 0; | |
3454 | } | |
3455 | ||
15be625d CM |
3456 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3457 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3458 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3459 | ||
3460 | /* Return the minimum alignment for this store instruction. */ | |
3461 | ||
3462 | static int | |
3463 | fix_24k_align_to (const struct mips_opcode *mo) | |
3464 | { | |
3465 | if (strcmp (mo->name, "sh") == 0) | |
3466 | return 2; | |
3467 | ||
3468 | if (strcmp (mo->name, "swc1") == 0 | |
3469 | || strcmp (mo->name, "swc2") == 0 | |
3470 | || strcmp (mo->name, "sw") == 0 | |
3471 | || strcmp (mo->name, "sc") == 0 | |
3472 | || strcmp (mo->name, "s.s") == 0) | |
3473 | return 4; | |
3474 | ||
3475 | if (strcmp (mo->name, "sdc1") == 0 | |
3476 | || strcmp (mo->name, "sdc2") == 0 | |
3477 | || strcmp (mo->name, "s.d") == 0) | |
3478 | return 8; | |
3479 | ||
3480 | /* sb, swl, swr */ | |
3481 | return 1; | |
3482 | } | |
3483 | ||
3484 | struct fix_24k_store_info | |
3485 | { | |
3486 | /* Immediate offset, if any, for this store instruction. */ | |
3487 | short off; | |
3488 | /* Alignment required by this store instruction. */ | |
3489 | int align_to; | |
3490 | /* True for register offsets. */ | |
3491 | int register_offset; | |
3492 | }; | |
3493 | ||
3494 | /* Comparison function used by qsort. */ | |
3495 | ||
3496 | static int | |
3497 | fix_24k_sort (const void *a, const void *b) | |
3498 | { | |
3499 | const struct fix_24k_store_info *pos1 = a; | |
3500 | const struct fix_24k_store_info *pos2 = b; | |
3501 | ||
3502 | return (pos1->off - pos2->off); | |
3503 | } | |
3504 | ||
3505 | /* INSN is a store instruction. Try to record the store information | |
3506 | in STINFO. Return false if the information isn't known. */ | |
3507 | ||
3508 | static bfd_boolean | |
3509 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3510 | const struct mips_cl_insn *insn) |
15be625d CM |
3511 | { |
3512 | /* The instruction must have a known offset. */ | |
3513 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3514 | return FALSE; | |
3515 | ||
3516 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3517 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3518 | return TRUE; | |
3519 | } | |
3520 | ||
932d1a1b RS |
3521 | /* Return the number of nops that would be needed to work around the 24k |
3522 | "lost data on stores during refill" errata if instruction INSN | |
3523 | immediately followed the 2 instructions described by HIST. | |
3524 | Ignore hazards that are contained within the first IGNORE | |
3525 | instructions of HIST. | |
3526 | ||
3527 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3528 | for the data cache refills and store data. The following describes | |
3529 | the scenario where the store data could be lost. | |
3530 | ||
3531 | * A data cache miss, due to either a load or a store, causing fill | |
3532 | data to be supplied by the memory subsystem | |
3533 | * The first three doublewords of fill data are returned and written | |
3534 | into the cache | |
3535 | * A sequence of four stores occurs in consecutive cycles around the | |
3536 | final doubleword of the fill: | |
3537 | * Store A | |
3538 | * Store B | |
3539 | * Store C | |
3540 | * Zero, One or more instructions | |
3541 | * Store D | |
3542 | ||
3543 | The four stores A-D must be to different doublewords of the line that | |
3544 | is being filled. The fourth instruction in the sequence above permits | |
3545 | the fill of the final doubleword to be transferred from the FSB into | |
3546 | the cache. In the sequence above, the stores may be either integer | |
3547 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3548 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3549 | different doublewords on the line. If the floating point unit is | |
3550 | running in 1:2 mode, it is not possible to create the sequence above | |
3551 | using only floating point store instructions. | |
15be625d CM |
3552 | |
3553 | In this case, the cache line being filled is incorrectly marked | |
3554 | invalid, thereby losing the data from any store to the line that | |
3555 | occurs between the original miss and the completion of the five | |
3556 | cycle sequence shown above. | |
3557 | ||
932d1a1b | 3558 | The workarounds are: |
15be625d | 3559 | |
932d1a1b RS |
3560 | * Run the data cache in write-through mode. |
3561 | * Insert a non-store instruction between | |
3562 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3563 | |
3564 | static int | |
932d1a1b | 3565 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3566 | const struct mips_cl_insn *insn) |
3567 | { | |
3568 | struct fix_24k_store_info pos[3]; | |
3569 | int align, i, base_offset; | |
3570 | ||
932d1a1b RS |
3571 | if (ignore >= 2) |
3572 | return 0; | |
3573 | ||
ab9794cf RS |
3574 | /* If the previous instruction wasn't a store, there's nothing to |
3575 | worry about. */ | |
15be625d CM |
3576 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3577 | return 0; | |
3578 | ||
ab9794cf RS |
3579 | /* If the instructions after the previous one are unknown, we have |
3580 | to assume the worst. */ | |
3581 | if (!insn) | |
15be625d CM |
3582 | return 1; |
3583 | ||
ab9794cf RS |
3584 | /* Check whether we are dealing with three consecutive stores. */ |
3585 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3586 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3587 | return 0; |
3588 | ||
3589 | /* If we don't know the relationship between the store addresses, | |
3590 | assume the worst. */ | |
ab9794cf | 3591 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3592 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3593 | return 1; | |
3594 | ||
3595 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3596 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3597 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3598 | return 1; | |
3599 | ||
3600 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3601 | ||
3602 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3603 | X bytes and such that the base register + X is known to be aligned | |
3604 | to align bytes. */ | |
3605 | ||
3606 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3607 | align = 8; | |
3608 | else | |
3609 | { | |
3610 | align = pos[0].align_to; | |
3611 | base_offset = pos[0].off; | |
3612 | for (i = 1; i < 3; i++) | |
3613 | if (align < pos[i].align_to) | |
3614 | { | |
3615 | align = pos[i].align_to; | |
3616 | base_offset = pos[i].off; | |
3617 | } | |
3618 | for (i = 0; i < 3; i++) | |
3619 | pos[i].off -= base_offset; | |
3620 | } | |
3621 | ||
3622 | pos[0].off &= ~align + 1; | |
3623 | pos[1].off &= ~align + 1; | |
3624 | pos[2].off &= ~align + 1; | |
3625 | ||
3626 | /* If any two stores write to the same chunk, they also write to the | |
3627 | same doubleword. The offsets are still sorted at this point. */ | |
3628 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3629 | return 0; | |
3630 | ||
3631 | /* A range of at least 9 bytes is needed for the stores to be in | |
3632 | non-overlapping doublewords. */ | |
3633 | if (pos[2].off - pos[0].off <= 8) | |
3634 | return 0; | |
3635 | ||
3636 | if (pos[2].off - pos[1].off >= 24 | |
3637 | || pos[1].off - pos[0].off >= 24 | |
3638 | || pos[2].off - pos[0].off >= 32) | |
3639 | return 0; | |
3640 | ||
3641 | return 1; | |
3642 | } | |
3643 | ||
71400594 | 3644 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3645 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3646 | where HIST[0] is the most recent instruction. Ignore hazards |
3647 | between INSN and the first IGNORE instructions in HIST. | |
3648 | ||
3649 | If INSN is null, return the worse-case number of nops for any | |
3650 | instruction. */ | |
bdaaa2e1 | 3651 | |
71400594 | 3652 | static int |
932d1a1b | 3653 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3654 | const struct mips_cl_insn *insn) |
3655 | { | |
3656 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3657 | |
71400594 | 3658 | nops = 0; |
932d1a1b | 3659 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3660 | { |
91d6fa6a | 3661 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3662 | if (tmp_nops > nops) |
3663 | nops = tmp_nops; | |
3664 | } | |
7d8e00cf | 3665 | |
df58fc94 | 3666 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3667 | { |
932d1a1b | 3668 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3669 | if (tmp_nops > nops) |
3670 | nops = tmp_nops; | |
3671 | } | |
3672 | ||
df58fc94 | 3673 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3674 | { |
932d1a1b | 3675 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3676 | if (tmp_nops > nops) |
3677 | nops = tmp_nops; | |
3678 | } | |
3679 | ||
71400594 RS |
3680 | return nops; |
3681 | } | |
252b5132 | 3682 | |
71400594 | 3683 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3684 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3685 | would be needed after the extended sequence, ignoring hazards |
3686 | in the first IGNORE instructions. */ | |
252b5132 | 3687 | |
71400594 | 3688 | static int |
932d1a1b RS |
3689 | nops_for_sequence (int num_insns, int ignore, |
3690 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3691 | { |
3692 | va_list args; | |
3693 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3694 | struct mips_cl_insn *cursor; | |
3695 | int nops; | |
3696 | ||
91d6fa6a | 3697 | va_start (args, hist); |
71400594 | 3698 | cursor = buffer + num_insns; |
91d6fa6a | 3699 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3700 | while (cursor > buffer) |
3701 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3702 | ||
932d1a1b | 3703 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3704 | va_end (args); |
3705 | return nops; | |
3706 | } | |
252b5132 | 3707 | |
71400594 RS |
3708 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3709 | worst-case delay for the branch target. */ | |
252b5132 | 3710 | |
71400594 | 3711 | static int |
932d1a1b | 3712 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3713 | const struct mips_cl_insn *insn) |
3714 | { | |
3715 | int nops, tmp_nops; | |
60b63b72 | 3716 | |
932d1a1b | 3717 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3718 | if (delayed_branch_p (insn)) |
71400594 | 3719 | { |
932d1a1b | 3720 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3721 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3722 | if (tmp_nops > nops) |
3723 | nops = tmp_nops; | |
3724 | } | |
11625dd8 | 3725 | else if (compact_branch_p (insn)) |
71400594 | 3726 | { |
932d1a1b | 3727 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3728 | if (tmp_nops > nops) |
3729 | nops = tmp_nops; | |
3730 | } | |
3731 | return nops; | |
3732 | } | |
3733 | ||
c67a084a NC |
3734 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3735 | ||
3736 | static void | |
3737 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3738 | { | |
df58fc94 | 3739 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3740 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3741 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3742 | } | |
3743 | ||
3744 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3745 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3746 | ||
3747 | static void | |
3748 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3749 | { | |
df58fc94 | 3750 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3751 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3752 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3753 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3754 | { | |
3755 | int sreg; | |
3756 | expressionS ep; | |
3757 | ||
3758 | if (! mips_opts.at) | |
3759 | return; | |
3760 | ||
df58fc94 | 3761 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3762 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3763 | return; | |
3764 | ||
3765 | ep.X_op = O_constant; | |
3766 | ep.X_add_number = 0xcfff0000; | |
3767 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3768 | ep.X_add_number = 0xffff; | |
3769 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3770 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3771 | } | |
3772 | } | |
3773 | ||
3774 | static void | |
3775 | fix_loongson2f (struct mips_cl_insn * ip) | |
3776 | { | |
3777 | if (mips_fix_loongson2f_nop) | |
3778 | fix_loongson2f_nop (ip); | |
3779 | ||
3780 | if (mips_fix_loongson2f_jump) | |
3781 | fix_loongson2f_jump (ip); | |
3782 | } | |
3783 | ||
a4e06468 RS |
3784 | /* IP is a branch that has a delay slot, and we need to fill it |
3785 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3786 | with the previous instruction. |
3787 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3788 | RELOC_TYPE. */ | |
a4e06468 RS |
3789 | |
3790 | static bfd_boolean | |
e407c74b NC |
3791 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3792 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3793 | { |
2b0c8b40 | 3794 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3795 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3796 | ||
3797 | /* -O2 and above is required for this optimization. */ | |
3798 | if (mips_optimize < 2) | |
3799 | return FALSE; | |
3800 | ||
3801 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3802 | if (mips_opts.nomove) | |
3803 | return FALSE; | |
3804 | ||
3805 | /* We can't swap if the previous instruction's position is fixed. */ | |
3806 | if (history[0].fixed_p) | |
3807 | return FALSE; | |
3808 | ||
3809 | /* If the previous previous insn was in a .set noreorder, we can't | |
3810 | swap. Actually, the MIPS assembler will swap in this situation. | |
3811 | However, gcc configured -with-gnu-as will generate code like | |
3812 | ||
3813 | .set noreorder | |
3814 | lw $4,XXX | |
3815 | .set reorder | |
3816 | INSN | |
3817 | bne $4,$0,foo | |
3818 | ||
3819 | in which we can not swap the bne and INSN. If gcc is not configured | |
3820 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3821 | if (history[1].noreorder_p) | |
3822 | return FALSE; | |
3823 | ||
87333bb7 MR |
3824 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3825 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3826 | if (mips_opts.mips16 && history[0].fixp[0]) |
3827 | return FALSE; | |
3828 | ||
3829 | /* If the branch is itself the target of a branch, we can not swap. | |
3830 | We cheat on this; all we check for is whether there is a label on | |
3831 | this instruction. If there are any branches to anything other than | |
3832 | a label, users must use .set noreorder. */ | |
3833 | if (seg_info (now_seg)->label_list) | |
3834 | return FALSE; | |
3835 | ||
3836 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3837 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3838 | MIPS16 code, which uses variant frags for different purposes. */ |
3839 | if (!mips_opts.mips16 | |
a4e06468 RS |
3840 | && history[0].frag |
3841 | && history[0].frag->fr_type == rs_machine_dependent) | |
3842 | return FALSE; | |
3843 | ||
bcd530a7 RS |
3844 | /* We do not swap with instructions that cannot architecturally |
3845 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3846 | also refrain from swapping with a trap instruction, since it | |
3847 | complicates trap handlers to have the trap instruction be in | |
3848 | a delay slot. */ | |
a4e06468 | 3849 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3850 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3851 | return FALSE; |
3852 | ||
3853 | /* Check for conflicts between the branch and the instructions | |
3854 | before the candidate delay slot. */ | |
3855 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3856 | return FALSE; | |
3857 | ||
3858 | /* Check for conflicts between the swapped sequence and the | |
3859 | target of the branch. */ | |
3860 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3861 | return FALSE; | |
3862 | ||
3863 | /* If the branch reads a register that the previous | |
3864 | instruction sets, we can not swap. */ | |
3865 | gpr_read = gpr_read_mask (ip); | |
3866 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3867 | if (gpr_read & prev_gpr_write) | |
3868 | return FALSE; | |
3869 | ||
3870 | /* If the branch writes a register that the previous | |
3871 | instruction sets, we can not swap. */ | |
3872 | gpr_write = gpr_write_mask (ip); | |
3873 | if (gpr_write & prev_gpr_write) | |
3874 | return FALSE; | |
3875 | ||
3876 | /* If the branch writes a register that the previous | |
3877 | instruction reads, we can not swap. */ | |
3878 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3879 | if (gpr_write & prev_gpr_read) | |
3880 | return FALSE; | |
3881 | ||
3882 | /* If one instruction sets a condition code and the | |
3883 | other one uses a condition code, we can not swap. */ | |
3884 | pinfo = ip->insn_mo->pinfo; | |
3885 | if ((pinfo & INSN_READ_COND_CODE) | |
3886 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3887 | return FALSE; | |
3888 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3889 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3890 | return FALSE; | |
3891 | ||
3892 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3893 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3894 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3895 | return FALSE; | |
2b0c8b40 MR |
3896 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3897 | return FALSE; | |
a4e06468 | 3898 | |
df58fc94 RS |
3899 | /* If the previous instruction has an incorrect size for a fixed |
3900 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3901 | pinfo2 = ip->insn_mo->pinfo2; |
3902 | if (mips_opts.micromips | |
3903 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3904 | && insn_length (history) != 2) | |
3905 | return FALSE; | |
3906 | if (mips_opts.micromips | |
3907 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3908 | && insn_length (history) != 4) | |
3909 | return FALSE; | |
3910 | ||
e407c74b NC |
3911 | /* On R5900 short loops need to be fixed by inserting a nop in |
3912 | the branch delay slots. | |
3913 | A short loop can be terminated too early. */ | |
3914 | if (mips_opts.arch == CPU_R5900 | |
3915 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3916 | && (address_expr != NULL) | |
3917 | /* Parameter must be 16 bit. */ | |
3918 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3919 | /* Branch to same segment. */ | |
3920 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3921 | /* Branch to same code fragment. */ | |
3922 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3923 | /* Can only calculate branch offset if value is known. */ | |
3924 | && symbol_constant_p(address_expr->X_add_symbol) | |
3925 | /* Check if branch is really conditional. */ | |
3926 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3927 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3928 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3929 | { | |
3930 | int distance; | |
3931 | /* Check if loop is shorter than 6 instructions including | |
3932 | branch and delay slot. */ | |
3933 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3934 | if (distance <= 20) | |
3935 | { | |
3936 | int i; | |
3937 | int rv; | |
3938 | ||
3939 | rv = FALSE; | |
3940 | /* When the loop includes branches or jumps, | |
3941 | it is not a short loop. */ | |
3942 | for (i = 0; i < (distance / 4); i++) | |
3943 | { | |
3944 | if ((history[i].cleared_p) | |
3945 | || delayed_branch_p(&history[i])) | |
3946 | { | |
3947 | rv = TRUE; | |
3948 | break; | |
3949 | } | |
3950 | } | |
3951 | if (rv == FALSE) | |
3952 | { | |
3953 | /* Insert nop after branch to fix short loop. */ | |
3954 | return FALSE; | |
3955 | } | |
3956 | } | |
3957 | } | |
3958 | ||
a4e06468 RS |
3959 | return TRUE; |
3960 | } | |
3961 | ||
e407c74b NC |
3962 | /* Decide how we should add IP to the instruction stream. |
3963 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3964 | RELOC_TYPE. */ | |
a4e06468 RS |
3965 | |
3966 | static enum append_method | |
e407c74b NC |
3967 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3968 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3969 | { |
3970 | unsigned long pinfo; | |
3971 | ||
3972 | /* The relaxed version of a macro sequence must be inherently | |
3973 | hazard-free. */ | |
3974 | if (mips_relax.sequence == 2) | |
3975 | return APPEND_ADD; | |
3976 | ||
3977 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3978 | if (mips_opts.noreorder) | |
3979 | return APPEND_ADD; | |
3980 | ||
3981 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3982 | if (delayed_branch_p (ip)) |
a4e06468 | 3983 | { |
e407c74b NC |
3984 | if (!branch_likely_p (ip) |
3985 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
3986 | return APPEND_SWAP; |
3987 | ||
11625dd8 | 3988 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3989 | if (mips_opts.mips16 |
3990 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3991 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3992 | return APPEND_ADD_COMPACT; | |
3993 | ||
3994 | return APPEND_ADD_WITH_NOP; | |
3995 | } | |
3996 | ||
a4e06468 RS |
3997 | return APPEND_ADD; |
3998 | } | |
3999 | ||
ceb94aa5 RS |
4000 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4001 | Point IP->insn_mo to the new opcode's definition. */ | |
4002 | ||
4003 | static void | |
4004 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4005 | { | |
4006 | const struct mips_opcode *mo, *end; | |
4007 | ||
4008 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4009 | for (mo = ip->insn_mo; mo < end; mo++) | |
4010 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4011 | { | |
4012 | ip->insn_mo = mo; | |
4013 | return; | |
4014 | } | |
4015 | abort (); | |
4016 | } | |
4017 | ||
df58fc94 RS |
4018 | /* For microMIPS macros, we need to generate a local number label |
4019 | as the target of branches. */ | |
4020 | #define MICROMIPS_LABEL_CHAR '\037' | |
4021 | static unsigned long micromips_target_label; | |
4022 | static char micromips_target_name[32]; | |
4023 | ||
4024 | static char * | |
4025 | micromips_label_name (void) | |
4026 | { | |
4027 | char *p = micromips_target_name; | |
4028 | char symbol_name_temporary[24]; | |
4029 | unsigned long l; | |
4030 | int i; | |
4031 | ||
4032 | if (*p) | |
4033 | return p; | |
4034 | ||
4035 | i = 0; | |
4036 | l = micromips_target_label; | |
4037 | #ifdef LOCAL_LABEL_PREFIX | |
4038 | *p++ = LOCAL_LABEL_PREFIX; | |
4039 | #endif | |
4040 | *p++ = 'L'; | |
4041 | *p++ = MICROMIPS_LABEL_CHAR; | |
4042 | do | |
4043 | { | |
4044 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4045 | l /= 10; | |
4046 | } | |
4047 | while (l != 0); | |
4048 | while (i > 0) | |
4049 | *p++ = symbol_name_temporary[--i]; | |
4050 | *p = '\0'; | |
4051 | ||
4052 | return micromips_target_name; | |
4053 | } | |
4054 | ||
4055 | static void | |
4056 | micromips_label_expr (expressionS *label_expr) | |
4057 | { | |
4058 | label_expr->X_op = O_symbol; | |
4059 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4060 | label_expr->X_add_number = 0; | |
4061 | } | |
4062 | ||
4063 | static void | |
4064 | micromips_label_inc (void) | |
4065 | { | |
4066 | micromips_target_label++; | |
4067 | *micromips_target_name = '\0'; | |
4068 | } | |
4069 | ||
4070 | static void | |
4071 | micromips_add_label (void) | |
4072 | { | |
4073 | symbolS *s; | |
4074 | ||
4075 | s = colon (micromips_label_name ()); | |
4076 | micromips_label_inc (); | |
4077 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4078 | if (IS_ELF) | |
4079 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4080 | #else |
4081 | (void) s; | |
df58fc94 RS |
4082 | #endif |
4083 | } | |
4084 | ||
4085 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4086 | corresponding to the requested one if any. Otherwise return | |
4087 | the reloc unchanged. */ | |
4088 | ||
4089 | static bfd_reloc_code_real_type | |
4090 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4091 | { | |
4092 | static const bfd_reloc_code_real_type relocs[][2] = | |
4093 | { | |
4094 | /* Keep sorted incrementally by the left-hand key. */ | |
4095 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4096 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4097 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4098 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4099 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4100 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4101 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4102 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4103 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4104 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4105 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4106 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4107 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4108 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4109 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4110 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4111 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4112 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4113 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4114 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4115 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4116 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4117 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4118 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4119 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4120 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4121 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4122 | }; | |
4123 | bfd_reloc_code_real_type r; | |
4124 | size_t i; | |
4125 | ||
4126 | if (!mips_opts.micromips) | |
4127 | return reloc; | |
4128 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4129 | { | |
4130 | r = relocs[i][0]; | |
4131 | if (r > reloc) | |
4132 | return reloc; | |
4133 | if (r == reloc) | |
4134 | return relocs[i][1]; | |
4135 | } | |
4136 | return reloc; | |
4137 | } | |
4138 | ||
b886a2ab RS |
4139 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4140 | Return true on success, storing the resolved value in RESULT. */ | |
4141 | ||
4142 | static bfd_boolean | |
4143 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4144 | offsetT *result) | |
4145 | { | |
4146 | switch (reloc) | |
4147 | { | |
4148 | case BFD_RELOC_MIPS_HIGHEST: | |
4149 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4150 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4151 | return TRUE; | |
4152 | ||
4153 | case BFD_RELOC_MIPS_HIGHER: | |
4154 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4155 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4156 | return TRUE; | |
4157 | ||
4158 | case BFD_RELOC_HI16_S: | |
4159 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4160 | case BFD_RELOC_MIPS16_HI16_S: | |
4161 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4162 | return TRUE; | |
4163 | ||
4164 | case BFD_RELOC_HI16: | |
4165 | case BFD_RELOC_MICROMIPS_HI16: | |
4166 | case BFD_RELOC_MIPS16_HI16: | |
4167 | *result = (operand >> 16) & 0xffff; | |
4168 | return TRUE; | |
4169 | ||
4170 | case BFD_RELOC_LO16: | |
4171 | case BFD_RELOC_MICROMIPS_LO16: | |
4172 | case BFD_RELOC_MIPS16_LO16: | |
4173 | *result = operand & 0xffff; | |
4174 | return TRUE; | |
4175 | ||
4176 | case BFD_RELOC_UNUSED: | |
4177 | *result = operand; | |
4178 | return TRUE; | |
4179 | ||
4180 | default: | |
4181 | return FALSE; | |
4182 | } | |
4183 | } | |
4184 | ||
71400594 RS |
4185 | /* Output an instruction. IP is the instruction information. |
4186 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4187 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4188 | a macro expansion. */ | |
71400594 RS |
4189 | |
4190 | static void | |
4191 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4192 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4193 | { |
14fe068b | 4194 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4195 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4196 | enum append_method method; |
2309ddf2 | 4197 | bfd_boolean relax32; |
2b0c8b40 | 4198 | int branch_disp; |
71400594 | 4199 | |
2309ddf2 | 4200 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4201 | fix_loongson2f (ip); |
4202 | ||
738f4d98 | 4203 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4204 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4205 | |
df58fc94 | 4206 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4207 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4208 | |
4209 | if (mips_opts.micromips | |
4210 | && !expansionp | |
4211 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4212 | && micromips_insn_length (ip->insn_mo) != 2) | |
4213 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4214 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4215 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4216 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4217 | |
15be625d CM |
4218 | if (address_expr == NULL) |
4219 | ip->complete_p = 1; | |
b886a2ab RS |
4220 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4221 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4222 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4223 | && address_expr->X_op == O_constant) |
4224 | { | |
15be625d CM |
4225 | switch (*reloc_type) |
4226 | { | |
15be625d | 4227 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4228 | { |
4229 | int shift; | |
4230 | ||
4231 | shift = mips_opts.micromips ? 1 : 2; | |
4232 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4233 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4234 | (unsigned long) address_expr->X_add_number); | |
4235 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4236 | & 0x3ffffff); | |
335574df | 4237 | ip->complete_p = 1; |
df58fc94 | 4238 | } |
15be625d CM |
4239 | break; |
4240 | ||
4241 | case BFD_RELOC_MIPS16_JMP: | |
4242 | if ((address_expr->X_add_number & 3) != 0) | |
4243 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4244 | (unsigned long) address_expr->X_add_number); | |
4245 | ip->insn_opcode |= | |
4246 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4247 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4248 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4249 | ip->complete_p = 1; |
15be625d CM |
4250 | break; |
4251 | ||
4252 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4253 | { |
4254 | int shift; | |
4255 | ||
4256 | shift = mips_opts.micromips ? 1 : 2; | |
4257 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4258 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4259 | (unsigned long) address_expr->X_add_number); | |
4260 | if (!mips_relax_branch) | |
4261 | { | |
4262 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4263 | & ~((1 << (shift + 16)) - 1)) | |
4264 | as_bad (_("branch address range overflow (0x%lx)"), | |
4265 | (unsigned long) address_expr->X_add_number); | |
4266 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4267 | & 0xffff); | |
4268 | } | |
df58fc94 | 4269 | } |
15be625d CM |
4270 | break; |
4271 | ||
4272 | default: | |
b886a2ab RS |
4273 | { |
4274 | offsetT value; | |
4275 | ||
4276 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4277 | &value)) | |
4278 | { | |
4279 | ip->insn_opcode |= value & 0xffff; | |
4280 | ip->complete_p = 1; | |
4281 | } | |
4282 | } | |
4283 | break; | |
4284 | } | |
15be625d CM |
4285 | } |
4286 | ||
71400594 RS |
4287 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4288 | { | |
4289 | /* There are a lot of optimizations we could do that we don't. | |
4290 | In particular, we do not, in general, reorder instructions. | |
4291 | If you use gcc with optimization, it will reorder | |
4292 | instructions and generally do much more optimization then we | |
4293 | do here; repeating all that work in the assembler would only | |
4294 | benefit hand written assembly code, and does not seem worth | |
4295 | it. */ | |
4296 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4297 | ? nops_for_insn (0, history, NULL) |
4298 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4299 | if (nops > 0) |
252b5132 RH |
4300 | { |
4301 | fragS *old_frag; | |
4302 | unsigned long old_frag_offset; | |
4303 | int i; | |
252b5132 RH |
4304 | |
4305 | old_frag = frag_now; | |
4306 | old_frag_offset = frag_now_fix (); | |
4307 | ||
4308 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4309 | add_fixed_insn (NOP_INSN); |
4310 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4311 | |
4312 | if (listing) | |
4313 | { | |
4314 | listing_prev_line (); | |
4315 | /* We may be at the start of a variant frag. In case we | |
4316 | are, make sure there is enough space for the frag | |
4317 | after the frags created by listing_prev_line. The | |
4318 | argument to frag_grow here must be at least as large | |
4319 | as the argument to all other calls to frag_grow in | |
4320 | this file. We don't have to worry about being in the | |
4321 | middle of a variant frag, because the variants insert | |
4322 | all needed nop instructions themselves. */ | |
4323 | frag_grow (40); | |
4324 | } | |
4325 | ||
462427c4 | 4326 | mips_move_text_labels (); |
252b5132 RH |
4327 | |
4328 | #ifndef NO_ECOFF_DEBUGGING | |
4329 | if (ECOFF_DEBUGGING) | |
4330 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4331 | #endif | |
4332 | } | |
71400594 RS |
4333 | } |
4334 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4335 | { | |
932d1a1b RS |
4336 | int nops; |
4337 | ||
4338 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4339 | ignoring hazards generated by the first prev_nop_frag_since | |
4340 | instructions. */ | |
4341 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4342 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4343 | |
71400594 RS |
4344 | /* Enforce NOPS as a minimum. */ |
4345 | if (nops > prev_nop_frag_required) | |
4346 | prev_nop_frag_required = nops; | |
252b5132 | 4347 | |
71400594 RS |
4348 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4349 | { | |
4350 | /* Settle for the current number of nops. Update the history | |
4351 | accordingly (for the benefit of any future .set reorder code). */ | |
4352 | prev_nop_frag = NULL; | |
4353 | insert_into_history (prev_nop_frag_since, | |
4354 | prev_nop_frag_holds, NOP_INSN); | |
4355 | } | |
4356 | else | |
4357 | { | |
4358 | /* Allow this instruction to replace one of the nops that was | |
4359 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4360 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4361 | prev_nop_frag_holds--; |
4362 | prev_nop_frag_since++; | |
252b5132 RH |
4363 | } |
4364 | } | |
4365 | ||
e407c74b | 4366 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4367 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4368 | |
58e2ea4d MR |
4369 | #ifdef OBJ_ELF |
4370 | /* The value passed to dwarf2_emit_insn is the distance between | |
4371 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4372 | should be recorded in the debug tables. This is normally the |
4373 | current address. | |
4374 | ||
df58fc94 RS |
4375 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4376 | addresses, so we use -1 for an address higher by one than the | |
4377 | current one. | |
e3a82c8e MR |
4378 | |
4379 | If the instruction produced is a branch that we will swap with | |
4380 | the preceding instruction, then we add the displacement by which | |
4381 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4382 | and for MIPS16/microMIPS code also prevents a debugger from |
4383 | placing a breakpoint in the middle of the branch (and corrupting | |
4384 | code if software breakpoints are used). */ | |
2b0c8b40 | 4385 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4386 | #endif |
4387 | ||
df58fc94 RS |
4388 | relax32 = (mips_relax_branch |
4389 | /* Don't try branch relaxation within .set nomacro, or within | |
4390 | .set noat if we use $at for PIC computations. If it turns | |
4391 | out that the branch was out-of-range, we'll get an error. */ | |
4392 | && !mips_opts.warn_about_macros | |
4393 | && (mips_opts.at || mips_pic == NO_PIC) | |
4394 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4395 | branches. */ | |
40209cad | 4396 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4397 | |
4398 | if (!HAVE_CODE_COMPRESSION | |
4399 | && address_expr | |
4400 | && relax32 | |
0b25d3e6 | 4401 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4402 | && delayed_branch_p (ip)) |
4a6a3df4 | 4403 | { |
895921c9 | 4404 | relaxed_branch = TRUE; |
1e915849 RS |
4405 | add_relaxed_insn (ip, (relaxed_branch_length |
4406 | (NULL, NULL, | |
11625dd8 RS |
4407 | uncond_branch_p (ip) ? -1 |
4408 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4409 | : 0)), 4, |
4410 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4411 | (AT, |
11625dd8 RS |
4412 | uncond_branch_p (ip), |
4413 | branch_likely_p (ip), | |
1e915849 RS |
4414 | pinfo & INSN_WRITE_GPR_31, |
4415 | 0), | |
4416 | address_expr->X_add_symbol, | |
4417 | address_expr->X_add_number); | |
4a6a3df4 AO |
4418 | *reloc_type = BFD_RELOC_UNUSED; |
4419 | } | |
df58fc94 RS |
4420 | else if (mips_opts.micromips |
4421 | && address_expr | |
4422 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4423 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4424 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4425 | /* Don't try branch relaxation when users specify | |
4426 | 16-bit/32-bit instructions. */ | |
4427 | && !forced_insn_length) | |
df58fc94 RS |
4428 | { |
4429 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4430 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4431 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4432 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4433 | int al = pinfo & INSN_WRITE_GPR_31; |
4434 | int length32; | |
4435 | ||
4436 | gas_assert (address_expr != NULL); | |
4437 | gas_assert (!mips_relax.sequence); | |
4438 | ||
2b0c8b40 | 4439 | relaxed_branch = TRUE; |
df58fc94 RS |
4440 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4441 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4442 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4443 | relax32, 0, 0), | |
df58fc94 RS |
4444 | address_expr->X_add_symbol, |
4445 | address_expr->X_add_number); | |
4446 | *reloc_type = BFD_RELOC_UNUSED; | |
4447 | } | |
4448 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4449 | { |
4450 | /* We need to set up a variant frag. */ | |
df58fc94 | 4451 | gas_assert (address_expr != NULL); |
1e915849 RS |
4452 | add_relaxed_insn (ip, 4, 0, |
4453 | RELAX_MIPS16_ENCODE | |
4454 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4455 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4456 | delayed_branch_p (&history[0]), |
1e915849 RS |
4457 | history[0].mips16_absolute_jump_p), |
4458 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4459 | } |
5c04167a | 4460 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4461 | { |
11625dd8 | 4462 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4463 | /* Make sure there is enough room to swap this instruction with |
4464 | a following jump instruction. */ | |
4465 | frag_grow (6); | |
1e915849 | 4466 | add_fixed_insn (ip); |
252b5132 RH |
4467 | } |
4468 | else | |
4469 | { | |
4470 | if (mips_opts.mips16 | |
4471 | && mips_opts.noreorder | |
11625dd8 | 4472 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4473 | as_warn (_("extended instruction in delay slot")); |
4474 | ||
4d7206a2 RS |
4475 | if (mips_relax.sequence) |
4476 | { | |
4477 | /* If we've reached the end of this frag, turn it into a variant | |
4478 | frag and record the information for the instructions we've | |
4479 | written so far. */ | |
4480 | if (frag_room () < 4) | |
4481 | relax_close_frag (); | |
df58fc94 | 4482 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4483 | } |
4484 | ||
584892a6 | 4485 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4486 | { |
4487 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4488 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4489 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4490 | mips_macro_warning.insns[0]++; | |
4491 | } | |
584892a6 | 4492 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4493 | { |
4494 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4495 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4496 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4497 | mips_macro_warning.insns[1]++; | |
4498 | } | |
584892a6 | 4499 | |
1e915849 RS |
4500 | if (mips_opts.mips16) |
4501 | { | |
4502 | ip->fixed_p = 1; | |
4503 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4504 | } | |
4505 | add_fixed_insn (ip); | |
252b5132 RH |
4506 | } |
4507 | ||
9fe77896 | 4508 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4509 | { |
df58fc94 | 4510 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4511 | reloc_howto_type *howto0; |
9fe77896 RS |
4512 | reloc_howto_type *howto; |
4513 | int i; | |
34ce925e | 4514 | |
df58fc94 RS |
4515 | /* Perform any necessary conversion to microMIPS relocations |
4516 | and find out how many relocations there actually are. */ | |
4517 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4518 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4519 | ||
9fe77896 RS |
4520 | /* In a compound relocation, it is the final (outermost) |
4521 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4522 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4523 | ||
9fe77896 RS |
4524 | if (howto == NULL) |
4525 | { | |
4526 | /* To reproduce this failure try assembling gas/testsuites/ | |
4527 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4528 | assembler. */ | |
df58fc94 RS |
4529 | as_bad (_("Unsupported MIPS relocation number %d"), |
4530 | final_type[i - 1]); | |
9fe77896 RS |
4531 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4532 | } | |
2309ddf2 MR |
4533 | |
4534 | if (i > 1) | |
4535 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4536 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4537 | bfd_get_reloc_size (howto), | |
4538 | address_expr, | |
2309ddf2 MR |
4539 | howto0 && howto0->pc_relative, |
4540 | final_type[0]); | |
9fe77896 RS |
4541 | |
4542 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4543 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4544 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4545 | ||
4546 | /* These relocations can have an addend that won't fit in | |
4547 | 4 octets for 64bit assembly. */ | |
4548 | if (HAVE_64BIT_GPRS | |
4549 | && ! howto->partial_inplace | |
4550 | && (reloc_type[0] == BFD_RELOC_16 | |
4551 | || reloc_type[0] == BFD_RELOC_32 | |
4552 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4553 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4554 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4555 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4556 | || reloc_type[0] == BFD_RELOC_64 | |
4557 | || reloc_type[0] == BFD_RELOC_CTOR | |
4558 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4559 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4560 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4561 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4562 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4563 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4564 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4565 | || hi16_reloc_p (reloc_type[0]) | |
4566 | || lo16_reloc_p (reloc_type[0]))) | |
4567 | ip->fixp[0]->fx_no_overflow = 1; | |
4568 | ||
ddaf2c41 MR |
4569 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4570 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4571 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4572 | ip->fixp[0]->fx_no_overflow = 1; | |
4573 | ||
9fe77896 RS |
4574 | if (mips_relax.sequence) |
4575 | { | |
4576 | if (mips_relax.first_fixup == 0) | |
4577 | mips_relax.first_fixup = ip->fixp[0]; | |
4578 | } | |
4579 | else if (reloc_needs_lo_p (*reloc_type)) | |
4580 | { | |
4581 | struct mips_hi_fixup *hi_fixup; | |
4582 | ||
4583 | /* Reuse the last entry if it already has a matching %lo. */ | |
4584 | hi_fixup = mips_hi_fixup_list; | |
4585 | if (hi_fixup == 0 | |
4586 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4587 | { |
9fe77896 RS |
4588 | hi_fixup = ((struct mips_hi_fixup *) |
4589 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4590 | hi_fixup->next = mips_hi_fixup_list; | |
4591 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4592 | } |
9fe77896 RS |
4593 | hi_fixup->fixp = ip->fixp[0]; |
4594 | hi_fixup->seg = now_seg; | |
4595 | } | |
252b5132 | 4596 | |
9fe77896 RS |
4597 | /* Add fixups for the second and third relocations, if given. |
4598 | Note that the ABI allows the second relocation to be | |
4599 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4600 | moment we only use RSS_UNDEF, but we could add support | |
4601 | for the others if it ever becomes necessary. */ | |
4602 | for (i = 1; i < 3; i++) | |
4603 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4604 | { | |
4605 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4606 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4607 | FALSE, final_type[i]); |
f6688943 | 4608 | |
9fe77896 RS |
4609 | /* Use fx_tcbit to mark compound relocs. */ |
4610 | ip->fixp[0]->fx_tcbit = 1; | |
4611 | ip->fixp[i]->fx_tcbit = 1; | |
4612 | } | |
252b5132 | 4613 | } |
1e915849 | 4614 | install_insn (ip); |
252b5132 RH |
4615 | |
4616 | /* Update the register mask information. */ | |
4c260379 RS |
4617 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4618 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4619 | |
a4e06468 | 4620 | switch (method) |
252b5132 | 4621 | { |
a4e06468 RS |
4622 | case APPEND_ADD: |
4623 | insert_into_history (0, 1, ip); | |
4624 | break; | |
4625 | ||
4626 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4627 | { |
4628 | struct mips_cl_insn *nop; | |
4629 | ||
4630 | insert_into_history (0, 1, ip); | |
4631 | nop = get_delay_slot_nop (ip); | |
4632 | add_fixed_insn (nop); | |
4633 | insert_into_history (0, 1, nop); | |
4634 | if (mips_relax.sequence) | |
4635 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4636 | } | |
a4e06468 RS |
4637 | break; |
4638 | ||
4639 | case APPEND_ADD_COMPACT: | |
4640 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4641 | gas_assert (mips_opts.mips16); | |
4642 | ip->insn_opcode |= 0x0080; | |
4643 | find_altered_mips16_opcode (ip); | |
4644 | install_insn (ip); | |
4645 | insert_into_history (0, 1, ip); | |
4646 | break; | |
4647 | ||
4648 | case APPEND_SWAP: | |
4649 | { | |
4650 | struct mips_cl_insn delay = history[0]; | |
4651 | if (mips_opts.mips16) | |
4652 | { | |
4653 | know (delay.frag == ip->frag); | |
4654 | move_insn (ip, delay.frag, delay.where); | |
4655 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4656 | } | |
464ab0e5 | 4657 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4658 | { |
4659 | /* Add the delay slot instruction to the end of the | |
4660 | current frag and shrink the fixed part of the | |
4661 | original frag. If the branch occupies the tail of | |
4662 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4663 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4664 | if (delay.frag == ip->frag) |
2b0c8b40 | 4665 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4666 | add_fixed_insn (&delay); |
4667 | } | |
4668 | else | |
4669 | { | |
2b0c8b40 MR |
4670 | move_insn (&delay, ip->frag, |
4671 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4672 | move_insn (ip, history[0].frag, history[0].where); |
4673 | } | |
4674 | history[0] = *ip; | |
4675 | delay.fixed_p = 1; | |
4676 | insert_into_history (0, 1, &delay); | |
4677 | } | |
4678 | break; | |
252b5132 RH |
4679 | } |
4680 | ||
13408f1e | 4681 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4682 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4683 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4684 | { |
4685 | unsigned int i; | |
4686 | ||
79850f26 | 4687 | mips_no_prev_insn (); |
13408f1e | 4688 | |
e407c74b | 4689 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4690 | history[i].cleared_p = 1; |
e407c74b NC |
4691 | } |
4692 | ||
df58fc94 RS |
4693 | /* We need to emit a label at the end of branch-likely macros. */ |
4694 | if (emit_branch_likely_macro) | |
4695 | { | |
4696 | emit_branch_likely_macro = FALSE; | |
4697 | micromips_add_label (); | |
4698 | } | |
4699 | ||
252b5132 RH |
4700 | /* We just output an insn, so the next one doesn't have a label. */ |
4701 | mips_clear_insn_labels (); | |
252b5132 RH |
4702 | } |
4703 | ||
e407c74b NC |
4704 | /* Forget that there was any previous instruction or label. |
4705 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4706 | |
4707 | static void | |
7d10b47d | 4708 | mips_no_prev_insn (void) |
252b5132 | 4709 | { |
7d10b47d RS |
4710 | prev_nop_frag = NULL; |
4711 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4712 | mips_clear_insn_labels (); |
4713 | } | |
4714 | ||
7d10b47d RS |
4715 | /* This function must be called before we emit something other than |
4716 | instructions. It is like mips_no_prev_insn except that it inserts | |
4717 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4718 | |
7d10b47d RS |
4719 | void |
4720 | mips_emit_delays (void) | |
252b5132 RH |
4721 | { |
4722 | if (! mips_opts.noreorder) | |
4723 | { | |
932d1a1b | 4724 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4725 | if (nops > 0) |
4726 | { | |
7d10b47d RS |
4727 | while (nops-- > 0) |
4728 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4729 | mips_move_text_labels (); |
7d10b47d RS |
4730 | } |
4731 | } | |
4732 | mips_no_prev_insn (); | |
4733 | } | |
4734 | ||
4735 | /* Start a (possibly nested) noreorder block. */ | |
4736 | ||
4737 | static void | |
4738 | start_noreorder (void) | |
4739 | { | |
4740 | if (mips_opts.noreorder == 0) | |
4741 | { | |
4742 | unsigned int i; | |
4743 | int nops; | |
4744 | ||
4745 | /* None of the instructions before the .set noreorder can be moved. */ | |
4746 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4747 | history[i].fixed_p = 1; | |
4748 | ||
4749 | /* Insert any nops that might be needed between the .set noreorder | |
4750 | block and the previous instructions. We will later remove any | |
4751 | nops that turn out not to be needed. */ | |
932d1a1b | 4752 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4753 | if (nops > 0) |
4754 | { | |
4755 | if (mips_optimize != 0) | |
252b5132 RH |
4756 | { |
4757 | /* Record the frag which holds the nop instructions, so | |
4758 | that we can remove them if we don't need them. */ | |
df58fc94 | 4759 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4760 | prev_nop_frag = frag_now; |
4761 | prev_nop_frag_holds = nops; | |
4762 | prev_nop_frag_required = 0; | |
4763 | prev_nop_frag_since = 0; | |
4764 | } | |
4765 | ||
4766 | for (; nops > 0; --nops) | |
1e915849 | 4767 | add_fixed_insn (NOP_INSN); |
252b5132 | 4768 | |
7d10b47d RS |
4769 | /* Move on to a new frag, so that it is safe to simply |
4770 | decrease the size of prev_nop_frag. */ | |
4771 | frag_wane (frag_now); | |
4772 | frag_new (0); | |
462427c4 | 4773 | mips_move_text_labels (); |
252b5132 | 4774 | } |
df58fc94 | 4775 | mips_mark_labels (); |
7d10b47d | 4776 | mips_clear_insn_labels (); |
252b5132 | 4777 | } |
7d10b47d RS |
4778 | mips_opts.noreorder++; |
4779 | mips_any_noreorder = 1; | |
4780 | } | |
252b5132 | 4781 | |
7d10b47d | 4782 | /* End a nested noreorder block. */ |
252b5132 | 4783 | |
7d10b47d RS |
4784 | static void |
4785 | end_noreorder (void) | |
4786 | { | |
4787 | mips_opts.noreorder--; | |
4788 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4789 | { | |
4790 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4791 | handling nop insertion the .set reorder way. */ | |
4792 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4793 | * NOP_INSN_SIZE); |
7d10b47d RS |
4794 | insert_into_history (prev_nop_frag_since, |
4795 | prev_nop_frag_required, NOP_INSN); | |
4796 | prev_nop_frag = NULL; | |
4797 | } | |
252b5132 RH |
4798 | } |
4799 | ||
584892a6 RS |
4800 | /* Set up global variables for the start of a new macro. */ |
4801 | ||
4802 | static void | |
4803 | macro_start (void) | |
4804 | { | |
4805 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4806 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4807 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4808 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4809 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4810 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4811 | switch (history[0].insn_mo->pinfo2 |
4812 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4813 | { | |
4814 | case INSN2_BRANCH_DELAY_32BIT: | |
4815 | mips_macro_warning.delay_slot_length = 4; | |
4816 | break; | |
4817 | case INSN2_BRANCH_DELAY_16BIT: | |
4818 | mips_macro_warning.delay_slot_length = 2; | |
4819 | break; | |
4820 | default: | |
4821 | mips_macro_warning.delay_slot_length = 0; | |
4822 | break; | |
4823 | } | |
4824 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4825 | } |
4826 | ||
df58fc94 RS |
4827 | /* Given that a macro is longer than one instruction or of the wrong size, |
4828 | return the appropriate warning for it. Return null if no warning is | |
4829 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4830 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4831 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4832 | |
4833 | static const char * | |
4834 | macro_warning (relax_substateT subtype) | |
4835 | { | |
4836 | if (subtype & RELAX_DELAY_SLOT) | |
4837 | return _("Macro instruction expanded into multiple instructions" | |
4838 | " in a branch delay slot"); | |
4839 | else if (subtype & RELAX_NOMACRO) | |
4840 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4841 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4842 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4843 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4844 | ? _("Macro instruction expanded into a wrong size instruction" | |
4845 | " in a 16-bit branch delay slot") | |
4846 | : _("Macro instruction expanded into a wrong size instruction" | |
4847 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4848 | else |
4849 | return 0; | |
4850 | } | |
4851 | ||
4852 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4853 | ||
4854 | static void | |
4855 | macro_end (void) | |
4856 | { | |
df58fc94 RS |
4857 | /* Relaxation warning flags. */ |
4858 | relax_substateT subtype = 0; | |
4859 | ||
4860 | /* Check delay slot size requirements. */ | |
4861 | if (mips_macro_warning.delay_slot_length == 2) | |
4862 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4863 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4864 | { |
df58fc94 RS |
4865 | if (mips_macro_warning.delay_slot_length |
4866 | != mips_macro_warning.first_insn_sizes[0]) | |
4867 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4868 | if (mips_macro_warning.delay_slot_length | |
4869 | != mips_macro_warning.first_insn_sizes[1]) | |
4870 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4871 | } | |
584892a6 | 4872 | |
df58fc94 RS |
4873 | /* Check instruction count requirements. */ |
4874 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4875 | { | |
4876 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4877 | subtype |= RELAX_SECOND_LONGER; |
4878 | if (mips_opts.warn_about_macros) | |
4879 | subtype |= RELAX_NOMACRO; | |
4880 | if (mips_macro_warning.delay_slot_p) | |
4881 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4882 | } |
584892a6 | 4883 | |
df58fc94 RS |
4884 | /* If both alternatives fail to fill a delay slot correctly, |
4885 | emit the warning now. */ | |
4886 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4887 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4888 | { | |
4889 | relax_substateT s; | |
4890 | const char *msg; | |
4891 | ||
4892 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4893 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4894 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4895 | msg = macro_warning (s); | |
4896 | if (msg != NULL) | |
4897 | as_warn ("%s", msg); | |
4898 | subtype &= ~s; | |
4899 | } | |
4900 | ||
4901 | /* If both implementations are longer than 1 instruction, then emit the | |
4902 | warning now. */ | |
4903 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4904 | { | |
4905 | relax_substateT s; | |
4906 | const char *msg; | |
4907 | ||
4908 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4909 | msg = macro_warning (s); | |
4910 | if (msg != NULL) | |
4911 | as_warn ("%s", msg); | |
4912 | subtype &= ~s; | |
584892a6 | 4913 | } |
df58fc94 RS |
4914 | |
4915 | /* If any flags still set, then one implementation might need a warning | |
4916 | and the other either will need one of a different kind or none at all. | |
4917 | Pass any remaining flags over to relaxation. */ | |
4918 | if (mips_macro_warning.first_frag != NULL) | |
4919 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4920 | } |
4921 | ||
df58fc94 RS |
4922 | /* Instruction operand formats used in macros that vary between |
4923 | standard MIPS and microMIPS code. */ | |
4924 | ||
4925 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4926 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4927 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4928 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4929 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4930 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4931 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4932 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4933 | ||
4934 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4935 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4936 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4937 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4938 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4939 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4940 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4941 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4942 | ||
6e1304d8 RS |
4943 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4944 | The first argument in *ARGS will be either the code for a single | |
4945 | relocation or -1 followed by the three codes that make up a | |
4946 | composite relocation. */ | |
4947 | ||
4948 | static void | |
4949 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4950 | { | |
4951 | int i, next; | |
4952 | ||
4953 | next = va_arg (*args, int); | |
4954 | if (next >= 0) | |
4955 | r[0] = (bfd_reloc_code_real_type) next; | |
4956 | else | |
4957 | for (i = 0; i < 3; i++) | |
4958 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4959 | } | |
4960 | ||
252b5132 RH |
4961 | /* Build an instruction created by a macro expansion. This is passed |
4962 | a pointer to the count of instructions created so far, an | |
4963 | expression, the name of the instruction to build, an operand format | |
4964 | string, and corresponding arguments. */ | |
4965 | ||
252b5132 | 4966 | static void |
67c0d1eb | 4967 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4968 | { |
df58fc94 | 4969 | const struct mips_opcode *mo = NULL; |
f6688943 | 4970 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4971 | const struct mips_opcode *amo; |
4972 | struct hash_control *hash; | |
4973 | struct mips_cl_insn insn; | |
252b5132 | 4974 | va_list args; |
252b5132 | 4975 | |
252b5132 | 4976 | va_start (args, fmt); |
252b5132 | 4977 | |
252b5132 RH |
4978 | if (mips_opts.mips16) |
4979 | { | |
03ea81db | 4980 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4981 | va_end (args); |
4982 | return; | |
4983 | } | |
4984 | ||
f6688943 TS |
4985 | r[0] = BFD_RELOC_UNUSED; |
4986 | r[1] = BFD_RELOC_UNUSED; | |
4987 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4988 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4989 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4990 | gas_assert (amo); | |
4991 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4992 | |
df58fc94 | 4993 | do |
8b082fb1 TS |
4994 | { |
4995 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4996 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4997 | We try to match an instruction that fulfils the branch delay | |
4998 | slot instruction length requirement (if any) of the previous | |
4999 | instruction. While doing this we record the first instruction | |
5000 | seen that matches all the other conditions and use it anyway | |
5001 | if the requirement cannot be met; we will issue an appropriate | |
5002 | warning later on. */ | |
5003 | if (strcmp (fmt, amo->args) == 0 | |
5004 | && amo->pinfo != INSN_MACRO | |
5005 | && is_opcode_valid (amo) | |
5006 | && is_size_valid (amo)) | |
5007 | { | |
5008 | if (is_delay_slot_valid (amo)) | |
5009 | { | |
5010 | mo = amo; | |
5011 | break; | |
5012 | } | |
5013 | else if (!mo) | |
5014 | mo = amo; | |
5015 | } | |
8b082fb1 | 5016 | |
df58fc94 RS |
5017 | ++amo; |
5018 | gas_assert (amo->name); | |
252b5132 | 5019 | } |
df58fc94 | 5020 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5021 | |
df58fc94 | 5022 | gas_assert (mo); |
1e915849 | 5023 | create_insn (&insn, mo); |
252b5132 RH |
5024 | for (;;) |
5025 | { | |
5026 | switch (*fmt++) | |
5027 | { | |
5028 | case '\0': | |
5029 | break; | |
5030 | ||
5031 | case ',': | |
5032 | case '(': | |
5033 | case ')': | |
5034 | continue; | |
5035 | ||
5f74bc13 CD |
5036 | case '+': |
5037 | switch (*fmt++) | |
5038 | { | |
5039 | case 'A': | |
5040 | case 'E': | |
df58fc94 RS |
5041 | INSERT_OPERAND (mips_opts.micromips, |
5042 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5043 | continue; |
5044 | ||
5045 | case 'B': | |
5046 | case 'F': | |
5047 | /* Note that in the macro case, these arguments are already | |
5048 | in MSB form. (When handling the instruction in the | |
5049 | non-macro case, these arguments are sizes from which | |
5050 | MSB values must be calculated.) */ | |
df58fc94 RS |
5051 | INSERT_OPERAND (mips_opts.micromips, |
5052 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5053 | continue; |
5054 | ||
b015e599 AP |
5055 | case 'J': |
5056 | gas_assert (!mips_opts.micromips); | |
5057 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5058 | continue; | |
5059 | ||
5f74bc13 CD |
5060 | case 'C': |
5061 | case 'G': | |
5062 | case 'H': | |
5063 | /* Note that in the macro case, these arguments are already | |
5064 | in MSBD form. (When handling the instruction in the | |
5065 | non-macro case, these arguments are sizes from which | |
5066 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5067 | INSERT_OPERAND (mips_opts.micromips, |
5068 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5069 | continue; |
5070 | ||
dd3cbb7e | 5071 | case 'Q': |
df58fc94 RS |
5072 | gas_assert (!mips_opts.micromips); |
5073 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5074 | continue; |
5075 | ||
5f74bc13 | 5076 | default: |
b37df7c4 | 5077 | abort (); |
5f74bc13 CD |
5078 | } |
5079 | continue; | |
5080 | ||
8b082fb1 | 5081 | case '2': |
03f66e8a | 5082 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5083 | continue; |
5084 | ||
df58fc94 RS |
5085 | case 'n': |
5086 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5087 | case 't': |
5088 | case 'w': | |
5089 | case 'E': | |
df58fc94 | 5090 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5091 | continue; |
5092 | ||
5093 | case 'c': | |
df58fc94 RS |
5094 | gas_assert (!mips_opts.micromips); |
5095 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5096 | continue; |
5097 | ||
252b5132 | 5098 | case 'W': |
df58fc94 RS |
5099 | gas_assert (!mips_opts.micromips); |
5100 | case 'T': | |
5101 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5102 | continue; |
5103 | ||
252b5132 | 5104 | case 'G': |
df58fc94 RS |
5105 | if (mips_opts.micromips) |
5106 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5107 | else | |
5108 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5109 | continue; | |
5110 | ||
af7ee8bf | 5111 | case 'K': |
df58fc94 RS |
5112 | gas_assert (!mips_opts.micromips); |
5113 | case 'd': | |
5114 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5115 | continue; |
5116 | ||
4372b673 | 5117 | case 'U': |
df58fc94 | 5118 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5119 | { |
5120 | int tmp = va_arg (args, int); | |
5121 | ||
df58fc94 RS |
5122 | INSERT_OPERAND (0, RT, insn, tmp); |
5123 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5124 | } |
df58fc94 | 5125 | continue; |
4372b673 | 5126 | |
252b5132 RH |
5127 | case 'V': |
5128 | case 'S': | |
df58fc94 RS |
5129 | gas_assert (!mips_opts.micromips); |
5130 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5131 | continue; |
5132 | ||
5133 | case 'z': | |
5134 | continue; | |
5135 | ||
5136 | case '<': | |
df58fc94 RS |
5137 | INSERT_OPERAND (mips_opts.micromips, |
5138 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5139 | continue; |
5140 | ||
5141 | case 'D': | |
df58fc94 RS |
5142 | gas_assert (!mips_opts.micromips); |
5143 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5144 | continue; |
5145 | ||
5146 | case 'B': | |
df58fc94 RS |
5147 | gas_assert (!mips_opts.micromips); |
5148 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5149 | continue; |
5150 | ||
4372b673 | 5151 | case 'J': |
df58fc94 RS |
5152 | gas_assert (!mips_opts.micromips); |
5153 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5154 | continue; |
5155 | ||
252b5132 | 5156 | case 'q': |
df58fc94 RS |
5157 | gas_assert (!mips_opts.micromips); |
5158 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5159 | continue; |
5160 | ||
5161 | case 'b': | |
5162 | case 's': | |
5163 | case 'r': | |
5164 | case 'v': | |
df58fc94 | 5165 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5166 | continue; |
5167 | ||
5168 | case 'i': | |
5169 | case 'j': | |
6e1304d8 | 5170 | macro_read_relocs (&args, r); |
9c2799c2 | 5171 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5172 | || *r == BFD_RELOC_MIPS_HIGHER |
5173 | || *r == BFD_RELOC_HI16_S | |
5174 | || *r == BFD_RELOC_LO16 | |
5175 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5176 | continue; | |
5177 | ||
5178 | case 'o': | |
5179 | macro_read_relocs (&args, r); | |
252b5132 RH |
5180 | continue; |
5181 | ||
5182 | case 'u': | |
6e1304d8 | 5183 | macro_read_relocs (&args, r); |
9c2799c2 | 5184 | gas_assert (ep != NULL |
90ecf173 MR |
5185 | && (ep->X_op == O_constant |
5186 | || (ep->X_op == O_symbol | |
5187 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5188 | || *r == BFD_RELOC_HI16_S | |
5189 | || *r == BFD_RELOC_HI16 | |
5190 | || *r == BFD_RELOC_GPREL16 | |
5191 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5192 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5193 | continue; |
5194 | ||
5195 | case 'p': | |
9c2799c2 | 5196 | gas_assert (ep != NULL); |
bad36eac | 5197 | |
252b5132 RH |
5198 | /* |
5199 | * This allows macro() to pass an immediate expression for | |
5200 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5201 | * |
5202 | * We don't allow branch relaxation for these branches, as | |
5203 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5204 | */ |
5205 | if (ep->X_op == O_constant) | |
5206 | { | |
df58fc94 RS |
5207 | /* For microMIPS we always use relocations for branches. |
5208 | So we should not resolve immediate values. */ | |
5209 | gas_assert (!mips_opts.micromips); | |
5210 | ||
bad36eac DJ |
5211 | if ((ep->X_add_number & 3) != 0) |
5212 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5213 | (unsigned long) ep->X_add_number); | |
5214 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5215 | as_bad (_("branch address range overflow (0x%lx)"), | |
5216 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5217 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5218 | ep = NULL; | |
5219 | } | |
5220 | else | |
0b25d3e6 | 5221 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5222 | continue; |
5223 | ||
5224 | case 'a': | |
9c2799c2 | 5225 | gas_assert (ep != NULL); |
f6688943 | 5226 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5227 | continue; |
5228 | ||
5229 | case 'C': | |
df58fc94 RS |
5230 | gas_assert (!mips_opts.micromips); |
5231 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5232 | continue; |
5233 | ||
d43b4baf | 5234 | case 'k': |
df58fc94 RS |
5235 | INSERT_OPERAND (mips_opts.micromips, |
5236 | CACHE, insn, va_arg (args, unsigned long)); | |
5237 | continue; | |
5238 | ||
5239 | case '|': | |
5240 | gas_assert (mips_opts.micromips); | |
5241 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5242 | continue; | |
5243 | ||
5244 | case '.': | |
5245 | gas_assert (mips_opts.micromips); | |
5246 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5247 | continue; | |
5248 | ||
dec0624d MR |
5249 | case '\\': |
5250 | INSERT_OPERAND (mips_opts.micromips, | |
5251 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5252 | continue; | |
5253 | ||
df58fc94 | 5254 | case '~': |
dec0624d MR |
5255 | INSERT_OPERAND (mips_opts.micromips, |
5256 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5257 | continue; |
5258 | ||
5259 | case 'N': | |
5260 | gas_assert (mips_opts.micromips); | |
5261 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5262 | continue; | |
5263 | ||
5264 | case 'm': /* Opcode extension character. */ | |
5265 | gas_assert (mips_opts.micromips); | |
5266 | switch (*fmt++) | |
5267 | { | |
5268 | case 'j': | |
5269 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5270 | break; | |
5271 | ||
5272 | case 'p': | |
5273 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5274 | break; | |
5275 | ||
5276 | case 'F': | |
5277 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5278 | break; | |
5279 | ||
5280 | default: | |
b37df7c4 | 5281 | abort (); |
df58fc94 | 5282 | } |
d43b4baf TS |
5283 | continue; |
5284 | ||
252b5132 | 5285 | default: |
b37df7c4 | 5286 | abort (); |
252b5132 RH |
5287 | } |
5288 | break; | |
5289 | } | |
5290 | va_end (args); | |
9c2799c2 | 5291 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5292 | |
df58fc94 | 5293 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5294 | } |
5295 | ||
5296 | static void | |
67c0d1eb | 5297 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5298 | va_list *args) |
252b5132 | 5299 | { |
1e915849 | 5300 | struct mips_opcode *mo; |
252b5132 | 5301 | struct mips_cl_insn insn; |
f6688943 TS |
5302 | bfd_reloc_code_real_type r[3] |
5303 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5304 | |
1e915849 | 5305 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5306 | gas_assert (mo); |
5307 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5308 | |
1e915849 | 5309 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5310 | { |
1e915849 | 5311 | ++mo; |
9c2799c2 NC |
5312 | gas_assert (mo->name); |
5313 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5314 | } |
5315 | ||
1e915849 | 5316 | create_insn (&insn, mo); |
252b5132 RH |
5317 | for (;;) |
5318 | { | |
5319 | int c; | |
5320 | ||
5321 | c = *fmt++; | |
5322 | switch (c) | |
5323 | { | |
5324 | case '\0': | |
5325 | break; | |
5326 | ||
5327 | case ',': | |
5328 | case '(': | |
5329 | case ')': | |
5330 | continue; | |
5331 | ||
5332 | case 'y': | |
5333 | case 'w': | |
03ea81db | 5334 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5335 | continue; |
5336 | ||
5337 | case 'x': | |
5338 | case 'v': | |
03ea81db | 5339 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5340 | continue; |
5341 | ||
5342 | case 'z': | |
03ea81db | 5343 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5344 | continue; |
5345 | ||
5346 | case 'Z': | |
03ea81db | 5347 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5348 | continue; |
5349 | ||
5350 | case '0': | |
5351 | case 'S': | |
5352 | case 'P': | |
5353 | case 'R': | |
5354 | continue; | |
5355 | ||
5356 | case 'X': | |
03ea81db | 5357 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5358 | continue; |
5359 | ||
5360 | case 'Y': | |
5361 | { | |
5362 | int regno; | |
5363 | ||
03ea81db | 5364 | regno = va_arg (*args, int); |
252b5132 | 5365 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5366 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5367 | } |
5368 | continue; | |
5369 | ||
5370 | case '<': | |
5371 | case '>': | |
5372 | case '4': | |
5373 | case '5': | |
5374 | case 'H': | |
5375 | case 'W': | |
5376 | case 'D': | |
5377 | case 'j': | |
5378 | case '8': | |
5379 | case 'V': | |
5380 | case 'C': | |
5381 | case 'U': | |
5382 | case 'k': | |
5383 | case 'K': | |
5384 | case 'p': | |
5385 | case 'q': | |
5386 | { | |
b886a2ab RS |
5387 | offsetT value; |
5388 | ||
9c2799c2 | 5389 | gas_assert (ep != NULL); |
252b5132 RH |
5390 | |
5391 | if (ep->X_op != O_constant) | |
874e8986 | 5392 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5393 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5394 | { |
b886a2ab | 5395 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5396 | ep = NULL; |
f6688943 | 5397 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5398 | } |
5399 | } | |
5400 | continue; | |
5401 | ||
5402 | case '6': | |
03ea81db | 5403 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5404 | continue; |
5405 | } | |
5406 | ||
5407 | break; | |
5408 | } | |
5409 | ||
9c2799c2 | 5410 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5411 | |
df58fc94 | 5412 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5413 | } |
5414 | ||
2051e8c4 MR |
5415 | /* |
5416 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5417 | * higher bits unset. | |
5418 | */ | |
9f872bbe | 5419 | static void |
2051e8c4 MR |
5420 | normalize_constant_expr (expressionS *ex) |
5421 | { | |
9ee2a2d4 | 5422 | if (ex->X_op == O_constant |
2051e8c4 MR |
5423 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5424 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5425 | - 0x80000000); | |
5426 | } | |
5427 | ||
5428 | /* | |
5429 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5430 | * all higher bits unset. | |
5431 | */ | |
5432 | static void | |
5433 | normalize_address_expr (expressionS *ex) | |
5434 | { | |
5435 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5436 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5437 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5438 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5439 | - 0x80000000); | |
5440 | } | |
5441 | ||
438c16b8 TS |
5442 | /* |
5443 | * Generate a "jalr" instruction with a relocation hint to the called | |
5444 | * function. This occurs in NewABI PIC code. | |
5445 | */ | |
5446 | static void | |
df58fc94 | 5447 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5448 | { |
df58fc94 RS |
5449 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5450 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5451 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5452 | const char *jalr; | |
685736be | 5453 | char *f = NULL; |
b34976b6 | 5454 | |
1180b5a4 | 5455 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5456 | { |
cc3d92a5 | 5457 | frag_grow (8); |
f21f8242 AO |
5458 | f = frag_more (0); |
5459 | } | |
2906b037 | 5460 | if (mips_opts.micromips) |
df58fc94 RS |
5461 | { |
5462 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5463 | if (MIPS_JALR_HINT_P (ep) |
5464 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5465 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5466 | else | |
5467 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5468 | } | |
2906b037 MR |
5469 | else |
5470 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5471 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5472 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5473 | } |
5474 | ||
252b5132 RH |
5475 | /* |
5476 | * Generate a "lui" instruction. | |
5477 | */ | |
5478 | static void | |
67c0d1eb | 5479 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5480 | { |
9c2799c2 | 5481 | gas_assert (! mips_opts.mips16); |
252b5132 | 5482 | |
df58fc94 | 5483 | if (ep->X_op != O_constant) |
252b5132 | 5484 | { |
9c2799c2 | 5485 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5486 | /* _gp_disp is a special case, used from s_cpload. |
5487 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5488 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5489 | || (! HAVE_NEWABI |
aa6975fb ILT |
5490 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5491 | || (! mips_in_shared | |
bbe506e8 TS |
5492 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5493 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5494 | } |
5495 | ||
df58fc94 | 5496 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5497 | } |
5498 | ||
885add95 CD |
5499 | /* Generate a sequence of instructions to do a load or store from a constant |
5500 | offset off of a base register (breg) into/from a target register (treg), | |
5501 | using AT if necessary. */ | |
5502 | static void | |
67c0d1eb RS |
5503 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5504 | int treg, int breg, int dbl) | |
885add95 | 5505 | { |
9c2799c2 | 5506 | gas_assert (ep->X_op == O_constant); |
885add95 | 5507 | |
256ab948 | 5508 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5509 | if (!dbl) |
5510 | normalize_constant_expr (ep); | |
256ab948 | 5511 | |
67c1ffbe | 5512 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5513 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5514 | as_warn (_("operand overflow")); |
5515 | ||
5516 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5517 | { | |
5518 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5519 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5520 | } |
5521 | else | |
5522 | { | |
5523 | /* 32-bit offset, need multiple instructions and AT, like: | |
5524 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5525 | addu $tempreg,$tempreg,$breg | |
5526 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5527 | to handle the complete offset. */ | |
67c0d1eb RS |
5528 | macro_build_lui (ep, AT); |
5529 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5530 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5531 | |
741fe287 | 5532 | if (!mips_opts.at) |
8fc2e39e | 5533 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5534 | } |
5535 | } | |
5536 | ||
252b5132 RH |
5537 | /* set_at() |
5538 | * Generates code to set the $at register to true (one) | |
5539 | * if reg is less than the immediate expression. | |
5540 | */ | |
5541 | static void | |
67c0d1eb | 5542 | set_at (int reg, int unsignedp) |
252b5132 RH |
5543 | { |
5544 | if (imm_expr.X_op == O_constant | |
5545 | && imm_expr.X_add_number >= -0x8000 | |
5546 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5547 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5548 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5549 | else |
5550 | { | |
67c0d1eb RS |
5551 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5552 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5553 | } |
5554 | } | |
5555 | ||
5556 | /* Warn if an expression is not a constant. */ | |
5557 | ||
5558 | static void | |
17a2f251 | 5559 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5560 | { |
5561 | if (ex->X_op == O_big) | |
5562 | as_bad (_("unsupported large constant")); | |
5563 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5564 | as_bad (_("Instruction %s requires absolute expression"), |
5565 | ip->insn_mo->name); | |
13757d0c | 5566 | |
9ee2a2d4 MR |
5567 | if (HAVE_32BIT_GPRS) |
5568 | normalize_constant_expr (ex); | |
252b5132 RH |
5569 | } |
5570 | ||
5571 | /* Count the leading zeroes by performing a binary chop. This is a | |
5572 | bulky bit of source, but performance is a LOT better for the | |
5573 | majority of values than a simple loop to count the bits: | |
5574 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5575 | if ((v) & (1 << (31 - lcnt))) | |
5576 | break; | |
5577 | However it is not code size friendly, and the gain will drop a bit | |
5578 | on certain cached systems. | |
5579 | */ | |
5580 | #define COUNT_TOP_ZEROES(v) \ | |
5581 | (((v) & ~0xffff) == 0 \ | |
5582 | ? ((v) & ~0xff) == 0 \ | |
5583 | ? ((v) & ~0xf) == 0 \ | |
5584 | ? ((v) & ~0x3) == 0 \ | |
5585 | ? ((v) & ~0x1) == 0 \ | |
5586 | ? !(v) \ | |
5587 | ? 32 \ | |
5588 | : 31 \ | |
5589 | : 30 \ | |
5590 | : ((v) & ~0x7) == 0 \ | |
5591 | ? 29 \ | |
5592 | : 28 \ | |
5593 | : ((v) & ~0x3f) == 0 \ | |
5594 | ? ((v) & ~0x1f) == 0 \ | |
5595 | ? 27 \ | |
5596 | : 26 \ | |
5597 | : ((v) & ~0x7f) == 0 \ | |
5598 | ? 25 \ | |
5599 | : 24 \ | |
5600 | : ((v) & ~0xfff) == 0 \ | |
5601 | ? ((v) & ~0x3ff) == 0 \ | |
5602 | ? ((v) & ~0x1ff) == 0 \ | |
5603 | ? 23 \ | |
5604 | : 22 \ | |
5605 | : ((v) & ~0x7ff) == 0 \ | |
5606 | ? 21 \ | |
5607 | : 20 \ | |
5608 | : ((v) & ~0x3fff) == 0 \ | |
5609 | ? ((v) & ~0x1fff) == 0 \ | |
5610 | ? 19 \ | |
5611 | : 18 \ | |
5612 | : ((v) & ~0x7fff) == 0 \ | |
5613 | ? 17 \ | |
5614 | : 16 \ | |
5615 | : ((v) & ~0xffffff) == 0 \ | |
5616 | ? ((v) & ~0xfffff) == 0 \ | |
5617 | ? ((v) & ~0x3ffff) == 0 \ | |
5618 | ? ((v) & ~0x1ffff) == 0 \ | |
5619 | ? 15 \ | |
5620 | : 14 \ | |
5621 | : ((v) & ~0x7ffff) == 0 \ | |
5622 | ? 13 \ | |
5623 | : 12 \ | |
5624 | : ((v) & ~0x3fffff) == 0 \ | |
5625 | ? ((v) & ~0x1fffff) == 0 \ | |
5626 | ? 11 \ | |
5627 | : 10 \ | |
5628 | : ((v) & ~0x7fffff) == 0 \ | |
5629 | ? 9 \ | |
5630 | : 8 \ | |
5631 | : ((v) & ~0xfffffff) == 0 \ | |
5632 | ? ((v) & ~0x3ffffff) == 0 \ | |
5633 | ? ((v) & ~0x1ffffff) == 0 \ | |
5634 | ? 7 \ | |
5635 | : 6 \ | |
5636 | : ((v) & ~0x7ffffff) == 0 \ | |
5637 | ? 5 \ | |
5638 | : 4 \ | |
5639 | : ((v) & ~0x3fffffff) == 0 \ | |
5640 | ? ((v) & ~0x1fffffff) == 0 \ | |
5641 | ? 3 \ | |
5642 | : 2 \ | |
5643 | : ((v) & ~0x7fffffff) == 0 \ | |
5644 | ? 1 \ | |
5645 | : 0) | |
5646 | ||
5647 | /* load_register() | |
67c1ffbe | 5648 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5649 | * an absolute expression value into a register. |
5650 | */ | |
5651 | static void | |
67c0d1eb | 5652 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5653 | { |
5654 | int freg; | |
5655 | expressionS hi32, lo32; | |
5656 | ||
5657 | if (ep->X_op != O_big) | |
5658 | { | |
9c2799c2 | 5659 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5660 | |
5661 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5662 | if (!dbl) |
5663 | normalize_constant_expr (ep); | |
256ab948 TS |
5664 | |
5665 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5666 | { |
5667 | /* We can handle 16 bit signed values with an addiu to | |
5668 | $zero. No need to ever use daddiu here, since $zero and | |
5669 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5670 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5671 | return; |
5672 | } | |
5673 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5674 | { | |
5675 | /* We can handle 16 bit unsigned values with an ori to | |
5676 | $zero. */ | |
67c0d1eb | 5677 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5678 | return; |
5679 | } | |
256ab948 | 5680 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5681 | { |
5682 | /* 32 bit values require an lui. */ | |
df58fc94 | 5683 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5684 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5685 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5686 | return; |
5687 | } | |
5688 | } | |
5689 | ||
5690 | /* The value is larger than 32 bits. */ | |
5691 | ||
2051e8c4 | 5692 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5693 | { |
55e08f71 NC |
5694 | char value[32]; |
5695 | ||
5696 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5697 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5698 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5699 | return; |
5700 | } | |
5701 | ||
5702 | if (ep->X_op != O_big) | |
5703 | { | |
5704 | hi32 = *ep; | |
5705 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5706 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5707 | hi32.X_add_number &= 0xffffffff; | |
5708 | lo32 = *ep; | |
5709 | lo32.X_add_number &= 0xffffffff; | |
5710 | } | |
5711 | else | |
5712 | { | |
9c2799c2 | 5713 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5714 | if (ep->X_add_number == 3) |
5715 | generic_bignum[3] = 0; | |
5716 | else if (ep->X_add_number > 4) | |
5717 | as_bad (_("Number larger than 64 bits")); | |
5718 | lo32.X_op = O_constant; | |
5719 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5720 | hi32.X_op = O_constant; | |
5721 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5722 | } | |
5723 | ||
5724 | if (hi32.X_add_number == 0) | |
5725 | freg = 0; | |
5726 | else | |
5727 | { | |
5728 | int shift, bit; | |
5729 | unsigned long hi, lo; | |
5730 | ||
956cd1d6 | 5731 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5732 | { |
5733 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5734 | { | |
67c0d1eb | 5735 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5736 | return; |
5737 | } | |
5738 | if (lo32.X_add_number & 0x80000000) | |
5739 | { | |
df58fc94 | 5740 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5741 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5742 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5743 | return; |
5744 | } | |
5745 | } | |
252b5132 RH |
5746 | |
5747 | /* Check for 16bit shifted constant. We know that hi32 is | |
5748 | non-zero, so start the mask on the first bit of the hi32 | |
5749 | value. */ | |
5750 | shift = 17; | |
5751 | do | |
beae10d5 KH |
5752 | { |
5753 | unsigned long himask, lomask; | |
5754 | ||
5755 | if (shift < 32) | |
5756 | { | |
5757 | himask = 0xffff >> (32 - shift); | |
5758 | lomask = (0xffff << shift) & 0xffffffff; | |
5759 | } | |
5760 | else | |
5761 | { | |
5762 | himask = 0xffff << (shift - 32); | |
5763 | lomask = 0; | |
5764 | } | |
5765 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5766 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5767 | { | |
5768 | expressionS tmp; | |
5769 | ||
5770 | tmp.X_op = O_constant; | |
5771 | if (shift < 32) | |
5772 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5773 | | (lo32.X_add_number >> shift)); | |
5774 | else | |
5775 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5776 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5777 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5778 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5779 | return; |
5780 | } | |
f9419b05 | 5781 | ++shift; |
beae10d5 KH |
5782 | } |
5783 | while (shift <= (64 - 16)); | |
252b5132 RH |
5784 | |
5785 | /* Find the bit number of the lowest one bit, and store the | |
5786 | shifted value in hi/lo. */ | |
5787 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5788 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5789 | if (lo != 0) | |
5790 | { | |
5791 | bit = 0; | |
5792 | while ((lo & 1) == 0) | |
5793 | { | |
5794 | lo >>= 1; | |
5795 | ++bit; | |
5796 | } | |
5797 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5798 | hi >>= bit; | |
5799 | } | |
5800 | else | |
5801 | { | |
5802 | bit = 32; | |
5803 | while ((hi & 1) == 0) | |
5804 | { | |
5805 | hi >>= 1; | |
5806 | ++bit; | |
5807 | } | |
5808 | lo = hi; | |
5809 | hi = 0; | |
5810 | } | |
5811 | ||
5812 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5813 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5814 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5815 | { |
5816 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5817 | if (shift != 0) |
beae10d5 | 5818 | { |
252b5132 RH |
5819 | expressionS tmp; |
5820 | ||
5821 | /* This instruction will set the register to be all | |
5822 | ones. */ | |
beae10d5 KH |
5823 | tmp.X_op = O_constant; |
5824 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5825 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5826 | if (bit != 0) |
5827 | { | |
5828 | bit += shift; | |
df58fc94 | 5829 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5830 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5831 | } |
df58fc94 | 5832 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5833 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5834 | return; |
5835 | } | |
5836 | } | |
252b5132 RH |
5837 | |
5838 | /* Sign extend hi32 before calling load_register, because we can | |
5839 | generally get better code when we load a sign extended value. */ | |
5840 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5841 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5842 | load_register (reg, &hi32, 0); |
252b5132 RH |
5843 | freg = reg; |
5844 | } | |
5845 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5846 | { | |
5847 | if (freg != 0) | |
5848 | { | |
df58fc94 | 5849 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5850 | freg = reg; |
5851 | } | |
5852 | } | |
5853 | else | |
5854 | { | |
5855 | expressionS mid16; | |
5856 | ||
956cd1d6 | 5857 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5858 | { |
df58fc94 RS |
5859 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5860 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5861 | return; |
5862 | } | |
252b5132 RH |
5863 | |
5864 | if (freg != 0) | |
5865 | { | |
df58fc94 | 5866 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5867 | freg = reg; |
5868 | } | |
5869 | mid16 = lo32; | |
5870 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5871 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5872 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5873 | freg = reg; |
5874 | } | |
5875 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5876 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5877 | } |
5878 | ||
269137b2 TS |
5879 | static inline void |
5880 | load_delay_nop (void) | |
5881 | { | |
5882 | if (!gpr_interlocks) | |
5883 | macro_build (NULL, "nop", ""); | |
5884 | } | |
5885 | ||
252b5132 RH |
5886 | /* Load an address into a register. */ |
5887 | ||
5888 | static void | |
67c0d1eb | 5889 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5890 | { |
252b5132 RH |
5891 | if (ep->X_op != O_constant |
5892 | && ep->X_op != O_symbol) | |
5893 | { | |
5894 | as_bad (_("expression too complex")); | |
5895 | ep->X_op = O_constant; | |
5896 | } | |
5897 | ||
5898 | if (ep->X_op == O_constant) | |
5899 | { | |
67c0d1eb | 5900 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5901 | return; |
5902 | } | |
5903 | ||
5904 | if (mips_pic == NO_PIC) | |
5905 | { | |
5906 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5907 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5908 | Otherwise we want |
5909 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5910 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5911 | If we have an addend, we always use the latter form. |
76b3015f | 5912 | |
d6bc6245 TS |
5913 | With 64bit address space and a usable $at we want |
5914 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5915 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5916 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5917 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5918 | dsll32 $reg,0 | |
3a482fd5 | 5919 | daddu $reg,$reg,$at |
76b3015f | 5920 | |
c03099e6 | 5921 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5922 | on superscalar processors. |
5923 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5924 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5925 | dsll $reg,16 | |
5926 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5927 | dsll $reg,16 | |
5928 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5929 | |
5930 | For GP relative symbols in 64bit address space we can use | |
5931 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5932 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5933 | { |
6caf9ef4 TS |
5934 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5935 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5936 | { | |
5937 | relax_start (ep->X_add_symbol); | |
5938 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5939 | mips_gp_register, BFD_RELOC_GPREL16); | |
5940 | relax_switch (); | |
5941 | } | |
d6bc6245 | 5942 | |
741fe287 | 5943 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5944 | { |
df58fc94 RS |
5945 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5946 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5947 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5948 | BFD_RELOC_MIPS_HIGHER); | |
5949 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5950 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5951 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5952 | *used_at = 1; |
5953 | } | |
5954 | else | |
5955 | { | |
df58fc94 | 5956 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5957 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5958 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5959 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5960 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5961 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5962 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5963 | } |
6caf9ef4 TS |
5964 | |
5965 | if (mips_relax.sequence) | |
5966 | relax_end (); | |
d6bc6245 | 5967 | } |
252b5132 RH |
5968 | else |
5969 | { | |
d6bc6245 | 5970 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5971 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5972 | { |
4d7206a2 | 5973 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5974 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5975 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5976 | relax_switch (); |
d6bc6245 | 5977 | } |
67c0d1eb RS |
5978 | macro_build_lui (ep, reg); |
5979 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5980 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5981 | if (mips_relax.sequence) |
5982 | relax_end (); | |
d6bc6245 | 5983 | } |
252b5132 | 5984 | } |
0a44bf69 | 5985 | else if (!mips_big_got) |
252b5132 RH |
5986 | { |
5987 | expressionS ex; | |
5988 | ||
5989 | /* If this is a reference to an external symbol, we want | |
5990 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5991 | Otherwise we want | |
5992 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5993 | nop | |
5994 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5995 | If there is a constant, it must be added in after. |
5996 | ||
ed6fb7bd | 5997 | If we have NewABI, we want |
f5040a92 AO |
5998 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5999 | unless we're referencing a global symbol with a non-zero | |
6000 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6001 | if (HAVE_NEWABI) |
6002 | { | |
f5040a92 AO |
6003 | if (ep->X_add_number) |
6004 | { | |
4d7206a2 | 6005 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6006 | ep->X_add_number = 0; |
4d7206a2 | 6007 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6008 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6009 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6010 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6011 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6012 | ex.X_op = O_constant; | |
67c0d1eb | 6013 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6014 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6015 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6016 | relax_switch (); |
f5040a92 | 6017 | } |
67c0d1eb | 6018 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6019 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6020 | if (mips_relax.sequence) |
6021 | relax_end (); | |
ed6fb7bd SC |
6022 | } |
6023 | else | |
6024 | { | |
f5040a92 AO |
6025 | ex.X_add_number = ep->X_add_number; |
6026 | ep->X_add_number = 0; | |
67c0d1eb RS |
6027 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6028 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6029 | load_delay_nop (); |
4d7206a2 RS |
6030 | relax_start (ep->X_add_symbol); |
6031 | relax_switch (); | |
67c0d1eb | 6032 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6033 | BFD_RELOC_LO16); |
4d7206a2 | 6034 | relax_end (); |
ed6fb7bd | 6035 | |
f5040a92 AO |
6036 | if (ex.X_add_number != 0) |
6037 | { | |
6038 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6039 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6040 | ex.X_op = O_constant; | |
67c0d1eb | 6041 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6042 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6043 | } |
252b5132 RH |
6044 | } |
6045 | } | |
0a44bf69 | 6046 | else if (mips_big_got) |
252b5132 RH |
6047 | { |
6048 | expressionS ex; | |
252b5132 RH |
6049 | |
6050 | /* This is the large GOT case. If this is a reference to an | |
6051 | external symbol, we want | |
6052 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6053 | addu $reg,$reg,$gp | |
6054 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6055 | |
6056 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6057 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6058 | nop | |
6059 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6060 | If there is a constant, it must be added in after. |
f5040a92 AO |
6061 | |
6062 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6063 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6064 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6065 | */ |
438c16b8 TS |
6066 | if (HAVE_NEWABI) |
6067 | { | |
4d7206a2 | 6068 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6069 | ep->X_add_number = 0; |
4d7206a2 | 6070 | relax_start (ep->X_add_symbol); |
df58fc94 | 6071 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6073 | reg, reg, mips_gp_register); | |
6074 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6075 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6076 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6077 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6078 | else if (ex.X_add_number) | |
6079 | { | |
6080 | ex.X_op = O_constant; | |
67c0d1eb RS |
6081 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6082 | BFD_RELOC_LO16); | |
f5040a92 AO |
6083 | } |
6084 | ||
6085 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6086 | relax_switch (); |
67c0d1eb | 6087 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6088 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6089 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6090 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6091 | relax_end (); |
438c16b8 | 6092 | } |
252b5132 | 6093 | else |
438c16b8 | 6094 | { |
f5040a92 AO |
6095 | ex.X_add_number = ep->X_add_number; |
6096 | ep->X_add_number = 0; | |
4d7206a2 | 6097 | relax_start (ep->X_add_symbol); |
df58fc94 | 6098 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6099 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6100 | reg, reg, mips_gp_register); | |
6101 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6102 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6103 | relax_switch (); |
6104 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6105 | { |
6106 | /* We need a nop before loading from $gp. This special | |
6107 | check is required because the lui which starts the main | |
6108 | instruction stream does not refer to $gp, and so will not | |
6109 | insert the nop which may be required. */ | |
67c0d1eb | 6110 | macro_build (NULL, "nop", ""); |
438c16b8 | 6111 | } |
67c0d1eb | 6112 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6113 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6114 | load_delay_nop (); |
67c0d1eb | 6115 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6116 | BFD_RELOC_LO16); |
4d7206a2 | 6117 | relax_end (); |
438c16b8 | 6118 | |
f5040a92 AO |
6119 | if (ex.X_add_number != 0) |
6120 | { | |
6121 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6122 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6123 | ex.X_op = O_constant; | |
67c0d1eb RS |
6124 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6125 | BFD_RELOC_LO16); | |
f5040a92 | 6126 | } |
252b5132 RH |
6127 | } |
6128 | } | |
252b5132 RH |
6129 | else |
6130 | abort (); | |
8fc2e39e | 6131 | |
741fe287 | 6132 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6133 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6134 | } |
6135 | ||
ea1fb5dc RS |
6136 | /* Move the contents of register SOURCE into register DEST. */ |
6137 | ||
6138 | static void | |
67c0d1eb | 6139 | move_register (int dest, int source) |
ea1fb5dc | 6140 | { |
df58fc94 RS |
6141 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6142 | instruction specifically requires a 32-bit one. */ | |
6143 | if (mips_opts.micromips | |
6144 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6145 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6146 | else |
6147 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6148 | dest, source, 0); | |
ea1fb5dc RS |
6149 | } |
6150 | ||
4d7206a2 | 6151 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6152 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6153 | The two alternatives are: | |
4d7206a2 RS |
6154 | |
6155 | Global symbol Local sybmol | |
6156 | ------------- ------------ | |
6157 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6158 | ... ... | |
6159 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6160 | ||
6161 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6162 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6163 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6164 | |
6165 | static void | |
67c0d1eb | 6166 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6167 | { |
6168 | expressionS global; | |
6169 | ||
6170 | global = *local; | |
6171 | global.X_add_number = 0; | |
6172 | ||
6173 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6174 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6175 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6176 | relax_switch (); |
67c0d1eb RS |
6177 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6178 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6179 | relax_end (); |
6180 | } | |
6181 | ||
6182 | static void | |
67c0d1eb | 6183 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6184 | { |
6185 | expressionS global; | |
6186 | ||
6187 | global.X_op = O_constant; | |
6188 | global.X_op_symbol = NULL; | |
6189 | global.X_add_symbol = NULL; | |
6190 | global.X_add_number = local->X_add_number; | |
6191 | ||
6192 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6193 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6194 | dest, dest, BFD_RELOC_LO16); |
6195 | relax_switch (); | |
67c0d1eb | 6196 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6197 | relax_end (); |
6198 | } | |
6199 | ||
f6a22291 MR |
6200 | static void |
6201 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6202 | { | |
6203 | expressionS global; | |
6204 | int hold_mips_optimize; | |
6205 | ||
6206 | global.X_op = O_constant; | |
6207 | global.X_op_symbol = NULL; | |
6208 | global.X_add_symbol = NULL; | |
6209 | global.X_add_number = local->X_add_number; | |
6210 | ||
6211 | relax_start (local->X_add_symbol); | |
6212 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6213 | relax_switch (); | |
6214 | /* Set mips_optimize around the lui instruction to avoid | |
6215 | inserting an unnecessary nop after the lw. */ | |
6216 | hold_mips_optimize = mips_optimize; | |
6217 | mips_optimize = 2; | |
6218 | macro_build_lui (&global, tmp); | |
6219 | mips_optimize = hold_mips_optimize; | |
6220 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6221 | relax_end (); | |
6222 | ||
6223 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6224 | } | |
6225 | ||
df58fc94 RS |
6226 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6227 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6228 | is its complementing branch with the original condition negated. | |
6229 | CALL is set if the original branch specified the link operation. | |
6230 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6231 | ||
6232 | Code like this is produced in the noreorder mode: | |
6233 | ||
6234 | BRNEG <args>, 1f | |
6235 | nop | |
6236 | b <sym> | |
6237 | delay slot (executed only if branch taken) | |
6238 | 1: | |
6239 | ||
6240 | or, if CALL is set: | |
6241 | ||
6242 | BRNEG <args>, 1f | |
6243 | nop | |
6244 | bal <sym> | |
6245 | delay slot (executed only if branch taken) | |
6246 | 1: | |
6247 | ||
6248 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6249 | so code produced is simply: | |
6250 | ||
6251 | BR <args>, <sym> | |
6252 | nop | |
6253 | ||
6254 | This function is used when producing code for the microMIPS ASE that | |
6255 | does not implement branch likely instructions in hardware. */ | |
6256 | ||
6257 | static void | |
6258 | macro_build_branch_likely (const char *br, const char *brneg, | |
6259 | int call, expressionS *ep, const char *fmt, | |
6260 | unsigned int sreg, unsigned int treg) | |
6261 | { | |
6262 | int noreorder = mips_opts.noreorder; | |
6263 | expressionS expr1; | |
6264 | ||
6265 | gas_assert (mips_opts.micromips); | |
6266 | start_noreorder (); | |
6267 | if (noreorder) | |
6268 | { | |
6269 | micromips_label_expr (&expr1); | |
6270 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6271 | macro_build (NULL, "nop", ""); | |
6272 | macro_build (ep, call ? "bal" : "b", "p"); | |
6273 | ||
6274 | /* Set to true so that append_insn adds a label. */ | |
6275 | emit_branch_likely_macro = TRUE; | |
6276 | } | |
6277 | else | |
6278 | { | |
6279 | macro_build (ep, br, fmt, sreg, treg); | |
6280 | macro_build (NULL, "nop", ""); | |
6281 | } | |
6282 | end_noreorder (); | |
6283 | } | |
6284 | ||
6285 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6286 | the condition code tested. EP specifies the branch target. */ | |
6287 | ||
6288 | static void | |
6289 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6290 | { | |
6291 | const int call = 0; | |
6292 | const char *brneg; | |
6293 | const char *br; | |
6294 | ||
6295 | switch (type) | |
6296 | { | |
6297 | case M_BC1FL: | |
6298 | br = "bc1f"; | |
6299 | brneg = "bc1t"; | |
6300 | break; | |
6301 | case M_BC1TL: | |
6302 | br = "bc1t"; | |
6303 | brneg = "bc1f"; | |
6304 | break; | |
6305 | case M_BC2FL: | |
6306 | br = "bc2f"; | |
6307 | brneg = "bc2t"; | |
6308 | break; | |
6309 | case M_BC2TL: | |
6310 | br = "bc2t"; | |
6311 | brneg = "bc2f"; | |
6312 | break; | |
6313 | default: | |
6314 | abort (); | |
6315 | } | |
6316 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6317 | } | |
6318 | ||
6319 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6320 | the register tested. EP specifies the branch target. */ | |
6321 | ||
6322 | static void | |
6323 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6324 | { | |
6325 | const char *brneg = NULL; | |
6326 | const char *br; | |
6327 | int call = 0; | |
6328 | ||
6329 | switch (type) | |
6330 | { | |
6331 | case M_BGEZ: | |
6332 | br = "bgez"; | |
6333 | break; | |
6334 | case M_BGEZL: | |
6335 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6336 | brneg = "bltz"; | |
6337 | break; | |
6338 | case M_BGEZALL: | |
6339 | gas_assert (mips_opts.micromips); | |
6340 | br = "bgezals"; | |
6341 | brneg = "bltz"; | |
6342 | call = 1; | |
6343 | break; | |
6344 | case M_BGTZ: | |
6345 | br = "bgtz"; | |
6346 | break; | |
6347 | case M_BGTZL: | |
6348 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6349 | brneg = "blez"; | |
6350 | break; | |
6351 | case M_BLEZ: | |
6352 | br = "blez"; | |
6353 | break; | |
6354 | case M_BLEZL: | |
6355 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6356 | brneg = "bgtz"; | |
6357 | break; | |
6358 | case M_BLTZ: | |
6359 | br = "bltz"; | |
6360 | break; | |
6361 | case M_BLTZL: | |
6362 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6363 | brneg = "bgez"; | |
6364 | break; | |
6365 | case M_BLTZALL: | |
6366 | gas_assert (mips_opts.micromips); | |
6367 | br = "bltzals"; | |
6368 | brneg = "bgez"; | |
6369 | call = 1; | |
6370 | break; | |
6371 | default: | |
6372 | abort (); | |
6373 | } | |
6374 | if (mips_opts.micromips && brneg) | |
6375 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6376 | else | |
6377 | macro_build (ep, br, "s,p", sreg); | |
6378 | } | |
6379 | ||
6380 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6381 | TREG as the registers tested. EP specifies the branch target. */ | |
6382 | ||
6383 | static void | |
6384 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6385 | unsigned int sreg, unsigned int treg) | |
6386 | { | |
6387 | const char *brneg = NULL; | |
6388 | const int call = 0; | |
6389 | const char *br; | |
6390 | ||
6391 | switch (type) | |
6392 | { | |
6393 | case M_BEQ: | |
6394 | case M_BEQ_I: | |
6395 | br = "beq"; | |
6396 | break; | |
6397 | case M_BEQL: | |
6398 | case M_BEQL_I: | |
6399 | br = mips_opts.micromips ? "beq" : "beql"; | |
6400 | brneg = "bne"; | |
6401 | break; | |
6402 | case M_BNE: | |
6403 | case M_BNE_I: | |
6404 | br = "bne"; | |
6405 | break; | |
6406 | case M_BNEL: | |
6407 | case M_BNEL_I: | |
6408 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6409 | brneg = "beq"; | |
6410 | break; | |
6411 | default: | |
6412 | abort (); | |
6413 | } | |
6414 | if (mips_opts.micromips && brneg) | |
6415 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6416 | else | |
6417 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6418 | } | |
6419 | ||
252b5132 RH |
6420 | /* |
6421 | * Build macros | |
6422 | * This routine implements the seemingly endless macro or synthesized | |
6423 | * instructions and addressing modes in the mips assembly language. Many | |
6424 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6425 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6426 | * this verbose method. Others are not simple macros but are more like |
6427 | * optimizing code generation. | |
6428 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6429 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6430 | * The ensuing load upper instructions are ommited. This implies some kind |
6431 | * of global optimization. We currently only optimize within a single macro. | |
6432 | * For many of the load and store macros if the address is specified as a | |
6433 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6434 | * first load register 'at' with zero and use it as the base register. The | |
6435 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6436 | * we're missing. | |
6437 | */ | |
6438 | static void | |
17a2f251 | 6439 | macro (struct mips_cl_insn *ip) |
252b5132 | 6440 | { |
741fe287 MR |
6441 | unsigned int treg, sreg, dreg, breg; |
6442 | unsigned int tempreg; | |
252b5132 | 6443 | int mask; |
43841e91 | 6444 | int used_at = 0; |
df58fc94 | 6445 | expressionS label_expr; |
252b5132 | 6446 | expressionS expr1; |
df58fc94 | 6447 | expressionS *ep; |
252b5132 RH |
6448 | const char *s; |
6449 | const char *s2; | |
6450 | const char *fmt; | |
6451 | int likely = 0; | |
252b5132 | 6452 | int coproc = 0; |
df58fc94 | 6453 | int off12 = 0; |
1abe91b1 | 6454 | int call = 0; |
df58fc94 RS |
6455 | int jals = 0; |
6456 | int dbl = 0; | |
6457 | int imm = 0; | |
6458 | int ust = 0; | |
6459 | int lp = 0; | |
6460 | int ab = 0; | |
dd6a37e7 | 6461 | int off0 = 0; |
252b5132 | 6462 | int off; |
67c0d1eb | 6463 | offsetT maxnum; |
252b5132 | 6464 | bfd_reloc_code_real_type r; |
252b5132 RH |
6465 | int hold_mips_optimize; |
6466 | ||
9c2799c2 | 6467 | gas_assert (! mips_opts.mips16); |
252b5132 | 6468 | |
df58fc94 RS |
6469 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6470 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6471 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6472 | mask = ip->insn_mo->mask; |
6473 | ||
df58fc94 RS |
6474 | label_expr.X_op = O_constant; |
6475 | label_expr.X_op_symbol = NULL; | |
6476 | label_expr.X_add_symbol = NULL; | |
6477 | label_expr.X_add_number = 0; | |
6478 | ||
252b5132 RH |
6479 | expr1.X_op = O_constant; |
6480 | expr1.X_op_symbol = NULL; | |
6481 | expr1.X_add_symbol = NULL; | |
6482 | expr1.X_add_number = 1; | |
6483 | ||
6484 | switch (mask) | |
6485 | { | |
6486 | case M_DABS: | |
6487 | dbl = 1; | |
6488 | case M_ABS: | |
df58fc94 RS |
6489 | /* bgez $a0,1f |
6490 | move v0,$a0 | |
6491 | sub v0,$zero,$a0 | |
6492 | 1: | |
6493 | */ | |
252b5132 | 6494 | |
7d10b47d | 6495 | start_noreorder (); |
252b5132 | 6496 | |
df58fc94 RS |
6497 | if (mips_opts.micromips) |
6498 | micromips_label_expr (&label_expr); | |
6499 | else | |
6500 | label_expr.X_add_number = 8; | |
6501 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6502 | if (dreg == sreg) |
a605d2b3 | 6503 | macro_build (NULL, "nop", ""); |
252b5132 | 6504 | else |
67c0d1eb RS |
6505 | move_register (dreg, sreg); |
6506 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6507 | if (mips_opts.micromips) |
6508 | micromips_add_label (); | |
252b5132 | 6509 | |
7d10b47d | 6510 | end_noreorder (); |
8fc2e39e | 6511 | break; |
252b5132 RH |
6512 | |
6513 | case M_ADD_I: | |
6514 | s = "addi"; | |
6515 | s2 = "add"; | |
6516 | goto do_addi; | |
6517 | case M_ADDU_I: | |
6518 | s = "addiu"; | |
6519 | s2 = "addu"; | |
6520 | goto do_addi; | |
6521 | case M_DADD_I: | |
6522 | dbl = 1; | |
6523 | s = "daddi"; | |
6524 | s2 = "dadd"; | |
df58fc94 RS |
6525 | if (!mips_opts.micromips) |
6526 | goto do_addi; | |
6527 | if (imm_expr.X_op == O_constant | |
6528 | && imm_expr.X_add_number >= -0x200 | |
6529 | && imm_expr.X_add_number < 0x200) | |
6530 | { | |
6531 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6532 | break; | |
6533 | } | |
6534 | goto do_addi_i; | |
252b5132 RH |
6535 | case M_DADDU_I: |
6536 | dbl = 1; | |
6537 | s = "daddiu"; | |
6538 | s2 = "daddu"; | |
6539 | do_addi: | |
6540 | if (imm_expr.X_op == O_constant | |
6541 | && imm_expr.X_add_number >= -0x8000 | |
6542 | && imm_expr.X_add_number < 0x8000) | |
6543 | { | |
67c0d1eb | 6544 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6545 | break; |
252b5132 | 6546 | } |
df58fc94 | 6547 | do_addi_i: |
8fc2e39e | 6548 | used_at = 1; |
67c0d1eb RS |
6549 | load_register (AT, &imm_expr, dbl); |
6550 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6551 | break; |
6552 | ||
6553 | case M_AND_I: | |
6554 | s = "andi"; | |
6555 | s2 = "and"; | |
6556 | goto do_bit; | |
6557 | case M_OR_I: | |
6558 | s = "ori"; | |
6559 | s2 = "or"; | |
6560 | goto do_bit; | |
6561 | case M_NOR_I: | |
6562 | s = ""; | |
6563 | s2 = "nor"; | |
6564 | goto do_bit; | |
6565 | case M_XOR_I: | |
6566 | s = "xori"; | |
6567 | s2 = "xor"; | |
6568 | do_bit: | |
6569 | if (imm_expr.X_op == O_constant | |
6570 | && imm_expr.X_add_number >= 0 | |
6571 | && imm_expr.X_add_number < 0x10000) | |
6572 | { | |
6573 | if (mask != M_NOR_I) | |
67c0d1eb | 6574 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6575 | else |
6576 | { | |
67c0d1eb RS |
6577 | macro_build (&imm_expr, "ori", "t,r,i", |
6578 | treg, sreg, BFD_RELOC_LO16); | |
6579 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6580 | } |
8fc2e39e | 6581 | break; |
252b5132 RH |
6582 | } |
6583 | ||
8fc2e39e | 6584 | used_at = 1; |
67c0d1eb RS |
6585 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6586 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6587 | break; |
6588 | ||
8b082fb1 TS |
6589 | case M_BALIGN: |
6590 | switch (imm_expr.X_add_number) | |
6591 | { | |
6592 | case 0: | |
6593 | macro_build (NULL, "nop", ""); | |
6594 | break; | |
6595 | case 2: | |
6596 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6597 | break; | |
03f66e8a MR |
6598 | case 1: |
6599 | case 3: | |
8b082fb1 | 6600 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6601 | (int) imm_expr.X_add_number); |
8b082fb1 | 6602 | break; |
03f66e8a MR |
6603 | default: |
6604 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6605 | (unsigned long) imm_expr.X_add_number); | |
6606 | break; | |
8b082fb1 TS |
6607 | } |
6608 | break; | |
6609 | ||
df58fc94 RS |
6610 | case M_BC1FL: |
6611 | case M_BC1TL: | |
6612 | case M_BC2FL: | |
6613 | case M_BC2TL: | |
6614 | gas_assert (mips_opts.micromips); | |
6615 | macro_build_branch_ccl (mask, &offset_expr, | |
6616 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6617 | break; | |
6618 | ||
252b5132 | 6619 | case M_BEQ_I: |
252b5132 | 6620 | case M_BEQL_I: |
252b5132 | 6621 | case M_BNE_I: |
252b5132 | 6622 | case M_BNEL_I: |
252b5132 | 6623 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6624 | treg = 0; |
6625 | else | |
252b5132 | 6626 | { |
df58fc94 RS |
6627 | treg = AT; |
6628 | used_at = 1; | |
6629 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6630 | } |
df58fc94 RS |
6631 | /* Fall through. */ |
6632 | case M_BEQL: | |
6633 | case M_BNEL: | |
6634 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6635 | break; |
6636 | ||
6637 | case M_BGEL: | |
6638 | likely = 1; | |
6639 | case M_BGE: | |
6640 | if (treg == 0) | |
df58fc94 RS |
6641 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6642 | else if (sreg == 0) | |
6643 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6644 | else | |
252b5132 | 6645 | { |
df58fc94 RS |
6646 | used_at = 1; |
6647 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6648 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6649 | &offset_expr, AT, ZERO); | |
252b5132 | 6650 | } |
df58fc94 RS |
6651 | break; |
6652 | ||
6653 | case M_BGEZL: | |
6654 | case M_BGEZALL: | |
6655 | case M_BGTZL: | |
6656 | case M_BLEZL: | |
6657 | case M_BLTZL: | |
6658 | case M_BLTZALL: | |
6659 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6660 | break; |
6661 | ||
6662 | case M_BGTL_I: | |
6663 | likely = 1; | |
6664 | case M_BGT_I: | |
90ecf173 | 6665 | /* Check for > max integer. */ |
252b5132 | 6666 | maxnum = 0x7fffffff; |
ca4e0257 | 6667 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6668 | { |
6669 | maxnum <<= 16; | |
6670 | maxnum |= 0xffff; | |
6671 | maxnum <<= 16; | |
6672 | maxnum |= 0xffff; | |
6673 | } | |
6674 | if (imm_expr.X_op == O_constant | |
6675 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6676 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6677 | { |
6678 | do_false: | |
90ecf173 | 6679 | /* Result is always false. */ |
252b5132 | 6680 | if (! likely) |
a605d2b3 | 6681 | macro_build (NULL, "nop", ""); |
252b5132 | 6682 | else |
df58fc94 | 6683 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6684 | break; |
252b5132 RH |
6685 | } |
6686 | if (imm_expr.X_op != O_constant) | |
6687 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6688 | ++imm_expr.X_add_number; |
252b5132 RH |
6689 | /* FALLTHROUGH */ |
6690 | case M_BGE_I: | |
6691 | case M_BGEL_I: | |
6692 | if (mask == M_BGEL_I) | |
6693 | likely = 1; | |
6694 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6695 | { | |
df58fc94 RS |
6696 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6697 | &offset_expr, sreg); | |
8fc2e39e | 6698 | break; |
252b5132 RH |
6699 | } |
6700 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6701 | { | |
df58fc94 RS |
6702 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6703 | &offset_expr, sreg); | |
8fc2e39e | 6704 | break; |
252b5132 RH |
6705 | } |
6706 | maxnum = 0x7fffffff; | |
ca4e0257 | 6707 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6708 | { |
6709 | maxnum <<= 16; | |
6710 | maxnum |= 0xffff; | |
6711 | maxnum <<= 16; | |
6712 | maxnum |= 0xffff; | |
6713 | } | |
6714 | maxnum = - maxnum - 1; | |
6715 | if (imm_expr.X_op == O_constant | |
6716 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6717 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6718 | { |
6719 | do_true: | |
6720 | /* result is always true */ | |
6721 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6722 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6723 | break; |
252b5132 | 6724 | } |
8fc2e39e | 6725 | used_at = 1; |
67c0d1eb | 6726 | set_at (sreg, 0); |
df58fc94 RS |
6727 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6728 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6729 | break; |
6730 | ||
6731 | case M_BGEUL: | |
6732 | likely = 1; | |
6733 | case M_BGEU: | |
6734 | if (treg == 0) | |
6735 | goto do_true; | |
df58fc94 RS |
6736 | else if (sreg == 0) |
6737 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6738 | &offset_expr, ZERO, treg); | |
6739 | else | |
252b5132 | 6740 | { |
df58fc94 RS |
6741 | used_at = 1; |
6742 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6743 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6744 | &offset_expr, AT, ZERO); | |
252b5132 | 6745 | } |
252b5132 RH |
6746 | break; |
6747 | ||
6748 | case M_BGTUL_I: | |
6749 | likely = 1; | |
6750 | case M_BGTU_I: | |
6751 | if (sreg == 0 | |
ca4e0257 | 6752 | || (HAVE_32BIT_GPRS |
252b5132 | 6753 | && imm_expr.X_op == O_constant |
f01dc953 | 6754 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6755 | goto do_false; |
6756 | if (imm_expr.X_op != O_constant) | |
6757 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6758 | ++imm_expr.X_add_number; |
252b5132 RH |
6759 | /* FALLTHROUGH */ |
6760 | case M_BGEU_I: | |
6761 | case M_BGEUL_I: | |
6762 | if (mask == M_BGEUL_I) | |
6763 | likely = 1; | |
6764 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6765 | goto do_true; | |
df58fc94 RS |
6766 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6767 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6768 | &offset_expr, sreg, ZERO); | |
6769 | else | |
252b5132 | 6770 | { |
df58fc94 RS |
6771 | used_at = 1; |
6772 | set_at (sreg, 1); | |
6773 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6774 | &offset_expr, AT, ZERO); | |
252b5132 | 6775 | } |
252b5132 RH |
6776 | break; |
6777 | ||
6778 | case M_BGTL: | |
6779 | likely = 1; | |
6780 | case M_BGT: | |
6781 | if (treg == 0) | |
df58fc94 RS |
6782 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6783 | else if (sreg == 0) | |
6784 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6785 | else | |
252b5132 | 6786 | { |
df58fc94 RS |
6787 | used_at = 1; |
6788 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6789 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6790 | &offset_expr, AT, ZERO); | |
252b5132 | 6791 | } |
252b5132 RH |
6792 | break; |
6793 | ||
6794 | case M_BGTUL: | |
6795 | likely = 1; | |
6796 | case M_BGTU: | |
6797 | if (treg == 0) | |
df58fc94 RS |
6798 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6799 | &offset_expr, sreg, ZERO); | |
6800 | else if (sreg == 0) | |
6801 | goto do_false; | |
6802 | else | |
252b5132 | 6803 | { |
df58fc94 RS |
6804 | used_at = 1; |
6805 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6806 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6807 | &offset_expr, AT, ZERO); | |
252b5132 | 6808 | } |
252b5132 RH |
6809 | break; |
6810 | ||
6811 | case M_BLEL: | |
6812 | likely = 1; | |
6813 | case M_BLE: | |
6814 | if (treg == 0) | |
df58fc94 RS |
6815 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6816 | else if (sreg == 0) | |
6817 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6818 | else | |
252b5132 | 6819 | { |
df58fc94 RS |
6820 | used_at = 1; |
6821 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6822 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6823 | &offset_expr, AT, ZERO); | |
252b5132 | 6824 | } |
252b5132 RH |
6825 | break; |
6826 | ||
6827 | case M_BLEL_I: | |
6828 | likely = 1; | |
6829 | case M_BLE_I: | |
6830 | maxnum = 0x7fffffff; | |
ca4e0257 | 6831 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6832 | { |
6833 | maxnum <<= 16; | |
6834 | maxnum |= 0xffff; | |
6835 | maxnum <<= 16; | |
6836 | maxnum |= 0xffff; | |
6837 | } | |
6838 | if (imm_expr.X_op == O_constant | |
6839 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6840 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6841 | goto do_true; |
6842 | if (imm_expr.X_op != O_constant) | |
6843 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6844 | ++imm_expr.X_add_number; |
252b5132 RH |
6845 | /* FALLTHROUGH */ |
6846 | case M_BLT_I: | |
6847 | case M_BLTL_I: | |
6848 | if (mask == M_BLTL_I) | |
6849 | likely = 1; | |
6850 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6851 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6852 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6853 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6854 | else | |
252b5132 | 6855 | { |
df58fc94 RS |
6856 | used_at = 1; |
6857 | set_at (sreg, 0); | |
6858 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6859 | &offset_expr, AT, ZERO); | |
252b5132 | 6860 | } |
252b5132 RH |
6861 | break; |
6862 | ||
6863 | case M_BLEUL: | |
6864 | likely = 1; | |
6865 | case M_BLEU: | |
6866 | if (treg == 0) | |
df58fc94 RS |
6867 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6868 | &offset_expr, sreg, ZERO); | |
6869 | else if (sreg == 0) | |
6870 | goto do_true; | |
6871 | else | |
252b5132 | 6872 | { |
df58fc94 RS |
6873 | used_at = 1; |
6874 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6875 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6876 | &offset_expr, AT, ZERO); | |
252b5132 | 6877 | } |
252b5132 RH |
6878 | break; |
6879 | ||
6880 | case M_BLEUL_I: | |
6881 | likely = 1; | |
6882 | case M_BLEU_I: | |
6883 | if (sreg == 0 | |
ca4e0257 | 6884 | || (HAVE_32BIT_GPRS |
252b5132 | 6885 | && imm_expr.X_op == O_constant |
f01dc953 | 6886 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6887 | goto do_true; |
6888 | if (imm_expr.X_op != O_constant) | |
6889 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6890 | ++imm_expr.X_add_number; |
252b5132 RH |
6891 | /* FALLTHROUGH */ |
6892 | case M_BLTU_I: | |
6893 | case M_BLTUL_I: | |
6894 | if (mask == M_BLTUL_I) | |
6895 | likely = 1; | |
6896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6897 | goto do_false; | |
df58fc94 RS |
6898 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6899 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6900 | &offset_expr, sreg, ZERO); | |
6901 | else | |
252b5132 | 6902 | { |
df58fc94 RS |
6903 | used_at = 1; |
6904 | set_at (sreg, 1); | |
6905 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6906 | &offset_expr, AT, ZERO); | |
252b5132 | 6907 | } |
252b5132 RH |
6908 | break; |
6909 | ||
6910 | case M_BLTL: | |
6911 | likely = 1; | |
6912 | case M_BLT: | |
6913 | if (treg == 0) | |
df58fc94 RS |
6914 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6915 | else if (sreg == 0) | |
6916 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6917 | else | |
252b5132 | 6918 | { |
df58fc94 RS |
6919 | used_at = 1; |
6920 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6921 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6922 | &offset_expr, AT, ZERO); | |
252b5132 | 6923 | } |
252b5132 RH |
6924 | break; |
6925 | ||
6926 | case M_BLTUL: | |
6927 | likely = 1; | |
6928 | case M_BLTU: | |
6929 | if (treg == 0) | |
6930 | goto do_false; | |
df58fc94 RS |
6931 | else if (sreg == 0) |
6932 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6933 | &offset_expr, ZERO, treg); | |
6934 | else | |
252b5132 | 6935 | { |
df58fc94 RS |
6936 | used_at = 1; |
6937 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6938 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6939 | &offset_expr, AT, ZERO); | |
252b5132 | 6940 | } |
252b5132 RH |
6941 | break; |
6942 | ||
5f74bc13 CD |
6943 | case M_DEXT: |
6944 | { | |
d5818fca MR |
6945 | /* Use unsigned arithmetic. */ |
6946 | addressT pos; | |
6947 | addressT size; | |
5f74bc13 | 6948 | |
90ecf173 | 6949 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6950 | { |
6951 | as_bad (_("Unsupported large constant")); | |
6952 | pos = size = 1; | |
6953 | } | |
6954 | else | |
6955 | { | |
d5818fca MR |
6956 | pos = imm_expr.X_add_number; |
6957 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6958 | } |
6959 | ||
6960 | if (pos > 63) | |
6961 | { | |
d5818fca | 6962 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6963 | pos = 1; |
6964 | } | |
90ecf173 | 6965 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6966 | { |
6967 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6968 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6969 | size = 1; |
6970 | } | |
6971 | ||
6972 | if (size <= 32 && pos < 32) | |
6973 | { | |
6974 | s = "dext"; | |
6975 | fmt = "t,r,+A,+C"; | |
6976 | } | |
6977 | else if (size <= 32) | |
6978 | { | |
6979 | s = "dextu"; | |
6980 | fmt = "t,r,+E,+H"; | |
6981 | } | |
6982 | else | |
6983 | { | |
6984 | s = "dextm"; | |
6985 | fmt = "t,r,+A,+G"; | |
6986 | } | |
d5818fca MR |
6987 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6988 | (int) (size - 1)); | |
5f74bc13 | 6989 | } |
8fc2e39e | 6990 | break; |
5f74bc13 CD |
6991 | |
6992 | case M_DINS: | |
6993 | { | |
d5818fca MR |
6994 | /* Use unsigned arithmetic. */ |
6995 | addressT pos; | |
6996 | addressT size; | |
5f74bc13 | 6997 | |
90ecf173 | 6998 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6999 | { |
7000 | as_bad (_("Unsupported large constant")); | |
7001 | pos = size = 1; | |
7002 | } | |
7003 | else | |
7004 | { | |
d5818fca MR |
7005 | pos = imm_expr.X_add_number; |
7006 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7007 | } |
7008 | ||
7009 | if (pos > 63) | |
7010 | { | |
d5818fca | 7011 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7012 | pos = 1; |
7013 | } | |
90ecf173 | 7014 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7015 | { |
7016 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7017 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7018 | size = 1; |
7019 | } | |
7020 | ||
7021 | if (pos < 32 && (pos + size - 1) < 32) | |
7022 | { | |
7023 | s = "dins"; | |
7024 | fmt = "t,r,+A,+B"; | |
7025 | } | |
7026 | else if (pos >= 32) | |
7027 | { | |
7028 | s = "dinsu"; | |
7029 | fmt = "t,r,+E,+F"; | |
7030 | } | |
7031 | else | |
7032 | { | |
7033 | s = "dinsm"; | |
7034 | fmt = "t,r,+A,+F"; | |
7035 | } | |
750bdd57 AS |
7036 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7037 | (int) (pos + size - 1)); | |
5f74bc13 | 7038 | } |
8fc2e39e | 7039 | break; |
5f74bc13 | 7040 | |
252b5132 RH |
7041 | case M_DDIV_3: |
7042 | dbl = 1; | |
7043 | case M_DIV_3: | |
7044 | s = "mflo"; | |
7045 | goto do_div3; | |
7046 | case M_DREM_3: | |
7047 | dbl = 1; | |
7048 | case M_REM_3: | |
7049 | s = "mfhi"; | |
7050 | do_div3: | |
7051 | if (treg == 0) | |
7052 | { | |
7053 | as_warn (_("Divide by zero.")); | |
7054 | if (mips_trap) | |
df58fc94 | 7055 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7056 | else |
df58fc94 | 7057 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7058 | break; |
252b5132 RH |
7059 | } |
7060 | ||
7d10b47d | 7061 | start_noreorder (); |
252b5132 RH |
7062 | if (mips_trap) |
7063 | { | |
df58fc94 | 7064 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7065 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7066 | } |
7067 | else | |
7068 | { | |
df58fc94 RS |
7069 | if (mips_opts.micromips) |
7070 | micromips_label_expr (&label_expr); | |
7071 | else | |
7072 | label_expr.X_add_number = 8; | |
7073 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7074 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7075 | macro_build (NULL, "break", BRK_FMT, 7); |
7076 | if (mips_opts.micromips) | |
7077 | micromips_add_label (); | |
252b5132 RH |
7078 | } |
7079 | expr1.X_add_number = -1; | |
8fc2e39e | 7080 | used_at = 1; |
f6a22291 | 7081 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7082 | if (mips_opts.micromips) |
7083 | micromips_label_expr (&label_expr); | |
7084 | else | |
7085 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7086 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7087 | if (dbl) |
7088 | { | |
7089 | expr1.X_add_number = 1; | |
f6a22291 | 7090 | load_register (AT, &expr1, dbl); |
df58fc94 | 7091 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7092 | } |
7093 | else | |
7094 | { | |
7095 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7096 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7097 | } |
7098 | if (mips_trap) | |
7099 | { | |
df58fc94 | 7100 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7101 | /* We want to close the noreorder block as soon as possible, so |
7102 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7103 | end_noreorder (); |
252b5132 RH |
7104 | } |
7105 | else | |
7106 | { | |
df58fc94 RS |
7107 | if (mips_opts.micromips) |
7108 | micromips_label_expr (&label_expr); | |
7109 | else | |
7110 | label_expr.X_add_number = 8; | |
7111 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7112 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7113 | |
7114 | /* We want to close the noreorder block as soon as possible, so | |
7115 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7116 | end_noreorder (); |
252b5132 | 7117 | |
df58fc94 | 7118 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7119 | } |
df58fc94 RS |
7120 | if (mips_opts.micromips) |
7121 | micromips_add_label (); | |
7122 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7123 | break; |
7124 | ||
7125 | case M_DIV_3I: | |
7126 | s = "div"; | |
7127 | s2 = "mflo"; | |
7128 | goto do_divi; | |
7129 | case M_DIVU_3I: | |
7130 | s = "divu"; | |
7131 | s2 = "mflo"; | |
7132 | goto do_divi; | |
7133 | case M_REM_3I: | |
7134 | s = "div"; | |
7135 | s2 = "mfhi"; | |
7136 | goto do_divi; | |
7137 | case M_REMU_3I: | |
7138 | s = "divu"; | |
7139 | s2 = "mfhi"; | |
7140 | goto do_divi; | |
7141 | case M_DDIV_3I: | |
7142 | dbl = 1; | |
7143 | s = "ddiv"; | |
7144 | s2 = "mflo"; | |
7145 | goto do_divi; | |
7146 | case M_DDIVU_3I: | |
7147 | dbl = 1; | |
7148 | s = "ddivu"; | |
7149 | s2 = "mflo"; | |
7150 | goto do_divi; | |
7151 | case M_DREM_3I: | |
7152 | dbl = 1; | |
7153 | s = "ddiv"; | |
7154 | s2 = "mfhi"; | |
7155 | goto do_divi; | |
7156 | case M_DREMU_3I: | |
7157 | dbl = 1; | |
7158 | s = "ddivu"; | |
7159 | s2 = "mfhi"; | |
7160 | do_divi: | |
7161 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7162 | { | |
7163 | as_warn (_("Divide by zero.")); | |
7164 | if (mips_trap) | |
df58fc94 | 7165 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7166 | else |
df58fc94 | 7167 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7168 | break; |
252b5132 RH |
7169 | } |
7170 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7171 | { | |
7172 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7173 | move_register (dreg, sreg); |
252b5132 | 7174 | else |
c80c840e | 7175 | move_register (dreg, ZERO); |
8fc2e39e | 7176 | break; |
252b5132 RH |
7177 | } |
7178 | if (imm_expr.X_op == O_constant | |
7179 | && imm_expr.X_add_number == -1 | |
7180 | && s[strlen (s) - 1] != 'u') | |
7181 | { | |
7182 | if (strcmp (s2, "mflo") == 0) | |
7183 | { | |
67c0d1eb | 7184 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7185 | } |
7186 | else | |
c80c840e | 7187 | move_register (dreg, ZERO); |
8fc2e39e | 7188 | break; |
252b5132 RH |
7189 | } |
7190 | ||
8fc2e39e | 7191 | used_at = 1; |
67c0d1eb RS |
7192 | load_register (AT, &imm_expr, dbl); |
7193 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7194 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7195 | break; |
7196 | ||
7197 | case M_DIVU_3: | |
7198 | s = "divu"; | |
7199 | s2 = "mflo"; | |
7200 | goto do_divu3; | |
7201 | case M_REMU_3: | |
7202 | s = "divu"; | |
7203 | s2 = "mfhi"; | |
7204 | goto do_divu3; | |
7205 | case M_DDIVU_3: | |
7206 | s = "ddivu"; | |
7207 | s2 = "mflo"; | |
7208 | goto do_divu3; | |
7209 | case M_DREMU_3: | |
7210 | s = "ddivu"; | |
7211 | s2 = "mfhi"; | |
7212 | do_divu3: | |
7d10b47d | 7213 | start_noreorder (); |
252b5132 RH |
7214 | if (mips_trap) |
7215 | { | |
df58fc94 | 7216 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7217 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7218 | /* We want to close the noreorder block as soon as possible, so |
7219 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7220 | end_noreorder (); |
252b5132 RH |
7221 | } |
7222 | else | |
7223 | { | |
df58fc94 RS |
7224 | if (mips_opts.micromips) |
7225 | micromips_label_expr (&label_expr); | |
7226 | else | |
7227 | label_expr.X_add_number = 8; | |
7228 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7229 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7230 | |
7231 | /* We want to close the noreorder block as soon as possible, so | |
7232 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7233 | end_noreorder (); |
df58fc94 RS |
7234 | macro_build (NULL, "break", BRK_FMT, 7); |
7235 | if (mips_opts.micromips) | |
7236 | micromips_add_label (); | |
252b5132 | 7237 | } |
df58fc94 | 7238 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7239 | break; |
252b5132 | 7240 | |
1abe91b1 MR |
7241 | case M_DLCA_AB: |
7242 | dbl = 1; | |
7243 | case M_LCA_AB: | |
7244 | call = 1; | |
7245 | goto do_la; | |
252b5132 RH |
7246 | case M_DLA_AB: |
7247 | dbl = 1; | |
7248 | case M_LA_AB: | |
1abe91b1 | 7249 | do_la: |
252b5132 RH |
7250 | /* Load the address of a symbol into a register. If breg is not |
7251 | zero, we then add a base register to it. */ | |
7252 | ||
3bec30a8 TS |
7253 | if (dbl && HAVE_32BIT_GPRS) |
7254 | as_warn (_("dla used to load 32-bit register")); | |
7255 | ||
90ecf173 | 7256 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7257 | as_warn (_("la used to load 64-bit address")); |
7258 | ||
0c11417f MR |
7259 | if (offset_expr.X_op == O_constant |
7260 | && offset_expr.X_add_number >= -0x8000 | |
7261 | && offset_expr.X_add_number < 0x8000) | |
7262 | { | |
aed1a261 | 7263 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7264 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7265 | break; |
0c11417f MR |
7266 | } |
7267 | ||
741fe287 | 7268 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7269 | { |
7270 | tempreg = AT; | |
7271 | used_at = 1; | |
7272 | } | |
7273 | else | |
7274 | { | |
7275 | tempreg = treg; | |
afdbd6d0 CD |
7276 | } |
7277 | ||
252b5132 RH |
7278 | if (offset_expr.X_op != O_symbol |
7279 | && offset_expr.X_op != O_constant) | |
7280 | { | |
f71d0d44 | 7281 | as_bad (_("Expression too complex")); |
252b5132 RH |
7282 | offset_expr.X_op = O_constant; |
7283 | } | |
7284 | ||
252b5132 | 7285 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7286 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7287 | else if (mips_pic == NO_PIC) |
7288 | { | |
d6bc6245 | 7289 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7290 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7291 | Otherwise we want |
7292 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7293 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7294 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7295 | so we may as well always use the latter form. |
76b3015f | 7296 | |
6caf9ef4 TS |
7297 | With 64bit address space and a usable $at we want |
7298 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7299 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7300 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7301 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7302 | dsll32 $tempreg,0 | |
7303 | daddu $tempreg,$tempreg,$at | |
7304 | ||
7305 | If $at is already in use, we use a path which is suboptimal | |
7306 | on superscalar processors. | |
7307 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7308 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7309 | dsll $tempreg,16 | |
7310 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7311 | dsll $tempreg,16 | |
7312 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7313 | ||
7314 | For GP relative symbols in 64bit address space we can use | |
7315 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7316 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7317 | { |
6caf9ef4 TS |
7318 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7319 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7320 | { | |
7321 | relax_start (offset_expr.X_add_symbol); | |
7322 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7323 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7324 | relax_switch (); | |
7325 | } | |
d6bc6245 | 7326 | |
741fe287 | 7327 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7328 | { |
df58fc94 | 7329 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7330 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7331 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7332 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7333 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7334 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7335 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7336 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7337 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7338 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7339 | used_at = 1; |
7340 | } | |
7341 | else | |
7342 | { | |
df58fc94 | 7343 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7344 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7345 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7346 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7347 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7348 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7349 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7350 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7351 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7352 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7353 | } |
6caf9ef4 TS |
7354 | |
7355 | if (mips_relax.sequence) | |
7356 | relax_end (); | |
98d3f06f KH |
7357 | } |
7358 | else | |
7359 | { | |
7360 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7361 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7362 | { |
4d7206a2 | 7363 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7364 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7365 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7366 | relax_switch (); |
98d3f06f | 7367 | } |
6943caf0 | 7368 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7369 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7370 | macro_build_lui (&offset_expr, tempreg); |
7371 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7372 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7373 | if (mips_relax.sequence) |
7374 | relax_end (); | |
98d3f06f | 7375 | } |
252b5132 | 7376 | } |
0a44bf69 | 7377 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7378 | { |
9117d219 NC |
7379 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7380 | ||
252b5132 RH |
7381 | /* If this is a reference to an external symbol, and there |
7382 | is no constant, we want | |
7383 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7384 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7385 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7386 | For a local symbol, we want |
7387 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7388 | nop | |
7389 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7390 | ||
7391 | If we have a small constant, and this is a reference to | |
7392 | an external symbol, we want | |
7393 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7394 | nop | |
7395 | addiu $tempreg,$tempreg,<constant> | |
7396 | For a local symbol, we want the same instruction | |
7397 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7398 | addiu instruction. | |
7399 | ||
7400 | If we have a large constant, and this is a reference to | |
7401 | an external symbol, we want | |
7402 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7403 | lui $at,<hiconstant> | |
7404 | addiu $at,$at,<loconstant> | |
7405 | addu $tempreg,$tempreg,$at | |
7406 | For a local symbol, we want the same instruction | |
7407 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7408 | addiu instruction. |
ed6fb7bd SC |
7409 | */ |
7410 | ||
4d7206a2 | 7411 | if (offset_expr.X_add_number == 0) |
252b5132 | 7412 | { |
0a44bf69 RS |
7413 | if (mips_pic == SVR4_PIC |
7414 | && breg == 0 | |
7415 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7416 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7417 | ||
7418 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7419 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7420 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7421 | if (breg != 0) |
252b5132 RH |
7422 | { |
7423 | /* We're going to put in an addu instruction using | |
7424 | tempreg, so we may as well insert the nop right | |
7425 | now. */ | |
269137b2 | 7426 | load_delay_nop (); |
252b5132 | 7427 | } |
4d7206a2 | 7428 | relax_switch (); |
67c0d1eb RS |
7429 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7430 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7431 | load_delay_nop (); |
67c0d1eb RS |
7432 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7433 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7434 | relax_end (); |
252b5132 RH |
7435 | /* FIXME: If breg == 0, and the next instruction uses |
7436 | $tempreg, then if this variant case is used an extra | |
7437 | nop will be generated. */ | |
7438 | } | |
4d7206a2 RS |
7439 | else if (offset_expr.X_add_number >= -0x8000 |
7440 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7441 | { |
67c0d1eb | 7442 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7443 | load_delay_nop (); |
67c0d1eb | 7444 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7445 | } |
7446 | else | |
7447 | { | |
4d7206a2 RS |
7448 | expr1.X_add_number = offset_expr.X_add_number; |
7449 | offset_expr.X_add_number = | |
43c0598f | 7450 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7451 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7452 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7453 | /* If we are going to add in a base register, and the |
7454 | target register and the base register are the same, | |
7455 | then we are using AT as a temporary register. Since | |
7456 | we want to load the constant into AT, we add our | |
7457 | current AT (from the global offset table) and the | |
7458 | register into the register now, and pretend we were | |
7459 | not using a base register. */ | |
67c0d1eb | 7460 | if (breg == treg) |
252b5132 | 7461 | { |
269137b2 | 7462 | load_delay_nop (); |
67c0d1eb | 7463 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7464 | treg, AT, breg); |
252b5132 RH |
7465 | breg = 0; |
7466 | tempreg = treg; | |
252b5132 | 7467 | } |
f6a22291 | 7468 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7469 | used_at = 1; |
7470 | } | |
7471 | } | |
0a44bf69 | 7472 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7473 | { |
67c0d1eb | 7474 | int add_breg_early = 0; |
f5040a92 AO |
7475 | |
7476 | /* If this is a reference to an external, and there is no | |
7477 | constant, or local symbol (*), with or without a | |
7478 | constant, we want | |
7479 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7480 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7481 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7482 | ||
7483 | If we have a small constant, and this is a reference to | |
7484 | an external symbol, we want | |
7485 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7486 | addiu $tempreg,$tempreg,<constant> | |
7487 | ||
7488 | If we have a large constant, and this is a reference to | |
7489 | an external symbol, we want | |
7490 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7491 | lui $at,<hiconstant> | |
7492 | addiu $at,$at,<loconstant> | |
7493 | addu $tempreg,$tempreg,$at | |
7494 | ||
7495 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7496 | local symbols, even though it introduces an additional | |
7497 | instruction. */ | |
7498 | ||
f5040a92 AO |
7499 | if (offset_expr.X_add_number) |
7500 | { | |
4d7206a2 | 7501 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7502 | offset_expr.X_add_number = 0; |
7503 | ||
4d7206a2 | 7504 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7505 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7506 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7507 | |
7508 | if (expr1.X_add_number >= -0x8000 | |
7509 | && expr1.X_add_number < 0x8000) | |
7510 | { | |
67c0d1eb RS |
7511 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7512 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7513 | } |
ecd13cd3 | 7514 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7515 | { |
f5040a92 AO |
7516 | /* If we are going to add in a base register, and the |
7517 | target register and the base register are the same, | |
7518 | then we are using AT as a temporary register. Since | |
7519 | we want to load the constant into AT, we add our | |
7520 | current AT (from the global offset table) and the | |
7521 | register into the register now, and pretend we were | |
7522 | not using a base register. */ | |
7523 | if (breg != treg) | |
7524 | dreg = tempreg; | |
7525 | else | |
7526 | { | |
9c2799c2 | 7527 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7528 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7529 | treg, AT, breg); | |
f5040a92 | 7530 | dreg = treg; |
67c0d1eb | 7531 | add_breg_early = 1; |
f5040a92 AO |
7532 | } |
7533 | ||
f6a22291 | 7534 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7535 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7536 | dreg, dreg, AT); |
f5040a92 | 7537 | |
f5040a92 AO |
7538 | used_at = 1; |
7539 | } | |
7540 | else | |
7541 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7542 | ||
4d7206a2 | 7543 | relax_switch (); |
f5040a92 AO |
7544 | offset_expr.X_add_number = expr1.X_add_number; |
7545 | ||
67c0d1eb RS |
7546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7547 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7548 | if (add_breg_early) | |
f5040a92 | 7549 | { |
67c0d1eb | 7550 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7551 | treg, tempreg, breg); |
f5040a92 AO |
7552 | breg = 0; |
7553 | tempreg = treg; | |
7554 | } | |
4d7206a2 | 7555 | relax_end (); |
f5040a92 | 7556 | } |
4d7206a2 | 7557 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7558 | { |
4d7206a2 | 7559 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7560 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7561 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7562 | relax_switch (); |
67c0d1eb RS |
7563 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7564 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7565 | relax_end (); |
f5040a92 | 7566 | } |
4d7206a2 | 7567 | else |
f5040a92 | 7568 | { |
67c0d1eb RS |
7569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7570 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7571 | } |
7572 | } | |
0a44bf69 | 7573 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7574 | { |
67c0d1eb | 7575 | int gpdelay; |
9117d219 NC |
7576 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7577 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7578 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7579 | |
7580 | /* This is the large GOT case. If this is a reference to an | |
7581 | external symbol, and there is no constant, we want | |
7582 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7583 | addu $tempreg,$tempreg,$gp | |
7584 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7585 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7586 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7587 | addu $tempreg,$tempreg,$gp | |
7588 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7589 | For a local symbol, we want |
7590 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7591 | nop | |
7592 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7593 | ||
7594 | If we have a small constant, and this is a reference to | |
7595 | an external symbol, we want | |
7596 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7597 | addu $tempreg,$tempreg,$gp | |
7598 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7599 | nop | |
7600 | addiu $tempreg,$tempreg,<constant> | |
7601 | For a local symbol, we want | |
7602 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7603 | nop | |
7604 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7605 | ||
7606 | If we have a large constant, and this is a reference to | |
7607 | an external symbol, we want | |
7608 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7609 | addu $tempreg,$tempreg,$gp | |
7610 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7611 | lui $at,<hiconstant> | |
7612 | addiu $at,$at,<loconstant> | |
7613 | addu $tempreg,$tempreg,$at | |
7614 | For a local symbol, we want | |
7615 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7616 | lui $at,<hiconstant> | |
7617 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7618 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7619 | */ |
438c16b8 | 7620 | |
252b5132 RH |
7621 | expr1.X_add_number = offset_expr.X_add_number; |
7622 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7623 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7624 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7625 | if (expr1.X_add_number == 0 && breg == 0 |
7626 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7627 | { |
7628 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7629 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7630 | } | |
df58fc94 | 7631 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7632 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7633 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7634 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7635 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7636 | if (expr1.X_add_number == 0) |
7637 | { | |
67c0d1eb | 7638 | if (breg != 0) |
252b5132 RH |
7639 | { |
7640 | /* We're going to put in an addu instruction using | |
7641 | tempreg, so we may as well insert the nop right | |
7642 | now. */ | |
269137b2 | 7643 | load_delay_nop (); |
252b5132 | 7644 | } |
252b5132 RH |
7645 | } |
7646 | else if (expr1.X_add_number >= -0x8000 | |
7647 | && expr1.X_add_number < 0x8000) | |
7648 | { | |
269137b2 | 7649 | load_delay_nop (); |
67c0d1eb | 7650 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7651 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7652 | } |
7653 | else | |
7654 | { | |
252b5132 RH |
7655 | /* If we are going to add in a base register, and the |
7656 | target register and the base register are the same, | |
7657 | then we are using AT as a temporary register. Since | |
7658 | we want to load the constant into AT, we add our | |
7659 | current AT (from the global offset table) and the | |
7660 | register into the register now, and pretend we were | |
7661 | not using a base register. */ | |
7662 | if (breg != treg) | |
67c0d1eb | 7663 | dreg = tempreg; |
252b5132 RH |
7664 | else |
7665 | { | |
9c2799c2 | 7666 | gas_assert (tempreg == AT); |
269137b2 | 7667 | load_delay_nop (); |
67c0d1eb | 7668 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7669 | treg, AT, breg); |
252b5132 | 7670 | dreg = treg; |
252b5132 RH |
7671 | } |
7672 | ||
f6a22291 | 7673 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7674 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7675 | |
252b5132 RH |
7676 | used_at = 1; |
7677 | } | |
43c0598f | 7678 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7679 | relax_switch (); |
252b5132 | 7680 | |
67c0d1eb | 7681 | if (gpdelay) |
252b5132 RH |
7682 | { |
7683 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7684 | the first instruction on the main stream does not. */ |
67c0d1eb | 7685 | macro_build (NULL, "nop", ""); |
252b5132 | 7686 | } |
ed6fb7bd | 7687 | |
67c0d1eb RS |
7688 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7689 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7690 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7691 | && expr1.X_add_number < 0x8000) |
7692 | { | |
269137b2 | 7693 | load_delay_nop (); |
67c0d1eb RS |
7694 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7695 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7696 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7697 | register, the external symbol case ended with a load, |
7698 | so if the symbol turns out to not be external, and | |
7699 | the next instruction uses tempreg, an unnecessary nop | |
7700 | will be inserted. */ | |
252b5132 RH |
7701 | } |
7702 | else | |
7703 | { | |
7704 | if (breg == treg) | |
7705 | { | |
7706 | /* We must add in the base register now, as in the | |
f5040a92 | 7707 | external symbol case. */ |
9c2799c2 | 7708 | gas_assert (tempreg == AT); |
269137b2 | 7709 | load_delay_nop (); |
67c0d1eb | 7710 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7711 | treg, AT, breg); |
252b5132 RH |
7712 | tempreg = treg; |
7713 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7714 | it in in both cases. */ |
252b5132 RH |
7715 | breg = 0; |
7716 | } | |
7717 | ||
67c0d1eb RS |
7718 | macro_build_lui (&expr1, AT); |
7719 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7720 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7721 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7722 | tempreg, tempreg, AT); |
8fc2e39e | 7723 | used_at = 1; |
252b5132 | 7724 | } |
4d7206a2 | 7725 | relax_end (); |
252b5132 | 7726 | } |
0a44bf69 | 7727 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7728 | { |
f5040a92 AO |
7729 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7730 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7731 | int add_breg_early = 0; |
f5040a92 AO |
7732 | |
7733 | /* This is the large GOT case. If this is a reference to an | |
7734 | external symbol, and there is no constant, we want | |
7735 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7736 | add $tempreg,$tempreg,$gp | |
7737 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7738 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7739 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7740 | add $tempreg,$tempreg,$gp | |
7741 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7742 | ||
7743 | If we have a small constant, and this is a reference to | |
7744 | an external symbol, we want | |
7745 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7746 | add $tempreg,$tempreg,$gp | |
7747 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7748 | addi $tempreg,$tempreg,<constant> | |
7749 | ||
7750 | If we have a large constant, and this is a reference to | |
7751 | an external symbol, we want | |
7752 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7753 | addu $tempreg,$tempreg,$gp | |
7754 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7755 | lui $at,<hiconstant> | |
7756 | addi $at,$at,<loconstant> | |
7757 | add $tempreg,$tempreg,$at | |
7758 | ||
7759 | If we have NewABI, and we know it's a local symbol, we want | |
7760 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7761 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7762 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7763 | ||
4d7206a2 | 7764 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7765 | |
4d7206a2 | 7766 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7767 | offset_expr.X_add_number = 0; |
7768 | ||
1abe91b1 MR |
7769 | if (expr1.X_add_number == 0 && breg == 0 |
7770 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7771 | { |
7772 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7773 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7774 | } | |
df58fc94 | 7775 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7776 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7777 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7778 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7779 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7780 | |
7781 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7782 | ; |
f5040a92 AO |
7783 | else if (expr1.X_add_number >= -0x8000 |
7784 | && expr1.X_add_number < 0x8000) | |
7785 | { | |
67c0d1eb | 7786 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7787 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7788 | } |
ecd13cd3 | 7789 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7790 | { |
f5040a92 AO |
7791 | /* If we are going to add in a base register, and the |
7792 | target register and the base register are the same, | |
7793 | then we are using AT as a temporary register. Since | |
7794 | we want to load the constant into AT, we add our | |
7795 | current AT (from the global offset table) and the | |
7796 | register into the register now, and pretend we were | |
7797 | not using a base register. */ | |
7798 | if (breg != treg) | |
7799 | dreg = tempreg; | |
7800 | else | |
7801 | { | |
9c2799c2 | 7802 | gas_assert (tempreg == AT); |
67c0d1eb | 7803 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7804 | treg, AT, breg); |
f5040a92 | 7805 | dreg = treg; |
67c0d1eb | 7806 | add_breg_early = 1; |
f5040a92 AO |
7807 | } |
7808 | ||
f6a22291 | 7809 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7810 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7811 | |
f5040a92 AO |
7812 | used_at = 1; |
7813 | } | |
7814 | else | |
7815 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7816 | ||
4d7206a2 | 7817 | relax_switch (); |
f5040a92 | 7818 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7819 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7820 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7821 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7822 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7823 | if (add_breg_early) | |
f5040a92 | 7824 | { |
67c0d1eb | 7825 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7826 | treg, tempreg, breg); |
f5040a92 AO |
7827 | breg = 0; |
7828 | tempreg = treg; | |
7829 | } | |
4d7206a2 | 7830 | relax_end (); |
f5040a92 | 7831 | } |
252b5132 RH |
7832 | else |
7833 | abort (); | |
7834 | ||
7835 | if (breg != 0) | |
aed1a261 | 7836 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7837 | break; |
7838 | ||
52b6b6b9 | 7839 | case M_MSGSND: |
df58fc94 | 7840 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7841 | { |
7842 | unsigned long temp = (treg << 16) | (0x01); | |
7843 | macro_build (NULL, "c2", "C", temp); | |
7844 | } | |
c7af4273 | 7845 | break; |
52b6b6b9 JM |
7846 | |
7847 | case M_MSGLD: | |
df58fc94 | 7848 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7849 | { |
7850 | unsigned long temp = (0x02); | |
7851 | macro_build (NULL, "c2", "C", temp); | |
7852 | } | |
c7af4273 | 7853 | break; |
52b6b6b9 JM |
7854 | |
7855 | case M_MSGLD_T: | |
df58fc94 | 7856 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7857 | { |
7858 | unsigned long temp = (treg << 16) | (0x02); | |
7859 | macro_build (NULL, "c2", "C", temp); | |
7860 | } | |
c7af4273 | 7861 | break; |
52b6b6b9 JM |
7862 | |
7863 | case M_MSGWAIT: | |
df58fc94 | 7864 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7865 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7866 | break; |
52b6b6b9 JM |
7867 | |
7868 | case M_MSGWAIT_T: | |
df58fc94 | 7869 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7870 | { |
7871 | unsigned long temp = (treg << 16) | 0x03; | |
7872 | macro_build (NULL, "c2", "C", temp); | |
7873 | } | |
c7af4273 | 7874 | break; |
52b6b6b9 | 7875 | |
252b5132 RH |
7876 | case M_J_A: |
7877 | /* The j instruction may not be used in PIC code, since it | |
7878 | requires an absolute address. We convert it to a b | |
7879 | instruction. */ | |
7880 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7881 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7882 | else |
67c0d1eb | 7883 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7884 | break; |
252b5132 RH |
7885 | |
7886 | /* The jal instructions must be handled as macros because when | |
7887 | generating PIC code they expand to multi-instruction | |
7888 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7889 | case M_JALS_1: |
7890 | dreg = RA; | |
7891 | /* Fall through. */ | |
7892 | case M_JALS_2: | |
7893 | gas_assert (mips_opts.micromips); | |
7894 | jals = 1; | |
7895 | goto jal; | |
252b5132 RH |
7896 | case M_JAL_1: |
7897 | dreg = RA; | |
7898 | /* Fall through. */ | |
7899 | case M_JAL_2: | |
df58fc94 | 7900 | jal: |
3e722fb5 | 7901 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7902 | { |
7903 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7904 | if (mips_opts.micromips |
7905 | && dreg == RA | |
7906 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7907 | macro_build (NULL, s, "mj", sreg); |
7908 | else | |
7909 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7910 | } | |
0a44bf69 | 7911 | else |
252b5132 | 7912 | { |
df58fc94 RS |
7913 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7914 | && mips_cprestore_offset >= 0); | |
7915 | ||
252b5132 RH |
7916 | if (sreg != PIC_CALL_REG) |
7917 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7918 | |
df58fc94 RS |
7919 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7920 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7921 | if (mips_opts.micromips |
7922 | && dreg == RA | |
7923 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7924 | macro_build (NULL, s, "mj", sreg); |
7925 | else | |
7926 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7927 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7928 | { |
6478892d TS |
7929 | if (mips_cprestore_offset < 0) |
7930 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7931 | else | |
7932 | { | |
90ecf173 | 7933 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7934 | { |
7935 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7936 | /* Quiet this warning. */ | |
7937 | mips_frame_reg_valid = 1; | |
7938 | } | |
90ecf173 | 7939 | if (!mips_cprestore_valid) |
7a621144 DJ |
7940 | { |
7941 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7942 | /* Quiet this warning. */ | |
7943 | mips_cprestore_valid = 1; | |
7944 | } | |
d3fca0b5 MR |
7945 | if (mips_opts.noreorder) |
7946 | macro_build (NULL, "nop", ""); | |
6478892d | 7947 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7948 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7949 | mips_gp_register, |
256ab948 TS |
7950 | mips_frame_reg, |
7951 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7952 | } |
252b5132 RH |
7953 | } |
7954 | } | |
252b5132 | 7955 | |
8fc2e39e | 7956 | break; |
252b5132 | 7957 | |
df58fc94 RS |
7958 | case M_JALS_A: |
7959 | gas_assert (mips_opts.micromips); | |
7960 | jals = 1; | |
7961 | /* Fall through. */ | |
252b5132 RH |
7962 | case M_JAL_A: |
7963 | if (mips_pic == NO_PIC) | |
df58fc94 | 7964 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7965 | else if (mips_pic == SVR4_PIC) |
7966 | { | |
7967 | /* If this is a reference to an external symbol, and we are | |
7968 | using a small GOT, we want | |
7969 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7970 | nop | |
f9419b05 | 7971 | jalr $ra,$25 |
252b5132 RH |
7972 | nop |
7973 | lw $gp,cprestore($sp) | |
7974 | The cprestore value is set using the .cprestore | |
7975 | pseudo-op. If we are using a big GOT, we want | |
7976 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7977 | addu $25,$25,$gp | |
7978 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7979 | nop | |
f9419b05 | 7980 | jalr $ra,$25 |
252b5132 RH |
7981 | nop |
7982 | lw $gp,cprestore($sp) | |
7983 | If the symbol is not external, we want | |
7984 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7985 | nop | |
7986 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7987 | jalr $ra,$25 |
252b5132 | 7988 | nop |
438c16b8 | 7989 | lw $gp,cprestore($sp) |
f5040a92 AO |
7990 | |
7991 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7992 | sequences above, minus nops, unless the symbol is local, | |
7993 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7994 | GOT_DISP. */ | |
438c16b8 | 7995 | if (HAVE_NEWABI) |
252b5132 | 7996 | { |
90ecf173 | 7997 | if (!mips_big_got) |
f5040a92 | 7998 | { |
4d7206a2 | 7999 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8000 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8001 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8002 | mips_gp_register); |
4d7206a2 | 8003 | relax_switch (); |
67c0d1eb RS |
8004 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8005 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8006 | mips_gp_register); |
8007 | relax_end (); | |
f5040a92 AO |
8008 | } |
8009 | else | |
8010 | { | |
4d7206a2 | 8011 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8012 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8013 | BFD_RELOC_MIPS_CALL_HI16); |
8014 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8015 | PIC_CALL_REG, mips_gp_register); | |
8016 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8017 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8018 | PIC_CALL_REG); | |
4d7206a2 | 8019 | relax_switch (); |
67c0d1eb RS |
8020 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8021 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8022 | mips_gp_register); | |
8023 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8024 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8025 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8026 | relax_end (); |
f5040a92 | 8027 | } |
684022ea | 8028 | |
df58fc94 | 8029 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8030 | } |
8031 | else | |
8032 | { | |
4d7206a2 | 8033 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8034 | if (!mips_big_got) |
438c16b8 | 8035 | { |
67c0d1eb RS |
8036 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8037 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8038 | mips_gp_register); |
269137b2 | 8039 | load_delay_nop (); |
4d7206a2 | 8040 | relax_switch (); |
438c16b8 | 8041 | } |
252b5132 | 8042 | else |
252b5132 | 8043 | { |
67c0d1eb RS |
8044 | int gpdelay; |
8045 | ||
8046 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8047 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8048 | BFD_RELOC_MIPS_CALL_HI16); |
8049 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8050 | PIC_CALL_REG, mips_gp_register); | |
8051 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8052 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8053 | PIC_CALL_REG); | |
269137b2 | 8054 | load_delay_nop (); |
4d7206a2 | 8055 | relax_switch (); |
67c0d1eb RS |
8056 | if (gpdelay) |
8057 | macro_build (NULL, "nop", ""); | |
252b5132 | 8058 | } |
67c0d1eb RS |
8059 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8060 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8061 | mips_gp_register); |
269137b2 | 8062 | load_delay_nop (); |
67c0d1eb RS |
8063 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8064 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8065 | relax_end (); |
df58fc94 | 8066 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8067 | |
6478892d TS |
8068 | if (mips_cprestore_offset < 0) |
8069 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8070 | else | |
8071 | { | |
90ecf173 | 8072 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8073 | { |
8074 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8075 | /* Quiet this warning. */ | |
8076 | mips_frame_reg_valid = 1; | |
8077 | } | |
90ecf173 | 8078 | if (!mips_cprestore_valid) |
7a621144 DJ |
8079 | { |
8080 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8081 | /* Quiet this warning. */ | |
8082 | mips_cprestore_valid = 1; | |
8083 | } | |
6478892d | 8084 | if (mips_opts.noreorder) |
67c0d1eb | 8085 | macro_build (NULL, "nop", ""); |
6478892d | 8086 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8087 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8088 | mips_gp_register, |
256ab948 TS |
8089 | mips_frame_reg, |
8090 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8091 | } |
252b5132 RH |
8092 | } |
8093 | } | |
0a44bf69 RS |
8094 | else if (mips_pic == VXWORKS_PIC) |
8095 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8096 | else |
8097 | abort (); | |
8098 | ||
8fc2e39e | 8099 | break; |
252b5132 | 8100 | |
dec0624d MR |
8101 | case M_ACLR_AB: |
8102 | ab = 1; | |
8103 | case M_ACLR_OB: | |
8104 | s = "aclr"; | |
8105 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8106 | fmt = "\\,~(b)"; | |
8107 | off12 = 1; | |
8108 | goto ld_st; | |
8109 | case M_ASET_AB: | |
8110 | ab = 1; | |
8111 | case M_ASET_OB: | |
8112 | s = "aset"; | |
8113 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8114 | fmt = "\\,~(b)"; | |
8115 | off12 = 1; | |
8116 | goto ld_st; | |
252b5132 | 8117 | case M_LB_AB: |
df58fc94 | 8118 | ab = 1; |
252b5132 | 8119 | s = "lb"; |
df58fc94 | 8120 | fmt = "t,o(b)"; |
252b5132 RH |
8121 | goto ld; |
8122 | case M_LBU_AB: | |
df58fc94 | 8123 | ab = 1; |
252b5132 | 8124 | s = "lbu"; |
df58fc94 | 8125 | fmt = "t,o(b)"; |
252b5132 RH |
8126 | goto ld; |
8127 | case M_LH_AB: | |
df58fc94 | 8128 | ab = 1; |
252b5132 | 8129 | s = "lh"; |
df58fc94 | 8130 | fmt = "t,o(b)"; |
252b5132 RH |
8131 | goto ld; |
8132 | case M_LHU_AB: | |
df58fc94 | 8133 | ab = 1; |
252b5132 | 8134 | s = "lhu"; |
df58fc94 | 8135 | fmt = "t,o(b)"; |
252b5132 RH |
8136 | goto ld; |
8137 | case M_LW_AB: | |
df58fc94 | 8138 | ab = 1; |
252b5132 | 8139 | s = "lw"; |
df58fc94 | 8140 | fmt = "t,o(b)"; |
252b5132 RH |
8141 | goto ld; |
8142 | case M_LWC0_AB: | |
df58fc94 RS |
8143 | ab = 1; |
8144 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8145 | s = "lwc0"; |
df58fc94 | 8146 | fmt = "E,o(b)"; |
bdaaa2e1 | 8147 | /* Itbl support may require additional care here. */ |
252b5132 | 8148 | coproc = 1; |
df58fc94 | 8149 | goto ld_st; |
252b5132 | 8150 | case M_LWC1_AB: |
df58fc94 | 8151 | ab = 1; |
252b5132 | 8152 | s = "lwc1"; |
df58fc94 | 8153 | fmt = "T,o(b)"; |
bdaaa2e1 | 8154 | /* Itbl support may require additional care here. */ |
252b5132 | 8155 | coproc = 1; |
df58fc94 | 8156 | goto ld_st; |
252b5132 | 8157 | case M_LWC2_AB: |
df58fc94 RS |
8158 | ab = 1; |
8159 | case M_LWC2_OB: | |
252b5132 | 8160 | s = "lwc2"; |
df58fc94 RS |
8161 | fmt = COP12_FMT; |
8162 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8163 | /* Itbl support may require additional care here. */ |
252b5132 | 8164 | coproc = 1; |
df58fc94 | 8165 | goto ld_st; |
252b5132 | 8166 | case M_LWC3_AB: |
df58fc94 RS |
8167 | ab = 1; |
8168 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8169 | s = "lwc3"; |
df58fc94 | 8170 | fmt = "E,o(b)"; |
bdaaa2e1 | 8171 | /* Itbl support may require additional care here. */ |
252b5132 | 8172 | coproc = 1; |
df58fc94 | 8173 | goto ld_st; |
252b5132 | 8174 | case M_LWL_AB: |
df58fc94 RS |
8175 | ab = 1; |
8176 | case M_LWL_OB: | |
252b5132 | 8177 | s = "lwl"; |
df58fc94 RS |
8178 | fmt = MEM12_FMT; |
8179 | off12 = mips_opts.micromips; | |
8180 | goto ld_st; | |
252b5132 | 8181 | case M_LWR_AB: |
df58fc94 RS |
8182 | ab = 1; |
8183 | case M_LWR_OB: | |
252b5132 | 8184 | s = "lwr"; |
df58fc94 RS |
8185 | fmt = MEM12_FMT; |
8186 | off12 = mips_opts.micromips; | |
8187 | goto ld_st; | |
252b5132 | 8188 | case M_LDC1_AB: |
df58fc94 | 8189 | ab = 1; |
252b5132 | 8190 | s = "ldc1"; |
df58fc94 | 8191 | fmt = "T,o(b)"; |
bdaaa2e1 | 8192 | /* Itbl support may require additional care here. */ |
252b5132 | 8193 | coproc = 1; |
df58fc94 | 8194 | goto ld_st; |
252b5132 | 8195 | case M_LDC2_AB: |
df58fc94 RS |
8196 | ab = 1; |
8197 | case M_LDC2_OB: | |
252b5132 | 8198 | s = "ldc2"; |
df58fc94 RS |
8199 | fmt = COP12_FMT; |
8200 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8201 | /* Itbl support may require additional care here. */ |
252b5132 | 8202 | coproc = 1; |
df58fc94 | 8203 | goto ld_st; |
c77c0862 RS |
8204 | case M_LQC2_AB: |
8205 | ab = 1; | |
8206 | s = "lqc2"; | |
8207 | fmt = "E,o(b)"; | |
8208 | /* Itbl support may require additional care here. */ | |
8209 | coproc = 1; | |
8210 | goto ld_st; | |
252b5132 | 8211 | case M_LDC3_AB: |
df58fc94 | 8212 | ab = 1; |
252b5132 | 8213 | s = "ldc3"; |
df58fc94 | 8214 | fmt = "E,o(b)"; |
bdaaa2e1 | 8215 | /* Itbl support may require additional care here. */ |
252b5132 | 8216 | coproc = 1; |
df58fc94 | 8217 | goto ld_st; |
252b5132 | 8218 | case M_LDL_AB: |
df58fc94 RS |
8219 | ab = 1; |
8220 | case M_LDL_OB: | |
252b5132 | 8221 | s = "ldl"; |
df58fc94 RS |
8222 | fmt = MEM12_FMT; |
8223 | off12 = mips_opts.micromips; | |
8224 | goto ld_st; | |
252b5132 | 8225 | case M_LDR_AB: |
df58fc94 RS |
8226 | ab = 1; |
8227 | case M_LDR_OB: | |
252b5132 | 8228 | s = "ldr"; |
df58fc94 RS |
8229 | fmt = MEM12_FMT; |
8230 | off12 = mips_opts.micromips; | |
8231 | goto ld_st; | |
252b5132 | 8232 | case M_LL_AB: |
df58fc94 RS |
8233 | ab = 1; |
8234 | case M_LL_OB: | |
252b5132 | 8235 | s = "ll"; |
df58fc94 RS |
8236 | fmt = MEM12_FMT; |
8237 | off12 = mips_opts.micromips; | |
252b5132 RH |
8238 | goto ld; |
8239 | case M_LLD_AB: | |
df58fc94 RS |
8240 | ab = 1; |
8241 | case M_LLD_OB: | |
252b5132 | 8242 | s = "lld"; |
df58fc94 RS |
8243 | fmt = MEM12_FMT; |
8244 | off12 = mips_opts.micromips; | |
252b5132 RH |
8245 | goto ld; |
8246 | case M_LWU_AB: | |
df58fc94 RS |
8247 | ab = 1; |
8248 | case M_LWU_OB: | |
252b5132 | 8249 | s = "lwu"; |
df58fc94 RS |
8250 | fmt = MEM12_FMT; |
8251 | off12 = mips_opts.micromips; | |
8252 | goto ld; | |
8253 | case M_LWP_AB: | |
8254 | ab = 1; | |
8255 | case M_LWP_OB: | |
8256 | gas_assert (mips_opts.micromips); | |
8257 | s = "lwp"; | |
8258 | fmt = "t,~(b)"; | |
8259 | off12 = 1; | |
8260 | lp = 1; | |
8261 | goto ld; | |
8262 | case M_LDP_AB: | |
8263 | ab = 1; | |
8264 | case M_LDP_OB: | |
8265 | gas_assert (mips_opts.micromips); | |
8266 | s = "ldp"; | |
8267 | fmt = "t,~(b)"; | |
8268 | off12 = 1; | |
8269 | lp = 1; | |
8270 | goto ld; | |
8271 | case M_LWM_AB: | |
8272 | ab = 1; | |
8273 | case M_LWM_OB: | |
8274 | gas_assert (mips_opts.micromips); | |
8275 | s = "lwm"; | |
8276 | fmt = "n,~(b)"; | |
8277 | off12 = 1; | |
8278 | goto ld_st; | |
8279 | case M_LDM_AB: | |
8280 | ab = 1; | |
8281 | case M_LDM_OB: | |
8282 | gas_assert (mips_opts.micromips); | |
8283 | s = "ldm"; | |
8284 | fmt = "n,~(b)"; | |
8285 | off12 = 1; | |
8286 | goto ld_st; | |
8287 | ||
252b5132 | 8288 | ld: |
df58fc94 RS |
8289 | if (breg == treg + lp) |
8290 | goto ld_st; | |
252b5132 | 8291 | else |
df58fc94 RS |
8292 | tempreg = treg + lp; |
8293 | goto ld_noat; | |
8294 | ||
252b5132 | 8295 | case M_SB_AB: |
df58fc94 | 8296 | ab = 1; |
252b5132 | 8297 | s = "sb"; |
df58fc94 RS |
8298 | fmt = "t,o(b)"; |
8299 | goto ld_st; | |
252b5132 | 8300 | case M_SH_AB: |
df58fc94 | 8301 | ab = 1; |
252b5132 | 8302 | s = "sh"; |
df58fc94 RS |
8303 | fmt = "t,o(b)"; |
8304 | goto ld_st; | |
252b5132 | 8305 | case M_SW_AB: |
df58fc94 | 8306 | ab = 1; |
252b5132 | 8307 | s = "sw"; |
df58fc94 RS |
8308 | fmt = "t,o(b)"; |
8309 | goto ld_st; | |
252b5132 | 8310 | case M_SWC0_AB: |
df58fc94 RS |
8311 | ab = 1; |
8312 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8313 | s = "swc0"; |
df58fc94 | 8314 | fmt = "E,o(b)"; |
bdaaa2e1 | 8315 | /* Itbl support may require additional care here. */ |
252b5132 | 8316 | coproc = 1; |
df58fc94 | 8317 | goto ld_st; |
252b5132 | 8318 | case M_SWC1_AB: |
df58fc94 | 8319 | ab = 1; |
252b5132 | 8320 | s = "swc1"; |
df58fc94 | 8321 | fmt = "T,o(b)"; |
bdaaa2e1 | 8322 | /* Itbl support may require additional care here. */ |
252b5132 | 8323 | coproc = 1; |
df58fc94 | 8324 | goto ld_st; |
252b5132 | 8325 | case M_SWC2_AB: |
df58fc94 RS |
8326 | ab = 1; |
8327 | case M_SWC2_OB: | |
252b5132 | 8328 | s = "swc2"; |
df58fc94 RS |
8329 | fmt = COP12_FMT; |
8330 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8331 | /* Itbl support may require additional care here. */ |
252b5132 | 8332 | coproc = 1; |
df58fc94 | 8333 | goto ld_st; |
252b5132 | 8334 | case M_SWC3_AB: |
df58fc94 RS |
8335 | ab = 1; |
8336 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8337 | s = "swc3"; |
df58fc94 | 8338 | fmt = "E,o(b)"; |
bdaaa2e1 | 8339 | /* Itbl support may require additional care here. */ |
252b5132 | 8340 | coproc = 1; |
df58fc94 | 8341 | goto ld_st; |
252b5132 | 8342 | case M_SWL_AB: |
df58fc94 RS |
8343 | ab = 1; |
8344 | case M_SWL_OB: | |
252b5132 | 8345 | s = "swl"; |
df58fc94 RS |
8346 | fmt = MEM12_FMT; |
8347 | off12 = mips_opts.micromips; | |
8348 | goto ld_st; | |
252b5132 | 8349 | case M_SWR_AB: |
df58fc94 RS |
8350 | ab = 1; |
8351 | case M_SWR_OB: | |
252b5132 | 8352 | s = "swr"; |
df58fc94 RS |
8353 | fmt = MEM12_FMT; |
8354 | off12 = mips_opts.micromips; | |
8355 | goto ld_st; | |
252b5132 | 8356 | case M_SC_AB: |
df58fc94 RS |
8357 | ab = 1; |
8358 | case M_SC_OB: | |
252b5132 | 8359 | s = "sc"; |
df58fc94 RS |
8360 | fmt = MEM12_FMT; |
8361 | off12 = mips_opts.micromips; | |
8362 | goto ld_st; | |
252b5132 | 8363 | case M_SCD_AB: |
df58fc94 RS |
8364 | ab = 1; |
8365 | case M_SCD_OB: | |
252b5132 | 8366 | s = "scd"; |
df58fc94 RS |
8367 | fmt = MEM12_FMT; |
8368 | off12 = mips_opts.micromips; | |
8369 | goto ld_st; | |
d43b4baf | 8370 | case M_CACHE_AB: |
df58fc94 RS |
8371 | ab = 1; |
8372 | case M_CACHE_OB: | |
d43b4baf | 8373 | s = "cache"; |
df58fc94 RS |
8374 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8375 | off12 = mips_opts.micromips; | |
8376 | goto ld_st; | |
3eebd5eb | 8377 | case M_PREF_AB: |
df58fc94 RS |
8378 | ab = 1; |
8379 | case M_PREF_OB: | |
3eebd5eb | 8380 | s = "pref"; |
df58fc94 RS |
8381 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8382 | off12 = mips_opts.micromips; | |
8383 | goto ld_st; | |
252b5132 | 8384 | case M_SDC1_AB: |
df58fc94 | 8385 | ab = 1; |
252b5132 | 8386 | s = "sdc1"; |
df58fc94 | 8387 | fmt = "T,o(b)"; |
252b5132 | 8388 | coproc = 1; |
bdaaa2e1 | 8389 | /* Itbl support may require additional care here. */ |
df58fc94 | 8390 | goto ld_st; |
252b5132 | 8391 | case M_SDC2_AB: |
df58fc94 RS |
8392 | ab = 1; |
8393 | case M_SDC2_OB: | |
252b5132 | 8394 | s = "sdc2"; |
df58fc94 RS |
8395 | fmt = COP12_FMT; |
8396 | off12 = mips_opts.micromips; | |
c77c0862 RS |
8397 | /* Itbl support may require additional care here. */ |
8398 | coproc = 1; | |
8399 | goto ld_st; | |
8400 | case M_SQC2_AB: | |
8401 | ab = 1; | |
8402 | s = "sqc2"; | |
8403 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8404 | /* Itbl support may require additional care here. */ |
252b5132 | 8405 | coproc = 1; |
df58fc94 | 8406 | goto ld_st; |
252b5132 | 8407 | case M_SDC3_AB: |
df58fc94 RS |
8408 | ab = 1; |
8409 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8410 | s = "sdc3"; |
df58fc94 | 8411 | fmt = "E,o(b)"; |
bdaaa2e1 | 8412 | /* Itbl support may require additional care here. */ |
252b5132 | 8413 | coproc = 1; |
df58fc94 | 8414 | goto ld_st; |
252b5132 | 8415 | case M_SDL_AB: |
df58fc94 RS |
8416 | ab = 1; |
8417 | case M_SDL_OB: | |
252b5132 | 8418 | s = "sdl"; |
df58fc94 RS |
8419 | fmt = MEM12_FMT; |
8420 | off12 = mips_opts.micromips; | |
8421 | goto ld_st; | |
252b5132 | 8422 | case M_SDR_AB: |
df58fc94 RS |
8423 | ab = 1; |
8424 | case M_SDR_OB: | |
252b5132 | 8425 | s = "sdr"; |
df58fc94 RS |
8426 | fmt = MEM12_FMT; |
8427 | off12 = mips_opts.micromips; | |
8428 | goto ld_st; | |
8429 | case M_SWP_AB: | |
8430 | ab = 1; | |
8431 | case M_SWP_OB: | |
8432 | gas_assert (mips_opts.micromips); | |
8433 | s = "swp"; | |
8434 | fmt = "t,~(b)"; | |
8435 | off12 = 1; | |
8436 | goto ld_st; | |
8437 | case M_SDP_AB: | |
8438 | ab = 1; | |
8439 | case M_SDP_OB: | |
8440 | gas_assert (mips_opts.micromips); | |
8441 | s = "sdp"; | |
8442 | fmt = "t,~(b)"; | |
8443 | off12 = 1; | |
8444 | goto ld_st; | |
8445 | case M_SWM_AB: | |
8446 | ab = 1; | |
8447 | case M_SWM_OB: | |
8448 | gas_assert (mips_opts.micromips); | |
8449 | s = "swm"; | |
8450 | fmt = "n,~(b)"; | |
8451 | off12 = 1; | |
8452 | goto ld_st; | |
8453 | case M_SDM_AB: | |
8454 | ab = 1; | |
8455 | case M_SDM_OB: | |
8456 | gas_assert (mips_opts.micromips); | |
8457 | s = "sdm"; | |
8458 | fmt = "n,~(b)"; | |
8459 | off12 = 1; | |
8460 | ||
8461 | ld_st: | |
8fc2e39e TS |
8462 | tempreg = AT; |
8463 | used_at = 1; | |
df58fc94 | 8464 | ld_noat: |
252b5132 RH |
8465 | if (offset_expr.X_op != O_constant |
8466 | && offset_expr.X_op != O_symbol) | |
8467 | { | |
f71d0d44 | 8468 | as_bad (_("Expression too complex")); |
252b5132 RH |
8469 | offset_expr.X_op = O_constant; |
8470 | } | |
8471 | ||
2051e8c4 MR |
8472 | if (HAVE_32BIT_ADDRESSES |
8473 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8474 | { |
8475 | char value [32]; | |
8476 | ||
8477 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8478 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8479 | } |
2051e8c4 | 8480 | |
252b5132 RH |
8481 | /* A constant expression in PIC code can be handled just as it |
8482 | is in non PIC code. */ | |
aed1a261 RS |
8483 | if (offset_expr.X_op == O_constant) |
8484 | { | |
df58fc94 RS |
8485 | int hipart = 0; |
8486 | ||
842f8b2a | 8487 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8488 | normalize_address_expr (&expr1); |
df58fc94 | 8489 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8490 | { |
8491 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8492 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8493 | hipart = 1; |
8494 | } | |
8495 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8496 | { | |
8497 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8498 | & ~(bfd_vma) 0xfff); | |
8499 | hipart = 1; | |
8500 | } | |
8501 | if (hipart) | |
8502 | { | |
842f8b2a MR |
8503 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8504 | if (breg != 0) | |
8505 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8506 | tempreg, tempreg, breg); | |
8507 | breg = tempreg; | |
8508 | } | |
dd6a37e7 AP |
8509 | if (off0) |
8510 | { | |
8511 | if (offset_expr.X_add_number == 0) | |
8512 | tempreg = breg; | |
8513 | else | |
8514 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8515 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8516 | macro_build (NULL, s, fmt, treg, tempreg); | |
8517 | } | |
8518 | else if (!off12) | |
df58fc94 RS |
8519 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8520 | else | |
8521 | macro_build (NULL, s, fmt, | |
8522 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8523 | } | |
dd6a37e7 | 8524 | else if (off12 || off0) |
df58fc94 | 8525 | { |
dd6a37e7 AP |
8526 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8527 | for a low-part relocation, so load the whole address into | |
8528 | the auxillary register. In the case of "A(b)" addresses, | |
8529 | we first load absolute address "A" into the register and | |
8530 | then add base register "b". In the case of "o(b)" addresses, | |
8531 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8532 | offset_reloc already contains the relocations associated |
8533 | with "o". */ | |
8534 | if (ab) | |
8535 | { | |
8536 | load_address (tempreg, &offset_expr, &used_at); | |
8537 | if (breg != 0) | |
8538 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8539 | tempreg, tempreg, breg); | |
8540 | } | |
8541 | else | |
8542 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8543 | tempreg, breg, -1, | |
8544 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8545 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8546 | if (off0) |
8547 | macro_build (NULL, s, fmt, treg, tempreg); | |
8548 | else | |
8549 | macro_build (NULL, s, fmt, | |
8550 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8551 | } |
8552 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8553 | { |
8554 | /* If this is a reference to a GP relative symbol, and there | |
8555 | is no base register, we want | |
cdf6fd85 | 8556 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8557 | Otherwise, if there is no base register, we want |
8558 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8559 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8560 | If we have a constant, we need two instructions anyhow, | |
8561 | so we always use the latter form. | |
8562 | ||
8563 | If we have a base register, and this is a reference to a | |
8564 | GP relative symbol, we want | |
8565 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8566 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8567 | Otherwise we want |
8568 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8569 | addu $tempreg,$tempreg,$breg | |
8570 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8571 | With a constant we always use the latter case. |
76b3015f | 8572 | |
d6bc6245 TS |
8573 | With 64bit address space and no base register and $at usable, |
8574 | we want | |
8575 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8576 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8577 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8578 | dsll32 $tempreg,0 | |
8579 | daddu $tempreg,$at | |
8580 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8581 | If we have a base register, we want | |
8582 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8583 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8584 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8585 | daddu $at,$breg | |
8586 | dsll32 $tempreg,0 | |
8587 | daddu $tempreg,$at | |
8588 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8589 | ||
8590 | Without $at we can't generate the optimal path for superscalar | |
8591 | processors here since this would require two temporary registers. | |
8592 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8593 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8594 | dsll $tempreg,16 | |
8595 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8596 | dsll $tempreg,16 | |
8597 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8598 | If we have a base register, we want | |
8599 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8600 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8601 | dsll $tempreg,16 | |
8602 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8603 | dsll $tempreg,16 | |
8604 | daddu $tempreg,$tempreg,$breg | |
8605 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8606 | |
6caf9ef4 | 8607 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8608 | the same sequence as in 32bit address space. */ |
8609 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8610 | { |
aed1a261 | 8611 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8612 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8613 | { | |
8614 | relax_start (offset_expr.X_add_symbol); | |
8615 | if (breg == 0) | |
8616 | { | |
8617 | macro_build (&offset_expr, s, fmt, treg, | |
8618 | BFD_RELOC_GPREL16, mips_gp_register); | |
8619 | } | |
8620 | else | |
8621 | { | |
8622 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8623 | tempreg, breg, mips_gp_register); | |
8624 | macro_build (&offset_expr, s, fmt, treg, | |
8625 | BFD_RELOC_GPREL16, tempreg); | |
8626 | } | |
8627 | relax_switch (); | |
8628 | } | |
d6bc6245 | 8629 | |
741fe287 | 8630 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8631 | { |
df58fc94 | 8632 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8633 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8634 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8635 | BFD_RELOC_HI16_S); |
8636 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8637 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8638 | if (breg != 0) |
67c0d1eb | 8639 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8640 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8641 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8642 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8643 | tempreg); | |
d6bc6245 TS |
8644 | used_at = 1; |
8645 | } | |
8646 | else | |
8647 | { | |
df58fc94 | 8648 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8649 | BFD_RELOC_MIPS_HIGHEST); |
8650 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8651 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8652 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8653 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8654 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8655 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8656 | if (breg != 0) |
67c0d1eb | 8657 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8658 | tempreg, tempreg, breg); |
67c0d1eb | 8659 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8660 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8661 | } |
6caf9ef4 TS |
8662 | |
8663 | if (mips_relax.sequence) | |
8664 | relax_end (); | |
8fc2e39e | 8665 | break; |
d6bc6245 | 8666 | } |
256ab948 | 8667 | |
252b5132 RH |
8668 | if (breg == 0) |
8669 | { | |
67c0d1eb | 8670 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8671 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8672 | { |
4d7206a2 | 8673 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8674 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8675 | mips_gp_register); | |
4d7206a2 | 8676 | relax_switch (); |
252b5132 | 8677 | } |
67c0d1eb RS |
8678 | macro_build_lui (&offset_expr, tempreg); |
8679 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8680 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8681 | if (mips_relax.sequence) |
8682 | relax_end (); | |
252b5132 RH |
8683 | } |
8684 | else | |
8685 | { | |
67c0d1eb | 8686 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8687 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8688 | { |
4d7206a2 | 8689 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8690 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8691 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8692 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8693 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8694 | relax_switch (); |
252b5132 | 8695 | } |
67c0d1eb RS |
8696 | macro_build_lui (&offset_expr, tempreg); |
8697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8698 | tempreg, tempreg, breg); |
67c0d1eb | 8699 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8700 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8701 | if (mips_relax.sequence) |
8702 | relax_end (); | |
252b5132 RH |
8703 | } |
8704 | } | |
0a44bf69 | 8705 | else if (!mips_big_got) |
252b5132 | 8706 | { |
ed6fb7bd | 8707 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8708 | |
252b5132 RH |
8709 | /* If this is a reference to an external symbol, we want |
8710 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8711 | nop | |
8712 | <op> $treg,0($tempreg) | |
8713 | Otherwise we want | |
8714 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8715 | nop | |
8716 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8717 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8718 | |
8719 | For NewABI, we want | |
8720 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8721 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8722 | ||
252b5132 RH |
8723 | If there is a base register, we add it to $tempreg before |
8724 | the <op>. If there is a constant, we stick it in the | |
8725 | <op> instruction. We don't handle constants larger than | |
8726 | 16 bits, because we have no way to load the upper 16 bits | |
8727 | (actually, we could handle them for the subset of cases | |
8728 | in which we are not using $at). */ | |
9c2799c2 | 8729 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8730 | if (HAVE_NEWABI) |
8731 | { | |
67c0d1eb RS |
8732 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8733 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8734 | if (breg != 0) |
67c0d1eb | 8735 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8736 | tempreg, tempreg, breg); |
67c0d1eb | 8737 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8738 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8739 | break; |
8740 | } | |
252b5132 RH |
8741 | expr1.X_add_number = offset_expr.X_add_number; |
8742 | offset_expr.X_add_number = 0; | |
8743 | if (expr1.X_add_number < -0x8000 | |
8744 | || expr1.X_add_number >= 0x8000) | |
8745 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8746 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8747 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8748 | load_delay_nop (); |
4d7206a2 RS |
8749 | relax_start (offset_expr.X_add_symbol); |
8750 | relax_switch (); | |
67c0d1eb RS |
8751 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8752 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8753 | relax_end (); |
252b5132 | 8754 | if (breg != 0) |
67c0d1eb | 8755 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8756 | tempreg, tempreg, breg); |
67c0d1eb | 8757 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8758 | } |
0a44bf69 | 8759 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8760 | { |
67c0d1eb | 8761 | int gpdelay; |
252b5132 RH |
8762 | |
8763 | /* If this is a reference to an external symbol, we want | |
8764 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8765 | addu $tempreg,$tempreg,$gp | |
8766 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8767 | <op> $treg,0($tempreg) | |
8768 | Otherwise we want | |
8769 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8770 | nop | |
8771 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8772 | <op> $treg,0($tempreg) | |
8773 | If there is a base register, we add it to $tempreg before | |
8774 | the <op>. If there is a constant, we stick it in the | |
8775 | <op> instruction. We don't handle constants larger than | |
8776 | 16 bits, because we have no way to load the upper 16 bits | |
8777 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8778 | in which we are not using $at). */ |
9c2799c2 | 8779 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8780 | expr1.X_add_number = offset_expr.X_add_number; |
8781 | offset_expr.X_add_number = 0; | |
8782 | if (expr1.X_add_number < -0x8000 | |
8783 | || expr1.X_add_number >= 0x8000) | |
8784 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8785 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8786 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8787 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8788 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8789 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8790 | mips_gp_register); | |
8791 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8792 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8793 | relax_switch (); |
67c0d1eb RS |
8794 | if (gpdelay) |
8795 | macro_build (NULL, "nop", ""); | |
8796 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8797 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8798 | load_delay_nop (); |
67c0d1eb RS |
8799 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8800 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8801 | relax_end (); |
8802 | ||
252b5132 | 8803 | if (breg != 0) |
67c0d1eb | 8804 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8805 | tempreg, tempreg, breg); |
67c0d1eb | 8806 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8807 | } |
0a44bf69 | 8808 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8809 | { |
f5040a92 AO |
8810 | /* If this is a reference to an external symbol, we want |
8811 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8812 | add $tempreg,$tempreg,$gp | |
8813 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8814 | <op> $treg,<ofst>($tempreg) | |
8815 | Otherwise, for local symbols, we want: | |
8816 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8817 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8818 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8819 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8820 | offset_expr.X_add_number = 0; |
8821 | if (expr1.X_add_number < -0x8000 | |
8822 | || expr1.X_add_number >= 0x8000) | |
8823 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8824 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8825 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8826 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8827 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8828 | mips_gp_register); | |
8829 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8830 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8831 | if (breg != 0) |
67c0d1eb | 8832 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8833 | tempreg, tempreg, breg); |
67c0d1eb | 8834 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8835 | |
4d7206a2 | 8836 | relax_switch (); |
f5040a92 | 8837 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8838 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8839 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8840 | if (breg != 0) |
67c0d1eb | 8841 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8842 | tempreg, tempreg, breg); |
67c0d1eb | 8843 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8844 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8845 | relax_end (); |
f5040a92 | 8846 | } |
252b5132 RH |
8847 | else |
8848 | abort (); | |
8849 | ||
252b5132 RH |
8850 | break; |
8851 | ||
8852 | case M_LI: | |
8853 | case M_LI_S: | |
67c0d1eb | 8854 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8855 | break; |
252b5132 RH |
8856 | |
8857 | case M_DLI: | |
67c0d1eb | 8858 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8859 | break; |
252b5132 RH |
8860 | |
8861 | case M_LI_SS: | |
8862 | if (imm_expr.X_op == O_constant) | |
8863 | { | |
8fc2e39e | 8864 | used_at = 1; |
67c0d1eb RS |
8865 | load_register (AT, &imm_expr, 0); |
8866 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8867 | break; |
8868 | } | |
8869 | else | |
8870 | { | |
9c2799c2 | 8871 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8872 | && strcmp (segment_name (S_GET_SEGMENT |
8873 | (offset_expr.X_add_symbol)), | |
8874 | ".lit4") == 0 | |
8875 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8876 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8877 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8878 | break; |
252b5132 RH |
8879 | } |
8880 | ||
8881 | case M_LI_D: | |
ca4e0257 RS |
8882 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8883 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8884 | order 32 bits of the value and the low order 32 bits are either | |
8885 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8886 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8887 | { | |
ca4e0257 | 8888 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8889 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8890 | else |
8891 | { | |
8892 | int hreg, lreg; | |
8893 | ||
8894 | if (target_big_endian) | |
8895 | { | |
8896 | hreg = treg; | |
8897 | lreg = treg + 1; | |
8898 | } | |
8899 | else | |
8900 | { | |
8901 | hreg = treg + 1; | |
8902 | lreg = treg; | |
8903 | } | |
8904 | ||
8905 | if (hreg <= 31) | |
67c0d1eb | 8906 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8907 | if (lreg <= 31) |
8908 | { | |
8909 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8910 | move_register (lreg, 0); |
252b5132 RH |
8911 | else |
8912 | { | |
9c2799c2 | 8913 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8914 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8915 | } |
8916 | } | |
8917 | } | |
8fc2e39e | 8918 | break; |
252b5132 RH |
8919 | } |
8920 | ||
8921 | /* We know that sym is in the .rdata section. First we get the | |
8922 | upper 16 bits of the address. */ | |
8923 | if (mips_pic == NO_PIC) | |
8924 | { | |
67c0d1eb | 8925 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8926 | used_at = 1; |
252b5132 | 8927 | } |
0a44bf69 | 8928 | else |
252b5132 | 8929 | { |
67c0d1eb RS |
8930 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8931 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8932 | used_at = 1; |
252b5132 | 8933 | } |
bdaaa2e1 | 8934 | |
252b5132 | 8935 | /* Now we load the register(s). */ |
ca4e0257 | 8936 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8937 | { |
8938 | used_at = 1; | |
8939 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8940 | } | |
252b5132 RH |
8941 | else |
8942 | { | |
8fc2e39e | 8943 | used_at = 1; |
67c0d1eb | 8944 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8945 | if (treg != RA) |
252b5132 RH |
8946 | { |
8947 | /* FIXME: How in the world do we deal with the possible | |
8948 | overflow here? */ | |
8949 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8950 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8951 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8952 | } |
8953 | } | |
252b5132 RH |
8954 | break; |
8955 | ||
8956 | case M_LI_DD: | |
ca4e0257 RS |
8957 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8958 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8959 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8960 | the value and the low order 32 bits are either zero or in | |
8961 | OFFSET_EXPR. */ | |
252b5132 RH |
8962 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8963 | { | |
8fc2e39e | 8964 | used_at = 1; |
67c0d1eb | 8965 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8966 | if (HAVE_64BIT_FPRS) |
8967 | { | |
9c2799c2 | 8968 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8969 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8970 | } |
252b5132 RH |
8971 | else |
8972 | { | |
67c0d1eb | 8973 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8974 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8975 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8976 | else |
8977 | { | |
9c2799c2 | 8978 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8979 | load_register (AT, &offset_expr, 0); |
8980 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8981 | } |
8982 | } | |
8983 | break; | |
8984 | } | |
8985 | ||
9c2799c2 | 8986 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8987 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8988 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8989 | if (strcmp (s, ".lit8") == 0) | |
8990 | { | |
0aa27725 | 8991 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 8992 | { |
67c0d1eb | 8993 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8994 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8995 | break; |
252b5132 | 8996 | } |
c9914766 | 8997 | breg = mips_gp_register; |
252b5132 RH |
8998 | r = BFD_RELOC_MIPS_LITERAL; |
8999 | goto dob; | |
9000 | } | |
9001 | else | |
9002 | { | |
9c2799c2 | 9003 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9004 | used_at = 1; |
0a44bf69 | 9005 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9006 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9007 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9008 | else |
9009 | { | |
9010 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9011 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9012 | } |
bdaaa2e1 | 9013 | |
0aa27725 | 9014 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9015 | { |
67c0d1eb RS |
9016 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9017 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9018 | break; |
9019 | } | |
9020 | breg = AT; | |
9021 | r = BFD_RELOC_LO16; | |
9022 | goto dob; | |
9023 | } | |
9024 | ||
9025 | case M_L_DOB: | |
252b5132 RH |
9026 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9027 | to adjust when loading from memory. */ | |
9028 | r = BFD_RELOC_LO16; | |
9029 | dob: | |
df58fc94 | 9030 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9031 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9032 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9033 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9034 | /* FIXME: A possible overflow which I don't know how to deal |
9035 | with. */ | |
9036 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9037 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9038 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9039 | break; |
9040 | ||
c4a68bea | 9041 | case M_S_DOB: |
df58fc94 | 9042 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9043 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9044 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9045 | to adjust when storing to memory. */ | |
9046 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9047 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9048 | offset_expr.X_add_number += 4; | |
9049 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9050 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9051 | break; | |
9052 | ||
252b5132 | 9053 | case M_L_DAB: |
df58fc94 | 9054 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9055 | /* |
9056 | * The MIPS assembler seems to check for X_add_number not | |
9057 | * being double aligned and generating: | |
9058 | * lui at,%hi(foo+1) | |
9059 | * addu at,at,v1 | |
9060 | * addiu at,at,%lo(foo+1) | |
9061 | * lwc1 f2,0(at) | |
9062 | * lwc1 f3,4(at) | |
9063 | * But, the resulting address is the same after relocation so why | |
9064 | * generate the extra instruction? | |
9065 | */ | |
bdaaa2e1 | 9066 | /* Itbl support may require additional care here. */ |
252b5132 | 9067 | coproc = 1; |
df58fc94 | 9068 | fmt = "T,o(b)"; |
0aa27725 | 9069 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9070 | { |
9071 | s = "ldc1"; | |
df58fc94 | 9072 | goto ld_st; |
252b5132 | 9073 | } |
252b5132 | 9074 | s = "lwc1"; |
252b5132 RH |
9075 | goto ldd_std; |
9076 | ||
9077 | case M_S_DAB: | |
df58fc94 RS |
9078 | gas_assert (!mips_opts.micromips); |
9079 | /* Itbl support may require additional care here. */ | |
9080 | coproc = 1; | |
9081 | fmt = "T,o(b)"; | |
0aa27725 | 9082 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9083 | { |
9084 | s = "sdc1"; | |
df58fc94 | 9085 | goto ld_st; |
252b5132 | 9086 | } |
252b5132 | 9087 | s = "swc1"; |
252b5132 RH |
9088 | goto ldd_std; |
9089 | ||
e407c74b NC |
9090 | case M_LQ_AB: |
9091 | fmt = "t,o(b)"; | |
9092 | s = "lq"; | |
9093 | goto ld; | |
9094 | ||
9095 | case M_SQ_AB: | |
9096 | fmt = "t,o(b)"; | |
9097 | s = "sq"; | |
9098 | goto ld_st; | |
9099 | ||
252b5132 | 9100 | case M_LD_AB: |
df58fc94 | 9101 | fmt = "t,o(b)"; |
ca4e0257 | 9102 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9103 | { |
9104 | s = "ld"; | |
9105 | goto ld; | |
9106 | } | |
252b5132 | 9107 | s = "lw"; |
252b5132 RH |
9108 | goto ldd_std; |
9109 | ||
9110 | case M_SD_AB: | |
df58fc94 | 9111 | fmt = "t,o(b)"; |
ca4e0257 | 9112 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9113 | { |
9114 | s = "sd"; | |
df58fc94 | 9115 | goto ld_st; |
252b5132 | 9116 | } |
252b5132 | 9117 | s = "sw"; |
252b5132 RH |
9118 | |
9119 | ldd_std: | |
9120 | if (offset_expr.X_op != O_symbol | |
9121 | && offset_expr.X_op != O_constant) | |
9122 | { | |
f71d0d44 | 9123 | as_bad (_("Expression too complex")); |
252b5132 RH |
9124 | offset_expr.X_op = O_constant; |
9125 | } | |
9126 | ||
2051e8c4 MR |
9127 | if (HAVE_32BIT_ADDRESSES |
9128 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9129 | { |
9130 | char value [32]; | |
9131 | ||
9132 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9133 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9134 | } |
2051e8c4 | 9135 | |
252b5132 RH |
9136 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9137 | to adjust when loading from memory. We set coproc if we must | |
9138 | load $fn+1 first. */ | |
bdaaa2e1 | 9139 | /* Itbl support may require additional care here. */ |
90ecf173 | 9140 | if (!target_big_endian) |
252b5132 RH |
9141 | coproc = 0; |
9142 | ||
90ecf173 | 9143 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9144 | { |
9145 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9146 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9147 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9148 | If we have a base register, we use this |
9149 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9150 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9151 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9152 | If this is not a GP relative symbol, we want |
9153 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9154 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9155 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9156 | If there is a base register, we add it to $at after the | |
9157 | lui instruction. If there is a constant, we always use | |
9158 | the last case. */ | |
39a59cf8 MR |
9159 | if (offset_expr.X_op == O_symbol |
9160 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9161 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9162 | { |
4d7206a2 | 9163 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9164 | if (breg == 0) |
9165 | { | |
c9914766 | 9166 | tempreg = mips_gp_register; |
252b5132 RH |
9167 | } |
9168 | else | |
9169 | { | |
67c0d1eb | 9170 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9171 | AT, breg, mips_gp_register); |
252b5132 | 9172 | tempreg = AT; |
252b5132 RH |
9173 | used_at = 1; |
9174 | } | |
9175 | ||
beae10d5 | 9176 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9177 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9178 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9179 | offset_expr.X_add_number += 4; |
9180 | ||
9181 | /* Set mips_optimize to 2 to avoid inserting an | |
9182 | undesired nop. */ | |
9183 | hold_mips_optimize = mips_optimize; | |
9184 | mips_optimize = 2; | |
beae10d5 | 9185 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9186 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9187 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9188 | mips_optimize = hold_mips_optimize; |
9189 | ||
4d7206a2 | 9190 | relax_switch (); |
252b5132 | 9191 | |
0970e49e | 9192 | offset_expr.X_add_number -= 4; |
252b5132 | 9193 | } |
8fc2e39e | 9194 | used_at = 1; |
67c0d1eb | 9195 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9196 | if (breg != 0) |
67c0d1eb | 9197 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9198 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9199 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9200 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9201 | /* FIXME: How do we handle overflow here? */ |
9202 | offset_expr.X_add_number += 4; | |
beae10d5 | 9203 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9204 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9205 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9206 | if (mips_relax.sequence) |
9207 | relax_end (); | |
bdaaa2e1 | 9208 | } |
0a44bf69 | 9209 | else if (!mips_big_got) |
252b5132 | 9210 | { |
252b5132 RH |
9211 | /* If this is a reference to an external symbol, we want |
9212 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9213 | nop | |
9214 | <op> $treg,0($at) | |
9215 | <op> $treg+1,4($at) | |
9216 | Otherwise we want | |
9217 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9218 | nop | |
9219 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9220 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9221 | If there is a base register we add it to $at before the | |
9222 | lwc1 instructions. If there is a constant we include it | |
9223 | in the lwc1 instructions. */ | |
9224 | used_at = 1; | |
9225 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9226 | if (expr1.X_add_number < -0x8000 |
9227 | || expr1.X_add_number >= 0x8000 - 4) | |
9228 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9229 | load_got_offset (AT, &offset_expr); |
269137b2 | 9230 | load_delay_nop (); |
252b5132 | 9231 | if (breg != 0) |
67c0d1eb | 9232 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9233 | |
9234 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9235 | nop. */ | |
9236 | hold_mips_optimize = mips_optimize; | |
9237 | mips_optimize = 2; | |
4d7206a2 | 9238 | |
beae10d5 | 9239 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9240 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9241 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9242 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9243 | expr1.X_add_number += 4; |
67c0d1eb RS |
9244 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9245 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9246 | relax_switch (); |
67c0d1eb RS |
9247 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9248 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9249 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9250 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9251 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9252 | relax_end (); |
252b5132 | 9253 | |
4d7206a2 | 9254 | mips_optimize = hold_mips_optimize; |
252b5132 | 9255 | } |
0a44bf69 | 9256 | else if (mips_big_got) |
252b5132 | 9257 | { |
67c0d1eb | 9258 | int gpdelay; |
252b5132 RH |
9259 | |
9260 | /* If this is a reference to an external symbol, we want | |
9261 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9262 | addu $at,$at,$gp | |
9263 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9264 | nop | |
9265 | <op> $treg,0($at) | |
9266 | <op> $treg+1,4($at) | |
9267 | Otherwise we want | |
9268 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9269 | nop | |
9270 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9271 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9272 | If there is a base register we add it to $at before the | |
9273 | lwc1 instructions. If there is a constant we include it | |
9274 | in the lwc1 instructions. */ | |
9275 | used_at = 1; | |
9276 | expr1.X_add_number = offset_expr.X_add_number; | |
9277 | offset_expr.X_add_number = 0; | |
9278 | if (expr1.X_add_number < -0x8000 | |
9279 | || expr1.X_add_number >= 0x8000 - 4) | |
9280 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9281 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9282 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9283 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9284 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9285 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9286 | AT, AT, mips_gp_register); |
67c0d1eb | 9287 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9288 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9289 | load_delay_nop (); |
252b5132 | 9290 | if (breg != 0) |
67c0d1eb | 9291 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9292 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9293 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9294 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9295 | expr1.X_add_number += 4; |
9296 | ||
9297 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9298 | nop. */ | |
9299 | hold_mips_optimize = mips_optimize; | |
9300 | mips_optimize = 2; | |
beae10d5 | 9301 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9302 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9303 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9304 | mips_optimize = hold_mips_optimize; |
9305 | expr1.X_add_number -= 4; | |
9306 | ||
4d7206a2 RS |
9307 | relax_switch (); |
9308 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9309 | if (gpdelay) |
9310 | macro_build (NULL, "nop", ""); | |
9311 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9312 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9313 | load_delay_nop (); |
252b5132 | 9314 | if (breg != 0) |
67c0d1eb | 9315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9316 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9317 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9318 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9319 | offset_expr.X_add_number += 4; |
252b5132 RH |
9320 | |
9321 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9322 | nop. */ | |
9323 | hold_mips_optimize = mips_optimize; | |
9324 | mips_optimize = 2; | |
beae10d5 | 9325 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9326 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9327 | BFD_RELOC_LO16, AT); | |
252b5132 | 9328 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9329 | relax_end (); |
252b5132 | 9330 | } |
252b5132 RH |
9331 | else |
9332 | abort (); | |
9333 | ||
252b5132 RH |
9334 | break; |
9335 | ||
9336 | case M_LD_OB: | |
704897fb | 9337 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9338 | goto sd_ob; |
9339 | case M_SD_OB: | |
704897fb | 9340 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9341 | sd_ob: |
4614d845 MR |
9342 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9343 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9344 | breg); | |
704897fb MR |
9345 | if (!HAVE_64BIT_GPRS) |
9346 | { | |
9347 | offset_expr.X_add_number += 4; | |
9348 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9349 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9350 | breg); | |
704897fb | 9351 | } |
8fc2e39e | 9352 | break; |
252b5132 | 9353 | |
dd6a37e7 AP |
9354 | |
9355 | case M_SAA_AB: | |
9356 | ab = 1; | |
9357 | case M_SAA_OB: | |
9358 | s = "saa"; | |
9359 | off0 = 1; | |
9360 | fmt = "t,(b)"; | |
9361 | goto ld_st; | |
9362 | case M_SAAD_AB: | |
9363 | ab = 1; | |
9364 | case M_SAAD_OB: | |
9365 | s = "saad"; | |
9366 | off0 = 1; | |
9367 | fmt = "t,(b)"; | |
9368 | goto ld_st; | |
9369 | ||
252b5132 RH |
9370 | /* New code added to support COPZ instructions. |
9371 | This code builds table entries out of the macros in mip_opcodes. | |
9372 | R4000 uses interlocks to handle coproc delays. | |
9373 | Other chips (like the R3000) require nops to be inserted for delays. | |
9374 | ||
f72c8c98 | 9375 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9376 | In order to fill delay slots for non-interlocked chips, |
9377 | we must have a way to specify delays based on the coprocessor. | |
9378 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9379 | What are the side-effects of the cop instruction? | |
9380 | What cache support might we have and what are its effects? | |
9381 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9382 | What registers are read/set/modified? |
252b5132 RH |
9383 | |
9384 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9385 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9386 | |
9387 | case M_COP0: | |
9388 | s = "c0"; | |
9389 | goto copz; | |
9390 | case M_COP1: | |
9391 | s = "c1"; | |
9392 | goto copz; | |
9393 | case M_COP2: | |
9394 | s = "c2"; | |
9395 | goto copz; | |
9396 | case M_COP3: | |
9397 | s = "c3"; | |
9398 | copz: | |
df58fc94 | 9399 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9400 | /* For now we just do C (same as Cz). The parameter will be |
9401 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9402 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9403 | break; |
252b5132 | 9404 | |
ea1fb5dc | 9405 | case M_MOVE: |
67c0d1eb | 9406 | move_register (dreg, sreg); |
8fc2e39e | 9407 | break; |
ea1fb5dc | 9408 | |
252b5132 RH |
9409 | case M_DMUL: |
9410 | dbl = 1; | |
9411 | case M_MUL: | |
e407c74b NC |
9412 | if (mips_opts.arch == CPU_R5900) |
9413 | { | |
9414 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9415 | } | |
9416 | else | |
9417 | { | |
67c0d1eb | 9418 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9419 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9420 | } |
8fc2e39e | 9421 | break; |
252b5132 RH |
9422 | |
9423 | case M_DMUL_I: | |
9424 | dbl = 1; | |
9425 | case M_MUL_I: | |
9426 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9427 | not trying to be that fancy. GCC should do this for us | |
9428 | anyway. */ | |
8fc2e39e | 9429 | used_at = 1; |
67c0d1eb RS |
9430 | load_register (AT, &imm_expr, dbl); |
9431 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9432 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9433 | break; |
9434 | ||
9435 | case M_DMULO_I: | |
9436 | dbl = 1; | |
9437 | case M_MULO_I: | |
9438 | imm = 1; | |
9439 | goto do_mulo; | |
9440 | ||
9441 | case M_DMULO: | |
9442 | dbl = 1; | |
9443 | case M_MULO: | |
9444 | do_mulo: | |
7d10b47d | 9445 | start_noreorder (); |
8fc2e39e | 9446 | used_at = 1; |
252b5132 | 9447 | if (imm) |
67c0d1eb RS |
9448 | load_register (AT, &imm_expr, dbl); |
9449 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9450 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9451 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9452 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9453 | if (mips_trap) |
df58fc94 | 9454 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9455 | else |
9456 | { | |
df58fc94 RS |
9457 | if (mips_opts.micromips) |
9458 | micromips_label_expr (&label_expr); | |
9459 | else | |
9460 | label_expr.X_add_number = 8; | |
9461 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9462 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9463 | macro_build (NULL, "break", BRK_FMT, 6); |
9464 | if (mips_opts.micromips) | |
9465 | micromips_add_label (); | |
252b5132 | 9466 | } |
7d10b47d | 9467 | end_noreorder (); |
df58fc94 | 9468 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9469 | break; |
9470 | ||
9471 | case M_DMULOU_I: | |
9472 | dbl = 1; | |
9473 | case M_MULOU_I: | |
9474 | imm = 1; | |
9475 | goto do_mulou; | |
9476 | ||
9477 | case M_DMULOU: | |
9478 | dbl = 1; | |
9479 | case M_MULOU: | |
9480 | do_mulou: | |
7d10b47d | 9481 | start_noreorder (); |
8fc2e39e | 9482 | used_at = 1; |
252b5132 | 9483 | if (imm) |
67c0d1eb RS |
9484 | load_register (AT, &imm_expr, dbl); |
9485 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9486 | sreg, imm ? AT : treg); |
df58fc94 RS |
9487 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9488 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9489 | if (mips_trap) |
df58fc94 | 9490 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9491 | else |
9492 | { | |
df58fc94 RS |
9493 | if (mips_opts.micromips) |
9494 | micromips_label_expr (&label_expr); | |
9495 | else | |
9496 | label_expr.X_add_number = 8; | |
9497 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9498 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9499 | macro_build (NULL, "break", BRK_FMT, 6); |
9500 | if (mips_opts.micromips) | |
9501 | micromips_add_label (); | |
252b5132 | 9502 | } |
7d10b47d | 9503 | end_noreorder (); |
252b5132 RH |
9504 | break; |
9505 | ||
771c7ce4 | 9506 | case M_DROL: |
fef14a42 | 9507 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9508 | { |
9509 | if (dreg == sreg) | |
9510 | { | |
9511 | tempreg = AT; | |
9512 | used_at = 1; | |
9513 | } | |
9514 | else | |
9515 | { | |
9516 | tempreg = dreg; | |
82dd0097 | 9517 | } |
67c0d1eb RS |
9518 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9519 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9520 | break; |
82dd0097 | 9521 | } |
8fc2e39e | 9522 | used_at = 1; |
c80c840e | 9523 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9524 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9525 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9526 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9527 | break; |
9528 | ||
252b5132 | 9529 | case M_ROL: |
fef14a42 | 9530 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9531 | { |
9532 | if (dreg == sreg) | |
9533 | { | |
9534 | tempreg = AT; | |
9535 | used_at = 1; | |
9536 | } | |
9537 | else | |
9538 | { | |
9539 | tempreg = dreg; | |
82dd0097 | 9540 | } |
67c0d1eb RS |
9541 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9542 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9543 | break; |
82dd0097 | 9544 | } |
8fc2e39e | 9545 | used_at = 1; |
c80c840e | 9546 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9547 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9548 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9549 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9550 | break; |
9551 | ||
771c7ce4 TS |
9552 | case M_DROL_I: |
9553 | { | |
9554 | unsigned int rot; | |
91d6fa6a NC |
9555 | char *l; |
9556 | char *rr; | |
771c7ce4 TS |
9557 | |
9558 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9559 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9560 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9561 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9562 | { |
9563 | rot = (64 - rot) & 0x3f; | |
9564 | if (rot >= 32) | |
df58fc94 | 9565 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9566 | else |
df58fc94 | 9567 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9568 | break; |
60b63b72 | 9569 | } |
483fc7cd | 9570 | if (rot == 0) |
483fc7cd | 9571 | { |
df58fc94 | 9572 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9573 | break; |
483fc7cd | 9574 | } |
82dd0097 | 9575 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9576 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9577 | rot &= 0x1f; |
8fc2e39e | 9578 | used_at = 1; |
df58fc94 RS |
9579 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9580 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9581 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9582 | } |
9583 | break; | |
9584 | ||
252b5132 | 9585 | case M_ROL_I: |
771c7ce4 TS |
9586 | { |
9587 | unsigned int rot; | |
9588 | ||
9589 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9590 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9591 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9592 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9593 | { |
df58fc94 | 9594 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9595 | break; |
60b63b72 | 9596 | } |
483fc7cd | 9597 | if (rot == 0) |
483fc7cd | 9598 | { |
df58fc94 | 9599 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9600 | break; |
483fc7cd | 9601 | } |
8fc2e39e | 9602 | used_at = 1; |
df58fc94 RS |
9603 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9604 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9605 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9606 | } |
9607 | break; | |
9608 | ||
9609 | case M_DROR: | |
fef14a42 | 9610 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9611 | { |
67c0d1eb | 9612 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9613 | break; |
82dd0097 | 9614 | } |
8fc2e39e | 9615 | used_at = 1; |
c80c840e | 9616 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9617 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9618 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9619 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9620 | break; |
9621 | ||
9622 | case M_ROR: | |
fef14a42 | 9623 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9624 | { |
67c0d1eb | 9625 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9626 | break; |
82dd0097 | 9627 | } |
8fc2e39e | 9628 | used_at = 1; |
c80c840e | 9629 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9630 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9631 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9632 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9633 | break; |
9634 | ||
771c7ce4 TS |
9635 | case M_DROR_I: |
9636 | { | |
9637 | unsigned int rot; | |
91d6fa6a NC |
9638 | char *l; |
9639 | char *rr; | |
771c7ce4 TS |
9640 | |
9641 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9642 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9643 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9644 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9645 | { |
9646 | if (rot >= 32) | |
df58fc94 | 9647 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9648 | else |
df58fc94 | 9649 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9650 | break; |
82dd0097 | 9651 | } |
483fc7cd | 9652 | if (rot == 0) |
483fc7cd | 9653 | { |
df58fc94 | 9654 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9655 | break; |
483fc7cd | 9656 | } |
91d6fa6a | 9657 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9658 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9659 | rot &= 0x1f; | |
8fc2e39e | 9660 | used_at = 1; |
df58fc94 RS |
9661 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9662 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9663 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9664 | } |
9665 | break; | |
9666 | ||
252b5132 | 9667 | case M_ROR_I: |
771c7ce4 TS |
9668 | { |
9669 | unsigned int rot; | |
9670 | ||
9671 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9672 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9673 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9674 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9675 | { |
df58fc94 | 9676 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9677 | break; |
82dd0097 | 9678 | } |
483fc7cd | 9679 | if (rot == 0) |
483fc7cd | 9680 | { |
df58fc94 | 9681 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9682 | break; |
483fc7cd | 9683 | } |
8fc2e39e | 9684 | used_at = 1; |
df58fc94 RS |
9685 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9686 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9687 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9688 | } |
252b5132 RH |
9689 | break; |
9690 | ||
252b5132 RH |
9691 | case M_SEQ: |
9692 | if (sreg == 0) | |
67c0d1eb | 9693 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9694 | else if (treg == 0) |
67c0d1eb | 9695 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9696 | else |
9697 | { | |
67c0d1eb RS |
9698 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9699 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9700 | } |
8fc2e39e | 9701 | break; |
252b5132 RH |
9702 | |
9703 | case M_SEQ_I: | |
9704 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9705 | { | |
67c0d1eb | 9706 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9707 | break; |
252b5132 RH |
9708 | } |
9709 | if (sreg == 0) | |
9710 | { | |
9711 | as_warn (_("Instruction %s: result is always false"), | |
9712 | ip->insn_mo->name); | |
67c0d1eb | 9713 | move_register (dreg, 0); |
8fc2e39e | 9714 | break; |
252b5132 | 9715 | } |
dd3cbb7e NC |
9716 | if (CPU_HAS_SEQ (mips_opts.arch) |
9717 | && -512 <= imm_expr.X_add_number | |
9718 | && imm_expr.X_add_number < 512) | |
9719 | { | |
9720 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9721 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9722 | break; |
9723 | } | |
252b5132 RH |
9724 | if (imm_expr.X_op == O_constant |
9725 | && imm_expr.X_add_number >= 0 | |
9726 | && imm_expr.X_add_number < 0x10000) | |
9727 | { | |
67c0d1eb | 9728 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9729 | } |
9730 | else if (imm_expr.X_op == O_constant | |
9731 | && imm_expr.X_add_number > -0x8000 | |
9732 | && imm_expr.X_add_number < 0) | |
9733 | { | |
9734 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9735 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9736 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9737 | } |
dd3cbb7e NC |
9738 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9739 | { | |
9740 | used_at = 1; | |
9741 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9742 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9743 | break; | |
9744 | } | |
252b5132 RH |
9745 | else |
9746 | { | |
67c0d1eb RS |
9747 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9748 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9749 | used_at = 1; |
9750 | } | |
67c0d1eb | 9751 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9752 | break; |
252b5132 RH |
9753 | |
9754 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9755 | s = "slt"; | |
9756 | goto sge; | |
9757 | case M_SGEU: | |
9758 | s = "sltu"; | |
9759 | sge: | |
67c0d1eb RS |
9760 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9761 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9762 | break; |
252b5132 RH |
9763 | |
9764 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9765 | case M_SGEU_I: | |
9766 | if (imm_expr.X_op == O_constant | |
9767 | && imm_expr.X_add_number >= -0x8000 | |
9768 | && imm_expr.X_add_number < 0x8000) | |
9769 | { | |
67c0d1eb RS |
9770 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9771 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9772 | } |
9773 | else | |
9774 | { | |
67c0d1eb RS |
9775 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9776 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9777 | dreg, sreg, AT); | |
252b5132 RH |
9778 | used_at = 1; |
9779 | } | |
67c0d1eb | 9780 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9781 | break; |
252b5132 RH |
9782 | |
9783 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9784 | s = "slt"; | |
9785 | goto sgt; | |
9786 | case M_SGTU: | |
9787 | s = "sltu"; | |
9788 | sgt: | |
67c0d1eb | 9789 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9790 | break; |
252b5132 RH |
9791 | |
9792 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9793 | s = "slt"; | |
9794 | goto sgti; | |
9795 | case M_SGTU_I: | |
9796 | s = "sltu"; | |
9797 | sgti: | |
8fc2e39e | 9798 | used_at = 1; |
67c0d1eb RS |
9799 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9800 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9801 | break; |
9802 | ||
2396cfb9 | 9803 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9804 | s = "slt"; |
9805 | goto sle; | |
9806 | case M_SLEU: | |
9807 | s = "sltu"; | |
9808 | sle: | |
67c0d1eb RS |
9809 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9810 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9811 | break; |
252b5132 | 9812 | |
2396cfb9 | 9813 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9814 | s = "slt"; |
9815 | goto slei; | |
9816 | case M_SLEU_I: | |
9817 | s = "sltu"; | |
9818 | slei: | |
8fc2e39e | 9819 | used_at = 1; |
67c0d1eb RS |
9820 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9821 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9822 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9823 | break; |
9824 | ||
9825 | case M_SLT_I: | |
9826 | if (imm_expr.X_op == O_constant | |
9827 | && imm_expr.X_add_number >= -0x8000 | |
9828 | && imm_expr.X_add_number < 0x8000) | |
9829 | { | |
67c0d1eb | 9830 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9831 | break; |
252b5132 | 9832 | } |
8fc2e39e | 9833 | used_at = 1; |
67c0d1eb RS |
9834 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9835 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9836 | break; |
9837 | ||
9838 | case M_SLTU_I: | |
9839 | if (imm_expr.X_op == O_constant | |
9840 | && imm_expr.X_add_number >= -0x8000 | |
9841 | && imm_expr.X_add_number < 0x8000) | |
9842 | { | |
67c0d1eb | 9843 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9844 | BFD_RELOC_LO16); |
8fc2e39e | 9845 | break; |
252b5132 | 9846 | } |
8fc2e39e | 9847 | used_at = 1; |
67c0d1eb RS |
9848 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9849 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9850 | break; |
9851 | ||
9852 | case M_SNE: | |
9853 | if (sreg == 0) | |
67c0d1eb | 9854 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9855 | else if (treg == 0) |
67c0d1eb | 9856 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9857 | else |
9858 | { | |
67c0d1eb RS |
9859 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9860 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9861 | } |
8fc2e39e | 9862 | break; |
252b5132 RH |
9863 | |
9864 | case M_SNE_I: | |
9865 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9866 | { | |
67c0d1eb | 9867 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9868 | break; |
252b5132 RH |
9869 | } |
9870 | if (sreg == 0) | |
9871 | { | |
9872 | as_warn (_("Instruction %s: result is always true"), | |
9873 | ip->insn_mo->name); | |
67c0d1eb RS |
9874 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9875 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9876 | break; |
252b5132 | 9877 | } |
dd3cbb7e NC |
9878 | if (CPU_HAS_SEQ (mips_opts.arch) |
9879 | && -512 <= imm_expr.X_add_number | |
9880 | && imm_expr.X_add_number < 512) | |
9881 | { | |
9882 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9883 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9884 | break; |
9885 | } | |
252b5132 RH |
9886 | if (imm_expr.X_op == O_constant |
9887 | && imm_expr.X_add_number >= 0 | |
9888 | && imm_expr.X_add_number < 0x10000) | |
9889 | { | |
67c0d1eb | 9890 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9891 | } |
9892 | else if (imm_expr.X_op == O_constant | |
9893 | && imm_expr.X_add_number > -0x8000 | |
9894 | && imm_expr.X_add_number < 0) | |
9895 | { | |
9896 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9897 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9898 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9899 | } |
dd3cbb7e NC |
9900 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9901 | { | |
9902 | used_at = 1; | |
9903 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9904 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9905 | break; | |
9906 | } | |
252b5132 RH |
9907 | else |
9908 | { | |
67c0d1eb RS |
9909 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9910 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9911 | used_at = 1; |
9912 | } | |
67c0d1eb | 9913 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9914 | break; |
252b5132 | 9915 | |
df58fc94 RS |
9916 | case M_SUB_I: |
9917 | s = "addi"; | |
9918 | s2 = "sub"; | |
9919 | goto do_subi; | |
9920 | case M_SUBU_I: | |
9921 | s = "addiu"; | |
9922 | s2 = "subu"; | |
9923 | goto do_subi; | |
252b5132 RH |
9924 | case M_DSUB_I: |
9925 | dbl = 1; | |
df58fc94 RS |
9926 | s = "daddi"; |
9927 | s2 = "dsub"; | |
9928 | if (!mips_opts.micromips) | |
9929 | goto do_subi; | |
252b5132 | 9930 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9931 | && imm_expr.X_add_number > -0x200 |
9932 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9933 | { |
df58fc94 | 9934 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9935 | break; |
252b5132 | 9936 | } |
df58fc94 | 9937 | goto do_subi_i; |
252b5132 RH |
9938 | case M_DSUBU_I: |
9939 | dbl = 1; | |
df58fc94 RS |
9940 | s = "daddiu"; |
9941 | s2 = "dsubu"; | |
9942 | do_subi: | |
252b5132 RH |
9943 | if (imm_expr.X_op == O_constant |
9944 | && imm_expr.X_add_number > -0x8000 | |
9945 | && imm_expr.X_add_number <= 0x8000) | |
9946 | { | |
9947 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9948 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9949 | break; |
252b5132 | 9950 | } |
df58fc94 | 9951 | do_subi_i: |
8fc2e39e | 9952 | used_at = 1; |
67c0d1eb | 9953 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9954 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9955 | break; |
9956 | ||
9957 | case M_TEQ_I: | |
9958 | s = "teq"; | |
9959 | goto trap; | |
9960 | case M_TGE_I: | |
9961 | s = "tge"; | |
9962 | goto trap; | |
9963 | case M_TGEU_I: | |
9964 | s = "tgeu"; | |
9965 | goto trap; | |
9966 | case M_TLT_I: | |
9967 | s = "tlt"; | |
9968 | goto trap; | |
9969 | case M_TLTU_I: | |
9970 | s = "tltu"; | |
9971 | goto trap; | |
9972 | case M_TNE_I: | |
9973 | s = "tne"; | |
9974 | trap: | |
8fc2e39e | 9975 | used_at = 1; |
67c0d1eb RS |
9976 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9977 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9978 | break; |
9979 | ||
252b5132 | 9980 | case M_TRUNCWS: |
43841e91 | 9981 | case M_TRUNCWD: |
df58fc94 | 9982 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9983 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9984 | used_at = 1; |
252b5132 RH |
9985 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9986 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9987 | ||
9988 | /* | |
9989 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9990 | * or is there a reason for it? | |
9991 | */ | |
7d10b47d | 9992 | start_noreorder (); |
67c0d1eb RS |
9993 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9994 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9995 | macro_build (NULL, "nop", ""); | |
252b5132 | 9996 | expr1.X_add_number = 3; |
67c0d1eb | 9997 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9998 | expr1.X_add_number = 2; |
67c0d1eb RS |
9999 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10000 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10001 | macro_build (NULL, "nop", ""); | |
10002 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10003 | dreg, sreg); | |
10004 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10005 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10006 | end_noreorder (); |
252b5132 RH |
10007 | break; |
10008 | ||
df58fc94 RS |
10009 | case M_ULH_A: |
10010 | ab = 1; | |
252b5132 RH |
10011 | case M_ULH: |
10012 | s = "lb"; | |
df58fc94 RS |
10013 | s2 = "lbu"; |
10014 | off = 1; | |
10015 | goto uld_st; | |
10016 | case M_ULHU_A: | |
10017 | ab = 1; | |
252b5132 RH |
10018 | case M_ULHU: |
10019 | s = "lbu"; | |
df58fc94 RS |
10020 | s2 = "lbu"; |
10021 | off = 1; | |
10022 | goto uld_st; | |
10023 | case M_ULW_A: | |
10024 | ab = 1; | |
10025 | case M_ULW: | |
10026 | s = "lwl"; | |
10027 | s2 = "lwr"; | |
10028 | off12 = mips_opts.micromips; | |
10029 | off = 3; | |
10030 | goto uld_st; | |
10031 | case M_ULD_A: | |
10032 | ab = 1; | |
252b5132 RH |
10033 | case M_ULD: |
10034 | s = "ldl"; | |
10035 | s2 = "ldr"; | |
df58fc94 | 10036 | off12 = mips_opts.micromips; |
252b5132 | 10037 | off = 7; |
df58fc94 RS |
10038 | goto uld_st; |
10039 | case M_USH_A: | |
10040 | ab = 1; | |
10041 | case M_USH: | |
10042 | s = "sb"; | |
10043 | s2 = "sb"; | |
10044 | off = 1; | |
10045 | ust = 1; | |
10046 | goto uld_st; | |
10047 | case M_USW_A: | |
10048 | ab = 1; | |
10049 | case M_USW: | |
10050 | s = "swl"; | |
10051 | s2 = "swr"; | |
10052 | off12 = mips_opts.micromips; | |
252b5132 | 10053 | off = 3; |
df58fc94 RS |
10054 | ust = 1; |
10055 | goto uld_st; | |
10056 | case M_USD_A: | |
10057 | ab = 1; | |
10058 | case M_USD: | |
10059 | s = "sdl"; | |
10060 | s2 = "sdr"; | |
10061 | off12 = mips_opts.micromips; | |
10062 | off = 7; | |
10063 | ust = 1; | |
10064 | ||
10065 | uld_st: | |
10066 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10067 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10068 | |
10069 | ep = &offset_expr; | |
10070 | expr1.X_add_number = 0; | |
10071 | if (ab) | |
10072 | { | |
10073 | used_at = 1; | |
10074 | tempreg = AT; | |
10075 | load_address (tempreg, ep, &used_at); | |
10076 | if (breg != 0) | |
10077 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10078 | tempreg, tempreg, breg); | |
10079 | breg = tempreg; | |
10080 | tempreg = treg; | |
10081 | ep = &expr1; | |
10082 | } | |
10083 | else if (off12 | |
10084 | && (offset_expr.X_op != O_constant | |
10085 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10086 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10087 | { | |
10088 | used_at = 1; | |
10089 | tempreg = AT; | |
10090 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10091 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10092 | breg = tempreg; | |
10093 | tempreg = treg; | |
10094 | ep = &expr1; | |
10095 | } | |
10096 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10097 | { |
10098 | used_at = 1; | |
10099 | tempreg = AT; | |
10100 | } | |
252b5132 | 10101 | else |
df58fc94 | 10102 | tempreg = treg; |
af22f5b2 | 10103 | |
df58fc94 RS |
10104 | if (off == 1) |
10105 | goto ulh_sh; | |
252b5132 | 10106 | |
90ecf173 | 10107 | if (!target_big_endian) |
df58fc94 RS |
10108 | ep->X_add_number += off; |
10109 | if (!off12) | |
10110 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10111 | else |
df58fc94 RS |
10112 | macro_build (NULL, s, "t,~(b)", |
10113 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10114 | ||
90ecf173 | 10115 | if (!target_big_endian) |
df58fc94 | 10116 | ep->X_add_number -= off; |
252b5132 | 10117 | else |
df58fc94 RS |
10118 | ep->X_add_number += off; |
10119 | if (!off12) | |
10120 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10121 | else | |
10122 | macro_build (NULL, s2, "t,~(b)", | |
10123 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10124 | |
df58fc94 RS |
10125 | /* If necessary, move the result in tempreg to the final destination. */ |
10126 | if (!ust && treg != tempreg) | |
10127 | { | |
10128 | /* Protect second load's delay slot. */ | |
10129 | load_delay_nop (); | |
10130 | move_register (treg, tempreg); | |
10131 | } | |
8fc2e39e | 10132 | break; |
252b5132 | 10133 | |
df58fc94 | 10134 | ulh_sh: |
d6bc6245 | 10135 | used_at = 1; |
df58fc94 RS |
10136 | if (target_big_endian == ust) |
10137 | ep->X_add_number += off; | |
10138 | tempreg = ust || ab ? treg : AT; | |
10139 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10140 | ||
10141 | /* For halfword transfers we need a temporary register to shuffle | |
10142 | bytes. Unfortunately for M_USH_A we have none available before | |
10143 | the next store as AT holds the base address. We deal with this | |
10144 | case by clobbering TREG and then restoring it as with ULH. */ | |
10145 | tempreg = ust == ab ? treg : AT; | |
10146 | if (ust) | |
10147 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10148 | ||
10149 | if (target_big_endian == ust) | |
10150 | ep->X_add_number -= off; | |
252b5132 | 10151 | else |
df58fc94 RS |
10152 | ep->X_add_number += off; |
10153 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10154 | |
df58fc94 RS |
10155 | /* For M_USH_A re-retrieve the LSB. */ |
10156 | if (ust && ab) | |
10157 | { | |
10158 | if (target_big_endian) | |
10159 | ep->X_add_number += off; | |
10160 | else | |
10161 | ep->X_add_number -= off; | |
10162 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10163 | } | |
10164 | /* For ULH and M_USH_A OR the LSB in. */ | |
10165 | if (!ust || ab) | |
10166 | { | |
10167 | tempreg = !ab ? AT : treg; | |
10168 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10169 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10170 | } | |
252b5132 RH |
10171 | break; |
10172 | ||
10173 | default: | |
10174 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10175 | are added dynamically. */ |
252b5132 RH |
10176 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10177 | break; | |
10178 | } | |
741fe287 | 10179 | if (!mips_opts.at && used_at) |
8fc2e39e | 10180 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10181 | } |
10182 | ||
10183 | /* Implement macros in mips16 mode. */ | |
10184 | ||
10185 | static void | |
17a2f251 | 10186 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10187 | { |
10188 | int mask; | |
10189 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10190 | expressionS expr1; |
10191 | int dbl; | |
10192 | const char *s, *s2, *s3; | |
10193 | ||
10194 | mask = ip->insn_mo->mask; | |
10195 | ||
bf12938e RS |
10196 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10197 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10198 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10199 | |
252b5132 RH |
10200 | expr1.X_op = O_constant; |
10201 | expr1.X_op_symbol = NULL; | |
10202 | expr1.X_add_symbol = NULL; | |
10203 | expr1.X_add_number = 1; | |
10204 | ||
10205 | dbl = 0; | |
10206 | ||
10207 | switch (mask) | |
10208 | { | |
10209 | default: | |
b37df7c4 | 10210 | abort (); |
252b5132 RH |
10211 | |
10212 | case M_DDIV_3: | |
10213 | dbl = 1; | |
10214 | case M_DIV_3: | |
10215 | s = "mflo"; | |
10216 | goto do_div3; | |
10217 | case M_DREM_3: | |
10218 | dbl = 1; | |
10219 | case M_REM_3: | |
10220 | s = "mfhi"; | |
10221 | do_div3: | |
7d10b47d | 10222 | start_noreorder (); |
67c0d1eb | 10223 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10224 | expr1.X_add_number = 2; |
67c0d1eb RS |
10225 | macro_build (&expr1, "bnez", "x,p", yreg); |
10226 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10227 | |
252b5132 RH |
10228 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10229 | since that causes an overflow. We should do that as well, | |
10230 | but I don't see how to do the comparisons without a temporary | |
10231 | register. */ | |
7d10b47d | 10232 | end_noreorder (); |
67c0d1eb | 10233 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10234 | break; |
10235 | ||
10236 | case M_DIVU_3: | |
10237 | s = "divu"; | |
10238 | s2 = "mflo"; | |
10239 | goto do_divu3; | |
10240 | case M_REMU_3: | |
10241 | s = "divu"; | |
10242 | s2 = "mfhi"; | |
10243 | goto do_divu3; | |
10244 | case M_DDIVU_3: | |
10245 | s = "ddivu"; | |
10246 | s2 = "mflo"; | |
10247 | goto do_divu3; | |
10248 | case M_DREMU_3: | |
10249 | s = "ddivu"; | |
10250 | s2 = "mfhi"; | |
10251 | do_divu3: | |
7d10b47d | 10252 | start_noreorder (); |
67c0d1eb | 10253 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10254 | expr1.X_add_number = 2; |
67c0d1eb RS |
10255 | macro_build (&expr1, "bnez", "x,p", yreg); |
10256 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10257 | end_noreorder (); |
67c0d1eb | 10258 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10259 | break; |
10260 | ||
10261 | case M_DMUL: | |
10262 | dbl = 1; | |
10263 | case M_MUL: | |
67c0d1eb RS |
10264 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10265 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10266 | break; |
252b5132 RH |
10267 | |
10268 | case M_DSUBU_I: | |
10269 | dbl = 1; | |
10270 | goto do_subu; | |
10271 | case M_SUBU_I: | |
10272 | do_subu: | |
10273 | if (imm_expr.X_op != O_constant) | |
10274 | as_bad (_("Unsupported large constant")); | |
10275 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10276 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10277 | break; |
10278 | ||
10279 | case M_SUBU_I_2: | |
10280 | if (imm_expr.X_op != O_constant) | |
10281 | as_bad (_("Unsupported large constant")); | |
10282 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10283 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10284 | break; |
10285 | ||
10286 | case M_DSUBU_I_2: | |
10287 | if (imm_expr.X_op != O_constant) | |
10288 | as_bad (_("Unsupported large constant")); | |
10289 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10290 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10291 | break; |
10292 | ||
10293 | case M_BEQ: | |
10294 | s = "cmp"; | |
10295 | s2 = "bteqz"; | |
10296 | goto do_branch; | |
10297 | case M_BNE: | |
10298 | s = "cmp"; | |
10299 | s2 = "btnez"; | |
10300 | goto do_branch; | |
10301 | case M_BLT: | |
10302 | s = "slt"; | |
10303 | s2 = "btnez"; | |
10304 | goto do_branch; | |
10305 | case M_BLTU: | |
10306 | s = "sltu"; | |
10307 | s2 = "btnez"; | |
10308 | goto do_branch; | |
10309 | case M_BLE: | |
10310 | s = "slt"; | |
10311 | s2 = "bteqz"; | |
10312 | goto do_reverse_branch; | |
10313 | case M_BLEU: | |
10314 | s = "sltu"; | |
10315 | s2 = "bteqz"; | |
10316 | goto do_reverse_branch; | |
10317 | case M_BGE: | |
10318 | s = "slt"; | |
10319 | s2 = "bteqz"; | |
10320 | goto do_branch; | |
10321 | case M_BGEU: | |
10322 | s = "sltu"; | |
10323 | s2 = "bteqz"; | |
10324 | goto do_branch; | |
10325 | case M_BGT: | |
10326 | s = "slt"; | |
10327 | s2 = "btnez"; | |
10328 | goto do_reverse_branch; | |
10329 | case M_BGTU: | |
10330 | s = "sltu"; | |
10331 | s2 = "btnez"; | |
10332 | ||
10333 | do_reverse_branch: | |
10334 | tmp = xreg; | |
10335 | xreg = yreg; | |
10336 | yreg = tmp; | |
10337 | ||
10338 | do_branch: | |
67c0d1eb RS |
10339 | macro_build (NULL, s, "x,y", xreg, yreg); |
10340 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10341 | break; |
10342 | ||
10343 | case M_BEQ_I: | |
10344 | s = "cmpi"; | |
10345 | s2 = "bteqz"; | |
10346 | s3 = "x,U"; | |
10347 | goto do_branch_i; | |
10348 | case M_BNE_I: | |
10349 | s = "cmpi"; | |
10350 | s2 = "btnez"; | |
10351 | s3 = "x,U"; | |
10352 | goto do_branch_i; | |
10353 | case M_BLT_I: | |
10354 | s = "slti"; | |
10355 | s2 = "btnez"; | |
10356 | s3 = "x,8"; | |
10357 | goto do_branch_i; | |
10358 | case M_BLTU_I: | |
10359 | s = "sltiu"; | |
10360 | s2 = "btnez"; | |
10361 | s3 = "x,8"; | |
10362 | goto do_branch_i; | |
10363 | case M_BLE_I: | |
10364 | s = "slti"; | |
10365 | s2 = "btnez"; | |
10366 | s3 = "x,8"; | |
10367 | goto do_addone_branch_i; | |
10368 | case M_BLEU_I: | |
10369 | s = "sltiu"; | |
10370 | s2 = "btnez"; | |
10371 | s3 = "x,8"; | |
10372 | goto do_addone_branch_i; | |
10373 | case M_BGE_I: | |
10374 | s = "slti"; | |
10375 | s2 = "bteqz"; | |
10376 | s3 = "x,8"; | |
10377 | goto do_branch_i; | |
10378 | case M_BGEU_I: | |
10379 | s = "sltiu"; | |
10380 | s2 = "bteqz"; | |
10381 | s3 = "x,8"; | |
10382 | goto do_branch_i; | |
10383 | case M_BGT_I: | |
10384 | s = "slti"; | |
10385 | s2 = "bteqz"; | |
10386 | s3 = "x,8"; | |
10387 | goto do_addone_branch_i; | |
10388 | case M_BGTU_I: | |
10389 | s = "sltiu"; | |
10390 | s2 = "bteqz"; | |
10391 | s3 = "x,8"; | |
10392 | ||
10393 | do_addone_branch_i: | |
10394 | if (imm_expr.X_op != O_constant) | |
10395 | as_bad (_("Unsupported large constant")); | |
10396 | ++imm_expr.X_add_number; | |
10397 | ||
10398 | do_branch_i: | |
67c0d1eb RS |
10399 | macro_build (&imm_expr, s, s3, xreg); |
10400 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10401 | break; |
10402 | ||
10403 | case M_ABS: | |
10404 | expr1.X_add_number = 0; | |
67c0d1eb | 10405 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10406 | if (xreg != yreg) |
67c0d1eb | 10407 | move_register (xreg, yreg); |
252b5132 | 10408 | expr1.X_add_number = 2; |
67c0d1eb RS |
10409 | macro_build (&expr1, "bteqz", "p"); |
10410 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10411 | } |
10412 | } | |
10413 | ||
10414 | /* For consistency checking, verify that all bits are specified either | |
10415 | by the match/mask part of the instruction definition, or by the | |
10416 | operand list. */ | |
10417 | static int | |
17a2f251 | 10418 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10419 | { |
10420 | const char *p = opc->args; | |
10421 | char c; | |
10422 | unsigned long used_bits = opc->mask; | |
10423 | ||
10424 | if ((used_bits & opc->match) != opc->match) | |
10425 | { | |
10426 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10427 | opc->name, opc->args); | |
10428 | return 0; | |
10429 | } | |
10430 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10431 | while (*p) | |
10432 | switch (c = *p++) | |
10433 | { | |
10434 | case ',': break; | |
10435 | case '(': break; | |
10436 | case ')': break; | |
af7ee8bf CD |
10437 | case '+': |
10438 | switch (c = *p++) | |
10439 | { | |
9bcd4f99 TS |
10440 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10441 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10442 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10443 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10444 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10445 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10446 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10447 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10448 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10449 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10450 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10451 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10452 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10453 | case 'I': break; | |
b015e599 | 10454 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10455 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10456 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10457 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10458 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10459 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10460 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10461 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10462 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10463 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10464 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10465 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10466 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10467 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10468 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10469 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10470 | |
af7ee8bf CD |
10471 | default: |
10472 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10473 | c, opc->name, opc->args); | |
10474 | return 0; | |
10475 | } | |
10476 | break; | |
252b5132 RH |
10477 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10478 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10479 | case 'A': break; | |
4372b673 | 10480 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10481 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10482 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10483 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10484 | case 'F': break; | |
10485 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10486 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10487 | case 'I': break; |
e972090a | 10488 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10489 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10490 | case 'L': break; |
10491 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10492 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10493 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10494 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10495 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10496 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10497 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10498 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10499 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10500 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10501 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10502 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10503 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10504 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10505 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10506 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10507 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10508 | case 'f': break; | |
10509 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10510 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10511 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10512 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10513 | case 'l': break; | |
10514 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10515 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10516 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10517 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10518 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10519 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10520 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10521 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10522 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10523 | case 'x': break; | |
10524 | case 'z': break; | |
10525 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10526 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10527 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10528 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10529 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10530 | case '[': break; | |
10531 | case ']': break; | |
620edafd | 10532 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10533 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10534 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10535 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10536 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10537 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10538 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10539 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10540 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10541 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10542 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10543 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10544 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10545 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10546 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10547 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10548 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10549 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10550 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10551 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10552 | default: |
10553 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10554 | c, opc->name, opc->args); | |
10555 | return 0; | |
10556 | } | |
10557 | #undef USE_BITS | |
10558 | if (used_bits != 0xffffffff) | |
10559 | { | |
10560 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10561 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10562 | return 0; | |
10563 | } | |
10564 | return 1; | |
10565 | } | |
10566 | ||
df58fc94 RS |
10567 | /* For consistency checking, verify that the length implied matches the |
10568 | major opcode and that all bits are specified either by the match/mask | |
10569 | part of the instruction definition, or by the operand list. */ | |
10570 | ||
10571 | static int | |
10572 | validate_micromips_insn (const struct mips_opcode *opc) | |
10573 | { | |
10574 | unsigned long match = opc->match; | |
10575 | unsigned long mask = opc->mask; | |
10576 | const char *p = opc->args; | |
10577 | unsigned long insn_bits; | |
10578 | unsigned long used_bits; | |
10579 | unsigned long major; | |
10580 | unsigned int length; | |
10581 | char e; | |
10582 | char c; | |
10583 | ||
10584 | if ((mask & match) != match) | |
10585 | { | |
10586 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10587 | opc->name, opc->args); | |
10588 | return 0; | |
10589 | } | |
10590 | length = micromips_insn_length (opc); | |
10591 | if (length != 2 && length != 4) | |
10592 | { | |
10593 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10594 | "%s %s"), length, opc->name, opc->args); | |
10595 | return 0; | |
10596 | } | |
10597 | major = match >> (10 + 8 * (length - 2)); | |
10598 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10599 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10600 | { | |
10601 | as_bad (_("Internal error: bad microMIPS opcode " | |
10602 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10603 | return 0; | |
10604 | } | |
10605 | ||
10606 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10607 | insn_bits = 1 << 4 * length; | |
10608 | insn_bits <<= 4 * length; | |
10609 | insn_bits -= 1; | |
10610 | used_bits = mask; | |
10611 | #define USE_BITS(field) \ | |
10612 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10613 | while (*p) | |
10614 | switch (c = *p++) | |
10615 | { | |
10616 | case ',': break; | |
10617 | case '(': break; | |
10618 | case ')': break; | |
10619 | case '+': | |
10620 | e = c; | |
10621 | switch (c = *p++) | |
10622 | { | |
10623 | case 'A': USE_BITS (EXTLSB); break; | |
10624 | case 'B': USE_BITS (INSMSB); break; | |
10625 | case 'C': USE_BITS (EXTMSBD); break; | |
10626 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10627 | case 'E': USE_BITS (EXTLSB); break; | |
10628 | case 'F': USE_BITS (INSMSB); break; | |
10629 | case 'G': USE_BITS (EXTMSBD); break; | |
10630 | case 'H': USE_BITS (EXTMSBD); break; | |
10631 | default: | |
10632 | as_bad (_("Internal error: bad mips opcode " | |
10633 | "(unknown extension operand type `%c%c'): %s %s"), | |
10634 | e, c, opc->name, opc->args); | |
10635 | return 0; | |
10636 | } | |
10637 | break; | |
10638 | case 'm': | |
10639 | e = c; | |
10640 | switch (c = *p++) | |
10641 | { | |
10642 | case 'A': USE_BITS (IMMA); break; | |
10643 | case 'B': USE_BITS (IMMB); break; | |
10644 | case 'C': USE_BITS (IMMC); break; | |
10645 | case 'D': USE_BITS (IMMD); break; | |
10646 | case 'E': USE_BITS (IMME); break; | |
10647 | case 'F': USE_BITS (IMMF); break; | |
10648 | case 'G': USE_BITS (IMMG); break; | |
10649 | case 'H': USE_BITS (IMMH); break; | |
10650 | case 'I': USE_BITS (IMMI); break; | |
10651 | case 'J': USE_BITS (IMMJ); break; | |
10652 | case 'L': USE_BITS (IMML); break; | |
10653 | case 'M': USE_BITS (IMMM); break; | |
10654 | case 'N': USE_BITS (IMMN); break; | |
10655 | case 'O': USE_BITS (IMMO); break; | |
10656 | case 'P': USE_BITS (IMMP); break; | |
10657 | case 'Q': USE_BITS (IMMQ); break; | |
10658 | case 'U': USE_BITS (IMMU); break; | |
10659 | case 'W': USE_BITS (IMMW); break; | |
10660 | case 'X': USE_BITS (IMMX); break; | |
10661 | case 'Y': USE_BITS (IMMY); break; | |
10662 | case 'Z': break; | |
10663 | case 'a': break; | |
10664 | case 'b': USE_BITS (MB); break; | |
10665 | case 'c': USE_BITS (MC); break; | |
10666 | case 'd': USE_BITS (MD); break; | |
10667 | case 'e': USE_BITS (ME); break; | |
10668 | case 'f': USE_BITS (MF); break; | |
10669 | case 'g': USE_BITS (MG); break; | |
10670 | case 'h': USE_BITS (MH); break; | |
10671 | case 'i': USE_BITS (MI); break; | |
10672 | case 'j': USE_BITS (MJ); break; | |
10673 | case 'l': USE_BITS (ML); break; | |
10674 | case 'm': USE_BITS (MM); break; | |
10675 | case 'n': USE_BITS (MN); break; | |
10676 | case 'p': USE_BITS (MP); break; | |
10677 | case 'q': USE_BITS (MQ); break; | |
10678 | case 'r': break; | |
10679 | case 's': break; | |
10680 | case 't': break; | |
10681 | case 'x': break; | |
10682 | case 'y': break; | |
10683 | case 'z': break; | |
10684 | default: | |
10685 | as_bad (_("Internal error: bad mips opcode " | |
10686 | "(unknown extension operand type `%c%c'): %s %s"), | |
10687 | e, c, opc->name, opc->args); | |
10688 | return 0; | |
10689 | } | |
10690 | break; | |
10691 | case '.': USE_BITS (OFFSET10); break; | |
10692 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10693 | case '2': USE_BITS (BP); break; |
10694 | case '3': USE_BITS (SA3); break; | |
10695 | case '4': USE_BITS (SA4); break; | |
10696 | case '5': USE_BITS (IMM8); break; | |
10697 | case '6': USE_BITS (RS); break; | |
10698 | case '7': USE_BITS (DSPACC); break; | |
10699 | case '8': USE_BITS (WRDSP); break; | |
10700 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10701 | case '<': USE_BITS (SHAMT); break; |
10702 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10703 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10704 | case 'B': USE_BITS (CODE10); break; |
10705 | case 'C': USE_BITS (COPZ); break; | |
10706 | case 'D': USE_BITS (FD); break; | |
10707 | case 'E': USE_BITS (RT); break; | |
10708 | case 'G': USE_BITS (RS); break; | |
444d75be | 10709 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10710 | case 'K': USE_BITS (RS); break; |
10711 | case 'M': USE_BITS (CCC); break; | |
10712 | case 'N': USE_BITS (BCC); break; | |
10713 | case 'R': USE_BITS (FR); break; | |
10714 | case 'S': USE_BITS (FS); break; | |
10715 | case 'T': USE_BITS (FT); break; | |
10716 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10717 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10718 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10719 | case 'a': USE_BITS (TARGET); break; |
10720 | case 'b': USE_BITS (RS); break; | |
10721 | case 'c': USE_BITS (CODE); break; | |
10722 | case 'd': USE_BITS (RD); break; | |
10723 | case 'h': USE_BITS (PREFX); break; | |
10724 | case 'i': USE_BITS (IMMEDIATE); break; | |
10725 | case 'j': USE_BITS (DELTA); break; | |
10726 | case 'k': USE_BITS (CACHE); break; | |
10727 | case 'n': USE_BITS (RT); break; | |
10728 | case 'o': USE_BITS (DELTA); break; | |
10729 | case 'p': USE_BITS (DELTA); break; | |
10730 | case 'q': USE_BITS (CODE2); break; | |
10731 | case 'r': USE_BITS (RS); break; | |
10732 | case 's': USE_BITS (RS); break; | |
10733 | case 't': USE_BITS (RT); break; | |
10734 | case 'u': USE_BITS (IMMEDIATE); break; | |
10735 | case 'v': USE_BITS (RS); break; | |
10736 | case 'w': USE_BITS (RT); break; | |
10737 | case 'y': USE_BITS (RS3); break; | |
10738 | case 'z': break; | |
10739 | case '|': USE_BITS (TRAP); break; | |
10740 | case '~': USE_BITS (OFFSET12); break; | |
10741 | default: | |
10742 | as_bad (_("Internal error: bad microMIPS opcode " | |
10743 | "(unknown operand type `%c'): %s %s"), | |
10744 | c, opc->name, opc->args); | |
10745 | return 0; | |
10746 | } | |
10747 | #undef USE_BITS | |
10748 | if (used_bits != insn_bits) | |
10749 | { | |
10750 | if (~used_bits & insn_bits) | |
10751 | as_bad (_("Internal error: bad microMIPS opcode " | |
10752 | "(bits 0x%lx undefined): %s %s"), | |
10753 | ~used_bits & insn_bits, opc->name, opc->args); | |
10754 | if (used_bits & ~insn_bits) | |
10755 | as_bad (_("Internal error: bad microMIPS opcode " | |
10756 | "(bits 0x%lx defined): %s %s"), | |
10757 | used_bits & ~insn_bits, opc->name, opc->args); | |
10758 | return 0; | |
10759 | } | |
10760 | return 1; | |
10761 | } | |
10762 | ||
9bcd4f99 TS |
10763 | /* UDI immediates. */ |
10764 | struct mips_immed { | |
10765 | char type; | |
10766 | unsigned int shift; | |
10767 | unsigned long mask; | |
10768 | const char * desc; | |
10769 | }; | |
10770 | ||
10771 | static const struct mips_immed mips_immed[] = { | |
10772 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10773 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10774 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10775 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10776 | { 0,0,0,0 } | |
10777 | }; | |
10778 | ||
7455baf8 TS |
10779 | /* Check whether an odd floating-point register is allowed. */ |
10780 | static int | |
10781 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10782 | { | |
10783 | const char *s = insn->name; | |
10784 | ||
10785 | if (insn->pinfo == INSN_MACRO) | |
10786 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10787 | return 1; | |
10788 | ||
e407c74b | 10789 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10790 | { |
10791 | /* Allow odd registers for single-precision ops. */ | |
10792 | switch (insn->pinfo & (FP_S | FP_D)) | |
10793 | { | |
10794 | case FP_S: | |
10795 | case 0: | |
10796 | return 1; /* both single precision - ok */ | |
10797 | case FP_D: | |
10798 | return 0; /* both double precision - fail */ | |
10799 | default: | |
10800 | break; | |
10801 | } | |
10802 | ||
10803 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10804 | s = strchr (insn->name, '.'); | |
10805 | if (argnum == 2) | |
10806 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10807 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10808 | } | |
10809 | ||
10810 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10811 | if ((insn->pinfo & FP_S) | |
10812 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10813 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10814 | return 1; | |
10815 | ||
10816 | return 0; | |
10817 | } | |
10818 | ||
df58fc94 RS |
10819 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10820 | taking bits from BIT up. */ | |
10821 | static int | |
10822 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10823 | { | |
10824 | return (ep->X_op == O_constant | |
10825 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10826 | && ep->X_add_number >= min << bit | |
10827 | && ep->X_add_number < max << bit); | |
10828 | } | |
10829 | ||
252b5132 RH |
10830 | /* This routine assembles an instruction into its binary format. As a |
10831 | side effect, it sets one of the global variables imm_reloc or | |
10832 | offset_reloc to the type of relocation to do if one of the operands | |
10833 | is an address expression. */ | |
10834 | ||
10835 | static void | |
17a2f251 | 10836 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10837 | { |
df58fc94 RS |
10838 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10839 | bfd_boolean need_delay_slot_ok = TRUE; | |
10840 | struct mips_opcode *firstinsn = NULL; | |
10841 | const struct mips_opcode *past; | |
10842 | struct hash_control *hash; | |
252b5132 RH |
10843 | char *s; |
10844 | const char *args; | |
43841e91 | 10845 | char c = 0; |
252b5132 RH |
10846 | struct mips_opcode *insn; |
10847 | char *argsStart; | |
10848 | unsigned int regno; | |
34224acf | 10849 | unsigned int lastregno; |
df58fc94 | 10850 | unsigned int destregno = 0; |
af7ee8bf | 10851 | unsigned int lastpos = 0; |
071742cf | 10852 | unsigned int limlo, limhi; |
f02d8318 | 10853 | int sizelo; |
252b5132 | 10854 | char *s_reset; |
74cd071d | 10855 | offsetT min_range, max_range; |
df58fc94 | 10856 | long opend; |
a40bc9dd | 10857 | char *name; |
707bfff6 TS |
10858 | int argnum; |
10859 | unsigned int rtype; | |
df58fc94 | 10860 | char *dot; |
a40bc9dd | 10861 | long end; |
252b5132 RH |
10862 | |
10863 | insn_error = NULL; | |
10864 | ||
df58fc94 RS |
10865 | if (mips_opts.micromips) |
10866 | { | |
10867 | hash = micromips_op_hash; | |
10868 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10869 | } | |
10870 | else | |
10871 | { | |
10872 | hash = op_hash; | |
10873 | past = &mips_opcodes[NUMOPCODES]; | |
10874 | } | |
10875 | forced_insn_length = 0; | |
252b5132 | 10876 | insn = NULL; |
252b5132 | 10877 | |
df58fc94 | 10878 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10879 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10880 | continue; | |
bdaaa2e1 | 10881 | |
a40bc9dd RS |
10882 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10883 | name = alloca (end + 1); | |
10884 | memcpy (name, str, end); | |
10885 | name[end] = '\0'; | |
252b5132 | 10886 | |
df58fc94 RS |
10887 | for (;;) |
10888 | { | |
10889 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10890 | ||
10891 | if (insn != NULL || !mips_opts.micromips) | |
10892 | break; | |
10893 | if (forced_insn_length) | |
10894 | break; | |
10895 | ||
10896 | /* See if there's an instruction size override suffix, | |
10897 | either `16' or `32', at the end of the mnemonic proper, | |
10898 | that defines the operation, i.e. before the first `.' | |
10899 | character if any. Strip it and retry. */ | |
10900 | dot = strchr (name, '.'); | |
10901 | opend = dot != NULL ? dot - name : end; | |
10902 | if (opend < 3) | |
10903 | break; | |
10904 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10905 | forced_insn_length = 2; | |
10906 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10907 | forced_insn_length = 4; | |
10908 | else | |
10909 | break; | |
10910 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10911 | } | |
252b5132 RH |
10912 | if (insn == NULL) |
10913 | { | |
a40bc9dd RS |
10914 | insn_error = _("Unrecognized opcode"); |
10915 | return; | |
252b5132 RH |
10916 | } |
10917 | ||
df58fc94 RS |
10918 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10919 | we make up to two passes over the relevant fragment of the opcode | |
10920 | table. First we try instructions that meet the delay slot's length | |
10921 | requirement. If none matched, then we retry with the remaining ones | |
10922 | and if one matches, then we use it and then issue an appropriate | |
10923 | warning later on. */ | |
a40bc9dd | 10924 | argsStart = s = str + end; |
252b5132 RH |
10925 | for (;;) |
10926 | { | |
df58fc94 RS |
10927 | bfd_boolean delay_slot_ok; |
10928 | bfd_boolean size_ok; | |
b34976b6 | 10929 | bfd_boolean ok; |
252b5132 | 10930 | |
a40bc9dd | 10931 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10932 | |
f79e2745 | 10933 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10934 | size_ok = is_size_valid (insn); |
10935 | delay_slot_ok = is_delay_slot_valid (insn); | |
10936 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10937 | { |
df58fc94 RS |
10938 | firstinsn = insn; |
10939 | wrong_delay_slot_insns = TRUE; | |
10940 | } | |
10941 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10942 | { | |
10943 | static char buf[256]; | |
10944 | ||
10945 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10946 | { |
10947 | ++insn; | |
10948 | continue; | |
10949 | } | |
df58fc94 | 10950 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10951 | { |
df58fc94 RS |
10952 | gas_assert (firstinsn); |
10953 | need_delay_slot_ok = FALSE; | |
10954 | past = insn + 1; | |
10955 | insn = firstinsn; | |
10956 | continue; | |
252b5132 | 10957 | } |
df58fc94 RS |
10958 | |
10959 | if (insn_error) | |
10960 | return; | |
10961 | ||
10962 | if (!ok) | |
7bd942df | 10963 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10964 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10965 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10966 | else | |
10967 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10968 | 8 * forced_insn_length); | |
10969 | insn_error = buf; | |
10970 | ||
10971 | return; | |
252b5132 RH |
10972 | } |
10973 | ||
1e915849 | 10974 | create_insn (ip, insn); |
268f6bed | 10975 | insn_error = NULL; |
707bfff6 | 10976 | argnum = 1; |
24864476 | 10977 | lastregno = 0xffffffff; |
252b5132 RH |
10978 | for (args = insn->args;; ++args) |
10979 | { | |
deec1734 CD |
10980 | int is_mdmx; |
10981 | ||
ad8d3bb3 | 10982 | s += strspn (s, " \t"); |
deec1734 | 10983 | is_mdmx = 0; |
252b5132 RH |
10984 | switch (*args) |
10985 | { | |
10986 | case '\0': /* end of args */ | |
10987 | if (*s == '\0') | |
10988 | return; | |
10989 | break; | |
10990 | ||
03f66e8a MR |
10991 | case '2': |
10992 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10993 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10994 | my_getExpression (&imm_expr, s); |
10995 | check_absolute_expr (ip, &imm_expr); | |
10996 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10997 | && (unsigned long) imm_expr.X_add_number != 3) | |
10998 | { | |
10999 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11000 | (unsigned long) imm_expr.X_add_number); | |
11001 | } | |
03f66e8a MR |
11002 | INSERT_OPERAND (mips_opts.micromips, |
11003 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11004 | imm_expr.X_op = O_absent; |
11005 | s = expr_end; | |
11006 | continue; | |
11007 | ||
03f66e8a MR |
11008 | case '3': |
11009 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11010 | code) or 21 (for microMIPS code). */ | |
11011 | { | |
11012 | unsigned long mask = (mips_opts.micromips | |
11013 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11014 | ||
11015 | my_getExpression (&imm_expr, s); | |
11016 | check_absolute_expr (ip, &imm_expr); | |
11017 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11018 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11019 | mask, (unsigned long) imm_expr.X_add_number); | |
11020 | INSERT_OPERAND (mips_opts.micromips, | |
11021 | SA3, *ip, imm_expr.X_add_number); | |
11022 | imm_expr.X_op = O_absent; | |
11023 | s = expr_end; | |
11024 | } | |
74cd071d CF |
11025 | continue; |
11026 | ||
03f66e8a MR |
11027 | case '4': |
11028 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11029 | code) or 21 (for microMIPS code). */ | |
11030 | { | |
11031 | unsigned long mask = (mips_opts.micromips | |
11032 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11033 | ||
11034 | my_getExpression (&imm_expr, s); | |
11035 | check_absolute_expr (ip, &imm_expr); | |
11036 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11037 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11038 | mask, (unsigned long) imm_expr.X_add_number); | |
11039 | INSERT_OPERAND (mips_opts.micromips, | |
11040 | SA4, *ip, imm_expr.X_add_number); | |
11041 | imm_expr.X_op = O_absent; | |
11042 | s = expr_end; | |
11043 | } | |
74cd071d CF |
11044 | continue; |
11045 | ||
03f66e8a MR |
11046 | case '5': |
11047 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11048 | code) or 16 (for microMIPS code). */ | |
11049 | { | |
11050 | unsigned long mask = (mips_opts.micromips | |
11051 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11052 | ||
11053 | my_getExpression (&imm_expr, s); | |
11054 | check_absolute_expr (ip, &imm_expr); | |
11055 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11056 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11057 | mask, (unsigned long) imm_expr.X_add_number); | |
11058 | INSERT_OPERAND (mips_opts.micromips, | |
11059 | IMM8, *ip, imm_expr.X_add_number); | |
11060 | imm_expr.X_op = O_absent; | |
11061 | s = expr_end; | |
11062 | } | |
74cd071d CF |
11063 | continue; |
11064 | ||
03f66e8a MR |
11065 | case '6': |
11066 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11067 | code) or 21 (for microMIPS code). */ | |
11068 | { | |
11069 | unsigned long mask = (mips_opts.micromips | |
11070 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11071 | ||
11072 | my_getExpression (&imm_expr, s); | |
11073 | check_absolute_expr (ip, &imm_expr); | |
11074 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11075 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11076 | mask, (unsigned long) imm_expr.X_add_number); | |
11077 | INSERT_OPERAND (mips_opts.micromips, | |
11078 | RS, *ip, imm_expr.X_add_number); | |
11079 | imm_expr.X_op = O_absent; | |
11080 | s = expr_end; | |
11081 | } | |
74cd071d CF |
11082 | continue; |
11083 | ||
90ecf173 | 11084 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11085 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11086 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11087 | { |
11088 | regno = s[3] - '0'; | |
11089 | s += 4; | |
03f66e8a | 11090 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11091 | continue; |
11092 | } | |
11093 | else | |
11094 | as_bad (_("Invalid dsp acc register")); | |
11095 | break; | |
11096 | ||
03f66e8a MR |
11097 | case '8': |
11098 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11099 | code) or 14 (for microMIPS code). */ | |
11100 | { | |
11101 | unsigned long mask = (mips_opts.micromips | |
11102 | ? MICROMIPSOP_MASK_WRDSP | |
11103 | : OP_MASK_WRDSP); | |
11104 | ||
11105 | my_getExpression (&imm_expr, s); | |
11106 | check_absolute_expr (ip, &imm_expr); | |
11107 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11108 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11109 | mask, (unsigned long) imm_expr.X_add_number); | |
11110 | INSERT_OPERAND (mips_opts.micromips, | |
11111 | WRDSP, *ip, imm_expr.X_add_number); | |
11112 | imm_expr.X_op = O_absent; | |
11113 | s = expr_end; | |
11114 | } | |
74cd071d CF |
11115 | continue; |
11116 | ||
90ecf173 | 11117 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11118 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11119 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11120 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11121 | { |
11122 | regno = s[3] - '0'; | |
11123 | s += 4; | |
df58fc94 | 11124 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11125 | continue; |
11126 | } | |
11127 | else | |
11128 | as_bad (_("Invalid dsp acc register")); | |
11129 | break; | |
11130 | ||
03f66e8a MR |
11131 | case '0': |
11132 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11133 | code) or 20 (for microMIPS code). */ | |
11134 | { | |
11135 | long mask = (mips_opts.micromips | |
11136 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11137 | ||
11138 | my_getExpression (&imm_expr, s); | |
11139 | check_absolute_expr (ip, &imm_expr); | |
11140 | min_range = -((mask + 1) >> 1); | |
11141 | max_range = ((mask + 1) >> 1) - 1; | |
11142 | if (imm_expr.X_add_number < min_range | |
11143 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11144 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11145 | (long) min_range, (long) max_range, | |
11146 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11147 | INSERT_OPERAND (mips_opts.micromips, |
11148 | DSPSFT, *ip, imm_expr.X_add_number); | |
11149 | imm_expr.X_op = O_absent; | |
11150 | s = expr_end; | |
11151 | } | |
74cd071d CF |
11152 | continue; |
11153 | ||
90ecf173 | 11154 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11155 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11156 | my_getExpression (&imm_expr, s); |
11157 | check_absolute_expr (ip, &imm_expr); | |
11158 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11159 | { | |
a9e24354 TS |
11160 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11161 | OP_MASK_RDDSP, | |
11162 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11163 | } |
df58fc94 | 11164 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11165 | imm_expr.X_op = O_absent; |
11166 | s = expr_end; | |
11167 | continue; | |
11168 | ||
90ecf173 | 11169 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11170 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11171 | my_getExpression (&imm_expr, s); |
11172 | check_absolute_expr (ip, &imm_expr); | |
11173 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11174 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11175 | if (imm_expr.X_add_number < min_range || | |
11176 | imm_expr.X_add_number > max_range) | |
11177 | { | |
a9e24354 TS |
11178 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11179 | (long) min_range, (long) max_range, | |
11180 | (long) imm_expr.X_add_number); | |
74cd071d | 11181 | } |
df58fc94 | 11182 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11183 | imm_expr.X_op = O_absent; |
11184 | s = expr_end; | |
11185 | continue; | |
11186 | ||
90ecf173 | 11187 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11188 | { |
11189 | long mask = (mips_opts.micromips | |
11190 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11191 | ||
11192 | my_getExpression (&imm_expr, s); | |
11193 | check_absolute_expr (ip, &imm_expr); | |
11194 | min_range = -((mask + 1) >> 1); | |
11195 | max_range = ((mask + 1) >> 1) - 1; | |
11196 | if (imm_expr.X_add_number < min_range | |
11197 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11198 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11199 | (long) min_range, (long) max_range, | |
11200 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11201 | INSERT_OPERAND (mips_opts.micromips, |
11202 | IMM10, *ip, imm_expr.X_add_number); | |
11203 | imm_expr.X_op = O_absent; | |
11204 | s = expr_end; | |
11205 | } | |
11206 | continue; | |
11207 | ||
11208 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11209 | gas_assert (mips_opts.micromips); | |
11210 | my_getExpression (&imm_expr, s); | |
11211 | check_absolute_expr (ip, &imm_expr); | |
11212 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11213 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11214 | MICROMIPSOP_MASK_RD, | |
11215 | (unsigned long) imm_expr.X_add_number); | |
11216 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11217 | imm_expr.X_op = O_absent; |
11218 | s = expr_end; | |
11219 | continue; | |
11220 | ||
a9e24354 | 11221 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11222 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11223 | my_getExpression (&imm_expr, s); |
11224 | check_absolute_expr (ip, &imm_expr); | |
11225 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11226 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11227 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11228 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11229 | imm_expr.X_op = O_absent; |
11230 | s = expr_end; | |
11231 | continue; | |
11232 | ||
a9e24354 | 11233 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11234 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11235 | my_getExpression (&imm_expr, s); |
11236 | check_absolute_expr (ip, &imm_expr); | |
11237 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11238 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11239 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11240 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11241 | imm_expr.X_op = O_absent; |
11242 | s = expr_end; | |
11243 | continue; | |
11244 | ||
90ecf173 | 11245 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11246 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11247 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11248 | s[3] >= '0' && s[3] <= '3') | |
11249 | { | |
11250 | regno = s[3] - '0'; | |
11251 | s += 4; | |
df58fc94 | 11252 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11253 | continue; |
11254 | } | |
11255 | else | |
11256 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11257 | break; | |
11258 | ||
90ecf173 | 11259 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11260 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11261 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11262 | s[3] >= '0' && s[3] <= '3') | |
11263 | { | |
11264 | regno = s[3] - '0'; | |
11265 | s += 4; | |
df58fc94 | 11266 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11267 | continue; |
11268 | } | |
11269 | else | |
11270 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11271 | break; | |
11272 | ||
dec0624d MR |
11273 | case '\\': /* 3-bit bit position. */ |
11274 | { | |
2906b037 MR |
11275 | unsigned long mask = (mips_opts.micromips |
11276 | ? MICROMIPSOP_MASK_3BITPOS | |
11277 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11278 | |
11279 | my_getExpression (&imm_expr, s); | |
11280 | check_absolute_expr (ip, &imm_expr); | |
11281 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11282 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11283 | ip->insn_mo->name, | |
11284 | mask, (unsigned long) imm_expr.X_add_number); | |
11285 | INSERT_OPERAND (mips_opts.micromips, | |
11286 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11287 | imm_expr.X_op = O_absent; | |
11288 | s = expr_end; | |
11289 | } | |
11290 | continue; | |
11291 | ||
252b5132 | 11292 | case ',': |
a339155f | 11293 | ++argnum; |
252b5132 RH |
11294 | if (*s++ == *args) |
11295 | continue; | |
11296 | s--; | |
11297 | switch (*++args) | |
11298 | { | |
11299 | case 'r': | |
11300 | case 'v': | |
df58fc94 | 11301 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11302 | continue; |
11303 | ||
11304 | case 'w': | |
df58fc94 | 11305 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11306 | continue; |
11307 | ||
252b5132 | 11308 | case 'W': |
df58fc94 RS |
11309 | gas_assert (!mips_opts.micromips); |
11310 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11311 | continue; |
11312 | ||
11313 | case 'V': | |
df58fc94 | 11314 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11315 | continue; |
11316 | } | |
11317 | break; | |
11318 | ||
11319 | case '(': | |
11320 | /* Handle optional base register. | |
11321 | Either the base register is omitted or | |
bdaaa2e1 | 11322 | we must have a left paren. */ |
252b5132 RH |
11323 | /* This is dependent on the next operand specifier |
11324 | is a base register specification. */ | |
df58fc94 RS |
11325 | gas_assert (args[1] == 'b' |
11326 | || (mips_opts.micromips | |
11327 | && args[1] == 'm' | |
11328 | && (args[2] == 'l' || args[2] == 'n' | |
11329 | || args[2] == 's' || args[2] == 'a'))); | |
11330 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11331 | return; |
df58fc94 | 11332 | /* Fall through. */ |
252b5132 | 11333 | |
90ecf173 | 11334 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11335 | if (*s++ == *args) |
11336 | continue; | |
11337 | break; | |
11338 | ||
11339 | case '[': /* These must match exactly. */ | |
60b63b72 | 11340 | case ']': |
df58fc94 | 11341 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11342 | if (*s++ == *args) |
11343 | continue; | |
11344 | break; | |
11345 | ||
af7ee8bf CD |
11346 | case '+': /* Opcode extension character. */ |
11347 | switch (*++args) | |
11348 | { | |
9bcd4f99 TS |
11349 | case '1': /* UDI immediates. */ |
11350 | case '2': | |
11351 | case '3': | |
11352 | case '4': | |
df58fc94 | 11353 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11354 | { |
11355 | const struct mips_immed *imm = mips_immed; | |
11356 | ||
11357 | while (imm->type && imm->type != *args) | |
11358 | ++imm; | |
11359 | if (! imm->type) | |
b37df7c4 | 11360 | abort (); |
9bcd4f99 TS |
11361 | my_getExpression (&imm_expr, s); |
11362 | check_absolute_expr (ip, &imm_expr); | |
11363 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11364 | { | |
11365 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11366 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11367 | (unsigned long) imm_expr.X_add_number, | |
11368 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11369 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11370 | } |
11371 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11372 | << imm->shift); | |
11373 | imm_expr.X_op = O_absent; | |
11374 | s = expr_end; | |
11375 | } | |
11376 | continue; | |
90ecf173 | 11377 | |
b015e599 AP |
11378 | case 'J': /* 10-bit hypcall code. */ |
11379 | gas_assert (!mips_opts.micromips); | |
11380 | { | |
11381 | unsigned long mask = OP_MASK_CODE10; | |
11382 | ||
11383 | my_getExpression (&imm_expr, s); | |
11384 | check_absolute_expr (ip, &imm_expr); | |
11385 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11386 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11387 | ip->insn_mo->name, | |
11388 | mask, (unsigned long) imm_expr.X_add_number); | |
11389 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11390 | imm_expr.X_op = O_absent; | |
11391 | s = expr_end; | |
11392 | } | |
11393 | continue; | |
11394 | ||
071742cf CD |
11395 | case 'A': /* ins/ext position, becomes LSB. */ |
11396 | limlo = 0; | |
11397 | limhi = 31; | |
5f74bc13 CD |
11398 | goto do_lsb; |
11399 | case 'E': | |
11400 | limlo = 32; | |
11401 | limhi = 63; | |
11402 | goto do_lsb; | |
90ecf173 | 11403 | do_lsb: |
071742cf CD |
11404 | my_getExpression (&imm_expr, s); |
11405 | check_absolute_expr (ip, &imm_expr); | |
11406 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11407 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11408 | { | |
11409 | as_bad (_("Improper position (%lu)"), | |
11410 | (unsigned long) imm_expr.X_add_number); | |
11411 | imm_expr.X_add_number = limlo; | |
11412 | } | |
11413 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11414 | INSERT_OPERAND (mips_opts.micromips, |
11415 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11416 | imm_expr.X_op = O_absent; |
11417 | s = expr_end; | |
11418 | continue; | |
11419 | ||
11420 | case 'B': /* ins size, becomes MSB. */ | |
11421 | limlo = 1; | |
11422 | limhi = 32; | |
5f74bc13 CD |
11423 | goto do_msb; |
11424 | case 'F': | |
11425 | limlo = 33; | |
11426 | limhi = 64; | |
11427 | goto do_msb; | |
90ecf173 | 11428 | do_msb: |
071742cf CD |
11429 | my_getExpression (&imm_expr, s); |
11430 | check_absolute_expr (ip, &imm_expr); | |
11431 | /* Check for negative input so that small negative numbers | |
11432 | will not succeed incorrectly. The checks against | |
11433 | (pos+size) transitively check "size" itself, | |
11434 | assuming that "pos" is reasonable. */ | |
11435 | if ((long) imm_expr.X_add_number < 0 | |
11436 | || ((unsigned long) imm_expr.X_add_number | |
11437 | + lastpos) < limlo | |
11438 | || ((unsigned long) imm_expr.X_add_number | |
11439 | + lastpos) > limhi) | |
11440 | { | |
11441 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11442 | (unsigned long) imm_expr.X_add_number, | |
11443 | (unsigned long) lastpos); | |
11444 | imm_expr.X_add_number = limlo - lastpos; | |
11445 | } | |
df58fc94 RS |
11446 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11447 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11448 | imm_expr.X_op = O_absent; |
11449 | s = expr_end; | |
11450 | continue; | |
11451 | ||
11452 | case 'C': /* ext size, becomes MSBD. */ | |
11453 | limlo = 1; | |
11454 | limhi = 32; | |
f02d8318 | 11455 | sizelo = 1; |
5f74bc13 CD |
11456 | goto do_msbd; |
11457 | case 'G': | |
11458 | limlo = 33; | |
11459 | limhi = 64; | |
f02d8318 | 11460 | sizelo = 33; |
5f74bc13 CD |
11461 | goto do_msbd; |
11462 | case 'H': | |
11463 | limlo = 33; | |
11464 | limhi = 64; | |
f02d8318 | 11465 | sizelo = 1; |
5f74bc13 | 11466 | goto do_msbd; |
90ecf173 | 11467 | do_msbd: |
071742cf CD |
11468 | my_getExpression (&imm_expr, s); |
11469 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11470 | /* The checks against (pos+size) don't transitively check |
11471 | "size" itself, assuming that "pos" is reasonable. | |
11472 | We also need to check the lower bound of "size". */ | |
11473 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11474 | || ((unsigned long) imm_expr.X_add_number |
11475 | + lastpos) < limlo | |
11476 | || ((unsigned long) imm_expr.X_add_number | |
11477 | + lastpos) > limhi) | |
11478 | { | |
11479 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11480 | (unsigned long) imm_expr.X_add_number, | |
11481 | (unsigned long) lastpos); | |
11482 | imm_expr.X_add_number = limlo - lastpos; | |
11483 | } | |
df58fc94 RS |
11484 | INSERT_OPERAND (mips_opts.micromips, |
11485 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11486 | imm_expr.X_op = O_absent; |
11487 | s = expr_end; | |
11488 | continue; | |
af7ee8bf | 11489 | |
bbcc0807 CD |
11490 | case 'D': |
11491 | /* +D is for disassembly only; never match. */ | |
11492 | break; | |
11493 | ||
5f74bc13 CD |
11494 | case 'I': |
11495 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11496 | my_getExpression (&imm2_expr, s); | |
11497 | if (imm2_expr.X_op != O_big | |
11498 | && imm2_expr.X_op != O_constant) | |
11499 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11500 | if (HAVE_32BIT_GPRS) |
11501 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11502 | s = expr_end; |
11503 | continue; | |
11504 | ||
707bfff6 | 11505 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11506 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11507 | /* +T is for disassembly only; never match. */ |
11508 | break; | |
11509 | ||
707bfff6 | 11510 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11511 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11512 | if (s[0] == '$' && ISDIGIT (s[1])) |
11513 | { | |
11514 | ++s; | |
11515 | regno = 0; | |
11516 | do | |
11517 | { | |
11518 | regno *= 10; | |
11519 | regno += *s - '0'; | |
11520 | ++s; | |
11521 | } | |
11522 | while (ISDIGIT (*s)); | |
11523 | if (regno > 31) | |
11524 | as_bad (_("Invalid register number (%d)"), regno); | |
11525 | else | |
11526 | { | |
df58fc94 | 11527 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11528 | continue; |
11529 | } | |
11530 | } | |
11531 | else | |
11532 | as_bad (_("Invalid coprocessor 0 register number")); | |
11533 | break; | |
11534 | ||
bb35fb24 NC |
11535 | case 'x': |
11536 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11537 | is not in the valid range. */ | |
df58fc94 | 11538 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11539 | my_getExpression (&imm_expr, s); |
11540 | check_absolute_expr (ip, &imm_expr); | |
11541 | if ((unsigned) imm_expr.X_add_number > 31) | |
11542 | { | |
11543 | as_bad (_("Improper bit index (%lu)"), | |
11544 | (unsigned long) imm_expr.X_add_number); | |
11545 | imm_expr.X_add_number = 0; | |
11546 | } | |
df58fc94 | 11547 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11548 | imm_expr.X_op = O_absent; |
11549 | s = expr_end; | |
11550 | continue; | |
11551 | ||
11552 | case 'X': | |
11553 | /* bbit[01] bit index when bbit is used but we generate | |
11554 | bbit[01]32 because the index is over 32. Move to the | |
11555 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11556 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11557 | my_getExpression (&imm_expr, s); |
11558 | check_absolute_expr (ip, &imm_expr); | |
11559 | if ((unsigned) imm_expr.X_add_number < 32 | |
11560 | || (unsigned) imm_expr.X_add_number > 63) | |
11561 | break; | |
df58fc94 | 11562 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11563 | imm_expr.X_op = O_absent; |
11564 | s = expr_end; | |
11565 | continue; | |
11566 | ||
11567 | case 'p': | |
11568 | /* cins, cins32, exts and exts32 position field. Give error | |
11569 | if it's not in the valid range. */ | |
df58fc94 | 11570 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11571 | my_getExpression (&imm_expr, s); |
11572 | check_absolute_expr (ip, &imm_expr); | |
11573 | if ((unsigned) imm_expr.X_add_number > 31) | |
11574 | { | |
11575 | as_bad (_("Improper position (%lu)"), | |
11576 | (unsigned long) imm_expr.X_add_number); | |
11577 | imm_expr.X_add_number = 0; | |
11578 | } | |
11579 | /* Make the pos explicit to simplify +S. */ | |
11580 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11581 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11582 | imm_expr.X_op = O_absent; |
11583 | s = expr_end; | |
11584 | continue; | |
11585 | ||
11586 | case 'P': | |
11587 | /* cins, cins32, exts and exts32 position field. Move to | |
11588 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11589 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11590 | my_getExpression (&imm_expr, s); |
11591 | check_absolute_expr (ip, &imm_expr); | |
11592 | if ((unsigned) imm_expr.X_add_number < 32 | |
11593 | || (unsigned) imm_expr.X_add_number > 63) | |
11594 | break; | |
11595 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11596 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11597 | imm_expr.X_op = O_absent; |
11598 | s = expr_end; | |
11599 | continue; | |
11600 | ||
11601 | case 's': | |
11602 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11603 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11604 | my_getExpression (&imm_expr, s); |
11605 | check_absolute_expr (ip, &imm_expr); | |
11606 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11607 | { | |
11608 | as_bad (_("Improper size (%lu)"), | |
11609 | (unsigned long) imm_expr.X_add_number); | |
11610 | imm_expr.X_add_number = 0; | |
11611 | } | |
df58fc94 | 11612 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11613 | imm_expr.X_op = O_absent; |
11614 | s = expr_end; | |
11615 | continue; | |
11616 | ||
11617 | case 'S': | |
11618 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11619 | length-minus-one field. */ | |
df58fc94 | 11620 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11621 | my_getExpression (&imm_expr, s); |
11622 | check_absolute_expr (ip, &imm_expr); | |
11623 | if ((long) imm_expr.X_add_number < 0 | |
11624 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11625 | { | |
11626 | as_bad (_("Improper size (%lu)"), | |
11627 | (unsigned long) imm_expr.X_add_number); | |
11628 | imm_expr.X_add_number = 0; | |
11629 | } | |
df58fc94 | 11630 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11631 | imm_expr.X_op = O_absent; |
11632 | s = expr_end; | |
11633 | continue; | |
11634 | ||
dd3cbb7e NC |
11635 | case 'Q': |
11636 | /* seqi/snei immediate field. */ | |
df58fc94 | 11637 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11638 | my_getExpression (&imm_expr, s); |
11639 | check_absolute_expr (ip, &imm_expr); | |
11640 | if ((long) imm_expr.X_add_number < -512 | |
11641 | || (long) imm_expr.X_add_number >= 512) | |
11642 | { | |
11643 | as_bad (_("Improper immediate (%ld)"), | |
11644 | (long) imm_expr.X_add_number); | |
11645 | imm_expr.X_add_number = 0; | |
11646 | } | |
df58fc94 | 11647 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11648 | imm_expr.X_op = O_absent; |
11649 | s = expr_end; | |
11650 | continue; | |
11651 | ||
98675402 | 11652 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11653 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11654 | my_getExpression (&imm_expr, s); |
11655 | check_absolute_expr (ip, &imm_expr); | |
11656 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11657 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11658 | if (imm_expr.X_add_number < min_range | |
11659 | || imm_expr.X_add_number > max_range) | |
11660 | { | |
c95354ed | 11661 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11662 | (long) min_range, (long) max_range, |
11663 | (long) imm_expr.X_add_number); | |
11664 | } | |
df58fc94 | 11665 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11666 | imm_expr.X_op = O_absent; |
11667 | s = expr_end; | |
11668 | continue; | |
11669 | ||
11670 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11671 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11672 | my_getExpression (&imm_expr, s); |
11673 | check_absolute_expr (ip, &imm_expr); | |
11674 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11675 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11676 | if (imm_expr.X_add_number < min_range | |
11677 | || imm_expr.X_add_number > max_range) | |
11678 | { | |
c95354ed | 11679 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11680 | (long) min_range, (long) max_range, |
11681 | (long) imm_expr.X_add_number); | |
11682 | } | |
df58fc94 | 11683 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11684 | imm_expr.X_op = O_absent; |
11685 | s = expr_end; | |
11686 | continue; | |
11687 | ||
11688 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11689 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11690 | my_getExpression (&imm_expr, s); |
11691 | check_absolute_expr (ip, &imm_expr); | |
11692 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11693 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11694 | /* We check the offset range before adjusted. */ |
11695 | min_range <<= 4; | |
11696 | max_range <<= 4; | |
98675402 RS |
11697 | if (imm_expr.X_add_number < min_range |
11698 | || imm_expr.X_add_number > max_range) | |
11699 | { | |
c95354ed | 11700 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11701 | (long) min_range, (long) max_range, |
11702 | (long) imm_expr.X_add_number); | |
11703 | } | |
c95354ed MX |
11704 | if (imm_expr.X_add_number & 0xf) |
11705 | { | |
11706 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11707 | (long) imm_expr.X_add_number); | |
11708 | } | |
11709 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11710 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11711 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11712 | imm_expr.X_op = O_absent; |
11713 | s = expr_end; | |
11714 | continue; | |
11715 | ||
11716 | case 'z': | |
df58fc94 | 11717 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11718 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11719 | break; | |
11720 | if (regno == AT && mips_opts.at) | |
11721 | { | |
11722 | if (mips_opts.at == ATREG) | |
11723 | as_warn (_("used $at without \".set noat\"")); | |
11724 | else | |
11725 | as_warn (_("used $%u with \".set at=$%u\""), | |
11726 | regno, mips_opts.at); | |
11727 | } | |
df58fc94 | 11728 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11729 | continue; |
11730 | ||
11731 | case 'Z': | |
df58fc94 | 11732 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11733 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11734 | break; | |
df58fc94 | 11735 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11736 | continue; |
11737 | ||
af7ee8bf | 11738 | default: |
df58fc94 | 11739 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11740 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11741 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11742 | *args, insn->name, insn->args); |
af7ee8bf CD |
11743 | /* Further processing is fruitless. */ |
11744 | return; | |
11745 | } | |
11746 | break; | |
11747 | ||
df58fc94 | 11748 | case '.': /* 10-bit offset. */ |
df58fc94 | 11749 | gas_assert (mips_opts.micromips); |
dec0624d | 11750 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11751 | { |
11752 | int shift = *args == '.' ? 9 : 11; | |
11753 | size_t i; | |
11754 | ||
11755 | /* Check whether there is only a single bracketed expression | |
11756 | left. If so, it must be the base register and the | |
11757 | constant must be zero. */ | |
11758 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11759 | continue; | |
11760 | ||
11761 | /* If this value won't fit into the offset, then go find | |
11762 | a macro that will generate a 16- or 32-bit offset code | |
11763 | pattern. */ | |
11764 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11765 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11766 | || imm_expr.X_add_number >= 1 << shift | |
11767 | || imm_expr.X_add_number < -1 << shift)) | |
11768 | || i > 0) | |
11769 | { | |
11770 | imm_expr.X_op = O_absent; | |
11771 | break; | |
11772 | } | |
11773 | if (shift == 9) | |
11774 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11775 | else | |
dec0624d MR |
11776 | INSERT_OPERAND (mips_opts.micromips, |
11777 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11778 | imm_expr.X_op = O_absent; |
11779 | s = expr_end; | |
11780 | } | |
11781 | continue; | |
11782 | ||
252b5132 RH |
11783 | case '<': /* must be at least one digit */ |
11784 | /* | |
11785 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11786 | * than 31 or less than 0, then the shift amount should be |
11787 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11788 | * We issue a warning and mask out all but the low 5 bits. |
11789 | */ | |
11790 | my_getExpression (&imm_expr, s); | |
11791 | check_absolute_expr (ip, &imm_expr); | |
11792 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11793 | as_warn (_("Improper shift amount (%lu)"), |
11794 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11795 | INSERT_OPERAND (mips_opts.micromips, |
11796 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11797 | imm_expr.X_op = O_absent; |
11798 | s = expr_end; | |
11799 | continue; | |
11800 | ||
11801 | case '>': /* shift amount minus 32 */ | |
11802 | my_getExpression (&imm_expr, s); | |
11803 | check_absolute_expr (ip, &imm_expr); | |
11804 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11805 | || (unsigned long) imm_expr.X_add_number > 63) | |
11806 | break; | |
df58fc94 RS |
11807 | INSERT_OPERAND (mips_opts.micromips, |
11808 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11809 | imm_expr.X_op = O_absent; |
11810 | s = expr_end; | |
11811 | continue; | |
11812 | ||
90ecf173 MR |
11813 | case 'k': /* CACHE code. */ |
11814 | case 'h': /* PREFX code. */ | |
11815 | case '1': /* SYNC type. */ | |
252b5132 RH |
11816 | my_getExpression (&imm_expr, s); |
11817 | check_absolute_expr (ip, &imm_expr); | |
11818 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11819 | as_warn (_("Invalid value for `%s' (%lu)"), |
11820 | ip->insn_mo->name, | |
11821 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11822 | switch (*args) |
d954098f | 11823 | { |
df58fc94 RS |
11824 | case 'k': |
11825 | if (mips_fix_cn63xxp1 | |
11826 | && !mips_opts.micromips | |
11827 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11828 | switch (imm_expr.X_add_number) |
11829 | { | |
11830 | case 5: | |
11831 | case 25: | |
11832 | case 26: | |
11833 | case 27: | |
11834 | case 28: | |
11835 | case 29: | |
11836 | case 30: | |
11837 | case 31: /* These are ok. */ | |
11838 | break; | |
11839 | ||
11840 | default: /* The rest must be changed to 28. */ | |
11841 | imm_expr.X_add_number = 28; | |
11842 | break; | |
11843 | } | |
df58fc94 RS |
11844 | INSERT_OPERAND (mips_opts.micromips, |
11845 | CACHE, *ip, imm_expr.X_add_number); | |
11846 | break; | |
11847 | case 'h': | |
11848 | INSERT_OPERAND (mips_opts.micromips, | |
11849 | PREFX, *ip, imm_expr.X_add_number); | |
11850 | break; | |
11851 | case '1': | |
11852 | INSERT_OPERAND (mips_opts.micromips, | |
11853 | STYPE, *ip, imm_expr.X_add_number); | |
11854 | break; | |
d954098f | 11855 | } |
252b5132 RH |
11856 | imm_expr.X_op = O_absent; |
11857 | s = expr_end; | |
11858 | continue; | |
11859 | ||
90ecf173 | 11860 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11861 | { |
11862 | unsigned long mask = (mips_opts.micromips | |
11863 | ? MICROMIPSOP_MASK_CODE | |
11864 | : OP_MASK_CODE); | |
11865 | ||
11866 | my_getExpression (&imm_expr, s); | |
11867 | check_absolute_expr (ip, &imm_expr); | |
11868 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11869 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11870 | ip->insn_mo->name, | |
11871 | mask, (unsigned long) imm_expr.X_add_number); | |
11872 | INSERT_OPERAND (mips_opts.micromips, | |
11873 | CODE, *ip, imm_expr.X_add_number); | |
11874 | imm_expr.X_op = O_absent; | |
11875 | s = expr_end; | |
11876 | } | |
252b5132 RH |
11877 | continue; |
11878 | ||
90ecf173 | 11879 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11880 | { |
11881 | unsigned long mask = (mips_opts.micromips | |
11882 | ? MICROMIPSOP_MASK_CODE2 | |
11883 | : OP_MASK_CODE2); | |
11884 | ||
11885 | my_getExpression (&imm_expr, s); | |
11886 | check_absolute_expr (ip, &imm_expr); | |
11887 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11888 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11889 | ip->insn_mo->name, | |
11890 | mask, (unsigned long) imm_expr.X_add_number); | |
11891 | INSERT_OPERAND (mips_opts.micromips, | |
11892 | CODE2, *ip, imm_expr.X_add_number); | |
11893 | imm_expr.X_op = O_absent; | |
11894 | s = expr_end; | |
11895 | } | |
252b5132 RH |
11896 | continue; |
11897 | ||
df58fc94 RS |
11898 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11899 | { | |
11900 | unsigned long mask = (mips_opts.micromips | |
11901 | ? MICROMIPSOP_MASK_CODE10 | |
11902 | : OP_MASK_CODE20); | |
11903 | ||
11904 | my_getExpression (&imm_expr, s); | |
11905 | check_absolute_expr (ip, &imm_expr); | |
11906 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11907 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11908 | ip->insn_mo->name, | |
11909 | mask, (unsigned long) imm_expr.X_add_number); | |
11910 | if (mips_opts.micromips) | |
11911 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11912 | else | |
11913 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11914 | imm_expr.X_op = O_absent; | |
11915 | s = expr_end; | |
11916 | } | |
252b5132 RH |
11917 | continue; |
11918 | ||
df58fc94 RS |
11919 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11920 | { | |
11921 | unsigned long mask = (mips_opts.micromips | |
11922 | ? MICROMIPSOP_MASK_COPZ | |
11923 | : OP_MASK_COPZ); | |
11924 | ||
11925 | my_getExpression (&imm_expr, s); | |
11926 | check_absolute_expr (ip, &imm_expr); | |
11927 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11928 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11929 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11930 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11931 | INSERT_OPERAND (mips_opts.micromips, |
11932 | COPZ, *ip, imm_expr.X_add_number); | |
11933 | imm_expr.X_op = O_absent; | |
11934 | s = expr_end; | |
11935 | } | |
beae10d5 | 11936 | continue; |
252b5132 | 11937 | |
df58fc94 RS |
11938 | case 'J': /* 19-bit WAIT code. */ |
11939 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11940 | my_getExpression (&imm_expr, s); |
11941 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11942 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11943 | { |
11944 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11945 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11946 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11947 | } | |
11948 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11949 | imm_expr.X_op = O_absent; |
11950 | s = expr_end; | |
11951 | continue; | |
11952 | ||
707bfff6 | 11953 | case 'P': /* Performance register. */ |
df58fc94 | 11954 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11955 | my_getExpression (&imm_expr, s); |
252b5132 | 11956 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11957 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11958 | as_warn (_("Invalid performance register (%lu)"), |
11959 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
11960 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
11961 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
11962 | as_warn (_("Invalid performance register (%lu)"), | |
11963 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11964 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11965 | imm_expr.X_op = O_absent; |
11966 | s = expr_end; | |
11967 | continue; | |
252b5132 | 11968 | |
707bfff6 | 11969 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11970 | { |
11971 | unsigned long opcode = ip->insn_opcode; | |
11972 | unsigned long mask; | |
11973 | unsigned int types; | |
11974 | int cop0; | |
11975 | ||
11976 | if (mips_opts.micromips) | |
11977 | { | |
11978 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11979 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11980 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11981 | opcode &= mask; | |
11982 | switch (opcode) | |
11983 | { | |
11984 | case 0x000000fc: /* mfc0 */ | |
11985 | case 0x000002fc: /* mtc0 */ | |
11986 | case 0x580000fc: /* dmfc0 */ | |
11987 | case 0x580002fc: /* dmtc0 */ | |
11988 | cop0 = 1; | |
11989 | break; | |
11990 | default: | |
11991 | cop0 = 0; | |
11992 | break; | |
11993 | } | |
11994 | } | |
11995 | else | |
11996 | { | |
11997 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11998 | cop0 = opcode == OP_OP_COP0; | |
11999 | } | |
12000 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12001 | ok = reg_lookup (&s, types, ®no); | |
12002 | if (mips_opts.micromips) | |
12003 | INSERT_OPERAND (1, RS, *ip, regno); | |
12004 | else | |
12005 | INSERT_OPERAND (0, RD, *ip, regno); | |
12006 | if (ok) | |
12007 | { | |
12008 | lastregno = regno; | |
12009 | continue; | |
12010 | } | |
12011 | } | |
12012 | break; | |
707bfff6 | 12013 | |
df58fc94 RS |
12014 | case 'y': /* ALNV.PS source register. */ |
12015 | gas_assert (mips_opts.micromips); | |
12016 | goto do_reg; | |
12017 | case 'x': /* Ignore register name. */ | |
12018 | case 'U': /* Destination register (CLO/CLZ). */ | |
12019 | case 'g': /* Coprocessor destination register. */ | |
12020 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12021 | case 'b': /* Base register. */ |
12022 | case 'd': /* Destination register. */ | |
12023 | case 's': /* Source register. */ | |
12024 | case 't': /* Target register. */ | |
12025 | case 'r': /* Both target and source. */ | |
12026 | case 'v': /* Both dest and source. */ | |
12027 | case 'w': /* Both dest and target. */ | |
12028 | case 'E': /* Coprocessor target register. */ | |
12029 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12030 | case 'z': /* Must be zero register. */ |
df58fc94 | 12031 | do_reg: |
90ecf173 | 12032 | s_reset = s; |
707bfff6 TS |
12033 | if (*args == 'E' || *args == 'K') |
12034 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12035 | else | |
12036 | { | |
12037 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12038 | if (regno == AT && mips_opts.at) |
12039 | { | |
12040 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12041 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12042 | else |
f71d0d44 | 12043 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12044 | regno, mips_opts.at); |
12045 | } | |
707bfff6 TS |
12046 | } |
12047 | if (ok) | |
252b5132 | 12048 | { |
252b5132 RH |
12049 | c = *args; |
12050 | if (*s == ' ') | |
f9419b05 | 12051 | ++s; |
252b5132 RH |
12052 | if (args[1] != *s) |
12053 | { | |
12054 | if (c == 'r' || c == 'v' || c == 'w') | |
12055 | { | |
12056 | regno = lastregno; | |
12057 | s = s_reset; | |
f9419b05 | 12058 | ++args; |
252b5132 RH |
12059 | } |
12060 | } | |
12061 | /* 'z' only matches $0. */ | |
12062 | if (c == 'z' && regno != 0) | |
12063 | break; | |
12064 | ||
24864476 | 12065 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12066 | { |
12067 | if (regno == lastregno) | |
90ecf173 MR |
12068 | { |
12069 | insn_error | |
f71d0d44 | 12070 | = _("Source and destination must be different"); |
e7c604dd | 12071 | continue; |
90ecf173 | 12072 | } |
24864476 | 12073 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12074 | { |
12075 | insn_error | |
f71d0d44 | 12076 | = _("A destination register must be supplied"); |
e7c604dd | 12077 | continue; |
90ecf173 | 12078 | } |
e7c604dd | 12079 | } |
90ecf173 MR |
12080 | /* Now that we have assembled one operand, we use the args |
12081 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12082 | switch (c) |
12083 | { | |
12084 | case 'r': | |
12085 | case 's': | |
12086 | case 'v': | |
12087 | case 'b': | |
df58fc94 | 12088 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12089 | break; |
df58fc94 | 12090 | |
af7ee8bf | 12091 | case 'K': |
df58fc94 RS |
12092 | if (mips_opts.micromips) |
12093 | INSERT_OPERAND (1, RS, *ip, regno); | |
12094 | else | |
12095 | INSERT_OPERAND (0, RD, *ip, regno); | |
12096 | break; | |
12097 | ||
12098 | case 'd': | |
ef2e4d86 | 12099 | case 'g': |
df58fc94 | 12100 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12101 | break; |
df58fc94 | 12102 | |
4372b673 | 12103 | case 'U': |
df58fc94 RS |
12104 | gas_assert (!mips_opts.micromips); |
12105 | INSERT_OPERAND (0, RD, *ip, regno); | |
12106 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12107 | break; |
df58fc94 | 12108 | |
252b5132 RH |
12109 | case 'w': |
12110 | case 't': | |
12111 | case 'E': | |
df58fc94 RS |
12112 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12113 | break; | |
12114 | ||
12115 | case 'y': | |
12116 | gas_assert (mips_opts.micromips); | |
12117 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12118 | break; |
df58fc94 | 12119 | |
252b5132 RH |
12120 | case 'x': |
12121 | /* This case exists because on the r3000 trunc | |
12122 | expands into a macro which requires a gp | |
12123 | register. On the r6000 or r4000 it is | |
12124 | assembled into a single instruction which | |
12125 | ignores the register. Thus the insn version | |
12126 | is MIPS_ISA2 and uses 'x', and the macro | |
12127 | version is MIPS_ISA1 and uses 't'. */ | |
12128 | break; | |
df58fc94 | 12129 | |
252b5132 RH |
12130 | case 'z': |
12131 | /* This case is for the div instruction, which | |
12132 | acts differently if the destination argument | |
12133 | is $0. This only matches $0, and is checked | |
12134 | outside the switch. */ | |
12135 | break; | |
252b5132 RH |
12136 | } |
12137 | lastregno = regno; | |
12138 | continue; | |
12139 | } | |
252b5132 RH |
12140 | switch (*args++) |
12141 | { | |
12142 | case 'r': | |
12143 | case 'v': | |
df58fc94 | 12144 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12145 | continue; |
df58fc94 | 12146 | |
252b5132 | 12147 | case 'w': |
df58fc94 | 12148 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12149 | continue; |
12150 | } | |
12151 | break; | |
12152 | ||
deec1734 | 12153 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12154 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12155 | my_getExpression (&imm_expr, s); |
12156 | check_absolute_expr (ip, &imm_expr); | |
12157 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12158 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12159 | (long) imm_expr.X_add_number); |
df58fc94 | 12160 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12161 | imm_expr.X_op = O_absent; |
12162 | s = expr_end; | |
12163 | continue; | |
12164 | ||
12165 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12166 | if (s[0] != '$') | |
12167 | { | |
12168 | /* MDMX Immediate. */ | |
df58fc94 | 12169 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12170 | my_getExpression (&imm_expr, s); |
12171 | check_absolute_expr (ip, &imm_expr); | |
12172 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12173 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12174 | (long) imm_expr.X_add_number); | |
df58fc94 | 12175 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12176 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12177 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12178 | else | |
12179 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12180 | imm_expr.X_op = O_absent; |
12181 | s = expr_end; | |
12182 | continue; | |
12183 | } | |
12184 | /* Not MDMX Immediate. Fall through. */ | |
12185 | case 'X': /* MDMX destination register. */ | |
12186 | case 'Y': /* MDMX source register. */ | |
12187 | case 'Z': /* MDMX target register. */ | |
12188 | is_mdmx = 1; | |
df58fc94 RS |
12189 | case 'W': |
12190 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12191 | case 'D': /* Floating point destination register. */ |
12192 | case 'S': /* Floating point source register. */ | |
12193 | case 'T': /* Floating point target register. */ | |
12194 | case 'R': /* Floating point source register. */ | |
252b5132 | 12195 | case 'V': |
707bfff6 TS |
12196 | rtype = RTYPE_FPU; |
12197 | if (is_mdmx | |
12198 | || (mips_opts.ase_mdmx | |
12199 | && (ip->insn_mo->pinfo & FP_D) | |
12200 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12201 | | INSN_COPROC_MEMORY_DELAY | |
12202 | | INSN_LOAD_COPROC_DELAY | |
12203 | | INSN_LOAD_MEMORY_DELAY | |
12204 | | INSN_STORE_MEMORY)))) | |
12205 | rtype |= RTYPE_VEC; | |
252b5132 | 12206 | s_reset = s; |
707bfff6 | 12207 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12208 | { |
252b5132 | 12209 | if ((regno & 1) != 0 |
ca4e0257 | 12210 | && HAVE_32BIT_FPRS |
90ecf173 | 12211 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12212 | as_warn (_("Float register should be even, was %d"), |
12213 | regno); | |
12214 | ||
12215 | c = *args; | |
12216 | if (*s == ' ') | |
f9419b05 | 12217 | ++s; |
252b5132 RH |
12218 | if (args[1] != *s) |
12219 | { | |
12220 | if (c == 'V' || c == 'W') | |
12221 | { | |
12222 | regno = lastregno; | |
12223 | s = s_reset; | |
f9419b05 | 12224 | ++args; |
252b5132 RH |
12225 | } |
12226 | } | |
12227 | switch (c) | |
12228 | { | |
12229 | case 'D': | |
deec1734 | 12230 | case 'X': |
df58fc94 | 12231 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12232 | break; |
df58fc94 | 12233 | |
252b5132 RH |
12234 | case 'V': |
12235 | case 'S': | |
deec1734 | 12236 | case 'Y': |
df58fc94 | 12237 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12238 | break; |
df58fc94 | 12239 | |
deec1734 CD |
12240 | case 'Q': |
12241 | /* This is like 'Z', but also needs to fix the MDMX | |
12242 | vector/scalar select bits. Note that the | |
12243 | scalar immediate case is handled above. */ | |
12244 | if (*s == '[') | |
12245 | { | |
12246 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12247 | int max_el = (is_qh ? 3 : 7); | |
12248 | s++; | |
12249 | my_getExpression(&imm_expr, s); | |
12250 | check_absolute_expr (ip, &imm_expr); | |
12251 | s = expr_end; | |
12252 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12253 | as_bad (_("Bad element selector %ld"), |
12254 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12255 | imm_expr.X_add_number &= max_el; |
12256 | ip->insn_opcode |= (imm_expr.X_add_number | |
12257 | << (OP_SH_VSEL + | |
12258 | (is_qh ? 2 : 1))); | |
01a3f561 | 12259 | imm_expr.X_op = O_absent; |
deec1734 | 12260 | if (*s != ']') |
20203fb9 | 12261 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12262 | else |
12263 | s++; | |
12264 | } | |
12265 | else | |
12266 | { | |
12267 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12268 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12269 | << OP_SH_VSEL); | |
12270 | else | |
12271 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12272 | OP_SH_VSEL); | |
12273 | } | |
90ecf173 | 12274 | /* Fall through. */ |
252b5132 RH |
12275 | case 'W': |
12276 | case 'T': | |
deec1734 | 12277 | case 'Z': |
df58fc94 | 12278 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12279 | break; |
df58fc94 | 12280 | |
252b5132 | 12281 | case 'R': |
df58fc94 | 12282 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12283 | break; |
12284 | } | |
12285 | lastregno = regno; | |
12286 | continue; | |
12287 | } | |
12288 | ||
252b5132 RH |
12289 | switch (*args++) |
12290 | { | |
12291 | case 'V': | |
df58fc94 | 12292 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12293 | continue; |
df58fc94 | 12294 | |
252b5132 | 12295 | case 'W': |
df58fc94 | 12296 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12297 | continue; |
12298 | } | |
12299 | break; | |
12300 | ||
12301 | case 'I': | |
12302 | my_getExpression (&imm_expr, s); | |
12303 | if (imm_expr.X_op != O_big | |
12304 | && imm_expr.X_op != O_constant) | |
12305 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12306 | if (HAVE_32BIT_GPRS) |
12307 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12308 | s = expr_end; |
12309 | continue; | |
12310 | ||
12311 | case 'A': | |
12312 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12313 | normalize_address_expr (&offset_expr); |
f6688943 | 12314 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12315 | s = expr_end; |
12316 | continue; | |
12317 | ||
12318 | case 'F': | |
12319 | case 'L': | |
12320 | case 'f': | |
12321 | case 'l': | |
12322 | { | |
12323 | int f64; | |
ca4e0257 | 12324 | int using_gprs; |
252b5132 RH |
12325 | char *save_in; |
12326 | char *err; | |
12327 | unsigned char temp[8]; | |
12328 | int len; | |
12329 | unsigned int length; | |
12330 | segT seg; | |
12331 | subsegT subseg; | |
12332 | char *p; | |
12333 | ||
12334 | /* These only appear as the last operand in an | |
12335 | instruction, and every instruction that accepts | |
12336 | them in any variant accepts them in all variants. | |
12337 | This means we don't have to worry about backing out | |
12338 | any changes if the instruction does not match. | |
12339 | ||
12340 | The difference between them is the size of the | |
12341 | floating point constant and where it goes. For 'F' | |
12342 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12343 | is 32 bits. Where the constant is placed is based | |
12344 | on how the MIPS assembler does things: | |
12345 | F -- .rdata | |
12346 | L -- .lit8 | |
12347 | f -- immediate value | |
12348 | l -- .lit4 | |
12349 | ||
12350 | The .lit4 and .lit8 sections are only used if | |
12351 | permitted by the -G argument. | |
12352 | ||
ca4e0257 RS |
12353 | The code below needs to know whether the target register |
12354 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12355 | 'F' are used with GPR-based instructions and 'l' and | |
12356 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12357 | |
12358 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12359 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12360 | |
12361 | save_in = input_line_pointer; | |
12362 | input_line_pointer = s; | |
12363 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12364 | length = len; | |
12365 | s = input_line_pointer; | |
12366 | input_line_pointer = save_in; | |
12367 | if (err != NULL && *err != '\0') | |
12368 | { | |
12369 | as_bad (_("Bad floating point constant: %s"), err); | |
12370 | memset (temp, '\0', sizeof temp); | |
12371 | length = f64 ? 8 : 4; | |
12372 | } | |
12373 | ||
9c2799c2 | 12374 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12375 | |
12376 | if (*args == 'f' | |
12377 | || (*args == 'l' | |
3e722fb5 | 12378 | && (g_switch_value < 4 |
252b5132 RH |
12379 | || (temp[0] == 0 && temp[1] == 0) |
12380 | || (temp[2] == 0 && temp[3] == 0)))) | |
12381 | { | |
12382 | imm_expr.X_op = O_constant; | |
90ecf173 | 12383 | if (!target_big_endian) |
252b5132 RH |
12384 | imm_expr.X_add_number = bfd_getl32 (temp); |
12385 | else | |
12386 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12387 | } | |
12388 | else if (length > 4 | |
90ecf173 | 12389 | && !mips_disable_float_construction |
ca4e0257 RS |
12390 | /* Constants can only be constructed in GPRs and |
12391 | copied to FPRs if the GPRs are at least as wide | |
12392 | as the FPRs. Force the constant into memory if | |
12393 | we are using 64-bit FPRs but the GPRs are only | |
12394 | 32 bits wide. */ | |
12395 | && (using_gprs | |
90ecf173 | 12396 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12397 | && ((temp[0] == 0 && temp[1] == 0) |
12398 | || (temp[2] == 0 && temp[3] == 0)) | |
12399 | && ((temp[4] == 0 && temp[5] == 0) | |
12400 | || (temp[6] == 0 && temp[7] == 0))) | |
12401 | { | |
ca4e0257 | 12402 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12403 | instructions. If using 32-bit registers, set |
12404 | imm_expr to the high order 32 bits and offset_expr to | |
12405 | the low order 32 bits. Otherwise, set imm_expr to | |
12406 | the entire 64 bit constant. */ | |
ca4e0257 | 12407 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12408 | { |
12409 | imm_expr.X_op = O_constant; | |
12410 | offset_expr.X_op = O_constant; | |
90ecf173 | 12411 | if (!target_big_endian) |
252b5132 RH |
12412 | { |
12413 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12414 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12415 | } | |
12416 | else | |
12417 | { | |
12418 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12419 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12420 | } | |
12421 | if (offset_expr.X_add_number == 0) | |
12422 | offset_expr.X_op = O_absent; | |
12423 | } | |
12424 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12425 | { | |
12426 | imm_expr.X_op = O_constant; | |
90ecf173 | 12427 | if (!target_big_endian) |
252b5132 RH |
12428 | imm_expr.X_add_number = bfd_getl64 (temp); |
12429 | else | |
12430 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12431 | } | |
12432 | else | |
12433 | { | |
12434 | imm_expr.X_op = O_big; | |
12435 | imm_expr.X_add_number = 4; | |
90ecf173 | 12436 | if (!target_big_endian) |
252b5132 RH |
12437 | { |
12438 | generic_bignum[0] = bfd_getl16 (temp); | |
12439 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12440 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12441 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12442 | } | |
12443 | else | |
12444 | { | |
12445 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12446 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12447 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12448 | generic_bignum[3] = bfd_getb16 (temp); | |
12449 | } | |
12450 | } | |
12451 | } | |
12452 | else | |
12453 | { | |
12454 | const char *newname; | |
12455 | segT new_seg; | |
12456 | ||
12457 | /* Switch to the right section. */ | |
12458 | seg = now_seg; | |
12459 | subseg = now_subseg; | |
12460 | switch (*args) | |
12461 | { | |
12462 | default: /* unused default case avoids warnings. */ | |
12463 | case 'L': | |
12464 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12465 | if (g_switch_value >= 8) |
252b5132 RH |
12466 | newname = ".lit8"; |
12467 | break; | |
12468 | case 'F': | |
3e722fb5 | 12469 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12470 | break; |
12471 | case 'l': | |
9c2799c2 | 12472 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12473 | newname = ".lit4"; |
12474 | break; | |
12475 | } | |
12476 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12477 | if (IS_ELF) |
252b5132 RH |
12478 | bfd_set_section_flags (stdoutput, new_seg, |
12479 | (SEC_ALLOC | |
12480 | | SEC_LOAD | |
12481 | | SEC_READONLY | |
12482 | | SEC_DATA)); | |
12483 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12484 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12485 | record_alignment (new_seg, 4); |
12486 | else | |
12487 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12488 | if (seg == now_seg) | |
12489 | as_bad (_("Can't use floating point insn in this section")); | |
12490 | ||
df58fc94 RS |
12491 | /* Set the argument to the current address in the |
12492 | section. */ | |
12493 | offset_expr.X_op = O_symbol; | |
12494 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12495 | offset_expr.X_add_number = 0; | |
12496 | ||
12497 | /* Put the floating point number into the section. */ | |
12498 | p = frag_more ((int) length); | |
12499 | memcpy (p, temp, length); | |
12500 | ||
12501 | /* Switch back to the original section. */ | |
12502 | subseg_set (seg, subseg); | |
12503 | } | |
12504 | } | |
12505 | continue; | |
12506 | ||
12507 | case 'i': /* 16-bit unsigned immediate. */ | |
12508 | case 'j': /* 16-bit signed immediate. */ | |
12509 | *imm_reloc = BFD_RELOC_LO16; | |
12510 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12511 | { | |
12512 | int more; | |
12513 | offsetT minval, maxval; | |
12514 | ||
12515 | more = (insn + 1 < past | |
12516 | && strcmp (insn->name, insn[1].name) == 0); | |
12517 | ||
12518 | /* If the expression was written as an unsigned number, | |
12519 | only treat it as signed if there are no more | |
12520 | alternatives. */ | |
12521 | if (more | |
12522 | && *args == 'j' | |
12523 | && sizeof (imm_expr.X_add_number) <= 4 | |
12524 | && imm_expr.X_op == O_constant | |
12525 | && imm_expr.X_add_number < 0 | |
12526 | && imm_expr.X_unsigned | |
12527 | && HAVE_64BIT_GPRS) | |
12528 | break; | |
12529 | ||
12530 | /* For compatibility with older assemblers, we accept | |
12531 | 0x8000-0xffff as signed 16-bit numbers when only | |
12532 | signed numbers are allowed. */ | |
12533 | if (*args == 'i') | |
12534 | minval = 0, maxval = 0xffff; | |
12535 | else if (more) | |
12536 | minval = -0x8000, maxval = 0x7fff; | |
12537 | else | |
12538 | minval = -0x8000, maxval = 0xffff; | |
12539 | ||
12540 | if (imm_expr.X_op != O_constant | |
12541 | || imm_expr.X_add_number < minval | |
12542 | || imm_expr.X_add_number > maxval) | |
12543 | { | |
12544 | if (more) | |
12545 | break; | |
12546 | if (imm_expr.X_op == O_constant | |
12547 | || imm_expr.X_op == O_big) | |
12548 | as_bad (_("Expression out of range")); | |
12549 | } | |
12550 | } | |
12551 | s = expr_end; | |
12552 | continue; | |
12553 | ||
12554 | case 'o': /* 16-bit offset. */ | |
12555 | offset_reloc[0] = BFD_RELOC_LO16; | |
12556 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12557 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12558 | ||
12559 | /* Check whether there is only a single bracketed expression | |
12560 | left. If so, it must be the base register and the | |
12561 | constant must be zero. */ | |
12562 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12563 | { | |
12564 | offset_expr.X_op = O_constant; | |
12565 | offset_expr.X_add_number = 0; | |
12566 | continue; | |
12567 | } | |
12568 | ||
12569 | /* If this value won't fit into a 16 bit offset, then go | |
12570 | find a macro that will generate the 32 bit offset | |
12571 | code pattern. */ | |
12572 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12573 | && (offset_expr.X_op != O_constant | |
12574 | || offset_expr.X_add_number >= 0x8000 | |
12575 | || offset_expr.X_add_number < -0x8000)) | |
12576 | break; | |
12577 | ||
12578 | s = expr_end; | |
12579 | continue; | |
12580 | ||
12581 | case 'p': /* PC-relative offset. */ | |
12582 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12583 | my_getExpression (&offset_expr, s); | |
12584 | s = expr_end; | |
12585 | continue; | |
12586 | ||
12587 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12588 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12589 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12590 | && imm_expr.X_op == O_constant | |
12591 | && (imm_expr.X_add_number < 0 | |
12592 | || imm_expr.X_add_number >= 0x10000)) | |
12593 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12594 | (unsigned long) imm_expr.X_add_number); | |
12595 | s = expr_end; | |
12596 | continue; | |
12597 | ||
12598 | case 'a': /* 26-bit address. */ | |
12599 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12600 | my_getExpression (&offset_expr, s); | |
12601 | s = expr_end; | |
12602 | continue; | |
12603 | ||
12604 | case 'N': /* 3-bit branch condition code. */ | |
12605 | case 'M': /* 3-bit compare condition code. */ | |
12606 | rtype = RTYPE_CCC; | |
12607 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12608 | rtype |= RTYPE_FCC; | |
12609 | if (!reg_lookup (&s, rtype, ®no)) | |
12610 | break; | |
12611 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12612 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12613 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12614 | && (regno & 1) != 0) | |
12615 | as_warn (_("Condition code register should be even for %s, " | |
12616 | "was %d"), | |
12617 | str, regno); | |
12618 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12619 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12620 | && (regno & 3) != 0) | |
12621 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12622 | "was %d"), | |
12623 | str, regno); | |
12624 | if (*args == 'N') | |
12625 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12626 | else | |
12627 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12628 | continue; | |
12629 | ||
12630 | case 'H': | |
12631 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12632 | s += 2; | |
12633 | if (ISDIGIT (*s)) | |
12634 | { | |
12635 | c = 0; | |
12636 | do | |
12637 | { | |
12638 | c *= 10; | |
12639 | c += *s - '0'; | |
12640 | ++s; | |
12641 | } | |
12642 | while (ISDIGIT (*s)); | |
12643 | } | |
12644 | else | |
12645 | c = 8; /* Invalid sel value. */ | |
12646 | ||
12647 | if (c > 7) | |
12648 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12649 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12650 | continue; | |
12651 | ||
12652 | case 'e': | |
12653 | gas_assert (!mips_opts.micromips); | |
12654 | /* Must be at least one digit. */ | |
12655 | my_getExpression (&imm_expr, s); | |
12656 | check_absolute_expr (ip, &imm_expr); | |
12657 | ||
12658 | if ((unsigned long) imm_expr.X_add_number | |
12659 | > (unsigned long) OP_MASK_VECBYTE) | |
12660 | { | |
12661 | as_bad (_("bad byte vector index (%ld)"), | |
12662 | (long) imm_expr.X_add_number); | |
12663 | imm_expr.X_add_number = 0; | |
12664 | } | |
12665 | ||
12666 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12667 | imm_expr.X_op = O_absent; | |
12668 | s = expr_end; | |
12669 | continue; | |
12670 | ||
12671 | case '%': | |
12672 | gas_assert (!mips_opts.micromips); | |
12673 | my_getExpression (&imm_expr, s); | |
12674 | check_absolute_expr (ip, &imm_expr); | |
12675 | ||
12676 | if ((unsigned long) imm_expr.X_add_number | |
12677 | > (unsigned long) OP_MASK_VECALIGN) | |
12678 | { | |
12679 | as_bad (_("bad byte vector index (%ld)"), | |
12680 | (long) imm_expr.X_add_number); | |
12681 | imm_expr.X_add_number = 0; | |
12682 | } | |
12683 | ||
12684 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12685 | imm_expr.X_op = O_absent; | |
12686 | s = expr_end; | |
12687 | continue; | |
12688 | ||
12689 | case 'm': /* Opcode extension character. */ | |
12690 | gas_assert (mips_opts.micromips); | |
12691 | c = *++args; | |
12692 | switch (c) | |
12693 | { | |
12694 | case 'r': | |
12695 | if (strncmp (s, "$pc", 3) == 0) | |
12696 | { | |
12697 | s += 3; | |
12698 | continue; | |
12699 | } | |
12700 | break; | |
12701 | ||
12702 | case 'a': | |
12703 | case 'b': | |
12704 | case 'c': | |
12705 | case 'd': | |
12706 | case 'e': | |
12707 | case 'f': | |
12708 | case 'g': | |
12709 | case 'h': | |
12710 | case 'i': | |
12711 | case 'j': | |
12712 | case 'l': | |
12713 | case 'm': | |
12714 | case 'n': | |
12715 | case 'p': | |
12716 | case 'q': | |
12717 | case 's': | |
12718 | case 't': | |
12719 | case 'x': | |
12720 | case 'y': | |
12721 | case 'z': | |
12722 | s_reset = s; | |
12723 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12724 | if (regno == AT && mips_opts.at) | |
12725 | { | |
12726 | if (mips_opts.at == ATREG) | |
12727 | as_warn (_("Used $at without \".set noat\"")); | |
12728 | else | |
12729 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12730 | regno, mips_opts.at); | |
12731 | } | |
12732 | if (!ok) | |
12733 | { | |
12734 | if (c == 'c') | |
12735 | { | |
12736 | gas_assert (args[1] == ','); | |
12737 | regno = lastregno; | |
12738 | ++args; | |
12739 | } | |
12740 | else if (c == 't') | |
12741 | { | |
12742 | gas_assert (args[1] == ','); | |
12743 | ++args; | |
12744 | continue; /* Nothing to do. */ | |
12745 | } | |
12746 | else | |
12747 | break; | |
12748 | } | |
12749 | ||
12750 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12751 | { | |
12752 | if (regno == lastregno) | |
12753 | { | |
12754 | insn_error | |
12755 | = _("Source and destination must be different"); | |
12756 | continue; | |
12757 | } | |
12758 | if (regno == 31 && lastregno == 0xffffffff) | |
12759 | { | |
12760 | insn_error | |
12761 | = _("A destination register must be supplied"); | |
12762 | continue; | |
12763 | } | |
12764 | } | |
12765 | ||
12766 | if (*s == ' ') | |
12767 | ++s; | |
12768 | if (args[1] != *s) | |
12769 | { | |
12770 | if (c == 'e') | |
12771 | { | |
12772 | gas_assert (args[1] == ','); | |
12773 | regno = lastregno; | |
12774 | s = s_reset; | |
12775 | ++args; | |
12776 | } | |
12777 | else if (c == 't') | |
12778 | { | |
12779 | gas_assert (args[1] == ','); | |
12780 | s = s_reset; | |
12781 | ++args; | |
12782 | continue; /* Nothing to do. */ | |
12783 | } | |
12784 | } | |
12785 | ||
12786 | /* Make sure regno is the same as lastregno. */ | |
12787 | if (c == 't' && regno != lastregno) | |
12788 | break; | |
12789 | ||
12790 | /* Make sure regno is the same as destregno. */ | |
12791 | if (c == 'x' && regno != destregno) | |
12792 | break; | |
12793 | ||
12794 | /* We need to save regno, before regno maps to the | |
12795 | microMIPS register encoding. */ | |
12796 | lastregno = regno; | |
12797 | ||
12798 | if (c == 'f') | |
12799 | destregno = regno; | |
12800 | ||
12801 | switch (c) | |
12802 | { | |
12803 | case 'a': | |
12804 | if (regno != GP) | |
12805 | regno = ILLEGAL_REG; | |
12806 | break; | |
12807 | ||
12808 | case 'b': | |
12809 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12810 | break; | |
12811 | ||
12812 | case 'c': | |
12813 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12814 | break; | |
12815 | ||
12816 | case 'd': | |
12817 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12818 | break; | |
12819 | ||
12820 | case 'e': | |
12821 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12822 | break; | |
12823 | ||
12824 | case 'f': | |
12825 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12826 | break; | |
12827 | ||
12828 | case 'g': | |
12829 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12830 | break; | |
12831 | ||
12832 | case 'h': | |
12833 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12834 | break; | |
12835 | ||
12836 | case 'i': | |
12837 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12838 | { | |
12839 | case 4: | |
12840 | if (regno == 21) | |
12841 | regno = 3; | |
12842 | else if (regno == 22) | |
12843 | regno = 4; | |
12844 | else if (regno == 5) | |
12845 | regno = 5; | |
12846 | else if (regno == 6) | |
12847 | regno = 6; | |
12848 | else if (regno == 7) | |
12849 | regno = 7; | |
12850 | else | |
12851 | regno = ILLEGAL_REG; | |
12852 | break; | |
12853 | ||
12854 | case 5: | |
12855 | if (regno == 6) | |
12856 | regno = 0; | |
12857 | else if (regno == 7) | |
12858 | regno = 1; | |
12859 | else | |
12860 | regno = ILLEGAL_REG; | |
12861 | break; | |
12862 | ||
12863 | case 6: | |
12864 | if (regno == 7) | |
12865 | regno = 2; | |
12866 | else | |
12867 | regno = ILLEGAL_REG; | |
12868 | break; | |
12869 | ||
12870 | default: | |
12871 | regno = ILLEGAL_REG; | |
12872 | break; | |
12873 | } | |
12874 | break; | |
12875 | ||
12876 | case 'l': | |
12877 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12878 | break; | |
12879 | ||
12880 | case 'm': | |
12881 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12882 | break; | |
12883 | ||
12884 | case 'n': | |
12885 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12886 | break; | |
12887 | ||
12888 | case 'q': | |
12889 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12890 | break; | |
12891 | ||
12892 | case 's': | |
12893 | if (regno != SP) | |
12894 | regno = ILLEGAL_REG; | |
12895 | break; | |
12896 | ||
12897 | case 'y': | |
12898 | if (regno != 31) | |
12899 | regno = ILLEGAL_REG; | |
12900 | break; | |
12901 | ||
12902 | case 'z': | |
12903 | if (regno != ZERO) | |
12904 | regno = ILLEGAL_REG; | |
12905 | break; | |
12906 | ||
12907 | case 'j': /* Do nothing. */ | |
12908 | case 'p': | |
12909 | case 't': | |
12910 | case 'x': | |
12911 | break; | |
12912 | ||
12913 | default: | |
b37df7c4 | 12914 | abort (); |
df58fc94 RS |
12915 | } |
12916 | ||
12917 | if (regno == ILLEGAL_REG) | |
12918 | break; | |
12919 | ||
12920 | switch (c) | |
12921 | { | |
12922 | case 'b': | |
12923 | INSERT_OPERAND (1, MB, *ip, regno); | |
12924 | break; | |
12925 | ||
12926 | case 'c': | |
12927 | INSERT_OPERAND (1, MC, *ip, regno); | |
12928 | break; | |
12929 | ||
12930 | case 'd': | |
12931 | INSERT_OPERAND (1, MD, *ip, regno); | |
12932 | break; | |
12933 | ||
12934 | case 'e': | |
12935 | INSERT_OPERAND (1, ME, *ip, regno); | |
12936 | break; | |
12937 | ||
12938 | case 'f': | |
12939 | INSERT_OPERAND (1, MF, *ip, regno); | |
12940 | break; | |
12941 | ||
12942 | case 'g': | |
12943 | INSERT_OPERAND (1, MG, *ip, regno); | |
12944 | break; | |
12945 | ||
12946 | case 'h': | |
12947 | INSERT_OPERAND (1, MH, *ip, regno); | |
12948 | break; | |
12949 | ||
12950 | case 'i': | |
12951 | INSERT_OPERAND (1, MI, *ip, regno); | |
12952 | break; | |
12953 | ||
12954 | case 'j': | |
12955 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12956 | break; | |
12957 | ||
12958 | case 'l': | |
12959 | INSERT_OPERAND (1, ML, *ip, regno); | |
12960 | break; | |
12961 | ||
12962 | case 'm': | |
12963 | INSERT_OPERAND (1, MM, *ip, regno); | |
12964 | break; | |
12965 | ||
12966 | case 'n': | |
12967 | INSERT_OPERAND (1, MN, *ip, regno); | |
12968 | break; | |
12969 | ||
12970 | case 'p': | |
12971 | INSERT_OPERAND (1, MP, *ip, regno); | |
12972 | break; | |
12973 | ||
12974 | case 'q': | |
12975 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12976 | break; | |
12977 | ||
12978 | case 'a': /* Do nothing. */ | |
12979 | case 's': /* Do nothing. */ | |
12980 | case 't': /* Do nothing. */ | |
12981 | case 'x': /* Do nothing. */ | |
12982 | case 'y': /* Do nothing. */ | |
12983 | case 'z': /* Do nothing. */ | |
12984 | break; | |
12985 | ||
12986 | default: | |
b37df7c4 | 12987 | abort (); |
df58fc94 RS |
12988 | } |
12989 | continue; | |
12990 | ||
12991 | case 'A': | |
12992 | { | |
12993 | bfd_reloc_code_real_type r[3]; | |
12994 | expressionS ep; | |
12995 | int imm; | |
12996 | ||
12997 | /* Check whether there is only a single bracketed | |
12998 | expression left. If so, it must be the base register | |
12999 | and the constant must be zero. */ | |
13000 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13001 | { | |
13002 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13003 | continue; | |
13004 | } | |
13005 | ||
13006 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13007 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13008 | break; | |
13009 | ||
13010 | imm = ep.X_add_number >> 2; | |
13011 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13012 | } | |
13013 | s = expr_end; | |
13014 | continue; | |
13015 | ||
13016 | case 'B': | |
13017 | { | |
13018 | bfd_reloc_code_real_type r[3]; | |
13019 | expressionS ep; | |
13020 | int imm; | |
13021 | ||
13022 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13023 | || ep.X_op != O_constant) | |
13024 | break; | |
13025 | ||
13026 | for (imm = 0; imm < 8; imm++) | |
13027 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13028 | break; | |
13029 | if (imm >= 8) | |
13030 | break; | |
13031 | ||
13032 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13033 | } | |
13034 | s = expr_end; | |
13035 | continue; | |
13036 | ||
13037 | case 'C': | |
13038 | { | |
13039 | bfd_reloc_code_real_type r[3]; | |
13040 | expressionS ep; | |
13041 | int imm; | |
13042 | ||
13043 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13044 | || ep.X_op != O_constant) | |
13045 | break; | |
13046 | ||
13047 | for (imm = 0; imm < 16; imm++) | |
13048 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13049 | break; | |
13050 | if (imm >= 16) | |
13051 | break; | |
13052 | ||
13053 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13054 | } | |
13055 | s = expr_end; | |
13056 | continue; | |
13057 | ||
13058 | case 'D': /* pc relative offset */ | |
13059 | case 'E': /* pc relative offset */ | |
13060 | my_getExpression (&offset_expr, s); | |
13061 | if (offset_expr.X_op == O_register) | |
13062 | break; | |
13063 | ||
40209cad MR |
13064 | if (!forced_insn_length) |
13065 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13066 | else if (c == 'D') | |
13067 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13068 | else | |
13069 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13070 | s = expr_end; |
13071 | continue; | |
13072 | ||
13073 | case 'F': | |
13074 | { | |
13075 | bfd_reloc_code_real_type r[3]; | |
13076 | expressionS ep; | |
13077 | int imm; | |
13078 | ||
13079 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13080 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13081 | break; | |
13082 | ||
13083 | imm = ep.X_add_number; | |
13084 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13085 | } | |
13086 | s = expr_end; | |
13087 | continue; | |
13088 | ||
13089 | case 'G': | |
13090 | { | |
13091 | bfd_reloc_code_real_type r[3]; | |
13092 | expressionS ep; | |
13093 | int imm; | |
13094 | ||
13095 | /* Check whether there is only a single bracketed | |
13096 | expression left. If so, it must be the base register | |
13097 | and the constant must be zero. */ | |
13098 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13099 | { | |
13100 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13101 | continue; | |
13102 | } | |
13103 | ||
13104 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13105 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13106 | break; | |
13107 | ||
13108 | imm = ep.X_add_number & 15; | |
13109 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13110 | } | |
13111 | s = expr_end; | |
13112 | continue; | |
13113 | ||
13114 | case 'H': | |
13115 | { | |
13116 | bfd_reloc_code_real_type r[3]; | |
13117 | expressionS ep; | |
13118 | int imm; | |
13119 | ||
13120 | /* Check whether there is only a single bracketed | |
13121 | expression left. If so, it must be the base register | |
13122 | and the constant must be zero. */ | |
13123 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13124 | { | |
13125 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13126 | continue; | |
13127 | } | |
13128 | ||
13129 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13130 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13131 | break; | |
13132 | ||
13133 | imm = ep.X_add_number >> 1; | |
13134 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13135 | } | |
13136 | s = expr_end; | |
13137 | continue; | |
13138 | ||
13139 | case 'I': | |
13140 | { | |
13141 | bfd_reloc_code_real_type r[3]; | |
13142 | expressionS ep; | |
13143 | int imm; | |
13144 | ||
13145 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13146 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13147 | break; | |
13148 | ||
13149 | imm = ep.X_add_number & 127; | |
13150 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13151 | } | |
13152 | s = expr_end; | |
13153 | continue; | |
13154 | ||
13155 | case 'J': | |
13156 | { | |
13157 | bfd_reloc_code_real_type r[3]; | |
13158 | expressionS ep; | |
13159 | int imm; | |
13160 | ||
13161 | /* Check whether there is only a single bracketed | |
13162 | expression left. If so, it must be the base register | |
13163 | and the constant must be zero. */ | |
13164 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13165 | { | |
13166 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13167 | continue; | |
13168 | } | |
13169 | ||
13170 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13171 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13172 | break; | |
13173 | ||
13174 | imm = ep.X_add_number >> 2; | |
13175 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13176 | } | |
13177 | s = expr_end; | |
13178 | continue; | |
13179 | ||
13180 | case 'L': | |
13181 | { | |
13182 | bfd_reloc_code_real_type r[3]; | |
13183 | expressionS ep; | |
13184 | int imm; | |
13185 | ||
13186 | /* Check whether there is only a single bracketed | |
13187 | expression left. If so, it must be the base register | |
13188 | and the constant must be zero. */ | |
13189 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13190 | { | |
13191 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13192 | continue; | |
13193 | } | |
13194 | ||
13195 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13196 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13197 | break; | |
13198 | ||
13199 | imm = ep.X_add_number; | |
13200 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13201 | } | |
13202 | s = expr_end; | |
13203 | continue; | |
13204 | ||
13205 | case 'M': | |
13206 | { | |
13207 | bfd_reloc_code_real_type r[3]; | |
13208 | expressionS ep; | |
13209 | int imm; | |
13210 | ||
13211 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13212 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13213 | break; | |
13214 | ||
13215 | imm = ep.X_add_number & 7; | |
13216 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13217 | } | |
13218 | s = expr_end; | |
13219 | continue; | |
13220 | ||
13221 | case 'N': /* Register list for lwm and swm. */ | |
13222 | { | |
13223 | /* A comma-separated list of registers and/or | |
13224 | dash-separated contiguous ranges including | |
13225 | both ra and a set of one or more registers | |
13226 | starting at s0 up to s3 which have to be | |
13227 | consecutive, e.g.: | |
13228 | ||
13229 | s0, ra | |
13230 | s0, s1, ra, s2, s3 | |
13231 | s0-s2, ra | |
13232 | ||
13233 | and any permutations of these. */ | |
13234 | unsigned int reglist; | |
13235 | int imm; | |
13236 | ||
13237 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13238 | break; | |
13239 | ||
13240 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13241 | break; | |
13242 | ||
13243 | reglist = (reglist >> 17) & 7; | |
13244 | reglist += 1; | |
13245 | if ((reglist & -reglist) != reglist) | |
13246 | break; | |
252b5132 | 13247 | |
df58fc94 RS |
13248 | imm = ffs (reglist) - 1; |
13249 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13250 | } | |
13251 | continue; | |
252b5132 | 13252 | |
df58fc94 RS |
13253 | case 'O': /* sdbbp 4-bit code. */ |
13254 | { | |
13255 | bfd_reloc_code_real_type r[3]; | |
13256 | expressionS ep; | |
13257 | int imm; | |
13258 | ||
13259 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13260 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13261 | break; | |
13262 | ||
13263 | imm = ep.X_add_number; | |
13264 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13265 | } |
df58fc94 RS |
13266 | s = expr_end; |
13267 | continue; | |
252b5132 | 13268 | |
df58fc94 RS |
13269 | case 'P': |
13270 | { | |
13271 | bfd_reloc_code_real_type r[3]; | |
13272 | expressionS ep; | |
13273 | int imm; | |
5e0116d5 | 13274 | |
df58fc94 RS |
13275 | if (my_getSmallExpression (&ep, r, s) > 0 |
13276 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13277 | break; | |
5e0116d5 | 13278 | |
df58fc94 RS |
13279 | imm = ep.X_add_number >> 2; |
13280 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13281 | } | |
13282 | s = expr_end; | |
13283 | continue; | |
5e0116d5 | 13284 | |
df58fc94 RS |
13285 | case 'Q': |
13286 | { | |
13287 | bfd_reloc_code_real_type r[3]; | |
13288 | expressionS ep; | |
13289 | int imm; | |
5e0116d5 | 13290 | |
df58fc94 RS |
13291 | if (my_getSmallExpression (&ep, r, s) > 0 |
13292 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13293 | break; | |
252b5132 | 13294 | |
df58fc94 RS |
13295 | imm = ep.X_add_number >> 2; |
13296 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13297 | } | |
13298 | s = expr_end; | |
13299 | continue; | |
4614d845 | 13300 | |
df58fc94 RS |
13301 | case 'U': |
13302 | { | |
13303 | bfd_reloc_code_real_type r[3]; | |
13304 | expressionS ep; | |
13305 | int imm; | |
13306 | ||
13307 | /* Check whether there is only a single bracketed | |
13308 | expression left. If so, it must be the base register | |
13309 | and the constant must be zero. */ | |
13310 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13311 | { | |
13312 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13313 | continue; | |
13314 | } | |
13315 | ||
13316 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13317 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13318 | break; | |
13319 | ||
13320 | imm = ep.X_add_number >> 2; | |
13321 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13322 | } | |
13323 | s = expr_end; | |
5e0116d5 | 13324 | continue; |
252b5132 | 13325 | |
df58fc94 RS |
13326 | case 'W': |
13327 | { | |
13328 | bfd_reloc_code_real_type r[3]; | |
13329 | expressionS ep; | |
13330 | int imm; | |
252b5132 | 13331 | |
df58fc94 RS |
13332 | if (my_getSmallExpression (&ep, r, s) > 0 |
13333 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13334 | break; | |
252b5132 | 13335 | |
df58fc94 RS |
13336 | imm = ep.X_add_number >> 2; |
13337 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13338 | } | |
13339 | s = expr_end; | |
13340 | continue; | |
252b5132 | 13341 | |
df58fc94 RS |
13342 | case 'X': |
13343 | { | |
13344 | bfd_reloc_code_real_type r[3]; | |
13345 | expressionS ep; | |
13346 | int imm; | |
252b5132 | 13347 | |
df58fc94 RS |
13348 | if (my_getSmallExpression (&ep, r, s) > 0 |
13349 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13350 | break; | |
252b5132 | 13351 | |
df58fc94 RS |
13352 | imm = ep.X_add_number; |
13353 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13354 | } | |
13355 | s = expr_end; | |
13356 | continue; | |
252b5132 | 13357 | |
df58fc94 RS |
13358 | case 'Y': |
13359 | { | |
13360 | bfd_reloc_code_real_type r[3]; | |
13361 | expressionS ep; | |
13362 | int imm; | |
156c2f8b | 13363 | |
df58fc94 RS |
13364 | if (my_getSmallExpression (&ep, r, s) > 0 |
13365 | || expr_const_in_range (&ep, -2, 2, 2) | |
13366 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13367 | break; | |
156c2f8b | 13368 | |
df58fc94 RS |
13369 | imm = ep.X_add_number >> 2; |
13370 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13371 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13372 | } | |
13373 | s = expr_end; | |
13374 | continue; | |
60b63b72 | 13375 | |
df58fc94 RS |
13376 | case 'Z': |
13377 | { | |
13378 | bfd_reloc_code_real_type r[3]; | |
13379 | expressionS ep; | |
13380 | ||
13381 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13382 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13383 | break; | |
13384 | } | |
13385 | s = expr_end; | |
13386 | continue; | |
13387 | ||
13388 | default: | |
13389 | as_bad (_("Internal error: bad microMIPS opcode " | |
13390 | "(unknown extension operand type `m%c'): %s %s"), | |
13391 | *args, insn->name, insn->args); | |
13392 | /* Further processing is fruitless. */ | |
13393 | return; | |
60b63b72 | 13394 | } |
df58fc94 | 13395 | break; |
60b63b72 | 13396 | |
df58fc94 RS |
13397 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13398 | gas_assert (mips_opts.micromips); | |
13399 | { | |
13400 | /* A comma-separated list of registers and/or | |
13401 | dash-separated contiguous ranges including | |
13402 | at least one of ra and a set of one or more | |
13403 | registers starting at s0 up to s7 and then | |
13404 | s8 which have to be consecutive, e.g.: | |
13405 | ||
13406 | ra | |
13407 | s0 | |
13408 | ra, s0, s1, s2 | |
13409 | s0-s8 | |
13410 | s0-s5, ra | |
13411 | ||
13412 | and any permutations of these. */ | |
13413 | unsigned int reglist; | |
13414 | int imm; | |
13415 | int ra; | |
13416 | ||
13417 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13418 | break; | |
13419 | ||
13420 | if ((reglist & 0x3f00ffff) != 0) | |
13421 | break; | |
13422 | ||
13423 | ra = (reglist >> 27) & 0x10; | |
13424 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13425 | reglist += 1; | |
13426 | if ((reglist & -reglist) != reglist) | |
13427 | break; | |
13428 | ||
13429 | imm = (ffs (reglist) - 1) | ra; | |
13430 | INSERT_OPERAND (1, RT, *ip, imm); | |
13431 | imm_expr.X_op = O_absent; | |
13432 | } | |
60b63b72 RS |
13433 | continue; |
13434 | ||
df58fc94 RS |
13435 | case '|': /* 4-bit trap code. */ |
13436 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13437 | my_getExpression (&imm_expr, s); |
13438 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13439 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13440 | > MICROMIPSOP_MASK_TRAP) |
13441 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13442 | (unsigned long) imm_expr.X_add_number, | |
13443 | ip->insn_mo->name); | |
13444 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13445 | imm_expr.X_op = O_absent; |
13446 | s = expr_end; | |
13447 | continue; | |
13448 | ||
252b5132 | 13449 | default: |
f71d0d44 | 13450 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13451 | abort (); |
252b5132 RH |
13452 | } |
13453 | break; | |
13454 | } | |
13455 | /* Args don't match. */ | |
df58fc94 RS |
13456 | s = argsStart; |
13457 | insn_error = _("Illegal operands"); | |
13458 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13459 | { |
13460 | ++insn; | |
252b5132 RH |
13461 | continue; |
13462 | } | |
df58fc94 RS |
13463 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13464 | { | |
13465 | gas_assert (firstinsn); | |
13466 | need_delay_slot_ok = FALSE; | |
13467 | past = insn + 1; | |
13468 | insn = firstinsn; | |
13469 | continue; | |
13470 | } | |
252b5132 RH |
13471 | return; |
13472 | } | |
13473 | } | |
13474 | ||
0499d65b TS |
13475 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13476 | ||
252b5132 RH |
13477 | /* This routine assembles an instruction into its binary format when |
13478 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13479 | global variables imm_reloc or offset_reloc to the type of relocation |
13480 | to do if one of the operands is an address expression. It also sets | |
13481 | forced_insn_length to the resulting instruction size in bytes if the | |
13482 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13483 | |
13484 | static void | |
17a2f251 | 13485 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13486 | { |
13487 | char *s; | |
13488 | const char *args; | |
13489 | struct mips_opcode *insn; | |
13490 | char *argsstart; | |
13491 | unsigned int regno; | |
13492 | unsigned int lastregno = 0; | |
13493 | char *s_reset; | |
d6f16593 | 13494 | size_t i; |
252b5132 RH |
13495 | |
13496 | insn_error = NULL; | |
13497 | ||
df58fc94 | 13498 | forced_insn_length = 0; |
252b5132 | 13499 | |
3882b010 | 13500 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13501 | ; |
13502 | switch (*s) | |
13503 | { | |
13504 | case '\0': | |
13505 | break; | |
13506 | ||
13507 | case ' ': | |
13508 | *s++ = '\0'; | |
13509 | break; | |
13510 | ||
13511 | case '.': | |
13512 | if (s[1] == 't' && s[2] == ' ') | |
13513 | { | |
13514 | *s = '\0'; | |
df58fc94 | 13515 | forced_insn_length = 2; |
252b5132 RH |
13516 | s += 3; |
13517 | break; | |
13518 | } | |
13519 | else if (s[1] == 'e' && s[2] == ' ') | |
13520 | { | |
13521 | *s = '\0'; | |
df58fc94 | 13522 | forced_insn_length = 4; |
252b5132 RH |
13523 | s += 3; |
13524 | break; | |
13525 | } | |
13526 | /* Fall through. */ | |
13527 | default: | |
13528 | insn_error = _("unknown opcode"); | |
13529 | return; | |
13530 | } | |
13531 | ||
df58fc94 RS |
13532 | if (mips_opts.noautoextend && !forced_insn_length) |
13533 | forced_insn_length = 2; | |
252b5132 RH |
13534 | |
13535 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13536 | { | |
13537 | insn_error = _("unrecognized opcode"); | |
13538 | return; | |
13539 | } | |
13540 | ||
13541 | argsstart = s; | |
13542 | for (;;) | |
13543 | { | |
9b3f89ee TS |
13544 | bfd_boolean ok; |
13545 | ||
9c2799c2 | 13546 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13547 | |
037b32b9 | 13548 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13549 | if (! ok) |
13550 | { | |
13551 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13552 | && strcmp (insn->name, insn[1].name) == 0) | |
13553 | { | |
13554 | ++insn; | |
13555 | continue; | |
13556 | } | |
13557 | else | |
13558 | { | |
13559 | if (!insn_error) | |
13560 | { | |
13561 | static char buf[100]; | |
13562 | sprintf (buf, | |
7bd942df | 13563 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13564 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13565 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13566 | insn_error = buf; | |
13567 | } | |
13568 | return; | |
13569 | } | |
13570 | } | |
13571 | ||
1e915849 | 13572 | create_insn (ip, insn); |
252b5132 | 13573 | imm_expr.X_op = O_absent; |
f6688943 TS |
13574 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13575 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13576 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13577 | imm2_expr.X_op = O_absent; |
252b5132 | 13578 | offset_expr.X_op = O_absent; |
f6688943 TS |
13579 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13580 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13581 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13582 | for (args = insn->args; 1; ++args) |
13583 | { | |
13584 | int c; | |
13585 | ||
13586 | if (*s == ' ') | |
13587 | ++s; | |
13588 | ||
13589 | /* In this switch statement we call break if we did not find | |
13590 | a match, continue if we did find a match, or return if we | |
13591 | are done. */ | |
13592 | ||
13593 | c = *args; | |
13594 | switch (c) | |
13595 | { | |
13596 | case '\0': | |
13597 | if (*s == '\0') | |
13598 | { | |
b886a2ab RS |
13599 | offsetT value; |
13600 | ||
252b5132 RH |
13601 | /* Stuff the immediate value in now, if we can. */ |
13602 | if (imm_expr.X_op == O_constant | |
f6688943 | 13603 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13604 | && insn->pinfo != INSN_MACRO |
13605 | && calculate_reloc (*offset_reloc, | |
13606 | imm_expr.X_add_number, &value)) | |
252b5132 | 13607 | { |
c4e7957c | 13608 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13609 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13610 | &ip->insn_opcode); |
252b5132 | 13611 | imm_expr.X_op = O_absent; |
f6688943 | 13612 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13613 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13614 | } |
13615 | ||
13616 | return; | |
13617 | } | |
13618 | break; | |
13619 | ||
13620 | case ',': | |
13621 | if (*s++ == c) | |
13622 | continue; | |
13623 | s--; | |
13624 | switch (*++args) | |
13625 | { | |
13626 | case 'v': | |
bf12938e | 13627 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13628 | continue; |
13629 | case 'w': | |
bf12938e | 13630 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13631 | continue; |
13632 | } | |
13633 | break; | |
13634 | ||
13635 | case '(': | |
13636 | case ')': | |
13637 | if (*s++ == c) | |
13638 | continue; | |
13639 | break; | |
13640 | ||
13641 | case 'v': | |
13642 | case 'w': | |
13643 | if (s[0] != '$') | |
13644 | { | |
13645 | if (c == 'v') | |
bf12938e | 13646 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13647 | else |
bf12938e | 13648 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13649 | ++args; |
13650 | continue; | |
13651 | } | |
13652 | /* Fall through. */ | |
13653 | case 'x': | |
13654 | case 'y': | |
13655 | case 'z': | |
13656 | case 'Z': | |
13657 | case '0': | |
13658 | case 'S': | |
13659 | case 'R': | |
13660 | case 'X': | |
13661 | case 'Y': | |
707bfff6 TS |
13662 | s_reset = s; |
13663 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13664 | { |
707bfff6 | 13665 | if (c == 'v' || c == 'w') |
85b51719 | 13666 | { |
707bfff6 | 13667 | if (c == 'v') |
a9e24354 | 13668 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13669 | else |
a9e24354 | 13670 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13671 | ++args; |
13672 | continue; | |
85b51719 | 13673 | } |
707bfff6 | 13674 | break; |
252b5132 RH |
13675 | } |
13676 | ||
13677 | if (*s == ' ') | |
13678 | ++s; | |
13679 | if (args[1] != *s) | |
13680 | { | |
13681 | if (c == 'v' || c == 'w') | |
13682 | { | |
13683 | regno = mips16_to_32_reg_map[lastregno]; | |
13684 | s = s_reset; | |
f9419b05 | 13685 | ++args; |
252b5132 RH |
13686 | } |
13687 | } | |
13688 | ||
13689 | switch (c) | |
13690 | { | |
13691 | case 'x': | |
13692 | case 'y': | |
13693 | case 'z': | |
13694 | case 'v': | |
13695 | case 'w': | |
13696 | case 'Z': | |
13697 | regno = mips32_to_16_reg_map[regno]; | |
13698 | break; | |
13699 | ||
13700 | case '0': | |
13701 | if (regno != 0) | |
13702 | regno = ILLEGAL_REG; | |
13703 | break; | |
13704 | ||
13705 | case 'S': | |
13706 | if (regno != SP) | |
13707 | regno = ILLEGAL_REG; | |
13708 | break; | |
13709 | ||
13710 | case 'R': | |
13711 | if (regno != RA) | |
13712 | regno = ILLEGAL_REG; | |
13713 | break; | |
13714 | ||
13715 | case 'X': | |
13716 | case 'Y': | |
741fe287 MR |
13717 | if (regno == AT && mips_opts.at) |
13718 | { | |
13719 | if (mips_opts.at == ATREG) | |
13720 | as_warn (_("used $at without \".set noat\"")); | |
13721 | else | |
13722 | as_warn (_("used $%u with \".set at=$%u\""), | |
13723 | regno, mips_opts.at); | |
13724 | } | |
252b5132 RH |
13725 | break; |
13726 | ||
13727 | default: | |
b37df7c4 | 13728 | abort (); |
252b5132 RH |
13729 | } |
13730 | ||
13731 | if (regno == ILLEGAL_REG) | |
13732 | break; | |
13733 | ||
13734 | switch (c) | |
13735 | { | |
13736 | case 'x': | |
13737 | case 'v': | |
bf12938e | 13738 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13739 | break; |
13740 | case 'y': | |
13741 | case 'w': | |
bf12938e | 13742 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13743 | break; |
13744 | case 'z': | |
bf12938e | 13745 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13746 | break; |
13747 | case 'Z': | |
bf12938e | 13748 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13749 | case '0': |
13750 | case 'S': | |
13751 | case 'R': | |
13752 | break; | |
13753 | case 'X': | |
bf12938e | 13754 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13755 | break; |
13756 | case 'Y': | |
13757 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13758 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13759 | break; |
13760 | default: | |
b37df7c4 | 13761 | abort (); |
252b5132 RH |
13762 | } |
13763 | ||
13764 | lastregno = regno; | |
13765 | continue; | |
13766 | ||
13767 | case 'P': | |
13768 | if (strncmp (s, "$pc", 3) == 0) | |
13769 | { | |
13770 | s += 3; | |
13771 | continue; | |
13772 | } | |
13773 | break; | |
13774 | ||
252b5132 RH |
13775 | case '5': |
13776 | case 'H': | |
13777 | case 'W': | |
13778 | case 'D': | |
13779 | case 'j': | |
252b5132 RH |
13780 | case 'V': |
13781 | case 'C': | |
13782 | case 'U': | |
13783 | case 'k': | |
13784 | case 'K': | |
d6f16593 MR |
13785 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13786 | if (i > 0) | |
252b5132 | 13787 | { |
d6f16593 | 13788 | if (imm_expr.X_op != O_constant) |
252b5132 | 13789 | { |
df58fc94 | 13790 | forced_insn_length = 4; |
5c04167a | 13791 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13792 | } |
d6f16593 MR |
13793 | else |
13794 | { | |
13795 | /* We need to relax this instruction. */ | |
13796 | *offset_reloc = *imm_reloc; | |
13797 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13798 | } | |
13799 | s = expr_end; | |
13800 | continue; | |
252b5132 | 13801 | } |
d6f16593 MR |
13802 | *imm_reloc = BFD_RELOC_UNUSED; |
13803 | /* Fall through. */ | |
13804 | case '<': | |
13805 | case '>': | |
13806 | case '[': | |
13807 | case ']': | |
13808 | case '4': | |
13809 | case '8': | |
13810 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13811 | if (imm_expr.X_op == O_register) |
13812 | { | |
13813 | /* What we thought was an expression turned out to | |
13814 | be a register. */ | |
13815 | ||
13816 | if (s[0] == '(' && args[1] == '(') | |
13817 | { | |
13818 | /* It looks like the expression was omitted | |
13819 | before a register indirection, which means | |
13820 | that the expression is implicitly zero. We | |
13821 | still set up imm_expr, so that we handle | |
13822 | explicit extensions correctly. */ | |
13823 | imm_expr.X_op = O_constant; | |
13824 | imm_expr.X_add_number = 0; | |
f6688943 | 13825 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13826 | continue; |
13827 | } | |
13828 | ||
13829 | break; | |
13830 | } | |
13831 | ||
13832 | /* We need to relax this instruction. */ | |
f6688943 | 13833 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13834 | s = expr_end; |
13835 | continue; | |
13836 | ||
13837 | case 'p': | |
13838 | case 'q': | |
13839 | case 'A': | |
13840 | case 'B': | |
13841 | case 'E': | |
13842 | /* We use offset_reloc rather than imm_reloc for the PC | |
13843 | relative operands. This lets macros with both | |
13844 | immediate and address operands work correctly. */ | |
13845 | my_getExpression (&offset_expr, s); | |
13846 | ||
13847 | if (offset_expr.X_op == O_register) | |
13848 | break; | |
13849 | ||
13850 | /* We need to relax this instruction. */ | |
f6688943 | 13851 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13852 | s = expr_end; |
13853 | continue; | |
13854 | ||
13855 | case '6': /* break code */ | |
13856 | my_getExpression (&imm_expr, s); | |
13857 | check_absolute_expr (ip, &imm_expr); | |
13858 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13859 | as_warn (_("Invalid value for `%s' (%lu)"), |
13860 | ip->insn_mo->name, | |
13861 | (unsigned long) imm_expr.X_add_number); | |
13862 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13863 | imm_expr.X_op = O_absent; |
13864 | s = expr_end; | |
13865 | continue; | |
13866 | ||
13867 | case 'a': /* 26 bit address */ | |
13868 | my_getExpression (&offset_expr, s); | |
13869 | s = expr_end; | |
f6688943 | 13870 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13871 | ip->insn_opcode <<= 16; |
13872 | continue; | |
13873 | ||
13874 | case 'l': /* register list for entry macro */ | |
13875 | case 'L': /* register list for exit macro */ | |
13876 | { | |
13877 | int mask; | |
13878 | ||
13879 | if (c == 'l') | |
13880 | mask = 0; | |
13881 | else | |
13882 | mask = 7 << 3; | |
13883 | while (*s != '\0') | |
13884 | { | |
707bfff6 | 13885 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13886 | |
13887 | while (*s == ' ' || *s == ',') | |
13888 | ++s; | |
707bfff6 | 13889 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13890 | freg = 0; |
707bfff6 TS |
13891 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13892 | freg = 1; | |
252b5132 RH |
13893 | else |
13894 | { | |
707bfff6 TS |
13895 | as_bad (_("can't parse register list")); |
13896 | break; | |
252b5132 RH |
13897 | } |
13898 | if (*s == ' ') | |
13899 | ++s; | |
13900 | if (*s != '-') | |
13901 | reg2 = reg1; | |
13902 | else | |
13903 | { | |
13904 | ++s; | |
707bfff6 TS |
13905 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13906 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13907 | { |
707bfff6 TS |
13908 | as_bad (_("invalid register list")); |
13909 | break; | |
252b5132 RH |
13910 | } |
13911 | } | |
13912 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13913 | { | |
13914 | mask &= ~ (7 << 3); | |
13915 | mask |= 5 << 3; | |
13916 | } | |
13917 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13918 | { | |
13919 | mask &= ~ (7 << 3); | |
13920 | mask |= 6 << 3; | |
13921 | } | |
13922 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13923 | mask |= (reg2 - 3) << 3; | |
13924 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13925 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13926 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13927 | mask |= 1; |
13928 | else | |
13929 | { | |
13930 | as_bad (_("invalid register list")); | |
13931 | break; | |
13932 | } | |
13933 | } | |
13934 | /* The mask is filled in in the opcode table for the | |
13935 | benefit of the disassembler. We remove it before | |
13936 | applying the actual mask. */ | |
13937 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13938 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13939 | } | |
13940 | continue; | |
13941 | ||
0499d65b TS |
13942 | case 'm': /* Register list for save insn. */ |
13943 | case 'M': /* Register list for restore insn. */ | |
13944 | { | |
5c04167a | 13945 | int opcode = ip->insn_opcode; |
0499d65b | 13946 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13947 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13948 | |
13949 | while (*s != '\0') | |
13950 | { | |
13951 | unsigned int reg1, reg2; | |
13952 | ||
13953 | SKIP_SPACE_TABS (s); | |
13954 | while (*s == ',') | |
13955 | ++s; | |
13956 | SKIP_SPACE_TABS (s); | |
13957 | ||
13958 | my_getExpression (&imm_expr, s); | |
13959 | if (imm_expr.X_op == O_constant) | |
13960 | { | |
13961 | /* Handle the frame size. */ | |
13962 | if (seen_framesz) | |
13963 | { | |
13964 | as_bad (_("more than one frame size in list")); | |
13965 | break; | |
13966 | } | |
13967 | seen_framesz = 1; | |
13968 | framesz = imm_expr.X_add_number; | |
13969 | imm_expr.X_op = O_absent; | |
13970 | s = expr_end; | |
13971 | continue; | |
13972 | } | |
13973 | ||
707bfff6 | 13974 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13975 | { |
13976 | as_bad (_("can't parse register list")); | |
13977 | break; | |
13978 | } | |
0499d65b | 13979 | |
707bfff6 TS |
13980 | while (*s == ' ') |
13981 | ++s; | |
13982 | ||
0499d65b TS |
13983 | if (*s != '-') |
13984 | reg2 = reg1; | |
13985 | else | |
13986 | { | |
13987 | ++s; | |
707bfff6 TS |
13988 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13989 | || reg2 < reg1) | |
0499d65b TS |
13990 | { |
13991 | as_bad (_("can't parse register list")); | |
13992 | break; | |
13993 | } | |
0499d65b TS |
13994 | } |
13995 | ||
13996 | while (reg1 <= reg2) | |
13997 | { | |
13998 | if (reg1 >= 4 && reg1 <= 7) | |
13999 | { | |
3a93f742 | 14000 | if (!seen_framesz) |
0499d65b | 14001 | /* args $a0-$a3 */ |
91d6fa6a | 14002 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14003 | else |
14004 | /* statics $a0-$a3 */ | |
14005 | statics |= 1 << (reg1 - 4); | |
14006 | } | |
14007 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14008 | { | |
14009 | /* $s0-$s8 */ | |
14010 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14011 | } | |
14012 | else if (reg1 == 31) | |
14013 | { | |
14014 | /* Add $ra to insn. */ | |
14015 | opcode |= 0x40; | |
14016 | } | |
14017 | else | |
14018 | { | |
14019 | as_bad (_("unexpected register in list")); | |
14020 | break; | |
14021 | } | |
14022 | if (++reg1 == 24) | |
14023 | reg1 = 30; | |
14024 | } | |
14025 | } | |
14026 | ||
14027 | /* Encode args/statics combination. */ | |
91d6fa6a | 14028 | if (nargs & statics) |
0499d65b | 14029 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14030 | else if (nargs == 0xf) |
0499d65b TS |
14031 | /* All $a0-$a3 are args. */ |
14032 | opcode |= MIPS16_ALL_ARGS << 16; | |
14033 | else if (statics == 0xf) | |
14034 | /* All $a0-$a3 are statics. */ | |
14035 | opcode |= MIPS16_ALL_STATICS << 16; | |
14036 | else | |
14037 | { | |
14038 | int narg = 0, nstat = 0; | |
14039 | ||
14040 | /* Count arg registers. */ | |
91d6fa6a | 14041 | while (nargs & 0x1) |
0499d65b | 14042 | { |
91d6fa6a | 14043 | nargs >>= 1; |
0499d65b TS |
14044 | narg++; |
14045 | } | |
91d6fa6a | 14046 | if (nargs != 0) |
0499d65b TS |
14047 | as_bad (_("invalid arg register list")); |
14048 | ||
14049 | /* Count static registers. */ | |
14050 | while (statics & 0x8) | |
14051 | { | |
14052 | statics = (statics << 1) & 0xf; | |
14053 | nstat++; | |
14054 | } | |
14055 | if (statics != 0) | |
14056 | as_bad (_("invalid static register list")); | |
14057 | ||
14058 | /* Encode args/statics. */ | |
14059 | opcode |= ((narg << 2) | nstat) << 16; | |
14060 | } | |
14061 | ||
14062 | /* Encode $s0/$s1. */ | |
14063 | if (sregs & (1 << 0)) /* $s0 */ | |
14064 | opcode |= 0x20; | |
14065 | if (sregs & (1 << 1)) /* $s1 */ | |
14066 | opcode |= 0x10; | |
14067 | sregs >>= 2; | |
14068 | ||
14069 | if (sregs != 0) | |
14070 | { | |
14071 | /* Count regs $s2-$s8. */ | |
14072 | int nsreg = 0; | |
14073 | while (sregs & 1) | |
14074 | { | |
14075 | sregs >>= 1; | |
14076 | nsreg++; | |
14077 | } | |
14078 | if (sregs != 0) | |
14079 | as_bad (_("invalid static register list")); | |
14080 | /* Encode $s2-$s8. */ | |
14081 | opcode |= nsreg << 24; | |
14082 | } | |
14083 | ||
14084 | /* Encode frame size. */ | |
14085 | if (!seen_framesz) | |
14086 | as_bad (_("missing frame size")); | |
14087 | else if ((framesz & 7) != 0 || framesz < 0 | |
14088 | || framesz > 0xff * 8) | |
14089 | as_bad (_("invalid frame size")); | |
14090 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14091 | { | |
14092 | framesz /= 8; | |
14093 | opcode |= (((framesz & 0xf0) << 16) | |
14094 | | (framesz & 0x0f)); | |
14095 | } | |
14096 | ||
14097 | /* Finally build the instruction. */ | |
14098 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14099 | opcode |= MIPS16_EXTEND; |
14100 | ip->insn_opcode = opcode; | |
0499d65b TS |
14101 | } |
14102 | continue; | |
14103 | ||
252b5132 RH |
14104 | case 'e': /* extend code */ |
14105 | my_getExpression (&imm_expr, s); | |
14106 | check_absolute_expr (ip, &imm_expr); | |
14107 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14108 | { | |
14109 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14110 | ip->insn_mo->name, | |
14111 | (unsigned long) imm_expr.X_add_number); | |
14112 | imm_expr.X_add_number &= 0x7ff; | |
14113 | } | |
14114 | ip->insn_opcode |= imm_expr.X_add_number; | |
14115 | imm_expr.X_op = O_absent; | |
14116 | s = expr_end; | |
14117 | continue; | |
14118 | ||
14119 | default: | |
b37df7c4 | 14120 | abort (); |
252b5132 RH |
14121 | } |
14122 | break; | |
14123 | } | |
14124 | ||
14125 | /* Args don't match. */ | |
14126 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14127 | strcmp (insn->name, insn[1].name) == 0) | |
14128 | { | |
14129 | ++insn; | |
14130 | s = argsstart; | |
14131 | continue; | |
14132 | } | |
14133 | ||
14134 | insn_error = _("illegal operands"); | |
14135 | ||
14136 | return; | |
14137 | } | |
14138 | } | |
14139 | ||
14140 | /* This structure holds information we know about a mips16 immediate | |
14141 | argument type. */ | |
14142 | ||
e972090a NC |
14143 | struct mips16_immed_operand |
14144 | { | |
252b5132 RH |
14145 | /* The type code used in the argument string in the opcode table. */ |
14146 | int type; | |
14147 | /* The number of bits in the short form of the opcode. */ | |
14148 | int nbits; | |
14149 | /* The number of bits in the extended form of the opcode. */ | |
14150 | int extbits; | |
14151 | /* The amount by which the short form is shifted when it is used; | |
14152 | for example, the sw instruction has a shift count of 2. */ | |
14153 | int shift; | |
14154 | /* The amount by which the short form is shifted when it is stored | |
14155 | into the instruction code. */ | |
14156 | int op_shift; | |
14157 | /* Non-zero if the short form is unsigned. */ | |
14158 | int unsp; | |
14159 | /* Non-zero if the extended form is unsigned. */ | |
14160 | int extu; | |
14161 | /* Non-zero if the value is PC relative. */ | |
14162 | int pcrel; | |
14163 | }; | |
14164 | ||
14165 | /* The mips16 immediate operand types. */ | |
14166 | ||
14167 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14168 | { | |
14169 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14170 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14171 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14172 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14173 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14174 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14175 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14176 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14177 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14178 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14179 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14180 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14181 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14182 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14183 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14184 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14185 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14186 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14187 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14188 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14189 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14190 | }; | |
14191 | ||
14192 | #define MIPS16_NUM_IMMED \ | |
14193 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14194 | ||
b886a2ab RS |
14195 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14196 | NBITS is the number of significant bits in VAL. */ | |
14197 | ||
14198 | static unsigned long | |
14199 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14200 | { | |
14201 | int extval; | |
14202 | if (nbits == 16) | |
14203 | { | |
14204 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14205 | val &= 0x1f; | |
14206 | } | |
14207 | else if (nbits == 15) | |
14208 | { | |
14209 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14210 | val &= 0xf; | |
14211 | } | |
14212 | else | |
14213 | { | |
14214 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14215 | val = 0; | |
14216 | } | |
14217 | return (extval << 16) | val; | |
14218 | } | |
14219 | ||
5c04167a RS |
14220 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14221 | extending it if necessary. The instruction in *INSN may | |
14222 | already be extended. | |
14223 | ||
43c0598f RS |
14224 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14225 | if none. In the former case, VAL is a 16-bit number with no | |
14226 | defined signedness. | |
14227 | ||
14228 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14229 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14230 | |
14231 | static void | |
43c0598f RS |
14232 | mips16_immed (char *file, unsigned int line, int type, |
14233 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14234 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14235 | { |
3994f87e | 14236 | const struct mips16_immed_operand *op; |
252b5132 | 14237 | int mintiny, maxtiny; |
252b5132 RH |
14238 | |
14239 | op = mips16_immed_operands; | |
14240 | while (op->type != type) | |
14241 | { | |
14242 | ++op; | |
9c2799c2 | 14243 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14244 | } |
14245 | ||
14246 | if (op->unsp) | |
14247 | { | |
14248 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14249 | { | |
14250 | mintiny = 1; | |
14251 | maxtiny = 1 << op->nbits; | |
14252 | } | |
14253 | else | |
14254 | { | |
14255 | mintiny = 0; | |
14256 | maxtiny = (1 << op->nbits) - 1; | |
14257 | } | |
43c0598f RS |
14258 | if (reloc != BFD_RELOC_UNUSED) |
14259 | val &= 0xffff; | |
252b5132 RH |
14260 | } |
14261 | else | |
14262 | { | |
14263 | mintiny = - (1 << (op->nbits - 1)); | |
14264 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14265 | if (reloc != BFD_RELOC_UNUSED) |
14266 | val = SEXT_16BIT (val); | |
252b5132 RH |
14267 | } |
14268 | ||
14269 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14270 | if (type == 'p' || type == 'q') | |
14271 | val /= 2; | |
14272 | ||
14273 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14274 | || val < (mintiny << op->shift) | |
14275 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14276 | { |
14277 | /* We need an extended instruction. */ | |
14278 | if (user_insn_length == 2) | |
14279 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14280 | else | |
14281 | *insn |= MIPS16_EXTEND; | |
14282 | } | |
14283 | else if (user_insn_length == 4) | |
14284 | { | |
14285 | /* The operand doesn't force an unextended instruction to be extended. | |
14286 | Warn if the user wanted an extended instruction anyway. */ | |
14287 | *insn |= MIPS16_EXTEND; | |
14288 | as_warn_where (file, line, | |
14289 | _("extended operand requested but not required")); | |
14290 | } | |
252b5132 | 14291 | |
5c04167a | 14292 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14293 | { |
14294 | int insnval; | |
14295 | ||
252b5132 RH |
14296 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14297 | insnval <<= op->op_shift; | |
14298 | *insn |= insnval; | |
14299 | } | |
14300 | else | |
14301 | { | |
14302 | long minext, maxext; | |
252b5132 | 14303 | |
43c0598f | 14304 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14305 | { |
43c0598f RS |
14306 | if (op->extu) |
14307 | { | |
14308 | minext = 0; | |
14309 | maxext = (1 << op->extbits) - 1; | |
14310 | } | |
14311 | else | |
14312 | { | |
14313 | minext = - (1 << (op->extbits - 1)); | |
14314 | maxext = (1 << (op->extbits - 1)) - 1; | |
14315 | } | |
14316 | if (val < minext || val > maxext) | |
14317 | as_bad_where (file, line, | |
14318 | _("operand value out of range for instruction")); | |
252b5132 | 14319 | } |
252b5132 | 14320 | |
b886a2ab | 14321 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14322 | } |
14323 | } | |
14324 | \f | |
d6f16593 | 14325 | struct percent_op_match |
ad8d3bb3 | 14326 | { |
5e0116d5 RS |
14327 | const char *str; |
14328 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14329 | }; |
14330 | ||
14331 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14332 | { |
5e0116d5 | 14333 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14334 | #ifdef OBJ_ELF |
5e0116d5 RS |
14335 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14336 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14337 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14338 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14339 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14340 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14341 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14342 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14343 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14344 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14345 | {"%half", BFD_RELOC_16}, | |
14346 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14347 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14348 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14349 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14350 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14351 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14352 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14353 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14354 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14355 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14356 | #endif |
5e0116d5 | 14357 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14358 | }; |
14359 | ||
d6f16593 MR |
14360 | static const struct percent_op_match mips16_percent_op[] = |
14361 | { | |
14362 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14363 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14364 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14365 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14366 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14367 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14368 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14369 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14370 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14371 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14372 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14373 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14374 | }; |
14375 | ||
252b5132 | 14376 | |
5e0116d5 RS |
14377 | /* Return true if *STR points to a relocation operator. When returning true, |
14378 | move *STR over the operator and store its relocation code in *RELOC. | |
14379 | Leave both *STR and *RELOC alone when returning false. */ | |
14380 | ||
14381 | static bfd_boolean | |
17a2f251 | 14382 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14383 | { |
d6f16593 MR |
14384 | const struct percent_op_match *percent_op; |
14385 | size_t limit, i; | |
14386 | ||
14387 | if (mips_opts.mips16) | |
14388 | { | |
14389 | percent_op = mips16_percent_op; | |
14390 | limit = ARRAY_SIZE (mips16_percent_op); | |
14391 | } | |
14392 | else | |
14393 | { | |
14394 | percent_op = mips_percent_op; | |
14395 | limit = ARRAY_SIZE (mips_percent_op); | |
14396 | } | |
76b3015f | 14397 | |
d6f16593 | 14398 | for (i = 0; i < limit; i++) |
5e0116d5 | 14399 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14400 | { |
3f98094e DJ |
14401 | int len = strlen (percent_op[i].str); |
14402 | ||
14403 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14404 | continue; | |
14405 | ||
5e0116d5 RS |
14406 | *str += strlen (percent_op[i].str); |
14407 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14408 | |
5e0116d5 RS |
14409 | /* Check whether the output BFD supports this relocation. |
14410 | If not, issue an error and fall back on something safe. */ | |
14411 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14412 | { |
20203fb9 | 14413 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14414 | percent_op[i].str); |
01a3f561 | 14415 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14416 | } |
5e0116d5 | 14417 | return TRUE; |
394f9b3a | 14418 | } |
5e0116d5 | 14419 | return FALSE; |
394f9b3a | 14420 | } |
ad8d3bb3 | 14421 | |
ad8d3bb3 | 14422 | |
5e0116d5 RS |
14423 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14424 | expression in *EP and the relocations in the array starting | |
14425 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14426 | |
01a3f561 | 14427 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14428 | |
5e0116d5 | 14429 | static size_t |
17a2f251 TS |
14430 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14431 | char *str) | |
ad8d3bb3 | 14432 | { |
5e0116d5 RS |
14433 | bfd_reloc_code_real_type reversed_reloc[3]; |
14434 | size_t reloc_index, i; | |
09b8f35a RS |
14435 | int crux_depth, str_depth; |
14436 | char *crux; | |
5e0116d5 RS |
14437 | |
14438 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14439 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14440 | of the main expression and with CRUX_DEPTH containing the number | |
14441 | of open brackets at that point. */ | |
14442 | reloc_index = -1; | |
14443 | str_depth = 0; | |
14444 | do | |
fb1b3232 | 14445 | { |
09b8f35a RS |
14446 | reloc_index++; |
14447 | crux = str; | |
14448 | crux_depth = str_depth; | |
14449 | ||
14450 | /* Skip over whitespace and brackets, keeping count of the number | |
14451 | of brackets. */ | |
14452 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14453 | if (*str++ == '(') | |
14454 | str_depth++; | |
5e0116d5 | 14455 | } |
09b8f35a RS |
14456 | while (*str == '%' |
14457 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14458 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14459 | |
09b8f35a | 14460 | my_getExpression (ep, crux); |
5e0116d5 | 14461 | str = expr_end; |
394f9b3a | 14462 | |
5e0116d5 | 14463 | /* Match every open bracket. */ |
09b8f35a | 14464 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14465 | if (*str++ == ')') |
09b8f35a | 14466 | crux_depth--; |
394f9b3a | 14467 | |
09b8f35a | 14468 | if (crux_depth > 0) |
20203fb9 | 14469 | as_bad (_("unclosed '('")); |
394f9b3a | 14470 | |
5e0116d5 | 14471 | expr_end = str; |
252b5132 | 14472 | |
01a3f561 | 14473 | if (reloc_index != 0) |
64bdfcaf RS |
14474 | { |
14475 | prev_reloc_op_frag = frag_now; | |
14476 | for (i = 0; i < reloc_index; i++) | |
14477 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14478 | } | |
fb1b3232 | 14479 | |
5e0116d5 | 14480 | return reloc_index; |
252b5132 RH |
14481 | } |
14482 | ||
14483 | static void | |
17a2f251 | 14484 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14485 | { |
14486 | char *save_in; | |
14487 | ||
14488 | save_in = input_line_pointer; | |
14489 | input_line_pointer = str; | |
14490 | expression (ep); | |
14491 | expr_end = input_line_pointer; | |
14492 | input_line_pointer = save_in; | |
252b5132 RH |
14493 | } |
14494 | ||
252b5132 | 14495 | char * |
17a2f251 | 14496 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14497 | { |
499ac353 | 14498 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14499 | } |
14500 | ||
14501 | void | |
17a2f251 | 14502 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14503 | { |
14504 | if (target_big_endian) | |
14505 | number_to_chars_bigendian (buf, val, n); | |
14506 | else | |
14507 | number_to_chars_littleendian (buf, val, n); | |
14508 | } | |
14509 | \f | |
ae948b86 | 14510 | #ifdef OBJ_ELF |
e013f690 TS |
14511 | static int support_64bit_objects(void) |
14512 | { | |
14513 | const char **list, **l; | |
aa3d8fdf | 14514 | int yes; |
e013f690 TS |
14515 | |
14516 | list = bfd_target_list (); | |
14517 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14518 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14519 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14520 | break; |
aa3d8fdf | 14521 | yes = (*l != NULL); |
e013f690 | 14522 | free (list); |
aa3d8fdf | 14523 | return yes; |
e013f690 | 14524 | } |
ae948b86 | 14525 | #endif /* OBJ_ELF */ |
e013f690 | 14526 | |
78849248 | 14527 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14528 | |
23fce1e3 NC |
14529 | enum options |
14530 | { | |
14531 | OPTION_MARCH = OPTION_MD_BASE, | |
14532 | OPTION_MTUNE, | |
14533 | OPTION_MIPS1, | |
14534 | OPTION_MIPS2, | |
14535 | OPTION_MIPS3, | |
14536 | OPTION_MIPS4, | |
14537 | OPTION_MIPS5, | |
14538 | OPTION_MIPS32, | |
14539 | OPTION_MIPS64, | |
14540 | OPTION_MIPS32R2, | |
14541 | OPTION_MIPS64R2, | |
14542 | OPTION_MIPS16, | |
14543 | OPTION_NO_MIPS16, | |
14544 | OPTION_MIPS3D, | |
14545 | OPTION_NO_MIPS3D, | |
14546 | OPTION_MDMX, | |
14547 | OPTION_NO_MDMX, | |
14548 | OPTION_DSP, | |
14549 | OPTION_NO_DSP, | |
14550 | OPTION_MT, | |
14551 | OPTION_NO_MT, | |
b015e599 AP |
14552 | OPTION_VIRT, |
14553 | OPTION_NO_VIRT, | |
23fce1e3 NC |
14554 | OPTION_SMARTMIPS, |
14555 | OPTION_NO_SMARTMIPS, | |
14556 | OPTION_DSPR2, | |
14557 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14558 | OPTION_MICROMIPS, |
14559 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14560 | OPTION_MCU, |
14561 | OPTION_NO_MCU, | |
23fce1e3 NC |
14562 | OPTION_COMPAT_ARCH_BASE, |
14563 | OPTION_M4650, | |
14564 | OPTION_NO_M4650, | |
14565 | OPTION_M4010, | |
14566 | OPTION_NO_M4010, | |
14567 | OPTION_M4100, | |
14568 | OPTION_NO_M4100, | |
14569 | OPTION_M3900, | |
14570 | OPTION_NO_M3900, | |
14571 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14572 | OPTION_MNO_7000_HILO_FIX, |
14573 | OPTION_FIX_24K, | |
14574 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14575 | OPTION_FIX_LOONGSON2F_JUMP, |
14576 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14577 | OPTION_FIX_LOONGSON2F_NOP, | |
14578 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14579 | OPTION_FIX_VR4120, |
14580 | OPTION_NO_FIX_VR4120, | |
14581 | OPTION_FIX_VR4130, | |
14582 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14583 | OPTION_FIX_CN63XXP1, |
14584 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14585 | OPTION_TRAP, |
14586 | OPTION_BREAK, | |
14587 | OPTION_EB, | |
14588 | OPTION_EL, | |
14589 | OPTION_FP32, | |
14590 | OPTION_GP32, | |
14591 | OPTION_CONSTRUCT_FLOATS, | |
14592 | OPTION_NO_CONSTRUCT_FLOATS, | |
14593 | OPTION_FP64, | |
14594 | OPTION_GP64, | |
14595 | OPTION_RELAX_BRANCH, | |
14596 | OPTION_NO_RELAX_BRANCH, | |
14597 | OPTION_MSHARED, | |
14598 | OPTION_MNO_SHARED, | |
14599 | OPTION_MSYM32, | |
14600 | OPTION_MNO_SYM32, | |
14601 | OPTION_SOFT_FLOAT, | |
14602 | OPTION_HARD_FLOAT, | |
14603 | OPTION_SINGLE_FLOAT, | |
14604 | OPTION_DOUBLE_FLOAT, | |
14605 | OPTION_32, | |
14606 | #ifdef OBJ_ELF | |
14607 | OPTION_CALL_SHARED, | |
14608 | OPTION_CALL_NONPIC, | |
14609 | OPTION_NON_SHARED, | |
14610 | OPTION_XGOT, | |
14611 | OPTION_MABI, | |
14612 | OPTION_N32, | |
14613 | OPTION_64, | |
14614 | OPTION_MDEBUG, | |
14615 | OPTION_NO_MDEBUG, | |
14616 | OPTION_PDR, | |
14617 | OPTION_NO_PDR, | |
14618 | OPTION_MVXWORKS_PIC, | |
14619 | #endif /* OBJ_ELF */ | |
14620 | OPTION_END_OF_ENUM | |
14621 | }; | |
14622 | ||
e972090a NC |
14623 | struct option md_longopts[] = |
14624 | { | |
f9b4148d | 14625 | /* Options which specify architecture. */ |
f9b4148d | 14626 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14627 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14628 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14629 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14630 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14631 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14632 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14633 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14634 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14635 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14636 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14637 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14638 | |
14639 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14640 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14641 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14642 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14643 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14644 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14645 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14646 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14647 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14648 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14649 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14650 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14651 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14652 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14653 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14654 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14655 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14656 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14657 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
b015e599 AP |
14658 | {"mvirt", no_argument, NULL, OPTION_VIRT}, |
14659 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
f9b4148d CD |
14660 | |
14661 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14662 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14663 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14664 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14665 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14666 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14667 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14668 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14669 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14670 | ||
14671 | /* Options which enable bug fixes. */ | |
f9b4148d | 14672 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14673 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14674 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14675 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14676 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14677 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14678 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14679 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14680 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14681 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14682 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14683 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14684 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14685 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14686 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14687 | |
14688 | /* Miscellaneous options. */ | |
252b5132 RH |
14689 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14690 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14691 | {"break", no_argument, NULL, OPTION_BREAK}, |
14692 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14693 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14694 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14695 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14696 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14697 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14698 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14699 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14700 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14701 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14702 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14703 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14704 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14705 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14706 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14707 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14708 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14709 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14710 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14711 | |
14712 | /* Strictly speaking this next option is ELF specific, | |
14713 | but we allow it for other ports as well in order to | |
14714 | make testing easier. */ | |
14715 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14716 | |
f9b4148d | 14717 | /* ELF-specific options. */ |
156c2f8b | 14718 | #ifdef OBJ_ELF |
156c2f8b NC |
14719 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14720 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14721 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14722 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14723 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14724 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14725 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14726 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14727 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14728 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14729 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14730 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14731 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14732 | #endif /* OBJ_ELF */ |
f9b4148d | 14733 | |
252b5132 RH |
14734 | {NULL, no_argument, NULL, 0} |
14735 | }; | |
156c2f8b | 14736 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14737 | |
316f5878 RS |
14738 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14739 | NEW_VALUE. Warn if another value was already specified. Note: | |
14740 | we have to defer parsing the -march and -mtune arguments in order | |
14741 | to handle 'from-abi' correctly, since the ABI might be specified | |
14742 | in a later argument. */ | |
14743 | ||
14744 | static void | |
17a2f251 | 14745 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14746 | { |
14747 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14748 | as_warn (_("A different %s was already specified, is now %s"), | |
14749 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14750 | new_value); | |
14751 | ||
14752 | *string_ptr = new_value; | |
14753 | } | |
14754 | ||
252b5132 | 14755 | int |
17a2f251 | 14756 | md_parse_option (int c, char *arg) |
252b5132 RH |
14757 | { |
14758 | switch (c) | |
14759 | { | |
119d663a NC |
14760 | case OPTION_CONSTRUCT_FLOATS: |
14761 | mips_disable_float_construction = 0; | |
14762 | break; | |
bdaaa2e1 | 14763 | |
119d663a NC |
14764 | case OPTION_NO_CONSTRUCT_FLOATS: |
14765 | mips_disable_float_construction = 1; | |
14766 | break; | |
bdaaa2e1 | 14767 | |
252b5132 RH |
14768 | case OPTION_TRAP: |
14769 | mips_trap = 1; | |
14770 | break; | |
14771 | ||
14772 | case OPTION_BREAK: | |
14773 | mips_trap = 0; | |
14774 | break; | |
14775 | ||
14776 | case OPTION_EB: | |
14777 | target_big_endian = 1; | |
14778 | break; | |
14779 | ||
14780 | case OPTION_EL: | |
14781 | target_big_endian = 0; | |
14782 | break; | |
14783 | ||
14784 | case 'O': | |
4ffff32f TS |
14785 | if (arg == NULL) |
14786 | mips_optimize = 1; | |
14787 | else if (arg[0] == '0') | |
14788 | mips_optimize = 0; | |
14789 | else if (arg[0] == '1') | |
252b5132 RH |
14790 | mips_optimize = 1; |
14791 | else | |
14792 | mips_optimize = 2; | |
14793 | break; | |
14794 | ||
14795 | case 'g': | |
14796 | if (arg == NULL) | |
14797 | mips_debug = 2; | |
14798 | else | |
14799 | mips_debug = atoi (arg); | |
252b5132 RH |
14800 | break; |
14801 | ||
14802 | case OPTION_MIPS1: | |
316f5878 | 14803 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14804 | break; |
14805 | ||
14806 | case OPTION_MIPS2: | |
316f5878 | 14807 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14808 | break; |
14809 | ||
14810 | case OPTION_MIPS3: | |
316f5878 | 14811 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14812 | break; |
14813 | ||
14814 | case OPTION_MIPS4: | |
316f5878 | 14815 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14816 | break; |
14817 | ||
84ea6cf2 | 14818 | case OPTION_MIPS5: |
316f5878 | 14819 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14820 | break; |
14821 | ||
e7af610e | 14822 | case OPTION_MIPS32: |
316f5878 | 14823 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14824 | break; |
14825 | ||
af7ee8bf CD |
14826 | case OPTION_MIPS32R2: |
14827 | file_mips_isa = ISA_MIPS32R2; | |
14828 | break; | |
14829 | ||
5f74bc13 CD |
14830 | case OPTION_MIPS64R2: |
14831 | file_mips_isa = ISA_MIPS64R2; | |
14832 | break; | |
14833 | ||
84ea6cf2 | 14834 | case OPTION_MIPS64: |
316f5878 | 14835 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14836 | break; |
14837 | ||
ec68c924 | 14838 | case OPTION_MTUNE: |
316f5878 RS |
14839 | mips_set_option_string (&mips_tune_string, arg); |
14840 | break; | |
ec68c924 | 14841 | |
316f5878 RS |
14842 | case OPTION_MARCH: |
14843 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14844 | break; |
14845 | ||
14846 | case OPTION_M4650: | |
316f5878 RS |
14847 | mips_set_option_string (&mips_arch_string, "4650"); |
14848 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14849 | break; |
14850 | ||
14851 | case OPTION_NO_M4650: | |
14852 | break; | |
14853 | ||
14854 | case OPTION_M4010: | |
316f5878 RS |
14855 | mips_set_option_string (&mips_arch_string, "4010"); |
14856 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14857 | break; |
14858 | ||
14859 | case OPTION_NO_M4010: | |
14860 | break; | |
14861 | ||
14862 | case OPTION_M4100: | |
316f5878 RS |
14863 | mips_set_option_string (&mips_arch_string, "4100"); |
14864 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14865 | break; |
14866 | ||
14867 | case OPTION_NO_M4100: | |
14868 | break; | |
14869 | ||
252b5132 | 14870 | case OPTION_M3900: |
316f5878 RS |
14871 | mips_set_option_string (&mips_arch_string, "3900"); |
14872 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14873 | break; |
bdaaa2e1 | 14874 | |
252b5132 RH |
14875 | case OPTION_NO_M3900: |
14876 | break; | |
14877 | ||
deec1734 CD |
14878 | case OPTION_MDMX: |
14879 | mips_opts.ase_mdmx = 1; | |
14880 | break; | |
14881 | ||
14882 | case OPTION_NO_MDMX: | |
14883 | mips_opts.ase_mdmx = 0; | |
14884 | break; | |
14885 | ||
74cd071d CF |
14886 | case OPTION_DSP: |
14887 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14888 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14889 | break; |
14890 | ||
14891 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14892 | mips_opts.ase_dsp = 0; |
14893 | mips_opts.ase_dspr2 = 0; | |
14894 | break; | |
14895 | ||
14896 | case OPTION_DSPR2: | |
14897 | mips_opts.ase_dspr2 = 1; | |
14898 | mips_opts.ase_dsp = 1; | |
14899 | break; | |
14900 | ||
14901 | case OPTION_NO_DSPR2: | |
14902 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14903 | mips_opts.ase_dsp = 0; |
14904 | break; | |
14905 | ||
ef2e4d86 CF |
14906 | case OPTION_MT: |
14907 | mips_opts.ase_mt = 1; | |
14908 | break; | |
14909 | ||
14910 | case OPTION_NO_MT: | |
14911 | mips_opts.ase_mt = 0; | |
14912 | break; | |
14913 | ||
dec0624d MR |
14914 | case OPTION_MCU: |
14915 | mips_opts.ase_mcu = 1; | |
14916 | break; | |
14917 | ||
14918 | case OPTION_NO_MCU: | |
14919 | mips_opts.ase_mcu = 0; | |
14920 | break; | |
14921 | ||
df58fc94 RS |
14922 | case OPTION_MICROMIPS: |
14923 | if (mips_opts.mips16 == 1) | |
14924 | { | |
14925 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14926 | return 0; | |
14927 | } | |
14928 | mips_opts.micromips = 1; | |
14929 | mips_no_prev_insn (); | |
14930 | break; | |
14931 | ||
14932 | case OPTION_NO_MICROMIPS: | |
14933 | mips_opts.micromips = 0; | |
14934 | mips_no_prev_insn (); | |
14935 | break; | |
14936 | ||
b015e599 AP |
14937 | case OPTION_VIRT: |
14938 | mips_opts.ase_virt = 1; | |
14939 | break; | |
14940 | ||
14941 | case OPTION_NO_VIRT: | |
14942 | mips_opts.ase_virt = 0; | |
14943 | break; | |
14944 | ||
252b5132 | 14945 | case OPTION_MIPS16: |
df58fc94 RS |
14946 | if (mips_opts.micromips == 1) |
14947 | { | |
14948 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14949 | return 0; | |
14950 | } | |
252b5132 | 14951 | mips_opts.mips16 = 1; |
7d10b47d | 14952 | mips_no_prev_insn (); |
252b5132 RH |
14953 | break; |
14954 | ||
14955 | case OPTION_NO_MIPS16: | |
14956 | mips_opts.mips16 = 0; | |
7d10b47d | 14957 | mips_no_prev_insn (); |
252b5132 RH |
14958 | break; |
14959 | ||
1f25f5d3 CD |
14960 | case OPTION_MIPS3D: |
14961 | mips_opts.ase_mips3d = 1; | |
14962 | break; | |
14963 | ||
14964 | case OPTION_NO_MIPS3D: | |
14965 | mips_opts.ase_mips3d = 0; | |
14966 | break; | |
14967 | ||
e16bfa71 TS |
14968 | case OPTION_SMARTMIPS: |
14969 | mips_opts.ase_smartmips = 1; | |
14970 | break; | |
14971 | ||
14972 | case OPTION_NO_SMARTMIPS: | |
14973 | mips_opts.ase_smartmips = 0; | |
14974 | break; | |
14975 | ||
6a32d874 CM |
14976 | case OPTION_FIX_24K: |
14977 | mips_fix_24k = 1; | |
14978 | break; | |
14979 | ||
14980 | case OPTION_NO_FIX_24K: | |
14981 | mips_fix_24k = 0; | |
14982 | break; | |
14983 | ||
c67a084a NC |
14984 | case OPTION_FIX_LOONGSON2F_JUMP: |
14985 | mips_fix_loongson2f_jump = TRUE; | |
14986 | break; | |
14987 | ||
14988 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14989 | mips_fix_loongson2f_jump = FALSE; | |
14990 | break; | |
14991 | ||
14992 | case OPTION_FIX_LOONGSON2F_NOP: | |
14993 | mips_fix_loongson2f_nop = TRUE; | |
14994 | break; | |
14995 | ||
14996 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14997 | mips_fix_loongson2f_nop = FALSE; | |
14998 | break; | |
14999 | ||
d766e8ec RS |
15000 | case OPTION_FIX_VR4120: |
15001 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15002 | break; |
15003 | ||
d766e8ec RS |
15004 | case OPTION_NO_FIX_VR4120: |
15005 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15006 | break; |
15007 | ||
7d8e00cf RS |
15008 | case OPTION_FIX_VR4130: |
15009 | mips_fix_vr4130 = 1; | |
15010 | break; | |
15011 | ||
15012 | case OPTION_NO_FIX_VR4130: | |
15013 | mips_fix_vr4130 = 0; | |
15014 | break; | |
15015 | ||
d954098f DD |
15016 | case OPTION_FIX_CN63XXP1: |
15017 | mips_fix_cn63xxp1 = TRUE; | |
15018 | break; | |
15019 | ||
15020 | case OPTION_NO_FIX_CN63XXP1: | |
15021 | mips_fix_cn63xxp1 = FALSE; | |
15022 | break; | |
15023 | ||
4a6a3df4 AO |
15024 | case OPTION_RELAX_BRANCH: |
15025 | mips_relax_branch = 1; | |
15026 | break; | |
15027 | ||
15028 | case OPTION_NO_RELAX_BRANCH: | |
15029 | mips_relax_branch = 0; | |
15030 | break; | |
15031 | ||
aa6975fb ILT |
15032 | case OPTION_MSHARED: |
15033 | mips_in_shared = TRUE; | |
15034 | break; | |
15035 | ||
15036 | case OPTION_MNO_SHARED: | |
15037 | mips_in_shared = FALSE; | |
15038 | break; | |
15039 | ||
aed1a261 RS |
15040 | case OPTION_MSYM32: |
15041 | mips_opts.sym32 = TRUE; | |
15042 | break; | |
15043 | ||
15044 | case OPTION_MNO_SYM32: | |
15045 | mips_opts.sym32 = FALSE; | |
15046 | break; | |
15047 | ||
0f074f60 | 15048 | #ifdef OBJ_ELF |
252b5132 RH |
15049 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15050 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15051 | intended to be compatible with Irix 5. */ | |
15052 | case OPTION_CALL_SHARED: | |
f43abd2b | 15053 | if (!IS_ELF) |
252b5132 RH |
15054 | { |
15055 | as_bad (_("-call_shared is supported only for ELF format")); | |
15056 | return 0; | |
15057 | } | |
15058 | mips_pic = SVR4_PIC; | |
143d77c5 | 15059 | mips_abicalls = TRUE; |
252b5132 RH |
15060 | break; |
15061 | ||
861fb55a DJ |
15062 | case OPTION_CALL_NONPIC: |
15063 | if (!IS_ELF) | |
15064 | { | |
15065 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
15066 | return 0; | |
15067 | } | |
15068 | mips_pic = NO_PIC; | |
15069 | mips_abicalls = TRUE; | |
15070 | break; | |
15071 | ||
252b5132 | 15072 | case OPTION_NON_SHARED: |
f43abd2b | 15073 | if (!IS_ELF) |
252b5132 RH |
15074 | { |
15075 | as_bad (_("-non_shared is supported only for ELF format")); | |
15076 | return 0; | |
15077 | } | |
15078 | mips_pic = NO_PIC; | |
143d77c5 | 15079 | mips_abicalls = FALSE; |
252b5132 RH |
15080 | break; |
15081 | ||
44075ae2 TS |
15082 | /* The -xgot option tells the assembler to use 32 bit offsets |
15083 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15084 | compatibility. */ |
15085 | case OPTION_XGOT: | |
15086 | mips_big_got = 1; | |
15087 | break; | |
0f074f60 | 15088 | #endif /* OBJ_ELF */ |
252b5132 RH |
15089 | |
15090 | case 'G': | |
6caf9ef4 TS |
15091 | g_switch_value = atoi (arg); |
15092 | g_switch_seen = 1; | |
252b5132 RH |
15093 | break; |
15094 | ||
34ba82a8 TS |
15095 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15096 | and -mabi=64. */ | |
252b5132 | 15097 | case OPTION_32: |
23fce1e3 NC |
15098 | if (IS_ELF) |
15099 | mips_abi = O32_ABI; | |
15100 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15101 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15102 | break; |
15103 | ||
23fce1e3 | 15104 | #ifdef OBJ_ELF |
e013f690 | 15105 | case OPTION_N32: |
f43abd2b | 15106 | if (!IS_ELF) |
34ba82a8 TS |
15107 | { |
15108 | as_bad (_("-n32 is supported for ELF format only")); | |
15109 | return 0; | |
15110 | } | |
316f5878 | 15111 | mips_abi = N32_ABI; |
e013f690 | 15112 | break; |
252b5132 | 15113 | |
e013f690 | 15114 | case OPTION_64: |
f43abd2b | 15115 | if (!IS_ELF) |
34ba82a8 TS |
15116 | { |
15117 | as_bad (_("-64 is supported for ELF format only")); | |
15118 | return 0; | |
15119 | } | |
316f5878 | 15120 | mips_abi = N64_ABI; |
f43abd2b | 15121 | if (!support_64bit_objects()) |
e013f690 | 15122 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15123 | break; |
ae948b86 | 15124 | #endif /* OBJ_ELF */ |
252b5132 | 15125 | |
c97ef257 | 15126 | case OPTION_GP32: |
a325df1d | 15127 | file_mips_gp32 = 1; |
c97ef257 AH |
15128 | break; |
15129 | ||
15130 | case OPTION_GP64: | |
a325df1d | 15131 | file_mips_gp32 = 0; |
c97ef257 | 15132 | break; |
252b5132 | 15133 | |
ca4e0257 | 15134 | case OPTION_FP32: |
a325df1d | 15135 | file_mips_fp32 = 1; |
316f5878 RS |
15136 | break; |
15137 | ||
15138 | case OPTION_FP64: | |
15139 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15140 | break; |
15141 | ||
037b32b9 AN |
15142 | case OPTION_SINGLE_FLOAT: |
15143 | file_mips_single_float = 1; | |
15144 | break; | |
15145 | ||
15146 | case OPTION_DOUBLE_FLOAT: | |
15147 | file_mips_single_float = 0; | |
15148 | break; | |
15149 | ||
15150 | case OPTION_SOFT_FLOAT: | |
15151 | file_mips_soft_float = 1; | |
15152 | break; | |
15153 | ||
15154 | case OPTION_HARD_FLOAT: | |
15155 | file_mips_soft_float = 0; | |
15156 | break; | |
15157 | ||
ae948b86 | 15158 | #ifdef OBJ_ELF |
252b5132 | 15159 | case OPTION_MABI: |
f43abd2b | 15160 | if (!IS_ELF) |
34ba82a8 TS |
15161 | { |
15162 | as_bad (_("-mabi is supported for ELF format only")); | |
15163 | return 0; | |
15164 | } | |
e013f690 | 15165 | if (strcmp (arg, "32") == 0) |
316f5878 | 15166 | mips_abi = O32_ABI; |
e013f690 | 15167 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15168 | mips_abi = O64_ABI; |
e013f690 | 15169 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15170 | mips_abi = N32_ABI; |
e013f690 TS |
15171 | else if (strcmp (arg, "64") == 0) |
15172 | { | |
316f5878 | 15173 | mips_abi = N64_ABI; |
e013f690 TS |
15174 | if (! support_64bit_objects()) |
15175 | as_fatal (_("No compiled in support for 64 bit object file " | |
15176 | "format")); | |
15177 | } | |
15178 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15179 | mips_abi = EABI_ABI; |
e013f690 | 15180 | else |
da0e507f TS |
15181 | { |
15182 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15183 | return 0; | |
15184 | } | |
252b5132 | 15185 | break; |
e013f690 | 15186 | #endif /* OBJ_ELF */ |
252b5132 | 15187 | |
6b76fefe | 15188 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15189 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15190 | break; |
15191 | ||
9ee72ff1 | 15192 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15193 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15194 | break; |
15195 | ||
ecb4347a DJ |
15196 | #ifdef OBJ_ELF |
15197 | case OPTION_MDEBUG: | |
b34976b6 | 15198 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15199 | break; |
15200 | ||
15201 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15202 | mips_flag_mdebug = FALSE; |
ecb4347a | 15203 | break; |
dcd410fe RO |
15204 | |
15205 | case OPTION_PDR: | |
15206 | mips_flag_pdr = TRUE; | |
15207 | break; | |
15208 | ||
15209 | case OPTION_NO_PDR: | |
15210 | mips_flag_pdr = FALSE; | |
15211 | break; | |
0a44bf69 RS |
15212 | |
15213 | case OPTION_MVXWORKS_PIC: | |
15214 | mips_pic = VXWORKS_PIC; | |
15215 | break; | |
ecb4347a DJ |
15216 | #endif /* OBJ_ELF */ |
15217 | ||
252b5132 RH |
15218 | default: |
15219 | return 0; | |
15220 | } | |
15221 | ||
c67a084a NC |
15222 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15223 | ||
252b5132 RH |
15224 | return 1; |
15225 | } | |
316f5878 RS |
15226 | \f |
15227 | /* Set up globals to generate code for the ISA or processor | |
15228 | described by INFO. */ | |
252b5132 | 15229 | |
252b5132 | 15230 | static void |
17a2f251 | 15231 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15232 | { |
316f5878 | 15233 | if (info != 0) |
252b5132 | 15234 | { |
fef14a42 TS |
15235 | file_mips_arch = info->cpu; |
15236 | mips_opts.arch = info->cpu; | |
316f5878 | 15237 | mips_opts.isa = info->isa; |
252b5132 | 15238 | } |
252b5132 RH |
15239 | } |
15240 | ||
252b5132 | 15241 | |
316f5878 | 15242 | /* Likewise for tuning. */ |
252b5132 | 15243 | |
316f5878 | 15244 | static void |
17a2f251 | 15245 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15246 | { |
15247 | if (info != 0) | |
fef14a42 | 15248 | mips_tune = info->cpu; |
316f5878 | 15249 | } |
80cc45a5 | 15250 | |
34ba82a8 | 15251 | |
252b5132 | 15252 | void |
17a2f251 | 15253 | mips_after_parse_args (void) |
e9670677 | 15254 | { |
fef14a42 TS |
15255 | const struct mips_cpu_info *arch_info = 0; |
15256 | const struct mips_cpu_info *tune_info = 0; | |
15257 | ||
e9670677 | 15258 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15259 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15260 | { |
6caf9ef4 | 15261 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15262 | as_bad (_("-G not supported in this configuration.")); |
15263 | g_switch_value = 0; | |
15264 | } | |
15265 | ||
cac012d6 AO |
15266 | if (mips_abi == NO_ABI) |
15267 | mips_abi = MIPS_DEFAULT_ABI; | |
15268 | ||
22923709 RS |
15269 | /* The following code determines the architecture and register size. |
15270 | Similar code was added to GCC 3.3 (see override_options() in | |
15271 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15272 | as much as possible. */ | |
e9670677 | 15273 | |
316f5878 | 15274 | if (mips_arch_string != 0) |
fef14a42 | 15275 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15276 | |
316f5878 | 15277 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15278 | { |
316f5878 | 15279 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15280 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15281 | the -march selection (if any). */ |
fef14a42 | 15282 | if (arch_info != 0) |
e9670677 | 15283 | { |
316f5878 RS |
15284 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15285 | There's no harm in specifying both as long as the ISA levels | |
15286 | are the same. */ | |
fef14a42 | 15287 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15288 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15289 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15290 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15291 | } |
316f5878 | 15292 | else |
fef14a42 | 15293 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15294 | } |
15295 | ||
fef14a42 | 15296 | if (arch_info == 0) |
95bfe26e MF |
15297 | { |
15298 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15299 | gas_assert (arch_info); | |
15300 | } | |
e9670677 | 15301 | |
fef14a42 | 15302 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15303 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15304 | arch_info->name); |
15305 | ||
15306 | mips_set_architecture (arch_info); | |
15307 | ||
15308 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15309 | if (mips_tune_string != 0) | |
15310 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15311 | |
fef14a42 TS |
15312 | if (tune_info == 0) |
15313 | mips_set_tune (arch_info); | |
15314 | else | |
15315 | mips_set_tune (tune_info); | |
e9670677 | 15316 | |
316f5878 | 15317 | if (file_mips_gp32 >= 0) |
e9670677 | 15318 | { |
316f5878 RS |
15319 | /* The user specified the size of the integer registers. Make sure |
15320 | it agrees with the ABI and ISA. */ | |
15321 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15322 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15323 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15324 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15325 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15326 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15327 | } |
15328 | else | |
15329 | { | |
316f5878 RS |
15330 | /* Infer the integer register size from the ABI and processor. |
15331 | Restrict ourselves to 32-bit registers if that's all the | |
15332 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15333 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15334 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15335 | } |
15336 | ||
ad3fea08 TS |
15337 | switch (file_mips_fp32) |
15338 | { | |
15339 | default: | |
15340 | case -1: | |
15341 | /* No user specified float register size. | |
15342 | ??? GAS treats single-float processors as though they had 64-bit | |
15343 | float registers (although it complains when double-precision | |
15344 | instructions are used). As things stand, saying they have 32-bit | |
15345 | registers would lead to spurious "register must be even" messages. | |
15346 | So here we assume float registers are never smaller than the | |
15347 | integer ones. */ | |
15348 | if (file_mips_gp32 == 0) | |
15349 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15350 | file_mips_fp32 = 0; | |
15351 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15352 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15353 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15354 | file_mips_fp32 = 0; | |
15355 | else | |
15356 | /* 32-bit float registers. */ | |
15357 | file_mips_fp32 = 1; | |
15358 | break; | |
15359 | ||
15360 | /* The user specified the size of the float registers. Check if it | |
15361 | agrees with the ABI and ISA. */ | |
15362 | case 0: | |
15363 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15364 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15365 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15366 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15367 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15368 | break; | |
15369 | case 1: | |
15370 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15371 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15372 | break; | |
15373 | } | |
e9670677 | 15374 | |
316f5878 | 15375 | /* End of GCC-shared inference code. */ |
e9670677 | 15376 | |
17a2f251 TS |
15377 | /* This flag is set when we have a 64-bit capable CPU but use only |
15378 | 32-bit wide registers. Note that EABI does not use it. */ | |
15379 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15380 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15381 | || mips_abi == O32_ABI)) | |
316f5878 | 15382 | mips_32bitmode = 1; |
e9670677 MR |
15383 | |
15384 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15385 | as_bad (_("trap exception not supported at ISA 1")); | |
15386 | ||
e9670677 MR |
15387 | /* If the selected architecture includes support for ASEs, enable |
15388 | generation of code for them. */ | |
a4672219 | 15389 | if (mips_opts.mips16 == -1) |
fef14a42 | 15390 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15391 | if (mips_opts.micromips == -1) |
15392 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15393 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15394 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15395 | && file_mips_fp32 == 0) ? 1 : 0; |
15396 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15397 | as_bad (_("-mfp32 used with -mips3d")); | |
15398 | ||
ffdefa66 | 15399 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15400 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15401 | && file_mips_fp32 == 0) ? 1 : 0; |
15402 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15403 | as_bad (_("-mfp32 used with -mdmx")); | |
15404 | ||
15405 | if (mips_opts.ase_smartmips == -1) | |
15406 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15407 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15408 | as_warn (_("%s ISA does not support SmartMIPS"), |
15409 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15410 | |
74cd071d | 15411 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15412 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15413 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15414 | as_warn (_("%s ISA does not support DSP ASE"), |
15415 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15416 | |
8b082fb1 TS |
15417 | if (mips_opts.ase_dspr2 == -1) |
15418 | { | |
15419 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15420 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15421 | } | |
15422 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15423 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15424 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15425 | |
ef2e4d86 | 15426 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15427 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15428 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15429 | as_warn (_("%s ISA does not support MT ASE"), |
15430 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15431 | |
dec0624d MR |
15432 | if (mips_opts.ase_mcu == -1) |
15433 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15434 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15435 | as_warn (_("%s ISA does not support MCU ASE"), | |
15436 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15437 | ||
b015e599 AP |
15438 | if (mips_opts.ase_virt == -1) |
15439 | mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0; | |
15440 | if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE) | |
15441 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
15442 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15443 | ||
e9670677 | 15444 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15445 | file_ase_mips3d = mips_opts.ase_mips3d; |
15446 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15447 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15448 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15449 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15450 | file_ase_mt = mips_opts.ase_mt; |
b015e599 | 15451 | file_ase_virt = mips_opts.ase_virt; |
e9670677 MR |
15452 | mips_opts.gp32 = file_mips_gp32; |
15453 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15454 | mips_opts.soft_float = file_mips_soft_float; |
15455 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15456 | |
ecb4347a DJ |
15457 | if (mips_flag_mdebug < 0) |
15458 | { | |
15459 | #ifdef OBJ_MAYBE_ECOFF | |
15460 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15461 | mips_flag_mdebug = 1; | |
15462 | else | |
15463 | #endif /* OBJ_MAYBE_ECOFF */ | |
15464 | mips_flag_mdebug = 0; | |
15465 | } | |
e9670677 MR |
15466 | } |
15467 | \f | |
15468 | void | |
17a2f251 | 15469 | mips_init_after_args (void) |
252b5132 RH |
15470 | { |
15471 | /* initialize opcodes */ | |
15472 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15473 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15474 | } |
15475 | ||
15476 | long | |
17a2f251 | 15477 | md_pcrel_from (fixS *fixP) |
252b5132 | 15478 | { |
a7ebbfdf TS |
15479 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15480 | switch (fixP->fx_r_type) | |
15481 | { | |
df58fc94 RS |
15482 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15483 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15484 | /* Return the address of the delay slot. */ | |
15485 | return addr + 2; | |
15486 | ||
15487 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15488 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15489 | case BFD_RELOC_16_PCREL_S2: |
15490 | case BFD_RELOC_MIPS_JMP: | |
15491 | /* Return the address of the delay slot. */ | |
15492 | return addr + 4; | |
df58fc94 | 15493 | |
b47468a6 CM |
15494 | case BFD_RELOC_32_PCREL: |
15495 | return addr; | |
15496 | ||
a7ebbfdf | 15497 | default: |
58ea3d6a | 15498 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15499 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15500 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15501 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15502 | return addr; |
15503 | } | |
252b5132 RH |
15504 | } |
15505 | ||
252b5132 RH |
15506 | /* This is called before the symbol table is processed. In order to |
15507 | work with gcc when using mips-tfile, we must keep all local labels. | |
15508 | However, in other cases, we want to discard them. If we were | |
15509 | called with -g, but we didn't see any debugging information, it may | |
15510 | mean that gcc is smuggling debugging information through to | |
15511 | mips-tfile, in which case we must generate all local labels. */ | |
15512 | ||
15513 | void | |
17a2f251 | 15514 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15515 | { |
15516 | #ifndef NO_ECOFF_DEBUGGING | |
15517 | if (ECOFF_DEBUGGING | |
15518 | && mips_debug != 0 | |
15519 | && ! ecoff_debugging_seen) | |
15520 | flag_keep_locals = 1; | |
15521 | #endif | |
15522 | } | |
15523 | ||
3b91255e | 15524 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15525 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15526 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15527 | relocation operators. | |
15528 | ||
15529 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15530 | expression if: | |
15531 | ||
15532 | (a) it refers to the same symbol; and | |
15533 | (b) the offset applied in the %lo() expression is no lower than | |
15534 | the offset applied in the %got() or %hi(). | |
15535 | ||
15536 | (b) allows us to cope with code like: | |
15537 | ||
15538 | lui $4,%hi(foo) | |
15539 | lh $4,%lo(foo+2)($4) | |
15540 | ||
15541 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15542 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15543 | the high 16 bits. | |
15544 | ||
15545 | When several %lo()s match a particular %got() or %hi(), we use the | |
15546 | following rules to distinguish them: | |
15547 | ||
15548 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15549 | higher offsets. | |
15550 | ||
15551 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15552 | that already have a matching %got() or %hi(). | |
15553 | ||
15554 | (3) later %lo()s are better than earlier %lo()s. | |
15555 | ||
15556 | These rules are applied in order. | |
15557 | ||
15558 | (1) means, among other things, that %lo()s with identical offsets are | |
15559 | chosen if they exist. | |
15560 | ||
15561 | (2) means that we won't associate several high-part relocations with | |
15562 | the same low-part relocation unless there's no alternative. Having | |
15563 | several high parts for the same low part is a GNU extension; this rule | |
15564 | allows careful users to avoid it. | |
15565 | ||
15566 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15567 | with the last high-part relocation being at the front of the list. | |
15568 | It therefore makes sense to choose the last matching low-part | |
15569 | relocation, all other things being equal. It's also easier | |
15570 | to code that way. */ | |
252b5132 RH |
15571 | |
15572 | void | |
17a2f251 | 15573 | mips_frob_file (void) |
252b5132 RH |
15574 | { |
15575 | struct mips_hi_fixup *l; | |
35903be0 | 15576 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15577 | |
15578 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15579 | { | |
15580 | segment_info_type *seginfo; | |
3b91255e RS |
15581 | bfd_boolean matched_lo_p; |
15582 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15583 | |
9c2799c2 | 15584 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15585 | |
5919d012 | 15586 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15587 | there isn't supposed to be a matching LO. Ignore %gots against |
15588 | constants; we'll report an error for those later. */ | |
738e5348 | 15589 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15590 | && !(l->fixp->fx_addsy |
15591 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15592 | continue; |
15593 | ||
15594 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15595 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15596 | continue; |
15597 | ||
252b5132 | 15598 | seginfo = seg_info (l->seg); |
252b5132 | 15599 | |
3b91255e RS |
15600 | /* Set HI_POS to the position of this relocation in the chain. |
15601 | Set LO_POS to the position of the chosen low-part relocation. | |
15602 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15603 | relocation that matches an immediately-preceding high-part | |
15604 | relocation. */ | |
15605 | hi_pos = NULL; | |
15606 | lo_pos = NULL; | |
15607 | matched_lo_p = FALSE; | |
738e5348 | 15608 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15609 | |
3b91255e RS |
15610 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15611 | { | |
15612 | if (*pos == l->fixp) | |
15613 | hi_pos = pos; | |
15614 | ||
35903be0 | 15615 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15616 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15617 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15618 | && (lo_pos == NULL | |
15619 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15620 | || (!matched_lo_p | |
15621 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15622 | lo_pos = pos; | |
15623 | ||
15624 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15625 | && fixup_has_matching_lo_p (*pos)); | |
15626 | } | |
15627 | ||
15628 | /* If we found a match, remove the high-part relocation from its | |
15629 | current position and insert it before the low-part relocation. | |
15630 | Make the offsets match so that fixup_has_matching_lo_p() | |
15631 | will return true. | |
15632 | ||
15633 | We don't warn about unmatched high-part relocations since some | |
15634 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15635 | instructions. */ | |
15636 | if (lo_pos != NULL) | |
15637 | { | |
15638 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15639 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15640 | { |
3b91255e RS |
15641 | *hi_pos = l->fixp->fx_next; |
15642 | l->fixp->fx_next = *lo_pos; | |
15643 | *lo_pos = l->fixp; | |
252b5132 | 15644 | } |
252b5132 RH |
15645 | } |
15646 | } | |
15647 | } | |
15648 | ||
252b5132 | 15649 | int |
17a2f251 | 15650 | mips_force_relocation (fixS *fixp) |
252b5132 | 15651 | { |
ae6063d4 | 15652 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15653 | return 1; |
15654 | ||
df58fc94 RS |
15655 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15656 | so that the linker relaxation can update targets. */ | |
15657 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15658 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15659 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15660 | return 1; | |
15661 | ||
3e722fb5 | 15662 | return 0; |
252b5132 RH |
15663 | } |
15664 | ||
b886a2ab RS |
15665 | /* Read the instruction associated with RELOC from BUF. */ |
15666 | ||
15667 | static unsigned int | |
15668 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15669 | { | |
15670 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15671 | return read_compressed_insn (buf, 4); | |
15672 | else | |
15673 | return read_insn (buf); | |
15674 | } | |
15675 | ||
15676 | /* Write instruction INSN to BUF, given that it has been relocated | |
15677 | by RELOC. */ | |
15678 | ||
15679 | static void | |
15680 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15681 | unsigned long insn) | |
15682 | { | |
15683 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15684 | write_compressed_insn (buf, insn, 4); | |
15685 | else | |
15686 | write_insn (buf, insn); | |
15687 | } | |
15688 | ||
252b5132 RH |
15689 | /* Apply a fixup to the object file. */ |
15690 | ||
94f592af | 15691 | void |
55cf6793 | 15692 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15693 | { |
4d68580a | 15694 | char *buf; |
b886a2ab | 15695 | unsigned long insn; |
a7ebbfdf | 15696 | reloc_howto_type *howto; |
252b5132 | 15697 | |
a7ebbfdf TS |
15698 | /* We ignore generic BFD relocations we don't know about. */ |
15699 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15700 | if (! howto) | |
15701 | return; | |
65551fa4 | 15702 | |
df58fc94 RS |
15703 | gas_assert (fixP->fx_size == 2 |
15704 | || fixP->fx_size == 4 | |
90ecf173 MR |
15705 | || fixP->fx_r_type == BFD_RELOC_16 |
15706 | || fixP->fx_r_type == BFD_RELOC_64 | |
15707 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15708 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15709 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15710 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15711 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15712 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15713 | |
4d68580a | 15714 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15715 | |
df58fc94 RS |
15716 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15717 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15718 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15719 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15720 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15721 | |
15722 | /* Don't treat parts of a composite relocation as done. There are two | |
15723 | reasons for this: | |
15724 | ||
15725 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15726 | should nevertheless be emitted if the first part is. | |
15727 | ||
15728 | (2) In normal usage, composite relocations are never assembly-time | |
15729 | constants. The easiest way of dealing with the pathological | |
15730 | exceptions is to generate a relocation against STN_UNDEF and | |
15731 | leave everything up to the linker. */ | |
3994f87e | 15732 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15733 | fixP->fx_done = 1; |
15734 | ||
15735 | switch (fixP->fx_r_type) | |
15736 | { | |
3f98094e DJ |
15737 | case BFD_RELOC_MIPS_TLS_GD: |
15738 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15739 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15740 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15741 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15742 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15743 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15744 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15745 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15746 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15747 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15748 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15749 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15750 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15751 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15752 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15753 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15754 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15755 | case BFD_RELOC_MIPS16_TLS_GD: |
15756 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15757 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15758 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15759 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15760 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15761 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15762 | if (!fixP->fx_addsy) |
15763 | { | |
15764 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15765 | _("TLS relocation against a constant")); | |
15766 | break; | |
15767 | } | |
3f98094e DJ |
15768 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15769 | /* fall through */ | |
15770 | ||
252b5132 | 15771 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15772 | case BFD_RELOC_MIPS_SHIFT5: |
15773 | case BFD_RELOC_MIPS_SHIFT6: | |
15774 | case BFD_RELOC_MIPS_GOT_DISP: | |
15775 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15776 | case BFD_RELOC_MIPS_GOT_OFST: | |
15777 | case BFD_RELOC_MIPS_SUB: | |
15778 | case BFD_RELOC_MIPS_INSERT_A: | |
15779 | case BFD_RELOC_MIPS_INSERT_B: | |
15780 | case BFD_RELOC_MIPS_DELETE: | |
15781 | case BFD_RELOC_MIPS_HIGHEST: | |
15782 | case BFD_RELOC_MIPS_HIGHER: | |
15783 | case BFD_RELOC_MIPS_SCN_DISP: | |
15784 | case BFD_RELOC_MIPS_REL16: | |
15785 | case BFD_RELOC_MIPS_RELGOT: | |
15786 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15787 | case BFD_RELOC_HI16: |
15788 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15789 | case BFD_RELOC_LO16: |
cdf6fd85 | 15790 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15791 | case BFD_RELOC_MIPS_LITERAL: |
15792 | case BFD_RELOC_MIPS_CALL16: | |
15793 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15794 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15795 | case BFD_RELOC_MIPS_GOT_HI16: |
15796 | case BFD_RELOC_MIPS_GOT_LO16: | |
15797 | case BFD_RELOC_MIPS_CALL_HI16: | |
15798 | case BFD_RELOC_MIPS_CALL_LO16: | |
15799 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15800 | case BFD_RELOC_MIPS16_GOT16: |
15801 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15802 | case BFD_RELOC_MIPS16_HI16: |
15803 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15804 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15805 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15806 | case BFD_RELOC_MICROMIPS_JMP: |
15807 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15808 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15809 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15810 | case BFD_RELOC_MICROMIPS_SUB: | |
15811 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15812 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15813 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15814 | case BFD_RELOC_MICROMIPS_JALR: | |
15815 | case BFD_RELOC_MICROMIPS_HI16: | |
15816 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15817 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15818 | case BFD_RELOC_MICROMIPS_GPREL16: |
15819 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15820 | case BFD_RELOC_MICROMIPS_CALL16: | |
15821 | case BFD_RELOC_MICROMIPS_GOT16: | |
15822 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15823 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15824 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15825 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
b886a2ab RS |
15826 | if (fixP->fx_done) |
15827 | { | |
15828 | offsetT value; | |
15829 | ||
15830 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15831 | { | |
15832 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15833 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15834 | insn |= mips16_immed_extend (value, 16); | |
15835 | else | |
15836 | insn |= (value & 0xffff); | |
15837 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15838 | } | |
15839 | else | |
15840 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15841 | _("Unsupported constant in relocation")); | |
15842 | } | |
252b5132 RH |
15843 | break; |
15844 | ||
252b5132 RH |
15845 | case BFD_RELOC_64: |
15846 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15847 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15848 | if (fixP->fx_done) |
252b5132 RH |
15849 | { |
15850 | if (8 <= sizeof (valueT)) | |
4d68580a | 15851 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15852 | else |
15853 | { | |
a7ebbfdf | 15854 | valueT hiv; |
252b5132 | 15855 | |
a7ebbfdf | 15856 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15857 | hiv = 0xffffffff; |
15858 | else | |
15859 | hiv = 0; | |
4d68580a RS |
15860 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15861 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15862 | } |
15863 | } | |
15864 | break; | |
15865 | ||
056350c6 | 15866 | case BFD_RELOC_RVA: |
252b5132 | 15867 | case BFD_RELOC_32: |
b47468a6 | 15868 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15869 | case BFD_RELOC_16: |
15870 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15871 | value now. This can happen if we have a .word which is not |
15872 | resolved when it appears but is later defined. */ | |
252b5132 | 15873 | if (fixP->fx_done) |
4d68580a | 15874 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15875 | break; |
15876 | ||
252b5132 | 15877 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15878 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15879 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15880 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15881 | |
54f4ddb3 TS |
15882 | /* We need to save the bits in the instruction since fixup_segment() |
15883 | might be deleting the relocation entry (i.e., a branch within | |
15884 | the current segment). */ | |
a7ebbfdf | 15885 | if (! fixP->fx_done) |
bb2d6cd7 | 15886 | break; |
252b5132 | 15887 | |
54f4ddb3 | 15888 | /* Update old instruction data. */ |
4d68580a | 15889 | insn = read_insn (buf); |
252b5132 | 15890 | |
a7ebbfdf TS |
15891 | if (*valP + 0x20000 <= 0x3ffff) |
15892 | { | |
15893 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15894 | write_insn (buf, insn); |
a7ebbfdf TS |
15895 | } |
15896 | else if (mips_pic == NO_PIC | |
15897 | && fixP->fx_done | |
15898 | && fixP->fx_frag->fr_address >= text_section->vma | |
15899 | && (fixP->fx_frag->fr_address | |
587aac4e | 15900 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15901 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15902 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15903 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15904 | { |
15905 | /* The branch offset is too large. If this is an | |
15906 | unconditional branch, and we are not generating PIC code, | |
15907 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15908 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15909 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15910 | else |
a7ebbfdf TS |
15911 | insn = 0x08000000; /* j */ |
15912 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15913 | fixP->fx_done = 0; | |
15914 | fixP->fx_addsy = section_symbol (text_section); | |
15915 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15916 | write_insn (buf, insn); |
a7ebbfdf TS |
15917 | } |
15918 | else | |
15919 | { | |
15920 | /* If we got here, we have branch-relaxation disabled, | |
15921 | and there's nothing we can do to fix this instruction | |
15922 | without turning it into a longer sequence. */ | |
15923 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15924 | _("Branch out of range")); | |
252b5132 | 15925 | } |
252b5132 RH |
15926 | break; |
15927 | ||
df58fc94 RS |
15928 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15929 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15930 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15931 | /* We adjust the offset back to even. */ | |
15932 | if ((*valP & 0x1) != 0) | |
15933 | --(*valP); | |
15934 | ||
15935 | if (! fixP->fx_done) | |
15936 | break; | |
15937 | ||
15938 | /* Should never visit here, because we keep the relocation. */ | |
15939 | abort (); | |
15940 | break; | |
15941 | ||
252b5132 RH |
15942 | case BFD_RELOC_VTABLE_INHERIT: |
15943 | fixP->fx_done = 0; | |
15944 | if (fixP->fx_addsy | |
15945 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15946 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15947 | S_SET_WEAK (fixP->fx_addsy); | |
15948 | break; | |
15949 | ||
15950 | case BFD_RELOC_VTABLE_ENTRY: | |
15951 | fixP->fx_done = 0; | |
15952 | break; | |
15953 | ||
15954 | default: | |
b37df7c4 | 15955 | abort (); |
252b5132 | 15956 | } |
a7ebbfdf TS |
15957 | |
15958 | /* Remember value for tc_gen_reloc. */ | |
15959 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15960 | } |
15961 | ||
252b5132 | 15962 | static symbolS * |
17a2f251 | 15963 | get_symbol (void) |
252b5132 RH |
15964 | { |
15965 | int c; | |
15966 | char *name; | |
15967 | symbolS *p; | |
15968 | ||
15969 | name = input_line_pointer; | |
15970 | c = get_symbol_end (); | |
15971 | p = (symbolS *) symbol_find_or_make (name); | |
15972 | *input_line_pointer = c; | |
15973 | return p; | |
15974 | } | |
15975 | ||
742a56fe RS |
15976 | /* Align the current frag to a given power of two. If a particular |
15977 | fill byte should be used, FILL points to an integer that contains | |
15978 | that byte, otherwise FILL is null. | |
15979 | ||
462427c4 RS |
15980 | This function used to have the comment: |
15981 | ||
15982 | The MIPS assembler also automatically adjusts any preceding label. | |
15983 | ||
15984 | The implementation therefore applied the adjustment to a maximum of | |
15985 | one label. However, other label adjustments are applied to batches | |
15986 | of labels, and adjusting just one caused problems when new labels | |
15987 | were added for the sake of debugging or unwind information. | |
15988 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15989 | |
15990 | static void | |
462427c4 | 15991 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15992 | { |
7d10b47d | 15993 | mips_emit_delays (); |
df58fc94 | 15994 | mips_record_compressed_mode (); |
742a56fe RS |
15995 | if (fill == NULL && subseg_text_p (now_seg)) |
15996 | frag_align_code (to, 0); | |
15997 | else | |
15998 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15999 | record_alignment (now_seg, to); |
462427c4 | 16000 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16001 | } |
16002 | ||
16003 | /* Align to a given power of two. .align 0 turns off the automatic | |
16004 | alignment used by the data creating pseudo-ops. */ | |
16005 | ||
16006 | static void | |
17a2f251 | 16007 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16008 | { |
742a56fe | 16009 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16010 | long max_alignment = 28; |
252b5132 | 16011 | |
54f4ddb3 | 16012 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16013 | to the aligned address. |
54f4ddb3 | 16014 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16015 | a .align pseudo instruction. |
54f4ddb3 | 16016 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16017 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16018 | We don't. */ |
252b5132 RH |
16019 | |
16020 | temp = get_absolute_expression (); | |
16021 | if (temp > max_alignment) | |
16022 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16023 | else if (temp < 0) | |
16024 | { | |
16025 | as_warn (_("Alignment negative: 0 assumed.")); | |
16026 | temp = 0; | |
16027 | } | |
16028 | if (*input_line_pointer == ',') | |
16029 | { | |
f9419b05 | 16030 | ++input_line_pointer; |
742a56fe RS |
16031 | fill_value = get_absolute_expression (); |
16032 | fill_ptr = &fill_value; | |
252b5132 RH |
16033 | } |
16034 | else | |
742a56fe | 16035 | fill_ptr = 0; |
252b5132 RH |
16036 | if (temp) |
16037 | { | |
a8dbcb85 TS |
16038 | segment_info_type *si = seg_info (now_seg); |
16039 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16040 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16041 | auto_align = 1; |
462427c4 | 16042 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16043 | } |
16044 | else | |
16045 | { | |
16046 | auto_align = 0; | |
16047 | } | |
16048 | ||
16049 | demand_empty_rest_of_line (); | |
16050 | } | |
16051 | ||
252b5132 | 16052 | static void |
17a2f251 | 16053 | s_change_sec (int sec) |
252b5132 RH |
16054 | { |
16055 | segT seg; | |
16056 | ||
252b5132 RH |
16057 | #ifdef OBJ_ELF |
16058 | /* The ELF backend needs to know that we are changing sections, so | |
16059 | that .previous works correctly. We could do something like check | |
b6ff326e | 16060 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16061 | as it would not be appropriate to use it in the section changing |
16062 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16063 | This should be cleaner, somehow. */ | |
f43abd2b TS |
16064 | if (IS_ELF) |
16065 | obj_elf_section_change_hook (); | |
252b5132 RH |
16066 | #endif |
16067 | ||
7d10b47d | 16068 | mips_emit_delays (); |
6a32d874 | 16069 | |
252b5132 RH |
16070 | switch (sec) |
16071 | { | |
16072 | case 't': | |
16073 | s_text (0); | |
16074 | break; | |
16075 | case 'd': | |
16076 | s_data (0); | |
16077 | break; | |
16078 | case 'b': | |
16079 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16080 | demand_empty_rest_of_line (); | |
16081 | break; | |
16082 | ||
16083 | case 'r': | |
4d0d148d TS |
16084 | seg = subseg_new (RDATA_SECTION_NAME, |
16085 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16086 | if (IS_ELF) |
252b5132 | 16087 | { |
4d0d148d TS |
16088 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16089 | | SEC_READONLY | SEC_RELOC | |
16090 | | SEC_DATA)); | |
c41e87e3 | 16091 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16092 | record_alignment (seg, 4); |
252b5132 | 16093 | } |
4d0d148d | 16094 | demand_empty_rest_of_line (); |
252b5132 RH |
16095 | break; |
16096 | ||
16097 | case 's': | |
4d0d148d | 16098 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16099 | if (IS_ELF) |
252b5132 | 16100 | { |
4d0d148d TS |
16101 | bfd_set_section_flags (stdoutput, seg, |
16102 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16103 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16104 | record_alignment (seg, 4); |
252b5132 | 16105 | } |
4d0d148d TS |
16106 | demand_empty_rest_of_line (); |
16107 | break; | |
998b3c36 MR |
16108 | |
16109 | case 'B': | |
16110 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16111 | if (IS_ELF) | |
16112 | { | |
16113 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16114 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16115 | record_alignment (seg, 4); | |
16116 | } | |
16117 | demand_empty_rest_of_line (); | |
16118 | break; | |
252b5132 RH |
16119 | } |
16120 | ||
16121 | auto_align = 1; | |
16122 | } | |
b34976b6 | 16123 | |
cca86cc8 | 16124 | void |
17a2f251 | 16125 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16126 | { |
7ed4a06a | 16127 | #ifdef OBJ_ELF |
cca86cc8 SC |
16128 | char *section_name; |
16129 | char c; | |
684022ea | 16130 | char next_c = 0; |
cca86cc8 SC |
16131 | int section_type; |
16132 | int section_flag; | |
16133 | int section_entry_size; | |
16134 | int section_alignment; | |
b34976b6 | 16135 | |
f43abd2b | 16136 | if (!IS_ELF) |
7ed4a06a TS |
16137 | return; |
16138 | ||
cca86cc8 SC |
16139 | section_name = input_line_pointer; |
16140 | c = get_symbol_end (); | |
a816d1ed AO |
16141 | if (c) |
16142 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16143 | |
4cf0dd0d TS |
16144 | /* Do we have .section Name<,"flags">? */ |
16145 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16146 | { |
4cf0dd0d TS |
16147 | /* just after name is now '\0'. */ |
16148 | *input_line_pointer = c; | |
cca86cc8 SC |
16149 | input_line_pointer = section_name; |
16150 | obj_elf_section (ignore); | |
16151 | return; | |
16152 | } | |
16153 | input_line_pointer++; | |
16154 | ||
16155 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16156 | if (c == ',') | |
16157 | section_type = get_absolute_expression (); | |
16158 | else | |
16159 | section_type = 0; | |
16160 | if (*input_line_pointer++ == ',') | |
16161 | section_flag = get_absolute_expression (); | |
16162 | else | |
16163 | section_flag = 0; | |
16164 | if (*input_line_pointer++ == ',') | |
16165 | section_entry_size = get_absolute_expression (); | |
16166 | else | |
16167 | section_entry_size = 0; | |
16168 | if (*input_line_pointer++ == ',') | |
16169 | section_alignment = get_absolute_expression (); | |
16170 | else | |
16171 | section_alignment = 0; | |
87975d2a AM |
16172 | /* FIXME: really ignore? */ |
16173 | (void) section_alignment; | |
cca86cc8 | 16174 | |
a816d1ed AO |
16175 | section_name = xstrdup (section_name); |
16176 | ||
8ab8a5c8 RS |
16177 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16178 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16179 | traditionally had to fall back on the more common @progbits instead. | |
16180 | ||
16181 | There's nothing really harmful in this, since bfd will correct | |
16182 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16183 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16184 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16185 | ||
16186 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16187 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16188 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16189 | generic type-checking code. */ | |
16190 | if (section_type == SHT_MIPS_DWARF) | |
16191 | section_type = SHT_PROGBITS; | |
16192 | ||
cca86cc8 SC |
16193 | obj_elf_change_section (section_name, section_type, section_flag, |
16194 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16195 | |
16196 | if (now_seg->name != section_name) | |
16197 | free (section_name); | |
7ed4a06a | 16198 | #endif /* OBJ_ELF */ |
cca86cc8 | 16199 | } |
252b5132 RH |
16200 | |
16201 | void | |
17a2f251 | 16202 | mips_enable_auto_align (void) |
252b5132 RH |
16203 | { |
16204 | auto_align = 1; | |
16205 | } | |
16206 | ||
16207 | static void | |
17a2f251 | 16208 | s_cons (int log_size) |
252b5132 | 16209 | { |
a8dbcb85 TS |
16210 | segment_info_type *si = seg_info (now_seg); |
16211 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16212 | |
7d10b47d | 16213 | mips_emit_delays (); |
252b5132 | 16214 | if (log_size > 0 && auto_align) |
462427c4 | 16215 | mips_align (log_size, 0, l); |
252b5132 | 16216 | cons (1 << log_size); |
a1facbec | 16217 | mips_clear_insn_labels (); |
252b5132 RH |
16218 | } |
16219 | ||
16220 | static void | |
17a2f251 | 16221 | s_float_cons (int type) |
252b5132 | 16222 | { |
a8dbcb85 TS |
16223 | segment_info_type *si = seg_info (now_seg); |
16224 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16225 | |
7d10b47d | 16226 | mips_emit_delays (); |
252b5132 RH |
16227 | |
16228 | if (auto_align) | |
49309057 ILT |
16229 | { |
16230 | if (type == 'd') | |
462427c4 | 16231 | mips_align (3, 0, l); |
49309057 | 16232 | else |
462427c4 | 16233 | mips_align (2, 0, l); |
49309057 | 16234 | } |
252b5132 | 16235 | |
252b5132 | 16236 | float_cons (type); |
a1facbec | 16237 | mips_clear_insn_labels (); |
252b5132 RH |
16238 | } |
16239 | ||
16240 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16241 | permitted to say | |
16242 | .globl foo .text | |
16243 | where foo is an undefined symbol, to mean that foo should be | |
16244 | considered to be the address of a function. */ | |
16245 | ||
16246 | static void | |
17a2f251 | 16247 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16248 | { |
16249 | char *name; | |
16250 | int c; | |
16251 | symbolS *symbolP; | |
16252 | flagword flag; | |
16253 | ||
8a06b769 | 16254 | do |
252b5132 | 16255 | { |
8a06b769 | 16256 | name = input_line_pointer; |
252b5132 | 16257 | c = get_symbol_end (); |
8a06b769 TS |
16258 | symbolP = symbol_find_or_make (name); |
16259 | S_SET_EXTERNAL (symbolP); | |
16260 | ||
252b5132 | 16261 | *input_line_pointer = c; |
8a06b769 | 16262 | SKIP_WHITESPACE (); |
252b5132 | 16263 | |
8a06b769 TS |
16264 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16265 | being a function is apparently labelled as being an object. */ | |
16266 | flag = BSF_OBJECT; | |
252b5132 | 16267 | |
8a06b769 TS |
16268 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16269 | && (*input_line_pointer != ',')) | |
16270 | { | |
16271 | char *secname; | |
16272 | asection *sec; | |
16273 | ||
16274 | secname = input_line_pointer; | |
16275 | c = get_symbol_end (); | |
16276 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16277 | if (sec == NULL) | |
16278 | as_bad (_("%s: no such section"), secname); | |
16279 | *input_line_pointer = c; | |
16280 | ||
16281 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16282 | flag = BSF_FUNCTION; | |
16283 | } | |
16284 | ||
16285 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16286 | ||
16287 | c = *input_line_pointer; | |
16288 | if (c == ',') | |
16289 | { | |
16290 | input_line_pointer++; | |
16291 | SKIP_WHITESPACE (); | |
16292 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16293 | c = '\n'; | |
16294 | } | |
16295 | } | |
16296 | while (c == ','); | |
252b5132 | 16297 | |
252b5132 RH |
16298 | demand_empty_rest_of_line (); |
16299 | } | |
16300 | ||
16301 | static void | |
17a2f251 | 16302 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16303 | { |
16304 | char *opt; | |
16305 | char c; | |
16306 | ||
16307 | opt = input_line_pointer; | |
16308 | c = get_symbol_end (); | |
16309 | ||
16310 | if (*opt == 'O') | |
16311 | { | |
16312 | /* FIXME: What does this mean? */ | |
16313 | } | |
16314 | else if (strncmp (opt, "pic", 3) == 0) | |
16315 | { | |
16316 | int i; | |
16317 | ||
16318 | i = atoi (opt + 3); | |
16319 | if (i == 0) | |
16320 | mips_pic = NO_PIC; | |
16321 | else if (i == 2) | |
143d77c5 | 16322 | { |
8b828383 | 16323 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16324 | mips_abicalls = TRUE; |
16325 | } | |
252b5132 RH |
16326 | else |
16327 | as_bad (_(".option pic%d not supported"), i); | |
16328 | ||
4d0d148d | 16329 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16330 | { |
16331 | if (g_switch_seen && g_switch_value != 0) | |
16332 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16333 | g_switch_value = 0; | |
16334 | bfd_set_gp_size (stdoutput, 0); | |
16335 | } | |
16336 | } | |
16337 | else | |
16338 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16339 | ||
16340 | *input_line_pointer = c; | |
16341 | demand_empty_rest_of_line (); | |
16342 | } | |
16343 | ||
16344 | /* This structure is used to hold a stack of .set values. */ | |
16345 | ||
e972090a NC |
16346 | struct mips_option_stack |
16347 | { | |
252b5132 RH |
16348 | struct mips_option_stack *next; |
16349 | struct mips_set_options options; | |
16350 | }; | |
16351 | ||
16352 | static struct mips_option_stack *mips_opts_stack; | |
16353 | ||
16354 | /* Handle the .set pseudo-op. */ | |
16355 | ||
16356 | static void | |
17a2f251 | 16357 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16358 | { |
16359 | char *name = input_line_pointer, ch; | |
16360 | ||
16361 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16362 | ++input_line_pointer; |
252b5132 RH |
16363 | ch = *input_line_pointer; |
16364 | *input_line_pointer = '\0'; | |
16365 | ||
16366 | if (strcmp (name, "reorder") == 0) | |
16367 | { | |
7d10b47d RS |
16368 | if (mips_opts.noreorder) |
16369 | end_noreorder (); | |
252b5132 RH |
16370 | } |
16371 | else if (strcmp (name, "noreorder") == 0) | |
16372 | { | |
7d10b47d RS |
16373 | if (!mips_opts.noreorder) |
16374 | start_noreorder (); | |
252b5132 | 16375 | } |
741fe287 MR |
16376 | else if (strncmp (name, "at=", 3) == 0) |
16377 | { | |
16378 | char *s = name + 3; | |
16379 | ||
16380 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16381 | as_bad (_("Unrecognized register name `%s'"), s); | |
16382 | } | |
252b5132 RH |
16383 | else if (strcmp (name, "at") == 0) |
16384 | { | |
741fe287 | 16385 | mips_opts.at = ATREG; |
252b5132 RH |
16386 | } |
16387 | else if (strcmp (name, "noat") == 0) | |
16388 | { | |
741fe287 | 16389 | mips_opts.at = ZERO; |
252b5132 RH |
16390 | } |
16391 | else if (strcmp (name, "macro") == 0) | |
16392 | { | |
16393 | mips_opts.warn_about_macros = 0; | |
16394 | } | |
16395 | else if (strcmp (name, "nomacro") == 0) | |
16396 | { | |
16397 | if (mips_opts.noreorder == 0) | |
16398 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16399 | mips_opts.warn_about_macros = 1; | |
16400 | } | |
16401 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16402 | { | |
16403 | mips_opts.nomove = 0; | |
16404 | } | |
16405 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16406 | { | |
16407 | mips_opts.nomove = 1; | |
16408 | } | |
16409 | else if (strcmp (name, "bopt") == 0) | |
16410 | { | |
16411 | mips_opts.nobopt = 0; | |
16412 | } | |
16413 | else if (strcmp (name, "nobopt") == 0) | |
16414 | { | |
16415 | mips_opts.nobopt = 1; | |
16416 | } | |
ad3fea08 TS |
16417 | else if (strcmp (name, "gp=default") == 0) |
16418 | mips_opts.gp32 = file_mips_gp32; | |
16419 | else if (strcmp (name, "gp=32") == 0) | |
16420 | mips_opts.gp32 = 1; | |
16421 | else if (strcmp (name, "gp=64") == 0) | |
16422 | { | |
16423 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16424 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16425 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16426 | mips_opts.gp32 = 0; | |
16427 | } | |
16428 | else if (strcmp (name, "fp=default") == 0) | |
16429 | mips_opts.fp32 = file_mips_fp32; | |
16430 | else if (strcmp (name, "fp=32") == 0) | |
16431 | mips_opts.fp32 = 1; | |
16432 | else if (strcmp (name, "fp=64") == 0) | |
16433 | { | |
16434 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16435 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16436 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16437 | mips_opts.fp32 = 0; | |
16438 | } | |
037b32b9 AN |
16439 | else if (strcmp (name, "softfloat") == 0) |
16440 | mips_opts.soft_float = 1; | |
16441 | else if (strcmp (name, "hardfloat") == 0) | |
16442 | mips_opts.soft_float = 0; | |
16443 | else if (strcmp (name, "singlefloat") == 0) | |
16444 | mips_opts.single_float = 1; | |
16445 | else if (strcmp (name, "doublefloat") == 0) | |
16446 | mips_opts.single_float = 0; | |
252b5132 RH |
16447 | else if (strcmp (name, "mips16") == 0 |
16448 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16449 | { |
16450 | if (mips_opts.micromips == 1) | |
16451 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16452 | mips_opts.mips16 = 1; | |
16453 | } | |
252b5132 RH |
16454 | else if (strcmp (name, "nomips16") == 0 |
16455 | || strcmp (name, "noMIPS-16") == 0) | |
16456 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16457 | else if (strcmp (name, "micromips") == 0) |
16458 | { | |
16459 | if (mips_opts.mips16 == 1) | |
16460 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16461 | mips_opts.micromips = 1; | |
16462 | } | |
16463 | else if (strcmp (name, "nomicromips") == 0) | |
16464 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16465 | else if (strcmp (name, "smartmips") == 0) |
16466 | { | |
ad3fea08 | 16467 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16468 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16469 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16470 | mips_opts.ase_smartmips = 1; | |
16471 | } | |
16472 | else if (strcmp (name, "nosmartmips") == 0) | |
16473 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16474 | else if (strcmp (name, "mips3d") == 0) |
16475 | mips_opts.ase_mips3d = 1; | |
16476 | else if (strcmp (name, "nomips3d") == 0) | |
16477 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16478 | else if (strcmp (name, "mdmx") == 0) |
16479 | mips_opts.ase_mdmx = 1; | |
16480 | else if (strcmp (name, "nomdmx") == 0) | |
16481 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16482 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16483 | { |
16484 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16485 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16486 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16487 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16488 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16489 | } |
74cd071d | 16490 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16491 | { |
16492 | mips_opts.ase_dsp = 0; | |
16493 | mips_opts.ase_dspr2 = 0; | |
16494 | } | |
16495 | else if (strcmp (name, "dspr2") == 0) | |
16496 | { | |
16497 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16498 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16499 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16500 | mips_opts.ase_dspr2 = 1; | |
16501 | mips_opts.ase_dsp = 1; | |
16502 | } | |
16503 | else if (strcmp (name, "nodspr2") == 0) | |
16504 | { | |
16505 | mips_opts.ase_dspr2 = 0; | |
16506 | mips_opts.ase_dsp = 0; | |
16507 | } | |
ef2e4d86 | 16508 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16509 | { |
16510 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16511 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16512 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16513 | mips_opts.ase_mt = 1; | |
16514 | } | |
ef2e4d86 CF |
16515 | else if (strcmp (name, "nomt") == 0) |
16516 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16517 | else if (strcmp (name, "mcu") == 0) |
16518 | mips_opts.ase_mcu = 1; | |
16519 | else if (strcmp (name, "nomcu") == 0) | |
16520 | mips_opts.ase_mcu = 0; | |
b015e599 AP |
16521 | else if (strcmp (name, "virt") == 0) |
16522 | { | |
16523 | if (!ISA_SUPPORTS_VIRT_ASE) | |
16524 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
16525 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
16526 | mips_opts.ase_virt = 1; | |
16527 | } | |
16528 | else if (strcmp (name, "novirt") == 0) | |
16529 | mips_opts.ase_virt = 0; | |
1a2c1fad | 16530 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16531 | { |
af7ee8bf | 16532 | int reset = 0; |
252b5132 | 16533 | |
1a2c1fad CD |
16534 | /* Permit the user to change the ISA and architecture on the fly. |
16535 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16536 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16537 | { |
16538 | reset = 1; | |
16539 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16540 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16541 | } |
16542 | else if (strncmp (name, "arch=", 5) == 0) | |
16543 | { | |
16544 | const struct mips_cpu_info *p; | |
16545 | ||
16546 | p = mips_parse_cpu("internal use", name + 5); | |
16547 | if (!p) | |
16548 | as_bad (_("unknown architecture %s"), name + 5); | |
16549 | else | |
16550 | { | |
16551 | mips_opts.arch = p->cpu; | |
16552 | mips_opts.isa = p->isa; | |
16553 | } | |
16554 | } | |
81a21e38 TS |
16555 | else if (strncmp (name, "mips", 4) == 0) |
16556 | { | |
16557 | const struct mips_cpu_info *p; | |
16558 | ||
16559 | p = mips_parse_cpu("internal use", name); | |
16560 | if (!p) | |
16561 | as_bad (_("unknown ISA level %s"), name + 4); | |
16562 | else | |
16563 | { | |
16564 | mips_opts.arch = p->cpu; | |
16565 | mips_opts.isa = p->isa; | |
16566 | } | |
16567 | } | |
af7ee8bf | 16568 | else |
81a21e38 | 16569 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16570 | |
16571 | switch (mips_opts.isa) | |
98d3f06f KH |
16572 | { |
16573 | case 0: | |
98d3f06f | 16574 | break; |
af7ee8bf CD |
16575 | case ISA_MIPS1: |
16576 | case ISA_MIPS2: | |
16577 | case ISA_MIPS32: | |
16578 | case ISA_MIPS32R2: | |
98d3f06f KH |
16579 | mips_opts.gp32 = 1; |
16580 | mips_opts.fp32 = 1; | |
16581 | break; | |
af7ee8bf CD |
16582 | case ISA_MIPS3: |
16583 | case ISA_MIPS4: | |
16584 | case ISA_MIPS5: | |
16585 | case ISA_MIPS64: | |
5f74bc13 | 16586 | case ISA_MIPS64R2: |
98d3f06f | 16587 | mips_opts.gp32 = 0; |
e407c74b NC |
16588 | if (mips_opts.arch == CPU_R5900) |
16589 | { | |
16590 | mips_opts.fp32 = 1; | |
16591 | } | |
16592 | else | |
16593 | { | |
98d3f06f | 16594 | mips_opts.fp32 = 0; |
e407c74b | 16595 | } |
98d3f06f KH |
16596 | break; |
16597 | default: | |
16598 | as_bad (_("unknown ISA level %s"), name + 4); | |
16599 | break; | |
16600 | } | |
af7ee8bf | 16601 | if (reset) |
98d3f06f | 16602 | { |
af7ee8bf CD |
16603 | mips_opts.gp32 = file_mips_gp32; |
16604 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16605 | } |
252b5132 RH |
16606 | } |
16607 | else if (strcmp (name, "autoextend") == 0) | |
16608 | mips_opts.noautoextend = 0; | |
16609 | else if (strcmp (name, "noautoextend") == 0) | |
16610 | mips_opts.noautoextend = 1; | |
16611 | else if (strcmp (name, "push") == 0) | |
16612 | { | |
16613 | struct mips_option_stack *s; | |
16614 | ||
16615 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16616 | s->next = mips_opts_stack; | |
16617 | s->options = mips_opts; | |
16618 | mips_opts_stack = s; | |
16619 | } | |
16620 | else if (strcmp (name, "pop") == 0) | |
16621 | { | |
16622 | struct mips_option_stack *s; | |
16623 | ||
16624 | s = mips_opts_stack; | |
16625 | if (s == NULL) | |
16626 | as_bad (_(".set pop with no .set push")); | |
16627 | else | |
16628 | { | |
16629 | /* If we're changing the reorder mode we need to handle | |
16630 | delay slots correctly. */ | |
16631 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16632 | start_noreorder (); |
252b5132 | 16633 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16634 | end_noreorder (); |
252b5132 RH |
16635 | |
16636 | mips_opts = s->options; | |
16637 | mips_opts_stack = s->next; | |
16638 | free (s); | |
16639 | } | |
16640 | } | |
aed1a261 RS |
16641 | else if (strcmp (name, "sym32") == 0) |
16642 | mips_opts.sym32 = TRUE; | |
16643 | else if (strcmp (name, "nosym32") == 0) | |
16644 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16645 | else if (strchr (name, ',')) |
16646 | { | |
16647 | /* Generic ".set" directive; use the generic handler. */ | |
16648 | *input_line_pointer = ch; | |
16649 | input_line_pointer = name; | |
16650 | s_set (0); | |
16651 | return; | |
16652 | } | |
252b5132 RH |
16653 | else |
16654 | { | |
16655 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16656 | } | |
16657 | *input_line_pointer = ch; | |
16658 | demand_empty_rest_of_line (); | |
16659 | } | |
16660 | ||
16661 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16662 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16663 | ||
16664 | static void | |
17a2f251 | 16665 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16666 | { |
16667 | mips_pic = SVR4_PIC; | |
143d77c5 | 16668 | mips_abicalls = TRUE; |
4d0d148d TS |
16669 | |
16670 | if (g_switch_seen && g_switch_value != 0) | |
16671 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16672 | g_switch_value = 0; | |
16673 | ||
252b5132 RH |
16674 | bfd_set_gp_size (stdoutput, 0); |
16675 | demand_empty_rest_of_line (); | |
16676 | } | |
16677 | ||
16678 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16679 | PIC code. It sets the $gp register for the function based on the | |
16680 | function address, which is in the register named in the argument. | |
16681 | This uses a relocation against _gp_disp, which is handled specially | |
16682 | by the linker. The result is: | |
16683 | lui $gp,%hi(_gp_disp) | |
16684 | addiu $gp,$gp,%lo(_gp_disp) | |
16685 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16686 | The .cpload argument is normally $25 == $t9. |
16687 | ||
16688 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16689 | lui $gp,%hi(__gnu_local_gp) |
16690 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16691 | and the argument is ignored. This saves an instruction, but the |
16692 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16693 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16694 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16695 | |
16696 | static void | |
17a2f251 | 16697 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16698 | { |
16699 | expressionS ex; | |
aa6975fb ILT |
16700 | int reg; |
16701 | int in_shared; | |
252b5132 | 16702 | |
6478892d TS |
16703 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16704 | .cpload is ignored. */ | |
16705 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16706 | { |
16707 | s_ignore (0); | |
16708 | return; | |
16709 | } | |
16710 | ||
a276b80c MR |
16711 | if (mips_opts.mips16) |
16712 | { | |
16713 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16714 | ignore_rest_of_line (); | |
16715 | return; | |
16716 | } | |
16717 | ||
d3ecfc59 | 16718 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16719 | if (mips_opts.noreorder == 0) |
16720 | as_warn (_(".cpload not in noreorder section")); | |
16721 | ||
aa6975fb ILT |
16722 | reg = tc_get_register (0); |
16723 | ||
16724 | /* If we need to produce a 64-bit address, we are better off using | |
16725 | the default instruction sequence. */ | |
aed1a261 | 16726 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16727 | |
252b5132 | 16728 | ex.X_op = O_symbol; |
bbe506e8 TS |
16729 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16730 | "__gnu_local_gp"); | |
252b5132 RH |
16731 | ex.X_op_symbol = NULL; |
16732 | ex.X_add_number = 0; | |
16733 | ||
16734 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16735 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16736 | |
8a75745d MR |
16737 | mips_mark_labels (); |
16738 | mips_assembling_insn = TRUE; | |
16739 | ||
584892a6 | 16740 | macro_start (); |
67c0d1eb RS |
16741 | macro_build_lui (&ex, mips_gp_register); |
16742 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16743 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16744 | if (in_shared) |
16745 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16746 | mips_gp_register, reg); | |
584892a6 | 16747 | macro_end (); |
252b5132 | 16748 | |
8a75745d | 16749 | mips_assembling_insn = FALSE; |
252b5132 RH |
16750 | demand_empty_rest_of_line (); |
16751 | } | |
16752 | ||
6478892d TS |
16753 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16754 | .cpsetup $reg1, offset|$reg2, label | |
16755 | ||
16756 | If offset is given, this results in: | |
16757 | sd $gp, offset($sp) | |
956cd1d6 | 16758 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16759 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16760 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16761 | |
16762 | If $reg2 is given, this results in: | |
16763 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16764 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16765 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16766 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16767 | $reg1 is normally $25 == $t9. |
16768 | ||
16769 | The -mno-shared option replaces the last three instructions with | |
16770 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16771 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16772 | |
6478892d | 16773 | static void |
17a2f251 | 16774 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16775 | { |
16776 | expressionS ex_off; | |
16777 | expressionS ex_sym; | |
16778 | int reg1; | |
6478892d | 16779 | |
8586fc66 | 16780 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16781 | We also need NewABI support. */ |
16782 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16783 | { | |
16784 | s_ignore (0); | |
16785 | return; | |
16786 | } | |
16787 | ||
a276b80c MR |
16788 | if (mips_opts.mips16) |
16789 | { | |
16790 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16791 | ignore_rest_of_line (); | |
16792 | return; | |
16793 | } | |
16794 | ||
6478892d TS |
16795 | reg1 = tc_get_register (0); |
16796 | SKIP_WHITESPACE (); | |
16797 | if (*input_line_pointer != ',') | |
16798 | { | |
16799 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16800 | return; | |
16801 | } | |
16802 | else | |
80245285 | 16803 | ++input_line_pointer; |
6478892d TS |
16804 | SKIP_WHITESPACE (); |
16805 | if (*input_line_pointer == '$') | |
80245285 TS |
16806 | { |
16807 | mips_cpreturn_register = tc_get_register (0); | |
16808 | mips_cpreturn_offset = -1; | |
16809 | } | |
6478892d | 16810 | else |
80245285 TS |
16811 | { |
16812 | mips_cpreturn_offset = get_absolute_expression (); | |
16813 | mips_cpreturn_register = -1; | |
16814 | } | |
6478892d TS |
16815 | SKIP_WHITESPACE (); |
16816 | if (*input_line_pointer != ',') | |
16817 | { | |
16818 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16819 | return; | |
16820 | } | |
16821 | else | |
f9419b05 | 16822 | ++input_line_pointer; |
6478892d | 16823 | SKIP_WHITESPACE (); |
f21f8242 | 16824 | expression (&ex_sym); |
6478892d | 16825 | |
8a75745d MR |
16826 | mips_mark_labels (); |
16827 | mips_assembling_insn = TRUE; | |
16828 | ||
584892a6 | 16829 | macro_start (); |
6478892d TS |
16830 | if (mips_cpreturn_register == -1) |
16831 | { | |
16832 | ex_off.X_op = O_constant; | |
16833 | ex_off.X_add_symbol = NULL; | |
16834 | ex_off.X_op_symbol = NULL; | |
16835 | ex_off.X_add_number = mips_cpreturn_offset; | |
16836 | ||
67c0d1eb | 16837 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16838 | BFD_RELOC_LO16, SP); |
6478892d TS |
16839 | } |
16840 | else | |
67c0d1eb | 16841 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16842 | mips_gp_register, 0); |
6478892d | 16843 | |
aed1a261 | 16844 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16845 | { |
df58fc94 | 16846 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16847 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16848 | BFD_RELOC_HI16_S); | |
16849 | ||
16850 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16851 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16852 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16853 | ||
16854 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16855 | mips_gp_register, reg1); | |
16856 | } | |
16857 | else | |
16858 | { | |
16859 | expressionS ex; | |
16860 | ||
16861 | ex.X_op = O_symbol; | |
4184909a | 16862 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16863 | ex.X_op_symbol = NULL; |
16864 | ex.X_add_number = 0; | |
6e1304d8 | 16865 | |
aa6975fb ILT |
16866 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16867 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16868 | ||
16869 | macro_build_lui (&ex, mips_gp_register); | |
16870 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16871 | mips_gp_register, BFD_RELOC_LO16); | |
16872 | } | |
f21f8242 | 16873 | |
584892a6 | 16874 | macro_end (); |
6478892d | 16875 | |
8a75745d | 16876 | mips_assembling_insn = FALSE; |
6478892d TS |
16877 | demand_empty_rest_of_line (); |
16878 | } | |
16879 | ||
16880 | static void | |
17a2f251 | 16881 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16882 | { |
16883 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16884 | .cplocal is ignored. */ |
6478892d TS |
16885 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16886 | { | |
16887 | s_ignore (0); | |
16888 | return; | |
16889 | } | |
16890 | ||
a276b80c MR |
16891 | if (mips_opts.mips16) |
16892 | { | |
16893 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16894 | ignore_rest_of_line (); | |
16895 | return; | |
16896 | } | |
16897 | ||
6478892d | 16898 | mips_gp_register = tc_get_register (0); |
85b51719 | 16899 | demand_empty_rest_of_line (); |
6478892d TS |
16900 | } |
16901 | ||
252b5132 RH |
16902 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16903 | offset from $sp. The offset is remembered, and after making a PIC | |
16904 | call $gp is restored from that location. */ | |
16905 | ||
16906 | static void | |
17a2f251 | 16907 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16908 | { |
16909 | expressionS ex; | |
252b5132 | 16910 | |
6478892d | 16911 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16912 | .cprestore is ignored. */ |
6478892d | 16913 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16914 | { |
16915 | s_ignore (0); | |
16916 | return; | |
16917 | } | |
16918 | ||
a276b80c MR |
16919 | if (mips_opts.mips16) |
16920 | { | |
16921 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16922 | ignore_rest_of_line (); | |
16923 | return; | |
16924 | } | |
16925 | ||
252b5132 | 16926 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16927 | mips_cprestore_valid = 1; |
252b5132 RH |
16928 | |
16929 | ex.X_op = O_constant; | |
16930 | ex.X_add_symbol = NULL; | |
16931 | ex.X_op_symbol = NULL; | |
16932 | ex.X_add_number = mips_cprestore_offset; | |
16933 | ||
8a75745d MR |
16934 | mips_mark_labels (); |
16935 | mips_assembling_insn = TRUE; | |
16936 | ||
584892a6 | 16937 | macro_start (); |
67c0d1eb RS |
16938 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16939 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16940 | macro_end (); |
252b5132 | 16941 | |
8a75745d | 16942 | mips_assembling_insn = FALSE; |
252b5132 RH |
16943 | demand_empty_rest_of_line (); |
16944 | } | |
16945 | ||
6478892d | 16946 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16947 | was given in the preceding .cpsetup, it results in: |
6478892d | 16948 | ld $gp, offset($sp) |
76b3015f | 16949 | |
6478892d | 16950 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16951 | daddu $gp, $reg2, $0 */ |
16952 | ||
6478892d | 16953 | static void |
17a2f251 | 16954 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16955 | { |
16956 | expressionS ex; | |
6478892d TS |
16957 | |
16958 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16959 | We also need NewABI support. */ | |
16960 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16961 | { | |
16962 | s_ignore (0); | |
16963 | return; | |
16964 | } | |
16965 | ||
a276b80c MR |
16966 | if (mips_opts.mips16) |
16967 | { | |
16968 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16969 | ignore_rest_of_line (); | |
16970 | return; | |
16971 | } | |
16972 | ||
8a75745d MR |
16973 | mips_mark_labels (); |
16974 | mips_assembling_insn = TRUE; | |
16975 | ||
584892a6 | 16976 | macro_start (); |
6478892d TS |
16977 | if (mips_cpreturn_register == -1) |
16978 | { | |
16979 | ex.X_op = O_constant; | |
16980 | ex.X_add_symbol = NULL; | |
16981 | ex.X_op_symbol = NULL; | |
16982 | ex.X_add_number = mips_cpreturn_offset; | |
16983 | ||
67c0d1eb | 16984 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16985 | } |
16986 | else | |
67c0d1eb | 16987 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16988 | mips_cpreturn_register, 0); |
584892a6 | 16989 | macro_end (); |
6478892d | 16990 | |
8a75745d | 16991 | mips_assembling_insn = FALSE; |
6478892d TS |
16992 | demand_empty_rest_of_line (); |
16993 | } | |
16994 | ||
d0f13682 CLT |
16995 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16996 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16997 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16998 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16999 | |
17000 | static void | |
d0f13682 CLT |
17001 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17002 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17003 | { |
17004 | expressionS ex; | |
17005 | char *p; | |
17006 | ||
17007 | expression (&ex); | |
17008 | ||
17009 | if (ex.X_op != O_symbol) | |
17010 | { | |
d0f13682 | 17011 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17012 | ignore_rest_of_line (); |
17013 | } | |
17014 | ||
17015 | p = frag_more (bytes); | |
17016 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17017 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17018 | demand_empty_rest_of_line (); |
de64cffd | 17019 | mips_clear_insn_labels (); |
741d6ea8 JM |
17020 | } |
17021 | ||
17022 | /* Handle .dtprelword. */ | |
17023 | ||
17024 | static void | |
17025 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17026 | { | |
d0f13682 | 17027 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17028 | } |
17029 | ||
17030 | /* Handle .dtpreldword. */ | |
17031 | ||
17032 | static void | |
17033 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17034 | { | |
d0f13682 CLT |
17035 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17036 | } | |
17037 | ||
17038 | /* Handle .tprelword. */ | |
17039 | ||
17040 | static void | |
17041 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17042 | { | |
17043 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17044 | } | |
17045 | ||
17046 | /* Handle .tpreldword. */ | |
17047 | ||
17048 | static void | |
17049 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17050 | { | |
17051 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17052 | } |
17053 | ||
6478892d TS |
17054 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17055 | code. It sets the offset to use in gp_rel relocations. */ | |
17056 | ||
17057 | static void | |
17a2f251 | 17058 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17059 | { |
17060 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17061 | We also need NewABI support. */ | |
17062 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17063 | { | |
17064 | s_ignore (0); | |
17065 | return; | |
17066 | } | |
17067 | ||
def2e0dd | 17068 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17069 | |
17070 | demand_empty_rest_of_line (); | |
17071 | } | |
17072 | ||
252b5132 RH |
17073 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17074 | code. It generates a 32 bit GP relative reloc. */ | |
17075 | ||
17076 | static void | |
17a2f251 | 17077 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17078 | { |
a8dbcb85 TS |
17079 | segment_info_type *si; |
17080 | struct insn_label_list *l; | |
252b5132 RH |
17081 | expressionS ex; |
17082 | char *p; | |
17083 | ||
17084 | /* When not generating PIC code, this is treated as .word. */ | |
17085 | if (mips_pic != SVR4_PIC) | |
17086 | { | |
17087 | s_cons (2); | |
17088 | return; | |
17089 | } | |
17090 | ||
a8dbcb85 TS |
17091 | si = seg_info (now_seg); |
17092 | l = si->label_list; | |
7d10b47d | 17093 | mips_emit_delays (); |
252b5132 | 17094 | if (auto_align) |
462427c4 | 17095 | mips_align (2, 0, l); |
252b5132 RH |
17096 | |
17097 | expression (&ex); | |
a1facbec | 17098 | mips_clear_insn_labels (); |
252b5132 RH |
17099 | |
17100 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17101 | { | |
17102 | as_bad (_("Unsupported use of .gpword")); | |
17103 | ignore_rest_of_line (); | |
17104 | } | |
17105 | ||
17106 | p = frag_more (4); | |
17a2f251 | 17107 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17108 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17109 | BFD_RELOC_GPREL32); |
252b5132 RH |
17110 | |
17111 | demand_empty_rest_of_line (); | |
17112 | } | |
17113 | ||
10181a0d | 17114 | static void |
17a2f251 | 17115 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17116 | { |
a8dbcb85 TS |
17117 | segment_info_type *si; |
17118 | struct insn_label_list *l; | |
10181a0d AO |
17119 | expressionS ex; |
17120 | char *p; | |
17121 | ||
17122 | /* When not generating PIC code, this is treated as .dword. */ | |
17123 | if (mips_pic != SVR4_PIC) | |
17124 | { | |
17125 | s_cons (3); | |
17126 | return; | |
17127 | } | |
17128 | ||
a8dbcb85 TS |
17129 | si = seg_info (now_seg); |
17130 | l = si->label_list; | |
7d10b47d | 17131 | mips_emit_delays (); |
10181a0d | 17132 | if (auto_align) |
462427c4 | 17133 | mips_align (3, 0, l); |
10181a0d AO |
17134 | |
17135 | expression (&ex); | |
a1facbec | 17136 | mips_clear_insn_labels (); |
10181a0d AO |
17137 | |
17138 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17139 | { | |
17140 | as_bad (_("Unsupported use of .gpdword")); | |
17141 | ignore_rest_of_line (); | |
17142 | } | |
17143 | ||
17144 | p = frag_more (8); | |
17a2f251 | 17145 | md_number_to_chars (p, 0, 8); |
a105a300 | 17146 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17147 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17148 | |
17149 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17150 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17151 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17152 | |
17153 | demand_empty_rest_of_line (); | |
17154 | } | |
17155 | ||
252b5132 RH |
17156 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17157 | tables in SVR4 PIC code. */ | |
17158 | ||
17159 | static void | |
17a2f251 | 17160 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17161 | { |
252b5132 RH |
17162 | int reg; |
17163 | ||
10181a0d AO |
17164 | /* This is ignored when not generating SVR4 PIC code. */ |
17165 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17166 | { |
17167 | s_ignore (0); | |
17168 | return; | |
17169 | } | |
17170 | ||
8a75745d MR |
17171 | mips_mark_labels (); |
17172 | mips_assembling_insn = TRUE; | |
17173 | ||
252b5132 | 17174 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17175 | macro_start (); |
252b5132 | 17176 | reg = tc_get_register (0); |
67c0d1eb | 17177 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17178 | macro_end (); |
252b5132 | 17179 | |
8a75745d | 17180 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17181 | demand_empty_rest_of_line (); |
252b5132 RH |
17182 | } |
17183 | ||
17184 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17185 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17186 | such as generating jalx instructions when needed. We also make |
17187 | them odd for the duration of the assembly, in order to generate the | |
17188 | right sort of code. We will make them even in the adjust_symtab | |
17189 | routine, while leaving them marked. This is convenient for the | |
17190 | debugger and the disassembler. The linker knows to make them odd | |
17191 | again. */ | |
17192 | ||
17193 | static void | |
17a2f251 | 17194 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17195 | { |
df58fc94 | 17196 | mips_mark_labels (); |
252b5132 RH |
17197 | |
17198 | demand_empty_rest_of_line (); | |
17199 | } | |
17200 | ||
754e2bb9 RS |
17201 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17202 | implemented in a transparent way, so that removing them would not | |
17203 | have any effect on the generated instructions. However, s_stab | |
17204 | internally changes the section, so in practice we need to decide | |
17205 | now whether the preceding label marks compressed code. We do not | |
17206 | support changing the compression mode of a label after a .stab* | |
17207 | directive, such as in: | |
17208 | ||
17209 | foo: | |
17210 | .stabs ... | |
17211 | .set mips16 | |
17212 | ||
17213 | so the current mode wins. */ | |
252b5132 RH |
17214 | |
17215 | static void | |
17a2f251 | 17216 | s_mips_stab (int type) |
252b5132 | 17217 | { |
754e2bb9 | 17218 | mips_mark_labels (); |
252b5132 RH |
17219 | s_stab (type); |
17220 | } | |
17221 | ||
54f4ddb3 | 17222 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17223 | |
17224 | static void | |
17a2f251 | 17225 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17226 | { |
17227 | char *name; | |
17228 | int c; | |
17229 | symbolS *symbolP; | |
17230 | expressionS exp; | |
17231 | ||
17232 | name = input_line_pointer; | |
17233 | c = get_symbol_end (); | |
17234 | symbolP = symbol_find_or_make (name); | |
17235 | S_SET_WEAK (symbolP); | |
17236 | *input_line_pointer = c; | |
17237 | ||
17238 | SKIP_WHITESPACE (); | |
17239 | ||
17240 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17241 | { | |
17242 | if (S_IS_DEFINED (symbolP)) | |
17243 | { | |
20203fb9 | 17244 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17245 | S_GET_NAME (symbolP)); |
17246 | ignore_rest_of_line (); | |
17247 | return; | |
17248 | } | |
bdaaa2e1 | 17249 | |
252b5132 RH |
17250 | if (*input_line_pointer == ',') |
17251 | { | |
17252 | ++input_line_pointer; | |
17253 | SKIP_WHITESPACE (); | |
17254 | } | |
bdaaa2e1 | 17255 | |
252b5132 RH |
17256 | expression (&exp); |
17257 | if (exp.X_op != O_symbol) | |
17258 | { | |
20203fb9 | 17259 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17260 | ignore_rest_of_line (); |
252b5132 RH |
17261 | return; |
17262 | } | |
49309057 | 17263 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17264 | } |
17265 | ||
17266 | demand_empty_rest_of_line (); | |
17267 | } | |
17268 | ||
17269 | /* Parse a register string into a number. Called from the ECOFF code | |
17270 | to parse .frame. The argument is non-zero if this is the frame | |
17271 | register, so that we can record it in mips_frame_reg. */ | |
17272 | ||
17273 | int | |
17a2f251 | 17274 | tc_get_register (int frame) |
252b5132 | 17275 | { |
707bfff6 | 17276 | unsigned int reg; |
252b5132 RH |
17277 | |
17278 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17279 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17280 | reg = 0; | |
252b5132 | 17281 | if (frame) |
7a621144 DJ |
17282 | { |
17283 | mips_frame_reg = reg != 0 ? reg : SP; | |
17284 | mips_frame_reg_valid = 1; | |
17285 | mips_cprestore_valid = 0; | |
17286 | } | |
252b5132 RH |
17287 | return reg; |
17288 | } | |
17289 | ||
17290 | valueT | |
17a2f251 | 17291 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17292 | { |
17293 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17294 | ||
b4c71f56 TS |
17295 | if (IS_ELF) |
17296 | { | |
17297 | /* We don't need to align ELF sections to the full alignment. | |
17298 | However, Irix 5 may prefer that we align them at least to a 16 | |
17299 | byte boundary. We don't bother to align the sections if we | |
17300 | are targeted for an embedded system. */ | |
c41e87e3 | 17301 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17302 | return addr; |
17303 | if (align > 4) | |
17304 | align = 4; | |
17305 | } | |
252b5132 RH |
17306 | |
17307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17308 | } | |
17309 | ||
17310 | /* Utility routine, called from above as well. If called while the | |
17311 | input file is still being read, it's only an approximation. (For | |
17312 | example, a symbol may later become defined which appeared to be | |
17313 | undefined earlier.) */ | |
17314 | ||
17315 | static int | |
17a2f251 | 17316 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17317 | { |
17318 | if (sym == 0) | |
17319 | return 0; | |
17320 | ||
4d0d148d | 17321 | if (g_switch_value > 0) |
252b5132 RH |
17322 | { |
17323 | const char *symname; | |
17324 | int change; | |
17325 | ||
c9914766 | 17326 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17327 | register. It can be if it is smaller than the -G size or if |
17328 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17329 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17330 | they can. */ |
17331 | symname = S_GET_NAME (sym); | |
17332 | if (symname != (const char *) NULL | |
17333 | && (strcmp (symname, "eprol") == 0 | |
17334 | || strcmp (symname, "etext") == 0 | |
17335 | || strcmp (symname, "_gp") == 0 | |
17336 | || strcmp (symname, "edata") == 0 | |
17337 | || strcmp (symname, "_fbss") == 0 | |
17338 | || strcmp (symname, "_fdata") == 0 | |
17339 | || strcmp (symname, "_ftext") == 0 | |
17340 | || strcmp (symname, "end") == 0 | |
17341 | || strcmp (symname, "_gp_disp") == 0)) | |
17342 | change = 1; | |
17343 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17344 | && (0 | |
17345 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17346 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17347 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17348 | <= g_switch_value)) | |
252b5132 RH |
17349 | #endif |
17350 | /* We must defer this decision until after the whole | |
17351 | file has been read, since there might be a .extern | |
17352 | after the first use of this symbol. */ | |
17353 | || (before_relaxing | |
17354 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17355 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17356 | #endif |
17357 | && S_GET_VALUE (sym) == 0) | |
17358 | || (S_GET_VALUE (sym) != 0 | |
17359 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17360 | change = 0; | |
17361 | else | |
17362 | { | |
17363 | const char *segname; | |
17364 | ||
17365 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17366 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17367 | && strcmp (segname, ".lit4") != 0); |
17368 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17369 | && strcmp (segname, ".sbss") != 0 |
17370 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17371 | && strncmp (segname, ".sbss.", 6) != 0 |
17372 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17373 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17374 | } |
17375 | return change; | |
17376 | } | |
17377 | else | |
c9914766 | 17378 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17379 | return 1; |
17380 | } | |
17381 | ||
5919d012 RS |
17382 | |
17383 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17384 | ||
17385 | static bfd_boolean | |
17a2f251 | 17386 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17387 | { |
17388 | asection *symsec; | |
5919d012 RS |
17389 | |
17390 | /* Handle the case of a symbol equated to another symbol. */ | |
17391 | while (symbol_equated_reloc_p (sym)) | |
17392 | { | |
17393 | symbolS *n; | |
17394 | ||
5f0fe04b | 17395 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17396 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17397 | if (n == sym) | |
17398 | break; | |
17399 | sym = n; | |
17400 | } | |
17401 | ||
df1f3cda DD |
17402 | if (symbol_section_p (sym)) |
17403 | return TRUE; | |
17404 | ||
5919d012 RS |
17405 | symsec = S_GET_SEGMENT (sym); |
17406 | ||
5919d012 | 17407 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17408 | return (!bfd_is_und_section (symsec) |
17409 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17410 | && !bfd_is_com_section (symsec) |
17411 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17412 | #ifdef OBJ_ELF |
17413 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17414 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17415 | #endif |
17416 | ); | |
17417 | } | |
17418 | ||
17419 | ||
252b5132 RH |
17420 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17421 | extended opcode. SEC is the section the frag is in. */ | |
17422 | ||
17423 | static int | |
17a2f251 | 17424 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17425 | { |
17426 | int type; | |
3994f87e | 17427 | const struct mips16_immed_operand *op; |
252b5132 RH |
17428 | offsetT val; |
17429 | int mintiny, maxtiny; | |
17430 | segT symsec; | |
98aa84af | 17431 | fragS *sym_frag; |
252b5132 RH |
17432 | |
17433 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17434 | return 0; | |
17435 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17436 | return 1; | |
17437 | ||
17438 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17439 | op = mips16_immed_operands; | |
17440 | while (op->type != type) | |
17441 | { | |
17442 | ++op; | |
9c2799c2 | 17443 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17444 | } |
17445 | ||
17446 | if (op->unsp) | |
17447 | { | |
17448 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17449 | { | |
17450 | mintiny = 1; | |
17451 | maxtiny = 1 << op->nbits; | |
17452 | } | |
17453 | else | |
17454 | { | |
17455 | mintiny = 0; | |
17456 | maxtiny = (1 << op->nbits) - 1; | |
17457 | } | |
17458 | } | |
17459 | else | |
17460 | { | |
17461 | mintiny = - (1 << (op->nbits - 1)); | |
17462 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17463 | } | |
17464 | ||
98aa84af | 17465 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17466 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17467 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17468 | |
17469 | if (op->pcrel) | |
17470 | { | |
17471 | addressT addr; | |
17472 | ||
17473 | /* We won't have the section when we are called from | |
17474 | mips_relax_frag. However, we will always have been called | |
17475 | from md_estimate_size_before_relax first. If this is a | |
17476 | branch to a different section, we mark it as such. If SEC is | |
17477 | NULL, and the frag is not marked, then it must be a branch to | |
17478 | the same section. */ | |
17479 | if (sec == NULL) | |
17480 | { | |
17481 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17482 | return 1; | |
17483 | } | |
17484 | else | |
17485 | { | |
98aa84af | 17486 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17487 | if (symsec != sec) |
17488 | { | |
17489 | fragp->fr_subtype = | |
17490 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17491 | ||
17492 | /* FIXME: We should support this, and let the linker | |
17493 | catch branches and loads that are out of range. */ | |
17494 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17495 | _("unsupported PC relative reference to different section")); | |
17496 | ||
17497 | return 1; | |
17498 | } | |
98aa84af AM |
17499 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17500 | /* Assume non-extended on the first relaxation pass. | |
17501 | The address we have calculated will be bogus if this is | |
17502 | a forward branch to another frag, as the forward frag | |
17503 | will have fr_address == 0. */ | |
17504 | return 0; | |
252b5132 RH |
17505 | } |
17506 | ||
17507 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17508 | the same section. If the relax_marker of the symbol fragment |
17509 | differs from the relax_marker of this fragment, we have not | |
17510 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17511 | in STRETCH in order to get a better estimate of the address. |
17512 | This particularly matters because of the shift bits. */ | |
17513 | if (stretch != 0 | |
98aa84af | 17514 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17515 | { |
17516 | fragS *f; | |
17517 | ||
17518 | /* Adjust stretch for any alignment frag. Note that if have | |
17519 | been expanding the earlier code, the symbol may be | |
17520 | defined in what appears to be an earlier frag. FIXME: | |
17521 | This doesn't handle the fr_subtype field, which specifies | |
17522 | a maximum number of bytes to skip when doing an | |
17523 | alignment. */ | |
98aa84af | 17524 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17525 | { |
17526 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17527 | { | |
17528 | if (stretch < 0) | |
17529 | stretch = - ((- stretch) | |
17530 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17531 | else | |
17532 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17533 | if (stretch == 0) | |
17534 | break; | |
17535 | } | |
17536 | } | |
17537 | if (f != NULL) | |
17538 | val += stretch; | |
17539 | } | |
17540 | ||
17541 | addr = fragp->fr_address + fragp->fr_fix; | |
17542 | ||
17543 | /* The base address rules are complicated. The base address of | |
17544 | a branch is the following instruction. The base address of a | |
17545 | PC relative load or add is the instruction itself, but if it | |
17546 | is in a delay slot (in which case it can not be extended) use | |
17547 | the address of the instruction whose delay slot it is in. */ | |
17548 | if (type == 'p' || type == 'q') | |
17549 | { | |
17550 | addr += 2; | |
17551 | ||
17552 | /* If we are currently assuming that this frag should be | |
17553 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17554 | higher. */ |
252b5132 RH |
17555 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17556 | addr += 2; | |
17557 | ||
17558 | /* Ignore the low bit in the target, since it will be set | |
17559 | for a text label. */ | |
17560 | if ((val & 1) != 0) | |
17561 | --val; | |
17562 | } | |
17563 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17564 | addr -= 4; | |
17565 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17566 | addr -= 2; | |
17567 | ||
17568 | val -= addr & ~ ((1 << op->shift) - 1); | |
17569 | ||
17570 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17571 | if (type == 'p' || type == 'q') | |
17572 | val /= 2; | |
17573 | ||
17574 | /* If any of the shifted bits are set, we must use an extended | |
17575 | opcode. If the address depends on the size of this | |
17576 | instruction, this can lead to a loop, so we arrange to always | |
17577 | use an extended opcode. We only check this when we are in | |
17578 | the main relaxation loop, when SEC is NULL. */ | |
17579 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17580 | { | |
17581 | fragp->fr_subtype = | |
17582 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17583 | return 1; | |
17584 | } | |
17585 | ||
17586 | /* If we are about to mark a frag as extended because the value | |
17587 | is precisely maxtiny + 1, then there is a chance of an | |
17588 | infinite loop as in the following code: | |
17589 | la $4,foo | |
17590 | .skip 1020 | |
17591 | .align 2 | |
17592 | foo: | |
17593 | In this case when the la is extended, foo is 0x3fc bytes | |
17594 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17595 | the la must be extended. To avoid this loop, we mark the | |
17596 | frag as extended if it was small, and is about to become | |
17597 | extended with a value of maxtiny + 1. */ | |
17598 | if (val == ((maxtiny + 1) << op->shift) | |
17599 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17600 | && sec == NULL) | |
17601 | { | |
17602 | fragp->fr_subtype = | |
17603 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17604 | return 1; | |
17605 | } | |
17606 | } | |
17607 | else if (symsec != absolute_section && sec != NULL) | |
17608 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17609 | ||
17610 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17611 | || val < (mintiny << op->shift) | |
17612 | || val > (maxtiny << op->shift)) | |
17613 | return 1; | |
17614 | else | |
17615 | return 0; | |
17616 | } | |
17617 | ||
4a6a3df4 AO |
17618 | /* Compute the length of a branch sequence, and adjust the |
17619 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17620 | worst-case length is computed, with UPDATE being used to indicate | |
17621 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17622 | branch is to be computed. */ | |
17623 | static int | |
17a2f251 | 17624 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17625 | { |
b34976b6 | 17626 | bfd_boolean toofar; |
4a6a3df4 AO |
17627 | int length; |
17628 | ||
17629 | if (fragp | |
17630 | && S_IS_DEFINED (fragp->fr_symbol) | |
17631 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17632 | { | |
17633 | addressT addr; | |
17634 | offsetT val; | |
17635 | ||
17636 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17637 | ||
17638 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17639 | ||
17640 | val -= addr; | |
17641 | ||
17642 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17643 | } | |
17644 | else if (fragp) | |
17645 | /* If the symbol is not defined or it's in a different segment, | |
17646 | assume the user knows what's going on and emit a short | |
17647 | branch. */ | |
b34976b6 | 17648 | toofar = FALSE; |
4a6a3df4 | 17649 | else |
b34976b6 | 17650 | toofar = TRUE; |
4a6a3df4 AO |
17651 | |
17652 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17653 | fragp->fr_subtype | |
66b3e8da MR |
17654 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17655 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17656 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17657 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17658 | toofar); | |
17659 | ||
17660 | length = 4; | |
17661 | if (toofar) | |
17662 | { | |
17663 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17664 | length += 8; | |
17665 | ||
17666 | if (mips_pic != NO_PIC) | |
17667 | { | |
17668 | /* Additional space for PIC loading of target address. */ | |
17669 | length += 8; | |
17670 | if (mips_opts.isa == ISA_MIPS1) | |
17671 | /* Additional space for $at-stabilizing nop. */ | |
17672 | length += 4; | |
17673 | } | |
17674 | ||
17675 | /* If branch is conditional. */ | |
17676 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17677 | length += 8; | |
17678 | } | |
b34976b6 | 17679 | |
4a6a3df4 AO |
17680 | return length; |
17681 | } | |
17682 | ||
df58fc94 RS |
17683 | /* Compute the length of a branch sequence, and adjust the |
17684 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17685 | worst-case length is computed, with UPDATE being used to indicate | |
17686 | whether an unconditional (-1), or regular (0) branch is to be | |
17687 | computed. */ | |
17688 | ||
17689 | static int | |
17690 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17691 | { | |
17692 | bfd_boolean toofar; | |
17693 | int length; | |
17694 | ||
17695 | if (fragp | |
17696 | && S_IS_DEFINED (fragp->fr_symbol) | |
17697 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17698 | { | |
17699 | addressT addr; | |
17700 | offsetT val; | |
17701 | ||
17702 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17703 | /* Ignore the low bit in the target, since it will be set | |
17704 | for a text label. */ | |
17705 | if ((val & 1) != 0) | |
17706 | --val; | |
17707 | ||
17708 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17709 | ||
17710 | val -= addr; | |
17711 | ||
17712 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17713 | } | |
17714 | else if (fragp) | |
17715 | /* If the symbol is not defined or it's in a different segment, | |
17716 | assume the user knows what's going on and emit a short | |
17717 | branch. */ | |
17718 | toofar = FALSE; | |
17719 | else | |
17720 | toofar = TRUE; | |
17721 | ||
17722 | if (fragp && update | |
17723 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17724 | fragp->fr_subtype = (toofar | |
17725 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17726 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17727 | ||
17728 | length = 4; | |
17729 | if (toofar) | |
17730 | { | |
17731 | bfd_boolean compact_known = fragp != NULL; | |
17732 | bfd_boolean compact = FALSE; | |
17733 | bfd_boolean uncond; | |
17734 | ||
17735 | if (compact_known) | |
17736 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17737 | if (fragp) | |
17738 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17739 | else | |
17740 | uncond = update < 0; | |
17741 | ||
17742 | /* If label is out of range, we turn branch <br>: | |
17743 | ||
17744 | <br> label # 4 bytes | |
17745 | 0: | |
17746 | ||
17747 | into: | |
17748 | ||
17749 | j label # 4 bytes | |
17750 | nop # 2 bytes if compact && !PIC | |
17751 | 0: | |
17752 | */ | |
17753 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17754 | length += 2; | |
17755 | ||
17756 | /* If assembling PIC code, we further turn: | |
17757 | ||
17758 | j label # 4 bytes | |
17759 | ||
17760 | into: | |
17761 | ||
17762 | lw/ld at, %got(label)(gp) # 4 bytes | |
17763 | d/addiu at, %lo(label) # 4 bytes | |
17764 | jr/c at # 2 bytes | |
17765 | */ | |
17766 | if (mips_pic != NO_PIC) | |
17767 | length += 6; | |
17768 | ||
17769 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17770 | ||
17771 | <brneg> 0f # 4 bytes | |
17772 | nop # 2 bytes if !compact | |
17773 | */ | |
17774 | if (!uncond) | |
17775 | length += (compact_known && compact) ? 4 : 6; | |
17776 | } | |
17777 | ||
17778 | return length; | |
17779 | } | |
17780 | ||
17781 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17782 | bit accordingly. */ | |
17783 | ||
17784 | static int | |
17785 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17786 | { | |
17787 | bfd_boolean toofar; | |
17788 | ||
df58fc94 RS |
17789 | if (fragp |
17790 | && S_IS_DEFINED (fragp->fr_symbol) | |
17791 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17792 | { | |
17793 | addressT addr; | |
17794 | offsetT val; | |
17795 | int type; | |
17796 | ||
17797 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17798 | /* Ignore the low bit in the target, since it will be set | |
17799 | for a text label. */ | |
17800 | if ((val & 1) != 0) | |
17801 | --val; | |
17802 | ||
17803 | /* Assume this is a 2-byte branch. */ | |
17804 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17805 | ||
17806 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17807 | long branches. */ | |
17808 | ||
17809 | val -= addr; | |
17810 | ||
17811 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17812 | if (type == 'D') | |
17813 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17814 | else if (type == 'E') | |
17815 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17816 | else | |
17817 | abort (); | |
17818 | } | |
17819 | else | |
17820 | /* If the symbol is not defined or it's in a different segment, | |
17821 | we emit a normal 32-bit branch. */ | |
17822 | toofar = TRUE; | |
17823 | ||
17824 | if (fragp && update | |
17825 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17826 | fragp->fr_subtype | |
17827 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17828 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17829 | ||
17830 | if (toofar) | |
17831 | return 4; | |
17832 | ||
17833 | return 2; | |
17834 | } | |
17835 | ||
252b5132 RH |
17836 | /* Estimate the size of a frag before relaxing. Unless this is the |
17837 | mips16, we are not really relaxing here, and the final size is | |
17838 | encoded in the subtype information. For the mips16, we have to | |
17839 | decide whether we are using an extended opcode or not. */ | |
17840 | ||
252b5132 | 17841 | int |
17a2f251 | 17842 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17843 | { |
5919d012 | 17844 | int change; |
252b5132 | 17845 | |
4a6a3df4 AO |
17846 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17847 | { | |
17848 | ||
b34976b6 AM |
17849 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17850 | ||
4a6a3df4 AO |
17851 | return fragp->fr_var; |
17852 | } | |
17853 | ||
252b5132 | 17854 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17855 | /* We don't want to modify the EXTENDED bit here; it might get us |
17856 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17857 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17858 | |
df58fc94 RS |
17859 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17860 | { | |
17861 | int length = 4; | |
17862 | ||
17863 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17864 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17865 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17866 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17867 | fragp->fr_var = length; | |
17868 | ||
17869 | return length; | |
17870 | } | |
17871 | ||
252b5132 | 17872 | if (mips_pic == NO_PIC) |
5919d012 | 17873 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17874 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17875 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17876 | else if (mips_pic == VXWORKS_PIC) |
17877 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17878 | change = 0; | |
252b5132 RH |
17879 | else |
17880 | abort (); | |
17881 | ||
17882 | if (change) | |
17883 | { | |
4d7206a2 | 17884 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17885 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17886 | } |
4d7206a2 RS |
17887 | else |
17888 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17889 | } |
17890 | ||
17891 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17892 | should be converted into a reloc against a section. */ |
252b5132 RH |
17893 | |
17894 | int | |
17a2f251 | 17895 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17896 | { |
252b5132 RH |
17897 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17898 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17899 | return 0; | |
a161fe53 | 17900 | |
252b5132 RH |
17901 | if (fixp->fx_addsy == NULL) |
17902 | return 1; | |
a161fe53 | 17903 | |
de7e6852 RS |
17904 | /* If symbol SYM is in a mergeable section, relocations of the form |
17905 | SYM + 0 can usually be made section-relative. The mergeable data | |
17906 | is then identified by the section offset rather than by the symbol. | |
17907 | ||
17908 | However, if we're generating REL LO16 relocations, the offset is split | |
17909 | between the LO16 and parterning high part relocation. The linker will | |
17910 | need to recalculate the complete offset in order to correctly identify | |
17911 | the merge data. | |
17912 | ||
17913 | The linker has traditionally not looked for the parterning high part | |
17914 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17915 | placed anywhere. Rather than break backwards compatibility by changing | |
17916 | this, it seems better not to force the issue, and instead keep the | |
17917 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17918 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17919 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17920 | && HAVE_IN_PLACE_ADDENDS |
17921 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17922 | return 0; | |
17923 | ||
ce70d90a | 17924 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17925 | Likewise an in-range offset of limited PC-relative relocations may |
17926 | overflow the in-place relocatable field if recalculated against the | |
17927 | start address of the symbol's containing section. */ | |
ce70d90a | 17928 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17929 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17930 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17931 | return 0; |
17932 | ||
252b5132 | 17933 | #ifdef OBJ_ELF |
b314ec0e RS |
17934 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17935 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17936 | relocations against MIPS16 functions; in this case, the stub becomes | |
17937 | the function's canonical address. | |
17938 | ||
17939 | Floating-point stubs are stored in unique .mips16.call.* or | |
17940 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17941 | the first relocation in section S must be against F; this is how the | |
17942 | linker determines the target function. All relocations that might | |
17943 | resolve to T must also be against F. We therefore have the following | |
17944 | restrictions, which are given in an intentionally-redundant way: | |
17945 | ||
17946 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17947 | symbols. | |
17948 | ||
17949 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17950 | if that stub might be used. | |
17951 | ||
17952 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17953 | symbols. | |
17954 | ||
17955 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17956 | that stub might be used. | |
17957 | ||
17958 | There is a further restriction: | |
17959 | ||
df58fc94 RS |
17960 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17961 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17962 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17963 | encode the low bit. |
17964 | ||
df58fc94 RS |
17965 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17966 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17967 | such relocations on REL targets. | |
b314ec0e RS |
17968 | |
17969 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17970 | relocation against some symbol R, no relocation against R may be | |
17971 | reduced. (Note that this deals with (2) as well as (1) because | |
17972 | relocations against global symbols will never be reduced on ELF | |
17973 | targets.) This approach is a little simpler than trying to detect | |
17974 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17975 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17976 | if (IS_ELF |
b314ec0e | 17977 | && fixp->fx_subsy == NULL |
30c09090 | 17978 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17979 | || *symbol_get_tc (fixp->fx_addsy) |
17980 | || (HAVE_IN_PLACE_ADDENDS | |
17981 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17982 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17983 | return 0; |
17984 | #endif | |
a161fe53 | 17985 | |
252b5132 RH |
17986 | return 1; |
17987 | } | |
17988 | ||
17989 | /* Translate internal representation of relocation info to BFD target | |
17990 | format. */ | |
17991 | ||
17992 | arelent ** | |
17a2f251 | 17993 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17994 | { |
17995 | static arelent *retval[4]; | |
17996 | arelent *reloc; | |
17997 | bfd_reloc_code_real_type code; | |
17998 | ||
4b0cff4e TS |
17999 | memset (retval, 0, sizeof(retval)); |
18000 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18001 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18002 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18003 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18004 | ||
bad36eac DJ |
18005 | if (fixp->fx_pcrel) |
18006 | { | |
df58fc94 RS |
18007 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18008 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18009 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18010 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18011 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18012 | |
18013 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18014 | Relocations want only the symbol offset. */ | |
18015 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 18016 | if (!IS_ELF) |
bad36eac DJ |
18017 | { |
18018 | /* A gruesome hack which is a result of the gruesome gas | |
18019 | reloc handling. What's worse, for COFF (as opposed to | |
18020 | ECOFF), we might need yet another copy of reloc->address. | |
18021 | See bfd_install_relocation. */ | |
18022 | reloc->addend += reloc->address; | |
18023 | } | |
18024 | } | |
18025 | else | |
18026 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18027 | |
438c16b8 TS |
18028 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18029 | entry to be used in the relocation's section offset. */ | |
18030 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18031 | { |
18032 | reloc->address = reloc->addend; | |
18033 | reloc->addend = 0; | |
18034 | } | |
18035 | ||
252b5132 | 18036 | code = fixp->fx_r_type; |
252b5132 | 18037 | |
bad36eac | 18038 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18039 | if (reloc->howto == NULL) |
18040 | { | |
18041 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18042 | _("Can not represent %s relocation in this object file format"), | |
18043 | bfd_get_reloc_code_name (code)); | |
18044 | retval[0] = NULL; | |
18045 | } | |
18046 | ||
18047 | return retval; | |
18048 | } | |
18049 | ||
18050 | /* Relax a machine dependent frag. This returns the amount by which | |
18051 | the current size of the frag should change. */ | |
18052 | ||
18053 | int | |
17a2f251 | 18054 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18055 | { |
4a6a3df4 AO |
18056 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18057 | { | |
18058 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18059 | |
18060 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18061 | |
18062 | return fragp->fr_var - old_var; | |
18063 | } | |
18064 | ||
df58fc94 RS |
18065 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18066 | { | |
18067 | offsetT old_var = fragp->fr_var; | |
18068 | offsetT new_var = 4; | |
18069 | ||
18070 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18071 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18072 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18073 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18074 | fragp->fr_var = new_var; | |
18075 | ||
18076 | return new_var - old_var; | |
18077 | } | |
18078 | ||
252b5132 RH |
18079 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18080 | return 0; | |
18081 | ||
c4e7957c | 18082 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18083 | { |
18084 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18085 | return 0; | |
18086 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18087 | return 2; | |
18088 | } | |
18089 | else | |
18090 | { | |
18091 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18092 | return 0; | |
18093 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18094 | return -2; | |
18095 | } | |
18096 | ||
18097 | return 0; | |
18098 | } | |
18099 | ||
18100 | /* Convert a machine dependent frag. */ | |
18101 | ||
18102 | void | |
17a2f251 | 18103 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18104 | { |
4a6a3df4 AO |
18105 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18106 | { | |
4d68580a | 18107 | char *buf; |
4a6a3df4 AO |
18108 | unsigned long insn; |
18109 | expressionS exp; | |
18110 | fixS *fixp; | |
b34976b6 | 18111 | |
4d68580a RS |
18112 | buf = fragp->fr_literal + fragp->fr_fix; |
18113 | insn = read_insn (buf); | |
b34976b6 | 18114 | |
4a6a3df4 AO |
18115 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18116 | { | |
18117 | /* We generate a fixup instead of applying it right now | |
18118 | because, if there are linker relaxations, we're going to | |
18119 | need the relocations. */ | |
18120 | exp.X_op = O_symbol; | |
18121 | exp.X_add_symbol = fragp->fr_symbol; | |
18122 | exp.X_add_number = fragp->fr_offset; | |
18123 | ||
4d68580a RS |
18124 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18125 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18126 | fixp->fx_file = fragp->fr_file; |
18127 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18128 | |
4d68580a | 18129 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18130 | } |
18131 | else | |
18132 | { | |
18133 | int i; | |
18134 | ||
18135 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18136 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18137 | |
18138 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18139 | goto uncond; | |
18140 | ||
18141 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18142 | { | |
18143 | /* Reverse the branch. */ | |
18144 | switch ((insn >> 28) & 0xf) | |
18145 | { | |
18146 | case 4: | |
18147 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
18148 | have the condition reversed by tweaking a single | |
18149 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 18150 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
18151 | insn ^= 0x00010000; |
18152 | break; | |
18153 | ||
18154 | case 0: | |
18155 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18156 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18157 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18158 | insn ^= 0x00010000; |
18159 | break; | |
b34976b6 | 18160 | |
4a6a3df4 AO |
18161 | case 1: |
18162 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18163 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18164 | insn ^= 0x04000000; |
18165 | break; | |
18166 | ||
18167 | default: | |
18168 | abort (); | |
18169 | } | |
18170 | } | |
18171 | ||
18172 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18173 | { | |
18174 | /* Clear the and-link bit. */ | |
9c2799c2 | 18175 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18176 | |
54f4ddb3 TS |
18177 | /* bltzal 0x04100000 bgezal 0x04110000 |
18178 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18179 | insn &= ~0x00100000; |
18180 | } | |
18181 | ||
18182 | /* Branch over the branch (if the branch was likely) or the | |
18183 | full jump (not likely case). Compute the offset from the | |
18184 | current instruction to branch to. */ | |
18185 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18186 | i = 16; | |
18187 | else | |
18188 | { | |
18189 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18190 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18191 | /* How many bytes in instructions from here to the end? */ |
18192 | i = fragp->fr_var - i; | |
18193 | } | |
18194 | /* Convert to instruction count. */ | |
18195 | i >>= 2; | |
18196 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18197 | i--; |
4a6a3df4 AO |
18198 | insn |= i; |
18199 | /* Branch over the jump. */ | |
4d68580a | 18200 | buf = write_insn (buf, insn); |
4a6a3df4 | 18201 | |
54f4ddb3 | 18202 | /* nop */ |
4d68580a | 18203 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18204 | |
18205 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18206 | { | |
18207 | /* beql $0, $0, 2f */ | |
18208 | insn = 0x50000000; | |
18209 | /* Compute the PC offset from the current instruction to | |
18210 | the end of the variable frag. */ | |
18211 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18212 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18213 | /* How many bytes in instructions from here to the end? */ |
18214 | i = fragp->fr_var - i; | |
18215 | /* Convert to instruction count. */ | |
18216 | i >>= 2; | |
18217 | /* Don't decrement i, because we want to branch over the | |
18218 | delay slot. */ | |
4a6a3df4 | 18219 | insn |= i; |
4a6a3df4 | 18220 | |
4d68580a RS |
18221 | buf = write_insn (buf, insn); |
18222 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18223 | } |
18224 | ||
18225 | uncond: | |
18226 | if (mips_pic == NO_PIC) | |
18227 | { | |
18228 | /* j or jal. */ | |
18229 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18230 | ? 0x0c000000 : 0x08000000); | |
18231 | exp.X_op = O_symbol; | |
18232 | exp.X_add_symbol = fragp->fr_symbol; | |
18233 | exp.X_add_number = fragp->fr_offset; | |
18234 | ||
4d68580a RS |
18235 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18236 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18237 | fixp->fx_file = fragp->fr_file; |
18238 | fixp->fx_line = fragp->fr_line; | |
18239 | ||
4d68580a | 18240 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18241 | } |
18242 | else | |
18243 | { | |
66b3e8da MR |
18244 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18245 | ||
4a6a3df4 | 18246 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18247 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18248 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18249 | exp.X_op = O_symbol; |
18250 | exp.X_add_symbol = fragp->fr_symbol; | |
18251 | exp.X_add_number = fragp->fr_offset; | |
18252 | ||
18253 | if (fragp->fr_offset) | |
18254 | { | |
18255 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18256 | exp.X_add_number = 0; | |
18257 | } | |
18258 | ||
4d68580a RS |
18259 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18260 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18261 | fixp->fx_file = fragp->fr_file; |
18262 | fixp->fx_line = fragp->fr_line; | |
18263 | ||
4d68580a | 18264 | buf = write_insn (buf, insn); |
b34976b6 | 18265 | |
4a6a3df4 | 18266 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18267 | /* nop */ |
18268 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18269 | |
18270 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18271 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18272 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18273 | |
4d68580a RS |
18274 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18275 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18276 | fixp->fx_file = fragp->fr_file; |
18277 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18278 | |
4d68580a | 18279 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18280 | |
18281 | /* j(al)r $at. */ | |
18282 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18283 | insn = 0x0000f809; |
4a6a3df4 | 18284 | else |
66b3e8da MR |
18285 | insn = 0x00000008; |
18286 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18287 | |
4d68580a | 18288 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18289 | } |
18290 | } | |
18291 | ||
4a6a3df4 | 18292 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18293 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18294 | return; |
18295 | } | |
18296 | ||
df58fc94 RS |
18297 | /* Relax microMIPS branches. */ |
18298 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18299 | { | |
4d68580a | 18300 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18301 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18302 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18303 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18304 | bfd_boolean short_ds; |
df58fc94 RS |
18305 | unsigned long insn; |
18306 | expressionS exp; | |
18307 | fixS *fixp; | |
18308 | ||
18309 | exp.X_op = O_symbol; | |
18310 | exp.X_add_symbol = fragp->fr_symbol; | |
18311 | exp.X_add_number = fragp->fr_offset; | |
18312 | ||
18313 | fragp->fr_fix += fragp->fr_var; | |
18314 | ||
18315 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18316 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18317 | { | |
18318 | /* We generate a fixup instead of applying it right now, | |
18319 | because if there is linker relaxation, we're going to | |
18320 | need the relocations. */ | |
18321 | if (type == 'D') | |
4d68580a | 18322 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18323 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18324 | else if (type == 'E') | |
4d68580a | 18325 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18326 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18327 | else | |
18328 | abort (); | |
18329 | ||
18330 | fixp->fx_file = fragp->fr_file; | |
18331 | fixp->fx_line = fragp->fr_line; | |
18332 | ||
18333 | /* These relocations can have an addend that won't fit in | |
18334 | 2 octets. */ | |
18335 | fixp->fx_no_overflow = 1; | |
18336 | ||
18337 | return; | |
18338 | } | |
18339 | ||
2309ddf2 | 18340 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18341 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18342 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18343 | { | |
18344 | /* We generate a fixup instead of applying it right now, | |
18345 | because if there is linker relaxation, we're going to | |
18346 | need the relocations. */ | |
4d68580a RS |
18347 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18348 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18349 | fixp->fx_file = fragp->fr_file; |
18350 | fixp->fx_line = fragp->fr_line; | |
18351 | ||
18352 | if (type == 0) | |
18353 | return; | |
18354 | } | |
18355 | ||
18356 | /* Relax 16-bit branches to 32-bit branches. */ | |
18357 | if (type != 0) | |
18358 | { | |
4d68580a | 18359 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18360 | |
18361 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18362 | insn = 0x94000000; /* beq */ | |
18363 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18364 | { | |
18365 | unsigned long regno; | |
18366 | ||
18367 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18368 | regno = micromips_to_32_reg_d_map [regno]; | |
18369 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18370 | insn |= regno << MICROMIPSOP_SH_RS; | |
18371 | } | |
18372 | else | |
18373 | abort (); | |
18374 | ||
18375 | /* Nothing else to do, just write it out. */ | |
18376 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18377 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18378 | { | |
4d68580a RS |
18379 | buf = write_compressed_insn (buf, insn, 4); |
18380 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18381 | return; |
18382 | } | |
18383 | } | |
18384 | else | |
4d68580a | 18385 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18386 | |
18387 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18388 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18389 | _("Relaxed out-of-range branch into a jump")); | |
18390 | ||
2309ddf2 MR |
18391 | /* Set the short-delay-slot bit. */ |
18392 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18393 | |
18394 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18395 | { | |
18396 | symbolS *l; | |
18397 | ||
18398 | /* Reverse the branch. */ | |
18399 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18400 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18401 | insn ^= 0x20000000; | |
18402 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18403 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18404 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18405 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18406 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18407 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18408 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18409 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18410 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18411 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18412 | insn ^= 0x00400000; | |
18413 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18414 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18415 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18416 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18417 | insn ^= 0x00200000; | |
18418 | else | |
18419 | abort (); | |
18420 | ||
18421 | if (al) | |
18422 | { | |
18423 | /* Clear the and-link and short-delay-slot bits. */ | |
18424 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18425 | ||
18426 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18427 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18428 | insn &= ~0x02200000; | |
18429 | } | |
18430 | ||
18431 | /* Make a label at the end for use with the branch. */ | |
18432 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18433 | micromips_label_inc (); | |
18434 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18435 | if (IS_ELF) | |
18436 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18437 | #endif | |
18438 | ||
18439 | /* Refer to it. */ | |
4d68580a RS |
18440 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18441 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18442 | fixp->fx_file = fragp->fr_file; |
18443 | fixp->fx_line = fragp->fr_line; | |
18444 | ||
18445 | /* Branch over the jump. */ | |
4d68580a | 18446 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18447 | if (!compact) |
4d68580a RS |
18448 | /* nop */ |
18449 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18450 | } |
18451 | ||
18452 | if (mips_pic == NO_PIC) | |
18453 | { | |
2309ddf2 MR |
18454 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18455 | ||
df58fc94 RS |
18456 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18457 | insn = al ? jal : 0xd4000000; | |
18458 | ||
4d68580a RS |
18459 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18460 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18461 | fixp->fx_file = fragp->fr_file; |
18462 | fixp->fx_line = fragp->fr_line; | |
18463 | ||
4d68580a | 18464 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18465 | if (compact) |
4d68580a RS |
18466 | /* nop */ |
18467 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18468 | } |
18469 | else | |
18470 | { | |
18471 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18472 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18473 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18474 | |
18475 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18476 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18477 | insn |= at << MICROMIPSOP_SH_RT; | |
18478 | ||
18479 | if (exp.X_add_number) | |
18480 | { | |
18481 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18482 | exp.X_add_number = 0; | |
18483 | } | |
18484 | ||
4d68580a RS |
18485 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18486 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18487 | fixp->fx_file = fragp->fr_file; |
18488 | fixp->fx_line = fragp->fr_line; | |
18489 | ||
4d68580a | 18490 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18491 | |
18492 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18493 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18494 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18495 | ||
4d68580a RS |
18496 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18497 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18498 | fixp->fx_file = fragp->fr_file; |
18499 | fixp->fx_line = fragp->fr_line; | |
18500 | ||
4d68580a | 18501 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18502 | |
18503 | /* jr/jrc/jalr/jalrs $at */ | |
18504 | insn = al ? jalr : jr; | |
18505 | insn |= at << MICROMIPSOP_SH_MJ; | |
18506 | ||
4d68580a | 18507 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18508 | } |
18509 | ||
4d68580a | 18510 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18511 | return; |
18512 | } | |
18513 | ||
252b5132 RH |
18514 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18515 | { | |
18516 | int type; | |
3994f87e | 18517 | const struct mips16_immed_operand *op; |
252b5132 | 18518 | offsetT val; |
5c04167a RS |
18519 | char *buf; |
18520 | unsigned int user_length, length; | |
252b5132 | 18521 | unsigned long insn; |
5c04167a | 18522 | bfd_boolean ext; |
252b5132 RH |
18523 | |
18524 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18525 | op = mips16_immed_operands; | |
18526 | while (op->type != type) | |
18527 | ++op; | |
18528 | ||
5c04167a | 18529 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18530 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18531 | if (op->pcrel) |
18532 | { | |
18533 | addressT addr; | |
18534 | ||
18535 | addr = fragp->fr_address + fragp->fr_fix; | |
18536 | ||
18537 | /* The rules for the base address of a PC relative reloc are | |
18538 | complicated; see mips16_extended_frag. */ | |
18539 | if (type == 'p' || type == 'q') | |
18540 | { | |
18541 | addr += 2; | |
18542 | if (ext) | |
18543 | addr += 2; | |
18544 | /* Ignore the low bit in the target, since it will be | |
18545 | set for a text label. */ | |
18546 | if ((val & 1) != 0) | |
18547 | --val; | |
18548 | } | |
18549 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18550 | addr -= 4; | |
18551 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18552 | addr -= 2; | |
18553 | ||
18554 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18555 | val -= addr; | |
18556 | ||
18557 | /* Make sure the section winds up with the alignment we have | |
18558 | assumed. */ | |
18559 | if (op->shift > 0) | |
18560 | record_alignment (asec, op->shift); | |
18561 | } | |
18562 | ||
18563 | if (ext | |
18564 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18565 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18566 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18567 | _("extended instruction in delay slot")); | |
18568 | ||
5c04167a | 18569 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18570 | |
4d68580a | 18571 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18572 | if (ext) |
18573 | insn |= MIPS16_EXTEND; | |
252b5132 | 18574 | |
5c04167a RS |
18575 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18576 | user_length = 4; | |
18577 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18578 | user_length = 2; | |
18579 | else | |
18580 | user_length = 0; | |
18581 | ||
43c0598f | 18582 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18583 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18584 | |
5c04167a RS |
18585 | length = (ext ? 4 : 2); |
18586 | gas_assert (mips16_opcode_length (insn) == length); | |
18587 | write_compressed_insn (buf, insn, length); | |
18588 | fragp->fr_fix += length; | |
252b5132 RH |
18589 | } |
18590 | else | |
18591 | { | |
df58fc94 RS |
18592 | relax_substateT subtype = fragp->fr_subtype; |
18593 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18594 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18595 | int first, second; |
18596 | fixS *fixp; | |
252b5132 | 18597 | |
df58fc94 RS |
18598 | first = RELAX_FIRST (subtype); |
18599 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18600 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18601 | |
df58fc94 RS |
18602 | /* If the delay slot chosen does not match the size of the instruction, |
18603 | then emit a warning. */ | |
18604 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18605 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18606 | { | |
18607 | relax_substateT s; | |
18608 | const char *msg; | |
18609 | ||
18610 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18611 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18612 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18613 | msg = macro_warning (s); | |
18614 | if (msg != NULL) | |
db9b2be4 | 18615 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18616 | subtype &= ~s; |
18617 | } | |
18618 | ||
584892a6 | 18619 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18620 | if (use_second == second_longer) |
584892a6 | 18621 | { |
df58fc94 RS |
18622 | relax_substateT s; |
18623 | const char *msg; | |
18624 | ||
18625 | s = (subtype | |
18626 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18627 | msg = macro_warning (s); | |
18628 | if (msg != NULL) | |
db9b2be4 | 18629 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18630 | subtype &= ~s; |
584892a6 RS |
18631 | } |
18632 | ||
4d7206a2 RS |
18633 | /* Go through all the fixups for the first sequence. Disable them |
18634 | (by marking them as done) if we're going to use the second | |
18635 | sequence instead. */ | |
18636 | while (fixp | |
18637 | && fixp->fx_frag == fragp | |
18638 | && fixp->fx_where < fragp->fr_fix - second) | |
18639 | { | |
df58fc94 | 18640 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18641 | fixp->fx_done = 1; |
18642 | fixp = fixp->fx_next; | |
18643 | } | |
252b5132 | 18644 | |
4d7206a2 RS |
18645 | /* Go through the fixups for the second sequence. Disable them if |
18646 | we're going to use the first sequence, otherwise adjust their | |
18647 | addresses to account for the relaxation. */ | |
18648 | while (fixp && fixp->fx_frag == fragp) | |
18649 | { | |
df58fc94 | 18650 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18651 | fixp->fx_where -= first; |
18652 | else | |
18653 | fixp->fx_done = 1; | |
18654 | fixp = fixp->fx_next; | |
18655 | } | |
18656 | ||
18657 | /* Now modify the frag contents. */ | |
df58fc94 | 18658 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18659 | { |
18660 | char *start; | |
18661 | ||
18662 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18663 | memmove (start, start + first, second); | |
18664 | fragp->fr_fix -= first; | |
18665 | } | |
18666 | else | |
18667 | fragp->fr_fix -= second; | |
252b5132 RH |
18668 | } |
18669 | } | |
18670 | ||
18671 | #ifdef OBJ_ELF | |
18672 | ||
18673 | /* This function is called after the relocs have been generated. | |
18674 | We've been storing mips16 text labels as odd. Here we convert them | |
18675 | back to even for the convenience of the debugger. */ | |
18676 | ||
18677 | void | |
17a2f251 | 18678 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18679 | { |
18680 | asymbol **syms; | |
18681 | unsigned int count, i; | |
18682 | ||
f43abd2b | 18683 | if (!IS_ELF) |
252b5132 RH |
18684 | return; |
18685 | ||
18686 | syms = bfd_get_outsymbols (stdoutput); | |
18687 | count = bfd_get_symcount (stdoutput); | |
18688 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18689 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18690 | && ((*syms)->value & 1) != 0) | |
18691 | { | |
18692 | (*syms)->value &= ~1; | |
18693 | /* If the symbol has an odd size, it was probably computed | |
18694 | incorrectly, so adjust that as well. */ | |
18695 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18696 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18697 | } | |
252b5132 RH |
18698 | } |
18699 | ||
18700 | #endif | |
18701 | ||
a1facbec MR |
18702 | /* This function is called whenever a label is defined, including fake |
18703 | labels instantiated off the dot special symbol. It is used when | |
18704 | handling branch delays; if a branch has a label, we assume we cannot | |
18705 | move it. This also bumps the value of the symbol by 1 in compressed | |
18706 | code. */ | |
252b5132 | 18707 | |
e1b47bd5 | 18708 | static void |
a1facbec | 18709 | mips_record_label (symbolS *sym) |
252b5132 | 18710 | { |
a8dbcb85 | 18711 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18712 | struct insn_label_list *l; |
18713 | ||
18714 | if (free_insn_labels == NULL) | |
18715 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18716 | else | |
18717 | { | |
18718 | l = free_insn_labels; | |
18719 | free_insn_labels = l->next; | |
18720 | } | |
18721 | ||
18722 | l->label = sym; | |
a8dbcb85 TS |
18723 | l->next = si->label_list; |
18724 | si->label_list = l; | |
a1facbec | 18725 | } |
07a53e5c | 18726 | |
a1facbec MR |
18727 | /* This function is called as tc_frob_label() whenever a label is defined |
18728 | and adds a DWARF-2 record we only want for true labels. */ | |
18729 | ||
18730 | void | |
18731 | mips_define_label (symbolS *sym) | |
18732 | { | |
18733 | mips_record_label (sym); | |
07a53e5c RH |
18734 | #ifdef OBJ_ELF |
18735 | dwarf2_emit_label (sym); | |
18736 | #endif | |
252b5132 | 18737 | } |
e1b47bd5 RS |
18738 | |
18739 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18740 | is defined. */ | |
18741 | ||
18742 | void | |
18743 | mips_add_dot_label (symbolS *sym) | |
18744 | { | |
18745 | mips_record_label (sym); | |
18746 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18747 | mips_compressed_mark_label (sym); | |
18748 | } | |
252b5132 RH |
18749 | \f |
18750 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18751 | ||
18752 | /* Some special processing for a MIPS ELF file. */ | |
18753 | ||
18754 | void | |
17a2f251 | 18755 | mips_elf_final_processing (void) |
252b5132 RH |
18756 | { |
18757 | /* Write out the register information. */ | |
316f5878 | 18758 | if (mips_abi != N64_ABI) |
252b5132 RH |
18759 | { |
18760 | Elf32_RegInfo s; | |
18761 | ||
18762 | s.ri_gprmask = mips_gprmask; | |
18763 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18764 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18765 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18766 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18767 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18768 | ||
18769 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18770 | ((Elf32_External_RegInfo *) | |
18771 | mips_regmask_frag)); | |
18772 | } | |
18773 | else | |
18774 | { | |
18775 | Elf64_Internal_RegInfo s; | |
18776 | ||
18777 | s.ri_gprmask = mips_gprmask; | |
18778 | s.ri_pad = 0; | |
18779 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18780 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18781 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18782 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18783 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18784 | ||
18785 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18786 | ((Elf64_External_RegInfo *) | |
18787 | mips_regmask_frag)); | |
18788 | } | |
18789 | ||
18790 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18791 | sort of BFD interface for this. */ | |
18792 | if (mips_any_noreorder) | |
18793 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18794 | if (mips_pic != NO_PIC) | |
143d77c5 | 18795 | { |
8b828383 | 18796 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18797 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18798 | } | |
18799 | if (mips_abicalls) | |
18800 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18801 | |
b015e599 AP |
18802 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18803 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18804 | if (file_ase_mips16) |
18805 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18806 | if (file_ase_micromips) |
18807 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18808 | #if 0 /* XXX FIXME */ |
18809 | if (file_ase_mips3d) | |
18810 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18811 | #endif | |
deec1734 CD |
18812 | if (file_ase_mdmx) |
18813 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18814 | |
bdaaa2e1 | 18815 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18816 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18817 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18818 | else if (mips_abi == O64_ABI) |
252b5132 | 18819 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18820 | else if (mips_abi == EABI_ABI) |
252b5132 | 18821 | { |
316f5878 | 18822 | if (!file_mips_gp32) |
252b5132 RH |
18823 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18824 | else | |
18825 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18826 | } | |
316f5878 | 18827 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18828 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18829 | ||
c9914766 | 18830 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18831 | |
18832 | if (mips_32bitmode) | |
18833 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18834 | |
18835 | #if 0 /* XXX FIXME */ | |
18836 | /* 32 bit code with 64 bit FP registers. */ | |
18837 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18838 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18839 | #endif | |
252b5132 RH |
18840 | } |
18841 | ||
18842 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18843 | \f | |
beae10d5 | 18844 | typedef struct proc { |
9b2f1d35 EC |
18845 | symbolS *func_sym; |
18846 | symbolS *func_end_sym; | |
beae10d5 KH |
18847 | unsigned long reg_mask; |
18848 | unsigned long reg_offset; | |
18849 | unsigned long fpreg_mask; | |
18850 | unsigned long fpreg_offset; | |
18851 | unsigned long frame_offset; | |
18852 | unsigned long frame_reg; | |
18853 | unsigned long pc_reg; | |
18854 | } procS; | |
252b5132 RH |
18855 | |
18856 | static procS cur_proc; | |
18857 | static procS *cur_proc_ptr; | |
18858 | static int numprocs; | |
18859 | ||
df58fc94 RS |
18860 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18861 | as "2", and a normal nop as "0". */ | |
18862 | ||
18863 | #define NOP_OPCODE_MIPS 0 | |
18864 | #define NOP_OPCODE_MIPS16 1 | |
18865 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18866 | |
18867 | char | |
18868 | mips_nop_opcode (void) | |
18869 | { | |
df58fc94 RS |
18870 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18871 | return NOP_OPCODE_MICROMIPS; | |
18872 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18873 | return NOP_OPCODE_MIPS16; | |
18874 | else | |
18875 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18876 | } |
18877 | ||
df58fc94 RS |
18878 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18879 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18880 | |
0a9ef439 | 18881 | void |
17a2f251 | 18882 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18883 | { |
df58fc94 | 18884 | char nop_opcode; |
742a56fe | 18885 | char *p; |
c67a084a NC |
18886 | int bytes, size, excess; |
18887 | valueT opcode; | |
742a56fe | 18888 | |
0a9ef439 RH |
18889 | if (fragp->fr_type != rs_align_code) |
18890 | return; | |
18891 | ||
742a56fe | 18892 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18893 | nop_opcode = *p; |
18894 | switch (nop_opcode) | |
a19d8eb0 | 18895 | { |
df58fc94 RS |
18896 | case NOP_OPCODE_MICROMIPS: |
18897 | opcode = micromips_nop32_insn.insn_opcode; | |
18898 | size = 4; | |
18899 | break; | |
18900 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18901 | opcode = mips16_nop_insn.insn_opcode; |
18902 | size = 2; | |
df58fc94 RS |
18903 | break; |
18904 | case NOP_OPCODE_MIPS: | |
18905 | default: | |
c67a084a NC |
18906 | opcode = nop_insn.insn_opcode; |
18907 | size = 4; | |
df58fc94 | 18908 | break; |
c67a084a | 18909 | } |
a19d8eb0 | 18910 | |
c67a084a NC |
18911 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18912 | excess = bytes % size; | |
df58fc94 RS |
18913 | |
18914 | /* Handle the leading part if we're not inserting a whole number of | |
18915 | instructions, and make it the end of the fixed part of the frag. | |
18916 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18917 | and use zeroes otherwise. */ | |
18918 | gas_assert (excess < 4); | |
18919 | fragp->fr_fix += excess; | |
18920 | switch (excess) | |
c67a084a | 18921 | { |
df58fc94 RS |
18922 | case 3: |
18923 | *p++ = '\0'; | |
18924 | /* Fall through. */ | |
18925 | case 2: | |
18926 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18927 | { | |
4d68580a | 18928 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18929 | break; |
18930 | } | |
18931 | *p++ = '\0'; | |
18932 | /* Fall through. */ | |
18933 | case 1: | |
18934 | *p++ = '\0'; | |
18935 | /* Fall through. */ | |
18936 | case 0: | |
18937 | break; | |
a19d8eb0 | 18938 | } |
c67a084a NC |
18939 | |
18940 | md_number_to_chars (p, opcode, size); | |
18941 | fragp->fr_var = size; | |
a19d8eb0 CP |
18942 | } |
18943 | ||
252b5132 | 18944 | static void |
17a2f251 | 18945 | md_obj_begin (void) |
252b5132 RH |
18946 | { |
18947 | } | |
18948 | ||
18949 | static void | |
17a2f251 | 18950 | md_obj_end (void) |
252b5132 | 18951 | { |
54f4ddb3 | 18952 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18953 | if (cur_proc_ptr) |
9a41af64 | 18954 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18955 | } |
18956 | ||
18957 | static long | |
17a2f251 | 18958 | get_number (void) |
252b5132 RH |
18959 | { |
18960 | int negative = 0; | |
18961 | long val = 0; | |
18962 | ||
18963 | if (*input_line_pointer == '-') | |
18964 | { | |
18965 | ++input_line_pointer; | |
18966 | negative = 1; | |
18967 | } | |
3882b010 | 18968 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18969 | as_bad (_("expected simple number")); |
252b5132 RH |
18970 | if (input_line_pointer[0] == '0') |
18971 | { | |
18972 | if (input_line_pointer[1] == 'x') | |
18973 | { | |
18974 | input_line_pointer += 2; | |
3882b010 | 18975 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18976 | { |
18977 | val <<= 4; | |
18978 | val |= hex_value (*input_line_pointer++); | |
18979 | } | |
18980 | return negative ? -val : val; | |
18981 | } | |
18982 | else | |
18983 | { | |
18984 | ++input_line_pointer; | |
3882b010 | 18985 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18986 | { |
18987 | val <<= 3; | |
18988 | val |= *input_line_pointer++ - '0'; | |
18989 | } | |
18990 | return negative ? -val : val; | |
18991 | } | |
18992 | } | |
3882b010 | 18993 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18994 | { |
18995 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18996 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18997 | as_warn (_("invalid number")); |
252b5132 RH |
18998 | return -1; |
18999 | } | |
3882b010 | 19000 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19001 | { |
19002 | val *= 10; | |
19003 | val += *input_line_pointer++ - '0'; | |
19004 | } | |
19005 | return negative ? -val : val; | |
19006 | } | |
19007 | ||
19008 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19009 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19010 | case .file implies DWARF-2. */ | |
19011 | ||
19012 | static void | |
17a2f251 | 19013 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19014 | { |
ecb4347a DJ |
19015 | static int first_file_directive = 0; |
19016 | ||
c5dd6aab DJ |
19017 | if (ECOFF_DEBUGGING) |
19018 | { | |
19019 | get_number (); | |
19020 | s_app_file (0); | |
19021 | } | |
19022 | else | |
ecb4347a DJ |
19023 | { |
19024 | char *filename; | |
19025 | ||
19026 | filename = dwarf2_directive_file (0); | |
19027 | ||
19028 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19029 | directive even for stabs output. Make sure that this | |
19030 | ".file" is handled. Note that you need a version of GCC | |
19031 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19032 | if (filename != NULL && ! first_file_directive) | |
19033 | { | |
19034 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19035 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19036 | } |
19037 | first_file_directive = 1; | |
19038 | } | |
c5dd6aab DJ |
19039 | } |
19040 | ||
19041 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19042 | |
19043 | static void | |
17a2f251 | 19044 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19045 | { |
c5dd6aab DJ |
19046 | if (!ECOFF_DEBUGGING) |
19047 | dwarf2_directive_loc (0); | |
252b5132 RH |
19048 | } |
19049 | ||
252b5132 RH |
19050 | /* The .end directive. */ |
19051 | ||
19052 | static void | |
17a2f251 | 19053 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19054 | { |
19055 | symbolS *p; | |
252b5132 | 19056 | |
7a621144 DJ |
19057 | /* Following functions need their own .frame and .cprestore directives. */ |
19058 | mips_frame_reg_valid = 0; | |
19059 | mips_cprestore_valid = 0; | |
19060 | ||
252b5132 RH |
19061 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19062 | { | |
19063 | p = get_symbol (); | |
19064 | demand_empty_rest_of_line (); | |
19065 | } | |
19066 | else | |
19067 | p = NULL; | |
19068 | ||
14949570 | 19069 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19070 | as_warn (_(".end not in text section")); |
19071 | ||
19072 | if (!cur_proc_ptr) | |
19073 | { | |
19074 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19075 | demand_empty_rest_of_line (); | |
19076 | return; | |
19077 | } | |
19078 | ||
19079 | if (p != NULL) | |
19080 | { | |
9c2799c2 | 19081 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19082 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19083 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19084 | |
19085 | if (debug_type == DEBUG_STABS) | |
19086 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19087 | S_GET_NAME (p)); | |
252b5132 RH |
19088 | } |
19089 | else | |
19090 | as_warn (_(".end directive missing or unknown symbol")); | |
19091 | ||
2132e3a3 | 19092 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19093 | /* Create an expression to calculate the size of the function. */ |
19094 | if (p && cur_proc_ptr) | |
19095 | { | |
19096 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19097 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19098 | ||
19099 | obj->size = exp; | |
19100 | exp->X_op = O_subtract; | |
19101 | exp->X_add_symbol = symbol_temp_new_now (); | |
19102 | exp->X_op_symbol = p; | |
19103 | exp->X_add_number = 0; | |
19104 | ||
19105 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19106 | } | |
19107 | ||
ecb4347a | 19108 | /* Generate a .pdr section. */ |
f43abd2b | 19109 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19110 | { |
19111 | segT saved_seg = now_seg; | |
19112 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19113 | expressionS exp; |
19114 | char *fragp; | |
252b5132 | 19115 | |
252b5132 | 19116 | #ifdef md_flush_pending_output |
ecb4347a | 19117 | md_flush_pending_output (); |
252b5132 RH |
19118 | #endif |
19119 | ||
9c2799c2 | 19120 | gas_assert (pdr_seg); |
ecb4347a | 19121 | subseg_set (pdr_seg, 0); |
252b5132 | 19122 | |
ecb4347a DJ |
19123 | /* Write the symbol. */ |
19124 | exp.X_op = O_symbol; | |
19125 | exp.X_add_symbol = p; | |
19126 | exp.X_add_number = 0; | |
19127 | emit_expr (&exp, 4); | |
252b5132 | 19128 | |
ecb4347a | 19129 | fragp = frag_more (7 * 4); |
252b5132 | 19130 | |
17a2f251 TS |
19131 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19132 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19133 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19134 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19135 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19136 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19137 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19138 | |
ecb4347a DJ |
19139 | subseg_set (saved_seg, saved_subseg); |
19140 | } | |
19141 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19142 | |
19143 | cur_proc_ptr = NULL; | |
19144 | } | |
19145 | ||
19146 | /* The .aent and .ent directives. */ | |
19147 | ||
19148 | static void | |
17a2f251 | 19149 | s_mips_ent (int aent) |
252b5132 | 19150 | { |
252b5132 | 19151 | symbolS *symbolP; |
252b5132 RH |
19152 | |
19153 | symbolP = get_symbol (); | |
19154 | if (*input_line_pointer == ',') | |
f9419b05 | 19155 | ++input_line_pointer; |
252b5132 | 19156 | SKIP_WHITESPACE (); |
3882b010 | 19157 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19158 | || *input_line_pointer == '-') |
874e8986 | 19159 | get_number (); |
252b5132 | 19160 | |
14949570 | 19161 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19162 | as_warn (_(".ent or .aent not in text section.")); |
19163 | ||
19164 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19165 | as_warn (_("missing .end")); |
252b5132 RH |
19166 | |
19167 | if (!aent) | |
19168 | { | |
7a621144 DJ |
19169 | /* This function needs its own .frame and .cprestore directives. */ |
19170 | mips_frame_reg_valid = 0; | |
19171 | mips_cprestore_valid = 0; | |
19172 | ||
252b5132 RH |
19173 | cur_proc_ptr = &cur_proc; |
19174 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19175 | ||
9b2f1d35 | 19176 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19177 | |
f9419b05 | 19178 | ++numprocs; |
ecb4347a DJ |
19179 | |
19180 | if (debug_type == DEBUG_STABS) | |
19181 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19182 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19183 | } |
19184 | ||
7c0fc524 MR |
19185 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19186 | ||
252b5132 RH |
19187 | demand_empty_rest_of_line (); |
19188 | } | |
19189 | ||
19190 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19191 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19192 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19193 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19194 | symbol table (in the mdebug section). */ |
19195 | ||
19196 | static void | |
17a2f251 | 19197 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19198 | { |
ecb4347a | 19199 | #ifdef OBJ_ELF |
f43abd2b | 19200 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19201 | { |
19202 | long val; | |
252b5132 | 19203 | |
ecb4347a DJ |
19204 | if (cur_proc_ptr == (procS *) NULL) |
19205 | { | |
19206 | as_warn (_(".frame outside of .ent")); | |
19207 | demand_empty_rest_of_line (); | |
19208 | return; | |
19209 | } | |
252b5132 | 19210 | |
ecb4347a DJ |
19211 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19212 | ||
19213 | SKIP_WHITESPACE (); | |
19214 | if (*input_line_pointer++ != ',' | |
19215 | || get_absolute_expression_and_terminator (&val) != ',') | |
19216 | { | |
19217 | as_warn (_("Bad .frame directive")); | |
19218 | --input_line_pointer; | |
19219 | demand_empty_rest_of_line (); | |
19220 | return; | |
19221 | } | |
252b5132 | 19222 | |
ecb4347a DJ |
19223 | cur_proc_ptr->frame_offset = val; |
19224 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19225 | |
252b5132 | 19226 | demand_empty_rest_of_line (); |
252b5132 | 19227 | } |
ecb4347a DJ |
19228 | else |
19229 | #endif /* OBJ_ELF */ | |
19230 | s_ignore (ignore); | |
252b5132 RH |
19231 | } |
19232 | ||
bdaaa2e1 KH |
19233 | /* The .fmask and .mask directives. If the mdebug section is present |
19234 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19235 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19236 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19237 | make reference to the ecoff symbol table (in the mdebug section). */ |
19238 | ||
19239 | static void | |
17a2f251 | 19240 | s_mips_mask (int reg_type) |
252b5132 | 19241 | { |
ecb4347a | 19242 | #ifdef OBJ_ELF |
f43abd2b | 19243 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19244 | { |
ecb4347a | 19245 | long mask, off; |
252b5132 | 19246 | |
ecb4347a DJ |
19247 | if (cur_proc_ptr == (procS *) NULL) |
19248 | { | |
19249 | as_warn (_(".mask/.fmask outside of .ent")); | |
19250 | demand_empty_rest_of_line (); | |
19251 | return; | |
19252 | } | |
252b5132 | 19253 | |
ecb4347a DJ |
19254 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19255 | { | |
19256 | as_warn (_("Bad .mask/.fmask directive")); | |
19257 | --input_line_pointer; | |
19258 | demand_empty_rest_of_line (); | |
19259 | return; | |
19260 | } | |
252b5132 | 19261 | |
ecb4347a DJ |
19262 | off = get_absolute_expression (); |
19263 | ||
19264 | if (reg_type == 'F') | |
19265 | { | |
19266 | cur_proc_ptr->fpreg_mask = mask; | |
19267 | cur_proc_ptr->fpreg_offset = off; | |
19268 | } | |
19269 | else | |
19270 | { | |
19271 | cur_proc_ptr->reg_mask = mask; | |
19272 | cur_proc_ptr->reg_offset = off; | |
19273 | } | |
19274 | ||
19275 | demand_empty_rest_of_line (); | |
252b5132 RH |
19276 | } |
19277 | else | |
ecb4347a DJ |
19278 | #endif /* OBJ_ELF */ |
19279 | s_ignore (reg_type); | |
252b5132 RH |
19280 | } |
19281 | ||
316f5878 RS |
19282 | /* A table describing all the processors gas knows about. Names are |
19283 | matched in the order listed. | |
e7af610e | 19284 | |
316f5878 RS |
19285 | To ease comparison, please keep this table in the same order as |
19286 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19287 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19288 | { | |
316f5878 | 19289 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19290 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19291 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19292 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19293 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19294 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19295 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19296 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19297 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19298 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19299 | |
19300 | /* MIPS I */ | |
ad3fea08 TS |
19301 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19302 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19303 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19304 | |
19305 | /* MIPS II */ | |
ad3fea08 | 19306 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19307 | |
19308 | /* MIPS III */ | |
ad3fea08 TS |
19309 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19310 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19311 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19312 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19313 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19314 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19315 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19316 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19317 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19318 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19319 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19320 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19321 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19322 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19323 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19324 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19325 | |
19326 | /* MIPS IV */ | |
ad3fea08 TS |
19327 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19328 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19329 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19330 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19331 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19332 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19333 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19334 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19335 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19336 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19337 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19338 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19339 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19340 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19341 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19342 | |
19343 | /* MIPS 32 */ | |
ad3fea08 TS |
19344 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19345 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19346 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19347 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19348 | ||
19349 | /* MIPS 32 Release 2 */ | |
19350 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19351 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19352 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19353 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19354 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19355 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19356 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19357 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19358 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19359 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19360 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19361 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19362 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19363 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19364 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19365 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19366 | /* Deprecated forms of the above. */ | |
19367 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19368 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19369 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19370 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19371 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19372 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19373 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19374 | /* Deprecated forms of the above. */ | |
19375 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19376 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19377 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19378 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19379 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19380 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19381 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19382 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19383 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19384 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19385 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19386 | /* Deprecated forms of the above. */ | |
19387 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19388 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19389 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19390 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19391 | /* 34Kn is a 34kc without DSP. */ |
19392 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19393 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19394 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19395 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19396 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19397 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19398 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19399 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19400 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19401 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19402 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19403 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19404 | /* Deprecated forms of the above. */ | |
19405 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19406 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19407 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19408 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19409 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19410 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19411 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19412 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19413 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19414 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19415 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19416 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19417 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19418 | |
316f5878 | 19419 | /* MIPS 64 */ |
ad3fea08 TS |
19420 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19421 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19422 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19423 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19424 | |
c7a23324 | 19425 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19426 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19427 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19428 | /* Broadcom SB-1A CPU core */ |
19429 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19430 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19431 | |
19432 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19433 | |
ed163775 MR |
19434 | /* MIPS 64 Release 2 */ |
19435 | ||
967344c6 AN |
19436 | /* Cavium Networks Octeon CPU core */ |
19437 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19438 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19439 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19440 | |
52b6b6b9 JM |
19441 | /* RMI Xlr */ |
19442 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19443 | ||
55a36193 MK |
19444 | /* Broadcom XLP. |
19445 | XLP is mostly like XLR, with the prominent exception that it is | |
19446 | MIPS64R2 rather than MIPS64. */ | |
19447 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19448 | ||
316f5878 RS |
19449 | /* End marker */ |
19450 | { NULL, 0, 0, 0 } | |
19451 | }; | |
e7af610e | 19452 | |
84ea6cf2 | 19453 | |
316f5878 RS |
19454 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19455 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19456 | |
316f5878 | 19457 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19458 | |
b34976b6 | 19459 | static bfd_boolean |
17a2f251 | 19460 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19461 | { |
19462 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19463 | given++, canonical++; | |
19464 | ||
19465 | return ((*given == 0 && *canonical == 0) | |
19466 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19467 | } | |
19468 | ||
19469 | ||
19470 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19471 | CPU name. We've traditionally allowed a lot of variation here. | |
19472 | ||
19473 | Note: this function is shared between GCC and GAS. */ | |
19474 | ||
b34976b6 | 19475 | static bfd_boolean |
17a2f251 | 19476 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19477 | { |
19478 | /* First see if the name matches exactly, or with a final "000" | |
19479 | turned into "k". */ | |
19480 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19481 | return TRUE; |
316f5878 RS |
19482 | |
19483 | /* If not, try comparing based on numerical designation alone. | |
19484 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19485 | if (TOLOWER (*given) == 'r') | |
19486 | given++; | |
19487 | if (!ISDIGIT (*given)) | |
b34976b6 | 19488 | return FALSE; |
316f5878 RS |
19489 | |
19490 | /* Skip over some well-known prefixes in the canonical name, | |
19491 | hoping to find a number there too. */ | |
19492 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19493 | canonical += 2; | |
19494 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19495 | canonical += 2; | |
19496 | else if (TOLOWER (canonical[0]) == 'r') | |
19497 | canonical += 1; | |
19498 | ||
19499 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19500 | } | |
19501 | ||
19502 | ||
19503 | /* Parse an option that takes the name of a processor as its argument. | |
19504 | OPTION is the name of the option and CPU_STRING is the argument. | |
19505 | Return the corresponding processor enumeration if the CPU_STRING is | |
19506 | recognized, otherwise report an error and return null. | |
19507 | ||
19508 | A similar function exists in GCC. */ | |
e7af610e NC |
19509 | |
19510 | static const struct mips_cpu_info * | |
17a2f251 | 19511 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19512 | { |
316f5878 | 19513 | const struct mips_cpu_info *p; |
e7af610e | 19514 | |
316f5878 RS |
19515 | /* 'from-abi' selects the most compatible architecture for the given |
19516 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19517 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19518 | version. Look first at the -mgp options, if given, otherwise base | |
19519 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19520 | |
316f5878 RS |
19521 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19522 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19523 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19524 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19525 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19526 | { | |
19527 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19528 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19529 | ||
19530 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19531 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19532 | ||
19533 | if (file_mips_gp32 >= 0) | |
19534 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19535 | ||
19536 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19537 | ? ISA_MIPS3 | |
19538 | : ISA_MIPS1); | |
19539 | } | |
19540 | ||
19541 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19542 | if (strcasecmp (cpu_string, "default") == 0) | |
19543 | return 0; | |
19544 | ||
19545 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19546 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19547 | return p; | |
19548 | ||
20203fb9 | 19549 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19550 | return 0; |
e7af610e NC |
19551 | } |
19552 | ||
316f5878 RS |
19553 | /* Return the canonical processor information for ISA (a member of the |
19554 | ISA_MIPS* enumeration). */ | |
19555 | ||
e7af610e | 19556 | static const struct mips_cpu_info * |
17a2f251 | 19557 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19558 | { |
19559 | int i; | |
19560 | ||
19561 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19562 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19563 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19564 | return (&mips_cpu_info_table[i]); |
19565 | ||
e972090a | 19566 | return NULL; |
e7af610e | 19567 | } |
fef14a42 TS |
19568 | |
19569 | static const struct mips_cpu_info * | |
17a2f251 | 19570 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19571 | { |
19572 | int i; | |
19573 | ||
19574 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19575 | if (arch == mips_cpu_info_table[i].cpu) | |
19576 | return (&mips_cpu_info_table[i]); | |
19577 | ||
19578 | return NULL; | |
19579 | } | |
316f5878 RS |
19580 | \f |
19581 | static void | |
17a2f251 | 19582 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19583 | { |
19584 | if (*first_p) | |
19585 | { | |
19586 | fprintf (stream, "%24s", ""); | |
19587 | *col_p = 24; | |
19588 | } | |
19589 | else | |
19590 | { | |
19591 | fprintf (stream, ", "); | |
19592 | *col_p += 2; | |
19593 | } | |
e7af610e | 19594 | |
316f5878 RS |
19595 | if (*col_p + strlen (string) > 72) |
19596 | { | |
19597 | fprintf (stream, "\n%24s", ""); | |
19598 | *col_p = 24; | |
19599 | } | |
19600 | ||
19601 | fprintf (stream, "%s", string); | |
19602 | *col_p += strlen (string); | |
19603 | ||
19604 | *first_p = 0; | |
19605 | } | |
19606 | ||
19607 | void | |
17a2f251 | 19608 | md_show_usage (FILE *stream) |
e7af610e | 19609 | { |
316f5878 RS |
19610 | int column, first; |
19611 | size_t i; | |
19612 | ||
19613 | fprintf (stream, _("\ | |
19614 | MIPS options:\n\ | |
316f5878 RS |
19615 | -EB generate big endian output\n\ |
19616 | -EL generate little endian output\n\ | |
19617 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19618 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19619 | implicitly with the gp register [default 8]\n")); | |
19620 | fprintf (stream, _("\ | |
19621 | -mips1 generate MIPS ISA I instructions\n\ | |
19622 | -mips2 generate MIPS ISA II instructions\n\ | |
19623 | -mips3 generate MIPS ISA III instructions\n\ | |
19624 | -mips4 generate MIPS ISA IV instructions\n\ | |
19625 | -mips5 generate MIPS ISA V instructions\n\ | |
19626 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19627 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19628 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19629 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19630 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19631 | ||
19632 | first = 1; | |
e7af610e NC |
19633 | |
19634 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19635 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19636 | show (stream, "from-abi", &column, &first); | |
19637 | fputc ('\n', stream); | |
e7af610e | 19638 | |
316f5878 RS |
19639 | fprintf (stream, _("\ |
19640 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19641 | -no-mCPU don't generate code specific to CPU.\n\ | |
19642 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19643 | ||
19644 | first = 1; | |
19645 | ||
19646 | show (stream, "3900", &column, &first); | |
19647 | show (stream, "4010", &column, &first); | |
19648 | show (stream, "4100", &column, &first); | |
19649 | show (stream, "4650", &column, &first); | |
19650 | fputc ('\n', stream); | |
19651 | ||
19652 | fprintf (stream, _("\ | |
19653 | -mips16 generate mips16 instructions\n\ | |
19654 | -no-mips16 do not generate mips16 instructions\n")); | |
19655 | fprintf (stream, _("\ | |
df58fc94 RS |
19656 | -mmicromips generate microMIPS instructions\n\ |
19657 | -mno-micromips do not generate microMIPS instructions\n")); | |
19658 | fprintf (stream, _("\ | |
e16bfa71 TS |
19659 | -msmartmips generate smartmips instructions\n\ |
19660 | -mno-smartmips do not generate smartmips instructions\n")); | |
19661 | fprintf (stream, _("\ | |
74cd071d CF |
19662 | -mdsp generate DSP instructions\n\ |
19663 | -mno-dsp do not generate DSP instructions\n")); | |
19664 | fprintf (stream, _("\ | |
8b082fb1 TS |
19665 | -mdspr2 generate DSP R2 instructions\n\ |
19666 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19667 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19668 | -mmt generate MT instructions\n\ |
19669 | -mno-mt do not generate MT instructions\n")); | |
19670 | fprintf (stream, _("\ | |
dec0624d MR |
19671 | -mmcu generate MCU instructions\n\ |
19672 | -mno-mcu do not generate MCU instructions\n")); | |
19673 | fprintf (stream, _("\ | |
b015e599 AP |
19674 | -mvirt generate Virtualization instructions\n\ |
19675 | -mno-virt do not generate Virtualization instructions\n")); | |
19676 | fprintf (stream, _("\ | |
c67a084a NC |
19677 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19678 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19679 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19680 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19681 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19682 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19683 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19684 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19685 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19686 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19687 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19688 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19689 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19690 | fprintf (stream, _("\ |
19691 | -mhard-float allow floating-point instructions\n\ | |
19692 | -msoft-float do not allow floating-point instructions\n\ | |
19693 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19694 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19695 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19696 | )); | |
316f5878 RS |
19697 | #ifdef OBJ_ELF |
19698 | fprintf (stream, _("\ | |
19699 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19700 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19701 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19702 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19703 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19704 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19705 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19706 | position dependent (non shared) code\n\ |
316f5878 RS |
19707 | -mabi=ABI create ABI conformant object file for:\n")); |
19708 | ||
19709 | first = 1; | |
19710 | ||
19711 | show (stream, "32", &column, &first); | |
19712 | show (stream, "o64", &column, &first); | |
19713 | show (stream, "n32", &column, &first); | |
19714 | show (stream, "64", &column, &first); | |
19715 | show (stream, "eabi", &column, &first); | |
19716 | ||
19717 | fputc ('\n', stream); | |
19718 | ||
19719 | fprintf (stream, _("\ | |
19720 | -32 create o32 ABI object file (default)\n\ | |
19721 | -n32 create n32 ABI object file\n\ | |
19722 | -64 create 64 ABI object file\n")); | |
19723 | #endif | |
e7af610e | 19724 | } |
14e777e0 | 19725 | |
1575952e | 19726 | #ifdef TE_IRIX |
14e777e0 | 19727 | enum dwarf2_format |
413a266c | 19728 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19729 | { |
369943fe | 19730 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19731 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19732 | else |
19733 | return dwarf2_format_32bit; | |
19734 | } | |
1575952e | 19735 | #endif |
73369e65 EC |
19736 | |
19737 | int | |
19738 | mips_dwarf2_addr_size (void) | |
19739 | { | |
6b6b3450 | 19740 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19741 | return 8; |
73369e65 EC |
19742 | else |
19743 | return 4; | |
19744 | } | |
5862107c EC |
19745 | |
19746 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19747 | void | |
19748 | mips_cfi_frame_initial_instructions (void) | |
19749 | { | |
19750 | cfi_add_CFA_def_cfa_register (SP); | |
19751 | } | |
19752 | ||
707bfff6 TS |
19753 | int |
19754 | tc_mips_regname_to_dw2regnum (char *regname) | |
19755 | { | |
19756 | unsigned int regnum = -1; | |
19757 | unsigned int reg; | |
19758 | ||
19759 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19760 | regnum = reg; | |
19761 | ||
19762 | return regnum; | |
19763 | } |