Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
f7e42eb4 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
29 | ||
30 | #include <ctype.h> | |
31 | ||
32 | #ifdef USE_STDARG | |
33 | #include <stdarg.h> | |
34 | #endif | |
35 | #ifdef USE_VARARGS | |
36 | #include <varargs.h> | |
37 | #endif | |
38 | ||
39 | #include "opcode/mips.h" | |
40 | #include "itbl-ops.h" | |
41 | ||
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
80 | #include "ecoff.h" | |
81 | ||
82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
83 | static char *mips_regmask_frag; | |
84 | #endif | |
85 | ||
86 | #define AT 1 | |
87 | #define TREG 24 | |
88 | #define PIC_CALL_REG 25 | |
89 | #define KT0 26 | |
90 | #define KT1 27 | |
91 | #define GP 28 | |
92 | #define SP 29 | |
93 | #define FP 30 | |
94 | #define RA 31 | |
95 | ||
96 | #define ILLEGAL_REG (32) | |
97 | ||
98 | /* Allow override of standard little-endian ECOFF format. */ | |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
104 | extern int target_big_endian; | |
105 | ||
106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the | |
107 | 32 bit ABI. This has no meaning for ECOFF. | |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
110 | static int mips_64; | |
111 | ||
112 | /* The default target format to use. */ | |
beae10d5 | 113 | |
252b5132 RH |
114 | const char * |
115 | mips_target_format () | |
116 | { | |
117 | switch (OUTPUT_FLAVOR) | |
118 | { | |
119 | case bfd_target_aout_flavour: | |
120 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
121 | case bfd_target_ecoff_flavour: | |
122 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
056350c6 NC |
123 | case bfd_target_coff_flavour: |
124 | return "pe-mips"; | |
252b5132 | 125 | case bfd_target_elf_flavour: |
8614eeee UC |
126 | #ifdef TE_TMIPS |
127 | /* This is traditional mips */ | |
128 | return (target_big_endian | |
af9539e4 L |
129 | ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips") |
130 | : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips")); | |
8614eeee | 131 | #else |
252b5132 RH |
132 | return (target_big_endian |
133 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
134 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
8614eeee | 135 | #endif |
252b5132 RH |
136 | default: |
137 | abort (); | |
138 | return NULL; | |
139 | } | |
140 | } | |
141 | ||
142 | /* The name of the readonly data section. */ | |
143 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
144 | ? ".data" \ | |
145 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
146 | ? ".rdata" \ | |
056350c6 NC |
147 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
148 | ? ".rdata" \ | |
252b5132 RH |
149 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
150 | ? ".rodata" \ | |
151 | : (abort (), "")) | |
152 | ||
153 | /* This is the set of options which may be modified by the .set | |
154 | pseudo-op. We use a struct so that .set push and .set pop are more | |
155 | reliable. */ | |
156 | ||
e972090a NC |
157 | struct mips_set_options |
158 | { | |
252b5132 RH |
159 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
160 | if it has not been initialized. Changed by `.set mipsN', and the | |
161 | -mipsN command line option, and the default CPU. */ | |
162 | int isa; | |
163 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
164 | not, 1 if we are, and -1 if the value has not been initialized. | |
165 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
166 | -nomips16 command line options, and the default CPU. */ | |
167 | int mips16; | |
168 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
169 | reorder' and `.set noreorder'. */ | |
170 | int noreorder; | |
171 | /* Non-zero if we should not permit the $at ($1) register to be used | |
172 | in instructions. Changed by `.set at' and `.set noat'. */ | |
173 | int noat; | |
174 | /* Non-zero if we should warn when a macro instruction expands into | |
175 | more than one machine instruction. Changed by `.set nomacro' and | |
176 | `.set macro'. */ | |
177 | int warn_about_macros; | |
178 | /* Non-zero if we should not move instructions. Changed by `.set | |
179 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
180 | int nomove; | |
181 | /* Non-zero if we should not optimize branches by moving the target | |
182 | of the branch into the delay slot. Actually, we don't perform | |
183 | this optimization anyhow. Changed by `.set bopt' and `.set | |
184 | nobopt'. */ | |
185 | int nobopt; | |
186 | /* Non-zero if we should not autoextend mips16 instructions. | |
187 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
188 | int noautoextend; | |
189 | }; | |
190 | ||
191 | /* This is the struct we use to hold the current set of options. Note | |
e7af610e NC |
192 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
193 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 194 | |
e972090a NC |
195 | static struct mips_set_options mips_opts = |
196 | { | |
e7af610e NC |
197 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 |
198 | }; | |
252b5132 RH |
199 | |
200 | /* These variables are filled in with the masks of registers used. | |
201 | The object format code reads them and puts them in the appropriate | |
202 | place. */ | |
203 | unsigned long mips_gprmask; | |
204 | unsigned long mips_cprmask[4]; | |
205 | ||
206 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 207 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 208 | |
e7af610e NC |
209 | /* The CPU type we are using for this output file. */ |
210 | static int mips_cpu = CPU_UNKNOWN; | |
252b5132 | 211 | |
bdaaa2e1 | 212 | /* The argument of the -mabi= flag. */ |
e972090a | 213 | static char * mips_abi_string = 0; |
252b5132 | 214 | |
bdaaa2e1 | 215 | /* Wether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
216 | static int mips_eabi64 = 0; |
217 | ||
218 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 219 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
220 | static int mips_32bitmode = 0; |
221 | ||
bdaaa2e1 | 222 | /* True if -mgp32 was passed. */ |
c97ef257 AH |
223 | static int mips_gp32 = 0; |
224 | ||
9ce8a5dd GRK |
225 | /* Some ISA's have delay slots for instructions which read or write |
226 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 227 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
228 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
229 | delay slot in this ISA. The uses of this macro assume that any | |
230 | ISA that has delay slots for one of these, has them for all. They | |
231 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 232 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 233 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
234 | (ISA) == ISA_MIPS1 \ |
235 | || (ISA) == ISA_MIPS2 \ | |
236 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
237 | ) |
238 | ||
bdaaa2e1 | 239 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 240 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS3 \ |
242 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 243 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 244 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
245 | ) |
246 | ||
bdaaa2e1 | 247 | /* Whether the processor uses hardware interlocks to protect |
252b5132 RH |
248 | reads from the HI and LO registers, and thus does not |
249 | require nops to be inserted. | |
250 | ||
251 | FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO: | |
252 | -mcpu=FOO schedules for FOO, but still produces code that meets the | |
253 | requirements of MIPS ISA I. For example, it won't generate any | |
254 | FOO-specific instructions, and it will still assume that any | |
255 | scheduling hazards described in MIPS ISA I are there, even if FOO | |
256 | has interlocks. -mFOO gives GCC permission to generate code that | |
257 | will only run on a FOO; it will generate FOO-specific instructions, | |
258 | and assume interlocks provided by a FOO. | |
259 | ||
260 | However, GAS currently doesn't make this distinction; before Jan 28 | |
261 | 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's | |
262 | assumptions. The GCC driver passes these flags through to GAS, so | |
263 | if GAS actually does anything that doesn't meet MIPS ISA I with | |
264 | -mFOO, then GCC's -mcpu=FOO flag isn't going to work. | |
265 | ||
266 | And furthermore, it did not assume that -mFOO implied -mcpu=FOO, | |
267 | which seems senseless --- why generate code which will only run on | |
268 | a FOO, but schedule for something else? | |
269 | ||
270 | So now, at least, -mcpu=FOO and -mFOO are exactly equivalent. | |
271 | ||
272 | -- Jim Blandy <jimb@cygnus.com> */ | |
273 | ||
156c2f8b | 274 | #define hilo_interlocks (mips_cpu == CPU_R4010 \ |
252b5132 RH |
275 | ) |
276 | ||
277 | /* Whether the processor uses hardware interlocks to protect reads | |
278 | from the GPRs, and thus does not require nops to be inserted. */ | |
279 | #define gpr_interlocks \ | |
e7af610e | 280 | (mips_opts.isa != ISA_MIPS1 \ |
156c2f8b | 281 | || mips_cpu == CPU_R3900) |
252b5132 RH |
282 | |
283 | /* As with other "interlocks" this is used by hardware that has FP | |
284 | (co-processor) interlocks. */ | |
bdaaa2e1 | 285 | /* Itbl support may require additional care here. */ |
156c2f8b | 286 | #define cop_interlocks (mips_cpu == CPU_R4300 \ |
252b5132 RH |
287 | ) |
288 | ||
6b76fefe CM |
289 | /* Is this a mfhi or mflo instruction? */ |
290 | #define MF_HILO_INSN(PINFO) \ | |
291 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
292 | ||
252b5132 RH |
293 | /* MIPS PIC level. */ |
294 | ||
e972090a NC |
295 | enum mips_pic_level |
296 | { | |
252b5132 RH |
297 | /* Do not generate PIC code. */ |
298 | NO_PIC, | |
299 | ||
300 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
301 | not sure what it is supposed to do. */ | |
302 | IRIX4_PIC, | |
303 | ||
304 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
305 | SVR4_PIC, | |
306 | ||
307 | /* Generate PIC code without using a global offset table: the data | |
308 | segment has a maximum size of 64K, all data references are off | |
309 | the $gp register, and all text references are PC relative. This | |
310 | is used on some embedded systems. */ | |
311 | EMBEDDED_PIC | |
312 | }; | |
313 | ||
314 | static enum mips_pic_level mips_pic; | |
315 | ||
316 | /* 1 if we should generate 32 bit offsets from the GP register in | |
317 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
318 | static int mips_big_got; | |
319 | ||
320 | /* 1 if trap instructions should used for overflow rather than break | |
321 | instructions. */ | |
322 | static int mips_trap; | |
323 | ||
119d663a NC |
324 | /* 1 if double width floating point constants should not be constructed |
325 | by a assembling two single width halves into two single width floating | |
326 | point registers which just happen to alias the double width destination | |
327 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 328 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
329 | automatically at assemble time. */ |
330 | static int mips_disable_float_construction; | |
331 | ||
252b5132 RH |
332 | /* Non-zero if any .set noreorder directives were used. */ |
333 | ||
334 | static int mips_any_noreorder; | |
335 | ||
6b76fefe CM |
336 | /* Non-zero if nops should be inserted when the register referenced in |
337 | an mfhi/mflo instruction is read in the next two instructions. */ | |
338 | static int mips_7000_hilo_fix; | |
339 | ||
252b5132 | 340 | /* The size of the small data section. */ |
156c2f8b | 341 | static unsigned int g_switch_value = 8; |
252b5132 RH |
342 | /* Whether the -G option was used. */ |
343 | static int g_switch_seen = 0; | |
344 | ||
345 | #define N_RMASK 0xc4 | |
346 | #define N_VFP 0xd4 | |
347 | ||
348 | /* If we can determine in advance that GP optimization won't be | |
349 | possible, we can skip the relaxation stuff that tries to produce | |
350 | GP-relative references. This makes delay slot optimization work | |
351 | better. | |
352 | ||
353 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
354 | gcc output. It needs to guess right for gcc, otherwise gcc |
355 | will put what it thinks is a GP-relative instruction in a branch | |
356 | delay slot. | |
252b5132 RH |
357 | |
358 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
359 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
360 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
361 | ||
362 | /* handle of the OPCODE hash table */ | |
363 | static struct hash_control *op_hash = NULL; | |
364 | ||
365 | /* The opcode hash table we use for the mips16. */ | |
366 | static struct hash_control *mips16_op_hash = NULL; | |
367 | ||
368 | /* This array holds the chars that always start a comment. If the | |
369 | pre-processor is disabled, these aren't very useful */ | |
370 | const char comment_chars[] = "#"; | |
371 | ||
372 | /* This array holds the chars that only start a comment at the beginning of | |
373 | a line. If the line seems to have the form '# 123 filename' | |
374 | .line and .file directives will appear in the pre-processed output */ | |
375 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
376 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 377 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
378 | /* Also note that C style comments are always supported. */ |
379 | const char line_comment_chars[] = "#"; | |
380 | ||
bdaaa2e1 | 381 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 382 | const char line_separator_chars[] = ";"; |
252b5132 RH |
383 | |
384 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
385 | const char EXP_CHARS[] = "eE"; | |
386 | ||
387 | /* Chars that mean this number is a floating point constant */ | |
388 | /* As in 0f12.456 */ | |
389 | /* or 0d1.2345e12 */ | |
390 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
391 | ||
392 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
393 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
394 | but nothing is ideal around here. | |
395 | */ | |
396 | ||
397 | static char *insn_error; | |
398 | ||
399 | static int auto_align = 1; | |
400 | ||
401 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
402 | offset in the stack frame from which to restore the $gp register. | |
403 | This is set by the .cprestore pseudo-op, and saved in this | |
404 | variable. */ | |
405 | static offsetT mips_cprestore_offset = -1; | |
406 | ||
407 | /* This is the register which holds the stack frame, as set by the | |
408 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
409 | static int mips_frame_reg = SP; | |
410 | ||
411 | /* To output NOP instructions correctly, we need to keep information | |
412 | about the previous two instructions. */ | |
413 | ||
414 | /* Whether we are optimizing. The default value of 2 means to remove | |
415 | unneeded NOPs and swap branch instructions when possible. A value | |
416 | of 1 means to not swap branches. A value of 0 means to always | |
417 | insert NOPs. */ | |
418 | static int mips_optimize = 2; | |
419 | ||
420 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
421 | equivalent to seeing no -g option at all. */ | |
422 | static int mips_debug = 0; | |
423 | ||
424 | /* The previous instruction. */ | |
425 | static struct mips_cl_insn prev_insn; | |
426 | ||
427 | /* The instruction before prev_insn. */ | |
428 | static struct mips_cl_insn prev_prev_insn; | |
429 | ||
430 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
431 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 432 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
433 | |
434 | /* Non-zero if prev_insn is valid. */ | |
435 | static int prev_insn_valid; | |
436 | ||
437 | /* The frag for the previous instruction. */ | |
438 | static struct frag *prev_insn_frag; | |
439 | ||
440 | /* The offset into prev_insn_frag for the previous instruction. */ | |
441 | static long prev_insn_where; | |
442 | ||
443 | /* The reloc type for the previous instruction, if any. */ | |
444 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
445 | ||
446 | /* The reloc for the previous instruction, if any. */ | |
447 | static fixS *prev_insn_fixp; | |
448 | ||
449 | /* Non-zero if the previous instruction was in a delay slot. */ | |
450 | static int prev_insn_is_delay_slot; | |
451 | ||
452 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
453 | static int prev_insn_unreordered; | |
454 | ||
455 | /* Non-zero if the previous instruction uses an extend opcode (if | |
456 | mips16). */ | |
457 | static int prev_insn_extended; | |
458 | ||
459 | /* Non-zero if the previous previous instruction was in a .set | |
460 | noreorder. */ | |
461 | static int prev_prev_insn_unreordered; | |
462 | ||
463 | /* If this is set, it points to a frag holding nop instructions which | |
464 | were inserted before the start of a noreorder section. If those | |
465 | nops turn out to be unnecessary, the size of the frag can be | |
466 | decreased. */ | |
467 | static fragS *prev_nop_frag; | |
468 | ||
469 | /* The number of nop instructions we created in prev_nop_frag. */ | |
470 | static int prev_nop_frag_holds; | |
471 | ||
472 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 473 | prev_nop_frag. */ |
252b5132 RH |
474 | static int prev_nop_frag_required; |
475 | ||
476 | /* The number of instructions we've seen since prev_nop_frag. */ | |
477 | static int prev_nop_frag_since; | |
478 | ||
479 | /* For ECOFF and ELF, relocations against symbols are done in two | |
480 | parts, with a HI relocation and a LO relocation. Each relocation | |
481 | has only 16 bits of space to store an addend. This means that in | |
482 | order for the linker to handle carries correctly, it must be able | |
483 | to locate both the HI and the LO relocation. This means that the | |
484 | relocations must appear in order in the relocation table. | |
485 | ||
486 | In order to implement this, we keep track of each unmatched HI | |
487 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 488 | corresponding LO relocation. */ |
252b5132 | 489 | |
e972090a NC |
490 | struct mips_hi_fixup |
491 | { | |
252b5132 RH |
492 | /* Next HI fixup. */ |
493 | struct mips_hi_fixup *next; | |
494 | /* This fixup. */ | |
495 | fixS *fixp; | |
496 | /* The section this fixup is in. */ | |
497 | segT seg; | |
498 | }; | |
499 | ||
500 | /* The list of unmatched HI relocs. */ | |
501 | ||
502 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
503 | ||
504 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
505 | ||
506 | #define X ILLEGAL_REG | |
e972090a NC |
507 | static const int mips32_to_16_reg_map[] = |
508 | { | |
252b5132 RH |
509 | X, X, 2, 3, 4, 5, 6, 7, |
510 | X, X, X, X, X, X, X, X, | |
511 | 0, 1, X, X, X, X, X, X, | |
512 | X, X, X, X, X, X, X, X | |
513 | }; | |
514 | #undef X | |
515 | ||
516 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
517 | ||
e972090a NC |
518 | static const unsigned int mips16_to_32_reg_map[] = |
519 | { | |
252b5132 RH |
520 | 16, 17, 2, 3, 4, 5, 6, 7 |
521 | }; | |
522 | \f | |
523 | /* Since the MIPS does not have multiple forms of PC relative | |
524 | instructions, we do not have to do relaxing as is done on other | |
525 | platforms. However, we do have to handle GP relative addressing | |
526 | correctly, which turns out to be a similar problem. | |
527 | ||
528 | Every macro that refers to a symbol can occur in (at least) two | |
529 | forms, one with GP relative addressing and one without. For | |
530 | example, loading a global variable into a register generally uses | |
531 | a macro instruction like this: | |
532 | lw $4,i | |
533 | If i can be addressed off the GP register (this is true if it is in | |
534 | the .sbss or .sdata section, or if it is known to be smaller than | |
535 | the -G argument) this will generate the following instruction: | |
536 | lw $4,i($gp) | |
537 | This instruction will use a GPREL reloc. If i can not be addressed | |
538 | off the GP register, the following instruction sequence will be used: | |
539 | lui $at,i | |
540 | lw $4,i($at) | |
541 | In this case the first instruction will have a HI16 reloc, and the | |
542 | second reloc will have a LO16 reloc. Both relocs will be against | |
543 | the symbol i. | |
544 | ||
545 | The issue here is that we may not know whether i is GP addressable | |
546 | until after we see the instruction that uses it. Therefore, we | |
547 | want to be able to choose the final instruction sequence only at | |
548 | the end of the assembly. This is similar to the way other | |
549 | platforms choose the size of a PC relative instruction only at the | |
550 | end of assembly. | |
551 | ||
552 | When generating position independent code we do not use GP | |
553 | addressing in quite the same way, but the issue still arises as | |
554 | external symbols and local symbols must be handled differently. | |
555 | ||
556 | We handle these issues by actually generating both possible | |
557 | instruction sequences. The longer one is put in a frag_var with | |
558 | type rs_machine_dependent. We encode what to do with the frag in | |
559 | the subtype field. We encode (1) the number of existing bytes to | |
560 | replace, (2) the number of new bytes to use, (3) the offset from | |
561 | the start of the existing bytes to the first reloc we must generate | |
562 | (that is, the offset is applied from the start of the existing | |
563 | bytes after they are replaced by the new bytes, if any), (4) the | |
564 | offset from the start of the existing bytes to the second reloc, | |
565 | (5) whether a third reloc is needed (the third reloc is always four | |
566 | bytes after the second reloc), and (6) whether to warn if this | |
567 | variant is used (this is sometimes needed if .set nomacro or .set | |
568 | noat is in effect). All these numbers are reasonably small. | |
569 | ||
570 | Generating two instruction sequences must be handled carefully to | |
571 | ensure that delay slots are handled correctly. Fortunately, there | |
572 | are a limited number of cases. When the second instruction | |
573 | sequence is generated, append_insn is directed to maintain the | |
574 | existing delay slot information, so it continues to apply to any | |
575 | code after the second instruction sequence. This means that the | |
576 | second instruction sequence must not impose any requirements not | |
577 | required by the first instruction sequence. | |
578 | ||
579 | These variant frags are then handled in functions called by the | |
580 | machine independent code. md_estimate_size_before_relax returns | |
581 | the final size of the frag. md_convert_frag sets up the final form | |
582 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
583 | one if needed. */ | |
584 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
585 | ((relax_substateT) \ | |
586 | (((old) << 23) \ | |
587 | | ((new) << 16) \ | |
588 | | (((reloc1) + 64) << 9) \ | |
589 | | (((reloc2) + 64) << 2) \ | |
590 | | ((reloc3) ? (1 << 1) : 0) \ | |
591 | | ((warn) ? 1 : 0))) | |
592 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
593 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
beae10d5 KH |
594 | #define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64) |
595 | #define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
596 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
597 | #define RELAX_WARN(i) ((i) & 1) | |
598 | ||
599 | /* For mips16 code, we use an entirely different form of relaxation. | |
600 | mips16 supports two versions of most instructions which take | |
601 | immediate values: a small one which takes some small value, and a | |
602 | larger one which takes a 16 bit value. Since branches also follow | |
603 | this pattern, relaxing these values is required. | |
604 | ||
605 | We can assemble both mips16 and normal MIPS code in a single | |
606 | object. Therefore, we need to support this type of relaxation at | |
607 | the same time that we support the relaxation described above. We | |
608 | use the high bit of the subtype field to distinguish these cases. | |
609 | ||
610 | The information we store for this type of relaxation is the | |
611 | argument code found in the opcode file for this relocation, whether | |
612 | the user explicitly requested a small or extended form, and whether | |
613 | the relocation is in a jump or jal delay slot. That tells us the | |
614 | size of the value, and how it should be stored. We also store | |
615 | whether the fragment is considered to be extended or not. We also | |
616 | store whether this is known to be a branch to a different section, | |
617 | whether we have tried to relax this frag yet, and whether we have | |
618 | ever extended a PC relative fragment because of a shift count. */ | |
619 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
620 | (0x80000000 \ | |
621 | | ((type) & 0xff) \ | |
622 | | ((small) ? 0x100 : 0) \ | |
623 | | ((ext) ? 0x200 : 0) \ | |
624 | | ((dslot) ? 0x400 : 0) \ | |
625 | | ((jal_dslot) ? 0x800 : 0)) | |
626 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
627 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
628 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
629 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
630 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
631 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
632 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
633 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
634 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
635 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
636 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
637 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
638 | \f | |
639 | /* Prototypes for static functions. */ | |
640 | ||
641 | #ifdef __STDC__ | |
642 | #define internalError() \ | |
643 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
644 | #else | |
645 | #define internalError() as_fatal (_("MIPS internal Error")); | |
646 | #endif | |
647 | ||
648 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
649 | ||
650 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
651 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 652 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
653 | static void mips16_mark_labels PARAMS ((void)); |
654 | static void append_insn PARAMS ((char *place, | |
655 | struct mips_cl_insn * ip, | |
656 | expressionS * p, | |
657 | bfd_reloc_code_real_type r, | |
658 | boolean)); | |
659 | static void mips_no_prev_insn PARAMS ((int)); | |
660 | static void mips_emit_delays PARAMS ((boolean)); | |
661 | #ifdef USE_STDARG | |
662 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
663 | const char *name, const char *fmt, | |
664 | ...)); | |
665 | #else | |
666 | static void macro_build (); | |
667 | #endif | |
668 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
669 | const char *, const char *, | |
670 | va_list)); | |
671 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
672 | expressionS * ep, int regnum)); | |
673 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
674 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
675 | expressionS *)); | |
676 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
677 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
678 | static void macro PARAMS ((struct mips_cl_insn * ip)); | |
679 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
680 | #ifdef LOSING_COMPILER | |
681 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
682 | #endif | |
683 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
684 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
685 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
686 | boolean, boolean, unsigned long *, | |
687 | boolean *, unsigned short *)); | |
688 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
689 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
690 | static symbolS *get_symbol PARAMS ((void)); | |
691 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
692 | static void s_align PARAMS ((int)); | |
693 | static void s_change_sec PARAMS ((int)); | |
694 | static void s_cons PARAMS ((int)); | |
695 | static void s_float_cons PARAMS ((int)); | |
696 | static void s_mips_globl PARAMS ((int)); | |
697 | static void s_option PARAMS ((int)); | |
698 | static void s_mipsset PARAMS ((int)); | |
699 | static void s_abicalls PARAMS ((int)); | |
700 | static void s_cpload PARAMS ((int)); | |
701 | static void s_cprestore PARAMS ((int)); | |
702 | static void s_gpword PARAMS ((int)); | |
703 | static void s_cpadd PARAMS ((int)); | |
704 | static void s_insn PARAMS ((int)); | |
705 | static void md_obj_begin PARAMS ((void)); | |
706 | static void md_obj_end PARAMS ((void)); | |
707 | static long get_number PARAMS ((void)); | |
708 | static void s_mips_ent PARAMS ((int)); | |
709 | static void s_mips_end PARAMS ((int)); | |
710 | static void s_mips_frame PARAMS ((int)); | |
711 | static void s_mips_mask PARAMS ((int)); | |
712 | static void s_mips_stab PARAMS ((int)); | |
713 | static void s_mips_weakext PARAMS ((int)); | |
714 | static void s_file PARAMS ((int)); | |
715 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
716 | static const char *mips_isa_to_str PARAMS ((int)); |
717 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 718 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e7af610e NC |
719 | |
720 | /* Table and functions used to map between CPU/ISA names, and | |
721 | ISA levels, and CPU numbers. */ | |
722 | ||
e972090a NC |
723 | struct mips_cpu_info |
724 | { | |
e7af610e NC |
725 | const char *name; /* CPU or ISA name. */ |
726 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
727 | int isa; /* ISA level. */ | |
728 | int cpu; /* CPU number (default CPU if ISA). */ | |
729 | }; | |
730 | ||
731 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
732 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
733 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
734 | \f |
735 | /* Pseudo-op table. | |
736 | ||
737 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
738 | should be defined here, but are currently unsupported: .alias, | |
739 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
740 | ||
741 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
742 | specific to the type of debugging information being generated, and | |
743 | should be defined by the object format: .aent, .begin, .bend, | |
744 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
745 | .vreg. | |
746 | ||
747 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
748 | not MIPS CPU specific, but are also not specific to the object file | |
749 | format. This file is probably the best place to define them, but | |
750 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
751 | .struct. */ | |
752 | ||
e972090a NC |
753 | static const pseudo_typeS mips_pseudo_table[] = |
754 | { | |
beae10d5 | 755 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
756 | {"option", s_option, 0}, |
757 | {"set", s_mipsset, 0}, | |
758 | {"rdata", s_change_sec, 'r'}, | |
759 | {"sdata", s_change_sec, 's'}, | |
760 | {"livereg", s_ignore, 0}, | |
761 | {"abicalls", s_abicalls, 0}, | |
762 | {"cpload", s_cpload, 0}, | |
763 | {"cprestore", s_cprestore, 0}, | |
764 | {"gpword", s_gpword, 0}, | |
765 | {"cpadd", s_cpadd, 0}, | |
766 | {"insn", s_insn, 0}, | |
767 | ||
beae10d5 | 768 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
769 | chips. */ |
770 | {"asciiz", stringer, 1}, | |
771 | {"bss", s_change_sec, 'b'}, | |
772 | {"err", s_err, 0}, | |
773 | {"half", s_cons, 1}, | |
774 | {"dword", s_cons, 3}, | |
775 | {"weakext", s_mips_weakext, 0}, | |
776 | ||
beae10d5 | 777 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
778 | here for one reason or another. */ |
779 | {"align", s_align, 0}, | |
780 | {"byte", s_cons, 0}, | |
781 | {"data", s_change_sec, 'd'}, | |
782 | {"double", s_float_cons, 'd'}, | |
783 | {"float", s_float_cons, 'f'}, | |
784 | {"globl", s_mips_globl, 0}, | |
785 | {"global", s_mips_globl, 0}, | |
786 | {"hword", s_cons, 1}, | |
787 | {"int", s_cons, 2}, | |
788 | {"long", s_cons, 2}, | |
789 | {"octa", s_cons, 4}, | |
790 | {"quad", s_cons, 3}, | |
791 | {"short", s_cons, 1}, | |
792 | {"single", s_float_cons, 'f'}, | |
793 | {"stabn", s_mips_stab, 'n'}, | |
794 | {"text", s_change_sec, 't'}, | |
795 | {"word", s_cons, 2}, | |
43841e91 | 796 | { NULL, NULL, 0 }, |
252b5132 RH |
797 | }; |
798 | ||
e972090a NC |
799 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
800 | { | |
beae10d5 KH |
801 | /* These pseudo-ops should be defined by the object file format. |
802 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
803 | {"aent", s_mips_ent, 1}, |
804 | {"bgnb", s_ignore, 0}, | |
805 | {"end", s_mips_end, 0}, | |
806 | {"endb", s_ignore, 0}, | |
807 | {"ent", s_mips_ent, 0}, | |
808 | {"file", s_file, 0}, | |
809 | {"fmask", s_mips_mask, 'F'}, | |
810 | {"frame", s_mips_frame, 0}, | |
811 | {"loc", s_ignore, 0}, | |
812 | {"mask", s_mips_mask, 'R'}, | |
813 | {"verstamp", s_ignore, 0}, | |
43841e91 | 814 | { NULL, NULL, 0 }, |
252b5132 RH |
815 | }; |
816 | ||
817 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
818 | ||
819 | void | |
820 | mips_pop_insert () | |
821 | { | |
822 | pop_insert (mips_pseudo_table); | |
823 | if (! ECOFF_DEBUGGING) | |
824 | pop_insert (mips_nonecoff_pseudo_table); | |
825 | } | |
826 | \f | |
827 | /* Symbols labelling the current insn. */ | |
828 | ||
e972090a NC |
829 | struct insn_label_list |
830 | { | |
252b5132 RH |
831 | struct insn_label_list *next; |
832 | symbolS *label; | |
833 | }; | |
834 | ||
835 | static struct insn_label_list *insn_labels; | |
836 | static struct insn_label_list *free_insn_labels; | |
837 | ||
838 | static void mips_clear_insn_labels PARAMS ((void)); | |
839 | ||
840 | static inline void | |
841 | mips_clear_insn_labels () | |
842 | { | |
843 | register struct insn_label_list **pl; | |
844 | ||
845 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
846 | ; | |
847 | *pl = insn_labels; | |
848 | insn_labels = NULL; | |
849 | } | |
850 | \f | |
851 | static char *expr_end; | |
852 | ||
853 | /* Expressions which appear in instructions. These are set by | |
854 | mips_ip. */ | |
855 | ||
856 | static expressionS imm_expr; | |
857 | static expressionS offset_expr; | |
858 | ||
859 | /* Relocs associated with imm_expr and offset_expr. */ | |
860 | ||
861 | static bfd_reloc_code_real_type imm_reloc; | |
862 | static bfd_reloc_code_real_type offset_reloc; | |
863 | ||
864 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
865 | ||
866 | static boolean imm_unmatched_hi; | |
867 | ||
868 | /* These are set by mips16_ip if an explicit extension is used. */ | |
869 | ||
870 | static boolean mips16_small, mips16_ext; | |
871 | ||
872 | #ifdef MIPS_STABS_ELF | |
873 | /* The pdr segment for per procedure frame/regmask info */ | |
874 | ||
875 | static segT pdr_seg; | |
876 | #endif | |
877 | ||
e7af610e NC |
878 | static const char * |
879 | mips_isa_to_str (isa) | |
880 | int isa; | |
881 | { | |
882 | const struct mips_cpu_info *ci; | |
883 | static char s[20]; | |
884 | ||
885 | ci = mips_cpu_info_from_isa (isa); | |
886 | if (ci != NULL) | |
887 | return (ci->name); | |
888 | ||
889 | sprintf (s, "ISA#%d", isa); | |
890 | return s; | |
891 | } | |
892 | ||
893 | static const char * | |
156c2f8b NC |
894 | mips_cpu_to_str (cpu) |
895 | int cpu; | |
896 | { | |
e7af610e | 897 | const struct mips_cpu_info *ci; |
156c2f8b | 898 | static char s[16]; |
e7af610e NC |
899 | |
900 | ci = mips_cpu_info_from_cpu (cpu); | |
901 | if (ci != NULL) | |
902 | return (ci->name); | |
903 | ||
904 | sprintf (s, "CPU#%d", cpu); | |
905 | return s; | |
156c2f8b NC |
906 | } |
907 | ||
908 | /* This function is called once, at assembler startup time. It should | |
909 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
910 | ||
252b5132 RH |
911 | void |
912 | md_begin () | |
913 | { | |
252b5132 | 914 | register const char *retval = NULL; |
156c2f8b | 915 | int i = 0; |
252b5132 RH |
916 | const char *cpu; |
917 | char *a = NULL; | |
918 | int broken = 0; | |
919 | int mips_isa_from_cpu; | |
e7af610e NC |
920 | int target_cpu_had_mips16 = 0; |
921 | const struct mips_cpu_info *ci; | |
252b5132 | 922 | |
056350c6 NC |
923 | /* GP relative stuff not working for PE */ |
924 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
925 | && g_switch_value != 0) | |
926 | { | |
927 | if (g_switch_seen) | |
928 | as_bad (_("-G not supported in this configuration.")); | |
929 | g_switch_value = 0; | |
930 | } | |
931 | ||
252b5132 RH |
932 | cpu = TARGET_CPU; |
933 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
934 | { | |
935 | a = xmalloc (sizeof TARGET_CPU); | |
936 | strcpy (a, TARGET_CPU); | |
937 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
938 | cpu = a; | |
939 | } | |
940 | ||
e7af610e | 941 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 942 | { |
e7af610e NC |
943 | target_cpu_had_mips16 = 1; |
944 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
945 | } |
946 | ||
e7af610e NC |
947 | if (mips_opts.mips16 < 0) |
948 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 949 | |
e7af610e NC |
950 | /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was |
951 | specified on the command line, or some other value if one was. | |
952 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
953 | the command line, or will be set otherwise if one was. */ | |
954 | if (mips_cpu != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) | |
252b5132 | 955 | { |
e7af610e | 956 | /* We have it all. There's nothing to do. */ |
252b5132 | 957 | } |
e7af610e | 958 | else if (mips_cpu != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 959 | { |
e7af610e NC |
960 | /* We have CPU, we need ISA. */ |
961 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
962 | assert (ci != NULL); | |
963 | mips_opts.isa = ci->isa; | |
964 | } | |
965 | else if (mips_cpu == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) | |
966 | { | |
967 | /* We have ISA, we need default CPU. */ | |
968 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
969 | assert (ci != NULL); | |
970 | mips_cpu = ci->cpu; | |
971 | } | |
972 | else | |
973 | { | |
974 | /* We need to set both ISA and CPU from target cpu. */ | |
975 | ci = mips_cpu_info_from_name (cpu); | |
976 | if (ci == NULL) | |
beae10d5 | 977 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
978 | assert (ci != NULL); |
979 | mips_opts.isa = ci->isa; | |
980 | mips_cpu = ci->cpu; | |
252b5132 RH |
981 | } |
982 | ||
e7af610e NC |
983 | ci = mips_cpu_info_from_cpu (mips_cpu); |
984 | assert (ci != NULL); | |
985 | mips_isa_from_cpu = ci->isa; | |
986 | ||
252b5132 | 987 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 988 | if necessary. */ |
252b5132 RH |
989 | cpu = NULL; |
990 | if (a != NULL) | |
991 | { | |
156c2f8b NC |
992 | free (a); |
993 | a = NULL; | |
252b5132 RH |
994 | } |
995 | ||
e7af610e | 996 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
997 | as_bad (_("trap exception not supported at ISA 1")); |
998 | ||
999 | /* Set the EABI kind based on the ISA before the user gets | |
1000 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1001 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1002 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 | 1003 | && mips_abi_string |
beae10d5 | 1004 | && 0 == strcmp (mips_abi_string, "eabi")) |
252b5132 RH |
1005 | mips_eabi64 = 1; |
1006 | ||
e7af610e NC |
1007 | /* If they asked for mips1 or mips2 and a cpu that is |
1008 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1009 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1010 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1011 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1012 | mips_32bitmode = 1; | |
252b5132 | 1013 | |
e7af610e | 1014 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu)) |
252b5132 RH |
1015 | as_warn (_("Could not set architecture and machine")); |
1016 | ||
1017 | file_mips_isa = mips_opts.isa; | |
1018 | ||
1019 | op_hash = hash_new (); | |
1020 | ||
1021 | for (i = 0; i < NUMOPCODES;) | |
1022 | { | |
1023 | const char *name = mips_opcodes[i].name; | |
1024 | ||
1025 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1026 | if (retval != NULL) | |
1027 | { | |
1028 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1029 | mips_opcodes[i].name, retval); | |
1030 | /* Probably a memory allocation problem? Give up now. */ | |
1031 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1032 | } | |
1033 | do | |
1034 | { | |
1035 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1036 | { | |
1037 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1038 | broken = 1; | |
1039 | } | |
1040 | ++i; | |
1041 | } | |
1042 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1043 | } | |
1044 | ||
1045 | mips16_op_hash = hash_new (); | |
1046 | ||
1047 | i = 0; | |
1048 | while (i < bfd_mips16_num_opcodes) | |
1049 | { | |
1050 | const char *name = mips16_opcodes[i].name; | |
1051 | ||
1052 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1053 | if (retval != NULL) | |
1054 | as_fatal (_("internal: can't hash `%s': %s"), | |
1055 | mips16_opcodes[i].name, retval); | |
1056 | do | |
1057 | { | |
1058 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1059 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1060 | != mips16_opcodes[i].match)) | |
1061 | { | |
1062 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1063 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1064 | broken = 1; | |
1065 | } | |
1066 | ++i; | |
1067 | } | |
1068 | while (i < bfd_mips16_num_opcodes | |
1069 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1070 | } | |
1071 | ||
1072 | if (broken) | |
1073 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1074 | ||
1075 | /* We add all the general register names to the symbol table. This | |
1076 | helps us detect invalid uses of them. */ | |
1077 | for (i = 0; i < 32; i++) | |
1078 | { | |
1079 | char buf[5]; | |
1080 | ||
1081 | sprintf (buf, "$%d", i); | |
1082 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1083 | &zero_address_frag)); | |
1084 | } | |
1085 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1086 | &zero_address_frag)); | |
1087 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1088 | &zero_address_frag)); | |
1089 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1090 | &zero_address_frag)); | |
1091 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1092 | &zero_address_frag)); | |
1093 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1094 | &zero_address_frag)); | |
1095 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1096 | &zero_address_frag)); | |
1097 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1098 | &zero_address_frag)); | |
1099 | ||
1100 | mips_no_prev_insn (false); | |
1101 | ||
1102 | mips_gprmask = 0; | |
1103 | mips_cprmask[0] = 0; | |
1104 | mips_cprmask[1] = 0; | |
1105 | mips_cprmask[2] = 0; | |
1106 | mips_cprmask[3] = 0; | |
1107 | ||
1108 | /* set the default alignment for the text section (2**2) */ | |
1109 | record_alignment (text_section, 2); | |
1110 | ||
1111 | if (USE_GLOBAL_POINTER_OPT) | |
1112 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1113 | ||
1114 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1115 | { | |
1116 | /* On a native system, sections must be aligned to 16 byte | |
1117 | boundaries. When configured for an embedded ELF target, we | |
1118 | don't bother. */ | |
1119 | if (strcmp (TARGET_OS, "elf") != 0) | |
1120 | { | |
1121 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1122 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1123 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1124 | } | |
1125 | ||
1126 | /* Create a .reginfo section for register masks and a .mdebug | |
1127 | section for debugging information. */ | |
1128 | { | |
1129 | segT seg; | |
1130 | subsegT subseg; | |
1131 | flagword flags; | |
1132 | segT sec; | |
1133 | ||
1134 | seg = now_seg; | |
1135 | subseg = now_subseg; | |
1136 | ||
1137 | /* The ABI says this section should be loaded so that the | |
1138 | running program can access it. However, we don't load it | |
1139 | if we are configured for an embedded target */ | |
1140 | flags = SEC_READONLY | SEC_DATA; | |
1141 | if (strcmp (TARGET_OS, "elf") != 0) | |
1142 | flags |= SEC_ALLOC | SEC_LOAD; | |
1143 | ||
1144 | if (! mips_64) | |
1145 | { | |
1146 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1147 | ||
252b5132 RH |
1148 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
1149 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
bdaaa2e1 | 1150 | |
252b5132 RH |
1151 | #ifdef OBJ_ELF |
1152 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1153 | #endif | |
1154 | } | |
1155 | else | |
1156 | { | |
1157 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1158 | .reginfo section. */ | |
1159 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1160 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1161 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1162 | ||
1163 | #ifdef OBJ_ELF | |
1164 | /* Set up the option header. */ | |
1165 | { | |
1166 | Elf_Internal_Options opthdr; | |
1167 | char *f; | |
1168 | ||
1169 | opthdr.kind = ODK_REGINFO; | |
1170 | opthdr.size = (sizeof (Elf_External_Options) | |
1171 | + sizeof (Elf64_External_RegInfo)); | |
1172 | opthdr.section = 0; | |
1173 | opthdr.info = 0; | |
1174 | f = frag_more (sizeof (Elf_External_Options)); | |
1175 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1176 | (Elf_External_Options *) f); | |
1177 | ||
1178 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1179 | } | |
1180 | #endif | |
1181 | } | |
1182 | ||
1183 | if (ECOFF_DEBUGGING) | |
1184 | { | |
1185 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1186 | (void) bfd_set_section_flags (stdoutput, sec, | |
1187 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1188 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1189 | } | |
1190 | ||
1191 | #ifdef MIPS_STABS_ELF | |
1192 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1193 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1194 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1195 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1196 | #endif | |
1197 | ||
1198 | subseg_set (seg, subseg); | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | if (! ECOFF_DEBUGGING) | |
1203 | md_obj_begin (); | |
1204 | } | |
1205 | ||
1206 | void | |
1207 | md_mips_end () | |
1208 | { | |
1209 | if (! ECOFF_DEBUGGING) | |
1210 | md_obj_end (); | |
1211 | } | |
1212 | ||
1213 | void | |
1214 | md_assemble (str) | |
1215 | char *str; | |
1216 | { | |
1217 | struct mips_cl_insn insn; | |
1218 | ||
1219 | imm_expr.X_op = O_absent; | |
1220 | imm_reloc = BFD_RELOC_UNUSED; | |
1221 | imm_unmatched_hi = false; | |
1222 | offset_expr.X_op = O_absent; | |
1223 | offset_reloc = BFD_RELOC_UNUSED; | |
1224 | ||
1225 | if (mips_opts.mips16) | |
1226 | mips16_ip (str, &insn); | |
1227 | else | |
1228 | { | |
1229 | mips_ip (str, &insn); | |
beae10d5 KH |
1230 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1231 | str, insn.insn_opcode)); | |
252b5132 RH |
1232 | } |
1233 | ||
1234 | if (insn_error) | |
1235 | { | |
1236 | as_bad ("%s `%s'", insn_error, str); | |
1237 | return; | |
1238 | } | |
1239 | ||
1240 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1241 | { | |
1242 | if (mips_opts.mips16) | |
1243 | mips16_macro (&insn); | |
1244 | else | |
1245 | macro (&insn); | |
1246 | } | |
1247 | else | |
1248 | { | |
1249 | if (imm_expr.X_op != O_absent) | |
1250 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1251 | imm_unmatched_hi); | |
1252 | else if (offset_expr.X_op != O_absent) | |
1253 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1254 | else | |
1255 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | /* See whether instruction IP reads register REG. CLASS is the type | |
1260 | of register. */ | |
1261 | ||
1262 | static int | |
1263 | insn_uses_reg (ip, reg, class) | |
1264 | struct mips_cl_insn *ip; | |
1265 | unsigned int reg; | |
1266 | enum mips_regclass class; | |
1267 | { | |
1268 | if (class == MIPS16_REG) | |
1269 | { | |
1270 | assert (mips_opts.mips16); | |
1271 | reg = mips16_to_32_reg_map[reg]; | |
1272 | class = MIPS_GR_REG; | |
1273 | } | |
1274 | ||
1275 | /* Don't report on general register 0, since it never changes. */ | |
1276 | if (class == MIPS_GR_REG && reg == 0) | |
1277 | return 0; | |
1278 | ||
1279 | if (class == MIPS_FP_REG) | |
1280 | { | |
1281 | assert (! mips_opts.mips16); | |
1282 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1283 | This is not optimal, because it will introduce an unnecessary | |
1284 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1285 | need to distinguish reading both $f0 and $f1 or just one of | |
1286 | them. Note that we don't have to check the other way, | |
1287 | because there is no instruction that sets both $f0 and $f1 | |
1288 | and requires a delay. */ | |
1289 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1290 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1291 | == (reg &~ (unsigned) 1))) | |
1292 | return 1; | |
1293 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1294 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1295 | == (reg &~ (unsigned) 1))) | |
1296 | return 1; | |
1297 | } | |
1298 | else if (! mips_opts.mips16) | |
1299 | { | |
1300 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1301 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1302 | return 1; | |
1303 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1304 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1305 | return 1; | |
1306 | } | |
1307 | else | |
1308 | { | |
1309 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1310 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1311 | & MIPS16OP_MASK_RX)] | |
1312 | == reg)) | |
1313 | return 1; | |
1314 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1315 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1316 | & MIPS16OP_MASK_RY)] | |
1317 | == reg)) | |
1318 | return 1; | |
1319 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1320 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1321 | & MIPS16OP_MASK_MOVE32Z)] | |
1322 | == reg)) | |
1323 | return 1; | |
1324 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1325 | return 1; | |
1326 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1327 | return 1; | |
1328 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1329 | return 1; | |
1330 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1331 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1332 | & MIPS16OP_MASK_REGR32) == reg) | |
1333 | return 1; | |
1334 | } | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | /* This function returns true if modifying a register requires a | |
1340 | delay. */ | |
1341 | ||
1342 | static int | |
1343 | reg_needs_delay (reg) | |
156c2f8b | 1344 | unsigned int reg; |
252b5132 RH |
1345 | { |
1346 | unsigned long prev_pinfo; | |
1347 | ||
1348 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1349 | if (! mips_opts.noreorder | |
9ce8a5dd | 1350 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1351 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1352 | || (! gpr_interlocks | |
1353 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1354 | { | |
1355 | /* A load from a coprocessor or from memory. All load | |
1356 | delays delay the use of general register rt for one | |
1357 | instruction on the r3000. The r6000 and r4000 use | |
1358 | interlocks. */ | |
bdaaa2e1 | 1359 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1360 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1361 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1362 | return 1; | |
1363 | } | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1369 | handle them specially, such as generating jalx instructions when | |
1370 | needed. We also make them odd for the duration of the assembly, in | |
1371 | order to generate the right sort of code. We will make them even | |
1372 | in the adjust_symtab routine, while leaving them marked. This is | |
1373 | convenient for the debugger and the disassembler. The linker knows | |
1374 | to make them odd again. */ | |
1375 | ||
1376 | static void | |
1377 | mips16_mark_labels () | |
1378 | { | |
1379 | if (mips_opts.mips16) | |
1380 | { | |
1381 | struct insn_label_list *l; | |
1382 | ||
1383 | for (l = insn_labels; l != NULL; l = l->next) | |
1384 | { | |
1385 | #ifdef OBJ_ELF | |
1386 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1387 | S_SET_OTHER (l->label, STO_MIPS16); | |
1388 | #endif | |
49309057 ILT |
1389 | if ((S_GET_VALUE (l->label) & 1) == 0) |
1390 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); | |
252b5132 RH |
1391 | } |
1392 | } | |
1393 | } | |
1394 | ||
1395 | /* Output an instruction. PLACE is where to put the instruction; if | |
1396 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1397 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1398 | used with RELOC_TYPE. */ | |
1399 | ||
1400 | static void | |
1401 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1402 | char *place; | |
1403 | struct mips_cl_insn *ip; | |
1404 | expressionS *address_expr; | |
1405 | bfd_reloc_code_real_type reloc_type; | |
1406 | boolean unmatched_hi; | |
1407 | { | |
1408 | register unsigned long prev_pinfo, pinfo; | |
1409 | char *f; | |
1410 | fixS *fixp; | |
1411 | int nops = 0; | |
1412 | ||
1413 | /* Mark instruction labels in mips16 mode. */ | |
1414 | if (mips_opts.mips16) | |
1415 | mips16_mark_labels (); | |
1416 | ||
1417 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1418 | pinfo = ip->insn_mo->pinfo; | |
1419 | ||
1420 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1421 | { | |
1422 | int prev_prev_nop; | |
1423 | ||
1424 | /* If the previous insn required any delay slots, see if we need | |
1425 | to insert a NOP or two. There are eight kinds of possible | |
1426 | hazards, of which an instruction can have at most one type. | |
1427 | (1) a load from memory delay | |
1428 | (2) a load from a coprocessor delay | |
1429 | (3) an unconditional branch delay | |
1430 | (4) a conditional branch delay | |
1431 | (5) a move to coprocessor register delay | |
1432 | (6) a load coprocessor register from memory delay | |
1433 | (7) a coprocessor condition code delay | |
1434 | (8) a HI/LO special register delay | |
1435 | ||
1436 | There are a lot of optimizations we could do that we don't. | |
1437 | In particular, we do not, in general, reorder instructions. | |
1438 | If you use gcc with optimization, it will reorder | |
1439 | instructions and generally do much more optimization then we | |
1440 | do here; repeating all that work in the assembler would only | |
1441 | benefit hand written assembly code, and does not seem worth | |
1442 | it. */ | |
1443 | ||
1444 | /* This is how a NOP is emitted. */ | |
1445 | #define emit_nop() \ | |
1446 | (mips_opts.mips16 \ | |
1447 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1448 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1449 | ||
1450 | /* The previous insn might require a delay slot, depending upon | |
1451 | the contents of the current insn. */ | |
1452 | if (! mips_opts.mips16 | |
9ce8a5dd | 1453 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1454 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1455 | && ! cop_interlocks) | |
1456 | || (! gpr_interlocks | |
1457 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1458 | { | |
1459 | /* A load from a coprocessor or from memory. All load | |
1460 | delays delay the use of general register rt for one | |
1461 | instruction on the r3000. The r6000 and r4000 use | |
1462 | interlocks. */ | |
beae10d5 | 1463 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1464 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1465 | if (mips_optimize == 0 | |
1466 | || insn_uses_reg (ip, | |
1467 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1468 | & OP_MASK_RT), | |
1469 | MIPS_GR_REG)) | |
1470 | ++nops; | |
1471 | } | |
1472 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1473 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1474 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1475 | && ! cop_interlocks) |
e7af610e | 1476 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1477 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1478 | { | |
1479 | /* A generic coprocessor delay. The previous instruction | |
1480 | modified a coprocessor general or control register. If | |
1481 | it modified a control register, we need to avoid any | |
1482 | coprocessor instruction (this is probably not always | |
1483 | required, but it sometimes is). If it modified a general | |
1484 | register, we avoid using that register. | |
1485 | ||
1486 | On the r6000 and r4000 loading a coprocessor register | |
1487 | from memory is interlocked, and does not require a delay. | |
1488 | ||
1489 | This case is not handled very well. There is no special | |
1490 | knowledge of CP0 handling, and the coprocessors other | |
1491 | than the floating point unit are not distinguished at | |
1492 | all. */ | |
1493 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1494 | Need to modify this to include knowledge about |
252b5132 RH |
1495 | user specified delays! */ |
1496 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1497 | { | |
1498 | if (mips_optimize == 0 | |
1499 | || insn_uses_reg (ip, | |
1500 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1501 | & OP_MASK_FT), | |
1502 | MIPS_FP_REG)) | |
1503 | ++nops; | |
1504 | } | |
1505 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1506 | { | |
1507 | if (mips_optimize == 0 | |
1508 | || insn_uses_reg (ip, | |
1509 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1510 | & OP_MASK_FS), | |
1511 | MIPS_FP_REG)) | |
1512 | ++nops; | |
1513 | } | |
1514 | else | |
1515 | { | |
1516 | /* We don't know exactly what the previous instruction | |
1517 | does. If the current instruction uses a coprocessor | |
1518 | register, we must insert a NOP. If previous | |
1519 | instruction may set the condition codes, and the | |
1520 | current instruction uses them, we must insert two | |
1521 | NOPS. */ | |
bdaaa2e1 | 1522 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1523 | if (mips_optimize == 0 |
1524 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1525 | && (pinfo & INSN_READ_COND_CODE))) | |
1526 | nops += 2; | |
1527 | else if (pinfo & INSN_COP) | |
1528 | ++nops; | |
1529 | } | |
1530 | } | |
1531 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1532 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1533 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1534 | && ! cop_interlocks) | |
1535 | { | |
1536 | /* The previous instruction sets the coprocessor condition | |
1537 | codes, but does not require a general coprocessor delay | |
1538 | (this means it is a floating point comparison | |
1539 | instruction). If this instruction uses the condition | |
1540 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1541 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1542 | if (mips_optimize == 0 |
1543 | || (pinfo & INSN_READ_COND_CODE)) | |
1544 | ++nops; | |
1545 | } | |
6b76fefe CM |
1546 | |
1547 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1548 | previous insn was an mfhi/mflo and the current insn | |
1549 | reads the register that the mfhi/mflo wrote to, then | |
1550 | insert two nops. */ | |
1551 | ||
1552 | else if (mips_7000_hilo_fix | |
1553 | && MF_HILO_INSN (prev_pinfo) | |
1554 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1555 | & OP_MASK_RD), |
1556 | MIPS_GR_REG)) | |
6b76fefe CM |
1557 | { |
1558 | nops += 2; | |
1559 | } | |
1560 | ||
1561 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1562 | 2nd previous insn was an mfhi/mflo and the current insn | |
1563 | reads the register that the mfhi/mflo wrote to, then | |
1564 | insert one nop. */ | |
1565 | ||
1566 | else if (mips_7000_hilo_fix | |
1567 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1568 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1569 | & OP_MASK_RD), | |
1570 | MIPS_GR_REG)) | |
bdaaa2e1 | 1571 | |
6b76fefe CM |
1572 | { |
1573 | nops += 1; | |
1574 | } | |
bdaaa2e1 | 1575 | |
252b5132 RH |
1576 | else if (prev_pinfo & INSN_READ_LO) |
1577 | { | |
1578 | /* The previous instruction reads the LO register; if the | |
1579 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1580 | insert two NOPS. Some newer processors have interlocks. |
1581 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1582 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1583 | though the tx39's divide insns still do require the |
1584 | delay. */ | |
252b5132 | 1585 | if (! (hilo_interlocks |
156c2f8b | 1586 | || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1587 | && (mips_optimize == 0 |
1588 | || (pinfo & INSN_WRITE_LO))) | |
1589 | nops += 2; | |
1590 | /* Most mips16 branch insns don't have a delay slot. | |
1591 | If a read from LO is immediately followed by a branch | |
1592 | to a write to LO we have a read followed by a write | |
1593 | less than 2 insns away. We assume the target of | |
1594 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1595 | between a read and an immediately following branch. */ |
252b5132 RH |
1596 | else if (mips_opts.mips16 |
1597 | && (mips_optimize == 0 | |
1598 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1599 | nops += 1; | |
1600 | } | |
1601 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1602 | { | |
1603 | /* The previous instruction reads the HI register; if the | |
1604 | current instruction writes to the HI register, we must | |
1605 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1606 | Also the note tx39's multiply above. */ |
252b5132 | 1607 | if (! (hilo_interlocks |
156c2f8b | 1608 | || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1609 | && (mips_optimize == 0 |
1610 | || (pinfo & INSN_WRITE_HI))) | |
1611 | nops += 2; | |
1612 | /* Most mips16 branch insns don't have a delay slot. | |
1613 | If a read from HI is immediately followed by a branch | |
1614 | to a write to HI we have a read followed by a write | |
1615 | less than 2 insns away. We assume the target of | |
1616 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1617 | between a read and an immediately following branch. */ |
252b5132 RH |
1618 | else if (mips_opts.mips16 |
1619 | && (mips_optimize == 0 | |
1620 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1621 | nops += 1; | |
1622 | } | |
1623 | ||
1624 | /* If the previous instruction was in a noreorder section, then | |
1625 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1626 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1627 | if (prev_insn_unreordered) |
1628 | nops = 0; | |
1629 | ||
1630 | /* There are two cases which require two intervening | |
1631 | instructions: 1) setting the condition codes using a move to | |
1632 | coprocessor instruction which requires a general coprocessor | |
1633 | delay and then reading the condition codes 2) reading the HI | |
1634 | or LO register and then writing to it (except on processors | |
1635 | which have interlocks). If we are not already emitting a NOP | |
1636 | instruction, we must check for these cases compared to the | |
1637 | instruction previous to the previous instruction. */ | |
1638 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1639 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1640 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1641 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1642 | && (pinfo & INSN_READ_COND_CODE) | |
1643 | && ! cop_interlocks) | |
1644 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1645 | && (pinfo & INSN_WRITE_LO) | |
1646 | && ! (hilo_interlocks | |
156c2f8b | 1647 | || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1648 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1649 | && (pinfo & INSN_WRITE_HI) | |
1650 | && ! (hilo_interlocks | |
156c2f8b | 1651 | || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1652 | prev_prev_nop = 1; |
1653 | else | |
1654 | prev_prev_nop = 0; | |
1655 | ||
1656 | if (prev_prev_insn_unreordered) | |
1657 | prev_prev_nop = 0; | |
1658 | ||
1659 | if (prev_prev_nop && nops == 0) | |
1660 | ++nops; | |
1661 | ||
1662 | /* If we are being given a nop instruction, don't bother with | |
1663 | one of the nops we would otherwise output. This will only | |
1664 | happen when a nop instruction is used with mips_optimize set | |
1665 | to 0. */ | |
1666 | if (nops > 0 | |
1667 | && ! mips_opts.noreorder | |
156c2f8b | 1668 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1669 | --nops; |
1670 | ||
1671 | /* Now emit the right number of NOP instructions. */ | |
1672 | if (nops > 0 && ! mips_opts.noreorder) | |
1673 | { | |
1674 | fragS *old_frag; | |
1675 | unsigned long old_frag_offset; | |
1676 | int i; | |
1677 | struct insn_label_list *l; | |
1678 | ||
1679 | old_frag = frag_now; | |
1680 | old_frag_offset = frag_now_fix (); | |
1681 | ||
1682 | for (i = 0; i < nops; i++) | |
1683 | emit_nop (); | |
1684 | ||
1685 | if (listing) | |
1686 | { | |
1687 | listing_prev_line (); | |
1688 | /* We may be at the start of a variant frag. In case we | |
1689 | are, make sure there is enough space for the frag | |
1690 | after the frags created by listing_prev_line. The | |
1691 | argument to frag_grow here must be at least as large | |
1692 | as the argument to all other calls to frag_grow in | |
1693 | this file. We don't have to worry about being in the | |
1694 | middle of a variant frag, because the variants insert | |
1695 | all needed nop instructions themselves. */ | |
1696 | frag_grow (40); | |
1697 | } | |
1698 | ||
1699 | for (l = insn_labels; l != NULL; l = l->next) | |
1700 | { | |
1701 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 1702 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
1703 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
1704 | /* mips16 text labels are stored as odd. */ | |
1705 | if (mips_opts.mips16) | |
49309057 | 1706 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
1707 | } |
1708 | ||
1709 | #ifndef NO_ECOFF_DEBUGGING | |
1710 | if (ECOFF_DEBUGGING) | |
1711 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1712 | #endif | |
1713 | } | |
1714 | else if (prev_nop_frag != NULL) | |
1715 | { | |
1716 | /* We have a frag holding nops we may be able to remove. If | |
1717 | we don't need any nops, we can decrease the size of | |
1718 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1719 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1720 | if (prev_nop_frag_since == 0) |
1721 | { | |
1722 | if (nops == 0) | |
1723 | { | |
1724 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1725 | --prev_nop_frag_holds; | |
1726 | } | |
1727 | else | |
1728 | prev_nop_frag_required += nops; | |
1729 | } | |
1730 | else | |
1731 | { | |
1732 | if (prev_prev_nop == 0) | |
1733 | { | |
1734 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1735 | --prev_nop_frag_holds; | |
1736 | } | |
1737 | else | |
1738 | ++prev_nop_frag_required; | |
1739 | } | |
1740 | ||
1741 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1742 | prev_nop_frag = NULL; | |
1743 | ||
1744 | ++prev_nop_frag_since; | |
1745 | ||
1746 | /* Sanity check: by the time we reach the second instruction | |
1747 | after prev_nop_frag, we should have used up all the nops | |
1748 | one way or another. */ | |
1749 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | if (reloc_type > BFD_RELOC_UNUSED) | |
1754 | { | |
1755 | /* We need to set up a variant frag. */ | |
1756 | assert (mips_opts.mips16 && address_expr != NULL); | |
1757 | f = frag_var (rs_machine_dependent, 4, 0, | |
1758 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, | |
1759 | mips16_small, mips16_ext, | |
1760 | (prev_pinfo | |
1761 | & INSN_UNCOND_BRANCH_DELAY), | |
1762 | (prev_insn_reloc_type | |
1763 | == BFD_RELOC_MIPS16_JMP)), | |
1764 | make_expr_symbol (address_expr), (offsetT) 0, | |
1765 | (char *) NULL); | |
1766 | } | |
1767 | else if (place != NULL) | |
1768 | f = place; | |
1769 | else if (mips_opts.mips16 | |
1770 | && ! ip->use_extend | |
1771 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
1772 | { | |
1773 | /* Make sure there is enough room to swap this instruction with | |
1774 | a following jump instruction. */ | |
1775 | frag_grow (6); | |
1776 | f = frag_more (2); | |
1777 | } | |
1778 | else | |
1779 | { | |
1780 | if (mips_opts.mips16 | |
1781 | && mips_opts.noreorder | |
1782 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1783 | as_warn (_("extended instruction in delay slot")); | |
1784 | ||
1785 | f = frag_more (4); | |
1786 | } | |
1787 | ||
1788 | fixp = NULL; | |
1789 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) | |
1790 | { | |
1791 | if (address_expr->X_op == O_constant) | |
1792 | { | |
1793 | switch (reloc_type) | |
1794 | { | |
1795 | case BFD_RELOC_32: | |
1796 | ip->insn_opcode |= address_expr->X_add_number; | |
1797 | break; | |
1798 | ||
1799 | case BFD_RELOC_LO16: | |
1800 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1801 | break; | |
1802 | ||
1803 | case BFD_RELOC_MIPS_JMP: | |
1804 | if ((address_expr->X_add_number & 3) != 0) | |
1805 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1806 | (unsigned long) address_expr->X_add_number); | |
1807 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1808 | break; | |
1809 | ||
1810 | case BFD_RELOC_MIPS16_JMP: | |
1811 | if ((address_expr->X_add_number & 3) != 0) | |
1812 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1813 | (unsigned long) address_expr->X_add_number); | |
1814 | ip->insn_opcode |= | |
1815 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1816 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1817 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1818 | break; | |
1819 | ||
252b5132 RH |
1820 | case BFD_RELOC_16_PCREL_S2: |
1821 | goto need_reloc; | |
1822 | ||
1823 | default: | |
1824 | internalError (); | |
1825 | } | |
1826 | } | |
1827 | else | |
1828 | { | |
1829 | need_reloc: | |
1830 | /* Don't generate a reloc if we are writing into a variant | |
1831 | frag. */ | |
1832 | if (place == NULL) | |
1833 | { | |
1834 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1835 | address_expr, | |
1836 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1837 | reloc_type); | |
1838 | if (unmatched_hi) | |
1839 | { | |
1840 | struct mips_hi_fixup *hi_fixup; | |
1841 | ||
1842 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1843 | hi_fixup = ((struct mips_hi_fixup *) | |
1844 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1845 | hi_fixup->fixp = fixp; | |
1846 | hi_fixup->seg = now_seg; | |
1847 | hi_fixup->next = mips_hi_fixup_list; | |
1848 | mips_hi_fixup_list = hi_fixup; | |
1849 | } | |
1850 | } | |
1851 | } | |
1852 | } | |
1853 | ||
1854 | if (! mips_opts.mips16) | |
1855 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1856 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) | |
1857 | { | |
1858 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1859 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1860 | } | |
1861 | else | |
1862 | { | |
1863 | if (ip->use_extend) | |
1864 | { | |
1865 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1866 | f += 2; | |
1867 | } | |
1868 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1869 | } | |
1870 | ||
1871 | /* Update the register mask information. */ | |
1872 | if (! mips_opts.mips16) | |
1873 | { | |
1874 | if (pinfo & INSN_WRITE_GPR_D) | |
1875 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1876 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1877 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1878 | if (pinfo & INSN_READ_GPR_S) | |
1879 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1880 | if (pinfo & INSN_WRITE_GPR_31) | |
1881 | mips_gprmask |= 1 << 31; | |
1882 | if (pinfo & INSN_WRITE_FPR_D) | |
1883 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1884 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1885 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1886 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1887 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1888 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1889 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1890 | if (pinfo & INSN_COP) | |
1891 | { | |
bdaaa2e1 KH |
1892 | /* We don't keep enough information to sort these cases out. |
1893 | The itbl support does keep this information however, although | |
1894 | we currently don't support itbl fprmats as part of the cop | |
1895 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
1896 | } |
1897 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 1898 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
1899 | } |
1900 | else | |
1901 | { | |
1902 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
1903 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1904 | & MIPS16OP_MASK_RX); | |
1905 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1906 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1907 | & MIPS16OP_MASK_RY); | |
1908 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1909 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1910 | & MIPS16OP_MASK_RZ); | |
1911 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1912 | mips_gprmask |= 1 << TREG; | |
1913 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1914 | mips_gprmask |= 1 << SP; | |
1915 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1916 | mips_gprmask |= 1 << RA; | |
1917 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1918 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1919 | if (pinfo & MIPS16_INSN_READ_Z) | |
1920 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1921 | & MIPS16OP_MASK_MOVE32Z); | |
1922 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1923 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1924 | & MIPS16OP_MASK_REGR32); | |
1925 | } | |
1926 | ||
1927 | if (place == NULL && ! mips_opts.noreorder) | |
1928 | { | |
1929 | /* Filling the branch delay slot is more complex. We try to | |
1930 | switch the branch with the previous instruction, which we can | |
1931 | do if the previous instruction does not set up a condition | |
1932 | that the branch tests and if the branch is not itself the | |
1933 | target of any branch. */ | |
1934 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1935 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
1936 | { | |
1937 | if (mips_optimize < 2 | |
1938 | /* If we have seen .set volatile or .set nomove, don't | |
1939 | optimize. */ | |
1940 | || mips_opts.nomove != 0 | |
1941 | /* If we had to emit any NOP instructions, then we | |
1942 | already know we can not swap. */ | |
1943 | || nops != 0 | |
1944 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 1945 | swap. */ |
252b5132 RH |
1946 | || ! prev_insn_valid |
1947 | /* If the previous insn is already in a branch delay | |
1948 | slot, then we can not swap. */ | |
1949 | || prev_insn_is_delay_slot | |
1950 | /* If the previous previous insn was in a .set | |
1951 | noreorder, we can't swap. Actually, the MIPS | |
1952 | assembler will swap in this situation. However, gcc | |
1953 | configured -with-gnu-as will generate code like | |
1954 | .set noreorder | |
1955 | lw $4,XXX | |
1956 | .set reorder | |
1957 | INSN | |
1958 | bne $4,$0,foo | |
1959 | in which we can not swap the bne and INSN. If gcc is | |
1960 | not configured -with-gnu-as, it does not output the | |
1961 | .set pseudo-ops. We don't have to check | |
1962 | prev_insn_unreordered, because prev_insn_valid will | |
1963 | be 0 in that case. We don't want to use | |
1964 | prev_prev_insn_valid, because we do want to be able | |
1965 | to swap at the start of a function. */ | |
1966 | || prev_prev_insn_unreordered | |
1967 | /* If the branch is itself the target of a branch, we | |
1968 | can not swap. We cheat on this; all we check for is | |
1969 | whether there is a label on this instruction. If | |
1970 | there are any branches to anything other than a | |
1971 | label, users must use .set noreorder. */ | |
1972 | || insn_labels != NULL | |
1973 | /* If the previous instruction is in a variant frag, we | |
1974 | can not do the swap. This does not apply to the | |
1975 | mips16, which uses variant frags for different | |
1976 | purposes. */ | |
1977 | || (! mips_opts.mips16 | |
1978 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
1979 | /* If the branch reads the condition codes, we don't | |
1980 | even try to swap, because in the sequence | |
1981 | ctc1 $X,$31 | |
1982 | INSN | |
1983 | INSN | |
1984 | bc1t LABEL | |
1985 | we can not swap, and I don't feel like handling that | |
1986 | case. */ | |
1987 | || (! mips_opts.mips16 | |
9ce8a5dd | 1988 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1989 | && (pinfo & INSN_READ_COND_CODE)) |
1990 | /* We can not swap with an instruction that requires a | |
1991 | delay slot, becase the target of the branch might | |
1992 | interfere with that instruction. */ | |
1993 | || (! mips_opts.mips16 | |
9ce8a5dd | 1994 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1995 | && (prev_pinfo |
bdaaa2e1 | 1996 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1997 | & (INSN_LOAD_COPROC_DELAY |
1998 | | INSN_COPROC_MOVE_DELAY | |
1999 | | INSN_WRITE_COND_CODE))) | |
2000 | || (! (hilo_interlocks | |
156c2f8b | 2001 | || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2002 | && (prev_pinfo |
2003 | & (INSN_READ_LO | |
2004 | | INSN_READ_HI))) | |
2005 | || (! mips_opts.mips16 | |
2006 | && ! gpr_interlocks | |
2007 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2008 | || (! mips_opts.mips16 | |
e7af610e | 2009 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2010 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2011 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2012 | /* We can not swap with a branch instruction. */ | |
2013 | || (prev_pinfo | |
2014 | & (INSN_UNCOND_BRANCH_DELAY | |
2015 | | INSN_COND_BRANCH_DELAY | |
2016 | | INSN_COND_BRANCH_LIKELY)) | |
2017 | /* We do not swap with a trap instruction, since it | |
2018 | complicates trap handlers to have the trap | |
2019 | instruction be in a delay slot. */ | |
2020 | || (prev_pinfo & INSN_TRAP) | |
2021 | /* If the branch reads a register that the previous | |
2022 | instruction sets, we can not swap. */ | |
2023 | || (! mips_opts.mips16 | |
2024 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2025 | && insn_uses_reg (ip, | |
2026 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2027 | & OP_MASK_RT), | |
2028 | MIPS_GR_REG)) | |
2029 | || (! mips_opts.mips16 | |
2030 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2031 | && insn_uses_reg (ip, | |
2032 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2033 | & OP_MASK_RD), | |
2034 | MIPS_GR_REG)) | |
2035 | || (mips_opts.mips16 | |
2036 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2037 | && insn_uses_reg (ip, | |
2038 | ((prev_insn.insn_opcode | |
2039 | >> MIPS16OP_SH_RX) | |
2040 | & MIPS16OP_MASK_RX), | |
2041 | MIPS16_REG)) | |
2042 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2043 | && insn_uses_reg (ip, | |
2044 | ((prev_insn.insn_opcode | |
2045 | >> MIPS16OP_SH_RY) | |
2046 | & MIPS16OP_MASK_RY), | |
2047 | MIPS16_REG)) | |
2048 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2049 | && insn_uses_reg (ip, | |
2050 | ((prev_insn.insn_opcode | |
2051 | >> MIPS16OP_SH_RZ) | |
2052 | & MIPS16OP_MASK_RZ), | |
2053 | MIPS16_REG)) | |
2054 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2055 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2056 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2057 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2058 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2059 | && insn_uses_reg (ip, | |
2060 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2061 | insn_opcode), | |
2062 | MIPS_GR_REG)))) | |
2063 | /* If the branch writes a register that the previous | |
2064 | instruction sets, we can not swap (we know that | |
2065 | branches write only to RD or to $31). */ | |
2066 | || (! mips_opts.mips16 | |
2067 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2068 | && (((pinfo & INSN_WRITE_GPR_D) | |
2069 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2070 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2071 | || ((pinfo & INSN_WRITE_GPR_31) | |
2072 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2073 | & OP_MASK_RT) | |
2074 | == 31)))) | |
2075 | || (! mips_opts.mips16 | |
2076 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2077 | && (((pinfo & INSN_WRITE_GPR_D) | |
2078 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2079 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2080 | || ((pinfo & INSN_WRITE_GPR_31) | |
2081 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2082 | & OP_MASK_RD) | |
2083 | == 31)))) | |
2084 | || (mips_opts.mips16 | |
2085 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2086 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2087 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2088 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2089 | == RA)))) | |
2090 | /* If the branch writes a register that the previous | |
2091 | instruction reads, we can not swap (we know that | |
2092 | branches only write to RD or to $31). */ | |
2093 | || (! mips_opts.mips16 | |
2094 | && (pinfo & INSN_WRITE_GPR_D) | |
2095 | && insn_uses_reg (&prev_insn, | |
2096 | ((ip->insn_opcode >> OP_SH_RD) | |
2097 | & OP_MASK_RD), | |
2098 | MIPS_GR_REG)) | |
2099 | || (! mips_opts.mips16 | |
2100 | && (pinfo & INSN_WRITE_GPR_31) | |
2101 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2102 | || (mips_opts.mips16 | |
2103 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2104 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2105 | /* If we are generating embedded PIC code, the branch | |
2106 | might be expanded into a sequence which uses $at, so | |
2107 | we can't swap with an instruction which reads it. */ | |
2108 | || (mips_pic == EMBEDDED_PIC | |
2109 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2110 | /* If the previous previous instruction has a load | |
2111 | delay, and sets a register that the branch reads, we | |
2112 | can not swap. */ | |
2113 | || (! mips_opts.mips16 | |
9ce8a5dd | 2114 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2115 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2116 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2117 | || (! gpr_interlocks | |
2118 | && (prev_prev_insn.insn_mo->pinfo | |
2119 | & INSN_LOAD_MEMORY_DELAY))) | |
2120 | && insn_uses_reg (ip, | |
2121 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2122 | & OP_MASK_RT), | |
2123 | MIPS_GR_REG)) | |
2124 | /* If one instruction sets a condition code and the | |
2125 | other one uses a condition code, we can not swap. */ | |
2126 | || ((pinfo & INSN_READ_COND_CODE) | |
2127 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2128 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2129 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2130 | /* If the previous instruction uses the PC, we can not | |
2131 | swap. */ | |
2132 | || (mips_opts.mips16 | |
2133 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2134 | /* If the previous instruction was extended, we can not | |
2135 | swap. */ | |
2136 | || (mips_opts.mips16 && prev_insn_extended) | |
2137 | /* If the previous instruction had a fixup in mips16 | |
2138 | mode, we can not swap. This normally means that the | |
2139 | previous instruction was a 4 byte branch anyhow. */ | |
2140 | || (mips_opts.mips16 && prev_insn_fixp) | |
bdaaa2e1 KH |
2141 | /* If the previous instruction is a sync, sync.l, or |
2142 | sync.p, we can not swap. */ | |
f173e82e | 2143 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2144 | { |
2145 | /* We could do even better for unconditional branches to | |
2146 | portions of this object file; we could pick up the | |
2147 | instruction at the destination, put it in the delay | |
2148 | slot, and bump the destination address. */ | |
2149 | emit_nop (); | |
2150 | /* Update the previous insn information. */ | |
2151 | prev_prev_insn = *ip; | |
2152 | prev_insn.insn_mo = &dummy_opcode; | |
2153 | } | |
2154 | else | |
2155 | { | |
2156 | /* It looks like we can actually do the swap. */ | |
2157 | if (! mips_opts.mips16) | |
2158 | { | |
2159 | char *prev_f; | |
2160 | char temp[4]; | |
2161 | ||
2162 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2163 | memcpy (temp, prev_f, 4); | |
2164 | memcpy (prev_f, f, 4); | |
2165 | memcpy (f, temp, 4); | |
2166 | if (prev_insn_fixp) | |
2167 | { | |
2168 | prev_insn_fixp->fx_frag = frag_now; | |
2169 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2170 | } | |
2171 | if (fixp) | |
2172 | { | |
2173 | fixp->fx_frag = prev_insn_frag; | |
2174 | fixp->fx_where = prev_insn_where; | |
2175 | } | |
2176 | } | |
2177 | else | |
2178 | { | |
2179 | char *prev_f; | |
2180 | char temp[2]; | |
2181 | ||
2182 | assert (prev_insn_fixp == NULL); | |
2183 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2184 | memcpy (temp, prev_f, 2); | |
2185 | memcpy (prev_f, f, 2); | |
2186 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
2187 | { | |
2188 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2189 | memcpy (f, temp, 2); | |
2190 | } | |
2191 | else | |
2192 | { | |
2193 | memcpy (f, f + 2, 2); | |
2194 | memcpy (f + 2, temp, 2); | |
2195 | } | |
2196 | if (fixp) | |
2197 | { | |
2198 | fixp->fx_frag = prev_insn_frag; | |
2199 | fixp->fx_where = prev_insn_where; | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | /* Update the previous insn information; leave prev_insn | |
2204 | unchanged. */ | |
2205 | prev_prev_insn = *ip; | |
2206 | } | |
2207 | prev_insn_is_delay_slot = 1; | |
2208 | ||
2209 | /* If that was an unconditional branch, forget the previous | |
2210 | insn information. */ | |
2211 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2212 | { | |
2213 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2214 | prev_insn.insn_mo = &dummy_opcode; | |
2215 | } | |
2216 | ||
2217 | prev_insn_fixp = NULL; | |
2218 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2219 | prev_insn_extended = 0; | |
2220 | } | |
2221 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2222 | { | |
2223 | /* We don't yet optimize a branch likely. What we should do | |
2224 | is look at the target, copy the instruction found there | |
2225 | into the delay slot, and increment the branch to jump to | |
2226 | the next instruction. */ | |
2227 | emit_nop (); | |
2228 | /* Update the previous insn information. */ | |
2229 | prev_prev_insn = *ip; | |
2230 | prev_insn.insn_mo = &dummy_opcode; | |
2231 | prev_insn_fixp = NULL; | |
2232 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2233 | prev_insn_extended = 0; | |
2234 | } | |
2235 | else | |
2236 | { | |
2237 | /* Update the previous insn information. */ | |
2238 | if (nops > 0) | |
2239 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2240 | else | |
2241 | prev_prev_insn = prev_insn; | |
2242 | prev_insn = *ip; | |
2243 | ||
2244 | /* Any time we see a branch, we always fill the delay slot | |
2245 | immediately; since this insn is not a branch, we know it | |
2246 | is not in a delay slot. */ | |
2247 | prev_insn_is_delay_slot = 0; | |
2248 | ||
2249 | prev_insn_fixp = fixp; | |
2250 | prev_insn_reloc_type = reloc_type; | |
2251 | if (mips_opts.mips16) | |
2252 | prev_insn_extended = (ip->use_extend | |
2253 | || reloc_type > BFD_RELOC_UNUSED); | |
2254 | } | |
2255 | ||
2256 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2257 | prev_insn_unreordered = 0; | |
2258 | prev_insn_frag = frag_now; | |
2259 | prev_insn_where = f - frag_now->fr_literal; | |
2260 | prev_insn_valid = 1; | |
2261 | } | |
2262 | else if (place == NULL) | |
2263 | { | |
2264 | /* We need to record a bit of information even when we are not | |
2265 | reordering, in order to determine the base address for mips16 | |
2266 | PC relative relocs. */ | |
2267 | prev_prev_insn = prev_insn; | |
2268 | prev_insn = *ip; | |
2269 | prev_insn_reloc_type = reloc_type; | |
2270 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2271 | prev_insn_unreordered = 1; | |
2272 | } | |
2273 | ||
2274 | /* We just output an insn, so the next one doesn't have a label. */ | |
2275 | mips_clear_insn_labels (); | |
2276 | ||
2277 | /* We must ensure that a fixup associated with an unmatched %hi | |
2278 | reloc does not become a variant frag. Otherwise, the | |
2279 | rearrangement of %hi relocs in frob_file may confuse | |
2280 | tc_gen_reloc. */ | |
2281 | if (unmatched_hi) | |
2282 | { | |
2283 | frag_wane (frag_now); | |
2284 | frag_new (0); | |
2285 | } | |
2286 | } | |
2287 | ||
2288 | /* This function forgets that there was any previous instruction or | |
2289 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2290 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2291 | |
2292 | static void | |
2293 | mips_no_prev_insn (preserve) | |
2294 | int preserve; | |
2295 | { | |
2296 | if (! preserve) | |
2297 | { | |
2298 | prev_insn.insn_mo = &dummy_opcode; | |
2299 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2300 | prev_nop_frag = NULL; | |
2301 | prev_nop_frag_holds = 0; | |
2302 | prev_nop_frag_required = 0; | |
2303 | prev_nop_frag_since = 0; | |
2304 | } | |
2305 | prev_insn_valid = 0; | |
2306 | prev_insn_is_delay_slot = 0; | |
2307 | prev_insn_unreordered = 0; | |
2308 | prev_insn_extended = 0; | |
2309 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2310 | prev_prev_insn_unreordered = 0; | |
2311 | mips_clear_insn_labels (); | |
2312 | } | |
2313 | ||
2314 | /* This function must be called whenever we turn on noreorder or emit | |
2315 | something other than instructions. It inserts any NOPS which might | |
2316 | be needed by the previous instruction, and clears the information | |
2317 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2318 | instructions are to follow. */ |
252b5132 RH |
2319 | |
2320 | static void | |
2321 | mips_emit_delays (insns) | |
2322 | boolean insns; | |
2323 | { | |
2324 | if (! mips_opts.noreorder) | |
2325 | { | |
2326 | int nops; | |
2327 | ||
2328 | nops = 0; | |
2329 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2330 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2331 | && (! cop_interlocks |
2332 | && (prev_insn.insn_mo->pinfo | |
2333 | & (INSN_LOAD_COPROC_DELAY | |
2334 | | INSN_COPROC_MOVE_DELAY | |
2335 | | INSN_WRITE_COND_CODE)))) | |
2336 | || (! hilo_interlocks | |
2337 | && (prev_insn.insn_mo->pinfo | |
2338 | & (INSN_READ_LO | |
2339 | | INSN_READ_HI))) | |
2340 | || (! mips_opts.mips16 | |
2341 | && ! gpr_interlocks | |
bdaaa2e1 | 2342 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2343 | & INSN_LOAD_MEMORY_DELAY)) |
2344 | || (! mips_opts.mips16 | |
e7af610e | 2345 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2346 | && (prev_insn.insn_mo->pinfo |
2347 | & INSN_COPROC_MEMORY_DELAY))) | |
2348 | { | |
beae10d5 | 2349 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2350 | ++nops; |
2351 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2352 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2353 | && (! cop_interlocks |
2354 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2355 | || (! hilo_interlocks | |
2356 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2357 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2358 | ++nops; | |
2359 | ||
2360 | if (prev_insn_unreordered) | |
2361 | nops = 0; | |
2362 | } | |
2363 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2364 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2365 | && (! cop_interlocks |
2366 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2367 | || (! hilo_interlocks | |
2368 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2369 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2370 | { | |
beae10d5 | 2371 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2372 | if (! prev_prev_insn_unreordered) |
2373 | ++nops; | |
2374 | } | |
2375 | ||
2376 | if (nops > 0) | |
2377 | { | |
2378 | struct insn_label_list *l; | |
2379 | ||
2380 | if (insns) | |
2381 | { | |
2382 | /* Record the frag which holds the nop instructions, so | |
2383 | that we can remove them if we don't need them. */ | |
2384 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2385 | prev_nop_frag = frag_now; | |
2386 | prev_nop_frag_holds = nops; | |
2387 | prev_nop_frag_required = 0; | |
2388 | prev_nop_frag_since = 0; | |
2389 | } | |
2390 | ||
2391 | for (; nops > 0; --nops) | |
2392 | emit_nop (); | |
2393 | ||
2394 | if (insns) | |
2395 | { | |
2396 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2397 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2398 | frag_wane (frag_now); |
2399 | frag_new (0); | |
2400 | } | |
2401 | ||
2402 | for (l = insn_labels; l != NULL; l = l->next) | |
2403 | { | |
2404 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 2405 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
2406 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
2407 | /* mips16 text labels are stored as odd. */ | |
2408 | if (mips_opts.mips16) | |
49309057 | 2409 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
2410 | } |
2411 | } | |
2412 | } | |
2413 | ||
2414 | /* Mark instruction labels in mips16 mode. */ | |
2415 | if (mips_opts.mips16 && insns) | |
2416 | mips16_mark_labels (); | |
2417 | ||
2418 | mips_no_prev_insn (insns); | |
2419 | } | |
2420 | ||
2421 | /* Build an instruction created by a macro expansion. This is passed | |
2422 | a pointer to the count of instructions created so far, an | |
2423 | expression, the name of the instruction to build, an operand format | |
2424 | string, and corresponding arguments. */ | |
2425 | ||
2426 | #ifdef USE_STDARG | |
2427 | static void | |
2428 | macro_build (char *place, | |
2429 | int *counter, | |
2430 | expressionS * ep, | |
2431 | const char *name, | |
2432 | const char *fmt, | |
2433 | ...) | |
2434 | #else | |
2435 | static void | |
2436 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2437 | char *place; | |
2438 | int *counter; | |
2439 | expressionS *ep; | |
2440 | const char *name; | |
2441 | const char *fmt; | |
2442 | va_dcl | |
2443 | #endif | |
2444 | { | |
2445 | struct mips_cl_insn insn; | |
2446 | bfd_reloc_code_real_type r; | |
2447 | va_list args; | |
252b5132 RH |
2448 | |
2449 | #ifdef USE_STDARG | |
2450 | va_start (args, fmt); | |
2451 | #else | |
2452 | va_start (args); | |
2453 | #endif | |
2454 | ||
2455 | /* | |
2456 | * If the macro is about to expand into a second instruction, | |
2457 | * print a warning if needed. We need to pass ip as a parameter | |
2458 | * to generate a better warning message here... | |
2459 | */ | |
2460 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2461 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2462 | ||
2463 | if (place == NULL) | |
2464 | *counter += 1; /* bump instruction counter */ | |
2465 | ||
2466 | if (mips_opts.mips16) | |
2467 | { | |
2468 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2469 | va_end (args); | |
2470 | return; | |
2471 | } | |
2472 | ||
2473 | r = BFD_RELOC_UNUSED; | |
2474 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2475 | assert (insn.insn_mo); | |
2476 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2477 | ||
2478 | /* Search until we get a match for NAME. */ | |
2479 | while (1) | |
2480 | { | |
252b5132 RH |
2481 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2482 | && insn.insn_mo->pinfo != INSN_MACRO | |
bdaaa2e1 | 2483 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu, |
c97ef257 | 2484 | mips_gp32) |
156c2f8b | 2485 | && (mips_cpu != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2486 | break; |
2487 | ||
2488 | ++insn.insn_mo; | |
2489 | assert (insn.insn_mo->name); | |
2490 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2491 | } | |
2492 | ||
2493 | insn.insn_opcode = insn.insn_mo->match; | |
2494 | for (;;) | |
2495 | { | |
2496 | switch (*fmt++) | |
2497 | { | |
2498 | case '\0': | |
2499 | break; | |
2500 | ||
2501 | case ',': | |
2502 | case '(': | |
2503 | case ')': | |
2504 | continue; | |
2505 | ||
2506 | case 't': | |
2507 | case 'w': | |
2508 | case 'E': | |
2509 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2510 | continue; | |
2511 | ||
2512 | case 'c': | |
2513 | case 'T': | |
2514 | case 'W': | |
2515 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2516 | continue; | |
2517 | ||
2518 | case 'd': | |
2519 | case 'G': | |
2520 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2521 | continue; | |
2522 | ||
4372b673 NC |
2523 | case 'U': |
2524 | { | |
2525 | int tmp = va_arg (args, int); | |
2526 | ||
2527 | insn.insn_opcode |= tmp << 16; | |
2528 | insn.insn_opcode |= tmp << 11; | |
beae10d5 | 2529 | continue; |
4372b673 NC |
2530 | } |
2531 | ||
252b5132 RH |
2532 | case 'V': |
2533 | case 'S': | |
2534 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2535 | continue; | |
2536 | ||
2537 | case 'z': | |
2538 | continue; | |
2539 | ||
2540 | case '<': | |
2541 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2542 | continue; | |
2543 | ||
2544 | case 'D': | |
2545 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2546 | continue; | |
2547 | ||
2548 | case 'B': | |
2549 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2550 | continue; | |
2551 | ||
4372b673 NC |
2552 | case 'J': |
2553 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2554 | continue; | |
2555 | ||
252b5132 RH |
2556 | case 'q': |
2557 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2558 | continue; | |
2559 | ||
2560 | case 'b': | |
2561 | case 's': | |
2562 | case 'r': | |
2563 | case 'v': | |
2564 | insn.insn_opcode |= va_arg (args, int) << 21; | |
2565 | continue; | |
2566 | ||
2567 | case 'i': | |
2568 | case 'j': | |
2569 | case 'o': | |
2570 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2571 | assert (r == BFD_RELOC_MIPS_GPREL | |
2572 | || r == BFD_RELOC_MIPS_LITERAL | |
2573 | || r == BFD_RELOC_LO16 | |
2574 | || r == BFD_RELOC_MIPS_GOT16 | |
2575 | || r == BFD_RELOC_MIPS_CALL16 | |
2576 | || r == BFD_RELOC_MIPS_GOT_LO16 | |
2577 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
2578 | || (ep->X_op == O_subtract | |
252b5132 RH |
2579 | && r == BFD_RELOC_PCREL_LO16)); |
2580 | continue; | |
2581 | ||
2582 | case 'u': | |
2583 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2584 | assert (ep != NULL | |
2585 | && (ep->X_op == O_constant | |
2586 | || (ep->X_op == O_symbol | |
2587 | && (r == BFD_RELOC_HI16_S | |
2588 | || r == BFD_RELOC_HI16 | |
2589 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2590 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
2591 | || (ep->X_op == O_subtract | |
252b5132 RH |
2592 | && r == BFD_RELOC_PCREL_HI16_S))); |
2593 | if (ep->X_op == O_constant) | |
2594 | { | |
2595 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2596 | ep = NULL; | |
2597 | r = BFD_RELOC_UNUSED; | |
2598 | } | |
2599 | continue; | |
2600 | ||
2601 | case 'p': | |
2602 | assert (ep != NULL); | |
2603 | /* | |
2604 | * This allows macro() to pass an immediate expression for | |
2605 | * creating short branches without creating a symbol. | |
2606 | * Note that the expression still might come from the assembly | |
2607 | * input, in which case the value is not checked for range nor | |
2608 | * is a relocation entry generated (yuck). | |
2609 | */ | |
2610 | if (ep->X_op == O_constant) | |
2611 | { | |
2612 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2613 | ep = NULL; | |
2614 | } | |
2615 | else | |
2616 | r = BFD_RELOC_16_PCREL_S2; | |
2617 | continue; | |
2618 | ||
2619 | case 'a': | |
2620 | assert (ep != NULL); | |
2621 | r = BFD_RELOC_MIPS_JMP; | |
2622 | continue; | |
2623 | ||
2624 | case 'C': | |
2625 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2626 | continue; | |
2627 | ||
2628 | default: | |
2629 | internalError (); | |
2630 | } | |
2631 | break; | |
2632 | } | |
2633 | va_end (args); | |
2634 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2635 | ||
2636 | append_insn (place, &insn, ep, r, false); | |
2637 | } | |
2638 | ||
2639 | static void | |
2640 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2641 | char *place; | |
43841e91 | 2642 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2643 | expressionS *ep; |
2644 | const char *name; | |
2645 | const char *fmt; | |
2646 | va_list args; | |
2647 | { | |
2648 | struct mips_cl_insn insn; | |
2649 | bfd_reloc_code_real_type r; | |
2650 | ||
2651 | r = BFD_RELOC_UNUSED; | |
2652 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2653 | assert (insn.insn_mo); | |
2654 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2655 | ||
2656 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2657 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2658 | { | |
2659 | ++insn.insn_mo; | |
2660 | assert (insn.insn_mo->name); | |
2661 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2662 | } | |
2663 | ||
2664 | insn.insn_opcode = insn.insn_mo->match; | |
2665 | insn.use_extend = false; | |
2666 | ||
2667 | for (;;) | |
2668 | { | |
2669 | int c; | |
2670 | ||
2671 | c = *fmt++; | |
2672 | switch (c) | |
2673 | { | |
2674 | case '\0': | |
2675 | break; | |
2676 | ||
2677 | case ',': | |
2678 | case '(': | |
2679 | case ')': | |
2680 | continue; | |
2681 | ||
2682 | case 'y': | |
2683 | case 'w': | |
2684 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2685 | continue; | |
2686 | ||
2687 | case 'x': | |
2688 | case 'v': | |
2689 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2690 | continue; | |
2691 | ||
2692 | case 'z': | |
2693 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2694 | continue; | |
2695 | ||
2696 | case 'Z': | |
2697 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2698 | continue; | |
2699 | ||
2700 | case '0': | |
2701 | case 'S': | |
2702 | case 'P': | |
2703 | case 'R': | |
2704 | continue; | |
2705 | ||
2706 | case 'X': | |
2707 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2708 | continue; | |
2709 | ||
2710 | case 'Y': | |
2711 | { | |
2712 | int regno; | |
2713 | ||
2714 | regno = va_arg (args, int); | |
2715 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2716 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2717 | } | |
2718 | continue; | |
2719 | ||
2720 | case '<': | |
2721 | case '>': | |
2722 | case '4': | |
2723 | case '5': | |
2724 | case 'H': | |
2725 | case 'W': | |
2726 | case 'D': | |
2727 | case 'j': | |
2728 | case '8': | |
2729 | case 'V': | |
2730 | case 'C': | |
2731 | case 'U': | |
2732 | case 'k': | |
2733 | case 'K': | |
2734 | case 'p': | |
2735 | case 'q': | |
2736 | { | |
2737 | assert (ep != NULL); | |
2738 | ||
2739 | if (ep->X_op != O_constant) | |
2740 | r = BFD_RELOC_UNUSED + c; | |
2741 | else | |
2742 | { | |
2743 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
2744 | false, false, &insn.insn_opcode, | |
2745 | &insn.use_extend, &insn.extend); | |
2746 | ep = NULL; | |
2747 | r = BFD_RELOC_UNUSED; | |
2748 | } | |
2749 | } | |
2750 | continue; | |
2751 | ||
2752 | case '6': | |
2753 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2754 | continue; | |
2755 | } | |
2756 | ||
2757 | break; | |
2758 | } | |
2759 | ||
2760 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2761 | ||
2762 | append_insn (place, &insn, ep, r, false); | |
2763 | } | |
2764 | ||
2765 | /* | |
2766 | * Generate a "lui" instruction. | |
2767 | */ | |
2768 | static void | |
2769 | macro_build_lui (place, counter, ep, regnum) | |
2770 | char *place; | |
2771 | int *counter; | |
2772 | expressionS *ep; | |
2773 | int regnum; | |
2774 | { | |
2775 | expressionS high_expr; | |
2776 | struct mips_cl_insn insn; | |
2777 | bfd_reloc_code_real_type r; | |
2778 | CONST char *name = "lui"; | |
2779 | CONST char *fmt = "t,u"; | |
2780 | ||
2781 | assert (! mips_opts.mips16); | |
2782 | ||
2783 | if (place == NULL) | |
2784 | high_expr = *ep; | |
2785 | else | |
2786 | { | |
2787 | high_expr.X_op = O_constant; | |
2788 | high_expr.X_add_number = ep->X_add_number; | |
2789 | } | |
2790 | ||
2791 | if (high_expr.X_op == O_constant) | |
2792 | { | |
2793 | /* we can compute the instruction now without a relocation entry */ | |
2794 | if (high_expr.X_add_number & 0x8000) | |
2795 | high_expr.X_add_number += 0x10000; | |
2796 | high_expr.X_add_number = | |
2797 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2798 | r = BFD_RELOC_UNUSED; | |
2799 | } | |
2800 | else | |
2801 | { | |
2802 | assert (ep->X_op == O_symbol); | |
2803 | /* _gp_disp is a special case, used from s_cpload. */ | |
2804 | assert (mips_pic == NO_PIC | |
2805 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
2806 | r = BFD_RELOC_HI16_S; | |
2807 | } | |
2808 | ||
2809 | /* | |
2810 | * If the macro is about to expand into a second instruction, | |
2811 | * print a warning if needed. We need to pass ip as a parameter | |
2812 | * to generate a better warning message here... | |
2813 | */ | |
2814 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2815 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2816 | ||
2817 | if (place == NULL) | |
2818 | *counter += 1; /* bump instruction counter */ | |
2819 | ||
2820 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2821 | assert (insn.insn_mo); | |
2822 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2823 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2824 | ||
2825 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
2826 | if (r == BFD_RELOC_UNUSED) | |
2827 | { | |
2828 | insn.insn_opcode |= high_expr.X_add_number; | |
2829 | append_insn (place, &insn, NULL, r, false); | |
2830 | } | |
2831 | else | |
2832 | append_insn (place, &insn, &high_expr, r, false); | |
2833 | } | |
2834 | ||
2835 | /* set_at() | |
2836 | * Generates code to set the $at register to true (one) | |
2837 | * if reg is less than the immediate expression. | |
2838 | */ | |
2839 | static void | |
2840 | set_at (counter, reg, unsignedp) | |
2841 | int *counter; | |
2842 | int reg; | |
2843 | int unsignedp; | |
2844 | { | |
2845 | if (imm_expr.X_op == O_constant | |
2846 | && imm_expr.X_add_number >= -0x8000 | |
2847 | && imm_expr.X_add_number < 0x8000) | |
2848 | macro_build ((char *) NULL, counter, &imm_expr, | |
2849 | unsignedp ? "sltiu" : "slti", | |
2850 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
2851 | else | |
2852 | { | |
2853 | load_register (counter, AT, &imm_expr, 0); | |
2854 | macro_build ((char *) NULL, counter, NULL, | |
2855 | unsignedp ? "sltu" : "slt", | |
2856 | "d,v,t", AT, reg, AT); | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | /* Warn if an expression is not a constant. */ | |
2861 | ||
2862 | static void | |
2863 | check_absolute_expr (ip, ex) | |
2864 | struct mips_cl_insn *ip; | |
2865 | expressionS *ex; | |
2866 | { | |
2867 | if (ex->X_op == O_big) | |
2868 | as_bad (_("unsupported large constant")); | |
2869 | else if (ex->X_op != O_constant) | |
2870 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
2871 | } | |
2872 | ||
2873 | /* Count the leading zeroes by performing a binary chop. This is a | |
2874 | bulky bit of source, but performance is a LOT better for the | |
2875 | majority of values than a simple loop to count the bits: | |
2876 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2877 | if ((v) & (1 << (31 - lcnt))) | |
2878 | break; | |
2879 | However it is not code size friendly, and the gain will drop a bit | |
2880 | on certain cached systems. | |
2881 | */ | |
2882 | #define COUNT_TOP_ZEROES(v) \ | |
2883 | (((v) & ~0xffff) == 0 \ | |
2884 | ? ((v) & ~0xff) == 0 \ | |
2885 | ? ((v) & ~0xf) == 0 \ | |
2886 | ? ((v) & ~0x3) == 0 \ | |
2887 | ? ((v) & ~0x1) == 0 \ | |
2888 | ? !(v) \ | |
2889 | ? 32 \ | |
2890 | : 31 \ | |
2891 | : 30 \ | |
2892 | : ((v) & ~0x7) == 0 \ | |
2893 | ? 29 \ | |
2894 | : 28 \ | |
2895 | : ((v) & ~0x3f) == 0 \ | |
2896 | ? ((v) & ~0x1f) == 0 \ | |
2897 | ? 27 \ | |
2898 | : 26 \ | |
2899 | : ((v) & ~0x7f) == 0 \ | |
2900 | ? 25 \ | |
2901 | : 24 \ | |
2902 | : ((v) & ~0xfff) == 0 \ | |
2903 | ? ((v) & ~0x3ff) == 0 \ | |
2904 | ? ((v) & ~0x1ff) == 0 \ | |
2905 | ? 23 \ | |
2906 | : 22 \ | |
2907 | : ((v) & ~0x7ff) == 0 \ | |
2908 | ? 21 \ | |
2909 | : 20 \ | |
2910 | : ((v) & ~0x3fff) == 0 \ | |
2911 | ? ((v) & ~0x1fff) == 0 \ | |
2912 | ? 19 \ | |
2913 | : 18 \ | |
2914 | : ((v) & ~0x7fff) == 0 \ | |
2915 | ? 17 \ | |
2916 | : 16 \ | |
2917 | : ((v) & ~0xffffff) == 0 \ | |
2918 | ? ((v) & ~0xfffff) == 0 \ | |
2919 | ? ((v) & ~0x3ffff) == 0 \ | |
2920 | ? ((v) & ~0x1ffff) == 0 \ | |
2921 | ? 15 \ | |
2922 | : 14 \ | |
2923 | : ((v) & ~0x7ffff) == 0 \ | |
2924 | ? 13 \ | |
2925 | : 12 \ | |
2926 | : ((v) & ~0x3fffff) == 0 \ | |
2927 | ? ((v) & ~0x1fffff) == 0 \ | |
2928 | ? 11 \ | |
2929 | : 10 \ | |
2930 | : ((v) & ~0x7fffff) == 0 \ | |
2931 | ? 9 \ | |
2932 | : 8 \ | |
2933 | : ((v) & ~0xfffffff) == 0 \ | |
2934 | ? ((v) & ~0x3ffffff) == 0 \ | |
2935 | ? ((v) & ~0x1ffffff) == 0 \ | |
2936 | ? 7 \ | |
2937 | : 6 \ | |
2938 | : ((v) & ~0x7ffffff) == 0 \ | |
2939 | ? 5 \ | |
2940 | : 4 \ | |
2941 | : ((v) & ~0x3fffffff) == 0 \ | |
2942 | ? ((v) & ~0x1fffffff) == 0 \ | |
2943 | ? 3 \ | |
2944 | : 2 \ | |
2945 | : ((v) & ~0x7fffffff) == 0 \ | |
2946 | ? 1 \ | |
2947 | : 0) | |
2948 | ||
2949 | /* load_register() | |
2950 | * This routine generates the least number of instructions neccessary to load | |
2951 | * an absolute expression value into a register. | |
2952 | */ | |
2953 | static void | |
2954 | load_register (counter, reg, ep, dbl) | |
2955 | int *counter; | |
2956 | int reg; | |
2957 | expressionS *ep; | |
2958 | int dbl; | |
2959 | { | |
2960 | int freg; | |
2961 | expressionS hi32, lo32; | |
2962 | ||
2963 | if (ep->X_op != O_big) | |
2964 | { | |
2965 | assert (ep->X_op == O_constant); | |
2966 | if (ep->X_add_number < 0x8000 | |
2967 | && (ep->X_add_number >= 0 | |
2968 | || (ep->X_add_number >= -0x8000 | |
2969 | && (! dbl | |
2970 | || ! ep->X_unsigned | |
2971 | || sizeof (ep->X_add_number) > 4)))) | |
2972 | { | |
2973 | /* We can handle 16 bit signed values with an addiu to | |
2974 | $zero. No need to ever use daddiu here, since $zero and | |
2975 | the result are always correct in 32 bit mode. */ | |
2976 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2977 | (int) BFD_RELOC_LO16); | |
2978 | return; | |
2979 | } | |
2980 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2981 | { | |
2982 | /* We can handle 16 bit unsigned values with an ori to | |
2983 | $zero. */ | |
2984 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2985 | (int) BFD_RELOC_LO16); | |
2986 | return; | |
2987 | } | |
2988 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
2989 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2990 | == ~ (offsetT) 0x7fffffff)) | |
2991 | && (! dbl | |
2992 | || ! ep->X_unsigned | |
2993 | || sizeof (ep->X_add_number) > 4 | |
2994 | || (ep->X_add_number & 0x80000000) == 0)) | |
9ce8a5dd | 2995 | || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl) |
252b5132 | 2996 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
9ce8a5dd | 2997 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
2998 | && ! dbl |
2999 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3000 | == ~ (offsetT) 0xffffffff))) | |
3001 | { | |
3002 | /* 32 bit values require an lui. */ | |
3003 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3004 | (int) BFD_RELOC_HI16); | |
3005 | if ((ep->X_add_number & 0xffff) != 0) | |
3006 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3007 | (int) BFD_RELOC_LO16); | |
3008 | return; | |
3009 | } | |
3010 | } | |
3011 | ||
3012 | /* The value is larger than 32 bits. */ | |
3013 | ||
9ce8a5dd | 3014 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3015 | { |
3016 | as_bad (_("Number larger than 32 bits")); | |
3017 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3018 | (int) BFD_RELOC_LO16); | |
3019 | return; | |
3020 | } | |
3021 | ||
3022 | if (ep->X_op != O_big) | |
3023 | { | |
3024 | hi32 = *ep; | |
3025 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3026 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3027 | hi32.X_add_number &= 0xffffffff; | |
3028 | lo32 = *ep; | |
3029 | lo32.X_add_number &= 0xffffffff; | |
3030 | } | |
3031 | else | |
3032 | { | |
3033 | assert (ep->X_add_number > 2); | |
3034 | if (ep->X_add_number == 3) | |
3035 | generic_bignum[3] = 0; | |
3036 | else if (ep->X_add_number > 4) | |
3037 | as_bad (_("Number larger than 64 bits")); | |
3038 | lo32.X_op = O_constant; | |
3039 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3040 | hi32.X_op = O_constant; | |
3041 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3042 | } | |
3043 | ||
3044 | if (hi32.X_add_number == 0) | |
3045 | freg = 0; | |
3046 | else | |
3047 | { | |
3048 | int shift, bit; | |
3049 | unsigned long hi, lo; | |
3050 | ||
3051 | if (hi32.X_add_number == 0xffffffff) | |
beae10d5 KH |
3052 | { |
3053 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3054 | { | |
3055 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3056 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3057 | return; |
3058 | } | |
3059 | if (lo32.X_add_number & 0x80000000) | |
3060 | { | |
3061 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3062 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3063 | if (lo32.X_add_number & 0xffff) |
3064 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3065 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3066 | return; |
3067 | } | |
3068 | } | |
252b5132 RH |
3069 | |
3070 | /* Check for 16bit shifted constant. We know that hi32 is | |
3071 | non-zero, so start the mask on the first bit of the hi32 | |
3072 | value. */ | |
3073 | shift = 17; | |
3074 | do | |
beae10d5 KH |
3075 | { |
3076 | unsigned long himask, lomask; | |
3077 | ||
3078 | if (shift < 32) | |
3079 | { | |
3080 | himask = 0xffff >> (32 - shift); | |
3081 | lomask = (0xffff << shift) & 0xffffffff; | |
3082 | } | |
3083 | else | |
3084 | { | |
3085 | himask = 0xffff << (shift - 32); | |
3086 | lomask = 0; | |
3087 | } | |
3088 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3089 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3090 | { | |
3091 | expressionS tmp; | |
3092 | ||
3093 | tmp.X_op = O_constant; | |
3094 | if (shift < 32) | |
3095 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3096 | | (lo32.X_add_number >> shift)); | |
3097 | else | |
3098 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3099 | macro_build ((char *) NULL, counter, &tmp, | |
3100 | "ori", "t,r,i", reg, 0, | |
3101 | (int) BFD_RELOC_LO16); | |
3102 | macro_build ((char *) NULL, counter, NULL, | |
3103 | (shift >= 32) ? "dsll32" : "dsll", | |
3104 | "d,w,<", reg, reg, | |
3105 | (shift >= 32) ? shift - 32 : shift); | |
3106 | return; | |
3107 | } | |
3108 | shift++; | |
3109 | } | |
3110 | while (shift <= (64 - 16)); | |
252b5132 RH |
3111 | |
3112 | /* Find the bit number of the lowest one bit, and store the | |
3113 | shifted value in hi/lo. */ | |
3114 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3115 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3116 | if (lo != 0) | |
3117 | { | |
3118 | bit = 0; | |
3119 | while ((lo & 1) == 0) | |
3120 | { | |
3121 | lo >>= 1; | |
3122 | ++bit; | |
3123 | } | |
3124 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3125 | hi >>= bit; | |
3126 | } | |
3127 | else | |
3128 | { | |
3129 | bit = 32; | |
3130 | while ((hi & 1) == 0) | |
3131 | { | |
3132 | hi >>= 1; | |
3133 | ++bit; | |
3134 | } | |
3135 | lo = hi; | |
3136 | hi = 0; | |
3137 | } | |
3138 | ||
3139 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3140 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3141 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3142 | { |
3143 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3144 | if (shift != 0) |
beae10d5 | 3145 | { |
252b5132 RH |
3146 | expressionS tmp; |
3147 | ||
3148 | /* This instruction will set the register to be all | |
3149 | ones. */ | |
beae10d5 KH |
3150 | tmp.X_op = O_constant; |
3151 | tmp.X_add_number = (offsetT) -1; | |
3152 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3153 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3154 | if (bit != 0) |
3155 | { | |
3156 | bit += shift; | |
3157 | macro_build ((char *) NULL, counter, NULL, | |
3158 | (bit >= 32) ? "dsll32" : "dsll", | |
3159 | "d,w,<", reg, reg, | |
3160 | (bit >= 32) ? bit - 32 : bit); | |
3161 | } | |
3162 | macro_build ((char *) NULL, counter, NULL, | |
252b5132 | 3163 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3164 | "d,w,<", reg, reg, |
252b5132 | 3165 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3166 | return; |
3167 | } | |
3168 | } | |
252b5132 RH |
3169 | |
3170 | /* Sign extend hi32 before calling load_register, because we can | |
3171 | generally get better code when we load a sign extended value. */ | |
3172 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3173 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3174 | load_register (counter, reg, &hi32, 0); |
3175 | freg = reg; | |
3176 | } | |
3177 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3178 | { | |
3179 | if (freg != 0) | |
3180 | { | |
3181 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3182 | freg, 0); | |
3183 | freg = reg; | |
3184 | } | |
3185 | } | |
3186 | else | |
3187 | { | |
3188 | expressionS mid16; | |
3189 | ||
3190 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
beae10d5 | 3191 | { |
252b5132 RH |
3192 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3193 | (int) BFD_RELOC_HI16); | |
beae10d5 KH |
3194 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, |
3195 | reg, 0); | |
3196 | return; | |
3197 | } | |
252b5132 RH |
3198 | |
3199 | if (freg != 0) | |
3200 | { | |
3201 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3202 | freg, 16); | |
3203 | freg = reg; | |
3204 | } | |
3205 | mid16 = lo32; | |
3206 | mid16.X_add_number >>= 16; | |
3207 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3208 | freg, (int) BFD_RELOC_LO16); | |
3209 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3210 | reg, 16); | |
3211 | freg = reg; | |
3212 | } | |
3213 | if ((lo32.X_add_number & 0xffff) != 0) | |
3214 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3215 | (int) BFD_RELOC_LO16); | |
3216 | } | |
3217 | ||
3218 | /* Load an address into a register. */ | |
3219 | ||
3220 | static void | |
3221 | load_address (counter, reg, ep) | |
3222 | int *counter; | |
3223 | int reg; | |
3224 | expressionS *ep; | |
3225 | { | |
3226 | char *p; | |
3227 | ||
3228 | if (ep->X_op != O_constant | |
3229 | && ep->X_op != O_symbol) | |
3230 | { | |
3231 | as_bad (_("expression too complex")); | |
3232 | ep->X_op = O_constant; | |
3233 | } | |
3234 | ||
3235 | if (ep->X_op == O_constant) | |
3236 | { | |
3237 | load_register (counter, reg, ep, 0); | |
3238 | return; | |
3239 | } | |
3240 | ||
3241 | if (mips_pic == NO_PIC) | |
3242 | { | |
3243 | /* If this is a reference to a GP relative symbol, we want | |
3244 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3245 | Otherwise we want | |
3246 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3247 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3248 | If we have an addend, we always use the latter form. */ | |
3249 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET | |
beae10d5 | 3250 | || nopic_need_relax (ep->X_add_symbol, 1)) |
252b5132 RH |
3251 | p = NULL; |
3252 | else | |
3253 | { | |
3254 | frag_grow (20); | |
3255 | macro_build ((char *) NULL, counter, ep, | |
3256 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3257 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3258 | ? "addiu" : "daddiu"), |
3259 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3260 | p = frag_var (rs_machine_dependent, 8, 0, | |
3261 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3262 | mips_opts.warn_about_macros), | |
3263 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3264 | } | |
3265 | macro_build_lui (p, counter, ep, reg); | |
3266 | if (p != NULL) | |
3267 | p += 4; | |
3268 | macro_build (p, counter, ep, | |
3269 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3270 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3271 | ? "addiu" : "daddiu"), |
3272 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3273 | } | |
3274 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3275 | { | |
3276 | expressionS ex; | |
3277 | ||
3278 | /* If this is a reference to an external symbol, we want | |
3279 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3280 | Otherwise we want | |
3281 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3282 | nop | |
3283 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3284 | If there is a constant, it must be added in after. */ | |
3285 | ex.X_add_number = ep->X_add_number; | |
3286 | ep->X_add_number = 0; | |
3287 | frag_grow (20); | |
3288 | macro_build ((char *) NULL, counter, ep, | |
3289 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3290 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3291 | ? "lw" : "ld"), |
3292 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3293 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3294 | p = frag_var (rs_machine_dependent, 4, 0, | |
3295 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3296 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3297 | macro_build (p, counter, ep, | |
3298 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3299 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3300 | ? "addiu" : "daddiu"), |
3301 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3302 | if (ex.X_add_number != 0) | |
3303 | { | |
3304 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3305 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3306 | ex.X_op = O_constant; | |
3307 | macro_build ((char *) NULL, counter, &ex, | |
3308 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3309 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3310 | ? "addiu" : "daddiu"), |
3311 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3312 | } | |
3313 | } | |
3314 | else if (mips_pic == SVR4_PIC) | |
3315 | { | |
3316 | expressionS ex; | |
3317 | int off; | |
3318 | ||
3319 | /* This is the large GOT case. If this is a reference to an | |
3320 | external symbol, we want | |
3321 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3322 | addu $reg,$reg,$gp | |
3323 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3324 | Otherwise, for a reference to a local symbol, we want | |
3325 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3326 | nop | |
3327 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3328 | If there is a constant, it must be added in after. */ | |
3329 | ex.X_add_number = ep->X_add_number; | |
3330 | ep->X_add_number = 0; | |
3331 | if (reg_needs_delay (GP)) | |
3332 | off = 4; | |
3333 | else | |
3334 | off = 0; | |
3335 | frag_grow (32); | |
3336 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3337 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3338 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3339 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3340 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3341 | ? "addu" : "daddu"), |
3342 | "d,v,t", reg, reg, GP); | |
3343 | macro_build ((char *) NULL, counter, ep, | |
3344 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3345 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3346 | ? "lw" : "ld"), |
3347 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3348 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3349 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3350 | mips_opts.warn_about_macros), | |
3351 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3352 | if (off > 0) | |
3353 | { | |
3354 | /* We need a nop before loading from $gp. This special | |
3355 | check is required because the lui which starts the main | |
3356 | instruction stream does not refer to $gp, and so will not | |
3357 | insert the nop which may be required. */ | |
3358 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3359 | p += 4; | |
3360 | } | |
3361 | macro_build (p, counter, ep, | |
3362 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3363 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3364 | ? "lw" : "ld"), |
3365 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3366 | p += 4; | |
3367 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3368 | p += 4; | |
3369 | macro_build (p, counter, ep, | |
3370 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3371 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3372 | ? "addiu" : "daddiu"), |
3373 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3374 | if (ex.X_add_number != 0) | |
3375 | { | |
3376 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3377 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3378 | ex.X_op = O_constant; | |
3379 | macro_build ((char *) NULL, counter, &ex, | |
3380 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3381 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3382 | ? "addiu" : "daddiu"), |
3383 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3384 | } | |
3385 | } | |
3386 | else if (mips_pic == EMBEDDED_PIC) | |
3387 | { | |
3388 | /* We always do | |
3389 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3390 | */ | |
3391 | macro_build ((char *) NULL, counter, ep, | |
3392 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3393 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3394 | ? "addiu" : "daddiu"), |
3395 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3396 | } | |
3397 | else | |
3398 | abort (); | |
3399 | } | |
3400 | ||
3401 | /* | |
3402 | * Build macros | |
3403 | * This routine implements the seemingly endless macro or synthesized | |
3404 | * instructions and addressing modes in the mips assembly language. Many | |
3405 | * of these macros are simple and are similar to each other. These could | |
3406 | * probably be handled by some kind of table or grammer aproach instead of | |
3407 | * this verbose method. Others are not simple macros but are more like | |
3408 | * optimizing code generation. | |
3409 | * One interesting optimization is when several store macros appear | |
3410 | * consecutivly that would load AT with the upper half of the same address. | |
3411 | * The ensuing load upper instructions are ommited. This implies some kind | |
3412 | * of global optimization. We currently only optimize within a single macro. | |
3413 | * For many of the load and store macros if the address is specified as a | |
3414 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3415 | * first load register 'at' with zero and use it as the base register. The | |
3416 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3417 | * we're missing. | |
3418 | */ | |
3419 | static void | |
3420 | macro (ip) | |
3421 | struct mips_cl_insn *ip; | |
3422 | { | |
3423 | register int treg, sreg, dreg, breg; | |
3424 | int tempreg; | |
3425 | int mask; | |
3426 | int icnt = 0; | |
43841e91 | 3427 | int used_at = 0; |
252b5132 RH |
3428 | expressionS expr1; |
3429 | const char *s; | |
3430 | const char *s2; | |
3431 | const char *fmt; | |
3432 | int likely = 0; | |
3433 | int dbl = 0; | |
3434 | int coproc = 0; | |
3435 | int lr = 0; | |
3436 | int imm = 0; | |
3437 | offsetT maxnum; | |
3438 | int off; | |
3439 | bfd_reloc_code_real_type r; | |
3440 | char *p; | |
3441 | int hold_mips_optimize; | |
3442 | ||
3443 | assert (! mips_opts.mips16); | |
3444 | ||
3445 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3446 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3447 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3448 | mask = ip->insn_mo->mask; | |
3449 | ||
3450 | expr1.X_op = O_constant; | |
3451 | expr1.X_op_symbol = NULL; | |
3452 | expr1.X_add_symbol = NULL; | |
3453 | expr1.X_add_number = 1; | |
3454 | ||
3455 | switch (mask) | |
3456 | { | |
3457 | case M_DABS: | |
3458 | dbl = 1; | |
3459 | case M_ABS: | |
3460 | /* bgez $a0,.+12 | |
3461 | move v0,$a0 | |
3462 | sub v0,$zero,$a0 | |
3463 | */ | |
3464 | ||
3465 | mips_emit_delays (true); | |
3466 | ++mips_opts.noreorder; | |
3467 | mips_any_noreorder = 1; | |
3468 | ||
3469 | expr1.X_add_number = 8; | |
3470 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3471 | if (dreg == sreg) | |
3472 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3473 | else | |
3474 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); | |
3475 | macro_build ((char *) NULL, &icnt, NULL, | |
3476 | dbl ? "dsub" : "sub", | |
3477 | "d,v,t", dreg, 0, sreg); | |
3478 | ||
3479 | --mips_opts.noreorder; | |
3480 | return; | |
3481 | ||
3482 | case M_ADD_I: | |
3483 | s = "addi"; | |
3484 | s2 = "add"; | |
3485 | goto do_addi; | |
3486 | case M_ADDU_I: | |
3487 | s = "addiu"; | |
3488 | s2 = "addu"; | |
3489 | goto do_addi; | |
3490 | case M_DADD_I: | |
3491 | dbl = 1; | |
3492 | s = "daddi"; | |
3493 | s2 = "dadd"; | |
3494 | goto do_addi; | |
3495 | case M_DADDU_I: | |
3496 | dbl = 1; | |
3497 | s = "daddiu"; | |
3498 | s2 = "daddu"; | |
3499 | do_addi: | |
3500 | if (imm_expr.X_op == O_constant | |
3501 | && imm_expr.X_add_number >= -0x8000 | |
3502 | && imm_expr.X_add_number < 0x8000) | |
3503 | { | |
3504 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3505 | (int) BFD_RELOC_LO16); | |
3506 | return; | |
3507 | } | |
3508 | load_register (&icnt, AT, &imm_expr, dbl); | |
3509 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3510 | break; | |
3511 | ||
3512 | case M_AND_I: | |
3513 | s = "andi"; | |
3514 | s2 = "and"; | |
3515 | goto do_bit; | |
3516 | case M_OR_I: | |
3517 | s = "ori"; | |
3518 | s2 = "or"; | |
3519 | goto do_bit; | |
3520 | case M_NOR_I: | |
3521 | s = ""; | |
3522 | s2 = "nor"; | |
3523 | goto do_bit; | |
3524 | case M_XOR_I: | |
3525 | s = "xori"; | |
3526 | s2 = "xor"; | |
3527 | do_bit: | |
3528 | if (imm_expr.X_op == O_constant | |
3529 | && imm_expr.X_add_number >= 0 | |
3530 | && imm_expr.X_add_number < 0x10000) | |
3531 | { | |
3532 | if (mask != M_NOR_I) | |
3533 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3534 | sreg, (int) BFD_RELOC_LO16); | |
3535 | else | |
3536 | { | |
3537 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3538 | treg, sreg, (int) BFD_RELOC_LO16); | |
3539 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3540 | treg, treg, 0); | |
3541 | } | |
3542 | return; | |
3543 | } | |
3544 | ||
3545 | load_register (&icnt, AT, &imm_expr, 0); | |
3546 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3547 | break; | |
3548 | ||
3549 | case M_BEQ_I: | |
3550 | s = "beq"; | |
3551 | goto beq_i; | |
3552 | case M_BEQL_I: | |
3553 | s = "beql"; | |
3554 | likely = 1; | |
3555 | goto beq_i; | |
3556 | case M_BNE_I: | |
3557 | s = "bne"; | |
3558 | goto beq_i; | |
3559 | case M_BNEL_I: | |
3560 | s = "bnel"; | |
3561 | likely = 1; | |
3562 | beq_i: | |
3563 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3564 | { | |
3565 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3566 | 0); | |
3567 | return; | |
3568 | } | |
3569 | load_register (&icnt, AT, &imm_expr, 0); | |
3570 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3571 | break; | |
3572 | ||
3573 | case M_BGEL: | |
3574 | likely = 1; | |
3575 | case M_BGE: | |
3576 | if (treg == 0) | |
3577 | { | |
3578 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3579 | likely ? "bgezl" : "bgez", | |
3580 | "s,p", sreg); | |
3581 | return; | |
3582 | } | |
3583 | if (sreg == 0) | |
3584 | { | |
3585 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3586 | likely ? "blezl" : "blez", | |
3587 | "s,p", treg); | |
3588 | return; | |
3589 | } | |
3590 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3591 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3592 | likely ? "beql" : "beq", | |
3593 | "s,t,p", AT, 0); | |
3594 | break; | |
3595 | ||
3596 | case M_BGTL_I: | |
3597 | likely = 1; | |
3598 | case M_BGT_I: | |
3599 | /* check for > max integer */ | |
3600 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3601 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3602 | { |
3603 | maxnum <<= 16; | |
3604 | maxnum |= 0xffff; | |
3605 | maxnum <<= 16; | |
3606 | maxnum |= 0xffff; | |
3607 | } | |
3608 | if (imm_expr.X_op == O_constant | |
3609 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3610 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3611 | { |
3612 | do_false: | |
3613 | /* result is always false */ | |
3614 | if (! likely) | |
3615 | { | |
3616 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); | |
3617 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3618 | } | |
3619 | else | |
3620 | { | |
3621 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); | |
3622 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", | |
3623 | "s,t,p", 0, 0); | |
3624 | } | |
3625 | return; | |
3626 | } | |
3627 | if (imm_expr.X_op != O_constant) | |
3628 | as_bad (_("Unsupported large constant")); | |
3629 | imm_expr.X_add_number++; | |
3630 | /* FALLTHROUGH */ | |
3631 | case M_BGE_I: | |
3632 | case M_BGEL_I: | |
3633 | if (mask == M_BGEL_I) | |
3634 | likely = 1; | |
3635 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3636 | { | |
3637 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3638 | likely ? "bgezl" : "bgez", | |
3639 | "s,p", sreg); | |
3640 | return; | |
3641 | } | |
3642 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3643 | { | |
3644 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3645 | likely ? "bgtzl" : "bgtz", | |
3646 | "s,p", sreg); | |
3647 | return; | |
3648 | } | |
3649 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3650 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3651 | { |
3652 | maxnum <<= 16; | |
3653 | maxnum |= 0xffff; | |
3654 | maxnum <<= 16; | |
3655 | maxnum |= 0xffff; | |
3656 | } | |
3657 | maxnum = - maxnum - 1; | |
3658 | if (imm_expr.X_op == O_constant | |
3659 | && imm_expr.X_add_number <= maxnum | |
9ce8a5dd | 3660 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3661 | { |
3662 | do_true: | |
3663 | /* result is always true */ | |
3664 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
3665 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
3666 | return; | |
3667 | } | |
3668 | set_at (&icnt, sreg, 0); | |
3669 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3670 | likely ? "beql" : "beq", | |
3671 | "s,t,p", AT, 0); | |
3672 | break; | |
3673 | ||
3674 | case M_BGEUL: | |
3675 | likely = 1; | |
3676 | case M_BGEU: | |
3677 | if (treg == 0) | |
3678 | goto do_true; | |
3679 | if (sreg == 0) | |
3680 | { | |
3681 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3682 | likely ? "beql" : "beq", | |
3683 | "s,t,p", 0, treg); | |
3684 | return; | |
3685 | } | |
3686 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3687 | treg); | |
3688 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3689 | likely ? "beql" : "beq", | |
3690 | "s,t,p", AT, 0); | |
3691 | break; | |
3692 | ||
3693 | case M_BGTUL_I: | |
3694 | likely = 1; | |
3695 | case M_BGTU_I: | |
3696 | if (sreg == 0 | |
9ce8a5dd | 3697 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3698 | && imm_expr.X_op == O_constant |
3699 | && imm_expr.X_add_number == 0xffffffff)) | |
3700 | goto do_false; | |
3701 | if (imm_expr.X_op != O_constant) | |
3702 | as_bad (_("Unsupported large constant")); | |
3703 | imm_expr.X_add_number++; | |
3704 | /* FALLTHROUGH */ | |
3705 | case M_BGEU_I: | |
3706 | case M_BGEUL_I: | |
3707 | if (mask == M_BGEUL_I) | |
3708 | likely = 1; | |
3709 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3710 | goto do_true; | |
3711 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3712 | { | |
3713 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3714 | likely ? "bnel" : "bne", | |
3715 | "s,t,p", sreg, 0); | |
3716 | return; | |
3717 | } | |
3718 | set_at (&icnt, sreg, 1); | |
3719 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3720 | likely ? "beql" : "beq", | |
3721 | "s,t,p", AT, 0); | |
3722 | break; | |
3723 | ||
3724 | case M_BGTL: | |
3725 | likely = 1; | |
3726 | case M_BGT: | |
3727 | if (treg == 0) | |
3728 | { | |
3729 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3730 | likely ? "bgtzl" : "bgtz", | |
3731 | "s,p", sreg); | |
3732 | return; | |
3733 | } | |
3734 | if (sreg == 0) | |
3735 | { | |
3736 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3737 | likely ? "bltzl" : "bltz", | |
3738 | "s,p", treg); | |
3739 | return; | |
3740 | } | |
3741 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3742 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3743 | likely ? "bnel" : "bne", | |
3744 | "s,t,p", AT, 0); | |
3745 | break; | |
3746 | ||
3747 | case M_BGTUL: | |
3748 | likely = 1; | |
3749 | case M_BGTU: | |
3750 | if (treg == 0) | |
3751 | { | |
3752 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3753 | likely ? "bnel" : "bne", | |
3754 | "s,t,p", sreg, 0); | |
3755 | return; | |
3756 | } | |
3757 | if (sreg == 0) | |
3758 | goto do_false; | |
3759 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3760 | sreg); | |
3761 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3762 | likely ? "bnel" : "bne", | |
3763 | "s,t,p", AT, 0); | |
3764 | break; | |
3765 | ||
3766 | case M_BLEL: | |
3767 | likely = 1; | |
3768 | case M_BLE: | |
3769 | if (treg == 0) | |
3770 | { | |
3771 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3772 | likely ? "blezl" : "blez", | |
3773 | "s,p", sreg); | |
3774 | return; | |
3775 | } | |
3776 | if (sreg == 0) | |
3777 | { | |
3778 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3779 | likely ? "bgezl" : "bgez", | |
3780 | "s,p", treg); | |
3781 | return; | |
3782 | } | |
3783 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3784 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3785 | likely ? "beql" : "beq", | |
3786 | "s,t,p", AT, 0); | |
3787 | break; | |
3788 | ||
3789 | case M_BLEL_I: | |
3790 | likely = 1; | |
3791 | case M_BLE_I: | |
3792 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3793 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3794 | { |
3795 | maxnum <<= 16; | |
3796 | maxnum |= 0xffff; | |
3797 | maxnum <<= 16; | |
3798 | maxnum |= 0xffff; | |
3799 | } | |
3800 | if (imm_expr.X_op == O_constant | |
3801 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3802 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3803 | goto do_true; |
3804 | if (imm_expr.X_op != O_constant) | |
3805 | as_bad (_("Unsupported large constant")); | |
3806 | imm_expr.X_add_number++; | |
3807 | /* FALLTHROUGH */ | |
3808 | case M_BLT_I: | |
3809 | case M_BLTL_I: | |
3810 | if (mask == M_BLTL_I) | |
3811 | likely = 1; | |
3812 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3813 | { | |
3814 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3815 | likely ? "bltzl" : "bltz", | |
3816 | "s,p", sreg); | |
3817 | return; | |
3818 | } | |
3819 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3820 | { | |
3821 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3822 | likely ? "blezl" : "blez", | |
3823 | "s,p", sreg); | |
3824 | return; | |
3825 | } | |
3826 | set_at (&icnt, sreg, 0); | |
3827 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3828 | likely ? "bnel" : "bne", | |
3829 | "s,t,p", AT, 0); | |
3830 | break; | |
3831 | ||
3832 | case M_BLEUL: | |
3833 | likely = 1; | |
3834 | case M_BLEU: | |
3835 | if (treg == 0) | |
3836 | { | |
3837 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3838 | likely ? "beql" : "beq", | |
3839 | "s,t,p", sreg, 0); | |
3840 | return; | |
3841 | } | |
3842 | if (sreg == 0) | |
3843 | goto do_true; | |
3844 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3845 | sreg); | |
3846 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3847 | likely ? "beql" : "beq", | |
3848 | "s,t,p", AT, 0); | |
3849 | break; | |
3850 | ||
3851 | case M_BLEUL_I: | |
3852 | likely = 1; | |
3853 | case M_BLEU_I: | |
3854 | if (sreg == 0 | |
9ce8a5dd | 3855 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3856 | && imm_expr.X_op == O_constant |
3857 | && imm_expr.X_add_number == 0xffffffff)) | |
3858 | goto do_true; | |
3859 | if (imm_expr.X_op != O_constant) | |
3860 | as_bad (_("Unsupported large constant")); | |
3861 | imm_expr.X_add_number++; | |
3862 | /* FALLTHROUGH */ | |
3863 | case M_BLTU_I: | |
3864 | case M_BLTUL_I: | |
3865 | if (mask == M_BLTUL_I) | |
3866 | likely = 1; | |
3867 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3868 | goto do_false; | |
3869 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3870 | { | |
3871 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3872 | likely ? "beql" : "beq", | |
3873 | "s,t,p", sreg, 0); | |
3874 | return; | |
3875 | } | |
3876 | set_at (&icnt, sreg, 1); | |
3877 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3878 | likely ? "bnel" : "bne", | |
3879 | "s,t,p", AT, 0); | |
3880 | break; | |
3881 | ||
3882 | case M_BLTL: | |
3883 | likely = 1; | |
3884 | case M_BLT: | |
3885 | if (treg == 0) | |
3886 | { | |
3887 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3888 | likely ? "bltzl" : "bltz", | |
3889 | "s,p", sreg); | |
3890 | return; | |
3891 | } | |
3892 | if (sreg == 0) | |
3893 | { | |
3894 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3895 | likely ? "bgtzl" : "bgtz", | |
3896 | "s,p", treg); | |
3897 | return; | |
3898 | } | |
3899 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3900 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3901 | likely ? "bnel" : "bne", | |
3902 | "s,t,p", AT, 0); | |
3903 | break; | |
3904 | ||
3905 | case M_BLTUL: | |
3906 | likely = 1; | |
3907 | case M_BLTU: | |
3908 | if (treg == 0) | |
3909 | goto do_false; | |
3910 | if (sreg == 0) | |
3911 | { | |
3912 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3913 | likely ? "bnel" : "bne", | |
3914 | "s,t,p", 0, treg); | |
3915 | return; | |
3916 | } | |
3917 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3918 | treg); | |
3919 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3920 | likely ? "bnel" : "bne", | |
3921 | "s,t,p", AT, 0); | |
3922 | break; | |
3923 | ||
3924 | case M_DDIV_3: | |
3925 | dbl = 1; | |
3926 | case M_DIV_3: | |
3927 | s = "mflo"; | |
3928 | goto do_div3; | |
3929 | case M_DREM_3: | |
3930 | dbl = 1; | |
3931 | case M_REM_3: | |
3932 | s = "mfhi"; | |
3933 | do_div3: | |
3934 | if (treg == 0) | |
3935 | { | |
3936 | as_warn (_("Divide by zero.")); | |
3937 | if (mips_trap) | |
3938 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3939 | else | |
9117d219 | 3940 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3941 | return; |
3942 | } | |
3943 | ||
3944 | mips_emit_delays (true); | |
3945 | ++mips_opts.noreorder; | |
3946 | mips_any_noreorder = 1; | |
3947 | if (mips_trap) | |
3948 | { | |
3949 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3950 | macro_build ((char *) NULL, &icnt, NULL, | |
3951 | dbl ? "ddiv" : "div", | |
3952 | "z,s,t", sreg, treg); | |
3953 | } | |
3954 | else | |
3955 | { | |
3956 | expr1.X_add_number = 8; | |
3957 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3958 | macro_build ((char *) NULL, &icnt, NULL, | |
3959 | dbl ? "ddiv" : "div", | |
3960 | "z,s,t", sreg, treg); | |
9117d219 | 3961 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
3962 | } |
3963 | expr1.X_add_number = -1; | |
3964 | macro_build ((char *) NULL, &icnt, &expr1, | |
3965 | dbl ? "daddiu" : "addiu", | |
3966 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
3967 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
3968 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
3969 | if (dbl) | |
3970 | { | |
3971 | expr1.X_add_number = 1; | |
3972 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
3973 | (int) BFD_RELOC_LO16); | |
3974 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
3975 | 31); | |
3976 | } | |
3977 | else | |
3978 | { | |
3979 | expr1.X_add_number = 0x80000000; | |
3980 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
3981 | (int) BFD_RELOC_HI16); | |
3982 | } | |
3983 | if (mips_trap) | |
3984 | { | |
3985 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3986 | /* We want to close the noreorder block as soon as possible, so | |
3987 | that later insns are available for delay slot filling. */ | |
3988 | --mips_opts.noreorder; | |
3989 | } | |
3990 | else | |
3991 | { | |
3992 | expr1.X_add_number = 8; | |
3993 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3994 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3995 | ||
3996 | /* We want to close the noreorder block as soon as possible, so | |
3997 | that later insns are available for delay slot filling. */ | |
3998 | --mips_opts.noreorder; | |
3999 | ||
9117d219 | 4000 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
4001 | } |
4002 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4003 | break; | |
4004 | ||
4005 | case M_DIV_3I: | |
4006 | s = "div"; | |
4007 | s2 = "mflo"; | |
4008 | goto do_divi; | |
4009 | case M_DIVU_3I: | |
4010 | s = "divu"; | |
4011 | s2 = "mflo"; | |
4012 | goto do_divi; | |
4013 | case M_REM_3I: | |
4014 | s = "div"; | |
4015 | s2 = "mfhi"; | |
4016 | goto do_divi; | |
4017 | case M_REMU_3I: | |
4018 | s = "divu"; | |
4019 | s2 = "mfhi"; | |
4020 | goto do_divi; | |
4021 | case M_DDIV_3I: | |
4022 | dbl = 1; | |
4023 | s = "ddiv"; | |
4024 | s2 = "mflo"; | |
4025 | goto do_divi; | |
4026 | case M_DDIVU_3I: | |
4027 | dbl = 1; | |
4028 | s = "ddivu"; | |
4029 | s2 = "mflo"; | |
4030 | goto do_divi; | |
4031 | case M_DREM_3I: | |
4032 | dbl = 1; | |
4033 | s = "ddiv"; | |
4034 | s2 = "mfhi"; | |
4035 | goto do_divi; | |
4036 | case M_DREMU_3I: | |
4037 | dbl = 1; | |
4038 | s = "ddivu"; | |
4039 | s2 = "mfhi"; | |
4040 | do_divi: | |
4041 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4042 | { | |
4043 | as_warn (_("Divide by zero.")); | |
4044 | if (mips_trap) | |
4045 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4046 | else | |
beae10d5 | 4047 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4048 | return; |
4049 | } | |
4050 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4051 | { | |
4052 | if (strcmp (s2, "mflo") == 0) | |
4053 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, | |
4054 | sreg); | |
4055 | else | |
4056 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4057 | return; | |
4058 | } | |
4059 | if (imm_expr.X_op == O_constant | |
4060 | && imm_expr.X_add_number == -1 | |
4061 | && s[strlen (s) - 1] != 'u') | |
4062 | { | |
4063 | if (strcmp (s2, "mflo") == 0) | |
4064 | { | |
4065 | if (dbl) | |
4066 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, | |
4067 | sreg); | |
4068 | else | |
4069 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, | |
4070 | sreg); | |
4071 | } | |
4072 | else | |
4073 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4074 | return; | |
4075 | } | |
4076 | ||
4077 | load_register (&icnt, AT, &imm_expr, dbl); | |
4078 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4079 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4080 | break; | |
4081 | ||
4082 | case M_DIVU_3: | |
4083 | s = "divu"; | |
4084 | s2 = "mflo"; | |
4085 | goto do_divu3; | |
4086 | case M_REMU_3: | |
4087 | s = "divu"; | |
4088 | s2 = "mfhi"; | |
4089 | goto do_divu3; | |
4090 | case M_DDIVU_3: | |
4091 | s = "ddivu"; | |
4092 | s2 = "mflo"; | |
4093 | goto do_divu3; | |
4094 | case M_DREMU_3: | |
4095 | s = "ddivu"; | |
4096 | s2 = "mfhi"; | |
4097 | do_divu3: | |
4098 | mips_emit_delays (true); | |
4099 | ++mips_opts.noreorder; | |
4100 | mips_any_noreorder = 1; | |
4101 | if (mips_trap) | |
4102 | { | |
4103 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4104 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4105 | /* We want to close the noreorder block as soon as possible, so | |
4106 | that later insns are available for delay slot filling. */ | |
4107 | --mips_opts.noreorder; | |
4108 | } | |
4109 | else | |
4110 | { | |
4111 | expr1.X_add_number = 8; | |
4112 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4113 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4114 | ||
4115 | /* We want to close the noreorder block as soon as possible, so | |
4116 | that later insns are available for delay slot filling. */ | |
4117 | --mips_opts.noreorder; | |
beae10d5 | 4118 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4119 | } |
4120 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4121 | return; | |
4122 | ||
4123 | case M_DLA_AB: | |
4124 | dbl = 1; | |
4125 | case M_LA_AB: | |
4126 | /* Load the address of a symbol into a register. If breg is not | |
4127 | zero, we then add a base register to it. */ | |
4128 | ||
4129 | /* When generating embedded PIC code, we permit expressions of | |
4130 | the form | |
4131 | la $4,foo-bar | |
bb2d6cd7 | 4132 | where bar is an address in the current section. These are used |
252b5132 RH |
4133 | when getting the addresses of functions. We don't permit |
4134 | X_add_number to be non-zero, because if the symbol is | |
4135 | external the relaxing code needs to know that any addend is | |
4136 | purely the offset to X_op_symbol. */ | |
4137 | if (mips_pic == EMBEDDED_PIC | |
4138 | && offset_expr.X_op == O_subtract | |
49309057 | 4139 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4140 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4141 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4142 | && (S_GET_SEGMENT | |
4143 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4144 | ->X_add_symbol) | |
bb2d6cd7 | 4145 | == now_seg))) |
252b5132 | 4146 | && breg == 0 |
bb2d6cd7 GK |
4147 | && (offset_expr.X_add_number == 0 |
4148 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 RH |
4149 | { |
4150 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4151 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4152 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4153 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4154 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4155 | ? "addiu" : "daddiu"), |
4156 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
4157 | return; | |
4158 | } | |
4159 | ||
4160 | if (offset_expr.X_op != O_symbol | |
4161 | && offset_expr.X_op != O_constant) | |
4162 | { | |
4163 | as_bad (_("expression too complex")); | |
4164 | offset_expr.X_op = O_constant; | |
4165 | } | |
4166 | ||
4167 | if (treg == breg) | |
4168 | { | |
4169 | tempreg = AT; | |
4170 | used_at = 1; | |
4171 | } | |
4172 | else | |
4173 | { | |
4174 | tempreg = treg; | |
4175 | used_at = 0; | |
4176 | } | |
4177 | ||
4178 | if (offset_expr.X_op == O_constant) | |
4179 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4180 | else if (mips_pic == NO_PIC) | |
4181 | { | |
4182 | /* If this is a reference to an GP relative symbol, we want | |
4183 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4184 | Otherwise we want | |
4185 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4186 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4187 | If we have a constant, we need two instructions anyhow, | |
4188 | so we may as well always use the latter form. */ | |
4189 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4190 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4191 | p = NULL; | |
4192 | else | |
4193 | { | |
4194 | frag_grow (20); | |
4195 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4196 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4197 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4198 | ? "addiu" : "daddiu"), |
4199 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4200 | p = frag_var (rs_machine_dependent, 8, 0, | |
4201 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4202 | mips_opts.warn_about_macros), | |
4203 | offset_expr.X_add_symbol, (offsetT) 0, | |
4204 | (char *) NULL); | |
4205 | } | |
4206 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4207 | if (p != NULL) | |
4208 | p += 4; | |
4209 | macro_build (p, &icnt, &offset_expr, | |
4210 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4211 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4212 | ? "addiu" : "daddiu"), |
4213 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4214 | } | |
4215 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4216 | { | |
9117d219 NC |
4217 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4218 | ||
252b5132 RH |
4219 | /* If this is a reference to an external symbol, and there |
4220 | is no constant, we want | |
4221 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4222 | or if tempreg is PIC_CALL_REG |
4223 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4224 | For a local symbol, we want |
4225 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4226 | nop | |
4227 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4228 | ||
4229 | If we have a small constant, and this is a reference to | |
4230 | an external symbol, we want | |
4231 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4232 | nop | |
4233 | addiu $tempreg,$tempreg,<constant> | |
4234 | For a local symbol, we want the same instruction | |
4235 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4236 | addiu instruction. | |
4237 | ||
4238 | If we have a large constant, and this is a reference to | |
4239 | an external symbol, we want | |
4240 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4241 | lui $at,<hiconstant> | |
4242 | addiu $at,$at,<loconstant> | |
4243 | addu $tempreg,$tempreg,$at | |
4244 | For a local symbol, we want the same instruction | |
4245 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4246 | addiu instruction. */ | |
4247 | expr1.X_add_number = offset_expr.X_add_number; | |
4248 | offset_expr.X_add_number = 0; | |
4249 | frag_grow (32); | |
9117d219 NC |
4250 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4251 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
252b5132 RH |
4252 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4253 | dbl ? "ld" : "lw", | |
9117d219 | 4254 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4255 | if (expr1.X_add_number == 0) |
4256 | { | |
4257 | int off; | |
4258 | ||
4259 | if (breg == 0) | |
4260 | off = 0; | |
4261 | else | |
4262 | { | |
4263 | /* We're going to put in an addu instruction using | |
4264 | tempreg, so we may as well insert the nop right | |
4265 | now. */ | |
4266 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4267 | "nop", ""); | |
4268 | off = 4; | |
4269 | } | |
4270 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4271 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4272 | (breg == 0 | |
4273 | ? mips_opts.warn_about_macros | |
4274 | : 0)), | |
4275 | offset_expr.X_add_symbol, (offsetT) 0, | |
4276 | (char *) NULL); | |
4277 | if (breg == 0) | |
4278 | { | |
4279 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4280 | p += 4; | |
4281 | } | |
4282 | macro_build (p, &icnt, &expr1, | |
4283 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4284 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4285 | ? "addiu" : "daddiu"), |
4286 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4287 | /* FIXME: If breg == 0, and the next instruction uses | |
4288 | $tempreg, then if this variant case is used an extra | |
4289 | nop will be generated. */ | |
4290 | } | |
4291 | else if (expr1.X_add_number >= -0x8000 | |
4292 | && expr1.X_add_number < 0x8000) | |
4293 | { | |
4294 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4295 | "nop", ""); | |
4296 | macro_build ((char *) NULL, &icnt, &expr1, | |
4297 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4298 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4299 | ? "addiu" : "daddiu"), |
4300 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4301 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4302 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4303 | offset_expr.X_add_symbol, (offsetT) 0, | |
4304 | (char *) NULL); | |
4305 | } | |
4306 | else | |
4307 | { | |
4308 | int off1; | |
4309 | ||
4310 | /* If we are going to add in a base register, and the | |
4311 | target register and the base register are the same, | |
4312 | then we are using AT as a temporary register. Since | |
4313 | we want to load the constant into AT, we add our | |
4314 | current AT (from the global offset table) and the | |
4315 | register into the register now, and pretend we were | |
4316 | not using a base register. */ | |
4317 | if (breg != treg) | |
4318 | off1 = 0; | |
4319 | else | |
4320 | { | |
4321 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4322 | "nop", ""); | |
4323 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4324 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4325 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4326 | ? "addu" : "daddu"), |
4327 | "d,v,t", treg, AT, breg); | |
4328 | breg = 0; | |
4329 | tempreg = treg; | |
4330 | off1 = -8; | |
4331 | } | |
4332 | ||
4333 | /* Set mips_optimize around the lui instruction to avoid | |
4334 | inserting an unnecessary nop after the lw. */ | |
4335 | hold_mips_optimize = mips_optimize; | |
4336 | mips_optimize = 2; | |
4337 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4338 | mips_optimize = hold_mips_optimize; | |
4339 | ||
4340 | macro_build ((char *) NULL, &icnt, &expr1, | |
4341 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4342 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4343 | ? "addiu" : "daddiu"), |
4344 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4346 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4347 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4348 | ? "addu" : "daddu"), |
4349 | "d,v,t", tempreg, tempreg, AT); | |
4350 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4351 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4352 | offset_expr.X_add_symbol, (offsetT) 0, | |
4353 | (char *) NULL); | |
4354 | used_at = 1; | |
4355 | } | |
4356 | } | |
4357 | else if (mips_pic == SVR4_PIC) | |
4358 | { | |
4359 | int gpdel; | |
9117d219 NC |
4360 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4361 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4362 | |
4363 | /* This is the large GOT case. If this is a reference to an | |
4364 | external symbol, and there is no constant, we want | |
4365 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4366 | addu $tempreg,$tempreg,$gp | |
4367 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4368 | or if tempreg is PIC_CALL_REG |
4369 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4370 | addu $tempreg,$tempreg,$gp | |
4371 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4372 | For a local symbol, we want |
4373 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4374 | nop | |
4375 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4376 | ||
4377 | If we have a small constant, and this is a reference to | |
4378 | an external symbol, we want | |
4379 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4380 | addu $tempreg,$tempreg,$gp | |
4381 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4382 | nop | |
4383 | addiu $tempreg,$tempreg,<constant> | |
4384 | For a local symbol, we want | |
4385 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4386 | nop | |
4387 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4388 | ||
4389 | If we have a large constant, and this is a reference to | |
4390 | an external symbol, we want | |
4391 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4392 | addu $tempreg,$tempreg,$gp | |
4393 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4394 | lui $at,<hiconstant> | |
4395 | addiu $at,$at,<loconstant> | |
4396 | addu $tempreg,$tempreg,$at | |
4397 | For a local symbol, we want | |
4398 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4399 | lui $at,<hiconstant> | |
4400 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4401 | addu $tempreg,$tempreg,$at | |
4402 | */ | |
4403 | expr1.X_add_number = offset_expr.X_add_number; | |
4404 | offset_expr.X_add_number = 0; | |
4405 | frag_grow (52); | |
4406 | if (reg_needs_delay (GP)) | |
4407 | gpdel = 4; | |
4408 | else | |
4409 | gpdel = 0; | |
9117d219 NC |
4410 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4411 | { | |
4412 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4413 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4414 | } | |
252b5132 | 4415 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4416 | tempreg, lui_reloc_type); |
252b5132 RH |
4417 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4418 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4419 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4420 | ? "addu" : "daddu"), |
4421 | "d,v,t", tempreg, tempreg, GP); | |
4422 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4423 | dbl ? "ld" : "lw", | |
9117d219 | 4424 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4425 | if (expr1.X_add_number == 0) |
4426 | { | |
4427 | int off; | |
4428 | ||
4429 | if (breg == 0) | |
4430 | off = 0; | |
4431 | else | |
4432 | { | |
4433 | /* We're going to put in an addu instruction using | |
4434 | tempreg, so we may as well insert the nop right | |
4435 | now. */ | |
4436 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4437 | "nop", ""); | |
4438 | off = 4; | |
4439 | } | |
4440 | ||
4441 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4442 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4443 | 8 + gpdel, 0, | |
4444 | (breg == 0 | |
4445 | ? mips_opts.warn_about_macros | |
4446 | : 0)), | |
4447 | offset_expr.X_add_symbol, (offsetT) 0, | |
4448 | (char *) NULL); | |
4449 | } | |
4450 | else if (expr1.X_add_number >= -0x8000 | |
4451 | && expr1.X_add_number < 0x8000) | |
4452 | { | |
4453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4454 | "nop", ""); | |
4455 | macro_build ((char *) NULL, &icnt, &expr1, | |
4456 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4457 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4458 | ? "addiu" : "daddiu"), |
4459 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4460 | ||
4461 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4462 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4463 | (breg == 0 | |
4464 | ? mips_opts.warn_about_macros | |
4465 | : 0)), | |
4466 | offset_expr.X_add_symbol, (offsetT) 0, | |
4467 | (char *) NULL); | |
4468 | } | |
4469 | else | |
4470 | { | |
4471 | int adj, dreg; | |
4472 | ||
4473 | /* If we are going to add in a base register, and the | |
4474 | target register and the base register are the same, | |
4475 | then we are using AT as a temporary register. Since | |
4476 | we want to load the constant into AT, we add our | |
4477 | current AT (from the global offset table) and the | |
4478 | register into the register now, and pretend we were | |
4479 | not using a base register. */ | |
4480 | if (breg != treg) | |
4481 | { | |
4482 | adj = 0; | |
4483 | dreg = tempreg; | |
4484 | } | |
4485 | else | |
4486 | { | |
4487 | assert (tempreg == AT); | |
4488 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4489 | "nop", ""); | |
4490 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4491 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4492 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4493 | ? "addu" : "daddu"), |
4494 | "d,v,t", treg, AT, breg); | |
4495 | dreg = treg; | |
4496 | adj = 8; | |
4497 | } | |
4498 | ||
4499 | /* Set mips_optimize around the lui instruction to avoid | |
4500 | inserting an unnecessary nop after the lw. */ | |
4501 | hold_mips_optimize = mips_optimize; | |
4502 | mips_optimize = 2; | |
4503 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4504 | mips_optimize = hold_mips_optimize; | |
4505 | ||
4506 | macro_build ((char *) NULL, &icnt, &expr1, | |
4507 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4508 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4509 | ? "addiu" : "daddiu"), |
4510 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4512 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4513 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4514 | ? "addu" : "daddu"), |
4515 | "d,v,t", dreg, dreg, AT); | |
4516 | ||
4517 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4518 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4519 | 8 + gpdel, 0, | |
4520 | (breg == 0 | |
4521 | ? mips_opts.warn_about_macros | |
4522 | : 0)), | |
4523 | offset_expr.X_add_symbol, (offsetT) 0, | |
4524 | (char *) NULL); | |
4525 | ||
4526 | used_at = 1; | |
4527 | } | |
4528 | ||
4529 | if (gpdel > 0) | |
4530 | { | |
4531 | /* This is needed because this instruction uses $gp, but | |
4532 | the first instruction on the main stream does not. */ | |
4533 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4534 | p += 4; | |
4535 | } | |
4536 | macro_build (p, &icnt, &offset_expr, | |
4537 | dbl ? "ld" : "lw", | |
4538 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4539 | p += 4; | |
4540 | if (expr1.X_add_number >= -0x8000 | |
4541 | && expr1.X_add_number < 0x8000) | |
4542 | { | |
4543 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4544 | p += 4; | |
4545 | macro_build (p, &icnt, &expr1, | |
4546 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4547 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4548 | ? "addiu" : "daddiu"), |
4549 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4550 | /* FIXME: If add_number is 0, and there was no base | |
4551 | register, the external symbol case ended with a load, | |
4552 | so if the symbol turns out to not be external, and | |
4553 | the next instruction uses tempreg, an unnecessary nop | |
4554 | will be inserted. */ | |
4555 | } | |
4556 | else | |
4557 | { | |
4558 | if (breg == treg) | |
4559 | { | |
4560 | /* We must add in the base register now, as in the | |
4561 | external symbol case. */ | |
4562 | assert (tempreg == AT); | |
4563 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4564 | p += 4; | |
4565 | macro_build (p, &icnt, (expressionS *) NULL, | |
4566 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4567 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4568 | ? "addu" : "daddu"), |
4569 | "d,v,t", treg, AT, breg); | |
4570 | p += 4; | |
4571 | tempreg = treg; | |
4572 | /* We set breg to 0 because we have arranged to add | |
4573 | it in in both cases. */ | |
4574 | breg = 0; | |
4575 | } | |
4576 | ||
4577 | macro_build_lui (p, &icnt, &expr1, AT); | |
4578 | p += 4; | |
4579 | macro_build (p, &icnt, &expr1, | |
4580 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4581 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4582 | ? "addiu" : "daddiu"), |
4583 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4584 | p += 4; | |
4585 | macro_build (p, &icnt, (expressionS *) NULL, | |
4586 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4587 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4588 | ? "addu" : "daddu"), |
4589 | "d,v,t", tempreg, tempreg, AT); | |
4590 | p += 4; | |
4591 | } | |
4592 | } | |
4593 | else if (mips_pic == EMBEDDED_PIC) | |
4594 | { | |
4595 | /* We use | |
4596 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4597 | */ | |
4598 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4599 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4600 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4601 | ? "addiu" : "daddiu"), |
4602 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4603 | } | |
4604 | else | |
4605 | abort (); | |
4606 | ||
4607 | if (breg != 0) | |
4608 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4609 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4610 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4611 | ? "addu" : "daddu"), |
4612 | "d,v,t", treg, tempreg, breg); | |
4613 | ||
4614 | if (! used_at) | |
4615 | return; | |
4616 | ||
4617 | break; | |
4618 | ||
4619 | case M_J_A: | |
4620 | /* The j instruction may not be used in PIC code, since it | |
4621 | requires an absolute address. We convert it to a b | |
4622 | instruction. */ | |
4623 | if (mips_pic == NO_PIC) | |
4624 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4625 | else | |
4626 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4627 | return; | |
4628 | ||
4629 | /* The jal instructions must be handled as macros because when | |
4630 | generating PIC code they expand to multi-instruction | |
4631 | sequences. Normally they are simple instructions. */ | |
4632 | case M_JAL_1: | |
4633 | dreg = RA; | |
4634 | /* Fall through. */ | |
4635 | case M_JAL_2: | |
4636 | if (mips_pic == NO_PIC | |
4637 | || mips_pic == EMBEDDED_PIC) | |
4638 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4639 | "d,s", dreg, sreg); | |
4640 | else if (mips_pic == SVR4_PIC) | |
4641 | { | |
4642 | if (sreg != PIC_CALL_REG) | |
4643 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 4644 | |
252b5132 RH |
4645 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4646 | "d,s", dreg, sreg); | |
4647 | if (mips_cprestore_offset < 0) | |
4648 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4649 | else | |
4650 | { | |
4651 | expr1.X_add_number = mips_cprestore_offset; | |
4652 | macro_build ((char *) NULL, &icnt, &expr1, | |
4653 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4654 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4655 | ? "lw" : "ld"), |
4656 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4657 | } | |
4658 | } | |
4659 | else | |
4660 | abort (); | |
4661 | ||
4662 | return; | |
4663 | ||
4664 | case M_JAL_A: | |
4665 | if (mips_pic == NO_PIC) | |
4666 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4667 | else if (mips_pic == SVR4_PIC) | |
4668 | { | |
4669 | /* If this is a reference to an external symbol, and we are | |
4670 | using a small GOT, we want | |
4671 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4672 | nop | |
4673 | jalr $25 | |
4674 | nop | |
4675 | lw $gp,cprestore($sp) | |
4676 | The cprestore value is set using the .cprestore | |
4677 | pseudo-op. If we are using a big GOT, we want | |
4678 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4679 | addu $25,$25,$gp | |
4680 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4681 | nop | |
4682 | jalr $25 | |
4683 | nop | |
4684 | lw $gp,cprestore($sp) | |
4685 | If the symbol is not external, we want | |
4686 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4687 | nop | |
4688 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4689 | jalr $25 | |
4690 | nop | |
4691 | lw $gp,cprestore($sp) */ | |
4692 | frag_grow (40); | |
4693 | if (! mips_big_got) | |
4694 | { | |
4695 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4696 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4697 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4698 | ? "lw" : "ld"), |
4699 | "t,o(b)", PIC_CALL_REG, | |
4700 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4702 | "nop", ""); | |
4703 | p = frag_var (rs_machine_dependent, 4, 0, | |
4704 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4705 | offset_expr.X_add_symbol, (offsetT) 0, | |
4706 | (char *) NULL); | |
4707 | } | |
4708 | else | |
4709 | { | |
4710 | int gpdel; | |
4711 | ||
4712 | if (reg_needs_delay (GP)) | |
4713 | gpdel = 4; | |
4714 | else | |
4715 | gpdel = 0; | |
4716 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4717 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4718 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4719 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4720 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4721 | ? "addu" : "daddu"), |
4722 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4723 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4724 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4725 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4726 | ? "lw" : "ld"), |
4727 | "t,o(b)", PIC_CALL_REG, | |
4728 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4730 | "nop", ""); | |
4731 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4732 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4733 | 0, 0), | |
4734 | offset_expr.X_add_symbol, (offsetT) 0, | |
4735 | (char *) NULL); | |
4736 | if (gpdel > 0) | |
4737 | { | |
4738 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4739 | p += 4; | |
4740 | } | |
4741 | macro_build (p, &icnt, &offset_expr, | |
4742 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4743 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4744 | ? "lw" : "ld"), |
4745 | "t,o(b)", PIC_CALL_REG, | |
4746 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4747 | p += 4; | |
4748 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4749 | p += 4; | |
bdaaa2e1 | 4750 | } |
252b5132 RH |
4751 | macro_build (p, &icnt, &offset_expr, |
4752 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4753 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4754 | ? "addiu" : "daddiu"), |
4755 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4756 | (int) BFD_RELOC_LO16); | |
4757 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4758 | "jalr", "s", PIC_CALL_REG); | |
4759 | if (mips_cprestore_offset < 0) | |
4760 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4761 | else | |
4762 | { | |
4763 | if (mips_opts.noreorder) | |
4764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4765 | "nop", ""); | |
4766 | expr1.X_add_number = mips_cprestore_offset; | |
4767 | macro_build ((char *) NULL, &icnt, &expr1, | |
4768 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4769 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4770 | ? "lw" : "ld"), |
4771 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4772 | mips_frame_reg); | |
4773 | } | |
4774 | } | |
4775 | else if (mips_pic == EMBEDDED_PIC) | |
4776 | { | |
4777 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4778 | /* The linker may expand the call to a longer sequence which | |
4779 | uses $at, so we must break rather than return. */ | |
4780 | break; | |
4781 | } | |
4782 | else | |
4783 | abort (); | |
4784 | ||
4785 | return; | |
4786 | ||
4787 | case M_LB_AB: | |
4788 | s = "lb"; | |
4789 | goto ld; | |
4790 | case M_LBU_AB: | |
4791 | s = "lbu"; | |
4792 | goto ld; | |
4793 | case M_LH_AB: | |
4794 | s = "lh"; | |
4795 | goto ld; | |
4796 | case M_LHU_AB: | |
4797 | s = "lhu"; | |
4798 | goto ld; | |
4799 | case M_LW_AB: | |
4800 | s = "lw"; | |
4801 | goto ld; | |
4802 | case M_LWC0_AB: | |
4803 | s = "lwc0"; | |
bdaaa2e1 | 4804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4805 | coproc = 1; |
4806 | goto ld; | |
4807 | case M_LWC1_AB: | |
4808 | s = "lwc1"; | |
bdaaa2e1 | 4809 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4810 | coproc = 1; |
4811 | goto ld; | |
4812 | case M_LWC2_AB: | |
4813 | s = "lwc2"; | |
bdaaa2e1 | 4814 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4815 | coproc = 1; |
4816 | goto ld; | |
4817 | case M_LWC3_AB: | |
4818 | s = "lwc3"; | |
bdaaa2e1 | 4819 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4820 | coproc = 1; |
4821 | goto ld; | |
4822 | case M_LWL_AB: | |
4823 | s = "lwl"; | |
4824 | lr = 1; | |
4825 | goto ld; | |
4826 | case M_LWR_AB: | |
4827 | s = "lwr"; | |
4828 | lr = 1; | |
4829 | goto ld; | |
4830 | case M_LDC1_AB: | |
156c2f8b | 4831 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
4832 | { |
4833 | as_bad (_("opcode not supported on this processor")); | |
4834 | return; | |
4835 | } | |
4836 | s = "ldc1"; | |
bdaaa2e1 | 4837 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4838 | coproc = 1; |
4839 | goto ld; | |
4840 | case M_LDC2_AB: | |
4841 | s = "ldc2"; | |
bdaaa2e1 | 4842 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4843 | coproc = 1; |
4844 | goto ld; | |
4845 | case M_LDC3_AB: | |
4846 | s = "ldc3"; | |
bdaaa2e1 | 4847 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4848 | coproc = 1; |
4849 | goto ld; | |
4850 | case M_LDL_AB: | |
4851 | s = "ldl"; | |
4852 | lr = 1; | |
4853 | goto ld; | |
4854 | case M_LDR_AB: | |
4855 | s = "ldr"; | |
4856 | lr = 1; | |
4857 | goto ld; | |
4858 | case M_LL_AB: | |
4859 | s = "ll"; | |
4860 | goto ld; | |
4861 | case M_LLD_AB: | |
4862 | s = "lld"; | |
4863 | goto ld; | |
4864 | case M_LWU_AB: | |
4865 | s = "lwu"; | |
4866 | ld: | |
4867 | if (breg == treg || coproc || lr) | |
4868 | { | |
4869 | tempreg = AT; | |
4870 | used_at = 1; | |
4871 | } | |
4872 | else | |
4873 | { | |
4874 | tempreg = treg; | |
4875 | used_at = 0; | |
4876 | } | |
4877 | goto ld_st; | |
4878 | case M_SB_AB: | |
4879 | s = "sb"; | |
4880 | goto st; | |
4881 | case M_SH_AB: | |
4882 | s = "sh"; | |
4883 | goto st; | |
4884 | case M_SW_AB: | |
4885 | s = "sw"; | |
4886 | goto st; | |
4887 | case M_SWC0_AB: | |
4888 | s = "swc0"; | |
bdaaa2e1 | 4889 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4890 | coproc = 1; |
4891 | goto st; | |
4892 | case M_SWC1_AB: | |
4893 | s = "swc1"; | |
bdaaa2e1 | 4894 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4895 | coproc = 1; |
4896 | goto st; | |
4897 | case M_SWC2_AB: | |
4898 | s = "swc2"; | |
bdaaa2e1 | 4899 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4900 | coproc = 1; |
4901 | goto st; | |
4902 | case M_SWC3_AB: | |
4903 | s = "swc3"; | |
bdaaa2e1 | 4904 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4905 | coproc = 1; |
4906 | goto st; | |
4907 | case M_SWL_AB: | |
4908 | s = "swl"; | |
4909 | goto st; | |
4910 | case M_SWR_AB: | |
4911 | s = "swr"; | |
4912 | goto st; | |
4913 | case M_SC_AB: | |
4914 | s = "sc"; | |
4915 | goto st; | |
4916 | case M_SCD_AB: | |
4917 | s = "scd"; | |
4918 | goto st; | |
4919 | case M_SDC1_AB: | |
156c2f8b | 4920 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
4921 | { |
4922 | as_bad (_("opcode not supported on this processor")); | |
4923 | return; | |
4924 | } | |
4925 | s = "sdc1"; | |
4926 | coproc = 1; | |
bdaaa2e1 | 4927 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4928 | goto st; |
4929 | case M_SDC2_AB: | |
4930 | s = "sdc2"; | |
bdaaa2e1 | 4931 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4932 | coproc = 1; |
4933 | goto st; | |
4934 | case M_SDC3_AB: | |
4935 | s = "sdc3"; | |
bdaaa2e1 | 4936 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4937 | coproc = 1; |
4938 | goto st; | |
4939 | case M_SDL_AB: | |
4940 | s = "sdl"; | |
4941 | goto st; | |
4942 | case M_SDR_AB: | |
4943 | s = "sdr"; | |
4944 | st: | |
4945 | tempreg = AT; | |
4946 | used_at = 1; | |
4947 | ld_st: | |
bdaaa2e1 | 4948 | /* Itbl support may require additional care here. */ |
252b5132 RH |
4949 | if (mask == M_LWC1_AB |
4950 | || mask == M_SWC1_AB | |
4951 | || mask == M_LDC1_AB | |
4952 | || mask == M_SDC1_AB | |
4953 | || mask == M_L_DAB | |
4954 | || mask == M_S_DAB) | |
4955 | fmt = "T,o(b)"; | |
4956 | else if (coproc) | |
4957 | fmt = "E,o(b)"; | |
4958 | else | |
4959 | fmt = "t,o(b)"; | |
4960 | ||
4961 | if (offset_expr.X_op != O_constant | |
4962 | && offset_expr.X_op != O_symbol) | |
4963 | { | |
4964 | as_bad (_("expression too complex")); | |
4965 | offset_expr.X_op = O_constant; | |
4966 | } | |
4967 | ||
4968 | /* A constant expression in PIC code can be handled just as it | |
4969 | is in non PIC code. */ | |
4970 | if (mips_pic == NO_PIC | |
4971 | || offset_expr.X_op == O_constant) | |
4972 | { | |
4973 | /* If this is a reference to a GP relative symbol, and there | |
4974 | is no base register, we want | |
4975 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4976 | Otherwise, if there is no base register, we want | |
4977 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4978 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4979 | If we have a constant, we need two instructions anyhow, | |
4980 | so we always use the latter form. | |
4981 | ||
4982 | If we have a base register, and this is a reference to a | |
4983 | GP relative symbol, we want | |
4984 | addu $tempreg,$breg,$gp | |
4985 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4986 | Otherwise we want | |
4987 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4988 | addu $tempreg,$tempreg,$breg | |
4989 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4990 | With a constant we always use the latter case. */ | |
4991 | if (breg == 0) | |
4992 | { | |
4993 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4994 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4995 | p = NULL; | |
4996 | else | |
4997 | { | |
4998 | frag_grow (20); | |
4999 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5000 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5001 | p = frag_var (rs_machine_dependent, 8, 0, | |
5002 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5003 | (mips_opts.warn_about_macros | |
5004 | || (used_at | |
5005 | && mips_opts.noat))), | |
5006 | offset_expr.X_add_symbol, (offsetT) 0, | |
5007 | (char *) NULL); | |
5008 | used_at = 0; | |
5009 | } | |
5010 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5011 | if (p != NULL) | |
5012 | p += 4; | |
5013 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5014 | (int) BFD_RELOC_LO16, tempreg); | |
5015 | } | |
5016 | else | |
5017 | { | |
5018 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5019 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5020 | p = NULL; | |
5021 | else | |
5022 | { | |
5023 | frag_grow (28); | |
5024 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5025 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5026 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5027 | ? "addu" : "daddu"), |
5028 | "d,v,t", tempreg, breg, GP); | |
5029 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5030 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5031 | p = frag_var (rs_machine_dependent, 12, 0, | |
5032 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
5033 | offset_expr.X_add_symbol, (offsetT) 0, | |
5034 | (char *) NULL); | |
5035 | } | |
5036 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5037 | if (p != NULL) | |
5038 | p += 4; | |
5039 | macro_build (p, &icnt, (expressionS *) NULL, | |
5040 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5041 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5042 | ? "addu" : "daddu"), |
5043 | "d,v,t", tempreg, tempreg, breg); | |
5044 | if (p != NULL) | |
5045 | p += 4; | |
5046 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5047 | (int) BFD_RELOC_LO16, tempreg); | |
5048 | } | |
5049 | } | |
5050 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5051 | { | |
5052 | /* If this is a reference to an external symbol, we want | |
5053 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5054 | nop | |
5055 | <op> $treg,0($tempreg) | |
5056 | Otherwise we want | |
5057 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5058 | nop | |
5059 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5060 | <op> $treg,0($tempreg) | |
5061 | If there is a base register, we add it to $tempreg before | |
5062 | the <op>. If there is a constant, we stick it in the | |
5063 | <op> instruction. We don't handle constants larger than | |
5064 | 16 bits, because we have no way to load the upper 16 bits | |
5065 | (actually, we could handle them for the subset of cases | |
5066 | in which we are not using $at). */ | |
5067 | assert (offset_expr.X_op == O_symbol); | |
5068 | expr1.X_add_number = offset_expr.X_add_number; | |
5069 | offset_expr.X_add_number = 0; | |
5070 | if (expr1.X_add_number < -0x8000 | |
5071 | || expr1.X_add_number >= 0x8000) | |
5072 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5073 | frag_grow (20); | |
5074 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5075 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5076 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5077 | ? "lw" : "ld"), |
5078 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5079 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5080 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 RH |
5081 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
5082 | offset_expr.X_add_symbol, (offsetT) 0, | |
5083 | (char *) NULL); | |
5084 | macro_build (p, &icnt, &offset_expr, | |
5085 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5086 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5087 | ? "addiu" : "daddiu"), |
5088 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5089 | if (breg != 0) | |
5090 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5091 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5092 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5093 | ? "addu" : "daddu"), |
5094 | "d,v,t", tempreg, tempreg, breg); | |
5095 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5096 | (int) BFD_RELOC_LO16, tempreg); | |
5097 | } | |
5098 | else if (mips_pic == SVR4_PIC) | |
5099 | { | |
5100 | int gpdel; | |
5101 | ||
5102 | /* If this is a reference to an external symbol, we want | |
5103 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5104 | addu $tempreg,$tempreg,$gp | |
5105 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5106 | <op> $treg,0($tempreg) | |
5107 | Otherwise we want | |
5108 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5109 | nop | |
5110 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5111 | <op> $treg,0($tempreg) | |
5112 | If there is a base register, we add it to $tempreg before | |
5113 | the <op>. If there is a constant, we stick it in the | |
5114 | <op> instruction. We don't handle constants larger than | |
5115 | 16 bits, because we have no way to load the upper 16 bits | |
5116 | (actually, we could handle them for the subset of cases | |
5117 | in which we are not using $at). */ | |
5118 | assert (offset_expr.X_op == O_symbol); | |
5119 | expr1.X_add_number = offset_expr.X_add_number; | |
5120 | offset_expr.X_add_number = 0; | |
5121 | if (expr1.X_add_number < -0x8000 | |
5122 | || expr1.X_add_number >= 0x8000) | |
5123 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5124 | if (reg_needs_delay (GP)) | |
5125 | gpdel = 4; | |
5126 | else | |
5127 | gpdel = 0; | |
5128 | frag_grow (36); | |
5129 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5130 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5131 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5132 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5133 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5134 | ? "addu" : "daddu"), |
5135 | "d,v,t", tempreg, tempreg, GP); | |
5136 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5137 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5138 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5139 | ? "lw" : "ld"), |
5140 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
5141 | tempreg); | |
5142 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5143 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5144 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5145 | if (gpdel > 0) | |
5146 | { | |
5147 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5148 | p += 4; | |
5149 | } | |
5150 | macro_build (p, &icnt, &offset_expr, | |
5151 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5152 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5153 | ? "lw" : "ld"), |
5154 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5155 | p += 4; | |
5156 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5157 | p += 4; | |
5158 | macro_build (p, &icnt, &offset_expr, | |
5159 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5160 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5161 | ? "addiu" : "daddiu"), |
5162 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5163 | if (breg != 0) | |
5164 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5165 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5166 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5167 | ? "addu" : "daddu"), |
5168 | "d,v,t", tempreg, tempreg, breg); | |
5169 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5170 | (int) BFD_RELOC_LO16, tempreg); | |
5171 | } | |
5172 | else if (mips_pic == EMBEDDED_PIC) | |
5173 | { | |
5174 | /* If there is no base register, we want | |
5175 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5176 | If there is a base register, we want | |
5177 | addu $tempreg,$breg,$gp | |
5178 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5179 | */ | |
5180 | assert (offset_expr.X_op == O_symbol); | |
5181 | if (breg == 0) | |
5182 | { | |
5183 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5184 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5185 | used_at = 0; | |
5186 | } | |
5187 | else | |
5188 | { | |
5189 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5190 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5191 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5192 | ? "addu" : "daddu"), |
5193 | "d,v,t", tempreg, breg, GP); | |
5194 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5195 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5196 | } | |
5197 | } | |
5198 | else | |
5199 | abort (); | |
5200 | ||
5201 | if (! used_at) | |
5202 | return; | |
5203 | ||
5204 | break; | |
5205 | ||
5206 | case M_LI: | |
5207 | case M_LI_S: | |
5208 | load_register (&icnt, treg, &imm_expr, 0); | |
5209 | return; | |
5210 | ||
5211 | case M_DLI: | |
5212 | load_register (&icnt, treg, &imm_expr, 1); | |
5213 | return; | |
5214 | ||
5215 | case M_LI_SS: | |
5216 | if (imm_expr.X_op == O_constant) | |
5217 | { | |
5218 | load_register (&icnt, AT, &imm_expr, 0); | |
5219 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5220 | "mtc1", "t,G", AT, treg); | |
5221 | break; | |
5222 | } | |
5223 | else | |
5224 | { | |
5225 | assert (offset_expr.X_op == O_symbol | |
5226 | && strcmp (segment_name (S_GET_SEGMENT | |
5227 | (offset_expr.X_add_symbol)), | |
5228 | ".lit4") == 0 | |
5229 | && offset_expr.X_add_number == 0); | |
5230 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5231 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5232 | return; | |
5233 | } | |
5234 | ||
5235 | case M_LI_D: | |
5236 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5237 | the entire value, and in mips1 mode it is the high order 32 | |
5238 | bits of the value and the low order 32 bits are either zero | |
5239 | or in offset_expr. */ | |
5240 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5241 | { | |
9ce8a5dd | 5242 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5243 | load_register (&icnt, treg, &imm_expr, 1); |
5244 | else | |
5245 | { | |
5246 | int hreg, lreg; | |
5247 | ||
5248 | if (target_big_endian) | |
5249 | { | |
5250 | hreg = treg; | |
5251 | lreg = treg + 1; | |
5252 | } | |
5253 | else | |
5254 | { | |
5255 | hreg = treg + 1; | |
5256 | lreg = treg; | |
5257 | } | |
5258 | ||
5259 | if (hreg <= 31) | |
5260 | load_register (&icnt, hreg, &imm_expr, 0); | |
5261 | if (lreg <= 31) | |
5262 | { | |
5263 | if (offset_expr.X_op == O_absent) | |
5264 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5265 | lreg, 0); | |
5266 | else | |
5267 | { | |
5268 | assert (offset_expr.X_op == O_constant); | |
5269 | load_register (&icnt, lreg, &offset_expr, 0); | |
5270 | } | |
5271 | } | |
5272 | } | |
5273 | return; | |
5274 | } | |
5275 | ||
5276 | /* We know that sym is in the .rdata section. First we get the | |
5277 | upper 16 bits of the address. */ | |
5278 | if (mips_pic == NO_PIC) | |
5279 | { | |
5280 | /* FIXME: This won't work for a 64 bit address. */ | |
5281 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5282 | } | |
5283 | else if (mips_pic == SVR4_PIC) | |
5284 | { | |
5285 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5286 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5287 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5288 | ? "lw" : "ld"), |
5289 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5290 | } | |
5291 | else if (mips_pic == EMBEDDED_PIC) | |
5292 | { | |
5293 | /* For embedded PIC we pick up the entire address off $gp in | |
5294 | a single instruction. */ | |
5295 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5296 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5297 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5298 | ? "addiu" : "daddiu"), |
5299 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
5300 | offset_expr.X_op = O_constant; | |
5301 | offset_expr.X_add_number = 0; | |
5302 | } | |
5303 | else | |
5304 | abort (); | |
bdaaa2e1 | 5305 | |
252b5132 | 5306 | /* Now we load the register(s). */ |
9ce8a5dd | 5307 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5308 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5309 | treg, (int) BFD_RELOC_LO16, AT); | |
5310 | else | |
5311 | { | |
5312 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5313 | treg, (int) BFD_RELOC_LO16, AT); | |
5314 | if (treg != 31) | |
5315 | { | |
5316 | /* FIXME: How in the world do we deal with the possible | |
5317 | overflow here? */ | |
5318 | offset_expr.X_add_number += 4; | |
5319 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5320 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5321 | } | |
5322 | } | |
5323 | ||
5324 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5325 | does not become a variant frag. */ | |
5326 | frag_wane (frag_now); | |
5327 | frag_new (0); | |
5328 | ||
5329 | break; | |
5330 | ||
5331 | case M_LI_DD: | |
5332 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5333 | the entire value, and in mips1 mode it is the high order 32 | |
5334 | bits of the value and the low order 32 bits are either zero | |
5335 | or in offset_expr. */ | |
5336 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5337 | { | |
9ce8a5dd GRK |
5338 | load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa)); |
5339 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
252b5132 RH |
5340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5341 | "dmtc1", "t,S", AT, treg); | |
5342 | else | |
5343 | { | |
5344 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5345 | "mtc1", "t,G", AT, treg + 1); | |
5346 | if (offset_expr.X_op == O_absent) | |
5347 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5348 | "mtc1", "t,G", 0, treg); | |
5349 | else | |
5350 | { | |
5351 | assert (offset_expr.X_op == O_constant); | |
5352 | load_register (&icnt, AT, &offset_expr, 0); | |
5353 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5354 | "mtc1", "t,G", AT, treg); | |
5355 | } | |
5356 | } | |
5357 | break; | |
5358 | } | |
5359 | ||
5360 | assert (offset_expr.X_op == O_symbol | |
5361 | && offset_expr.X_add_number == 0); | |
5362 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5363 | if (strcmp (s, ".lit8") == 0) | |
5364 | { | |
e7af610e | 5365 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5366 | { |
5367 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5368 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5369 | return; | |
5370 | } | |
5371 | breg = GP; | |
5372 | r = BFD_RELOC_MIPS_LITERAL; | |
5373 | goto dob; | |
5374 | } | |
5375 | else | |
5376 | { | |
5377 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5378 | if (mips_pic == SVR4_PIC) | |
5379 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5380 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5381 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5382 | ? "lw" : "ld"), |
5383 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5384 | else | |
5385 | { | |
5386 | /* FIXME: This won't work for a 64 bit address. */ | |
5387 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5388 | } | |
bdaaa2e1 | 5389 | |
e7af610e | 5390 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5391 | { |
5392 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5393 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5394 | ||
5395 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5396 | that this does not become a variant frag. */ | |
5397 | frag_wane (frag_now); | |
5398 | frag_new (0); | |
5399 | ||
5400 | break; | |
5401 | } | |
5402 | breg = AT; | |
5403 | r = BFD_RELOC_LO16; | |
5404 | goto dob; | |
5405 | } | |
5406 | ||
5407 | case M_L_DOB: | |
156c2f8b | 5408 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
5409 | { |
5410 | as_bad (_("opcode not supported on this processor")); | |
5411 | return; | |
5412 | } | |
5413 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5414 | to adjust when loading from memory. */ | |
5415 | r = BFD_RELOC_LO16; | |
5416 | dob: | |
e7af610e | 5417 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
5418 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5419 | target_big_endian ? treg + 1 : treg, | |
5420 | (int) r, breg); | |
5421 | /* FIXME: A possible overflow which I don't know how to deal | |
5422 | with. */ | |
5423 | offset_expr.X_add_number += 4; | |
5424 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5425 | target_big_endian ? treg : treg + 1, | |
5426 | (int) r, breg); | |
5427 | ||
5428 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5429 | does not become a variant frag. */ | |
5430 | frag_wane (frag_now); | |
5431 | frag_new (0); | |
5432 | ||
5433 | if (breg != AT) | |
5434 | return; | |
5435 | break; | |
5436 | ||
5437 | case M_L_DAB: | |
5438 | /* | |
5439 | * The MIPS assembler seems to check for X_add_number not | |
5440 | * being double aligned and generating: | |
5441 | * lui at,%hi(foo+1) | |
5442 | * addu at,at,v1 | |
5443 | * addiu at,at,%lo(foo+1) | |
5444 | * lwc1 f2,0(at) | |
5445 | * lwc1 f3,4(at) | |
5446 | * But, the resulting address is the same after relocation so why | |
5447 | * generate the extra instruction? | |
5448 | */ | |
156c2f8b | 5449 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
5450 | { |
5451 | as_bad (_("opcode not supported on this processor")); | |
5452 | return; | |
5453 | } | |
bdaaa2e1 | 5454 | /* Itbl support may require additional care here. */ |
252b5132 | 5455 | coproc = 1; |
e7af610e | 5456 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5457 | { |
5458 | s = "ldc1"; | |
5459 | goto ld; | |
5460 | } | |
5461 | ||
5462 | s = "lwc1"; | |
5463 | fmt = "T,o(b)"; | |
5464 | goto ldd_std; | |
5465 | ||
5466 | case M_S_DAB: | |
156c2f8b | 5467 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
5468 | { |
5469 | as_bad (_("opcode not supported on this processor")); | |
5470 | return; | |
5471 | } | |
5472 | ||
e7af610e | 5473 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5474 | { |
5475 | s = "sdc1"; | |
5476 | goto st; | |
5477 | } | |
5478 | ||
5479 | s = "swc1"; | |
5480 | fmt = "T,o(b)"; | |
bdaaa2e1 | 5481 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5482 | coproc = 1; |
5483 | goto ldd_std; | |
5484 | ||
5485 | case M_LD_AB: | |
9ce8a5dd | 5486 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5487 | { |
5488 | s = "ld"; | |
5489 | goto ld; | |
5490 | } | |
5491 | ||
5492 | s = "lw"; | |
5493 | fmt = "t,o(b)"; | |
5494 | goto ldd_std; | |
5495 | ||
5496 | case M_SD_AB: | |
9ce8a5dd | 5497 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5498 | { |
5499 | s = "sd"; | |
5500 | goto st; | |
5501 | } | |
5502 | ||
5503 | s = "sw"; | |
5504 | fmt = "t,o(b)"; | |
5505 | ||
5506 | ldd_std: | |
5507 | if (offset_expr.X_op != O_symbol | |
5508 | && offset_expr.X_op != O_constant) | |
5509 | { | |
5510 | as_bad (_("expression too complex")); | |
5511 | offset_expr.X_op = O_constant; | |
5512 | } | |
5513 | ||
5514 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5515 | to adjust when loading from memory. We set coproc if we must | |
5516 | load $fn+1 first. */ | |
bdaaa2e1 | 5517 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5518 | if (! target_big_endian) |
5519 | coproc = 0; | |
5520 | ||
5521 | if (mips_pic == NO_PIC | |
5522 | || offset_expr.X_op == O_constant) | |
5523 | { | |
5524 | /* If this is a reference to a GP relative symbol, we want | |
5525 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5526 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5527 | If we have a base register, we use this | |
5528 | addu $at,$breg,$gp | |
5529 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5530 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5531 | If this is not a GP relative symbol, we want | |
5532 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5533 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5534 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5535 | If there is a base register, we add it to $at after the | |
5536 | lui instruction. If there is a constant, we always use | |
5537 | the last case. */ | |
5538 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5539 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5540 | { | |
5541 | p = NULL; | |
5542 | used_at = 1; | |
5543 | } | |
5544 | else | |
5545 | { | |
5546 | int off; | |
5547 | ||
5548 | if (breg == 0) | |
5549 | { | |
5550 | frag_grow (28); | |
5551 | tempreg = GP; | |
5552 | off = 0; | |
5553 | used_at = 0; | |
5554 | } | |
5555 | else | |
5556 | { | |
5557 | frag_grow (36); | |
5558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5559 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5560 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5561 | ? "addu" : "daddu"), |
5562 | "d,v,t", AT, breg, GP); | |
5563 | tempreg = AT; | |
5564 | off = 4; | |
5565 | used_at = 1; | |
5566 | } | |
5567 | ||
beae10d5 | 5568 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5569 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5570 | coproc ? treg + 1 : treg, | |
5571 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5572 | offset_expr.X_add_number += 4; | |
5573 | ||
5574 | /* Set mips_optimize to 2 to avoid inserting an | |
5575 | undesired nop. */ | |
5576 | hold_mips_optimize = mips_optimize; | |
5577 | mips_optimize = 2; | |
beae10d5 | 5578 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5579 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5580 | coproc ? treg : treg + 1, | |
5581 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5582 | mips_optimize = hold_mips_optimize; | |
5583 | ||
5584 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5585 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5586 | used_at && mips_opts.noat), | |
5587 | offset_expr.X_add_symbol, (offsetT) 0, | |
5588 | (char *) NULL); | |
5589 | ||
5590 | /* We just generated two relocs. When tc_gen_reloc | |
5591 | handles this case, it will skip the first reloc and | |
5592 | handle the second. The second reloc already has an | |
5593 | extra addend of 4, which we added above. We must | |
5594 | subtract it out, and then subtract another 4 to make | |
5595 | the first reloc come out right. The second reloc | |
5596 | will come out right because we are going to add 4 to | |
5597 | offset_expr when we build its instruction below. | |
5598 | ||
5599 | If we have a symbol, then we don't want to include | |
5600 | the offset, because it will wind up being included | |
5601 | when we generate the reloc. */ | |
5602 | ||
5603 | if (offset_expr.X_op == O_constant) | |
5604 | offset_expr.X_add_number -= 8; | |
5605 | else | |
5606 | { | |
5607 | offset_expr.X_add_number = -4; | |
5608 | offset_expr.X_op = O_constant; | |
5609 | } | |
5610 | } | |
5611 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5612 | if (p != NULL) | |
5613 | p += 4; | |
5614 | if (breg != 0) | |
5615 | { | |
5616 | macro_build (p, &icnt, (expressionS *) NULL, | |
5617 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5618 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5619 | ? "addu" : "daddu"), |
5620 | "d,v,t", AT, breg, AT); | |
5621 | if (p != NULL) | |
5622 | p += 4; | |
5623 | } | |
beae10d5 | 5624 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5625 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5626 | coproc ? treg + 1 : treg, | |
5627 | (int) BFD_RELOC_LO16, AT); | |
5628 | if (p != NULL) | |
5629 | p += 4; | |
5630 | /* FIXME: How do we handle overflow here? */ | |
5631 | offset_expr.X_add_number += 4; | |
beae10d5 | 5632 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5633 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5634 | coproc ? treg : treg + 1, | |
5635 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 5636 | } |
252b5132 RH |
5637 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
5638 | { | |
5639 | int off; | |
5640 | ||
5641 | /* If this is a reference to an external symbol, we want | |
5642 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5643 | nop | |
5644 | <op> $treg,0($at) | |
5645 | <op> $treg+1,4($at) | |
5646 | Otherwise we want | |
5647 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5648 | nop | |
5649 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5650 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5651 | If there is a base register we add it to $at before the | |
5652 | lwc1 instructions. If there is a constant we include it | |
5653 | in the lwc1 instructions. */ | |
5654 | used_at = 1; | |
5655 | expr1.X_add_number = offset_expr.X_add_number; | |
5656 | offset_expr.X_add_number = 0; | |
5657 | if (expr1.X_add_number < -0x8000 | |
5658 | || expr1.X_add_number >= 0x8000 - 4) | |
5659 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5660 | if (breg == 0) | |
5661 | off = 0; | |
5662 | else | |
5663 | off = 4; | |
5664 | frag_grow (24 + off); | |
5665 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5666 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5667 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5668 | ? "lw" : "ld"), |
5669 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5671 | if (breg != 0) | |
5672 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5673 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5674 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5675 | ? "addu" : "daddu"), |
5676 | "d,v,t", AT, breg, AT); | |
beae10d5 | 5677 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5678 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5679 | coproc ? treg + 1 : treg, | |
5680 | (int) BFD_RELOC_LO16, AT); | |
5681 | expr1.X_add_number += 4; | |
5682 | ||
5683 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5684 | nop. */ | |
5685 | hold_mips_optimize = mips_optimize; | |
5686 | mips_optimize = 2; | |
beae10d5 | 5687 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5688 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5689 | coproc ? treg : treg + 1, | |
5690 | (int) BFD_RELOC_LO16, AT); | |
5691 | mips_optimize = hold_mips_optimize; | |
5692 | ||
5693 | (void) frag_var (rs_machine_dependent, 0, 0, | |
5694 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5695 | offset_expr.X_add_symbol, (offsetT) 0, | |
5696 | (char *) NULL); | |
5697 | } | |
5698 | else if (mips_pic == SVR4_PIC) | |
5699 | { | |
5700 | int gpdel, off; | |
5701 | ||
5702 | /* If this is a reference to an external symbol, we want | |
5703 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5704 | addu $at,$at,$gp | |
5705 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5706 | nop | |
5707 | <op> $treg,0($at) | |
5708 | <op> $treg+1,4($at) | |
5709 | Otherwise we want | |
5710 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5711 | nop | |
5712 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5713 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5714 | If there is a base register we add it to $at before the | |
5715 | lwc1 instructions. If there is a constant we include it | |
5716 | in the lwc1 instructions. */ | |
5717 | used_at = 1; | |
5718 | expr1.X_add_number = offset_expr.X_add_number; | |
5719 | offset_expr.X_add_number = 0; | |
5720 | if (expr1.X_add_number < -0x8000 | |
5721 | || expr1.X_add_number >= 0x8000 - 4) | |
5722 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5723 | if (reg_needs_delay (GP)) | |
5724 | gpdel = 4; | |
5725 | else | |
5726 | gpdel = 0; | |
5727 | if (breg == 0) | |
5728 | off = 0; | |
5729 | else | |
5730 | off = 4; | |
5731 | frag_grow (56); | |
5732 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5733 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5734 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5735 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5736 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5737 | ? "addu" : "daddu"), |
5738 | "d,v,t", AT, AT, GP); | |
5739 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5740 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5741 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5742 | ? "lw" : "ld"), |
5743 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5745 | if (breg != 0) | |
5746 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5747 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5748 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5749 | ? "addu" : "daddu"), |
5750 | "d,v,t", AT, breg, AT); | |
beae10d5 | 5751 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5752 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5753 | coproc ? treg + 1 : treg, | |
5754 | (int) BFD_RELOC_LO16, AT); | |
5755 | expr1.X_add_number += 4; | |
5756 | ||
5757 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5758 | nop. */ | |
5759 | hold_mips_optimize = mips_optimize; | |
5760 | mips_optimize = 2; | |
beae10d5 | 5761 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5762 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5763 | coproc ? treg : treg + 1, | |
5764 | (int) BFD_RELOC_LO16, AT); | |
5765 | mips_optimize = hold_mips_optimize; | |
5766 | expr1.X_add_number -= 4; | |
5767 | ||
5768 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5769 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5770 | 8 + gpdel + off, 1, 0), | |
5771 | offset_expr.X_add_symbol, (offsetT) 0, | |
5772 | (char *) NULL); | |
5773 | if (gpdel > 0) | |
5774 | { | |
5775 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5776 | p += 4; | |
5777 | } | |
5778 | macro_build (p, &icnt, &offset_expr, | |
5779 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5780 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5781 | ? "lw" : "ld"), |
5782 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5783 | p += 4; | |
5784 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5785 | p += 4; | |
5786 | if (breg != 0) | |
5787 | { | |
5788 | macro_build (p, &icnt, (expressionS *) NULL, | |
5789 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5790 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5791 | ? "addu" : "daddu"), |
5792 | "d,v,t", AT, breg, AT); | |
5793 | p += 4; | |
5794 | } | |
beae10d5 | 5795 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5796 | macro_build (p, &icnt, &expr1, s, fmt, |
5797 | coproc ? treg + 1 : treg, | |
5798 | (int) BFD_RELOC_LO16, AT); | |
5799 | p += 4; | |
5800 | expr1.X_add_number += 4; | |
5801 | ||
5802 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5803 | nop. */ | |
5804 | hold_mips_optimize = mips_optimize; | |
5805 | mips_optimize = 2; | |
beae10d5 | 5806 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5807 | macro_build (p, &icnt, &expr1, s, fmt, |
5808 | coproc ? treg : treg + 1, | |
5809 | (int) BFD_RELOC_LO16, AT); | |
5810 | mips_optimize = hold_mips_optimize; | |
5811 | } | |
5812 | else if (mips_pic == EMBEDDED_PIC) | |
5813 | { | |
5814 | /* If there is no base register, we use | |
5815 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5816 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5817 | If we have a base register, we use | |
5818 | addu $at,$breg,$gp | |
5819 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5820 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5821 | */ | |
5822 | if (breg == 0) | |
5823 | { | |
5824 | tempreg = GP; | |
5825 | used_at = 0; | |
5826 | } | |
5827 | else | |
5828 | { | |
5829 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5830 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5831 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5832 | ? "addu" : "daddu"), |
5833 | "d,v,t", AT, breg, GP); | |
5834 | tempreg = AT; | |
5835 | used_at = 1; | |
5836 | } | |
5837 | ||
beae10d5 | 5838 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5839 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5840 | coproc ? treg + 1 : treg, | |
5841 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5842 | offset_expr.X_add_number += 4; | |
beae10d5 | 5843 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5844 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5845 | coproc ? treg : treg + 1, | |
5846 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5847 | } | |
5848 | else | |
5849 | abort (); | |
5850 | ||
5851 | if (! used_at) | |
5852 | return; | |
5853 | ||
5854 | break; | |
5855 | ||
5856 | case M_LD_OB: | |
5857 | s = "lw"; | |
5858 | goto sd_ob; | |
5859 | case M_SD_OB: | |
5860 | s = "sw"; | |
5861 | sd_ob: | |
bdaaa2e1 | 5862 | assert (bfd_arch_bits_per_address (stdoutput) == 32 |
9ce8a5dd | 5863 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)); |
252b5132 RH |
5864 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5865 | (int) BFD_RELOC_LO16, breg); | |
5866 | offset_expr.X_add_number += 4; | |
5867 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5868 | (int) BFD_RELOC_LO16, breg); | |
5869 | return; | |
5870 | ||
5871 | /* New code added to support COPZ instructions. | |
5872 | This code builds table entries out of the macros in mip_opcodes. | |
5873 | R4000 uses interlocks to handle coproc delays. | |
5874 | Other chips (like the R3000) require nops to be inserted for delays. | |
5875 | ||
5876 | FIXME: Currently, we require that the user handle delays. | |
5877 | In order to fill delay slots for non-interlocked chips, | |
5878 | we must have a way to specify delays based on the coprocessor. | |
5879 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5880 | What are the side-effects of the cop instruction? | |
5881 | What cache support might we have and what are its effects? | |
5882 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 5883 | What registers are read/set/modified? |
252b5132 RH |
5884 | |
5885 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 5886 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
5887 | |
5888 | case M_COP0: | |
5889 | s = "c0"; | |
5890 | goto copz; | |
5891 | case M_COP1: | |
5892 | s = "c1"; | |
5893 | goto copz; | |
5894 | case M_COP2: | |
5895 | s = "c2"; | |
5896 | goto copz; | |
5897 | case M_COP3: | |
5898 | s = "c3"; | |
5899 | copz: | |
5900 | /* For now we just do C (same as Cz). The parameter will be | |
5901 | stored in insn_opcode by mips_ip. */ | |
5902 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5903 | ip->insn_opcode); | |
5904 | return; | |
5905 | ||
5906 | #ifdef LOSING_COMPILER | |
5907 | default: | |
5908 | /* Try and see if this is a new itbl instruction. | |
5909 | This code builds table entries out of the macros in mip_opcodes. | |
5910 | FIXME: For now we just assemble the expression and pass it's | |
5911 | value along as a 32-bit immediate. | |
bdaaa2e1 | 5912 | We may want to have the assembler assemble this value, |
252b5132 RH |
5913 | so that we gain the assembler's knowledge of delay slots, |
5914 | symbols, etc. | |
5915 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 5916 | if (itbl_have_entries |
252b5132 | 5917 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 5918 | { |
252b5132 RH |
5919 | s = ip->insn_mo->name; |
5920 | s2 = "cop3"; | |
5921 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
5922 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5923 | return; | |
beae10d5 | 5924 | } |
252b5132 RH |
5925 | macro2 (ip); |
5926 | return; | |
5927 | } | |
5928 | if (mips_opts.noat) | |
5929 | as_warn (_("Macro used $at after \".set noat\"")); | |
5930 | } | |
bdaaa2e1 | 5931 | |
252b5132 RH |
5932 | static void |
5933 | macro2 (ip) | |
5934 | struct mips_cl_insn *ip; | |
5935 | { | |
5936 | register int treg, sreg, dreg, breg; | |
5937 | int tempreg; | |
5938 | int mask; | |
5939 | int icnt = 0; | |
5940 | int used_at; | |
5941 | expressionS expr1; | |
5942 | const char *s; | |
5943 | const char *s2; | |
5944 | const char *fmt; | |
5945 | int likely = 0; | |
5946 | int dbl = 0; | |
5947 | int coproc = 0; | |
5948 | int lr = 0; | |
5949 | int imm = 0; | |
5950 | int off; | |
5951 | offsetT maxnum; | |
5952 | bfd_reloc_code_real_type r; | |
5953 | char *p; | |
bdaaa2e1 | 5954 | |
252b5132 RH |
5955 | treg = (ip->insn_opcode >> 16) & 0x1f; |
5956 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5957 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5958 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 5959 | |
252b5132 RH |
5960 | expr1.X_op = O_constant; |
5961 | expr1.X_op_symbol = NULL; | |
5962 | expr1.X_add_symbol = NULL; | |
5963 | expr1.X_add_number = 1; | |
bdaaa2e1 | 5964 | |
252b5132 RH |
5965 | switch (mask) |
5966 | { | |
5967 | #endif /* LOSING_COMPILER */ | |
5968 | ||
5969 | case M_DMUL: | |
5970 | dbl = 1; | |
5971 | case M_MUL: | |
5972 | macro_build ((char *) NULL, &icnt, NULL, | |
5973 | dbl ? "dmultu" : "multu", | |
5974 | "s,t", sreg, treg); | |
5975 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5976 | return; | |
5977 | ||
5978 | case M_DMUL_I: | |
5979 | dbl = 1; | |
5980 | case M_MUL_I: | |
5981 | /* The MIPS assembler some times generates shifts and adds. I'm | |
5982 | not trying to be that fancy. GCC should do this for us | |
5983 | anyway. */ | |
5984 | load_register (&icnt, AT, &imm_expr, dbl); | |
5985 | macro_build ((char *) NULL, &icnt, NULL, | |
5986 | dbl ? "dmult" : "mult", | |
5987 | "s,t", sreg, AT); | |
5988 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5989 | break; | |
5990 | ||
5991 | case M_DMULO_I: | |
5992 | dbl = 1; | |
5993 | case M_MULO_I: | |
5994 | imm = 1; | |
5995 | goto do_mulo; | |
5996 | ||
5997 | case M_DMULO: | |
5998 | dbl = 1; | |
5999 | case M_MULO: | |
6000 | do_mulo: | |
6001 | mips_emit_delays (true); | |
6002 | ++mips_opts.noreorder; | |
6003 | mips_any_noreorder = 1; | |
6004 | if (imm) | |
6005 | load_register (&icnt, AT, &imm_expr, dbl); | |
6006 | macro_build ((char *) NULL, &icnt, NULL, | |
6007 | dbl ? "dmult" : "mult", | |
6008 | "s,t", sreg, imm ? AT : treg); | |
6009 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6010 | macro_build ((char *) NULL, &icnt, NULL, | |
6011 | dbl ? "dsra32" : "sra", | |
6012 | "d,w,<", dreg, dreg, 31); | |
6013 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6014 | if (mips_trap) | |
6015 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6016 | else | |
6017 | { | |
6018 | expr1.X_add_number = 8; | |
6019 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6020 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6021 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6022 | } |
6023 | --mips_opts.noreorder; | |
6024 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6025 | break; | |
6026 | ||
6027 | case M_DMULOU_I: | |
6028 | dbl = 1; | |
6029 | case M_MULOU_I: | |
6030 | imm = 1; | |
6031 | goto do_mulou; | |
6032 | ||
6033 | case M_DMULOU: | |
6034 | dbl = 1; | |
6035 | case M_MULOU: | |
6036 | do_mulou: | |
6037 | mips_emit_delays (true); | |
6038 | ++mips_opts.noreorder; | |
6039 | mips_any_noreorder = 1; | |
6040 | if (imm) | |
6041 | load_register (&icnt, AT, &imm_expr, dbl); | |
6042 | macro_build ((char *) NULL, &icnt, NULL, | |
6043 | dbl ? "dmultu" : "multu", | |
6044 | "s,t", sreg, imm ? AT : treg); | |
6045 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6046 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6047 | if (mips_trap) | |
6048 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6049 | else | |
6050 | { | |
6051 | expr1.X_add_number = 8; | |
6052 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6053 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
beae10d5 | 6054 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
252b5132 RH |
6055 | } |
6056 | --mips_opts.noreorder; | |
6057 | break; | |
6058 | ||
6059 | case M_ROL: | |
6060 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6061 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6062 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6063 | treg); | |
6064 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6065 | break; | |
6066 | ||
6067 | case M_ROL_I: | |
6068 | if (imm_expr.X_op != O_constant) | |
6069 | as_bad (_("rotate count too large")); | |
6070 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
6071 | (int) (imm_expr.X_add_number & 0x1f)); | |
6072 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
6073 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6074 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6075 | break; | |
6076 | ||
6077 | case M_ROR: | |
6078 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6079 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6080 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6081 | treg); | |
6082 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6083 | break; | |
6084 | ||
6085 | case M_ROR_I: | |
6086 | if (imm_expr.X_op != O_constant) | |
6087 | as_bad (_("rotate count too large")); | |
6088 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6089 | (int) (imm_expr.X_add_number & 0x1f)); | |
6090 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6091 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6092 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6093 | break; | |
6094 | ||
6095 | case M_S_DOB: | |
156c2f8b | 6096 | if (mips_cpu == CPU_R4650) |
252b5132 RH |
6097 | { |
6098 | as_bad (_("opcode not supported on this processor")); | |
6099 | return; | |
6100 | } | |
e7af610e | 6101 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6102 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6103 | to adjust when storing to memory. */ | |
6104 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6105 | target_big_endian ? treg + 1 : treg, | |
6106 | (int) BFD_RELOC_LO16, breg); | |
6107 | offset_expr.X_add_number += 4; | |
6108 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6109 | target_big_endian ? treg : treg + 1, | |
6110 | (int) BFD_RELOC_LO16, breg); | |
6111 | return; | |
6112 | ||
6113 | case M_SEQ: | |
6114 | if (sreg == 0) | |
6115 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6116 | treg, (int) BFD_RELOC_LO16); | |
6117 | else if (treg == 0) | |
6118 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6119 | sreg, (int) BFD_RELOC_LO16); | |
6120 | else | |
6121 | { | |
6122 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6123 | sreg, treg); | |
6124 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6125 | dreg, (int) BFD_RELOC_LO16); | |
6126 | } | |
6127 | return; | |
6128 | ||
6129 | case M_SEQ_I: | |
6130 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6131 | { | |
6132 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6133 | sreg, (int) BFD_RELOC_LO16); | |
6134 | return; | |
6135 | } | |
6136 | if (sreg == 0) | |
6137 | { | |
6138 | as_warn (_("Instruction %s: result is always false"), | |
6139 | ip->insn_mo->name); | |
6140 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
6141 | return; | |
6142 | } | |
6143 | if (imm_expr.X_op == O_constant | |
6144 | && imm_expr.X_add_number >= 0 | |
6145 | && imm_expr.X_add_number < 0x10000) | |
6146 | { | |
6147 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6148 | sreg, (int) BFD_RELOC_LO16); | |
6149 | used_at = 0; | |
6150 | } | |
6151 | else if (imm_expr.X_op == O_constant | |
6152 | && imm_expr.X_add_number > -0x8000 | |
6153 | && imm_expr.X_add_number < 0) | |
6154 | { | |
6155 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6156 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6157 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6158 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6159 | ? "addiu" : "daddiu"), |
6160 | "t,r,j", dreg, sreg, | |
6161 | (int) BFD_RELOC_LO16); | |
6162 | used_at = 0; | |
6163 | } | |
6164 | else | |
6165 | { | |
6166 | load_register (&icnt, AT, &imm_expr, 0); | |
6167 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6168 | sreg, AT); | |
6169 | used_at = 1; | |
6170 | } | |
6171 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6172 | (int) BFD_RELOC_LO16); | |
6173 | if (used_at) | |
6174 | break; | |
6175 | return; | |
6176 | ||
6177 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6178 | s = "slt"; | |
6179 | goto sge; | |
6180 | case M_SGEU: | |
6181 | s = "sltu"; | |
6182 | sge: | |
6183 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6184 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6185 | (int) BFD_RELOC_LO16); | |
6186 | return; | |
6187 | ||
6188 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6189 | case M_SGEU_I: | |
6190 | if (imm_expr.X_op == O_constant | |
6191 | && imm_expr.X_add_number >= -0x8000 | |
6192 | && imm_expr.X_add_number < 0x8000) | |
6193 | { | |
6194 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6195 | mask == M_SGE_I ? "slti" : "sltiu", | |
6196 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6197 | used_at = 0; | |
6198 | } | |
6199 | else | |
6200 | { | |
6201 | load_register (&icnt, AT, &imm_expr, 0); | |
6202 | macro_build ((char *) NULL, &icnt, NULL, | |
6203 | mask == M_SGE_I ? "slt" : "sltu", | |
6204 | "d,v,t", dreg, sreg, AT); | |
6205 | used_at = 1; | |
6206 | } | |
6207 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6208 | (int) BFD_RELOC_LO16); | |
6209 | if (used_at) | |
6210 | break; | |
6211 | return; | |
6212 | ||
6213 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6214 | s = "slt"; | |
6215 | goto sgt; | |
6216 | case M_SGTU: | |
6217 | s = "sltu"; | |
6218 | sgt: | |
6219 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6220 | return; | |
6221 | ||
6222 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6223 | s = "slt"; | |
6224 | goto sgti; | |
6225 | case M_SGTU_I: | |
6226 | s = "sltu"; | |
6227 | sgti: | |
6228 | load_register (&icnt, AT, &imm_expr, 0); | |
6229 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6230 | break; | |
6231 | ||
6232 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6233 | s = "slt"; | |
6234 | goto sle; | |
6235 | case M_SLEU: | |
6236 | s = "sltu"; | |
6237 | sle: | |
6238 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6239 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6240 | (int) BFD_RELOC_LO16); | |
6241 | return; | |
6242 | ||
6243 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6244 | s = "slt"; | |
6245 | goto slei; | |
6246 | case M_SLEU_I: | |
6247 | s = "sltu"; | |
6248 | slei: | |
6249 | load_register (&icnt, AT, &imm_expr, 0); | |
6250 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6251 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6252 | (int) BFD_RELOC_LO16); | |
6253 | break; | |
6254 | ||
6255 | case M_SLT_I: | |
6256 | if (imm_expr.X_op == O_constant | |
6257 | && imm_expr.X_add_number >= -0x8000 | |
6258 | && imm_expr.X_add_number < 0x8000) | |
6259 | { | |
6260 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6261 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6262 | return; | |
6263 | } | |
6264 | load_register (&icnt, AT, &imm_expr, 0); | |
6265 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6266 | break; | |
6267 | ||
6268 | case M_SLTU_I: | |
6269 | if (imm_expr.X_op == O_constant | |
6270 | && imm_expr.X_add_number >= -0x8000 | |
6271 | && imm_expr.X_add_number < 0x8000) | |
6272 | { | |
6273 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6274 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6275 | return; | |
6276 | } | |
6277 | load_register (&icnt, AT, &imm_expr, 0); | |
6278 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6279 | AT); | |
6280 | break; | |
6281 | ||
6282 | case M_SNE: | |
6283 | if (sreg == 0) | |
6284 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6285 | treg); | |
6286 | else if (treg == 0) | |
6287 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6288 | sreg); | |
6289 | else | |
6290 | { | |
6291 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6292 | sreg, treg); | |
6293 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6294 | dreg); | |
6295 | } | |
6296 | return; | |
6297 | ||
6298 | case M_SNE_I: | |
6299 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6300 | { | |
6301 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6302 | sreg); | |
6303 | return; | |
6304 | } | |
6305 | if (sreg == 0) | |
6306 | { | |
6307 | as_warn (_("Instruction %s: result is always true"), | |
6308 | ip->insn_mo->name); | |
6309 | macro_build ((char *) NULL, &icnt, &expr1, | |
6310 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6311 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6312 | ? "addiu" : "daddiu"), |
6313 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); | |
6314 | return; | |
6315 | } | |
6316 | if (imm_expr.X_op == O_constant | |
6317 | && imm_expr.X_add_number >= 0 | |
6318 | && imm_expr.X_add_number < 0x10000) | |
6319 | { | |
6320 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6321 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6322 | used_at = 0; | |
6323 | } | |
6324 | else if (imm_expr.X_op == O_constant | |
6325 | && imm_expr.X_add_number > -0x8000 | |
6326 | && imm_expr.X_add_number < 0) | |
6327 | { | |
6328 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6329 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6330 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6331 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6332 | ? "addiu" : "daddiu"), |
6333 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6334 | used_at = 0; | |
6335 | } | |
6336 | else | |
6337 | { | |
6338 | load_register (&icnt, AT, &imm_expr, 0); | |
6339 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6340 | sreg, AT); | |
6341 | used_at = 1; | |
6342 | } | |
6343 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6344 | if (used_at) | |
6345 | break; | |
6346 | return; | |
6347 | ||
6348 | case M_DSUB_I: | |
6349 | dbl = 1; | |
6350 | case M_SUB_I: | |
6351 | if (imm_expr.X_op == O_constant | |
6352 | && imm_expr.X_add_number > -0x8000 | |
6353 | && imm_expr.X_add_number <= 0x8000) | |
6354 | { | |
6355 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6356 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6357 | dbl ? "daddi" : "addi", | |
6358 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6359 | return; | |
6360 | } | |
6361 | load_register (&icnt, AT, &imm_expr, dbl); | |
6362 | macro_build ((char *) NULL, &icnt, NULL, | |
6363 | dbl ? "dsub" : "sub", | |
6364 | "d,v,t", dreg, sreg, AT); | |
6365 | break; | |
6366 | ||
6367 | case M_DSUBU_I: | |
6368 | dbl = 1; | |
6369 | case M_SUBU_I: | |
6370 | if (imm_expr.X_op == O_constant | |
6371 | && imm_expr.X_add_number > -0x8000 | |
6372 | && imm_expr.X_add_number <= 0x8000) | |
6373 | { | |
6374 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6375 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6376 | dbl ? "daddiu" : "addiu", | |
6377 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6378 | return; | |
6379 | } | |
6380 | load_register (&icnt, AT, &imm_expr, dbl); | |
6381 | macro_build ((char *) NULL, &icnt, NULL, | |
6382 | dbl ? "dsubu" : "subu", | |
6383 | "d,v,t", dreg, sreg, AT); | |
6384 | break; | |
6385 | ||
6386 | case M_TEQ_I: | |
6387 | s = "teq"; | |
6388 | goto trap; | |
6389 | case M_TGE_I: | |
6390 | s = "tge"; | |
6391 | goto trap; | |
6392 | case M_TGEU_I: | |
6393 | s = "tgeu"; | |
6394 | goto trap; | |
6395 | case M_TLT_I: | |
6396 | s = "tlt"; | |
6397 | goto trap; | |
6398 | case M_TLTU_I: | |
6399 | s = "tltu"; | |
6400 | goto trap; | |
6401 | case M_TNE_I: | |
6402 | s = "tne"; | |
6403 | trap: | |
6404 | load_register (&icnt, AT, &imm_expr, 0); | |
6405 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6406 | break; | |
6407 | ||
252b5132 | 6408 | case M_TRUNCWS: |
43841e91 | 6409 | case M_TRUNCWD: |
e7af610e | 6410 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6411 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6412 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6413 | ||
6414 | /* | |
6415 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6416 | * or is there a reason for it? | |
6417 | */ | |
6418 | mips_emit_delays (true); | |
6419 | ++mips_opts.noreorder; | |
6420 | mips_any_noreorder = 1; | |
6421 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6422 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6423 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6424 | expr1.X_add_number = 3; | |
6425 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6426 | (int) BFD_RELOC_LO16); | |
6427 | expr1.X_add_number = 2; | |
6428 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6429 | (int) BFD_RELOC_LO16); | |
6430 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6431 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6432 | macro_build ((char *) NULL, &icnt, NULL, | |
6433 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6434 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6435 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6436 | --mips_opts.noreorder; | |
6437 | break; | |
6438 | ||
6439 | case M_ULH: | |
6440 | s = "lb"; | |
6441 | goto ulh; | |
6442 | case M_ULHU: | |
6443 | s = "lbu"; | |
6444 | ulh: | |
6445 | if (offset_expr.X_add_number >= 0x7fff) | |
6446 | as_bad (_("operand overflow")); | |
6447 | /* avoid load delay */ | |
6448 | if (! target_big_endian) | |
6449 | offset_expr.X_add_number += 1; | |
6450 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6451 | (int) BFD_RELOC_LO16, breg); | |
6452 | if (! target_big_endian) | |
6453 | offset_expr.X_add_number -= 1; | |
6454 | else | |
6455 | offset_expr.X_add_number += 1; | |
6456 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6457 | (int) BFD_RELOC_LO16, breg); | |
6458 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6459 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6460 | break; | |
6461 | ||
6462 | case M_ULD: | |
6463 | s = "ldl"; | |
6464 | s2 = "ldr"; | |
6465 | off = 7; | |
6466 | goto ulw; | |
6467 | case M_ULW: | |
6468 | s = "lwl"; | |
6469 | s2 = "lwr"; | |
6470 | off = 3; | |
6471 | ulw: | |
6472 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6473 | as_bad (_("operand overflow")); | |
6474 | if (! target_big_endian) | |
6475 | offset_expr.X_add_number += off; | |
6476 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6477 | (int) BFD_RELOC_LO16, breg); | |
6478 | if (! target_big_endian) | |
6479 | offset_expr.X_add_number -= off; | |
6480 | else | |
6481 | offset_expr.X_add_number += off; | |
6482 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6483 | (int) BFD_RELOC_LO16, breg); | |
6484 | return; | |
6485 | ||
6486 | case M_ULD_A: | |
6487 | s = "ldl"; | |
6488 | s2 = "ldr"; | |
6489 | off = 7; | |
6490 | goto ulwa; | |
6491 | case M_ULW_A: | |
6492 | s = "lwl"; | |
6493 | s2 = "lwr"; | |
6494 | off = 3; | |
6495 | ulwa: | |
6496 | load_address (&icnt, AT, &offset_expr); | |
6497 | if (breg != 0) | |
6498 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6499 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6500 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6501 | ? "addu" : "daddu"), |
6502 | "d,v,t", AT, AT, breg); | |
6503 | if (! target_big_endian) | |
6504 | expr1.X_add_number = off; | |
6505 | else | |
6506 | expr1.X_add_number = 0; | |
6507 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6508 | (int) BFD_RELOC_LO16, AT); | |
6509 | if (! target_big_endian) | |
6510 | expr1.X_add_number = 0; | |
6511 | else | |
6512 | expr1.X_add_number = off; | |
6513 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6514 | (int) BFD_RELOC_LO16, AT); | |
6515 | break; | |
6516 | ||
6517 | case M_ULH_A: | |
6518 | case M_ULHU_A: | |
6519 | load_address (&icnt, AT, &offset_expr); | |
6520 | if (breg != 0) | |
6521 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6522 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6523 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6524 | ? "addu" : "daddu"), |
6525 | "d,v,t", AT, AT, breg); | |
6526 | if (target_big_endian) | |
6527 | expr1.X_add_number = 0; | |
6528 | macro_build ((char *) NULL, &icnt, &expr1, | |
6529 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6530 | (int) BFD_RELOC_LO16, AT); | |
6531 | if (target_big_endian) | |
6532 | expr1.X_add_number = 1; | |
6533 | else | |
6534 | expr1.X_add_number = 0; | |
6535 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6536 | (int) BFD_RELOC_LO16, AT); | |
6537 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6538 | treg, 8); | |
6539 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6540 | treg, AT); | |
6541 | break; | |
6542 | ||
6543 | case M_USH: | |
6544 | if (offset_expr.X_add_number >= 0x7fff) | |
6545 | as_bad (_("operand overflow")); | |
6546 | if (target_big_endian) | |
6547 | offset_expr.X_add_number += 1; | |
6548 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6549 | (int) BFD_RELOC_LO16, breg); | |
6550 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6551 | if (target_big_endian) | |
6552 | offset_expr.X_add_number -= 1; | |
6553 | else | |
6554 | offset_expr.X_add_number += 1; | |
6555 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6556 | (int) BFD_RELOC_LO16, breg); | |
6557 | break; | |
6558 | ||
6559 | case M_USD: | |
6560 | s = "sdl"; | |
6561 | s2 = "sdr"; | |
6562 | off = 7; | |
6563 | goto usw; | |
6564 | case M_USW: | |
6565 | s = "swl"; | |
6566 | s2 = "swr"; | |
6567 | off = 3; | |
6568 | usw: | |
6569 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6570 | as_bad (_("operand overflow")); | |
6571 | if (! target_big_endian) | |
6572 | offset_expr.X_add_number += off; | |
6573 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6574 | (int) BFD_RELOC_LO16, breg); | |
6575 | if (! target_big_endian) | |
6576 | offset_expr.X_add_number -= off; | |
6577 | else | |
6578 | offset_expr.X_add_number += off; | |
6579 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6580 | (int) BFD_RELOC_LO16, breg); | |
6581 | return; | |
6582 | ||
6583 | case M_USD_A: | |
6584 | s = "sdl"; | |
6585 | s2 = "sdr"; | |
6586 | off = 7; | |
6587 | goto uswa; | |
6588 | case M_USW_A: | |
6589 | s = "swl"; | |
6590 | s2 = "swr"; | |
6591 | off = 3; | |
6592 | uswa: | |
6593 | load_address (&icnt, AT, &offset_expr); | |
6594 | if (breg != 0) | |
6595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6596 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6597 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6598 | ? "addu" : "daddu"), |
6599 | "d,v,t", AT, AT, breg); | |
6600 | if (! target_big_endian) | |
6601 | expr1.X_add_number = off; | |
6602 | else | |
6603 | expr1.X_add_number = 0; | |
6604 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6605 | (int) BFD_RELOC_LO16, AT); | |
6606 | if (! target_big_endian) | |
6607 | expr1.X_add_number = 0; | |
6608 | else | |
6609 | expr1.X_add_number = off; | |
6610 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6611 | (int) BFD_RELOC_LO16, AT); | |
6612 | break; | |
6613 | ||
6614 | case M_USH_A: | |
6615 | load_address (&icnt, AT, &offset_expr); | |
6616 | if (breg != 0) | |
6617 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6618 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6619 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6620 | ? "addu" : "daddu"), |
6621 | "d,v,t", AT, AT, breg); | |
6622 | if (! target_big_endian) | |
6623 | expr1.X_add_number = 0; | |
6624 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6625 | (int) BFD_RELOC_LO16, AT); | |
6626 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6627 | treg, 8); | |
6628 | if (! target_big_endian) | |
6629 | expr1.X_add_number = 1; | |
6630 | else | |
6631 | expr1.X_add_number = 0; | |
6632 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6633 | (int) BFD_RELOC_LO16, AT); | |
6634 | if (! target_big_endian) | |
6635 | expr1.X_add_number = 0; | |
6636 | else | |
6637 | expr1.X_add_number = 1; | |
6638 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6639 | (int) BFD_RELOC_LO16, AT); | |
6640 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6641 | treg, 8); | |
6642 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6643 | treg, AT); | |
6644 | break; | |
6645 | ||
6646 | default: | |
6647 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 6648 | are added dynamically. */ |
252b5132 RH |
6649 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
6650 | break; | |
6651 | } | |
6652 | if (mips_opts.noat) | |
6653 | as_warn (_("Macro used $at after \".set noat\"")); | |
6654 | } | |
6655 | ||
6656 | /* Implement macros in mips16 mode. */ | |
6657 | ||
6658 | static void | |
6659 | mips16_macro (ip) | |
6660 | struct mips_cl_insn *ip; | |
6661 | { | |
6662 | int mask; | |
6663 | int xreg, yreg, zreg, tmp; | |
6664 | int icnt; | |
6665 | expressionS expr1; | |
6666 | int dbl; | |
6667 | const char *s, *s2, *s3; | |
6668 | ||
6669 | mask = ip->insn_mo->mask; | |
6670 | ||
6671 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
6672 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6673 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
6674 | ||
6675 | icnt = 0; | |
6676 | ||
6677 | expr1.X_op = O_constant; | |
6678 | expr1.X_op_symbol = NULL; | |
6679 | expr1.X_add_symbol = NULL; | |
6680 | expr1.X_add_number = 1; | |
6681 | ||
6682 | dbl = 0; | |
6683 | ||
6684 | switch (mask) | |
6685 | { | |
6686 | default: | |
6687 | internalError (); | |
6688 | ||
6689 | case M_DDIV_3: | |
6690 | dbl = 1; | |
6691 | case M_DIV_3: | |
6692 | s = "mflo"; | |
6693 | goto do_div3; | |
6694 | case M_DREM_3: | |
6695 | dbl = 1; | |
6696 | case M_REM_3: | |
6697 | s = "mfhi"; | |
6698 | do_div3: | |
6699 | mips_emit_delays (true); | |
6700 | ++mips_opts.noreorder; | |
6701 | mips_any_noreorder = 1; | |
6702 | macro_build ((char *) NULL, &icnt, NULL, | |
6703 | dbl ? "ddiv" : "div", | |
6704 | "0,x,y", xreg, yreg); | |
6705 | expr1.X_add_number = 2; | |
6706 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
beae10d5 | 6707 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
bdaaa2e1 | 6708 | |
252b5132 RH |
6709 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6710 | since that causes an overflow. We should do that as well, | |
6711 | but I don't see how to do the comparisons without a temporary | |
6712 | register. */ | |
6713 | --mips_opts.noreorder; | |
6714 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6715 | break; | |
6716 | ||
6717 | case M_DIVU_3: | |
6718 | s = "divu"; | |
6719 | s2 = "mflo"; | |
6720 | goto do_divu3; | |
6721 | case M_REMU_3: | |
6722 | s = "divu"; | |
6723 | s2 = "mfhi"; | |
6724 | goto do_divu3; | |
6725 | case M_DDIVU_3: | |
6726 | s = "ddivu"; | |
6727 | s2 = "mflo"; | |
6728 | goto do_divu3; | |
6729 | case M_DREMU_3: | |
6730 | s = "ddivu"; | |
6731 | s2 = "mfhi"; | |
6732 | do_divu3: | |
6733 | mips_emit_delays (true); | |
6734 | ++mips_opts.noreorder; | |
6735 | mips_any_noreorder = 1; | |
6736 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
6737 | expr1.X_add_number = 2; | |
6738 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6739 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6740 | --mips_opts.noreorder; | |
6741 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6742 | break; | |
6743 | ||
6744 | case M_DMUL: | |
6745 | dbl = 1; | |
6746 | case M_MUL: | |
6747 | macro_build ((char *) NULL, &icnt, NULL, | |
6748 | dbl ? "dmultu" : "multu", | |
6749 | "x,y", xreg, yreg); | |
6750 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6751 | return; | |
6752 | ||
6753 | case M_DSUBU_I: | |
6754 | dbl = 1; | |
6755 | goto do_subu; | |
6756 | case M_SUBU_I: | |
6757 | do_subu: | |
6758 | if (imm_expr.X_op != O_constant) | |
6759 | as_bad (_("Unsupported large constant")); | |
6760 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6761 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6762 | dbl ? "daddiu" : "addiu", | |
6763 | "y,x,4", yreg, xreg); | |
6764 | break; | |
6765 | ||
6766 | case M_SUBU_I_2: | |
6767 | if (imm_expr.X_op != O_constant) | |
6768 | as_bad (_("Unsupported large constant")); | |
6769 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6770 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6771 | "x,k", xreg); | |
6772 | break; | |
6773 | ||
6774 | case M_DSUBU_I_2: | |
6775 | if (imm_expr.X_op != O_constant) | |
6776 | as_bad (_("Unsupported large constant")); | |
6777 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6778 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6779 | "y,j", yreg); | |
6780 | break; | |
6781 | ||
6782 | case M_BEQ: | |
6783 | s = "cmp"; | |
6784 | s2 = "bteqz"; | |
6785 | goto do_branch; | |
6786 | case M_BNE: | |
6787 | s = "cmp"; | |
6788 | s2 = "btnez"; | |
6789 | goto do_branch; | |
6790 | case M_BLT: | |
6791 | s = "slt"; | |
6792 | s2 = "btnez"; | |
6793 | goto do_branch; | |
6794 | case M_BLTU: | |
6795 | s = "sltu"; | |
6796 | s2 = "btnez"; | |
6797 | goto do_branch; | |
6798 | case M_BLE: | |
6799 | s = "slt"; | |
6800 | s2 = "bteqz"; | |
6801 | goto do_reverse_branch; | |
6802 | case M_BLEU: | |
6803 | s = "sltu"; | |
6804 | s2 = "bteqz"; | |
6805 | goto do_reverse_branch; | |
6806 | case M_BGE: | |
6807 | s = "slt"; | |
6808 | s2 = "bteqz"; | |
6809 | goto do_branch; | |
6810 | case M_BGEU: | |
6811 | s = "sltu"; | |
6812 | s2 = "bteqz"; | |
6813 | goto do_branch; | |
6814 | case M_BGT: | |
6815 | s = "slt"; | |
6816 | s2 = "btnez"; | |
6817 | goto do_reverse_branch; | |
6818 | case M_BGTU: | |
6819 | s = "sltu"; | |
6820 | s2 = "btnez"; | |
6821 | ||
6822 | do_reverse_branch: | |
6823 | tmp = xreg; | |
6824 | xreg = yreg; | |
6825 | yreg = tmp; | |
6826 | ||
6827 | do_branch: | |
6828 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6829 | xreg, yreg); | |
6830 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6831 | break; | |
6832 | ||
6833 | case M_BEQ_I: | |
6834 | s = "cmpi"; | |
6835 | s2 = "bteqz"; | |
6836 | s3 = "x,U"; | |
6837 | goto do_branch_i; | |
6838 | case M_BNE_I: | |
6839 | s = "cmpi"; | |
6840 | s2 = "btnez"; | |
6841 | s3 = "x,U"; | |
6842 | goto do_branch_i; | |
6843 | case M_BLT_I: | |
6844 | s = "slti"; | |
6845 | s2 = "btnez"; | |
6846 | s3 = "x,8"; | |
6847 | goto do_branch_i; | |
6848 | case M_BLTU_I: | |
6849 | s = "sltiu"; | |
6850 | s2 = "btnez"; | |
6851 | s3 = "x,8"; | |
6852 | goto do_branch_i; | |
6853 | case M_BLE_I: | |
6854 | s = "slti"; | |
6855 | s2 = "btnez"; | |
6856 | s3 = "x,8"; | |
6857 | goto do_addone_branch_i; | |
6858 | case M_BLEU_I: | |
6859 | s = "sltiu"; | |
6860 | s2 = "btnez"; | |
6861 | s3 = "x,8"; | |
6862 | goto do_addone_branch_i; | |
6863 | case M_BGE_I: | |
6864 | s = "slti"; | |
6865 | s2 = "bteqz"; | |
6866 | s3 = "x,8"; | |
6867 | goto do_branch_i; | |
6868 | case M_BGEU_I: | |
6869 | s = "sltiu"; | |
6870 | s2 = "bteqz"; | |
6871 | s3 = "x,8"; | |
6872 | goto do_branch_i; | |
6873 | case M_BGT_I: | |
6874 | s = "slti"; | |
6875 | s2 = "bteqz"; | |
6876 | s3 = "x,8"; | |
6877 | goto do_addone_branch_i; | |
6878 | case M_BGTU_I: | |
6879 | s = "sltiu"; | |
6880 | s2 = "bteqz"; | |
6881 | s3 = "x,8"; | |
6882 | ||
6883 | do_addone_branch_i: | |
6884 | if (imm_expr.X_op != O_constant) | |
6885 | as_bad (_("Unsupported large constant")); | |
6886 | ++imm_expr.X_add_number; | |
6887 | ||
6888 | do_branch_i: | |
6889 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6890 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6891 | break; | |
6892 | ||
6893 | case M_ABS: | |
6894 | expr1.X_add_number = 0; | |
6895 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6896 | if (xreg != yreg) | |
6897 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6898 | "move", "y,X", xreg, yreg); | |
6899 | expr1.X_add_number = 2; | |
6900 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6901 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6902 | "neg", "x,w", xreg, xreg); | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | /* For consistency checking, verify that all bits are specified either | |
6907 | by the match/mask part of the instruction definition, or by the | |
6908 | operand list. */ | |
6909 | static int | |
6910 | validate_mips_insn (opc) | |
6911 | const struct mips_opcode *opc; | |
6912 | { | |
6913 | const char *p = opc->args; | |
6914 | char c; | |
6915 | unsigned long used_bits = opc->mask; | |
6916 | ||
6917 | if ((used_bits & opc->match) != opc->match) | |
6918 | { | |
6919 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
6920 | opc->name, opc->args); | |
6921 | return 0; | |
6922 | } | |
6923 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6924 | while (*p) | |
6925 | switch (c = *p++) | |
6926 | { | |
6927 | case ',': break; | |
6928 | case '(': break; | |
6929 | case ')': break; | |
6930 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6931 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6932 | case 'A': break; | |
4372b673 | 6933 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
6934 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
6935 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6936 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6937 | case 'F': break; | |
6938 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 6939 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 6940 | case 'I': break; |
e972090a | 6941 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
6942 | case 'L': break; |
6943 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6944 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6945 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6946 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6947 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6948 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6949 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6950 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6951 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6952 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6953 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6954 | case 'f': break; | |
6955 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6956 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6957 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6958 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6959 | case 'l': break; | |
6960 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6961 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6962 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
6963 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6964 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6965 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6966 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6967 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6968 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6969 | case 'x': break; | |
6970 | case 'z': break; | |
6971 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
6972 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
6973 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
6974 | default: |
6975 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
6976 | c, opc->name, opc->args); | |
6977 | return 0; | |
6978 | } | |
6979 | #undef USE_BITS | |
6980 | if (used_bits != 0xffffffff) | |
6981 | { | |
6982 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
6983 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6984 | return 0; | |
6985 | } | |
6986 | return 1; | |
6987 | } | |
6988 | ||
6989 | /* This routine assembles an instruction into its binary format. As a | |
6990 | side effect, it sets one of the global variables imm_reloc or | |
6991 | offset_reloc to the type of relocation to do if one of the operands | |
6992 | is an address expression. */ | |
6993 | ||
6994 | static void | |
6995 | mips_ip (str, ip) | |
6996 | char *str; | |
6997 | struct mips_cl_insn *ip; | |
6998 | { | |
6999 | char *s; | |
7000 | const char *args; | |
43841e91 | 7001 | char c = 0; |
252b5132 RH |
7002 | struct mips_opcode *insn; |
7003 | char *argsStart; | |
7004 | unsigned int regno; | |
7005 | unsigned int lastregno = 0; | |
7006 | char *s_reset; | |
7007 | char save_c = 0; | |
7008 | int full_opcode_match = 1; | |
7009 | ||
7010 | insn_error = NULL; | |
7011 | ||
7012 | /* If the instruction contains a '.', we first try to match an instruction | |
7013 | including the '.'. Then we try again without the '.'. */ | |
7014 | insn = NULL; | |
d9a62219 | 7015 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7016 | continue; |
7017 | ||
7018 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7019 | the call to hash_find. Save the character we replaced just in case we | |
7020 | have to re-parse the instruction. */ | |
d9a62219 | 7021 | if (isspace ((unsigned char) *s)) |
252b5132 RH |
7022 | { |
7023 | save_c = *s; | |
7024 | *s++ = '\0'; | |
7025 | } | |
bdaaa2e1 | 7026 | |
252b5132 RH |
7027 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7028 | ||
7029 | /* If we didn't find the instruction in the opcode table, try again, but | |
7030 | this time with just the instruction up to, but not including the | |
7031 | first '.'. */ | |
7032 | if (insn == NULL) | |
7033 | { | |
bdaaa2e1 | 7034 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7035 | if (save_c) |
7036 | *(--s) = save_c; | |
7037 | ||
7038 | /* Scan up to the first '.' or whitespace. */ | |
d9a62219 | 7039 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7040 | continue; |
7041 | ||
7042 | /* If we did not find a '.', then we can quit now. */ | |
7043 | if (*s != '.') | |
7044 | { | |
7045 | insn_error = "unrecognized opcode"; | |
7046 | return; | |
7047 | } | |
7048 | ||
7049 | /* Lookup the instruction in the hash table. */ | |
7050 | *s++ = '\0'; | |
7051 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7052 | { | |
7053 | insn_error = "unrecognized opcode"; | |
7054 | return; | |
7055 | } | |
7056 | ||
7057 | full_opcode_match = 0; | |
7058 | } | |
7059 | ||
7060 | argsStart = s; | |
7061 | for (;;) | |
7062 | { | |
252b5132 RH |
7063 | boolean ok; |
7064 | ||
7065 | assert (strcmp (insn->name, str) == 0); | |
7066 | ||
c97ef257 | 7067 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu, mips_gp32)) |
252b5132 | 7068 | ok = true; |
bdaaa2e1 | 7069 | else |
252b5132 | 7070 | ok = false; |
bdaaa2e1 | 7071 | |
252b5132 RH |
7072 | if (insn->pinfo != INSN_MACRO) |
7073 | { | |
156c2f8b | 7074 | if (mips_cpu == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7075 | ok = false; |
7076 | } | |
7077 | ||
7078 | if (! ok) | |
7079 | { | |
7080 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7081 | && strcmp (insn->name, insn[1].name) == 0) | |
7082 | { | |
7083 | ++insn; | |
7084 | continue; | |
7085 | } | |
252b5132 | 7086 | else |
beae10d5 | 7087 | { |
252b5132 | 7088 | static char buf[100]; |
bdaaa2e1 | 7089 | sprintf (buf, |
e7af610e NC |
7090 | _("opcode not supported on this processor: %s (%s)"), |
7091 | mips_cpu_to_str (mips_cpu), | |
7092 | mips_isa_to_str (mips_opts.isa)); | |
bdaaa2e1 | 7093 | |
252b5132 | 7094 | insn_error = buf; |
2bd7f1f3 | 7095 | return; |
252b5132 | 7096 | } |
252b5132 RH |
7097 | } |
7098 | ||
7099 | ip->insn_mo = insn; | |
7100 | ip->insn_opcode = insn->match; | |
7101 | for (args = insn->args;; ++args) | |
7102 | { | |
7103 | if (*s == ' ') | |
7104 | ++s; | |
7105 | switch (*args) | |
7106 | { | |
7107 | case '\0': /* end of args */ | |
7108 | if (*s == '\0') | |
7109 | return; | |
7110 | break; | |
7111 | ||
7112 | case ',': | |
7113 | if (*s++ == *args) | |
7114 | continue; | |
7115 | s--; | |
7116 | switch (*++args) | |
7117 | { | |
7118 | case 'r': | |
7119 | case 'v': | |
7120 | ip->insn_opcode |= lastregno << 21; | |
7121 | continue; | |
7122 | ||
7123 | case 'w': | |
7124 | case 'W': | |
7125 | ip->insn_opcode |= lastregno << 16; | |
7126 | continue; | |
7127 | ||
7128 | case 'V': | |
7129 | ip->insn_opcode |= lastregno << 11; | |
7130 | continue; | |
7131 | } | |
7132 | break; | |
7133 | ||
7134 | case '(': | |
7135 | /* Handle optional base register. | |
7136 | Either the base register is omitted or | |
bdaaa2e1 | 7137 | we must have a left paren. */ |
252b5132 RH |
7138 | /* This is dependent on the next operand specifier |
7139 | is a base register specification. */ | |
7140 | assert (args[1] == 'b' || args[1] == '5' | |
7141 | || args[1] == '-' || args[1] == '4'); | |
7142 | if (*s == '\0') | |
7143 | return; | |
7144 | ||
7145 | case ')': /* these must match exactly */ | |
7146 | if (*s++ == *args) | |
7147 | continue; | |
7148 | break; | |
7149 | ||
7150 | case '<': /* must be at least one digit */ | |
7151 | /* | |
7152 | * According to the manual, if the shift amount is greater | |
7153 | * than 31 or less than 0 the the shift amount should be | |
7154 | * mod 32. In reality the mips assembler issues an error. | |
7155 | * We issue a warning and mask out all but the low 5 bits. | |
7156 | */ | |
7157 | my_getExpression (&imm_expr, s); | |
7158 | check_absolute_expr (ip, &imm_expr); | |
7159 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7160 | { | |
7161 | as_warn (_("Improper shift amount (%ld)"), | |
7162 | (long) imm_expr.X_add_number); | |
7163 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; | |
7164 | } | |
7165 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7166 | imm_expr.X_op = O_absent; | |
7167 | s = expr_end; | |
7168 | continue; | |
7169 | ||
7170 | case '>': /* shift amount minus 32 */ | |
7171 | my_getExpression (&imm_expr, s); | |
7172 | check_absolute_expr (ip, &imm_expr); | |
7173 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7174 | || (unsigned long) imm_expr.X_add_number > 63) | |
7175 | break; | |
7176 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7177 | imm_expr.X_op = O_absent; | |
7178 | s = expr_end; | |
7179 | continue; | |
7180 | ||
252b5132 RH |
7181 | case 'k': /* cache code */ |
7182 | case 'h': /* prefx code */ | |
7183 | my_getExpression (&imm_expr, s); | |
7184 | check_absolute_expr (ip, &imm_expr); | |
7185 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7186 | { | |
7187 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7188 | ip->insn_mo->name, | |
7189 | (unsigned long) imm_expr.X_add_number); | |
7190 | imm_expr.X_add_number &= 0x1f; | |
7191 | } | |
7192 | if (*args == 'k') | |
7193 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7194 | else | |
7195 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7196 | imm_expr.X_op = O_absent; | |
7197 | s = expr_end; | |
7198 | continue; | |
7199 | ||
7200 | case 'c': /* break code */ | |
7201 | my_getExpression (&imm_expr, s); | |
7202 | check_absolute_expr (ip, &imm_expr); | |
7203 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7204 | { | |
7205 | as_warn (_("Illegal break code (%ld)"), | |
7206 | (long) imm_expr.X_add_number); | |
7207 | imm_expr.X_add_number &= 0x3ff; | |
7208 | } | |
7209 | ip->insn_opcode |= imm_expr.X_add_number << 16; | |
7210 | imm_expr.X_op = O_absent; | |
7211 | s = expr_end; | |
7212 | continue; | |
7213 | ||
7214 | case 'q': /* lower break code */ | |
7215 | my_getExpression (&imm_expr, s); | |
7216 | check_absolute_expr (ip, &imm_expr); | |
7217 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7218 | { | |
7219 | as_warn (_("Illegal lower break code (%ld)"), | |
7220 | (long) imm_expr.X_add_number); | |
7221 | imm_expr.X_add_number &= 0x3ff; | |
7222 | } | |
7223 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7224 | imm_expr.X_op = O_absent; | |
7225 | s = expr_end; | |
7226 | continue; | |
7227 | ||
4372b673 | 7228 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7229 | my_getExpression (&imm_expr, s); |
156c2f8b | 7230 | check_absolute_expr (ip, &imm_expr); |
156c2f8b | 7231 | if ((unsigned) imm_expr.X_add_number > 0xfffff) |
4372b673 | 7232 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 RH |
7233 | (long) imm_expr.X_add_number); |
7234 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7235 | imm_expr.X_op = O_absent; | |
7236 | s = expr_end; | |
7237 | continue; | |
7238 | ||
7239 | case 'C': /* Coprocessor code */ | |
beae10d5 | 7240 | my_getExpression (&imm_expr, s); |
252b5132 | 7241 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7242 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
252b5132 | 7243 | { |
beae10d5 | 7244 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7245 | (long) imm_expr.X_add_number); |
beae10d5 | 7246 | imm_expr.X_add_number &= ((1<<25) - 1); |
252b5132 | 7247 | } |
beae10d5 KH |
7248 | ip->insn_opcode |= imm_expr.X_add_number; |
7249 | imm_expr.X_op = O_absent; | |
7250 | s = expr_end; | |
7251 | continue; | |
252b5132 | 7252 | |
4372b673 NC |
7253 | case 'J': /* 19-bit wait code. */ |
7254 | my_getExpression (&imm_expr, s); | |
7255 | check_absolute_expr (ip, &imm_expr); | |
7256 | if ((unsigned) imm_expr.X_add_number > 0x7ffff) | |
7257 | as_warn (_("Illegal 19-bit code (%ld)"), | |
7258 | (long) imm_expr.X_add_number); | |
7259 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7260 | imm_expr.X_op = O_absent; | |
7261 | s = expr_end; | |
7262 | continue; | |
7263 | ||
252b5132 | 7264 | case 'P': /* Performance register */ |
beae10d5 | 7265 | my_getExpression (&imm_expr, s); |
252b5132 | 7266 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7267 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 7268 | { |
beae10d5 | 7269 | as_warn (_("Invalidate performance regster (%ld)"), |
252b5132 | 7270 | (long) imm_expr.X_add_number); |
beae10d5 | 7271 | imm_expr.X_add_number &= 1; |
252b5132 | 7272 | } |
beae10d5 KH |
7273 | ip->insn_opcode |= (imm_expr.X_add_number << 1); |
7274 | imm_expr.X_op = O_absent; | |
7275 | s = expr_end; | |
7276 | continue; | |
252b5132 RH |
7277 | |
7278 | case 'b': /* base register */ | |
7279 | case 'd': /* destination register */ | |
7280 | case 's': /* source register */ | |
7281 | case 't': /* target register */ | |
7282 | case 'r': /* both target and source */ | |
7283 | case 'v': /* both dest and source */ | |
7284 | case 'w': /* both dest and target */ | |
7285 | case 'E': /* coprocessor target register */ | |
7286 | case 'G': /* coprocessor destination register */ | |
7287 | case 'x': /* ignore register name */ | |
7288 | case 'z': /* must be zero register */ | |
4372b673 | 7289 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
7290 | s_reset = s; |
7291 | if (s[0] == '$') | |
7292 | { | |
7293 | ||
d9a62219 | 7294 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
7295 | { |
7296 | ++s; | |
7297 | regno = 0; | |
7298 | do | |
7299 | { | |
7300 | regno *= 10; | |
7301 | regno += *s - '0'; | |
7302 | ++s; | |
7303 | } | |
d9a62219 | 7304 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7305 | if (regno > 31) |
7306 | as_bad (_("Invalid register number (%d)"), regno); | |
7307 | } | |
7308 | else if (*args == 'E' || *args == 'G') | |
7309 | goto notreg; | |
7310 | else | |
7311 | { | |
7312 | if (s[1] == 'f' && s[2] == 'p') | |
7313 | { | |
7314 | s += 3; | |
7315 | regno = FP; | |
7316 | } | |
7317 | else if (s[1] == 's' && s[2] == 'p') | |
7318 | { | |
7319 | s += 3; | |
7320 | regno = SP; | |
7321 | } | |
7322 | else if (s[1] == 'g' && s[2] == 'p') | |
7323 | { | |
7324 | s += 3; | |
7325 | regno = GP; | |
7326 | } | |
7327 | else if (s[1] == 'a' && s[2] == 't') | |
7328 | { | |
7329 | s += 3; | |
7330 | regno = AT; | |
7331 | } | |
7332 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7333 | { | |
7334 | s += 4; | |
7335 | regno = KT0; | |
7336 | } | |
7337 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7338 | { | |
7339 | s += 4; | |
7340 | regno = KT1; | |
7341 | } | |
7342 | else if (itbl_have_entries) | |
7343 | { | |
7344 | char *p, *n; | |
d7ba4a77 | 7345 | unsigned long r; |
252b5132 | 7346 | |
d7ba4a77 | 7347 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7348 | n = itbl_get_field (&p); /* n is name */ |
7349 | ||
d7ba4a77 ILT |
7350 | /* See if this is a register defined in an |
7351 | itbl entry. */ | |
7352 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7353 | { |
7354 | /* Get_field advances to the start of | |
7355 | the next field, so we need to back | |
d7ba4a77 | 7356 | rack to the end of the last field. */ |
bdaaa2e1 | 7357 | if (p) |
252b5132 | 7358 | s = p - 1; |
bdaaa2e1 | 7359 | else |
d7ba4a77 | 7360 | s = strchr (s, '\0'); |
252b5132 RH |
7361 | regno = r; |
7362 | } | |
7363 | else | |
7364 | goto notreg; | |
beae10d5 | 7365 | } |
252b5132 RH |
7366 | else |
7367 | goto notreg; | |
7368 | } | |
7369 | if (regno == AT | |
7370 | && ! mips_opts.noat | |
7371 | && *args != 'E' | |
7372 | && *args != 'G') | |
7373 | as_warn (_("Used $at without \".set noat\"")); | |
7374 | c = *args; | |
7375 | if (*s == ' ') | |
7376 | s++; | |
7377 | if (args[1] != *s) | |
7378 | { | |
7379 | if (c == 'r' || c == 'v' || c == 'w') | |
7380 | { | |
7381 | regno = lastregno; | |
7382 | s = s_reset; | |
7383 | args++; | |
7384 | } | |
7385 | } | |
7386 | /* 'z' only matches $0. */ | |
7387 | if (c == 'z' && regno != 0) | |
7388 | break; | |
7389 | ||
bdaaa2e1 KH |
7390 | /* Now that we have assembled one operand, we use the args string |
7391 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
7392 | switch (c) |
7393 | { | |
7394 | case 'r': | |
7395 | case 's': | |
7396 | case 'v': | |
7397 | case 'b': | |
7398 | ip->insn_opcode |= regno << 21; | |
7399 | break; | |
7400 | case 'd': | |
7401 | case 'G': | |
7402 | ip->insn_opcode |= regno << 11; | |
7403 | break; | |
4372b673 NC |
7404 | case 'U': |
7405 | ip->insn_opcode |= regno << 11; | |
7406 | ip->insn_opcode |= regno << 16; | |
7407 | break; | |
252b5132 RH |
7408 | case 'w': |
7409 | case 't': | |
7410 | case 'E': | |
7411 | ip->insn_opcode |= regno << 16; | |
7412 | break; | |
7413 | case 'x': | |
7414 | /* This case exists because on the r3000 trunc | |
7415 | expands into a macro which requires a gp | |
7416 | register. On the r6000 or r4000 it is | |
7417 | assembled into a single instruction which | |
7418 | ignores the register. Thus the insn version | |
7419 | is MIPS_ISA2 and uses 'x', and the macro | |
7420 | version is MIPS_ISA1 and uses 't'. */ | |
7421 | break; | |
7422 | case 'z': | |
7423 | /* This case is for the div instruction, which | |
7424 | acts differently if the destination argument | |
7425 | is $0. This only matches $0, and is checked | |
7426 | outside the switch. */ | |
7427 | break; | |
7428 | case 'D': | |
7429 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7430 | break; | |
7431 | /* What about all other operands like 'i', which | |
7432 | can be specified in the opcode table? */ | |
7433 | } | |
7434 | lastregno = regno; | |
7435 | continue; | |
7436 | } | |
7437 | notreg: | |
7438 | switch (*args++) | |
7439 | { | |
7440 | case 'r': | |
7441 | case 'v': | |
7442 | ip->insn_opcode |= lastregno << 21; | |
7443 | continue; | |
7444 | case 'w': | |
7445 | ip->insn_opcode |= lastregno << 16; | |
7446 | continue; | |
7447 | } | |
7448 | break; | |
7449 | ||
7450 | case 'D': /* floating point destination register */ | |
7451 | case 'S': /* floating point source register */ | |
7452 | case 'T': /* floating point target register */ | |
7453 | case 'R': /* floating point source register */ | |
7454 | case 'V': | |
7455 | case 'W': | |
7456 | s_reset = s; | |
d9a62219 | 7457 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
252b5132 RH |
7458 | { |
7459 | s += 2; | |
7460 | regno = 0; | |
7461 | do | |
7462 | { | |
7463 | regno *= 10; | |
7464 | regno += *s - '0'; | |
7465 | ++s; | |
7466 | } | |
d9a62219 | 7467 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7468 | |
7469 | if (regno > 31) | |
7470 | as_bad (_("Invalid float register number (%d)"), regno); | |
7471 | ||
7472 | if ((regno & 1) != 0 | |
9ce8a5dd | 7473 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7474 | && ! (strcmp (str, "mtc1") == 0 |
7475 | || strcmp (str, "mfc1") == 0 | |
7476 | || strcmp (str, "lwc1") == 0 | |
7477 | || strcmp (str, "swc1") == 0 | |
7478 | || strcmp (str, "l.s") == 0 | |
7479 | || strcmp (str, "s.s") == 0)) | |
7480 | as_warn (_("Float register should be even, was %d"), | |
7481 | regno); | |
7482 | ||
7483 | c = *args; | |
7484 | if (*s == ' ') | |
7485 | s++; | |
7486 | if (args[1] != *s) | |
7487 | { | |
7488 | if (c == 'V' || c == 'W') | |
7489 | { | |
7490 | regno = lastregno; | |
7491 | s = s_reset; | |
7492 | args++; | |
7493 | } | |
7494 | } | |
7495 | switch (c) | |
7496 | { | |
7497 | case 'D': | |
7498 | ip->insn_opcode |= regno << 6; | |
7499 | break; | |
7500 | case 'V': | |
7501 | case 'S': | |
7502 | ip->insn_opcode |= regno << 11; | |
7503 | break; | |
7504 | case 'W': | |
7505 | case 'T': | |
7506 | ip->insn_opcode |= regno << 16; | |
7507 | break; | |
7508 | case 'R': | |
7509 | ip->insn_opcode |= regno << 21; | |
7510 | break; | |
7511 | } | |
7512 | lastregno = regno; | |
7513 | continue; | |
7514 | } | |
7515 | ||
252b5132 RH |
7516 | switch (*args++) |
7517 | { | |
7518 | case 'V': | |
7519 | ip->insn_opcode |= lastregno << 11; | |
7520 | continue; | |
7521 | case 'W': | |
7522 | ip->insn_opcode |= lastregno << 16; | |
7523 | continue; | |
7524 | } | |
7525 | break; | |
7526 | ||
7527 | case 'I': | |
7528 | my_getExpression (&imm_expr, s); | |
7529 | if (imm_expr.X_op != O_big | |
7530 | && imm_expr.X_op != O_constant) | |
7531 | insn_error = _("absolute expression required"); | |
7532 | s = expr_end; | |
7533 | continue; | |
7534 | ||
7535 | case 'A': | |
7536 | my_getExpression (&offset_expr, s); | |
7537 | imm_reloc = BFD_RELOC_32; | |
7538 | s = expr_end; | |
7539 | continue; | |
7540 | ||
7541 | case 'F': | |
7542 | case 'L': | |
7543 | case 'f': | |
7544 | case 'l': | |
7545 | { | |
7546 | int f64; | |
7547 | char *save_in; | |
7548 | char *err; | |
7549 | unsigned char temp[8]; | |
7550 | int len; | |
7551 | unsigned int length; | |
7552 | segT seg; | |
7553 | subsegT subseg; | |
7554 | char *p; | |
7555 | ||
7556 | /* These only appear as the last operand in an | |
7557 | instruction, and every instruction that accepts | |
7558 | them in any variant accepts them in all variants. | |
7559 | This means we don't have to worry about backing out | |
7560 | any changes if the instruction does not match. | |
7561 | ||
7562 | The difference between them is the size of the | |
7563 | floating point constant and where it goes. For 'F' | |
7564 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7565 | is 32 bits. Where the constant is placed is based | |
7566 | on how the MIPS assembler does things: | |
7567 | F -- .rdata | |
7568 | L -- .lit8 | |
7569 | f -- immediate value | |
7570 | l -- .lit4 | |
7571 | ||
7572 | The .lit4 and .lit8 sections are only used if | |
7573 | permitted by the -G argument. | |
7574 | ||
7575 | When generating embedded PIC code, we use the | |
7576 | .lit8 section but not the .lit4 section (we can do | |
7577 | .lit4 inline easily; we need to put .lit8 | |
7578 | somewhere in the data segment, and using .lit8 | |
7579 | permits the linker to eventually combine identical | |
7580 | .lit8 entries). */ | |
7581 | ||
7582 | f64 = *args == 'F' || *args == 'L'; | |
7583 | ||
7584 | save_in = input_line_pointer; | |
7585 | input_line_pointer = s; | |
7586 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7587 | length = len; | |
7588 | s = input_line_pointer; | |
7589 | input_line_pointer = save_in; | |
7590 | if (err != NULL && *err != '\0') | |
7591 | { | |
7592 | as_bad (_("Bad floating point constant: %s"), err); | |
7593 | memset (temp, '\0', sizeof temp); | |
7594 | length = f64 ? 8 : 4; | |
7595 | } | |
7596 | ||
156c2f8b | 7597 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
7598 | |
7599 | if (*args == 'f' | |
7600 | || (*args == 'l' | |
7601 | && (! USE_GLOBAL_POINTER_OPT | |
7602 | || mips_pic == EMBEDDED_PIC | |
7603 | || g_switch_value < 4 | |
7604 | || (temp[0] == 0 && temp[1] == 0) | |
7605 | || (temp[2] == 0 && temp[3] == 0)))) | |
7606 | { | |
7607 | imm_expr.X_op = O_constant; | |
7608 | if (! target_big_endian) | |
7609 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7610 | else | |
7611 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7612 | } | |
7613 | else if (length > 4 | |
119d663a | 7614 | && ! mips_disable_float_construction |
252b5132 RH |
7615 | && ((temp[0] == 0 && temp[1] == 0) |
7616 | || (temp[2] == 0 && temp[3] == 0)) | |
7617 | && ((temp[4] == 0 && temp[5] == 0) | |
7618 | || (temp[6] == 0 && temp[7] == 0))) | |
7619 | { | |
7620 | /* The value is simple enough to load with a | |
7621 | couple of instructions. In mips1 mode, set | |
7622 | imm_expr to the high order 32 bits and | |
7623 | offset_expr to the low order 32 bits. | |
7624 | Otherwise, set imm_expr to the entire 64 bit | |
7625 | constant. */ | |
9ce8a5dd | 7626 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
7627 | { |
7628 | imm_expr.X_op = O_constant; | |
7629 | offset_expr.X_op = O_constant; | |
7630 | if (! target_big_endian) | |
7631 | { | |
7632 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7633 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7634 | } | |
7635 | else | |
7636 | { | |
7637 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7638 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7639 | } | |
7640 | if (offset_expr.X_add_number == 0) | |
7641 | offset_expr.X_op = O_absent; | |
7642 | } | |
7643 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7644 | { | |
7645 | imm_expr.X_op = O_constant; | |
7646 | if (! target_big_endian) | |
7647 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7648 | else | |
7649 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7650 | } | |
7651 | else | |
7652 | { | |
7653 | imm_expr.X_op = O_big; | |
7654 | imm_expr.X_add_number = 4; | |
7655 | if (! target_big_endian) | |
7656 | { | |
7657 | generic_bignum[0] = bfd_getl16 (temp); | |
7658 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7659 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7660 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7661 | } | |
7662 | else | |
7663 | { | |
7664 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7665 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7666 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7667 | generic_bignum[3] = bfd_getb16 (temp); | |
7668 | } | |
7669 | } | |
7670 | } | |
7671 | else | |
7672 | { | |
7673 | const char *newname; | |
7674 | segT new_seg; | |
7675 | ||
7676 | /* Switch to the right section. */ | |
7677 | seg = now_seg; | |
7678 | subseg = now_subseg; | |
7679 | switch (*args) | |
7680 | { | |
7681 | default: /* unused default case avoids warnings. */ | |
7682 | case 'L': | |
7683 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
7684 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
7685 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
7686 | newname = ".lit8"; |
7687 | break; | |
7688 | case 'F': | |
bb2d6cd7 GK |
7689 | if (mips_pic == EMBEDDED_PIC) |
7690 | newname = ".lit8"; | |
7691 | else | |
7692 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
7693 | break; |
7694 | case 'l': | |
7695 | assert (!USE_GLOBAL_POINTER_OPT | |
7696 | || g_switch_value >= 4); | |
7697 | newname = ".lit4"; | |
7698 | break; | |
7699 | } | |
7700 | new_seg = subseg_new (newname, (subsegT) 0); | |
7701 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7702 | bfd_set_section_flags (stdoutput, new_seg, | |
7703 | (SEC_ALLOC | |
7704 | | SEC_LOAD | |
7705 | | SEC_READONLY | |
7706 | | SEC_DATA)); | |
7707 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
7708 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7709 | && strcmp (TARGET_OS, "elf") != 0) | |
7710 | record_alignment (new_seg, 4); | |
7711 | else | |
7712 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
7713 | if (seg == now_seg) | |
7714 | as_bad (_("Can't use floating point insn in this section")); | |
7715 | ||
7716 | /* Set the argument to the current address in the | |
7717 | section. */ | |
7718 | offset_expr.X_op = O_symbol; | |
7719 | offset_expr.X_add_symbol = | |
7720 | symbol_new ("L0\001", now_seg, | |
7721 | (valueT) frag_now_fix (), frag_now); | |
7722 | offset_expr.X_add_number = 0; | |
7723 | ||
7724 | /* Put the floating point number into the section. */ | |
7725 | p = frag_more ((int) length); | |
7726 | memcpy (p, temp, length); | |
7727 | ||
7728 | /* Switch back to the original section. */ | |
7729 | subseg_set (seg, subseg); | |
7730 | } | |
7731 | } | |
7732 | continue; | |
7733 | ||
7734 | case 'i': /* 16 bit unsigned immediate */ | |
7735 | case 'j': /* 16 bit signed immediate */ | |
7736 | imm_reloc = BFD_RELOC_LO16; | |
7737 | c = my_getSmallExpression (&imm_expr, s); | |
7738 | if (c != '\0') | |
7739 | { | |
7740 | if (c != 'l') | |
7741 | { | |
7742 | if (imm_expr.X_op == O_constant) | |
7743 | imm_expr.X_add_number = | |
7744 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7745 | else if (c == 'h') | |
7746 | { | |
7747 | imm_reloc = BFD_RELOC_HI16_S; | |
7748 | imm_unmatched_hi = true; | |
7749 | } | |
7750 | else | |
7751 | imm_reloc = BFD_RELOC_HI16; | |
7752 | } | |
7753 | else if (imm_expr.X_op == O_constant) | |
7754 | imm_expr.X_add_number &= 0xffff; | |
7755 | } | |
7756 | if (*args == 'i') | |
7757 | { | |
7758 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7759 | || ((imm_expr.X_add_number < 0 | |
beae10d5 KH |
7760 | || imm_expr.X_add_number >= 0x10000) |
7761 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
7762 | { |
7763 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7764 | !strcmp (insn->name, insn[1].name)) | |
7765 | break; | |
2ae7e77b AH |
7766 | if (imm_expr.X_op == O_constant |
7767 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7768 | as_bad (_("16 bit expression not in range 0..65535")); |
7769 | } | |
7770 | } | |
7771 | else | |
7772 | { | |
7773 | int more; | |
7774 | offsetT max; | |
7775 | ||
7776 | /* The upper bound should be 0x8000, but | |
7777 | unfortunately the MIPS assembler accepts numbers | |
7778 | from 0x8000 to 0xffff and sign extends them, and | |
7779 | we want to be compatible. We only permit this | |
7780 | extended range for an instruction which does not | |
7781 | provide any further alternates, since those | |
7782 | alternates may handle other cases. People should | |
7783 | use the numbers they mean, rather than relying on | |
7784 | a mysterious sign extension. */ | |
7785 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7786 | strcmp (insn->name, insn[1].name) == 0); | |
7787 | if (more) | |
7788 | max = 0x8000; | |
7789 | else | |
7790 | max = 0x10000; | |
7791 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7792 | || ((imm_expr.X_add_number < -0x8000 | |
beae10d5 KH |
7793 | || imm_expr.X_add_number >= max) |
7794 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
7795 | || (more |
7796 | && imm_expr.X_add_number < 0 | |
9ce8a5dd | 7797 | && ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7798 | && imm_expr.X_unsigned |
7799 | && sizeof (imm_expr.X_add_number) <= 4)) | |
7800 | { | |
7801 | if (more) | |
7802 | break; | |
2ae7e77b AH |
7803 | if (imm_expr.X_op == O_constant |
7804 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7805 | as_bad (_("16 bit expression not in range -32768..32767")); |
7806 | } | |
7807 | } | |
7808 | s = expr_end; | |
7809 | continue; | |
7810 | ||
7811 | case 'o': /* 16 bit offset */ | |
7812 | c = my_getSmallExpression (&offset_expr, s); | |
7813 | ||
7814 | /* If this value won't fit into a 16 bit offset, then go | |
7815 | find a macro that will generate the 32 bit offset | |
7816 | code pattern. As a special hack, we accept the | |
7817 | difference of two local symbols as a constant. This | |
7818 | is required to suppose embedded PIC switches, which | |
7819 | use an instruction which looks like | |
7820 | lw $4,$L12-$LS12($4) | |
7821 | The problem with handling this in a more general | |
7822 | fashion is that the macro function doesn't expect to | |
7823 | see anything which can be handled in a single | |
7824 | constant instruction. */ | |
7825 | if (c == 0 | |
7826 | && (offset_expr.X_op != O_constant | |
7827 | || offset_expr.X_add_number >= 0x8000 | |
7828 | || offset_expr.X_add_number < -0x8000) | |
7829 | && (mips_pic != EMBEDDED_PIC | |
7830 | || offset_expr.X_op != O_subtract | |
3dacdf2e NC |
7831 | || (S_GET_SEGMENT (offset_expr.X_add_symbol) |
7832 | != S_GET_SEGMENT (offset_expr.X_op_symbol)))) | |
252b5132 RH |
7833 | break; |
7834 | ||
7835 | if (c == 'h' || c == 'H') | |
7836 | { | |
7837 | if (offset_expr.X_op != O_constant) | |
7838 | break; | |
7839 | offset_expr.X_add_number = | |
7840 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7841 | } | |
7842 | offset_reloc = BFD_RELOC_LO16; | |
7843 | s = expr_end; | |
7844 | continue; | |
7845 | ||
7846 | case 'p': /* pc relative offset */ | |
7847 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7848 | my_getExpression (&offset_expr, s); | |
7849 | s = expr_end; | |
7850 | continue; | |
7851 | ||
7852 | case 'u': /* upper 16 bits */ | |
7853 | c = my_getSmallExpression (&imm_expr, s); | |
7854 | imm_reloc = BFD_RELOC_LO16; | |
7855 | if (c) | |
7856 | { | |
7857 | if (c != 'l') | |
7858 | { | |
7859 | if (imm_expr.X_op == O_constant) | |
7860 | imm_expr.X_add_number = | |
7861 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7862 | else if (c == 'h') | |
7863 | { | |
7864 | imm_reloc = BFD_RELOC_HI16_S; | |
7865 | imm_unmatched_hi = true; | |
7866 | } | |
7867 | else | |
7868 | imm_reloc = BFD_RELOC_HI16; | |
7869 | } | |
7870 | else if (imm_expr.X_op == O_constant) | |
7871 | imm_expr.X_add_number &= 0xffff; | |
7872 | } | |
7873 | if (imm_expr.X_op == O_constant | |
7874 | && (imm_expr.X_add_number < 0 | |
7875 | || imm_expr.X_add_number >= 0x10000)) | |
7876 | as_bad (_("lui expression not in range 0..65535")); | |
7877 | s = expr_end; | |
7878 | continue; | |
7879 | ||
7880 | case 'a': /* 26 bit address */ | |
7881 | my_getExpression (&offset_expr, s); | |
7882 | s = expr_end; | |
7883 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7884 | continue; | |
7885 | ||
7886 | case 'N': /* 3 bit branch condition code */ | |
7887 | case 'M': /* 3 bit compare condition code */ | |
7888 | if (strncmp (s, "$fcc", 4) != 0) | |
7889 | break; | |
7890 | s += 4; | |
7891 | regno = 0; | |
7892 | do | |
7893 | { | |
7894 | regno *= 10; | |
7895 | regno += *s - '0'; | |
7896 | ++s; | |
7897 | } | |
d9a62219 | 7898 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7899 | if (regno > 7) |
7900 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
7901 | if (*args == 'N') | |
7902 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7903 | else | |
7904 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 7905 | continue; |
252b5132 | 7906 | |
156c2f8b NC |
7907 | case 'H': |
7908 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
7909 | s += 2; | |
7910 | if (isdigit ((unsigned char) *s)) | |
7911 | { | |
7912 | c = 0; | |
7913 | do | |
7914 | { | |
7915 | c *= 10; | |
7916 | c += *s - '0'; | |
7917 | ++s; | |
7918 | } | |
7919 | while (isdigit ((unsigned char) *s)); | |
7920 | } | |
7921 | else | |
7922 | c = 8; /* Invalid sel value. */ | |
7923 | ||
7924 | if (c > 7) | |
7925 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
7926 | ip->insn_opcode |= c; | |
7927 | continue; | |
7928 | ||
252b5132 RH |
7929 | default: |
7930 | as_bad (_("bad char = '%c'\n"), *args); | |
7931 | internalError (); | |
7932 | } | |
7933 | break; | |
7934 | } | |
7935 | /* Args don't match. */ | |
7936 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7937 | !strcmp (insn->name, insn[1].name)) | |
7938 | { | |
7939 | ++insn; | |
7940 | s = argsStart; | |
7941 | continue; | |
7942 | } | |
7943 | insn_error = _("illegal operands"); | |
7944 | return; | |
7945 | } | |
7946 | } | |
7947 | ||
7948 | /* This routine assembles an instruction into its binary format when | |
7949 | assembling for the mips16. As a side effect, it sets one of the | |
7950 | global variables imm_reloc or offset_reloc to the type of | |
7951 | relocation to do if one of the operands is an address expression. | |
7952 | It also sets mips16_small and mips16_ext if the user explicitly | |
7953 | requested a small or extended instruction. */ | |
7954 | ||
7955 | static void | |
7956 | mips16_ip (str, ip) | |
7957 | char *str; | |
7958 | struct mips_cl_insn *ip; | |
7959 | { | |
7960 | char *s; | |
7961 | const char *args; | |
7962 | struct mips_opcode *insn; | |
7963 | char *argsstart; | |
7964 | unsigned int regno; | |
7965 | unsigned int lastregno = 0; | |
7966 | char *s_reset; | |
7967 | ||
7968 | insn_error = NULL; | |
7969 | ||
7970 | mips16_small = false; | |
7971 | mips16_ext = false; | |
7972 | ||
d9a62219 | 7973 | for (s = str; islower ((unsigned char) *s); ++s) |
252b5132 RH |
7974 | ; |
7975 | switch (*s) | |
7976 | { | |
7977 | case '\0': | |
7978 | break; | |
7979 | ||
7980 | case ' ': | |
7981 | *s++ = '\0'; | |
7982 | break; | |
7983 | ||
7984 | case '.': | |
7985 | if (s[1] == 't' && s[2] == ' ') | |
7986 | { | |
7987 | *s = '\0'; | |
7988 | mips16_small = true; | |
7989 | s += 3; | |
7990 | break; | |
7991 | } | |
7992 | else if (s[1] == 'e' && s[2] == ' ') | |
7993 | { | |
7994 | *s = '\0'; | |
7995 | mips16_ext = true; | |
7996 | s += 3; | |
7997 | break; | |
7998 | } | |
7999 | /* Fall through. */ | |
8000 | default: | |
8001 | insn_error = _("unknown opcode"); | |
8002 | return; | |
8003 | } | |
8004 | ||
8005 | if (mips_opts.noautoextend && ! mips16_ext) | |
8006 | mips16_small = true; | |
8007 | ||
8008 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8009 | { | |
8010 | insn_error = _("unrecognized opcode"); | |
8011 | return; | |
8012 | } | |
8013 | ||
8014 | argsstart = s; | |
8015 | for (;;) | |
8016 | { | |
8017 | assert (strcmp (insn->name, str) == 0); | |
8018 | ||
8019 | ip->insn_mo = insn; | |
8020 | ip->insn_opcode = insn->match; | |
8021 | ip->use_extend = false; | |
8022 | imm_expr.X_op = O_absent; | |
8023 | imm_reloc = BFD_RELOC_UNUSED; | |
8024 | offset_expr.X_op = O_absent; | |
8025 | offset_reloc = BFD_RELOC_UNUSED; | |
8026 | for (args = insn->args; 1; ++args) | |
8027 | { | |
8028 | int c; | |
8029 | ||
8030 | if (*s == ' ') | |
8031 | ++s; | |
8032 | ||
8033 | /* In this switch statement we call break if we did not find | |
8034 | a match, continue if we did find a match, or return if we | |
8035 | are done. */ | |
8036 | ||
8037 | c = *args; | |
8038 | switch (c) | |
8039 | { | |
8040 | case '\0': | |
8041 | if (*s == '\0') | |
8042 | { | |
8043 | /* Stuff the immediate value in now, if we can. */ | |
8044 | if (imm_expr.X_op == O_constant | |
8045 | && imm_reloc > BFD_RELOC_UNUSED | |
8046 | && insn->pinfo != INSN_MACRO) | |
8047 | { | |
8048 | mips16_immed ((char *) NULL, 0, | |
8049 | imm_reloc - BFD_RELOC_UNUSED, | |
8050 | imm_expr.X_add_number, true, mips16_small, | |
8051 | mips16_ext, &ip->insn_opcode, | |
8052 | &ip->use_extend, &ip->extend); | |
8053 | imm_expr.X_op = O_absent; | |
8054 | imm_reloc = BFD_RELOC_UNUSED; | |
8055 | } | |
8056 | ||
8057 | return; | |
8058 | } | |
8059 | break; | |
8060 | ||
8061 | case ',': | |
8062 | if (*s++ == c) | |
8063 | continue; | |
8064 | s--; | |
8065 | switch (*++args) | |
8066 | { | |
8067 | case 'v': | |
8068 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8069 | continue; | |
8070 | case 'w': | |
8071 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8072 | continue; | |
8073 | } | |
8074 | break; | |
8075 | ||
8076 | case '(': | |
8077 | case ')': | |
8078 | if (*s++ == c) | |
8079 | continue; | |
8080 | break; | |
8081 | ||
8082 | case 'v': | |
8083 | case 'w': | |
8084 | if (s[0] != '$') | |
8085 | { | |
8086 | if (c == 'v') | |
8087 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8088 | else | |
8089 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8090 | ++args; | |
8091 | continue; | |
8092 | } | |
8093 | /* Fall through. */ | |
8094 | case 'x': | |
8095 | case 'y': | |
8096 | case 'z': | |
8097 | case 'Z': | |
8098 | case '0': | |
8099 | case 'S': | |
8100 | case 'R': | |
8101 | case 'X': | |
8102 | case 'Y': | |
8103 | if (s[0] != '$') | |
8104 | break; | |
8105 | s_reset = s; | |
d9a62219 | 8106 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
8107 | { |
8108 | ++s; | |
8109 | regno = 0; | |
8110 | do | |
8111 | { | |
8112 | regno *= 10; | |
8113 | regno += *s - '0'; | |
8114 | ++s; | |
8115 | } | |
d9a62219 | 8116 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
8117 | if (regno > 31) |
8118 | { | |
8119 | as_bad (_("invalid register number (%d)"), regno); | |
8120 | regno = 2; | |
8121 | } | |
8122 | } | |
8123 | else | |
8124 | { | |
8125 | if (s[1] == 'f' && s[2] == 'p') | |
8126 | { | |
8127 | s += 3; | |
8128 | regno = FP; | |
8129 | } | |
8130 | else if (s[1] == 's' && s[2] == 'p') | |
8131 | { | |
8132 | s += 3; | |
8133 | regno = SP; | |
8134 | } | |
8135 | else if (s[1] == 'g' && s[2] == 'p') | |
8136 | { | |
8137 | s += 3; | |
8138 | regno = GP; | |
8139 | } | |
8140 | else if (s[1] == 'a' && s[2] == 't') | |
8141 | { | |
8142 | s += 3; | |
8143 | regno = AT; | |
8144 | } | |
8145 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8146 | { | |
8147 | s += 4; | |
8148 | regno = KT0; | |
8149 | } | |
8150 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8151 | { | |
8152 | s += 4; | |
8153 | regno = KT1; | |
8154 | } | |
8155 | else | |
8156 | break; | |
8157 | } | |
8158 | ||
8159 | if (*s == ' ') | |
8160 | ++s; | |
8161 | if (args[1] != *s) | |
8162 | { | |
8163 | if (c == 'v' || c == 'w') | |
8164 | { | |
8165 | regno = mips16_to_32_reg_map[lastregno]; | |
8166 | s = s_reset; | |
8167 | args++; | |
8168 | } | |
8169 | } | |
8170 | ||
8171 | switch (c) | |
8172 | { | |
8173 | case 'x': | |
8174 | case 'y': | |
8175 | case 'z': | |
8176 | case 'v': | |
8177 | case 'w': | |
8178 | case 'Z': | |
8179 | regno = mips32_to_16_reg_map[regno]; | |
8180 | break; | |
8181 | ||
8182 | case '0': | |
8183 | if (regno != 0) | |
8184 | regno = ILLEGAL_REG; | |
8185 | break; | |
8186 | ||
8187 | case 'S': | |
8188 | if (regno != SP) | |
8189 | regno = ILLEGAL_REG; | |
8190 | break; | |
8191 | ||
8192 | case 'R': | |
8193 | if (regno != RA) | |
8194 | regno = ILLEGAL_REG; | |
8195 | break; | |
8196 | ||
8197 | case 'X': | |
8198 | case 'Y': | |
8199 | if (regno == AT && ! mips_opts.noat) | |
8200 | as_warn (_("used $at without \".set noat\"")); | |
8201 | break; | |
8202 | ||
8203 | default: | |
8204 | internalError (); | |
8205 | } | |
8206 | ||
8207 | if (regno == ILLEGAL_REG) | |
8208 | break; | |
8209 | ||
8210 | switch (c) | |
8211 | { | |
8212 | case 'x': | |
8213 | case 'v': | |
8214 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8215 | break; | |
8216 | case 'y': | |
8217 | case 'w': | |
8218 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8219 | break; | |
8220 | case 'z': | |
8221 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8222 | break; | |
8223 | case 'Z': | |
8224 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8225 | case '0': | |
8226 | case 'S': | |
8227 | case 'R': | |
8228 | break; | |
8229 | case 'X': | |
8230 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8231 | break; | |
8232 | case 'Y': | |
8233 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8234 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8235 | break; | |
8236 | default: | |
8237 | internalError (); | |
8238 | } | |
8239 | ||
8240 | lastregno = regno; | |
8241 | continue; | |
8242 | ||
8243 | case 'P': | |
8244 | if (strncmp (s, "$pc", 3) == 0) | |
8245 | { | |
8246 | s += 3; | |
8247 | continue; | |
8248 | } | |
8249 | break; | |
8250 | ||
8251 | case '<': | |
8252 | case '>': | |
8253 | case '[': | |
8254 | case ']': | |
8255 | case '4': | |
8256 | case '5': | |
8257 | case 'H': | |
8258 | case 'W': | |
8259 | case 'D': | |
8260 | case 'j': | |
8261 | case '8': | |
8262 | case 'V': | |
8263 | case 'C': | |
8264 | case 'U': | |
8265 | case 'k': | |
8266 | case 'K': | |
8267 | if (s[0] == '%' | |
8268 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8269 | { | |
8270 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8271 | and generate the appropriate reloc. If the text | |
8272 | inside %gprel is not a symbol name with an | |
8273 | optional offset, then we generate a normal reloc | |
8274 | and will probably fail later. */ | |
8275 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8276 | if (imm_expr.X_op == O_symbol) | |
8277 | { | |
8278 | mips16_ext = true; | |
8279 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8280 | s = expr_end; | |
8281 | ip->use_extend = true; | |
8282 | ip->extend = 0; | |
8283 | continue; | |
8284 | } | |
8285 | } | |
8286 | else | |
8287 | { | |
8288 | /* Just pick up a normal expression. */ | |
8289 | my_getExpression (&imm_expr, s); | |
8290 | } | |
8291 | ||
8292 | if (imm_expr.X_op == O_register) | |
8293 | { | |
8294 | /* What we thought was an expression turned out to | |
8295 | be a register. */ | |
8296 | ||
8297 | if (s[0] == '(' && args[1] == '(') | |
8298 | { | |
8299 | /* It looks like the expression was omitted | |
8300 | before a register indirection, which means | |
8301 | that the expression is implicitly zero. We | |
8302 | still set up imm_expr, so that we handle | |
8303 | explicit extensions correctly. */ | |
8304 | imm_expr.X_op = O_constant; | |
8305 | imm_expr.X_add_number = 0; | |
8306 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8307 | continue; | |
8308 | } | |
8309 | ||
8310 | break; | |
8311 | } | |
8312 | ||
8313 | /* We need to relax this instruction. */ | |
8314 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8315 | s = expr_end; | |
8316 | continue; | |
8317 | ||
8318 | case 'p': | |
8319 | case 'q': | |
8320 | case 'A': | |
8321 | case 'B': | |
8322 | case 'E': | |
8323 | /* We use offset_reloc rather than imm_reloc for the PC | |
8324 | relative operands. This lets macros with both | |
8325 | immediate and address operands work correctly. */ | |
8326 | my_getExpression (&offset_expr, s); | |
8327 | ||
8328 | if (offset_expr.X_op == O_register) | |
8329 | break; | |
8330 | ||
8331 | /* We need to relax this instruction. */ | |
8332 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8333 | s = expr_end; | |
8334 | continue; | |
8335 | ||
8336 | case '6': /* break code */ | |
8337 | my_getExpression (&imm_expr, s); | |
8338 | check_absolute_expr (ip, &imm_expr); | |
8339 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8340 | { | |
8341 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8342 | ip->insn_mo->name, | |
8343 | (unsigned long) imm_expr.X_add_number); | |
8344 | imm_expr.X_add_number &= 0x3f; | |
8345 | } | |
8346 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8347 | imm_expr.X_op = O_absent; | |
8348 | s = expr_end; | |
8349 | continue; | |
8350 | ||
8351 | case 'a': /* 26 bit address */ | |
8352 | my_getExpression (&offset_expr, s); | |
8353 | s = expr_end; | |
8354 | offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8355 | ip->insn_opcode <<= 16; | |
8356 | continue; | |
8357 | ||
8358 | case 'l': /* register list for entry macro */ | |
8359 | case 'L': /* register list for exit macro */ | |
8360 | { | |
8361 | int mask; | |
8362 | ||
8363 | if (c == 'l') | |
8364 | mask = 0; | |
8365 | else | |
8366 | mask = 7 << 3; | |
8367 | while (*s != '\0') | |
8368 | { | |
8369 | int freg, reg1, reg2; | |
8370 | ||
8371 | while (*s == ' ' || *s == ',') | |
8372 | ++s; | |
8373 | if (*s != '$') | |
8374 | { | |
8375 | as_bad (_("can't parse register list")); | |
8376 | break; | |
8377 | } | |
8378 | ++s; | |
8379 | if (*s != 'f') | |
8380 | freg = 0; | |
8381 | else | |
8382 | { | |
8383 | freg = 1; | |
8384 | ++s; | |
8385 | } | |
8386 | reg1 = 0; | |
d9a62219 | 8387 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8388 | { |
8389 | reg1 *= 10; | |
8390 | reg1 += *s - '0'; | |
8391 | ++s; | |
8392 | } | |
8393 | if (*s == ' ') | |
8394 | ++s; | |
8395 | if (*s != '-') | |
8396 | reg2 = reg1; | |
8397 | else | |
8398 | { | |
8399 | ++s; | |
8400 | if (*s != '$') | |
8401 | break; | |
8402 | ++s; | |
8403 | if (freg) | |
8404 | { | |
8405 | if (*s == 'f') | |
8406 | ++s; | |
8407 | else | |
8408 | { | |
8409 | as_bad (_("invalid register list")); | |
8410 | break; | |
8411 | } | |
8412 | } | |
8413 | reg2 = 0; | |
d9a62219 | 8414 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8415 | { |
8416 | reg2 *= 10; | |
8417 | reg2 += *s - '0'; | |
8418 | ++s; | |
8419 | } | |
8420 | } | |
8421 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8422 | { | |
8423 | mask &= ~ (7 << 3); | |
8424 | mask |= 5 << 3; | |
8425 | } | |
8426 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8427 | { | |
8428 | mask &= ~ (7 << 3); | |
8429 | mask |= 6 << 3; | |
8430 | } | |
8431 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8432 | mask |= (reg2 - 3) << 3; | |
8433 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8434 | mask |= (reg2 - 15) << 1; | |
8435 | else if (reg1 == 31 && reg2 == 31) | |
8436 | mask |= 1; | |
8437 | else | |
8438 | { | |
8439 | as_bad (_("invalid register list")); | |
8440 | break; | |
8441 | } | |
8442 | } | |
8443 | /* The mask is filled in in the opcode table for the | |
8444 | benefit of the disassembler. We remove it before | |
8445 | applying the actual mask. */ | |
8446 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8447 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8448 | } | |
8449 | continue; | |
8450 | ||
8451 | case 'e': /* extend code */ | |
8452 | my_getExpression (&imm_expr, s); | |
8453 | check_absolute_expr (ip, &imm_expr); | |
8454 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8455 | { | |
8456 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8457 | ip->insn_mo->name, | |
8458 | (unsigned long) imm_expr.X_add_number); | |
8459 | imm_expr.X_add_number &= 0x7ff; | |
8460 | } | |
8461 | ip->insn_opcode |= imm_expr.X_add_number; | |
8462 | imm_expr.X_op = O_absent; | |
8463 | s = expr_end; | |
8464 | continue; | |
8465 | ||
8466 | default: | |
8467 | internalError (); | |
8468 | } | |
8469 | break; | |
8470 | } | |
8471 | ||
8472 | /* Args don't match. */ | |
8473 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8474 | strcmp (insn->name, insn[1].name) == 0) | |
8475 | { | |
8476 | ++insn; | |
8477 | s = argsstart; | |
8478 | continue; | |
8479 | } | |
8480 | ||
8481 | insn_error = _("illegal operands"); | |
8482 | ||
8483 | return; | |
8484 | } | |
8485 | } | |
8486 | ||
8487 | /* This structure holds information we know about a mips16 immediate | |
8488 | argument type. */ | |
8489 | ||
e972090a NC |
8490 | struct mips16_immed_operand |
8491 | { | |
252b5132 RH |
8492 | /* The type code used in the argument string in the opcode table. */ |
8493 | int type; | |
8494 | /* The number of bits in the short form of the opcode. */ | |
8495 | int nbits; | |
8496 | /* The number of bits in the extended form of the opcode. */ | |
8497 | int extbits; | |
8498 | /* The amount by which the short form is shifted when it is used; | |
8499 | for example, the sw instruction has a shift count of 2. */ | |
8500 | int shift; | |
8501 | /* The amount by which the short form is shifted when it is stored | |
8502 | into the instruction code. */ | |
8503 | int op_shift; | |
8504 | /* Non-zero if the short form is unsigned. */ | |
8505 | int unsp; | |
8506 | /* Non-zero if the extended form is unsigned. */ | |
8507 | int extu; | |
8508 | /* Non-zero if the value is PC relative. */ | |
8509 | int pcrel; | |
8510 | }; | |
8511 | ||
8512 | /* The mips16 immediate operand types. */ | |
8513 | ||
8514 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8515 | { | |
8516 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8517 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8518 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8519 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8520 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8521 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8522 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8523 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8524 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8525 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8526 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8527 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8528 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8529 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8530 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8531 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8532 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8533 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8534 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8535 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8536 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8537 | }; | |
8538 | ||
8539 | #define MIPS16_NUM_IMMED \ | |
8540 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8541 | ||
8542 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8543 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8544 | whether an extended value is needed; if one is needed, it sets | |
8545 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8546 | If SMALL is true, an unextended opcode was explicitly requested. | |
8547 | If EXT is true, an extended opcode was explicitly requested. If | |
8548 | WARN is true, warn if EXT does not match reality. */ | |
8549 | ||
8550 | static void | |
8551 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8552 | extend) | |
8553 | char *file; | |
8554 | unsigned int line; | |
8555 | int type; | |
8556 | offsetT val; | |
8557 | boolean warn; | |
8558 | boolean small; | |
8559 | boolean ext; | |
8560 | unsigned long *insn; | |
8561 | boolean *use_extend; | |
8562 | unsigned short *extend; | |
8563 | { | |
8564 | register const struct mips16_immed_operand *op; | |
8565 | int mintiny, maxtiny; | |
8566 | boolean needext; | |
8567 | ||
8568 | op = mips16_immed_operands; | |
8569 | while (op->type != type) | |
8570 | { | |
8571 | ++op; | |
8572 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8573 | } | |
8574 | ||
8575 | if (op->unsp) | |
8576 | { | |
8577 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8578 | { | |
8579 | mintiny = 1; | |
8580 | maxtiny = 1 << op->nbits; | |
8581 | } | |
8582 | else | |
8583 | { | |
8584 | mintiny = 0; | |
8585 | maxtiny = (1 << op->nbits) - 1; | |
8586 | } | |
8587 | } | |
8588 | else | |
8589 | { | |
8590 | mintiny = - (1 << (op->nbits - 1)); | |
8591 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8592 | } | |
8593 | ||
8594 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8595 | if (type == 'p' || type == 'q') | |
8596 | val /= 2; | |
8597 | ||
8598 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8599 | || val < (mintiny << op->shift) | |
8600 | || val > (maxtiny << op->shift)) | |
8601 | needext = true; | |
8602 | else | |
8603 | needext = false; | |
8604 | ||
8605 | if (warn && ext && ! needext) | |
beae10d5 KH |
8606 | as_warn_where (file, line, |
8607 | _("extended operand requested but not required")); | |
252b5132 RH |
8608 | if (small && needext) |
8609 | as_bad_where (file, line, _("invalid unextended operand value")); | |
8610 | ||
8611 | if (small || (! ext && ! needext)) | |
8612 | { | |
8613 | int insnval; | |
8614 | ||
8615 | *use_extend = false; | |
8616 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8617 | insnval <<= op->op_shift; | |
8618 | *insn |= insnval; | |
8619 | } | |
8620 | else | |
8621 | { | |
8622 | long minext, maxext; | |
8623 | int extval; | |
8624 | ||
8625 | if (op->extu) | |
8626 | { | |
8627 | minext = 0; | |
8628 | maxext = (1 << op->extbits) - 1; | |
8629 | } | |
8630 | else | |
8631 | { | |
8632 | minext = - (1 << (op->extbits - 1)); | |
8633 | maxext = (1 << (op->extbits - 1)) - 1; | |
8634 | } | |
8635 | if (val < minext || val > maxext) | |
8636 | as_bad_where (file, line, | |
8637 | _("operand value out of range for instruction")); | |
8638 | ||
8639 | *use_extend = true; | |
8640 | if (op->extbits == 16) | |
8641 | { | |
8642 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8643 | val &= 0x1f; | |
8644 | } | |
8645 | else if (op->extbits == 15) | |
8646 | { | |
8647 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8648 | val &= 0xf; | |
8649 | } | |
8650 | else | |
8651 | { | |
8652 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8653 | val = 0; | |
8654 | } | |
8655 | ||
8656 | *extend = (unsigned short) extval; | |
8657 | *insn |= val; | |
8658 | } | |
8659 | } | |
8660 | \f | |
8661 | #define LP '(' | |
8662 | #define RP ')' | |
8663 | ||
8664 | static int | |
8665 | my_getSmallExpression (ep, str) | |
8666 | expressionS *ep; | |
8667 | char *str; | |
8668 | { | |
8669 | char *sp; | |
8670 | int c = 0; | |
8671 | ||
8672 | if (*str == ' ') | |
8673 | str++; | |
8674 | if (*str == LP | |
8675 | || (*str == '%' && | |
8676 | ((str[1] == 'h' && str[2] == 'i') | |
8677 | || (str[1] == 'H' && str[2] == 'I') | |
8678 | || (str[1] == 'l' && str[2] == 'o')) | |
8679 | && str[3] == LP)) | |
8680 | { | |
8681 | if (*str == LP) | |
8682 | c = 0; | |
8683 | else | |
8684 | { | |
8685 | c = str[1]; | |
8686 | str += 3; | |
8687 | } | |
8688 | ||
8689 | /* | |
8690 | * A small expression may be followed by a base register. | |
8691 | * Scan to the end of this operand, and then back over a possible | |
8692 | * base register. Then scan the small expression up to that | |
8693 | * point. (Based on code in sparc.c...) | |
8694 | */ | |
8695 | for (sp = str; *sp && *sp != ','; sp++) | |
8696 | ; | |
8697 | if (sp - 4 >= str && sp[-1] == RP) | |
8698 | { | |
d9a62219 | 8699 | if (isdigit ((unsigned char) sp[-2])) |
252b5132 | 8700 | { |
d9a62219 | 8701 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
252b5132 RH |
8702 | ; |
8703 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8704 | { | |
8705 | sp--; | |
8706 | goto do_it; | |
8707 | } | |
8708 | } | |
8709 | else if (sp - 5 >= str | |
8710 | && sp[-5] == LP | |
8711 | && sp[-4] == '$' | |
8712 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8713 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8714 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8715 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8716 | { | |
8717 | sp -= 5; | |
8718 | do_it: | |
8719 | if (sp == str) | |
8720 | { | |
8721 | /* no expression means zero offset */ | |
8722 | if (c) | |
8723 | { | |
8724 | /* %xx(reg) is an error */ | |
8725 | ep->X_op = O_absent; | |
8726 | expr_end = str - 3; | |
8727 | } | |
8728 | else | |
8729 | { | |
8730 | ep->X_op = O_constant; | |
8731 | expr_end = sp; | |
8732 | } | |
8733 | ep->X_add_symbol = NULL; | |
8734 | ep->X_op_symbol = NULL; | |
8735 | ep->X_add_number = 0; | |
8736 | } | |
8737 | else | |
8738 | { | |
8739 | *sp = '\0'; | |
8740 | my_getExpression (ep, str); | |
8741 | *sp = LP; | |
8742 | } | |
8743 | return c; | |
8744 | } | |
8745 | } | |
8746 | } | |
8747 | my_getExpression (ep, str); | |
8748 | return c; /* => %hi or %lo encountered */ | |
8749 | } | |
8750 | ||
8751 | static void | |
8752 | my_getExpression (ep, str) | |
8753 | expressionS *ep; | |
8754 | char *str; | |
8755 | { | |
8756 | char *save_in; | |
8757 | ||
8758 | save_in = input_line_pointer; | |
8759 | input_line_pointer = str; | |
8760 | expression (ep); | |
8761 | expr_end = input_line_pointer; | |
8762 | input_line_pointer = save_in; | |
8763 | ||
8764 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8765 | then we bump the value of the symbol by 1 since that is how other | |
8766 | text symbols are handled. We don't bother to handle complex | |
8767 | expressions, just `.' plus or minus a constant. */ | |
8768 | if (mips_opts.mips16 | |
8769 | && ep->X_op == O_symbol | |
8770 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8771 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
8772 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
8773 | && symbol_constant_p (ep->X_add_symbol) | |
8774 | && S_GET_VALUE (ep->X_add_symbol) == frag_now_fix ()) | |
8775 | S_SET_VALUE (ep->X_add_symbol, S_GET_VALUE (ep->X_add_symbol) + 1); | |
252b5132 RH |
8776 | } |
8777 | ||
8778 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
8779 | of type TYPE, and store the appropriate bytes in *LITP. The number |
8780 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
8781 | returned, or NULL on OK. */ |
8782 | ||
8783 | char * | |
8784 | md_atof (type, litP, sizeP) | |
8785 | int type; | |
8786 | char *litP; | |
8787 | int *sizeP; | |
8788 | { | |
8789 | int prec; | |
8790 | LITTLENUM_TYPE words[4]; | |
8791 | char *t; | |
8792 | int i; | |
8793 | ||
8794 | switch (type) | |
8795 | { | |
8796 | case 'f': | |
8797 | prec = 2; | |
8798 | break; | |
8799 | ||
8800 | case 'd': | |
8801 | prec = 4; | |
8802 | break; | |
8803 | ||
8804 | default: | |
8805 | *sizeP = 0; | |
8806 | return _("bad call to md_atof"); | |
8807 | } | |
8808 | ||
8809 | t = atof_ieee (input_line_pointer, type, words); | |
8810 | if (t) | |
8811 | input_line_pointer = t; | |
8812 | ||
8813 | *sizeP = prec * 2; | |
8814 | ||
8815 | if (! target_big_endian) | |
8816 | { | |
8817 | for (i = prec - 1; i >= 0; i--) | |
8818 | { | |
8819 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8820 | litP += 2; | |
8821 | } | |
8822 | } | |
8823 | else | |
8824 | { | |
8825 | for (i = 0; i < prec; i++) | |
8826 | { | |
8827 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8828 | litP += 2; | |
8829 | } | |
8830 | } | |
bdaaa2e1 | 8831 | |
252b5132 RH |
8832 | return NULL; |
8833 | } | |
8834 | ||
8835 | void | |
8836 | md_number_to_chars (buf, val, n) | |
8837 | char *buf; | |
8838 | valueT val; | |
8839 | int n; | |
8840 | { | |
8841 | if (target_big_endian) | |
8842 | number_to_chars_bigendian (buf, val, n); | |
8843 | else | |
8844 | number_to_chars_littleendian (buf, val, n); | |
8845 | } | |
8846 | \f | |
8847 | CONST char *md_shortopts = "O::g::G:"; | |
8848 | ||
e972090a NC |
8849 | struct option md_longopts[] = |
8850 | { | |
252b5132 RH |
8851 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
8852 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8853 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8854 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8855 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8856 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8857 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
8858 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
8859 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8860 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
8861 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
8862 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
8863 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
156c2f8b | 8864 | #define OPTION_TRAP (OPTION_MD_BASE + 7) |
252b5132 RH |
8865 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8866 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
156c2f8b | 8867 | #define OPTION_BREAK (OPTION_MD_BASE + 8) |
252b5132 RH |
8868 | {"break", no_argument, NULL, OPTION_BREAK}, |
8869 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
156c2f8b | 8870 | #define OPTION_EB (OPTION_MD_BASE + 9) |
252b5132 | 8871 | {"EB", no_argument, NULL, OPTION_EB}, |
156c2f8b | 8872 | #define OPTION_EL (OPTION_MD_BASE + 10) |
252b5132 | 8873 | {"EL", no_argument, NULL, OPTION_EL}, |
156c2f8b | 8874 | #define OPTION_M4650 (OPTION_MD_BASE + 11) |
252b5132 | 8875 | {"m4650", no_argument, NULL, OPTION_M4650}, |
156c2f8b | 8876 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 12) |
252b5132 | 8877 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
156c2f8b | 8878 | #define OPTION_M4010 (OPTION_MD_BASE + 13) |
252b5132 | 8879 | {"m4010", no_argument, NULL, OPTION_M4010}, |
156c2f8b | 8880 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 14) |
252b5132 | 8881 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
156c2f8b | 8882 | #define OPTION_M4100 (OPTION_MD_BASE + 15) |
252b5132 | 8883 | {"m4100", no_argument, NULL, OPTION_M4100}, |
156c2f8b | 8884 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 16) |
252b5132 | 8885 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
156c2f8b | 8886 | #define OPTION_MIPS16 (OPTION_MD_BASE + 17) |
252b5132 | 8887 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
156c2f8b | 8888 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18) |
252b5132 | 8889 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
156c2f8b | 8890 | #define OPTION_M3900 (OPTION_MD_BASE + 19) |
252b5132 | 8891 | {"m3900", no_argument, NULL, OPTION_M3900}, |
156c2f8b | 8892 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 20) |
252b5132 | 8893 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
156c2f8b | 8894 | #define OPTION_MABI (OPTION_MD_BASE + 21) |
252b5132 | 8895 | {"mabi", required_argument, NULL, OPTION_MABI}, |
156c2f8b | 8896 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22) |
6b76fefe | 8897 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
156c2f8b | 8898 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23) |
6b76fefe | 8899 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
156c2f8b | 8900 | #define OPTION_GP32 (OPTION_MD_BASE + 24) |
c97ef257 | 8901 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
156c2f8b | 8902 | #define OPTION_GP64 (OPTION_MD_BASE + 25) |
c97ef257 | 8903 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
156c2f8b | 8904 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26) |
119d663a | 8905 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
156c2f8b | 8906 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27) |
119d663a | 8907 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
156c2f8b NC |
8908 | #define OPTION_MIPS32 (OPTION_MD_BASE + 28) |
8909 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
84ea6cf2 NC |
8910 | #define OPTION_MIPS5 (OPTION_MD_BASE + 29) |
8911 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
8912 | #define OPTION_MIPS64 (OPTION_MD_BASE + 30) | |
8913 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
156c2f8b NC |
8914 | #ifdef OBJ_ELF |
8915 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) | |
8916 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) | |
8917 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) | |
8918 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) | |
8919 | #define OPTION_32 (OPTION_ELF_BASE + 3) | |
8920 | #define OPTION_64 (OPTION_ELF_BASE + 4) | |
8921 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
8922 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
8923 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
8924 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
8925 | {"32", no_argument, NULL, OPTION_32}, | |
8926 | {"64", no_argument, NULL, OPTION_64}, | |
8927 | #endif | |
119d663a | 8928 | |
252b5132 RH |
8929 | {NULL, no_argument, NULL, 0} |
8930 | }; | |
156c2f8b | 8931 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
8932 | |
8933 | int | |
8934 | md_parse_option (c, arg) | |
8935 | int c; | |
8936 | char *arg; | |
8937 | { | |
8938 | switch (c) | |
8939 | { | |
119d663a NC |
8940 | case OPTION_CONSTRUCT_FLOATS: |
8941 | mips_disable_float_construction = 0; | |
8942 | break; | |
bdaaa2e1 | 8943 | |
119d663a NC |
8944 | case OPTION_NO_CONSTRUCT_FLOATS: |
8945 | mips_disable_float_construction = 1; | |
8946 | break; | |
bdaaa2e1 | 8947 | |
252b5132 RH |
8948 | case OPTION_TRAP: |
8949 | mips_trap = 1; | |
8950 | break; | |
8951 | ||
8952 | case OPTION_BREAK: | |
8953 | mips_trap = 0; | |
8954 | break; | |
8955 | ||
8956 | case OPTION_EB: | |
8957 | target_big_endian = 1; | |
8958 | break; | |
8959 | ||
8960 | case OPTION_EL: | |
8961 | target_big_endian = 0; | |
8962 | break; | |
8963 | ||
8964 | case 'O': | |
8965 | if (arg && arg[1] == '0') | |
8966 | mips_optimize = 1; | |
8967 | else | |
8968 | mips_optimize = 2; | |
8969 | break; | |
8970 | ||
8971 | case 'g': | |
8972 | if (arg == NULL) | |
8973 | mips_debug = 2; | |
8974 | else | |
8975 | mips_debug = atoi (arg); | |
8976 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8977 | optimizations which limit full symbolic debugging. We take | |
8978 | that to be equivalent to -O0. */ | |
8979 | if (mips_debug == 2) | |
8980 | mips_optimize = 1; | |
8981 | break; | |
8982 | ||
8983 | case OPTION_MIPS1: | |
e7af610e | 8984 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
8985 | break; |
8986 | ||
8987 | case OPTION_MIPS2: | |
e7af610e | 8988 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
8989 | break; |
8990 | ||
8991 | case OPTION_MIPS3: | |
e7af610e | 8992 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
8993 | break; |
8994 | ||
8995 | case OPTION_MIPS4: | |
e7af610e NC |
8996 | mips_opts.isa = ISA_MIPS4; |
8997 | break; | |
8998 | ||
84ea6cf2 NC |
8999 | case OPTION_MIPS5: |
9000 | mips_opts.isa = ISA_MIPS5; | |
9001 | break; | |
9002 | ||
e7af610e NC |
9003 | case OPTION_MIPS32: |
9004 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
9005 | break; |
9006 | ||
84ea6cf2 NC |
9007 | case OPTION_MIPS64: |
9008 | mips_opts.isa = ISA_MIPS64; | |
9009 | break; | |
9010 | ||
252b5132 RH |
9011 | case OPTION_MCPU: |
9012 | { | |
e7af610e NC |
9013 | /* Identify the processor type. */ |
9014 | if (strcasecmp (arg, "default") == 0) | |
9015 | mips_cpu = CPU_UNKNOWN; | |
252b5132 RH |
9016 | else |
9017 | { | |
e7af610e | 9018 | const struct mips_cpu_info *ci; |
252b5132 | 9019 | |
e7af610e NC |
9020 | ci = mips_cpu_info_from_name (arg); |
9021 | if (ci == NULL || ci->is_isa) | |
beae10d5 | 9022 | as_bad (_("invalid architecture -mcpu=%s"), arg); |
e7af610e NC |
9023 | else |
9024 | mips_cpu = ci->cpu; | |
252b5132 RH |
9025 | } |
9026 | } | |
9027 | break; | |
9028 | ||
9029 | case OPTION_M4650: | |
156c2f8b | 9030 | mips_cpu = CPU_R4650; |
252b5132 RH |
9031 | break; |
9032 | ||
9033 | case OPTION_NO_M4650: | |
9034 | break; | |
9035 | ||
9036 | case OPTION_M4010: | |
156c2f8b | 9037 | mips_cpu = CPU_R4010; |
252b5132 RH |
9038 | break; |
9039 | ||
9040 | case OPTION_NO_M4010: | |
9041 | break; | |
9042 | ||
9043 | case OPTION_M4100: | |
156c2f8b | 9044 | mips_cpu = CPU_VR4100; |
252b5132 RH |
9045 | break; |
9046 | ||
9047 | case OPTION_NO_M4100: | |
9048 | break; | |
9049 | ||
252b5132 | 9050 | case OPTION_M3900: |
156c2f8b | 9051 | mips_cpu = CPU_R3900; |
252b5132 | 9052 | break; |
bdaaa2e1 | 9053 | |
252b5132 RH |
9054 | case OPTION_NO_M3900: |
9055 | break; | |
9056 | ||
9057 | case OPTION_MIPS16: | |
9058 | mips_opts.mips16 = 1; | |
9059 | mips_no_prev_insn (false); | |
9060 | break; | |
9061 | ||
9062 | case OPTION_NO_MIPS16: | |
9063 | mips_opts.mips16 = 0; | |
9064 | mips_no_prev_insn (false); | |
9065 | break; | |
9066 | ||
9067 | case OPTION_MEMBEDDED_PIC: | |
9068 | mips_pic = EMBEDDED_PIC; | |
9069 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9070 | { | |
9071 | as_bad (_("-G may not be used with embedded PIC code")); | |
9072 | return 0; | |
9073 | } | |
9074 | g_switch_value = 0x7fffffff; | |
9075 | break; | |
9076 | ||
0f074f60 | 9077 | #ifdef OBJ_ELF |
252b5132 RH |
9078 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9079 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9080 | intended to be compatible with Irix 5. */ | |
9081 | case OPTION_CALL_SHARED: | |
9082 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9083 | { | |
9084 | as_bad (_("-call_shared is supported only for ELF format")); | |
9085 | return 0; | |
9086 | } | |
9087 | mips_pic = SVR4_PIC; | |
9088 | if (g_switch_seen && g_switch_value != 0) | |
9089 | { | |
9090 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9091 | return 0; | |
9092 | } | |
9093 | g_switch_value = 0; | |
9094 | break; | |
9095 | ||
9096 | case OPTION_NON_SHARED: | |
9097 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9098 | { | |
9099 | as_bad (_("-non_shared is supported only for ELF format")); | |
9100 | return 0; | |
9101 | } | |
9102 | mips_pic = NO_PIC; | |
9103 | break; | |
9104 | ||
9105 | /* The -xgot option tells the assembler to use 32 offsets when | |
9106 | accessing the got in SVR4_PIC mode. It is for Irix | |
9107 | compatibility. */ | |
9108 | case OPTION_XGOT: | |
9109 | mips_big_got = 1; | |
9110 | break; | |
0f074f60 | 9111 | #endif /* OBJ_ELF */ |
252b5132 RH |
9112 | |
9113 | case 'G': | |
9114 | if (! USE_GLOBAL_POINTER_OPT) | |
9115 | { | |
9116 | as_bad (_("-G is not supported for this configuration")); | |
9117 | return 0; | |
9118 | } | |
9119 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9120 | { | |
9121 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9122 | return 0; | |
9123 | } | |
9124 | else | |
9125 | g_switch_value = atoi (arg); | |
9126 | g_switch_seen = 1; | |
9127 | break; | |
9128 | ||
0f074f60 | 9129 | #ifdef OBJ_ELF |
252b5132 RH |
9130 | /* The -32 and -64 options tell the assembler to output the 32 |
9131 | bit or the 64 bit MIPS ELF format. */ | |
9132 | case OPTION_32: | |
9133 | mips_64 = 0; | |
9134 | break; | |
9135 | ||
9136 | case OPTION_64: | |
9137 | { | |
9138 | const char **list, **l; | |
9139 | ||
9140 | list = bfd_target_list (); | |
9141 | for (l = list; *l != NULL; l++) | |
9142 | if (strcmp (*l, "elf64-bigmips") == 0 | |
f4ddc5e6 L |
9143 | || strcmp (*l, "elf64-littlemips") == 0 |
9144 | || strcmp (*l, "elf64-tradbigmips") == 0 | |
9145 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
252b5132 RH |
9146 | break; |
9147 | if (*l == NULL) | |
9148 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
9149 | free (list); | |
9150 | mips_64 = 1; | |
9151 | } | |
9152 | break; | |
0f074f60 | 9153 | #endif /* OBJ_ELF */ |
252b5132 | 9154 | |
c97ef257 AH |
9155 | case OPTION_GP32: |
9156 | mips_gp32 = 1; | |
9157 | mips_64 = 0; | |
9158 | ||
9159 | /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
9160 | flag in object files because to do so would make it | |
9161 | impossible to link with libraries compiled without "-gp32". | |
bdaaa2e1 | 9162 | This is unnecessarily restrictive. |
c97ef257 AH |
9163 | |
9164 | We could solve this problem by adding "-gp32" multilibs to | |
9165 | gcc, but to set this flag before gcc is built with such | |
bdaaa2e1 | 9166 | multilibs will break too many systems. */ |
c97ef257 | 9167 | |
beae10d5 KH |
9168 | #if 0 |
9169 | mips_32bitmode = 1; | |
9170 | #endif | |
c97ef257 AH |
9171 | break; |
9172 | ||
9173 | case OPTION_GP64: | |
9174 | mips_gp32 = 0; | |
9175 | mips_64 = 1; | |
beae10d5 KH |
9176 | #if 0 |
9177 | mips_32bitmode = 0; | |
9178 | #endif | |
c97ef257 | 9179 | break; |
252b5132 RH |
9180 | |
9181 | case OPTION_MABI: | |
beae10d5 KH |
9182 | if (strcmp (arg, "32") == 0 |
9183 | || strcmp (arg, "n32") == 0 | |
9184 | || strcmp (arg, "64") == 0 | |
9185 | || strcmp (arg, "o64") == 0 | |
9186 | || strcmp (arg, "eabi") == 0) | |
252b5132 RH |
9187 | mips_abi_string = arg; |
9188 | break; | |
9189 | ||
6b76fefe CM |
9190 | case OPTION_M7000_HILO_FIX: |
9191 | mips_7000_hilo_fix = true; | |
9192 | break; | |
9193 | ||
9194 | case OPTION_NO_M7000_HILO_FIX: | |
9195 | mips_7000_hilo_fix = false; | |
9196 | break; | |
9197 | ||
252b5132 RH |
9198 | default: |
9199 | return 0; | |
9200 | } | |
9201 | ||
9202 | return 1; | |
9203 | } | |
9204 | ||
252b5132 RH |
9205 | static void |
9206 | show (stream, string, col_p, first_p) | |
9207 | FILE *stream; | |
9208 | char *string; | |
9209 | int *col_p; | |
9210 | int *first_p; | |
9211 | { | |
9212 | if (*first_p) | |
9213 | { | |
9214 | fprintf (stream, "%24s", ""); | |
9215 | *col_p = 24; | |
9216 | } | |
9217 | else | |
9218 | { | |
9219 | fprintf (stream, ", "); | |
9220 | *col_p += 2; | |
9221 | } | |
9222 | ||
9223 | if (*col_p + strlen (string) > 72) | |
9224 | { | |
9225 | fprintf (stream, "\n%24s", ""); | |
9226 | *col_p = 24; | |
9227 | } | |
9228 | ||
9229 | fprintf (stream, "%s", string); | |
9230 | *col_p += strlen (string); | |
9231 | ||
9232 | *first_p = 0; | |
9233 | } | |
9234 | ||
252b5132 RH |
9235 | void |
9236 | md_show_usage (stream) | |
9237 | FILE *stream; | |
9238 | { | |
9239 | int column, first; | |
9240 | ||
beae10d5 | 9241 | fprintf (stream, _("\ |
252b5132 RH |
9242 | MIPS options:\n\ |
9243 | -membedded-pic generate embedded position independent code\n\ | |
9244 | -EB generate big endian output\n\ | |
9245 | -EL generate little endian output\n\ | |
9246 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9247 | -G NUM allow referencing objects up to NUM bytes\n\ | |
9248 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 9249 | fprintf (stream, _("\ |
252b5132 RH |
9250 | -mips1 generate MIPS ISA I instructions\n\ |
9251 | -mips2 generate MIPS ISA II instructions\n\ | |
9252 | -mips3 generate MIPS ISA III instructions\n\ | |
9253 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 9254 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 9255 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 9256 | -mips64 generate MIPS64 ISA instructions\n\ |
252b5132 RH |
9257 | -mcpu=CPU generate code for CPU, where CPU is one of:\n")); |
9258 | ||
9259 | first = 1; | |
9260 | ||
9261 | show (stream, "2000", &column, &first); | |
9262 | show (stream, "3000", &column, &first); | |
9263 | show (stream, "3900", &column, &first); | |
9264 | show (stream, "4000", &column, &first); | |
9265 | show (stream, "4010", &column, &first); | |
9266 | show (stream, "4100", &column, &first); | |
9267 | show (stream, "4111", &column, &first); | |
9268 | show (stream, "4300", &column, &first); | |
9269 | show (stream, "4400", &column, &first); | |
9270 | show (stream, "4600", &column, &first); | |
9271 | show (stream, "4650", &column, &first); | |
9272 | show (stream, "5000", &column, &first); | |
9273 | show (stream, "6000", &column, &first); | |
9274 | show (stream, "8000", &column, &first); | |
9275 | show (stream, "10000", &column, &first); | |
d1cf510e | 9276 | show (stream, "12000", &column, &first); |
e7af610e | 9277 | show (stream, "mips32-4k", &column, &first); |
c6c98b38 | 9278 | show (stream, "sb-1", &column, &first); |
252b5132 RH |
9279 | fputc ('\n', stream); |
9280 | ||
9281 | fprintf (stream, _("\ | |
9282 | -mCPU equivalent to -mcpu=CPU.\n\ | |
9283 | -no-mCPU don't generate code specific to CPU.\n\ | |
9284 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9285 | ||
9286 | first = 1; | |
9287 | ||
9288 | show (stream, "3900", &column, &first); | |
9289 | show (stream, "4010", &column, &first); | |
9290 | show (stream, "4100", &column, &first); | |
9291 | show (stream, "4650", &column, &first); | |
9292 | fputc ('\n', stream); | |
9293 | ||
beae10d5 | 9294 | fprintf (stream, _("\ |
252b5132 RH |
9295 | -mips16 generate mips16 instructions\n\ |
9296 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 9297 | fprintf (stream, _("\ |
252b5132 RH |
9298 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9299 | -O remove unneeded NOPs and swap branches\n\ | |
119d663a | 9300 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
9301 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
9302 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9303 | #ifdef OBJ_ELF | |
beae10d5 | 9304 | fprintf (stream, _("\ |
252b5132 RH |
9305 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
9306 | -non_shared do not generate position independent code\n\ | |
9307 | -xgot assume a 32 bit GOT\n\ | |
9308 | -32 create 32 bit object file (default)\n\ | |
9309 | -64 create 64 bit object file\n")); | |
9310 | #endif | |
9311 | } | |
9312 | \f | |
9313 | void | |
9314 | mips_init_after_args () | |
9315 | { | |
9316 | /* initialize opcodes */ | |
9317 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 9318 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
9319 | } |
9320 | ||
9321 | long | |
9322 | md_pcrel_from (fixP) | |
9323 | fixS *fixP; | |
9324 | { | |
9325 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9326 | && fixP->fx_addsy != (symbolS *) NULL | |
9327 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9328 | { | |
9329 | /* This makes a branch to an undefined symbol be a branch to the | |
9330 | current location. */ | |
9331 | return 4; | |
9332 | } | |
9333 | ||
9334 | /* return the address of the delay slot */ | |
9335 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9336 | } | |
9337 | ||
9338 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
9339 | reloc for a cons. We could use the definition there, except that | |
9340 | we want to handle 64 bit relocs specially. */ | |
9341 | ||
9342 | void | |
9343 | cons_fix_new_mips (frag, where, nbytes, exp) | |
43841e91 | 9344 | fragS *frag ATTRIBUTE_UNUSED; |
252b5132 RH |
9345 | int where; |
9346 | unsigned int nbytes; | |
9347 | expressionS *exp; | |
9348 | { | |
9349 | #ifndef OBJ_ELF | |
9350 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
9351 | 4 byte reloc. */ | |
9352 | if (nbytes == 8 && ! mips_64) | |
9353 | { | |
9354 | if (target_big_endian) | |
9355 | where += 4; | |
9356 | nbytes = 4; | |
9357 | } | |
9358 | #endif | |
9359 | ||
9360 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) | |
9361 | as_bad (_("Unsupported reloc size %d"), nbytes); | |
9362 | ||
9363 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
9364 | (nbytes == 2 | |
9365 | ? BFD_RELOC_16 | |
9366 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
9367 | } | |
9368 | ||
9369 | /* This is called before the symbol table is processed. In order to | |
9370 | work with gcc when using mips-tfile, we must keep all local labels. | |
9371 | However, in other cases, we want to discard them. If we were | |
9372 | called with -g, but we didn't see any debugging information, it may | |
9373 | mean that gcc is smuggling debugging information through to | |
9374 | mips-tfile, in which case we must generate all local labels. */ | |
9375 | ||
9376 | void | |
9377 | mips_frob_file_before_adjust () | |
9378 | { | |
9379 | #ifndef NO_ECOFF_DEBUGGING | |
9380 | if (ECOFF_DEBUGGING | |
9381 | && mips_debug != 0 | |
9382 | && ! ecoff_debugging_seen) | |
9383 | flag_keep_locals = 1; | |
9384 | #endif | |
9385 | } | |
9386 | ||
9387 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9388 | the corresponding LO reloc. This is called before md_apply_fix and | |
9389 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9390 | explicit use of the %hi modifier. */ | |
9391 | ||
9392 | void | |
9393 | mips_frob_file () | |
9394 | { | |
9395 | struct mips_hi_fixup *l; | |
9396 | ||
9397 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9398 | { | |
9399 | segment_info_type *seginfo; | |
9400 | int pass; | |
9401 | ||
9402 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9403 | ||
9404 | /* Check quickly whether the next fixup happens to be a matching | |
9405 | %lo. */ | |
9406 | if (l->fixp->fx_next != NULL | |
9407 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9408 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9409 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9410 | continue; | |
9411 | ||
9412 | /* Look through the fixups for this segment for a matching %lo. | |
9413 | When we find one, move the %hi just in front of it. We do | |
9414 | this in two passes. In the first pass, we try to find a | |
9415 | unique %lo. In the second pass, we permit multiple %hi | |
9416 | relocs for a single %lo (this is a GNU extension). */ | |
9417 | seginfo = seg_info (l->seg); | |
9418 | for (pass = 0; pass < 2; pass++) | |
9419 | { | |
9420 | fixS *f, *prev; | |
9421 | ||
9422 | prev = NULL; | |
9423 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
9424 | { | |
9425 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
9426 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9427 | && f->fx_addsy == l->fixp->fx_addsy | |
9428 | && f->fx_offset == l->fixp->fx_offset | |
9429 | && (pass == 1 | |
9430 | || prev == NULL | |
9431 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9432 | || prev->fx_addsy != f->fx_addsy | |
9433 | || prev->fx_offset != f->fx_offset)) | |
9434 | { | |
9435 | fixS **pf; | |
9436 | ||
9437 | /* Move l->fixp before f. */ | |
9438 | for (pf = &seginfo->fix_root; | |
9439 | *pf != l->fixp; | |
9440 | pf = &(*pf)->fx_next) | |
9441 | assert (*pf != NULL); | |
9442 | ||
9443 | *pf = l->fixp->fx_next; | |
9444 | ||
9445 | l->fixp->fx_next = f; | |
9446 | if (prev == NULL) | |
9447 | seginfo->fix_root = l->fixp; | |
9448 | else | |
9449 | prev->fx_next = l->fixp; | |
9450 | ||
9451 | break; | |
9452 | } | |
9453 | ||
9454 | prev = f; | |
9455 | } | |
9456 | ||
9457 | if (f != NULL) | |
9458 | break; | |
9459 | ||
9460 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
9461 | can leave a %hi without a %lo. */ | |
9462 | if (pass == 1) | |
9463 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9464 | _("Unmatched %%hi reloc")); | |
9465 | #endif | |
9466 | } | |
9467 | } | |
9468 | } | |
9469 | ||
9470 | /* When generating embedded PIC code we need to use a special | |
9471 | relocation to represent the difference of two symbols in the .text | |
9472 | section (switch tables use a difference of this sort). See | |
9473 | include/coff/mips.h for details. This macro checks whether this | |
9474 | fixup requires the special reloc. */ | |
9475 | #define SWITCH_TABLE(fixp) \ | |
9476 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 9477 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
9478 | && (fixp)->fx_addsy != NULL \ |
9479 | && (fixp)->fx_subsy != NULL \ | |
9480 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9481 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9482 | ||
9483 | /* When generating embedded PIC code we must keep all PC relative | |
9484 | relocations, in case the linker has to relax a call. We also need | |
9485 | to keep relocations for switch table entries. */ | |
9486 | ||
252b5132 RH |
9487 | int |
9488 | mips_force_relocation (fixp) | |
9489 | fixS *fixp; | |
9490 | { | |
9491 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9492 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9493 | return 1; | |
9494 | ||
9495 | return (mips_pic == EMBEDDED_PIC | |
9496 | && (fixp->fx_pcrel | |
9497 | || SWITCH_TABLE (fixp) | |
9498 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9499 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
9500 | } | |
9501 | ||
9502 | /* Apply a fixup to the object file. */ | |
9503 | ||
9504 | int | |
9505 | md_apply_fix (fixP, valueP) | |
9506 | fixS *fixP; | |
9507 | valueT *valueP; | |
9508 | { | |
9509 | unsigned char *buf; | |
9510 | long insn, value; | |
9511 | ||
9512 | assert (fixP->fx_size == 4 | |
9513 | || fixP->fx_r_type == BFD_RELOC_16 | |
9514 | || fixP->fx_r_type == BFD_RELOC_64 | |
9515 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9516 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
9517 | ||
9518 | value = *valueP; | |
9519 | ||
9520 | /* If we aren't adjusting this fixup to be against the section | |
9521 | symbol, we need to adjust the value. */ | |
9522 | #ifdef OBJ_ELF | |
9523 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 9524 | { |
bdaaa2e1 | 9525 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
252b5132 | 9526 | || S_IS_WEAK (fixP->fx_addsy) |
49309057 ILT |
9527 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
9528 | && (((bfd_get_section_flags (stdoutput, | |
bb2d6cd7 GK |
9529 | S_GET_SEGMENT (fixP->fx_addsy)) |
9530 | & SEC_LINK_ONCE) != 0) | |
9531 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
9532 | ".gnu.linkonce", | |
9533 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 RH |
9534 | |
9535 | { | |
9536 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9537 | if (value != 0 && ! fixP->fx_pcrel) | |
9538 | { | |
9539 | /* In this case, the bfd_install_relocation routine will | |
9540 | incorrectly add the symbol value back in. We just want | |
bdaaa2e1 | 9541 | the addend to appear in the object file. |
bb2d6cd7 | 9542 | FIXME: If this makes VALUE zero, we're toast. */ |
252b5132 RH |
9543 | value -= S_GET_VALUE (fixP->fx_addsy); |
9544 | } | |
9545 | } | |
252b5132 | 9546 | |
bb2d6cd7 GK |
9547 | /* This code was generated using trial and error and so is |
9548 | fragile and not trustworthy. If you change it, you should | |
9549 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
9550 | they still pass. */ | |
9551 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
9552 | { | |
9553 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9554 | ||
9555 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
9556 | This gives the right results, but it can't possibly | |
9557 | be the way things are supposed to work. */ | |
9558 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
9559 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) | |
9560 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9561 | } | |
9562 | } | |
9563 | #endif | |
252b5132 RH |
9564 | |
9565 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
9566 | ||
9567 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
9568 | fixP->fx_done = 1; | |
9569 | ||
9570 | switch (fixP->fx_r_type) | |
9571 | { | |
9572 | case BFD_RELOC_MIPS_JMP: | |
9573 | case BFD_RELOC_HI16: | |
9574 | case BFD_RELOC_HI16_S: | |
9575 | case BFD_RELOC_MIPS_GPREL: | |
9576 | case BFD_RELOC_MIPS_LITERAL: | |
9577 | case BFD_RELOC_MIPS_CALL16: | |
9578 | case BFD_RELOC_MIPS_GOT16: | |
9579 | case BFD_RELOC_MIPS_GPREL32: | |
9580 | case BFD_RELOC_MIPS_GOT_HI16: | |
9581 | case BFD_RELOC_MIPS_GOT_LO16: | |
9582 | case BFD_RELOC_MIPS_CALL_HI16: | |
9583 | case BFD_RELOC_MIPS_CALL_LO16: | |
9584 | case BFD_RELOC_MIPS16_GPREL: | |
9585 | if (fixP->fx_pcrel) | |
9586 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9587 | _("Invalid PC relative reloc")); | |
9588 | /* Nothing needed to do. The value comes from the reloc entry */ | |
9589 | break; | |
9590 | ||
9591 | case BFD_RELOC_MIPS16_JMP: | |
9592 | /* We currently always generate a reloc against a symbol, which | |
9593 | means that we don't want an addend even if the symbol is | |
9594 | defined. */ | |
9595 | fixP->fx_addnumber = 0; | |
9596 | break; | |
9597 | ||
9598 | case BFD_RELOC_PCREL_HI16_S: | |
9599 | /* The addend for this is tricky if it is internal, so we just | |
9600 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9601 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9602 | && !fixP->fx_done |
9603 | && value != 0) | |
9604 | break; | |
9605 | if (fixP->fx_addsy | |
9606 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9607 | { |
9608 | /* For an external symbol adjust by the address to make it | |
9609 | pcrel_offset. We use the address of the RELLO reloc | |
9610 | which follows this one. */ | |
9611 | value += (fixP->fx_next->fx_frag->fr_address | |
9612 | + fixP->fx_next->fx_where); | |
9613 | } | |
9614 | if (value & 0x8000) | |
9615 | value += 0x10000; | |
9616 | value >>= 16; | |
9617 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9618 | if (target_big_endian) | |
9619 | buf += 2; | |
9620 | md_number_to_chars (buf, value, 2); | |
9621 | break; | |
9622 | ||
9623 | case BFD_RELOC_PCREL_LO16: | |
9624 | /* The addend for this is tricky if it is internal, so we just | |
9625 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 9626 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
9627 | && !fixP->fx_done |
9628 | && value != 0) | |
9629 | break; | |
9630 | if (fixP->fx_addsy | |
9631 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9632 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
9633 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9634 | if (target_big_endian) | |
9635 | buf += 2; | |
9636 | md_number_to_chars (buf, value, 2); | |
9637 | break; | |
9638 | ||
9639 | case BFD_RELOC_64: | |
9640 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9641 | extended value if we are only 32 bits. */ | |
9642 | if (fixP->fx_done | |
9643 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9644 | { | |
9645 | if (8 <= sizeof (valueT)) | |
9646 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9647 | value, 8); | |
9648 | else | |
9649 | { | |
9650 | long w1, w2; | |
9651 | long hiv; | |
9652 | ||
9653 | w1 = w2 = fixP->fx_where; | |
9654 | if (target_big_endian) | |
9655 | w1 += 4; | |
9656 | else | |
9657 | w2 += 4; | |
9658 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9659 | if ((value & 0x80000000) != 0) | |
9660 | hiv = 0xffffffff; | |
9661 | else | |
9662 | hiv = 0; | |
9663 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9664 | } | |
9665 | } | |
9666 | break; | |
9667 | ||
056350c6 | 9668 | case BFD_RELOC_RVA: |
252b5132 RH |
9669 | case BFD_RELOC_32: |
9670 | /* If we are deleting this reloc entry, we must fill in the | |
9671 | value now. This can happen if we have a .word which is not | |
9672 | resolved when it appears but is later defined. We also need | |
9673 | to fill in the value if this is an embedded PIC switch table | |
9674 | entry. */ | |
9675 | if (fixP->fx_done | |
9676 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9677 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9678 | value, 4); | |
9679 | break; | |
9680 | ||
9681 | case BFD_RELOC_16: | |
9682 | /* If we are deleting this reloc entry, we must fill in the | |
9683 | value now. */ | |
9684 | assert (fixP->fx_size == 2); | |
9685 | if (fixP->fx_done) | |
9686 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9687 | value, 2); | |
9688 | break; | |
9689 | ||
9690 | case BFD_RELOC_LO16: | |
9691 | /* When handling an embedded PIC switch statement, we can wind | |
9692 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9693 | if (fixP->fx_done) | |
9694 | { | |
9695 | if (value < -0x8000 || value > 0x7fff) | |
9696 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9697 | _("relocation overflow")); | |
9698 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9699 | if (target_big_endian) | |
9700 | buf += 2; | |
9701 | md_number_to_chars (buf, value, 2); | |
9702 | } | |
9703 | break; | |
9704 | ||
9705 | case BFD_RELOC_16_PCREL_S2: | |
9706 | /* | |
9707 | * We need to save the bits in the instruction since fixup_segment() | |
9708 | * might be deleting the relocation entry (i.e., a branch within | |
9709 | * the current segment). | |
9710 | */ | |
9711 | if ((value & 0x3) != 0) | |
9712 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9713 | _("Branch to odd address (%lx)"), value); | |
bb2d6cd7 GK |
9714 | |
9715 | if (!fixP->fx_done && value != 0) | |
9716 | break; | |
9717 | /* If 'value' is zero, the remaining reloc code won't actually | |
9718 | do the store, so it must be done here. This is probably | |
9719 | a bug somewhere. */ | |
9720 | if (!fixP->fx_done) | |
9721 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
bdaaa2e1 | 9722 | |
252b5132 RH |
9723 | value >>= 2; |
9724 | ||
9725 | /* update old instruction data */ | |
9726 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
9727 | if (target_big_endian) | |
9728 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9729 | else | |
9730 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9731 | ||
9732 | if (value >= -0x8000 && value < 0x8000) | |
9733 | insn |= value & 0xffff; | |
9734 | else | |
9735 | { | |
9736 | /* The branch offset is too large. If this is an | |
9737 | unconditional branch, and we are not generating PIC code, | |
9738 | we can convert it to an absolute jump instruction. */ | |
9739 | if (mips_pic == NO_PIC | |
9740 | && fixP->fx_done | |
9741 | && fixP->fx_frag->fr_address >= text_section->vma | |
9742 | && (fixP->fx_frag->fr_address | |
9743 | < text_section->vma + text_section->_raw_size) | |
9744 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9745 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9746 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9747 | { | |
9748 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9749 | insn = 0x0c000000; /* jal */ | |
9750 | else | |
9751 | insn = 0x08000000; /* j */ | |
9752 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9753 | fixP->fx_done = 0; | |
9754 | fixP->fx_addsy = section_symbol (text_section); | |
9755 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9756 | } | |
9757 | else | |
9758 | { | |
9759 | /* FIXME. It would be possible in principle to handle | |
9760 | conditional branches which overflow. They could be | |
9761 | transformed into a branch around a jump. This would | |
9762 | require setting up variant frags for each different | |
9763 | branch type. The native MIPS assembler attempts to | |
9764 | handle these cases, but it appears to do it | |
9765 | incorrectly. */ | |
9766 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9767 | _("Branch out of range")); | |
9768 | } | |
9769 | } | |
9770 | ||
9771 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
9772 | break; | |
9773 | ||
9774 | case BFD_RELOC_VTABLE_INHERIT: | |
9775 | fixP->fx_done = 0; | |
9776 | if (fixP->fx_addsy | |
9777 | && !S_IS_DEFINED (fixP->fx_addsy) | |
9778 | && !S_IS_WEAK (fixP->fx_addsy)) | |
9779 | S_SET_WEAK (fixP->fx_addsy); | |
9780 | break; | |
9781 | ||
9782 | case BFD_RELOC_VTABLE_ENTRY: | |
9783 | fixP->fx_done = 0; | |
9784 | break; | |
9785 | ||
9786 | default: | |
9787 | internalError (); | |
9788 | } | |
9789 | ||
9790 | return 1; | |
9791 | } | |
9792 | ||
9793 | #if 0 | |
9794 | void | |
9795 | printInsn (oc) | |
9796 | unsigned long oc; | |
9797 | { | |
9798 | const struct mips_opcode *p; | |
9799 | int treg, sreg, dreg, shamt; | |
9800 | short imm; | |
9801 | const char *args; | |
9802 | int i; | |
9803 | ||
9804 | for (i = 0; i < NUMOPCODES; ++i) | |
9805 | { | |
9806 | p = &mips_opcodes[i]; | |
9807 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9808 | { | |
9809 | printf ("%08lx %s\t", oc, p->name); | |
9810 | treg = (oc >> 16) & 0x1f; | |
9811 | sreg = (oc >> 21) & 0x1f; | |
9812 | dreg = (oc >> 11) & 0x1f; | |
9813 | shamt = (oc >> 6) & 0x1f; | |
9814 | imm = oc; | |
9815 | for (args = p->args;; ++args) | |
9816 | { | |
9817 | switch (*args) | |
9818 | { | |
9819 | case '\0': | |
9820 | printf ("\n"); | |
9821 | break; | |
9822 | ||
9823 | case ',': | |
9824 | case '(': | |
9825 | case ')': | |
9826 | printf ("%c", *args); | |
9827 | continue; | |
9828 | ||
9829 | case 'r': | |
9830 | assert (treg == sreg); | |
9831 | printf ("$%d,$%d", treg, sreg); | |
9832 | continue; | |
9833 | ||
9834 | case 'd': | |
9835 | case 'G': | |
9836 | printf ("$%d", dreg); | |
9837 | continue; | |
9838 | ||
9839 | case 't': | |
9840 | case 'E': | |
9841 | printf ("$%d", treg); | |
9842 | continue; | |
9843 | ||
9844 | case 'k': | |
9845 | printf ("0x%x", treg); | |
9846 | continue; | |
9847 | ||
9848 | case 'b': | |
9849 | case 's': | |
9850 | printf ("$%d", sreg); | |
9851 | continue; | |
9852 | ||
9853 | case 'a': | |
9854 | printf ("0x%08lx", oc & 0x1ffffff); | |
9855 | continue; | |
9856 | ||
9857 | case 'i': | |
9858 | case 'j': | |
9859 | case 'o': | |
9860 | case 'u': | |
9861 | printf ("%d", imm); | |
9862 | continue; | |
9863 | ||
9864 | case '<': | |
9865 | case '>': | |
9866 | printf ("$%d", shamt); | |
9867 | continue; | |
9868 | ||
9869 | default: | |
9870 | internalError (); | |
9871 | } | |
9872 | break; | |
9873 | } | |
9874 | return; | |
9875 | } | |
9876 | } | |
9877 | printf (_("%08lx UNDEFINED\n"), oc); | |
9878 | } | |
9879 | #endif | |
9880 | ||
9881 | static symbolS * | |
9882 | get_symbol () | |
9883 | { | |
9884 | int c; | |
9885 | char *name; | |
9886 | symbolS *p; | |
9887 | ||
9888 | name = input_line_pointer; | |
9889 | c = get_symbol_end (); | |
9890 | p = (symbolS *) symbol_find_or_make (name); | |
9891 | *input_line_pointer = c; | |
9892 | return p; | |
9893 | } | |
9894 | ||
9895 | /* Align the current frag to a given power of two. The MIPS assembler | |
9896 | also automatically adjusts any preceding label. */ | |
9897 | ||
9898 | static void | |
9899 | mips_align (to, fill, label) | |
9900 | int to; | |
9901 | int fill; | |
9902 | symbolS *label; | |
9903 | { | |
9904 | mips_emit_delays (false); | |
9905 | frag_align (to, fill, 0); | |
9906 | record_alignment (now_seg, to); | |
9907 | if (label != NULL) | |
9908 | { | |
9909 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 9910 | symbol_set_frag (label, frag_now); |
252b5132 RH |
9911 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
9912 | } | |
9913 | } | |
9914 | ||
9915 | /* Align to a given power of two. .align 0 turns off the automatic | |
9916 | alignment used by the data creating pseudo-ops. */ | |
9917 | ||
9918 | static void | |
9919 | s_align (x) | |
43841e91 | 9920 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
9921 | { |
9922 | register int temp; | |
9923 | register long temp_fill; | |
9924 | long max_alignment = 15; | |
9925 | ||
9926 | /* | |
9927 | ||
9928 | o Note that the assembler pulls down any immediately preceeding label | |
9929 | to the aligned address. | |
9930 | o It's not documented but auto alignment is reinstated by | |
9931 | a .align pseudo instruction. | |
9932 | o Note also that after auto alignment is turned off the mips assembler | |
9933 | issues an error on attempt to assemble an improperly aligned data item. | |
9934 | We don't. | |
9935 | ||
9936 | */ | |
9937 | ||
9938 | temp = get_absolute_expression (); | |
9939 | if (temp > max_alignment) | |
9940 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
9941 | else if (temp < 0) | |
9942 | { | |
9943 | as_warn (_("Alignment negative: 0 assumed.")); | |
9944 | temp = 0; | |
9945 | } | |
9946 | if (*input_line_pointer == ',') | |
9947 | { | |
9948 | input_line_pointer++; | |
9949 | temp_fill = get_absolute_expression (); | |
9950 | } | |
9951 | else | |
9952 | temp_fill = 0; | |
9953 | if (temp) | |
9954 | { | |
9955 | auto_align = 1; | |
9956 | mips_align (temp, (int) temp_fill, | |
9957 | insn_labels != NULL ? insn_labels->label : NULL); | |
9958 | } | |
9959 | else | |
9960 | { | |
9961 | auto_align = 0; | |
9962 | } | |
9963 | ||
9964 | demand_empty_rest_of_line (); | |
9965 | } | |
9966 | ||
9967 | void | |
9968 | mips_flush_pending_output () | |
9969 | { | |
9970 | mips_emit_delays (false); | |
9971 | mips_clear_insn_labels (); | |
9972 | } | |
9973 | ||
9974 | static void | |
9975 | s_change_sec (sec) | |
9976 | int sec; | |
9977 | { | |
9978 | segT seg; | |
9979 | ||
9980 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
9981 | .sdata and .sbss sections. We change the .data and .rdata | |
9982 | pseudo-ops to use .sdata. */ | |
9983 | if (mips_pic == EMBEDDED_PIC | |
9984 | && (sec == 'd' || sec == 'r')) | |
9985 | sec = 's'; | |
9986 | ||
9987 | #ifdef OBJ_ELF | |
9988 | /* The ELF backend needs to know that we are changing sections, so | |
9989 | that .previous works correctly. We could do something like check | |
9990 | for a obj_section_change_hook macro, but that might be confusing | |
9991 | as it would not be appropriate to use it in the section changing | |
9992 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9993 | This should be cleaner, somehow. */ | |
9994 | obj_elf_section_change_hook (); | |
9995 | #endif | |
9996 | ||
9997 | mips_emit_delays (false); | |
9998 | switch (sec) | |
9999 | { | |
10000 | case 't': | |
10001 | s_text (0); | |
10002 | break; | |
10003 | case 'd': | |
10004 | s_data (0); | |
10005 | break; | |
10006 | case 'b': | |
10007 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10008 | demand_empty_rest_of_line (); | |
10009 | break; | |
10010 | ||
10011 | case 'r': | |
10012 | if (USE_GLOBAL_POINTER_OPT) | |
10013 | { | |
10014 | seg = subseg_new (RDATA_SECTION_NAME, | |
10015 | (subsegT) get_absolute_expression ()); | |
10016 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10017 | { | |
10018 | bfd_set_section_flags (stdoutput, seg, | |
10019 | (SEC_ALLOC | |
10020 | | SEC_LOAD | |
10021 | | SEC_READONLY | |
10022 | | SEC_RELOC | |
10023 | | SEC_DATA)); | |
10024 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10025 | record_alignment (seg, 4); |
252b5132 RH |
10026 | } |
10027 | demand_empty_rest_of_line (); | |
10028 | } | |
10029 | else | |
10030 | { | |
10031 | as_bad (_("No read only data section in this object file format")); | |
10032 | demand_empty_rest_of_line (); | |
10033 | return; | |
10034 | } | |
10035 | break; | |
10036 | ||
10037 | case 's': | |
10038 | if (USE_GLOBAL_POINTER_OPT) | |
10039 | { | |
10040 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10041 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10042 | { | |
10043 | bfd_set_section_flags (stdoutput, seg, | |
10044 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10045 | | SEC_DATA); | |
10046 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10047 | record_alignment (seg, 4); |
252b5132 RH |
10048 | } |
10049 | demand_empty_rest_of_line (); | |
10050 | break; | |
10051 | } | |
10052 | else | |
10053 | { | |
10054 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10055 | demand_empty_rest_of_line (); | |
10056 | return; | |
10057 | } | |
10058 | } | |
10059 | ||
10060 | auto_align = 1; | |
10061 | } | |
10062 | ||
10063 | void | |
10064 | mips_enable_auto_align () | |
10065 | { | |
10066 | auto_align = 1; | |
10067 | } | |
10068 | ||
10069 | static void | |
10070 | s_cons (log_size) | |
10071 | int log_size; | |
10072 | { | |
10073 | symbolS *label; | |
10074 | ||
10075 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10076 | mips_emit_delays (false); | |
10077 | if (log_size > 0 && auto_align) | |
10078 | mips_align (log_size, 0, label); | |
10079 | mips_clear_insn_labels (); | |
10080 | cons (1 << log_size); | |
10081 | } | |
10082 | ||
10083 | static void | |
10084 | s_float_cons (type) | |
10085 | int type; | |
10086 | { | |
10087 | symbolS *label; | |
10088 | ||
10089 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10090 | ||
10091 | mips_emit_delays (false); | |
10092 | ||
10093 | if (auto_align) | |
49309057 ILT |
10094 | { |
10095 | if (type == 'd') | |
10096 | mips_align (3, 0, label); | |
10097 | else | |
10098 | mips_align (2, 0, label); | |
10099 | } | |
252b5132 RH |
10100 | |
10101 | mips_clear_insn_labels (); | |
10102 | ||
10103 | float_cons (type); | |
10104 | } | |
10105 | ||
10106 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10107 | permitted to say | |
10108 | .globl foo .text | |
10109 | where foo is an undefined symbol, to mean that foo should be | |
10110 | considered to be the address of a function. */ | |
10111 | ||
10112 | static void | |
10113 | s_mips_globl (x) | |
43841e91 | 10114 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10115 | { |
10116 | char *name; | |
10117 | int c; | |
10118 | symbolS *symbolP; | |
10119 | flagword flag; | |
10120 | ||
10121 | name = input_line_pointer; | |
10122 | c = get_symbol_end (); | |
10123 | symbolP = symbol_find_or_make (name); | |
10124 | *input_line_pointer = c; | |
10125 | SKIP_WHITESPACE (); | |
10126 | ||
10127 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10128 | being a function is apparently labelled as being an object. */ | |
10129 | flag = BSF_OBJECT; | |
10130 | ||
10131 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10132 | { | |
10133 | char *secname; | |
10134 | asection *sec; | |
10135 | ||
10136 | secname = input_line_pointer; | |
10137 | c = get_symbol_end (); | |
10138 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10139 | if (sec == NULL) | |
10140 | as_bad (_("%s: no such section"), secname); | |
10141 | *input_line_pointer = c; | |
10142 | ||
10143 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10144 | flag = BSF_FUNCTION; | |
10145 | } | |
10146 | ||
49309057 | 10147 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10148 | |
10149 | S_SET_EXTERNAL (symbolP); | |
10150 | demand_empty_rest_of_line (); | |
10151 | } | |
10152 | ||
10153 | static void | |
10154 | s_option (x) | |
43841e91 | 10155 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10156 | { |
10157 | char *opt; | |
10158 | char c; | |
10159 | ||
10160 | opt = input_line_pointer; | |
10161 | c = get_symbol_end (); | |
10162 | ||
10163 | if (*opt == 'O') | |
10164 | { | |
10165 | /* FIXME: What does this mean? */ | |
10166 | } | |
10167 | else if (strncmp (opt, "pic", 3) == 0) | |
10168 | { | |
10169 | int i; | |
10170 | ||
10171 | i = atoi (opt + 3); | |
10172 | if (i == 0) | |
10173 | mips_pic = NO_PIC; | |
10174 | else if (i == 2) | |
10175 | mips_pic = SVR4_PIC; | |
10176 | else | |
10177 | as_bad (_(".option pic%d not supported"), i); | |
10178 | ||
10179 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10180 | { | |
10181 | if (g_switch_seen && g_switch_value != 0) | |
10182 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10183 | g_switch_value = 0; | |
10184 | bfd_set_gp_size (stdoutput, 0); | |
10185 | } | |
10186 | } | |
10187 | else | |
10188 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10189 | ||
10190 | *input_line_pointer = c; | |
10191 | demand_empty_rest_of_line (); | |
10192 | } | |
10193 | ||
10194 | /* This structure is used to hold a stack of .set values. */ | |
10195 | ||
e972090a NC |
10196 | struct mips_option_stack |
10197 | { | |
252b5132 RH |
10198 | struct mips_option_stack *next; |
10199 | struct mips_set_options options; | |
10200 | }; | |
10201 | ||
10202 | static struct mips_option_stack *mips_opts_stack; | |
10203 | ||
10204 | /* Handle the .set pseudo-op. */ | |
10205 | ||
10206 | static void | |
10207 | s_mipsset (x) | |
43841e91 | 10208 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10209 | { |
10210 | char *name = input_line_pointer, ch; | |
10211 | ||
10212 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10213 | input_line_pointer++; | |
10214 | ch = *input_line_pointer; | |
10215 | *input_line_pointer = '\0'; | |
10216 | ||
10217 | if (strcmp (name, "reorder") == 0) | |
10218 | { | |
10219 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10220 | { | |
10221 | /* If we still have pending nops, we can discard them. The | |
10222 | usual nop handling will insert any that are still | |
bdaaa2e1 | 10223 | needed. */ |
252b5132 RH |
10224 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10225 | * (mips_opts.mips16 ? 2 : 4)); | |
10226 | prev_nop_frag = NULL; | |
10227 | } | |
10228 | mips_opts.noreorder = 0; | |
10229 | } | |
10230 | else if (strcmp (name, "noreorder") == 0) | |
10231 | { | |
10232 | mips_emit_delays (true); | |
10233 | mips_opts.noreorder = 1; | |
10234 | mips_any_noreorder = 1; | |
10235 | } | |
10236 | else if (strcmp (name, "at") == 0) | |
10237 | { | |
10238 | mips_opts.noat = 0; | |
10239 | } | |
10240 | else if (strcmp (name, "noat") == 0) | |
10241 | { | |
10242 | mips_opts.noat = 1; | |
10243 | } | |
10244 | else if (strcmp (name, "macro") == 0) | |
10245 | { | |
10246 | mips_opts.warn_about_macros = 0; | |
10247 | } | |
10248 | else if (strcmp (name, "nomacro") == 0) | |
10249 | { | |
10250 | if (mips_opts.noreorder == 0) | |
10251 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10252 | mips_opts.warn_about_macros = 1; | |
10253 | } | |
10254 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10255 | { | |
10256 | mips_opts.nomove = 0; | |
10257 | } | |
10258 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10259 | { | |
10260 | mips_opts.nomove = 1; | |
10261 | } | |
10262 | else if (strcmp (name, "bopt") == 0) | |
10263 | { | |
10264 | mips_opts.nobopt = 0; | |
10265 | } | |
10266 | else if (strcmp (name, "nobopt") == 0) | |
10267 | { | |
10268 | mips_opts.nobopt = 1; | |
10269 | } | |
10270 | else if (strcmp (name, "mips16") == 0 | |
10271 | || strcmp (name, "MIPS-16") == 0) | |
10272 | mips_opts.mips16 = 1; | |
10273 | else if (strcmp (name, "nomips16") == 0 | |
10274 | || strcmp (name, "noMIPS-16") == 0) | |
10275 | mips_opts.mips16 = 0; | |
10276 | else if (strncmp (name, "mips", 4) == 0) | |
10277 | { | |
10278 | int isa; | |
10279 | ||
10280 | /* Permit the user to change the ISA on the fly. Needless to | |
10281 | say, misuse can cause serious problems. */ | |
10282 | isa = atoi (name + 4); | |
e7af610e NC |
10283 | switch (isa) |
10284 | { | |
84ea6cf2 NC |
10285 | case 0: mips_opts.isa = file_mips_isa; break; |
10286 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
10287 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
10288 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
10289 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
10290 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
10291 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
10292 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
10293 | default: as_bad (_("unknown ISA level")); break; | |
e7af610e | 10294 | } |
252b5132 RH |
10295 | } |
10296 | else if (strcmp (name, "autoextend") == 0) | |
10297 | mips_opts.noautoextend = 0; | |
10298 | else if (strcmp (name, "noautoextend") == 0) | |
10299 | mips_opts.noautoextend = 1; | |
10300 | else if (strcmp (name, "push") == 0) | |
10301 | { | |
10302 | struct mips_option_stack *s; | |
10303 | ||
10304 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10305 | s->next = mips_opts_stack; | |
10306 | s->options = mips_opts; | |
10307 | mips_opts_stack = s; | |
10308 | } | |
10309 | else if (strcmp (name, "pop") == 0) | |
10310 | { | |
10311 | struct mips_option_stack *s; | |
10312 | ||
10313 | s = mips_opts_stack; | |
10314 | if (s == NULL) | |
10315 | as_bad (_(".set pop with no .set push")); | |
10316 | else | |
10317 | { | |
10318 | /* If we're changing the reorder mode we need to handle | |
10319 | delay slots correctly. */ | |
10320 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10321 | mips_emit_delays (true); | |
10322 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10323 | { | |
10324 | if (prev_nop_frag != NULL) | |
10325 | { | |
10326 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10327 | * (mips_opts.mips16 ? 2 : 4)); | |
10328 | prev_nop_frag = NULL; | |
10329 | } | |
10330 | } | |
10331 | ||
10332 | mips_opts = s->options; | |
10333 | mips_opts_stack = s->next; | |
10334 | free (s); | |
10335 | } | |
10336 | } | |
10337 | else | |
10338 | { | |
10339 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
10340 | } | |
10341 | *input_line_pointer = ch; | |
10342 | demand_empty_rest_of_line (); | |
10343 | } | |
10344 | ||
10345 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
10346 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10347 | ||
10348 | static void | |
10349 | s_abicalls (ignore) | |
43841e91 | 10350 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10351 | { |
10352 | mips_pic = SVR4_PIC; | |
10353 | if (USE_GLOBAL_POINTER_OPT) | |
10354 | { | |
10355 | if (g_switch_seen && g_switch_value != 0) | |
10356 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10357 | g_switch_value = 0; | |
10358 | } | |
10359 | bfd_set_gp_size (stdoutput, 0); | |
10360 | demand_empty_rest_of_line (); | |
10361 | } | |
10362 | ||
10363 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10364 | PIC code. It sets the $gp register for the function based on the | |
10365 | function address, which is in the register named in the argument. | |
10366 | This uses a relocation against _gp_disp, which is handled specially | |
10367 | by the linker. The result is: | |
10368 | lui $gp,%hi(_gp_disp) | |
10369 | addiu $gp,$gp,%lo(_gp_disp) | |
10370 | addu $gp,$gp,.cpload argument | |
10371 | The .cpload argument is normally $25 == $t9. */ | |
10372 | ||
10373 | static void | |
10374 | s_cpload (ignore) | |
43841e91 | 10375 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10376 | { |
10377 | expressionS ex; | |
10378 | int icnt = 0; | |
10379 | ||
10380 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ | |
10381 | if (mips_pic != SVR4_PIC) | |
10382 | { | |
10383 | s_ignore (0); | |
10384 | return; | |
10385 | } | |
10386 | ||
10387 | /* .cpload should be a in .set noreorder section. */ | |
10388 | if (mips_opts.noreorder == 0) | |
10389 | as_warn (_(".cpload not in noreorder section")); | |
10390 | ||
10391 | ex.X_op = O_symbol; | |
10392 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10393 | ex.X_op_symbol = NULL; | |
10394 | ex.X_add_number = 0; | |
10395 | ||
10396 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 10397 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
10398 | |
10399 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
10400 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
10401 | (int) BFD_RELOC_LO16); | |
10402 | ||
10403 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
10404 | GP, GP, tc_get_register (0)); | |
10405 | ||
10406 | demand_empty_rest_of_line (); | |
10407 | } | |
10408 | ||
10409 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10410 | offset from $sp. The offset is remembered, and after making a PIC | |
10411 | call $gp is restored from that location. */ | |
10412 | ||
10413 | static void | |
10414 | s_cprestore (ignore) | |
43841e91 | 10415 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10416 | { |
10417 | expressionS ex; | |
10418 | int icnt = 0; | |
10419 | ||
10420 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ | |
10421 | if (mips_pic != SVR4_PIC) | |
10422 | { | |
10423 | s_ignore (0); | |
10424 | return; | |
10425 | } | |
10426 | ||
10427 | mips_cprestore_offset = get_absolute_expression (); | |
10428 | ||
10429 | ex.X_op = O_constant; | |
10430 | ex.X_add_symbol = NULL; | |
10431 | ex.X_op_symbol = NULL; | |
10432 | ex.X_add_number = mips_cprestore_offset; | |
10433 | ||
10434 | macro_build ((char *) NULL, &icnt, &ex, | |
10435 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10436 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10437 | ? "sw" : "sd"), |
10438 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
10439 | ||
10440 | demand_empty_rest_of_line (); | |
10441 | } | |
10442 | ||
10443 | /* Handle the .gpword pseudo-op. This is used when generating PIC | |
10444 | code. It generates a 32 bit GP relative reloc. */ | |
10445 | ||
10446 | static void | |
10447 | s_gpword (ignore) | |
43841e91 | 10448 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10449 | { |
10450 | symbolS *label; | |
10451 | expressionS ex; | |
10452 | char *p; | |
10453 | ||
10454 | /* When not generating PIC code, this is treated as .word. */ | |
10455 | if (mips_pic != SVR4_PIC) | |
10456 | { | |
10457 | s_cons (2); | |
10458 | return; | |
10459 | } | |
10460 | ||
10461 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10462 | mips_emit_delays (true); | |
10463 | if (auto_align) | |
10464 | mips_align (2, 0, label); | |
10465 | mips_clear_insn_labels (); | |
10466 | ||
10467 | expression (&ex); | |
10468 | ||
10469 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10470 | { | |
10471 | as_bad (_("Unsupported use of .gpword")); | |
10472 | ignore_rest_of_line (); | |
10473 | } | |
10474 | ||
10475 | p = frag_more (4); | |
10476 | md_number_to_chars (p, (valueT) 0, 4); | |
10477 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10478 | BFD_RELOC_MIPS_GPREL32); | |
10479 | ||
10480 | demand_empty_rest_of_line (); | |
10481 | } | |
10482 | ||
10483 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10484 | tables in SVR4 PIC code. */ | |
10485 | ||
10486 | static void | |
10487 | s_cpadd (ignore) | |
43841e91 | 10488 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10489 | { |
10490 | int icnt = 0; | |
10491 | int reg; | |
10492 | ||
10493 | /* This is ignored when not generating SVR4 PIC code. */ | |
10494 | if (mips_pic != SVR4_PIC) | |
10495 | { | |
10496 | s_ignore (0); | |
10497 | return; | |
10498 | } | |
10499 | ||
10500 | /* Add $gp to the register named as an argument. */ | |
10501 | reg = tc_get_register (0); | |
10502 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
10503 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10504 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10505 | ? "addu" : "daddu"), |
10506 | "d,v,t", reg, reg, GP); | |
10507 | ||
bdaaa2e1 | 10508 | demand_empty_rest_of_line (); |
252b5132 RH |
10509 | } |
10510 | ||
10511 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
10512 | mips16 mode. This permits the linker to handle them specially, | |
10513 | such as generating jalx instructions when needed. We also make | |
10514 | them odd for the duration of the assembly, in order to generate the | |
10515 | right sort of code. We will make them even in the adjust_symtab | |
10516 | routine, while leaving them marked. This is convenient for the | |
10517 | debugger and the disassembler. The linker knows to make them odd | |
10518 | again. */ | |
10519 | ||
10520 | static void | |
10521 | s_insn (ignore) | |
43841e91 | 10522 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10523 | { |
10524 | if (mips_opts.mips16) | |
10525 | mips16_mark_labels (); | |
10526 | ||
10527 | demand_empty_rest_of_line (); | |
10528 | } | |
10529 | ||
10530 | /* Handle a .stabn directive. We need these in order to mark a label | |
10531 | as being a mips16 text label correctly. Sometimes the compiler | |
10532 | will emit a label, followed by a .stabn, and then switch sections. | |
10533 | If the label and .stabn are in mips16 mode, then the label is | |
10534 | really a mips16 text label. */ | |
10535 | ||
10536 | static void | |
10537 | s_mips_stab (type) | |
10538 | int type; | |
10539 | { | |
10540 | if (type == 'n' && mips_opts.mips16) | |
10541 | mips16_mark_labels (); | |
10542 | ||
10543 | s_stab (type); | |
10544 | } | |
10545 | ||
10546 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
10547 | */ | |
10548 | ||
10549 | static void | |
10550 | s_mips_weakext (ignore) | |
43841e91 | 10551 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10552 | { |
10553 | char *name; | |
10554 | int c; | |
10555 | symbolS *symbolP; | |
10556 | expressionS exp; | |
10557 | ||
10558 | name = input_line_pointer; | |
10559 | c = get_symbol_end (); | |
10560 | symbolP = symbol_find_or_make (name); | |
10561 | S_SET_WEAK (symbolP); | |
10562 | *input_line_pointer = c; | |
10563 | ||
10564 | SKIP_WHITESPACE (); | |
10565 | ||
10566 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10567 | { | |
10568 | if (S_IS_DEFINED (symbolP)) | |
10569 | { | |
10570 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10571 | S_GET_NAME (symbolP)); | |
10572 | ignore_rest_of_line (); | |
10573 | return; | |
10574 | } | |
bdaaa2e1 | 10575 | |
252b5132 RH |
10576 | if (*input_line_pointer == ',') |
10577 | { | |
10578 | ++input_line_pointer; | |
10579 | SKIP_WHITESPACE (); | |
10580 | } | |
bdaaa2e1 | 10581 | |
252b5132 RH |
10582 | expression (&exp); |
10583 | if (exp.X_op != O_symbol) | |
10584 | { | |
10585 | as_bad ("bad .weakext directive"); | |
10586 | ignore_rest_of_line(); | |
10587 | return; | |
10588 | } | |
49309057 | 10589 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
10590 | } |
10591 | ||
10592 | demand_empty_rest_of_line (); | |
10593 | } | |
10594 | ||
10595 | /* Parse a register string into a number. Called from the ECOFF code | |
10596 | to parse .frame. The argument is non-zero if this is the frame | |
10597 | register, so that we can record it in mips_frame_reg. */ | |
10598 | ||
10599 | int | |
10600 | tc_get_register (frame) | |
10601 | int frame; | |
10602 | { | |
10603 | int reg; | |
10604 | ||
10605 | SKIP_WHITESPACE (); | |
10606 | if (*input_line_pointer++ != '$') | |
10607 | { | |
10608 | as_warn (_("expected `$'")); | |
10609 | reg = 0; | |
10610 | } | |
10611 | else if (isdigit ((unsigned char) *input_line_pointer)) | |
10612 | { | |
10613 | reg = get_absolute_expression (); | |
10614 | if (reg < 0 || reg >= 32) | |
10615 | { | |
10616 | as_warn (_("Bad register number")); | |
10617 | reg = 0; | |
10618 | } | |
10619 | } | |
10620 | else | |
10621 | { | |
10622 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
10623 | reg = FP; | |
10624 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
10625 | reg = SP; | |
10626 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
10627 | reg = GP; | |
10628 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
10629 | reg = AT; | |
10630 | else | |
10631 | { | |
10632 | as_warn (_("Unrecognized register name")); | |
10633 | reg = 0; | |
10634 | } | |
10635 | input_line_pointer += 2; | |
10636 | } | |
10637 | if (frame) | |
10638 | mips_frame_reg = reg != 0 ? reg : SP; | |
10639 | return reg; | |
10640 | } | |
10641 | ||
10642 | valueT | |
10643 | md_section_align (seg, addr) | |
10644 | asection *seg; | |
10645 | valueT addr; | |
10646 | { | |
10647 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10648 | ||
10649 | #ifdef OBJ_ELF | |
10650 | /* We don't need to align ELF sections to the full alignment. | |
10651 | However, Irix 5 may prefer that we align them at least to a 16 | |
10652 | byte boundary. We don't bother to align the sections if we are | |
10653 | targeted for an embedded system. */ | |
10654 | if (strcmp (TARGET_OS, "elf") == 0) | |
10655 | return addr; | |
10656 | if (align > 4) | |
10657 | align = 4; | |
10658 | #endif | |
10659 | ||
10660 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
10661 | } | |
10662 | ||
10663 | /* Utility routine, called from above as well. If called while the | |
10664 | input file is still being read, it's only an approximation. (For | |
10665 | example, a symbol may later become defined which appeared to be | |
10666 | undefined earlier.) */ | |
10667 | ||
10668 | static int | |
10669 | nopic_need_relax (sym, before_relaxing) | |
10670 | symbolS *sym; | |
10671 | int before_relaxing; | |
10672 | { | |
10673 | if (sym == 0) | |
10674 | return 0; | |
10675 | ||
10676 | if (USE_GLOBAL_POINTER_OPT) | |
10677 | { | |
10678 | const char *symname; | |
10679 | int change; | |
10680 | ||
10681 | /* Find out whether this symbol can be referenced off the GP | |
10682 | register. It can be if it is smaller than the -G size or if | |
10683 | it is in the .sdata or .sbss section. Certain symbols can | |
10684 | not be referenced off the GP, although it appears as though | |
10685 | they can. */ | |
10686 | symname = S_GET_NAME (sym); | |
10687 | if (symname != (const char *) NULL | |
10688 | && (strcmp (symname, "eprol") == 0 | |
10689 | || strcmp (symname, "etext") == 0 | |
10690 | || strcmp (symname, "_gp") == 0 | |
10691 | || strcmp (symname, "edata") == 0 | |
10692 | || strcmp (symname, "_fbss") == 0 | |
10693 | || strcmp (symname, "_fdata") == 0 | |
10694 | || strcmp (symname, "_ftext") == 0 | |
10695 | || strcmp (symname, "end") == 0 | |
10696 | || strcmp (symname, "_gp_disp") == 0)) | |
10697 | change = 1; | |
10698 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
10699 | && (0 | |
10700 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
10701 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
10702 | && (symbol_get_obj (sym)->ecoff_extern_size | |
10703 | <= g_switch_value)) | |
252b5132 RH |
10704 | #endif |
10705 | /* We must defer this decision until after the whole | |
10706 | file has been read, since there might be a .extern | |
10707 | after the first use of this symbol. */ | |
10708 | || (before_relaxing | |
10709 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 10710 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
10711 | #endif |
10712 | && S_GET_VALUE (sym) == 0) | |
10713 | || (S_GET_VALUE (sym) != 0 | |
10714 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10715 | change = 0; | |
10716 | else | |
10717 | { | |
10718 | const char *segname; | |
10719 | ||
10720 | segname = segment_name (S_GET_SEGMENT (sym)); | |
10721 | assert (strcmp (segname, ".lit8") != 0 | |
10722 | && strcmp (segname, ".lit4") != 0); | |
10723 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
10724 | && strcmp (segname, ".sbss") != 0 |
10725 | && strncmp (segname, ".sdata.", 7) != 0 | |
10726 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
10727 | } |
10728 | return change; | |
10729 | } | |
10730 | else | |
10731 | /* We are not optimizing for the GP register. */ | |
10732 | return 1; | |
10733 | } | |
10734 | ||
10735 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
10736 | extended opcode. SEC is the section the frag is in. */ | |
10737 | ||
10738 | static int | |
10739 | mips16_extended_frag (fragp, sec, stretch) | |
10740 | fragS *fragp; | |
10741 | asection *sec; | |
10742 | long stretch; | |
10743 | { | |
10744 | int type; | |
10745 | register const struct mips16_immed_operand *op; | |
10746 | offsetT val; | |
10747 | int mintiny, maxtiny; | |
10748 | segT symsec; | |
10749 | ||
10750 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
10751 | return 0; | |
10752 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10753 | return 1; | |
10754 | ||
10755 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10756 | op = mips16_immed_operands; | |
10757 | while (op->type != type) | |
10758 | { | |
10759 | ++op; | |
10760 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10761 | } | |
10762 | ||
10763 | if (op->unsp) | |
10764 | { | |
10765 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10766 | { | |
10767 | mintiny = 1; | |
10768 | maxtiny = 1 << op->nbits; | |
10769 | } | |
10770 | else | |
10771 | { | |
10772 | mintiny = 0; | |
10773 | maxtiny = (1 << op->nbits) - 1; | |
10774 | } | |
10775 | } | |
10776 | else | |
10777 | { | |
10778 | mintiny = - (1 << (op->nbits - 1)); | |
10779 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10780 | } | |
10781 | ||
49309057 ILT |
10782 | /* We can't always call S_GET_VALUE here, because we don't want to |
10783 | lock in a particular frag address. */ | |
10784 | if (symbol_constant_p (fragp->fr_symbol)) | |
252b5132 | 10785 | { |
49309057 ILT |
10786 | val = (S_GET_VALUE (fragp->fr_symbol) |
10787 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
252b5132 RH |
10788 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
10789 | } | |
49309057 ILT |
10790 | else if (symbol_equated_p (fragp->fr_symbol) |
10791 | && (symbol_constant_p | |
10792 | (symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol))) | |
252b5132 | 10793 | { |
49309057 ILT |
10794 | symbolS *eqsym; |
10795 | ||
10796 | eqsym = symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol; | |
10797 | val = (S_GET_VALUE (eqsym) | |
10798 | + symbol_get_frag (eqsym)->fr_address | |
10799 | + symbol_get_value_expression (fragp->fr_symbol)->X_add_number | |
10800 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
10801 | symsec = S_GET_SEGMENT (eqsym); | |
252b5132 RH |
10802 | } |
10803 | else | |
10804 | return 1; | |
10805 | ||
10806 | if (op->pcrel) | |
10807 | { | |
10808 | addressT addr; | |
10809 | ||
10810 | /* We won't have the section when we are called from | |
10811 | mips_relax_frag. However, we will always have been called | |
10812 | from md_estimate_size_before_relax first. If this is a | |
10813 | branch to a different section, we mark it as such. If SEC is | |
10814 | NULL, and the frag is not marked, then it must be a branch to | |
10815 | the same section. */ | |
10816 | if (sec == NULL) | |
10817 | { | |
10818 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10819 | return 1; | |
10820 | } | |
10821 | else | |
10822 | { | |
10823 | if (symsec != sec) | |
10824 | { | |
10825 | fragp->fr_subtype = | |
10826 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10827 | ||
10828 | /* FIXME: We should support this, and let the linker | |
10829 | catch branches and loads that are out of range. */ | |
10830 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10831 | _("unsupported PC relative reference to different section")); | |
10832 | ||
10833 | return 1; | |
10834 | } | |
10835 | } | |
10836 | ||
10837 | /* In this case, we know for sure that the symbol fragment is in | |
10838 | the same section. If the fr_address of the symbol fragment | |
10839 | is greater then the address of this fragment we want to add | |
10840 | in STRETCH in order to get a better estimate of the address. | |
10841 | This particularly matters because of the shift bits. */ | |
10842 | if (stretch != 0 | |
49309057 ILT |
10843 | && (symbol_get_frag (fragp->fr_symbol)->fr_address |
10844 | >= fragp->fr_address)) | |
252b5132 RH |
10845 | { |
10846 | fragS *f; | |
10847 | ||
10848 | /* Adjust stretch for any alignment frag. Note that if have | |
10849 | been expanding the earlier code, the symbol may be | |
10850 | defined in what appears to be an earlier frag. FIXME: | |
10851 | This doesn't handle the fr_subtype field, which specifies | |
10852 | a maximum number of bytes to skip when doing an | |
10853 | alignment. */ | |
10854 | for (f = fragp; | |
49309057 | 10855 | f != NULL && f != symbol_get_frag (fragp->fr_symbol); |
252b5132 RH |
10856 | f = f->fr_next) |
10857 | { | |
10858 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
10859 | { | |
10860 | if (stretch < 0) | |
10861 | stretch = - ((- stretch) | |
10862 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10863 | else | |
10864 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10865 | if (stretch == 0) | |
10866 | break; | |
10867 | } | |
10868 | } | |
10869 | if (f != NULL) | |
10870 | val += stretch; | |
10871 | } | |
10872 | ||
10873 | addr = fragp->fr_address + fragp->fr_fix; | |
10874 | ||
10875 | /* The base address rules are complicated. The base address of | |
10876 | a branch is the following instruction. The base address of a | |
10877 | PC relative load or add is the instruction itself, but if it | |
10878 | is in a delay slot (in which case it can not be extended) use | |
10879 | the address of the instruction whose delay slot it is in. */ | |
10880 | if (type == 'p' || type == 'q') | |
10881 | { | |
10882 | addr += 2; | |
10883 | ||
10884 | /* If we are currently assuming that this frag should be | |
10885 | extended, then, the current address is two bytes | |
bdaaa2e1 | 10886 | higher. */ |
252b5132 RH |
10887 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
10888 | addr += 2; | |
10889 | ||
10890 | /* Ignore the low bit in the target, since it will be set | |
10891 | for a text label. */ | |
10892 | if ((val & 1) != 0) | |
10893 | --val; | |
10894 | } | |
10895 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
10896 | addr -= 4; | |
10897 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10898 | addr -= 2; | |
10899 | ||
10900 | val -= addr & ~ ((1 << op->shift) - 1); | |
10901 | ||
10902 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10903 | if (type == 'p' || type == 'q') | |
10904 | val /= 2; | |
10905 | ||
10906 | /* If any of the shifted bits are set, we must use an extended | |
10907 | opcode. If the address depends on the size of this | |
10908 | instruction, this can lead to a loop, so we arrange to always | |
10909 | use an extended opcode. We only check this when we are in | |
10910 | the main relaxation loop, when SEC is NULL. */ | |
10911 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10912 | { | |
10913 | fragp->fr_subtype = | |
10914 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10915 | return 1; | |
10916 | } | |
10917 | ||
10918 | /* If we are about to mark a frag as extended because the value | |
10919 | is precisely maxtiny + 1, then there is a chance of an | |
10920 | infinite loop as in the following code: | |
10921 | la $4,foo | |
10922 | .skip 1020 | |
10923 | .align 2 | |
10924 | foo: | |
10925 | In this case when the la is extended, foo is 0x3fc bytes | |
10926 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10927 | the la must be extended. To avoid this loop, we mark the | |
10928 | frag as extended if it was small, and is about to become | |
10929 | extended with a value of maxtiny + 1. */ | |
10930 | if (val == ((maxtiny + 1) << op->shift) | |
10931 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10932 | && sec == NULL) | |
10933 | { | |
10934 | fragp->fr_subtype = | |
10935 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10936 | return 1; | |
10937 | } | |
10938 | } | |
10939 | else if (symsec != absolute_section && sec != NULL) | |
10940 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
10941 | ||
10942 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10943 | || val < (mintiny << op->shift) | |
10944 | || val > (maxtiny << op->shift)) | |
10945 | return 1; | |
10946 | else | |
10947 | return 0; | |
10948 | } | |
10949 | ||
10950 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10951 | mips16, we are not really relaxing here, and the final size is | |
10952 | encoded in the subtype information. For the mips16, we have to | |
10953 | decide whether we are using an extended opcode or not. */ | |
10954 | ||
252b5132 RH |
10955 | int |
10956 | md_estimate_size_before_relax (fragp, segtype) | |
10957 | fragS *fragp; | |
10958 | asection *segtype; | |
10959 | { | |
43841e91 | 10960 | int change = 0; |
8614eeee | 10961 | boolean linkonce = false; |
252b5132 RH |
10962 | |
10963 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
10964 | { | |
10965 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10966 | { | |
10967 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10968 | return 4; | |
10969 | } | |
10970 | else | |
10971 | { | |
10972 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10973 | return 2; | |
10974 | } | |
10975 | } | |
10976 | ||
10977 | if (mips_pic == NO_PIC) | |
10978 | { | |
10979 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
10980 | } | |
10981 | else if (mips_pic == SVR4_PIC) | |
10982 | { | |
10983 | symbolS *sym; | |
10984 | asection *symsec; | |
10985 | ||
10986 | sym = fragp->fr_symbol; | |
10987 | ||
10988 | /* Handle the case of a symbol equated to another symbol. */ | |
49309057 | 10989 | while (symbol_equated_p (sym) |
252b5132 RH |
10990 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
10991 | { | |
10992 | symbolS *n; | |
10993 | ||
10994 | /* It's possible to get a loop here in a badly written | |
10995 | program. */ | |
49309057 | 10996 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
10997 | if (n == sym) |
10998 | break; | |
10999 | sym = n; | |
11000 | } | |
11001 | ||
11002 | symsec = S_GET_SEGMENT (sym); | |
11003 | ||
8614eeee UC |
11004 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
11005 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
11006 | { |
11007 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
11008 | != 0) | |
11009 | linkonce = true; | |
11010 | ||
11011 | /* The GNU toolchain uses an extension for ELF: a section | |
11012 | beginning with the magic string .gnu.linkonce is a linkonce | |
11013 | section. */ | |
11014 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
11015 | sizeof ".gnu.linkonce" - 1) == 0) | |
11016 | linkonce = true; | |
11017 | } | |
8614eeee | 11018 | |
252b5132 RH |
11019 | /* This must duplicate the test in adjust_reloc_syms. */ |
11020 | change = (symsec != &bfd_und_section | |
11021 | && symsec != &bfd_abs_section | |
426b0403 | 11022 | && ! bfd_is_com_section (symsec) |
8614eeee | 11023 | && !linkonce |
426b0403 AM |
11024 | #ifdef OBJ_ELF |
11025 | /* A weak symbol is treated as external. */ | |
11026 | && ! S_IS_WEAK (sym) | |
11027 | #endif | |
11028 | ); | |
252b5132 RH |
11029 | } |
11030 | else | |
11031 | abort (); | |
11032 | ||
11033 | if (change) | |
11034 | { | |
11035 | /* Record the offset to the first reloc in the fr_opcode field. | |
11036 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11037 | must be expanded. */ | |
11038 | fragp->fr_opcode = (fragp->fr_literal | |
11039 | + fragp->fr_fix | |
11040 | - RELAX_OLD (fragp->fr_subtype) | |
11041 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11042 | /* FIXME: This really needs as_warn_where. */ | |
11043 | if (RELAX_WARN (fragp->fr_subtype)) | |
11044 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); | |
11045 | } | |
11046 | ||
11047 | if (! change) | |
11048 | return 0; | |
11049 | else | |
11050 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11051 | } | |
11052 | ||
11053 | /* This is called to see whether a reloc against a defined symbol | |
11054 | should be converted into a reloc against a section. Don't adjust | |
11055 | MIPS16 jump relocations, so we don't have to worry about the format | |
11056 | of the offset in the .o file. Don't adjust relocations against | |
11057 | mips16 symbols, so that the linker can find them if it needs to set | |
11058 | up a stub. */ | |
11059 | ||
11060 | int | |
11061 | mips_fix_adjustable (fixp) | |
11062 | fixS *fixp; | |
11063 | { | |
11064 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11065 | return 0; | |
11066 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11067 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11068 | return 0; | |
11069 | if (fixp->fx_addsy == NULL) | |
11070 | return 1; | |
11071 | #ifdef OBJ_ELF | |
11072 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
11073 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
11074 | && fixp->fx_subsy == NULL) | |
11075 | return 0; | |
11076 | #endif | |
11077 | return 1; | |
11078 | } | |
11079 | ||
11080 | /* Translate internal representation of relocation info to BFD target | |
11081 | format. */ | |
11082 | ||
11083 | arelent ** | |
11084 | tc_gen_reloc (section, fixp) | |
43841e91 | 11085 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
11086 | fixS *fixp; |
11087 | { | |
11088 | static arelent *retval[4]; | |
11089 | arelent *reloc; | |
11090 | bfd_reloc_code_real_type code; | |
11091 | ||
11092 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11093 | retval[1] = NULL; | |
11094 | ||
49309057 ILT |
11095 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11096 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11097 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11098 | ||
11099 | if (mips_pic == EMBEDDED_PIC | |
11100 | && SWITCH_TABLE (fixp)) | |
11101 | { | |
11102 | /* For a switch table entry we use a special reloc. The addend | |
11103 | is actually the difference between the reloc address and the | |
11104 | subtrahend. */ | |
11105 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11106 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
11107 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
11108 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
11109 | } | |
bb2d6cd7 GK |
11110 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
11111 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
11112 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11113 | { | |
11114 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 11115 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11116 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
11117 | else | |
11118 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11119 | } | |
11120 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11121 | { | |
11122 | assert (fixp->fx_next != NULL | |
11123 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11124 | /* We use a special addend for an internal RELHI reloc. The | |
11125 | reloc is relative to the RELLO; adjust the addend | |
11126 | accordingly. */ | |
49309057 | 11127 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11128 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
11129 | + fixp->fx_next->fx_where | |
11130 | - S_GET_VALUE (fixp->fx_subsy)); | |
11131 | else | |
11132 | reloc->addend = (fixp->fx_addnumber | |
11133 | + fixp->fx_next->fx_frag->fr_address | |
11134 | + fixp->fx_next->fx_where); | |
11135 | } | |
252b5132 RH |
11136 | else |
11137 | { | |
11138 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
11139 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11140 | handling. */ | |
11141 | reloc->addend = reloc->address; | |
11142 | else | |
11143 | reloc->addend = -reloc->address; | |
11144 | } | |
11145 | ||
11146 | /* If this is a variant frag, we may need to adjust the existing | |
11147 | reloc and generate a new one. */ | |
11148 | if (fixp->fx_frag->fr_opcode != NULL | |
11149 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11150 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11151 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
11152 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11153 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11154 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11155 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
11156 | { | |
11157 | arelent *reloc2; | |
11158 | ||
11159 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
11160 | ||
11161 | /* If this is not the last reloc in this frag, then we have two | |
11162 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
11163 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11164 | the second one handle all of them. */ | |
11165 | if (fixp->fx_next != NULL | |
11166 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11167 | { | |
11168 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11169 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11170 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11171 | && (fixp->fx_next->fx_r_type | |
11172 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11173 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11174 | && (fixp->fx_next->fx_r_type | |
11175 | == BFD_RELOC_MIPS_CALL_LO16))); | |
11176 | retval[0] = NULL; | |
11177 | return retval; | |
11178 | } | |
11179 | ||
11180 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11181 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11182 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11183 | retval[2] = NULL; | |
49309057 ILT |
11184 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11185 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11186 | reloc2->address = (reloc->address |
11187 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11188 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11189 | reloc2->addend = fixp->fx_addnumber; | |
11190 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11191 | assert (reloc2->howto != NULL); | |
11192 | ||
11193 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11194 | { | |
11195 | arelent *reloc3; | |
11196 | ||
11197 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11198 | retval[3] = NULL; | |
11199 | *reloc3 = *reloc2; | |
11200 | reloc3->address += 4; | |
11201 | } | |
11202 | ||
11203 | if (mips_pic == NO_PIC) | |
11204 | { | |
11205 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11206 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11207 | } | |
11208 | else if (mips_pic == SVR4_PIC) | |
11209 | { | |
11210 | switch (fixp->fx_r_type) | |
11211 | { | |
11212 | default: | |
11213 | abort (); | |
11214 | case BFD_RELOC_MIPS_GOT16: | |
11215 | break; | |
11216 | case BFD_RELOC_MIPS_CALL16: | |
11217 | case BFD_RELOC_MIPS_GOT_LO16: | |
11218 | case BFD_RELOC_MIPS_CALL_LO16: | |
11219 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
11220 | break; | |
11221 | } | |
11222 | } | |
11223 | else | |
11224 | abort (); | |
11225 | } | |
11226 | ||
11227 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
11228 | to be used in the relocation's section offset. */ | |
11229 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11230 | { | |
11231 | reloc->address = reloc->addend; | |
11232 | reloc->addend = 0; | |
11233 | } | |
11234 | ||
11235 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
11236 | fixup_segment converted a non-PC relative reloc into a PC | |
11237 | relative reloc. In such a case, we need to convert the reloc | |
11238 | code. */ | |
11239 | code = fixp->fx_r_type; | |
11240 | if (fixp->fx_pcrel) | |
11241 | { | |
11242 | switch (code) | |
11243 | { | |
11244 | case BFD_RELOC_8: | |
11245 | code = BFD_RELOC_8_PCREL; | |
11246 | break; | |
11247 | case BFD_RELOC_16: | |
11248 | code = BFD_RELOC_16_PCREL; | |
11249 | break; | |
11250 | case BFD_RELOC_32: | |
11251 | code = BFD_RELOC_32_PCREL; | |
11252 | break; | |
11253 | case BFD_RELOC_64: | |
11254 | code = BFD_RELOC_64_PCREL; | |
11255 | break; | |
11256 | case BFD_RELOC_8_PCREL: | |
11257 | case BFD_RELOC_16_PCREL: | |
11258 | case BFD_RELOC_32_PCREL: | |
11259 | case BFD_RELOC_64_PCREL: | |
11260 | case BFD_RELOC_16_PCREL_S2: | |
11261 | case BFD_RELOC_PCREL_HI16_S: | |
11262 | case BFD_RELOC_PCREL_LO16: | |
11263 | break; | |
11264 | default: | |
11265 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11266 | _("Cannot make %s relocation PC relative"), | |
11267 | bfd_get_reloc_code_name (code)); | |
11268 | } | |
11269 | } | |
11270 | ||
11271 | /* To support a PC relative reloc when generating embedded PIC code | |
11272 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11273 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
11274 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11275 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
11276 | && code == BFD_RELOC_16_PCREL_S2 |
11277 | && mips_pic != EMBEDDED_PIC) | |
11278 | reloc->howto = NULL; | |
11279 | else | |
11280 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
11281 | ||
11282 | if (reloc->howto == NULL) | |
11283 | { | |
11284 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11285 | _("Can not represent %s relocation in this object file format"), | |
11286 | bfd_get_reloc_code_name (code)); | |
11287 | retval[0] = NULL; | |
11288 | } | |
11289 | ||
11290 | return retval; | |
11291 | } | |
11292 | ||
11293 | /* Relax a machine dependent frag. This returns the amount by which | |
11294 | the current size of the frag should change. */ | |
11295 | ||
11296 | int | |
11297 | mips_relax_frag (fragp, stretch) | |
11298 | fragS *fragp; | |
11299 | long stretch; | |
11300 | { | |
11301 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11302 | return 0; | |
11303 | ||
11304 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11305 | { | |
11306 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11307 | return 0; | |
11308 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11309 | return 2; | |
11310 | } | |
11311 | else | |
11312 | { | |
11313 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11314 | return 0; | |
11315 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11316 | return -2; | |
11317 | } | |
11318 | ||
11319 | return 0; | |
11320 | } | |
11321 | ||
11322 | /* Convert a machine dependent frag. */ | |
11323 | ||
11324 | void | |
11325 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 11326 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
11327 | segT asec; |
11328 | fragS *fragp; | |
11329 | { | |
11330 | int old, new; | |
11331 | char *fixptr; | |
11332 | ||
11333 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11334 | { | |
11335 | int type; | |
11336 | register const struct mips16_immed_operand *op; | |
11337 | boolean small, ext; | |
11338 | offsetT val; | |
11339 | bfd_byte *buf; | |
11340 | unsigned long insn; | |
11341 | boolean use_extend; | |
11342 | unsigned short extend; | |
11343 | ||
11344 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11345 | op = mips16_immed_operands; | |
11346 | while (op->type != type) | |
11347 | ++op; | |
11348 | ||
11349 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11350 | { | |
11351 | small = false; | |
11352 | ext = true; | |
11353 | } | |
11354 | else | |
11355 | { | |
11356 | small = true; | |
11357 | ext = false; | |
11358 | } | |
11359 | ||
6386f3a7 | 11360 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
11361 | val = S_GET_VALUE (fragp->fr_symbol); |
11362 | if (op->pcrel) | |
11363 | { | |
11364 | addressT addr; | |
11365 | ||
11366 | addr = fragp->fr_address + fragp->fr_fix; | |
11367 | ||
11368 | /* The rules for the base address of a PC relative reloc are | |
11369 | complicated; see mips16_extended_frag. */ | |
11370 | if (type == 'p' || type == 'q') | |
11371 | { | |
11372 | addr += 2; | |
11373 | if (ext) | |
11374 | addr += 2; | |
11375 | /* Ignore the low bit in the target, since it will be | |
11376 | set for a text label. */ | |
11377 | if ((val & 1) != 0) | |
11378 | --val; | |
11379 | } | |
11380 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11381 | addr -= 4; | |
11382 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11383 | addr -= 2; | |
11384 | ||
11385 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
11386 | val -= addr; | |
11387 | ||
11388 | /* Make sure the section winds up with the alignment we have | |
11389 | assumed. */ | |
11390 | if (op->shift > 0) | |
11391 | record_alignment (asec, op->shift); | |
11392 | } | |
11393 | ||
11394 | if (ext | |
11395 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11396 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11397 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11398 | _("extended instruction in delay slot")); | |
11399 | ||
11400 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
11401 | ||
11402 | if (target_big_endian) | |
11403 | insn = bfd_getb16 (buf); | |
11404 | else | |
11405 | insn = bfd_getl16 (buf); | |
11406 | ||
11407 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
11408 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11409 | small, ext, &insn, &use_extend, &extend); | |
11410 | ||
11411 | if (use_extend) | |
11412 | { | |
11413 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11414 | fragp->fr_fix += 2; | |
11415 | buf += 2; | |
11416 | } | |
11417 | ||
11418 | md_number_to_chars (buf, insn, 2); | |
11419 | fragp->fr_fix += 2; | |
11420 | buf += 2; | |
11421 | } | |
11422 | else | |
11423 | { | |
11424 | if (fragp->fr_opcode == NULL) | |
11425 | return; | |
11426 | ||
11427 | old = RELAX_OLD (fragp->fr_subtype); | |
11428 | new = RELAX_NEW (fragp->fr_subtype); | |
11429 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
11430 | ||
11431 | if (new > 0) | |
11432 | memcpy (fixptr - old, fixptr, new); | |
11433 | ||
11434 | fragp->fr_fix += new - old; | |
11435 | } | |
11436 | } | |
11437 | ||
11438 | #ifdef OBJ_ELF | |
11439 | ||
11440 | /* This function is called after the relocs have been generated. | |
11441 | We've been storing mips16 text labels as odd. Here we convert them | |
11442 | back to even for the convenience of the debugger. */ | |
11443 | ||
11444 | void | |
11445 | mips_frob_file_after_relocs () | |
11446 | { | |
11447 | asymbol **syms; | |
11448 | unsigned int count, i; | |
11449 | ||
11450 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11451 | return; | |
11452 | ||
11453 | syms = bfd_get_outsymbols (stdoutput); | |
11454 | count = bfd_get_symcount (stdoutput); | |
11455 | for (i = 0; i < count; i++, syms++) | |
11456 | { | |
11457 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11458 | && ((*syms)->value & 1) != 0) | |
11459 | { | |
11460 | (*syms)->value &= ~1; | |
11461 | /* If the symbol has an odd size, it was probably computed | |
11462 | incorrectly, so adjust that as well. */ | |
11463 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11464 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11465 | } | |
11466 | } | |
11467 | } | |
11468 | ||
11469 | #endif | |
11470 | ||
11471 | /* This function is called whenever a label is defined. It is used | |
11472 | when handling branch delays; if a branch has a label, we assume we | |
11473 | can not move it. */ | |
11474 | ||
11475 | void | |
11476 | mips_define_label (sym) | |
11477 | symbolS *sym; | |
11478 | { | |
11479 | struct insn_label_list *l; | |
11480 | ||
11481 | if (free_insn_labels == NULL) | |
11482 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11483 | else | |
11484 | { | |
11485 | l = free_insn_labels; | |
11486 | free_insn_labels = l->next; | |
11487 | } | |
11488 | ||
11489 | l->label = sym; | |
11490 | l->next = insn_labels; | |
11491 | insn_labels = l; | |
11492 | } | |
11493 | \f | |
11494 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11495 | ||
11496 | /* Some special processing for a MIPS ELF file. */ | |
11497 | ||
11498 | void | |
11499 | mips_elf_final_processing () | |
11500 | { | |
11501 | /* Write out the register information. */ | |
11502 | if (! mips_64) | |
11503 | { | |
11504 | Elf32_RegInfo s; | |
11505 | ||
11506 | s.ri_gprmask = mips_gprmask; | |
11507 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11508 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11509 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11510 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11511 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11512 | ||
11513 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11514 | ((Elf32_External_RegInfo *) | |
11515 | mips_regmask_frag)); | |
11516 | } | |
11517 | else | |
11518 | { | |
11519 | Elf64_Internal_RegInfo s; | |
11520 | ||
11521 | s.ri_gprmask = mips_gprmask; | |
11522 | s.ri_pad = 0; | |
11523 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11524 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11525 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11526 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11527 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11528 | ||
11529 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11530 | ((Elf64_External_RegInfo *) | |
11531 | mips_regmask_frag)); | |
11532 | } | |
11533 | ||
11534 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11535 | sort of BFD interface for this. */ | |
11536 | if (mips_any_noreorder) | |
11537 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
11538 | if (mips_pic != NO_PIC) | |
11539 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
11540 | ||
bdaaa2e1 | 11541 | /* Set the MIPS ELF ABI flags. */ |
252b5132 RH |
11542 | if (mips_abi_string == 0) |
11543 | ; | |
beae10d5 | 11544 | else if (strcmp (mips_abi_string, "32") == 0) |
252b5132 | 11545 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
beae10d5 | 11546 | else if (strcmp (mips_abi_string, "o64") == 0) |
252b5132 | 11547 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
beae10d5 | 11548 | else if (strcmp (mips_abi_string, "eabi") == 0) |
252b5132 RH |
11549 | { |
11550 | if (mips_eabi64) | |
11551 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
11552 | else | |
11553 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
11554 | } | |
11555 | ||
11556 | if (mips_32bitmode) | |
11557 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
11558 | } | |
11559 | ||
11560 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
11561 | \f | |
beae10d5 KH |
11562 | typedef struct proc { |
11563 | symbolS *isym; | |
11564 | unsigned long reg_mask; | |
11565 | unsigned long reg_offset; | |
11566 | unsigned long fpreg_mask; | |
11567 | unsigned long fpreg_offset; | |
11568 | unsigned long frame_offset; | |
11569 | unsigned long frame_reg; | |
11570 | unsigned long pc_reg; | |
11571 | } procS; | |
252b5132 RH |
11572 | |
11573 | static procS cur_proc; | |
11574 | static procS *cur_proc_ptr; | |
11575 | static int numprocs; | |
11576 | ||
0a9ef439 | 11577 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 11578 | |
0a9ef439 RH |
11579 | void |
11580 | mips_handle_align (fragp) | |
11581 | fragS *fragp; | |
a19d8eb0 | 11582 | { |
0a9ef439 RH |
11583 | if (fragp->fr_type != rs_align_code) |
11584 | return; | |
11585 | ||
11586 | if (mips_opts.mips16) | |
a19d8eb0 CP |
11587 | { |
11588 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
11589 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
11590 | ||
0a9ef439 RH |
11591 | int bytes; |
11592 | char *p; | |
a19d8eb0 | 11593 | |
0a9ef439 RH |
11594 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
11595 | p = fragp->fr_literal + fragp->fr_fix; | |
11596 | ||
11597 | if (bytes & 1) | |
11598 | { | |
11599 | *p++ = 0; | |
11600 | fragp->fr_fix += 1; | |
11601 | } | |
11602 | ||
11603 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
11604 | fragp->fr_var = 2; | |
a19d8eb0 CP |
11605 | } |
11606 | ||
0a9ef439 | 11607 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
11608 | } |
11609 | ||
252b5132 RH |
11610 | static void |
11611 | md_obj_begin () | |
11612 | { | |
11613 | } | |
11614 | ||
11615 | static void | |
11616 | md_obj_end () | |
11617 | { | |
11618 | /* check for premature end, nesting errors, etc */ | |
11619 | if (cur_proc_ptr) | |
11620 | as_warn (_("missing `.end' at end of assembly")); | |
11621 | } | |
11622 | ||
11623 | static long | |
11624 | get_number () | |
11625 | { | |
11626 | int negative = 0; | |
11627 | long val = 0; | |
11628 | ||
11629 | if (*input_line_pointer == '-') | |
11630 | { | |
11631 | ++input_line_pointer; | |
11632 | negative = 1; | |
11633 | } | |
d9a62219 | 11634 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11635 | as_bad (_("Expected simple number.")); |
11636 | if (input_line_pointer[0] == '0') | |
11637 | { | |
11638 | if (input_line_pointer[1] == 'x') | |
11639 | { | |
11640 | input_line_pointer += 2; | |
d9a62219 | 11641 | while (isxdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11642 | { |
11643 | val <<= 4; | |
11644 | val |= hex_value (*input_line_pointer++); | |
11645 | } | |
11646 | return negative ? -val : val; | |
11647 | } | |
11648 | else | |
11649 | { | |
11650 | ++input_line_pointer; | |
d9a62219 | 11651 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11652 | { |
11653 | val <<= 3; | |
11654 | val |= *input_line_pointer++ - '0'; | |
11655 | } | |
11656 | return negative ? -val : val; | |
11657 | } | |
11658 | } | |
d9a62219 | 11659 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11660 | { |
11661 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
11662 | *input_line_pointer, *input_line_pointer); | |
11663 | as_warn (_("Invalid number")); | |
11664 | return -1; | |
11665 | } | |
d9a62219 | 11666 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11667 | { |
11668 | val *= 10; | |
11669 | val += *input_line_pointer++ - '0'; | |
11670 | } | |
11671 | return negative ? -val : val; | |
11672 | } | |
11673 | ||
11674 | /* The .file directive; just like the usual .file directive, but there | |
11675 | is an initial number which is the ECOFF file index. */ | |
11676 | ||
11677 | static void | |
11678 | s_file (x) | |
43841e91 | 11679 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11680 | { |
11681 | int line; | |
11682 | ||
11683 | line = get_number (); | |
11684 | s_app_file (0); | |
11685 | } | |
11686 | ||
252b5132 RH |
11687 | /* The .end directive. */ |
11688 | ||
11689 | static void | |
11690 | s_mips_end (x) | |
43841e91 | 11691 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11692 | { |
11693 | symbolS *p; | |
11694 | int maybe_text; | |
11695 | ||
11696 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11697 | { | |
11698 | p = get_symbol (); | |
11699 | demand_empty_rest_of_line (); | |
11700 | } | |
11701 | else | |
11702 | p = NULL; | |
11703 | ||
11704 | #ifdef BFD_ASSEMBLER | |
11705 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11706 | maybe_text = 1; | |
11707 | else | |
11708 | maybe_text = 0; | |
11709 | #else | |
11710 | if (now_seg != data_section && now_seg != bss_section) | |
11711 | maybe_text = 1; | |
11712 | else | |
11713 | maybe_text = 0; | |
11714 | #endif | |
11715 | ||
11716 | if (!maybe_text) | |
11717 | as_warn (_(".end not in text section")); | |
11718 | ||
11719 | if (!cur_proc_ptr) | |
11720 | { | |
11721 | as_warn (_(".end directive without a preceding .ent directive.")); | |
11722 | demand_empty_rest_of_line (); | |
11723 | return; | |
11724 | } | |
11725 | ||
11726 | if (p != NULL) | |
11727 | { | |
11728 | assert (S_GET_NAME (p)); | |
11729 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
11730 | as_warn (_(".end symbol does not match .ent symbol.")); | |
11731 | } | |
11732 | else | |
11733 | as_warn (_(".end directive missing or unknown symbol")); | |
11734 | ||
11735 | #ifdef MIPS_STABS_ELF | |
11736 | { | |
11737 | segT saved_seg = now_seg; | |
11738 | subsegT saved_subseg = now_subseg; | |
11739 | fragS *saved_frag = frag_now; | |
11740 | valueT dot; | |
11741 | segT seg; | |
11742 | expressionS exp; | |
11743 | char *fragp; | |
11744 | ||
11745 | dot = frag_now_fix (); | |
11746 | ||
11747 | #ifdef md_flush_pending_output | |
11748 | md_flush_pending_output (); | |
11749 | #endif | |
11750 | ||
11751 | assert (pdr_seg); | |
11752 | subseg_set (pdr_seg, 0); | |
11753 | ||
beae10d5 | 11754 | /* Write the symbol. */ |
252b5132 RH |
11755 | exp.X_op = O_symbol; |
11756 | exp.X_add_symbol = p; | |
11757 | exp.X_add_number = 0; | |
11758 | emit_expr (&exp, 4); | |
11759 | ||
beae10d5 | 11760 | fragp = frag_more (7 * 4); |
252b5132 | 11761 | |
beae10d5 KH |
11762 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
11763 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
11764 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
11765 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
11766 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
11767 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
11768 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
11769 | |
11770 | subseg_set (saved_seg, saved_subseg); | |
11771 | } | |
11772 | #endif | |
11773 | ||
11774 | cur_proc_ptr = NULL; | |
11775 | } | |
11776 | ||
11777 | /* The .aent and .ent directives. */ | |
11778 | ||
11779 | static void | |
11780 | s_mips_ent (aent) | |
11781 | int aent; | |
11782 | { | |
11783 | int number = 0; | |
11784 | symbolS *symbolP; | |
11785 | int maybe_text; | |
11786 | ||
11787 | symbolP = get_symbol (); | |
11788 | if (*input_line_pointer == ',') | |
11789 | input_line_pointer++; | |
11790 | SKIP_WHITESPACE (); | |
d9a62219 DE |
11791 | if (isdigit ((unsigned char) *input_line_pointer) |
11792 | || *input_line_pointer == '-') | |
252b5132 RH |
11793 | number = get_number (); |
11794 | ||
11795 | #ifdef BFD_ASSEMBLER | |
11796 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11797 | maybe_text = 1; | |
11798 | else | |
11799 | maybe_text = 0; | |
11800 | #else | |
11801 | if (now_seg != data_section && now_seg != bss_section) | |
11802 | maybe_text = 1; | |
11803 | else | |
11804 | maybe_text = 0; | |
11805 | #endif | |
11806 | ||
11807 | if (!maybe_text) | |
11808 | as_warn (_(".ent or .aent not in text section.")); | |
11809 | ||
11810 | if (!aent && cur_proc_ptr) | |
11811 | as_warn (_("missing `.end'")); | |
11812 | ||
11813 | if (!aent) | |
11814 | { | |
11815 | cur_proc_ptr = &cur_proc; | |
11816 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
11817 | ||
11818 | cur_proc_ptr->isym = symbolP; | |
11819 | ||
49309057 | 11820 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
11821 | |
11822 | numprocs++; | |
11823 | } | |
11824 | ||
11825 | demand_empty_rest_of_line (); | |
11826 | } | |
11827 | ||
11828 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 11829 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 11830 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 11831 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
11832 | symbol table (in the mdebug section). */ |
11833 | ||
11834 | static void | |
11835 | s_mips_frame (ignore) | |
11836 | int ignore; | |
11837 | { | |
11838 | #ifdef MIPS_STABS_ELF | |
11839 | ||
11840 | long val; | |
11841 | ||
beae10d5 | 11842 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
11843 | { |
11844 | as_warn (_(".frame outside of .ent")); | |
11845 | demand_empty_rest_of_line (); | |
11846 | return; | |
11847 | } | |
11848 | ||
11849 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
11850 | ||
11851 | SKIP_WHITESPACE (); | |
11852 | if (*input_line_pointer++ != ',' | |
11853 | || get_absolute_expression_and_terminator (&val) != ',') | |
11854 | { | |
11855 | as_warn (_("Bad .frame directive")); | |
11856 | --input_line_pointer; | |
11857 | demand_empty_rest_of_line (); | |
11858 | return; | |
11859 | } | |
11860 | ||
11861 | cur_proc_ptr->frame_offset = val; | |
11862 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
11863 | ||
11864 | demand_empty_rest_of_line (); | |
11865 | #else | |
11866 | s_ignore (ignore); | |
11867 | #endif /* MIPS_STABS_ELF */ | |
11868 | } | |
11869 | ||
bdaaa2e1 KH |
11870 | /* The .fmask and .mask directives. If the mdebug section is present |
11871 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 11872 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 11873 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
11874 | make reference to the ecoff symbol table (in the mdebug section). */ |
11875 | ||
11876 | static void | |
11877 | s_mips_mask (reg_type) | |
11878 | char reg_type; | |
11879 | { | |
11880 | #ifdef MIPS_STABS_ELF | |
11881 | long mask, off; | |
bdaaa2e1 | 11882 | |
252b5132 RH |
11883 | if (cur_proc_ptr == (procS *) NULL) |
11884 | { | |
11885 | as_warn (_(".mask/.fmask outside of .ent")); | |
11886 | demand_empty_rest_of_line (); | |
11887 | return; | |
11888 | } | |
11889 | ||
11890 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
11891 | { | |
11892 | as_warn (_("Bad .mask/.fmask directive")); | |
11893 | --input_line_pointer; | |
11894 | demand_empty_rest_of_line (); | |
11895 | return; | |
11896 | } | |
11897 | ||
11898 | off = get_absolute_expression (); | |
11899 | ||
11900 | if (reg_type == 'F') | |
11901 | { | |
11902 | cur_proc_ptr->fpreg_mask = mask; | |
11903 | cur_proc_ptr->fpreg_offset = off; | |
11904 | } | |
11905 | else | |
11906 | { | |
11907 | cur_proc_ptr->reg_mask = mask; | |
11908 | cur_proc_ptr->reg_offset = off; | |
11909 | } | |
11910 | ||
11911 | demand_empty_rest_of_line (); | |
11912 | #else | |
11913 | s_ignore (reg_type); | |
11914 | #endif /* MIPS_STABS_ELF */ | |
11915 | } | |
11916 | ||
11917 | /* The .loc directive. */ | |
11918 | ||
11919 | #if 0 | |
11920 | static void | |
11921 | s_loc (x) | |
11922 | int x; | |
11923 | { | |
11924 | symbolS *symbolP; | |
11925 | int lineno; | |
11926 | int addroff; | |
11927 | ||
11928 | assert (now_seg == text_section); | |
11929 | ||
11930 | lineno = get_number (); | |
11931 | addroff = frag_now_fix (); | |
11932 | ||
11933 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
11934 | S_SET_TYPE (symbolP, N_SLINE); | |
11935 | S_SET_OTHER (symbolP, 0); | |
11936 | S_SET_DESC (symbolP, lineno); | |
11937 | symbolP->sy_segment = now_seg; | |
11938 | } | |
11939 | #endif | |
e7af610e NC |
11940 | |
11941 | /* CPU name/ISA/number mapping table. | |
11942 | ||
11943 | Entries are grouped by type. The first matching CPU or ISA entry | |
11944 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
11945 | for that type. Entries after that within the type are sorted | |
11946 | alphabetically. | |
11947 | ||
11948 | Case is ignored in comparison, so put the canonical entry in the | |
11949 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
11950 | static const struct mips_cpu_info mips_cpu_info_table[] = |
11951 | { | |
e7af610e NC |
11952 | /* MIPS1 ISA */ |
11953 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
11954 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
11955 | ||
11956 | /* MIPS2 ISA */ | |
11957 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
11958 | ||
11959 | /* MIPS3 ISA */ | |
11960 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
11961 | ||
11962 | /* MIPS4 ISA */ | |
11963 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
11964 | ||
84ea6cf2 NC |
11965 | /* MIPS5 ISA */ |
11966 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
11967 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
11968 | ||
e7af610e NC |
11969 | /* MIPS32 ISA */ |
11970 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
11971 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, | |
11972 | ||
84ea6cf2 | 11973 | #if 1 |
e7af610e NC |
11974 | /* XXX for now, MIPS64 -> MIPS3 because of history */ |
11975 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */ | |
84ea6cf2 NC |
11976 | #else |
11977 | /* MIPS64 ISA */ | |
11978 | { "MIPS64", 1, ISA_MIPS64, CPU_MIPS64 }, | |
11979 | #endif | |
11980 | { "mips64isa", 1, ISA_MIPS64, CPU_MIPS64 }, | |
11981 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
11982 | |
11983 | /* R2000 CPU */ | |
11984 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
11985 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
11986 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
11987 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
11988 | ||
11989 | /* R3000 CPU */ | |
11990 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
11991 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
11992 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
11993 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
11994 | ||
11995 | /* TX3900 CPU */ | |
11996 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
11997 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 11998 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
11999 | |
12000 | /* R4000 CPU */ | |
12001 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12002 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
12003 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
12004 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
12005 | ||
12006 | /* R4010 CPU */ | |
12007 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12008 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
12009 | ||
12010 | /* R4400 CPU */ | |
12011 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12012 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
12013 | ||
12014 | /* R4600 CPU */ | |
12015 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12016 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
12017 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12018 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
12019 | ||
12020 | /* R4650 CPU */ | |
12021 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12022 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
12023 | ||
12024 | /* R6000 CPU */ | |
12025 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12026 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
12027 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12028 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
12029 | ||
12030 | /* R8000 CPU */ | |
12031 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12032 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
12033 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12034 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
12035 | ||
12036 | /* R10000 CPU */ | |
12037 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12038 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
12039 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12040 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
12041 | ||
d1cf510e NC |
12042 | /* R12000 CPU */ |
12043 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12044 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
12045 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12046 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
12047 | ||
e7af610e NC |
12048 | /* VR4100 CPU */ |
12049 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12050 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12051 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12052 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
12053 | ||
12054 | /* VR4111 CPU */ | |
12055 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12056 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12057 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12058 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
12059 | ||
12060 | /* VR4300 CPU */ | |
12061 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12062 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12063 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12064 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
12065 | ||
12066 | /* VR5000 CPU */ | |
12067 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12068 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12069 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
12070 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12071 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
12072 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
12073 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, | |
12074 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, | |
12075 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, | |
12076 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, | |
12077 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, | |
12078 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
12079 | ||
12080 | /* MIPS32 4K CPU */ | |
12081 | { "MIPS32-4K", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12082 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12083 | { "4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12084 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12085 | { "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12086 | { "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12087 | { "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, | |
12088 | ||
c6c98b38 NC |
12089 | /* SiByte SB-1 CPU */ |
12090 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, | |
e972090a | 12091 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
12092 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
12093 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
12094 | ||
beae10d5 | 12095 | /* End marker. */ |
e7af610e NC |
12096 | { NULL, 0, 0, 0, }, |
12097 | }; | |
12098 | ||
12099 | static const struct mips_cpu_info * | |
12100 | mips_cpu_info_from_name (name) | |
12101 | const char *name; | |
12102 | { | |
12103 | int i; | |
12104 | ||
12105 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 12106 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
12107 | return (&mips_cpu_info_table[i]); |
12108 | ||
e972090a | 12109 | return NULL; |
e7af610e NC |
12110 | } |
12111 | ||
12112 | static const struct mips_cpu_info * | |
12113 | mips_cpu_info_from_isa (isa) | |
12114 | int isa; | |
12115 | { | |
12116 | int i; | |
12117 | ||
12118 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12119 | if (mips_cpu_info_table[i].is_isa | |
12120 | && isa == mips_cpu_info_table[i].isa) | |
12121 | return (&mips_cpu_info_table[i]); | |
12122 | ||
e972090a | 12123 | return NULL; |
e7af610e NC |
12124 | } |
12125 | ||
12126 | static const struct mips_cpu_info * | |
12127 | mips_cpu_info_from_cpu (cpu) | |
12128 | int cpu; | |
12129 | { | |
12130 | int i; | |
12131 | ||
12132 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
12133 | if (!mips_cpu_info_table[i].is_isa | |
12134 | && cpu == mips_cpu_info_table[i].cpu) | |
12135 | return (&mips_cpu_info_table[i]); | |
12136 | ||
e972090a | 12137 | return NULL; |
e7af610e | 12138 | } |