Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e7c604dd | 3 | 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
741fe287 | 92 | #define ATREG 1 |
252b5132 RH |
93 | #define TREG 24 |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
741fe287 MR |
104 | #define AT mips_opts.at |
105 | ||
252b5132 RH |
106 | /* Allow override of standard little-endian ECOFF format. */ |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
8b082fb1 | 198 | int ase_dspr2; |
ef2e4d86 | 199 | int ase_mt; |
252b5132 RH |
200 | /* Whether we are assembling for the mips16 processor. 0 if we are |
201 | not, 1 if we are, and -1 if the value has not been initialized. | |
202 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
203 | -nomips16 command line options, and the default CPU. */ | |
204 | int mips16; | |
205 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
206 | reorder' and `.set noreorder'. */ | |
207 | int noreorder; | |
741fe287 MR |
208 | /* Non-zero if we should not permit the register designated "assembler |
209 | temporary" to be used in instructions. The value is the register | |
210 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
211 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
212 | unsigned int at; | |
252b5132 RH |
213 | /* Non-zero if we should warn when a macro instruction expands into |
214 | more than one machine instruction. Changed by `.set nomacro' and | |
215 | `.set macro'. */ | |
216 | int warn_about_macros; | |
217 | /* Non-zero if we should not move instructions. Changed by `.set | |
218 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
219 | int nomove; | |
220 | /* Non-zero if we should not optimize branches by moving the target | |
221 | of the branch into the delay slot. Actually, we don't perform | |
222 | this optimization anyhow. Changed by `.set bopt' and `.set | |
223 | nobopt'. */ | |
224 | int nobopt; | |
225 | /* Non-zero if we should not autoextend mips16 instructions. | |
226 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
227 | int noautoextend; | |
a325df1d TS |
228 | /* Restrict general purpose registers and floating point registers |
229 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
230 | is passed but can changed if the assembler code uses .set mipsN. */ | |
231 | int gp32; | |
232 | int fp32; | |
fef14a42 TS |
233 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
234 | command line option, and the default CPU. */ | |
235 | int arch; | |
aed1a261 RS |
236 | /* True if ".set sym32" is in effect. */ |
237 | bfd_boolean sym32; | |
037b32b9 AN |
238 | /* True if floating-point operations are not allowed. Changed by .set |
239 | softfloat or .set hardfloat, by command line options -msoft-float or | |
240 | -mhard-float. The default is false. */ | |
241 | bfd_boolean soft_float; | |
242 | ||
243 | /* True if only single-precision floating-point operations are allowed. | |
244 | Changed by .set singlefloat or .set doublefloat, command-line options | |
245 | -msingle-float or -mdouble-float. The default is false. */ | |
246 | bfd_boolean single_float; | |
252b5132 RH |
247 | }; |
248 | ||
037b32b9 AN |
249 | /* This is the struct we use to hold the current set of options. Note |
250 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
251 | -1 to indicate that they have not been initialized. */ | |
252 | ||
a325df1d | 253 | /* True if -mgp32 was passed. */ |
a8e8e863 | 254 | static int file_mips_gp32 = -1; |
a325df1d TS |
255 | |
256 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 257 | static int file_mips_fp32 = -1; |
a325df1d | 258 | |
037b32b9 AN |
259 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
260 | static int file_mips_soft_float = 0; | |
261 | ||
262 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
263 | static int file_mips_single_float = 0; | |
252b5132 | 264 | |
e972090a NC |
265 | static struct mips_set_options mips_opts = |
266 | { | |
037b32b9 AN |
267 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
268 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
269 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
270 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
271 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
272 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 273 | }; |
252b5132 RH |
274 | |
275 | /* These variables are filled in with the masks of registers used. | |
276 | The object format code reads them and puts them in the appropriate | |
277 | place. */ | |
278 | unsigned long mips_gprmask; | |
279 | unsigned long mips_cprmask[4]; | |
280 | ||
281 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 282 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 283 | |
a4672219 TS |
284 | /* True if -mips16 was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_mips16; | |
287 | ||
3994f87e TS |
288 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
289 | || mips_opts.isa == ISA_MIPS32R2 \ | |
290 | || mips_opts.isa == ISA_MIPS64 \ | |
291 | || mips_opts.isa == ISA_MIPS64R2) | |
292 | ||
1f25f5d3 CD |
293 | /* True if -mips3d was passed or implied by arguments passed on the |
294 | command line (e.g., by -march). */ | |
295 | static int file_ase_mips3d; | |
296 | ||
deec1734 CD |
297 | /* True if -mdmx was passed or implied by arguments passed on the |
298 | command line (e.g., by -march). */ | |
299 | static int file_ase_mdmx; | |
300 | ||
e16bfa71 TS |
301 | /* True if -msmartmips was passed or implied by arguments passed on the |
302 | command line (e.g., by -march). */ | |
303 | static int file_ase_smartmips; | |
304 | ||
ad3fea08 TS |
305 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
306 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 307 | |
74cd071d CF |
308 | /* True if -mdsp was passed or implied by arguments passed on the |
309 | command line (e.g., by -march). */ | |
310 | static int file_ase_dsp; | |
311 | ||
ad3fea08 TS |
312 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
313 | || mips_opts.isa == ISA_MIPS64R2) | |
314 | ||
65263ce3 TS |
315 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
316 | ||
8b082fb1 TS |
317 | /* True if -mdspr2 was passed or implied by arguments passed on the |
318 | command line (e.g., by -march). */ | |
319 | static int file_ase_dspr2; | |
320 | ||
321 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
322 | || mips_opts.isa == ISA_MIPS64R2) | |
323 | ||
ef2e4d86 CF |
324 | /* True if -mmt was passed or implied by arguments passed on the |
325 | command line (e.g., by -march). */ | |
326 | static int file_ase_mt; | |
327 | ||
ad3fea08 TS |
328 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
329 | || mips_opts.isa == ISA_MIPS64R2) | |
330 | ||
ec68c924 | 331 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 332 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 333 | static const char *mips_arch_string; |
ec68c924 EC |
334 | |
335 | /* The argument of the -mtune= flag. The architecture for which we | |
336 | are optimizing. */ | |
337 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 338 | static const char *mips_tune_string; |
ec68c924 | 339 | |
316f5878 | 340 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
341 | static int mips_32bitmode = 0; |
342 | ||
316f5878 RS |
343 | /* True if the given ABI requires 32-bit registers. */ |
344 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
345 | ||
346 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
347 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
348 | ((ABI) == N32_ABI \ | |
349 | || (ABI) == N64_ABI \ | |
316f5878 RS |
350 | || (ABI) == O64_ABI) |
351 | ||
ad3fea08 | 352 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
353 | #define ISA_HAS_64BIT_REGS(ISA) \ |
354 | ((ISA) == ISA_MIPS3 \ | |
355 | || (ISA) == ISA_MIPS4 \ | |
356 | || (ISA) == ISA_MIPS5 \ | |
357 | || (ISA) == ISA_MIPS64 \ | |
358 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 359 | |
ad3fea08 TS |
360 | /* Return true if ISA supports 64 bit wide float registers. */ |
361 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS32R2 \ | |
366 | || (ISA) == ISA_MIPS64 \ | |
367 | || (ISA) == ISA_MIPS64R2) | |
368 | ||
af7ee8bf CD |
369 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
370 | instructions. */ | |
707bfff6 TS |
371 | #define ISA_HAS_DROR(ISA) \ |
372 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
373 | |
374 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
375 | instructions. */ | |
707bfff6 TS |
376 | #define ISA_HAS_ROR(ISA) \ |
377 | ((ISA) == ISA_MIPS32R2 \ | |
378 | || (ISA) == ISA_MIPS64R2 \ | |
379 | || mips_opts.ase_smartmips) | |
380 | ||
7455baf8 TS |
381 | /* Return true if ISA supports single-precision floats in odd registers. */ |
382 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
383 | ((ISA) == ISA_MIPS32 \ | |
384 | || (ISA) == ISA_MIPS32R2 \ | |
385 | || (ISA) == ISA_MIPS64 \ | |
386 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 387 | |
ad3fea08 TS |
388 | /* Return true if ISA supports move to/from high part of a 64-bit |
389 | floating-point register. */ | |
390 | #define ISA_HAS_MXHC1(ISA) \ | |
391 | ((ISA) == ISA_MIPS32R2 \ | |
392 | || (ISA) == ISA_MIPS64R2) | |
393 | ||
e013f690 | 394 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 395 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 396 | |
e013f690 | 397 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 398 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 399 | |
ad3fea08 TS |
400 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
401 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 402 | |
316f5878 | 403 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 404 | |
316f5878 | 405 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 406 | |
3b91255e RS |
407 | /* True if relocations are stored in-place. */ |
408 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
409 | ||
aed1a261 RS |
410 | /* The ABI-derived address size. */ |
411 | #define HAVE_64BIT_ADDRESSES \ | |
412 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
413 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 414 | |
aed1a261 RS |
415 | /* The size of symbolic constants (i.e., expressions of the form |
416 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
417 | #define HAVE_32BIT_SYMBOLS \ | |
418 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
419 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 420 | |
b7c7d6c1 TS |
421 | /* Addresses are loaded in different ways, depending on the address size |
422 | in use. The n32 ABI Documentation also mandates the use of additions | |
423 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 424 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 425 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
426 | |
427 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 428 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
429 | |
430 | #define ADDRESS_LOAD_INSN \ | |
431 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
432 | ||
433 | #define ADDRESS_STORE_INSN \ | |
434 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
435 | ||
a4672219 | 436 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
437 | #define CPU_HAS_MIPS16(cpu) \ |
438 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
439 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 440 | |
60b63b72 RS |
441 | /* True if CPU has a dror instruction. */ |
442 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
443 | ||
444 | /* True if CPU has a ror instruction. */ | |
445 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
446 | ||
dd3cbb7e NC |
447 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
448 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
449 | ||
c8978940 CD |
450 | /* True if mflo and mfhi can be immediately followed by instructions |
451 | which write to the HI and LO registers. | |
452 | ||
453 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
454 | (at least) two instructions between the reads of HI/LO and | |
455 | instructions which write them, and later ISAs do not. Contradicting | |
456 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
457 | the UM for the NEC Vr5000) document needing the instructions between | |
458 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
459 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
460 | earlier-ISA CPUs for which CPU documentation declares that the | |
461 | instructions are really interlocked. */ | |
462 | #define hilo_interlocks \ | |
463 | (mips_opts.isa == ISA_MIPS32 \ | |
464 | || mips_opts.isa == ISA_MIPS32R2 \ | |
465 | || mips_opts.isa == ISA_MIPS64 \ | |
466 | || mips_opts.isa == ISA_MIPS64R2 \ | |
467 | || mips_opts.arch == CPU_R4010 \ | |
468 | || mips_opts.arch == CPU_R10000 \ | |
469 | || mips_opts.arch == CPU_R12000 \ | |
470 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
471 | || mips_opts.arch == CPU_VR5500 \ |
472 | ) | |
252b5132 RH |
473 | |
474 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
475 | from the GPRs after they are loaded from memory, and thus does not |
476 | require nops to be inserted. This applies to instructions marked | |
477 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
478 | level I. */ | |
252b5132 | 479 | #define gpr_interlocks \ |
e7af610e | 480 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 481 | || mips_opts.arch == CPU_R3900) |
252b5132 | 482 | |
81912461 ILT |
483 | /* Whether the processor uses hardware interlocks to avoid delays |
484 | required by coprocessor instructions, and thus does not require | |
485 | nops to be inserted. This applies to instructions marked | |
486 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
487 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
488 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
489 | levels I, II, and III. */ | |
bdaaa2e1 | 490 | /* Itbl support may require additional care here. */ |
81912461 ILT |
491 | #define cop_interlocks \ |
492 | ((mips_opts.isa != ISA_MIPS1 \ | |
493 | && mips_opts.isa != ISA_MIPS2 \ | |
494 | && mips_opts.isa != ISA_MIPS3) \ | |
495 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
496 | ) |
497 | ||
498 | /* Whether the processor uses hardware interlocks to protect reads | |
499 | from coprocessor registers after they are loaded from memory, and | |
500 | thus does not require nops to be inserted. This applies to | |
501 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
502 | requires at MIPS ISA level I. */ | |
503 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 504 | |
6b76fefe CM |
505 | /* Is this a mfhi or mflo instruction? */ |
506 | #define MF_HILO_INSN(PINFO) \ | |
507 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
508 | ||
252b5132 RH |
509 | /* MIPS PIC level. */ |
510 | ||
a161fe53 | 511 | enum mips_pic_level mips_pic; |
252b5132 | 512 | |
c9914766 | 513 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 514 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 515 | static int mips_big_got = 0; |
252b5132 RH |
516 | |
517 | /* 1 if trap instructions should used for overflow rather than break | |
518 | instructions. */ | |
c9914766 | 519 | static int mips_trap = 0; |
252b5132 | 520 | |
119d663a | 521 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 522 | by assembling two single width halves into two single width floating |
119d663a NC |
523 | point registers which just happen to alias the double width destination |
524 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 525 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
526 | automatically at assemble time. */ |
527 | static int mips_disable_float_construction; | |
528 | ||
252b5132 RH |
529 | /* Non-zero if any .set noreorder directives were used. */ |
530 | ||
531 | static int mips_any_noreorder; | |
532 | ||
6b76fefe CM |
533 | /* Non-zero if nops should be inserted when the register referenced in |
534 | an mfhi/mflo instruction is read in the next two instructions. */ | |
535 | static int mips_7000_hilo_fix; | |
536 | ||
02ffd3e4 | 537 | /* The size of objects in the small data section. */ |
156c2f8b | 538 | static unsigned int g_switch_value = 8; |
252b5132 RH |
539 | /* Whether the -G option was used. */ |
540 | static int g_switch_seen = 0; | |
541 | ||
542 | #define N_RMASK 0xc4 | |
543 | #define N_VFP 0xd4 | |
544 | ||
545 | /* If we can determine in advance that GP optimization won't be | |
546 | possible, we can skip the relaxation stuff that tries to produce | |
547 | GP-relative references. This makes delay slot optimization work | |
548 | better. | |
549 | ||
550 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
551 | gcc output. It needs to guess right for gcc, otherwise gcc |
552 | will put what it thinks is a GP-relative instruction in a branch | |
553 | delay slot. | |
252b5132 RH |
554 | |
555 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
556 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 557 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
558 | |
559 | /* handle of the OPCODE hash table */ | |
560 | static struct hash_control *op_hash = NULL; | |
561 | ||
562 | /* The opcode hash table we use for the mips16. */ | |
563 | static struct hash_control *mips16_op_hash = NULL; | |
564 | ||
565 | /* This array holds the chars that always start a comment. If the | |
566 | pre-processor is disabled, these aren't very useful */ | |
567 | const char comment_chars[] = "#"; | |
568 | ||
569 | /* This array holds the chars that only start a comment at the beginning of | |
570 | a line. If the line seems to have the form '# 123 filename' | |
571 | .line and .file directives will appear in the pre-processed output */ | |
572 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
573 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 574 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
575 | /* Also note that C style comments are always supported. */ |
576 | const char line_comment_chars[] = "#"; | |
577 | ||
bdaaa2e1 | 578 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 579 | const char line_separator_chars[] = ";"; |
252b5132 RH |
580 | |
581 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
582 | const char EXP_CHARS[] = "eE"; | |
583 | ||
584 | /* Chars that mean this number is a floating point constant */ | |
585 | /* As in 0f12.456 */ | |
586 | /* or 0d1.2345e12 */ | |
587 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
588 | ||
589 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
590 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
591 | but nothing is ideal around here. | |
592 | */ | |
593 | ||
594 | static char *insn_error; | |
595 | ||
596 | static int auto_align = 1; | |
597 | ||
598 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
599 | offset in the stack frame from which to restore the $gp register. | |
600 | This is set by the .cprestore pseudo-op, and saved in this | |
601 | variable. */ | |
602 | static offsetT mips_cprestore_offset = -1; | |
603 | ||
67c1ffbe | 604 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 605 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 606 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
607 | static offsetT mips_cpreturn_offset = -1; |
608 | static int mips_cpreturn_register = -1; | |
609 | static int mips_gp_register = GP; | |
def2e0dd | 610 | static int mips_gprel_offset = 0; |
6478892d | 611 | |
7a621144 DJ |
612 | /* Whether mips_cprestore_offset has been set in the current function |
613 | (or whether it has already been warned about, if not). */ | |
614 | static int mips_cprestore_valid = 0; | |
615 | ||
252b5132 RH |
616 | /* This is the register which holds the stack frame, as set by the |
617 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
618 | static int mips_frame_reg = SP; | |
619 | ||
7a621144 DJ |
620 | /* Whether mips_frame_reg has been set in the current function |
621 | (or whether it has already been warned about, if not). */ | |
622 | static int mips_frame_reg_valid = 0; | |
623 | ||
252b5132 RH |
624 | /* To output NOP instructions correctly, we need to keep information |
625 | about the previous two instructions. */ | |
626 | ||
627 | /* Whether we are optimizing. The default value of 2 means to remove | |
628 | unneeded NOPs and swap branch instructions when possible. A value | |
629 | of 1 means to not swap branches. A value of 0 means to always | |
630 | insert NOPs. */ | |
631 | static int mips_optimize = 2; | |
632 | ||
633 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
634 | equivalent to seeing no -g option at all. */ | |
635 | static int mips_debug = 0; | |
636 | ||
7d8e00cf RS |
637 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
638 | #define MAX_VR4130_NOPS 4 | |
639 | ||
640 | /* The maximum number of NOPs needed to fill delay slots. */ | |
641 | #define MAX_DELAY_NOPS 2 | |
642 | ||
643 | /* The maximum number of NOPs needed for any purpose. */ | |
644 | #define MAX_NOPS 4 | |
71400594 RS |
645 | |
646 | /* A list of previous instructions, with index 0 being the most recent. | |
647 | We need to look back MAX_NOPS instructions when filling delay slots | |
648 | or working around processor errata. We need to look back one | |
649 | instruction further if we're thinking about using history[0] to | |
650 | fill a branch delay slot. */ | |
651 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 652 | |
1e915849 RS |
653 | /* Nop instructions used by emit_nop. */ |
654 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
655 | ||
656 | /* The appropriate nop for the current mode. */ | |
657 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 658 | |
252b5132 RH |
659 | /* If this is set, it points to a frag holding nop instructions which |
660 | were inserted before the start of a noreorder section. If those | |
661 | nops turn out to be unnecessary, the size of the frag can be | |
662 | decreased. */ | |
663 | static fragS *prev_nop_frag; | |
664 | ||
665 | /* The number of nop instructions we created in prev_nop_frag. */ | |
666 | static int prev_nop_frag_holds; | |
667 | ||
668 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 669 | prev_nop_frag. */ |
252b5132 RH |
670 | static int prev_nop_frag_required; |
671 | ||
672 | /* The number of instructions we've seen since prev_nop_frag. */ | |
673 | static int prev_nop_frag_since; | |
674 | ||
675 | /* For ECOFF and ELF, relocations against symbols are done in two | |
676 | parts, with a HI relocation and a LO relocation. Each relocation | |
677 | has only 16 bits of space to store an addend. This means that in | |
678 | order for the linker to handle carries correctly, it must be able | |
679 | to locate both the HI and the LO relocation. This means that the | |
680 | relocations must appear in order in the relocation table. | |
681 | ||
682 | In order to implement this, we keep track of each unmatched HI | |
683 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 684 | corresponding LO relocation. */ |
252b5132 | 685 | |
e972090a NC |
686 | struct mips_hi_fixup |
687 | { | |
252b5132 RH |
688 | /* Next HI fixup. */ |
689 | struct mips_hi_fixup *next; | |
690 | /* This fixup. */ | |
691 | fixS *fixp; | |
692 | /* The section this fixup is in. */ | |
693 | segT seg; | |
694 | }; | |
695 | ||
696 | /* The list of unmatched HI relocs. */ | |
697 | ||
698 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
699 | ||
64bdfcaf RS |
700 | /* The frag containing the last explicit relocation operator. |
701 | Null if explicit relocations have not been used. */ | |
702 | ||
703 | static fragS *prev_reloc_op_frag; | |
704 | ||
252b5132 RH |
705 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
706 | ||
707 | #define X ILLEGAL_REG | |
e972090a NC |
708 | static const int mips32_to_16_reg_map[] = |
709 | { | |
252b5132 RH |
710 | X, X, 2, 3, 4, 5, 6, 7, |
711 | X, X, X, X, X, X, X, X, | |
712 | 0, 1, X, X, X, X, X, X, | |
713 | X, X, X, X, X, X, X, X | |
714 | }; | |
715 | #undef X | |
716 | ||
717 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
718 | ||
e972090a NC |
719 | static const unsigned int mips16_to_32_reg_map[] = |
720 | { | |
252b5132 RH |
721 | 16, 17, 2, 3, 4, 5, 6, 7 |
722 | }; | |
60b63b72 | 723 | |
71400594 RS |
724 | /* Classifies the kind of instructions we're interested in when |
725 | implementing -mfix-vr4120. */ | |
726 | enum fix_vr4120_class { | |
727 | FIX_VR4120_MACC, | |
728 | FIX_VR4120_DMACC, | |
729 | FIX_VR4120_MULT, | |
730 | FIX_VR4120_DMULT, | |
731 | FIX_VR4120_DIV, | |
732 | FIX_VR4120_MTHILO, | |
733 | NUM_FIX_VR4120_CLASSES | |
734 | }; | |
735 | ||
736 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
737 | there must be at least one other instruction between an instruction | |
738 | of type X and an instruction of type Y. */ | |
739 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
740 | ||
741 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 742 | static int mips_fix_vr4120; |
4a6a3df4 | 743 | |
7d8e00cf RS |
744 | /* ...likewise -mfix-vr4130. */ |
745 | static int mips_fix_vr4130; | |
746 | ||
4a6a3df4 AO |
747 | /* We don't relax branches by default, since this causes us to expand |
748 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
749 | fail to compute the offset before expanding the macro to the most | |
750 | efficient expansion. */ | |
751 | ||
752 | static int mips_relax_branch; | |
252b5132 | 753 | \f |
4d7206a2 RS |
754 | /* The expansion of many macros depends on the type of symbol that |
755 | they refer to. For example, when generating position-dependent code, | |
756 | a macro that refers to a symbol may have two different expansions, | |
757 | one which uses GP-relative addresses and one which uses absolute | |
758 | addresses. When generating SVR4-style PIC, a macro may have | |
759 | different expansions for local and global symbols. | |
760 | ||
761 | We handle these situations by generating both sequences and putting | |
762 | them in variant frags. In position-dependent code, the first sequence | |
763 | will be the GP-relative one and the second sequence will be the | |
764 | absolute one. In SVR4 PIC, the first sequence will be for global | |
765 | symbols and the second will be for local symbols. | |
766 | ||
584892a6 RS |
767 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
768 | SECOND are the lengths of the two sequences in bytes. These fields | |
769 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
770 | the subtype has the following flags: | |
4d7206a2 | 771 | |
584892a6 RS |
772 | RELAX_USE_SECOND |
773 | Set if it has been decided that we should use the second | |
774 | sequence instead of the first. | |
775 | ||
776 | RELAX_SECOND_LONGER | |
777 | Set in the first variant frag if the macro's second implementation | |
778 | is longer than its first. This refers to the macro as a whole, | |
779 | not an individual relaxation. | |
780 | ||
781 | RELAX_NOMACRO | |
782 | Set in the first variant frag if the macro appeared in a .set nomacro | |
783 | block and if one alternative requires a warning but the other does not. | |
784 | ||
785 | RELAX_DELAY_SLOT | |
786 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
787 | delay slot. | |
4d7206a2 RS |
788 | |
789 | The frag's "opcode" points to the first fixup for relaxable code. | |
790 | ||
791 | Relaxable macros are generated using a sequence such as: | |
792 | ||
793 | relax_start (SYMBOL); | |
794 | ... generate first expansion ... | |
795 | relax_switch (); | |
796 | ... generate second expansion ... | |
797 | relax_end (); | |
798 | ||
799 | The code and fixups for the unwanted alternative are discarded | |
800 | by md_convert_frag. */ | |
584892a6 | 801 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 802 | |
584892a6 RS |
803 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
804 | #define RELAX_SECOND(X) ((X) & 0xff) | |
805 | #define RELAX_USE_SECOND 0x10000 | |
806 | #define RELAX_SECOND_LONGER 0x20000 | |
807 | #define RELAX_NOMACRO 0x40000 | |
808 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 809 | |
4a6a3df4 AO |
810 | /* Branch without likely bit. If label is out of range, we turn: |
811 | ||
812 | beq reg1, reg2, label | |
813 | delay slot | |
814 | ||
815 | into | |
816 | ||
817 | bne reg1, reg2, 0f | |
818 | nop | |
819 | j label | |
820 | 0: delay slot | |
821 | ||
822 | with the following opcode replacements: | |
823 | ||
824 | beq <-> bne | |
825 | blez <-> bgtz | |
826 | bltz <-> bgez | |
827 | bc1f <-> bc1t | |
828 | ||
829 | bltzal <-> bgezal (with jal label instead of j label) | |
830 | ||
831 | Even though keeping the delay slot instruction in the delay slot of | |
832 | the branch would be more efficient, it would be very tricky to do | |
833 | correctly, because we'd have to introduce a variable frag *after* | |
834 | the delay slot instruction, and expand that instead. Let's do it | |
835 | the easy way for now, even if the branch-not-taken case now costs | |
836 | one additional instruction. Out-of-range branches are not supposed | |
837 | to be common, anyway. | |
838 | ||
839 | Branch likely. If label is out of range, we turn: | |
840 | ||
841 | beql reg1, reg2, label | |
842 | delay slot (annulled if branch not taken) | |
843 | ||
844 | into | |
845 | ||
846 | beql reg1, reg2, 1f | |
847 | nop | |
848 | beql $0, $0, 2f | |
849 | nop | |
850 | 1: j[al] label | |
851 | delay slot (executed only if branch taken) | |
852 | 2: | |
853 | ||
854 | It would be possible to generate a shorter sequence by losing the | |
855 | likely bit, generating something like: | |
b34976b6 | 856 | |
4a6a3df4 AO |
857 | bne reg1, reg2, 0f |
858 | nop | |
859 | j[al] label | |
860 | delay slot (executed only if branch taken) | |
861 | 0: | |
862 | ||
863 | beql -> bne | |
864 | bnel -> beq | |
865 | blezl -> bgtz | |
866 | bgtzl -> blez | |
867 | bltzl -> bgez | |
868 | bgezl -> bltz | |
869 | bc1fl -> bc1t | |
870 | bc1tl -> bc1f | |
871 | ||
872 | bltzall -> bgezal (with jal label instead of j label) | |
873 | bgezall -> bltzal (ditto) | |
874 | ||
875 | ||
876 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 877 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
878 | ((relax_substateT) \ |
879 | (0xc0000000 \ | |
880 | | ((toofar) ? 1 : 0) \ | |
881 | | ((link) ? 2 : 0) \ | |
882 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 883 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 884 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
885 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
886 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
887 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 888 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 889 | |
252b5132 RH |
890 | /* For mips16 code, we use an entirely different form of relaxation. |
891 | mips16 supports two versions of most instructions which take | |
892 | immediate values: a small one which takes some small value, and a | |
893 | larger one which takes a 16 bit value. Since branches also follow | |
894 | this pattern, relaxing these values is required. | |
895 | ||
896 | We can assemble both mips16 and normal MIPS code in a single | |
897 | object. Therefore, we need to support this type of relaxation at | |
898 | the same time that we support the relaxation described above. We | |
899 | use the high bit of the subtype field to distinguish these cases. | |
900 | ||
901 | The information we store for this type of relaxation is the | |
902 | argument code found in the opcode file for this relocation, whether | |
903 | the user explicitly requested a small or extended form, and whether | |
904 | the relocation is in a jump or jal delay slot. That tells us the | |
905 | size of the value, and how it should be stored. We also store | |
906 | whether the fragment is considered to be extended or not. We also | |
907 | store whether this is known to be a branch to a different section, | |
908 | whether we have tried to relax this frag yet, and whether we have | |
909 | ever extended a PC relative fragment because of a shift count. */ | |
910 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
911 | (0x80000000 \ | |
912 | | ((type) & 0xff) \ | |
913 | | ((small) ? 0x100 : 0) \ | |
914 | | ((ext) ? 0x200 : 0) \ | |
915 | | ((dslot) ? 0x400 : 0) \ | |
916 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 917 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
918 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
919 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
920 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
921 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
922 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
923 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
924 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
925 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
926 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
927 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
928 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
929 | |
930 | /* Is the given value a sign-extended 32-bit value? */ | |
931 | #define IS_SEXT_32BIT_NUM(x) \ | |
932 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
933 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
934 | ||
935 | /* Is the given value a sign-extended 16-bit value? */ | |
936 | #define IS_SEXT_16BIT_NUM(x) \ | |
937 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
938 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
939 | ||
2051e8c4 MR |
940 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
941 | #define IS_ZEXT_32BIT_NUM(x) \ | |
942 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
943 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
944 | ||
bf12938e RS |
945 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
946 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
947 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
948 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
949 | | (((VALUE) & (MASK)) << (SHIFT))) | |
950 | ||
951 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
952 | SHIFT places. */ | |
953 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
954 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
955 | ||
956 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
957 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
958 | ||
959 | include/opcode/mips.h specifies operand fields using the macros | |
960 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
961 | with "MIPS16OP" instead of "OP". */ | |
962 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
963 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
964 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
965 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
966 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
967 | ||
968 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
969 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
970 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
971 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
972 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
973 | MIPS16OP_MASK_##FIELD, \ | |
974 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
975 | \f |
976 | /* Global variables used when generating relaxable macros. See the | |
977 | comment above RELAX_ENCODE for more details about how relaxation | |
978 | is used. */ | |
979 | static struct { | |
980 | /* 0 if we're not emitting a relaxable macro. | |
981 | 1 if we're emitting the first of the two relaxation alternatives. | |
982 | 2 if we're emitting the second alternative. */ | |
983 | int sequence; | |
984 | ||
985 | /* The first relaxable fixup in the current frag. (In other words, | |
986 | the first fixup that refers to relaxable code.) */ | |
987 | fixS *first_fixup; | |
988 | ||
989 | /* sizes[0] says how many bytes of the first alternative are stored in | |
990 | the current frag. Likewise sizes[1] for the second alternative. */ | |
991 | unsigned int sizes[2]; | |
992 | ||
993 | /* The symbol on which the choice of sequence depends. */ | |
994 | symbolS *symbol; | |
995 | } mips_relax; | |
252b5132 | 996 | \f |
584892a6 RS |
997 | /* Global variables used to decide whether a macro needs a warning. */ |
998 | static struct { | |
999 | /* True if the macro is in a branch delay slot. */ | |
1000 | bfd_boolean delay_slot_p; | |
1001 | ||
1002 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1003 | in bytes and sizes[1] is the length of the second alternative. | |
1004 | For non-relaxable macros, both elements give the length of the | |
1005 | macro in bytes. */ | |
1006 | unsigned int sizes[2]; | |
1007 | ||
1008 | /* The first variant frag for this macro. */ | |
1009 | fragS *first_frag; | |
1010 | } mips_macro_warning; | |
1011 | \f | |
252b5132 RH |
1012 | /* Prototypes for static functions. */ |
1013 | ||
17a2f251 | 1014 | #define internalError() \ |
252b5132 | 1015 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1016 | |
1017 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1018 | ||
b34976b6 | 1019 | static void append_insn |
4d7206a2 | 1020 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 1021 | static void mips_no_prev_insn (void); |
b34976b6 | 1022 | static void mips16_macro_build |
67c0d1eb RS |
1023 | (expressionS *, const char *, const char *, va_list); |
1024 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
1025 | static void macro_start (void); |
1026 | static void macro_end (void); | |
17a2f251 TS |
1027 | static void macro (struct mips_cl_insn * ip); |
1028 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1029 | #ifdef LOSING_COMPILER |
17a2f251 | 1030 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1031 | #endif |
17a2f251 TS |
1032 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1033 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1034 | static void mips16_immed |
17a2f251 TS |
1035 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1036 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1037 | static size_t my_getSmallExpression |
17a2f251 TS |
1038 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1039 | static void my_getExpression (expressionS *, char *); | |
1040 | static void s_align (int); | |
1041 | static void s_change_sec (int); | |
1042 | static void s_change_section (int); | |
1043 | static void s_cons (int); | |
1044 | static void s_float_cons (int); | |
1045 | static void s_mips_globl (int); | |
1046 | static void s_option (int); | |
1047 | static void s_mipsset (int); | |
1048 | static void s_abicalls (int); | |
1049 | static void s_cpload (int); | |
1050 | static void s_cpsetup (int); | |
1051 | static void s_cplocal (int); | |
1052 | static void s_cprestore (int); | |
1053 | static void s_cpreturn (int); | |
741d6ea8 JM |
1054 | static void s_dtprelword (int); |
1055 | static void s_dtpreldword (int); | |
17a2f251 TS |
1056 | static void s_gpvalue (int); |
1057 | static void s_gpword (int); | |
1058 | static void s_gpdword (int); | |
1059 | static void s_cpadd (int); | |
1060 | static void s_insn (int); | |
1061 | static void md_obj_begin (void); | |
1062 | static void md_obj_end (void); | |
1063 | static void s_mips_ent (int); | |
1064 | static void s_mips_end (int); | |
1065 | static void s_mips_frame (int); | |
1066 | static void s_mips_mask (int reg_type); | |
1067 | static void s_mips_stab (int); | |
1068 | static void s_mips_weakext (int); | |
1069 | static void s_mips_file (int); | |
1070 | static void s_mips_loc (int); | |
1071 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1072 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1073 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1074 | |
1075 | /* Table and functions used to map between CPU/ISA names, and | |
1076 | ISA levels, and CPU numbers. */ | |
1077 | ||
e972090a NC |
1078 | struct mips_cpu_info |
1079 | { | |
e7af610e | 1080 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1081 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1082 | int isa; /* ISA level. */ |
1083 | int cpu; /* CPU number (default CPU if ISA). */ | |
1084 | }; | |
1085 | ||
ad3fea08 TS |
1086 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1087 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1088 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1089 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1090 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1091 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1092 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1093 | |
17a2f251 TS |
1094 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1095 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1096 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1097 | \f |
1098 | /* Pseudo-op table. | |
1099 | ||
1100 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1101 | should be defined here, but are currently unsupported: .alias, | |
1102 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1103 | ||
1104 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1105 | specific to the type of debugging information being generated, and | |
1106 | should be defined by the object format: .aent, .begin, .bend, | |
1107 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1108 | .vreg. | |
1109 | ||
1110 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1111 | not MIPS CPU specific, but are also not specific to the object file | |
1112 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1113 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1114 | |
e972090a NC |
1115 | static const pseudo_typeS mips_pseudo_table[] = |
1116 | { | |
beae10d5 | 1117 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1118 | {"option", s_option, 0}, |
1119 | {"set", s_mipsset, 0}, | |
1120 | {"rdata", s_change_sec, 'r'}, | |
1121 | {"sdata", s_change_sec, 's'}, | |
1122 | {"livereg", s_ignore, 0}, | |
1123 | {"abicalls", s_abicalls, 0}, | |
1124 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1125 | {"cpsetup", s_cpsetup, 0}, |
1126 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1127 | {"cprestore", s_cprestore, 0}, |
6478892d | 1128 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1129 | {"dtprelword", s_dtprelword, 0}, |
1130 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1131 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1132 | {"gpword", s_gpword, 0}, |
10181a0d | 1133 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1134 | {"cpadd", s_cpadd, 0}, |
1135 | {"insn", s_insn, 0}, | |
1136 | ||
beae10d5 | 1137 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1138 | chips. */ |
38a57ae7 | 1139 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1140 | {"bss", s_change_sec, 'b'}, |
1141 | {"err", s_err, 0}, | |
1142 | {"half", s_cons, 1}, | |
1143 | {"dword", s_cons, 3}, | |
1144 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1145 | {"origin", s_org, 0}, |
1146 | {"repeat", s_rept, 0}, | |
252b5132 | 1147 | |
beae10d5 | 1148 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1149 | here for one reason or another. */ |
1150 | {"align", s_align, 0}, | |
1151 | {"byte", s_cons, 0}, | |
1152 | {"data", s_change_sec, 'd'}, | |
1153 | {"double", s_float_cons, 'd'}, | |
1154 | {"float", s_float_cons, 'f'}, | |
1155 | {"globl", s_mips_globl, 0}, | |
1156 | {"global", s_mips_globl, 0}, | |
1157 | {"hword", s_cons, 1}, | |
1158 | {"int", s_cons, 2}, | |
1159 | {"long", s_cons, 2}, | |
1160 | {"octa", s_cons, 4}, | |
1161 | {"quad", s_cons, 3}, | |
cca86cc8 | 1162 | {"section", s_change_section, 0}, |
252b5132 RH |
1163 | {"short", s_cons, 1}, |
1164 | {"single", s_float_cons, 'f'}, | |
1165 | {"stabn", s_mips_stab, 'n'}, | |
1166 | {"text", s_change_sec, 't'}, | |
1167 | {"word", s_cons, 2}, | |
add56521 | 1168 | |
add56521 | 1169 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1170 | |
43841e91 | 1171 | { NULL, NULL, 0 }, |
252b5132 RH |
1172 | }; |
1173 | ||
e972090a NC |
1174 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1175 | { | |
beae10d5 KH |
1176 | /* These pseudo-ops should be defined by the object file format. |
1177 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1178 | {"aent", s_mips_ent, 1}, |
1179 | {"bgnb", s_ignore, 0}, | |
1180 | {"end", s_mips_end, 0}, | |
1181 | {"endb", s_ignore, 0}, | |
1182 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1183 | {"file", s_mips_file, 0}, |
252b5132 RH |
1184 | {"fmask", s_mips_mask, 'F'}, |
1185 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1186 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1187 | {"mask", s_mips_mask, 'R'}, |
1188 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1189 | { NULL, NULL, 0 }, |
252b5132 RH |
1190 | }; |
1191 | ||
17a2f251 | 1192 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1193 | |
1194 | void | |
17a2f251 | 1195 | mips_pop_insert (void) |
252b5132 RH |
1196 | { |
1197 | pop_insert (mips_pseudo_table); | |
1198 | if (! ECOFF_DEBUGGING) | |
1199 | pop_insert (mips_nonecoff_pseudo_table); | |
1200 | } | |
1201 | \f | |
1202 | /* Symbols labelling the current insn. */ | |
1203 | ||
e972090a NC |
1204 | struct insn_label_list |
1205 | { | |
252b5132 RH |
1206 | struct insn_label_list *next; |
1207 | symbolS *label; | |
1208 | }; | |
1209 | ||
252b5132 | 1210 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1211 | #define label_list tc_segment_info_data.labels |
252b5132 | 1212 | |
17a2f251 | 1213 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1214 | |
1215 | static inline void | |
17a2f251 | 1216 | mips_clear_insn_labels (void) |
252b5132 RH |
1217 | { |
1218 | register struct insn_label_list **pl; | |
a8dbcb85 | 1219 | segment_info_type *si; |
252b5132 | 1220 | |
a8dbcb85 TS |
1221 | if (now_seg) |
1222 | { | |
1223 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1224 | ; | |
1225 | ||
1226 | si = seg_info (now_seg); | |
1227 | *pl = si->label_list; | |
1228 | si->label_list = NULL; | |
1229 | } | |
252b5132 | 1230 | } |
a8dbcb85 | 1231 | |
252b5132 RH |
1232 | \f |
1233 | static char *expr_end; | |
1234 | ||
1235 | /* Expressions which appear in instructions. These are set by | |
1236 | mips_ip. */ | |
1237 | ||
1238 | static expressionS imm_expr; | |
5f74bc13 | 1239 | static expressionS imm2_expr; |
252b5132 RH |
1240 | static expressionS offset_expr; |
1241 | ||
1242 | /* Relocs associated with imm_expr and offset_expr. */ | |
1243 | ||
f6688943 TS |
1244 | static bfd_reloc_code_real_type imm_reloc[3] |
1245 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1246 | static bfd_reloc_code_real_type offset_reloc[3] | |
1247 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1248 | |
252b5132 RH |
1249 | /* These are set by mips16_ip if an explicit extension is used. */ |
1250 | ||
b34976b6 | 1251 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1252 | |
7ed4a06a | 1253 | #ifdef OBJ_ELF |
ecb4347a DJ |
1254 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1255 | ECOFF debugging. */ | |
252b5132 RH |
1256 | |
1257 | static segT pdr_seg; | |
7ed4a06a | 1258 | #endif |
252b5132 | 1259 | |
e013f690 TS |
1260 | /* The default target format to use. */ |
1261 | ||
1262 | const char * | |
17a2f251 | 1263 | mips_target_format (void) |
e013f690 TS |
1264 | { |
1265 | switch (OUTPUT_FLAVOR) | |
1266 | { | |
e013f690 TS |
1267 | case bfd_target_ecoff_flavour: |
1268 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1269 | case bfd_target_coff_flavour: | |
1270 | return "pe-mips"; | |
1271 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1272 | #ifdef TE_VXWORKS |
1273 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1274 | return (target_big_endian | |
1275 | ? "elf32-bigmips-vxworks" | |
1276 | : "elf32-littlemips-vxworks"); | |
1277 | #endif | |
e013f690 | 1278 | #ifdef TE_TMIPS |
cfe86eaa | 1279 | /* This is traditional mips. */ |
e013f690 | 1280 | return (target_big_endian |
cfe86eaa TS |
1281 | ? (HAVE_64BIT_OBJECTS |
1282 | ? "elf64-tradbigmips" | |
1283 | : (HAVE_NEWABI | |
1284 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1285 | : (HAVE_64BIT_OBJECTS | |
1286 | ? "elf64-tradlittlemips" | |
1287 | : (HAVE_NEWABI | |
1288 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1289 | #else |
1290 | return (target_big_endian | |
cfe86eaa TS |
1291 | ? (HAVE_64BIT_OBJECTS |
1292 | ? "elf64-bigmips" | |
1293 | : (HAVE_NEWABI | |
1294 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1295 | : (HAVE_64BIT_OBJECTS | |
1296 | ? "elf64-littlemips" | |
1297 | : (HAVE_NEWABI | |
1298 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1299 | #endif |
1300 | default: | |
1301 | abort (); | |
1302 | return NULL; | |
1303 | } | |
1304 | } | |
1305 | ||
1e915849 RS |
1306 | /* Return the length of instruction INSN. */ |
1307 | ||
1308 | static inline unsigned int | |
1309 | insn_length (const struct mips_cl_insn *insn) | |
1310 | { | |
1311 | if (!mips_opts.mips16) | |
1312 | return 4; | |
1313 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1314 | } | |
1315 | ||
1316 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1317 | ||
1318 | static void | |
1319 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1320 | { | |
1321 | size_t i; | |
1322 | ||
1323 | insn->insn_mo = mo; | |
1324 | insn->use_extend = FALSE; | |
1325 | insn->extend = 0; | |
1326 | insn->insn_opcode = mo->match; | |
1327 | insn->frag = NULL; | |
1328 | insn->where = 0; | |
1329 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1330 | insn->fixp[i] = NULL; | |
1331 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1332 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1333 | insn->mips16_absolute_jump_p = 0; | |
1334 | } | |
1335 | ||
742a56fe RS |
1336 | /* Record the current MIPS16 mode in now_seg. */ |
1337 | ||
1338 | static void | |
1339 | mips_record_mips16_mode (void) | |
1340 | { | |
1341 | segment_info_type *si; | |
1342 | ||
1343 | si = seg_info (now_seg); | |
1344 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1345 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1346 | } | |
1347 | ||
1e915849 RS |
1348 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1349 | ||
1350 | static void | |
1351 | install_insn (const struct mips_cl_insn *insn) | |
1352 | { | |
1353 | char *f = insn->frag->fr_literal + insn->where; | |
1354 | if (!mips_opts.mips16) | |
1355 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1356 | else if (insn->mips16_absolute_jump_p) | |
1357 | { | |
1358 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1359 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1360 | } | |
1361 | else | |
1362 | { | |
1363 | if (insn->use_extend) | |
1364 | { | |
1365 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1366 | f += 2; | |
1367 | } | |
1368 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1369 | } | |
742a56fe | 1370 | mips_record_mips16_mode (); |
1e915849 RS |
1371 | } |
1372 | ||
1373 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1374 | and install the opcode in the new location. */ | |
1375 | ||
1376 | static void | |
1377 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1378 | { | |
1379 | size_t i; | |
1380 | ||
1381 | insn->frag = frag; | |
1382 | insn->where = where; | |
1383 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1384 | if (insn->fixp[i] != NULL) | |
1385 | { | |
1386 | insn->fixp[i]->fx_frag = frag; | |
1387 | insn->fixp[i]->fx_where = where; | |
1388 | } | |
1389 | install_insn (insn); | |
1390 | } | |
1391 | ||
1392 | /* Add INSN to the end of the output. */ | |
1393 | ||
1394 | static void | |
1395 | add_fixed_insn (struct mips_cl_insn *insn) | |
1396 | { | |
1397 | char *f = frag_more (insn_length (insn)); | |
1398 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1399 | } | |
1400 | ||
1401 | /* Start a variant frag and move INSN to the start of the variant part, | |
1402 | marking it as fixed. The other arguments are as for frag_var. */ | |
1403 | ||
1404 | static void | |
1405 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1406 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1407 | { | |
1408 | frag_grow (max_chars); | |
1409 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1410 | insn->fixed_p = 1; | |
1411 | frag_var (rs_machine_dependent, max_chars, var, | |
1412 | subtype, symbol, offset, NULL); | |
1413 | } | |
1414 | ||
1415 | /* Insert N copies of INSN into the history buffer, starting at | |
1416 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1417 | ||
1418 | static void | |
1419 | insert_into_history (unsigned int first, unsigned int n, | |
1420 | const struct mips_cl_insn *insn) | |
1421 | { | |
1422 | if (mips_relax.sequence != 2) | |
1423 | { | |
1424 | unsigned int i; | |
1425 | ||
1426 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1427 | if (i >= first + n) | |
1428 | history[i] = history[i - n]; | |
1429 | else | |
1430 | history[i] = *insn; | |
1431 | } | |
1432 | } | |
1433 | ||
1434 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1435 | ||
1436 | static void | |
1437 | emit_nop (void) | |
1438 | { | |
1439 | add_fixed_insn (NOP_INSN); | |
1440 | insert_into_history (0, 1, NOP_INSN); | |
1441 | } | |
1442 | ||
71400594 RS |
1443 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1444 | the idea is to make it obvious at a glance that each errata is | |
1445 | included. */ | |
1446 | ||
1447 | static void | |
1448 | init_vr4120_conflicts (void) | |
1449 | { | |
1450 | #define CONFLICT(FIRST, SECOND) \ | |
1451 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1452 | ||
1453 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1454 | CONFLICT (MACC, DIV); | |
1455 | CONFLICT (DMACC, DIV); | |
1456 | ||
1457 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1458 | CONFLICT (DMULT, DMULT); | |
1459 | CONFLICT (DMULT, DMACC); | |
1460 | CONFLICT (DMACC, DMULT); | |
1461 | CONFLICT (DMACC, DMACC); | |
1462 | ||
1463 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1464 | CONFLICT (MACC, MTHILO); | |
1465 | CONFLICT (DMACC, MTHILO); | |
1466 | ||
1467 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1468 | instruction is executed immediately after a MACC or DMACC | |
1469 | instruction, the result of [either instruction] is incorrect." */ | |
1470 | CONFLICT (MACC, MULT); | |
1471 | CONFLICT (MACC, DMULT); | |
1472 | CONFLICT (DMACC, MULT); | |
1473 | CONFLICT (DMACC, DMULT); | |
1474 | ||
1475 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1476 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1477 | DDIV or DDIVU instruction, the result of the MACC or | |
1478 | DMACC instruction is incorrect.". */ | |
1479 | CONFLICT (DMULT, MACC); | |
1480 | CONFLICT (DMULT, DMACC); | |
1481 | CONFLICT (DIV, MACC); | |
1482 | CONFLICT (DIV, DMACC); | |
1483 | ||
1484 | #undef CONFLICT | |
1485 | } | |
1486 | ||
707bfff6 TS |
1487 | struct regname { |
1488 | const char *name; | |
1489 | unsigned int num; | |
1490 | }; | |
1491 | ||
1492 | #define RTYPE_MASK 0x1ff00 | |
1493 | #define RTYPE_NUM 0x00100 | |
1494 | #define RTYPE_FPU 0x00200 | |
1495 | #define RTYPE_FCC 0x00400 | |
1496 | #define RTYPE_VEC 0x00800 | |
1497 | #define RTYPE_GP 0x01000 | |
1498 | #define RTYPE_CP0 0x02000 | |
1499 | #define RTYPE_PC 0x04000 | |
1500 | #define RTYPE_ACC 0x08000 | |
1501 | #define RTYPE_CCC 0x10000 | |
1502 | #define RNUM_MASK 0x000ff | |
1503 | #define RWARN 0x80000 | |
1504 | ||
1505 | #define GENERIC_REGISTER_NUMBERS \ | |
1506 | {"$0", RTYPE_NUM | 0}, \ | |
1507 | {"$1", RTYPE_NUM | 1}, \ | |
1508 | {"$2", RTYPE_NUM | 2}, \ | |
1509 | {"$3", RTYPE_NUM | 3}, \ | |
1510 | {"$4", RTYPE_NUM | 4}, \ | |
1511 | {"$5", RTYPE_NUM | 5}, \ | |
1512 | {"$6", RTYPE_NUM | 6}, \ | |
1513 | {"$7", RTYPE_NUM | 7}, \ | |
1514 | {"$8", RTYPE_NUM | 8}, \ | |
1515 | {"$9", RTYPE_NUM | 9}, \ | |
1516 | {"$10", RTYPE_NUM | 10}, \ | |
1517 | {"$11", RTYPE_NUM | 11}, \ | |
1518 | {"$12", RTYPE_NUM | 12}, \ | |
1519 | {"$13", RTYPE_NUM | 13}, \ | |
1520 | {"$14", RTYPE_NUM | 14}, \ | |
1521 | {"$15", RTYPE_NUM | 15}, \ | |
1522 | {"$16", RTYPE_NUM | 16}, \ | |
1523 | {"$17", RTYPE_NUM | 17}, \ | |
1524 | {"$18", RTYPE_NUM | 18}, \ | |
1525 | {"$19", RTYPE_NUM | 19}, \ | |
1526 | {"$20", RTYPE_NUM | 20}, \ | |
1527 | {"$21", RTYPE_NUM | 21}, \ | |
1528 | {"$22", RTYPE_NUM | 22}, \ | |
1529 | {"$23", RTYPE_NUM | 23}, \ | |
1530 | {"$24", RTYPE_NUM | 24}, \ | |
1531 | {"$25", RTYPE_NUM | 25}, \ | |
1532 | {"$26", RTYPE_NUM | 26}, \ | |
1533 | {"$27", RTYPE_NUM | 27}, \ | |
1534 | {"$28", RTYPE_NUM | 28}, \ | |
1535 | {"$29", RTYPE_NUM | 29}, \ | |
1536 | {"$30", RTYPE_NUM | 30}, \ | |
1537 | {"$31", RTYPE_NUM | 31} | |
1538 | ||
1539 | #define FPU_REGISTER_NAMES \ | |
1540 | {"$f0", RTYPE_FPU | 0}, \ | |
1541 | {"$f1", RTYPE_FPU | 1}, \ | |
1542 | {"$f2", RTYPE_FPU | 2}, \ | |
1543 | {"$f3", RTYPE_FPU | 3}, \ | |
1544 | {"$f4", RTYPE_FPU | 4}, \ | |
1545 | {"$f5", RTYPE_FPU | 5}, \ | |
1546 | {"$f6", RTYPE_FPU | 6}, \ | |
1547 | {"$f7", RTYPE_FPU | 7}, \ | |
1548 | {"$f8", RTYPE_FPU | 8}, \ | |
1549 | {"$f9", RTYPE_FPU | 9}, \ | |
1550 | {"$f10", RTYPE_FPU | 10}, \ | |
1551 | {"$f11", RTYPE_FPU | 11}, \ | |
1552 | {"$f12", RTYPE_FPU | 12}, \ | |
1553 | {"$f13", RTYPE_FPU | 13}, \ | |
1554 | {"$f14", RTYPE_FPU | 14}, \ | |
1555 | {"$f15", RTYPE_FPU | 15}, \ | |
1556 | {"$f16", RTYPE_FPU | 16}, \ | |
1557 | {"$f17", RTYPE_FPU | 17}, \ | |
1558 | {"$f18", RTYPE_FPU | 18}, \ | |
1559 | {"$f19", RTYPE_FPU | 19}, \ | |
1560 | {"$f20", RTYPE_FPU | 20}, \ | |
1561 | {"$f21", RTYPE_FPU | 21}, \ | |
1562 | {"$f22", RTYPE_FPU | 22}, \ | |
1563 | {"$f23", RTYPE_FPU | 23}, \ | |
1564 | {"$f24", RTYPE_FPU | 24}, \ | |
1565 | {"$f25", RTYPE_FPU | 25}, \ | |
1566 | {"$f26", RTYPE_FPU | 26}, \ | |
1567 | {"$f27", RTYPE_FPU | 27}, \ | |
1568 | {"$f28", RTYPE_FPU | 28}, \ | |
1569 | {"$f29", RTYPE_FPU | 29}, \ | |
1570 | {"$f30", RTYPE_FPU | 30}, \ | |
1571 | {"$f31", RTYPE_FPU | 31} | |
1572 | ||
1573 | #define FPU_CONDITION_CODE_NAMES \ | |
1574 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1575 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1576 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1577 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1578 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1579 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1580 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1581 | {"$fcc7", RTYPE_FCC | 7} | |
1582 | ||
1583 | #define COPROC_CONDITION_CODE_NAMES \ | |
1584 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1585 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1586 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1587 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1588 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1589 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1590 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1591 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1592 | ||
1593 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1594 | {"$a4", RTYPE_GP | 8}, \ | |
1595 | {"$a5", RTYPE_GP | 9}, \ | |
1596 | {"$a6", RTYPE_GP | 10}, \ | |
1597 | {"$a7", RTYPE_GP | 11}, \ | |
1598 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1599 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1600 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1601 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1602 | {"$t0", RTYPE_GP | 12}, \ | |
1603 | {"$t1", RTYPE_GP | 13}, \ | |
1604 | {"$t2", RTYPE_GP | 14}, \ | |
1605 | {"$t3", RTYPE_GP | 15} | |
1606 | ||
1607 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1608 | {"$t0", RTYPE_GP | 8}, \ | |
1609 | {"$t1", RTYPE_GP | 9}, \ | |
1610 | {"$t2", RTYPE_GP | 10}, \ | |
1611 | {"$t3", RTYPE_GP | 11}, \ | |
1612 | {"$t4", RTYPE_GP | 12}, \ | |
1613 | {"$t5", RTYPE_GP | 13}, \ | |
1614 | {"$t6", RTYPE_GP | 14}, \ | |
1615 | {"$t7", RTYPE_GP | 15}, \ | |
1616 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1617 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1618 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1619 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1620 | ||
1621 | /* Remaining symbolic register names */ | |
1622 | #define SYMBOLIC_REGISTER_NAMES \ | |
1623 | {"$zero", RTYPE_GP | 0}, \ | |
1624 | {"$at", RTYPE_GP | 1}, \ | |
1625 | {"$AT", RTYPE_GP | 1}, \ | |
1626 | {"$v0", RTYPE_GP | 2}, \ | |
1627 | {"$v1", RTYPE_GP | 3}, \ | |
1628 | {"$a0", RTYPE_GP | 4}, \ | |
1629 | {"$a1", RTYPE_GP | 5}, \ | |
1630 | {"$a2", RTYPE_GP | 6}, \ | |
1631 | {"$a3", RTYPE_GP | 7}, \ | |
1632 | {"$s0", RTYPE_GP | 16}, \ | |
1633 | {"$s1", RTYPE_GP | 17}, \ | |
1634 | {"$s2", RTYPE_GP | 18}, \ | |
1635 | {"$s3", RTYPE_GP | 19}, \ | |
1636 | {"$s4", RTYPE_GP | 20}, \ | |
1637 | {"$s5", RTYPE_GP | 21}, \ | |
1638 | {"$s6", RTYPE_GP | 22}, \ | |
1639 | {"$s7", RTYPE_GP | 23}, \ | |
1640 | {"$t8", RTYPE_GP | 24}, \ | |
1641 | {"$t9", RTYPE_GP | 25}, \ | |
1642 | {"$k0", RTYPE_GP | 26}, \ | |
1643 | {"$kt0", RTYPE_GP | 26}, \ | |
1644 | {"$k1", RTYPE_GP | 27}, \ | |
1645 | {"$kt1", RTYPE_GP | 27}, \ | |
1646 | {"$gp", RTYPE_GP | 28}, \ | |
1647 | {"$sp", RTYPE_GP | 29}, \ | |
1648 | {"$s8", RTYPE_GP | 30}, \ | |
1649 | {"$fp", RTYPE_GP | 30}, \ | |
1650 | {"$ra", RTYPE_GP | 31} | |
1651 | ||
1652 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1653 | {"$pc", RTYPE_PC | 0} | |
1654 | ||
1655 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1656 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1657 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1658 | {"$v2", RTYPE_VEC | 2}, \ | |
1659 | {"$v3", RTYPE_VEC | 3}, \ | |
1660 | {"$v4", RTYPE_VEC | 4}, \ | |
1661 | {"$v5", RTYPE_VEC | 5}, \ | |
1662 | {"$v6", RTYPE_VEC | 6}, \ | |
1663 | {"$v7", RTYPE_VEC | 7}, \ | |
1664 | {"$v8", RTYPE_VEC | 8}, \ | |
1665 | {"$v9", RTYPE_VEC | 9}, \ | |
1666 | {"$v10", RTYPE_VEC | 10}, \ | |
1667 | {"$v11", RTYPE_VEC | 11}, \ | |
1668 | {"$v12", RTYPE_VEC | 12}, \ | |
1669 | {"$v13", RTYPE_VEC | 13}, \ | |
1670 | {"$v14", RTYPE_VEC | 14}, \ | |
1671 | {"$v15", RTYPE_VEC | 15}, \ | |
1672 | {"$v16", RTYPE_VEC | 16}, \ | |
1673 | {"$v17", RTYPE_VEC | 17}, \ | |
1674 | {"$v18", RTYPE_VEC | 18}, \ | |
1675 | {"$v19", RTYPE_VEC | 19}, \ | |
1676 | {"$v20", RTYPE_VEC | 20}, \ | |
1677 | {"$v21", RTYPE_VEC | 21}, \ | |
1678 | {"$v22", RTYPE_VEC | 22}, \ | |
1679 | {"$v23", RTYPE_VEC | 23}, \ | |
1680 | {"$v24", RTYPE_VEC | 24}, \ | |
1681 | {"$v25", RTYPE_VEC | 25}, \ | |
1682 | {"$v26", RTYPE_VEC | 26}, \ | |
1683 | {"$v27", RTYPE_VEC | 27}, \ | |
1684 | {"$v28", RTYPE_VEC | 28}, \ | |
1685 | {"$v29", RTYPE_VEC | 29}, \ | |
1686 | {"$v30", RTYPE_VEC | 30}, \ | |
1687 | {"$v31", RTYPE_VEC | 31} | |
1688 | ||
1689 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1690 | {"$ac0", RTYPE_ACC | 0}, \ | |
1691 | {"$ac1", RTYPE_ACC | 1}, \ | |
1692 | {"$ac2", RTYPE_ACC | 2}, \ | |
1693 | {"$ac3", RTYPE_ACC | 3} | |
1694 | ||
1695 | static const struct regname reg_names[] = { | |
1696 | GENERIC_REGISTER_NUMBERS, | |
1697 | FPU_REGISTER_NAMES, | |
1698 | FPU_CONDITION_CODE_NAMES, | |
1699 | COPROC_CONDITION_CODE_NAMES, | |
1700 | ||
1701 | /* The $txx registers depends on the abi, | |
1702 | these will be added later into the symbol table from | |
1703 | one of the tables below once mips_abi is set after | |
1704 | parsing of arguments from the command line. */ | |
1705 | SYMBOLIC_REGISTER_NAMES, | |
1706 | ||
1707 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1708 | MDMX_VECTOR_REGISTER_NAMES, | |
1709 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1710 | {0, 0} | |
1711 | }; | |
1712 | ||
1713 | static const struct regname reg_names_o32[] = { | |
1714 | O32_SYMBOLIC_REGISTER_NAMES, | |
1715 | {0, 0} | |
1716 | }; | |
1717 | ||
1718 | static const struct regname reg_names_n32n64[] = { | |
1719 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1720 | {0, 0} | |
1721 | }; | |
1722 | ||
1723 | static int | |
1724 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1725 | { | |
1726 | symbolS *symbolP; | |
1727 | char *e; | |
1728 | char save_c; | |
1729 | int reg = -1; | |
1730 | ||
1731 | /* Find end of name. */ | |
1732 | e = *s; | |
1733 | if (is_name_beginner (*e)) | |
1734 | ++e; | |
1735 | while (is_part_of_name (*e)) | |
1736 | ++e; | |
1737 | ||
1738 | /* Terminate name. */ | |
1739 | save_c = *e; | |
1740 | *e = '\0'; | |
1741 | ||
1742 | /* Look for a register symbol. */ | |
1743 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1744 | { | |
1745 | int r = S_GET_VALUE (symbolP); | |
1746 | if (r & types) | |
1747 | reg = r & RNUM_MASK; | |
1748 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1749 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1750 | reg = (r & RNUM_MASK) - 2; | |
1751 | } | |
1752 | /* Else see if this is a register defined in an itbl entry. */ | |
1753 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1754 | { | |
1755 | char *n = *s; | |
1756 | unsigned long r; | |
1757 | ||
1758 | if (*n == '$') | |
1759 | ++n; | |
1760 | if (itbl_get_reg_val (n, &r)) | |
1761 | reg = r & RNUM_MASK; | |
1762 | } | |
1763 | ||
1764 | /* Advance to next token if a register was recognised. */ | |
1765 | if (reg >= 0) | |
1766 | *s = e; | |
1767 | else if (types & RWARN) | |
1768 | as_warn ("Unrecognized register name `%s'", *s); | |
1769 | ||
1770 | *e = save_c; | |
1771 | if (regnop) | |
1772 | *regnop = reg; | |
1773 | return reg >= 0; | |
1774 | } | |
1775 | ||
037b32b9 AN |
1776 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
1777 | architecture. If EXPANSIONP is TRUE then this check is done while | |
1778 | expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
1779 | ||
1780 | static bfd_boolean | |
1781 | is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp) | |
1782 | { | |
1783 | int isa = mips_opts.isa; | |
1784 | int fp_s, fp_d; | |
1785 | ||
1786 | if (mips_opts.ase_mdmx) | |
1787 | isa |= INSN_MDMX; | |
1788 | if (mips_opts.ase_dsp) | |
1789 | isa |= INSN_DSP; | |
1790 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1791 | isa |= INSN_DSP64; | |
1792 | if (mips_opts.ase_dspr2) | |
1793 | isa |= INSN_DSPR2; | |
1794 | if (mips_opts.ase_mt) | |
1795 | isa |= INSN_MT; | |
1796 | if (mips_opts.ase_mips3d) | |
1797 | isa |= INSN_MIPS3D; | |
1798 | if (mips_opts.ase_smartmips) | |
1799 | isa |= INSN_SMARTMIPS; | |
1800 | ||
1801 | /* For user code we don't check for mips_opts.mips16 since we want | |
1802 | to allow jalx if -mips16 was specified on the command line. */ | |
1803 | if (expansionp ? mips_opts.mips16 : file_ase_mips16) | |
1804 | isa |= INSN_MIPS16; | |
1805 | ||
1806 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) | |
1807 | return FALSE; | |
1808 | ||
1809 | /* Check whether the instruction or macro requires single-precision or | |
1810 | double-precision floating-point support. Note that this information is | |
1811 | stored differently in the opcode table for insns and macros. */ | |
1812 | if (mo->pinfo == INSN_MACRO) | |
1813 | { | |
1814 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1815 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1816 | } | |
1817 | else | |
1818 | { | |
1819 | fp_s = mo->pinfo & FP_S; | |
1820 | fp_d = mo->pinfo & FP_D; | |
1821 | } | |
1822 | ||
1823 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1824 | return FALSE; | |
1825 | ||
1826 | if (fp_s && mips_opts.soft_float) | |
1827 | return FALSE; | |
1828 | ||
1829 | return TRUE; | |
1830 | } | |
1831 | ||
1832 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1833 | selected ISA and architecture. */ | |
1834 | ||
1835 | static bfd_boolean | |
1836 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1837 | { | |
1838 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1839 | } | |
1840 | ||
707bfff6 TS |
1841 | /* This function is called once, at assembler startup time. It should set up |
1842 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1843 | |
252b5132 | 1844 | void |
17a2f251 | 1845 | md_begin (void) |
252b5132 | 1846 | { |
3994f87e | 1847 | const char *retval = NULL; |
156c2f8b | 1848 | int i = 0; |
252b5132 | 1849 | int broken = 0; |
1f25f5d3 | 1850 | |
0a44bf69 RS |
1851 | if (mips_pic != NO_PIC) |
1852 | { | |
1853 | if (g_switch_seen && g_switch_value != 0) | |
1854 | as_bad (_("-G may not be used in position-independent code")); | |
1855 | g_switch_value = 0; | |
1856 | } | |
1857 | ||
fef14a42 | 1858 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1859 | as_warn (_("Could not set architecture and machine")); |
1860 | ||
252b5132 RH |
1861 | op_hash = hash_new (); |
1862 | ||
1863 | for (i = 0; i < NUMOPCODES;) | |
1864 | { | |
1865 | const char *name = mips_opcodes[i].name; | |
1866 | ||
17a2f251 | 1867 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1868 | if (retval != NULL) |
1869 | { | |
1870 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1871 | mips_opcodes[i].name, retval); | |
1872 | /* Probably a memory allocation problem? Give up now. */ | |
1873 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1874 | } | |
1875 | do | |
1876 | { | |
1877 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1878 | { | |
1879 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1880 | broken = 1; | |
1e915849 RS |
1881 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1882 | { | |
1883 | create_insn (&nop_insn, mips_opcodes + i); | |
1884 | nop_insn.fixed_p = 1; | |
1885 | } | |
252b5132 RH |
1886 | } |
1887 | ++i; | |
1888 | } | |
1889 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1890 | } | |
1891 | ||
1892 | mips16_op_hash = hash_new (); | |
1893 | ||
1894 | i = 0; | |
1895 | while (i < bfd_mips16_num_opcodes) | |
1896 | { | |
1897 | const char *name = mips16_opcodes[i].name; | |
1898 | ||
17a2f251 | 1899 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1900 | if (retval != NULL) |
1901 | as_fatal (_("internal: can't hash `%s': %s"), | |
1902 | mips16_opcodes[i].name, retval); | |
1903 | do | |
1904 | { | |
1905 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1906 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1907 | != mips16_opcodes[i].match)) | |
1908 | { | |
1909 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1910 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1911 | broken = 1; | |
1912 | } | |
1e915849 RS |
1913 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1914 | { | |
1915 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1916 | mips16_nop_insn.fixed_p = 1; | |
1917 | } | |
252b5132 RH |
1918 | ++i; |
1919 | } | |
1920 | while (i < bfd_mips16_num_opcodes | |
1921 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1922 | } | |
1923 | ||
1924 | if (broken) | |
1925 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1926 | ||
1927 | /* We add all the general register names to the symbol table. This | |
1928 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1929 | for (i = 0; reg_names[i].name; i++) |
1930 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1931 | reg_names[i].num, // & RNUM_MASK, | |
1932 | &zero_address_frag)); | |
1933 | if (HAVE_NEWABI) | |
1934 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1935 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1936 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1937 | &zero_address_frag)); |
707bfff6 TS |
1938 | else |
1939 | for (i = 0; reg_names_o32[i].name; i++) | |
1940 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1941 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1942 | &zero_address_frag)); |
6047c971 | 1943 | |
7d10b47d | 1944 | mips_no_prev_insn (); |
252b5132 RH |
1945 | |
1946 | mips_gprmask = 0; | |
1947 | mips_cprmask[0] = 0; | |
1948 | mips_cprmask[1] = 0; | |
1949 | mips_cprmask[2] = 0; | |
1950 | mips_cprmask[3] = 0; | |
1951 | ||
1952 | /* set the default alignment for the text section (2**2) */ | |
1953 | record_alignment (text_section, 2); | |
1954 | ||
4d0d148d | 1955 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1956 | |
707bfff6 | 1957 | #ifdef OBJ_ELF |
f43abd2b | 1958 | if (IS_ELF) |
252b5132 | 1959 | { |
0a44bf69 RS |
1960 | /* On a native system other than VxWorks, sections must be aligned |
1961 | to 16 byte boundaries. When configured for an embedded ELF | |
1962 | target, we don't bother. */ | |
c41e87e3 CF |
1963 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
1964 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
1965 | { |
1966 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1967 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1968 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1969 | } | |
1970 | ||
1971 | /* Create a .reginfo section for register masks and a .mdebug | |
1972 | section for debugging information. */ | |
1973 | { | |
1974 | segT seg; | |
1975 | subsegT subseg; | |
1976 | flagword flags; | |
1977 | segT sec; | |
1978 | ||
1979 | seg = now_seg; | |
1980 | subseg = now_subseg; | |
1981 | ||
1982 | /* The ABI says this section should be loaded so that the | |
1983 | running program can access it. However, we don't load it | |
1984 | if we are configured for an embedded target */ | |
1985 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 1986 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
1987 | flags |= SEC_ALLOC | SEC_LOAD; |
1988 | ||
316f5878 | 1989 | if (mips_abi != N64_ABI) |
252b5132 RH |
1990 | { |
1991 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1992 | ||
195325d2 TS |
1993 | bfd_set_section_flags (stdoutput, sec, flags); |
1994 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1995 | |
252b5132 | 1996 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1997 | } |
1998 | else | |
1999 | { | |
2000 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2001 | .reginfo section. */ | |
2002 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2003 | bfd_set_section_flags (stdoutput, sec, flags); |
2004 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2005 | |
252b5132 RH |
2006 | /* Set up the option header. */ |
2007 | { | |
2008 | Elf_Internal_Options opthdr; | |
2009 | char *f; | |
2010 | ||
2011 | opthdr.kind = ODK_REGINFO; | |
2012 | opthdr.size = (sizeof (Elf_External_Options) | |
2013 | + sizeof (Elf64_External_RegInfo)); | |
2014 | opthdr.section = 0; | |
2015 | opthdr.info = 0; | |
2016 | f = frag_more (sizeof (Elf_External_Options)); | |
2017 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2018 | (Elf_External_Options *) f); | |
2019 | ||
2020 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2021 | } | |
252b5132 RH |
2022 | } |
2023 | ||
2024 | if (ECOFF_DEBUGGING) | |
2025 | { | |
2026 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2027 | (void) bfd_set_section_flags (stdoutput, sec, | |
2028 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2029 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2030 | } | |
f43abd2b | 2031 | else if (mips_flag_pdr) |
ecb4347a DJ |
2032 | { |
2033 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2034 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2035 | SEC_READONLY | SEC_RELOC | |
2036 | | SEC_DEBUGGING); | |
2037 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2038 | } | |
252b5132 RH |
2039 | |
2040 | subseg_set (seg, subseg); | |
2041 | } | |
2042 | } | |
707bfff6 | 2043 | #endif /* OBJ_ELF */ |
252b5132 RH |
2044 | |
2045 | if (! ECOFF_DEBUGGING) | |
2046 | md_obj_begin (); | |
71400594 RS |
2047 | |
2048 | if (mips_fix_vr4120) | |
2049 | init_vr4120_conflicts (); | |
252b5132 RH |
2050 | } |
2051 | ||
2052 | void | |
17a2f251 | 2053 | md_mips_end (void) |
252b5132 RH |
2054 | { |
2055 | if (! ECOFF_DEBUGGING) | |
2056 | md_obj_end (); | |
2057 | } | |
2058 | ||
2059 | void | |
17a2f251 | 2060 | md_assemble (char *str) |
252b5132 RH |
2061 | { |
2062 | struct mips_cl_insn insn; | |
f6688943 TS |
2063 | bfd_reloc_code_real_type unused_reloc[3] |
2064 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2065 | |
2066 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2067 | imm2_expr.X_op = O_absent; |
252b5132 | 2068 | offset_expr.X_op = O_absent; |
f6688943 TS |
2069 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2070 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2071 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2072 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2073 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2074 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2075 | |
2076 | if (mips_opts.mips16) | |
2077 | mips16_ip (str, &insn); | |
2078 | else | |
2079 | { | |
2080 | mips_ip (str, &insn); | |
beae10d5 KH |
2081 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2082 | str, insn.insn_opcode)); | |
252b5132 RH |
2083 | } |
2084 | ||
2085 | if (insn_error) | |
2086 | { | |
2087 | as_bad ("%s `%s'", insn_error, str); | |
2088 | return; | |
2089 | } | |
2090 | ||
2091 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2092 | { | |
584892a6 | 2093 | macro_start (); |
252b5132 RH |
2094 | if (mips_opts.mips16) |
2095 | mips16_macro (&insn); | |
2096 | else | |
2097 | macro (&insn); | |
584892a6 | 2098 | macro_end (); |
252b5132 RH |
2099 | } |
2100 | else | |
2101 | { | |
2102 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2103 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2104 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2105 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2106 | else |
4d7206a2 | 2107 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2108 | } |
2109 | } | |
2110 | ||
5919d012 | 2111 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2112 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2113 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2114 | |
2115 | static inline bfd_boolean | |
17a2f251 | 2116 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2117 | { |
3b91255e RS |
2118 | return (HAVE_IN_PLACE_ADDENDS |
2119 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2120 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2121 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2122 | all GOT16 relocations evaluate to "G". */ | |
2123 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2124 | } |
2125 | ||
2126 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2127 | relocation. */ | |
2128 | ||
2129 | static inline bfd_boolean | |
17a2f251 | 2130 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2131 | { |
2132 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2133 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2134 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2135 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2136 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2137 | } | |
2138 | ||
252b5132 RH |
2139 | /* See whether instruction IP reads register REG. CLASS is the type |
2140 | of register. */ | |
2141 | ||
2142 | static int | |
71400594 | 2143 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2144 | enum mips_regclass class) |
252b5132 RH |
2145 | { |
2146 | if (class == MIPS16_REG) | |
2147 | { | |
2148 | assert (mips_opts.mips16); | |
2149 | reg = mips16_to_32_reg_map[reg]; | |
2150 | class = MIPS_GR_REG; | |
2151 | } | |
2152 | ||
85b51719 TS |
2153 | /* Don't report on general register ZERO, since it never changes. */ |
2154 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2155 | return 0; |
2156 | ||
2157 | if (class == MIPS_FP_REG) | |
2158 | { | |
2159 | assert (! mips_opts.mips16); | |
2160 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2161 | This is not optimal, because it will introduce an unnecessary | |
2162 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2163 | need to distinguish reading both $f0 and $f1 or just one of | |
2164 | them. Note that we don't have to check the other way, | |
2165 | because there is no instruction that sets both $f0 and $f1 | |
2166 | and requires a delay. */ | |
2167 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2168 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2169 | == (reg &~ (unsigned) 1))) |
2170 | return 1; | |
2171 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2172 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2173 | == (reg &~ (unsigned) 1))) |
2174 | return 1; | |
2175 | } | |
2176 | else if (! mips_opts.mips16) | |
2177 | { | |
2178 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2179 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2180 | return 1; |
2181 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2182 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2183 | return 1; |
2184 | } | |
2185 | else | |
2186 | { | |
2187 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2188 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2189 | return 1; |
2190 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2191 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2192 | return 1; |
2193 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2194 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2195 | == reg)) |
2196 | return 1; | |
2197 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2198 | return 1; | |
2199 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2200 | return 1; | |
2201 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2202 | return 1; | |
2203 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2204 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2205 | return 1; |
2206 | } | |
2207 | ||
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | /* This function returns true if modifying a register requires a | |
2212 | delay. */ | |
2213 | ||
2214 | static int | |
17a2f251 | 2215 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2216 | { |
2217 | unsigned long prev_pinfo; | |
2218 | ||
47e39b9d | 2219 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2220 | if (! mips_opts.noreorder |
81912461 ILT |
2221 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2222 | && ! gpr_interlocks) | |
2223 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2224 | && ! cop_interlocks))) | |
252b5132 | 2225 | { |
81912461 ILT |
2226 | /* A load from a coprocessor or from memory. All load delays |
2227 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2228 | /* Itbl support may require additional care here. */ |
252b5132 | 2229 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2230 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2231 | return 1; |
2232 | } | |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
404a8071 RS |
2237 | /* Move all labels in insn_labels to the current insertion point. */ |
2238 | ||
2239 | static void | |
2240 | mips_move_labels (void) | |
2241 | { | |
a8dbcb85 | 2242 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2243 | struct insn_label_list *l; |
2244 | valueT val; | |
2245 | ||
a8dbcb85 | 2246 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2247 | { |
2248 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2249 | symbol_set_frag (l->label, frag_now); | |
2250 | val = (valueT) frag_now_fix (); | |
2251 | /* mips16 text labels are stored as odd. */ | |
2252 | if (mips_opts.mips16) | |
2253 | ++val; | |
2254 | S_SET_VALUE (l->label, val); | |
2255 | } | |
2256 | } | |
2257 | ||
5f0fe04b TS |
2258 | static bfd_boolean |
2259 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2260 | { | |
2261 | bfd_boolean linkonce = FALSE; | |
2262 | segT symseg = S_GET_SEGMENT (sym); | |
2263 | ||
2264 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2265 | { | |
2266 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2267 | linkonce = TRUE; | |
2268 | #ifdef OBJ_ELF | |
2269 | /* The GNU toolchain uses an extension for ELF: a section | |
2270 | beginning with the magic string .gnu.linkonce is a | |
2271 | linkonce section. */ | |
2272 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2273 | sizeof ".gnu.linkonce" - 1) == 0) | |
2274 | linkonce = TRUE; | |
2275 | #endif | |
2276 | } | |
2277 | return linkonce; | |
2278 | } | |
2279 | ||
252b5132 RH |
2280 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2281 | handle them specially, such as generating jalx instructions when | |
2282 | needed. We also make them odd for the duration of the assembly, in | |
2283 | order to generate the right sort of code. We will make them even | |
2284 | in the adjust_symtab routine, while leaving them marked. This is | |
2285 | convenient for the debugger and the disassembler. The linker knows | |
2286 | to make them odd again. */ | |
2287 | ||
2288 | static void | |
17a2f251 | 2289 | mips16_mark_labels (void) |
252b5132 | 2290 | { |
a8dbcb85 TS |
2291 | segment_info_type *si = seg_info (now_seg); |
2292 | struct insn_label_list *l; | |
252b5132 | 2293 | |
a8dbcb85 TS |
2294 | if (!mips_opts.mips16) |
2295 | return; | |
2296 | ||
2297 | for (l = si->label_list; l != NULL; l = l->next) | |
2298 | { | |
2299 | symbolS *label = l->label; | |
2300 | ||
2301 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2302 | if (IS_ELF) |
a8dbcb85 | 2303 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2304 | #endif |
5f0fe04b TS |
2305 | if ((S_GET_VALUE (label) & 1) == 0 |
2306 | /* Don't adjust the address if the label is global or weak, or | |
2307 | in a link-once section, since we'll be emitting symbol reloc | |
2308 | references to it which will be patched up by the linker, and | |
2309 | the final value of the symbol may or may not be MIPS16. */ | |
2310 | && ! S_IS_WEAK (label) | |
2311 | && ! S_IS_EXTERNAL (label) | |
2312 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2313 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2314 | } |
2315 | } | |
2316 | ||
4d7206a2 RS |
2317 | /* End the current frag. Make it a variant frag and record the |
2318 | relaxation info. */ | |
2319 | ||
2320 | static void | |
2321 | relax_close_frag (void) | |
2322 | { | |
584892a6 | 2323 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2324 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2325 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2326 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2327 | ||
2328 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2329 | mips_relax.first_fixup = 0; | |
2330 | } | |
2331 | ||
2332 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2333 | See the comment above RELAX_ENCODE for more details. */ | |
2334 | ||
2335 | static void | |
2336 | relax_start (symbolS *symbol) | |
2337 | { | |
2338 | assert (mips_relax.sequence == 0); | |
2339 | mips_relax.sequence = 1; | |
2340 | mips_relax.symbol = symbol; | |
2341 | } | |
2342 | ||
2343 | /* Start generating the second version of a relaxable sequence. | |
2344 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2345 | |
2346 | static void | |
4d7206a2 RS |
2347 | relax_switch (void) |
2348 | { | |
2349 | assert (mips_relax.sequence == 1); | |
2350 | mips_relax.sequence = 2; | |
2351 | } | |
2352 | ||
2353 | /* End the current relaxable sequence. */ | |
2354 | ||
2355 | static void | |
2356 | relax_end (void) | |
2357 | { | |
2358 | assert (mips_relax.sequence == 2); | |
2359 | relax_close_frag (); | |
2360 | mips_relax.sequence = 0; | |
2361 | } | |
2362 | ||
71400594 RS |
2363 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2364 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2365 | by VR4120 errata. */ | |
4d7206a2 | 2366 | |
71400594 RS |
2367 | static unsigned int |
2368 | classify_vr4120_insn (const char *name) | |
252b5132 | 2369 | { |
71400594 RS |
2370 | if (strncmp (name, "macc", 4) == 0) |
2371 | return FIX_VR4120_MACC; | |
2372 | if (strncmp (name, "dmacc", 5) == 0) | |
2373 | return FIX_VR4120_DMACC; | |
2374 | if (strncmp (name, "mult", 4) == 0) | |
2375 | return FIX_VR4120_MULT; | |
2376 | if (strncmp (name, "dmult", 5) == 0) | |
2377 | return FIX_VR4120_DMULT; | |
2378 | if (strstr (name, "div")) | |
2379 | return FIX_VR4120_DIV; | |
2380 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2381 | return FIX_VR4120_MTHILO; | |
2382 | return NUM_FIX_VR4120_CLASSES; | |
2383 | } | |
252b5132 | 2384 | |
71400594 RS |
2385 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2386 | where INSN1 is the earlier instruction. Return the worst-case value | |
2387 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2388 | |
71400594 RS |
2389 | static unsigned int |
2390 | insns_between (const struct mips_cl_insn *insn1, | |
2391 | const struct mips_cl_insn *insn2) | |
2392 | { | |
2393 | unsigned long pinfo1, pinfo2; | |
2394 | ||
2395 | /* This function needs to know which pinfo flags are set for INSN2 | |
2396 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2397 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2398 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2399 | pinfo1 = insn1->insn_mo->pinfo; | |
2400 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2401 | |
71400594 RS |
2402 | #define INSN2_USES_REG(REG, CLASS) \ |
2403 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2404 | ||
2405 | /* For most targets, write-after-read dependencies on the HI and LO | |
2406 | registers must be separated by at least two instructions. */ | |
2407 | if (!hilo_interlocks) | |
252b5132 | 2408 | { |
71400594 RS |
2409 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2410 | return 2; | |
2411 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2412 | return 2; | |
2413 | } | |
2414 | ||
2415 | /* If we're working around r7000 errata, there must be two instructions | |
2416 | between an mfhi or mflo and any instruction that uses the result. */ | |
2417 | if (mips_7000_hilo_fix | |
2418 | && MF_HILO_INSN (pinfo1) | |
2419 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2420 | return 2; | |
2421 | ||
2422 | /* If working around VR4120 errata, check for combinations that need | |
2423 | a single intervening instruction. */ | |
2424 | if (mips_fix_vr4120) | |
2425 | { | |
2426 | unsigned int class1, class2; | |
252b5132 | 2427 | |
71400594 RS |
2428 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2429 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2430 | { |
71400594 RS |
2431 | if (insn2 == NULL) |
2432 | return 1; | |
2433 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2434 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2435 | return 1; | |
252b5132 | 2436 | } |
71400594 RS |
2437 | } |
2438 | ||
2439 | if (!mips_opts.mips16) | |
2440 | { | |
2441 | /* Check for GPR or coprocessor load delays. All such delays | |
2442 | are on the RT register. */ | |
2443 | /* Itbl support may require additional care here. */ | |
2444 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2445 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2446 | { |
71400594 RS |
2447 | know (pinfo1 & INSN_WRITE_GPR_T); |
2448 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2449 | return 1; | |
2450 | } | |
2451 | ||
2452 | /* Check for generic coprocessor hazards. | |
2453 | ||
2454 | This case is not handled very well. There is no special | |
2455 | knowledge of CP0 handling, and the coprocessors other than | |
2456 | the floating point unit are not distinguished at all. */ | |
2457 | /* Itbl support may require additional care here. FIXME! | |
2458 | Need to modify this to include knowledge about | |
2459 | user specified delays! */ | |
2460 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2461 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2462 | { | |
2463 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2464 | register. There must be a one instruction delay before INSN2 | |
2465 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2466 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2467 | { |
71400594 RS |
2468 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2469 | return 1; | |
252b5132 | 2470 | } |
71400594 | 2471 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2472 | { |
71400594 RS |
2473 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2474 | return 1; | |
252b5132 RH |
2475 | } |
2476 | else | |
2477 | { | |
71400594 RS |
2478 | /* Read-after-write dependencies on the control registers |
2479 | require a two-instruction gap. */ | |
2480 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2481 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2482 | return 2; | |
2483 | ||
2484 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2485 | also a coprocessor instruction, assume there must be | |
2486 | a one instruction gap. */ | |
2487 | if (pinfo2 & INSN_COP) | |
2488 | return 1; | |
252b5132 RH |
2489 | } |
2490 | } | |
6b76fefe | 2491 | |
71400594 RS |
2492 | /* Check for read-after-write dependencies on the coprocessor |
2493 | control registers in cases where INSN1 does not need a general | |
2494 | coprocessor delay. This means that INSN1 is a floating point | |
2495 | comparison instruction. */ | |
2496 | /* Itbl support may require additional care here. */ | |
2497 | else if (!cop_interlocks | |
2498 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2499 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2500 | return 1; | |
2501 | } | |
6b76fefe | 2502 | |
71400594 | 2503 | #undef INSN2_USES_REG |
6b76fefe | 2504 | |
71400594 RS |
2505 | return 0; |
2506 | } | |
6b76fefe | 2507 | |
7d8e00cf RS |
2508 | /* Return the number of nops that would be needed to work around the |
2509 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2510 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2511 | ||
2512 | static int | |
2513 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2514 | const struct mips_cl_insn *insn) | |
2515 | { | |
2516 | int i, j, reg; | |
2517 | ||
2518 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2519 | are not affected by the errata. */ | |
2520 | if (insn != 0 | |
2521 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2522 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2523 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2524 | return 0; | |
2525 | ||
2526 | /* Search for the first MFLO or MFHI. */ | |
2527 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2528 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2529 | { | |
2530 | /* Extract the destination register. */ | |
2531 | if (mips_opts.mips16) | |
2532 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2533 | else | |
2534 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2535 | ||
2536 | /* No nops are needed if INSN reads that register. */ | |
2537 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2538 | return 0; | |
2539 | ||
2540 | /* ...or if any of the intervening instructions do. */ | |
2541 | for (j = 0; j < i; j++) | |
2542 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2543 | return 0; | |
2544 | ||
2545 | return MAX_VR4130_NOPS - i; | |
2546 | } | |
2547 | return 0; | |
2548 | } | |
2549 | ||
71400594 RS |
2550 | /* Return the number of nops that would be needed if instruction INSN |
2551 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2552 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2553 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2554 | |
71400594 RS |
2555 | static int |
2556 | nops_for_insn (const struct mips_cl_insn *history, | |
2557 | const struct mips_cl_insn *insn) | |
2558 | { | |
2559 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2560 | |
71400594 | 2561 | nops = 0; |
7d8e00cf | 2562 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2563 | if (!history[i].noreorder_p) |
2564 | { | |
2565 | tmp_nops = insns_between (history + i, insn) - i; | |
2566 | if (tmp_nops > nops) | |
2567 | nops = tmp_nops; | |
2568 | } | |
7d8e00cf RS |
2569 | |
2570 | if (mips_fix_vr4130) | |
2571 | { | |
2572 | tmp_nops = nops_for_vr4130 (history, insn); | |
2573 | if (tmp_nops > nops) | |
2574 | nops = tmp_nops; | |
2575 | } | |
2576 | ||
71400594 RS |
2577 | return nops; |
2578 | } | |
252b5132 | 2579 | |
71400594 RS |
2580 | /* The variable arguments provide NUM_INSNS extra instructions that |
2581 | might be added to HISTORY. Return the largest number of nops that | |
2582 | would be needed after the extended sequence. */ | |
252b5132 | 2583 | |
71400594 RS |
2584 | static int |
2585 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2586 | { | |
2587 | va_list args; | |
2588 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2589 | struct mips_cl_insn *cursor; | |
2590 | int nops; | |
2591 | ||
2592 | va_start (args, history); | |
2593 | cursor = buffer + num_insns; | |
2594 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2595 | while (cursor > buffer) | |
2596 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2597 | ||
2598 | nops = nops_for_insn (buffer, NULL); | |
2599 | va_end (args); | |
2600 | return nops; | |
2601 | } | |
252b5132 | 2602 | |
71400594 RS |
2603 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2604 | worst-case delay for the branch target. */ | |
252b5132 | 2605 | |
71400594 RS |
2606 | static int |
2607 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2608 | const struct mips_cl_insn *insn) | |
2609 | { | |
2610 | int nops, tmp_nops; | |
60b63b72 | 2611 | |
71400594 RS |
2612 | nops = nops_for_insn (history, insn); |
2613 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2614 | | INSN_COND_BRANCH_DELAY | |
2615 | | INSN_COND_BRANCH_LIKELY)) | |
2616 | { | |
2617 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2618 | if (tmp_nops > nops) | |
2619 | nops = tmp_nops; | |
2620 | } | |
2621 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2622 | { | |
2623 | tmp_nops = nops_for_sequence (1, history, insn); | |
2624 | if (tmp_nops > nops) | |
2625 | nops = tmp_nops; | |
2626 | } | |
2627 | return nops; | |
2628 | } | |
2629 | ||
2630 | /* Output an instruction. IP is the instruction information. | |
2631 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2632 | RELOC_TYPE. */ | |
2633 | ||
2634 | static void | |
2635 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2636 | bfd_reloc_code_real_type *reloc_type) | |
2637 | { | |
3994f87e | 2638 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2639 | relax_stateT prev_insn_frag_type = 0; |
2640 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2641 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2642 | |
2643 | /* Mark instruction labels in mips16 mode. */ | |
2644 | mips16_mark_labels (); | |
2645 | ||
2646 | prev_pinfo = history[0].insn_mo->pinfo; | |
2647 | pinfo = ip->insn_mo->pinfo; | |
2648 | ||
2649 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2650 | { | |
2651 | /* There are a lot of optimizations we could do that we don't. | |
2652 | In particular, we do not, in general, reorder instructions. | |
2653 | If you use gcc with optimization, it will reorder | |
2654 | instructions and generally do much more optimization then we | |
2655 | do here; repeating all that work in the assembler would only | |
2656 | benefit hand written assembly code, and does not seem worth | |
2657 | it. */ | |
2658 | int nops = (mips_optimize == 0 | |
2659 | ? nops_for_insn (history, NULL) | |
2660 | : nops_for_insn_or_target (history, ip)); | |
2661 | if (nops > 0) | |
252b5132 RH |
2662 | { |
2663 | fragS *old_frag; | |
2664 | unsigned long old_frag_offset; | |
2665 | int i; | |
252b5132 RH |
2666 | |
2667 | old_frag = frag_now; | |
2668 | old_frag_offset = frag_now_fix (); | |
2669 | ||
2670 | for (i = 0; i < nops; i++) | |
2671 | emit_nop (); | |
2672 | ||
2673 | if (listing) | |
2674 | { | |
2675 | listing_prev_line (); | |
2676 | /* We may be at the start of a variant frag. In case we | |
2677 | are, make sure there is enough space for the frag | |
2678 | after the frags created by listing_prev_line. The | |
2679 | argument to frag_grow here must be at least as large | |
2680 | as the argument to all other calls to frag_grow in | |
2681 | this file. We don't have to worry about being in the | |
2682 | middle of a variant frag, because the variants insert | |
2683 | all needed nop instructions themselves. */ | |
2684 | frag_grow (40); | |
2685 | } | |
2686 | ||
404a8071 | 2687 | mips_move_labels (); |
252b5132 RH |
2688 | |
2689 | #ifndef NO_ECOFF_DEBUGGING | |
2690 | if (ECOFF_DEBUGGING) | |
2691 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2692 | #endif | |
2693 | } | |
71400594 RS |
2694 | } |
2695 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2696 | { | |
2697 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2698 | int nops = nops_for_insn_or_target (history, ip); | |
2699 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2700 | |
71400594 RS |
2701 | /* Enforce NOPS as a minimum. */ |
2702 | if (nops > prev_nop_frag_required) | |
2703 | prev_nop_frag_required = nops; | |
252b5132 | 2704 | |
71400594 RS |
2705 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2706 | { | |
2707 | /* Settle for the current number of nops. Update the history | |
2708 | accordingly (for the benefit of any future .set reorder code). */ | |
2709 | prev_nop_frag = NULL; | |
2710 | insert_into_history (prev_nop_frag_since, | |
2711 | prev_nop_frag_holds, NOP_INSN); | |
2712 | } | |
2713 | else | |
2714 | { | |
2715 | /* Allow this instruction to replace one of the nops that was | |
2716 | tentatively added to prev_nop_frag. */ | |
2717 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2718 | prev_nop_frag_holds--; | |
2719 | prev_nop_frag_since++; | |
252b5132 RH |
2720 | } |
2721 | } | |
2722 | ||
58e2ea4d MR |
2723 | #ifdef OBJ_ELF |
2724 | /* The value passed to dwarf2_emit_insn is the distance between | |
2725 | the beginning of the current instruction and the address that | |
2726 | should be recorded in the debug tables. For MIPS16 debug info | |
2727 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2728 | address higher by one than the current. */ | |
2729 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2730 | #endif | |
2731 | ||
895921c9 | 2732 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2733 | if (history[0].frag) |
2734 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2735 | |
4d7206a2 | 2736 | if (address_expr |
0b25d3e6 | 2737 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2738 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2739 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2740 | && mips_relax_branch | |
2741 | /* Don't try branch relaxation within .set nomacro, or within | |
2742 | .set noat if we use $at for PIC computations. If it turns | |
2743 | out that the branch was out-of-range, we'll get an error. */ | |
2744 | && !mips_opts.warn_about_macros | |
741fe287 | 2745 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2746 | && !mips_opts.mips16) |
2747 | { | |
895921c9 | 2748 | relaxed_branch = TRUE; |
1e915849 RS |
2749 | add_relaxed_insn (ip, (relaxed_branch_length |
2750 | (NULL, NULL, | |
2751 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2752 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2753 | : 0)), 4, | |
2754 | RELAX_BRANCH_ENCODE | |
2755 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2756 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2757 | pinfo & INSN_WRITE_GPR_31, | |
2758 | 0), | |
2759 | address_expr->X_add_symbol, | |
2760 | address_expr->X_add_number); | |
4a6a3df4 AO |
2761 | *reloc_type = BFD_RELOC_UNUSED; |
2762 | } | |
2763 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2764 | { |
2765 | /* We need to set up a variant frag. */ | |
2766 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2767 | add_relaxed_insn (ip, 4, 0, |
2768 | RELAX_MIPS16_ENCODE | |
2769 | (*reloc_type - BFD_RELOC_UNUSED, | |
2770 | mips16_small, mips16_ext, | |
2771 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2772 | history[0].mips16_absolute_jump_p), | |
2773 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2774 | } |
252b5132 RH |
2775 | else if (mips_opts.mips16 |
2776 | && ! ip->use_extend | |
f6688943 | 2777 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2778 | { |
b8ee1a6e DU |
2779 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2780 | /* Make sure there is enough room to swap this instruction with | |
2781 | a following jump instruction. */ | |
2782 | frag_grow (6); | |
1e915849 | 2783 | add_fixed_insn (ip); |
252b5132 RH |
2784 | } |
2785 | else | |
2786 | { | |
2787 | if (mips_opts.mips16 | |
2788 | && mips_opts.noreorder | |
2789 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2790 | as_warn (_("extended instruction in delay slot")); | |
2791 | ||
4d7206a2 RS |
2792 | if (mips_relax.sequence) |
2793 | { | |
2794 | /* If we've reached the end of this frag, turn it into a variant | |
2795 | frag and record the information for the instructions we've | |
2796 | written so far. */ | |
2797 | if (frag_room () < 4) | |
2798 | relax_close_frag (); | |
2799 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2800 | } | |
2801 | ||
584892a6 RS |
2802 | if (mips_relax.sequence != 2) |
2803 | mips_macro_warning.sizes[0] += 4; | |
2804 | if (mips_relax.sequence != 1) | |
2805 | mips_macro_warning.sizes[1] += 4; | |
2806 | ||
1e915849 RS |
2807 | if (mips_opts.mips16) |
2808 | { | |
2809 | ip->fixed_p = 1; | |
2810 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2811 | } | |
2812 | add_fixed_insn (ip); | |
252b5132 RH |
2813 | } |
2814 | ||
01a3f561 | 2815 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2816 | { |
2817 | if (address_expr->X_op == O_constant) | |
2818 | { | |
f17c130b | 2819 | unsigned int tmp; |
f6688943 TS |
2820 | |
2821 | switch (*reloc_type) | |
252b5132 RH |
2822 | { |
2823 | case BFD_RELOC_32: | |
2824 | ip->insn_opcode |= address_expr->X_add_number; | |
2825 | break; | |
2826 | ||
f6688943 | 2827 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2828 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2829 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2830 | break; |
2831 | ||
2832 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2833 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2834 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2835 | break; |
2836 | ||
2837 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2838 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2839 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2840 | break; |
2841 | ||
2842 | case BFD_RELOC_HI16: | |
2843 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2844 | break; | |
2845 | ||
01a3f561 | 2846 | case BFD_RELOC_UNUSED: |
252b5132 | 2847 | case BFD_RELOC_LO16: |
ed6fb7bd | 2848 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2849 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2850 | break; | |
2851 | ||
2852 | case BFD_RELOC_MIPS_JMP: | |
2853 | if ((address_expr->X_add_number & 3) != 0) | |
2854 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2855 | (unsigned long) address_expr->X_add_number); | |
2856 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2857 | break; | |
2858 | ||
2859 | case BFD_RELOC_MIPS16_JMP: | |
2860 | if ((address_expr->X_add_number & 3) != 0) | |
2861 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2862 | (unsigned long) address_expr->X_add_number); | |
2863 | ip->insn_opcode |= | |
2864 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2865 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2866 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2867 | break; | |
2868 | ||
252b5132 | 2869 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2870 | if ((address_expr->X_add_number & 3) != 0) |
2871 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2872 | (unsigned long) address_expr->X_add_number); | |
2873 | if (mips_relax_branch) | |
2874 | goto need_reloc; | |
2875 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2876 | as_bad (_("branch address range overflow (0x%lx)"), | |
2877 | (unsigned long) address_expr->X_add_number); | |
2878 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2879 | break; | |
252b5132 RH |
2880 | |
2881 | default: | |
2882 | internalError (); | |
2883 | } | |
2884 | } | |
01a3f561 | 2885 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2886 | need_reloc: |
4d7206a2 RS |
2887 | { |
2888 | reloc_howto_type *howto; | |
2889 | int i; | |
34ce925e | 2890 | |
4d7206a2 RS |
2891 | /* In a compound relocation, it is the final (outermost) |
2892 | operator that determines the relocated field. */ | |
2893 | for (i = 1; i < 3; i++) | |
2894 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2895 | break; | |
34ce925e | 2896 | |
4d7206a2 | 2897 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2898 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2899 | bfd_get_reloc_size (howto), | |
2900 | address_expr, | |
2901 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2902 | reloc_type[0]); | |
4d7206a2 | 2903 | |
b314ec0e RS |
2904 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
2905 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
2906 | && ip->fixp[0]->fx_addsy) | |
2907 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
2908 | ||
4d7206a2 RS |
2909 | /* These relocations can have an addend that won't fit in |
2910 | 4 octets for 64bit assembly. */ | |
2911 | if (HAVE_64BIT_GPRS | |
2912 | && ! howto->partial_inplace | |
2913 | && (reloc_type[0] == BFD_RELOC_16 | |
2914 | || reloc_type[0] == BFD_RELOC_32 | |
2915 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2916 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2917 | || reloc_type[0] == BFD_RELOC_LO16 | |
2918 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2919 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2920 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2921 | || reloc_type[0] == BFD_RELOC_64 | |
2922 | || reloc_type[0] == BFD_RELOC_CTOR | |
2923 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2924 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2925 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2926 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2927 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2928 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2929 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2930 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2931 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2932 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2933 | |
2934 | if (mips_relax.sequence) | |
2935 | { | |
2936 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2937 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2938 | } |
2939 | else if (reloc_needs_lo_p (*reloc_type)) | |
2940 | { | |
2941 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2942 | |
4d7206a2 RS |
2943 | /* Reuse the last entry if it already has a matching %lo. */ |
2944 | hi_fixup = mips_hi_fixup_list; | |
2945 | if (hi_fixup == 0 | |
2946 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2947 | { | |
2948 | hi_fixup = ((struct mips_hi_fixup *) | |
2949 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2950 | hi_fixup->next = mips_hi_fixup_list; | |
2951 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2952 | } |
1e915849 | 2953 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2954 | hi_fixup->seg = now_seg; |
2955 | } | |
f6688943 | 2956 | |
4d7206a2 RS |
2957 | /* Add fixups for the second and third relocations, if given. |
2958 | Note that the ABI allows the second relocation to be | |
2959 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2960 | moment we only use RSS_UNDEF, but we could add support | |
2961 | for the others if it ever becomes necessary. */ | |
2962 | for (i = 1; i < 3; i++) | |
2963 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2964 | { | |
1e915849 RS |
2965 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2966 | ip->fixp[0]->fx_size, NULL, 0, | |
2967 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2968 | |
2969 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2970 | ip->fixp[0]->fx_tcbit = 1; |
2971 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2972 | } |
252b5132 RH |
2973 | } |
2974 | } | |
1e915849 | 2975 | install_insn (ip); |
252b5132 RH |
2976 | |
2977 | /* Update the register mask information. */ | |
2978 | if (! mips_opts.mips16) | |
2979 | { | |
2980 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2981 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2982 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2983 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2984 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2985 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2986 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2987 | mips_gprmask |= 1 << RA; |
252b5132 | 2988 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2989 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2990 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2991 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2992 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2993 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2994 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2995 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2996 | if (pinfo & INSN_COP) |
2997 | { | |
bdaaa2e1 KH |
2998 | /* We don't keep enough information to sort these cases out. |
2999 | The itbl support does keep this information however, although | |
3000 | we currently don't support itbl fprmats as part of the cop | |
3001 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3002 | } |
3003 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3004 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3005 | } |
3006 | else | |
3007 | { | |
3008 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3009 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3010 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3011 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3012 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3013 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3014 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3015 | mips_gprmask |= 1 << TREG; | |
3016 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3017 | mips_gprmask |= 1 << SP; | |
3018 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3019 | mips_gprmask |= 1 << RA; | |
3020 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3021 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3022 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3023 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3024 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3025 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3026 | } |
3027 | ||
4d7206a2 | 3028 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3029 | { |
3030 | /* Filling the branch delay slot is more complex. We try to | |
3031 | switch the branch with the previous instruction, which we can | |
3032 | do if the previous instruction does not set up a condition | |
3033 | that the branch tests and if the branch is not itself the | |
3034 | target of any branch. */ | |
3035 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3036 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3037 | { | |
3038 | if (mips_optimize < 2 | |
3039 | /* If we have seen .set volatile or .set nomove, don't | |
3040 | optimize. */ | |
3041 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3042 | /* We can't swap if the previous instruction's position |
3043 | is fixed. */ | |
3044 | || history[0].fixed_p | |
252b5132 RH |
3045 | /* If the previous previous insn was in a .set |
3046 | noreorder, we can't swap. Actually, the MIPS | |
3047 | assembler will swap in this situation. However, gcc | |
3048 | configured -with-gnu-as will generate code like | |
3049 | .set noreorder | |
3050 | lw $4,XXX | |
3051 | .set reorder | |
3052 | INSN | |
3053 | bne $4,$0,foo | |
3054 | in which we can not swap the bne and INSN. If gcc is | |
3055 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3056 | .set pseudo-ops. */ |
47e39b9d | 3057 | || history[1].noreorder_p |
252b5132 RH |
3058 | /* If the branch is itself the target of a branch, we |
3059 | can not swap. We cheat on this; all we check for is | |
3060 | whether there is a label on this instruction. If | |
3061 | there are any branches to anything other than a | |
3062 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3063 | || si->label_list != NULL |
895921c9 MR |
3064 | /* If the previous instruction is in a variant frag |
3065 | other than this branch's one, we cannot do the swap. | |
3066 | This does not apply to the mips16, which uses variant | |
3067 | frags for different purposes. */ | |
252b5132 | 3068 | || (! mips_opts.mips16 |
895921c9 | 3069 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3070 | /* Check for conflicts between the branch and the instructions |
3071 | before the candidate delay slot. */ | |
3072 | || nops_for_insn (history + 1, ip) > 0 | |
3073 | /* Check for conflicts between the swapped sequence and the | |
3074 | target of the branch. */ | |
3075 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3076 | /* We do not swap with a trap instruction, since it |
3077 | complicates trap handlers to have the trap | |
3078 | instruction be in a delay slot. */ | |
3079 | || (prev_pinfo & INSN_TRAP) | |
3080 | /* If the branch reads a register that the previous | |
3081 | instruction sets, we can not swap. */ | |
3082 | || (! mips_opts.mips16 | |
3083 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3084 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3085 | MIPS_GR_REG)) |
3086 | || (! mips_opts.mips16 | |
3087 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3088 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3089 | MIPS_GR_REG)) |
3090 | || (mips_opts.mips16 | |
3091 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3092 | && (insn_uses_reg |
3093 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3094 | MIPS16_REG))) | |
252b5132 | 3095 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3096 | && (insn_uses_reg |
3097 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3098 | MIPS16_REG))) | |
252b5132 | 3099 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3100 | && (insn_uses_reg |
3101 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3102 | MIPS16_REG))) | |
252b5132 RH |
3103 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3104 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3105 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3106 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3107 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3108 | && insn_uses_reg (ip, | |
47e39b9d RS |
3109 | MIPS16OP_EXTRACT_REG32R |
3110 | (history[0].insn_opcode), | |
252b5132 RH |
3111 | MIPS_GR_REG)))) |
3112 | /* If the branch writes a register that the previous | |
3113 | instruction sets, we can not swap (we know that | |
3114 | branches write only to RD or to $31). */ | |
3115 | || (! mips_opts.mips16 | |
3116 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3117 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3118 | && (EXTRACT_OPERAND (RT, history[0]) |
3119 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3120 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3121 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3122 | || (! mips_opts.mips16 |
3123 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3124 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3125 | && (EXTRACT_OPERAND (RD, history[0]) |
3126 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3127 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3128 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3129 | || (mips_opts.mips16 |
3130 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3131 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3132 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3133 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3134 | == RA)))) |
3135 | /* If the branch writes a register that the previous | |
3136 | instruction reads, we can not swap (we know that | |
3137 | branches only write to RD or to $31). */ | |
3138 | || (! mips_opts.mips16 | |
3139 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3140 | && insn_uses_reg (&history[0], |
bf12938e | 3141 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3142 | MIPS_GR_REG)) |
3143 | || (! mips_opts.mips16 | |
3144 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3145 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3146 | || (mips_opts.mips16 |
3147 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3148 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3149 | /* If one instruction sets a condition code and the |
3150 | other one uses a condition code, we can not swap. */ | |
3151 | || ((pinfo & INSN_READ_COND_CODE) | |
3152 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3153 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3154 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3155 | /* If the previous instruction uses the PC, we can not | |
3156 | swap. */ | |
3157 | || (mips_opts.mips16 | |
3158 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3159 | /* If the previous instruction had a fixup in mips16 |
3160 | mode, we can not swap. This normally means that the | |
3161 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3162 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3163 | /* If the previous instruction is a sync, sync.l, or |
3164 | sync.p, we can not swap. */ | |
f173e82e | 3165 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3166 | { |
29024861 DU |
3167 | if (mips_opts.mips16 |
3168 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3169 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3170 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3171 | { |
3172 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3173 | ip->insn_opcode |= 0x0080; | |
3174 | install_insn (ip); | |
3175 | insert_into_history (0, 1, ip); | |
3176 | } | |
3177 | else | |
3178 | { | |
3179 | /* We could do even better for unconditional branches to | |
3180 | portions of this object file; we could pick up the | |
3181 | instruction at the destination, put it in the delay | |
3182 | slot, and bump the destination address. */ | |
3183 | insert_into_history (0, 1, ip); | |
3184 | emit_nop (); | |
3185 | } | |
3186 | ||
dd22970f ILT |
3187 | if (mips_relax.sequence) |
3188 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3189 | } |
3190 | else | |
3191 | { | |
3192 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3193 | struct mips_cl_insn delay = history[0]; |
3194 | if (mips_opts.mips16) | |
252b5132 | 3195 | { |
b8ee1a6e DU |
3196 | know (delay.frag == ip->frag); |
3197 | move_insn (ip, delay.frag, delay.where); | |
3198 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3199 | } |
3200 | else if (relaxed_branch) | |
3201 | { | |
3202 | /* Add the delay slot instruction to the end of the | |
3203 | current frag and shrink the fixed part of the | |
3204 | original frag. If the branch occupies the tail of | |
3205 | the latter, move it backwards to cover the gap. */ | |
3206 | delay.frag->fr_fix -= 4; | |
3207 | if (delay.frag == ip->frag) | |
3208 | move_insn (ip, ip->frag, ip->where - 4); | |
3209 | add_fixed_insn (&delay); | |
252b5132 RH |
3210 | } |
3211 | else | |
3212 | { | |
1e915849 RS |
3213 | move_insn (&delay, ip->frag, ip->where); |
3214 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3215 | } |
1e915849 RS |
3216 | history[0] = *ip; |
3217 | delay.fixed_p = 1; | |
3218 | insert_into_history (0, 1, &delay); | |
252b5132 | 3219 | } |
252b5132 RH |
3220 | |
3221 | /* If that was an unconditional branch, forget the previous | |
3222 | insn information. */ | |
3223 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3224 | mips_no_prev_insn (); |
252b5132 RH |
3225 | } |
3226 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3227 | { | |
3228 | /* We don't yet optimize a branch likely. What we should do | |
3229 | is look at the target, copy the instruction found there | |
3230 | into the delay slot, and increment the branch to jump to | |
3231 | the next instruction. */ | |
1e915849 | 3232 | insert_into_history (0, 1, ip); |
252b5132 | 3233 | emit_nop (); |
252b5132 RH |
3234 | } |
3235 | else | |
1e915849 | 3236 | insert_into_history (0, 1, ip); |
252b5132 | 3237 | } |
1e915849 RS |
3238 | else |
3239 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3240 | |
3241 | /* We just output an insn, so the next one doesn't have a label. */ | |
3242 | mips_clear_insn_labels (); | |
252b5132 RH |
3243 | } |
3244 | ||
7d10b47d | 3245 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3246 | |
3247 | static void | |
7d10b47d | 3248 | mips_no_prev_insn (void) |
252b5132 | 3249 | { |
7d10b47d RS |
3250 | prev_nop_frag = NULL; |
3251 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3252 | mips_clear_insn_labels (); |
3253 | } | |
3254 | ||
7d10b47d RS |
3255 | /* This function must be called before we emit something other than |
3256 | instructions. It is like mips_no_prev_insn except that it inserts | |
3257 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3258 | |
7d10b47d RS |
3259 | void |
3260 | mips_emit_delays (void) | |
252b5132 RH |
3261 | { |
3262 | if (! mips_opts.noreorder) | |
3263 | { | |
71400594 | 3264 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3265 | if (nops > 0) |
3266 | { | |
7d10b47d RS |
3267 | while (nops-- > 0) |
3268 | add_fixed_insn (NOP_INSN); | |
3269 | mips_move_labels (); | |
3270 | } | |
3271 | } | |
3272 | mips_no_prev_insn (); | |
3273 | } | |
3274 | ||
3275 | /* Start a (possibly nested) noreorder block. */ | |
3276 | ||
3277 | static void | |
3278 | start_noreorder (void) | |
3279 | { | |
3280 | if (mips_opts.noreorder == 0) | |
3281 | { | |
3282 | unsigned int i; | |
3283 | int nops; | |
3284 | ||
3285 | /* None of the instructions before the .set noreorder can be moved. */ | |
3286 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3287 | history[i].fixed_p = 1; | |
3288 | ||
3289 | /* Insert any nops that might be needed between the .set noreorder | |
3290 | block and the previous instructions. We will later remove any | |
3291 | nops that turn out not to be needed. */ | |
3292 | nops = nops_for_insn (history, NULL); | |
3293 | if (nops > 0) | |
3294 | { | |
3295 | if (mips_optimize != 0) | |
252b5132 RH |
3296 | { |
3297 | /* Record the frag which holds the nop instructions, so | |
3298 | that we can remove them if we don't need them. */ | |
3299 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3300 | prev_nop_frag = frag_now; | |
3301 | prev_nop_frag_holds = nops; | |
3302 | prev_nop_frag_required = 0; | |
3303 | prev_nop_frag_since = 0; | |
3304 | } | |
3305 | ||
3306 | for (; nops > 0; --nops) | |
1e915849 | 3307 | add_fixed_insn (NOP_INSN); |
252b5132 | 3308 | |
7d10b47d RS |
3309 | /* Move on to a new frag, so that it is safe to simply |
3310 | decrease the size of prev_nop_frag. */ | |
3311 | frag_wane (frag_now); | |
3312 | frag_new (0); | |
404a8071 | 3313 | mips_move_labels (); |
252b5132 | 3314 | } |
7d10b47d RS |
3315 | mips16_mark_labels (); |
3316 | mips_clear_insn_labels (); | |
252b5132 | 3317 | } |
7d10b47d RS |
3318 | mips_opts.noreorder++; |
3319 | mips_any_noreorder = 1; | |
3320 | } | |
252b5132 | 3321 | |
7d10b47d | 3322 | /* End a nested noreorder block. */ |
252b5132 | 3323 | |
7d10b47d RS |
3324 | static void |
3325 | end_noreorder (void) | |
3326 | { | |
3327 | mips_opts.noreorder--; | |
3328 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3329 | { | |
3330 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3331 | handling nop insertion the .set reorder way. */ | |
3332 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3333 | * (mips_opts.mips16 ? 2 : 4)); | |
3334 | insert_into_history (prev_nop_frag_since, | |
3335 | prev_nop_frag_required, NOP_INSN); | |
3336 | prev_nop_frag = NULL; | |
3337 | } | |
252b5132 RH |
3338 | } |
3339 | ||
584892a6 RS |
3340 | /* Set up global variables for the start of a new macro. */ |
3341 | ||
3342 | static void | |
3343 | macro_start (void) | |
3344 | { | |
3345 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3346 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3347 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3348 | & (INSN_UNCOND_BRANCH_DELAY |
3349 | | INSN_COND_BRANCH_DELAY | |
3350 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3351 | } | |
3352 | ||
3353 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3354 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3355 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3356 | ||
3357 | static const char * | |
3358 | macro_warning (relax_substateT subtype) | |
3359 | { | |
3360 | if (subtype & RELAX_DELAY_SLOT) | |
3361 | return _("Macro instruction expanded into multiple instructions" | |
3362 | " in a branch delay slot"); | |
3363 | else if (subtype & RELAX_NOMACRO) | |
3364 | return _("Macro instruction expanded into multiple instructions"); | |
3365 | else | |
3366 | return 0; | |
3367 | } | |
3368 | ||
3369 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3370 | ||
3371 | static void | |
3372 | macro_end (void) | |
3373 | { | |
3374 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3375 | { | |
3376 | relax_substateT subtype; | |
3377 | ||
3378 | /* Set up the relaxation warning flags. */ | |
3379 | subtype = 0; | |
3380 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3381 | subtype |= RELAX_SECOND_LONGER; | |
3382 | if (mips_opts.warn_about_macros) | |
3383 | subtype |= RELAX_NOMACRO; | |
3384 | if (mips_macro_warning.delay_slot_p) | |
3385 | subtype |= RELAX_DELAY_SLOT; | |
3386 | ||
3387 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3388 | { | |
3389 | /* Either the macro has a single implementation or both | |
3390 | implementations are longer than 4 bytes. Emit the | |
3391 | warning now. */ | |
3392 | const char *msg = macro_warning (subtype); | |
3393 | if (msg != 0) | |
3394 | as_warn (msg); | |
3395 | } | |
3396 | else | |
3397 | { | |
3398 | /* One implementation might need a warning but the other | |
3399 | definitely doesn't. */ | |
3400 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3401 | } | |
3402 | } | |
3403 | } | |
3404 | ||
6e1304d8 RS |
3405 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3406 | The first argument in *ARGS will be either the code for a single | |
3407 | relocation or -1 followed by the three codes that make up a | |
3408 | composite relocation. */ | |
3409 | ||
3410 | static void | |
3411 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3412 | { | |
3413 | int i, next; | |
3414 | ||
3415 | next = va_arg (*args, int); | |
3416 | if (next >= 0) | |
3417 | r[0] = (bfd_reloc_code_real_type) next; | |
3418 | else | |
3419 | for (i = 0; i < 3; i++) | |
3420 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3421 | } | |
3422 | ||
252b5132 RH |
3423 | /* Build an instruction created by a macro expansion. This is passed |
3424 | a pointer to the count of instructions created so far, an | |
3425 | expression, the name of the instruction to build, an operand format | |
3426 | string, and corresponding arguments. */ | |
3427 | ||
252b5132 | 3428 | static void |
67c0d1eb | 3429 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3430 | { |
1e915849 | 3431 | const struct mips_opcode *mo; |
252b5132 | 3432 | struct mips_cl_insn insn; |
f6688943 | 3433 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3434 | va_list args; |
252b5132 | 3435 | |
252b5132 | 3436 | va_start (args, fmt); |
252b5132 | 3437 | |
252b5132 RH |
3438 | if (mips_opts.mips16) |
3439 | { | |
67c0d1eb | 3440 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3441 | va_end (args); |
3442 | return; | |
3443 | } | |
3444 | ||
f6688943 TS |
3445 | r[0] = BFD_RELOC_UNUSED; |
3446 | r[1] = BFD_RELOC_UNUSED; | |
3447 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3448 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3449 | assert (mo); | |
3450 | assert (strcmp (name, mo->name) == 0); | |
3451 | ||
8b082fb1 TS |
3452 | while (1) |
3453 | { | |
3454 | /* Search until we get a match for NAME. It is assumed here that | |
3455 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3456 | if (strcmp (fmt, mo->args) == 0 | |
3457 | && mo->pinfo != INSN_MACRO | |
037b32b9 | 3458 | && is_opcode_valid (mo, TRUE)) |
8b082fb1 TS |
3459 | break; |
3460 | ||
1e915849 RS |
3461 | ++mo; |
3462 | assert (mo->name); | |
3463 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3464 | } |
3465 | ||
1e915849 | 3466 | create_insn (&insn, mo); |
252b5132 RH |
3467 | for (;;) |
3468 | { | |
3469 | switch (*fmt++) | |
3470 | { | |
3471 | case '\0': | |
3472 | break; | |
3473 | ||
3474 | case ',': | |
3475 | case '(': | |
3476 | case ')': | |
3477 | continue; | |
3478 | ||
5f74bc13 CD |
3479 | case '+': |
3480 | switch (*fmt++) | |
3481 | { | |
3482 | case 'A': | |
3483 | case 'E': | |
bf12938e | 3484 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3485 | continue; |
3486 | ||
3487 | case 'B': | |
3488 | case 'F': | |
3489 | /* Note that in the macro case, these arguments are already | |
3490 | in MSB form. (When handling the instruction in the | |
3491 | non-macro case, these arguments are sizes from which | |
3492 | MSB values must be calculated.) */ | |
bf12938e | 3493 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3494 | continue; |
3495 | ||
3496 | case 'C': | |
3497 | case 'G': | |
3498 | case 'H': | |
3499 | /* Note that in the macro case, these arguments are already | |
3500 | in MSBD form. (When handling the instruction in the | |
3501 | non-macro case, these arguments are sizes from which | |
3502 | MSBD values must be calculated.) */ | |
bf12938e | 3503 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3504 | continue; |
3505 | ||
dd3cbb7e NC |
3506 | case 'Q': |
3507 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3508 | continue; | |
3509 | ||
5f74bc13 CD |
3510 | default: |
3511 | internalError (); | |
3512 | } | |
3513 | continue; | |
3514 | ||
8b082fb1 TS |
3515 | case '2': |
3516 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3517 | continue; | |
3518 | ||
252b5132 RH |
3519 | case 't': |
3520 | case 'w': | |
3521 | case 'E': | |
bf12938e | 3522 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3523 | continue; |
3524 | ||
3525 | case 'c': | |
bf12938e | 3526 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3527 | continue; |
3528 | ||
252b5132 RH |
3529 | case 'T': |
3530 | case 'W': | |
bf12938e | 3531 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3532 | continue; |
3533 | ||
3534 | case 'd': | |
3535 | case 'G': | |
af7ee8bf | 3536 | case 'K': |
bf12938e | 3537 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3538 | continue; |
3539 | ||
4372b673 NC |
3540 | case 'U': |
3541 | { | |
3542 | int tmp = va_arg (args, int); | |
3543 | ||
bf12938e RS |
3544 | INSERT_OPERAND (RT, insn, tmp); |
3545 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3546 | continue; |
4372b673 NC |
3547 | } |
3548 | ||
252b5132 RH |
3549 | case 'V': |
3550 | case 'S': | |
bf12938e | 3551 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3552 | continue; |
3553 | ||
3554 | case 'z': | |
3555 | continue; | |
3556 | ||
3557 | case '<': | |
bf12938e | 3558 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3559 | continue; |
3560 | ||
3561 | case 'D': | |
bf12938e | 3562 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3563 | continue; |
3564 | ||
3565 | case 'B': | |
bf12938e | 3566 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3567 | continue; |
3568 | ||
4372b673 | 3569 | case 'J': |
bf12938e | 3570 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3571 | continue; |
3572 | ||
252b5132 | 3573 | case 'q': |
bf12938e | 3574 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3575 | continue; |
3576 | ||
3577 | case 'b': | |
3578 | case 's': | |
3579 | case 'r': | |
3580 | case 'v': | |
bf12938e | 3581 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3582 | continue; |
3583 | ||
3584 | case 'i': | |
3585 | case 'j': | |
3586 | case 'o': | |
6e1304d8 | 3587 | macro_read_relocs (&args, r); |
cdf6fd85 | 3588 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3589 | || *r == BFD_RELOC_MIPS_LITERAL |
3590 | || *r == BFD_RELOC_MIPS_HIGHER | |
3591 | || *r == BFD_RELOC_HI16_S | |
3592 | || *r == BFD_RELOC_LO16 | |
3593 | || *r == BFD_RELOC_MIPS_GOT16 | |
3594 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3595 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3596 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3597 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3598 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3599 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3600 | continue; |
3601 | ||
3602 | case 'u': | |
6e1304d8 | 3603 | macro_read_relocs (&args, r); |
252b5132 RH |
3604 | assert (ep != NULL |
3605 | && (ep->X_op == O_constant | |
3606 | || (ep->X_op == O_symbol | |
f6688943 TS |
3607 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3608 | || *r == BFD_RELOC_HI16_S | |
3609 | || *r == BFD_RELOC_HI16 | |
3610 | || *r == BFD_RELOC_GPREL16 | |
3611 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3612 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3613 | continue; |
3614 | ||
3615 | case 'p': | |
3616 | assert (ep != NULL); | |
bad36eac | 3617 | |
252b5132 RH |
3618 | /* |
3619 | * This allows macro() to pass an immediate expression for | |
3620 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3621 | * |
3622 | * We don't allow branch relaxation for these branches, as | |
3623 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3624 | */ |
3625 | if (ep->X_op == O_constant) | |
3626 | { | |
bad36eac DJ |
3627 | if ((ep->X_add_number & 3) != 0) |
3628 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3629 | (unsigned long) ep->X_add_number); | |
3630 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3631 | as_bad (_("branch address range overflow (0x%lx)"), | |
3632 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3633 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3634 | ep = NULL; | |
3635 | } | |
3636 | else | |
0b25d3e6 | 3637 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3638 | continue; |
3639 | ||
3640 | case 'a': | |
3641 | assert (ep != NULL); | |
f6688943 | 3642 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3643 | continue; |
3644 | ||
3645 | case 'C': | |
a9e24354 | 3646 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3647 | continue; |
3648 | ||
d43b4baf | 3649 | case 'k': |
a9e24354 | 3650 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3651 | continue; |
3652 | ||
252b5132 RH |
3653 | default: |
3654 | internalError (); | |
3655 | } | |
3656 | break; | |
3657 | } | |
3658 | va_end (args); | |
f6688943 | 3659 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3660 | |
4d7206a2 | 3661 | append_insn (&insn, ep, r); |
252b5132 RH |
3662 | } |
3663 | ||
3664 | static void | |
67c0d1eb | 3665 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3666 | va_list args) |
252b5132 | 3667 | { |
1e915849 | 3668 | struct mips_opcode *mo; |
252b5132 | 3669 | struct mips_cl_insn insn; |
f6688943 TS |
3670 | bfd_reloc_code_real_type r[3] |
3671 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3672 | |
1e915849 RS |
3673 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3674 | assert (mo); | |
3675 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3676 | |
1e915849 | 3677 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3678 | { |
1e915849 RS |
3679 | ++mo; |
3680 | assert (mo->name); | |
3681 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3682 | } |
3683 | ||
1e915849 | 3684 | create_insn (&insn, mo); |
252b5132 RH |
3685 | for (;;) |
3686 | { | |
3687 | int c; | |
3688 | ||
3689 | c = *fmt++; | |
3690 | switch (c) | |
3691 | { | |
3692 | case '\0': | |
3693 | break; | |
3694 | ||
3695 | case ',': | |
3696 | case '(': | |
3697 | case ')': | |
3698 | continue; | |
3699 | ||
3700 | case 'y': | |
3701 | case 'w': | |
bf12938e | 3702 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3703 | continue; |
3704 | ||
3705 | case 'x': | |
3706 | case 'v': | |
bf12938e | 3707 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3708 | continue; |
3709 | ||
3710 | case 'z': | |
bf12938e | 3711 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3712 | continue; |
3713 | ||
3714 | case 'Z': | |
bf12938e | 3715 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3716 | continue; |
3717 | ||
3718 | case '0': | |
3719 | case 'S': | |
3720 | case 'P': | |
3721 | case 'R': | |
3722 | continue; | |
3723 | ||
3724 | case 'X': | |
bf12938e | 3725 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3726 | continue; |
3727 | ||
3728 | case 'Y': | |
3729 | { | |
3730 | int regno; | |
3731 | ||
3732 | regno = va_arg (args, int); | |
3733 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3734 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3735 | } |
3736 | continue; | |
3737 | ||
3738 | case '<': | |
3739 | case '>': | |
3740 | case '4': | |
3741 | case '5': | |
3742 | case 'H': | |
3743 | case 'W': | |
3744 | case 'D': | |
3745 | case 'j': | |
3746 | case '8': | |
3747 | case 'V': | |
3748 | case 'C': | |
3749 | case 'U': | |
3750 | case 'k': | |
3751 | case 'K': | |
3752 | case 'p': | |
3753 | case 'q': | |
3754 | { | |
3755 | assert (ep != NULL); | |
3756 | ||
3757 | if (ep->X_op != O_constant) | |
874e8986 | 3758 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3759 | else |
3760 | { | |
b34976b6 AM |
3761 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3762 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3763 | &insn.extend); |
252b5132 | 3764 | ep = NULL; |
f6688943 | 3765 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3766 | } |
3767 | } | |
3768 | continue; | |
3769 | ||
3770 | case '6': | |
bf12938e | 3771 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3772 | continue; |
3773 | } | |
3774 | ||
3775 | break; | |
3776 | } | |
3777 | ||
f6688943 | 3778 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3779 | |
4d7206a2 | 3780 | append_insn (&insn, ep, r); |
252b5132 RH |
3781 | } |
3782 | ||
2051e8c4 MR |
3783 | /* |
3784 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3785 | * higher bits unset. | |
3786 | */ | |
9f872bbe | 3787 | static void |
2051e8c4 MR |
3788 | normalize_constant_expr (expressionS *ex) |
3789 | { | |
9ee2a2d4 | 3790 | if (ex->X_op == O_constant |
2051e8c4 MR |
3791 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3792 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3793 | - 0x80000000); | |
3794 | } | |
3795 | ||
3796 | /* | |
3797 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3798 | * all higher bits unset. | |
3799 | */ | |
3800 | static void | |
3801 | normalize_address_expr (expressionS *ex) | |
3802 | { | |
3803 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3804 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3805 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3806 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3807 | - 0x80000000); | |
3808 | } | |
3809 | ||
438c16b8 TS |
3810 | /* |
3811 | * Generate a "jalr" instruction with a relocation hint to the called | |
3812 | * function. This occurs in NewABI PIC code. | |
3813 | */ | |
3814 | static void | |
67c0d1eb | 3815 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3816 | { |
685736be | 3817 | char *f = NULL; |
b34976b6 | 3818 | |
438c16b8 | 3819 | if (HAVE_NEWABI) |
f21f8242 | 3820 | { |
cc3d92a5 | 3821 | frag_grow (8); |
f21f8242 AO |
3822 | f = frag_more (0); |
3823 | } | |
67c0d1eb | 3824 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3825 | if (HAVE_NEWABI) |
f21f8242 | 3826 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3827 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3828 | } |
3829 | ||
252b5132 RH |
3830 | /* |
3831 | * Generate a "lui" instruction. | |
3832 | */ | |
3833 | static void | |
67c0d1eb | 3834 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3835 | { |
3836 | expressionS high_expr; | |
1e915849 | 3837 | const struct mips_opcode *mo; |
252b5132 | 3838 | struct mips_cl_insn insn; |
f6688943 TS |
3839 | bfd_reloc_code_real_type r[3] |
3840 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3841 | const char *name = "lui"; |
3842 | const char *fmt = "t,u"; | |
252b5132 RH |
3843 | |
3844 | assert (! mips_opts.mips16); | |
3845 | ||
4d7206a2 | 3846 | high_expr = *ep; |
252b5132 RH |
3847 | |
3848 | if (high_expr.X_op == O_constant) | |
3849 | { | |
54f4ddb3 | 3850 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3851 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3852 | >> 16) & 0xffff; | |
f6688943 | 3853 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3854 | } |
78e1bb40 | 3855 | else |
252b5132 RH |
3856 | { |
3857 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3858 | /* _gp_disp is a special case, used from s_cpload. |
3859 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3860 | assert (mips_pic == NO_PIC |
78e1bb40 | 3861 | || (! HAVE_NEWABI |
aa6975fb ILT |
3862 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3863 | || (! mips_in_shared | |
bbe506e8 TS |
3864 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3865 | "__gnu_local_gp") == 0)); | |
f6688943 | 3866 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3867 | } |
3868 | ||
1e915849 RS |
3869 | mo = hash_find (op_hash, name); |
3870 | assert (strcmp (name, mo->name) == 0); | |
3871 | assert (strcmp (fmt, mo->args) == 0); | |
3872 | create_insn (&insn, mo); | |
252b5132 | 3873 | |
bf12938e RS |
3874 | insn.insn_opcode = insn.insn_mo->match; |
3875 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3876 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3877 | { |
3878 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3879 | append_insn (&insn, NULL, r); |
252b5132 RH |
3880 | } |
3881 | else | |
4d7206a2 | 3882 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3883 | } |
3884 | ||
885add95 CD |
3885 | /* Generate a sequence of instructions to do a load or store from a constant |
3886 | offset off of a base register (breg) into/from a target register (treg), | |
3887 | using AT if necessary. */ | |
3888 | static void | |
67c0d1eb RS |
3889 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3890 | int treg, int breg, int dbl) | |
885add95 CD |
3891 | { |
3892 | assert (ep->X_op == O_constant); | |
3893 | ||
256ab948 | 3894 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3895 | if (!dbl) |
3896 | normalize_constant_expr (ep); | |
256ab948 | 3897 | |
67c1ffbe | 3898 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3899 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3900 | as_warn (_("operand overflow")); |
3901 | ||
3902 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3903 | { | |
3904 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3905 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3906 | } |
3907 | else | |
3908 | { | |
3909 | /* 32-bit offset, need multiple instructions and AT, like: | |
3910 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3911 | addu $tempreg,$tempreg,$breg | |
3912 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3913 | to handle the complete offset. */ | |
67c0d1eb RS |
3914 | macro_build_lui (ep, AT); |
3915 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3916 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 3917 | |
741fe287 | 3918 | if (!mips_opts.at) |
8fc2e39e | 3919 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3920 | } |
3921 | } | |
3922 | ||
252b5132 RH |
3923 | /* set_at() |
3924 | * Generates code to set the $at register to true (one) | |
3925 | * if reg is less than the immediate expression. | |
3926 | */ | |
3927 | static void | |
67c0d1eb | 3928 | set_at (int reg, int unsignedp) |
252b5132 RH |
3929 | { |
3930 | if (imm_expr.X_op == O_constant | |
3931 | && imm_expr.X_add_number >= -0x8000 | |
3932 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3933 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3934 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3935 | else |
3936 | { | |
67c0d1eb RS |
3937 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3938 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3939 | } |
3940 | } | |
3941 | ||
3942 | /* Warn if an expression is not a constant. */ | |
3943 | ||
3944 | static void | |
17a2f251 | 3945 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3946 | { |
3947 | if (ex->X_op == O_big) | |
3948 | as_bad (_("unsupported large constant")); | |
3949 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3950 | as_bad (_("Instruction %s requires absolute expression"), |
3951 | ip->insn_mo->name); | |
13757d0c | 3952 | |
9ee2a2d4 MR |
3953 | if (HAVE_32BIT_GPRS) |
3954 | normalize_constant_expr (ex); | |
252b5132 RH |
3955 | } |
3956 | ||
3957 | /* Count the leading zeroes by performing a binary chop. This is a | |
3958 | bulky bit of source, but performance is a LOT better for the | |
3959 | majority of values than a simple loop to count the bits: | |
3960 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3961 | if ((v) & (1 << (31 - lcnt))) | |
3962 | break; | |
3963 | However it is not code size friendly, and the gain will drop a bit | |
3964 | on certain cached systems. | |
3965 | */ | |
3966 | #define COUNT_TOP_ZEROES(v) \ | |
3967 | (((v) & ~0xffff) == 0 \ | |
3968 | ? ((v) & ~0xff) == 0 \ | |
3969 | ? ((v) & ~0xf) == 0 \ | |
3970 | ? ((v) & ~0x3) == 0 \ | |
3971 | ? ((v) & ~0x1) == 0 \ | |
3972 | ? !(v) \ | |
3973 | ? 32 \ | |
3974 | : 31 \ | |
3975 | : 30 \ | |
3976 | : ((v) & ~0x7) == 0 \ | |
3977 | ? 29 \ | |
3978 | : 28 \ | |
3979 | : ((v) & ~0x3f) == 0 \ | |
3980 | ? ((v) & ~0x1f) == 0 \ | |
3981 | ? 27 \ | |
3982 | : 26 \ | |
3983 | : ((v) & ~0x7f) == 0 \ | |
3984 | ? 25 \ | |
3985 | : 24 \ | |
3986 | : ((v) & ~0xfff) == 0 \ | |
3987 | ? ((v) & ~0x3ff) == 0 \ | |
3988 | ? ((v) & ~0x1ff) == 0 \ | |
3989 | ? 23 \ | |
3990 | : 22 \ | |
3991 | : ((v) & ~0x7ff) == 0 \ | |
3992 | ? 21 \ | |
3993 | : 20 \ | |
3994 | : ((v) & ~0x3fff) == 0 \ | |
3995 | ? ((v) & ~0x1fff) == 0 \ | |
3996 | ? 19 \ | |
3997 | : 18 \ | |
3998 | : ((v) & ~0x7fff) == 0 \ | |
3999 | ? 17 \ | |
4000 | : 16 \ | |
4001 | : ((v) & ~0xffffff) == 0 \ | |
4002 | ? ((v) & ~0xfffff) == 0 \ | |
4003 | ? ((v) & ~0x3ffff) == 0 \ | |
4004 | ? ((v) & ~0x1ffff) == 0 \ | |
4005 | ? 15 \ | |
4006 | : 14 \ | |
4007 | : ((v) & ~0x7ffff) == 0 \ | |
4008 | ? 13 \ | |
4009 | : 12 \ | |
4010 | : ((v) & ~0x3fffff) == 0 \ | |
4011 | ? ((v) & ~0x1fffff) == 0 \ | |
4012 | ? 11 \ | |
4013 | : 10 \ | |
4014 | : ((v) & ~0x7fffff) == 0 \ | |
4015 | ? 9 \ | |
4016 | : 8 \ | |
4017 | : ((v) & ~0xfffffff) == 0 \ | |
4018 | ? ((v) & ~0x3ffffff) == 0 \ | |
4019 | ? ((v) & ~0x1ffffff) == 0 \ | |
4020 | ? 7 \ | |
4021 | : 6 \ | |
4022 | : ((v) & ~0x7ffffff) == 0 \ | |
4023 | ? 5 \ | |
4024 | : 4 \ | |
4025 | : ((v) & ~0x3fffffff) == 0 \ | |
4026 | ? ((v) & ~0x1fffffff) == 0 \ | |
4027 | ? 3 \ | |
4028 | : 2 \ | |
4029 | : ((v) & ~0x7fffffff) == 0 \ | |
4030 | ? 1 \ | |
4031 | : 0) | |
4032 | ||
4033 | /* load_register() | |
67c1ffbe | 4034 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4035 | * an absolute expression value into a register. |
4036 | */ | |
4037 | static void | |
67c0d1eb | 4038 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4039 | { |
4040 | int freg; | |
4041 | expressionS hi32, lo32; | |
4042 | ||
4043 | if (ep->X_op != O_big) | |
4044 | { | |
4045 | assert (ep->X_op == O_constant); | |
256ab948 TS |
4046 | |
4047 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4048 | if (!dbl) |
4049 | normalize_constant_expr (ep); | |
256ab948 TS |
4050 | |
4051 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4052 | { |
4053 | /* We can handle 16 bit signed values with an addiu to | |
4054 | $zero. No need to ever use daddiu here, since $zero and | |
4055 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4056 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4057 | return; |
4058 | } | |
4059 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4060 | { | |
4061 | /* We can handle 16 bit unsigned values with an ori to | |
4062 | $zero. */ | |
67c0d1eb | 4063 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4064 | return; |
4065 | } | |
256ab948 | 4066 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4067 | { |
4068 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4069 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4070 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4071 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4072 | return; |
4073 | } | |
4074 | } | |
4075 | ||
4076 | /* The value is larger than 32 bits. */ | |
4077 | ||
2051e8c4 | 4078 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4079 | { |
55e08f71 NC |
4080 | char value[32]; |
4081 | ||
4082 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4083 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4084 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4085 | return; |
4086 | } | |
4087 | ||
4088 | if (ep->X_op != O_big) | |
4089 | { | |
4090 | hi32 = *ep; | |
4091 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4092 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4093 | hi32.X_add_number &= 0xffffffff; | |
4094 | lo32 = *ep; | |
4095 | lo32.X_add_number &= 0xffffffff; | |
4096 | } | |
4097 | else | |
4098 | { | |
4099 | assert (ep->X_add_number > 2); | |
4100 | if (ep->X_add_number == 3) | |
4101 | generic_bignum[3] = 0; | |
4102 | else if (ep->X_add_number > 4) | |
4103 | as_bad (_("Number larger than 64 bits")); | |
4104 | lo32.X_op = O_constant; | |
4105 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4106 | hi32.X_op = O_constant; | |
4107 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4108 | } | |
4109 | ||
4110 | if (hi32.X_add_number == 0) | |
4111 | freg = 0; | |
4112 | else | |
4113 | { | |
4114 | int shift, bit; | |
4115 | unsigned long hi, lo; | |
4116 | ||
956cd1d6 | 4117 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4118 | { |
4119 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4120 | { | |
67c0d1eb | 4121 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4122 | return; |
4123 | } | |
4124 | if (lo32.X_add_number & 0x80000000) | |
4125 | { | |
67c0d1eb | 4126 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4127 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4128 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4129 | return; |
4130 | } | |
4131 | } | |
252b5132 RH |
4132 | |
4133 | /* Check for 16bit shifted constant. We know that hi32 is | |
4134 | non-zero, so start the mask on the first bit of the hi32 | |
4135 | value. */ | |
4136 | shift = 17; | |
4137 | do | |
beae10d5 KH |
4138 | { |
4139 | unsigned long himask, lomask; | |
4140 | ||
4141 | if (shift < 32) | |
4142 | { | |
4143 | himask = 0xffff >> (32 - shift); | |
4144 | lomask = (0xffff << shift) & 0xffffffff; | |
4145 | } | |
4146 | else | |
4147 | { | |
4148 | himask = 0xffff << (shift - 32); | |
4149 | lomask = 0; | |
4150 | } | |
4151 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4152 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4153 | { | |
4154 | expressionS tmp; | |
4155 | ||
4156 | tmp.X_op = O_constant; | |
4157 | if (shift < 32) | |
4158 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4159 | | (lo32.X_add_number >> shift)); | |
4160 | else | |
4161 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4162 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4163 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4164 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4165 | return; |
4166 | } | |
f9419b05 | 4167 | ++shift; |
beae10d5 KH |
4168 | } |
4169 | while (shift <= (64 - 16)); | |
252b5132 RH |
4170 | |
4171 | /* Find the bit number of the lowest one bit, and store the | |
4172 | shifted value in hi/lo. */ | |
4173 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4174 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4175 | if (lo != 0) | |
4176 | { | |
4177 | bit = 0; | |
4178 | while ((lo & 1) == 0) | |
4179 | { | |
4180 | lo >>= 1; | |
4181 | ++bit; | |
4182 | } | |
4183 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4184 | hi >>= bit; | |
4185 | } | |
4186 | else | |
4187 | { | |
4188 | bit = 32; | |
4189 | while ((hi & 1) == 0) | |
4190 | { | |
4191 | hi >>= 1; | |
4192 | ++bit; | |
4193 | } | |
4194 | lo = hi; | |
4195 | hi = 0; | |
4196 | } | |
4197 | ||
4198 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4199 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4200 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4201 | { |
4202 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4203 | if (shift != 0) |
beae10d5 | 4204 | { |
252b5132 RH |
4205 | expressionS tmp; |
4206 | ||
4207 | /* This instruction will set the register to be all | |
4208 | ones. */ | |
beae10d5 KH |
4209 | tmp.X_op = O_constant; |
4210 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4211 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4212 | if (bit != 0) |
4213 | { | |
4214 | bit += shift; | |
67c0d1eb RS |
4215 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4216 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4217 | } |
67c0d1eb RS |
4218 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4219 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4220 | return; |
4221 | } | |
4222 | } | |
252b5132 RH |
4223 | |
4224 | /* Sign extend hi32 before calling load_register, because we can | |
4225 | generally get better code when we load a sign extended value. */ | |
4226 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4227 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4228 | load_register (reg, &hi32, 0); |
252b5132 RH |
4229 | freg = reg; |
4230 | } | |
4231 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4232 | { | |
4233 | if (freg != 0) | |
4234 | { | |
67c0d1eb | 4235 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4236 | freg = reg; |
4237 | } | |
4238 | } | |
4239 | else | |
4240 | { | |
4241 | expressionS mid16; | |
4242 | ||
956cd1d6 | 4243 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4244 | { |
67c0d1eb RS |
4245 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4246 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4247 | return; |
4248 | } | |
252b5132 RH |
4249 | |
4250 | if (freg != 0) | |
4251 | { | |
67c0d1eb | 4252 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4253 | freg = reg; |
4254 | } | |
4255 | mid16 = lo32; | |
4256 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4257 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4258 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4259 | freg = reg; |
4260 | } | |
4261 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4262 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4263 | } |
4264 | ||
269137b2 TS |
4265 | static inline void |
4266 | load_delay_nop (void) | |
4267 | { | |
4268 | if (!gpr_interlocks) | |
4269 | macro_build (NULL, "nop", ""); | |
4270 | } | |
4271 | ||
252b5132 RH |
4272 | /* Load an address into a register. */ |
4273 | ||
4274 | static void | |
67c0d1eb | 4275 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4276 | { |
252b5132 RH |
4277 | if (ep->X_op != O_constant |
4278 | && ep->X_op != O_symbol) | |
4279 | { | |
4280 | as_bad (_("expression too complex")); | |
4281 | ep->X_op = O_constant; | |
4282 | } | |
4283 | ||
4284 | if (ep->X_op == O_constant) | |
4285 | { | |
67c0d1eb | 4286 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4287 | return; |
4288 | } | |
4289 | ||
4290 | if (mips_pic == NO_PIC) | |
4291 | { | |
4292 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4293 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4294 | Otherwise we want |
4295 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4296 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4297 | If we have an addend, we always use the latter form. |
76b3015f | 4298 | |
d6bc6245 TS |
4299 | With 64bit address space and a usable $at we want |
4300 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4301 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4302 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4303 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4304 | dsll32 $reg,0 | |
3a482fd5 | 4305 | daddu $reg,$reg,$at |
76b3015f | 4306 | |
c03099e6 | 4307 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4308 | on superscalar processors. |
4309 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4310 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4311 | dsll $reg,16 | |
4312 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4313 | dsll $reg,16 | |
4314 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4315 | |
4316 | For GP relative symbols in 64bit address space we can use | |
4317 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4318 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4319 | { |
6caf9ef4 TS |
4320 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4321 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4322 | { | |
4323 | relax_start (ep->X_add_symbol); | |
4324 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4325 | mips_gp_register, BFD_RELOC_GPREL16); | |
4326 | relax_switch (); | |
4327 | } | |
d6bc6245 | 4328 | |
741fe287 | 4329 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4330 | { |
67c0d1eb RS |
4331 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4332 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4333 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4334 | BFD_RELOC_MIPS_HIGHER); | |
4335 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4336 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4337 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4338 | *used_at = 1; |
4339 | } | |
4340 | else | |
4341 | { | |
67c0d1eb RS |
4342 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4343 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4344 | BFD_RELOC_MIPS_HIGHER); | |
4345 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4346 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4347 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4348 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4349 | } |
6caf9ef4 TS |
4350 | |
4351 | if (mips_relax.sequence) | |
4352 | relax_end (); | |
d6bc6245 | 4353 | } |
252b5132 RH |
4354 | else |
4355 | { | |
d6bc6245 | 4356 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4357 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4358 | { |
4d7206a2 | 4359 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4360 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4361 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4362 | relax_switch (); |
d6bc6245 | 4363 | } |
67c0d1eb RS |
4364 | macro_build_lui (ep, reg); |
4365 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4366 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4367 | if (mips_relax.sequence) |
4368 | relax_end (); | |
d6bc6245 | 4369 | } |
252b5132 | 4370 | } |
0a44bf69 | 4371 | else if (!mips_big_got) |
252b5132 RH |
4372 | { |
4373 | expressionS ex; | |
4374 | ||
4375 | /* If this is a reference to an external symbol, we want | |
4376 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4377 | Otherwise we want | |
4378 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4379 | nop | |
4380 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4381 | If there is a constant, it must be added in after. |
4382 | ||
ed6fb7bd | 4383 | If we have NewABI, we want |
f5040a92 AO |
4384 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4385 | unless we're referencing a global symbol with a non-zero | |
4386 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4387 | if (HAVE_NEWABI) |
4388 | { | |
f5040a92 AO |
4389 | if (ep->X_add_number) |
4390 | { | |
4d7206a2 | 4391 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4392 | ep->X_add_number = 0; |
4d7206a2 | 4393 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4394 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4395 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4396 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4397 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4398 | ex.X_op = O_constant; | |
67c0d1eb | 4399 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4400 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4401 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4402 | relax_switch (); |
f5040a92 | 4403 | } |
67c0d1eb | 4404 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4405 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4406 | if (mips_relax.sequence) |
4407 | relax_end (); | |
ed6fb7bd SC |
4408 | } |
4409 | else | |
4410 | { | |
f5040a92 AO |
4411 | ex.X_add_number = ep->X_add_number; |
4412 | ep->X_add_number = 0; | |
67c0d1eb RS |
4413 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4414 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4415 | load_delay_nop (); |
4d7206a2 RS |
4416 | relax_start (ep->X_add_symbol); |
4417 | relax_switch (); | |
67c0d1eb | 4418 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4419 | BFD_RELOC_LO16); |
4d7206a2 | 4420 | relax_end (); |
ed6fb7bd | 4421 | |
f5040a92 AO |
4422 | if (ex.X_add_number != 0) |
4423 | { | |
4424 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4425 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4426 | ex.X_op = O_constant; | |
67c0d1eb | 4427 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4428 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4429 | } |
252b5132 RH |
4430 | } |
4431 | } | |
0a44bf69 | 4432 | else if (mips_big_got) |
252b5132 RH |
4433 | { |
4434 | expressionS ex; | |
252b5132 RH |
4435 | |
4436 | /* This is the large GOT case. If this is a reference to an | |
4437 | external symbol, we want | |
4438 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4439 | addu $reg,$reg,$gp | |
4440 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4441 | |
4442 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4443 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4444 | nop | |
4445 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4446 | If there is a constant, it must be added in after. |
f5040a92 AO |
4447 | |
4448 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4449 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4450 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4451 | */ |
438c16b8 TS |
4452 | if (HAVE_NEWABI) |
4453 | { | |
4d7206a2 | 4454 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4455 | ep->X_add_number = 0; |
4d7206a2 | 4456 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4457 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4458 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4459 | reg, reg, mips_gp_register); | |
4460 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4461 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4462 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4463 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4464 | else if (ex.X_add_number) | |
4465 | { | |
4466 | ex.X_op = O_constant; | |
67c0d1eb RS |
4467 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4468 | BFD_RELOC_LO16); | |
f5040a92 AO |
4469 | } |
4470 | ||
4471 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4472 | relax_switch (); |
67c0d1eb | 4473 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4474 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4475 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4476 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4477 | relax_end (); |
438c16b8 | 4478 | } |
252b5132 | 4479 | else |
438c16b8 | 4480 | { |
f5040a92 AO |
4481 | ex.X_add_number = ep->X_add_number; |
4482 | ep->X_add_number = 0; | |
4d7206a2 | 4483 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4484 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4485 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4486 | reg, reg, mips_gp_register); | |
4487 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4488 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4489 | relax_switch (); |
4490 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4491 | { |
4492 | /* We need a nop before loading from $gp. This special | |
4493 | check is required because the lui which starts the main | |
4494 | instruction stream does not refer to $gp, and so will not | |
4495 | insert the nop which may be required. */ | |
67c0d1eb | 4496 | macro_build (NULL, "nop", ""); |
438c16b8 | 4497 | } |
67c0d1eb | 4498 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4499 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4500 | load_delay_nop (); |
67c0d1eb | 4501 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4502 | BFD_RELOC_LO16); |
4d7206a2 | 4503 | relax_end (); |
438c16b8 | 4504 | |
f5040a92 AO |
4505 | if (ex.X_add_number != 0) |
4506 | { | |
4507 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4508 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4509 | ex.X_op = O_constant; | |
67c0d1eb RS |
4510 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4511 | BFD_RELOC_LO16); | |
f5040a92 | 4512 | } |
252b5132 RH |
4513 | } |
4514 | } | |
252b5132 RH |
4515 | else |
4516 | abort (); | |
8fc2e39e | 4517 | |
741fe287 | 4518 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4519 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4520 | } |
4521 | ||
ea1fb5dc RS |
4522 | /* Move the contents of register SOURCE into register DEST. */ |
4523 | ||
4524 | static void | |
67c0d1eb | 4525 | move_register (int dest, int source) |
ea1fb5dc | 4526 | { |
67c0d1eb RS |
4527 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4528 | dest, source, 0); | |
ea1fb5dc RS |
4529 | } |
4530 | ||
4d7206a2 | 4531 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4532 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4533 | The two alternatives are: | |
4d7206a2 RS |
4534 | |
4535 | Global symbol Local sybmol | |
4536 | ------------- ------------ | |
4537 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4538 | ... ... | |
4539 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4540 | ||
4541 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4542 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4543 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4544 | |
4545 | static void | |
67c0d1eb | 4546 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4547 | { |
4548 | expressionS global; | |
4549 | ||
4550 | global = *local; | |
4551 | global.X_add_number = 0; | |
4552 | ||
4553 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4554 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4555 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4556 | relax_switch (); |
67c0d1eb RS |
4557 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4558 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4559 | relax_end (); |
4560 | } | |
4561 | ||
4562 | static void | |
67c0d1eb | 4563 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4564 | { |
4565 | expressionS global; | |
4566 | ||
4567 | global.X_op = O_constant; | |
4568 | global.X_op_symbol = NULL; | |
4569 | global.X_add_symbol = NULL; | |
4570 | global.X_add_number = local->X_add_number; | |
4571 | ||
4572 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4573 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4574 | dest, dest, BFD_RELOC_LO16); |
4575 | relax_switch (); | |
67c0d1eb | 4576 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4577 | relax_end (); |
4578 | } | |
4579 | ||
f6a22291 MR |
4580 | static void |
4581 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4582 | { | |
4583 | expressionS global; | |
4584 | int hold_mips_optimize; | |
4585 | ||
4586 | global.X_op = O_constant; | |
4587 | global.X_op_symbol = NULL; | |
4588 | global.X_add_symbol = NULL; | |
4589 | global.X_add_number = local->X_add_number; | |
4590 | ||
4591 | relax_start (local->X_add_symbol); | |
4592 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4593 | relax_switch (); | |
4594 | /* Set mips_optimize around the lui instruction to avoid | |
4595 | inserting an unnecessary nop after the lw. */ | |
4596 | hold_mips_optimize = mips_optimize; | |
4597 | mips_optimize = 2; | |
4598 | macro_build_lui (&global, tmp); | |
4599 | mips_optimize = hold_mips_optimize; | |
4600 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4601 | relax_end (); | |
4602 | ||
4603 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4604 | } | |
4605 | ||
252b5132 RH |
4606 | /* |
4607 | * Build macros | |
4608 | * This routine implements the seemingly endless macro or synthesized | |
4609 | * instructions and addressing modes in the mips assembly language. Many | |
4610 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4611 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4612 | * this verbose method. Others are not simple macros but are more like |
4613 | * optimizing code generation. | |
4614 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4615 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4616 | * The ensuing load upper instructions are ommited. This implies some kind |
4617 | * of global optimization. We currently only optimize within a single macro. | |
4618 | * For many of the load and store macros if the address is specified as a | |
4619 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4620 | * first load register 'at' with zero and use it as the base register. The | |
4621 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4622 | * we're missing. | |
4623 | */ | |
4624 | static void | |
17a2f251 | 4625 | macro (struct mips_cl_insn *ip) |
252b5132 | 4626 | { |
741fe287 MR |
4627 | unsigned int treg, sreg, dreg, breg; |
4628 | unsigned int tempreg; | |
252b5132 | 4629 | int mask; |
43841e91 | 4630 | int used_at = 0; |
252b5132 RH |
4631 | expressionS expr1; |
4632 | const char *s; | |
4633 | const char *s2; | |
4634 | const char *fmt; | |
4635 | int likely = 0; | |
4636 | int dbl = 0; | |
4637 | int coproc = 0; | |
4638 | int lr = 0; | |
4639 | int imm = 0; | |
1abe91b1 | 4640 | int call = 0; |
252b5132 | 4641 | int off; |
67c0d1eb | 4642 | offsetT maxnum; |
252b5132 | 4643 | bfd_reloc_code_real_type r; |
252b5132 RH |
4644 | int hold_mips_optimize; |
4645 | ||
4646 | assert (! mips_opts.mips16); | |
4647 | ||
4648 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4649 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4650 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4651 | mask = ip->insn_mo->mask; | |
4652 | ||
4653 | expr1.X_op = O_constant; | |
4654 | expr1.X_op_symbol = NULL; | |
4655 | expr1.X_add_symbol = NULL; | |
4656 | expr1.X_add_number = 1; | |
4657 | ||
4658 | switch (mask) | |
4659 | { | |
4660 | case M_DABS: | |
4661 | dbl = 1; | |
4662 | case M_ABS: | |
4663 | /* bgez $a0,.+12 | |
4664 | move v0,$a0 | |
4665 | sub v0,$zero,$a0 | |
4666 | */ | |
4667 | ||
7d10b47d | 4668 | start_noreorder (); |
252b5132 RH |
4669 | |
4670 | expr1.X_add_number = 8; | |
67c0d1eb | 4671 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4672 | if (dreg == sreg) |
67c0d1eb | 4673 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4674 | else |
67c0d1eb RS |
4675 | move_register (dreg, sreg); |
4676 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4677 | |
7d10b47d | 4678 | end_noreorder (); |
8fc2e39e | 4679 | break; |
252b5132 RH |
4680 | |
4681 | case M_ADD_I: | |
4682 | s = "addi"; | |
4683 | s2 = "add"; | |
4684 | goto do_addi; | |
4685 | case M_ADDU_I: | |
4686 | s = "addiu"; | |
4687 | s2 = "addu"; | |
4688 | goto do_addi; | |
4689 | case M_DADD_I: | |
4690 | dbl = 1; | |
4691 | s = "daddi"; | |
4692 | s2 = "dadd"; | |
4693 | goto do_addi; | |
4694 | case M_DADDU_I: | |
4695 | dbl = 1; | |
4696 | s = "daddiu"; | |
4697 | s2 = "daddu"; | |
4698 | do_addi: | |
4699 | if (imm_expr.X_op == O_constant | |
4700 | && imm_expr.X_add_number >= -0x8000 | |
4701 | && imm_expr.X_add_number < 0x8000) | |
4702 | { | |
67c0d1eb | 4703 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4704 | break; |
252b5132 | 4705 | } |
8fc2e39e | 4706 | used_at = 1; |
67c0d1eb RS |
4707 | load_register (AT, &imm_expr, dbl); |
4708 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4709 | break; |
4710 | ||
4711 | case M_AND_I: | |
4712 | s = "andi"; | |
4713 | s2 = "and"; | |
4714 | goto do_bit; | |
4715 | case M_OR_I: | |
4716 | s = "ori"; | |
4717 | s2 = "or"; | |
4718 | goto do_bit; | |
4719 | case M_NOR_I: | |
4720 | s = ""; | |
4721 | s2 = "nor"; | |
4722 | goto do_bit; | |
4723 | case M_XOR_I: | |
4724 | s = "xori"; | |
4725 | s2 = "xor"; | |
4726 | do_bit: | |
4727 | if (imm_expr.X_op == O_constant | |
4728 | && imm_expr.X_add_number >= 0 | |
4729 | && imm_expr.X_add_number < 0x10000) | |
4730 | { | |
4731 | if (mask != M_NOR_I) | |
67c0d1eb | 4732 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4733 | else |
4734 | { | |
67c0d1eb RS |
4735 | macro_build (&imm_expr, "ori", "t,r,i", |
4736 | treg, sreg, BFD_RELOC_LO16); | |
4737 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4738 | } |
8fc2e39e | 4739 | break; |
252b5132 RH |
4740 | } |
4741 | ||
8fc2e39e | 4742 | used_at = 1; |
67c0d1eb RS |
4743 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4744 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4745 | break; |
4746 | ||
8b082fb1 TS |
4747 | case M_BALIGN: |
4748 | switch (imm_expr.X_add_number) | |
4749 | { | |
4750 | case 0: | |
4751 | macro_build (NULL, "nop", ""); | |
4752 | break; | |
4753 | case 2: | |
4754 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4755 | break; | |
4756 | default: | |
4757 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4758 | (int)imm_expr.X_add_number); | |
4759 | break; | |
4760 | } | |
4761 | break; | |
4762 | ||
252b5132 RH |
4763 | case M_BEQ_I: |
4764 | s = "beq"; | |
4765 | goto beq_i; | |
4766 | case M_BEQL_I: | |
4767 | s = "beql"; | |
4768 | likely = 1; | |
4769 | goto beq_i; | |
4770 | case M_BNE_I: | |
4771 | s = "bne"; | |
4772 | goto beq_i; | |
4773 | case M_BNEL_I: | |
4774 | s = "bnel"; | |
4775 | likely = 1; | |
4776 | beq_i: | |
4777 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4778 | { | |
67c0d1eb | 4779 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4780 | break; |
252b5132 | 4781 | } |
8fc2e39e | 4782 | used_at = 1; |
67c0d1eb RS |
4783 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4784 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4785 | break; |
4786 | ||
4787 | case M_BGEL: | |
4788 | likely = 1; | |
4789 | case M_BGE: | |
4790 | if (treg == 0) | |
4791 | { | |
67c0d1eb | 4792 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4793 | break; |
252b5132 RH |
4794 | } |
4795 | if (sreg == 0) | |
4796 | { | |
67c0d1eb | 4797 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4798 | break; |
252b5132 | 4799 | } |
8fc2e39e | 4800 | used_at = 1; |
67c0d1eb RS |
4801 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4802 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4803 | break; |
4804 | ||
4805 | case M_BGTL_I: | |
4806 | likely = 1; | |
4807 | case M_BGT_I: | |
4808 | /* check for > max integer */ | |
4809 | maxnum = 0x7fffffff; | |
ca4e0257 | 4810 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4811 | { |
4812 | maxnum <<= 16; | |
4813 | maxnum |= 0xffff; | |
4814 | maxnum <<= 16; | |
4815 | maxnum |= 0xffff; | |
4816 | } | |
4817 | if (imm_expr.X_op == O_constant | |
4818 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4819 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4820 | { |
4821 | do_false: | |
4822 | /* result is always false */ | |
4823 | if (! likely) | |
67c0d1eb | 4824 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4825 | else |
67c0d1eb | 4826 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4827 | break; |
252b5132 RH |
4828 | } |
4829 | if (imm_expr.X_op != O_constant) | |
4830 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4831 | ++imm_expr.X_add_number; |
252b5132 RH |
4832 | /* FALLTHROUGH */ |
4833 | case M_BGE_I: | |
4834 | case M_BGEL_I: | |
4835 | if (mask == M_BGEL_I) | |
4836 | likely = 1; | |
4837 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4838 | { | |
67c0d1eb | 4839 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4840 | break; |
252b5132 RH |
4841 | } |
4842 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4843 | { | |
67c0d1eb | 4844 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4845 | break; |
252b5132 RH |
4846 | } |
4847 | maxnum = 0x7fffffff; | |
ca4e0257 | 4848 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4849 | { |
4850 | maxnum <<= 16; | |
4851 | maxnum |= 0xffff; | |
4852 | maxnum <<= 16; | |
4853 | maxnum |= 0xffff; | |
4854 | } | |
4855 | maxnum = - maxnum - 1; | |
4856 | if (imm_expr.X_op == O_constant | |
4857 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4858 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4859 | { |
4860 | do_true: | |
4861 | /* result is always true */ | |
4862 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4863 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4864 | break; |
252b5132 | 4865 | } |
8fc2e39e | 4866 | used_at = 1; |
67c0d1eb RS |
4867 | set_at (sreg, 0); |
4868 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4869 | break; |
4870 | ||
4871 | case M_BGEUL: | |
4872 | likely = 1; | |
4873 | case M_BGEU: | |
4874 | if (treg == 0) | |
4875 | goto do_true; | |
4876 | if (sreg == 0) | |
4877 | { | |
67c0d1eb | 4878 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4879 | "s,t,p", 0, treg); |
8fc2e39e | 4880 | break; |
252b5132 | 4881 | } |
8fc2e39e | 4882 | used_at = 1; |
67c0d1eb RS |
4883 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4884 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4885 | break; |
4886 | ||
4887 | case M_BGTUL_I: | |
4888 | likely = 1; | |
4889 | case M_BGTU_I: | |
4890 | if (sreg == 0 | |
ca4e0257 | 4891 | || (HAVE_32BIT_GPRS |
252b5132 | 4892 | && imm_expr.X_op == O_constant |
956cd1d6 | 4893 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4894 | goto do_false; |
4895 | if (imm_expr.X_op != O_constant) | |
4896 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4897 | ++imm_expr.X_add_number; |
252b5132 RH |
4898 | /* FALLTHROUGH */ |
4899 | case M_BGEU_I: | |
4900 | case M_BGEUL_I: | |
4901 | if (mask == M_BGEUL_I) | |
4902 | likely = 1; | |
4903 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4904 | goto do_true; | |
4905 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4906 | { | |
67c0d1eb | 4907 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4908 | "s,t,p", sreg, 0); |
8fc2e39e | 4909 | break; |
252b5132 | 4910 | } |
8fc2e39e | 4911 | used_at = 1; |
67c0d1eb RS |
4912 | set_at (sreg, 1); |
4913 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4914 | break; |
4915 | ||
4916 | case M_BGTL: | |
4917 | likely = 1; | |
4918 | case M_BGT: | |
4919 | if (treg == 0) | |
4920 | { | |
67c0d1eb | 4921 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4922 | break; |
252b5132 RH |
4923 | } |
4924 | if (sreg == 0) | |
4925 | { | |
67c0d1eb | 4926 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4927 | break; |
252b5132 | 4928 | } |
8fc2e39e | 4929 | used_at = 1; |
67c0d1eb RS |
4930 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4931 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4932 | break; |
4933 | ||
4934 | case M_BGTUL: | |
4935 | likely = 1; | |
4936 | case M_BGTU: | |
4937 | if (treg == 0) | |
4938 | { | |
67c0d1eb | 4939 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4940 | "s,t,p", sreg, 0); |
8fc2e39e | 4941 | break; |
252b5132 RH |
4942 | } |
4943 | if (sreg == 0) | |
4944 | goto do_false; | |
8fc2e39e | 4945 | used_at = 1; |
67c0d1eb RS |
4946 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4947 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4948 | break; |
4949 | ||
4950 | case M_BLEL: | |
4951 | likely = 1; | |
4952 | case M_BLE: | |
4953 | if (treg == 0) | |
4954 | { | |
67c0d1eb | 4955 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4956 | break; |
252b5132 RH |
4957 | } |
4958 | if (sreg == 0) | |
4959 | { | |
67c0d1eb | 4960 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4961 | break; |
252b5132 | 4962 | } |
8fc2e39e | 4963 | used_at = 1; |
67c0d1eb RS |
4964 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4965 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4966 | break; |
4967 | ||
4968 | case M_BLEL_I: | |
4969 | likely = 1; | |
4970 | case M_BLE_I: | |
4971 | maxnum = 0x7fffffff; | |
ca4e0257 | 4972 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4973 | { |
4974 | maxnum <<= 16; | |
4975 | maxnum |= 0xffff; | |
4976 | maxnum <<= 16; | |
4977 | maxnum |= 0xffff; | |
4978 | } | |
4979 | if (imm_expr.X_op == O_constant | |
4980 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4981 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4982 | goto do_true; |
4983 | if (imm_expr.X_op != O_constant) | |
4984 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4985 | ++imm_expr.X_add_number; |
252b5132 RH |
4986 | /* FALLTHROUGH */ |
4987 | case M_BLT_I: | |
4988 | case M_BLTL_I: | |
4989 | if (mask == M_BLTL_I) | |
4990 | likely = 1; | |
4991 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4992 | { | |
67c0d1eb | 4993 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4994 | break; |
252b5132 RH |
4995 | } |
4996 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4997 | { | |
67c0d1eb | 4998 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4999 | break; |
252b5132 | 5000 | } |
8fc2e39e | 5001 | used_at = 1; |
67c0d1eb RS |
5002 | set_at (sreg, 0); |
5003 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5004 | break; |
5005 | ||
5006 | case M_BLEUL: | |
5007 | likely = 1; | |
5008 | case M_BLEU: | |
5009 | if (treg == 0) | |
5010 | { | |
67c0d1eb | 5011 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5012 | "s,t,p", sreg, 0); |
8fc2e39e | 5013 | break; |
252b5132 RH |
5014 | } |
5015 | if (sreg == 0) | |
5016 | goto do_true; | |
8fc2e39e | 5017 | used_at = 1; |
67c0d1eb RS |
5018 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5019 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5020 | break; |
5021 | ||
5022 | case M_BLEUL_I: | |
5023 | likely = 1; | |
5024 | case M_BLEU_I: | |
5025 | if (sreg == 0 | |
ca4e0257 | 5026 | || (HAVE_32BIT_GPRS |
252b5132 | 5027 | && imm_expr.X_op == O_constant |
956cd1d6 | 5028 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5029 | goto do_true; |
5030 | if (imm_expr.X_op != O_constant) | |
5031 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5032 | ++imm_expr.X_add_number; |
252b5132 RH |
5033 | /* FALLTHROUGH */ |
5034 | case M_BLTU_I: | |
5035 | case M_BLTUL_I: | |
5036 | if (mask == M_BLTUL_I) | |
5037 | likely = 1; | |
5038 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5039 | goto do_false; | |
5040 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5041 | { | |
67c0d1eb | 5042 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 5043 | "s,t,p", sreg, 0); |
8fc2e39e | 5044 | break; |
252b5132 | 5045 | } |
8fc2e39e | 5046 | used_at = 1; |
67c0d1eb RS |
5047 | set_at (sreg, 1); |
5048 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5049 | break; |
5050 | ||
5051 | case M_BLTL: | |
5052 | likely = 1; | |
5053 | case M_BLT: | |
5054 | if (treg == 0) | |
5055 | { | |
67c0d1eb | 5056 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5057 | break; |
252b5132 RH |
5058 | } |
5059 | if (sreg == 0) | |
5060 | { | |
67c0d1eb | 5061 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5062 | break; |
252b5132 | 5063 | } |
8fc2e39e | 5064 | used_at = 1; |
67c0d1eb RS |
5065 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
5066 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5067 | break; |
5068 | ||
5069 | case M_BLTUL: | |
5070 | likely = 1; | |
5071 | case M_BLTU: | |
5072 | if (treg == 0) | |
5073 | goto do_false; | |
5074 | if (sreg == 0) | |
5075 | { | |
67c0d1eb | 5076 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5077 | "s,t,p", 0, treg); |
8fc2e39e | 5078 | break; |
252b5132 | 5079 | } |
8fc2e39e | 5080 | used_at = 1; |
67c0d1eb RS |
5081 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5082 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5083 | break; |
5084 | ||
5f74bc13 CD |
5085 | case M_DEXT: |
5086 | { | |
5087 | unsigned long pos; | |
5088 | unsigned long size; | |
5089 | ||
5090 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5091 | { | |
5092 | as_bad (_("Unsupported large constant")); | |
5093 | pos = size = 1; | |
5094 | } | |
5095 | else | |
5096 | { | |
5097 | pos = (unsigned long) imm_expr.X_add_number; | |
5098 | size = (unsigned long) imm2_expr.X_add_number; | |
5099 | } | |
5100 | ||
5101 | if (pos > 63) | |
5102 | { | |
5103 | as_bad (_("Improper position (%lu)"), pos); | |
5104 | pos = 1; | |
5105 | } | |
5106 | if (size == 0 || size > 64 | |
5107 | || (pos + size - 1) > 63) | |
5108 | { | |
5109 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5110 | size, pos); | |
5111 | size = 1; | |
5112 | } | |
5113 | ||
5114 | if (size <= 32 && pos < 32) | |
5115 | { | |
5116 | s = "dext"; | |
5117 | fmt = "t,r,+A,+C"; | |
5118 | } | |
5119 | else if (size <= 32) | |
5120 | { | |
5121 | s = "dextu"; | |
5122 | fmt = "t,r,+E,+H"; | |
5123 | } | |
5124 | else | |
5125 | { | |
5126 | s = "dextm"; | |
5127 | fmt = "t,r,+A,+G"; | |
5128 | } | |
67c0d1eb | 5129 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5130 | } |
8fc2e39e | 5131 | break; |
5f74bc13 CD |
5132 | |
5133 | case M_DINS: | |
5134 | { | |
5135 | unsigned long pos; | |
5136 | unsigned long size; | |
5137 | ||
5138 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5139 | { | |
5140 | as_bad (_("Unsupported large constant")); | |
5141 | pos = size = 1; | |
5142 | } | |
5143 | else | |
5144 | { | |
5145 | pos = (unsigned long) imm_expr.X_add_number; | |
5146 | size = (unsigned long) imm2_expr.X_add_number; | |
5147 | } | |
5148 | ||
5149 | if (pos > 63) | |
5150 | { | |
5151 | as_bad (_("Improper position (%lu)"), pos); | |
5152 | pos = 1; | |
5153 | } | |
5154 | if (size == 0 || size > 64 | |
5155 | || (pos + size - 1) > 63) | |
5156 | { | |
5157 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5158 | size, pos); | |
5159 | size = 1; | |
5160 | } | |
5161 | ||
5162 | if (pos < 32 && (pos + size - 1) < 32) | |
5163 | { | |
5164 | s = "dins"; | |
5165 | fmt = "t,r,+A,+B"; | |
5166 | } | |
5167 | else if (pos >= 32) | |
5168 | { | |
5169 | s = "dinsu"; | |
5170 | fmt = "t,r,+E,+F"; | |
5171 | } | |
5172 | else | |
5173 | { | |
5174 | s = "dinsm"; | |
5175 | fmt = "t,r,+A,+F"; | |
5176 | } | |
67c0d1eb RS |
5177 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5178 | pos + size - 1); | |
5f74bc13 | 5179 | } |
8fc2e39e | 5180 | break; |
5f74bc13 | 5181 | |
252b5132 RH |
5182 | case M_DDIV_3: |
5183 | dbl = 1; | |
5184 | case M_DIV_3: | |
5185 | s = "mflo"; | |
5186 | goto do_div3; | |
5187 | case M_DREM_3: | |
5188 | dbl = 1; | |
5189 | case M_REM_3: | |
5190 | s = "mfhi"; | |
5191 | do_div3: | |
5192 | if (treg == 0) | |
5193 | { | |
5194 | as_warn (_("Divide by zero.")); | |
5195 | if (mips_trap) | |
67c0d1eb | 5196 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5197 | else |
67c0d1eb | 5198 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5199 | break; |
252b5132 RH |
5200 | } |
5201 | ||
7d10b47d | 5202 | start_noreorder (); |
252b5132 RH |
5203 | if (mips_trap) |
5204 | { | |
67c0d1eb RS |
5205 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5206 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5207 | } |
5208 | else | |
5209 | { | |
5210 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5211 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5212 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5213 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5214 | } |
5215 | expr1.X_add_number = -1; | |
8fc2e39e | 5216 | used_at = 1; |
f6a22291 | 5217 | load_register (AT, &expr1, dbl); |
252b5132 | 5218 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5219 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5220 | if (dbl) |
5221 | { | |
5222 | expr1.X_add_number = 1; | |
f6a22291 | 5223 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5224 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5225 | } |
5226 | else | |
5227 | { | |
5228 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5229 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5230 | } |
5231 | if (mips_trap) | |
5232 | { | |
67c0d1eb | 5233 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5234 | /* We want to close the noreorder block as soon as possible, so |
5235 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5236 | end_noreorder (); |
252b5132 RH |
5237 | } |
5238 | else | |
5239 | { | |
5240 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5241 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5242 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5243 | |
5244 | /* We want to close the noreorder block as soon as possible, so | |
5245 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5246 | end_noreorder (); |
252b5132 | 5247 | |
67c0d1eb | 5248 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5249 | } |
67c0d1eb | 5250 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5251 | break; |
5252 | ||
5253 | case M_DIV_3I: | |
5254 | s = "div"; | |
5255 | s2 = "mflo"; | |
5256 | goto do_divi; | |
5257 | case M_DIVU_3I: | |
5258 | s = "divu"; | |
5259 | s2 = "mflo"; | |
5260 | goto do_divi; | |
5261 | case M_REM_3I: | |
5262 | s = "div"; | |
5263 | s2 = "mfhi"; | |
5264 | goto do_divi; | |
5265 | case M_REMU_3I: | |
5266 | s = "divu"; | |
5267 | s2 = "mfhi"; | |
5268 | goto do_divi; | |
5269 | case M_DDIV_3I: | |
5270 | dbl = 1; | |
5271 | s = "ddiv"; | |
5272 | s2 = "mflo"; | |
5273 | goto do_divi; | |
5274 | case M_DDIVU_3I: | |
5275 | dbl = 1; | |
5276 | s = "ddivu"; | |
5277 | s2 = "mflo"; | |
5278 | goto do_divi; | |
5279 | case M_DREM_3I: | |
5280 | dbl = 1; | |
5281 | s = "ddiv"; | |
5282 | s2 = "mfhi"; | |
5283 | goto do_divi; | |
5284 | case M_DREMU_3I: | |
5285 | dbl = 1; | |
5286 | s = "ddivu"; | |
5287 | s2 = "mfhi"; | |
5288 | do_divi: | |
5289 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5290 | { | |
5291 | as_warn (_("Divide by zero.")); | |
5292 | if (mips_trap) | |
67c0d1eb | 5293 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5294 | else |
67c0d1eb | 5295 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5296 | break; |
252b5132 RH |
5297 | } |
5298 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5299 | { | |
5300 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5301 | move_register (dreg, sreg); |
252b5132 | 5302 | else |
67c0d1eb | 5303 | move_register (dreg, 0); |
8fc2e39e | 5304 | break; |
252b5132 RH |
5305 | } |
5306 | if (imm_expr.X_op == O_constant | |
5307 | && imm_expr.X_add_number == -1 | |
5308 | && s[strlen (s) - 1] != 'u') | |
5309 | { | |
5310 | if (strcmp (s2, "mflo") == 0) | |
5311 | { | |
67c0d1eb | 5312 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5313 | } |
5314 | else | |
67c0d1eb | 5315 | move_register (dreg, 0); |
8fc2e39e | 5316 | break; |
252b5132 RH |
5317 | } |
5318 | ||
8fc2e39e | 5319 | used_at = 1; |
67c0d1eb RS |
5320 | load_register (AT, &imm_expr, dbl); |
5321 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5322 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5323 | break; |
5324 | ||
5325 | case M_DIVU_3: | |
5326 | s = "divu"; | |
5327 | s2 = "mflo"; | |
5328 | goto do_divu3; | |
5329 | case M_REMU_3: | |
5330 | s = "divu"; | |
5331 | s2 = "mfhi"; | |
5332 | goto do_divu3; | |
5333 | case M_DDIVU_3: | |
5334 | s = "ddivu"; | |
5335 | s2 = "mflo"; | |
5336 | goto do_divu3; | |
5337 | case M_DREMU_3: | |
5338 | s = "ddivu"; | |
5339 | s2 = "mfhi"; | |
5340 | do_divu3: | |
7d10b47d | 5341 | start_noreorder (); |
252b5132 RH |
5342 | if (mips_trap) |
5343 | { | |
67c0d1eb RS |
5344 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5345 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5346 | /* We want to close the noreorder block as soon as possible, so |
5347 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5348 | end_noreorder (); |
252b5132 RH |
5349 | } |
5350 | else | |
5351 | { | |
5352 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5353 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5354 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5355 | |
5356 | /* We want to close the noreorder block as soon as possible, so | |
5357 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5358 | end_noreorder (); |
67c0d1eb | 5359 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5360 | } |
67c0d1eb | 5361 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5362 | break; |
252b5132 | 5363 | |
1abe91b1 MR |
5364 | case M_DLCA_AB: |
5365 | dbl = 1; | |
5366 | case M_LCA_AB: | |
5367 | call = 1; | |
5368 | goto do_la; | |
252b5132 RH |
5369 | case M_DLA_AB: |
5370 | dbl = 1; | |
5371 | case M_LA_AB: | |
1abe91b1 | 5372 | do_la: |
252b5132 RH |
5373 | /* Load the address of a symbol into a register. If breg is not |
5374 | zero, we then add a base register to it. */ | |
5375 | ||
3bec30a8 TS |
5376 | if (dbl && HAVE_32BIT_GPRS) |
5377 | as_warn (_("dla used to load 32-bit register")); | |
5378 | ||
c90bbe5b | 5379 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5380 | as_warn (_("la used to load 64-bit address")); |
5381 | ||
0c11417f MR |
5382 | if (offset_expr.X_op == O_constant |
5383 | && offset_expr.X_add_number >= -0x8000 | |
5384 | && offset_expr.X_add_number < 0x8000) | |
5385 | { | |
aed1a261 | 5386 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5387 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5388 | break; |
0c11417f MR |
5389 | } |
5390 | ||
741fe287 | 5391 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5392 | { |
5393 | tempreg = AT; | |
5394 | used_at = 1; | |
5395 | } | |
5396 | else | |
5397 | { | |
5398 | tempreg = treg; | |
afdbd6d0 CD |
5399 | } |
5400 | ||
252b5132 RH |
5401 | if (offset_expr.X_op != O_symbol |
5402 | && offset_expr.X_op != O_constant) | |
5403 | { | |
5404 | as_bad (_("expression too complex")); | |
5405 | offset_expr.X_op = O_constant; | |
5406 | } | |
5407 | ||
252b5132 | 5408 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5409 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5410 | else if (mips_pic == NO_PIC) |
5411 | { | |
d6bc6245 | 5412 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5413 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5414 | Otherwise we want |
5415 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5416 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5417 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5418 | so we may as well always use the latter form. |
76b3015f | 5419 | |
6caf9ef4 TS |
5420 | With 64bit address space and a usable $at we want |
5421 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5422 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5423 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5424 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5425 | dsll32 $tempreg,0 | |
5426 | daddu $tempreg,$tempreg,$at | |
5427 | ||
5428 | If $at is already in use, we use a path which is suboptimal | |
5429 | on superscalar processors. | |
5430 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5431 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5432 | dsll $tempreg,16 | |
5433 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5434 | dsll $tempreg,16 | |
5435 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5436 | ||
5437 | For GP relative symbols in 64bit address space we can use | |
5438 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5439 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5440 | { |
6caf9ef4 TS |
5441 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5442 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5443 | { | |
5444 | relax_start (offset_expr.X_add_symbol); | |
5445 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5446 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5447 | relax_switch (); | |
5448 | } | |
d6bc6245 | 5449 | |
741fe287 | 5450 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5451 | { |
67c0d1eb | 5452 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5453 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5454 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5455 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5456 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5457 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5458 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5459 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5460 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5461 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5462 | used_at = 1; |
5463 | } | |
5464 | else | |
5465 | { | |
67c0d1eb | 5466 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5467 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5468 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5469 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5470 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5471 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5472 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5473 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5474 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5475 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5476 | } |
6caf9ef4 TS |
5477 | |
5478 | if (mips_relax.sequence) | |
5479 | relax_end (); | |
98d3f06f KH |
5480 | } |
5481 | else | |
5482 | { | |
5483 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5484 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5485 | { |
4d7206a2 | 5486 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5487 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5488 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5489 | relax_switch (); |
98d3f06f | 5490 | } |
6943caf0 ILT |
5491 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5492 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5493 | macro_build_lui (&offset_expr, tempreg); |
5494 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5495 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5496 | if (mips_relax.sequence) |
5497 | relax_end (); | |
98d3f06f | 5498 | } |
252b5132 | 5499 | } |
0a44bf69 | 5500 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5501 | { |
9117d219 NC |
5502 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5503 | ||
252b5132 RH |
5504 | /* If this is a reference to an external symbol, and there |
5505 | is no constant, we want | |
5506 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5507 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5508 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5509 | For a local symbol, we want |
5510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5511 | nop | |
5512 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5513 | ||
5514 | If we have a small constant, and this is a reference to | |
5515 | an external symbol, we want | |
5516 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5517 | nop | |
5518 | addiu $tempreg,$tempreg,<constant> | |
5519 | For a local symbol, we want the same instruction | |
5520 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5521 | addiu instruction. | |
5522 | ||
5523 | If we have a large constant, and this is a reference to | |
5524 | an external symbol, we want | |
5525 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5526 | lui $at,<hiconstant> | |
5527 | addiu $at,$at,<loconstant> | |
5528 | addu $tempreg,$tempreg,$at | |
5529 | For a local symbol, we want the same instruction | |
5530 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5531 | addiu instruction. |
ed6fb7bd SC |
5532 | */ |
5533 | ||
4d7206a2 | 5534 | if (offset_expr.X_add_number == 0) |
252b5132 | 5535 | { |
0a44bf69 RS |
5536 | if (mips_pic == SVR4_PIC |
5537 | && breg == 0 | |
5538 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5539 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5540 | ||
5541 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5542 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5543 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5544 | if (breg != 0) |
252b5132 RH |
5545 | { |
5546 | /* We're going to put in an addu instruction using | |
5547 | tempreg, so we may as well insert the nop right | |
5548 | now. */ | |
269137b2 | 5549 | load_delay_nop (); |
252b5132 | 5550 | } |
4d7206a2 | 5551 | relax_switch (); |
67c0d1eb RS |
5552 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5553 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5554 | load_delay_nop (); |
67c0d1eb RS |
5555 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5556 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5557 | relax_end (); |
252b5132 RH |
5558 | /* FIXME: If breg == 0, and the next instruction uses |
5559 | $tempreg, then if this variant case is used an extra | |
5560 | nop will be generated. */ | |
5561 | } | |
4d7206a2 RS |
5562 | else if (offset_expr.X_add_number >= -0x8000 |
5563 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5564 | { |
67c0d1eb | 5565 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5566 | load_delay_nop (); |
67c0d1eb | 5567 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5568 | } |
5569 | else | |
5570 | { | |
4d7206a2 RS |
5571 | expr1.X_add_number = offset_expr.X_add_number; |
5572 | offset_expr.X_add_number = | |
5573 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5574 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5575 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5576 | /* If we are going to add in a base register, and the |
5577 | target register and the base register are the same, | |
5578 | then we are using AT as a temporary register. Since | |
5579 | we want to load the constant into AT, we add our | |
5580 | current AT (from the global offset table) and the | |
5581 | register into the register now, and pretend we were | |
5582 | not using a base register. */ | |
67c0d1eb | 5583 | if (breg == treg) |
252b5132 | 5584 | { |
269137b2 | 5585 | load_delay_nop (); |
67c0d1eb | 5586 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5587 | treg, AT, breg); |
252b5132 RH |
5588 | breg = 0; |
5589 | tempreg = treg; | |
252b5132 | 5590 | } |
f6a22291 | 5591 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5592 | used_at = 1; |
5593 | } | |
5594 | } | |
0a44bf69 | 5595 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5596 | { |
67c0d1eb | 5597 | int add_breg_early = 0; |
f5040a92 AO |
5598 | |
5599 | /* If this is a reference to an external, and there is no | |
5600 | constant, or local symbol (*), with or without a | |
5601 | constant, we want | |
5602 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5603 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5604 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5605 | ||
5606 | If we have a small constant, and this is a reference to | |
5607 | an external symbol, we want | |
5608 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5609 | addiu $tempreg,$tempreg,<constant> | |
5610 | ||
5611 | If we have a large constant, and this is a reference to | |
5612 | an external symbol, we want | |
5613 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5614 | lui $at,<hiconstant> | |
5615 | addiu $at,$at,<loconstant> | |
5616 | addu $tempreg,$tempreg,$at | |
5617 | ||
5618 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5619 | local symbols, even though it introduces an additional | |
5620 | instruction. */ | |
5621 | ||
f5040a92 AO |
5622 | if (offset_expr.X_add_number) |
5623 | { | |
4d7206a2 | 5624 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5625 | offset_expr.X_add_number = 0; |
5626 | ||
4d7206a2 | 5627 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5628 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5629 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5630 | |
5631 | if (expr1.X_add_number >= -0x8000 | |
5632 | && expr1.X_add_number < 0x8000) | |
5633 | { | |
67c0d1eb RS |
5634 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5635 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5636 | } |
ecd13cd3 | 5637 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5638 | { |
5639 | int dreg; | |
5640 | ||
5641 | /* If we are going to add in a base register, and the | |
5642 | target register and the base register are the same, | |
5643 | then we are using AT as a temporary register. Since | |
5644 | we want to load the constant into AT, we add our | |
5645 | current AT (from the global offset table) and the | |
5646 | register into the register now, and pretend we were | |
5647 | not using a base register. */ | |
5648 | if (breg != treg) | |
5649 | dreg = tempreg; | |
5650 | else | |
5651 | { | |
5652 | assert (tempreg == AT); | |
67c0d1eb RS |
5653 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5654 | treg, AT, breg); | |
f5040a92 | 5655 | dreg = treg; |
67c0d1eb | 5656 | add_breg_early = 1; |
f5040a92 AO |
5657 | } |
5658 | ||
f6a22291 | 5659 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5660 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5661 | dreg, dreg, AT); |
f5040a92 | 5662 | |
f5040a92 AO |
5663 | used_at = 1; |
5664 | } | |
5665 | else | |
5666 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5667 | ||
4d7206a2 | 5668 | relax_switch (); |
f5040a92 AO |
5669 | offset_expr.X_add_number = expr1.X_add_number; |
5670 | ||
67c0d1eb RS |
5671 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5672 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5673 | if (add_breg_early) | |
f5040a92 | 5674 | { |
67c0d1eb | 5675 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5676 | treg, tempreg, breg); |
f5040a92 AO |
5677 | breg = 0; |
5678 | tempreg = treg; | |
5679 | } | |
4d7206a2 | 5680 | relax_end (); |
f5040a92 | 5681 | } |
4d7206a2 | 5682 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5683 | { |
4d7206a2 | 5684 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5685 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5686 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5687 | relax_switch (); |
67c0d1eb RS |
5688 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5689 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5690 | relax_end (); |
f5040a92 | 5691 | } |
4d7206a2 | 5692 | else |
f5040a92 | 5693 | { |
67c0d1eb RS |
5694 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5695 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5696 | } |
5697 | } | |
0a44bf69 | 5698 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5699 | { |
67c0d1eb | 5700 | int gpdelay; |
9117d219 NC |
5701 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5702 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5703 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5704 | |
5705 | /* This is the large GOT case. If this is a reference to an | |
5706 | external symbol, and there is no constant, we want | |
5707 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5708 | addu $tempreg,$tempreg,$gp | |
5709 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5710 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5711 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5712 | addu $tempreg,$tempreg,$gp | |
5713 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5714 | For a local symbol, we want |
5715 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5716 | nop | |
5717 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5718 | ||
5719 | If we have a small constant, and this is a reference to | |
5720 | an external symbol, we want | |
5721 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5722 | addu $tempreg,$tempreg,$gp | |
5723 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5724 | nop | |
5725 | addiu $tempreg,$tempreg,<constant> | |
5726 | For a local symbol, we want | |
5727 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5728 | nop | |
5729 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5730 | ||
5731 | If we have a large constant, and this is a reference to | |
5732 | an external symbol, we want | |
5733 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5734 | addu $tempreg,$tempreg,$gp | |
5735 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5736 | lui $at,<hiconstant> | |
5737 | addiu $at,$at,<loconstant> | |
5738 | addu $tempreg,$tempreg,$at | |
5739 | For a local symbol, we want | |
5740 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5741 | lui $at,<hiconstant> | |
5742 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5743 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5744 | */ |
438c16b8 | 5745 | |
252b5132 RH |
5746 | expr1.X_add_number = offset_expr.X_add_number; |
5747 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5748 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5749 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5750 | if (expr1.X_add_number == 0 && breg == 0 |
5751 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5752 | { |
5753 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5754 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5755 | } | |
67c0d1eb RS |
5756 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5757 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5758 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5759 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5760 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5761 | if (expr1.X_add_number == 0) |
5762 | { | |
67c0d1eb | 5763 | if (breg != 0) |
252b5132 RH |
5764 | { |
5765 | /* We're going to put in an addu instruction using | |
5766 | tempreg, so we may as well insert the nop right | |
5767 | now. */ | |
269137b2 | 5768 | load_delay_nop (); |
252b5132 | 5769 | } |
252b5132 RH |
5770 | } |
5771 | else if (expr1.X_add_number >= -0x8000 | |
5772 | && expr1.X_add_number < 0x8000) | |
5773 | { | |
269137b2 | 5774 | load_delay_nop (); |
67c0d1eb | 5775 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5776 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5777 | } |
5778 | else | |
5779 | { | |
67c0d1eb | 5780 | int dreg; |
252b5132 RH |
5781 | |
5782 | /* If we are going to add in a base register, and the | |
5783 | target register and the base register are the same, | |
5784 | then we are using AT as a temporary register. Since | |
5785 | we want to load the constant into AT, we add our | |
5786 | current AT (from the global offset table) and the | |
5787 | register into the register now, and pretend we were | |
5788 | not using a base register. */ | |
5789 | if (breg != treg) | |
67c0d1eb | 5790 | dreg = tempreg; |
252b5132 RH |
5791 | else |
5792 | { | |
5793 | assert (tempreg == AT); | |
269137b2 | 5794 | load_delay_nop (); |
67c0d1eb | 5795 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5796 | treg, AT, breg); |
252b5132 | 5797 | dreg = treg; |
252b5132 RH |
5798 | } |
5799 | ||
f6a22291 | 5800 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5801 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5802 | |
252b5132 RH |
5803 | used_at = 1; |
5804 | } | |
4d7206a2 RS |
5805 | offset_expr.X_add_number = |
5806 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5807 | relax_switch (); | |
252b5132 | 5808 | |
67c0d1eb | 5809 | if (gpdelay) |
252b5132 RH |
5810 | { |
5811 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5812 | the first instruction on the main stream does not. */ |
67c0d1eb | 5813 | macro_build (NULL, "nop", ""); |
252b5132 | 5814 | } |
ed6fb7bd | 5815 | |
67c0d1eb RS |
5816 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5817 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5818 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5819 | && expr1.X_add_number < 0x8000) |
5820 | { | |
269137b2 | 5821 | load_delay_nop (); |
67c0d1eb RS |
5822 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5823 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5824 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5825 | register, the external symbol case ended with a load, |
5826 | so if the symbol turns out to not be external, and | |
5827 | the next instruction uses tempreg, an unnecessary nop | |
5828 | will be inserted. */ | |
252b5132 RH |
5829 | } |
5830 | else | |
5831 | { | |
5832 | if (breg == treg) | |
5833 | { | |
5834 | /* We must add in the base register now, as in the | |
f5040a92 | 5835 | external symbol case. */ |
252b5132 | 5836 | assert (tempreg == AT); |
269137b2 | 5837 | load_delay_nop (); |
67c0d1eb | 5838 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5839 | treg, AT, breg); |
252b5132 RH |
5840 | tempreg = treg; |
5841 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5842 | it in in both cases. */ |
252b5132 RH |
5843 | breg = 0; |
5844 | } | |
5845 | ||
67c0d1eb RS |
5846 | macro_build_lui (&expr1, AT); |
5847 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5848 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5849 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5850 | tempreg, tempreg, AT); |
8fc2e39e | 5851 | used_at = 1; |
252b5132 | 5852 | } |
4d7206a2 | 5853 | relax_end (); |
252b5132 | 5854 | } |
0a44bf69 | 5855 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5856 | { |
f5040a92 AO |
5857 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5858 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5859 | int add_breg_early = 0; |
f5040a92 AO |
5860 | |
5861 | /* This is the large GOT case. If this is a reference to an | |
5862 | external symbol, and there is no constant, we want | |
5863 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5864 | add $tempreg,$tempreg,$gp | |
5865 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5866 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5867 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5868 | add $tempreg,$tempreg,$gp | |
5869 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5870 | ||
5871 | If we have a small constant, and this is a reference to | |
5872 | an external symbol, we want | |
5873 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5874 | add $tempreg,$tempreg,$gp | |
5875 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5876 | addi $tempreg,$tempreg,<constant> | |
5877 | ||
5878 | If we have a large constant, and this is a reference to | |
5879 | an external symbol, we want | |
5880 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5881 | addu $tempreg,$tempreg,$gp | |
5882 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5883 | lui $at,<hiconstant> | |
5884 | addi $at,$at,<loconstant> | |
5885 | add $tempreg,$tempreg,$at | |
5886 | ||
5887 | If we have NewABI, and we know it's a local symbol, we want | |
5888 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5889 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5890 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5891 | ||
4d7206a2 | 5892 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5893 | |
4d7206a2 | 5894 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5895 | offset_expr.X_add_number = 0; |
5896 | ||
1abe91b1 MR |
5897 | if (expr1.X_add_number == 0 && breg == 0 |
5898 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5899 | { |
5900 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5901 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5902 | } | |
67c0d1eb RS |
5903 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5904 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5905 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5906 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5907 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5908 | |
5909 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5910 | ; |
f5040a92 AO |
5911 | else if (expr1.X_add_number >= -0x8000 |
5912 | && expr1.X_add_number < 0x8000) | |
5913 | { | |
67c0d1eb | 5914 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5915 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5916 | } |
ecd13cd3 | 5917 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5918 | { |
5919 | int dreg; | |
5920 | ||
5921 | /* If we are going to add in a base register, and the | |
5922 | target register and the base register are the same, | |
5923 | then we are using AT as a temporary register. Since | |
5924 | we want to load the constant into AT, we add our | |
5925 | current AT (from the global offset table) and the | |
5926 | register into the register now, and pretend we were | |
5927 | not using a base register. */ | |
5928 | if (breg != treg) | |
5929 | dreg = tempreg; | |
5930 | else | |
5931 | { | |
5932 | assert (tempreg == AT); | |
67c0d1eb | 5933 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5934 | treg, AT, breg); |
f5040a92 | 5935 | dreg = treg; |
67c0d1eb | 5936 | add_breg_early = 1; |
f5040a92 AO |
5937 | } |
5938 | ||
f6a22291 | 5939 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5940 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5941 | |
f5040a92 AO |
5942 | used_at = 1; |
5943 | } | |
5944 | else | |
5945 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5946 | ||
4d7206a2 | 5947 | relax_switch (); |
f5040a92 | 5948 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5949 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5950 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5951 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5952 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5953 | if (add_breg_early) | |
f5040a92 | 5954 | { |
67c0d1eb | 5955 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5956 | treg, tempreg, breg); |
f5040a92 AO |
5957 | breg = 0; |
5958 | tempreg = treg; | |
5959 | } | |
4d7206a2 | 5960 | relax_end (); |
f5040a92 | 5961 | } |
252b5132 RH |
5962 | else |
5963 | abort (); | |
5964 | ||
5965 | if (breg != 0) | |
aed1a261 | 5966 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5967 | break; |
5968 | ||
5969 | case M_J_A: | |
5970 | /* The j instruction may not be used in PIC code, since it | |
5971 | requires an absolute address. We convert it to a b | |
5972 | instruction. */ | |
5973 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5974 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5975 | else |
67c0d1eb | 5976 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5977 | break; |
252b5132 RH |
5978 | |
5979 | /* The jal instructions must be handled as macros because when | |
5980 | generating PIC code they expand to multi-instruction | |
5981 | sequences. Normally they are simple instructions. */ | |
5982 | case M_JAL_1: | |
5983 | dreg = RA; | |
5984 | /* Fall through. */ | |
5985 | case M_JAL_2: | |
3e722fb5 | 5986 | if (mips_pic == NO_PIC) |
67c0d1eb | 5987 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5988 | else |
252b5132 RH |
5989 | { |
5990 | if (sreg != PIC_CALL_REG) | |
5991 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5992 | |
67c0d1eb | 5993 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5994 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5995 | { |
6478892d TS |
5996 | if (mips_cprestore_offset < 0) |
5997 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5998 | else | |
5999 | { | |
7a621144 DJ |
6000 | if (! mips_frame_reg_valid) |
6001 | { | |
6002 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6003 | /* Quiet this warning. */ | |
6004 | mips_frame_reg_valid = 1; | |
6005 | } | |
6006 | if (! mips_cprestore_valid) | |
6007 | { | |
6008 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6009 | /* Quiet this warning. */ | |
6010 | mips_cprestore_valid = 1; | |
6011 | } | |
6478892d | 6012 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6013 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6014 | mips_gp_register, |
256ab948 TS |
6015 | mips_frame_reg, |
6016 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6017 | } |
252b5132 RH |
6018 | } |
6019 | } | |
252b5132 | 6020 | |
8fc2e39e | 6021 | break; |
252b5132 RH |
6022 | |
6023 | case M_JAL_A: | |
6024 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6025 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6026 | else if (mips_pic == SVR4_PIC) |
6027 | { | |
6028 | /* If this is a reference to an external symbol, and we are | |
6029 | using a small GOT, we want | |
6030 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6031 | nop | |
f9419b05 | 6032 | jalr $ra,$25 |
252b5132 RH |
6033 | nop |
6034 | lw $gp,cprestore($sp) | |
6035 | The cprestore value is set using the .cprestore | |
6036 | pseudo-op. If we are using a big GOT, we want | |
6037 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6038 | addu $25,$25,$gp | |
6039 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6040 | nop | |
f9419b05 | 6041 | jalr $ra,$25 |
252b5132 RH |
6042 | nop |
6043 | lw $gp,cprestore($sp) | |
6044 | If the symbol is not external, we want | |
6045 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6046 | nop | |
6047 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6048 | jalr $ra,$25 |
252b5132 | 6049 | nop |
438c16b8 | 6050 | lw $gp,cprestore($sp) |
f5040a92 AO |
6051 | |
6052 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6053 | sequences above, minus nops, unless the symbol is local, | |
6054 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6055 | GOT_DISP. */ | |
438c16b8 | 6056 | if (HAVE_NEWABI) |
252b5132 | 6057 | { |
f5040a92 AO |
6058 | if (! mips_big_got) |
6059 | { | |
4d7206a2 | 6060 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6061 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6062 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6063 | mips_gp_register); |
4d7206a2 | 6064 | relax_switch (); |
67c0d1eb RS |
6065 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6066 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6067 | mips_gp_register); |
6068 | relax_end (); | |
f5040a92 AO |
6069 | } |
6070 | else | |
6071 | { | |
4d7206a2 | 6072 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6073 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6074 | BFD_RELOC_MIPS_CALL_HI16); | |
6075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6076 | PIC_CALL_REG, mips_gp_register); | |
6077 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6078 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6079 | PIC_CALL_REG); | |
4d7206a2 | 6080 | relax_switch (); |
67c0d1eb RS |
6081 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6082 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6083 | mips_gp_register); | |
6084 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6085 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6086 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6087 | relax_end (); |
f5040a92 | 6088 | } |
684022ea | 6089 | |
67c0d1eb | 6090 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6091 | } |
6092 | else | |
6093 | { | |
4d7206a2 | 6094 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6095 | if (! mips_big_got) |
6096 | { | |
67c0d1eb RS |
6097 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6098 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6099 | mips_gp_register); |
269137b2 | 6100 | load_delay_nop (); |
4d7206a2 | 6101 | relax_switch (); |
438c16b8 | 6102 | } |
252b5132 | 6103 | else |
252b5132 | 6104 | { |
67c0d1eb RS |
6105 | int gpdelay; |
6106 | ||
6107 | gpdelay = reg_needs_delay (mips_gp_register); | |
6108 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6109 | BFD_RELOC_MIPS_CALL_HI16); | |
6110 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6111 | PIC_CALL_REG, mips_gp_register); | |
6112 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6113 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6114 | PIC_CALL_REG); | |
269137b2 | 6115 | load_delay_nop (); |
4d7206a2 | 6116 | relax_switch (); |
67c0d1eb RS |
6117 | if (gpdelay) |
6118 | macro_build (NULL, "nop", ""); | |
252b5132 | 6119 | } |
67c0d1eb RS |
6120 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6121 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6122 | mips_gp_register); |
269137b2 | 6123 | load_delay_nop (); |
67c0d1eb RS |
6124 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6125 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6126 | relax_end (); |
67c0d1eb | 6127 | macro_build_jalr (&offset_expr); |
438c16b8 | 6128 | |
6478892d TS |
6129 | if (mips_cprestore_offset < 0) |
6130 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6131 | else | |
6132 | { | |
7a621144 DJ |
6133 | if (! mips_frame_reg_valid) |
6134 | { | |
6135 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6136 | /* Quiet this warning. */ | |
6137 | mips_frame_reg_valid = 1; | |
6138 | } | |
6139 | if (! mips_cprestore_valid) | |
6140 | { | |
6141 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6142 | /* Quiet this warning. */ | |
6143 | mips_cprestore_valid = 1; | |
6144 | } | |
6478892d | 6145 | if (mips_opts.noreorder) |
67c0d1eb | 6146 | macro_build (NULL, "nop", ""); |
6478892d | 6147 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6148 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6149 | mips_gp_register, |
256ab948 TS |
6150 | mips_frame_reg, |
6151 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6152 | } |
252b5132 RH |
6153 | } |
6154 | } | |
0a44bf69 RS |
6155 | else if (mips_pic == VXWORKS_PIC) |
6156 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6157 | else |
6158 | abort (); | |
6159 | ||
8fc2e39e | 6160 | break; |
252b5132 RH |
6161 | |
6162 | case M_LB_AB: | |
6163 | s = "lb"; | |
6164 | goto ld; | |
6165 | case M_LBU_AB: | |
6166 | s = "lbu"; | |
6167 | goto ld; | |
6168 | case M_LH_AB: | |
6169 | s = "lh"; | |
6170 | goto ld; | |
6171 | case M_LHU_AB: | |
6172 | s = "lhu"; | |
6173 | goto ld; | |
6174 | case M_LW_AB: | |
6175 | s = "lw"; | |
6176 | goto ld; | |
6177 | case M_LWC0_AB: | |
6178 | s = "lwc0"; | |
bdaaa2e1 | 6179 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6180 | coproc = 1; |
6181 | goto ld; | |
6182 | case M_LWC1_AB: | |
6183 | s = "lwc1"; | |
bdaaa2e1 | 6184 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6185 | coproc = 1; |
6186 | goto ld; | |
6187 | case M_LWC2_AB: | |
6188 | s = "lwc2"; | |
bdaaa2e1 | 6189 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6190 | coproc = 1; |
6191 | goto ld; | |
6192 | case M_LWC3_AB: | |
6193 | s = "lwc3"; | |
bdaaa2e1 | 6194 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6195 | coproc = 1; |
6196 | goto ld; | |
6197 | case M_LWL_AB: | |
6198 | s = "lwl"; | |
6199 | lr = 1; | |
6200 | goto ld; | |
6201 | case M_LWR_AB: | |
6202 | s = "lwr"; | |
6203 | lr = 1; | |
6204 | goto ld; | |
6205 | case M_LDC1_AB: | |
252b5132 | 6206 | s = "ldc1"; |
bdaaa2e1 | 6207 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6208 | coproc = 1; |
6209 | goto ld; | |
6210 | case M_LDC2_AB: | |
6211 | s = "ldc2"; | |
bdaaa2e1 | 6212 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6213 | coproc = 1; |
6214 | goto ld; | |
6215 | case M_LDC3_AB: | |
6216 | s = "ldc3"; | |
bdaaa2e1 | 6217 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6218 | coproc = 1; |
6219 | goto ld; | |
6220 | case M_LDL_AB: | |
6221 | s = "ldl"; | |
6222 | lr = 1; | |
6223 | goto ld; | |
6224 | case M_LDR_AB: | |
6225 | s = "ldr"; | |
6226 | lr = 1; | |
6227 | goto ld; | |
6228 | case M_LL_AB: | |
6229 | s = "ll"; | |
6230 | goto ld; | |
6231 | case M_LLD_AB: | |
6232 | s = "lld"; | |
6233 | goto ld; | |
6234 | case M_LWU_AB: | |
6235 | s = "lwu"; | |
6236 | ld: | |
8fc2e39e | 6237 | if (breg == treg || coproc || lr) |
252b5132 RH |
6238 | { |
6239 | tempreg = AT; | |
6240 | used_at = 1; | |
6241 | } | |
6242 | else | |
6243 | { | |
6244 | tempreg = treg; | |
252b5132 RH |
6245 | } |
6246 | goto ld_st; | |
6247 | case M_SB_AB: | |
6248 | s = "sb"; | |
6249 | goto st; | |
6250 | case M_SH_AB: | |
6251 | s = "sh"; | |
6252 | goto st; | |
6253 | case M_SW_AB: | |
6254 | s = "sw"; | |
6255 | goto st; | |
6256 | case M_SWC0_AB: | |
6257 | s = "swc0"; | |
bdaaa2e1 | 6258 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6259 | coproc = 1; |
6260 | goto st; | |
6261 | case M_SWC1_AB: | |
6262 | s = "swc1"; | |
bdaaa2e1 | 6263 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6264 | coproc = 1; |
6265 | goto st; | |
6266 | case M_SWC2_AB: | |
6267 | s = "swc2"; | |
bdaaa2e1 | 6268 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6269 | coproc = 1; |
6270 | goto st; | |
6271 | case M_SWC3_AB: | |
6272 | s = "swc3"; | |
bdaaa2e1 | 6273 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6274 | coproc = 1; |
6275 | goto st; | |
6276 | case M_SWL_AB: | |
6277 | s = "swl"; | |
6278 | goto st; | |
6279 | case M_SWR_AB: | |
6280 | s = "swr"; | |
6281 | goto st; | |
6282 | case M_SC_AB: | |
6283 | s = "sc"; | |
6284 | goto st; | |
6285 | case M_SCD_AB: | |
6286 | s = "scd"; | |
6287 | goto st; | |
d43b4baf TS |
6288 | case M_CACHE_AB: |
6289 | s = "cache"; | |
6290 | goto st; | |
252b5132 | 6291 | case M_SDC1_AB: |
252b5132 RH |
6292 | s = "sdc1"; |
6293 | coproc = 1; | |
bdaaa2e1 | 6294 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6295 | goto st; |
6296 | case M_SDC2_AB: | |
6297 | s = "sdc2"; | |
bdaaa2e1 | 6298 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6299 | coproc = 1; |
6300 | goto st; | |
6301 | case M_SDC3_AB: | |
6302 | s = "sdc3"; | |
bdaaa2e1 | 6303 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6304 | coproc = 1; |
6305 | goto st; | |
6306 | case M_SDL_AB: | |
6307 | s = "sdl"; | |
6308 | goto st; | |
6309 | case M_SDR_AB: | |
6310 | s = "sdr"; | |
6311 | st: | |
8fc2e39e TS |
6312 | tempreg = AT; |
6313 | used_at = 1; | |
252b5132 | 6314 | ld_st: |
bdaaa2e1 | 6315 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6316 | if (mask == M_LWC1_AB |
6317 | || mask == M_SWC1_AB | |
6318 | || mask == M_LDC1_AB | |
6319 | || mask == M_SDC1_AB | |
6320 | || mask == M_L_DAB | |
6321 | || mask == M_S_DAB) | |
6322 | fmt = "T,o(b)"; | |
d43b4baf TS |
6323 | else if (mask == M_CACHE_AB) |
6324 | fmt = "k,o(b)"; | |
252b5132 RH |
6325 | else if (coproc) |
6326 | fmt = "E,o(b)"; | |
6327 | else | |
6328 | fmt = "t,o(b)"; | |
6329 | ||
6330 | if (offset_expr.X_op != O_constant | |
6331 | && offset_expr.X_op != O_symbol) | |
6332 | { | |
6333 | as_bad (_("expression too complex")); | |
6334 | offset_expr.X_op = O_constant; | |
6335 | } | |
6336 | ||
2051e8c4 MR |
6337 | if (HAVE_32BIT_ADDRESSES |
6338 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6339 | { |
6340 | char value [32]; | |
6341 | ||
6342 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6343 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6344 | } |
2051e8c4 | 6345 | |
252b5132 RH |
6346 | /* A constant expression in PIC code can be handled just as it |
6347 | is in non PIC code. */ | |
aed1a261 RS |
6348 | if (offset_expr.X_op == O_constant) |
6349 | { | |
aed1a261 RS |
6350 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6351 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6352 | normalize_address_expr (&expr1); |
aed1a261 RS |
6353 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6354 | if (breg != 0) | |
6355 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6356 | tempreg, tempreg, breg); | |
6357 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6358 | } | |
6359 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6360 | { |
6361 | /* If this is a reference to a GP relative symbol, and there | |
6362 | is no base register, we want | |
cdf6fd85 | 6363 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6364 | Otherwise, if there is no base register, we want |
6365 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6366 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6367 | If we have a constant, we need two instructions anyhow, | |
6368 | so we always use the latter form. | |
6369 | ||
6370 | If we have a base register, and this is a reference to a | |
6371 | GP relative symbol, we want | |
6372 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6373 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6374 | Otherwise we want |
6375 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6376 | addu $tempreg,$tempreg,$breg | |
6377 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6378 | With a constant we always use the latter case. |
76b3015f | 6379 | |
d6bc6245 TS |
6380 | With 64bit address space and no base register and $at usable, |
6381 | we want | |
6382 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6383 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6384 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6385 | dsll32 $tempreg,0 | |
6386 | daddu $tempreg,$at | |
6387 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6388 | If we have a base register, we want | |
6389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6390 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6391 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6392 | daddu $at,$breg | |
6393 | dsll32 $tempreg,0 | |
6394 | daddu $tempreg,$at | |
6395 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6396 | ||
6397 | Without $at we can't generate the optimal path for superscalar | |
6398 | processors here since this would require two temporary registers. | |
6399 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6400 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6401 | dsll $tempreg,16 | |
6402 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6403 | dsll $tempreg,16 | |
6404 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6405 | If we have a base register, we want | |
6406 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6407 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6408 | dsll $tempreg,16 | |
6409 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6410 | dsll $tempreg,16 | |
6411 | daddu $tempreg,$tempreg,$breg | |
6412 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6413 | |
6caf9ef4 | 6414 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6415 | the same sequence as in 32bit address space. */ |
6416 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6417 | { |
aed1a261 | 6418 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6419 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6420 | { | |
6421 | relax_start (offset_expr.X_add_symbol); | |
6422 | if (breg == 0) | |
6423 | { | |
6424 | macro_build (&offset_expr, s, fmt, treg, | |
6425 | BFD_RELOC_GPREL16, mips_gp_register); | |
6426 | } | |
6427 | else | |
6428 | { | |
6429 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6430 | tempreg, breg, mips_gp_register); | |
6431 | macro_build (&offset_expr, s, fmt, treg, | |
6432 | BFD_RELOC_GPREL16, tempreg); | |
6433 | } | |
6434 | relax_switch (); | |
6435 | } | |
d6bc6245 | 6436 | |
741fe287 | 6437 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6438 | { |
67c0d1eb RS |
6439 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6440 | BFD_RELOC_MIPS_HIGHEST); | |
6441 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6442 | BFD_RELOC_HI16_S); | |
6443 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6444 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6445 | if (breg != 0) |
67c0d1eb RS |
6446 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6447 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6448 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6449 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6450 | tempreg); | |
d6bc6245 TS |
6451 | used_at = 1; |
6452 | } | |
6453 | else | |
6454 | { | |
67c0d1eb RS |
6455 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6456 | BFD_RELOC_MIPS_HIGHEST); | |
6457 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6458 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6459 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6460 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6461 | tempreg, BFD_RELOC_HI16_S); | |
6462 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6463 | if (breg != 0) |
67c0d1eb | 6464 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6465 | tempreg, tempreg, breg); |
67c0d1eb | 6466 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6467 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6468 | } |
6caf9ef4 TS |
6469 | |
6470 | if (mips_relax.sequence) | |
6471 | relax_end (); | |
8fc2e39e | 6472 | break; |
d6bc6245 | 6473 | } |
256ab948 | 6474 | |
252b5132 RH |
6475 | if (breg == 0) |
6476 | { | |
67c0d1eb | 6477 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6478 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6479 | { |
4d7206a2 | 6480 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6481 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6482 | mips_gp_register); | |
4d7206a2 | 6483 | relax_switch (); |
252b5132 | 6484 | } |
67c0d1eb RS |
6485 | macro_build_lui (&offset_expr, tempreg); |
6486 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6487 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6488 | if (mips_relax.sequence) |
6489 | relax_end (); | |
252b5132 RH |
6490 | } |
6491 | else | |
6492 | { | |
67c0d1eb | 6493 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6494 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6495 | { |
4d7206a2 | 6496 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6497 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6498 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6499 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6500 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6501 | relax_switch (); |
252b5132 | 6502 | } |
67c0d1eb RS |
6503 | macro_build_lui (&offset_expr, tempreg); |
6504 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6505 | tempreg, tempreg, breg); |
67c0d1eb | 6506 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6507 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6508 | if (mips_relax.sequence) |
6509 | relax_end (); | |
252b5132 RH |
6510 | } |
6511 | } | |
0a44bf69 | 6512 | else if (!mips_big_got) |
252b5132 | 6513 | { |
ed6fb7bd | 6514 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6515 | |
252b5132 RH |
6516 | /* If this is a reference to an external symbol, we want |
6517 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6518 | nop | |
6519 | <op> $treg,0($tempreg) | |
6520 | Otherwise we want | |
6521 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6522 | nop | |
6523 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6524 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6525 | |
6526 | For NewABI, we want | |
6527 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6528 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6529 | ||
252b5132 RH |
6530 | If there is a base register, we add it to $tempreg before |
6531 | the <op>. If there is a constant, we stick it in the | |
6532 | <op> instruction. We don't handle constants larger than | |
6533 | 16 bits, because we have no way to load the upper 16 bits | |
6534 | (actually, we could handle them for the subset of cases | |
6535 | in which we are not using $at). */ | |
6536 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6537 | if (HAVE_NEWABI) |
6538 | { | |
67c0d1eb RS |
6539 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6540 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6541 | if (breg != 0) |
67c0d1eb | 6542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6543 | tempreg, tempreg, breg); |
67c0d1eb | 6544 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6545 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6546 | break; |
6547 | } | |
252b5132 RH |
6548 | expr1.X_add_number = offset_expr.X_add_number; |
6549 | offset_expr.X_add_number = 0; | |
6550 | if (expr1.X_add_number < -0x8000 | |
6551 | || expr1.X_add_number >= 0x8000) | |
6552 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6553 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6554 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6555 | load_delay_nop (); |
4d7206a2 RS |
6556 | relax_start (offset_expr.X_add_symbol); |
6557 | relax_switch (); | |
67c0d1eb RS |
6558 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6559 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6560 | relax_end (); |
252b5132 | 6561 | if (breg != 0) |
67c0d1eb | 6562 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6563 | tempreg, tempreg, breg); |
67c0d1eb | 6564 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6565 | } |
0a44bf69 | 6566 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6567 | { |
67c0d1eb | 6568 | int gpdelay; |
252b5132 RH |
6569 | |
6570 | /* If this is a reference to an external symbol, we want | |
6571 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6572 | addu $tempreg,$tempreg,$gp | |
6573 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6574 | <op> $treg,0($tempreg) | |
6575 | Otherwise we want | |
6576 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6577 | nop | |
6578 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6579 | <op> $treg,0($tempreg) | |
6580 | If there is a base register, we add it to $tempreg before | |
6581 | the <op>. If there is a constant, we stick it in the | |
6582 | <op> instruction. We don't handle constants larger than | |
6583 | 16 bits, because we have no way to load the upper 16 bits | |
6584 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6585 | in which we are not using $at). */ |
252b5132 RH |
6586 | assert (offset_expr.X_op == O_symbol); |
6587 | expr1.X_add_number = offset_expr.X_add_number; | |
6588 | offset_expr.X_add_number = 0; | |
6589 | if (expr1.X_add_number < -0x8000 | |
6590 | || expr1.X_add_number >= 0x8000) | |
6591 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6592 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6593 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6594 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6595 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6596 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6597 | mips_gp_register); | |
6598 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6599 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6600 | relax_switch (); |
67c0d1eb RS |
6601 | if (gpdelay) |
6602 | macro_build (NULL, "nop", ""); | |
6603 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6604 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6605 | load_delay_nop (); |
67c0d1eb RS |
6606 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6607 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6608 | relax_end (); |
6609 | ||
252b5132 | 6610 | if (breg != 0) |
67c0d1eb | 6611 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6612 | tempreg, tempreg, breg); |
67c0d1eb | 6613 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6614 | } |
0a44bf69 | 6615 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6616 | { |
f5040a92 AO |
6617 | /* If this is a reference to an external symbol, we want |
6618 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6619 | add $tempreg,$tempreg,$gp | |
6620 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6621 | <op> $treg,<ofst>($tempreg) | |
6622 | Otherwise, for local symbols, we want: | |
6623 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6624 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6625 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6626 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6627 | offset_expr.X_add_number = 0; |
6628 | if (expr1.X_add_number < -0x8000 | |
6629 | || expr1.X_add_number >= 0x8000) | |
6630 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6631 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6632 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6633 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6635 | mips_gp_register); | |
6636 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6637 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6638 | if (breg != 0) |
67c0d1eb | 6639 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6640 | tempreg, tempreg, breg); |
67c0d1eb | 6641 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6642 | |
4d7206a2 | 6643 | relax_switch (); |
f5040a92 | 6644 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6645 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6646 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6647 | if (breg != 0) |
67c0d1eb | 6648 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6649 | tempreg, tempreg, breg); |
67c0d1eb | 6650 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6651 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6652 | relax_end (); |
f5040a92 | 6653 | } |
252b5132 RH |
6654 | else |
6655 | abort (); | |
6656 | ||
252b5132 RH |
6657 | break; |
6658 | ||
6659 | case M_LI: | |
6660 | case M_LI_S: | |
67c0d1eb | 6661 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6662 | break; |
252b5132 RH |
6663 | |
6664 | case M_DLI: | |
67c0d1eb | 6665 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6666 | break; |
252b5132 RH |
6667 | |
6668 | case M_LI_SS: | |
6669 | if (imm_expr.X_op == O_constant) | |
6670 | { | |
8fc2e39e | 6671 | used_at = 1; |
67c0d1eb RS |
6672 | load_register (AT, &imm_expr, 0); |
6673 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6674 | break; |
6675 | } | |
6676 | else | |
6677 | { | |
6678 | assert (offset_expr.X_op == O_symbol | |
6679 | && strcmp (segment_name (S_GET_SEGMENT | |
6680 | (offset_expr.X_add_symbol)), | |
6681 | ".lit4") == 0 | |
6682 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6683 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6684 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6685 | break; |
252b5132 RH |
6686 | } |
6687 | ||
6688 | case M_LI_D: | |
ca4e0257 RS |
6689 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6690 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6691 | order 32 bits of the value and the low order 32 bits are either | |
6692 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6693 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6694 | { | |
ca4e0257 | 6695 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6696 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6697 | else |
6698 | { | |
6699 | int hreg, lreg; | |
6700 | ||
6701 | if (target_big_endian) | |
6702 | { | |
6703 | hreg = treg; | |
6704 | lreg = treg + 1; | |
6705 | } | |
6706 | else | |
6707 | { | |
6708 | hreg = treg + 1; | |
6709 | lreg = treg; | |
6710 | } | |
6711 | ||
6712 | if (hreg <= 31) | |
67c0d1eb | 6713 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6714 | if (lreg <= 31) |
6715 | { | |
6716 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6717 | move_register (lreg, 0); |
252b5132 RH |
6718 | else |
6719 | { | |
6720 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6721 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6722 | } |
6723 | } | |
6724 | } | |
8fc2e39e | 6725 | break; |
252b5132 RH |
6726 | } |
6727 | ||
6728 | /* We know that sym is in the .rdata section. First we get the | |
6729 | upper 16 bits of the address. */ | |
6730 | if (mips_pic == NO_PIC) | |
6731 | { | |
67c0d1eb | 6732 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6733 | used_at = 1; |
252b5132 | 6734 | } |
0a44bf69 | 6735 | else |
252b5132 | 6736 | { |
67c0d1eb RS |
6737 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6738 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6739 | used_at = 1; |
252b5132 | 6740 | } |
bdaaa2e1 | 6741 | |
252b5132 | 6742 | /* Now we load the register(s). */ |
ca4e0257 | 6743 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6744 | { |
6745 | used_at = 1; | |
6746 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6747 | } | |
252b5132 RH |
6748 | else |
6749 | { | |
8fc2e39e | 6750 | used_at = 1; |
67c0d1eb | 6751 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6752 | if (treg != RA) |
252b5132 RH |
6753 | { |
6754 | /* FIXME: How in the world do we deal with the possible | |
6755 | overflow here? */ | |
6756 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6757 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6758 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6759 | } |
6760 | } | |
252b5132 RH |
6761 | break; |
6762 | ||
6763 | case M_LI_DD: | |
ca4e0257 RS |
6764 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6765 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6766 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6767 | the value and the low order 32 bits are either zero or in | |
6768 | OFFSET_EXPR. */ | |
252b5132 RH |
6769 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6770 | { | |
8fc2e39e | 6771 | used_at = 1; |
67c0d1eb | 6772 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6773 | if (HAVE_64BIT_FPRS) |
6774 | { | |
6775 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6776 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6777 | } |
252b5132 RH |
6778 | else |
6779 | { | |
67c0d1eb | 6780 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6781 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6782 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6783 | else |
6784 | { | |
6785 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6786 | load_register (AT, &offset_expr, 0); |
6787 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6788 | } |
6789 | } | |
6790 | break; | |
6791 | } | |
6792 | ||
6793 | assert (offset_expr.X_op == O_symbol | |
6794 | && offset_expr.X_add_number == 0); | |
6795 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6796 | if (strcmp (s, ".lit8") == 0) | |
6797 | { | |
e7af610e | 6798 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6799 | { |
67c0d1eb | 6800 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6801 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6802 | break; |
252b5132 | 6803 | } |
c9914766 | 6804 | breg = mips_gp_register; |
252b5132 RH |
6805 | r = BFD_RELOC_MIPS_LITERAL; |
6806 | goto dob; | |
6807 | } | |
6808 | else | |
6809 | { | |
6810 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6811 | used_at = 1; |
0a44bf69 | 6812 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6813 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6814 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6815 | else |
6816 | { | |
6817 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6818 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6819 | } |
bdaaa2e1 | 6820 | |
e7af610e | 6821 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6822 | { |
67c0d1eb RS |
6823 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6824 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6825 | break; |
6826 | } | |
6827 | breg = AT; | |
6828 | r = BFD_RELOC_LO16; | |
6829 | goto dob; | |
6830 | } | |
6831 | ||
6832 | case M_L_DOB: | |
252b5132 RH |
6833 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6834 | to adjust when loading from memory. */ | |
6835 | r = BFD_RELOC_LO16; | |
6836 | dob: | |
e7af610e | 6837 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6838 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6839 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6840 | /* FIXME: A possible overflow which I don't know how to deal |
6841 | with. */ | |
6842 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6843 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6844 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6845 | break; |
6846 | ||
6847 | case M_L_DAB: | |
6848 | /* | |
6849 | * The MIPS assembler seems to check for X_add_number not | |
6850 | * being double aligned and generating: | |
6851 | * lui at,%hi(foo+1) | |
6852 | * addu at,at,v1 | |
6853 | * addiu at,at,%lo(foo+1) | |
6854 | * lwc1 f2,0(at) | |
6855 | * lwc1 f3,4(at) | |
6856 | * But, the resulting address is the same after relocation so why | |
6857 | * generate the extra instruction? | |
6858 | */ | |
bdaaa2e1 | 6859 | /* Itbl support may require additional care here. */ |
252b5132 | 6860 | coproc = 1; |
e7af610e | 6861 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6862 | { |
6863 | s = "ldc1"; | |
6864 | goto ld; | |
6865 | } | |
6866 | ||
6867 | s = "lwc1"; | |
6868 | fmt = "T,o(b)"; | |
6869 | goto ldd_std; | |
6870 | ||
6871 | case M_S_DAB: | |
e7af610e | 6872 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6873 | { |
6874 | s = "sdc1"; | |
6875 | goto st; | |
6876 | } | |
6877 | ||
6878 | s = "swc1"; | |
6879 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6880 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6881 | coproc = 1; |
6882 | goto ldd_std; | |
6883 | ||
6884 | case M_LD_AB: | |
ca4e0257 | 6885 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6886 | { |
6887 | s = "ld"; | |
6888 | goto ld; | |
6889 | } | |
6890 | ||
6891 | s = "lw"; | |
6892 | fmt = "t,o(b)"; | |
6893 | goto ldd_std; | |
6894 | ||
6895 | case M_SD_AB: | |
ca4e0257 | 6896 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6897 | { |
6898 | s = "sd"; | |
6899 | goto st; | |
6900 | } | |
6901 | ||
6902 | s = "sw"; | |
6903 | fmt = "t,o(b)"; | |
6904 | ||
6905 | ldd_std: | |
6906 | if (offset_expr.X_op != O_symbol | |
6907 | && offset_expr.X_op != O_constant) | |
6908 | { | |
6909 | as_bad (_("expression too complex")); | |
6910 | offset_expr.X_op = O_constant; | |
6911 | } | |
6912 | ||
2051e8c4 MR |
6913 | if (HAVE_32BIT_ADDRESSES |
6914 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6915 | { |
6916 | char value [32]; | |
6917 | ||
6918 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6919 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6920 | } |
2051e8c4 | 6921 | |
252b5132 RH |
6922 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6923 | to adjust when loading from memory. We set coproc if we must | |
6924 | load $fn+1 first. */ | |
bdaaa2e1 | 6925 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6926 | if (! target_big_endian) |
6927 | coproc = 0; | |
6928 | ||
6929 | if (mips_pic == NO_PIC | |
6930 | || offset_expr.X_op == O_constant) | |
6931 | { | |
6932 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6933 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6934 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6935 | If we have a base register, we use this |
6936 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6937 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6938 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6939 | If this is not a GP relative symbol, we want |
6940 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6941 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6942 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6943 | If there is a base register, we add it to $at after the | |
6944 | lui instruction. If there is a constant, we always use | |
6945 | the last case. */ | |
39a59cf8 MR |
6946 | if (offset_expr.X_op == O_symbol |
6947 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6948 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6949 | { |
4d7206a2 | 6950 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6951 | if (breg == 0) |
6952 | { | |
c9914766 | 6953 | tempreg = mips_gp_register; |
252b5132 RH |
6954 | } |
6955 | else | |
6956 | { | |
67c0d1eb | 6957 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6958 | AT, breg, mips_gp_register); |
252b5132 | 6959 | tempreg = AT; |
252b5132 RH |
6960 | used_at = 1; |
6961 | } | |
6962 | ||
beae10d5 | 6963 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6964 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6965 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6966 | offset_expr.X_add_number += 4; |
6967 | ||
6968 | /* Set mips_optimize to 2 to avoid inserting an | |
6969 | undesired nop. */ | |
6970 | hold_mips_optimize = mips_optimize; | |
6971 | mips_optimize = 2; | |
beae10d5 | 6972 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6973 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6974 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6975 | mips_optimize = hold_mips_optimize; |
6976 | ||
4d7206a2 | 6977 | relax_switch (); |
252b5132 RH |
6978 | |
6979 | /* We just generated two relocs. When tc_gen_reloc | |
6980 | handles this case, it will skip the first reloc and | |
6981 | handle the second. The second reloc already has an | |
6982 | extra addend of 4, which we added above. We must | |
6983 | subtract it out, and then subtract another 4 to make | |
6984 | the first reloc come out right. The second reloc | |
6985 | will come out right because we are going to add 4 to | |
6986 | offset_expr when we build its instruction below. | |
6987 | ||
6988 | If we have a symbol, then we don't want to include | |
6989 | the offset, because it will wind up being included | |
6990 | when we generate the reloc. */ | |
6991 | ||
6992 | if (offset_expr.X_op == O_constant) | |
6993 | offset_expr.X_add_number -= 8; | |
6994 | else | |
6995 | { | |
6996 | offset_expr.X_add_number = -4; | |
6997 | offset_expr.X_op = O_constant; | |
6998 | } | |
6999 | } | |
8fc2e39e | 7000 | used_at = 1; |
67c0d1eb | 7001 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7002 | if (breg != 0) |
67c0d1eb | 7003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7004 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7005 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7006 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7007 | /* FIXME: How do we handle overflow here? */ |
7008 | offset_expr.X_add_number += 4; | |
beae10d5 | 7009 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7010 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7011 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7012 | if (mips_relax.sequence) |
7013 | relax_end (); | |
bdaaa2e1 | 7014 | } |
0a44bf69 | 7015 | else if (!mips_big_got) |
252b5132 | 7016 | { |
252b5132 RH |
7017 | /* If this is a reference to an external symbol, we want |
7018 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7019 | nop | |
7020 | <op> $treg,0($at) | |
7021 | <op> $treg+1,4($at) | |
7022 | Otherwise we want | |
7023 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7024 | nop | |
7025 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7026 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7027 | If there is a base register we add it to $at before the | |
7028 | lwc1 instructions. If there is a constant we include it | |
7029 | in the lwc1 instructions. */ | |
7030 | used_at = 1; | |
7031 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7032 | if (expr1.X_add_number < -0x8000 |
7033 | || expr1.X_add_number >= 0x8000 - 4) | |
7034 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7035 | load_got_offset (AT, &offset_expr); |
269137b2 | 7036 | load_delay_nop (); |
252b5132 | 7037 | if (breg != 0) |
67c0d1eb | 7038 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7039 | |
7040 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7041 | nop. */ | |
7042 | hold_mips_optimize = mips_optimize; | |
7043 | mips_optimize = 2; | |
4d7206a2 | 7044 | |
beae10d5 | 7045 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7046 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7047 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7048 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7049 | expr1.X_add_number += 4; |
67c0d1eb RS |
7050 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7051 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7052 | relax_switch (); |
67c0d1eb RS |
7053 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7054 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7055 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7056 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7057 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7058 | relax_end (); |
252b5132 | 7059 | |
4d7206a2 | 7060 | mips_optimize = hold_mips_optimize; |
252b5132 | 7061 | } |
0a44bf69 | 7062 | else if (mips_big_got) |
252b5132 | 7063 | { |
67c0d1eb | 7064 | int gpdelay; |
252b5132 RH |
7065 | |
7066 | /* If this is a reference to an external symbol, we want | |
7067 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7068 | addu $at,$at,$gp | |
7069 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7070 | nop | |
7071 | <op> $treg,0($at) | |
7072 | <op> $treg+1,4($at) | |
7073 | Otherwise we want | |
7074 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7075 | nop | |
7076 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7077 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7078 | If there is a base register we add it to $at before the | |
7079 | lwc1 instructions. If there is a constant we include it | |
7080 | in the lwc1 instructions. */ | |
7081 | used_at = 1; | |
7082 | expr1.X_add_number = offset_expr.X_add_number; | |
7083 | offset_expr.X_add_number = 0; | |
7084 | if (expr1.X_add_number < -0x8000 | |
7085 | || expr1.X_add_number >= 0x8000 - 4) | |
7086 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7087 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7088 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7089 | macro_build (&offset_expr, "lui", "t,u", |
7090 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7091 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7092 | AT, AT, mips_gp_register); |
67c0d1eb | 7093 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7094 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7095 | load_delay_nop (); |
252b5132 | 7096 | if (breg != 0) |
67c0d1eb | 7097 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7098 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7099 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7100 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7101 | expr1.X_add_number += 4; |
7102 | ||
7103 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7104 | nop. */ | |
7105 | hold_mips_optimize = mips_optimize; | |
7106 | mips_optimize = 2; | |
beae10d5 | 7107 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7108 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7109 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7110 | mips_optimize = hold_mips_optimize; |
7111 | expr1.X_add_number -= 4; | |
7112 | ||
4d7206a2 RS |
7113 | relax_switch (); |
7114 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7115 | if (gpdelay) |
7116 | macro_build (NULL, "nop", ""); | |
7117 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7118 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7119 | load_delay_nop (); |
252b5132 | 7120 | if (breg != 0) |
67c0d1eb | 7121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7122 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7123 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7124 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7125 | offset_expr.X_add_number += 4; |
252b5132 RH |
7126 | |
7127 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7128 | nop. */ | |
7129 | hold_mips_optimize = mips_optimize; | |
7130 | mips_optimize = 2; | |
beae10d5 | 7131 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7132 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7133 | BFD_RELOC_LO16, AT); | |
252b5132 | 7134 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7135 | relax_end (); |
252b5132 | 7136 | } |
252b5132 RH |
7137 | else |
7138 | abort (); | |
7139 | ||
252b5132 RH |
7140 | break; |
7141 | ||
7142 | case M_LD_OB: | |
7143 | s = "lw"; | |
7144 | goto sd_ob; | |
7145 | case M_SD_OB: | |
7146 | s = "sw"; | |
7147 | sd_ob: | |
ca4e0257 | 7148 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7149 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7150 | offset_expr.X_add_number += 4; |
67c0d1eb | 7151 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7152 | break; |
252b5132 RH |
7153 | |
7154 | /* New code added to support COPZ instructions. | |
7155 | This code builds table entries out of the macros in mip_opcodes. | |
7156 | R4000 uses interlocks to handle coproc delays. | |
7157 | Other chips (like the R3000) require nops to be inserted for delays. | |
7158 | ||
f72c8c98 | 7159 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7160 | In order to fill delay slots for non-interlocked chips, |
7161 | we must have a way to specify delays based on the coprocessor. | |
7162 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7163 | What are the side-effects of the cop instruction? | |
7164 | What cache support might we have and what are its effects? | |
7165 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7166 | What registers are read/set/modified? |
252b5132 RH |
7167 | |
7168 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7169 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7170 | |
7171 | case M_COP0: | |
7172 | s = "c0"; | |
7173 | goto copz; | |
7174 | case M_COP1: | |
7175 | s = "c1"; | |
7176 | goto copz; | |
7177 | case M_COP2: | |
7178 | s = "c2"; | |
7179 | goto copz; | |
7180 | case M_COP3: | |
7181 | s = "c3"; | |
7182 | copz: | |
7183 | /* For now we just do C (same as Cz). The parameter will be | |
7184 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7185 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7186 | break; |
252b5132 | 7187 | |
ea1fb5dc | 7188 | case M_MOVE: |
67c0d1eb | 7189 | move_register (dreg, sreg); |
8fc2e39e | 7190 | break; |
ea1fb5dc | 7191 | |
252b5132 RH |
7192 | #ifdef LOSING_COMPILER |
7193 | default: | |
7194 | /* Try and see if this is a new itbl instruction. | |
7195 | This code builds table entries out of the macros in mip_opcodes. | |
7196 | FIXME: For now we just assemble the expression and pass it's | |
7197 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7198 | We may want to have the assembler assemble this value, |
252b5132 RH |
7199 | so that we gain the assembler's knowledge of delay slots, |
7200 | symbols, etc. | |
7201 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7202 | if (itbl_have_entries |
252b5132 | 7203 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7204 | { |
252b5132 RH |
7205 | s = ip->insn_mo->name; |
7206 | s2 = "cop3"; | |
7207 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7208 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7209 | break; |
beae10d5 | 7210 | } |
252b5132 | 7211 | macro2 (ip); |
8fc2e39e | 7212 | break; |
252b5132 | 7213 | } |
741fe287 | 7214 | if (!mips_opts.at && used_at) |
8fc2e39e | 7215 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7216 | } |
bdaaa2e1 | 7217 | |
252b5132 | 7218 | static void |
17a2f251 | 7219 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7220 | { |
741fe287 MR |
7221 | unsigned int treg, sreg, dreg, breg; |
7222 | unsigned int tempreg; | |
252b5132 | 7223 | int mask; |
252b5132 RH |
7224 | int used_at; |
7225 | expressionS expr1; | |
7226 | const char *s; | |
7227 | const char *s2; | |
7228 | const char *fmt; | |
7229 | int likely = 0; | |
7230 | int dbl = 0; | |
7231 | int coproc = 0; | |
7232 | int lr = 0; | |
7233 | int imm = 0; | |
7234 | int off; | |
7235 | offsetT maxnum; | |
7236 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7237 | |
252b5132 RH |
7238 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7239 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7240 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7241 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7242 | |
252b5132 RH |
7243 | expr1.X_op = O_constant; |
7244 | expr1.X_op_symbol = NULL; | |
7245 | expr1.X_add_symbol = NULL; | |
7246 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7247 | |
252b5132 RH |
7248 | switch (mask) |
7249 | { | |
7250 | #endif /* LOSING_COMPILER */ | |
7251 | ||
7252 | case M_DMUL: | |
7253 | dbl = 1; | |
7254 | case M_MUL: | |
67c0d1eb RS |
7255 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7256 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7257 | break; |
252b5132 RH |
7258 | |
7259 | case M_DMUL_I: | |
7260 | dbl = 1; | |
7261 | case M_MUL_I: | |
7262 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7263 | not trying to be that fancy. GCC should do this for us | |
7264 | anyway. */ | |
8fc2e39e | 7265 | used_at = 1; |
67c0d1eb RS |
7266 | load_register (AT, &imm_expr, dbl); |
7267 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7268 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7269 | break; |
7270 | ||
7271 | case M_DMULO_I: | |
7272 | dbl = 1; | |
7273 | case M_MULO_I: | |
7274 | imm = 1; | |
7275 | goto do_mulo; | |
7276 | ||
7277 | case M_DMULO: | |
7278 | dbl = 1; | |
7279 | case M_MULO: | |
7280 | do_mulo: | |
7d10b47d | 7281 | start_noreorder (); |
8fc2e39e | 7282 | used_at = 1; |
252b5132 | 7283 | if (imm) |
67c0d1eb RS |
7284 | load_register (AT, &imm_expr, dbl); |
7285 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7286 | macro_build (NULL, "mflo", "d", dreg); | |
7287 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7288 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7289 | if (mips_trap) |
67c0d1eb | 7290 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7291 | else |
7292 | { | |
7293 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7294 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7295 | macro_build (NULL, "nop", "", 0); | |
7296 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7297 | } |
7d10b47d | 7298 | end_noreorder (); |
67c0d1eb | 7299 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7300 | break; |
7301 | ||
7302 | case M_DMULOU_I: | |
7303 | dbl = 1; | |
7304 | case M_MULOU_I: | |
7305 | imm = 1; | |
7306 | goto do_mulou; | |
7307 | ||
7308 | case M_DMULOU: | |
7309 | dbl = 1; | |
7310 | case M_MULOU: | |
7311 | do_mulou: | |
7d10b47d | 7312 | start_noreorder (); |
8fc2e39e | 7313 | used_at = 1; |
252b5132 | 7314 | if (imm) |
67c0d1eb RS |
7315 | load_register (AT, &imm_expr, dbl); |
7316 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7317 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7318 | macro_build (NULL, "mfhi", "d", AT); |
7319 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7320 | if (mips_trap) |
67c0d1eb | 7321 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7322 | else |
7323 | { | |
7324 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7325 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7326 | macro_build (NULL, "nop", "", 0); | |
7327 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7328 | } |
7d10b47d | 7329 | end_noreorder (); |
252b5132 RH |
7330 | break; |
7331 | ||
771c7ce4 | 7332 | case M_DROL: |
fef14a42 | 7333 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7334 | { |
7335 | if (dreg == sreg) | |
7336 | { | |
7337 | tempreg = AT; | |
7338 | used_at = 1; | |
7339 | } | |
7340 | else | |
7341 | { | |
7342 | tempreg = dreg; | |
82dd0097 | 7343 | } |
67c0d1eb RS |
7344 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7345 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7346 | break; |
82dd0097 | 7347 | } |
8fc2e39e | 7348 | used_at = 1; |
67c0d1eb RS |
7349 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7350 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7351 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7352 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7353 | break; |
7354 | ||
252b5132 | 7355 | case M_ROL: |
fef14a42 | 7356 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7357 | { |
7358 | if (dreg == sreg) | |
7359 | { | |
7360 | tempreg = AT; | |
7361 | used_at = 1; | |
7362 | } | |
7363 | else | |
7364 | { | |
7365 | tempreg = dreg; | |
82dd0097 | 7366 | } |
67c0d1eb RS |
7367 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7368 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7369 | break; |
82dd0097 | 7370 | } |
8fc2e39e | 7371 | used_at = 1; |
67c0d1eb RS |
7372 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7373 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7374 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7375 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7376 | break; |
7377 | ||
771c7ce4 TS |
7378 | case M_DROL_I: |
7379 | { | |
7380 | unsigned int rot; | |
82dd0097 | 7381 | char *l, *r; |
771c7ce4 TS |
7382 | |
7383 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7384 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7385 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7386 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7387 | { |
7388 | rot = (64 - rot) & 0x3f; | |
7389 | if (rot >= 32) | |
67c0d1eb | 7390 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7391 | else |
67c0d1eb | 7392 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7393 | break; |
60b63b72 | 7394 | } |
483fc7cd | 7395 | if (rot == 0) |
483fc7cd | 7396 | { |
67c0d1eb | 7397 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7398 | break; |
483fc7cd | 7399 | } |
82dd0097 CD |
7400 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7401 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7402 | rot &= 0x1f; | |
8fc2e39e | 7403 | used_at = 1; |
67c0d1eb RS |
7404 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7405 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7406 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7407 | } |
7408 | break; | |
7409 | ||
252b5132 | 7410 | case M_ROL_I: |
771c7ce4 TS |
7411 | { |
7412 | unsigned int rot; | |
7413 | ||
7414 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7415 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7416 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7417 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7418 | { |
67c0d1eb | 7419 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7420 | break; |
60b63b72 | 7421 | } |
483fc7cd | 7422 | if (rot == 0) |
483fc7cd | 7423 | { |
67c0d1eb | 7424 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7425 | break; |
483fc7cd | 7426 | } |
8fc2e39e | 7427 | used_at = 1; |
67c0d1eb RS |
7428 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7429 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7430 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7431 | } |
7432 | break; | |
7433 | ||
7434 | case M_DROR: | |
fef14a42 | 7435 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7436 | { |
67c0d1eb | 7437 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7438 | break; |
82dd0097 | 7439 | } |
8fc2e39e | 7440 | used_at = 1; |
67c0d1eb RS |
7441 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7442 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7443 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7444 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7445 | break; |
7446 | ||
7447 | case M_ROR: | |
fef14a42 | 7448 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7449 | { |
67c0d1eb | 7450 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7451 | break; |
82dd0097 | 7452 | } |
8fc2e39e | 7453 | used_at = 1; |
67c0d1eb RS |
7454 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7455 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7456 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7457 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7458 | break; |
7459 | ||
771c7ce4 TS |
7460 | case M_DROR_I: |
7461 | { | |
7462 | unsigned int rot; | |
82dd0097 | 7463 | char *l, *r; |
771c7ce4 TS |
7464 | |
7465 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7466 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7467 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7468 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7469 | { |
7470 | if (rot >= 32) | |
67c0d1eb | 7471 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7472 | else |
67c0d1eb | 7473 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7474 | break; |
82dd0097 | 7475 | } |
483fc7cd | 7476 | if (rot == 0) |
483fc7cd | 7477 | { |
67c0d1eb | 7478 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7479 | break; |
483fc7cd | 7480 | } |
82dd0097 CD |
7481 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7482 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7483 | rot &= 0x1f; | |
8fc2e39e | 7484 | used_at = 1; |
67c0d1eb RS |
7485 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7486 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7487 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7488 | } |
7489 | break; | |
7490 | ||
252b5132 | 7491 | case M_ROR_I: |
771c7ce4 TS |
7492 | { |
7493 | unsigned int rot; | |
7494 | ||
7495 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7496 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7497 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7498 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7499 | { |
67c0d1eb | 7500 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7501 | break; |
82dd0097 | 7502 | } |
483fc7cd | 7503 | if (rot == 0) |
483fc7cd | 7504 | { |
67c0d1eb | 7505 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7506 | break; |
483fc7cd | 7507 | } |
8fc2e39e | 7508 | used_at = 1; |
67c0d1eb RS |
7509 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7510 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7511 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7512 | } |
252b5132 RH |
7513 | break; |
7514 | ||
7515 | case M_S_DOB: | |
e7af610e | 7516 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7517 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7518 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7519 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7520 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7521 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7522 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7523 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7524 | break; |
252b5132 RH |
7525 | |
7526 | case M_SEQ: | |
7527 | if (sreg == 0) | |
67c0d1eb | 7528 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7529 | else if (treg == 0) |
67c0d1eb | 7530 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7531 | else |
7532 | { | |
67c0d1eb RS |
7533 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7534 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7535 | } |
8fc2e39e | 7536 | break; |
252b5132 RH |
7537 | |
7538 | case M_SEQ_I: | |
7539 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7540 | { | |
67c0d1eb | 7541 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7542 | break; |
252b5132 RH |
7543 | } |
7544 | if (sreg == 0) | |
7545 | { | |
7546 | as_warn (_("Instruction %s: result is always false"), | |
7547 | ip->insn_mo->name); | |
67c0d1eb | 7548 | move_register (dreg, 0); |
8fc2e39e | 7549 | break; |
252b5132 | 7550 | } |
dd3cbb7e NC |
7551 | if (CPU_HAS_SEQ (mips_opts.arch) |
7552 | && -512 <= imm_expr.X_add_number | |
7553 | && imm_expr.X_add_number < 512) | |
7554 | { | |
7555 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
7556 | imm_expr.X_add_number); | |
7557 | break; | |
7558 | } | |
252b5132 RH |
7559 | if (imm_expr.X_op == O_constant |
7560 | && imm_expr.X_add_number >= 0 | |
7561 | && imm_expr.X_add_number < 0x10000) | |
7562 | { | |
67c0d1eb | 7563 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7564 | } |
7565 | else if (imm_expr.X_op == O_constant | |
7566 | && imm_expr.X_add_number > -0x8000 | |
7567 | && imm_expr.X_add_number < 0) | |
7568 | { | |
7569 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7570 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7571 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7572 | } |
dd3cbb7e NC |
7573 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7574 | { | |
7575 | used_at = 1; | |
7576 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7577 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7578 | break; | |
7579 | } | |
252b5132 RH |
7580 | else |
7581 | { | |
67c0d1eb RS |
7582 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7583 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7584 | used_at = 1; |
7585 | } | |
67c0d1eb | 7586 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7587 | break; |
252b5132 RH |
7588 | |
7589 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7590 | s = "slt"; | |
7591 | goto sge; | |
7592 | case M_SGEU: | |
7593 | s = "sltu"; | |
7594 | sge: | |
67c0d1eb RS |
7595 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7596 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7597 | break; |
252b5132 RH |
7598 | |
7599 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7600 | case M_SGEU_I: | |
7601 | if (imm_expr.X_op == O_constant | |
7602 | && imm_expr.X_add_number >= -0x8000 | |
7603 | && imm_expr.X_add_number < 0x8000) | |
7604 | { | |
67c0d1eb RS |
7605 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7606 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7607 | } |
7608 | else | |
7609 | { | |
67c0d1eb RS |
7610 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7611 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7612 | dreg, sreg, AT); | |
252b5132 RH |
7613 | used_at = 1; |
7614 | } | |
67c0d1eb | 7615 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7616 | break; |
252b5132 RH |
7617 | |
7618 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7619 | s = "slt"; | |
7620 | goto sgt; | |
7621 | case M_SGTU: | |
7622 | s = "sltu"; | |
7623 | sgt: | |
67c0d1eb | 7624 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7625 | break; |
252b5132 RH |
7626 | |
7627 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7628 | s = "slt"; | |
7629 | goto sgti; | |
7630 | case M_SGTU_I: | |
7631 | s = "sltu"; | |
7632 | sgti: | |
8fc2e39e | 7633 | used_at = 1; |
67c0d1eb RS |
7634 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7635 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7636 | break; |
7637 | ||
2396cfb9 | 7638 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7639 | s = "slt"; |
7640 | goto sle; | |
7641 | case M_SLEU: | |
7642 | s = "sltu"; | |
7643 | sle: | |
67c0d1eb RS |
7644 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7645 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7646 | break; |
252b5132 | 7647 | |
2396cfb9 | 7648 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7649 | s = "slt"; |
7650 | goto slei; | |
7651 | case M_SLEU_I: | |
7652 | s = "sltu"; | |
7653 | slei: | |
8fc2e39e | 7654 | used_at = 1; |
67c0d1eb RS |
7655 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7656 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7657 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7658 | break; |
7659 | ||
7660 | case M_SLT_I: | |
7661 | if (imm_expr.X_op == O_constant | |
7662 | && imm_expr.X_add_number >= -0x8000 | |
7663 | && imm_expr.X_add_number < 0x8000) | |
7664 | { | |
67c0d1eb | 7665 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7666 | break; |
252b5132 | 7667 | } |
8fc2e39e | 7668 | used_at = 1; |
67c0d1eb RS |
7669 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7670 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7671 | break; |
7672 | ||
7673 | case M_SLTU_I: | |
7674 | if (imm_expr.X_op == O_constant | |
7675 | && imm_expr.X_add_number >= -0x8000 | |
7676 | && imm_expr.X_add_number < 0x8000) | |
7677 | { | |
67c0d1eb | 7678 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7679 | BFD_RELOC_LO16); |
8fc2e39e | 7680 | break; |
252b5132 | 7681 | } |
8fc2e39e | 7682 | used_at = 1; |
67c0d1eb RS |
7683 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7684 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7685 | break; |
7686 | ||
7687 | case M_SNE: | |
7688 | if (sreg == 0) | |
67c0d1eb | 7689 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7690 | else if (treg == 0) |
67c0d1eb | 7691 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7692 | else |
7693 | { | |
67c0d1eb RS |
7694 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7695 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7696 | } |
8fc2e39e | 7697 | break; |
252b5132 RH |
7698 | |
7699 | case M_SNE_I: | |
7700 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7701 | { | |
67c0d1eb | 7702 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7703 | break; |
252b5132 RH |
7704 | } |
7705 | if (sreg == 0) | |
7706 | { | |
7707 | as_warn (_("Instruction %s: result is always true"), | |
7708 | ip->insn_mo->name); | |
67c0d1eb RS |
7709 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7710 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7711 | break; |
252b5132 | 7712 | } |
dd3cbb7e NC |
7713 | if (CPU_HAS_SEQ (mips_opts.arch) |
7714 | && -512 <= imm_expr.X_add_number | |
7715 | && imm_expr.X_add_number < 512) | |
7716 | { | |
7717 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
7718 | imm_expr.X_add_number); | |
7719 | break; | |
7720 | } | |
252b5132 RH |
7721 | if (imm_expr.X_op == O_constant |
7722 | && imm_expr.X_add_number >= 0 | |
7723 | && imm_expr.X_add_number < 0x10000) | |
7724 | { | |
67c0d1eb | 7725 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7726 | } |
7727 | else if (imm_expr.X_op == O_constant | |
7728 | && imm_expr.X_add_number > -0x8000 | |
7729 | && imm_expr.X_add_number < 0) | |
7730 | { | |
7731 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7732 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7733 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7734 | } |
dd3cbb7e NC |
7735 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7736 | { | |
7737 | used_at = 1; | |
7738 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7739 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7740 | break; | |
7741 | } | |
252b5132 RH |
7742 | else |
7743 | { | |
67c0d1eb RS |
7744 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7745 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7746 | used_at = 1; |
7747 | } | |
67c0d1eb | 7748 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7749 | break; |
252b5132 RH |
7750 | |
7751 | case M_DSUB_I: | |
7752 | dbl = 1; | |
7753 | case M_SUB_I: | |
7754 | if (imm_expr.X_op == O_constant | |
7755 | && imm_expr.X_add_number > -0x8000 | |
7756 | && imm_expr.X_add_number <= 0x8000) | |
7757 | { | |
7758 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7759 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7760 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7761 | break; |
252b5132 | 7762 | } |
8fc2e39e | 7763 | used_at = 1; |
67c0d1eb RS |
7764 | load_register (AT, &imm_expr, dbl); |
7765 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7766 | break; |
7767 | ||
7768 | case M_DSUBU_I: | |
7769 | dbl = 1; | |
7770 | case M_SUBU_I: | |
7771 | if (imm_expr.X_op == O_constant | |
7772 | && imm_expr.X_add_number > -0x8000 | |
7773 | && imm_expr.X_add_number <= 0x8000) | |
7774 | { | |
7775 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7776 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7777 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7778 | break; |
252b5132 | 7779 | } |
8fc2e39e | 7780 | used_at = 1; |
67c0d1eb RS |
7781 | load_register (AT, &imm_expr, dbl); |
7782 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7783 | break; |
7784 | ||
7785 | case M_TEQ_I: | |
7786 | s = "teq"; | |
7787 | goto trap; | |
7788 | case M_TGE_I: | |
7789 | s = "tge"; | |
7790 | goto trap; | |
7791 | case M_TGEU_I: | |
7792 | s = "tgeu"; | |
7793 | goto trap; | |
7794 | case M_TLT_I: | |
7795 | s = "tlt"; | |
7796 | goto trap; | |
7797 | case M_TLTU_I: | |
7798 | s = "tltu"; | |
7799 | goto trap; | |
7800 | case M_TNE_I: | |
7801 | s = "tne"; | |
7802 | trap: | |
8fc2e39e | 7803 | used_at = 1; |
67c0d1eb RS |
7804 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7805 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7806 | break; |
7807 | ||
252b5132 | 7808 | case M_TRUNCWS: |
43841e91 | 7809 | case M_TRUNCWD: |
e7af610e | 7810 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7811 | used_at = 1; |
252b5132 RH |
7812 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7813 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7814 | ||
7815 | /* | |
7816 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7817 | * or is there a reason for it? | |
7818 | */ | |
7d10b47d | 7819 | start_noreorder (); |
67c0d1eb RS |
7820 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7821 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7822 | macro_build (NULL, "nop", ""); | |
252b5132 | 7823 | expr1.X_add_number = 3; |
67c0d1eb | 7824 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7825 | expr1.X_add_number = 2; |
67c0d1eb RS |
7826 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7827 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7828 | macro_build (NULL, "nop", ""); | |
7829 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7830 | dreg, sreg); | |
7831 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7832 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7833 | end_noreorder (); |
252b5132 RH |
7834 | break; |
7835 | ||
7836 | case M_ULH: | |
7837 | s = "lb"; | |
7838 | goto ulh; | |
7839 | case M_ULHU: | |
7840 | s = "lbu"; | |
7841 | ulh: | |
8fc2e39e | 7842 | used_at = 1; |
252b5132 RH |
7843 | if (offset_expr.X_add_number >= 0x7fff) |
7844 | as_bad (_("operand overflow")); | |
252b5132 | 7845 | if (! target_big_endian) |
f9419b05 | 7846 | ++offset_expr.X_add_number; |
67c0d1eb | 7847 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7848 | if (! target_big_endian) |
f9419b05 | 7849 | --offset_expr.X_add_number; |
252b5132 | 7850 | else |
f9419b05 | 7851 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7852 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7853 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7854 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7855 | break; |
7856 | ||
7857 | case M_ULD: | |
7858 | s = "ldl"; | |
7859 | s2 = "ldr"; | |
7860 | off = 7; | |
7861 | goto ulw; | |
7862 | case M_ULW: | |
7863 | s = "lwl"; | |
7864 | s2 = "lwr"; | |
7865 | off = 3; | |
7866 | ulw: | |
7867 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7868 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7869 | if (treg != breg) |
7870 | tempreg = treg; | |
7871 | else | |
8fc2e39e TS |
7872 | { |
7873 | used_at = 1; | |
7874 | tempreg = AT; | |
7875 | } | |
252b5132 RH |
7876 | if (! target_big_endian) |
7877 | offset_expr.X_add_number += off; | |
67c0d1eb | 7878 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7879 | if (! target_big_endian) |
7880 | offset_expr.X_add_number -= off; | |
7881 | else | |
7882 | offset_expr.X_add_number += off; | |
67c0d1eb | 7883 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7884 | |
7885 | /* If necessary, move the result in tempreg the final destination. */ | |
7886 | if (treg == tempreg) | |
8fc2e39e | 7887 | break; |
af22f5b2 | 7888 | /* Protect second load's delay slot. */ |
017315e4 | 7889 | load_delay_nop (); |
67c0d1eb | 7890 | move_register (treg, tempreg); |
af22f5b2 | 7891 | break; |
252b5132 RH |
7892 | |
7893 | case M_ULD_A: | |
7894 | s = "ldl"; | |
7895 | s2 = "ldr"; | |
7896 | off = 7; | |
7897 | goto ulwa; | |
7898 | case M_ULW_A: | |
7899 | s = "lwl"; | |
7900 | s2 = "lwr"; | |
7901 | off = 3; | |
7902 | ulwa: | |
d6bc6245 | 7903 | used_at = 1; |
67c0d1eb | 7904 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7905 | if (breg != 0) |
67c0d1eb | 7906 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7907 | if (! target_big_endian) |
7908 | expr1.X_add_number = off; | |
7909 | else | |
7910 | expr1.X_add_number = 0; | |
67c0d1eb | 7911 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7912 | if (! target_big_endian) |
7913 | expr1.X_add_number = 0; | |
7914 | else | |
7915 | expr1.X_add_number = off; | |
67c0d1eb | 7916 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7917 | break; |
7918 | ||
7919 | case M_ULH_A: | |
7920 | case M_ULHU_A: | |
d6bc6245 | 7921 | used_at = 1; |
67c0d1eb | 7922 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7923 | if (breg != 0) |
67c0d1eb | 7924 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7925 | if (target_big_endian) |
7926 | expr1.X_add_number = 0; | |
67c0d1eb | 7927 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7928 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7929 | if (target_big_endian) |
7930 | expr1.X_add_number = 1; | |
7931 | else | |
7932 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7933 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7934 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7935 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7936 | break; |
7937 | ||
7938 | case M_USH: | |
8fc2e39e | 7939 | used_at = 1; |
252b5132 RH |
7940 | if (offset_expr.X_add_number >= 0x7fff) |
7941 | as_bad (_("operand overflow")); | |
7942 | if (target_big_endian) | |
f9419b05 | 7943 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7944 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7945 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7946 | if (target_big_endian) |
f9419b05 | 7947 | --offset_expr.X_add_number; |
252b5132 | 7948 | else |
f9419b05 | 7949 | ++offset_expr.X_add_number; |
67c0d1eb | 7950 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7951 | break; |
7952 | ||
7953 | case M_USD: | |
7954 | s = "sdl"; | |
7955 | s2 = "sdr"; | |
7956 | off = 7; | |
7957 | goto usw; | |
7958 | case M_USW: | |
7959 | s = "swl"; | |
7960 | s2 = "swr"; | |
7961 | off = 3; | |
7962 | usw: | |
7963 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7964 | as_bad (_("operand overflow")); | |
7965 | if (! target_big_endian) | |
7966 | offset_expr.X_add_number += off; | |
67c0d1eb | 7967 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7968 | if (! target_big_endian) |
7969 | offset_expr.X_add_number -= off; | |
7970 | else | |
7971 | offset_expr.X_add_number += off; | |
67c0d1eb | 7972 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7973 | break; |
252b5132 RH |
7974 | |
7975 | case M_USD_A: | |
7976 | s = "sdl"; | |
7977 | s2 = "sdr"; | |
7978 | off = 7; | |
7979 | goto uswa; | |
7980 | case M_USW_A: | |
7981 | s = "swl"; | |
7982 | s2 = "swr"; | |
7983 | off = 3; | |
7984 | uswa: | |
d6bc6245 | 7985 | used_at = 1; |
67c0d1eb | 7986 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7987 | if (breg != 0) |
67c0d1eb | 7988 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7989 | if (! target_big_endian) |
7990 | expr1.X_add_number = off; | |
7991 | else | |
7992 | expr1.X_add_number = 0; | |
67c0d1eb | 7993 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7994 | if (! target_big_endian) |
7995 | expr1.X_add_number = 0; | |
7996 | else | |
7997 | expr1.X_add_number = off; | |
67c0d1eb | 7998 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7999 | break; |
8000 | ||
8001 | case M_USH_A: | |
d6bc6245 | 8002 | used_at = 1; |
67c0d1eb | 8003 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8004 | if (breg != 0) |
67c0d1eb | 8005 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8006 | if (! target_big_endian) |
8007 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8008 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8009 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
8010 | if (! target_big_endian) |
8011 | expr1.X_add_number = 1; | |
8012 | else | |
8013 | expr1.X_add_number = 0; | |
67c0d1eb | 8014 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8015 | if (! target_big_endian) |
8016 | expr1.X_add_number = 0; | |
8017 | else | |
8018 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8019 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8020 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8021 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8022 | break; |
8023 | ||
8024 | default: | |
8025 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8026 | are added dynamically. */ |
252b5132 RH |
8027 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8028 | break; | |
8029 | } | |
741fe287 | 8030 | if (!mips_opts.at && used_at) |
8fc2e39e | 8031 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8032 | } |
8033 | ||
8034 | /* Implement macros in mips16 mode. */ | |
8035 | ||
8036 | static void | |
17a2f251 | 8037 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8038 | { |
8039 | int mask; | |
8040 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8041 | expressionS expr1; |
8042 | int dbl; | |
8043 | const char *s, *s2, *s3; | |
8044 | ||
8045 | mask = ip->insn_mo->mask; | |
8046 | ||
bf12938e RS |
8047 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8048 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8049 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8050 | |
252b5132 RH |
8051 | expr1.X_op = O_constant; |
8052 | expr1.X_op_symbol = NULL; | |
8053 | expr1.X_add_symbol = NULL; | |
8054 | expr1.X_add_number = 1; | |
8055 | ||
8056 | dbl = 0; | |
8057 | ||
8058 | switch (mask) | |
8059 | { | |
8060 | default: | |
8061 | internalError (); | |
8062 | ||
8063 | case M_DDIV_3: | |
8064 | dbl = 1; | |
8065 | case M_DIV_3: | |
8066 | s = "mflo"; | |
8067 | goto do_div3; | |
8068 | case M_DREM_3: | |
8069 | dbl = 1; | |
8070 | case M_REM_3: | |
8071 | s = "mfhi"; | |
8072 | do_div3: | |
7d10b47d | 8073 | start_noreorder (); |
67c0d1eb | 8074 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8075 | expr1.X_add_number = 2; |
67c0d1eb RS |
8076 | macro_build (&expr1, "bnez", "x,p", yreg); |
8077 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8078 | |
252b5132 RH |
8079 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8080 | since that causes an overflow. We should do that as well, | |
8081 | but I don't see how to do the comparisons without a temporary | |
8082 | register. */ | |
7d10b47d | 8083 | end_noreorder (); |
67c0d1eb | 8084 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8085 | break; |
8086 | ||
8087 | case M_DIVU_3: | |
8088 | s = "divu"; | |
8089 | s2 = "mflo"; | |
8090 | goto do_divu3; | |
8091 | case M_REMU_3: | |
8092 | s = "divu"; | |
8093 | s2 = "mfhi"; | |
8094 | goto do_divu3; | |
8095 | case M_DDIVU_3: | |
8096 | s = "ddivu"; | |
8097 | s2 = "mflo"; | |
8098 | goto do_divu3; | |
8099 | case M_DREMU_3: | |
8100 | s = "ddivu"; | |
8101 | s2 = "mfhi"; | |
8102 | do_divu3: | |
7d10b47d | 8103 | start_noreorder (); |
67c0d1eb | 8104 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8105 | expr1.X_add_number = 2; |
67c0d1eb RS |
8106 | macro_build (&expr1, "bnez", "x,p", yreg); |
8107 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8108 | end_noreorder (); |
67c0d1eb | 8109 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8110 | break; |
8111 | ||
8112 | case M_DMUL: | |
8113 | dbl = 1; | |
8114 | case M_MUL: | |
67c0d1eb RS |
8115 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8116 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8117 | break; |
252b5132 RH |
8118 | |
8119 | case M_DSUBU_I: | |
8120 | dbl = 1; | |
8121 | goto do_subu; | |
8122 | case M_SUBU_I: | |
8123 | do_subu: | |
8124 | if (imm_expr.X_op != O_constant) | |
8125 | as_bad (_("Unsupported large constant")); | |
8126 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8127 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8128 | break; |
8129 | ||
8130 | case M_SUBU_I_2: | |
8131 | if (imm_expr.X_op != O_constant) | |
8132 | as_bad (_("Unsupported large constant")); | |
8133 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8134 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8135 | break; |
8136 | ||
8137 | case M_DSUBU_I_2: | |
8138 | if (imm_expr.X_op != O_constant) | |
8139 | as_bad (_("Unsupported large constant")); | |
8140 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8141 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8142 | break; |
8143 | ||
8144 | case M_BEQ: | |
8145 | s = "cmp"; | |
8146 | s2 = "bteqz"; | |
8147 | goto do_branch; | |
8148 | case M_BNE: | |
8149 | s = "cmp"; | |
8150 | s2 = "btnez"; | |
8151 | goto do_branch; | |
8152 | case M_BLT: | |
8153 | s = "slt"; | |
8154 | s2 = "btnez"; | |
8155 | goto do_branch; | |
8156 | case M_BLTU: | |
8157 | s = "sltu"; | |
8158 | s2 = "btnez"; | |
8159 | goto do_branch; | |
8160 | case M_BLE: | |
8161 | s = "slt"; | |
8162 | s2 = "bteqz"; | |
8163 | goto do_reverse_branch; | |
8164 | case M_BLEU: | |
8165 | s = "sltu"; | |
8166 | s2 = "bteqz"; | |
8167 | goto do_reverse_branch; | |
8168 | case M_BGE: | |
8169 | s = "slt"; | |
8170 | s2 = "bteqz"; | |
8171 | goto do_branch; | |
8172 | case M_BGEU: | |
8173 | s = "sltu"; | |
8174 | s2 = "bteqz"; | |
8175 | goto do_branch; | |
8176 | case M_BGT: | |
8177 | s = "slt"; | |
8178 | s2 = "btnez"; | |
8179 | goto do_reverse_branch; | |
8180 | case M_BGTU: | |
8181 | s = "sltu"; | |
8182 | s2 = "btnez"; | |
8183 | ||
8184 | do_reverse_branch: | |
8185 | tmp = xreg; | |
8186 | xreg = yreg; | |
8187 | yreg = tmp; | |
8188 | ||
8189 | do_branch: | |
67c0d1eb RS |
8190 | macro_build (NULL, s, "x,y", xreg, yreg); |
8191 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8192 | break; |
8193 | ||
8194 | case M_BEQ_I: | |
8195 | s = "cmpi"; | |
8196 | s2 = "bteqz"; | |
8197 | s3 = "x,U"; | |
8198 | goto do_branch_i; | |
8199 | case M_BNE_I: | |
8200 | s = "cmpi"; | |
8201 | s2 = "btnez"; | |
8202 | s3 = "x,U"; | |
8203 | goto do_branch_i; | |
8204 | case M_BLT_I: | |
8205 | s = "slti"; | |
8206 | s2 = "btnez"; | |
8207 | s3 = "x,8"; | |
8208 | goto do_branch_i; | |
8209 | case M_BLTU_I: | |
8210 | s = "sltiu"; | |
8211 | s2 = "btnez"; | |
8212 | s3 = "x,8"; | |
8213 | goto do_branch_i; | |
8214 | case M_BLE_I: | |
8215 | s = "slti"; | |
8216 | s2 = "btnez"; | |
8217 | s3 = "x,8"; | |
8218 | goto do_addone_branch_i; | |
8219 | case M_BLEU_I: | |
8220 | s = "sltiu"; | |
8221 | s2 = "btnez"; | |
8222 | s3 = "x,8"; | |
8223 | goto do_addone_branch_i; | |
8224 | case M_BGE_I: | |
8225 | s = "slti"; | |
8226 | s2 = "bteqz"; | |
8227 | s3 = "x,8"; | |
8228 | goto do_branch_i; | |
8229 | case M_BGEU_I: | |
8230 | s = "sltiu"; | |
8231 | s2 = "bteqz"; | |
8232 | s3 = "x,8"; | |
8233 | goto do_branch_i; | |
8234 | case M_BGT_I: | |
8235 | s = "slti"; | |
8236 | s2 = "bteqz"; | |
8237 | s3 = "x,8"; | |
8238 | goto do_addone_branch_i; | |
8239 | case M_BGTU_I: | |
8240 | s = "sltiu"; | |
8241 | s2 = "bteqz"; | |
8242 | s3 = "x,8"; | |
8243 | ||
8244 | do_addone_branch_i: | |
8245 | if (imm_expr.X_op != O_constant) | |
8246 | as_bad (_("Unsupported large constant")); | |
8247 | ++imm_expr.X_add_number; | |
8248 | ||
8249 | do_branch_i: | |
67c0d1eb RS |
8250 | macro_build (&imm_expr, s, s3, xreg); |
8251 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8252 | break; |
8253 | ||
8254 | case M_ABS: | |
8255 | expr1.X_add_number = 0; | |
67c0d1eb | 8256 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8257 | if (xreg != yreg) |
67c0d1eb | 8258 | move_register (xreg, yreg); |
252b5132 | 8259 | expr1.X_add_number = 2; |
67c0d1eb RS |
8260 | macro_build (&expr1, "bteqz", "p"); |
8261 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8262 | } |
8263 | } | |
8264 | ||
8265 | /* For consistency checking, verify that all bits are specified either | |
8266 | by the match/mask part of the instruction definition, or by the | |
8267 | operand list. */ | |
8268 | static int | |
17a2f251 | 8269 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8270 | { |
8271 | const char *p = opc->args; | |
8272 | char c; | |
8273 | unsigned long used_bits = opc->mask; | |
8274 | ||
8275 | if ((used_bits & opc->match) != opc->match) | |
8276 | { | |
8277 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8278 | opc->name, opc->args); | |
8279 | return 0; | |
8280 | } | |
8281 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8282 | while (*p) | |
8283 | switch (c = *p++) | |
8284 | { | |
8285 | case ',': break; | |
8286 | case '(': break; | |
8287 | case ')': break; | |
af7ee8bf CD |
8288 | case '+': |
8289 | switch (c = *p++) | |
8290 | { | |
9bcd4f99 TS |
8291 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8292 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8293 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8294 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8295 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8296 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8297 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8298 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8299 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8300 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8301 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8302 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8303 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8304 | case 'I': break; | |
ef2e4d86 CF |
8305 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8306 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8307 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8308 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8309 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8310 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8311 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8312 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8313 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8314 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
8315 | ||
af7ee8bf CD |
8316 | default: |
8317 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8318 | c, opc->name, opc->args); | |
8319 | return 0; | |
8320 | } | |
8321 | break; | |
252b5132 RH |
8322 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8323 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8324 | case 'A': break; | |
4372b673 | 8325 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8326 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8327 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8328 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8329 | case 'F': break; | |
8330 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8331 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8332 | case 'I': break; |
e972090a | 8333 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8334 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8335 | case 'L': break; |
8336 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8337 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8338 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8339 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8340 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8341 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8342 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8343 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8344 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8345 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8346 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8347 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8348 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8349 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8350 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8351 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8352 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8353 | case 'f': break; | |
8354 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8355 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8356 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8357 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8358 | case 'l': break; | |
8359 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8360 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8361 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8362 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8363 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8364 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8365 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8366 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8367 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8368 | case 'x': break; | |
8369 | case 'z': break; | |
8370 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8371 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8372 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8373 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8374 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8375 | case '[': break; | |
8376 | case ']': break; | |
8b082fb1 | 8377 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8378 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8379 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8380 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8381 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8382 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8383 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8384 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8385 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8386 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8387 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8388 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8389 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8390 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8391 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8392 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8393 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8394 | default: |
8395 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8396 | c, opc->name, opc->args); | |
8397 | return 0; | |
8398 | } | |
8399 | #undef USE_BITS | |
8400 | if (used_bits != 0xffffffff) | |
8401 | { | |
8402 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8403 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8404 | return 0; | |
8405 | } | |
8406 | return 1; | |
8407 | } | |
8408 | ||
9bcd4f99 TS |
8409 | /* UDI immediates. */ |
8410 | struct mips_immed { | |
8411 | char type; | |
8412 | unsigned int shift; | |
8413 | unsigned long mask; | |
8414 | const char * desc; | |
8415 | }; | |
8416 | ||
8417 | static const struct mips_immed mips_immed[] = { | |
8418 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8419 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8420 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8421 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8422 | { 0,0,0,0 } | |
8423 | }; | |
8424 | ||
7455baf8 TS |
8425 | /* Check whether an odd floating-point register is allowed. */ |
8426 | static int | |
8427 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8428 | { | |
8429 | const char *s = insn->name; | |
8430 | ||
8431 | if (insn->pinfo == INSN_MACRO) | |
8432 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8433 | return 1; | |
8434 | ||
8435 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8436 | { | |
8437 | /* Allow odd registers for single-precision ops. */ | |
8438 | switch (insn->pinfo & (FP_S | FP_D)) | |
8439 | { | |
8440 | case FP_S: | |
8441 | case 0: | |
8442 | return 1; /* both single precision - ok */ | |
8443 | case FP_D: | |
8444 | return 0; /* both double precision - fail */ | |
8445 | default: | |
8446 | break; | |
8447 | } | |
8448 | ||
8449 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8450 | s = strchr (insn->name, '.'); | |
8451 | if (argnum == 2) | |
8452 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8453 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8454 | } | |
8455 | ||
8456 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8457 | if ((insn->pinfo & FP_S) | |
8458 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8459 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8460 | return 1; | |
8461 | ||
8462 | return 0; | |
8463 | } | |
8464 | ||
252b5132 RH |
8465 | /* This routine assembles an instruction into its binary format. As a |
8466 | side effect, it sets one of the global variables imm_reloc or | |
8467 | offset_reloc to the type of relocation to do if one of the operands | |
8468 | is an address expression. */ | |
8469 | ||
8470 | static void | |
17a2f251 | 8471 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8472 | { |
8473 | char *s; | |
8474 | const char *args; | |
43841e91 | 8475 | char c = 0; |
252b5132 RH |
8476 | struct mips_opcode *insn; |
8477 | char *argsStart; | |
8478 | unsigned int regno; | |
8479 | unsigned int lastregno = 0; | |
af7ee8bf | 8480 | unsigned int lastpos = 0; |
071742cf | 8481 | unsigned int limlo, limhi; |
252b5132 RH |
8482 | char *s_reset; |
8483 | char save_c = 0; | |
74cd071d | 8484 | offsetT min_range, max_range; |
707bfff6 TS |
8485 | int argnum; |
8486 | unsigned int rtype; | |
252b5132 RH |
8487 | |
8488 | insn_error = NULL; | |
8489 | ||
8490 | /* If the instruction contains a '.', we first try to match an instruction | |
8491 | including the '.'. Then we try again without the '.'. */ | |
8492 | insn = NULL; | |
3882b010 | 8493 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8494 | continue; |
8495 | ||
8496 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8497 | the call to hash_find. Save the character we replaced just in case we | |
8498 | have to re-parse the instruction. */ | |
3882b010 | 8499 | if (ISSPACE (*s)) |
252b5132 RH |
8500 | { |
8501 | save_c = *s; | |
8502 | *s++ = '\0'; | |
8503 | } | |
bdaaa2e1 | 8504 | |
252b5132 RH |
8505 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8506 | ||
8507 | /* If we didn't find the instruction in the opcode table, try again, but | |
8508 | this time with just the instruction up to, but not including the | |
8509 | first '.'. */ | |
8510 | if (insn == NULL) | |
8511 | { | |
bdaaa2e1 | 8512 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8513 | if (save_c) |
8514 | *(--s) = save_c; | |
8515 | ||
8516 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8517 | for (s = str; |
8518 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8519 | ++s) | |
252b5132 RH |
8520 | continue; |
8521 | ||
8522 | /* If we did not find a '.', then we can quit now. */ | |
8523 | if (*s != '.') | |
8524 | { | |
8525 | insn_error = "unrecognized opcode"; | |
8526 | return; | |
8527 | } | |
8528 | ||
8529 | /* Lookup the instruction in the hash table. */ | |
8530 | *s++ = '\0'; | |
8531 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8532 | { | |
8533 | insn_error = "unrecognized opcode"; | |
8534 | return; | |
8535 | } | |
252b5132 RH |
8536 | } |
8537 | ||
8538 | argsStart = s; | |
8539 | for (;;) | |
8540 | { | |
b34976b6 | 8541 | bfd_boolean ok; |
252b5132 RH |
8542 | |
8543 | assert (strcmp (insn->name, str) == 0); | |
8544 | ||
037b32b9 | 8545 | ok = is_opcode_valid (insn, FALSE); |
252b5132 RH |
8546 | if (! ok) |
8547 | { | |
8548 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8549 | && strcmp (insn->name, insn[1].name) == 0) | |
8550 | { | |
8551 | ++insn; | |
8552 | continue; | |
8553 | } | |
252b5132 | 8554 | else |
beae10d5 | 8555 | { |
268f6bed L |
8556 | if (!insn_error) |
8557 | { | |
8558 | static char buf[100]; | |
fef14a42 TS |
8559 | sprintf (buf, |
8560 | _("opcode not supported on this processor: %s (%s)"), | |
8561 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8562 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8563 | insn_error = buf; |
8564 | } | |
8565 | if (save_c) | |
8566 | *(--s) = save_c; | |
2bd7f1f3 | 8567 | return; |
252b5132 | 8568 | } |
252b5132 RH |
8569 | } |
8570 | ||
1e915849 | 8571 | create_insn (ip, insn); |
268f6bed | 8572 | insn_error = NULL; |
707bfff6 | 8573 | argnum = 1; |
252b5132 RH |
8574 | for (args = insn->args;; ++args) |
8575 | { | |
deec1734 CD |
8576 | int is_mdmx; |
8577 | ||
ad8d3bb3 | 8578 | s += strspn (s, " \t"); |
deec1734 | 8579 | is_mdmx = 0; |
252b5132 RH |
8580 | switch (*args) |
8581 | { | |
8582 | case '\0': /* end of args */ | |
8583 | if (*s == '\0') | |
8584 | return; | |
8585 | break; | |
8586 | ||
8b082fb1 TS |
8587 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8588 | my_getExpression (&imm_expr, s); | |
8589 | check_absolute_expr (ip, &imm_expr); | |
8590 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8591 | && (unsigned long) imm_expr.X_add_number != 3) | |
8592 | { | |
8593 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8594 | (unsigned long) imm_expr.X_add_number); | |
8595 | } | |
8596 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8597 | imm_expr.X_op = O_absent; | |
8598 | s = expr_end; | |
8599 | continue; | |
8600 | ||
74cd071d CF |
8601 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8602 | my_getExpression (&imm_expr, s); | |
8603 | check_absolute_expr (ip, &imm_expr); | |
8604 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8605 | { | |
a9e24354 TS |
8606 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8607 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8608 | } |
a9e24354 | 8609 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8610 | imm_expr.X_op = O_absent; |
8611 | s = expr_end; | |
8612 | continue; | |
8613 | ||
8614 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8615 | my_getExpression (&imm_expr, s); | |
8616 | check_absolute_expr (ip, &imm_expr); | |
8617 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8618 | { | |
a9e24354 TS |
8619 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8620 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8621 | } |
a9e24354 | 8622 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8623 | imm_expr.X_op = O_absent; |
8624 | s = expr_end; | |
8625 | continue; | |
8626 | ||
8627 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8628 | my_getExpression (&imm_expr, s); | |
8629 | check_absolute_expr (ip, &imm_expr); | |
8630 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8631 | { | |
a9e24354 TS |
8632 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8633 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8634 | } |
a9e24354 | 8635 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8636 | imm_expr.X_op = O_absent; |
8637 | s = expr_end; | |
8638 | continue; | |
8639 | ||
8640 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8641 | my_getExpression (&imm_expr, s); | |
8642 | check_absolute_expr (ip, &imm_expr); | |
8643 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8644 | { | |
a9e24354 TS |
8645 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8646 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8647 | } |
a9e24354 | 8648 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8649 | imm_expr.X_op = O_absent; |
8650 | s = expr_end; | |
8651 | continue; | |
8652 | ||
8653 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8654 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8655 | s[3] >= '0' && s[3] <= '3') | |
8656 | { | |
8657 | regno = s[3] - '0'; | |
8658 | s += 4; | |
a9e24354 | 8659 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8660 | continue; |
8661 | } | |
8662 | else | |
8663 | as_bad (_("Invalid dsp acc register")); | |
8664 | break; | |
8665 | ||
8666 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8667 | my_getExpression (&imm_expr, s); | |
8668 | check_absolute_expr (ip, &imm_expr); | |
8669 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8670 | { | |
a9e24354 TS |
8671 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8672 | OP_MASK_WRDSP, | |
8673 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8674 | } |
a9e24354 | 8675 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8676 | imm_expr.X_op = O_absent; |
8677 | s = expr_end; | |
8678 | continue; | |
8679 | ||
8680 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8681 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8682 | s[3] >= '0' && s[3] <= '3') | |
8683 | { | |
8684 | regno = s[3] - '0'; | |
8685 | s += 4; | |
a9e24354 | 8686 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8687 | continue; |
8688 | } | |
8689 | else | |
8690 | as_bad (_("Invalid dsp acc register")); | |
8691 | break; | |
8692 | ||
8693 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8694 | my_getExpression (&imm_expr, s); | |
8695 | check_absolute_expr (ip, &imm_expr); | |
8696 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8697 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8698 | if (imm_expr.X_add_number < min_range || | |
8699 | imm_expr.X_add_number > max_range) | |
8700 | { | |
a9e24354 TS |
8701 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8702 | (long) min_range, (long) max_range, | |
8703 | (long) imm_expr.X_add_number); | |
74cd071d | 8704 | } |
a9e24354 | 8705 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8706 | imm_expr.X_op = O_absent; |
8707 | s = expr_end; | |
8708 | continue; | |
8709 | ||
8710 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8711 | my_getExpression (&imm_expr, s); | |
8712 | check_absolute_expr (ip, &imm_expr); | |
8713 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8714 | { | |
a9e24354 TS |
8715 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8716 | OP_MASK_RDDSP, | |
8717 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8718 | } |
a9e24354 | 8719 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8720 | imm_expr.X_op = O_absent; |
8721 | s = expr_end; | |
8722 | continue; | |
8723 | ||
8724 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8725 | my_getExpression (&imm_expr, s); | |
8726 | check_absolute_expr (ip, &imm_expr); | |
8727 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8728 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8729 | if (imm_expr.X_add_number < min_range || | |
8730 | imm_expr.X_add_number > max_range) | |
8731 | { | |
a9e24354 TS |
8732 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8733 | (long) min_range, (long) max_range, | |
8734 | (long) imm_expr.X_add_number); | |
74cd071d | 8735 | } |
a9e24354 | 8736 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8737 | imm_expr.X_op = O_absent; |
8738 | s = expr_end; | |
8739 | continue; | |
8740 | ||
8741 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8742 | my_getExpression (&imm_expr, s); | |
8743 | check_absolute_expr (ip, &imm_expr); | |
8744 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8745 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8746 | if (imm_expr.X_add_number < min_range || | |
8747 | imm_expr.X_add_number > max_range) | |
8748 | { | |
a9e24354 TS |
8749 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8750 | (long) min_range, (long) max_range, | |
8751 | (long) imm_expr.X_add_number); | |
74cd071d | 8752 | } |
a9e24354 | 8753 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8754 | imm_expr.X_op = O_absent; |
8755 | s = expr_end; | |
8756 | continue; | |
8757 | ||
a9e24354 | 8758 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8759 | my_getExpression (&imm_expr, s); |
8760 | check_absolute_expr (ip, &imm_expr); | |
8761 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8762 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8763 | (unsigned long) imm_expr.X_add_number); | |
8764 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8765 | imm_expr.X_op = O_absent; |
8766 | s = expr_end; | |
8767 | continue; | |
8768 | ||
a9e24354 | 8769 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8770 | my_getExpression (&imm_expr, s); |
8771 | check_absolute_expr (ip, &imm_expr); | |
8772 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8773 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8774 | (unsigned long) imm_expr.X_add_number); | |
8775 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8776 | imm_expr.X_op = O_absent; |
8777 | s = expr_end; | |
8778 | continue; | |
8779 | ||
8780 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8781 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8782 | s[3] >= '0' && s[3] <= '3') | |
8783 | { | |
8784 | regno = s[3] - '0'; | |
8785 | s += 4; | |
a9e24354 | 8786 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8787 | continue; |
8788 | } | |
8789 | else | |
8790 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8791 | break; | |
8792 | ||
8793 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8794 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8795 | s[3] >= '0' && s[3] <= '3') | |
8796 | { | |
8797 | regno = s[3] - '0'; | |
8798 | s += 4; | |
a9e24354 | 8799 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8800 | continue; |
8801 | } | |
8802 | else | |
8803 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8804 | break; | |
8805 | ||
252b5132 | 8806 | case ',': |
a339155f | 8807 | ++argnum; |
252b5132 RH |
8808 | if (*s++ == *args) |
8809 | continue; | |
8810 | s--; | |
8811 | switch (*++args) | |
8812 | { | |
8813 | case 'r': | |
8814 | case 'v': | |
bf12938e | 8815 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8816 | continue; |
8817 | ||
8818 | case 'w': | |
bf12938e | 8819 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8820 | continue; |
8821 | ||
252b5132 | 8822 | case 'W': |
bf12938e | 8823 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8824 | continue; |
8825 | ||
8826 | case 'V': | |
bf12938e | 8827 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8828 | continue; |
8829 | } | |
8830 | break; | |
8831 | ||
8832 | case '(': | |
8833 | /* Handle optional base register. | |
8834 | Either the base register is omitted or | |
bdaaa2e1 | 8835 | we must have a left paren. */ |
252b5132 RH |
8836 | /* This is dependent on the next operand specifier |
8837 | is a base register specification. */ | |
8838 | assert (args[1] == 'b' || args[1] == '5' | |
8839 | || args[1] == '-' || args[1] == '4'); | |
8840 | if (*s == '\0') | |
8841 | return; | |
8842 | ||
8843 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8844 | case '[': |
8845 | case ']': | |
252b5132 RH |
8846 | if (*s++ == *args) |
8847 | continue; | |
8848 | break; | |
8849 | ||
af7ee8bf CD |
8850 | case '+': /* Opcode extension character. */ |
8851 | switch (*++args) | |
8852 | { | |
9bcd4f99 TS |
8853 | case '1': /* UDI immediates. */ |
8854 | case '2': | |
8855 | case '3': | |
8856 | case '4': | |
8857 | { | |
8858 | const struct mips_immed *imm = mips_immed; | |
8859 | ||
8860 | while (imm->type && imm->type != *args) | |
8861 | ++imm; | |
8862 | if (! imm->type) | |
8863 | internalError (); | |
8864 | my_getExpression (&imm_expr, s); | |
8865 | check_absolute_expr (ip, &imm_expr); | |
8866 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8867 | { | |
8868 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8869 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8870 | (unsigned long) imm_expr.X_add_number, | |
8871 | (unsigned long) imm_expr.X_add_number); | |
8872 | imm_expr.X_add_number &= imm->mask; | |
8873 | } | |
8874 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8875 | << imm->shift); | |
8876 | imm_expr.X_op = O_absent; | |
8877 | s = expr_end; | |
8878 | } | |
8879 | continue; | |
8880 | ||
071742cf CD |
8881 | case 'A': /* ins/ext position, becomes LSB. */ |
8882 | limlo = 0; | |
8883 | limhi = 31; | |
5f74bc13 CD |
8884 | goto do_lsb; |
8885 | case 'E': | |
8886 | limlo = 32; | |
8887 | limhi = 63; | |
8888 | goto do_lsb; | |
8889 | do_lsb: | |
071742cf CD |
8890 | my_getExpression (&imm_expr, s); |
8891 | check_absolute_expr (ip, &imm_expr); | |
8892 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8893 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8894 | { | |
8895 | as_bad (_("Improper position (%lu)"), | |
8896 | (unsigned long) imm_expr.X_add_number); | |
8897 | imm_expr.X_add_number = limlo; | |
8898 | } | |
8899 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8900 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8901 | imm_expr.X_op = O_absent; |
8902 | s = expr_end; | |
8903 | continue; | |
8904 | ||
8905 | case 'B': /* ins size, becomes MSB. */ | |
8906 | limlo = 1; | |
8907 | limhi = 32; | |
5f74bc13 CD |
8908 | goto do_msb; |
8909 | case 'F': | |
8910 | limlo = 33; | |
8911 | limhi = 64; | |
8912 | goto do_msb; | |
8913 | do_msb: | |
071742cf CD |
8914 | my_getExpression (&imm_expr, s); |
8915 | check_absolute_expr (ip, &imm_expr); | |
8916 | /* Check for negative input so that small negative numbers | |
8917 | will not succeed incorrectly. The checks against | |
8918 | (pos+size) transitively check "size" itself, | |
8919 | assuming that "pos" is reasonable. */ | |
8920 | if ((long) imm_expr.X_add_number < 0 | |
8921 | || ((unsigned long) imm_expr.X_add_number | |
8922 | + lastpos) < limlo | |
8923 | || ((unsigned long) imm_expr.X_add_number | |
8924 | + lastpos) > limhi) | |
8925 | { | |
8926 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8927 | (unsigned long) imm_expr.X_add_number, | |
8928 | (unsigned long) lastpos); | |
8929 | imm_expr.X_add_number = limlo - lastpos; | |
8930 | } | |
bf12938e RS |
8931 | INSERT_OPERAND (INSMSB, *ip, |
8932 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8933 | imm_expr.X_op = O_absent; |
8934 | s = expr_end; | |
8935 | continue; | |
8936 | ||
8937 | case 'C': /* ext size, becomes MSBD. */ | |
8938 | limlo = 1; | |
8939 | limhi = 32; | |
5f74bc13 CD |
8940 | goto do_msbd; |
8941 | case 'G': | |
8942 | limlo = 33; | |
8943 | limhi = 64; | |
8944 | goto do_msbd; | |
8945 | case 'H': | |
8946 | limlo = 33; | |
8947 | limhi = 64; | |
8948 | goto do_msbd; | |
8949 | do_msbd: | |
071742cf CD |
8950 | my_getExpression (&imm_expr, s); |
8951 | check_absolute_expr (ip, &imm_expr); | |
8952 | /* Check for negative input so that small negative numbers | |
8953 | will not succeed incorrectly. The checks against | |
8954 | (pos+size) transitively check "size" itself, | |
8955 | assuming that "pos" is reasonable. */ | |
8956 | if ((long) imm_expr.X_add_number < 0 | |
8957 | || ((unsigned long) imm_expr.X_add_number | |
8958 | + lastpos) < limlo | |
8959 | || ((unsigned long) imm_expr.X_add_number | |
8960 | + lastpos) > limhi) | |
8961 | { | |
8962 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8963 | (unsigned long) imm_expr.X_add_number, | |
8964 | (unsigned long) lastpos); | |
8965 | imm_expr.X_add_number = limlo - lastpos; | |
8966 | } | |
bf12938e | 8967 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8968 | imm_expr.X_op = O_absent; |
8969 | s = expr_end; | |
8970 | continue; | |
af7ee8bf | 8971 | |
bbcc0807 CD |
8972 | case 'D': |
8973 | /* +D is for disassembly only; never match. */ | |
8974 | break; | |
8975 | ||
5f74bc13 CD |
8976 | case 'I': |
8977 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8978 | my_getExpression (&imm2_expr, s); | |
8979 | if (imm2_expr.X_op != O_big | |
8980 | && imm2_expr.X_op != O_constant) | |
8981 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8982 | if (HAVE_32BIT_GPRS) |
8983 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8984 | s = expr_end; |
8985 | continue; | |
8986 | ||
707bfff6 | 8987 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8988 | /* +T is for disassembly only; never match. */ |
8989 | break; | |
8990 | ||
707bfff6 | 8991 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8992 | if (s[0] == '$' && ISDIGIT (s[1])) |
8993 | { | |
8994 | ++s; | |
8995 | regno = 0; | |
8996 | do | |
8997 | { | |
8998 | regno *= 10; | |
8999 | regno += *s - '0'; | |
9000 | ++s; | |
9001 | } | |
9002 | while (ISDIGIT (*s)); | |
9003 | if (regno > 31) | |
9004 | as_bad (_("Invalid register number (%d)"), regno); | |
9005 | else | |
9006 | { | |
a9e24354 | 9007 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9008 | continue; |
9009 | } | |
9010 | } | |
9011 | else | |
9012 | as_bad (_("Invalid coprocessor 0 register number")); | |
9013 | break; | |
9014 | ||
bb35fb24 NC |
9015 | case 'x': |
9016 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9017 | is not in the valid range. */ | |
9018 | my_getExpression (&imm_expr, s); | |
9019 | check_absolute_expr (ip, &imm_expr); | |
9020 | if ((unsigned) imm_expr.X_add_number > 31) | |
9021 | { | |
9022 | as_bad (_("Improper bit index (%lu)"), | |
9023 | (unsigned long) imm_expr.X_add_number); | |
9024 | imm_expr.X_add_number = 0; | |
9025 | } | |
9026 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9027 | imm_expr.X_op = O_absent; | |
9028 | s = expr_end; | |
9029 | continue; | |
9030 | ||
9031 | case 'X': | |
9032 | /* bbit[01] bit index when bbit is used but we generate | |
9033 | bbit[01]32 because the index is over 32. Move to the | |
9034 | next candidate if index is not in the valid range. */ | |
9035 | my_getExpression (&imm_expr, s); | |
9036 | check_absolute_expr (ip, &imm_expr); | |
9037 | if ((unsigned) imm_expr.X_add_number < 32 | |
9038 | || (unsigned) imm_expr.X_add_number > 63) | |
9039 | break; | |
9040 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9041 | imm_expr.X_op = O_absent; | |
9042 | s = expr_end; | |
9043 | continue; | |
9044 | ||
9045 | case 'p': | |
9046 | /* cins, cins32, exts and exts32 position field. Give error | |
9047 | if it's not in the valid range. */ | |
9048 | my_getExpression (&imm_expr, s); | |
9049 | check_absolute_expr (ip, &imm_expr); | |
9050 | if ((unsigned) imm_expr.X_add_number > 31) | |
9051 | { | |
9052 | as_bad (_("Improper position (%lu)"), | |
9053 | (unsigned long) imm_expr.X_add_number); | |
9054 | imm_expr.X_add_number = 0; | |
9055 | } | |
9056 | /* Make the pos explicit to simplify +S. */ | |
9057 | lastpos = imm_expr.X_add_number + 32; | |
9058 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9059 | imm_expr.X_op = O_absent; | |
9060 | s = expr_end; | |
9061 | continue; | |
9062 | ||
9063 | case 'P': | |
9064 | /* cins, cins32, exts and exts32 position field. Move to | |
9065 | the next candidate if it's not in the valid range. */ | |
9066 | my_getExpression (&imm_expr, s); | |
9067 | check_absolute_expr (ip, &imm_expr); | |
9068 | if ((unsigned) imm_expr.X_add_number < 32 | |
9069 | || (unsigned) imm_expr.X_add_number > 63) | |
9070 | break; | |
9071 | lastpos = imm_expr.X_add_number; | |
9072 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9073 | imm_expr.X_op = O_absent; | |
9074 | s = expr_end; | |
9075 | continue; | |
9076 | ||
9077 | case 's': | |
9078 | /* cins and exts length-minus-one field. */ | |
9079 | my_getExpression (&imm_expr, s); | |
9080 | check_absolute_expr (ip, &imm_expr); | |
9081 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9082 | { | |
9083 | as_bad (_("Improper size (%lu)"), | |
9084 | (unsigned long) imm_expr.X_add_number); | |
9085 | imm_expr.X_add_number = 0; | |
9086 | } | |
9087 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9088 | imm_expr.X_op = O_absent; | |
9089 | s = expr_end; | |
9090 | continue; | |
9091 | ||
9092 | case 'S': | |
9093 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9094 | length-minus-one field. */ | |
9095 | my_getExpression (&imm_expr, s); | |
9096 | check_absolute_expr (ip, &imm_expr); | |
9097 | if ((long) imm_expr.X_add_number < 0 | |
9098 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9099 | { | |
9100 | as_bad (_("Improper size (%lu)"), | |
9101 | (unsigned long) imm_expr.X_add_number); | |
9102 | imm_expr.X_add_number = 0; | |
9103 | } | |
9104 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9105 | imm_expr.X_op = O_absent; | |
9106 | s = expr_end; | |
9107 | continue; | |
9108 | ||
dd3cbb7e NC |
9109 | case 'Q': |
9110 | /* seqi/snei immediate field. */ | |
9111 | my_getExpression (&imm_expr, s); | |
9112 | check_absolute_expr (ip, &imm_expr); | |
9113 | if ((long) imm_expr.X_add_number < -512 | |
9114 | || (long) imm_expr.X_add_number >= 512) | |
9115 | { | |
9116 | as_bad (_("Improper immediate (%ld)"), | |
9117 | (long) imm_expr.X_add_number); | |
9118 | imm_expr.X_add_number = 0; | |
9119 | } | |
9120 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9121 | imm_expr.X_op = O_absent; | |
9122 | s = expr_end; | |
9123 | continue; | |
9124 | ||
af7ee8bf CD |
9125 | default: |
9126 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
9127 | *args, insn->name, insn->args); | |
9128 | /* Further processing is fruitless. */ | |
9129 | return; | |
9130 | } | |
9131 | break; | |
9132 | ||
252b5132 RH |
9133 | case '<': /* must be at least one digit */ |
9134 | /* | |
9135 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9136 | * than 31 or less than 0, then the shift amount should be |
9137 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9138 | * We issue a warning and mask out all but the low 5 bits. |
9139 | */ | |
9140 | my_getExpression (&imm_expr, s); | |
9141 | check_absolute_expr (ip, &imm_expr); | |
9142 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9143 | as_warn (_("Improper shift amount (%lu)"), |
9144 | (unsigned long) imm_expr.X_add_number); | |
9145 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9146 | imm_expr.X_op = O_absent; |
9147 | s = expr_end; | |
9148 | continue; | |
9149 | ||
9150 | case '>': /* shift amount minus 32 */ | |
9151 | my_getExpression (&imm_expr, s); | |
9152 | check_absolute_expr (ip, &imm_expr); | |
9153 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9154 | || (unsigned long) imm_expr.X_add_number > 63) | |
9155 | break; | |
bf12938e | 9156 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9157 | imm_expr.X_op = O_absent; |
9158 | s = expr_end; | |
9159 | continue; | |
9160 | ||
252b5132 RH |
9161 | case 'k': /* cache code */ |
9162 | case 'h': /* prefx code */ | |
9163 | my_getExpression (&imm_expr, s); | |
9164 | check_absolute_expr (ip, &imm_expr); | |
9165 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9166 | as_warn (_("Invalid value for `%s' (%lu)"), |
9167 | ip->insn_mo->name, | |
9168 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9169 | if (*args == 'k') |
bf12938e | 9170 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 9171 | else |
bf12938e | 9172 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
9173 | imm_expr.X_op = O_absent; |
9174 | s = expr_end; | |
9175 | continue; | |
9176 | ||
9177 | case 'c': /* break code */ | |
9178 | my_getExpression (&imm_expr, s); | |
9179 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9180 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9181 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9182 | ip->insn_mo->name, | |
bf12938e RS |
9183 | (unsigned long) imm_expr.X_add_number); |
9184 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9185 | imm_expr.X_op = O_absent; |
9186 | s = expr_end; | |
9187 | continue; | |
9188 | ||
9189 | case 'q': /* lower break code */ | |
9190 | my_getExpression (&imm_expr, s); | |
9191 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9192 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9193 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9194 | ip->insn_mo->name, | |
bf12938e RS |
9195 | (unsigned long) imm_expr.X_add_number); |
9196 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9197 | imm_expr.X_op = O_absent; |
9198 | s = expr_end; | |
9199 | continue; | |
9200 | ||
4372b673 | 9201 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9202 | my_getExpression (&imm_expr, s); |
156c2f8b | 9203 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9204 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9205 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9206 | ip->insn_mo->name, | |
793b27f4 | 9207 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9208 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9209 | imm_expr.X_op = O_absent; |
9210 | s = expr_end; | |
9211 | continue; | |
9212 | ||
98d3f06f | 9213 | case 'C': /* Coprocessor code */ |
beae10d5 | 9214 | my_getExpression (&imm_expr, s); |
252b5132 | 9215 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9216 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9217 | { |
793b27f4 TS |
9218 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9219 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9220 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9221 | } |
a9e24354 | 9222 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9223 | imm_expr.X_op = O_absent; |
9224 | s = expr_end; | |
9225 | continue; | |
252b5132 | 9226 | |
4372b673 NC |
9227 | case 'J': /* 19-bit wait code. */ |
9228 | my_getExpression (&imm_expr, s); | |
9229 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9230 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9231 | { |
9232 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9233 | (unsigned long) imm_expr.X_add_number); | |
9234 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9235 | } | |
bf12938e | 9236 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9237 | imm_expr.X_op = O_absent; |
9238 | s = expr_end; | |
9239 | continue; | |
9240 | ||
707bfff6 | 9241 | case 'P': /* Performance register. */ |
beae10d5 | 9242 | my_getExpression (&imm_expr, s); |
252b5132 | 9243 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9244 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9245 | as_warn (_("Invalid performance register (%lu)"), |
9246 | (unsigned long) imm_expr.X_add_number); | |
9247 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9248 | imm_expr.X_op = O_absent; |
9249 | s = expr_end; | |
9250 | continue; | |
252b5132 | 9251 | |
707bfff6 TS |
9252 | case 'G': /* Coprocessor destination register. */ |
9253 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9254 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9255 | else | |
9256 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9257 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9258 | if (ok) |
9259 | { | |
9260 | lastregno = regno; | |
9261 | continue; | |
9262 | } | |
9263 | else | |
9264 | break; | |
9265 | ||
252b5132 RH |
9266 | case 'b': /* base register */ |
9267 | case 'd': /* destination register */ | |
9268 | case 's': /* source register */ | |
9269 | case 't': /* target register */ | |
9270 | case 'r': /* both target and source */ | |
9271 | case 'v': /* both dest and source */ | |
9272 | case 'w': /* both dest and target */ | |
9273 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9274 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9275 | case 'x': /* ignore register name */ |
9276 | case 'z': /* must be zero register */ | |
4372b673 | 9277 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9278 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9279 | s_reset = s; |
9280 | if (*args == 'E' || *args == 'K') | |
9281 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9282 | else | |
9283 | { | |
9284 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9285 | if (regno == AT && mips_opts.at) |
9286 | { | |
9287 | if (mips_opts.at == ATREG) | |
9288 | as_warn (_("used $at without \".set noat\"")); | |
9289 | else | |
9290 | as_warn (_("used $%u with \".set at=$%u\""), | |
9291 | regno, mips_opts.at); | |
9292 | } | |
707bfff6 TS |
9293 | } |
9294 | if (ok) | |
252b5132 | 9295 | { |
252b5132 RH |
9296 | c = *args; |
9297 | if (*s == ' ') | |
f9419b05 | 9298 | ++s; |
252b5132 RH |
9299 | if (args[1] != *s) |
9300 | { | |
9301 | if (c == 'r' || c == 'v' || c == 'w') | |
9302 | { | |
9303 | regno = lastregno; | |
9304 | s = s_reset; | |
f9419b05 | 9305 | ++args; |
252b5132 RH |
9306 | } |
9307 | } | |
9308 | /* 'z' only matches $0. */ | |
9309 | if (c == 'z' && regno != 0) | |
9310 | break; | |
9311 | ||
e7c604dd CM |
9312 | if (c == 's' && !strcmp (ip->insn_mo->name, "jalr")) |
9313 | { | |
9314 | if (regno == lastregno) | |
9315 | { | |
9316 | insn_error = _("source and destinationations must be different"); | |
9317 | continue; | |
9318 | } | |
9319 | if (regno == 31 && lastregno == 0) | |
9320 | { | |
9321 | insn_error = _("a destination register must be supplied"); | |
9322 | continue; | |
9323 | } | |
9324 | } | |
bdaaa2e1 KH |
9325 | /* Now that we have assembled one operand, we use the args string |
9326 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9327 | switch (c) |
9328 | { | |
9329 | case 'r': | |
9330 | case 's': | |
9331 | case 'v': | |
9332 | case 'b': | |
bf12938e | 9333 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9334 | break; |
9335 | case 'd': | |
9336 | case 'G': | |
af7ee8bf | 9337 | case 'K': |
ef2e4d86 | 9338 | case 'g': |
bf12938e | 9339 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9340 | break; |
4372b673 | 9341 | case 'U': |
bf12938e RS |
9342 | INSERT_OPERAND (RD, *ip, regno); |
9343 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9344 | break; |
252b5132 RH |
9345 | case 'w': |
9346 | case 't': | |
9347 | case 'E': | |
bf12938e | 9348 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9349 | break; |
9350 | case 'x': | |
9351 | /* This case exists because on the r3000 trunc | |
9352 | expands into a macro which requires a gp | |
9353 | register. On the r6000 or r4000 it is | |
9354 | assembled into a single instruction which | |
9355 | ignores the register. Thus the insn version | |
9356 | is MIPS_ISA2 and uses 'x', and the macro | |
9357 | version is MIPS_ISA1 and uses 't'. */ | |
9358 | break; | |
9359 | case 'z': | |
9360 | /* This case is for the div instruction, which | |
9361 | acts differently if the destination argument | |
9362 | is $0. This only matches $0, and is checked | |
9363 | outside the switch. */ | |
9364 | break; | |
9365 | case 'D': | |
9366 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9367 | break; | |
9368 | /* What about all other operands like 'i', which | |
9369 | can be specified in the opcode table? */ | |
9370 | } | |
9371 | lastregno = regno; | |
9372 | continue; | |
9373 | } | |
252b5132 RH |
9374 | switch (*args++) |
9375 | { | |
9376 | case 'r': | |
9377 | case 'v': | |
bf12938e | 9378 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9379 | continue; |
9380 | case 'w': | |
bf12938e | 9381 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9382 | continue; |
9383 | } | |
9384 | break; | |
9385 | ||
deec1734 CD |
9386 | case 'O': /* MDMX alignment immediate constant. */ |
9387 | my_getExpression (&imm_expr, s); | |
9388 | check_absolute_expr (ip, &imm_expr); | |
9389 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9390 | as_warn ("Improper align amount (%ld), using low bits", |
9391 | (long) imm_expr.X_add_number); | |
9392 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9393 | imm_expr.X_op = O_absent; |
9394 | s = expr_end; | |
9395 | continue; | |
9396 | ||
9397 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9398 | if (s[0] != '$') | |
9399 | { | |
9400 | /* MDMX Immediate. */ | |
9401 | my_getExpression (&imm_expr, s); | |
9402 | check_absolute_expr (ip, &imm_expr); | |
9403 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9404 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9405 | (long) imm_expr.X_add_number); | |
9406 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9407 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9408 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9409 | else | |
9410 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9411 | imm_expr.X_op = O_absent; |
9412 | s = expr_end; | |
9413 | continue; | |
9414 | } | |
9415 | /* Not MDMX Immediate. Fall through. */ | |
9416 | case 'X': /* MDMX destination register. */ | |
9417 | case 'Y': /* MDMX source register. */ | |
9418 | case 'Z': /* MDMX target register. */ | |
9419 | is_mdmx = 1; | |
252b5132 RH |
9420 | case 'D': /* floating point destination register */ |
9421 | case 'S': /* floating point source register */ | |
9422 | case 'T': /* floating point target register */ | |
9423 | case 'R': /* floating point source register */ | |
9424 | case 'V': | |
9425 | case 'W': | |
707bfff6 TS |
9426 | rtype = RTYPE_FPU; |
9427 | if (is_mdmx | |
9428 | || (mips_opts.ase_mdmx | |
9429 | && (ip->insn_mo->pinfo & FP_D) | |
9430 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9431 | | INSN_COPROC_MEMORY_DELAY | |
9432 | | INSN_LOAD_COPROC_DELAY | |
9433 | | INSN_LOAD_MEMORY_DELAY | |
9434 | | INSN_STORE_MEMORY)))) | |
9435 | rtype |= RTYPE_VEC; | |
252b5132 | 9436 | s_reset = s; |
707bfff6 | 9437 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9438 | { |
252b5132 | 9439 | if ((regno & 1) != 0 |
ca4e0257 | 9440 | && HAVE_32BIT_FPRS |
7455baf8 | 9441 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9442 | as_warn (_("Float register should be even, was %d"), |
9443 | regno); | |
9444 | ||
9445 | c = *args; | |
9446 | if (*s == ' ') | |
f9419b05 | 9447 | ++s; |
252b5132 RH |
9448 | if (args[1] != *s) |
9449 | { | |
9450 | if (c == 'V' || c == 'W') | |
9451 | { | |
9452 | regno = lastregno; | |
9453 | s = s_reset; | |
f9419b05 | 9454 | ++args; |
252b5132 RH |
9455 | } |
9456 | } | |
9457 | switch (c) | |
9458 | { | |
9459 | case 'D': | |
deec1734 | 9460 | case 'X': |
bf12938e | 9461 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9462 | break; |
9463 | case 'V': | |
9464 | case 'S': | |
deec1734 | 9465 | case 'Y': |
bf12938e | 9466 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9467 | break; |
deec1734 CD |
9468 | case 'Q': |
9469 | /* This is like 'Z', but also needs to fix the MDMX | |
9470 | vector/scalar select bits. Note that the | |
9471 | scalar immediate case is handled above. */ | |
9472 | if (*s == '[') | |
9473 | { | |
9474 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9475 | int max_el = (is_qh ? 3 : 7); | |
9476 | s++; | |
9477 | my_getExpression(&imm_expr, s); | |
9478 | check_absolute_expr (ip, &imm_expr); | |
9479 | s = expr_end; | |
9480 | if (imm_expr.X_add_number > max_el) | |
9481 | as_bad(_("Bad element selector %ld"), | |
9482 | (long) imm_expr.X_add_number); | |
9483 | imm_expr.X_add_number &= max_el; | |
9484 | ip->insn_opcode |= (imm_expr.X_add_number | |
9485 | << (OP_SH_VSEL + | |
9486 | (is_qh ? 2 : 1))); | |
01a3f561 | 9487 | imm_expr.X_op = O_absent; |
deec1734 CD |
9488 | if (*s != ']') |
9489 | as_warn(_("Expecting ']' found '%s'"), s); | |
9490 | else | |
9491 | s++; | |
9492 | } | |
9493 | else | |
9494 | { | |
9495 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9496 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9497 | << OP_SH_VSEL); | |
9498 | else | |
9499 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9500 | OP_SH_VSEL); | |
9501 | } | |
9502 | /* Fall through */ | |
252b5132 RH |
9503 | case 'W': |
9504 | case 'T': | |
deec1734 | 9505 | case 'Z': |
bf12938e | 9506 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9507 | break; |
9508 | case 'R': | |
bf12938e | 9509 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9510 | break; |
9511 | } | |
9512 | lastregno = regno; | |
9513 | continue; | |
9514 | } | |
9515 | ||
252b5132 RH |
9516 | switch (*args++) |
9517 | { | |
9518 | case 'V': | |
bf12938e | 9519 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9520 | continue; |
9521 | case 'W': | |
bf12938e | 9522 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9523 | continue; |
9524 | } | |
9525 | break; | |
9526 | ||
9527 | case 'I': | |
9528 | my_getExpression (&imm_expr, s); | |
9529 | if (imm_expr.X_op != O_big | |
9530 | && imm_expr.X_op != O_constant) | |
9531 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9532 | if (HAVE_32BIT_GPRS) |
9533 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9534 | s = expr_end; |
9535 | continue; | |
9536 | ||
9537 | case 'A': | |
9538 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9539 | normalize_address_expr (&offset_expr); |
f6688943 | 9540 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9541 | s = expr_end; |
9542 | continue; | |
9543 | ||
9544 | case 'F': | |
9545 | case 'L': | |
9546 | case 'f': | |
9547 | case 'l': | |
9548 | { | |
9549 | int f64; | |
ca4e0257 | 9550 | int using_gprs; |
252b5132 RH |
9551 | char *save_in; |
9552 | char *err; | |
9553 | unsigned char temp[8]; | |
9554 | int len; | |
9555 | unsigned int length; | |
9556 | segT seg; | |
9557 | subsegT subseg; | |
9558 | char *p; | |
9559 | ||
9560 | /* These only appear as the last operand in an | |
9561 | instruction, and every instruction that accepts | |
9562 | them in any variant accepts them in all variants. | |
9563 | This means we don't have to worry about backing out | |
9564 | any changes if the instruction does not match. | |
9565 | ||
9566 | The difference between them is the size of the | |
9567 | floating point constant and where it goes. For 'F' | |
9568 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9569 | is 32 bits. Where the constant is placed is based | |
9570 | on how the MIPS assembler does things: | |
9571 | F -- .rdata | |
9572 | L -- .lit8 | |
9573 | f -- immediate value | |
9574 | l -- .lit4 | |
9575 | ||
9576 | The .lit4 and .lit8 sections are only used if | |
9577 | permitted by the -G argument. | |
9578 | ||
ca4e0257 RS |
9579 | The code below needs to know whether the target register |
9580 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9581 | 'F' are used with GPR-based instructions and 'l' and | |
9582 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9583 | |
9584 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9585 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9586 | |
9587 | save_in = input_line_pointer; | |
9588 | input_line_pointer = s; | |
9589 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9590 | length = len; | |
9591 | s = input_line_pointer; | |
9592 | input_line_pointer = save_in; | |
9593 | if (err != NULL && *err != '\0') | |
9594 | { | |
9595 | as_bad (_("Bad floating point constant: %s"), err); | |
9596 | memset (temp, '\0', sizeof temp); | |
9597 | length = f64 ? 8 : 4; | |
9598 | } | |
9599 | ||
156c2f8b | 9600 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9601 | |
9602 | if (*args == 'f' | |
9603 | || (*args == 'l' | |
3e722fb5 | 9604 | && (g_switch_value < 4 |
252b5132 RH |
9605 | || (temp[0] == 0 && temp[1] == 0) |
9606 | || (temp[2] == 0 && temp[3] == 0)))) | |
9607 | { | |
9608 | imm_expr.X_op = O_constant; | |
9609 | if (! target_big_endian) | |
9610 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9611 | else | |
9612 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9613 | } | |
9614 | else if (length > 4 | |
119d663a | 9615 | && ! mips_disable_float_construction |
ca4e0257 RS |
9616 | /* Constants can only be constructed in GPRs and |
9617 | copied to FPRs if the GPRs are at least as wide | |
9618 | as the FPRs. Force the constant into memory if | |
9619 | we are using 64-bit FPRs but the GPRs are only | |
9620 | 32 bits wide. */ | |
9621 | && (using_gprs | |
9622 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9623 | && ((temp[0] == 0 && temp[1] == 0) |
9624 | || (temp[2] == 0 && temp[3] == 0)) | |
9625 | && ((temp[4] == 0 && temp[5] == 0) | |
9626 | || (temp[6] == 0 && temp[7] == 0))) | |
9627 | { | |
ca4e0257 RS |
9628 | /* The value is simple enough to load with a couple of |
9629 | instructions. If using 32-bit registers, set | |
9630 | imm_expr to the high order 32 bits and offset_expr to | |
9631 | the low order 32 bits. Otherwise, set imm_expr to | |
9632 | the entire 64 bit constant. */ | |
9633 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9634 | { |
9635 | imm_expr.X_op = O_constant; | |
9636 | offset_expr.X_op = O_constant; | |
9637 | if (! target_big_endian) | |
9638 | { | |
9639 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9640 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9641 | } | |
9642 | else | |
9643 | { | |
9644 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9645 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9646 | } | |
9647 | if (offset_expr.X_add_number == 0) | |
9648 | offset_expr.X_op = O_absent; | |
9649 | } | |
9650 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9651 | { | |
9652 | imm_expr.X_op = O_constant; | |
9653 | if (! target_big_endian) | |
9654 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9655 | else | |
9656 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9657 | } | |
9658 | else | |
9659 | { | |
9660 | imm_expr.X_op = O_big; | |
9661 | imm_expr.X_add_number = 4; | |
9662 | if (! target_big_endian) | |
9663 | { | |
9664 | generic_bignum[0] = bfd_getl16 (temp); | |
9665 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9666 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9667 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9668 | } | |
9669 | else | |
9670 | { | |
9671 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9672 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9673 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9674 | generic_bignum[3] = bfd_getb16 (temp); | |
9675 | } | |
9676 | } | |
9677 | } | |
9678 | else | |
9679 | { | |
9680 | const char *newname; | |
9681 | segT new_seg; | |
9682 | ||
9683 | /* Switch to the right section. */ | |
9684 | seg = now_seg; | |
9685 | subseg = now_subseg; | |
9686 | switch (*args) | |
9687 | { | |
9688 | default: /* unused default case avoids warnings. */ | |
9689 | case 'L': | |
9690 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9691 | if (g_switch_value >= 8) |
252b5132 RH |
9692 | newname = ".lit8"; |
9693 | break; | |
9694 | case 'F': | |
3e722fb5 | 9695 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9696 | break; |
9697 | case 'l': | |
4d0d148d | 9698 | assert (g_switch_value >= 4); |
252b5132 RH |
9699 | newname = ".lit4"; |
9700 | break; | |
9701 | } | |
9702 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9703 | if (IS_ELF) |
252b5132 RH |
9704 | bfd_set_section_flags (stdoutput, new_seg, |
9705 | (SEC_ALLOC | |
9706 | | SEC_LOAD | |
9707 | | SEC_READONLY | |
9708 | | SEC_DATA)); | |
9709 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9710 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9711 | record_alignment (new_seg, 4); |
9712 | else | |
9713 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9714 | if (seg == now_seg) | |
9715 | as_bad (_("Can't use floating point insn in this section")); | |
9716 | ||
9717 | /* Set the argument to the current address in the | |
9718 | section. */ | |
9719 | offset_expr.X_op = O_symbol; | |
9720 | offset_expr.X_add_symbol = | |
9721 | symbol_new ("L0\001", now_seg, | |
9722 | (valueT) frag_now_fix (), frag_now); | |
9723 | offset_expr.X_add_number = 0; | |
9724 | ||
9725 | /* Put the floating point number into the section. */ | |
9726 | p = frag_more ((int) length); | |
9727 | memcpy (p, temp, length); | |
9728 | ||
9729 | /* Switch back to the original section. */ | |
9730 | subseg_set (seg, subseg); | |
9731 | } | |
9732 | } | |
9733 | continue; | |
9734 | ||
9735 | case 'i': /* 16 bit unsigned immediate */ | |
9736 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9737 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9738 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9739 | { |
9740 | int more; | |
5e0116d5 RS |
9741 | offsetT minval, maxval; |
9742 | ||
9743 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9744 | && strcmp (insn->name, insn[1].name) == 0); | |
9745 | ||
9746 | /* If the expression was written as an unsigned number, | |
9747 | only treat it as signed if there are no more | |
9748 | alternatives. */ | |
9749 | if (more | |
9750 | && *args == 'j' | |
9751 | && sizeof (imm_expr.X_add_number) <= 4 | |
9752 | && imm_expr.X_op == O_constant | |
9753 | && imm_expr.X_add_number < 0 | |
9754 | && imm_expr.X_unsigned | |
9755 | && HAVE_64BIT_GPRS) | |
9756 | break; | |
9757 | ||
9758 | /* For compatibility with older assemblers, we accept | |
9759 | 0x8000-0xffff as signed 16-bit numbers when only | |
9760 | signed numbers are allowed. */ | |
9761 | if (*args == 'i') | |
9762 | minval = 0, maxval = 0xffff; | |
9763 | else if (more) | |
9764 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9765 | else |
5e0116d5 RS |
9766 | minval = -0x8000, maxval = 0xffff; |
9767 | ||
9768 | if (imm_expr.X_op != O_constant | |
9769 | || imm_expr.X_add_number < minval | |
9770 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9771 | { |
9772 | if (more) | |
9773 | break; | |
2ae7e77b AH |
9774 | if (imm_expr.X_op == O_constant |
9775 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9776 | as_bad (_("expression out of range")); |
252b5132 RH |
9777 | } |
9778 | } | |
9779 | s = expr_end; | |
9780 | continue; | |
9781 | ||
9782 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9783 | /* Check whether there is only a single bracketed expression |
9784 | left. If so, it must be the base register and the | |
9785 | constant must be zero. */ | |
9786 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9787 | { | |
9788 | offset_expr.X_op = O_constant; | |
9789 | offset_expr.X_add_number = 0; | |
9790 | continue; | |
9791 | } | |
252b5132 RH |
9792 | |
9793 | /* If this value won't fit into a 16 bit offset, then go | |
9794 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9795 | code pattern. */ |
5e0116d5 | 9796 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9797 | && (offset_expr.X_op != O_constant |
9798 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9799 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9800 | break; |
9801 | ||
252b5132 RH |
9802 | s = expr_end; |
9803 | continue; | |
9804 | ||
9805 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9806 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9807 | my_getExpression (&offset_expr, s); |
9808 | s = expr_end; | |
9809 | continue; | |
9810 | ||
9811 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9812 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9813 | && imm_expr.X_op == O_constant | |
9814 | && (imm_expr.X_add_number < 0 | |
9815 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9816 | as_bad (_("lui expression not in range 0..65535")); |
9817 | s = expr_end; | |
9818 | continue; | |
9819 | ||
9820 | case 'a': /* 26 bit address */ | |
9821 | my_getExpression (&offset_expr, s); | |
9822 | s = expr_end; | |
f6688943 | 9823 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9824 | continue; |
9825 | ||
9826 | case 'N': /* 3 bit branch condition code */ | |
9827 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9828 | rtype = RTYPE_CCC; |
9829 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9830 | rtype |= RTYPE_FCC; | |
9831 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9832 | break; |
30c378fd CD |
9833 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9834 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9835 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9836 | && (regno & 1) != 0) | |
9837 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9838 | str, regno); | |
9839 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9840 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9841 | && (regno & 3) != 0) | |
9842 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9843 | str, regno); | |
252b5132 | 9844 | if (*args == 'N') |
bf12938e | 9845 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9846 | else |
bf12938e | 9847 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9848 | continue; |
252b5132 | 9849 | |
156c2f8b NC |
9850 | case 'H': |
9851 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9852 | s += 2; | |
3882b010 | 9853 | if (ISDIGIT (*s)) |
156c2f8b NC |
9854 | { |
9855 | c = 0; | |
9856 | do | |
9857 | { | |
9858 | c *= 10; | |
9859 | c += *s - '0'; | |
9860 | ++s; | |
9861 | } | |
3882b010 | 9862 | while (ISDIGIT (*s)); |
156c2f8b NC |
9863 | } |
9864 | else | |
9865 | c = 8; /* Invalid sel value. */ | |
9866 | ||
9867 | if (c > 7) | |
9868 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9869 | ip->insn_opcode |= c; | |
9870 | continue; | |
9871 | ||
60b63b72 RS |
9872 | case 'e': |
9873 | /* Must be at least one digit. */ | |
9874 | my_getExpression (&imm_expr, s); | |
9875 | check_absolute_expr (ip, &imm_expr); | |
9876 | ||
9877 | if ((unsigned long) imm_expr.X_add_number | |
9878 | > (unsigned long) OP_MASK_VECBYTE) | |
9879 | { | |
9880 | as_bad (_("bad byte vector index (%ld)"), | |
9881 | (long) imm_expr.X_add_number); | |
9882 | imm_expr.X_add_number = 0; | |
9883 | } | |
9884 | ||
bf12938e | 9885 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9886 | imm_expr.X_op = O_absent; |
9887 | s = expr_end; | |
9888 | continue; | |
9889 | ||
9890 | case '%': | |
9891 | my_getExpression (&imm_expr, s); | |
9892 | check_absolute_expr (ip, &imm_expr); | |
9893 | ||
9894 | if ((unsigned long) imm_expr.X_add_number | |
9895 | > (unsigned long) OP_MASK_VECALIGN) | |
9896 | { | |
9897 | as_bad (_("bad byte vector index (%ld)"), | |
9898 | (long) imm_expr.X_add_number); | |
9899 | imm_expr.X_add_number = 0; | |
9900 | } | |
9901 | ||
bf12938e | 9902 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9903 | imm_expr.X_op = O_absent; |
9904 | s = expr_end; | |
9905 | continue; | |
9906 | ||
252b5132 RH |
9907 | default: |
9908 | as_bad (_("bad char = '%c'\n"), *args); | |
9909 | internalError (); | |
9910 | } | |
9911 | break; | |
9912 | } | |
9913 | /* Args don't match. */ | |
9914 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9915 | !strcmp (insn->name, insn[1].name)) | |
9916 | { | |
9917 | ++insn; | |
9918 | s = argsStart; | |
268f6bed | 9919 | insn_error = _("illegal operands"); |
252b5132 RH |
9920 | continue; |
9921 | } | |
268f6bed L |
9922 | if (save_c) |
9923 | *(--s) = save_c; | |
252b5132 RH |
9924 | insn_error = _("illegal operands"); |
9925 | return; | |
9926 | } | |
9927 | } | |
9928 | ||
0499d65b TS |
9929 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9930 | ||
252b5132 RH |
9931 | /* This routine assembles an instruction into its binary format when |
9932 | assembling for the mips16. As a side effect, it sets one of the | |
9933 | global variables imm_reloc or offset_reloc to the type of | |
9934 | relocation to do if one of the operands is an address expression. | |
9935 | It also sets mips16_small and mips16_ext if the user explicitly | |
9936 | requested a small or extended instruction. */ | |
9937 | ||
9938 | static void | |
17a2f251 | 9939 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9940 | { |
9941 | char *s; | |
9942 | const char *args; | |
9943 | struct mips_opcode *insn; | |
9944 | char *argsstart; | |
9945 | unsigned int regno; | |
9946 | unsigned int lastregno = 0; | |
9947 | char *s_reset; | |
d6f16593 | 9948 | size_t i; |
252b5132 RH |
9949 | |
9950 | insn_error = NULL; | |
9951 | ||
b34976b6 AM |
9952 | mips16_small = FALSE; |
9953 | mips16_ext = FALSE; | |
252b5132 | 9954 | |
3882b010 | 9955 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9956 | ; |
9957 | switch (*s) | |
9958 | { | |
9959 | case '\0': | |
9960 | break; | |
9961 | ||
9962 | case ' ': | |
9963 | *s++ = '\0'; | |
9964 | break; | |
9965 | ||
9966 | case '.': | |
9967 | if (s[1] == 't' && s[2] == ' ') | |
9968 | { | |
9969 | *s = '\0'; | |
b34976b6 | 9970 | mips16_small = TRUE; |
252b5132 RH |
9971 | s += 3; |
9972 | break; | |
9973 | } | |
9974 | else if (s[1] == 'e' && s[2] == ' ') | |
9975 | { | |
9976 | *s = '\0'; | |
b34976b6 | 9977 | mips16_ext = TRUE; |
252b5132 RH |
9978 | s += 3; |
9979 | break; | |
9980 | } | |
9981 | /* Fall through. */ | |
9982 | default: | |
9983 | insn_error = _("unknown opcode"); | |
9984 | return; | |
9985 | } | |
9986 | ||
9987 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9988 | mips16_small = TRUE; |
252b5132 RH |
9989 | |
9990 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9991 | { | |
9992 | insn_error = _("unrecognized opcode"); | |
9993 | return; | |
9994 | } | |
9995 | ||
9996 | argsstart = s; | |
9997 | for (;;) | |
9998 | { | |
9b3f89ee TS |
9999 | bfd_boolean ok; |
10000 | ||
252b5132 RH |
10001 | assert (strcmp (insn->name, str) == 0); |
10002 | ||
037b32b9 | 10003 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10004 | if (! ok) |
10005 | { | |
10006 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10007 | && strcmp (insn->name, insn[1].name) == 0) | |
10008 | { | |
10009 | ++insn; | |
10010 | continue; | |
10011 | } | |
10012 | else | |
10013 | { | |
10014 | if (!insn_error) | |
10015 | { | |
10016 | static char buf[100]; | |
10017 | sprintf (buf, | |
10018 | _("opcode not supported on this processor: %s (%s)"), | |
10019 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10020 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10021 | insn_error = buf; | |
10022 | } | |
10023 | return; | |
10024 | } | |
10025 | } | |
10026 | ||
1e915849 | 10027 | create_insn (ip, insn); |
252b5132 | 10028 | imm_expr.X_op = O_absent; |
f6688943 TS |
10029 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10030 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10031 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10032 | imm2_expr.X_op = O_absent; |
252b5132 | 10033 | offset_expr.X_op = O_absent; |
f6688943 TS |
10034 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10035 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10036 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10037 | for (args = insn->args; 1; ++args) |
10038 | { | |
10039 | int c; | |
10040 | ||
10041 | if (*s == ' ') | |
10042 | ++s; | |
10043 | ||
10044 | /* In this switch statement we call break if we did not find | |
10045 | a match, continue if we did find a match, or return if we | |
10046 | are done. */ | |
10047 | ||
10048 | c = *args; | |
10049 | switch (c) | |
10050 | { | |
10051 | case '\0': | |
10052 | if (*s == '\0') | |
10053 | { | |
10054 | /* Stuff the immediate value in now, if we can. */ | |
10055 | if (imm_expr.X_op == O_constant | |
f6688943 | 10056 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
10057 | && insn->pinfo != INSN_MACRO) |
10058 | { | |
d6f16593 MR |
10059 | valueT tmp; |
10060 | ||
10061 | switch (*offset_reloc) | |
10062 | { | |
10063 | case BFD_RELOC_MIPS16_HI16_S: | |
10064 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10065 | break; | |
10066 | ||
10067 | case BFD_RELOC_MIPS16_HI16: | |
10068 | tmp = imm_expr.X_add_number >> 16; | |
10069 | break; | |
10070 | ||
10071 | case BFD_RELOC_MIPS16_LO16: | |
10072 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10073 | - 0x8000; | |
10074 | break; | |
10075 | ||
10076 | case BFD_RELOC_UNUSED: | |
10077 | tmp = imm_expr.X_add_number; | |
10078 | break; | |
10079 | ||
10080 | default: | |
10081 | internalError (); | |
10082 | } | |
10083 | *offset_reloc = BFD_RELOC_UNUSED; | |
10084 | ||
c4e7957c | 10085 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10086 | tmp, TRUE, mips16_small, |
252b5132 RH |
10087 | mips16_ext, &ip->insn_opcode, |
10088 | &ip->use_extend, &ip->extend); | |
10089 | imm_expr.X_op = O_absent; | |
f6688943 | 10090 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10091 | } |
10092 | ||
10093 | return; | |
10094 | } | |
10095 | break; | |
10096 | ||
10097 | case ',': | |
10098 | if (*s++ == c) | |
10099 | continue; | |
10100 | s--; | |
10101 | switch (*++args) | |
10102 | { | |
10103 | case 'v': | |
bf12938e | 10104 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10105 | continue; |
10106 | case 'w': | |
bf12938e | 10107 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10108 | continue; |
10109 | } | |
10110 | break; | |
10111 | ||
10112 | case '(': | |
10113 | case ')': | |
10114 | if (*s++ == c) | |
10115 | continue; | |
10116 | break; | |
10117 | ||
10118 | case 'v': | |
10119 | case 'w': | |
10120 | if (s[0] != '$') | |
10121 | { | |
10122 | if (c == 'v') | |
bf12938e | 10123 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10124 | else |
bf12938e | 10125 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10126 | ++args; |
10127 | continue; | |
10128 | } | |
10129 | /* Fall through. */ | |
10130 | case 'x': | |
10131 | case 'y': | |
10132 | case 'z': | |
10133 | case 'Z': | |
10134 | case '0': | |
10135 | case 'S': | |
10136 | case 'R': | |
10137 | case 'X': | |
10138 | case 'Y': | |
707bfff6 TS |
10139 | s_reset = s; |
10140 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10141 | { |
707bfff6 | 10142 | if (c == 'v' || c == 'w') |
85b51719 | 10143 | { |
707bfff6 | 10144 | if (c == 'v') |
a9e24354 | 10145 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10146 | else |
a9e24354 | 10147 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10148 | ++args; |
10149 | continue; | |
85b51719 | 10150 | } |
707bfff6 | 10151 | break; |
252b5132 RH |
10152 | } |
10153 | ||
10154 | if (*s == ' ') | |
10155 | ++s; | |
10156 | if (args[1] != *s) | |
10157 | { | |
10158 | if (c == 'v' || c == 'w') | |
10159 | { | |
10160 | regno = mips16_to_32_reg_map[lastregno]; | |
10161 | s = s_reset; | |
f9419b05 | 10162 | ++args; |
252b5132 RH |
10163 | } |
10164 | } | |
10165 | ||
10166 | switch (c) | |
10167 | { | |
10168 | case 'x': | |
10169 | case 'y': | |
10170 | case 'z': | |
10171 | case 'v': | |
10172 | case 'w': | |
10173 | case 'Z': | |
10174 | regno = mips32_to_16_reg_map[regno]; | |
10175 | break; | |
10176 | ||
10177 | case '0': | |
10178 | if (regno != 0) | |
10179 | regno = ILLEGAL_REG; | |
10180 | break; | |
10181 | ||
10182 | case 'S': | |
10183 | if (regno != SP) | |
10184 | regno = ILLEGAL_REG; | |
10185 | break; | |
10186 | ||
10187 | case 'R': | |
10188 | if (regno != RA) | |
10189 | regno = ILLEGAL_REG; | |
10190 | break; | |
10191 | ||
10192 | case 'X': | |
10193 | case 'Y': | |
741fe287 MR |
10194 | if (regno == AT && mips_opts.at) |
10195 | { | |
10196 | if (mips_opts.at == ATREG) | |
10197 | as_warn (_("used $at without \".set noat\"")); | |
10198 | else | |
10199 | as_warn (_("used $%u with \".set at=$%u\""), | |
10200 | regno, mips_opts.at); | |
10201 | } | |
252b5132 RH |
10202 | break; |
10203 | ||
10204 | default: | |
10205 | internalError (); | |
10206 | } | |
10207 | ||
10208 | if (regno == ILLEGAL_REG) | |
10209 | break; | |
10210 | ||
10211 | switch (c) | |
10212 | { | |
10213 | case 'x': | |
10214 | case 'v': | |
bf12938e | 10215 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10216 | break; |
10217 | case 'y': | |
10218 | case 'w': | |
bf12938e | 10219 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10220 | break; |
10221 | case 'z': | |
bf12938e | 10222 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10223 | break; |
10224 | case 'Z': | |
bf12938e | 10225 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10226 | case '0': |
10227 | case 'S': | |
10228 | case 'R': | |
10229 | break; | |
10230 | case 'X': | |
bf12938e | 10231 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10232 | break; |
10233 | case 'Y': | |
10234 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10235 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10236 | break; |
10237 | default: | |
10238 | internalError (); | |
10239 | } | |
10240 | ||
10241 | lastregno = regno; | |
10242 | continue; | |
10243 | ||
10244 | case 'P': | |
10245 | if (strncmp (s, "$pc", 3) == 0) | |
10246 | { | |
10247 | s += 3; | |
10248 | continue; | |
10249 | } | |
10250 | break; | |
10251 | ||
252b5132 RH |
10252 | case '5': |
10253 | case 'H': | |
10254 | case 'W': | |
10255 | case 'D': | |
10256 | case 'j': | |
252b5132 RH |
10257 | case 'V': |
10258 | case 'C': | |
10259 | case 'U': | |
10260 | case 'k': | |
10261 | case 'K': | |
d6f16593 MR |
10262 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10263 | if (i > 0) | |
252b5132 | 10264 | { |
d6f16593 | 10265 | if (imm_expr.X_op != O_constant) |
252b5132 | 10266 | { |
b34976b6 | 10267 | mips16_ext = TRUE; |
b34976b6 | 10268 | ip->use_extend = TRUE; |
252b5132 | 10269 | ip->extend = 0; |
252b5132 | 10270 | } |
d6f16593 MR |
10271 | else |
10272 | { | |
10273 | /* We need to relax this instruction. */ | |
10274 | *offset_reloc = *imm_reloc; | |
10275 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10276 | } | |
10277 | s = expr_end; | |
10278 | continue; | |
252b5132 | 10279 | } |
d6f16593 MR |
10280 | *imm_reloc = BFD_RELOC_UNUSED; |
10281 | /* Fall through. */ | |
10282 | case '<': | |
10283 | case '>': | |
10284 | case '[': | |
10285 | case ']': | |
10286 | case '4': | |
10287 | case '8': | |
10288 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10289 | if (imm_expr.X_op == O_register) |
10290 | { | |
10291 | /* What we thought was an expression turned out to | |
10292 | be a register. */ | |
10293 | ||
10294 | if (s[0] == '(' && args[1] == '(') | |
10295 | { | |
10296 | /* It looks like the expression was omitted | |
10297 | before a register indirection, which means | |
10298 | that the expression is implicitly zero. We | |
10299 | still set up imm_expr, so that we handle | |
10300 | explicit extensions correctly. */ | |
10301 | imm_expr.X_op = O_constant; | |
10302 | imm_expr.X_add_number = 0; | |
f6688943 | 10303 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10304 | continue; |
10305 | } | |
10306 | ||
10307 | break; | |
10308 | } | |
10309 | ||
10310 | /* We need to relax this instruction. */ | |
f6688943 | 10311 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10312 | s = expr_end; |
10313 | continue; | |
10314 | ||
10315 | case 'p': | |
10316 | case 'q': | |
10317 | case 'A': | |
10318 | case 'B': | |
10319 | case 'E': | |
10320 | /* We use offset_reloc rather than imm_reloc for the PC | |
10321 | relative operands. This lets macros with both | |
10322 | immediate and address operands work correctly. */ | |
10323 | my_getExpression (&offset_expr, s); | |
10324 | ||
10325 | if (offset_expr.X_op == O_register) | |
10326 | break; | |
10327 | ||
10328 | /* We need to relax this instruction. */ | |
f6688943 | 10329 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10330 | s = expr_end; |
10331 | continue; | |
10332 | ||
10333 | case '6': /* break code */ | |
10334 | my_getExpression (&imm_expr, s); | |
10335 | check_absolute_expr (ip, &imm_expr); | |
10336 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10337 | as_warn (_("Invalid value for `%s' (%lu)"), |
10338 | ip->insn_mo->name, | |
10339 | (unsigned long) imm_expr.X_add_number); | |
10340 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10341 | imm_expr.X_op = O_absent; |
10342 | s = expr_end; | |
10343 | continue; | |
10344 | ||
10345 | case 'a': /* 26 bit address */ | |
10346 | my_getExpression (&offset_expr, s); | |
10347 | s = expr_end; | |
f6688943 | 10348 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10349 | ip->insn_opcode <<= 16; |
10350 | continue; | |
10351 | ||
10352 | case 'l': /* register list for entry macro */ | |
10353 | case 'L': /* register list for exit macro */ | |
10354 | { | |
10355 | int mask; | |
10356 | ||
10357 | if (c == 'l') | |
10358 | mask = 0; | |
10359 | else | |
10360 | mask = 7 << 3; | |
10361 | while (*s != '\0') | |
10362 | { | |
707bfff6 | 10363 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10364 | |
10365 | while (*s == ' ' || *s == ',') | |
10366 | ++s; | |
707bfff6 | 10367 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10368 | freg = 0; |
707bfff6 TS |
10369 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10370 | freg = 1; | |
252b5132 RH |
10371 | else |
10372 | { | |
707bfff6 TS |
10373 | as_bad (_("can't parse register list")); |
10374 | break; | |
252b5132 RH |
10375 | } |
10376 | if (*s == ' ') | |
10377 | ++s; | |
10378 | if (*s != '-') | |
10379 | reg2 = reg1; | |
10380 | else | |
10381 | { | |
10382 | ++s; | |
707bfff6 TS |
10383 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10384 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10385 | { |
707bfff6 TS |
10386 | as_bad (_("invalid register list")); |
10387 | break; | |
252b5132 RH |
10388 | } |
10389 | } | |
10390 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10391 | { | |
10392 | mask &= ~ (7 << 3); | |
10393 | mask |= 5 << 3; | |
10394 | } | |
10395 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10396 | { | |
10397 | mask &= ~ (7 << 3); | |
10398 | mask |= 6 << 3; | |
10399 | } | |
10400 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10401 | mask |= (reg2 - 3) << 3; | |
10402 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10403 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10404 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10405 | mask |= 1; |
10406 | else | |
10407 | { | |
10408 | as_bad (_("invalid register list")); | |
10409 | break; | |
10410 | } | |
10411 | } | |
10412 | /* The mask is filled in in the opcode table for the | |
10413 | benefit of the disassembler. We remove it before | |
10414 | applying the actual mask. */ | |
10415 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10416 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10417 | } | |
10418 | continue; | |
10419 | ||
0499d65b TS |
10420 | case 'm': /* Register list for save insn. */ |
10421 | case 'M': /* Register list for restore insn. */ | |
10422 | { | |
10423 | int opcode = 0; | |
10424 | int framesz = 0, seen_framesz = 0; | |
10425 | int args = 0, statics = 0, sregs = 0; | |
10426 | ||
10427 | while (*s != '\0') | |
10428 | { | |
10429 | unsigned int reg1, reg2; | |
10430 | ||
10431 | SKIP_SPACE_TABS (s); | |
10432 | while (*s == ',') | |
10433 | ++s; | |
10434 | SKIP_SPACE_TABS (s); | |
10435 | ||
10436 | my_getExpression (&imm_expr, s); | |
10437 | if (imm_expr.X_op == O_constant) | |
10438 | { | |
10439 | /* Handle the frame size. */ | |
10440 | if (seen_framesz) | |
10441 | { | |
10442 | as_bad (_("more than one frame size in list")); | |
10443 | break; | |
10444 | } | |
10445 | seen_framesz = 1; | |
10446 | framesz = imm_expr.X_add_number; | |
10447 | imm_expr.X_op = O_absent; | |
10448 | s = expr_end; | |
10449 | continue; | |
10450 | } | |
10451 | ||
707bfff6 | 10452 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10453 | { |
10454 | as_bad (_("can't parse register list")); | |
10455 | break; | |
10456 | } | |
0499d65b | 10457 | |
707bfff6 TS |
10458 | while (*s == ' ') |
10459 | ++s; | |
10460 | ||
0499d65b TS |
10461 | if (*s != '-') |
10462 | reg2 = reg1; | |
10463 | else | |
10464 | { | |
10465 | ++s; | |
707bfff6 TS |
10466 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10467 | || reg2 < reg1) | |
0499d65b TS |
10468 | { |
10469 | as_bad (_("can't parse register list")); | |
10470 | break; | |
10471 | } | |
0499d65b TS |
10472 | } |
10473 | ||
10474 | while (reg1 <= reg2) | |
10475 | { | |
10476 | if (reg1 >= 4 && reg1 <= 7) | |
10477 | { | |
3a93f742 | 10478 | if (!seen_framesz) |
0499d65b TS |
10479 | /* args $a0-$a3 */ |
10480 | args |= 1 << (reg1 - 4); | |
10481 | else | |
10482 | /* statics $a0-$a3 */ | |
10483 | statics |= 1 << (reg1 - 4); | |
10484 | } | |
10485 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10486 | { | |
10487 | /* $s0-$s8 */ | |
10488 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10489 | } | |
10490 | else if (reg1 == 31) | |
10491 | { | |
10492 | /* Add $ra to insn. */ | |
10493 | opcode |= 0x40; | |
10494 | } | |
10495 | else | |
10496 | { | |
10497 | as_bad (_("unexpected register in list")); | |
10498 | break; | |
10499 | } | |
10500 | if (++reg1 == 24) | |
10501 | reg1 = 30; | |
10502 | } | |
10503 | } | |
10504 | ||
10505 | /* Encode args/statics combination. */ | |
10506 | if (args & statics) | |
10507 | as_bad (_("arg/static registers overlap")); | |
10508 | else if (args == 0xf) | |
10509 | /* All $a0-$a3 are args. */ | |
10510 | opcode |= MIPS16_ALL_ARGS << 16; | |
10511 | else if (statics == 0xf) | |
10512 | /* All $a0-$a3 are statics. */ | |
10513 | opcode |= MIPS16_ALL_STATICS << 16; | |
10514 | else | |
10515 | { | |
10516 | int narg = 0, nstat = 0; | |
10517 | ||
10518 | /* Count arg registers. */ | |
10519 | while (args & 0x1) | |
10520 | { | |
10521 | args >>= 1; | |
10522 | narg++; | |
10523 | } | |
10524 | if (args != 0) | |
10525 | as_bad (_("invalid arg register list")); | |
10526 | ||
10527 | /* Count static registers. */ | |
10528 | while (statics & 0x8) | |
10529 | { | |
10530 | statics = (statics << 1) & 0xf; | |
10531 | nstat++; | |
10532 | } | |
10533 | if (statics != 0) | |
10534 | as_bad (_("invalid static register list")); | |
10535 | ||
10536 | /* Encode args/statics. */ | |
10537 | opcode |= ((narg << 2) | nstat) << 16; | |
10538 | } | |
10539 | ||
10540 | /* Encode $s0/$s1. */ | |
10541 | if (sregs & (1 << 0)) /* $s0 */ | |
10542 | opcode |= 0x20; | |
10543 | if (sregs & (1 << 1)) /* $s1 */ | |
10544 | opcode |= 0x10; | |
10545 | sregs >>= 2; | |
10546 | ||
10547 | if (sregs != 0) | |
10548 | { | |
10549 | /* Count regs $s2-$s8. */ | |
10550 | int nsreg = 0; | |
10551 | while (sregs & 1) | |
10552 | { | |
10553 | sregs >>= 1; | |
10554 | nsreg++; | |
10555 | } | |
10556 | if (sregs != 0) | |
10557 | as_bad (_("invalid static register list")); | |
10558 | /* Encode $s2-$s8. */ | |
10559 | opcode |= nsreg << 24; | |
10560 | } | |
10561 | ||
10562 | /* Encode frame size. */ | |
10563 | if (!seen_framesz) | |
10564 | as_bad (_("missing frame size")); | |
10565 | else if ((framesz & 7) != 0 || framesz < 0 | |
10566 | || framesz > 0xff * 8) | |
10567 | as_bad (_("invalid frame size")); | |
10568 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10569 | { | |
10570 | framesz /= 8; | |
10571 | opcode |= (((framesz & 0xf0) << 16) | |
10572 | | (framesz & 0x0f)); | |
10573 | } | |
10574 | ||
10575 | /* Finally build the instruction. */ | |
10576 | if ((opcode >> 16) != 0 || framesz == 0) | |
10577 | { | |
10578 | ip->use_extend = TRUE; | |
10579 | ip->extend = opcode >> 16; | |
10580 | } | |
10581 | ip->insn_opcode |= opcode & 0x7f; | |
10582 | } | |
10583 | continue; | |
10584 | ||
252b5132 RH |
10585 | case 'e': /* extend code */ |
10586 | my_getExpression (&imm_expr, s); | |
10587 | check_absolute_expr (ip, &imm_expr); | |
10588 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10589 | { | |
10590 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10591 | ip->insn_mo->name, | |
10592 | (unsigned long) imm_expr.X_add_number); | |
10593 | imm_expr.X_add_number &= 0x7ff; | |
10594 | } | |
10595 | ip->insn_opcode |= imm_expr.X_add_number; | |
10596 | imm_expr.X_op = O_absent; | |
10597 | s = expr_end; | |
10598 | continue; | |
10599 | ||
10600 | default: | |
10601 | internalError (); | |
10602 | } | |
10603 | break; | |
10604 | } | |
10605 | ||
10606 | /* Args don't match. */ | |
10607 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10608 | strcmp (insn->name, insn[1].name) == 0) | |
10609 | { | |
10610 | ++insn; | |
10611 | s = argsstart; | |
10612 | continue; | |
10613 | } | |
10614 | ||
10615 | insn_error = _("illegal operands"); | |
10616 | ||
10617 | return; | |
10618 | } | |
10619 | } | |
10620 | ||
10621 | /* This structure holds information we know about a mips16 immediate | |
10622 | argument type. */ | |
10623 | ||
e972090a NC |
10624 | struct mips16_immed_operand |
10625 | { | |
252b5132 RH |
10626 | /* The type code used in the argument string in the opcode table. */ |
10627 | int type; | |
10628 | /* The number of bits in the short form of the opcode. */ | |
10629 | int nbits; | |
10630 | /* The number of bits in the extended form of the opcode. */ | |
10631 | int extbits; | |
10632 | /* The amount by which the short form is shifted when it is used; | |
10633 | for example, the sw instruction has a shift count of 2. */ | |
10634 | int shift; | |
10635 | /* The amount by which the short form is shifted when it is stored | |
10636 | into the instruction code. */ | |
10637 | int op_shift; | |
10638 | /* Non-zero if the short form is unsigned. */ | |
10639 | int unsp; | |
10640 | /* Non-zero if the extended form is unsigned. */ | |
10641 | int extu; | |
10642 | /* Non-zero if the value is PC relative. */ | |
10643 | int pcrel; | |
10644 | }; | |
10645 | ||
10646 | /* The mips16 immediate operand types. */ | |
10647 | ||
10648 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10649 | { | |
10650 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10651 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10652 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10653 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10654 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10655 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10656 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10657 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10658 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10659 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10660 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10661 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10662 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10663 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10664 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10665 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10666 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10667 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10668 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10669 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10670 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10671 | }; | |
10672 | ||
10673 | #define MIPS16_NUM_IMMED \ | |
10674 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10675 | ||
10676 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10677 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10678 | whether an extended value is needed; if one is needed, it sets | |
10679 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10680 | If SMALL is true, an unextended opcode was explicitly requested. | |
10681 | If EXT is true, an extended opcode was explicitly requested. If | |
10682 | WARN is true, warn if EXT does not match reality. */ | |
10683 | ||
10684 | static void | |
17a2f251 TS |
10685 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10686 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10687 | unsigned long *insn, bfd_boolean *use_extend, | |
10688 | unsigned short *extend) | |
252b5132 | 10689 | { |
3994f87e | 10690 | const struct mips16_immed_operand *op; |
252b5132 | 10691 | int mintiny, maxtiny; |
b34976b6 | 10692 | bfd_boolean needext; |
252b5132 RH |
10693 | |
10694 | op = mips16_immed_operands; | |
10695 | while (op->type != type) | |
10696 | { | |
10697 | ++op; | |
10698 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10699 | } | |
10700 | ||
10701 | if (op->unsp) | |
10702 | { | |
10703 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10704 | { | |
10705 | mintiny = 1; | |
10706 | maxtiny = 1 << op->nbits; | |
10707 | } | |
10708 | else | |
10709 | { | |
10710 | mintiny = 0; | |
10711 | maxtiny = (1 << op->nbits) - 1; | |
10712 | } | |
10713 | } | |
10714 | else | |
10715 | { | |
10716 | mintiny = - (1 << (op->nbits - 1)); | |
10717 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10718 | } | |
10719 | ||
10720 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10721 | if (type == 'p' || type == 'q') | |
10722 | val /= 2; | |
10723 | ||
10724 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10725 | || val < (mintiny << op->shift) | |
10726 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10727 | needext = TRUE; |
252b5132 | 10728 | else |
b34976b6 | 10729 | needext = FALSE; |
252b5132 RH |
10730 | |
10731 | if (warn && ext && ! needext) | |
beae10d5 KH |
10732 | as_warn_where (file, line, |
10733 | _("extended operand requested but not required")); | |
252b5132 RH |
10734 | if (small && needext) |
10735 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10736 | ||
10737 | if (small || (! ext && ! needext)) | |
10738 | { | |
10739 | int insnval; | |
10740 | ||
b34976b6 | 10741 | *use_extend = FALSE; |
252b5132 RH |
10742 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10743 | insnval <<= op->op_shift; | |
10744 | *insn |= insnval; | |
10745 | } | |
10746 | else | |
10747 | { | |
10748 | long minext, maxext; | |
10749 | int extval; | |
10750 | ||
10751 | if (op->extu) | |
10752 | { | |
10753 | minext = 0; | |
10754 | maxext = (1 << op->extbits) - 1; | |
10755 | } | |
10756 | else | |
10757 | { | |
10758 | minext = - (1 << (op->extbits - 1)); | |
10759 | maxext = (1 << (op->extbits - 1)) - 1; | |
10760 | } | |
10761 | if (val < minext || val > maxext) | |
10762 | as_bad_where (file, line, | |
10763 | _("operand value out of range for instruction")); | |
10764 | ||
b34976b6 | 10765 | *use_extend = TRUE; |
252b5132 RH |
10766 | if (op->extbits == 16) |
10767 | { | |
10768 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10769 | val &= 0x1f; | |
10770 | } | |
10771 | else if (op->extbits == 15) | |
10772 | { | |
10773 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10774 | val &= 0xf; | |
10775 | } | |
10776 | else | |
10777 | { | |
10778 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10779 | val = 0; | |
10780 | } | |
10781 | ||
10782 | *extend = (unsigned short) extval; | |
10783 | *insn |= val; | |
10784 | } | |
10785 | } | |
10786 | \f | |
d6f16593 | 10787 | struct percent_op_match |
ad8d3bb3 | 10788 | { |
5e0116d5 RS |
10789 | const char *str; |
10790 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10791 | }; |
10792 | ||
10793 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10794 | { |
5e0116d5 | 10795 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10796 | #ifdef OBJ_ELF |
5e0116d5 RS |
10797 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10798 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10799 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10800 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10801 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10802 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10803 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10804 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10805 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10806 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10807 | {"%half", BFD_RELOC_16}, | |
10808 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10809 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10810 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10811 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10812 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10813 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10814 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10815 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10816 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10817 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10818 | #endif |
5e0116d5 | 10819 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10820 | }; |
10821 | ||
d6f16593 MR |
10822 | static const struct percent_op_match mips16_percent_op[] = |
10823 | { | |
10824 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10825 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10826 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10827 | }; | |
10828 | ||
252b5132 | 10829 | |
5e0116d5 RS |
10830 | /* Return true if *STR points to a relocation operator. When returning true, |
10831 | move *STR over the operator and store its relocation code in *RELOC. | |
10832 | Leave both *STR and *RELOC alone when returning false. */ | |
10833 | ||
10834 | static bfd_boolean | |
17a2f251 | 10835 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10836 | { |
d6f16593 MR |
10837 | const struct percent_op_match *percent_op; |
10838 | size_t limit, i; | |
10839 | ||
10840 | if (mips_opts.mips16) | |
10841 | { | |
10842 | percent_op = mips16_percent_op; | |
10843 | limit = ARRAY_SIZE (mips16_percent_op); | |
10844 | } | |
10845 | else | |
10846 | { | |
10847 | percent_op = mips_percent_op; | |
10848 | limit = ARRAY_SIZE (mips_percent_op); | |
10849 | } | |
76b3015f | 10850 | |
d6f16593 | 10851 | for (i = 0; i < limit; i++) |
5e0116d5 | 10852 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10853 | { |
3f98094e DJ |
10854 | int len = strlen (percent_op[i].str); |
10855 | ||
10856 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10857 | continue; | |
10858 | ||
5e0116d5 RS |
10859 | *str += strlen (percent_op[i].str); |
10860 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10861 | |
5e0116d5 RS |
10862 | /* Check whether the output BFD supports this relocation. |
10863 | If not, issue an error and fall back on something safe. */ | |
10864 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10865 | { |
5e0116d5 RS |
10866 | as_bad ("relocation %s isn't supported by the current ABI", |
10867 | percent_op[i].str); | |
01a3f561 | 10868 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10869 | } |
5e0116d5 | 10870 | return TRUE; |
394f9b3a | 10871 | } |
5e0116d5 | 10872 | return FALSE; |
394f9b3a | 10873 | } |
ad8d3bb3 | 10874 | |
ad8d3bb3 | 10875 | |
5e0116d5 RS |
10876 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10877 | expression in *EP and the relocations in the array starting | |
10878 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10879 | |
01a3f561 | 10880 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10881 | |
5e0116d5 | 10882 | static size_t |
17a2f251 TS |
10883 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10884 | char *str) | |
ad8d3bb3 | 10885 | { |
5e0116d5 RS |
10886 | bfd_reloc_code_real_type reversed_reloc[3]; |
10887 | size_t reloc_index, i; | |
09b8f35a RS |
10888 | int crux_depth, str_depth; |
10889 | char *crux; | |
5e0116d5 RS |
10890 | |
10891 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10892 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10893 | of the main expression and with CRUX_DEPTH containing the number | |
10894 | of open brackets at that point. */ | |
10895 | reloc_index = -1; | |
10896 | str_depth = 0; | |
10897 | do | |
fb1b3232 | 10898 | { |
09b8f35a RS |
10899 | reloc_index++; |
10900 | crux = str; | |
10901 | crux_depth = str_depth; | |
10902 | ||
10903 | /* Skip over whitespace and brackets, keeping count of the number | |
10904 | of brackets. */ | |
10905 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10906 | if (*str++ == '(') | |
10907 | str_depth++; | |
5e0116d5 | 10908 | } |
09b8f35a RS |
10909 | while (*str == '%' |
10910 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10911 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10912 | |
09b8f35a | 10913 | my_getExpression (ep, crux); |
5e0116d5 | 10914 | str = expr_end; |
394f9b3a | 10915 | |
5e0116d5 | 10916 | /* Match every open bracket. */ |
09b8f35a | 10917 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10918 | if (*str++ == ')') |
09b8f35a | 10919 | crux_depth--; |
394f9b3a | 10920 | |
09b8f35a | 10921 | if (crux_depth > 0) |
5e0116d5 | 10922 | as_bad ("unclosed '('"); |
394f9b3a | 10923 | |
5e0116d5 | 10924 | expr_end = str; |
252b5132 | 10925 | |
01a3f561 | 10926 | if (reloc_index != 0) |
64bdfcaf RS |
10927 | { |
10928 | prev_reloc_op_frag = frag_now; | |
10929 | for (i = 0; i < reloc_index; i++) | |
10930 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10931 | } | |
fb1b3232 | 10932 | |
5e0116d5 | 10933 | return reloc_index; |
252b5132 RH |
10934 | } |
10935 | ||
10936 | static void | |
17a2f251 | 10937 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10938 | { |
10939 | char *save_in; | |
98aa84af | 10940 | valueT val; |
252b5132 RH |
10941 | |
10942 | save_in = input_line_pointer; | |
10943 | input_line_pointer = str; | |
10944 | expression (ep); | |
10945 | expr_end = input_line_pointer; | |
10946 | input_line_pointer = save_in; | |
10947 | ||
10948 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10949 | then we bump the value of the symbol by 1 since that is how other | |
10950 | text symbols are handled. We don't bother to handle complex | |
10951 | expressions, just `.' plus or minus a constant. */ | |
10952 | if (mips_opts.mips16 | |
10953 | && ep->X_op == O_symbol | |
10954 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10955 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10956 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10957 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10958 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10959 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10960 | } |
10961 | ||
252b5132 | 10962 | char * |
17a2f251 | 10963 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10964 | { |
499ac353 | 10965 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
10966 | } |
10967 | ||
10968 | void | |
17a2f251 | 10969 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10970 | { |
10971 | if (target_big_endian) | |
10972 | number_to_chars_bigendian (buf, val, n); | |
10973 | else | |
10974 | number_to_chars_littleendian (buf, val, n); | |
10975 | } | |
10976 | \f | |
ae948b86 | 10977 | #ifdef OBJ_ELF |
e013f690 TS |
10978 | static int support_64bit_objects(void) |
10979 | { | |
10980 | const char **list, **l; | |
aa3d8fdf | 10981 | int yes; |
e013f690 TS |
10982 | |
10983 | list = bfd_target_list (); | |
10984 | for (l = list; *l != NULL; l++) | |
10985 | #ifdef TE_TMIPS | |
10986 | /* This is traditional mips */ | |
10987 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10988 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10989 | #else | |
10990 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10991 | || strcmp (*l, "elf64-littlemips") == 0) | |
10992 | #endif | |
10993 | break; | |
aa3d8fdf | 10994 | yes = (*l != NULL); |
e013f690 | 10995 | free (list); |
aa3d8fdf | 10996 | return yes; |
e013f690 | 10997 | } |
ae948b86 | 10998 | #endif /* OBJ_ELF */ |
e013f690 | 10999 | |
78849248 | 11000 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11001 | |
e972090a NC |
11002 | struct option md_longopts[] = |
11003 | { | |
f9b4148d CD |
11004 | /* Options which specify architecture. */ |
11005 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
11006 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
11007 | {"march", required_argument, NULL, OPTION_MARCH}, | |
11008 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
11009 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
11010 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
11011 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11012 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 11013 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 11014 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 11015 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 11016 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 11017 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 11018 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 11019 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 11020 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 11021 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 11022 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 11023 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 11024 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
11025 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
11026 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
11027 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
11028 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
11029 | |
11030 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 11031 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
11032 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
11033 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
11034 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
11035 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
11036 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
11037 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
11038 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
11039 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
11040 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
11041 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
11042 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
11043 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
11044 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
11045 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
11046 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
11047 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
11048 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
11049 | {"mmt", no_argument, NULL, OPTION_MT}, | |
11050 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
11051 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
11052 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
11053 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
11054 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
11055 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
8b082fb1 TS |
11056 | #define OPTION_DSPR2 (OPTION_ASE_BASE + 12) |
11057 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
11058 | #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) | |
11059 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
f9b4148d CD |
11060 | |
11061 | /* Old-style architecture options. Don't add more of these. */ | |
8b082fb1 | 11062 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) |
f9b4148d CD |
11063 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
11064 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
11065 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
11066 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
11067 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
11068 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
11069 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
11070 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
11071 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
11072 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
11073 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
11074 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
11075 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
11076 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
11077 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
11078 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
11079 | ||
11080 | /* Options which enable bug fixes. */ | |
11081 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
11082 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
11083 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
11084 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
11085 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
11086 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
11087 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
11088 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
11089 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
11090 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11091 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
11092 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
11093 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
11094 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
11095 | |
11096 | /* Miscellaneous options. */ | |
7d8e00cf | 11097 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 11098 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
11099 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11100 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 11101 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
11102 | {"break", no_argument, NULL, OPTION_BREAK}, |
11103 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 11104 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 11105 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 11106 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 11107 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 11108 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 11109 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 11110 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 11111 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 11112 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 11113 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 11114 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 11115 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 11116 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 11117 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 11118 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 11119 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
11120 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
11121 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
11122 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11123 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11124 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
11125 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
11126 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
11127 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11128 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
11129 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
11130 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
11131 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11132 | #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16) |
11133 | #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17) | |
11134 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
11135 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
11136 | #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18) | |
11137 | #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19) | |
11138 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
11139 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
11140 | ||
f9b4148d | 11141 | /* ELF-specific options. */ |
156c2f8b | 11142 | #ifdef OBJ_ELF |
037b32b9 | 11143 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20) |
156c2f8b | 11144 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
11145 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11146 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 11147 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 11148 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 11149 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 11150 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
11151 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
11152 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
11153 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 11154 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 11155 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 11156 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 11157 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 11158 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
11159 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
11160 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
11161 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
11162 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
11163 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
11164 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
11165 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
11166 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
11167 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
11168 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 11169 | #endif /* OBJ_ELF */ |
f9b4148d | 11170 | |
252b5132 RH |
11171 | {NULL, no_argument, NULL, 0} |
11172 | }; | |
156c2f8b | 11173 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11174 | |
316f5878 RS |
11175 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11176 | NEW_VALUE. Warn if another value was already specified. Note: | |
11177 | we have to defer parsing the -march and -mtune arguments in order | |
11178 | to handle 'from-abi' correctly, since the ABI might be specified | |
11179 | in a later argument. */ | |
11180 | ||
11181 | static void | |
17a2f251 | 11182 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11183 | { |
11184 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11185 | as_warn (_("A different %s was already specified, is now %s"), | |
11186 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11187 | new_value); | |
11188 | ||
11189 | *string_ptr = new_value; | |
11190 | } | |
11191 | ||
252b5132 | 11192 | int |
17a2f251 | 11193 | md_parse_option (int c, char *arg) |
252b5132 RH |
11194 | { |
11195 | switch (c) | |
11196 | { | |
119d663a NC |
11197 | case OPTION_CONSTRUCT_FLOATS: |
11198 | mips_disable_float_construction = 0; | |
11199 | break; | |
bdaaa2e1 | 11200 | |
119d663a NC |
11201 | case OPTION_NO_CONSTRUCT_FLOATS: |
11202 | mips_disable_float_construction = 1; | |
11203 | break; | |
bdaaa2e1 | 11204 | |
252b5132 RH |
11205 | case OPTION_TRAP: |
11206 | mips_trap = 1; | |
11207 | break; | |
11208 | ||
11209 | case OPTION_BREAK: | |
11210 | mips_trap = 0; | |
11211 | break; | |
11212 | ||
11213 | case OPTION_EB: | |
11214 | target_big_endian = 1; | |
11215 | break; | |
11216 | ||
11217 | case OPTION_EL: | |
11218 | target_big_endian = 0; | |
11219 | break; | |
11220 | ||
11221 | case 'O': | |
4ffff32f TS |
11222 | if (arg == NULL) |
11223 | mips_optimize = 1; | |
11224 | else if (arg[0] == '0') | |
11225 | mips_optimize = 0; | |
11226 | else if (arg[0] == '1') | |
252b5132 RH |
11227 | mips_optimize = 1; |
11228 | else | |
11229 | mips_optimize = 2; | |
11230 | break; | |
11231 | ||
11232 | case 'g': | |
11233 | if (arg == NULL) | |
11234 | mips_debug = 2; | |
11235 | else | |
11236 | mips_debug = atoi (arg); | |
252b5132 RH |
11237 | break; |
11238 | ||
11239 | case OPTION_MIPS1: | |
316f5878 | 11240 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11241 | break; |
11242 | ||
11243 | case OPTION_MIPS2: | |
316f5878 | 11244 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11245 | break; |
11246 | ||
11247 | case OPTION_MIPS3: | |
316f5878 | 11248 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11249 | break; |
11250 | ||
11251 | case OPTION_MIPS4: | |
316f5878 | 11252 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11253 | break; |
11254 | ||
84ea6cf2 | 11255 | case OPTION_MIPS5: |
316f5878 | 11256 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11257 | break; |
11258 | ||
e7af610e | 11259 | case OPTION_MIPS32: |
316f5878 | 11260 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11261 | break; |
11262 | ||
af7ee8bf CD |
11263 | case OPTION_MIPS32R2: |
11264 | file_mips_isa = ISA_MIPS32R2; | |
11265 | break; | |
11266 | ||
5f74bc13 CD |
11267 | case OPTION_MIPS64R2: |
11268 | file_mips_isa = ISA_MIPS64R2; | |
11269 | break; | |
11270 | ||
84ea6cf2 | 11271 | case OPTION_MIPS64: |
316f5878 | 11272 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11273 | break; |
11274 | ||
ec68c924 | 11275 | case OPTION_MTUNE: |
316f5878 RS |
11276 | mips_set_option_string (&mips_tune_string, arg); |
11277 | break; | |
ec68c924 | 11278 | |
316f5878 RS |
11279 | case OPTION_MARCH: |
11280 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11281 | break; |
11282 | ||
11283 | case OPTION_M4650: | |
316f5878 RS |
11284 | mips_set_option_string (&mips_arch_string, "4650"); |
11285 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11286 | break; |
11287 | ||
11288 | case OPTION_NO_M4650: | |
11289 | break; | |
11290 | ||
11291 | case OPTION_M4010: | |
316f5878 RS |
11292 | mips_set_option_string (&mips_arch_string, "4010"); |
11293 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11294 | break; |
11295 | ||
11296 | case OPTION_NO_M4010: | |
11297 | break; | |
11298 | ||
11299 | case OPTION_M4100: | |
316f5878 RS |
11300 | mips_set_option_string (&mips_arch_string, "4100"); |
11301 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11302 | break; |
11303 | ||
11304 | case OPTION_NO_M4100: | |
11305 | break; | |
11306 | ||
252b5132 | 11307 | case OPTION_M3900: |
316f5878 RS |
11308 | mips_set_option_string (&mips_arch_string, "3900"); |
11309 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11310 | break; |
bdaaa2e1 | 11311 | |
252b5132 RH |
11312 | case OPTION_NO_M3900: |
11313 | break; | |
11314 | ||
deec1734 CD |
11315 | case OPTION_MDMX: |
11316 | mips_opts.ase_mdmx = 1; | |
11317 | break; | |
11318 | ||
11319 | case OPTION_NO_MDMX: | |
11320 | mips_opts.ase_mdmx = 0; | |
11321 | break; | |
11322 | ||
74cd071d CF |
11323 | case OPTION_DSP: |
11324 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11325 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11326 | break; |
11327 | ||
11328 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11329 | mips_opts.ase_dsp = 0; |
11330 | mips_opts.ase_dspr2 = 0; | |
11331 | break; | |
11332 | ||
11333 | case OPTION_DSPR2: | |
11334 | mips_opts.ase_dspr2 = 1; | |
11335 | mips_opts.ase_dsp = 1; | |
11336 | break; | |
11337 | ||
11338 | case OPTION_NO_DSPR2: | |
11339 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11340 | mips_opts.ase_dsp = 0; |
11341 | break; | |
11342 | ||
ef2e4d86 CF |
11343 | case OPTION_MT: |
11344 | mips_opts.ase_mt = 1; | |
11345 | break; | |
11346 | ||
11347 | case OPTION_NO_MT: | |
11348 | mips_opts.ase_mt = 0; | |
11349 | break; | |
11350 | ||
252b5132 RH |
11351 | case OPTION_MIPS16: |
11352 | mips_opts.mips16 = 1; | |
7d10b47d | 11353 | mips_no_prev_insn (); |
252b5132 RH |
11354 | break; |
11355 | ||
11356 | case OPTION_NO_MIPS16: | |
11357 | mips_opts.mips16 = 0; | |
7d10b47d | 11358 | mips_no_prev_insn (); |
252b5132 RH |
11359 | break; |
11360 | ||
1f25f5d3 CD |
11361 | case OPTION_MIPS3D: |
11362 | mips_opts.ase_mips3d = 1; | |
11363 | break; | |
11364 | ||
11365 | case OPTION_NO_MIPS3D: | |
11366 | mips_opts.ase_mips3d = 0; | |
11367 | break; | |
11368 | ||
e16bfa71 TS |
11369 | case OPTION_SMARTMIPS: |
11370 | mips_opts.ase_smartmips = 1; | |
11371 | break; | |
11372 | ||
11373 | case OPTION_NO_SMARTMIPS: | |
11374 | mips_opts.ase_smartmips = 0; | |
11375 | break; | |
11376 | ||
d766e8ec RS |
11377 | case OPTION_FIX_VR4120: |
11378 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11379 | break; |
11380 | ||
d766e8ec RS |
11381 | case OPTION_NO_FIX_VR4120: |
11382 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11383 | break; |
11384 | ||
7d8e00cf RS |
11385 | case OPTION_FIX_VR4130: |
11386 | mips_fix_vr4130 = 1; | |
11387 | break; | |
11388 | ||
11389 | case OPTION_NO_FIX_VR4130: | |
11390 | mips_fix_vr4130 = 0; | |
11391 | break; | |
11392 | ||
4a6a3df4 AO |
11393 | case OPTION_RELAX_BRANCH: |
11394 | mips_relax_branch = 1; | |
11395 | break; | |
11396 | ||
11397 | case OPTION_NO_RELAX_BRANCH: | |
11398 | mips_relax_branch = 0; | |
11399 | break; | |
11400 | ||
aa6975fb ILT |
11401 | case OPTION_MSHARED: |
11402 | mips_in_shared = TRUE; | |
11403 | break; | |
11404 | ||
11405 | case OPTION_MNO_SHARED: | |
11406 | mips_in_shared = FALSE; | |
11407 | break; | |
11408 | ||
aed1a261 RS |
11409 | case OPTION_MSYM32: |
11410 | mips_opts.sym32 = TRUE; | |
11411 | break; | |
11412 | ||
11413 | case OPTION_MNO_SYM32: | |
11414 | mips_opts.sym32 = FALSE; | |
11415 | break; | |
11416 | ||
0f074f60 | 11417 | #ifdef OBJ_ELF |
252b5132 RH |
11418 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11419 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11420 | intended to be compatible with Irix 5. */ | |
11421 | case OPTION_CALL_SHARED: | |
f43abd2b | 11422 | if (!IS_ELF) |
252b5132 RH |
11423 | { |
11424 | as_bad (_("-call_shared is supported only for ELF format")); | |
11425 | return 0; | |
11426 | } | |
11427 | mips_pic = SVR4_PIC; | |
143d77c5 | 11428 | mips_abicalls = TRUE; |
252b5132 RH |
11429 | break; |
11430 | ||
11431 | case OPTION_NON_SHARED: | |
f43abd2b | 11432 | if (!IS_ELF) |
252b5132 RH |
11433 | { |
11434 | as_bad (_("-non_shared is supported only for ELF format")); | |
11435 | return 0; | |
11436 | } | |
11437 | mips_pic = NO_PIC; | |
143d77c5 | 11438 | mips_abicalls = FALSE; |
252b5132 RH |
11439 | break; |
11440 | ||
44075ae2 TS |
11441 | /* The -xgot option tells the assembler to use 32 bit offsets |
11442 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11443 | compatibility. */ |
11444 | case OPTION_XGOT: | |
11445 | mips_big_got = 1; | |
11446 | break; | |
0f074f60 | 11447 | #endif /* OBJ_ELF */ |
252b5132 RH |
11448 | |
11449 | case 'G': | |
6caf9ef4 TS |
11450 | g_switch_value = atoi (arg); |
11451 | g_switch_seen = 1; | |
252b5132 RH |
11452 | break; |
11453 | ||
0f074f60 | 11454 | #ifdef OBJ_ELF |
34ba82a8 TS |
11455 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11456 | and -mabi=64. */ | |
252b5132 | 11457 | case OPTION_32: |
f43abd2b | 11458 | if (!IS_ELF) |
34ba82a8 TS |
11459 | { |
11460 | as_bad (_("-32 is supported for ELF format only")); | |
11461 | return 0; | |
11462 | } | |
316f5878 | 11463 | mips_abi = O32_ABI; |
252b5132 RH |
11464 | break; |
11465 | ||
e013f690 | 11466 | case OPTION_N32: |
f43abd2b | 11467 | if (!IS_ELF) |
34ba82a8 TS |
11468 | { |
11469 | as_bad (_("-n32 is supported for ELF format only")); | |
11470 | return 0; | |
11471 | } | |
316f5878 | 11472 | mips_abi = N32_ABI; |
e013f690 | 11473 | break; |
252b5132 | 11474 | |
e013f690 | 11475 | case OPTION_64: |
f43abd2b | 11476 | if (!IS_ELF) |
34ba82a8 TS |
11477 | { |
11478 | as_bad (_("-64 is supported for ELF format only")); | |
11479 | return 0; | |
11480 | } | |
316f5878 | 11481 | mips_abi = N64_ABI; |
f43abd2b | 11482 | if (!support_64bit_objects()) |
e013f690 | 11483 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11484 | break; |
ae948b86 | 11485 | #endif /* OBJ_ELF */ |
252b5132 | 11486 | |
c97ef257 | 11487 | case OPTION_GP32: |
a325df1d | 11488 | file_mips_gp32 = 1; |
c97ef257 AH |
11489 | break; |
11490 | ||
11491 | case OPTION_GP64: | |
a325df1d | 11492 | file_mips_gp32 = 0; |
c97ef257 | 11493 | break; |
252b5132 | 11494 | |
ca4e0257 | 11495 | case OPTION_FP32: |
a325df1d | 11496 | file_mips_fp32 = 1; |
316f5878 RS |
11497 | break; |
11498 | ||
11499 | case OPTION_FP64: | |
11500 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11501 | break; |
11502 | ||
037b32b9 AN |
11503 | case OPTION_SINGLE_FLOAT: |
11504 | file_mips_single_float = 1; | |
11505 | break; | |
11506 | ||
11507 | case OPTION_DOUBLE_FLOAT: | |
11508 | file_mips_single_float = 0; | |
11509 | break; | |
11510 | ||
11511 | case OPTION_SOFT_FLOAT: | |
11512 | file_mips_soft_float = 1; | |
11513 | break; | |
11514 | ||
11515 | case OPTION_HARD_FLOAT: | |
11516 | file_mips_soft_float = 0; | |
11517 | break; | |
11518 | ||
ae948b86 | 11519 | #ifdef OBJ_ELF |
252b5132 | 11520 | case OPTION_MABI: |
f43abd2b | 11521 | if (!IS_ELF) |
34ba82a8 TS |
11522 | { |
11523 | as_bad (_("-mabi is supported for ELF format only")); | |
11524 | return 0; | |
11525 | } | |
e013f690 | 11526 | if (strcmp (arg, "32") == 0) |
316f5878 | 11527 | mips_abi = O32_ABI; |
e013f690 | 11528 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11529 | mips_abi = O64_ABI; |
e013f690 | 11530 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11531 | mips_abi = N32_ABI; |
e013f690 TS |
11532 | else if (strcmp (arg, "64") == 0) |
11533 | { | |
316f5878 | 11534 | mips_abi = N64_ABI; |
e013f690 TS |
11535 | if (! support_64bit_objects()) |
11536 | as_fatal (_("No compiled in support for 64 bit object file " | |
11537 | "format")); | |
11538 | } | |
11539 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11540 | mips_abi = EABI_ABI; |
e013f690 | 11541 | else |
da0e507f TS |
11542 | { |
11543 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11544 | return 0; | |
11545 | } | |
252b5132 | 11546 | break; |
e013f690 | 11547 | #endif /* OBJ_ELF */ |
252b5132 | 11548 | |
6b76fefe | 11549 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11550 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11551 | break; |
11552 | ||
9ee72ff1 | 11553 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11554 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11555 | break; |
11556 | ||
ecb4347a DJ |
11557 | #ifdef OBJ_ELF |
11558 | case OPTION_MDEBUG: | |
b34976b6 | 11559 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11560 | break; |
11561 | ||
11562 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11563 | mips_flag_mdebug = FALSE; |
ecb4347a | 11564 | break; |
dcd410fe RO |
11565 | |
11566 | case OPTION_PDR: | |
11567 | mips_flag_pdr = TRUE; | |
11568 | break; | |
11569 | ||
11570 | case OPTION_NO_PDR: | |
11571 | mips_flag_pdr = FALSE; | |
11572 | break; | |
0a44bf69 RS |
11573 | |
11574 | case OPTION_MVXWORKS_PIC: | |
11575 | mips_pic = VXWORKS_PIC; | |
11576 | break; | |
ecb4347a DJ |
11577 | #endif /* OBJ_ELF */ |
11578 | ||
252b5132 RH |
11579 | default: |
11580 | return 0; | |
11581 | } | |
11582 | ||
11583 | return 1; | |
11584 | } | |
316f5878 RS |
11585 | \f |
11586 | /* Set up globals to generate code for the ISA or processor | |
11587 | described by INFO. */ | |
252b5132 | 11588 | |
252b5132 | 11589 | static void |
17a2f251 | 11590 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11591 | { |
316f5878 | 11592 | if (info != 0) |
252b5132 | 11593 | { |
fef14a42 TS |
11594 | file_mips_arch = info->cpu; |
11595 | mips_opts.arch = info->cpu; | |
316f5878 | 11596 | mips_opts.isa = info->isa; |
252b5132 | 11597 | } |
252b5132 RH |
11598 | } |
11599 | ||
252b5132 | 11600 | |
316f5878 | 11601 | /* Likewise for tuning. */ |
252b5132 | 11602 | |
316f5878 | 11603 | static void |
17a2f251 | 11604 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11605 | { |
11606 | if (info != 0) | |
fef14a42 | 11607 | mips_tune = info->cpu; |
316f5878 | 11608 | } |
80cc45a5 | 11609 | |
34ba82a8 | 11610 | |
252b5132 | 11611 | void |
17a2f251 | 11612 | mips_after_parse_args (void) |
e9670677 | 11613 | { |
fef14a42 TS |
11614 | const struct mips_cpu_info *arch_info = 0; |
11615 | const struct mips_cpu_info *tune_info = 0; | |
11616 | ||
e9670677 | 11617 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11618 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11619 | { |
6caf9ef4 | 11620 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11621 | as_bad (_("-G not supported in this configuration.")); |
11622 | g_switch_value = 0; | |
11623 | } | |
11624 | ||
cac012d6 AO |
11625 | if (mips_abi == NO_ABI) |
11626 | mips_abi = MIPS_DEFAULT_ABI; | |
11627 | ||
22923709 RS |
11628 | /* The following code determines the architecture and register size. |
11629 | Similar code was added to GCC 3.3 (see override_options() in | |
11630 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11631 | as much as possible. */ | |
e9670677 | 11632 | |
316f5878 | 11633 | if (mips_arch_string != 0) |
fef14a42 | 11634 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11635 | |
316f5878 | 11636 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11637 | { |
316f5878 | 11638 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11639 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11640 | the -march selection (if any). */ |
fef14a42 | 11641 | if (arch_info != 0) |
e9670677 | 11642 | { |
316f5878 RS |
11643 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11644 | There's no harm in specifying both as long as the ISA levels | |
11645 | are the same. */ | |
fef14a42 | 11646 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11647 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11648 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11649 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11650 | } |
316f5878 | 11651 | else |
fef14a42 | 11652 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11653 | } |
11654 | ||
fef14a42 TS |
11655 | if (arch_info == 0) |
11656 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11657 | |
fef14a42 | 11658 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11659 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11660 | arch_info->name); |
11661 | ||
11662 | mips_set_architecture (arch_info); | |
11663 | ||
11664 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11665 | if (mips_tune_string != 0) | |
11666 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11667 | |
fef14a42 TS |
11668 | if (tune_info == 0) |
11669 | mips_set_tune (arch_info); | |
11670 | else | |
11671 | mips_set_tune (tune_info); | |
e9670677 | 11672 | |
316f5878 | 11673 | if (file_mips_gp32 >= 0) |
e9670677 | 11674 | { |
316f5878 RS |
11675 | /* The user specified the size of the integer registers. Make sure |
11676 | it agrees with the ABI and ISA. */ | |
11677 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11678 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11679 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11680 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11681 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11682 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11683 | } |
11684 | else | |
11685 | { | |
316f5878 RS |
11686 | /* Infer the integer register size from the ABI and processor. |
11687 | Restrict ourselves to 32-bit registers if that's all the | |
11688 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11689 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11690 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11691 | } |
11692 | ||
ad3fea08 TS |
11693 | switch (file_mips_fp32) |
11694 | { | |
11695 | default: | |
11696 | case -1: | |
11697 | /* No user specified float register size. | |
11698 | ??? GAS treats single-float processors as though they had 64-bit | |
11699 | float registers (although it complains when double-precision | |
11700 | instructions are used). As things stand, saying they have 32-bit | |
11701 | registers would lead to spurious "register must be even" messages. | |
11702 | So here we assume float registers are never smaller than the | |
11703 | integer ones. */ | |
11704 | if (file_mips_gp32 == 0) | |
11705 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11706 | file_mips_fp32 = 0; | |
11707 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11708 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11709 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11710 | file_mips_fp32 = 0; | |
11711 | else | |
11712 | /* 32-bit float registers. */ | |
11713 | file_mips_fp32 = 1; | |
11714 | break; | |
11715 | ||
11716 | /* The user specified the size of the float registers. Check if it | |
11717 | agrees with the ABI and ISA. */ | |
11718 | case 0: | |
11719 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11720 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11721 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11722 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11723 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11724 | break; | |
11725 | case 1: | |
11726 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11727 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11728 | break; | |
11729 | } | |
e9670677 | 11730 | |
316f5878 | 11731 | /* End of GCC-shared inference code. */ |
e9670677 | 11732 | |
17a2f251 TS |
11733 | /* This flag is set when we have a 64-bit capable CPU but use only |
11734 | 32-bit wide registers. Note that EABI does not use it. */ | |
11735 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11736 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11737 | || mips_abi == O32_ABI)) | |
316f5878 | 11738 | mips_32bitmode = 1; |
e9670677 MR |
11739 | |
11740 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11741 | as_bad (_("trap exception not supported at ISA 1")); | |
11742 | ||
e9670677 MR |
11743 | /* If the selected architecture includes support for ASEs, enable |
11744 | generation of code for them. */ | |
a4672219 | 11745 | if (mips_opts.mips16 == -1) |
fef14a42 | 11746 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11747 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11748 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11749 | && file_mips_fp32 == 0) ? 1 : 0; |
11750 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11751 | as_bad (_("-mfp32 used with -mips3d")); | |
11752 | ||
ffdefa66 | 11753 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11754 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11755 | && file_mips_fp32 == 0) ? 1 : 0; |
11756 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11757 | as_bad (_("-mfp32 used with -mdmx")); | |
11758 | ||
11759 | if (mips_opts.ase_smartmips == -1) | |
11760 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11761 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11762 | as_warn ("%s ISA does not support SmartMIPS", | |
11763 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11764 | ||
74cd071d | 11765 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11766 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11767 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11768 | as_warn ("%s ISA does not support DSP ASE", | |
11769 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11770 | ||
8b082fb1 TS |
11771 | if (mips_opts.ase_dspr2 == -1) |
11772 | { | |
11773 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11774 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11775 | } | |
11776 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
11777 | as_warn ("%s ISA does not support DSP R2 ASE", | |
11778 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11779 | ||
ef2e4d86 | 11780 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11781 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11782 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
8b082fb1 | 11783 | as_warn ("%s ISA does not support MT ASE", |
ad3fea08 | 11784 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
e9670677 | 11785 | |
e9670677 | 11786 | file_mips_isa = mips_opts.isa; |
a4672219 | 11787 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11788 | file_ase_mips3d = mips_opts.ase_mips3d; |
11789 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11790 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11791 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11792 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11793 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11794 | mips_opts.gp32 = file_mips_gp32; |
11795 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
11796 | mips_opts.soft_float = file_mips_soft_float; |
11797 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 11798 | |
ecb4347a DJ |
11799 | if (mips_flag_mdebug < 0) |
11800 | { | |
11801 | #ifdef OBJ_MAYBE_ECOFF | |
11802 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11803 | mips_flag_mdebug = 1; | |
11804 | else | |
11805 | #endif /* OBJ_MAYBE_ECOFF */ | |
11806 | mips_flag_mdebug = 0; | |
11807 | } | |
e9670677 MR |
11808 | } |
11809 | \f | |
11810 | void | |
17a2f251 | 11811 | mips_init_after_args (void) |
252b5132 RH |
11812 | { |
11813 | /* initialize opcodes */ | |
11814 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11815 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11816 | } |
11817 | ||
11818 | long | |
17a2f251 | 11819 | md_pcrel_from (fixS *fixP) |
252b5132 | 11820 | { |
a7ebbfdf TS |
11821 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11822 | switch (fixP->fx_r_type) | |
11823 | { | |
11824 | case BFD_RELOC_16_PCREL_S2: | |
11825 | case BFD_RELOC_MIPS_JMP: | |
11826 | /* Return the address of the delay slot. */ | |
11827 | return addr + 4; | |
11828 | default: | |
58ea3d6a | 11829 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11830 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11831 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11832 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11833 | return addr; |
11834 | } | |
252b5132 RH |
11835 | } |
11836 | ||
252b5132 RH |
11837 | /* This is called before the symbol table is processed. In order to |
11838 | work with gcc when using mips-tfile, we must keep all local labels. | |
11839 | However, in other cases, we want to discard them. If we were | |
11840 | called with -g, but we didn't see any debugging information, it may | |
11841 | mean that gcc is smuggling debugging information through to | |
11842 | mips-tfile, in which case we must generate all local labels. */ | |
11843 | ||
11844 | void | |
17a2f251 | 11845 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11846 | { |
11847 | #ifndef NO_ECOFF_DEBUGGING | |
11848 | if (ECOFF_DEBUGGING | |
11849 | && mips_debug != 0 | |
11850 | && ! ecoff_debugging_seen) | |
11851 | flag_keep_locals = 1; | |
11852 | #endif | |
11853 | } | |
11854 | ||
3b91255e | 11855 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11856 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11857 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11858 | relocation operators. | |
11859 | ||
11860 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11861 | expression if: | |
11862 | ||
11863 | (a) it refers to the same symbol; and | |
11864 | (b) the offset applied in the %lo() expression is no lower than | |
11865 | the offset applied in the %got() or %hi(). | |
11866 | ||
11867 | (b) allows us to cope with code like: | |
11868 | ||
11869 | lui $4,%hi(foo) | |
11870 | lh $4,%lo(foo+2)($4) | |
11871 | ||
11872 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11873 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11874 | the high 16 bits. | |
11875 | ||
11876 | When several %lo()s match a particular %got() or %hi(), we use the | |
11877 | following rules to distinguish them: | |
11878 | ||
11879 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11880 | higher offsets. | |
11881 | ||
11882 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11883 | that already have a matching %got() or %hi(). | |
11884 | ||
11885 | (3) later %lo()s are better than earlier %lo()s. | |
11886 | ||
11887 | These rules are applied in order. | |
11888 | ||
11889 | (1) means, among other things, that %lo()s with identical offsets are | |
11890 | chosen if they exist. | |
11891 | ||
11892 | (2) means that we won't associate several high-part relocations with | |
11893 | the same low-part relocation unless there's no alternative. Having | |
11894 | several high parts for the same low part is a GNU extension; this rule | |
11895 | allows careful users to avoid it. | |
11896 | ||
11897 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11898 | with the last high-part relocation being at the front of the list. | |
11899 | It therefore makes sense to choose the last matching low-part | |
11900 | relocation, all other things being equal. It's also easier | |
11901 | to code that way. */ | |
252b5132 RH |
11902 | |
11903 | void | |
17a2f251 | 11904 | mips_frob_file (void) |
252b5132 RH |
11905 | { |
11906 | struct mips_hi_fixup *l; | |
35903be0 | 11907 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
11908 | |
11909 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11910 | { | |
11911 | segment_info_type *seginfo; | |
3b91255e RS |
11912 | bfd_boolean matched_lo_p; |
11913 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11914 | |
5919d012 | 11915 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11916 | |
5919d012 RS |
11917 | /* If a GOT16 relocation turns out to be against a global symbol, |
11918 | there isn't supposed to be a matching LO. */ | |
11919 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11920 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11921 | continue; | |
11922 | ||
11923 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11924 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11925 | continue; |
11926 | ||
252b5132 | 11927 | seginfo = seg_info (l->seg); |
252b5132 | 11928 | |
3b91255e RS |
11929 | /* Set HI_POS to the position of this relocation in the chain. |
11930 | Set LO_POS to the position of the chosen low-part relocation. | |
11931 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11932 | relocation that matches an immediately-preceding high-part | |
11933 | relocation. */ | |
11934 | hi_pos = NULL; | |
11935 | lo_pos = NULL; | |
11936 | matched_lo_p = FALSE; | |
35903be0 CM |
11937 | |
11938 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS16_HI16 | |
11939 | || l->fixp->fx_r_type == BFD_RELOC_MIPS16_HI16_S) | |
11940 | looking_for_rtype = BFD_RELOC_MIPS16_LO16; | |
11941 | else | |
11942 | looking_for_rtype = BFD_RELOC_LO16; | |
11943 | ||
3b91255e RS |
11944 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
11945 | { | |
11946 | if (*pos == l->fixp) | |
11947 | hi_pos = pos; | |
11948 | ||
35903be0 | 11949 | if ((*pos)->fx_r_type == looking_for_rtype |
3b91255e RS |
11950 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11951 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11952 | && (lo_pos == NULL | |
11953 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11954 | || (!matched_lo_p | |
11955 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11956 | lo_pos = pos; | |
11957 | ||
11958 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11959 | && fixup_has_matching_lo_p (*pos)); | |
11960 | } | |
11961 | ||
11962 | /* If we found a match, remove the high-part relocation from its | |
11963 | current position and insert it before the low-part relocation. | |
11964 | Make the offsets match so that fixup_has_matching_lo_p() | |
11965 | will return true. | |
11966 | ||
11967 | We don't warn about unmatched high-part relocations since some | |
11968 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11969 | instructions. */ | |
11970 | if (lo_pos != NULL) | |
11971 | { | |
11972 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11973 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11974 | { |
3b91255e RS |
11975 | *hi_pos = l->fixp->fx_next; |
11976 | l->fixp->fx_next = *lo_pos; | |
11977 | *lo_pos = l->fixp; | |
252b5132 | 11978 | } |
252b5132 RH |
11979 | } |
11980 | } | |
11981 | } | |
11982 | ||
3e722fb5 | 11983 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11984 | We have to prevent gas from dropping them. */ |
252b5132 | 11985 | |
252b5132 | 11986 | int |
17a2f251 | 11987 | mips_force_relocation (fixS *fixp) |
252b5132 | 11988 | { |
ae6063d4 | 11989 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11990 | return 1; |
11991 | ||
f6688943 TS |
11992 | if (HAVE_NEWABI |
11993 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11994 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11995 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11996 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11997 | return 1; | |
11998 | ||
3e722fb5 | 11999 | return 0; |
252b5132 RH |
12000 | } |
12001 | ||
12002 | /* Apply a fixup to the object file. */ | |
12003 | ||
94f592af | 12004 | void |
55cf6793 | 12005 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12006 | { |
874e8986 | 12007 | bfd_byte *buf; |
98aa84af | 12008 | long insn; |
a7ebbfdf | 12009 | reloc_howto_type *howto; |
252b5132 | 12010 | |
a7ebbfdf TS |
12011 | /* We ignore generic BFD relocations we don't know about. */ |
12012 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12013 | if (! howto) | |
12014 | return; | |
65551fa4 | 12015 | |
252b5132 RH |
12016 | assert (fixP->fx_size == 4 |
12017 | || fixP->fx_r_type == BFD_RELOC_16 | |
12018 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
12019 | || fixP->fx_r_type == BFD_RELOC_CTOR |
12020 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 12021 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
12022 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
12023 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12024 | |
a7ebbfdf | 12025 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12026 | |
3994f87e | 12027 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12028 | |
12029 | /* Don't treat parts of a composite relocation as done. There are two | |
12030 | reasons for this: | |
12031 | ||
12032 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12033 | should nevertheless be emitted if the first part is. | |
12034 | ||
12035 | (2) In normal usage, composite relocations are never assembly-time | |
12036 | constants. The easiest way of dealing with the pathological | |
12037 | exceptions is to generate a relocation against STN_UNDEF and | |
12038 | leave everything up to the linker. */ | |
3994f87e | 12039 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12040 | fixP->fx_done = 1; |
12041 | ||
12042 | switch (fixP->fx_r_type) | |
12043 | { | |
3f98094e DJ |
12044 | case BFD_RELOC_MIPS_TLS_GD: |
12045 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12046 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12047 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12048 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12049 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12050 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12051 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12052 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12053 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12054 | /* fall through */ | |
12055 | ||
252b5132 | 12056 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12057 | case BFD_RELOC_MIPS_SHIFT5: |
12058 | case BFD_RELOC_MIPS_SHIFT6: | |
12059 | case BFD_RELOC_MIPS_GOT_DISP: | |
12060 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12061 | case BFD_RELOC_MIPS_GOT_OFST: | |
12062 | case BFD_RELOC_MIPS_SUB: | |
12063 | case BFD_RELOC_MIPS_INSERT_A: | |
12064 | case BFD_RELOC_MIPS_INSERT_B: | |
12065 | case BFD_RELOC_MIPS_DELETE: | |
12066 | case BFD_RELOC_MIPS_HIGHEST: | |
12067 | case BFD_RELOC_MIPS_HIGHER: | |
12068 | case BFD_RELOC_MIPS_SCN_DISP: | |
12069 | case BFD_RELOC_MIPS_REL16: | |
12070 | case BFD_RELOC_MIPS_RELGOT: | |
12071 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12072 | case BFD_RELOC_HI16: |
12073 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12074 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12075 | case BFD_RELOC_MIPS_LITERAL: |
12076 | case BFD_RELOC_MIPS_CALL16: | |
12077 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12078 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12079 | case BFD_RELOC_MIPS_GOT_HI16: |
12080 | case BFD_RELOC_MIPS_GOT_LO16: | |
12081 | case BFD_RELOC_MIPS_CALL_HI16: | |
12082 | case BFD_RELOC_MIPS_CALL_LO16: | |
12083 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
12084 | case BFD_RELOC_MIPS16_HI16: |
12085 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12086 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12087 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12088 | break; |
12089 | ||
252b5132 RH |
12090 | case BFD_RELOC_64: |
12091 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12092 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12093 | if (fixP->fx_done) |
252b5132 RH |
12094 | { |
12095 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12096 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12097 | else |
12098 | { | |
a7ebbfdf | 12099 | valueT hiv; |
252b5132 | 12100 | |
a7ebbfdf | 12101 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12102 | hiv = 0xffffffff; |
12103 | else | |
12104 | hiv = 0; | |
b215186b | 12105 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12106 | *valP, 4); |
b215186b | 12107 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12108 | hiv, 4); |
252b5132 RH |
12109 | } |
12110 | } | |
12111 | break; | |
12112 | ||
056350c6 | 12113 | case BFD_RELOC_RVA: |
252b5132 | 12114 | case BFD_RELOC_32: |
252b5132 RH |
12115 | case BFD_RELOC_16: |
12116 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12117 | value now. This can happen if we have a .word which is not |
12118 | resolved when it appears but is later defined. */ | |
252b5132 | 12119 | if (fixP->fx_done) |
54f4ddb3 | 12120 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12121 | break; |
12122 | ||
12123 | case BFD_RELOC_LO16: | |
d6f16593 | 12124 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12125 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12126 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12127 | /* When handling an embedded PIC switch statement, we can wind |
12128 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12129 | if (fixP->fx_done) | |
12130 | { | |
a7ebbfdf | 12131 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12132 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12133 | _("relocation overflow")); | |
252b5132 RH |
12134 | if (target_big_endian) |
12135 | buf += 2; | |
2132e3a3 | 12136 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12137 | } |
12138 | break; | |
12139 | ||
12140 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12141 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12142 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12143 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12144 | |
54f4ddb3 TS |
12145 | /* We need to save the bits in the instruction since fixup_segment() |
12146 | might be deleting the relocation entry (i.e., a branch within | |
12147 | the current segment). */ | |
a7ebbfdf | 12148 | if (! fixP->fx_done) |
bb2d6cd7 | 12149 | break; |
252b5132 | 12150 | |
54f4ddb3 | 12151 | /* Update old instruction data. */ |
252b5132 RH |
12152 | if (target_big_endian) |
12153 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12154 | else | |
12155 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12156 | ||
a7ebbfdf TS |
12157 | if (*valP + 0x20000 <= 0x3ffff) |
12158 | { | |
12159 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12160 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12161 | } |
12162 | else if (mips_pic == NO_PIC | |
12163 | && fixP->fx_done | |
12164 | && fixP->fx_frag->fr_address >= text_section->vma | |
12165 | && (fixP->fx_frag->fr_address | |
587aac4e | 12166 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12167 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12168 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12169 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12170 | { |
12171 | /* The branch offset is too large. If this is an | |
12172 | unconditional branch, and we are not generating PIC code, | |
12173 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12174 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12175 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12176 | else |
a7ebbfdf TS |
12177 | insn = 0x08000000; /* j */ |
12178 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12179 | fixP->fx_done = 0; | |
12180 | fixP->fx_addsy = section_symbol (text_section); | |
12181 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12182 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12183 | } |
12184 | else | |
12185 | { | |
12186 | /* If we got here, we have branch-relaxation disabled, | |
12187 | and there's nothing we can do to fix this instruction | |
12188 | without turning it into a longer sequence. */ | |
12189 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12190 | _("Branch out of range")); | |
252b5132 | 12191 | } |
252b5132 RH |
12192 | break; |
12193 | ||
12194 | case BFD_RELOC_VTABLE_INHERIT: | |
12195 | fixP->fx_done = 0; | |
12196 | if (fixP->fx_addsy | |
12197 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12198 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12199 | S_SET_WEAK (fixP->fx_addsy); | |
12200 | break; | |
12201 | ||
12202 | case BFD_RELOC_VTABLE_ENTRY: | |
12203 | fixP->fx_done = 0; | |
12204 | break; | |
12205 | ||
12206 | default: | |
12207 | internalError (); | |
12208 | } | |
a7ebbfdf TS |
12209 | |
12210 | /* Remember value for tc_gen_reloc. */ | |
12211 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12212 | } |
12213 | ||
252b5132 | 12214 | static symbolS * |
17a2f251 | 12215 | get_symbol (void) |
252b5132 RH |
12216 | { |
12217 | int c; | |
12218 | char *name; | |
12219 | symbolS *p; | |
12220 | ||
12221 | name = input_line_pointer; | |
12222 | c = get_symbol_end (); | |
12223 | p = (symbolS *) symbol_find_or_make (name); | |
12224 | *input_line_pointer = c; | |
12225 | return p; | |
12226 | } | |
12227 | ||
742a56fe RS |
12228 | /* Align the current frag to a given power of two. If a particular |
12229 | fill byte should be used, FILL points to an integer that contains | |
12230 | that byte, otherwise FILL is null. | |
12231 | ||
12232 | The MIPS assembler also automatically adjusts any preceding | |
12233 | label. */ | |
252b5132 RH |
12234 | |
12235 | static void | |
742a56fe | 12236 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12237 | { |
7d10b47d | 12238 | mips_emit_delays (); |
742a56fe RS |
12239 | mips_record_mips16_mode (); |
12240 | if (fill == NULL && subseg_text_p (now_seg)) | |
12241 | frag_align_code (to, 0); | |
12242 | else | |
12243 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12244 | record_alignment (now_seg, to); |
12245 | if (label != NULL) | |
12246 | { | |
12247 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 12248 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12249 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12250 | } | |
12251 | } | |
12252 | ||
12253 | /* Align to a given power of two. .align 0 turns off the automatic | |
12254 | alignment used by the data creating pseudo-ops. */ | |
12255 | ||
12256 | static void | |
17a2f251 | 12257 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12258 | { |
742a56fe | 12259 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12260 | long max_alignment = 28; |
252b5132 | 12261 | |
54f4ddb3 | 12262 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12263 | to the aligned address. |
54f4ddb3 | 12264 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12265 | a .align pseudo instruction. |
54f4ddb3 | 12266 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12267 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12268 | We don't. */ |
252b5132 RH |
12269 | |
12270 | temp = get_absolute_expression (); | |
12271 | if (temp > max_alignment) | |
12272 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12273 | else if (temp < 0) | |
12274 | { | |
12275 | as_warn (_("Alignment negative: 0 assumed.")); | |
12276 | temp = 0; | |
12277 | } | |
12278 | if (*input_line_pointer == ',') | |
12279 | { | |
f9419b05 | 12280 | ++input_line_pointer; |
742a56fe RS |
12281 | fill_value = get_absolute_expression (); |
12282 | fill_ptr = &fill_value; | |
252b5132 RH |
12283 | } |
12284 | else | |
742a56fe | 12285 | fill_ptr = 0; |
252b5132 RH |
12286 | if (temp) |
12287 | { | |
a8dbcb85 TS |
12288 | segment_info_type *si = seg_info (now_seg); |
12289 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12290 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12291 | auto_align = 1; |
742a56fe | 12292 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12293 | } |
12294 | else | |
12295 | { | |
12296 | auto_align = 0; | |
12297 | } | |
12298 | ||
12299 | demand_empty_rest_of_line (); | |
12300 | } | |
12301 | ||
252b5132 | 12302 | static void |
17a2f251 | 12303 | s_change_sec (int sec) |
252b5132 RH |
12304 | { |
12305 | segT seg; | |
12306 | ||
252b5132 RH |
12307 | #ifdef OBJ_ELF |
12308 | /* The ELF backend needs to know that we are changing sections, so | |
12309 | that .previous works correctly. We could do something like check | |
b6ff326e | 12310 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12311 | as it would not be appropriate to use it in the section changing |
12312 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12313 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12314 | if (IS_ELF) |
12315 | obj_elf_section_change_hook (); | |
252b5132 RH |
12316 | #endif |
12317 | ||
7d10b47d | 12318 | mips_emit_delays (); |
252b5132 RH |
12319 | switch (sec) |
12320 | { | |
12321 | case 't': | |
12322 | s_text (0); | |
12323 | break; | |
12324 | case 'd': | |
12325 | s_data (0); | |
12326 | break; | |
12327 | case 'b': | |
12328 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12329 | demand_empty_rest_of_line (); | |
12330 | break; | |
12331 | ||
12332 | case 'r': | |
4d0d148d TS |
12333 | seg = subseg_new (RDATA_SECTION_NAME, |
12334 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12335 | if (IS_ELF) |
252b5132 | 12336 | { |
4d0d148d TS |
12337 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12338 | | SEC_READONLY | SEC_RELOC | |
12339 | | SEC_DATA)); | |
c41e87e3 | 12340 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12341 | record_alignment (seg, 4); |
252b5132 | 12342 | } |
4d0d148d | 12343 | demand_empty_rest_of_line (); |
252b5132 RH |
12344 | break; |
12345 | ||
12346 | case 's': | |
4d0d148d | 12347 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12348 | if (IS_ELF) |
252b5132 | 12349 | { |
4d0d148d TS |
12350 | bfd_set_section_flags (stdoutput, seg, |
12351 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12352 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12353 | record_alignment (seg, 4); |
252b5132 | 12354 | } |
4d0d148d TS |
12355 | demand_empty_rest_of_line (); |
12356 | break; | |
252b5132 RH |
12357 | } |
12358 | ||
12359 | auto_align = 1; | |
12360 | } | |
b34976b6 | 12361 | |
cca86cc8 | 12362 | void |
17a2f251 | 12363 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12364 | { |
7ed4a06a | 12365 | #ifdef OBJ_ELF |
cca86cc8 SC |
12366 | char *section_name; |
12367 | char c; | |
684022ea | 12368 | char next_c = 0; |
cca86cc8 SC |
12369 | int section_type; |
12370 | int section_flag; | |
12371 | int section_entry_size; | |
12372 | int section_alignment; | |
b34976b6 | 12373 | |
f43abd2b | 12374 | if (!IS_ELF) |
7ed4a06a TS |
12375 | return; |
12376 | ||
cca86cc8 SC |
12377 | section_name = input_line_pointer; |
12378 | c = get_symbol_end (); | |
a816d1ed AO |
12379 | if (c) |
12380 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12381 | |
4cf0dd0d TS |
12382 | /* Do we have .section Name<,"flags">? */ |
12383 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12384 | { |
4cf0dd0d TS |
12385 | /* just after name is now '\0'. */ |
12386 | *input_line_pointer = c; | |
cca86cc8 SC |
12387 | input_line_pointer = section_name; |
12388 | obj_elf_section (ignore); | |
12389 | return; | |
12390 | } | |
12391 | input_line_pointer++; | |
12392 | ||
12393 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12394 | if (c == ',') | |
12395 | section_type = get_absolute_expression (); | |
12396 | else | |
12397 | section_type = 0; | |
12398 | if (*input_line_pointer++ == ',') | |
12399 | section_flag = get_absolute_expression (); | |
12400 | else | |
12401 | section_flag = 0; | |
12402 | if (*input_line_pointer++ == ',') | |
12403 | section_entry_size = get_absolute_expression (); | |
12404 | else | |
12405 | section_entry_size = 0; | |
12406 | if (*input_line_pointer++ == ',') | |
12407 | section_alignment = get_absolute_expression (); | |
12408 | else | |
12409 | section_alignment = 0; | |
12410 | ||
a816d1ed AO |
12411 | section_name = xstrdup (section_name); |
12412 | ||
8ab8a5c8 RS |
12413 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12414 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12415 | traditionally had to fall back on the more common @progbits instead. | |
12416 | ||
12417 | There's nothing really harmful in this, since bfd will correct | |
12418 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12419 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12420 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12421 | ||
12422 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12423 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12424 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12425 | generic type-checking code. */ | |
12426 | if (section_type == SHT_MIPS_DWARF) | |
12427 | section_type = SHT_PROGBITS; | |
12428 | ||
cca86cc8 SC |
12429 | obj_elf_change_section (section_name, section_type, section_flag, |
12430 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12431 | |
12432 | if (now_seg->name != section_name) | |
12433 | free (section_name); | |
7ed4a06a | 12434 | #endif /* OBJ_ELF */ |
cca86cc8 | 12435 | } |
252b5132 RH |
12436 | |
12437 | void | |
17a2f251 | 12438 | mips_enable_auto_align (void) |
252b5132 RH |
12439 | { |
12440 | auto_align = 1; | |
12441 | } | |
12442 | ||
12443 | static void | |
17a2f251 | 12444 | s_cons (int log_size) |
252b5132 | 12445 | { |
a8dbcb85 TS |
12446 | segment_info_type *si = seg_info (now_seg); |
12447 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12448 | symbolS *label; |
12449 | ||
a8dbcb85 | 12450 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12451 | mips_emit_delays (); |
252b5132 RH |
12452 | if (log_size > 0 && auto_align) |
12453 | mips_align (log_size, 0, label); | |
12454 | mips_clear_insn_labels (); | |
12455 | cons (1 << log_size); | |
12456 | } | |
12457 | ||
12458 | static void | |
17a2f251 | 12459 | s_float_cons (int type) |
252b5132 | 12460 | { |
a8dbcb85 TS |
12461 | segment_info_type *si = seg_info (now_seg); |
12462 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12463 | symbolS *label; |
12464 | ||
a8dbcb85 | 12465 | label = l != NULL ? l->label : NULL; |
252b5132 | 12466 | |
7d10b47d | 12467 | mips_emit_delays (); |
252b5132 RH |
12468 | |
12469 | if (auto_align) | |
49309057 ILT |
12470 | { |
12471 | if (type == 'd') | |
12472 | mips_align (3, 0, label); | |
12473 | else | |
12474 | mips_align (2, 0, label); | |
12475 | } | |
252b5132 RH |
12476 | |
12477 | mips_clear_insn_labels (); | |
12478 | ||
12479 | float_cons (type); | |
12480 | } | |
12481 | ||
12482 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12483 | permitted to say | |
12484 | .globl foo .text | |
12485 | where foo is an undefined symbol, to mean that foo should be | |
12486 | considered to be the address of a function. */ | |
12487 | ||
12488 | static void | |
17a2f251 | 12489 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12490 | { |
12491 | char *name; | |
12492 | int c; | |
12493 | symbolS *symbolP; | |
12494 | flagword flag; | |
12495 | ||
8a06b769 | 12496 | do |
252b5132 | 12497 | { |
8a06b769 | 12498 | name = input_line_pointer; |
252b5132 | 12499 | c = get_symbol_end (); |
8a06b769 TS |
12500 | symbolP = symbol_find_or_make (name); |
12501 | S_SET_EXTERNAL (symbolP); | |
12502 | ||
252b5132 | 12503 | *input_line_pointer = c; |
8a06b769 | 12504 | SKIP_WHITESPACE (); |
252b5132 | 12505 | |
8a06b769 TS |
12506 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12507 | being a function is apparently labelled as being an object. */ | |
12508 | flag = BSF_OBJECT; | |
252b5132 | 12509 | |
8a06b769 TS |
12510 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12511 | && (*input_line_pointer != ',')) | |
12512 | { | |
12513 | char *secname; | |
12514 | asection *sec; | |
12515 | ||
12516 | secname = input_line_pointer; | |
12517 | c = get_symbol_end (); | |
12518 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12519 | if (sec == NULL) | |
12520 | as_bad (_("%s: no such section"), secname); | |
12521 | *input_line_pointer = c; | |
12522 | ||
12523 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12524 | flag = BSF_FUNCTION; | |
12525 | } | |
12526 | ||
12527 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12528 | ||
12529 | c = *input_line_pointer; | |
12530 | if (c == ',') | |
12531 | { | |
12532 | input_line_pointer++; | |
12533 | SKIP_WHITESPACE (); | |
12534 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12535 | c = '\n'; | |
12536 | } | |
12537 | } | |
12538 | while (c == ','); | |
252b5132 | 12539 | |
252b5132 RH |
12540 | demand_empty_rest_of_line (); |
12541 | } | |
12542 | ||
12543 | static void | |
17a2f251 | 12544 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12545 | { |
12546 | char *opt; | |
12547 | char c; | |
12548 | ||
12549 | opt = input_line_pointer; | |
12550 | c = get_symbol_end (); | |
12551 | ||
12552 | if (*opt == 'O') | |
12553 | { | |
12554 | /* FIXME: What does this mean? */ | |
12555 | } | |
12556 | else if (strncmp (opt, "pic", 3) == 0) | |
12557 | { | |
12558 | int i; | |
12559 | ||
12560 | i = atoi (opt + 3); | |
12561 | if (i == 0) | |
12562 | mips_pic = NO_PIC; | |
12563 | else if (i == 2) | |
143d77c5 | 12564 | { |
252b5132 | 12565 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12566 | mips_abicalls = TRUE; |
12567 | } | |
252b5132 RH |
12568 | else |
12569 | as_bad (_(".option pic%d not supported"), i); | |
12570 | ||
4d0d148d | 12571 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12572 | { |
12573 | if (g_switch_seen && g_switch_value != 0) | |
12574 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12575 | g_switch_value = 0; | |
12576 | bfd_set_gp_size (stdoutput, 0); | |
12577 | } | |
12578 | } | |
12579 | else | |
12580 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12581 | ||
12582 | *input_line_pointer = c; | |
12583 | demand_empty_rest_of_line (); | |
12584 | } | |
12585 | ||
12586 | /* This structure is used to hold a stack of .set values. */ | |
12587 | ||
e972090a NC |
12588 | struct mips_option_stack |
12589 | { | |
252b5132 RH |
12590 | struct mips_option_stack *next; |
12591 | struct mips_set_options options; | |
12592 | }; | |
12593 | ||
12594 | static struct mips_option_stack *mips_opts_stack; | |
12595 | ||
12596 | /* Handle the .set pseudo-op. */ | |
12597 | ||
12598 | static void | |
17a2f251 | 12599 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12600 | { |
12601 | char *name = input_line_pointer, ch; | |
12602 | ||
12603 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12604 | ++input_line_pointer; |
252b5132 RH |
12605 | ch = *input_line_pointer; |
12606 | *input_line_pointer = '\0'; | |
12607 | ||
12608 | if (strcmp (name, "reorder") == 0) | |
12609 | { | |
7d10b47d RS |
12610 | if (mips_opts.noreorder) |
12611 | end_noreorder (); | |
252b5132 RH |
12612 | } |
12613 | else if (strcmp (name, "noreorder") == 0) | |
12614 | { | |
7d10b47d RS |
12615 | if (!mips_opts.noreorder) |
12616 | start_noreorder (); | |
252b5132 | 12617 | } |
741fe287 MR |
12618 | else if (strncmp (name, "at=", 3) == 0) |
12619 | { | |
12620 | char *s = name + 3; | |
12621 | ||
12622 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12623 | as_bad (_("Unrecognized register name `%s'"), s); | |
12624 | } | |
252b5132 RH |
12625 | else if (strcmp (name, "at") == 0) |
12626 | { | |
741fe287 | 12627 | mips_opts.at = ATREG; |
252b5132 RH |
12628 | } |
12629 | else if (strcmp (name, "noat") == 0) | |
12630 | { | |
741fe287 | 12631 | mips_opts.at = ZERO; |
252b5132 RH |
12632 | } |
12633 | else if (strcmp (name, "macro") == 0) | |
12634 | { | |
12635 | mips_opts.warn_about_macros = 0; | |
12636 | } | |
12637 | else if (strcmp (name, "nomacro") == 0) | |
12638 | { | |
12639 | if (mips_opts.noreorder == 0) | |
12640 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12641 | mips_opts.warn_about_macros = 1; | |
12642 | } | |
12643 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12644 | { | |
12645 | mips_opts.nomove = 0; | |
12646 | } | |
12647 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12648 | { | |
12649 | mips_opts.nomove = 1; | |
12650 | } | |
12651 | else if (strcmp (name, "bopt") == 0) | |
12652 | { | |
12653 | mips_opts.nobopt = 0; | |
12654 | } | |
12655 | else if (strcmp (name, "nobopt") == 0) | |
12656 | { | |
12657 | mips_opts.nobopt = 1; | |
12658 | } | |
ad3fea08 TS |
12659 | else if (strcmp (name, "gp=default") == 0) |
12660 | mips_opts.gp32 = file_mips_gp32; | |
12661 | else if (strcmp (name, "gp=32") == 0) | |
12662 | mips_opts.gp32 = 1; | |
12663 | else if (strcmp (name, "gp=64") == 0) | |
12664 | { | |
12665 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12666 | as_warn ("%s isa does not support 64-bit registers", | |
12667 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12668 | mips_opts.gp32 = 0; | |
12669 | } | |
12670 | else if (strcmp (name, "fp=default") == 0) | |
12671 | mips_opts.fp32 = file_mips_fp32; | |
12672 | else if (strcmp (name, "fp=32") == 0) | |
12673 | mips_opts.fp32 = 1; | |
12674 | else if (strcmp (name, "fp=64") == 0) | |
12675 | { | |
12676 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12677 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12678 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12679 | mips_opts.fp32 = 0; | |
12680 | } | |
037b32b9 AN |
12681 | else if (strcmp (name, "softfloat") == 0) |
12682 | mips_opts.soft_float = 1; | |
12683 | else if (strcmp (name, "hardfloat") == 0) | |
12684 | mips_opts.soft_float = 0; | |
12685 | else if (strcmp (name, "singlefloat") == 0) | |
12686 | mips_opts.single_float = 1; | |
12687 | else if (strcmp (name, "doublefloat") == 0) | |
12688 | mips_opts.single_float = 0; | |
252b5132 RH |
12689 | else if (strcmp (name, "mips16") == 0 |
12690 | || strcmp (name, "MIPS-16") == 0) | |
12691 | mips_opts.mips16 = 1; | |
12692 | else if (strcmp (name, "nomips16") == 0 | |
12693 | || strcmp (name, "noMIPS-16") == 0) | |
12694 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12695 | else if (strcmp (name, "smartmips") == 0) |
12696 | { | |
ad3fea08 | 12697 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12698 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12699 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12700 | mips_opts.ase_smartmips = 1; | |
12701 | } | |
12702 | else if (strcmp (name, "nosmartmips") == 0) | |
12703 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12704 | else if (strcmp (name, "mips3d") == 0) |
12705 | mips_opts.ase_mips3d = 1; | |
12706 | else if (strcmp (name, "nomips3d") == 0) | |
12707 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12708 | else if (strcmp (name, "mdmx") == 0) |
12709 | mips_opts.ase_mdmx = 1; | |
12710 | else if (strcmp (name, "nomdmx") == 0) | |
12711 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12712 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12713 | { |
12714 | if (!ISA_SUPPORTS_DSP_ASE) | |
12715 | as_warn ("%s ISA does not support DSP ASE", | |
12716 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12717 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12718 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12719 | } |
74cd071d | 12720 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12721 | { |
12722 | mips_opts.ase_dsp = 0; | |
12723 | mips_opts.ase_dspr2 = 0; | |
12724 | } | |
12725 | else if (strcmp (name, "dspr2") == 0) | |
12726 | { | |
12727 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
12728 | as_warn ("%s ISA does not support DSP R2 ASE", | |
12729 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12730 | mips_opts.ase_dspr2 = 1; | |
12731 | mips_opts.ase_dsp = 1; | |
12732 | } | |
12733 | else if (strcmp (name, "nodspr2") == 0) | |
12734 | { | |
12735 | mips_opts.ase_dspr2 = 0; | |
12736 | mips_opts.ase_dsp = 0; | |
12737 | } | |
ef2e4d86 | 12738 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12739 | { |
12740 | if (!ISA_SUPPORTS_MT_ASE) | |
12741 | as_warn ("%s ISA does not support MT ASE", | |
12742 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12743 | mips_opts.ase_mt = 1; | |
12744 | } | |
ef2e4d86 CF |
12745 | else if (strcmp (name, "nomt") == 0) |
12746 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12747 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12748 | { |
af7ee8bf | 12749 | int reset = 0; |
252b5132 | 12750 | |
1a2c1fad CD |
12751 | /* Permit the user to change the ISA and architecture on the fly. |
12752 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12753 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12754 | { |
12755 | reset = 1; | |
12756 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12757 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12758 | } |
12759 | else if (strncmp (name, "arch=", 5) == 0) | |
12760 | { | |
12761 | const struct mips_cpu_info *p; | |
12762 | ||
12763 | p = mips_parse_cpu("internal use", name + 5); | |
12764 | if (!p) | |
12765 | as_bad (_("unknown architecture %s"), name + 5); | |
12766 | else | |
12767 | { | |
12768 | mips_opts.arch = p->cpu; | |
12769 | mips_opts.isa = p->isa; | |
12770 | } | |
12771 | } | |
81a21e38 TS |
12772 | else if (strncmp (name, "mips", 4) == 0) |
12773 | { | |
12774 | const struct mips_cpu_info *p; | |
12775 | ||
12776 | p = mips_parse_cpu("internal use", name); | |
12777 | if (!p) | |
12778 | as_bad (_("unknown ISA level %s"), name + 4); | |
12779 | else | |
12780 | { | |
12781 | mips_opts.arch = p->cpu; | |
12782 | mips_opts.isa = p->isa; | |
12783 | } | |
12784 | } | |
af7ee8bf | 12785 | else |
81a21e38 | 12786 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12787 | |
12788 | switch (mips_opts.isa) | |
98d3f06f KH |
12789 | { |
12790 | case 0: | |
98d3f06f | 12791 | break; |
af7ee8bf CD |
12792 | case ISA_MIPS1: |
12793 | case ISA_MIPS2: | |
12794 | case ISA_MIPS32: | |
12795 | case ISA_MIPS32R2: | |
98d3f06f KH |
12796 | mips_opts.gp32 = 1; |
12797 | mips_opts.fp32 = 1; | |
12798 | break; | |
af7ee8bf CD |
12799 | case ISA_MIPS3: |
12800 | case ISA_MIPS4: | |
12801 | case ISA_MIPS5: | |
12802 | case ISA_MIPS64: | |
5f74bc13 | 12803 | case ISA_MIPS64R2: |
98d3f06f KH |
12804 | mips_opts.gp32 = 0; |
12805 | mips_opts.fp32 = 0; | |
12806 | break; | |
12807 | default: | |
12808 | as_bad (_("unknown ISA level %s"), name + 4); | |
12809 | break; | |
12810 | } | |
af7ee8bf | 12811 | if (reset) |
98d3f06f | 12812 | { |
af7ee8bf CD |
12813 | mips_opts.gp32 = file_mips_gp32; |
12814 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12815 | } |
252b5132 RH |
12816 | } |
12817 | else if (strcmp (name, "autoextend") == 0) | |
12818 | mips_opts.noautoextend = 0; | |
12819 | else if (strcmp (name, "noautoextend") == 0) | |
12820 | mips_opts.noautoextend = 1; | |
12821 | else if (strcmp (name, "push") == 0) | |
12822 | { | |
12823 | struct mips_option_stack *s; | |
12824 | ||
12825 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12826 | s->next = mips_opts_stack; | |
12827 | s->options = mips_opts; | |
12828 | mips_opts_stack = s; | |
12829 | } | |
12830 | else if (strcmp (name, "pop") == 0) | |
12831 | { | |
12832 | struct mips_option_stack *s; | |
12833 | ||
12834 | s = mips_opts_stack; | |
12835 | if (s == NULL) | |
12836 | as_bad (_(".set pop with no .set push")); | |
12837 | else | |
12838 | { | |
12839 | /* If we're changing the reorder mode we need to handle | |
12840 | delay slots correctly. */ | |
12841 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12842 | start_noreorder (); |
252b5132 | 12843 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12844 | end_noreorder (); |
252b5132 RH |
12845 | |
12846 | mips_opts = s->options; | |
12847 | mips_opts_stack = s->next; | |
12848 | free (s); | |
12849 | } | |
12850 | } | |
aed1a261 RS |
12851 | else if (strcmp (name, "sym32") == 0) |
12852 | mips_opts.sym32 = TRUE; | |
12853 | else if (strcmp (name, "nosym32") == 0) | |
12854 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
12855 | else if (strchr (name, ',')) |
12856 | { | |
12857 | /* Generic ".set" directive; use the generic handler. */ | |
12858 | *input_line_pointer = ch; | |
12859 | input_line_pointer = name; | |
12860 | s_set (0); | |
12861 | return; | |
12862 | } | |
252b5132 RH |
12863 | else |
12864 | { | |
12865 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12866 | } | |
12867 | *input_line_pointer = ch; | |
12868 | demand_empty_rest_of_line (); | |
12869 | } | |
12870 | ||
12871 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12872 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12873 | ||
12874 | static void | |
17a2f251 | 12875 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12876 | { |
12877 | mips_pic = SVR4_PIC; | |
143d77c5 | 12878 | mips_abicalls = TRUE; |
4d0d148d TS |
12879 | |
12880 | if (g_switch_seen && g_switch_value != 0) | |
12881 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12882 | g_switch_value = 0; | |
12883 | ||
252b5132 RH |
12884 | bfd_set_gp_size (stdoutput, 0); |
12885 | demand_empty_rest_of_line (); | |
12886 | } | |
12887 | ||
12888 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12889 | PIC code. It sets the $gp register for the function based on the | |
12890 | function address, which is in the register named in the argument. | |
12891 | This uses a relocation against _gp_disp, which is handled specially | |
12892 | by the linker. The result is: | |
12893 | lui $gp,%hi(_gp_disp) | |
12894 | addiu $gp,$gp,%lo(_gp_disp) | |
12895 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12896 | The .cpload argument is normally $25 == $t9. |
12897 | ||
12898 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12899 | lui $gp,%hi(__gnu_local_gp) |
12900 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12901 | and the argument is ignored. This saves an instruction, but the |
12902 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12903 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12904 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12905 | |
12906 | static void | |
17a2f251 | 12907 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12908 | { |
12909 | expressionS ex; | |
aa6975fb ILT |
12910 | int reg; |
12911 | int in_shared; | |
252b5132 | 12912 | |
6478892d TS |
12913 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12914 | .cpload is ignored. */ | |
12915 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12916 | { |
12917 | s_ignore (0); | |
12918 | return; | |
12919 | } | |
12920 | ||
d3ecfc59 | 12921 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12922 | if (mips_opts.noreorder == 0) |
12923 | as_warn (_(".cpload not in noreorder section")); | |
12924 | ||
aa6975fb ILT |
12925 | reg = tc_get_register (0); |
12926 | ||
12927 | /* If we need to produce a 64-bit address, we are better off using | |
12928 | the default instruction sequence. */ | |
aed1a261 | 12929 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12930 | |
252b5132 | 12931 | ex.X_op = O_symbol; |
bbe506e8 TS |
12932 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12933 | "__gnu_local_gp"); | |
252b5132 RH |
12934 | ex.X_op_symbol = NULL; |
12935 | ex.X_add_number = 0; | |
12936 | ||
12937 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12938 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12939 | |
584892a6 | 12940 | macro_start (); |
67c0d1eb RS |
12941 | macro_build_lui (&ex, mips_gp_register); |
12942 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12943 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12944 | if (in_shared) |
12945 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12946 | mips_gp_register, reg); | |
584892a6 | 12947 | macro_end (); |
252b5132 RH |
12948 | |
12949 | demand_empty_rest_of_line (); | |
12950 | } | |
12951 | ||
6478892d TS |
12952 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12953 | .cpsetup $reg1, offset|$reg2, label | |
12954 | ||
12955 | If offset is given, this results in: | |
12956 | sd $gp, offset($sp) | |
956cd1d6 | 12957 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12958 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12959 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12960 | |
12961 | If $reg2 is given, this results in: | |
12962 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12963 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12964 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12965 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12966 | $reg1 is normally $25 == $t9. |
12967 | ||
12968 | The -mno-shared option replaces the last three instructions with | |
12969 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12970 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12971 | |
6478892d | 12972 | static void |
17a2f251 | 12973 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12974 | { |
12975 | expressionS ex_off; | |
12976 | expressionS ex_sym; | |
12977 | int reg1; | |
6478892d | 12978 | |
8586fc66 | 12979 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12980 | We also need NewABI support. */ |
12981 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12982 | { | |
12983 | s_ignore (0); | |
12984 | return; | |
12985 | } | |
12986 | ||
12987 | reg1 = tc_get_register (0); | |
12988 | SKIP_WHITESPACE (); | |
12989 | if (*input_line_pointer != ',') | |
12990 | { | |
12991 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12992 | return; | |
12993 | } | |
12994 | else | |
80245285 | 12995 | ++input_line_pointer; |
6478892d TS |
12996 | SKIP_WHITESPACE (); |
12997 | if (*input_line_pointer == '$') | |
80245285 TS |
12998 | { |
12999 | mips_cpreturn_register = tc_get_register (0); | |
13000 | mips_cpreturn_offset = -1; | |
13001 | } | |
6478892d | 13002 | else |
80245285 TS |
13003 | { |
13004 | mips_cpreturn_offset = get_absolute_expression (); | |
13005 | mips_cpreturn_register = -1; | |
13006 | } | |
6478892d TS |
13007 | SKIP_WHITESPACE (); |
13008 | if (*input_line_pointer != ',') | |
13009 | { | |
13010 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13011 | return; | |
13012 | } | |
13013 | else | |
f9419b05 | 13014 | ++input_line_pointer; |
6478892d | 13015 | SKIP_WHITESPACE (); |
f21f8242 | 13016 | expression (&ex_sym); |
6478892d | 13017 | |
584892a6 | 13018 | macro_start (); |
6478892d TS |
13019 | if (mips_cpreturn_register == -1) |
13020 | { | |
13021 | ex_off.X_op = O_constant; | |
13022 | ex_off.X_add_symbol = NULL; | |
13023 | ex_off.X_op_symbol = NULL; | |
13024 | ex_off.X_add_number = mips_cpreturn_offset; | |
13025 | ||
67c0d1eb | 13026 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13027 | BFD_RELOC_LO16, SP); |
6478892d TS |
13028 | } |
13029 | else | |
67c0d1eb | 13030 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13031 | mips_gp_register, 0); |
6478892d | 13032 | |
aed1a261 | 13033 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13034 | { |
13035 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13036 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13037 | BFD_RELOC_HI16_S); | |
13038 | ||
13039 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13040 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13041 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13042 | ||
13043 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13044 | mips_gp_register, reg1); | |
13045 | } | |
13046 | else | |
13047 | { | |
13048 | expressionS ex; | |
13049 | ||
13050 | ex.X_op = O_symbol; | |
4184909a | 13051 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13052 | ex.X_op_symbol = NULL; |
13053 | ex.X_add_number = 0; | |
6e1304d8 | 13054 | |
aa6975fb ILT |
13055 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13056 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13057 | ||
13058 | macro_build_lui (&ex, mips_gp_register); | |
13059 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13060 | mips_gp_register, BFD_RELOC_LO16); | |
13061 | } | |
f21f8242 | 13062 | |
584892a6 | 13063 | macro_end (); |
6478892d TS |
13064 | |
13065 | demand_empty_rest_of_line (); | |
13066 | } | |
13067 | ||
13068 | static void | |
17a2f251 | 13069 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13070 | { |
13071 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13072 | .cplocal is ignored. */ |
6478892d TS |
13073 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13074 | { | |
13075 | s_ignore (0); | |
13076 | return; | |
13077 | } | |
13078 | ||
13079 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13080 | demand_empty_rest_of_line (); |
6478892d TS |
13081 | } |
13082 | ||
252b5132 RH |
13083 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13084 | offset from $sp. The offset is remembered, and after making a PIC | |
13085 | call $gp is restored from that location. */ | |
13086 | ||
13087 | static void | |
17a2f251 | 13088 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13089 | { |
13090 | expressionS ex; | |
252b5132 | 13091 | |
6478892d | 13092 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13093 | .cprestore is ignored. */ |
6478892d | 13094 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13095 | { |
13096 | s_ignore (0); | |
13097 | return; | |
13098 | } | |
13099 | ||
13100 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13101 | mips_cprestore_valid = 1; |
252b5132 RH |
13102 | |
13103 | ex.X_op = O_constant; | |
13104 | ex.X_add_symbol = NULL; | |
13105 | ex.X_op_symbol = NULL; | |
13106 | ex.X_add_number = mips_cprestore_offset; | |
13107 | ||
584892a6 | 13108 | macro_start (); |
67c0d1eb RS |
13109 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13110 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13111 | macro_end (); |
252b5132 RH |
13112 | |
13113 | demand_empty_rest_of_line (); | |
13114 | } | |
13115 | ||
6478892d | 13116 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13117 | was given in the preceding .cpsetup, it results in: |
6478892d | 13118 | ld $gp, offset($sp) |
76b3015f | 13119 | |
6478892d | 13120 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13121 | daddu $gp, $reg2, $0 */ |
13122 | ||
6478892d | 13123 | static void |
17a2f251 | 13124 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13125 | { |
13126 | expressionS ex; | |
6478892d TS |
13127 | |
13128 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13129 | We also need NewABI support. */ | |
13130 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13131 | { | |
13132 | s_ignore (0); | |
13133 | return; | |
13134 | } | |
13135 | ||
584892a6 | 13136 | macro_start (); |
6478892d TS |
13137 | if (mips_cpreturn_register == -1) |
13138 | { | |
13139 | ex.X_op = O_constant; | |
13140 | ex.X_add_symbol = NULL; | |
13141 | ex.X_op_symbol = NULL; | |
13142 | ex.X_add_number = mips_cpreturn_offset; | |
13143 | ||
67c0d1eb | 13144 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13145 | } |
13146 | else | |
67c0d1eb | 13147 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13148 | mips_cpreturn_register, 0); |
584892a6 | 13149 | macro_end (); |
6478892d TS |
13150 | |
13151 | demand_empty_rest_of_line (); | |
13152 | } | |
13153 | ||
741d6ea8 JM |
13154 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13155 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13156 | use in DWARF debug information. */ | |
13157 | ||
13158 | static void | |
13159 | s_dtprel_internal (size_t bytes) | |
13160 | { | |
13161 | expressionS ex; | |
13162 | char *p; | |
13163 | ||
13164 | expression (&ex); | |
13165 | ||
13166 | if (ex.X_op != O_symbol) | |
13167 | { | |
13168 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13169 | ? ".dtpreldword" | |
13170 | : ".dtprelword")); | |
13171 | ignore_rest_of_line (); | |
13172 | } | |
13173 | ||
13174 | p = frag_more (bytes); | |
13175 | md_number_to_chars (p, 0, bytes); | |
13176 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13177 | (bytes == 8 | |
13178 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13179 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13180 | ||
13181 | demand_empty_rest_of_line (); | |
13182 | } | |
13183 | ||
13184 | /* Handle .dtprelword. */ | |
13185 | ||
13186 | static void | |
13187 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13188 | { | |
13189 | s_dtprel_internal (4); | |
13190 | } | |
13191 | ||
13192 | /* Handle .dtpreldword. */ | |
13193 | ||
13194 | static void | |
13195 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13196 | { | |
13197 | s_dtprel_internal (8); | |
13198 | } | |
13199 | ||
6478892d TS |
13200 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13201 | code. It sets the offset to use in gp_rel relocations. */ | |
13202 | ||
13203 | static void | |
17a2f251 | 13204 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13205 | { |
13206 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13207 | We also need NewABI support. */ | |
13208 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13209 | { | |
13210 | s_ignore (0); | |
13211 | return; | |
13212 | } | |
13213 | ||
def2e0dd | 13214 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13215 | |
13216 | demand_empty_rest_of_line (); | |
13217 | } | |
13218 | ||
252b5132 RH |
13219 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13220 | code. It generates a 32 bit GP relative reloc. */ | |
13221 | ||
13222 | static void | |
17a2f251 | 13223 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13224 | { |
a8dbcb85 TS |
13225 | segment_info_type *si; |
13226 | struct insn_label_list *l; | |
252b5132 RH |
13227 | symbolS *label; |
13228 | expressionS ex; | |
13229 | char *p; | |
13230 | ||
13231 | /* When not generating PIC code, this is treated as .word. */ | |
13232 | if (mips_pic != SVR4_PIC) | |
13233 | { | |
13234 | s_cons (2); | |
13235 | return; | |
13236 | } | |
13237 | ||
a8dbcb85 TS |
13238 | si = seg_info (now_seg); |
13239 | l = si->label_list; | |
13240 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13241 | mips_emit_delays (); |
252b5132 RH |
13242 | if (auto_align) |
13243 | mips_align (2, 0, label); | |
13244 | mips_clear_insn_labels (); | |
13245 | ||
13246 | expression (&ex); | |
13247 | ||
13248 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13249 | { | |
13250 | as_bad (_("Unsupported use of .gpword")); | |
13251 | ignore_rest_of_line (); | |
13252 | } | |
13253 | ||
13254 | p = frag_more (4); | |
17a2f251 | 13255 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13256 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13257 | BFD_RELOC_GPREL32); |
252b5132 RH |
13258 | |
13259 | demand_empty_rest_of_line (); | |
13260 | } | |
13261 | ||
10181a0d | 13262 | static void |
17a2f251 | 13263 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13264 | { |
a8dbcb85 TS |
13265 | segment_info_type *si; |
13266 | struct insn_label_list *l; | |
10181a0d AO |
13267 | symbolS *label; |
13268 | expressionS ex; | |
13269 | char *p; | |
13270 | ||
13271 | /* When not generating PIC code, this is treated as .dword. */ | |
13272 | if (mips_pic != SVR4_PIC) | |
13273 | { | |
13274 | s_cons (3); | |
13275 | return; | |
13276 | } | |
13277 | ||
a8dbcb85 TS |
13278 | si = seg_info (now_seg); |
13279 | l = si->label_list; | |
13280 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13281 | mips_emit_delays (); |
10181a0d AO |
13282 | if (auto_align) |
13283 | mips_align (3, 0, label); | |
13284 | mips_clear_insn_labels (); | |
13285 | ||
13286 | expression (&ex); | |
13287 | ||
13288 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13289 | { | |
13290 | as_bad (_("Unsupported use of .gpdword")); | |
13291 | ignore_rest_of_line (); | |
13292 | } | |
13293 | ||
13294 | p = frag_more (8); | |
17a2f251 | 13295 | md_number_to_chars (p, 0, 8); |
a105a300 | 13296 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13297 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13298 | |
13299 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13300 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13301 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13302 | |
13303 | demand_empty_rest_of_line (); | |
13304 | } | |
13305 | ||
252b5132 RH |
13306 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13307 | tables in SVR4 PIC code. */ | |
13308 | ||
13309 | static void | |
17a2f251 | 13310 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13311 | { |
252b5132 RH |
13312 | int reg; |
13313 | ||
10181a0d AO |
13314 | /* This is ignored when not generating SVR4 PIC code. */ |
13315 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13316 | { |
13317 | s_ignore (0); | |
13318 | return; | |
13319 | } | |
13320 | ||
13321 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13322 | macro_start (); |
252b5132 | 13323 | reg = tc_get_register (0); |
67c0d1eb | 13324 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13325 | macro_end (); |
252b5132 | 13326 | |
bdaaa2e1 | 13327 | demand_empty_rest_of_line (); |
252b5132 RH |
13328 | } |
13329 | ||
13330 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13331 | mips16 mode. This permits the linker to handle them specially, | |
13332 | such as generating jalx instructions when needed. We also make | |
13333 | them odd for the duration of the assembly, in order to generate the | |
13334 | right sort of code. We will make them even in the adjust_symtab | |
13335 | routine, while leaving them marked. This is convenient for the | |
13336 | debugger and the disassembler. The linker knows to make them odd | |
13337 | again. */ | |
13338 | ||
13339 | static void | |
17a2f251 | 13340 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13341 | { |
f9419b05 | 13342 | mips16_mark_labels (); |
252b5132 RH |
13343 | |
13344 | demand_empty_rest_of_line (); | |
13345 | } | |
13346 | ||
13347 | /* Handle a .stabn directive. We need these in order to mark a label | |
13348 | as being a mips16 text label correctly. Sometimes the compiler | |
13349 | will emit a label, followed by a .stabn, and then switch sections. | |
13350 | If the label and .stabn are in mips16 mode, then the label is | |
13351 | really a mips16 text label. */ | |
13352 | ||
13353 | static void | |
17a2f251 | 13354 | s_mips_stab (int type) |
252b5132 | 13355 | { |
f9419b05 | 13356 | if (type == 'n') |
252b5132 RH |
13357 | mips16_mark_labels (); |
13358 | ||
13359 | s_stab (type); | |
13360 | } | |
13361 | ||
54f4ddb3 | 13362 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13363 | |
13364 | static void | |
17a2f251 | 13365 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13366 | { |
13367 | char *name; | |
13368 | int c; | |
13369 | symbolS *symbolP; | |
13370 | expressionS exp; | |
13371 | ||
13372 | name = input_line_pointer; | |
13373 | c = get_symbol_end (); | |
13374 | symbolP = symbol_find_or_make (name); | |
13375 | S_SET_WEAK (symbolP); | |
13376 | *input_line_pointer = c; | |
13377 | ||
13378 | SKIP_WHITESPACE (); | |
13379 | ||
13380 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13381 | { | |
13382 | if (S_IS_DEFINED (symbolP)) | |
13383 | { | |
956cd1d6 | 13384 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
13385 | S_GET_NAME (symbolP)); |
13386 | ignore_rest_of_line (); | |
13387 | return; | |
13388 | } | |
bdaaa2e1 | 13389 | |
252b5132 RH |
13390 | if (*input_line_pointer == ',') |
13391 | { | |
13392 | ++input_line_pointer; | |
13393 | SKIP_WHITESPACE (); | |
13394 | } | |
bdaaa2e1 | 13395 | |
252b5132 RH |
13396 | expression (&exp); |
13397 | if (exp.X_op != O_symbol) | |
13398 | { | |
13399 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13400 | ignore_rest_of_line (); |
252b5132 RH |
13401 | return; |
13402 | } | |
49309057 | 13403 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13404 | } |
13405 | ||
13406 | demand_empty_rest_of_line (); | |
13407 | } | |
13408 | ||
13409 | /* Parse a register string into a number. Called from the ECOFF code | |
13410 | to parse .frame. The argument is non-zero if this is the frame | |
13411 | register, so that we can record it in mips_frame_reg. */ | |
13412 | ||
13413 | int | |
17a2f251 | 13414 | tc_get_register (int frame) |
252b5132 | 13415 | { |
707bfff6 | 13416 | unsigned int reg; |
252b5132 RH |
13417 | |
13418 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13419 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13420 | reg = 0; | |
252b5132 | 13421 | if (frame) |
7a621144 DJ |
13422 | { |
13423 | mips_frame_reg = reg != 0 ? reg : SP; | |
13424 | mips_frame_reg_valid = 1; | |
13425 | mips_cprestore_valid = 0; | |
13426 | } | |
252b5132 RH |
13427 | return reg; |
13428 | } | |
13429 | ||
13430 | valueT | |
17a2f251 | 13431 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13432 | { |
13433 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13434 | ||
b4c71f56 TS |
13435 | if (IS_ELF) |
13436 | { | |
13437 | /* We don't need to align ELF sections to the full alignment. | |
13438 | However, Irix 5 may prefer that we align them at least to a 16 | |
13439 | byte boundary. We don't bother to align the sections if we | |
13440 | are targeted for an embedded system. */ | |
c41e87e3 | 13441 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13442 | return addr; |
13443 | if (align > 4) | |
13444 | align = 4; | |
13445 | } | |
252b5132 RH |
13446 | |
13447 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13448 | } | |
13449 | ||
13450 | /* Utility routine, called from above as well. If called while the | |
13451 | input file is still being read, it's only an approximation. (For | |
13452 | example, a symbol may later become defined which appeared to be | |
13453 | undefined earlier.) */ | |
13454 | ||
13455 | static int | |
17a2f251 | 13456 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13457 | { |
13458 | if (sym == 0) | |
13459 | return 0; | |
13460 | ||
4d0d148d | 13461 | if (g_switch_value > 0) |
252b5132 RH |
13462 | { |
13463 | const char *symname; | |
13464 | int change; | |
13465 | ||
c9914766 | 13466 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13467 | register. It can be if it is smaller than the -G size or if |
13468 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13469 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13470 | they can. */ |
13471 | symname = S_GET_NAME (sym); | |
13472 | if (symname != (const char *) NULL | |
13473 | && (strcmp (symname, "eprol") == 0 | |
13474 | || strcmp (symname, "etext") == 0 | |
13475 | || strcmp (symname, "_gp") == 0 | |
13476 | || strcmp (symname, "edata") == 0 | |
13477 | || strcmp (symname, "_fbss") == 0 | |
13478 | || strcmp (symname, "_fdata") == 0 | |
13479 | || strcmp (symname, "_ftext") == 0 | |
13480 | || strcmp (symname, "end") == 0 | |
13481 | || strcmp (symname, "_gp_disp") == 0)) | |
13482 | change = 1; | |
13483 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13484 | && (0 | |
13485 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13486 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13487 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13488 | <= g_switch_value)) | |
252b5132 RH |
13489 | #endif |
13490 | /* We must defer this decision until after the whole | |
13491 | file has been read, since there might be a .extern | |
13492 | after the first use of this symbol. */ | |
13493 | || (before_relaxing | |
13494 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13495 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13496 | #endif |
13497 | && S_GET_VALUE (sym) == 0) | |
13498 | || (S_GET_VALUE (sym) != 0 | |
13499 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13500 | change = 0; | |
13501 | else | |
13502 | { | |
13503 | const char *segname; | |
13504 | ||
13505 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13506 | assert (strcmp (segname, ".lit8") != 0 | |
13507 | && strcmp (segname, ".lit4") != 0); | |
13508 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13509 | && strcmp (segname, ".sbss") != 0 |
13510 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13511 | && strncmp (segname, ".sbss.", 6) != 0 |
13512 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13513 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13514 | } |
13515 | return change; | |
13516 | } | |
13517 | else | |
c9914766 | 13518 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13519 | return 1; |
13520 | } | |
13521 | ||
5919d012 RS |
13522 | |
13523 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13524 | ||
13525 | static bfd_boolean | |
17a2f251 | 13526 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13527 | { |
13528 | asection *symsec; | |
5919d012 RS |
13529 | |
13530 | /* Handle the case of a symbol equated to another symbol. */ | |
13531 | while (symbol_equated_reloc_p (sym)) | |
13532 | { | |
13533 | symbolS *n; | |
13534 | ||
5f0fe04b | 13535 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13536 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13537 | if (n == sym) | |
13538 | break; | |
13539 | sym = n; | |
13540 | } | |
13541 | ||
df1f3cda DD |
13542 | if (symbol_section_p (sym)) |
13543 | return TRUE; | |
13544 | ||
5919d012 RS |
13545 | symsec = S_GET_SEGMENT (sym); |
13546 | ||
5919d012 RS |
13547 | /* This must duplicate the test in adjust_reloc_syms. */ |
13548 | return (symsec != &bfd_und_section | |
13549 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13550 | && !bfd_is_com_section (symsec) |
13551 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13552 | #ifdef OBJ_ELF |
13553 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13554 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13555 | #endif |
13556 | ); | |
13557 | } | |
13558 | ||
13559 | ||
252b5132 RH |
13560 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13561 | extended opcode. SEC is the section the frag is in. */ | |
13562 | ||
13563 | static int | |
17a2f251 | 13564 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13565 | { |
13566 | int type; | |
3994f87e | 13567 | const struct mips16_immed_operand *op; |
252b5132 RH |
13568 | offsetT val; |
13569 | int mintiny, maxtiny; | |
13570 | segT symsec; | |
98aa84af | 13571 | fragS *sym_frag; |
252b5132 RH |
13572 | |
13573 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13574 | return 0; | |
13575 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13576 | return 1; | |
13577 | ||
13578 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13579 | op = mips16_immed_operands; | |
13580 | while (op->type != type) | |
13581 | { | |
13582 | ++op; | |
13583 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13584 | } | |
13585 | ||
13586 | if (op->unsp) | |
13587 | { | |
13588 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13589 | { | |
13590 | mintiny = 1; | |
13591 | maxtiny = 1 << op->nbits; | |
13592 | } | |
13593 | else | |
13594 | { | |
13595 | mintiny = 0; | |
13596 | maxtiny = (1 << op->nbits) - 1; | |
13597 | } | |
13598 | } | |
13599 | else | |
13600 | { | |
13601 | mintiny = - (1 << (op->nbits - 1)); | |
13602 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13603 | } | |
13604 | ||
98aa84af | 13605 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13606 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13607 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13608 | |
13609 | if (op->pcrel) | |
13610 | { | |
13611 | addressT addr; | |
13612 | ||
13613 | /* We won't have the section when we are called from | |
13614 | mips_relax_frag. However, we will always have been called | |
13615 | from md_estimate_size_before_relax first. If this is a | |
13616 | branch to a different section, we mark it as such. If SEC is | |
13617 | NULL, and the frag is not marked, then it must be a branch to | |
13618 | the same section. */ | |
13619 | if (sec == NULL) | |
13620 | { | |
13621 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13622 | return 1; | |
13623 | } | |
13624 | else | |
13625 | { | |
98aa84af | 13626 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13627 | if (symsec != sec) |
13628 | { | |
13629 | fragp->fr_subtype = | |
13630 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13631 | ||
13632 | /* FIXME: We should support this, and let the linker | |
13633 | catch branches and loads that are out of range. */ | |
13634 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13635 | _("unsupported PC relative reference to different section")); | |
13636 | ||
13637 | return 1; | |
13638 | } | |
98aa84af AM |
13639 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13640 | /* Assume non-extended on the first relaxation pass. | |
13641 | The address we have calculated will be bogus if this is | |
13642 | a forward branch to another frag, as the forward frag | |
13643 | will have fr_address == 0. */ | |
13644 | return 0; | |
252b5132 RH |
13645 | } |
13646 | ||
13647 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13648 | the same section. If the relax_marker of the symbol fragment |
13649 | differs from the relax_marker of this fragment, we have not | |
13650 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13651 | in STRETCH in order to get a better estimate of the address. |
13652 | This particularly matters because of the shift bits. */ | |
13653 | if (stretch != 0 | |
98aa84af | 13654 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13655 | { |
13656 | fragS *f; | |
13657 | ||
13658 | /* Adjust stretch for any alignment frag. Note that if have | |
13659 | been expanding the earlier code, the symbol may be | |
13660 | defined in what appears to be an earlier frag. FIXME: | |
13661 | This doesn't handle the fr_subtype field, which specifies | |
13662 | a maximum number of bytes to skip when doing an | |
13663 | alignment. */ | |
98aa84af | 13664 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13665 | { |
13666 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13667 | { | |
13668 | if (stretch < 0) | |
13669 | stretch = - ((- stretch) | |
13670 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13671 | else | |
13672 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13673 | if (stretch == 0) | |
13674 | break; | |
13675 | } | |
13676 | } | |
13677 | if (f != NULL) | |
13678 | val += stretch; | |
13679 | } | |
13680 | ||
13681 | addr = fragp->fr_address + fragp->fr_fix; | |
13682 | ||
13683 | /* The base address rules are complicated. The base address of | |
13684 | a branch is the following instruction. The base address of a | |
13685 | PC relative load or add is the instruction itself, but if it | |
13686 | is in a delay slot (in which case it can not be extended) use | |
13687 | the address of the instruction whose delay slot it is in. */ | |
13688 | if (type == 'p' || type == 'q') | |
13689 | { | |
13690 | addr += 2; | |
13691 | ||
13692 | /* If we are currently assuming that this frag should be | |
13693 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13694 | higher. */ |
252b5132 RH |
13695 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13696 | addr += 2; | |
13697 | ||
13698 | /* Ignore the low bit in the target, since it will be set | |
13699 | for a text label. */ | |
13700 | if ((val & 1) != 0) | |
13701 | --val; | |
13702 | } | |
13703 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13704 | addr -= 4; | |
13705 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13706 | addr -= 2; | |
13707 | ||
13708 | val -= addr & ~ ((1 << op->shift) - 1); | |
13709 | ||
13710 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13711 | if (type == 'p' || type == 'q') | |
13712 | val /= 2; | |
13713 | ||
13714 | /* If any of the shifted bits are set, we must use an extended | |
13715 | opcode. If the address depends on the size of this | |
13716 | instruction, this can lead to a loop, so we arrange to always | |
13717 | use an extended opcode. We only check this when we are in | |
13718 | the main relaxation loop, when SEC is NULL. */ | |
13719 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13720 | { | |
13721 | fragp->fr_subtype = | |
13722 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13723 | return 1; | |
13724 | } | |
13725 | ||
13726 | /* If we are about to mark a frag as extended because the value | |
13727 | is precisely maxtiny + 1, then there is a chance of an | |
13728 | infinite loop as in the following code: | |
13729 | la $4,foo | |
13730 | .skip 1020 | |
13731 | .align 2 | |
13732 | foo: | |
13733 | In this case when the la is extended, foo is 0x3fc bytes | |
13734 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13735 | the la must be extended. To avoid this loop, we mark the | |
13736 | frag as extended if it was small, and is about to become | |
13737 | extended with a value of maxtiny + 1. */ | |
13738 | if (val == ((maxtiny + 1) << op->shift) | |
13739 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13740 | && sec == NULL) | |
13741 | { | |
13742 | fragp->fr_subtype = | |
13743 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13744 | return 1; | |
13745 | } | |
13746 | } | |
13747 | else if (symsec != absolute_section && sec != NULL) | |
13748 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13749 | ||
13750 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13751 | || val < (mintiny << op->shift) | |
13752 | || val > (maxtiny << op->shift)) | |
13753 | return 1; | |
13754 | else | |
13755 | return 0; | |
13756 | } | |
13757 | ||
4a6a3df4 AO |
13758 | /* Compute the length of a branch sequence, and adjust the |
13759 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13760 | worst-case length is computed, with UPDATE being used to indicate | |
13761 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13762 | branch is to be computed. */ | |
13763 | static int | |
17a2f251 | 13764 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13765 | { |
b34976b6 | 13766 | bfd_boolean toofar; |
4a6a3df4 AO |
13767 | int length; |
13768 | ||
13769 | if (fragp | |
13770 | && S_IS_DEFINED (fragp->fr_symbol) | |
13771 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13772 | { | |
13773 | addressT addr; | |
13774 | offsetT val; | |
13775 | ||
13776 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13777 | ||
13778 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13779 | ||
13780 | val -= addr; | |
13781 | ||
13782 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13783 | } | |
13784 | else if (fragp) | |
13785 | /* If the symbol is not defined or it's in a different segment, | |
13786 | assume the user knows what's going on and emit a short | |
13787 | branch. */ | |
b34976b6 | 13788 | toofar = FALSE; |
4a6a3df4 | 13789 | else |
b34976b6 | 13790 | toofar = TRUE; |
4a6a3df4 AO |
13791 | |
13792 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13793 | fragp->fr_subtype | |
af6ae2ad | 13794 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13795 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13796 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13797 | toofar); | |
13798 | ||
13799 | length = 4; | |
13800 | if (toofar) | |
13801 | { | |
13802 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13803 | length += 8; | |
13804 | ||
13805 | if (mips_pic != NO_PIC) | |
13806 | { | |
13807 | /* Additional space for PIC loading of target address. */ | |
13808 | length += 8; | |
13809 | if (mips_opts.isa == ISA_MIPS1) | |
13810 | /* Additional space for $at-stabilizing nop. */ | |
13811 | length += 4; | |
13812 | } | |
13813 | ||
13814 | /* If branch is conditional. */ | |
13815 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13816 | length += 8; | |
13817 | } | |
b34976b6 | 13818 | |
4a6a3df4 AO |
13819 | return length; |
13820 | } | |
13821 | ||
252b5132 RH |
13822 | /* Estimate the size of a frag before relaxing. Unless this is the |
13823 | mips16, we are not really relaxing here, and the final size is | |
13824 | encoded in the subtype information. For the mips16, we have to | |
13825 | decide whether we are using an extended opcode or not. */ | |
13826 | ||
252b5132 | 13827 | int |
17a2f251 | 13828 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13829 | { |
5919d012 | 13830 | int change; |
252b5132 | 13831 | |
4a6a3df4 AO |
13832 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13833 | { | |
13834 | ||
b34976b6 AM |
13835 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13836 | ||
4a6a3df4 AO |
13837 | return fragp->fr_var; |
13838 | } | |
13839 | ||
252b5132 | 13840 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13841 | /* We don't want to modify the EXTENDED bit here; it might get us |
13842 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13843 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13844 | |
13845 | if (mips_pic == NO_PIC) | |
5919d012 | 13846 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13847 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13848 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13849 | else if (mips_pic == VXWORKS_PIC) |
13850 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13851 | change = 0; | |
252b5132 RH |
13852 | else |
13853 | abort (); | |
13854 | ||
13855 | if (change) | |
13856 | { | |
4d7206a2 | 13857 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13858 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13859 | } |
4d7206a2 RS |
13860 | else |
13861 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13862 | } |
13863 | ||
13864 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13865 | should be converted into a reloc against a section. */ |
252b5132 RH |
13866 | |
13867 | int | |
17a2f251 | 13868 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13869 | { |
252b5132 RH |
13870 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13871 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13872 | return 0; | |
a161fe53 | 13873 | |
252b5132 RH |
13874 | if (fixp->fx_addsy == NULL) |
13875 | return 1; | |
a161fe53 | 13876 | |
de7e6852 RS |
13877 | /* If symbol SYM is in a mergeable section, relocations of the form |
13878 | SYM + 0 can usually be made section-relative. The mergeable data | |
13879 | is then identified by the section offset rather than by the symbol. | |
13880 | ||
13881 | However, if we're generating REL LO16 relocations, the offset is split | |
13882 | between the LO16 and parterning high part relocation. The linker will | |
13883 | need to recalculate the complete offset in order to correctly identify | |
13884 | the merge data. | |
13885 | ||
13886 | The linker has traditionally not looked for the parterning high part | |
13887 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13888 | placed anywhere. Rather than break backwards compatibility by changing | |
13889 | this, it seems better not to force the issue, and instead keep the | |
13890 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13891 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13892 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13893 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13894 | && HAVE_IN_PLACE_ADDENDS |
13895 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13896 | return 0; | |
13897 | ||
252b5132 | 13898 | #ifdef OBJ_ELF |
b314ec0e RS |
13899 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
13900 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
13901 | relocations against MIPS16 functions; in this case, the stub becomes | |
13902 | the function's canonical address. | |
13903 | ||
13904 | Floating-point stubs are stored in unique .mips16.call.* or | |
13905 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
13906 | the first relocation in section S must be against F; this is how the | |
13907 | linker determines the target function. All relocations that might | |
13908 | resolve to T must also be against F. We therefore have the following | |
13909 | restrictions, which are given in an intentionally-redundant way: | |
13910 | ||
13911 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
13912 | symbols. | |
13913 | ||
13914 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
13915 | if that stub might be used. | |
13916 | ||
13917 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
13918 | symbols. | |
13919 | ||
13920 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
13921 | that stub might be used. | |
13922 | ||
13923 | There is a further restriction: | |
13924 | ||
13925 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
13926 | on targets with in-place addends; the relocation field cannot | |
13927 | encode the low bit. | |
13928 | ||
13929 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
13930 | against a MIPS16 symbol. | |
13931 | ||
13932 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
13933 | relocation against some symbol R, no relocation against R may be | |
13934 | reduced. (Note that this deals with (2) as well as (1) because | |
13935 | relocations against global symbols will never be reduced on ELF | |
13936 | targets.) This approach is a little simpler than trying to detect | |
13937 | stub sections, and gives the "all or nothing" per-symbol consistency | |
13938 | that we have for MIPS16 symbols. */ | |
f43abd2b | 13939 | if (IS_ELF |
b314ec0e RS |
13940 | && fixp->fx_subsy == NULL |
13941 | && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13942 | || *symbol_get_tc (fixp->fx_addsy))) | |
252b5132 RH |
13943 | return 0; |
13944 | #endif | |
a161fe53 | 13945 | |
252b5132 RH |
13946 | return 1; |
13947 | } | |
13948 | ||
13949 | /* Translate internal representation of relocation info to BFD target | |
13950 | format. */ | |
13951 | ||
13952 | arelent ** | |
17a2f251 | 13953 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13954 | { |
13955 | static arelent *retval[4]; | |
13956 | arelent *reloc; | |
13957 | bfd_reloc_code_real_type code; | |
13958 | ||
4b0cff4e TS |
13959 | memset (retval, 0, sizeof(retval)); |
13960 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13961 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13962 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13963 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13964 | ||
bad36eac DJ |
13965 | if (fixp->fx_pcrel) |
13966 | { | |
13967 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13968 | ||
13969 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13970 | Relocations want only the symbol offset. */ | |
13971 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13972 | if (!IS_ELF) |
bad36eac DJ |
13973 | { |
13974 | /* A gruesome hack which is a result of the gruesome gas | |
13975 | reloc handling. What's worse, for COFF (as opposed to | |
13976 | ECOFF), we might need yet another copy of reloc->address. | |
13977 | See bfd_install_relocation. */ | |
13978 | reloc->addend += reloc->address; | |
13979 | } | |
13980 | } | |
13981 | else | |
13982 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13983 | |
438c16b8 TS |
13984 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13985 | entry to be used in the relocation's section offset. */ | |
13986 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13987 | { |
13988 | reloc->address = reloc->addend; | |
13989 | reloc->addend = 0; | |
13990 | } | |
13991 | ||
252b5132 | 13992 | code = fixp->fx_r_type; |
252b5132 | 13993 | |
bad36eac | 13994 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13995 | if (reloc->howto == NULL) |
13996 | { | |
13997 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13998 | _("Can not represent %s relocation in this object file format"), | |
13999 | bfd_get_reloc_code_name (code)); | |
14000 | retval[0] = NULL; | |
14001 | } | |
14002 | ||
14003 | return retval; | |
14004 | } | |
14005 | ||
14006 | /* Relax a machine dependent frag. This returns the amount by which | |
14007 | the current size of the frag should change. */ | |
14008 | ||
14009 | int | |
17a2f251 | 14010 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14011 | { |
4a6a3df4 AO |
14012 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14013 | { | |
14014 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14015 | |
14016 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14017 | |
14018 | return fragp->fr_var - old_var; | |
14019 | } | |
14020 | ||
252b5132 RH |
14021 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14022 | return 0; | |
14023 | ||
c4e7957c | 14024 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14025 | { |
14026 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14027 | return 0; | |
14028 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14029 | return 2; | |
14030 | } | |
14031 | else | |
14032 | { | |
14033 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14034 | return 0; | |
14035 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14036 | return -2; | |
14037 | } | |
14038 | ||
14039 | return 0; | |
14040 | } | |
14041 | ||
14042 | /* Convert a machine dependent frag. */ | |
14043 | ||
14044 | void | |
17a2f251 | 14045 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14046 | { |
4a6a3df4 AO |
14047 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14048 | { | |
14049 | bfd_byte *buf; | |
14050 | unsigned long insn; | |
14051 | expressionS exp; | |
14052 | fixS *fixp; | |
b34976b6 | 14053 | |
4a6a3df4 AO |
14054 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14055 | ||
14056 | if (target_big_endian) | |
14057 | insn = bfd_getb32 (buf); | |
14058 | else | |
14059 | insn = bfd_getl32 (buf); | |
b34976b6 | 14060 | |
4a6a3df4 AO |
14061 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14062 | { | |
14063 | /* We generate a fixup instead of applying it right now | |
14064 | because, if there are linker relaxations, we're going to | |
14065 | need the relocations. */ | |
14066 | exp.X_op = O_symbol; | |
14067 | exp.X_add_symbol = fragp->fr_symbol; | |
14068 | exp.X_add_number = fragp->fr_offset; | |
14069 | ||
14070 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14071 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14072 | fixp->fx_file = fragp->fr_file; |
14073 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14074 | |
2132e3a3 | 14075 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14076 | buf += 4; |
14077 | } | |
14078 | else | |
14079 | { | |
14080 | int i; | |
14081 | ||
14082 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14083 | _("relaxed out-of-range branch into a jump")); | |
14084 | ||
14085 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14086 | goto uncond; | |
14087 | ||
14088 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14089 | { | |
14090 | /* Reverse the branch. */ | |
14091 | switch ((insn >> 28) & 0xf) | |
14092 | { | |
14093 | case 4: | |
14094 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14095 | have the condition reversed by tweaking a single | |
14096 | bit, and their opcodes all have 0x4???????. */ | |
14097 | assert ((insn & 0xf1000000) == 0x41000000); | |
14098 | insn ^= 0x00010000; | |
14099 | break; | |
14100 | ||
14101 | case 0: | |
14102 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14103 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
14104 | assert ((insn & 0xfc0e0000) == 0x04000000); |
14105 | insn ^= 0x00010000; | |
14106 | break; | |
b34976b6 | 14107 | |
4a6a3df4 AO |
14108 | case 1: |
14109 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14110 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14111 | insn ^= 0x04000000; |
14112 | break; | |
14113 | ||
14114 | default: | |
14115 | abort (); | |
14116 | } | |
14117 | } | |
14118 | ||
14119 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14120 | { | |
14121 | /* Clear the and-link bit. */ | |
14122 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
14123 | ||
54f4ddb3 TS |
14124 | /* bltzal 0x04100000 bgezal 0x04110000 |
14125 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14126 | insn &= ~0x00100000; |
14127 | } | |
14128 | ||
14129 | /* Branch over the branch (if the branch was likely) or the | |
14130 | full jump (not likely case). Compute the offset from the | |
14131 | current instruction to branch to. */ | |
14132 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14133 | i = 16; | |
14134 | else | |
14135 | { | |
14136 | /* How many bytes in instructions we've already emitted? */ | |
14137 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14138 | /* How many bytes in instructions from here to the end? */ | |
14139 | i = fragp->fr_var - i; | |
14140 | } | |
14141 | /* Convert to instruction count. */ | |
14142 | i >>= 2; | |
14143 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14144 | i--; |
4a6a3df4 AO |
14145 | insn |= i; |
14146 | /* Branch over the jump. */ | |
2132e3a3 | 14147 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14148 | buf += 4; |
14149 | ||
54f4ddb3 | 14150 | /* nop */ |
2132e3a3 | 14151 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14152 | buf += 4; |
14153 | ||
14154 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14155 | { | |
14156 | /* beql $0, $0, 2f */ | |
14157 | insn = 0x50000000; | |
14158 | /* Compute the PC offset from the current instruction to | |
14159 | the end of the variable frag. */ | |
14160 | /* How many bytes in instructions we've already emitted? */ | |
14161 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14162 | /* How many bytes in instructions from here to the end? */ | |
14163 | i = fragp->fr_var - i; | |
14164 | /* Convert to instruction count. */ | |
14165 | i >>= 2; | |
14166 | /* Don't decrement i, because we want to branch over the | |
14167 | delay slot. */ | |
14168 | ||
14169 | insn |= i; | |
2132e3a3 | 14170 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14171 | buf += 4; |
14172 | ||
2132e3a3 | 14173 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14174 | buf += 4; |
14175 | } | |
14176 | ||
14177 | uncond: | |
14178 | if (mips_pic == NO_PIC) | |
14179 | { | |
14180 | /* j or jal. */ | |
14181 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14182 | ? 0x0c000000 : 0x08000000); | |
14183 | exp.X_op = O_symbol; | |
14184 | exp.X_add_symbol = fragp->fr_symbol; | |
14185 | exp.X_add_number = fragp->fr_offset; | |
14186 | ||
14187 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14188 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14189 | fixp->fx_file = fragp->fr_file; |
14190 | fixp->fx_line = fragp->fr_line; | |
14191 | ||
2132e3a3 | 14192 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14193 | buf += 4; |
14194 | } | |
14195 | else | |
14196 | { | |
14197 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14198 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14199 | exp.X_op = O_symbol; | |
14200 | exp.X_add_symbol = fragp->fr_symbol; | |
14201 | exp.X_add_number = fragp->fr_offset; | |
14202 | ||
14203 | if (fragp->fr_offset) | |
14204 | { | |
14205 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14206 | exp.X_add_number = 0; | |
14207 | } | |
14208 | ||
14209 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14210 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14211 | fixp->fx_file = fragp->fr_file; |
14212 | fixp->fx_line = fragp->fr_line; | |
14213 | ||
2132e3a3 | 14214 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14215 | buf += 4; |
b34976b6 | 14216 | |
4a6a3df4 AO |
14217 | if (mips_opts.isa == ISA_MIPS1) |
14218 | { | |
14219 | /* nop */ | |
2132e3a3 | 14220 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14221 | buf += 4; |
14222 | } | |
14223 | ||
14224 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14225 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14226 | ||
14227 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14228 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14229 | fixp->fx_file = fragp->fr_file; |
14230 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14231 | |
2132e3a3 | 14232 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14233 | buf += 4; |
14234 | ||
14235 | /* j(al)r $at. */ | |
14236 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14237 | insn = 0x0020f809; | |
14238 | else | |
14239 | insn = 0x00200008; | |
14240 | ||
2132e3a3 | 14241 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14242 | buf += 4; |
14243 | } | |
14244 | } | |
14245 | ||
14246 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14247 | + fragp->fr_fix + fragp->fr_var); | |
14248 | ||
14249 | fragp->fr_fix += fragp->fr_var; | |
14250 | ||
14251 | return; | |
14252 | } | |
14253 | ||
252b5132 RH |
14254 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14255 | { | |
14256 | int type; | |
3994f87e | 14257 | const struct mips16_immed_operand *op; |
b34976b6 | 14258 | bfd_boolean small, ext; |
252b5132 RH |
14259 | offsetT val; |
14260 | bfd_byte *buf; | |
14261 | unsigned long insn; | |
b34976b6 | 14262 | bfd_boolean use_extend; |
252b5132 RH |
14263 | unsigned short extend; |
14264 | ||
14265 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14266 | op = mips16_immed_operands; | |
14267 | while (op->type != type) | |
14268 | ++op; | |
14269 | ||
14270 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14271 | { | |
b34976b6 AM |
14272 | small = FALSE; |
14273 | ext = TRUE; | |
252b5132 RH |
14274 | } |
14275 | else | |
14276 | { | |
b34976b6 AM |
14277 | small = TRUE; |
14278 | ext = FALSE; | |
252b5132 RH |
14279 | } |
14280 | ||
6386f3a7 | 14281 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14282 | val = S_GET_VALUE (fragp->fr_symbol); |
14283 | if (op->pcrel) | |
14284 | { | |
14285 | addressT addr; | |
14286 | ||
14287 | addr = fragp->fr_address + fragp->fr_fix; | |
14288 | ||
14289 | /* The rules for the base address of a PC relative reloc are | |
14290 | complicated; see mips16_extended_frag. */ | |
14291 | if (type == 'p' || type == 'q') | |
14292 | { | |
14293 | addr += 2; | |
14294 | if (ext) | |
14295 | addr += 2; | |
14296 | /* Ignore the low bit in the target, since it will be | |
14297 | set for a text label. */ | |
14298 | if ((val & 1) != 0) | |
14299 | --val; | |
14300 | } | |
14301 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14302 | addr -= 4; | |
14303 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14304 | addr -= 2; | |
14305 | ||
14306 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14307 | val -= addr; | |
14308 | ||
14309 | /* Make sure the section winds up with the alignment we have | |
14310 | assumed. */ | |
14311 | if (op->shift > 0) | |
14312 | record_alignment (asec, op->shift); | |
14313 | } | |
14314 | ||
14315 | if (ext | |
14316 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14317 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14318 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14319 | _("extended instruction in delay slot")); | |
14320 | ||
14321 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14322 | ||
14323 | if (target_big_endian) | |
14324 | insn = bfd_getb16 (buf); | |
14325 | else | |
14326 | insn = bfd_getl16 (buf); | |
14327 | ||
14328 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14329 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14330 | small, ext, &insn, &use_extend, &extend); | |
14331 | ||
14332 | if (use_extend) | |
14333 | { | |
2132e3a3 | 14334 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14335 | fragp->fr_fix += 2; |
14336 | buf += 2; | |
14337 | } | |
14338 | ||
2132e3a3 | 14339 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14340 | fragp->fr_fix += 2; |
14341 | buf += 2; | |
14342 | } | |
14343 | else | |
14344 | { | |
4d7206a2 RS |
14345 | int first, second; |
14346 | fixS *fixp; | |
252b5132 | 14347 | |
4d7206a2 RS |
14348 | first = RELAX_FIRST (fragp->fr_subtype); |
14349 | second = RELAX_SECOND (fragp->fr_subtype); | |
14350 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14351 | |
584892a6 RS |
14352 | /* Possibly emit a warning if we've chosen the longer option. */ |
14353 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14354 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14355 | { | |
14356 | const char *msg = macro_warning (fragp->fr_subtype); | |
14357 | if (msg != 0) | |
14358 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
14359 | } | |
14360 | ||
4d7206a2 RS |
14361 | /* Go through all the fixups for the first sequence. Disable them |
14362 | (by marking them as done) if we're going to use the second | |
14363 | sequence instead. */ | |
14364 | while (fixp | |
14365 | && fixp->fx_frag == fragp | |
14366 | && fixp->fx_where < fragp->fr_fix - second) | |
14367 | { | |
14368 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14369 | fixp->fx_done = 1; | |
14370 | fixp = fixp->fx_next; | |
14371 | } | |
252b5132 | 14372 | |
4d7206a2 RS |
14373 | /* Go through the fixups for the second sequence. Disable them if |
14374 | we're going to use the first sequence, otherwise adjust their | |
14375 | addresses to account for the relaxation. */ | |
14376 | while (fixp && fixp->fx_frag == fragp) | |
14377 | { | |
14378 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14379 | fixp->fx_where -= first; | |
14380 | else | |
14381 | fixp->fx_done = 1; | |
14382 | fixp = fixp->fx_next; | |
14383 | } | |
14384 | ||
14385 | /* Now modify the frag contents. */ | |
14386 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14387 | { | |
14388 | char *start; | |
14389 | ||
14390 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14391 | memmove (start, start + first, second); | |
14392 | fragp->fr_fix -= first; | |
14393 | } | |
14394 | else | |
14395 | fragp->fr_fix -= second; | |
252b5132 RH |
14396 | } |
14397 | } | |
14398 | ||
14399 | #ifdef OBJ_ELF | |
14400 | ||
14401 | /* This function is called after the relocs have been generated. | |
14402 | We've been storing mips16 text labels as odd. Here we convert them | |
14403 | back to even for the convenience of the debugger. */ | |
14404 | ||
14405 | void | |
17a2f251 | 14406 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14407 | { |
14408 | asymbol **syms; | |
14409 | unsigned int count, i; | |
14410 | ||
f43abd2b | 14411 | if (!IS_ELF) |
252b5132 RH |
14412 | return; |
14413 | ||
14414 | syms = bfd_get_outsymbols (stdoutput); | |
14415 | count = bfd_get_symcount (stdoutput); | |
14416 | for (i = 0; i < count; i++, syms++) | |
14417 | { | |
14418 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14419 | && ((*syms)->value & 1) != 0) | |
14420 | { | |
14421 | (*syms)->value &= ~1; | |
14422 | /* If the symbol has an odd size, it was probably computed | |
14423 | incorrectly, so adjust that as well. */ | |
14424 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14425 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14426 | } | |
14427 | } | |
14428 | } | |
14429 | ||
14430 | #endif | |
14431 | ||
14432 | /* This function is called whenever a label is defined. It is used | |
14433 | when handling branch delays; if a branch has a label, we assume we | |
14434 | can not move it. */ | |
14435 | ||
14436 | void | |
17a2f251 | 14437 | mips_define_label (symbolS *sym) |
252b5132 | 14438 | { |
a8dbcb85 | 14439 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14440 | struct insn_label_list *l; |
14441 | ||
14442 | if (free_insn_labels == NULL) | |
14443 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14444 | else | |
14445 | { | |
14446 | l = free_insn_labels; | |
14447 | free_insn_labels = l->next; | |
14448 | } | |
14449 | ||
14450 | l->label = sym; | |
a8dbcb85 TS |
14451 | l->next = si->label_list; |
14452 | si->label_list = l; | |
07a53e5c RH |
14453 | |
14454 | #ifdef OBJ_ELF | |
14455 | dwarf2_emit_label (sym); | |
14456 | #endif | |
252b5132 RH |
14457 | } |
14458 | \f | |
14459 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14460 | ||
14461 | /* Some special processing for a MIPS ELF file. */ | |
14462 | ||
14463 | void | |
17a2f251 | 14464 | mips_elf_final_processing (void) |
252b5132 RH |
14465 | { |
14466 | /* Write out the register information. */ | |
316f5878 | 14467 | if (mips_abi != N64_ABI) |
252b5132 RH |
14468 | { |
14469 | Elf32_RegInfo s; | |
14470 | ||
14471 | s.ri_gprmask = mips_gprmask; | |
14472 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14473 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14474 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14475 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14476 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14477 | ||
14478 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14479 | ((Elf32_External_RegInfo *) | |
14480 | mips_regmask_frag)); | |
14481 | } | |
14482 | else | |
14483 | { | |
14484 | Elf64_Internal_RegInfo s; | |
14485 | ||
14486 | s.ri_gprmask = mips_gprmask; | |
14487 | s.ri_pad = 0; | |
14488 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14489 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14490 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14491 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14492 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14493 | ||
14494 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14495 | ((Elf64_External_RegInfo *) | |
14496 | mips_regmask_frag)); | |
14497 | } | |
14498 | ||
14499 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14500 | sort of BFD interface for this. */ | |
14501 | if (mips_any_noreorder) | |
14502 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14503 | if (mips_pic != NO_PIC) | |
143d77c5 | 14504 | { |
252b5132 | 14505 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14506 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14507 | } | |
14508 | if (mips_abicalls) | |
14509 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14510 | |
98d3f06f | 14511 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14512 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14513 | file_ase_dsp is true. */ | |
8b082fb1 | 14514 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14515 | /* We may need to define a new flag for MT ASE, and set this flag when |
14516 | file_ase_mt is true. */ | |
a4672219 TS |
14517 | if (file_ase_mips16) |
14518 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14519 | #if 0 /* XXX FIXME */ |
14520 | if (file_ase_mips3d) | |
14521 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14522 | #endif | |
deec1734 CD |
14523 | if (file_ase_mdmx) |
14524 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14525 | |
bdaaa2e1 | 14526 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14527 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14528 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14529 | else if (mips_abi == O64_ABI) |
252b5132 | 14530 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14531 | else if (mips_abi == EABI_ABI) |
252b5132 | 14532 | { |
316f5878 | 14533 | if (!file_mips_gp32) |
252b5132 RH |
14534 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14535 | else | |
14536 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14537 | } | |
316f5878 | 14538 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14539 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14540 | ||
c9914766 | 14541 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14542 | |
14543 | if (mips_32bitmode) | |
14544 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14545 | |
14546 | #if 0 /* XXX FIXME */ | |
14547 | /* 32 bit code with 64 bit FP registers. */ | |
14548 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14549 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14550 | #endif | |
252b5132 RH |
14551 | } |
14552 | ||
14553 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14554 | \f | |
beae10d5 | 14555 | typedef struct proc { |
9b2f1d35 EC |
14556 | symbolS *func_sym; |
14557 | symbolS *func_end_sym; | |
beae10d5 KH |
14558 | unsigned long reg_mask; |
14559 | unsigned long reg_offset; | |
14560 | unsigned long fpreg_mask; | |
14561 | unsigned long fpreg_offset; | |
14562 | unsigned long frame_offset; | |
14563 | unsigned long frame_reg; | |
14564 | unsigned long pc_reg; | |
14565 | } procS; | |
252b5132 RH |
14566 | |
14567 | static procS cur_proc; | |
14568 | static procS *cur_proc_ptr; | |
14569 | static int numprocs; | |
14570 | ||
742a56fe RS |
14571 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14572 | nop as "0". */ | |
14573 | ||
14574 | char | |
14575 | mips_nop_opcode (void) | |
14576 | { | |
14577 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14578 | } | |
14579 | ||
14580 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14581 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14582 | |
0a9ef439 | 14583 | void |
17a2f251 | 14584 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14585 | { |
742a56fe RS |
14586 | char *p; |
14587 | ||
0a9ef439 RH |
14588 | if (fragp->fr_type != rs_align_code) |
14589 | return; | |
14590 | ||
742a56fe RS |
14591 | p = fragp->fr_literal + fragp->fr_fix; |
14592 | if (*p) | |
a19d8eb0 | 14593 | { |
0a9ef439 | 14594 | int bytes; |
a19d8eb0 | 14595 | |
0a9ef439 | 14596 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
0a9ef439 RH |
14597 | if (bytes & 1) |
14598 | { | |
14599 | *p++ = 0; | |
f9419b05 | 14600 | fragp->fr_fix++; |
0a9ef439 | 14601 | } |
742a56fe | 14602 | md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2); |
0a9ef439 | 14603 | fragp->fr_var = 2; |
a19d8eb0 | 14604 | } |
a19d8eb0 CP |
14605 | } |
14606 | ||
252b5132 | 14607 | static void |
17a2f251 | 14608 | md_obj_begin (void) |
252b5132 RH |
14609 | { |
14610 | } | |
14611 | ||
14612 | static void | |
17a2f251 | 14613 | md_obj_end (void) |
252b5132 | 14614 | { |
54f4ddb3 | 14615 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14616 | if (cur_proc_ptr) |
9a41af64 | 14617 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14618 | } |
14619 | ||
14620 | static long | |
17a2f251 | 14621 | get_number (void) |
252b5132 RH |
14622 | { |
14623 | int negative = 0; | |
14624 | long val = 0; | |
14625 | ||
14626 | if (*input_line_pointer == '-') | |
14627 | { | |
14628 | ++input_line_pointer; | |
14629 | negative = 1; | |
14630 | } | |
3882b010 | 14631 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14632 | as_bad (_("expected simple number")); |
252b5132 RH |
14633 | if (input_line_pointer[0] == '0') |
14634 | { | |
14635 | if (input_line_pointer[1] == 'x') | |
14636 | { | |
14637 | input_line_pointer += 2; | |
3882b010 | 14638 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14639 | { |
14640 | val <<= 4; | |
14641 | val |= hex_value (*input_line_pointer++); | |
14642 | } | |
14643 | return negative ? -val : val; | |
14644 | } | |
14645 | else | |
14646 | { | |
14647 | ++input_line_pointer; | |
3882b010 | 14648 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14649 | { |
14650 | val <<= 3; | |
14651 | val |= *input_line_pointer++ - '0'; | |
14652 | } | |
14653 | return negative ? -val : val; | |
14654 | } | |
14655 | } | |
3882b010 | 14656 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14657 | { |
14658 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14659 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14660 | as_warn (_("invalid number")); |
252b5132 RH |
14661 | return -1; |
14662 | } | |
3882b010 | 14663 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14664 | { |
14665 | val *= 10; | |
14666 | val += *input_line_pointer++ - '0'; | |
14667 | } | |
14668 | return negative ? -val : val; | |
14669 | } | |
14670 | ||
14671 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14672 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14673 | case .file implies DWARF-2. */ | |
14674 | ||
14675 | static void | |
17a2f251 | 14676 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14677 | { |
ecb4347a DJ |
14678 | static int first_file_directive = 0; |
14679 | ||
c5dd6aab DJ |
14680 | if (ECOFF_DEBUGGING) |
14681 | { | |
14682 | get_number (); | |
14683 | s_app_file (0); | |
14684 | } | |
14685 | else | |
ecb4347a DJ |
14686 | { |
14687 | char *filename; | |
14688 | ||
14689 | filename = dwarf2_directive_file (0); | |
14690 | ||
14691 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14692 | directive even for stabs output. Make sure that this | |
14693 | ".file" is handled. Note that you need a version of GCC | |
14694 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14695 | if (filename != NULL && ! first_file_directive) | |
14696 | { | |
14697 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14698 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14699 | } |
14700 | first_file_directive = 1; | |
14701 | } | |
c5dd6aab DJ |
14702 | } |
14703 | ||
14704 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14705 | |
14706 | static void | |
17a2f251 | 14707 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14708 | { |
c5dd6aab DJ |
14709 | if (!ECOFF_DEBUGGING) |
14710 | dwarf2_directive_loc (0); | |
252b5132 RH |
14711 | } |
14712 | ||
252b5132 RH |
14713 | /* The .end directive. */ |
14714 | ||
14715 | static void | |
17a2f251 | 14716 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14717 | { |
14718 | symbolS *p; | |
252b5132 | 14719 | |
7a621144 DJ |
14720 | /* Following functions need their own .frame and .cprestore directives. */ |
14721 | mips_frame_reg_valid = 0; | |
14722 | mips_cprestore_valid = 0; | |
14723 | ||
252b5132 RH |
14724 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14725 | { | |
14726 | p = get_symbol (); | |
14727 | demand_empty_rest_of_line (); | |
14728 | } | |
14729 | else | |
14730 | p = NULL; | |
14731 | ||
14949570 | 14732 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14733 | as_warn (_(".end not in text section")); |
14734 | ||
14735 | if (!cur_proc_ptr) | |
14736 | { | |
14737 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14738 | demand_empty_rest_of_line (); | |
14739 | return; | |
14740 | } | |
14741 | ||
14742 | if (p != NULL) | |
14743 | { | |
14744 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14745 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14746 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14747 | |
14748 | if (debug_type == DEBUG_STABS) | |
14749 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14750 | S_GET_NAME (p)); | |
252b5132 RH |
14751 | } |
14752 | else | |
14753 | as_warn (_(".end directive missing or unknown symbol")); | |
14754 | ||
2132e3a3 | 14755 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14756 | /* Create an expression to calculate the size of the function. */ |
14757 | if (p && cur_proc_ptr) | |
14758 | { | |
14759 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14760 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14761 | ||
14762 | obj->size = exp; | |
14763 | exp->X_op = O_subtract; | |
14764 | exp->X_add_symbol = symbol_temp_new_now (); | |
14765 | exp->X_op_symbol = p; | |
14766 | exp->X_add_number = 0; | |
14767 | ||
14768 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14769 | } | |
14770 | ||
ecb4347a | 14771 | /* Generate a .pdr section. */ |
f43abd2b | 14772 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14773 | { |
14774 | segT saved_seg = now_seg; | |
14775 | subsegT saved_subseg = now_subseg; | |
14776 | valueT dot; | |
14777 | expressionS exp; | |
14778 | char *fragp; | |
252b5132 | 14779 | |
ecb4347a | 14780 | dot = frag_now_fix (); |
252b5132 RH |
14781 | |
14782 | #ifdef md_flush_pending_output | |
ecb4347a | 14783 | md_flush_pending_output (); |
252b5132 RH |
14784 | #endif |
14785 | ||
ecb4347a DJ |
14786 | assert (pdr_seg); |
14787 | subseg_set (pdr_seg, 0); | |
252b5132 | 14788 | |
ecb4347a DJ |
14789 | /* Write the symbol. */ |
14790 | exp.X_op = O_symbol; | |
14791 | exp.X_add_symbol = p; | |
14792 | exp.X_add_number = 0; | |
14793 | emit_expr (&exp, 4); | |
252b5132 | 14794 | |
ecb4347a | 14795 | fragp = frag_more (7 * 4); |
252b5132 | 14796 | |
17a2f251 TS |
14797 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14798 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14799 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14800 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14801 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14802 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14803 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14804 | |
ecb4347a DJ |
14805 | subseg_set (saved_seg, saved_subseg); |
14806 | } | |
14807 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14808 | |
14809 | cur_proc_ptr = NULL; | |
14810 | } | |
14811 | ||
14812 | /* The .aent and .ent directives. */ | |
14813 | ||
14814 | static void | |
17a2f251 | 14815 | s_mips_ent (int aent) |
252b5132 | 14816 | { |
252b5132 | 14817 | symbolS *symbolP; |
252b5132 RH |
14818 | |
14819 | symbolP = get_symbol (); | |
14820 | if (*input_line_pointer == ',') | |
f9419b05 | 14821 | ++input_line_pointer; |
252b5132 | 14822 | SKIP_WHITESPACE (); |
3882b010 | 14823 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14824 | || *input_line_pointer == '-') |
874e8986 | 14825 | get_number (); |
252b5132 | 14826 | |
14949570 | 14827 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14828 | as_warn (_(".ent or .aent not in text section.")); |
14829 | ||
14830 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14831 | as_warn (_("missing .end")); |
252b5132 RH |
14832 | |
14833 | if (!aent) | |
14834 | { | |
7a621144 DJ |
14835 | /* This function needs its own .frame and .cprestore directives. */ |
14836 | mips_frame_reg_valid = 0; | |
14837 | mips_cprestore_valid = 0; | |
14838 | ||
252b5132 RH |
14839 | cur_proc_ptr = &cur_proc; |
14840 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14841 | ||
9b2f1d35 | 14842 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14843 | |
49309057 | 14844 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14845 | |
f9419b05 | 14846 | ++numprocs; |
ecb4347a DJ |
14847 | |
14848 | if (debug_type == DEBUG_STABS) | |
14849 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14850 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14851 | } |
14852 | ||
14853 | demand_empty_rest_of_line (); | |
14854 | } | |
14855 | ||
14856 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14857 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14858 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14859 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14860 | symbol table (in the mdebug section). */ |
14861 | ||
14862 | static void | |
17a2f251 | 14863 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14864 | { |
ecb4347a | 14865 | #ifdef OBJ_ELF |
f43abd2b | 14866 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14867 | { |
14868 | long val; | |
252b5132 | 14869 | |
ecb4347a DJ |
14870 | if (cur_proc_ptr == (procS *) NULL) |
14871 | { | |
14872 | as_warn (_(".frame outside of .ent")); | |
14873 | demand_empty_rest_of_line (); | |
14874 | return; | |
14875 | } | |
252b5132 | 14876 | |
ecb4347a DJ |
14877 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14878 | ||
14879 | SKIP_WHITESPACE (); | |
14880 | if (*input_line_pointer++ != ',' | |
14881 | || get_absolute_expression_and_terminator (&val) != ',') | |
14882 | { | |
14883 | as_warn (_("Bad .frame directive")); | |
14884 | --input_line_pointer; | |
14885 | demand_empty_rest_of_line (); | |
14886 | return; | |
14887 | } | |
252b5132 | 14888 | |
ecb4347a DJ |
14889 | cur_proc_ptr->frame_offset = val; |
14890 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14891 | |
252b5132 | 14892 | demand_empty_rest_of_line (); |
252b5132 | 14893 | } |
ecb4347a DJ |
14894 | else |
14895 | #endif /* OBJ_ELF */ | |
14896 | s_ignore (ignore); | |
252b5132 RH |
14897 | } |
14898 | ||
bdaaa2e1 KH |
14899 | /* The .fmask and .mask directives. If the mdebug section is present |
14900 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14901 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14902 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14903 | make reference to the ecoff symbol table (in the mdebug section). */ |
14904 | ||
14905 | static void | |
17a2f251 | 14906 | s_mips_mask (int reg_type) |
252b5132 | 14907 | { |
ecb4347a | 14908 | #ifdef OBJ_ELF |
f43abd2b | 14909 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14910 | { |
ecb4347a | 14911 | long mask, off; |
252b5132 | 14912 | |
ecb4347a DJ |
14913 | if (cur_proc_ptr == (procS *) NULL) |
14914 | { | |
14915 | as_warn (_(".mask/.fmask outside of .ent")); | |
14916 | demand_empty_rest_of_line (); | |
14917 | return; | |
14918 | } | |
252b5132 | 14919 | |
ecb4347a DJ |
14920 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14921 | { | |
14922 | as_warn (_("Bad .mask/.fmask directive")); | |
14923 | --input_line_pointer; | |
14924 | demand_empty_rest_of_line (); | |
14925 | return; | |
14926 | } | |
252b5132 | 14927 | |
ecb4347a DJ |
14928 | off = get_absolute_expression (); |
14929 | ||
14930 | if (reg_type == 'F') | |
14931 | { | |
14932 | cur_proc_ptr->fpreg_mask = mask; | |
14933 | cur_proc_ptr->fpreg_offset = off; | |
14934 | } | |
14935 | else | |
14936 | { | |
14937 | cur_proc_ptr->reg_mask = mask; | |
14938 | cur_proc_ptr->reg_offset = off; | |
14939 | } | |
14940 | ||
14941 | demand_empty_rest_of_line (); | |
252b5132 RH |
14942 | } |
14943 | else | |
ecb4347a DJ |
14944 | #endif /* OBJ_ELF */ |
14945 | s_ignore (reg_type); | |
252b5132 RH |
14946 | } |
14947 | ||
316f5878 RS |
14948 | /* A table describing all the processors gas knows about. Names are |
14949 | matched in the order listed. | |
e7af610e | 14950 | |
316f5878 RS |
14951 | To ease comparison, please keep this table in the same order as |
14952 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14953 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14954 | { | |
316f5878 | 14955 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14956 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14957 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14958 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14959 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14960 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14961 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14962 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14963 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14964 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14965 | |
14966 | /* MIPS I */ | |
ad3fea08 TS |
14967 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14968 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14969 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14970 | |
14971 | /* MIPS II */ | |
ad3fea08 | 14972 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14973 | |
14974 | /* MIPS III */ | |
ad3fea08 TS |
14975 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14976 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14977 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14978 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14979 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14980 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14981 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14982 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14983 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14984 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14985 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14986 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
14987 | /* ST Microelectronics Loongson 2E and 2F cores */ |
14988 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
14989 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
14990 | |
14991 | /* MIPS IV */ | |
ad3fea08 TS |
14992 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14993 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14994 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14995 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14996 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14997 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14998 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14999 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15000 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15001 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15002 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15003 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15004 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15005 | |
15006 | /* MIPS 32 */ | |
ad3fea08 TS |
15007 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15008 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15009 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15010 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15011 | ||
15012 | /* MIPS 32 Release 2 */ | |
15013 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15014 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15015 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15016 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15017 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15018 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15019 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15020 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15021 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15022 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15023 | /* Deprecated forms of the above. */ | |
15024 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15025 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15026 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15027 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15028 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15029 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15030 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15031 | /* Deprecated forms of the above. */ | |
15032 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15033 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15034 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15035 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15036 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15037 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15038 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15039 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15040 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15041 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15042 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15043 | /* Deprecated forms of the above. */ | |
15044 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15045 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15046 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15047 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15048 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15049 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15050 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15051 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15052 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15053 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15054 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15055 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15056 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15057 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15058 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15059 | /* Deprecated forms of the above. */ | |
15060 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15061 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15062 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15063 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15064 | |
316f5878 | 15065 | /* MIPS 64 */ |
ad3fea08 TS |
15066 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15067 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15068 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15069 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
15070 | |
15071 | /* MIPS 64 Release 2 */ | |
e7af610e | 15072 | |
c7a23324 | 15073 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15074 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15075 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15076 | /* Broadcom SB-1A CPU core */ |
15077 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15078 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 15079 | |
967344c6 AN |
15080 | /* Cavium Networks Octeon CPU core */ |
15081 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15082 | ||
316f5878 RS |
15083 | /* End marker */ |
15084 | { NULL, 0, 0, 0 } | |
15085 | }; | |
e7af610e | 15086 | |
84ea6cf2 | 15087 | |
316f5878 RS |
15088 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15089 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15090 | |
316f5878 | 15091 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15092 | |
b34976b6 | 15093 | static bfd_boolean |
17a2f251 | 15094 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15095 | { |
15096 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15097 | given++, canonical++; | |
15098 | ||
15099 | return ((*given == 0 && *canonical == 0) | |
15100 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15101 | } | |
15102 | ||
15103 | ||
15104 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15105 | CPU name. We've traditionally allowed a lot of variation here. | |
15106 | ||
15107 | Note: this function is shared between GCC and GAS. */ | |
15108 | ||
b34976b6 | 15109 | static bfd_boolean |
17a2f251 | 15110 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15111 | { |
15112 | /* First see if the name matches exactly, or with a final "000" | |
15113 | turned into "k". */ | |
15114 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15115 | return TRUE; |
316f5878 RS |
15116 | |
15117 | /* If not, try comparing based on numerical designation alone. | |
15118 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15119 | if (TOLOWER (*given) == 'r') | |
15120 | given++; | |
15121 | if (!ISDIGIT (*given)) | |
b34976b6 | 15122 | return FALSE; |
316f5878 RS |
15123 | |
15124 | /* Skip over some well-known prefixes in the canonical name, | |
15125 | hoping to find a number there too. */ | |
15126 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15127 | canonical += 2; | |
15128 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15129 | canonical += 2; | |
15130 | else if (TOLOWER (canonical[0]) == 'r') | |
15131 | canonical += 1; | |
15132 | ||
15133 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15134 | } | |
15135 | ||
15136 | ||
15137 | /* Parse an option that takes the name of a processor as its argument. | |
15138 | OPTION is the name of the option and CPU_STRING is the argument. | |
15139 | Return the corresponding processor enumeration if the CPU_STRING is | |
15140 | recognized, otherwise report an error and return null. | |
15141 | ||
15142 | A similar function exists in GCC. */ | |
e7af610e NC |
15143 | |
15144 | static const struct mips_cpu_info * | |
17a2f251 | 15145 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15146 | { |
316f5878 | 15147 | const struct mips_cpu_info *p; |
e7af610e | 15148 | |
316f5878 RS |
15149 | /* 'from-abi' selects the most compatible architecture for the given |
15150 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15151 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15152 | version. Look first at the -mgp options, if given, otherwise base | |
15153 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15154 | |
316f5878 RS |
15155 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15156 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15157 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15158 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15159 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15160 | { | |
15161 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15162 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15163 | ||
15164 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15165 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15166 | ||
15167 | if (file_mips_gp32 >= 0) | |
15168 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15169 | ||
15170 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15171 | ? ISA_MIPS3 | |
15172 | : ISA_MIPS1); | |
15173 | } | |
15174 | ||
15175 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15176 | if (strcasecmp (cpu_string, "default") == 0) | |
15177 | return 0; | |
15178 | ||
15179 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15180 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15181 | return p; | |
15182 | ||
15183 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
15184 | return 0; | |
e7af610e NC |
15185 | } |
15186 | ||
316f5878 RS |
15187 | /* Return the canonical processor information for ISA (a member of the |
15188 | ISA_MIPS* enumeration). */ | |
15189 | ||
e7af610e | 15190 | static const struct mips_cpu_info * |
17a2f251 | 15191 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15192 | { |
15193 | int i; | |
15194 | ||
15195 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15196 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15197 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15198 | return (&mips_cpu_info_table[i]); |
15199 | ||
e972090a | 15200 | return NULL; |
e7af610e | 15201 | } |
fef14a42 TS |
15202 | |
15203 | static const struct mips_cpu_info * | |
17a2f251 | 15204 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15205 | { |
15206 | int i; | |
15207 | ||
15208 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15209 | if (arch == mips_cpu_info_table[i].cpu) | |
15210 | return (&mips_cpu_info_table[i]); | |
15211 | ||
15212 | return NULL; | |
15213 | } | |
316f5878 RS |
15214 | \f |
15215 | static void | |
17a2f251 | 15216 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15217 | { |
15218 | if (*first_p) | |
15219 | { | |
15220 | fprintf (stream, "%24s", ""); | |
15221 | *col_p = 24; | |
15222 | } | |
15223 | else | |
15224 | { | |
15225 | fprintf (stream, ", "); | |
15226 | *col_p += 2; | |
15227 | } | |
e7af610e | 15228 | |
316f5878 RS |
15229 | if (*col_p + strlen (string) > 72) |
15230 | { | |
15231 | fprintf (stream, "\n%24s", ""); | |
15232 | *col_p = 24; | |
15233 | } | |
15234 | ||
15235 | fprintf (stream, "%s", string); | |
15236 | *col_p += strlen (string); | |
15237 | ||
15238 | *first_p = 0; | |
15239 | } | |
15240 | ||
15241 | void | |
17a2f251 | 15242 | md_show_usage (FILE *stream) |
e7af610e | 15243 | { |
316f5878 RS |
15244 | int column, first; |
15245 | size_t i; | |
15246 | ||
15247 | fprintf (stream, _("\ | |
15248 | MIPS options:\n\ | |
316f5878 RS |
15249 | -EB generate big endian output\n\ |
15250 | -EL generate little endian output\n\ | |
15251 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15252 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15253 | implicitly with the gp register [default 8]\n")); | |
15254 | fprintf (stream, _("\ | |
15255 | -mips1 generate MIPS ISA I instructions\n\ | |
15256 | -mips2 generate MIPS ISA II instructions\n\ | |
15257 | -mips3 generate MIPS ISA III instructions\n\ | |
15258 | -mips4 generate MIPS ISA IV instructions\n\ | |
15259 | -mips5 generate MIPS ISA V instructions\n\ | |
15260 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15261 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15262 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15263 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15264 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15265 | ||
15266 | first = 1; | |
e7af610e NC |
15267 | |
15268 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15269 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15270 | show (stream, "from-abi", &column, &first); | |
15271 | fputc ('\n', stream); | |
e7af610e | 15272 | |
316f5878 RS |
15273 | fprintf (stream, _("\ |
15274 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15275 | -no-mCPU don't generate code specific to CPU.\n\ | |
15276 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15277 | ||
15278 | first = 1; | |
15279 | ||
15280 | show (stream, "3900", &column, &first); | |
15281 | show (stream, "4010", &column, &first); | |
15282 | show (stream, "4100", &column, &first); | |
15283 | show (stream, "4650", &column, &first); | |
15284 | fputc ('\n', stream); | |
15285 | ||
15286 | fprintf (stream, _("\ | |
15287 | -mips16 generate mips16 instructions\n\ | |
15288 | -no-mips16 do not generate mips16 instructions\n")); | |
15289 | fprintf (stream, _("\ | |
e16bfa71 TS |
15290 | -msmartmips generate smartmips instructions\n\ |
15291 | -mno-smartmips do not generate smartmips instructions\n")); | |
15292 | fprintf (stream, _("\ | |
74cd071d CF |
15293 | -mdsp generate DSP instructions\n\ |
15294 | -mno-dsp do not generate DSP instructions\n")); | |
15295 | fprintf (stream, _("\ | |
8b082fb1 TS |
15296 | -mdspr2 generate DSP R2 instructions\n\ |
15297 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15298 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15299 | -mmt generate MT instructions\n\ |
15300 | -mno-mt do not generate MT instructions\n")); | |
15301 | fprintf (stream, _("\ | |
d766e8ec | 15302 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15303 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
15304 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15305 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15306 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15307 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15308 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15309 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15310 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15311 | fprintf (stream, _("\ |
15312 | -mhard-float allow floating-point instructions\n\ | |
15313 | -msoft-float do not allow floating-point instructions\n\ | |
15314 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15315 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15316 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15317 | )); | |
316f5878 RS |
15318 | #ifdef OBJ_ELF |
15319 | fprintf (stream, _("\ | |
15320 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
0c000745 | 15321 | -mvxworks-pic generate VxWorks position independent code\n\ |
316f5878 RS |
15322 | -non_shared do not generate position independent code\n\ |
15323 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 15324 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15325 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15326 | position dependent (non shared) code\n\ |
316f5878 RS |
15327 | -mabi=ABI create ABI conformant object file for:\n")); |
15328 | ||
15329 | first = 1; | |
15330 | ||
15331 | show (stream, "32", &column, &first); | |
15332 | show (stream, "o64", &column, &first); | |
15333 | show (stream, "n32", &column, &first); | |
15334 | show (stream, "64", &column, &first); | |
15335 | show (stream, "eabi", &column, &first); | |
15336 | ||
15337 | fputc ('\n', stream); | |
15338 | ||
15339 | fprintf (stream, _("\ | |
15340 | -32 create o32 ABI object file (default)\n\ | |
15341 | -n32 create n32 ABI object file\n\ | |
15342 | -64 create 64 ABI object file\n")); | |
15343 | #endif | |
e7af610e | 15344 | } |
14e777e0 KB |
15345 | |
15346 | enum dwarf2_format | |
17a2f251 | 15347 | mips_dwarf2_format (void) |
14e777e0 | 15348 | { |
369943fe | 15349 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15350 | { |
15351 | #ifdef TE_IRIX | |
15352 | return dwarf2_format_64bit_irix; | |
15353 | #else | |
15354 | return dwarf2_format_64bit; | |
15355 | #endif | |
15356 | } | |
14e777e0 KB |
15357 | else |
15358 | return dwarf2_format_32bit; | |
15359 | } | |
73369e65 EC |
15360 | |
15361 | int | |
15362 | mips_dwarf2_addr_size (void) | |
15363 | { | |
369943fe | 15364 | if (HAVE_64BIT_SYMBOLS) |
73369e65 | 15365 | return 8; |
73369e65 EC |
15366 | else |
15367 | return 4; | |
15368 | } | |
5862107c EC |
15369 | |
15370 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15371 | void | |
15372 | mips_cfi_frame_initial_instructions (void) | |
15373 | { | |
15374 | cfi_add_CFA_def_cfa_register (SP); | |
15375 | } | |
15376 | ||
707bfff6 TS |
15377 | int |
15378 | tc_mips_regname_to_dw2regnum (char *regname) | |
15379 | { | |
15380 | unsigned int regnum = -1; | |
15381 | unsigned int reg; | |
15382 | ||
15383 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15384 | regnum = reg; | |
15385 | ||
15386 | return regnum; | |
15387 | } |