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* config/tc-mips.c (md_pseudo_table): Ignore .livereg pseudo-op.
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
3d3c5039
ILT		 1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
8358c818
ILT		 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
3d3c5039
ILT		 7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23
24#include "as.h"
8358c818 25#include "config.h"
3d3c5039
ILT		 26
27#include <ctype.h>
28
29#ifndef __STDC__
30#ifndef NO_STDARG
31#define NO_STDARG
32#endif
33#endif
34
35#ifndef NO_STDARG
36#include <stdarg.h>
37#else
38#ifndef NO_VARARGS
39#include <varargs.h>
40#endif /* NO_VARARGS */
41#endif /* NO_STDARG */
42
918692a5 43#include "opcode/mips.h"
3d3c5039 44
f2a663d3
ILT		 45#ifdef OBJ_ELF
46#include "elf/mips.h"
47
48static char *mips_regmask_frag;
49#endif
50
3d3c5039 51#define AT 1
670a50eb 52#define GP 28
3d3c5039
ILT		 53#define RA 31
54
88225433
ILT		 55/* Decide whether to do GP reference optimizations based on the object
56 file format. */
57#undef GPOPT
58#ifdef OBJ_ECOFF
59#define GPOPT
60#endif
61#ifdef OBJ_ELF
62#define GPOPT
63#endif
64
1aa6938e
ILT		 65/* These variables are filled in with the masks of registers used.
66 The object format code reads them and puts them in the appropriate
67 place. */
68unsigned long mips_gprmask;
69unsigned long mips_cprmask[4];
70
8358c818
ILT		 71/* MIPS ISA (Instruction Set Architecture) level. */
72static int mips_isa = -1;
73
3d3c5039
ILT		 74static int mips_warn_about_macros;
75static int mips_noreorder;
76static int mips_nomove;
77static int mips_noat;
78static int mips_nobopt;
79
88225433 80#ifdef GPOPT
670a50eb
ILT		 81/* The size of the small data section. */
82static int g_switch_value = 8;
83#endif
84
3d3c5039
ILT		 85#define N_RMASK 0xc4
86#define N_VFP 0xd4
87
88/* handle of the OPCODE hash table */
89static struct hash_control *op_hash = NULL;
90
91/* This array holds the chars that always start a comment. If the
92 pre-processor is disabled, these aren't very useful */
93const char comment_chars[] = "#";
94
95/* This array holds the chars that only start a comment at the beginning of
96 a line. If the line seems to have the form '# 123 filename'
97 .line and .file directives will appear in the pre-processed output */
98/* Note that input_file.c hand checks for '#' at the beginning of the
99 first line of the input file. This is because the compiler outputs
100 #NO_APP at the beginning of its output. */
101/* Also note that C style comments are always supported. */
102const char line_comment_chars[] = "#";
103
104/* This array holds machine specific line separator characters. */
105const char line_separator_chars[] = "";
106
107/* Chars that can be used to separate mant from exp in floating point nums */
108const char EXP_CHARS[] = "eE";
109
110/* Chars that mean this number is a floating point constant */
111/* As in 0f12.456 */
112/* or 0d1.2345e12 */
113const char FLT_CHARS[] = "rRsSfFdDxXpP";
114
115/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
116 changed in read.c . Ideally it shouldn't have to know about it at all,
117 but nothing is ideal around here.
118 */
119
670a50eb 120static char *insn_error;
3d3c5039
ILT		 121
122static int byte_order = BYTE_ORDER;
123
124static int auto_align = 1;
becfe05e
ILT		 125
126/* Symbol labelling the current insn. */
127static symbolS *insn_label;
128
129/* To output NOP instructions correctly, we need to keep information
130 about the previous two instructions. */
131
0aa07269
ILT		 132/* Whether we are optimizing. The default value of 2 means to remove
133 unneeded NOPs and swap branch instructions when possible. A value
134 of 1 means to not swap branches. A value of 0 means to always
135 insert NOPs. */
136static int mips_optimize = 2;
4e95866e 137
becfe05e
ILT		 138/* The previous instruction. */
139static struct mips_cl_insn prev_insn;
140
141/* The instruction before prev_insn. */
142static struct mips_cl_insn prev_prev_insn;
143
144/* If we don't want information for prev_insn or prev_prev_insn, we
145 point the insn_mo field at this dummy integer. */
146static const struct mips_opcode dummy_opcode = { 0 };
147
148/* Non-zero if prev_insn is valid. */
149static int prev_insn_valid;
150
151/* The frag for the previous instruction. */
152static struct frag *prev_insn_frag;
153
154/* The offset into prev_insn_frag for the previous instruction. */
155static long prev_insn_where;
156
157/* The reloc for the previous instruction, if any. */
158static fixS *prev_insn_fixp;
159
160/* Non-zero if the previous instruction was in a delay slot. */
161static int prev_insn_is_delay_slot;
4e95866e
ILT		 162
163/* Non-zero if the previous instruction was in a .set noreorder. */
164static int prev_insn_unreordered;
165
166/* Non-zero if the previous previous instruction was in a .set
167 noreorder. */
168static int prev_prev_insn_unreordered;
3d3c5039
ILT		 169\f
170/* Prototypes for static functions. */
171
172#ifdef __STDC__
173#define internalError() \
174 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
175#else
176#define internalError() as_fatal ("MIPS internal Error");
177#endif
178
becfe05e 179static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
604633ae 180 unsigned int reg, int fpr));
670a50eb
ILT		 181static void append_insn PARAMS ((struct mips_cl_insn * ip,
182 expressionS * p,
3d3c5039 183 bfd_reloc_code_real_type r));
becfe05e
ILT		 184static void mips_no_prev_insn PARAMS ((void));
185static void mips_emit_delays PARAMS ((void));
670a50eb
ILT		 186static int gp_reference PARAMS ((expressionS * ep));
187static void macro_build PARAMS ((int *counter, expressionS * ep,
3d3c5039
ILT		 188 const char *name, const char *fmt,
189 ...));
670a50eb 190static void macro_build_lui PARAMS ((int *counter, expressionS * ep,
3d3c5039 191 int regnum));
6e8dda9c 192static void set_at PARAMS ((int *counter, int reg, int unsignedp));
670a50eb 193static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
19ed8960 194 expressionS *));
3d3c5039 195static void load_register PARAMS ((int *counter,
670a50eb
ILT		 196 int reg, expressionS * ep));
197static void macro PARAMS ((struct mips_cl_insn * ip));
198static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
199static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
200static void my_getExpression PARAMS ((expressionS * ep, char *str));
3d3c5039 201static symbolS *get_symbol PARAMS ((void));
becfe05e 202static void mips_align PARAMS ((int to, int fill));
3d3c5039 203static void s_align PARAMS ((int));
becfe05e 204static void s_stringer PARAMS ((int));
3d3c5039
ILT		 205static void s_change_sec PARAMS ((int));
206static void s_cons PARAMS ((int));
207static void s_err PARAMS ((int));
208static void s_extern PARAMS ((int));
209static void s_float_cons PARAMS ((int));
210static void s_option PARAMS ((int));
211static void s_mipsset PARAMS ((int));
becfe05e 212static void s_mips_space PARAMS ((int));
3d3c5039
ILT		 213#ifndef OBJ_ECOFF
214static void md_obj_begin PARAMS ((void));
215static void md_obj_end PARAMS ((void));
216static long get_number PARAMS ((void));
217static void s_ent PARAMS ((int));
218static void s_mipsend PARAMS ((int));
219static void s_file PARAMS ((int));
88225433 220#if 0
3d3c5039
ILT		 221static void s_frame PARAMS ((int));
222static void s_loc PARAMS ((int));
223static void s_mask PARAMS ((char));
224#endif
88225433 225#endif
3d3c5039
ILT		 226\f
227/* Pseudo-op table.
228
229 The following pseudo-ops from the Kane and Heinrich MIPS book
230 should be defined here, but are currently unsupported: .alias,
231 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
232
233 The following pseudo-ops from the Kane and Heinrich MIPS book are
234 specific to the type of debugging information being generated, and
235 should be defined by the object format: .aent, .begin, .bend,
236 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
237 .vreg.
238
239 The following pseudo-ops from the Kane and Heinrich MIPS book are
240 not MIPS CPU specific, but are also not specific to the object file
241 format. This file is probably the best place to define them, but
242 they are not currently supported: .asm0, .endr, .lab, .repeat,
243 .struct, .weakext. */
244
245const pseudo_typeS md_pseudo_table[] =
246{
670a50eb
ILT		 247 /* MIPS specific pseudo-ops. */
248 {"option", s_option, 0},
249 {"set", s_mipsset, 0},
dd3f1f76
ILT		 250 {"rdata", s_change_sec, 'r'},
251 {"sdata", s_change_sec, 's'},
252 {"livereg", s_ignore, 0},
3d3c5039 253
670a50eb 254 /* Relatively generic pseudo-ops that happen to be used on MIPS
3d3c5039 255 chips. */
becfe05e 256 {"asciiz", s_stringer, 1},
670a50eb
ILT		 257 {"bss", s_change_sec, 'b'},
258 {"err", s_err, 0},
259 {"half", s_cons, 1},
3d3c5039 260
670a50eb 261 /* These pseudo-ops are defined in read.c, but must be overridden
3d3c5039 262 here for one reason or another. */
670a50eb 263 {"align", s_align, 0},
becfe05e
ILT		 264 {"ascii", s_stringer, 0},
265 {"asciz", s_stringer, 1},
670a50eb
ILT		 266 {"byte", s_cons, 0},
267 {"data", s_change_sec, 'd'},
becfe05e 268 {"double", s_float_cons, 'd'},
670a50eb 269 {"extern", s_extern, 0},
becfe05e
ILT		 270 {"float", s_float_cons, 'f'},
271 {"space", s_mips_space, 0},
670a50eb
ILT		 272 {"text", s_change_sec, 't'},
273 {"word", s_cons, 2},
3d3c5039
ILT		 274
275#ifndef OBJ_ECOFF
670a50eb 276 /* These pseudo-ops should be defined by the object file format.
3d3c5039
ILT		 277 However, ECOFF is the only format which currently defines them,
278 so we have versions here for a.out. */
670a50eb
ILT		 279 {"aent", s_ent, 1},
280 {"end", s_mipsend, 0},
281 {"ent", s_ent, 0},
282 {"file", s_file, 0},
283 {"fmask", s_ignore, 'F'},
284 {"frame", s_ignore, 0},
285 {"loc", s_ignore, 0},
286 {"mask", s_ignore, 'R'},
287 {"verstamp", s_ignore, 0},
3d3c5039
ILT		 288#endif
289
670a50eb
ILT		 290 /* Sentinel. */
291 {NULL}
3d3c5039
ILT		 292};
293\f
670a50eb
ILT		 294const relax_typeS md_relax_table[] =
295{
918692a5 296 { 0 }
3d3c5039
ILT		 297};
298
299
300static char *expr_end;
301
302static expressionS imm_expr;
303static expressionS offset_expr;
304static bfd_reloc_code_real_type imm_reloc;
305static bfd_reloc_code_real_type offset_reloc;
306
abdad6bc
ILT		 307/* FIXME: This should be handled in a different way. */
308extern int target_big_endian;
309
3d3c5039
ILT		 310/*
311 * This function is called once, at assembler startup time. It should
312 * set up all the tables, etc. that the MD part of the assembler will need.
313 */
314void
670a50eb 315md_begin ()
3d3c5039 316{
97f99d11 317 boolean ok;
604633ae 318 register const char *retval = NULL;
670a50eb 319 register unsigned int i = 0;
3d3c5039 320
8358c818
ILT		 321 if (mips_isa == -1)
322 {
323 if (strcmp (TARGET_CPU, "mips") == 0)
324 mips_isa = 1;
325 else if (strcmp (TARGET_CPU, "r6000") == 0
326 || strcmp (TARGET_CPU, "mips2") == 0)
327 mips_isa = 2;
328 else if (strcmp (TARGET_CPU, "mips64") == 0
329 || strcmp (TARGET_CPU, "r4000") == 0
330 || strcmp (TARGET_CPU, "mips3") == 0)
331 mips_isa = 3;
332 else
333 mips_isa = 1;
334 }
335
97f99d11
ILT		 336 switch (mips_isa)
337 {
338 case 1:
339 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000);
340 break;
341 case 2:
342 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000);
343 break;
344 case 3:
345 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000);
346 break;
347 }
348 if (! ok)
349 as_warn ("Could not set architecture and machine");
350
670a50eb
ILT		 351 if ((op_hash = hash_new ()) == NULL)
352 {
353 as_fatal ("Virtual memory exhausted");
3d3c5039 354 }
670a50eb
ILT		 355 for (i = 0; i < NUMOPCODES;)
356 {
357 const char *name = mips_opcodes[i].name;
358
604633ae 359 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
abdad6bc 360 if (retval != NULL)
670a50eb
ILT		 361 {
362 fprintf (stderr, "internal error: can't hash `%s': %s\n",
363 mips_opcodes[i].name, retval);
364 as_fatal ("Broken assembler. No assembly attempted.");
365 }
366 do
367 {
8358c818
ILT		 368 if (mips_opcodes[i].pinfo != INSN_MACRO
369 && ((mips_opcodes[i].match & mips_opcodes[i].mask)
370 != mips_opcodes[i].match))
670a50eb
ILT		 371 {
372 fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n",
373 mips_opcodes[i].name, mips_opcodes[i].args);
374 as_fatal ("Broken assembler. No assembly attempted.");
3d3c5039 375 }
670a50eb
ILT		 376 ++i;
377 }
378 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3d3c5039
ILT		 379 }
380
becfe05e
ILT		 381 mips_no_prev_insn ();
382
1aa6938e
ILT		 383 mips_gprmask = 0;
384 mips_cprmask[0] = 0;
385 mips_cprmask[1] = 0;
386 mips_cprmask[2] = 0;
387 mips_cprmask[3] = 0;
388
8358c818
ILT		 389 /* set the default alignment for the text section (2**2) */
390 record_alignment (text_section, 2);
391
abdad6bc
ILT		 392 /* FIXME: This should be handled in a different way. */
393 target_big_endian = byte_order == BIG_ENDIAN;
394
88225433 395#ifdef GPOPT
8358c818
ILT		 396 bfd_set_gp_size (stdoutput, g_switch_value);
397#endif
398
f2a663d3
ILT		 399#ifdef OBJ_ELF
400 /* Create a .reginfo section for register masks. */
401 {
402 segT seg;
403 subsegT subseg;
404 segT regsec;
405
406 seg = now_seg;
407 subseg = now_subseg;
408 regsec = subseg_new (".reginfo", (subsegT) 0);
409
410 /* I don't know why this section should be loaded, but the ABI
411 says that SHF_ALLOC should be set. */
412 bfd_set_section_flags (stdoutput, regsec,
413 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
414
415 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
416
417 subseg_set (seg, subseg);
418 }
419#endif /* OBJ_ELF */
420
3d3c5039 421#ifndef OBJ_ECOFF
670a50eb 422 md_obj_begin ();
3d3c5039
ILT		 423#endif
424}
425
426void
427md_end ()
428{
429#ifndef OBJ_ECOFF
430 md_obj_end ();
431#endif
432}
433
434void
670a50eb
ILT		 435md_assemble (str)
436 char *str;
3d3c5039 437{
670a50eb 438 struct mips_cl_insn insn;
3d3c5039 439
5ac34ac3
ILT		 440 imm_expr.X_op = O_absent;
441 offset_expr.X_op = O_absent;
3d3c5039 442
670a50eb
ILT		 443 mips_ip (str, &insn);
444 if (insn_error)
445 {
446 as_bad ("%s `%s'", insn_error, str);
447 return;
448 }
449 if (insn.insn_mo->pinfo == INSN_MACRO)
450 {
451 macro (&insn);
3d3c5039 452 }
670a50eb
ILT		 453 else
454 {
5ac34ac3 455 if (imm_expr.X_op != O_absent)
670a50eb 456 append_insn (&insn, &imm_expr, imm_reloc);
5ac34ac3 457 else if (offset_expr.X_op != O_absent)
670a50eb
ILT		 458 append_insn (&insn, &offset_expr, offset_reloc);
459 else
460 append_insn (&insn, NULL, BFD_RELOC_UNUSED);
3d3c5039
ILT		 461 }
462}
463
becfe05e
ILT		 464/* See whether instruction IP reads register REG. If FPR is non-zero,
465 REG is a floating point register. */
466
467static int
468insn_uses_reg (ip, reg, fpr)
469 struct mips_cl_insn *ip;
604633ae 470 unsigned int reg;
becfe05e
ILT		 471 int fpr;
472{
473 /* Don't report on general register 0, since it never changes. */
474 if (! fpr && reg == 0)
475 return 0;
476
477 if (fpr)
478 {
479 /* If we are called with either $f0 or $f1, we must check $f0.
480 This is not optimal, because it will introduce an unnecessary
481 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
482 need to distinguish reading both $f0 and $f1 or just one of
483 them. Note that we don't have to check the other way,
484 because there is no instruction that sets both $f0 and $f1
485 and requires a delay. */
486 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
604633ae
ILT		 487 && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS)
488 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 489 return 1;
490 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
604633ae
ILT		 491 && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT)
492 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 493 return 1;
494 }
495 else
496 {
497 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
498 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
499 return 1;
500 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
501 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
502 return 1;
503 }
504
505 return 0;
506}
507
3d3c5039
ILT		 508#define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
509#define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
510
511/*
512 * append insn
513 * Output an instruction.
514 */
515static void
670a50eb
ILT		 516append_insn (ip, address_expr, reloc_type)
517 struct mips_cl_insn *ip;
518 expressionS *address_expr;
519 bfd_reloc_code_real_type reloc_type;
3d3c5039 520{
1aa6938e 521 register unsigned long prev_pinfo, pinfo;
670a50eb 522 char *f;
becfe05e
ILT		 523 fixS *fixp;
524 int nops = 0;
3d3c5039 525
1aa6938e
ILT		 526 prev_pinfo = prev_insn.insn_mo->pinfo;
527 pinfo = ip->insn_mo->pinfo;
528
becfe05e
ILT		 529 if (! mips_noreorder)
530 {
531 /* If the previous insn required any delay slots, see if we need
8358c818 532 to insert a NOP or two. There are eight kinds of possible
becfe05e 533 hazards, of which an instruction can have at most one type.
8358c818
ILT		 534 (1) a load from memory delay
535 (2) a load from a coprocessor delay
536 (3) an unconditional branch delay
537 (4) a conditional branch delay
538 (5) a move to coprocessor register delay
539 (6) a load coprocessor register from memory delay
540 (7) a coprocessor condition code delay
541 (8) a HI/LO special register delay
becfe05e
ILT		 542
543 There are a lot of optimizations we could do that we don't.
544 In particular, we do not, in general, reorder instructions.
545 If you use gcc with optimization, it will reorder
546 instructions and generally do much more optimization then we
547 do here; repeating all that work in the assembler would only
548 benefit hand written assembly code, and does not seem worth
549 it. */
550
551 /* This is how a NOP is emitted. */
552#define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
553
554 /* The previous insn might require a delay slot, depending upon
555 the contents of the current insn. */
1aa6938e 556 if ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
8358c818 557 || (mips_isa < 2
1aa6938e 558 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))
8358c818
ILT		 559 {
560 /* A load from a coprocessor or from memory. All load
561 delays delay the use of general register rt for one
562 instruction on the r3000. The r6000 and r4000 use
563 interlocks. */
1aa6938e 564 know (prev_pinfo & INSN_WRITE_GPR_T);
0aa07269
ILT		 565 if (mips_optimize == 0
566 || insn_uses_reg (ip,
567 ((prev_insn.insn_opcode >> OP_SH_RT)
568 & OP_MASK_RT),
569 0))
becfe05e
ILT		 570 ++nops;
571 }
1aa6938e 572 else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY)
8358c818 573 || (mips_isa < 2
1aa6938e 574 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))
becfe05e
ILT		 575 {
576 /* A generic coprocessor delay. The previous instruction
577 modified a coprocessor general or control register. If
578 it modified a control register, we need to avoid any
579 coprocessor instruction (this is probably not always
580 required, but it sometimes is). If it modified a general
581 register, we avoid using that register.
582
8358c818
ILT		 583 On the r6000 and r4000 loading a coprocessor register
584 from memory is interlocked, and does not require a delay.
585
becfe05e
ILT		 586 This case is not handled very well. There is no special
587 knowledge of CP0 handling, and the coprocessors other
588 than the floating point unit are not distinguished at
589 all. */
1aa6938e 590 if (prev_pinfo & INSN_WRITE_FPR_T)
becfe05e 591 {
0aa07269
ILT		 592 if (mips_optimize == 0
593 || insn_uses_reg (ip,
8358c818
ILT		 594 ((prev_insn.insn_opcode >> OP_SH_FT)
595 & OP_MASK_FT),
0aa07269 596 1))
becfe05e
ILT		 597 ++nops;
598 }
1aa6938e 599 else if (prev_pinfo & INSN_WRITE_FPR_S)
becfe05e 600 {
0aa07269
ILT		 601 if (mips_optimize == 0
602 || insn_uses_reg (ip,
8358c818
ILT		 603 ((prev_insn.insn_opcode >> OP_SH_FS)
604 & OP_MASK_FS),
0aa07269 605 1))
becfe05e
ILT		 606 ++nops;
607 }
608 else
609 {
610 /* We don't know exactly what the previous instruction
611 does. If the current instruction uses a coprocessor
612 register, we must insert a NOP. If previous
613 instruction may set the condition codes, and the
614 current instruction uses them, we must insert two
615 NOPS. */
0aa07269 616 if (mips_optimize == 0
1aa6938e
ILT		 617 || ((prev_pinfo & INSN_WRITE_COND_CODE)
618 && (pinfo & INSN_READ_COND_CODE)))
becfe05e 619 nops += 2;
1aa6938e 620 else if (pinfo & INSN_COP)
becfe05e
ILT		 621 ++nops;
622 }
623 }
1aa6938e 624 else if (prev_pinfo & INSN_WRITE_COND_CODE)
becfe05e
ILT		 625 {
626 /* The previous instruction sets the coprocessor condition
627 codes, but does not require a general coprocessor delay
628 (this means it is a floating point comparison
629 instruction). If this instruction uses the condition
630 codes, we need to insert a single NOP. */
0aa07269 631 if (mips_optimize == 0
1aa6938e 632 || (pinfo & INSN_READ_COND_CODE))
becfe05e
ILT		 633 ++nops;
634 }
1aa6938e 635 else if (prev_pinfo & INSN_READ_LO)
becfe05e
ILT		 636 {
637 /* The previous instruction reads the LO register; if the
638 current instruction writes to the LO register, we must
639 insert two NOPS. */
0aa07269 640 if (mips_optimize == 0
1aa6938e 641 || (pinfo & INSN_WRITE_LO))
becfe05e
ILT		 642 nops += 2;
643 }
644 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
645 {
646 /* The previous instruction reads the HI register; if the
647 current instruction writes to the HI register, we must
648 insert a NOP. */
0aa07269 649 if (mips_optimize == 0
1aa6938e 650 || (pinfo & INSN_WRITE_HI))
becfe05e
ILT		 651 nops += 2;
652 }
653
654 /* There are two cases which require two intervening
655 instructions: 1) setting the condition codes using a move to
656 coprocessor instruction which requires a general coprocessor
657 delay and then reading the condition codes 2) reading the HI
658 or LO register and then writing to it. If we are not already
659 emitting a NOP instruction, we must check for these cases
660 compared to the instruction previous to the previous
661 instruction. */
662 if (nops == 0
8358c818 663 && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
becfe05e 664 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1aa6938e 665 && (pinfo & INSN_READ_COND_CODE))
becfe05e 666 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1aa6938e 667 && (pinfo & INSN_WRITE_LO))
becfe05e 668 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1aa6938e 669 && (pinfo & INSN_WRITE_HI))))
becfe05e
ILT		 670 ++nops;
671
672 /* Now emit the right number of NOP instructions. */
673 if (nops > 0)
674 {
675 emit_nop ();
676 if (nops > 1)
677 emit_nop ();
678 if (insn_label != NULL)
679 {
680 assert (S_GET_SEGMENT (insn_label) == now_seg);
681 insn_label->sy_frag = frag_now;
604633ae 682 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e
ILT		 683 }
684 }
685 }
686
670a50eb 687 f = frag_more (4);
becfe05e
ILT		 688#if 0
689 /* This is testing the address of the frag, not the alignment of
690 the instruction in the current section. */
670a50eb
ILT		 691 if ((int) f & 3)
692 {
693 as_bad (ALIGN_ERR);
694 as_bad (ALIGN_ERR2);
3d3c5039
ILT		 695 }
696#endif
becfe05e 697 fixp = NULL;
670a50eb
ILT		 698 if (address_expr != NULL)
699 {
5ac34ac3 700 if (address_expr->X_op == O_constant)
670a50eb
ILT		 701 {
702 switch (reloc_type)
703 {
3d3c5039 704 case BFD_RELOC_32:
670a50eb
ILT		 705 ip->insn_opcode |= address_expr->X_add_number;
706 break;
3d3c5039
ILT		 707
708 case BFD_RELOC_LO16:
670a50eb
ILT		 709 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
710 break;
3d3c5039
ILT		 711
712 case BFD_RELOC_MIPS_JMP:
713 case BFD_RELOC_16_PCREL_S2:
670a50eb 714 goto need_reloc;
3d3c5039
ILT		 715
716 default:
670a50eb 717 internalError ();
3d3c5039 718 }
670a50eb
ILT		 719 }
720 else
721 {
722 assert (reloc_type != BFD_RELOC_UNUSED);
3d3c5039 723 need_reloc:
5ac34ac3
ILT		 724 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
725 address_expr,
726 reloc_type == BFD_RELOC_16_PCREL_S2,
727 reloc_type);
3d3c5039
ILT		 728 }
729 }
becfe05e 730
670a50eb
ILT		 731 md_number_to_chars (f, ip->insn_opcode, 4);
732
1aa6938e
ILT		 733 /* Update the register mask information. */
734 if (pinfo & INSN_WRITE_GPR_D)
735 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
736 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
737 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
738 if (pinfo & INSN_READ_GPR_S)
739 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
740 if (pinfo & INSN_WRITE_GPR_31)
741 mips_gprmask |= 1 << 31;
742 if (pinfo & INSN_WRITE_FPR_D)
743 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
744 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
745 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
746 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
747 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
748 if (pinfo & INSN_COP)
749 {
750 /* We don't keep enough information to sort these cases out. */
751 }
752 /* Never set the bit for $0, which is always zero. */
753 mips_gprmask &=~ 1 << 0;
754
becfe05e 755 if (! mips_noreorder)
670a50eb 756 {
becfe05e
ILT		 757 /* Filling the branch delay slot is more complex. We try to
758 switch the branch with the previous instruction, which we can
759 do if the previous instruction does not set up a condition
760 that the branch tests and if the branch is not itself the
761 target of any branch. */
1aa6938e
ILT		 762 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
763 || (pinfo & INSN_COND_BRANCH_DELAY))
becfe05e 764 {
0aa07269 765 if (mips_optimize < 2
19ed8960
ILT		 766 /* If we have seen .set nobopt, don't optimize. */
767 || mips_nobopt != 0
768 /* If we have seen .set volatile or .set nomove, don't
769 optimize. */
770 || mips_nomove != 0
4e95866e
ILT		 771 /* If we had to emit any NOP instructions, then we
772 already know we can not swap. */
773 || nops != 0
becfe05e
ILT		 774 /* If we don't even know the previous insn, we can not
775 swap. */
776 || ! prev_insn_valid
777 /* If the previous insn is already in a branch delay
778 slot, then we can not swap. */
779 || prev_insn_is_delay_slot
4e95866e
ILT		 780 /* If the previous previous insn was in a .set
781 noreorder, we can't swap. Actually, the MIPS
782 assembler will swap in this situation. However, gcc
783 configured -with-gnu-as will generate code like
784 .set noreorder
785 lw $4,XXX
786 .set reorder
787 INSN
788 bne $4,$0,foo
789 in which we can not swap the bne and INSN. If gcc is
790 not configured -with-gnu-as, it does not output the
791 .set pseudo-ops. We don't have to check
792 prev_insn_unreordered, because prev_insn_valid will
793 be 0 in that case. We don't want to use
794 prev_prev_insn_valid, because we do want to be able
795 to swap at the start of a function. */
796 || prev_prev_insn_unreordered
becfe05e
ILT		 797 /* If the branch is itself the target of a branch, we
798 can not swap. We cheat on this; all we check for is
799 whether there is a label on this instruction. If
800 there are any branches to anything other than a
801 label, users must use .set noreorder. */
802 || insn_label != NULL
803 /* If the branch reads the condition codes, we don't
804 even try to swap, because in the sequence
805 ctc1 $X,$31
806 INSN
807 INSN
808 bc1t LABEL
809 we can not swap, and I don't feel like handling that
810 case. */
1aa6938e 811 || (pinfo & INSN_READ_COND_CODE)
becfe05e
ILT		 812 /* We can not swap with an instruction that requires a
813 delay slot, becase the target of the branch might
814 interfere with that instruction. */
1aa6938e 815 || (prev_pinfo
8358c818
ILT		 816 & (INSN_LOAD_COPROC_DELAY
817 | INSN_COPROC_MOVE_DELAY
becfe05e
ILT		 818 | INSN_WRITE_COND_CODE
819 | INSN_READ_LO
820 | INSN_READ_HI))
8358c818 821 || (mips_isa < 2
1aa6938e 822 && (prev_pinfo
8358c818
ILT		 823 & (INSN_LOAD_MEMORY_DELAY
824 | INSN_COPROC_MEMORY_DELAY)))
becfe05e 825 /* We can not swap with a branch instruction. */
1aa6938e 826 || (prev_pinfo
6e8dda9c
ILT		 827 & (INSN_UNCOND_BRANCH_DELAY
828 | INSN_COND_BRANCH_DELAY
829 | INSN_COND_BRANCH_LIKELY))
abdad6bc
ILT		 830 /* We do not swap with a trap instruction, since it
831 complicates trap handlers to have the trap
832 instruction be in a delay slot. */
1aa6938e 833 || (prev_pinfo & INSN_TRAP)
becfe05e
ILT		 834 /* If the branch reads a register that the previous
835 instruction sets, we can not swap. */
1aa6938e 836 || ((prev_pinfo & INSN_WRITE_GPR_T)
becfe05e
ILT		 837 && insn_uses_reg (ip,
838 ((prev_insn.insn_opcode >> OP_SH_RT)
839 & OP_MASK_RT),
840 0))
1aa6938e 841 || ((prev_pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 842 && insn_uses_reg (ip,
843 ((prev_insn.insn_opcode >> OP_SH_RD)
844 & OP_MASK_RD),
845 0))
1849d646
ILT		 846 /* If the branch writes a register that the previous
847 instruction sets, we can not swap (we know that
848 branches write only to RD or to $31). */
1aa6938e
ILT		 849 || ((prev_pinfo & INSN_WRITE_GPR_T)
850 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 851 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
852 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 853 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 854 && (((prev_insn.insn_opcode >> OP_SH_RT)
855 & OP_MASK_RT)
856 == 31))))
1aa6938e
ILT		 857 || ((prev_pinfo & INSN_WRITE_GPR_D)
858 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 859 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
860 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 861 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 862 && (((prev_insn.insn_opcode >> OP_SH_RD)
863 & OP_MASK_RD)
864 == 31))))
becfe05e
ILT		 865 /* If the branch writes a register that the previous
866 instruction reads, we can not swap (we know that
867 branches only write to RD or to $31). */
1aa6938e 868 || ((pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 869 && insn_uses_reg (&prev_insn,
870 ((ip->insn_opcode >> OP_SH_RD)
871 & OP_MASK_RD),
872 0))
1aa6938e 873 || ((pinfo & INSN_WRITE_GPR_31)
becfe05e
ILT		 874 && insn_uses_reg (&prev_insn, 31, 0))
875 /* If the previous previous instruction has a load
876 delay, and sets a register that the branch reads, we
877 can not swap. */
8358c818
ILT		 878 || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
879 || (mips_isa < 2
880 && (prev_prev_insn.insn_mo->pinfo
881 & INSN_LOAD_MEMORY_DELAY)))
becfe05e
ILT		 882 && insn_uses_reg (ip,
883 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
884 & OP_MASK_RT),
885 0)))
886 {
887 /* We could do even better for unconditional branches to
888 portions of this object file; we could pick up the
889 instruction at the destination, put it in the delay
890 slot, and bump the destination address. */
891 emit_nop ();
892 /* Update the previous insn information. */
893 prev_prev_insn = *ip;
894 prev_insn.insn_mo = &dummy_opcode;
895 }
896 else
897 {
898 char *prev_f;
899 char temp[4];
900
901 /* It looks like we can actually do the swap. */
902 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
903 memcpy (temp, prev_f, 4);
904 memcpy (prev_f, f, 4);
905 memcpy (f, temp, 4);
906 if (prev_insn_fixp)
907 {
908 prev_insn_fixp->fx_frag = frag_now;
909 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
910 }
911 if (fixp)
912 {
913 fixp->fx_frag = prev_insn_frag;
914 fixp->fx_where = prev_insn_where;
915 }
916 /* Update the previous insn information; leave prev_insn
917 unchanged. */
918 prev_prev_insn = *ip;
919 }
920 prev_insn_is_delay_slot = 1;
921
922 /* If that was an unconditional branch, forget the previous
923 insn information. */
1aa6938e 924 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
becfe05e
ILT		 925 {
926 prev_prev_insn.insn_mo = &dummy_opcode;
927 prev_insn.insn_mo = &dummy_opcode;
928 }
929 }
1aa6938e 930 else if (pinfo & INSN_COND_BRANCH_LIKELY)
8358c818
ILT		 931 {
932 /* We don't yet optimize a branch likely. What we should do
933 is look at the target, copy the instruction found there
934 into the delay slot, and increment the branch to jump to
935 the next instruction. */
936 emit_nop ();
937 /* Update the previous insn information. */
938 prev_prev_insn = *ip;
939 prev_insn.insn_mo = &dummy_opcode;
940 }
becfe05e 941 else
670a50eb 942 {
becfe05e
ILT		 943 /* Update the previous insn information. */
944 if (nops > 0)
945 prev_prev_insn.insn_mo = &dummy_opcode;
946 else
947 prev_prev_insn = prev_insn;
948 prev_insn = *ip;
949
950 /* Any time we see a branch, we always fill the delay slot
951 immediately; since this insn is not a branch, we know it
952 is not in a delay slot. */
953 prev_insn_is_delay_slot = 0;
954 }
955
4e95866e
ILT		 956 prev_prev_insn_unreordered = prev_insn_unreordered;
957 prev_insn_unreordered = 0;
becfe05e
ILT		 958 prev_insn_frag = frag_now;
959 prev_insn_where = f - frag_now->fr_literal;
960 prev_insn_fixp = fixp;
961 prev_insn_valid = 1;
962 }
3d3c5039 963
becfe05e
ILT		 964 /* We just output an insn, so the next one doesn't have a label. */
965 insn_label = NULL;
966}
967
968/* This function forgets that there was any previous instruction or
969 label. */
970
971static void
972mips_no_prev_insn ()
973{
974 prev_insn.insn_mo = &dummy_opcode;
975 prev_prev_insn.insn_mo = &dummy_opcode;
976 prev_insn_valid = 0;
977 prev_insn_is_delay_slot = 0;
4e95866e
ILT		 978 prev_insn_unreordered = 0;
979 prev_prev_insn_unreordered = 0;
becfe05e
ILT		 980 insn_label = NULL;
981}
982
983/* This function must be called whenever we turn on noreorder or emit
984 something other than instructions. It inserts any NOPS which might
985 be needed by the previous instruction, and clears the information
986 kept for the previous instructions. */
987
988static void
989mips_emit_delays ()
990{
991 if (! mips_noreorder)
992 {
993 int nop;
994
995 nop = 0;
8358c818
ILT		 996 if ((prev_insn.insn_mo->pinfo
997 & (INSN_LOAD_COPROC_DELAY
998 | INSN_COPROC_MOVE_DELAY
999 | INSN_WRITE_COND_CODE
1000 | INSN_READ_LO
1001 | INSN_READ_HI))
1002 || (mips_isa < 2
1003 && (prev_insn.insn_mo->pinfo
1004 & (INSN_LOAD_MEMORY_DELAY
1005 | INSN_COPROC_MEMORY_DELAY))))
becfe05e
ILT		 1006 {
1007 nop = 1;
1008 if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1009 || (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1010 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))
1011 emit_nop ();
1012 }
1013 else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1014 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1015 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))
1016 nop = 1;
1017 if (nop)
670a50eb 1018 {
becfe05e
ILT		 1019 emit_nop ();
1020 if (insn_label != NULL)
1021 {
1022 assert (S_GET_SEGMENT (insn_label) == now_seg);
1023 insn_label->sy_frag = frag_now;
604633ae 1024 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e 1025 }
3d3c5039 1026 }
becfe05e 1027 mips_no_prev_insn ();
3d3c5039
ILT		 1028 }
1029}
1030
670a50eb
ILT		 1031/* Return 1 if an expression can be accessed via the GP register. */
1032
1033static int
1034gp_reference (ep)
1035 expressionS *ep;
1036{
88225433 1037#ifdef GPOPT
670a50eb 1038 symbolS *sym;
9a7d824a 1039 const char *symname;
670a50eb
ILT		 1040 const char *segname;
1041
1042 sym = ep->X_add_symbol;
1043 if (sym == (symbolS *) NULL
5ac34ac3 1044 || ep->X_op_symbol != (symbolS *) NULL)
670a50eb 1045 return 0;
9a7d824a
ILT		 1046
1047 /* Certain symbols can not be referenced off the GP, although it
1048 appears as though they can. */
1049 symname = S_GET_NAME (sym);
1050 if (symname != (const char *) NULL
1051 && (strcmp (symname, "eprol") == 0
1052 || strcmp (symname, "etext") == 0
1053 || strcmp (symname, "_gp") == 0
1054 || strcmp (symname, "edata") == 0
1055 || strcmp (symname, "_fbss") == 0
1056 || strcmp (symname, "_fdata") == 0
1057 || strcmp (symname, "_ftext") == 0
1058 || strcmp (symname, "end") == 0))
1059 return 0;
670a50eb
ILT		 1060 if (! S_IS_DEFINED (sym)
1061 && S_GET_VALUE (sym) != 0
1062 && S_GET_VALUE (sym) <= g_switch_value)
1063 return 1;
1064 segname = segment_name (S_GET_SEGMENT (ep->X_add_symbol));
1065 return (strcmp (segname, ".sdata") == 0
19ed8960
ILT		 1066 || strcmp (segname, ".sbss") == 0
1067 || strcmp (segname, ".lit8") == 0
1068 || strcmp (segname, ".lit4") == 0);
88225433
ILT		 1069#else /* ! defined (GPOPT) */
1070 /* We are not optimizing for the GP register. */
670a50eb 1071 return 0;
88225433 1072#endif /* ! defined (GPOPT) */
670a50eb
ILT		 1073}
1074
1075/* Build an instruction created by a macro expansion. This is passed
1076 a pointer to the count of instructions created so far, an
1077 expression, the name of the instruction to build, an operand format
1078 string, and corresponding arguments. */
1079
3d3c5039
ILT		 1080#ifndef NO_STDARG
1081static void
1082macro_build (int *counter,
670a50eb 1083 expressionS * ep,
3d3c5039
ILT		 1084 const char *name,
1085 const char *fmt,
1086 ...)
1087#else /* ! defined (NO_STDARG) */
1088static void
1089macro_build (counter, ep, name, fmt, va_alist)
1090 int *counter;
1091 expressionS *ep;
1092 const char *name;
1093 const char *fmt;
1094 va_dcl
1095#endif /* ! defined (NO_STDARG) */
1096{
670a50eb
ILT		 1097 struct mips_cl_insn insn;
1098 bfd_reloc_code_real_type r;
1099 va_list args;
3d3c5039
ILT		 1100
1101#ifndef NO_STDARG
670a50eb 1102 va_start (args, fmt);
3d3c5039 1103#else
670a50eb 1104 va_start (args);
3d3c5039
ILT		 1105#endif
1106
670a50eb
ILT		 1107 /*
1108 * If the macro is about to expand into a second instruction,
1109 * print a warning if needed. We need to pass ip as a parameter
1110 * to generate a better warning message here...
1111 */
1112 if (mips_warn_about_macros && *counter == 1)
1113 as_warn ("Macro instruction expanded into multiple instructions");
1114
1115 *counter += 1; /* bump instruction counter */
1116
1117 r = BFD_RELOC_UNUSED;
1118 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1119 assert (insn.insn_mo);
1120 assert (strcmp (name, insn.insn_mo->name) == 0);
1121
1122 while (strcmp (fmt, insn.insn_mo->args) != 0)
1123 {
1124 ++insn.insn_mo;
1125 assert (insn.insn_mo->name);
1126 assert (strcmp (name, insn.insn_mo->name) == 0);
3d3c5039 1127 }
670a50eb
ILT		 1128 assert (insn.insn_mo->pinfo != INSN_MACRO);
1129 insn.insn_opcode = insn.insn_mo->match;
1130 for (;;)
1131 {
1132 switch (*fmt++)
1133 {
3d3c5039 1134 case '\0':
670a50eb 1135 break;
3d3c5039
ILT		 1136
1137 case ',':
1138 case '(':
1139 case ')':
670a50eb 1140 continue;
3d3c5039
ILT		 1141
1142 case 't':
1143 case 'w':
918692a5 1144 case 'E':
670a50eb
ILT		 1145 insn.insn_opcode |= va_arg (args, int) << 16;
1146 continue;
3d3c5039
ILT		 1147
1148 case 'c':
1149 case 'T':
1150 case 'W':
670a50eb
ILT		 1151 insn.insn_opcode |= va_arg (args, int) << 16;
1152 continue;
3d3c5039
ILT		 1153
1154 case 'd':
918692a5 1155 case 'G':
670a50eb
ILT		 1156 insn.insn_opcode |= va_arg (args, int) << 11;
1157 continue;
3d3c5039
ILT		 1158
1159 case 'V':
1160 case 'S':
670a50eb
ILT		 1161 insn.insn_opcode |= va_arg (args, int) << 11;
1162 continue;
3d3c5039 1163
ff3a5c18
ILT		 1164 case 'z':
1165 continue;
1166
3d3c5039 1167 case '<':
670a50eb
ILT		 1168 insn.insn_opcode |= va_arg (args, int) << 6;
1169 continue;
3d3c5039
ILT		 1170
1171 case 'D':
670a50eb
ILT		 1172 insn.insn_opcode |= va_arg (args, int) << 6;
1173 continue;
3d3c5039 1174
918692a5
ILT		 1175 case 'B':
1176 insn.insn_opcode |= va_arg (args, int) << 6;
1177 continue;
1178
3d3c5039
ILT		 1179 case 'b':
1180 case 's':
1181 case 'r':
1182 case 'v':
670a50eb
ILT		 1183 insn.insn_opcode |= va_arg (args, int) << 21;
1184 continue;
3d3c5039
ILT		 1185
1186 case 'i':
1187 case 'j':
1188 case 'o':
670a50eb
ILT		 1189 r = BFD_RELOC_LO16;
1190 continue;
3d3c5039 1191
6e8dda9c
ILT		 1192 case 'u':
1193 assert (ep != NULL && ep->X_op == O_constant);
1194 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
1195 ep = NULL;
1196 continue;
1197
3d3c5039 1198 case 'p':
670a50eb
ILT		 1199 assert (ep != NULL);
1200 /*
1201 * This allows macro() to pass an immediate expression for
1202 * creating short branches without creating a symbol.
1203 * Note that the expression still might come from the assembly
1204 * input, in which case the value is not checked for range nor
1205 * is a relocation entry generated (yuck).
1206 */
5ac34ac3 1207 if (ep->X_op == O_constant)
670a50eb
ILT		 1208 {
1209 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
1210 ep = NULL;
1211 }
1212 else
1213 r = BFD_RELOC_16_PCREL_S2;
1214 continue;
3d3c5039
ILT		 1215
1216 default:
670a50eb 1217 internalError ();
3d3c5039 1218 }
670a50eb 1219 break;
3d3c5039 1220 }
670a50eb
ILT		 1221 va_end (args);
1222 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1223
1224 /* Use GP relative addressing if possible. */
1225 if (r == BFD_RELOC_LO16
1226 && gp_reference (ep))
1227 r = BFD_RELOC_MIPS_GPREL;
1228
1229 append_insn (&insn, ep, r);
3d3c5039
ILT		 1230}
1231
1232/*
1233 * Generate a "lui" instruction.
1234 */
1235static void
1236macro_build_lui (counter, ep, regnum)
1237 int *counter;
1238 expressionS *ep;
1239 int regnum;
1240{
670a50eb
ILT		 1241 expressionS high_expr;
1242 struct mips_cl_insn insn;
1243 bfd_reloc_code_real_type r;
1244 CONST char *name = "lui";
1245 CONST char *fmt = "t,u";
1246
1247 high_expr = *ep;
1248
5ac34ac3 1249 if (high_expr.X_op == O_constant)
670a50eb
ILT		 1250 {
1251 /* we can compute the instruction now without a relocation entry */
1252 if (high_expr.X_add_number & 0x8000)
1253 high_expr.X_add_number += 0x10000;
1254 high_expr.X_add_number =
1255 ((unsigned long) high_expr.X_add_number >> 16) & 0xffff;
1256 r = BFD_RELOC_UNUSED;
1257 }
1258 else
1259 r = BFD_RELOC_HI16_S;
1260
1261 /*
1262 * If the macro is about to expand into a second instruction,
1263 * print a warning if needed. We need to pass ip as a parameter
1264 * to generate a better warning message here...
1265 */
1266 if (mips_warn_about_macros && *counter == 1)
1267 as_warn ("Macro instruction expanded into multiple instructions");
1268
1269 *counter += 1; /* bump instruction counter */
1270
1271 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1272 assert (insn.insn_mo);
1273 assert (strcmp (name, insn.insn_mo->name) == 0);
1274 assert (strcmp (fmt, insn.insn_mo->args) == 0);
1275
1276 insn.insn_opcode = insn.insn_mo->match | (regnum << 16);
1277 if (r == BFD_RELOC_UNUSED)
1278 {
1279 insn.insn_opcode |= high_expr.X_add_number;
1280 append_insn (&insn, NULL, r);
1281 }
1282 else
1283 append_insn (&insn, &high_expr, r);
3d3c5039
ILT		 1284}
1285
1286/* set_at()
1287 * Generates code to set the $at register to true (one)
1288 * if reg is less than the immediate expression.
1289 */
1290static void
6e8dda9c 1291set_at (counter, reg, unsignedp)
3d3c5039
ILT		 1292 int *counter;
1293 int reg;
6e8dda9c 1294 int unsignedp;
3d3c5039 1295{
6e8dda9c
ILT		 1296 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1297 macro_build (counter, &imm_expr,
1298 unsignedp ? "sltiu" : "slti",
1299 "t,r,j", AT, reg);
1300 else
670a50eb 1301 {
6e8dda9c
ILT		 1302 load_register (counter, AT, &imm_expr);
1303 macro_build (counter, NULL,
1304 unsignedp ? "sltu" : "slt",
1305 "d,v,t", AT, reg, AT);
670a50eb 1306 }
3d3c5039
ILT		 1307}
1308
6e8dda9c 1309/* Warn if an expression is not a constant. */
3d3c5039
ILT		 1310
1311static void
19ed8960 1312check_absolute_expr (ip, ex)
3d3c5039 1313 struct mips_cl_insn *ip;
19ed8960 1314 expressionS *ex;
3d3c5039 1315{
19ed8960 1316 if (ex->X_op != O_constant)
670a50eb 1317 as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name);
3d3c5039
ILT		 1318}
1319
1320/* load_register()
1321 * This routine generates the least number of instructions neccessary to load
1322 * an absolute expression value into a register.
1323 */
1324static void
6e8dda9c 1325load_register (counter, reg, ep)
670a50eb 1326 int *counter;
670a50eb
ILT		 1327 int reg;
1328 expressionS *ep;
3d3c5039 1329{
6e8dda9c
ILT		 1330 assert (ep->X_op == O_constant);
1331 if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000)
1332 macro_build (counter, ep,
1333 mips_isa < 3 ? "addiu" : "daddiu",
1334 "t,r,j", reg, 0);
1335 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
1336 macro_build (counter, ep, "ori", "t,r,i", reg, 0);
1337 else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
1338 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
1339 == ~ (offsetT) 0x7fffffff))
1340 {
1341 macro_build (counter, ep, "lui", "t,u", reg);
1342 if ((ep->X_add_number & 0xffff) != 0)
1343 macro_build (counter, ep, "ori", "t,r,i", reg, reg);
1344 }
1345 else if (mips_isa < 3)
670a50eb 1346 {
6e8dda9c 1347 as_bad ("Number larger than 32 bits");
670a50eb 1348 macro_build (counter, ep, "addiu", "t,r,j", reg, 0);
6e8dda9c
ILT		 1349 }
1350 else
1351 {
1352 int shift;
1353 expressionS hi32, lo32;
1354
1355 hi32 = *ep;
1356 shift = 32;
1357 hi32.X_add_number >>= shift;
1358 hi32.X_add_number &= 0xffffffff;
1359 if ((hi32.X_add_number & 0x80000000) != 0)
1360 hi32.X_add_number |= ~ (offsetT) 0xffffffff;
1361 load_register (counter, reg, &hi32);
1362 lo32 = *ep;
1363 lo32.X_add_number &= 0xffffffff;
1364 if ((lo32.X_add_number & 0xffff0000) == 0)
1365 macro_build (counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
1366 else
1367 {
1368 expressionS mid16;
670a50eb 1369
6e8dda9c
ILT		 1370 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1371 mid16 = lo32;
1372 mid16.X_add_number >>= 16;
1373 macro_build (counter, &mid16, "ori", "t,r,i", reg, reg);
1374 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1375 }
1376 if ((lo32.X_add_number & 0xffff) != 0)
1377 macro_build (counter, &lo32, "ori", "t,r,i", reg, reg);
670a50eb 1378 }
3d3c5039
ILT		 1379}
1380
3d3c5039
ILT		 1381/*
1382 * Build macros
1383 * This routine implements the seemingly endless macro or synthesized
1384 * instructions and addressing modes in the mips assembly language. Many
1385 * of these macros are simple and are similar to each other. These could
1386 * probably be handled by some kind of table or grammer aproach instead of
1387 * this verbose method. Others are not simple macros but are more like
1388 * optimizing code generation.
1389 * One interesting optimization is when several store macros appear
1390 * consecutivly that would load AT with the upper half of the same address.
1391 * The ensuing load upper instructions are ommited. This implies some kind
1392 * of global optimization. We currently only optimize within a single macro.
1393 * For many of the load and store macros if the address is specified as a
1394 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1395 * first load register 'at' with zero and use it as the base register. The
1396 * mips assembler simply uses register $zero. Just one tiny optimization
1397 * we're missing.
1398 */
1399static void
1400macro (ip)
1401 struct mips_cl_insn *ip;
1402{
670a50eb
ILT		 1403 register int treg, sreg, dreg, breg;
1404 int tempreg;
1405 int mask;
1406 int icnt = 0;
1407 int used_at;
670a50eb
ILT		 1408 expressionS expr1;
1409 const char *s;
8358c818 1410 const char *s2;
670a50eb 1411 const char *fmt;
8358c818
ILT		 1412 int likely = 0;
1413 int dbl = 0;
1414 int coproc = 0;
6e8dda9c 1415 offsetT maxnum;
670a50eb
ILT		 1416
1417 treg = (ip->insn_opcode >> 16) & 0x1f;
1418 dreg = (ip->insn_opcode >> 11) & 0x1f;
1419 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
1420 mask = ip->insn_mo->mask;
1421
5ac34ac3
ILT		 1422 expr1.X_op = O_constant;
1423 expr1.X_op_symbol = NULL;
670a50eb
ILT		 1424 expr1.X_add_symbol = NULL;
1425 expr1.X_add_number = 1;
1426
1427 switch (mask)
1428 {
6e8dda9c
ILT		 1429 case M_DABS:
1430 dbl = 1;
3d3c5039 1431 case M_ABS:
6e8dda9c
ILT		 1432 /* bgez $a0,.+12
1433 move v0,$a0
1434 sub v0,$zero,$a0
1435 */
3d3c5039 1436
becfe05e
ILT		 1437 mips_emit_delays ();
1438 ++mips_noreorder;
3d3c5039 1439
670a50eb
ILT		 1440 expr1.X_add_number = 8;
1441 macro_build (&icnt, &expr1, "bgez", "s,p", sreg);
6e8dda9c
ILT		 1442 if (dreg == sreg)
1443 macro_build (&icnt, NULL, "nop", "", 0);
1444 else
1445 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg, 0);
1446 macro_build (&icnt, NULL,
1447 dbl ? "dsub" : "sub",
1448 "d,v,t", dreg, 0, sreg);
3d3c5039 1449
becfe05e 1450 --mips_noreorder;
670a50eb 1451 return;
3d3c5039
ILT		 1452
1453 case M_ADD_I:
8358c818
ILT		 1454 s = "addi";
1455 s2 = "add";
1456 goto do_addi;
3d3c5039 1457 case M_ADDU_I:
8358c818
ILT		 1458 s = "addiu";
1459 s2 = "addu";
1460 goto do_addi;
1461 case M_DADD_I:
6e8dda9c 1462 dbl = 1;
8358c818
ILT		 1463 s = "daddi";
1464 s2 = "dadd";
1465 goto do_addi;
1466 case M_DADDU_I:
6e8dda9c 1467 dbl = 1;
8358c818
ILT		 1468 s = "daddiu";
1469 s2 = "daddu";
1470 do_addi:
6e8dda9c 1471 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 1472 {
8358c818 1473 macro_build (&icnt, &imm_expr, s, "t,r,j", treg, sreg);
670a50eb 1474 return;
3d3c5039 1475 }
6e8dda9c 1476 load_register (&icnt, AT, &imm_expr);
8358c818 1477 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 1478 break;
3d3c5039
ILT		 1479
1480 case M_AND_I:
6e8dda9c
ILT		 1481 s = "andi";
1482 s2 = "and";
1483 goto do_bit;
3d3c5039 1484 case M_OR_I:
6e8dda9c
ILT		 1485 s = "ori";
1486 s2 = "or";
1487 goto do_bit;
3d3c5039 1488 case M_NOR_I:
6e8dda9c
ILT		 1489 s = "";
1490 s2 = "nor";
1491 goto do_bit;
3d3c5039 1492 case M_XOR_I:
6e8dda9c
ILT		 1493 s = "xori";
1494 s2 = "xor";
1495 do_bit:
1496 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 1497 {
6e8dda9c
ILT		 1498 if (mask != M_NOR_I)
1499 macro_build (&icnt, &imm_expr, s, "t,r,i", treg, sreg);
1500 else
670a50eb 1501 {
670a50eb
ILT		 1502 macro_build (&icnt, &imm_expr, "ori", "t,r,i", treg, sreg);
1503 macro_build (&icnt, &imm_expr, "nor", "d,v,t", treg, treg, 0);
3d3c5039 1504 }
6e8dda9c 1505 return;
3d3c5039 1506 }
6e8dda9c
ILT		 1507
1508 load_register (&icnt, AT, &imm_expr);
1509 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 1510 break;
3d3c5039
ILT		 1511
1512 case M_BEQ_I:
8358c818
ILT		 1513 s = "beq";
1514 goto beq_i;
1515 case M_BEQL_I:
1516 s = "beql";
1517 likely = 1;
1518 goto beq_i;
3d3c5039 1519 case M_BNE_I:
8358c818
ILT		 1520 s = "bne";
1521 goto beq_i;
1522 case M_BNEL_I:
1523 s = "bnel";
1524 likely = 1;
1525 beq_i:
670a50eb
ILT		 1526 if (imm_expr.X_add_number == 0)
1527 {
8358c818 1528 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, 0);
670a50eb
ILT		 1529 return;
1530 }
6e8dda9c 1531 load_register (&icnt, AT, &imm_expr);
8358c818 1532 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, AT);
670a50eb 1533 break;
3d3c5039 1534
8358c818
ILT		 1535 case M_BGEL:
1536 likely = 1;
3d3c5039 1537 case M_BGE:
670a50eb
ILT		 1538 if (treg == 0)
1539 {
8358c818
ILT		 1540 macro_build (&icnt, &offset_expr,
1541 likely ? "bgezl" : "bgez",
1542 "s,p", sreg);
670a50eb 1543 return;
3d3c5039 1544 }
9a7d824a
ILT		 1545 if (sreg == 0)
1546 {
8358c818
ILT		 1547 macro_build (&icnt, &offset_expr,
1548 likely ? "blezl" : "blez",
1549 "s,p", treg);
9a7d824a
ILT		 1550 return;
1551 }
670a50eb 1552 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1553 macro_build (&icnt, &offset_expr,
1554 likely ? "beql" : "beq",
1555 "s,t,p", AT, 0);
670a50eb 1556 break;
3d3c5039 1557
8358c818
ILT		 1558 case M_BGTL_I:
1559 likely = 1;
3d3c5039 1560 case M_BGT_I:
9a7d824a 1561 /* check for > max integer */
6e8dda9c
ILT		 1562 maxnum = 0x7fffffff;
1563 if (mips_isa >= 3)
1564 {
1565 maxnum <<= 16;
1566 maxnum |= 0xffff;
1567 maxnum <<= 16;
1568 maxnum |= 0xffff;
1569 }
1570 if (imm_expr.X_add_number >= maxnum)
9a7d824a
ILT		 1571 {
1572 do_false:
1573 /* result is always false */
8358c818
ILT		 1574 if (! likely)
1575 {
1576 as_warn ("Branch %s is always false (nop)", ip->insn_mo->name);
1577 macro_build (&icnt, NULL, "nop", "", 0);
1578 }
1579 else
1580 {
1581 as_warn ("Branch likely %s is always false", ip->insn_mo->name);
1582 macro_build (&icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
1583 }
9a7d824a
ILT		 1584 return;
1585 }
670a50eb
ILT		 1586 imm_expr.X_add_number++;
1587 /* FALLTHROUGH */
3d3c5039 1588 case M_BGE_I:
8358c818
ILT		 1589 case M_BGEL_I:
1590 if (mask == M_BGEL_I)
1591 likely = 1;
670a50eb
ILT		 1592 if (imm_expr.X_add_number == 0)
1593 {
8358c818
ILT		 1594 macro_build (&icnt, &offset_expr,
1595 likely ? "bgezl" : "bgez",
1596 "s,p", sreg);
670a50eb 1597 return;
3d3c5039 1598 }
670a50eb
ILT		 1599 if (imm_expr.X_add_number == 1)
1600 {
8358c818
ILT		 1601 macro_build (&icnt, &offset_expr,
1602 likely ? "bgtzl" : "bgtz",
1603 "s,p", sreg);
670a50eb 1604 return;
3d3c5039 1605 }
6e8dda9c
ILT		 1606 maxnum = 0x7fffffff;
1607 if (mips_isa >= 3)
1608 {
1609 maxnum <<= 16;
1610 maxnum |= 0xffff;
1611 maxnum <<= 16;
1612 maxnum |= 0xffff;
1613 }
1614 maxnum = - maxnum - 1;
1615 if (imm_expr.X_add_number <= maxnum)
9a7d824a
ILT		 1616 {
1617 do_true:
1618 /* result is always true */
1619 as_warn ("Branch %s is always true", ip->insn_mo->name);
1620 macro_build (&icnt, &offset_expr, "b", "p");
1621 return;
1622 }
6e8dda9c 1623 set_at (&icnt, sreg, 0);
8358c818
ILT		 1624 macro_build (&icnt, &offset_expr,
1625 likely ? "beql" : "beq",
1626 "s,t,p", AT, 0);
670a50eb 1627 break;
3d3c5039 1628
8358c818
ILT		 1629 case M_BGEUL:
1630 likely = 1;
3d3c5039 1631 case M_BGEU:
670a50eb 1632 if (treg == 0)
9a7d824a
ILT		 1633 goto do_true;
1634 if (sreg == 0)
670a50eb 1635 {
8358c818
ILT		 1636 macro_build (&icnt, &offset_expr,
1637 likely ? "beql" : "beq",
1638 "s,t,p", 0, treg);
670a50eb 1639 return;
3d3c5039 1640 }
670a50eb 1641 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1642 macro_build (&icnt, &offset_expr,
1643 likely ? "beql" : "beq",
1644 "s,t,p", AT, 0);
670a50eb 1645 break;
3d3c5039 1646
8358c818
ILT		 1647 case M_BGTUL_I:
1648 likely = 1;
9a7d824a 1649 case M_BGTU_I:
6e8dda9c 1650 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 1651 goto do_false;
1652 imm_expr.X_add_number++;
1653 /* FALLTHROUGH */
3d3c5039 1654 case M_BGEU_I:
8358c818
ILT		 1655 case M_BGEUL_I:
1656 if (mask == M_BGEUL_I)
1657 likely = 1;
670a50eb 1658 if (imm_expr.X_add_number == 0)
9a7d824a 1659 goto do_true;
670a50eb
ILT		 1660 if (imm_expr.X_add_number == 1)
1661 {
8358c818
ILT		 1662 macro_build (&icnt, &offset_expr,
1663 likely ? "bnel" : "bne",
1664 "s,t,p", sreg, 0);
670a50eb 1665 return;
3d3c5039 1666 }
6e8dda9c 1667 set_at (&icnt, sreg, 1);
8358c818
ILT		 1668 macro_build (&icnt, &offset_expr,
1669 likely ? "beql" : "beq",
1670 "s,t,p", AT, 0);
670a50eb 1671 break;
3d3c5039 1672
8358c818
ILT		 1673 case M_BGTL:
1674 likely = 1;
3d3c5039 1675 case M_BGT:
670a50eb
ILT		 1676 if (treg == 0)
1677 {
8358c818
ILT		 1678 macro_build (&icnt, &offset_expr,
1679 likely ? "bgtzl" : "bgtz",
1680 "s,p", sreg);
670a50eb 1681 return;
3d3c5039 1682 }
9a7d824a
ILT		 1683 if (sreg == 0)
1684 {
8358c818
ILT		 1685 macro_build (&icnt, &offset_expr,
1686 likely ? "bltzl" : "bltz",
1687 "s,p", treg);
9a7d824a
ILT		 1688 return;
1689 }
670a50eb 1690 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1691 macro_build (&icnt, &offset_expr,
1692 likely ? "bnel" : "bne",
1693 "s,t,p", AT, 0);
670a50eb 1694 break;
3d3c5039 1695
8358c818
ILT		 1696 case M_BGTUL:
1697 likely = 1;
3d3c5039 1698 case M_BGTU:
670a50eb
ILT		 1699 if (treg == 0)
1700 {
8358c818
ILT		 1701 macro_build (&icnt, &offset_expr,
1702 likely ? "bnel" : "bne",
1703 "s,t,p", sreg, 0);
670a50eb 1704 return;
3d3c5039 1705 }
9a7d824a
ILT		 1706 if (sreg == 0)
1707 goto do_false;
670a50eb 1708 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1709 macro_build (&icnt, &offset_expr,
1710 likely ? "bnel" : "bne",
1711 "s,t,p", AT, 0);
670a50eb 1712 break;
3d3c5039 1713
8358c818
ILT		 1714 case M_BLEL:
1715 likely = 1;
3d3c5039 1716 case M_BLE:
670a50eb
ILT		 1717 if (treg == 0)
1718 {
8358c818
ILT		 1719 macro_build (&icnt, &offset_expr,
1720 likely ? "blezl" : "blez",
1721 "s,p", sreg);
670a50eb
ILT		 1722 return;
1723 }
9a7d824a
ILT		 1724 if (sreg == 0)
1725 {
8358c818
ILT		 1726 macro_build (&icnt, &offset_expr,
1727 likely ? "bgezl" : "bgez",
1728 "s,p", treg);
9a7d824a
ILT		 1729 return;
1730 }
670a50eb 1731 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1732 macro_build (&icnt, &offset_expr,
1733 likely ? "beql" : "beq",
1734 "s,t,p", AT, 0);
670a50eb 1735 break;
3d3c5039 1736
8358c818
ILT		 1737 case M_BLEL_I:
1738 likely = 1;
3d3c5039 1739 case M_BLE_I:
6e8dda9c
ILT		 1740 maxnum = 0x7fffffff;
1741 if (mips_isa >= 3)
1742 {
1743 maxnum <<= 16;
1744 maxnum |= 0xffff;
1745 maxnum <<= 16;
1746 maxnum |= 0xffff;
1747 }
1748 if (imm_expr.X_add_number >= maxnum)
9a7d824a
ILT		 1749 goto do_true;
1750 imm_expr.X_add_number++;
1751 /* FALLTHROUGH */
9a7d824a 1752 case M_BLT_I:
8358c818
ILT		 1753 case M_BLTL_I:
1754 if (mask == M_BLTL_I)
1755 likely = 1;
670a50eb
ILT		 1756 if (imm_expr.X_add_number == 0)
1757 {
8358c818
ILT		 1758 macro_build (&icnt, &offset_expr,
1759 likely ? "bltzl" : "bltz",
1760 "s,p", sreg);
670a50eb
ILT		 1761 return;
1762 }
9a7d824a 1763 if (imm_expr.X_add_number == 1)
670a50eb 1764 {
8358c818
ILT		 1765 macro_build (&icnt, &offset_expr,
1766 likely ? "blezl" : "blez",
1767 "s,p", sreg);
670a50eb
ILT		 1768 return;
1769 }
6e8dda9c 1770 set_at (&icnt, sreg, 0);
8358c818
ILT		 1771 macro_build (&icnt, &offset_expr,
1772 likely ? "bnel" : "bne",
1773 "s,t,p", AT, 0);
670a50eb 1774 break;
3d3c5039 1775
8358c818
ILT		 1776 case M_BLEUL:
1777 likely = 1;
3d3c5039 1778 case M_BLEU:
670a50eb
ILT		 1779 if (treg == 0)
1780 {
8358c818
ILT		 1781 macro_build (&icnt, &offset_expr,
1782 likely ? "beql" : "beq",
1783 "s,t,p", sreg, 0);
670a50eb 1784 return;
3d3c5039 1785 }
9a7d824a
ILT		 1786 if (sreg == 0)
1787 goto do_true;
670a50eb 1788 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1789 macro_build (&icnt, &offset_expr,
1790 likely ? "beql" : "beq",
1791 "s,t,p", AT, 0);
670a50eb 1792 break;
3d3c5039 1793
8358c818
ILT		 1794 case M_BLEUL_I:
1795 likely = 1;
3d3c5039 1796 case M_BLEU_I:
6e8dda9c 1797 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 1798 goto do_true;
1799 imm_expr.X_add_number++;
1800 /* FALLTHROUGH */
9a7d824a 1801 case M_BLTU_I:
8358c818
ILT		 1802 case M_BLTUL_I:
1803 if (mask == M_BLTUL_I)
1804 likely = 1;
670a50eb 1805 if (imm_expr.X_add_number == 0)
9a7d824a
ILT		 1806 goto do_false;
1807 if (imm_expr.X_add_number == 1)
670a50eb 1808 {
8358c818
ILT		 1809 macro_build (&icnt, &offset_expr,
1810 likely ? "beql" : "beq",
1811 "s,t,p", sreg, 0);
670a50eb 1812 return;
3d3c5039 1813 }
6e8dda9c 1814 set_at (&icnt, sreg, 1);
8358c818
ILT		 1815 macro_build (&icnt, &offset_expr,
1816 likely ? "bnel" : "bne",
1817 "s,t,p", AT, 0);
670a50eb 1818 break;
3d3c5039 1819
8358c818
ILT		 1820 case M_BLTL:
1821 likely = 1;
3d3c5039 1822 case M_BLT:
670a50eb
ILT		 1823 if (treg == 0)
1824 {
8358c818
ILT		 1825 macro_build (&icnt, &offset_expr,
1826 likely ? "bltzl" : "bltz",
1827 "s,p", sreg);
670a50eb 1828 return;
3d3c5039 1829 }
9a7d824a 1830 if (sreg == 0)
670a50eb 1831 {
8358c818
ILT		 1832 macro_build (&icnt, &offset_expr,
1833 likely ? "bgtzl" : "bgtz",
1834 "s,p", treg);
670a50eb 1835 return;
3d3c5039 1836 }
9a7d824a 1837 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1838 macro_build (&icnt, &offset_expr,
1839 likely ? "bnel" : "bne",
1840 "s,t,p", AT, 0);
670a50eb 1841 break;
3d3c5039 1842
8358c818
ILT		 1843 case M_BLTUL:
1844 likely = 1;
3d3c5039 1845 case M_BLTU:
670a50eb 1846 if (treg == 0)
9a7d824a
ILT		 1847 goto do_false;
1848 if (sreg == 0)
670a50eb 1849 {
8358c818
ILT		 1850 macro_build (&icnt, &offset_expr,
1851 likely ? "bnel" : "bne",
1852 "s,t,p", 0, treg);
670a50eb
ILT		 1853 return;
1854 }
1855 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1856 macro_build (&icnt, &offset_expr,
1857 likely ? "bnel" : "bne",
1858 "s,t,p", AT, 0);
670a50eb 1859 break;
3d3c5039 1860
8358c818
ILT		 1861 case M_DDIV_3:
1862 dbl = 1;
3d3c5039 1863 case M_DIV_3:
8358c818
ILT		 1864 s = "mflo";
1865 goto do_div3;
1866 case M_DREM_3:
1867 dbl = 1;
3d3c5039 1868 case M_REM_3:
8358c818
ILT		 1869 s = "mfhi";
1870 do_div3:
670a50eb
ILT		 1871 if (treg == 0)
1872 {
1873 as_warn ("Divide by zero.");
1874 macro_build (&icnt, NULL, "break", "c", 7);
1875 return;
1876 }
1877
becfe05e
ILT		 1878 mips_emit_delays ();
1879 ++mips_noreorder;
8358c818
ILT		 1880 macro_build (&icnt, NULL,
1881 dbl ? "ddiv" : "div",
ff3a5c18 1882 "z,s,t", sreg, treg);
670a50eb
ILT		 1883 expr1.X_add_number = 8;
1884 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
1885 macro_build (&icnt, NULL, "nop", "", 0);
1886 macro_build (&icnt, NULL, "break", "c", 7);
1887 expr1.X_add_number = -1;
8358c818
ILT		 1888 macro_build (&icnt, &expr1,
1889 dbl ? "daddiu" : "addiu",
1890 "t,r,j", AT, 0);
1891 expr1.X_add_number = dbl ? 20 : 16;
670a50eb 1892 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, AT);
8358c818
ILT		 1893 if (dbl)
1894 {
1895 expr1.X_add_number = 1;
1896 macro_build (&icnt, &expr1, "daddiu", "t,r,j", AT, 0);
1897 macro_build (&icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
1898 }
1899 else
1900 {
1901 expr1.X_add_number = 0x80000000;
6e8dda9c 1902 macro_build (&icnt, &expr1, "lui", "t,u", AT);
8358c818 1903 }
670a50eb
ILT		 1904 expr1.X_add_number = 8;
1905 macro_build (&icnt, &expr1, "bne", "s,t,p", sreg, AT);
1906 macro_build (&icnt, NULL, "nop", "", 0);
1907 macro_build (&icnt, NULL, "break", "c", 6);
becfe05e 1908 --mips_noreorder;
8358c818 1909 macro_build (&icnt, NULL, s, "d", dreg);
670a50eb 1910 break;
3d3c5039
ILT		 1911
1912 case M_DIV_3I:
8358c818
ILT		 1913 s = "div";
1914 s2 = "mflo";
1915 goto do_divi;
3d3c5039 1916 case M_DIVU_3I:
8358c818
ILT		 1917 s = "divu";
1918 s2 = "mflo";
1919 goto do_divi;
3d3c5039 1920 case M_REM_3I:
8358c818
ILT		 1921 s = "div";
1922 s2 = "mfhi";
1923 goto do_divi;
3d3c5039 1924 case M_REMU_3I:
8358c818
ILT		 1925 s = "divu";
1926 s2 = "mfhi";
1927 goto do_divi;
1928 case M_DDIV_3I:
1929 dbl = 1;
1930 s = "ddiv";
1931 s2 = "mflo";
1932 goto do_divi;
1933 case M_DDIVU_3I:
1934 dbl = 1;
1935 s = "ddivu";
1936 s2 = "mflo";
1937 goto do_divi;
1938 case M_DREM_3I:
1939 dbl = 1;
1940 s = "ddiv";
1941 s2 = "mfhi";
1942 goto do_divi;
1943 case M_DREMU_3I:
1944 dbl = 1;
1945 s = "ddivu";
1946 s2 = "mfhi";
1947 do_divi:
670a50eb
ILT		 1948 if (imm_expr.X_add_number == 0)
1949 {
1950 as_warn ("Divide by zero.");
1951 macro_build (&icnt, NULL, "break", "c", 7);
1952 return;
1953 }
1954 if (imm_expr.X_add_number == 1)
1955 {
8358c818 1956 if (strcmp (s2, "mflo") == 0)
670a50eb 1957 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg);
3d3c5039 1958 else
670a50eb 1959 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
3d3c5039
ILT		 1960 return;
1961 }
8358c818
ILT		 1962 if (imm_expr.X_add_number == -1
1963 && s[strlen (s) - 1] != 'u')
1964 {
1965 if (strcmp (s2, "mflo") == 0)
1966 {
1967 if (dbl)
1968 macro_build (&icnt, NULL, "dneg", "d,w", dreg, sreg);
1969 else
1970 macro_build (&icnt, NULL, "neg", "d,w", dreg, sreg);
1971 }
1972 else
1973 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
1974 return;
1975 }
3d3c5039 1976
6e8dda9c 1977 load_register (&icnt, AT, &imm_expr);
ff3a5c18 1978 macro_build (&icnt, NULL, s, "z,s,t", sreg, AT);
8358c818 1979 macro_build (&icnt, NULL, s2, "d", dreg);
670a50eb
ILT		 1980 break;
1981
1982 case M_DIVU_3:
8358c818
ILT		 1983 s = "divu";
1984 s2 = "mflo";
1985 goto do_divu3;
670a50eb 1986 case M_REMU_3:
8358c818
ILT		 1987 s = "divu";
1988 s2 = "mfhi";
1989 goto do_divu3;
1990 case M_DDIVU_3:
1991 s = "ddivu";
1992 s2 = "mflo";
1993 goto do_divu3;
1994 case M_DREMU_3:
1995 s = "ddivu";
1996 s2 = "mfhi";
1997 do_divu3:
becfe05e
ILT		 1998 mips_emit_delays ();
1999 ++mips_noreorder;
ff3a5c18 2000 macro_build (&icnt, NULL, s, "z,s,t", sreg, treg);
670a50eb
ILT		 2001 expr1.X_add_number = 8;
2002 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
2003 macro_build (&icnt, NULL, "nop", "", 0);
2004 macro_build (&icnt, NULL, "break", "c", 7);
becfe05e 2005 --mips_noreorder;
8358c818 2006 macro_build (&icnt, NULL, s2, "d", dreg);
670a50eb 2007 return;
3d3c5039
ILT		 2008
2009 case M_LA:
5ac34ac3 2010 if (offset_expr.X_op == O_constant)
670a50eb 2011 {
6e8dda9c 2012 load_register (&icnt, treg, &offset_expr);
670a50eb 2013 return;
3d3c5039 2014 }
670a50eb 2015 if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2016 macro_build (&icnt, &offset_expr,
2017 mips_isa < 3 ? "addiu" : "daddiu",
2018 "t,r,j", treg, GP);
670a50eb
ILT		 2019 else
2020 {
6e8dda9c 2021 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2022 macro_build_lui (&icnt, &offset_expr, treg);
6e8dda9c
ILT		 2023 macro_build (&icnt, &offset_expr,
2024 mips_isa < 3 ? "addiu" : "daddiu",
2025 "t,r,j", treg, treg);
670a50eb
ILT		 2026 }
2027 return;
3d3c5039
ILT		 2028
2029 case M_LA_AB:
670a50eb 2030 tempreg = (breg == treg) ? AT : treg;
5ac34ac3 2031 if (offset_expr.X_op == O_constant)
6e8dda9c 2032 load_register (&icnt, tempreg, &offset_expr);
670a50eb 2033 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2034 macro_build (&icnt, &offset_expr,
2035 mips_isa < 3 ? "addiu" : "daddiu",
2036 "t,r,j", tempreg, GP);
670a50eb
ILT		 2037 else
2038 {
6e8dda9c 2039 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2040 macro_build_lui (&icnt, &offset_expr, tempreg);
6e8dda9c
ILT		 2041 macro_build (&icnt, &offset_expr,
2042 mips_isa < 3 ? "addiu" : "daddiu",
2043 "t,r,j", tempreg, tempreg);
670a50eb
ILT		 2044 }
2045 if (breg != 0)
2046 macro_build (&icnt, NULL, "addu", "d,v,t", treg, tempreg, breg);
2047 if (breg == treg)
2048 break;
2049 return;
3d3c5039
ILT		 2050
2051 case M_LB_AB:
670a50eb
ILT		 2052 s = "lb";
2053 goto ld;
3d3c5039 2054 case M_LBU_AB:
670a50eb
ILT		 2055 s = "lbu";
2056 goto ld;
3d3c5039 2057 case M_LH_AB:
670a50eb
ILT		 2058 s = "lh";
2059 goto ld;
3d3c5039 2060 case M_LHU_AB:
670a50eb
ILT		 2061 s = "lhu";
2062 goto ld;
3d3c5039 2063 case M_LW_AB:
670a50eb
ILT		 2064 s = "lw";
2065 goto ld;
3d3c5039 2066 case M_LWC0_AB:
670a50eb 2067 s = "lwc0";
8358c818 2068 coproc = 1;
670a50eb 2069 goto ld;
3d3c5039 2070 case M_LWC1_AB:
19ed8960 2071 case M_LI_SS:
670a50eb 2072 s = "lwc1";
8358c818 2073 coproc = 1;
670a50eb 2074 goto ld;
3d3c5039 2075 case M_LWC2_AB:
670a50eb 2076 s = "lwc2";
8358c818 2077 coproc = 1;
670a50eb 2078 goto ld;
3d3c5039 2079 case M_LWC3_AB:
670a50eb 2080 s = "lwc3";
8358c818 2081 coproc = 1;
670a50eb 2082 goto ld;
3d3c5039 2083 case M_LWL_AB:
670a50eb
ILT		 2084 s = "lwl";
2085 goto ld;
3d3c5039 2086 case M_LWR_AB:
670a50eb 2087 s = "lwr";
8358c818
ILT		 2088 goto ld;
2089 case M_LDC1_AB:
2090 s = "ldc1";
2091 coproc = 1;
2092 goto ld;
2093 case M_LDC2_AB:
2094 s = "ldc2";
2095 coproc = 1;
2096 goto ld;
2097 case M_LDC3_AB:
2098 s = "ldc3";
2099 coproc = 1;
2100 goto ld;
2101 case M_LDL_AB:
2102 s = "ldl";
2103 goto ld;
2104 case M_LDR_AB:
2105 s = "ldr";
2106 goto ld;
2107 case M_LL_AB:
2108 s = "ll";
2109 goto ld;
2110 case M_LLD_AB:
2111 s = "lld";
2112 goto ld;
2113 case M_LWU_AB:
2114 s = "lwu";
3d3c5039 2115 ld:
8358c818 2116 if (breg == treg || coproc)
670a50eb
ILT		 2117 {
2118 tempreg = AT;
2119 used_at = 1;
2120 }
2121 else
2122 {
2123 tempreg = treg;
2124 used_at = 0;
2125 }
2126 goto ld_st;
3d3c5039 2127 case M_SB_AB:
670a50eb
ILT		 2128 s = "sb";
2129 goto st;
3d3c5039 2130 case M_SH_AB:
670a50eb
ILT		 2131 s = "sh";
2132 goto st;
3d3c5039 2133 case M_SW_AB:
670a50eb
ILT		 2134 s = "sw";
2135 goto st;
3d3c5039 2136 case M_SWC0_AB:
670a50eb 2137 s = "swc0";
8358c818 2138 coproc = 1;
670a50eb 2139 goto st;
3d3c5039 2140 case M_SWC1_AB:
670a50eb 2141 s = "swc1";
8358c818 2142 coproc = 1;
670a50eb 2143 goto st;
3d3c5039 2144 case M_SWC2_AB:
670a50eb 2145 s = "swc2";
8358c818 2146 coproc = 1;
670a50eb 2147 goto st;
3d3c5039 2148 case M_SWC3_AB:
670a50eb 2149 s = "swc3";
8358c818 2150 coproc = 1;
670a50eb 2151 goto st;
3d3c5039 2152 case M_SWL_AB:
670a50eb
ILT		 2153 s = "swl";
2154 goto st;
3d3c5039 2155 case M_SWR_AB:
670a50eb 2156 s = "swr";
8358c818
ILT		 2157 goto st;
2158 case M_SC_AB:
2159 s = "sc";
2160 goto st;
2161 case M_SCD_AB:
2162 s = "scd";
2163 goto st;
2164 case M_SDC1_AB:
2165 s = "sdc1";
2166 coproc = 1;
2167 goto st;
2168 case M_SDC2_AB:
2169 s = "sdc2";
2170 coproc = 1;
2171 goto st;
2172 case M_SDC3_AB:
2173 s = "sdc3";
2174 coproc = 1;
2175 goto st;
2176 case M_SDL_AB:
2177 s = "sdl";
2178 goto st;
2179 case M_SDR_AB:
2180 s = "sdr";
3d3c5039 2181 st:
670a50eb
ILT		 2182 tempreg = AT;
2183 used_at = 1;
3d3c5039 2184 ld_st:
8358c818
ILT		 2185 if (mask == M_LWC1_AB
2186 || mask == M_SWC1_AB
2187 || mask == M_LI_SS
2188 || mask == M_LDC1_AB
2189 || mask == M_SDC1_AB)
670a50eb 2190 fmt = "T,o(b)";
8358c818 2191 else if (coproc)
19ed8960 2192 fmt = "E,o(b)";
670a50eb
ILT		 2193 else
2194 fmt = "t,o(b)";
2195 if (gp_reference (&offset_expr))
2196 {
2197 if (breg == 0)
2198 {
2199 macro_build (&icnt, &offset_expr, s, fmt, treg, GP);
2200 return;
2201 }
6e8dda9c
ILT		 2202 macro_build (&icnt, (expressionS *) NULL,
2203 mips_isa < 3 ? "addu" : "daddu",
2204 "d,v,t", tempreg, breg, GP);
670a50eb
ILT		 2205 }
2206 else
2207 {
6e8dda9c 2208 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2209 macro_build_lui (&icnt, &offset_expr, tempreg);
2210 if (breg != 0)
6e8dda9c
ILT		 2211 macro_build (&icnt, NULL,
2212 mips_isa < 3 ? "addu" : "daddu",
2213 "d,v,t", tempreg, tempreg, breg);
670a50eb
ILT		 2214 }
2215 macro_build (&icnt, &offset_expr, s, fmt, treg, tempreg);
2216 if (used_at)
2217 break;
2218 return;
3d3c5039
ILT		 2219
2220 case M_LI:
19ed8960 2221 case M_LI_S:
6e8dda9c 2222 load_register (&icnt, treg, &imm_expr);
670a50eb 2223 return;
3d3c5039
ILT		 2224
2225 case M_LI_D:
19ed8960
ILT		 2226 /* lui $at,%hi(foo)
2227 lw $v0,%lo(foo)($at)
2228 lw $v1,%lo(foo+4)($at)
2229 .rdata
2230 foo:
2231 .double 3.133435
2232 */
6e8dda9c 2233 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2234 macro_build_lui (&icnt, &offset_expr, AT);
8358c818
ILT		 2235 if (mips_isa >= 3)
2236 macro_build (&icnt, &offset_expr, "ld", "t,o(b)", treg, AT);
2237 else
2238 {
2239 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg, AT);
2240 offset_expr.X_add_number += 4;
2241 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg + 1, AT);
2242 }
670a50eb 2243 break;
3d3c5039
ILT		 2244
2245 case M_LI_DD:
19ed8960 2246 /* Load a floating point number from the .lit8 section. */
8358c818
ILT		 2247 if (mips_isa >= 2)
2248 {
2249 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, GP);
2250 return;
2251 }
19ed8960
ILT		 2252 breg = GP;
2253 /* Fall through. */
3d3c5039 2254 case M_L_DOB:
9a7d824a
ILT		 2255 /* Even on a big endian machine $fn comes before $fn+1. We have
2256 to adjust when loading from memory. */
8358c818 2257 assert (mips_isa < 2);
9a7d824a
ILT		 2258 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2259 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2260 breg);
670a50eb 2261 offset_expr.X_add_number += 4;
9a7d824a
ILT		 2262 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2263 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2264 breg);
670a50eb 2265 return;
3d3c5039
ILT		 2266
2267 case M_L_DAB:
670a50eb
ILT		 2268 /*
2269 * The MIPS assembler seems to check for X_add_number not
2270 * being double aligned and generating:
2271 * lui at,%hi(foo+1)
2272 * addu at,at,v1
2273 * addiu at,at,%lo(foo+1)
2274 * lwc1 f2,0(at)
2275 * lwc1 f3,4(at)
2276 * But, the resulting address is the same after relocation so why
2277 * generate the extra instruction?
2278 */
2279 if (gp_reference (&offset_expr))
2280 {
2281 if (breg == 0)
2282 tempreg = GP;
2283 else
2284 {
6e8dda9c
ILT		 2285 macro_build (&icnt, &offset_expr,
2286 mips_isa < 3 ? "addu" : "daddu",
2287 "d,v,t", AT, breg, GP);
670a50eb
ILT		 2288 tempreg = AT;
2289 }
2290 }
2291 else
2292 {
6e8dda9c 2293 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2294 macro_build_lui (&icnt, &offset_expr, AT);
2295 if (breg != 0)
6e8dda9c
ILT		 2296 macro_build (&icnt, NULL,
2297 mips_isa < 3 ? "addu" : "daddu",
2298 "d,v,t", AT, AT, breg);
670a50eb
ILT		 2299 tempreg = AT;
2300 }
8358c818
ILT		 2301 if (mips_isa >= 2)
2302 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, tempreg);
2303 else
2304 {
2305 /* Even on a big endian machine $fn comes before $fn+1. We
2306 have to adjust when loading from memory. */
2307 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2308 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2309 tempreg);
2310 offset_expr.X_add_number += 4;
2311 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2312 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2313 tempreg);
2314 }
670a50eb 2315 if (tempreg == AT)
3d3c5039 2316 break;
670a50eb 2317 return;
3d3c5039
ILT		 2318
2319 case M_LD_OB:
670a50eb
ILT		 2320 s = "lw";
2321 goto sd_ob;
3d3c5039 2322 case M_SD_OB:
670a50eb 2323 s = "sw";
3d3c5039 2324 sd_ob:
8358c818 2325 assert (mips_isa < 3);
670a50eb 2326 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
8358c818 2327 offset_expr.X_add_number += 4;
670a50eb
ILT		 2328 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, breg);
2329 return;
3d3c5039
ILT		 2330
2331 case M_LD_AB:
670a50eb 2332 s = "lw";
8358c818 2333 s2 = "ld";
670a50eb
ILT		 2334 if (breg == treg)
2335 {
2336 tempreg = AT;
2337 used_at = 1;
2338 }
2339 else
2340 {
2341 tempreg = treg;
2342 used_at = 0;
2343 }
2344 goto sd_ab;
3d3c5039 2345 case M_SD_AB:
670a50eb 2346 s = "sw";
8358c818 2347 s2 = "sd";
670a50eb
ILT		 2348 tempreg = AT;
2349 used_at = 1;
3d3c5039 2350 sd_ab:
670a50eb
ILT		 2351 if (gp_reference (&offset_expr))
2352 {
2353 if (breg == 0)
2354 {
2355 tempreg = GP;
2356 used_at = 0;
2357 }
2358 else
6e8dda9c
ILT		 2359 macro_build (&icnt, (expressionS *) NULL,
2360 mips_isa < 3 ? "addu" : "daddu",
2361 "d,v,t", tempreg, breg, GP);
670a50eb
ILT		 2362 }
2363 else
2364 {
6e8dda9c 2365 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2366 macro_build_lui (&icnt, &offset_expr, tempreg);
2367 if (breg != 0)
6e8dda9c
ILT		 2368 macro_build (&icnt, NULL,
2369 mips_isa < 3 ? "addu" : "daddu",
2370 "d,v,t", tempreg, tempreg, breg);
670a50eb 2371 }
8358c818
ILT		 2372 if (mips_isa >= 3)
2373 macro_build (&icnt, &offset_expr, s2, "t,o(b)", treg, tempreg);
2374 else
2375 {
2376 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, tempreg);
2377 offset_expr.X_add_number += 4;
2378 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, tempreg);
2379 }
670a50eb
ILT		 2380 if (used_at)
2381 break;
2382 return;
3d3c5039 2383
8358c818
ILT		 2384 case M_DMUL:
2385 dbl = 1;
3d3c5039 2386 case M_MUL:
8358c818
ILT		 2387 macro_build (&icnt, NULL,
2388 dbl ? "dmultu" : "multu",
2389 "s,t", sreg, treg);
670a50eb 2390 macro_build (&icnt, NULL, "mflo", "d", dreg);
670a50eb 2391 return;
3d3c5039 2392
8358c818
ILT		 2393 case M_DMUL_I:
2394 dbl = 1;
3d3c5039 2395 case M_MUL_I:
8358c818
ILT		 2396 /* The MIPS assembler some times generates shifts and adds. I'm
2397 not trying to be that fancy. GCC should do this for us
2398 anyway. */
6e8dda9c 2399 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2400 macro_build (&icnt, NULL,
2401 dbl ? "dmult" : "mult",
2402 "s,t", sreg, AT);
670a50eb 2403 macro_build (&icnt, NULL, "mflo", "d", dreg);
670a50eb 2404 break;
3d3c5039 2405
8358c818
ILT		 2406 case M_DMULO:
2407 dbl = 1;
2408 case M_MULO:
2409 mips_emit_delays ();
2410 ++mips_noreorder;
2411 macro_build (&icnt, NULL,
2412 dbl ? "dmult" : "mult",
2413 "s,t", sreg, treg);
2414 macro_build (&icnt, NULL, "mflo", "d", dreg);
2415 macro_build (&icnt, NULL,
2416 dbl ? "dsra32" : "sra",
2417 "d,w,<", dreg, dreg, 31);
2418 macro_build (&icnt, NULL, "mfhi", "d", AT);
2419 expr1.X_add_number = 8;
2420 macro_build (&icnt, &expr1, "beq", "s,t,p", dreg, AT);
2421 macro_build (&icnt, NULL, "nop", "", 0);
2422 macro_build (&icnt, NULL, "break", "c", 6);
2423 --mips_noreorder;
2424 macro_build (&icnt, NULL, "mflo", "d", dreg);
2425 break;
2426
2427 case M_DMULOU:
2428 dbl = 1;
2429 case M_MULOU:
2430 mips_emit_delays ();
2431 ++mips_noreorder;
2432 macro_build (&icnt, NULL,
2433 dbl ? "dmultu" : "multu",
2434 "s,t", sreg, treg);
2435 macro_build (&icnt, NULL, "mfhi", "d", AT);
2436 macro_build (&icnt, NULL, "mflo", "d", dreg);
2437 expr1.X_add_number = 8;
2438 macro_build (&icnt, &expr1, "beq", "s,t,p", AT, 0);
2439 macro_build (&icnt, NULL, "nop", "", 0);
2440 macro_build (&icnt, NULL, "break", "c", 6);
2441 --mips_noreorder;
2442 break;
2443
3d3c5039 2444 case M_ROL:
670a50eb
ILT		 2445 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2446 macro_build (&icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
2447 macro_build (&icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
2448 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2449 break;
3d3c5039
ILT		 2450
2451 case M_ROL_I:
670a50eb
ILT		 2452 macro_build (&icnt, NULL, "sll", "d,w,<", AT, sreg,
2453 imm_expr.X_add_number & 0x1f);
2454 macro_build (&icnt, NULL, "srl", "d,w,<", dreg, sreg,
2455 (0 - imm_expr.X_add_number) & 0x1f);
2456 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2457 break;
3d3c5039
ILT		 2458
2459 case M_ROR:
670a50eb
ILT		 2460 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2461 macro_build (&icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
2462 macro_build (&icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
2463 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2464 break;
3d3c5039
ILT		 2465
2466 case M_ROR_I:
670a50eb
ILT		 2467 macro_build (&icnt, NULL, "srl", "d,w,<", AT, sreg,
2468 imm_expr.X_add_number & 0x1f);
2469 macro_build (&icnt, NULL, "sll", "d,w,<", dreg, sreg,
2470 (0 - imm_expr.X_add_number) & 0x1f);
2471 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2472 break;
3d3c5039
ILT		 2473
2474 case M_S_DOB:
8358c818 2475 assert (mips_isa < 2);
9a7d824a
ILT		 2476 /* Even on a big endian machine $fn comes before $fn+1. We have
2477 to adjust when storing to memory. */
2478 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2479 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2480 breg);
670a50eb 2481 offset_expr.X_add_number += 4;
9a7d824a
ILT		 2482 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2483 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2484 breg);
670a50eb 2485 return;
3d3c5039
ILT		 2486
2487 case M_S_DAB:
670a50eb
ILT		 2488 if (gp_reference (&offset_expr))
2489 {
2490 if (breg == 0)
2491 tempreg = GP;
2492 else
2493 {
6e8dda9c
ILT		 2494 macro_build (&icnt, (expressionS *) NULL,
2495 mips_isa < 3 ? "addu" : "daddu",
2496 "d,v,t", AT, breg, GP);
670a50eb
ILT		 2497 tempreg = AT;
2498 }
2499 }
2500 else
2501 {
6e8dda9c 2502 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2503 macro_build_lui (&icnt, &offset_expr, AT);
2504 if (breg != 0)
6e8dda9c
ILT		 2505 macro_build (&icnt, NULL,
2506 mips_isa < 3 ? "addu" : "daddu",
2507 "d,v,t", AT, AT, breg);
670a50eb
ILT		 2508 tempreg = AT;
2509 }
8358c818
ILT		 2510 if (mips_isa >= 2)
2511 macro_build (&icnt, &offset_expr, "sdc1", "T,o(b)", treg, tempreg);
2512 else
2513 {
2514 /* Even on a big endian machine $fn comes before $fn+1. We
2515 have to adjust when storing to memory. */
2516 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2517 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2518 tempreg);
2519 offset_expr.X_add_number += 4;
2520 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2521 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2522 tempreg);
2523 }
670a50eb 2524 if (tempreg == AT)
3d3c5039 2525 break;
670a50eb 2526 return;
3d3c5039
ILT		 2527
2528 case M_SEQ:
670a50eb
ILT		 2529 if (sreg == 0)
2530 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, treg);
2531 else if (treg == 0)
2532 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2533 else
2534 {
2535 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2536 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
3d3c5039 2537 }
670a50eb 2538 return;
3d3c5039
ILT		 2539
2540 case M_SEQ_I:
670a50eb
ILT		 2541 if (imm_expr.X_add_number == 0)
2542 {
2543 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2544 return;
3d3c5039 2545 }
670a50eb
ILT		 2546 if (sreg == 0)
2547 {
9a7d824a 2548 as_warn ("Instruction %s: result is always false",
6e8dda9c 2549 ip->insn_mo->name);
670a50eb
ILT		 2550 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
2551 return;
3d3c5039 2552 }
6e8dda9c 2553 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 2554 {
670a50eb
ILT		 2555 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2556 used_at = 0;
6e8dda9c
ILT		 2557 }
2558 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2559 {
2560 imm_expr.X_add_number = -imm_expr.X_add_number;
2561 macro_build (&icnt, &imm_expr,
2562 mips_isa < 3 ? "addiu" : "daddiu",
2563 "t,r,j", dreg, sreg);
2564 used_at = 0;
2565 }
2566 else
2567 {
2568 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2569 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2570 used_at = 1;
2571 }
2572 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
2573 if (used_at)
2574 break;
2575 return;
3d3c5039
ILT		 2576
2577 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
670a50eb
ILT		 2578 s = "slt";
2579 goto sge;
3d3c5039 2580 case M_SGEU:
670a50eb 2581 s = "sltu";
3d3c5039 2582 sge:
670a50eb
ILT		 2583 macro_build (&icnt, NULL, s, "d,v,t", dreg, sreg, treg);
2584 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2585 return;
3d3c5039 2586
670a50eb 2587 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
3d3c5039 2588 case M_SGEU_I:
6e8dda9c 2589 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2590 {
2591 macro_build (&icnt, &expr1,
6e8dda9c
ILT		 2592 mask == M_SGE_I ? "slti" : "sltiu",
2593 "t,r,j", dreg, sreg);
670a50eb
ILT		 2594 used_at = 0;
2595 }
2596 else
2597 {
6e8dda9c 2598 load_register (&icnt, AT, &imm_expr);
670a50eb 2599 macro_build (&icnt, NULL,
6e8dda9c
ILT		 2600 mask == M_SGE_I ? "slt" : "sltu",
2601 "d,v,t", dreg, sreg, AT);
670a50eb
ILT		 2602 used_at = 1;
2603 }
2604 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2605 if (used_at)
2606 break;
2607 return;
3d3c5039
ILT		 2608
2609 case M_SGT: /* sreg > treg <==> treg < sreg */
670a50eb
ILT		 2610 s = "slt";
2611 goto sgt;
3d3c5039 2612 case M_SGTU:
670a50eb 2613 s = "sltu";
3d3c5039 2614 sgt:
670a50eb
ILT		 2615 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
2616 return;
3d3c5039 2617
670a50eb
ILT		 2618 case M_SGT_I: /* sreg > I <==> I < sreg */
2619 s = "slt";
2620 goto sgti;
3d3c5039 2621 case M_SGTU_I:
670a50eb 2622 s = "sltu";
3d3c5039 2623 sgti:
6e8dda9c 2624 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2625 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
2626 break;
3d3c5039 2627
670a50eb
ILT		 2628 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2629 s = "slt";
2630 goto sle;
3d3c5039 2631 case M_SLEU:
670a50eb 2632 s = "sltu";
3d3c5039 2633 sle:
670a50eb 2634 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
9a7d824a 2635 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
670a50eb 2636 return;
3d3c5039 2637
670a50eb
ILT		 2638 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2639 s = "slt";
2640 goto slei;
3d3c5039 2641 case M_SLEU_I:
670a50eb 2642 s = "sltu";
3d3c5039 2643 slei:
6e8dda9c 2644 load_register (&icnt, AT, &imm_expr);
670a50eb 2645 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
9a7d824a 2646 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
670a50eb 2647 break;
3d3c5039
ILT		 2648
2649 case M_SLT_I:
6e8dda9c 2650 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2651 {
2652 macro_build (&icnt, &imm_expr, "slti", "t,r,j", dreg, sreg);
2653 return;
3d3c5039 2654 }
6e8dda9c 2655 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2656 macro_build (&icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
2657 break;
3d3c5039
ILT		 2658
2659 case M_SLTU_I:
6e8dda9c 2660 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2661 {
2662 macro_build (&icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg);
2663 return;
3d3c5039 2664 }
6e8dda9c 2665 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2666 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
2667 break;
3d3c5039
ILT		 2668
2669 case M_SNE:
670a50eb
ILT		 2670 if (sreg == 0)
2671 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, treg);
2672 else if (treg == 0)
2673 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2674 else
2675 {
2676 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2677 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
3d3c5039 2678 }
670a50eb 2679 return;
3d3c5039
ILT		 2680
2681 case M_SNE_I:
670a50eb
ILT		 2682 if (imm_expr.X_add_number == 0)
2683 {
2684 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2685 return;
3d3c5039 2686 }
670a50eb
ILT		 2687 if (sreg == 0)
2688 {
9a7d824a 2689 as_warn ("Instruction %s: result is always true",
6e8dda9c
ILT		 2690 ip->insn_mo->name);
2691 macro_build (&icnt, &expr1,
2692 mips_isa < 3 ? "addiu" : "daddiu",
2693 "t,r,j", dreg, 0);
670a50eb 2694 return;
3d3c5039 2695 }
6e8dda9c 2696 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 2697 {
670a50eb
ILT		 2698 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2699 used_at = 0;
6e8dda9c
ILT		 2700 }
2701 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2702 {
2703 imm_expr.X_add_number = -imm_expr.X_add_number;
2704 macro_build (&icnt, &imm_expr,
2705 mips_isa < 3 ? "addiu" : "daddiu",
2706 "t,r,j", dreg, sreg);
2707 used_at = 0;
2708 }
2709 else
2710 {
2711 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2712 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2713 used_at = 1;
2714 }
2715 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
2716 if (used_at)
2717 break;
2718 return;
3d3c5039 2719
8358c818
ILT		 2720 case M_DSUB_I:
2721 dbl = 1;
3d3c5039 2722 case M_SUB_I:
6e8dda9c 2723 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 2724 {
2725 imm_expr.X_add_number = -imm_expr.X_add_number;
8358c818
ILT		 2726 macro_build (&icnt, &imm_expr,
2727 dbl ? "daddi" : "addi",
2728 "t,r,j", dreg, sreg);
670a50eb 2729 return;
3d3c5039 2730 }
6e8dda9c 2731 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2732 macro_build (&icnt, NULL,
2733 dbl ? "dsub" : "sub",
2734 "d,v,t", dreg, sreg, AT);
670a50eb 2735 break;
3d3c5039 2736
8358c818
ILT		 2737 case M_DSUBU_I:
2738 dbl = 1;
3d3c5039 2739 case M_SUBU_I:
6e8dda9c 2740 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 2741 {
2742 imm_expr.X_add_number = -imm_expr.X_add_number;
8358c818
ILT		 2743 macro_build (&icnt, &imm_expr,
2744 dbl ? "daddiu" : "addiu",
2745 "t,r,j", dreg, sreg);
670a50eb 2746 return;
3d3c5039 2747 }
6e8dda9c 2748 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2749 macro_build (&icnt, NULL,
2750 dbl ? "dsubu" : "subu",
2751 "d,v,t", dreg, sreg, AT);
2752 break;
2753
2754 case M_TEQ_I:
2755 s = "teq";
2756 goto trap;
2757 case M_TGE_I:
2758 s = "tge";
2759 goto trap;
2760 case M_TGEU_I:
2761 s = "tgeu";
2762 goto trap;
2763 case M_TLT_I:
2764 s = "tlt";
2765 goto trap;
2766 case M_TLTU_I:
2767 s = "tltu";
2768 goto trap;
2769 case M_TNE_I:
2770 s = "tne";
2771 trap:
6e8dda9c 2772 load_register (&icnt, AT, &imm_expr);
8358c818 2773 macro_build (&icnt, NULL, s, "s,t", sreg, AT);
670a50eb 2774 break;
3d3c5039
ILT		 2775
2776 case M_TRUNCWD:
2777 case M_TRUNCWS:
8358c818 2778 assert (mips_isa < 2);
670a50eb
ILT		 2779 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
2780 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
2781
2782 /*
2783 * Is the double cfc1 instruction a bug in the mips assembler;
2784 * or is there a reason for it?
2785 */
becfe05e
ILT		 2786 mips_emit_delays ();
2787 ++mips_noreorder;
918692a5
ILT		 2788 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
2789 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
670a50eb
ILT		 2790 macro_build (&icnt, NULL, "nop", "");
2791 expr1.X_add_number = 3;
2792 macro_build (&icnt, &expr1, "ori", "t,r,i", AT, treg);
2793 expr1.X_add_number = 2;
2794 macro_build (&icnt, &expr1, "xori", "t,r,i", AT, AT);
918692a5 2795 macro_build (&icnt, NULL, "ctc1", "t,G", AT, 31);
670a50eb
ILT		 2796 macro_build (&icnt, NULL, "nop", "");
2797 macro_build (&icnt, NULL,
2798 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
918692a5 2799 macro_build (&icnt, NULL, "ctc1", "t,G", treg, 31);
670a50eb 2800 macro_build (&icnt, NULL, "nop", "");
becfe05e 2801 --mips_noreorder;
670a50eb 2802 break;
3d3c5039
ILT		 2803
2804 case M_ULH:
670a50eb
ILT		 2805 s = "lb";
2806 goto ulh;
3d3c5039 2807 case M_ULHU:
670a50eb 2808 s = "lbu";
3d3c5039 2809 ulh:
670a50eb
ILT		 2810 /* avoid load delay */
2811 offset_expr.X_add_number += 1;
2812 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
2813 offset_expr.X_add_number -= 1;
2814 macro_build (&icnt, &offset_expr, "lbu", "t,o(b)", AT, breg);
2815 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2816 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2817 break;
3d3c5039
ILT		 2818
2819 case M_ULW:
670a50eb
ILT		 2820 /* does this work on a big endian machine? */
2821 offset_expr.X_add_number += 3;
2822 macro_build (&icnt, &offset_expr, "lwl", "t,o(b)", treg, breg);
2823 offset_expr.X_add_number -= 3;
2824 macro_build (&icnt, &offset_expr, "lwr", "t,o(b)", treg, breg);
2825 return;
3d3c5039
ILT		 2826
2827 case M_ULH_A:
2828 case M_ULHU_A:
2829 case M_ULW_A:
5ac34ac3 2830 if (offset_expr.X_op == O_constant)
6e8dda9c 2831 load_register (&icnt, AT, &offset_expr);
670a50eb 2832 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2833 macro_build (&icnt, &offset_expr,
2834 mips_isa < 3 ? "addiu" : "daddiu",
2835 "t,r,j", AT, GP);
670a50eb
ILT		 2836 else
2837 {
6e8dda9c 2838 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2839 macro_build_lui (&icnt, &offset_expr, AT);
6e8dda9c
ILT		 2840 macro_build (&icnt, &offset_expr,
2841 mips_isa < 3 ? "addiu" : "daddiu",
2842 "t,r,j", AT, AT);
3d3c5039 2843 }
670a50eb
ILT		 2844 if (mask == M_ULW_A)
2845 {
2846 expr1.X_add_number = 3;
2847 macro_build (&icnt, &expr1, "lwl", "t,o(b)", treg, AT);
2848 imm_expr.X_add_number = 0;
2849 macro_build (&icnt, &expr1, "lwr", "t,o(b)", treg, AT);
2850 }
2851 else
2852 {
2853 macro_build (&icnt, &expr1,
2854 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, AT);
2855 imm_expr.X_add_number = 0;
2856 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2857 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2858 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2859 }
2860 break;
3d3c5039
ILT		 2861
2862 case M_USH:
670a50eb
ILT		 2863 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", treg, breg);
2864 macro_build (&icnt, NULL, "srl", "d,w,<", AT, treg, 8);
2865 offset_expr.X_add_number += 1;
2866 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", AT, breg);
2867 break;
3d3c5039
ILT		 2868
2869 case M_USW:
670a50eb
ILT		 2870 offset_expr.X_add_number += 3;
2871 macro_build (&icnt, &offset_expr, "swl", "t,o(b)", treg, breg);
2872 offset_expr.X_add_number -= 3;
2873 macro_build (&icnt, &offset_expr, "swr", "t,o(b)", treg, breg);
2874 return;
3d3c5039
ILT		 2875
2876 case M_USH_A:
2877 case M_USW_A:
5ac34ac3 2878 if (offset_expr.X_op == O_constant)
6e8dda9c 2879 load_register (&icnt, AT, &offset_expr);
670a50eb 2880 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2881 macro_build (&icnt, &offset_expr,
2882 mips_isa < 3 ? "addiu" : "daddiu",
2883 "t,r,j", AT, GP);
670a50eb
ILT		 2884 else
2885 {
6e8dda9c 2886 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2887 macro_build_lui (&icnt, &offset_expr, AT);
6e8dda9c
ILT		 2888 macro_build (&icnt, &offset_expr,
2889 mips_isa < 3 ? "addiu" : "daddiu",
2890 "t,r,j", AT, AT);
3d3c5039 2891 }
670a50eb
ILT		 2892 if (mask == M_USW_A)
2893 {
2894 expr1.X_add_number = 3;
2895 macro_build (&icnt, &expr1, "swl", "t,o(b)", treg, AT);
2896 expr1.X_add_number = 0;
2897 macro_build (&icnt, &expr1, "swr", "t,o(b)", treg, AT);
2898 }
2899 else
2900 {
2901 expr1.X_add_number = 0;
2902 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2903 macro_build (&icnt, NULL, "srl", "d,w,<", treg, treg, 8);
2904 expr1.X_add_number = 1;
2905 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2906 expr1.X_add_number = 0;
2907 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2908 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2909 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2910 }
2911 break;
3d3c5039
ILT		 2912
2913 default:
670a50eb 2914 as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
8358c818 2915 break;
3d3c5039 2916 }
670a50eb
ILT		 2917 if (mips_noat)
2918 as_warn ("Macro used $at after \".set noat\"");
3d3c5039
ILT		 2919}
2920
2921
2922/*
2923This routine assembles an instruction into its binary format. As a side
2924effect it sets one of the global variables imm_reloc or offset_reloc to the
2925type of relocation to do if one of the operands is an address expression.
2926*/
2927static void
2928mips_ip (str, ip)
2929 char *str;
2930 struct mips_cl_insn *ip;
2931{
670a50eb
ILT		 2932 char *s;
2933 const char *args;
2934 char c;
2935 struct mips_opcode *insn;
2936 char *argsStart;
2937 unsigned int regno;
2938 unsigned int lastregno = 0;
2939 char *s_reset;
2940
2941 insn_error = NULL;
2942
2943 for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s)
2944 continue;
2945 switch (*s)
2946 {
3d3c5039 2947 case '\0':
670a50eb 2948 break;
3d3c5039
ILT		 2949
2950 case ' ':
670a50eb
ILT		 2951 *s++ = '\0';
2952 break;
3d3c5039
ILT		 2953
2954 default:
670a50eb
ILT		 2955 as_warn ("Unknown opcode: `%s'", str);
2956 exit (1);
3d3c5039 2957 }
670a50eb
ILT		 2958 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
2959 {
2960 as_warn ("`%s' not in hash table.", str);
2961 insn_error = "ERROR: Unrecognized opcode";
2962 return;
3d3c5039 2963 }
670a50eb
ILT		 2964 argsStart = s;
2965 for (;;)
2966 {
8358c818
ILT		 2967 int insn_isa;
2968
670a50eb 2969 assert (strcmp (insn->name, str) == 0);
8358c818
ILT		 2970
2971 if (insn->pinfo == INSN_MACRO)
2972 insn_isa = insn->match;
2973 else if (insn->pinfo & INSN_ISA2)
2974 insn_isa = 2;
2975 else if (insn->pinfo & INSN_ISA3)
2976 insn_isa = 3;
2977 else
2978 insn_isa = 1;
2979
2980 if (insn_isa > mips_isa)
2981 {
2982 if (insn + 1 < &mips_opcodes[NUMOPCODES]
2983 && strcmp (insn->name, insn[1].name) == 0)
2984 {
2985 ++insn;
2986 continue;
2987 }
2988 insn_error = "ERROR: instruction not supported on this processor";
2989 return;
2990 }
2991
670a50eb
ILT		 2992 ip->insn_mo = insn;
2993 ip->insn_opcode = insn->match;
2994 for (args = insn->args;; ++args)
2995 {
2996 if (*s == ' ')
2997 ++s;
2998 switch (*args)
2999 {
3000 case '\0': /* end of args */
3001 if (*s == '\0')
3002 return;
3003 break;
3d3c5039
ILT		 3004
3005 case ',':
670a50eb
ILT		 3006 if (*s++ == *args)
3007 continue;
3008 s--;
3009 switch (*++args)
3010 {
3d3c5039
ILT		 3011 case 'r':
3012 case 'v':
670a50eb
ILT		 3013 ip->insn_opcode |= lastregno << 21;
3014 continue;
3d3c5039
ILT		 3015
3016 case 'w':
3017 case 'W':
670a50eb
ILT		 3018 ip->insn_opcode |= lastregno << 16;
3019 continue;
3d3c5039
ILT		 3020
3021 case 'V':
670a50eb
ILT		 3022 ip->insn_opcode |= lastregno << 11;
3023 continue;
3d3c5039 3024 }
670a50eb 3025 break;
3d3c5039
ILT		 3026
3027 case '(':
670a50eb
ILT		 3028 /* handle optional base register.
3029 Either the base register is omitted or
3030 we must have a left paren. */
3031 /* this is dependent on the next operand specifier
3032 is a 'b' for base register */
3033 assert (args[1] == 'b');
3034 if (*s == '\0')
3035 return;
3d3c5039 3036
670a50eb
ILT		 3037 case ')': /* these must match exactly */
3038 if (*s++ == *args)
3d3c5039 3039 continue;
670a50eb
ILT		 3040 break;
3041
3042 case '<': /* must be at least one digit */
3043 /*
3044 * According to the manual, if the shift amount is greater
3045 * than 31 or less than 0 the the shift amount should be
3046 * mod 32. In reality the mips assembler issues an error.
3047 * We issue a warning and do the mod.
3048 */
3049 my_getExpression (&imm_expr, s);
3050 check_absolute_expr (ip, &imm_expr);
3051 if ((unsigned long) imm_expr.X_add_number > 31)
3052 {
58d4951d
ILT		 3053 as_warn ("Improper shift amount (%ld)",
3054 (long) imm_expr.X_add_number);
670a50eb
ILT		 3055 imm_expr.X_add_number = imm_expr.X_add_number % 32;
3056 }
3057 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 3058 imm_expr.X_op = O_absent;
670a50eb
ILT		 3059 s = expr_end;
3060 continue;
3061
3062 case 'c': /* break code */
3063 my_getExpression (&imm_expr, s);
3064 check_absolute_expr (ip, &imm_expr);
3065 if ((unsigned) imm_expr.X_add_number > 1023)
58d4951d
ILT		 3066 as_warn ("Illegal break code (%ld)",
3067 (long) imm_expr.X_add_number);
670a50eb 3068 ip->insn_opcode |= imm_expr.X_add_number << 16;
5ac34ac3 3069 imm_expr.X_op = O_absent;
670a50eb
ILT		 3070 s = expr_end;
3071 continue;
3072
918692a5
ILT		 3073 case 'B': /* syscall code */
3074 my_getExpression (&imm_expr, s);
3075 check_absolute_expr (ip, &imm_expr);
3076 if ((unsigned) imm_expr.X_add_number > 0xfffff)
58d4951d
ILT		 3077 as_warn ("Illegal syscall code (%ld)",
3078 (long) imm_expr.X_add_number);
918692a5 3079 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 3080 imm_expr.X_op = O_absent;
918692a5
ILT		 3081 s = expr_end;
3082 continue;
3083
0aa07269
ILT		 3084 case 'C': /* Coprocessor code */
3085 my_getExpression (&imm_expr, s);
3086 check_absolute_expr (ip, &imm_expr);
3087 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
3088 {
58d4951d
ILT		 3089 as_warn ("Coproccesor code > 25 bits (%ld)",
3090 (long) imm_expr.X_add_number);
0aa07269
ILT		 3091 imm_expr.X_add_number &= ((1<<25) - 1);
3092 }
3093 ip->insn_opcode |= imm_expr.X_add_number;
3094 imm_expr.X_op = O_absent;
3095 s = expr_end;
3096 continue;
3097
670a50eb
ILT		 3098 case 'b': /* base register */
3099 case 'd': /* destination register */
3100 case 's': /* source register */
3101 case 't': /* target register */
3102 case 'r': /* both target and source */
3103 case 'v': /* both dest and source */
3104 case 'w': /* both dest and target */
918692a5
ILT		 3105 case 'E': /* coprocessor target register */
3106 case 'G': /* coprocessor destination register */
8358c818 3107 case 'x': /* ignore register name */
ff3a5c18 3108 case 'z': /* must be zero register */
670a50eb
ILT		 3109 s_reset = s;
3110 if (s[0] == '$')
3111 {
3112 if (isdigit (s[1]))
3113 {
3114 ++s;
3115 regno = 0;
3116 do
3117 {
3118 regno *= 10;
3119 regno += *s - '0';
3120 ++s;
3121 }
3122 while (isdigit (*s));
0aa07269
ILT		 3123 if (regno > 31)
3124 as_bad ("Invalid register number (%d)", regno);
670a50eb 3125 }
0aa07269 3126 else if (*args != 'E' && *args != 'G')
670a50eb 3127 {
0aa07269
ILT		 3128 if (s[1] == 'f' && s[2] == 'p')
3129 {
3130 s += 3;
3131 regno = 30;
3132 }
3133 else if (s[1] == 's' && s[2] == 'p')
3134 {
3135 s += 3;
3136 regno = 29;
3137 }
3138 else if (s[1] == 'g' && s[2] == 'p')
3139 {
3140 s += 3;
3141 regno = 28;
3142 }
3143 else if (s[1] == 'a' && s[2] == 't')
3144 {
3145 s += 3;
3146 regno = 1;
3147 }
3148 else
3149 goto notreg;
3150 if (regno == AT && ! mips_noat)
3151 as_warn ("Used $at without \".set noat\"");
670a50eb 3152 }
670a50eb
ILT		 3153 c = *args;
3154 if (*s == ' ')
3155 s++;
3156 if (args[1] != *s)
3157 {
3158 if (c == 'r' || c == 'v' || c == 'w')
3159 {
3160 regno = lastregno;
3161 s = s_reset;
3162 args++;
3163 }
3164 }
ff3a5c18
ILT		 3165 /* 'z' only matches $0. */
3166 if (c == 'z' && regno != 0)
3167 break;
670a50eb
ILT		 3168 switch (c)
3169 {
3d3c5039
ILT		 3170 case 'r':
3171 case 's':
3172 case 'v':
3173 case 'b':
670a50eb
ILT		 3174 ip->insn_opcode |= regno << 21;
3175 break;
3d3c5039 3176 case 'd':
918692a5 3177 case 'G':
670a50eb
ILT		 3178 ip->insn_opcode |= regno << 11;
3179 break;
3d3c5039
ILT		 3180 case 'w':
3181 case 't':
918692a5 3182 case 'E':
670a50eb 3183 ip->insn_opcode |= regno << 16;
8358c818
ILT		 3184 break;
3185 case 'x':
3186 /* This case exists because on the r3000 trunc
3187 expands into a macro which requires a gp
3188 register. On the r6000 or r4000 it is
3189 assembled into a single instruction which
3190 ignores the register. Thus the insn version
3191 is MIPS_ISA2 and uses 'x', and the macro
3192 version is MIPS_ISA1 and uses 't'. */
3193 break;
ff3a5c18
ILT		 3194 case 'z':
3195 /* This case is for the div instruction, which
3196 acts differently if the destination argument
3197 is $0. This only matches $0, and is checked
3198 outside the switch. */
3199 break;
3d3c5039 3200 }
670a50eb
ILT		 3201 lastregno = regno;
3202 continue;
3d3c5039
ILT		 3203 }
3204 notreg:
670a50eb
ILT		 3205 switch (*args++)
3206 {
3d3c5039
ILT		 3207 case 'r':
3208 case 'v':
670a50eb
ILT		 3209 ip->insn_opcode |= lastregno << 21;
3210 continue;
3d3c5039 3211 case 'w':
670a50eb
ILT		 3212 ip->insn_opcode |= lastregno << 16;
3213 continue;
3d3c5039 3214 }
670a50eb 3215 break;
3d3c5039 3216
670a50eb
ILT		 3217 case 'D': /* floating point destination register */
3218 case 'S': /* floating point source register */
3219 case 'T': /* floating point target register */
3d3c5039
ILT		 3220 case 'V':
3221 case 'W':
670a50eb
ILT		 3222 s_reset = s;
3223 if (s[0] == '$' && s[1] == 'f' && isdigit (s[2]))
3224 {
3225 s += 2;
3226 regno = 0;
3227 do
3228 {
3229 regno *= 10;
3230 regno += *s - '0';
3231 ++s;
3232 }
3233 while (isdigit (*s));
3234
3235 if (regno > 31)
3236 as_bad ("Invalid float register number (%d)", regno);
3237
3238 if ((regno & 1) &&
3239 !(strcmp (str, "mtc1") == 0 ||
3240 strcmp (str, "mfc1") == 0 ||
3241 strcmp (str, "lwc1") == 0 ||
3242 strcmp (str, "swc1") == 0))
3243 as_warn ("Float register should be even, was %d",
3244 regno);
3245
3246 c = *args;
3247 if (*s == ' ')
3248 s++;
3249 if (args[1] != *s)
3250 {
3251 if (c == 'V' || c == 'W')
3252 {
3253 regno = lastregno;
3254 s = s_reset;
3255 args++;
3d3c5039
ILT		 3256 }
3257 }
670a50eb
ILT		 3258 switch (c)
3259 {
3d3c5039 3260 case 'D':
670a50eb
ILT		 3261 ip->insn_opcode |= regno << 6;
3262 break;
3d3c5039
ILT		 3263 case 'V':
3264 case 'S':
670a50eb
ILT		 3265 ip->insn_opcode |= regno << 11;
3266 break;
3d3c5039
ILT		 3267 case 'W':
3268 case 'T':
670a50eb 3269 ip->insn_opcode |= regno << 16;
3d3c5039 3270 }
670a50eb
ILT		 3271 lastregno = regno;
3272 continue;
3d3c5039 3273 }
670a50eb
ILT		 3274 switch (*args++)
3275 {
3d3c5039 3276 case 'V':
670a50eb
ILT		 3277 ip->insn_opcode |= lastregno << 11;
3278 continue;
3d3c5039 3279 case 'W':
670a50eb
ILT		 3280 ip->insn_opcode |= lastregno << 16;
3281 continue;
3d3c5039 3282 }
670a50eb 3283 break;
3d3c5039
ILT		 3284
3285 case 'I':
670a50eb
ILT		 3286 my_getExpression (&imm_expr, s);
3287 check_absolute_expr (ip, &imm_expr);
3288 s = expr_end;
3289 continue;
3d3c5039
ILT		 3290
3291 case 'A':
670a50eb
ILT		 3292 my_getExpression (&offset_expr, s);
3293 imm_reloc = BFD_RELOC_32;
3294 s = expr_end;
3295 continue;
3d3c5039
ILT		 3296
3297 case 'F':
19ed8960
ILT		 3298 case 'L':
3299 case 'f':
3300 case 'l':
3301 {
3302 int f64;
3303 char *save_in;
3304 char *err;
3305 unsigned char temp[8];
604633ae
ILT		 3306 int len;
3307 unsigned int length;
19ed8960
ILT		 3308 segT seg;
3309 subsegT subseg;
3310 char *p;
3311
3312 /* These only appear as the last operand in an
3313 instruction, and every instruction that accepts
3314 them in any variant accepts them in all variants.
3315 This means we don't have to worry about backing out
3316 any changes if the instruction does not match.
3317
3318 The difference between them is the size of the
3319 floating point constant and where it goes. For 'F'
3320 and 'L' the constant is 64 bits; for 'f' and 'l' it
3321 is 32 bits. Where the constant is placed is based
3322 on how the MIPS assembler does things:
3323 F -- .rdata
3324 L -- .lit8
3325 f -- immediate value
3326 l -- .lit4
3327 */
3328
3329 f64 = *args == 'F' || *args == 'L';
3330
3331 save_in = input_line_pointer;
3332 input_line_pointer = s;
604633ae
ILT		 3333 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
3334 length = len;
19ed8960
ILT		 3335 s = input_line_pointer;
3336 input_line_pointer = save_in;
3337 if (err != NULL && *err != '\0')
3338 {
3339 as_bad ("Bad floating point constant: %s", err);
3340 memset (temp, '\0', sizeof temp);
3341 length = f64 ? 8 : 4;
3342 }
3343
3344 assert (length == (f64 ? 8 : 4));
3345
3346 if (*args == 'f')
3347 {
3348 imm_expr.X_op = O_constant;
3349 if (byte_order == LITTLE_ENDIAN)
3350 imm_expr.X_add_number =
3351 (((((((int) temp[3] << 8)
3352 | temp[2]) << 8)
3353 | temp[1]) << 8)
3354 | temp[0]);
3355 else
3356 imm_expr.X_add_number =
3357 (((((((int) temp[0] << 8)
3358 | temp[1]) << 8)
3359 | temp[2]) << 8)
3360 | temp[3]);
3361 }
3362 else
3363 {
3364 /* Switch to the right section. */
3365 seg = now_seg;
3366 subseg = now_subseg;
3367 switch (*args)
3368 {
3369 case 'F':
3370 subseg_new (".rdata", (subsegT) 0);
3371 break;
3372 case 'L':
3373 subseg_new (".lit8", (subsegT) 0);
3374 break;
3375 case 'l':
3376 subseg_new (".lit4", (subsegT) 0);
3377 break;
3378 }
3379 if (seg == now_seg)
3380 as_bad ("Can't use floating point insn in this section");
3381
3382 /* Set the argument to the current address in the
6e8dda9c 3383 section. */
19ed8960
ILT		 3384 offset_expr.X_op = O_symbol;
3385 offset_expr.X_add_symbol =
3386 symbol_new ("L0\001", now_seg,
3387 (valueT) frag_now_fix (), frag_now);
3388 offset_expr.X_add_number = 0;
3389
3390 /* Put the floating point number into the section. */
604633ae 3391 p = frag_more ((int) length);
19ed8960
ILT		 3392 memcpy (p, temp, length);
3393
3394 /* Switch back to the original section. */
3395 subseg_set (seg, subseg);
3396 }
3397 }
670a50eb
ILT		 3398 continue;
3399
3400 case 'i': /* 16 bit unsigned immediate */
3401 case 'j': /* 16 bit signed immediate */
3402 imm_reloc = BFD_RELOC_LO16;
3403 c = my_getSmallExpression (&imm_expr, s);
3404 if (c)
3405 {
3406 if (c != 'l')
3407 {
5ac34ac3 3408 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 3409 imm_expr.X_add_number =
3410 (imm_expr.X_add_number >> 16) & 0xffff;
3411 else if (c == 'h')
3412 imm_reloc = BFD_RELOC_HI16_S;
3413 else
3414 imm_reloc = BFD_RELOC_HI16;
3d3c5039 3415 }
670a50eb
ILT		 3416 }
3417 else
3418 check_absolute_expr (ip, &imm_expr);
3419 if (*args == 'i')
3420 {
6e8dda9c
ILT		 3421 if (imm_expr.X_add_number < 0
3422 || imm_expr.X_add_number >= 0x10000)
99c24539
ILT		 3423 {
3424 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3425 !strcmp (insn->name, insn[1].name))
3426 break;
3427 as_bad ("16 bit expression not in range 0..65535");
3428 }
670a50eb
ILT		 3429 }
3430 else
3431 {
6e8dda9c
ILT		 3432 if (imm_expr.X_add_number < -0x8000 ||
3433 imm_expr.X_add_number >= 0x8000)
99c24539
ILT		 3434 {
3435 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3436 !strcmp (insn->name, insn[1].name))
3437 break;
3438 as_bad ("16 bit expression not in range -32768..32767");
3439 }
3d3c5039 3440 }
670a50eb
ILT		 3441 s = expr_end;
3442 continue;
3443
3444 case 'o': /* 16 bit offset */
3445 c = my_getSmallExpression (&offset_expr, s);
3446 /*
3447 * If this value won't fit into a 16 bit offset, then
3448 * go find a macro that will generate the 32 bit offset
3449 * code pattern.
3450 */
6e8dda9c
ILT		 3451 if (offset_expr.X_op != O_constant
3452 || offset_expr.X_add_number >= 0x8000
3453 || offset_expr.X_add_number < -0x8000)
670a50eb 3454 break;
3d3c5039 3455
670a50eb
ILT		 3456 offset_reloc = BFD_RELOC_LO16;
3457 if (c == 'h' || c == 'H')
6e8dda9c
ILT		 3458 {
3459 assert (offset_expr.X_op == O_constant);
3460 offset_expr.X_add_number =
3461 (offset_expr.X_add_number >> 16) & 0xffff;
3462 }
670a50eb
ILT		 3463 s = expr_end;
3464 continue;
3465
3466 case 'p': /* pc relative offset */
3467 offset_reloc = BFD_RELOC_16_PCREL_S2;
3468 my_getExpression (&offset_expr, s);
3469 s = expr_end;
3470 continue;
3471
3472 case 'u': /* upper 16 bits */
3473 c = my_getSmallExpression (&imm_expr, s);
6e8dda9c
ILT		 3474 if (imm_expr.X_op != O_constant
3475 || imm_expr.X_add_number < 0
3476 || imm_expr.X_add_number >= 0x10000)
670a50eb
ILT		 3477 as_bad ("lui expression not in range 0..65535");
3478 imm_reloc = BFD_RELOC_LO16;
3479 if (c)
3480 {
3481 if (c != 'l')
3482 {
5ac34ac3 3483 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 3484 imm_expr.X_add_number =
3485 (imm_expr.X_add_number >> 16) & 0xffff;
3486 else if (c == 'h')
3487 imm_reloc = BFD_RELOC_HI16_S;
3488 else
3489 imm_reloc = BFD_RELOC_HI16;
3d3c5039
ILT		 3490 }
3491 }
670a50eb
ILT		 3492 s = expr_end;
3493 continue;
3d3c5039 3494
670a50eb
ILT		 3495 case 'a': /* 26 bit address */
3496 my_getExpression (&offset_expr, s);
3497 s = expr_end;
3498 offset_reloc = BFD_RELOC_MIPS_JMP;
3499 continue;
3d3c5039
ILT		 3500
3501 default:
670a50eb
ILT		 3502 fprintf (stderr, "bad char = '%c'\n", *args);
3503 internalError ();
3d3c5039 3504 }
670a50eb 3505 break;
3d3c5039 3506 }
670a50eb
ILT		 3507 /* Args don't match. */
3508 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3509 !strcmp (insn->name, insn[1].name))
3510 {
3511 ++insn;
3512 s = argsStart;
3513 continue;
3d3c5039 3514 }
670a50eb
ILT		 3515 insn_error = "ERROR: Illegal operands";
3516 return;
3d3c5039
ILT		 3517 }
3518}
3519
3520#define LP '('
3521#define RP ')'
3522
3523static int
3524my_getSmallExpression (ep, str)
670a50eb
ILT		 3525 expressionS *ep;
3526 char *str;
3d3c5039 3527{
670a50eb
ILT		 3528 char *sp;
3529 int c = 0;
3530
3531 if (*str == ' ')
3532 str++;
3533 if (*str == LP
3534 || (*str == '%' &&
3535 ((str[1] == 'h' && str[2] == 'i')
3536 || (str[1] == 'H' && str[2] == 'I')
3537 || (str[1] == 'l' && str[2] == 'o'))
3538 && str[3] == LP))
3539 {
3540 if (*str == LP)
3541 c = 0;
3542 else
3543 {
3544 c = str[1];
3545 str += 3;
3546 }
3547
3548 /*
3549 * A small expression may be followed by a base register.
3550 * Scan to the end of this operand, and then back over a possible
3551 * base register. Then scan the small expression up to that
3552 * point. (Based on code in sparc.c...)
3553 */
3554 for (sp = str; *sp && *sp != ','; sp++)
3555 ;
3556 if (sp - 4 >= str && sp[-1] == RP)
3557 {
3558 if (isdigit (sp[-2]))
3559 {
3560 for (sp -= 3; sp >= str && isdigit (*sp); sp--)
3561 ;
3562 if (*sp == '$' && sp > str && sp[-1] == LP)
3563 {
3564 sp--;
3565 goto do_it;
3d3c5039 3566 }
670a50eb
ILT		 3567 }
3568 else if (sp - 5 >= str
3569 && sp[-5] == LP
3570 && sp[-4] == '$'
3571 && ((sp[-3] == 'f' && sp[-2] == 'p')
3572 || (sp[-3] == 's' && sp[-2] == 'p')
3573 || (sp[-3] == 'g' && sp[-2] == 'p')
3574 || (sp[-3] == 'a' && sp[-2] == 't')))
3575 {
3576 sp -= 5;
3d3c5039 3577 do_it:
670a50eb
ILT		 3578 if (sp == str)
3579 {
3580 /* no expression means zero offset */
3581 if (c)
3582 {
3583 /* %xx(reg) is an error */
5ac34ac3 3584 ep->X_op = O_absent;
670a50eb 3585 expr_end = str - 3;
3d3c5039 3586 }
670a50eb
ILT		 3587 else
3588 {
5ac34ac3 3589 ep->X_op = O_absent;
670a50eb
ILT		 3590 expr_end = sp;
3591 }
3592 ep->X_add_symbol = NULL;
5ac34ac3 3593 ep->X_op_symbol = NULL;
670a50eb
ILT		 3594 ep->X_add_number = 0;
3595 }
3596 else
3597 {
3598 *sp = '\0';
3599 my_getExpression (ep, str);
3600 *sp = LP;
3d3c5039 3601 }
670a50eb 3602 return c;
3d3c5039
ILT		 3603 }
3604 }
3605 }
670a50eb
ILT		 3606 my_getExpression (ep, str);
3607 return c; /* => %hi or %lo encountered */
3d3c5039
ILT		 3608}
3609
3610static void
3611my_getExpression (ep, str)
670a50eb
ILT		 3612 expressionS *ep;
3613 char *str;
3d3c5039 3614{
670a50eb 3615 char *save_in;
670a50eb
ILT		 3616
3617 save_in = input_line_pointer;
3618 input_line_pointer = str;
5ac34ac3 3619 expression (ep);
670a50eb
ILT		 3620 expr_end = input_line_pointer;
3621 input_line_pointer = save_in;
3d3c5039
ILT		 3622}
3623
becfe05e
ILT		 3624/* Turn a string in input_line_pointer into a floating point constant
3625 of type type, and store the appropriate bytes in *litP. The number
3626 of LITTLENUMS emitted is stored in *sizeP . An error message is
3627 returned, or NULL on OK. */
3628
3d3c5039 3629char *
670a50eb 3630md_atof (type, litP, sizeP)
becfe05e 3631 int type;
3d3c5039
ILT		 3632 char *litP;
3633 int *sizeP;
3634{
becfe05e
ILT		 3635 int prec;
3636 LITTLENUM_TYPE words[4];
3637 char *t;
3638 int i;
3639
3640 switch (type)
3641 {
3642 case 'f':
3643 prec = 2;
3644 break;
3645
3646 case 'd':
3647 prec = 4;
3648 break;
3649
3650 default:
3651 *sizeP = 0;
3652 return "bad call to md_atof";
3653 }
3654
3655 t = atof_ieee (input_line_pointer, type, words);
3656 if (t)
3657 input_line_pointer = t;
3658
3659 *sizeP = prec * 2;
3660
3661 if (byte_order == LITTLE_ENDIAN)
3662 {
3663 for (i = prec - 1; i >= 0; i--)
3664 {
3665 md_number_to_chars (litP, (valueT) words[i], 2);
3666 litP += 2;
3667 }
3668 }
3669 else
3670 {
3671 for (i = 0; i < prec; i++)
3672 {
3673 md_number_to_chars (litP, (valueT) words[i], 2);
3674 litP += 2;
3675 }
3676 }
3677
670a50eb 3678 return NULL;
3d3c5039
ILT		 3679}
3680
3681void
3682md_number_to_chars (buf, val, n)
3683 char *buf;
918692a5 3684 valueT val;
3d3c5039
ILT		 3685 int n;
3686{
670a50eb
ILT		 3687 switch (byte_order)
3688 {
3d3c5039 3689 case LITTLE_ENDIAN:
670a50eb
ILT		 3690 switch (n)
3691 {
6e8dda9c
ILT		 3692 case 8:
3693 *buf++ = val;
3694 val >>= 8;
3695 *buf++ = val;
3696 val >>= 8;
3697 *buf++ = val;
3698 val >>= 8;
3699 *buf++ = val;
3700 val >>= 8;
3701 /* FALLTHROUGH */
3d3c5039 3702 case 4:
670a50eb 3703 *buf++ = val;
6e8dda9c
ILT		 3704 val >>= 8;
3705 *buf++ = val;
3706 val >>= 8;
3707 /* FALLTHROUGH */
670a50eb
ILT		 3708 case 2:
3709 *buf++ = val;
6e8dda9c
ILT		 3710 val >>= 8;
3711 /* FALLTHROUGH */
3d3c5039 3712 case 1:
670a50eb
ILT		 3713 *buf = val;
3714 return;
3d3c5039
ILT		 3715
3716 default:
670a50eb 3717 internalError ();
3d3c5039
ILT		 3718 }
3719
3720 case BIG_ENDIAN:
670a50eb
ILT		 3721 switch (n)
3722 {
6e8dda9c
ILT		 3723 case 8:
3724 {
3725 valueT hi;
3726
3727 hi = val;
3728 hi >>= 16;
3729 hi >>= 16;
3730 md_number_to_chars (buf, hi, 4);
3731 buf += 4;
3732 }
3733 /* FALLTHROUGH */
3d3c5039 3734 case 4:
670a50eb
ILT		 3735 *buf++ = val >> 24;
3736 *buf++ = val >> 16;
6e8dda9c 3737 /* FALLTHROUGH */
670a50eb
ILT		 3738 case 2:
3739 *buf++ = val >> 8;
6e8dda9c 3740 /* FALLTHROUGH */
3d3c5039 3741 case 1:
670a50eb
ILT		 3742 *buf = val;
3743 return;
3d3c5039
ILT		 3744
3745 default:
670a50eb 3746 internalError ();
3d3c5039
ILT		 3747 }
3748
3749 default:
670a50eb 3750 internalError ();
3d3c5039
ILT		 3751 }
3752}
3753
3754int
3755md_parse_option (argP, cntP, vecP)
3756 char **argP;
3757 int *cntP;
3758 char ***vecP;
3759{
670a50eb 3760 /* Accept -nocpp but ignore it. */
8358c818 3761 if (strcmp (*argP, "nocpp") == 0)
670a50eb
ILT		 3762 {
3763 *argP += 5;
3764 return 1;
3765 }
3766
3767 if (strcmp (*argP, "EL") == 0
3768 || strcmp (*argP, "EB") == 0)
3769 {
3770 /* FIXME: This breaks -L -EL. */
3771 flagseen['L'] = 0;
3772 *argP = "";
3773 return 1;
3774 }
3775
4e95866e
ILT		 3776 if (**argP == 'O')
3777 {
0aa07269
ILT		 3778 if ((*argP)[1] == '0')
3779 mips_optimize = 1;
3780 else
3781 mips_optimize = 2;
3782 return 1;
3783 }
3784
3785 if (**argP == 'g')
3786 {
3787 if ((*argP)[1] == '\0' || (*argP)[1] == '2')
3788 mips_optimize = 0;
4e95866e
ILT		 3789 return 1;
3790 }
3791
8358c818
ILT		 3792 if (strncmp (*argP, "mips", 4) == 0)
3793 {
3794 mips_isa = atol (*argP + 4);
3795 if (mips_isa == 0)
3796 mips_isa = 1;
3797 else if (mips_isa < 1 || mips_isa > 3)
3798 {
3799 as_bad ("-mips%d not supported", mips_isa);
3800 mips_isa = 1;
3801 }
3802 *argP = "";
3803 return 1;
3804 }
3805
3806 if (strncmp (*argP, "mcpu=", 5) == 0)
3807 {
3808 char *p;
3809
3810 /* Identify the processor type */
3811 p = *argP + 5;
3812 if (strcmp (p, "default") == 0
3813 || strcmp (p, "DEFAULT") == 0)
3814 mips_isa = -1;
3815 else
3816 {
3817 if (*p == 'r' || *p == 'R')
3818 p++;
3819
3820 mips_isa = -1;
3821 switch (*p)
3822 {
3823 case '2':
3824 if (strcmp (p, "2000") == 0
3825 || strcmp (p, "2k") == 0
3826 || strcmp (p, "2K") == 0)
3827 mips_isa = 1;
3828 break;
3829
3830 case '3':
3831 if (strcmp (p, "3000") == 0
3832 || strcmp (p, "3k") == 0
3833 || strcmp (p, "3K") == 0)
3834 mips_isa = 1;
3835 break;
3836
3837 case '4':
3838 if (strcmp (p, "4000") == 0
3839 || strcmp (p, "4k") == 0
3840 || strcmp (p, "4K") == 0)
3841 mips_isa = 3;
3842 break;
3843
3844 case '6':
3845 if (strcmp (p, "6000") == 0
3846 || strcmp (p, "6k") == 0
3847 || strcmp (p, "6K") == 0)
3848 mips_isa = 2;
3849 break;
3850 }
3851
3852 if (mips_isa == -1)
3853 {
3854 as_bad ("bad value (%s) for -mcpu= switch", *argP + 5);
3855 mips_isa = 1;
3856 }
3857 }
3858
3859 *argP = "";
3860 return 1;
3861 }
3862
3863
88225433 3864#ifdef GPOPT
670a50eb
ILT		 3865 if (**argP == 'G')
3866 {
3867 if ((*argP)[1] != '\0')
3868 g_switch_value = atoi (*argP + 1);
3869 else if (*cntP)
3870 {
3871 **vecP = (char *) NULL;
3872 (*cntP)--;
3873 (*vecP)++;
3874 g_switch_value = atoi (**vecP);
3875 }
3876 else
3877 as_warn ("Number expected after -G");
3878 *argP = "";
3879 return 1;
3d3c5039 3880 }
670a50eb 3881#endif
4e95866e 3882
670a50eb 3883 return 1; /* pretend you parsed the character */
3d3c5039
ILT		 3884}
3885
3886long
3887md_pcrel_from (fixP)
3888 fixS *fixP;
3889{
670a50eb
ILT		 3890 /* return the address of the delay slot */
3891 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3d3c5039
ILT		 3892}
3893
abdad6bc
ILT		 3894/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3895 reloc for a cons. We could use the definition there, except that
3896 we want to handle 64 bit relocs specially. */
3897
3898void
3899cons_fix_new_mips (frag, where, nbytes, exp)
3900 fragS *frag;
3901 int where;
3902 unsigned int nbytes;
3903 expressionS *exp;
3904{
3905 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3906 4 byte reloc.
3907 FIXME: There is no way to select anything but 32 bit mode right
3908 now. */
3909 if (nbytes == 8)
3910 {
3911 if (byte_order == BIG_ENDIAN)
3912 where += 4;
3913 nbytes = 4;
3914 }
3915
3916 if (nbytes != 2 && nbytes != 4)
3917 as_bad ("Unsupported reloc size %d", nbytes);
3918
3919 fix_new_exp (frag_now, where, (int) nbytes, exp, 0,
3920 nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32);
3921}
3922
3d3c5039
ILT		 3923int
3924md_apply_fix (fixP, valueP)
3925 fixS *fixP;
918692a5 3926 valueT *valueP;
3d3c5039 3927{
670a50eb
ILT		 3928 unsigned char *buf;
3929 long insn, value;
3d3c5039 3930
670a50eb 3931 assert (fixP->fx_size == 4);
3d3c5039 3932
670a50eb
ILT		 3933 value = *valueP;
3934 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
3d3c5039 3935
670a50eb
ILT		 3936 switch (fixP->fx_r_type)
3937 {
3d3c5039
ILT		 3938 case BFD_RELOC_32:
3939 case BFD_RELOC_MIPS_JMP:
3940 case BFD_RELOC_HI16:
3941 case BFD_RELOC_HI16_S:
3942 case BFD_RELOC_LO16:
670a50eb
ILT		 3943 case BFD_RELOC_MIPS_GPREL:
3944 /* Nothing needed to do. The value comes from the reloc entry */
3945 return 1;
3d3c5039
ILT		 3946
3947 case BFD_RELOC_16_PCREL_S2:
670a50eb
ILT		 3948 /*
3949 * We need to save the bits in the instruction since fixup_segment()
3950 * might be deleting the relocation entry (i.e., a branch within
3951 * the current segment).
3952 */
3953 if (value & 0x3)
58d4951d 3954 as_warn ("Branch to odd address (%lx)", value);
670a50eb
ILT		 3955 value >>= 2;
3956 if ((value & ~0xFFFF) && (value & ~0xFFFF) != (-1 & ~0xFFFF))
3957 as_bad ("Relocation overflow");
3958
3959 /* update old instruction data */
3960 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
3961 switch (byte_order)
3962 {
3d3c5039 3963 case LITTLE_ENDIAN:
670a50eb
ILT		 3964 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
3965 break;
3d3c5039
ILT		 3966
3967 case BIG_ENDIAN:
670a50eb
ILT		 3968 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
3969 break;
3d3c5039
ILT		 3970
3971 default:
670a50eb
ILT		 3972 internalError ();
3973 return 0;
3d3c5039 3974 }
670a50eb 3975 insn |= value & 0xFFFF;
604633ae 3976 md_number_to_chars ((char *) buf, (valueT) insn, 4);
670a50eb 3977 break;
3d3c5039
ILT		 3978
3979 default:
670a50eb 3980 internalError ();
3d3c5039 3981 }
670a50eb 3982 return 1;
3d3c5039
ILT		 3983}
3984
3985#if 0
3986void
670a50eb
ILT		 3987printInsn (oc)
3988 unsigned long oc;
3d3c5039 3989{
670a50eb
ILT		 3990 const struct mips_opcode *p;
3991 int treg, sreg, dreg, shamt;
3992 short imm;
3993 const char *args;
3994 int i;
3d3c5039 3995
670a50eb
ILT		 3996 for (i = 0; i < NUMOPCODES; ++i)
3997 {
3998 p = &mips_opcodes[i];
3999 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
4000 {
4001 printf ("%08lx %s\t", oc, p->name);
4002 treg = (oc >> 16) & 0x1f;
4003 sreg = (oc >> 21) & 0x1f;
4004 dreg = (oc >> 11) & 0x1f;
4005 shamt = (oc >> 6) & 0x1f;
4006 imm = oc;
4007 for (args = p->args;; ++args)
4008 {
4009 switch (*args)
4010 {
3d3c5039 4011 case '\0':
670a50eb
ILT		 4012 printf ("\n");
4013 break;
3d3c5039
ILT		 4014
4015 case ',':
4016 case '(':
4017 case ')':
670a50eb
ILT		 4018 printf ("%c", *args);
4019 continue;
3d3c5039
ILT		 4020
4021 case 'r':
670a50eb
ILT		 4022 assert (treg == sreg);
4023 printf ("$%d,$%d", treg, sreg);
4024 continue;
3d3c5039
ILT		 4025
4026 case 'd':
918692a5 4027 case 'G':
670a50eb
ILT		 4028 printf ("$%d", dreg);
4029 continue;
3d3c5039
ILT		 4030
4031 case 't':
918692a5 4032 case 'E':
670a50eb
ILT		 4033 printf ("$%d", treg);
4034 continue;
3d3c5039
ILT		 4035
4036 case 'b':
4037 case 's':
670a50eb
ILT		 4038 printf ("$%d", sreg);
4039 continue;
3d3c5039
ILT		 4040
4041 case 'a':
670a50eb
ILT		 4042 printf ("0x%08lx", oc & 0x1ffffff);
4043 continue;
3d3c5039
ILT		 4044
4045 case 'i':
4046 case 'j':
4047 case 'o':
4048 case 'u':
670a50eb
ILT		 4049 printf ("%d", imm);
4050 continue;
3d3c5039
ILT		 4051
4052 case '<':
670a50eb
ILT		 4053 printf ("$%d", shamt);
4054 continue;
3d3c5039
ILT		 4055
4056 default:
670a50eb 4057 internalError ();
3d3c5039 4058 }
670a50eb 4059 break;
3d3c5039 4060 }
670a50eb 4061 return;
3d3c5039
ILT		 4062 }
4063 }
670a50eb 4064 printf ("%08lx UNDEFINED\n", oc);
3d3c5039
ILT		 4065}
4066#endif
4067
4068static symbolS *
4069get_symbol ()
4070{
670a50eb
ILT		 4071 int c;
4072 char *name;
4073 symbolS *p;
4074
4075 name = input_line_pointer;
4076 c = get_symbol_end ();
4077 p = (symbolS *) symbol_find_or_make (name);
4078 *input_line_pointer = c;
4079 return p;
3d3c5039
ILT		 4080}
4081
becfe05e
ILT		 4082/* Align the current frag to a given power of two. The MIPS assembler
4083 also automatically adjusts any preceding label. */
4084
4085static void
4086mips_align (to, fill)
4087 int to;
4088 int fill;
4089{
4090 mips_emit_delays ();
4091 frag_align (to, fill);
4092 record_alignment (now_seg, to);
4093 if (insn_label != NULL)
4094 {
4095 assert (S_GET_SEGMENT (insn_label) == now_seg);
4096 insn_label->sy_frag = frag_now;
604633ae 4097 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
1849d646 4098 insn_label = NULL;
becfe05e
ILT		 4099 }
4100}
4101
4102/* Align to a given power of two. .align 0 turns off the automatic
4103 alignment used by the data creating pseudo-ops. */
4104
3d3c5039
ILT		 4105static void
4106s_align (x)
4107 int x;
4108{
670a50eb
ILT		 4109 register int temp;
4110 register long temp_fill;
4111 long max_alignment = 15;
3d3c5039 4112
670a50eb 4113 /*
3d3c5039
ILT		 4114
4115 o Note that the assembler pulls down any immediately preceeding label
4116 to the aligned address.
4117 o It's not documented but auto alignment is reinstated by
4118 a .align pseudo instruction.
4119 o Note also that after auto alignment is turned off the mips assembler
4120 issues an error on attempt to assemble an improperly aligned data item.
4121 We don't.
4122
4123 */
4124
670a50eb
ILT		 4125 temp = get_absolute_expression ();
4126 if (temp > max_alignment)
4127 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
4128 else if (temp < 0)
4129 {
4130 as_warn ("Alignment negative: 0 assumed.");
4131 temp = 0;
4132 }
4133 if (*input_line_pointer == ',')
4134 {
4135 input_line_pointer++;
4136 temp_fill = get_absolute_expression ();
4137 }
4138 else
4139 temp_fill = 0;
4140 if (temp)
4141 {
4142 auto_align = 1;
becfe05e 4143 mips_align (temp, (int) temp_fill);
3d3c5039 4144 }
670a50eb
ILT		 4145 else
4146 {
4147 auto_align = 0;
3d3c5039
ILT		 4148 }
4149
670a50eb 4150 demand_empty_rest_of_line ();
3d3c5039
ILT		 4151}
4152
becfe05e
ILT		 4153/* Handle .ascii and .asciiz. This just calls stringer and forgets
4154 that there was a previous instruction. */
4155
4156static void
4157s_stringer (append_zero)
4158 int append_zero;
4159{
4160 mips_emit_delays ();
1849d646 4161 insn_label = NULL;
becfe05e
ILT		 4162 stringer (append_zero);
4163}
4164
3d3c5039
ILT		 4165static void
4166s_change_sec (sec)
4167 int sec;
4168{
88225433
ILT		 4169#ifdef GPOPT
4170 segT seg;
4171#endif
becfe05e
ILT		 4172
4173 mips_emit_delays ();
670a50eb
ILT		 4174 switch (sec)
4175 {
3d3c5039 4176 case 't':
604633ae 4177 s_text (0);
670a50eb 4178 break;
3d3c5039 4179 case 'd':
604633ae 4180 s_data (0);
670a50eb 4181 break;
3d3c5039 4182 case 'b':
670a50eb 4183 subseg_set (bss_section, (subsegT) get_absolute_expression ());
670a50eb
ILT		 4184 demand_empty_rest_of_line ();
4185 break;
88225433
ILT		 4186
4187 case 'r':
670a50eb 4188#ifdef OBJ_ECOFF
88225433 4189 subseg_new (".rdata", (subsegT) get_absolute_expression ());
becfe05e 4190 demand_empty_rest_of_line ();
670a50eb 4191 break;
88225433
ILT		 4192#else /* ! defined (OBJ_ECOFF) */
4193#ifdef OBJ_ELF
4194 seg = subseg_new (".rodata", (subsegT) get_absolute_expression ());
4195 bfd_set_section_flags (stdoutput, seg,
4196 (SEC_ALLOC
4197 | SEC_LOAD
4198 | SEC_READONLY
4199 | SEC_RELOC
4200 | SEC_DATA));
4201 demand_empty_rest_of_line ();
4202 break;
4203#else /* ! defined (OBJ_ELF) */
4204 s_data (0);
4205 break;
4206#endif /* ! defined (OBJ_ELF) */
4207#endif /* ! defined (OBJ_ECOFF) */
4208
4209 case 's':
4210#ifdef GPOPT
4211 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
4212#ifdef OBJ_ELF
4213 bfd_set_section_flags (stdoutput, seg,
4214 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
4215#endif
4216 demand_empty_rest_of_line ();
4217 break;
4218#else /* ! defined (GPOPT) */
670a50eb 4219 as_bad ("Global pointers not supported; recompile -G 0");
becfe05e 4220 demand_empty_rest_of_line ();
670a50eb 4221 return;
88225433 4222#endif /* ! defined (GPOPT) */
3d3c5039 4223 }
88225433 4224
670a50eb 4225 auto_align = 1;
3d3c5039
ILT		 4226}
4227
4228static void
4229s_cons (log_size)
4230 int log_size;
4231{
becfe05e 4232 mips_emit_delays ();
670a50eb 4233 if (log_size > 0 && auto_align)
becfe05e 4234 mips_align (log_size, 0);
1849d646 4235 insn_label = NULL;
670a50eb 4236 cons (1 << log_size);
3d3c5039
ILT		 4237}
4238
4239static void
4240s_err (x)
4241 int x;
4242{
670a50eb 4243 as_fatal ("Encountered `.err', aborting assembly");
3d3c5039
ILT		 4244}
4245
4246static void
4247s_extern (x)
4248 int x;
4249{
604633ae 4250 valueT size;
670a50eb
ILT		 4251 symbolS *symbolP;
4252
4253 symbolP = get_symbol ();
4254 if (*input_line_pointer == ',')
4255 input_line_pointer++;
5ac34ac3 4256 size = get_absolute_expression ();
670a50eb
ILT		 4257 S_SET_VALUE (symbolP, size);
4258 S_SET_EXTERNAL (symbolP);
4259
4260#ifdef OBJ_ECOFF
4261 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4262 so we use an additional ECOFF specific field. */
4263 symbolP->ecoff_undefined = 1;
4264#endif
3d3c5039
ILT		 4265}
4266
4267static void
becfe05e
ILT		 4268s_float_cons (type)
4269 int type;
3d3c5039 4270{
becfe05e 4271 mips_emit_delays ();
670a50eb
ILT		 4272
4273 if (auto_align)
becfe05e
ILT		 4274 if (type == 'd')
4275 mips_align (3, 0);
670a50eb 4276 else
becfe05e 4277 mips_align (2, 0);
670a50eb 4278
1849d646
ILT		 4279 insn_label = NULL;
4280
becfe05e 4281 float_cons (type);
3d3c5039
ILT		 4282}
4283
4284static void
4285s_option (x)
4286 int x;
4287{
dd3f1f76
ILT		 4288 char *opt;
4289 char c;
4290
4291 opt = input_line_pointer;
4292 c = get_symbol_end ();
4293
4294 /* FIXME: What do these options mean? */
4295 if (*opt == 'O')
4296 ;
4297 else if (strncmp (opt, "pic", 3) == 0)
4298 ;
4299 else
4300 as_warn ("Unrecognized option \"%s\"", opt);
4301
4302 *input_line_pointer = c;
670a50eb 4303 demand_empty_rest_of_line ();
3d3c5039
ILT		 4304}
4305
4306static void
4307s_mipsset (x)
4308 int x;
4309{
670a50eb
ILT		 4310 char *name = input_line_pointer, ch;
4311
4312 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4313 input_line_pointer++;
4314 ch = *input_line_pointer;
4315 *input_line_pointer = '\0';
4316
4317 if (strcmp (name, "reorder") == 0)
4318 {
4e95866e
ILT		 4319 if (mips_noreorder)
4320 {
4321 prev_insn_unreordered = 1;
4322 prev_prev_insn_unreordered = 1;
4323 }
670a50eb
ILT		 4324 mips_noreorder = 0;
4325 }
4326 else if (strcmp (name, "noreorder") == 0)
4327 {
becfe05e 4328 mips_emit_delays ();
670a50eb
ILT		 4329 mips_noreorder = 1;
4330 }
4331 else if (strcmp (name, "at") == 0)
4332 {
4333 mips_noat = 0;
4334 }
4335 else if (strcmp (name, "noat") == 0)
4336 {
4337 mips_noat = 1;
3d3c5039 4338 }
670a50eb
ILT		 4339 else if (strcmp (name, "macro") == 0)
4340 {
4341 mips_warn_about_macros = 0;
4342 }
4343 else if (strcmp (name, "nomacro") == 0)
4344 {
4345 if (mips_noreorder == 0)
4346 as_bad ("`noreorder' must be set before `nomacro'");
4347 mips_warn_about_macros = 1;
4348 }
4349 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
4350 {
4351 mips_nomove = 0;
4352 }
4353 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
4354 {
4355 mips_nomove = 1;
4356 }
4357 else if (strcmp (name, "bopt") == 0)
4358 {
4359 mips_nobopt = 0;
4360 }
4361 else if (strcmp (name, "nobopt") == 0)
4362 {
4363 mips_nobopt = 1;
4364 }
4365 else
4366 {
4367 as_warn ("Tried to set unrecognized symbol: %s\n", name);
4368 }
4369 *input_line_pointer = ch;
4370 demand_empty_rest_of_line ();
3d3c5039
ILT		 4371}
4372
becfe05e
ILT		 4373/* The same as the usual .space directive, except that we have to
4374 forget about any previous instruction. */
4375
4376static void
4377s_mips_space (param)
4378 int param;
4379{
4380 mips_emit_delays ();
1849d646 4381 insn_label = NULL;
becfe05e
ILT		 4382 s_space (param);
4383}
4384
3d3c5039
ILT		 4385int
4386tc_get_register ()
4387{
4388 int reg;
4389
4390 SKIP_WHITESPACE ();
4391 if (*input_line_pointer++ != '$')
4392 {
4393 as_warn ("expected `$'");
4394 return 0;
4395 }
4396 if (isdigit ((unsigned char) *input_line_pointer))
4397 {
4398 reg = get_absolute_expression ();
4399 if (reg < 0 || reg >= 32)
4400 {
4401 as_warn ("Bad register number");
4402 reg = 0;
4403 }
4404 }
4405 else
4406 {
4407 if (strncmp (input_line_pointer, "fp", 2) == 0)
4408 reg = 30;
4409 else if (strncmp (input_line_pointer, "sp", 2) == 0)
4410 reg = 29;
4411 else if (strncmp (input_line_pointer, "gp", 2) == 0)
4412 reg = 28;
4413 else if (strncmp (input_line_pointer, "at", 2) == 0)
4414 reg = 1;
4415 else
4416 {
4417 as_warn ("Unrecognized register name");
4418 return 0;
4419 }
4420 input_line_pointer += 2;
4421 }
4422 return reg;
4423}
4424
4425/*
4426 * Translate internal representation of relocation info to BFD target format.
4427 */
4428arelent *
4429tc_gen_reloc (section, fixp)
4430 asection *section;
4431 fixS *fixp;
4432{
4433 arelent *reloc;
4434
4435 reloc = (arelent *) xmalloc (sizeof (arelent));
4436 assert (reloc != 0);
4437
4438 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
4439 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4440 if (fixp->fx_pcrel == 0)
4441 reloc->addend = fixp->fx_addnumber;
4442 else
4443#ifdef OBJ_ELF
4444 reloc->addend = 0;
4445#else
670a50eb 4446 reloc->addend = -reloc->address;
3d3c5039
ILT		 4447#endif
4448 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
4449 assert (reloc->howto != 0);
4450
3d3c5039
ILT		 4451 return reloc;
4452}
4453
4454/* should never be called */
918692a5 4455valueT
670a50eb
ILT		 4456md_section_align (seg, addr)
4457 asection *seg;
918692a5 4458 valueT addr;
3d3c5039 4459{
670a50eb 4460 int align = bfd_get_section_alignment (stdoutput, seg);
3d3c5039 4461
670a50eb 4462 return ((addr + (1 << align) - 1) & (-1 << align));
3d3c5039
ILT		 4463}
4464
4465int
670a50eb
ILT		 4466md_estimate_size_before_relax (fragP, segtype)
4467 fragS *fragP;
4468 asection *segtype;
3d3c5039 4469{
670a50eb
ILT		 4470 as_fatal ("md_estimate_size_before_relax");
4471 return (1);
4472} /* md_estimate_size_before_relax() */
becfe05e
ILT		 4473
4474/* This function is called whenever a label is defined. It is used
4475 when handling branch delays; if a branch has a label, we assume we
4476 can not move it. */
4477
4478void
4479mips_define_label (sym)
4480 symbolS *sym;
4481{
4482 insn_label = sym;
4483}
3d3c5039 4484\f
f2a663d3
ILT		 4485#ifdef OBJ_ELF
4486
4487/* Write out the .reginfo section for a MIPS ELF file. */
4488
4489void
4490mips_elf_final_processing ()
4491{
4492 Elf32_RegInfo s;
4493
4494 s.ri_gprmask = mips_gprmask;
4495 s.ri_cprmask[0] = mips_cprmask[0];
4496 s.ri_cprmask[1] = mips_cprmask[1];
4497 s.ri_cprmask[2] = mips_cprmask[2];
4498 s.ri_cprmask[3] = mips_cprmask[3];
4499 /* The gp_value field is set by the MIPS ELF backend. */
4500
4501 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
4502 ((Elf32_External_RegInfo *)
4503 mips_regmask_frag));
4504}
4505
4506#endif /* OBJ_ELF */
4507\f
3d3c5039
ILT		 4508#ifndef OBJ_ECOFF
4509
4510/* These functions should really be defined by the object file format,
4511 since they are related to debugging information. However, this
4512 code has to work for the a.out format, which does not define them,
4513 so we provide simple versions here. These don't actually generate
4514 any debugging information, but they do simple checking and someday
4515 somebody may make them useful. */
4516
670a50eb
ILT		 4517typedef struct loc
4518{
4519 struct loc *loc_next;
4520 unsigned long loc_fileno;
4521 unsigned long loc_lineno;
4522 unsigned long loc_offset;
4523 unsigned short loc_delta;
4524 unsigned short loc_count;
3d3c5039 4525#if 0
670a50eb 4526 fragS *loc_frag;
3d3c5039 4527#endif
670a50eb
ILT		 4528}
4529locS;
3d3c5039 4530
670a50eb
ILT		 4531typedef struct proc
4532 {
3d3c5039
ILT		 4533 struct proc *proc_next;
4534 struct symbol *proc_isym;
4535 struct symbol *proc_end;
4536 unsigned long proc_reg_mask;
4537 unsigned long proc_reg_offset;
4538 unsigned long proc_fpreg_mask;
4539 unsigned long proc_fpreg_offset;
4540 unsigned long proc_frameoffset;
4541 unsigned long proc_framereg;
4542 unsigned long proc_pcreg;
4543 locS *proc_iline;
4544 struct file *proc_file;
4545 int proc_index;
670a50eb
ILT		 4546 }
4547procS;
3d3c5039 4548
670a50eb
ILT		 4549typedef struct file
4550 {
3d3c5039
ILT		 4551 struct file *file_next;
4552 unsigned long file_fileno;
4553 struct symbol *file_symbol;
4554 struct symbol *file_end;
4555 struct proc *file_proc;
4556 int file_numprocs;
670a50eb
ILT		 4557 }
4558fileS;
3d3c5039
ILT		 4559
4560static struct obstack proc_frags;
4561static procS *proc_lastP;
4562static procS *proc_rootP;
4563static int numprocs;
4564
4565static void
4566md_obj_begin ()
4567{
670a50eb 4568 obstack_begin (&proc_frags, 0x2000);
3d3c5039
ILT		 4569}
4570
4571static void
4572md_obj_end ()
4573{
4574 /* check for premature end, nesting errors, etc */
4575 if (proc_lastP && proc_lastP->proc_end == NULL)
670a50eb 4576 as_warn ("missing `.end' at end of assembly");
3d3c5039
ILT		 4577}
4578
4579extern char hex_value[];
4580
4581static long
4582get_number ()
4583{
670a50eb
ILT		 4584 int negative = 0;
4585 long val = 0;
3d3c5039 4586
670a50eb
ILT		 4587 if (*input_line_pointer == '-')
4588 {
4589 ++input_line_pointer;
4590 negative = 1;
3d3c5039 4591 }
670a50eb
ILT		 4592 if (!isdigit (*input_line_pointer))
4593 as_bad ("Expected simple number.");
4594 if (input_line_pointer[0] == '0')
4595 {
4596 if (input_line_pointer[1] == 'x')
4597 {
4598 input_line_pointer += 2;
4599 while (isxdigit (*input_line_pointer))
4600 {
4601 val <<= 4;
4602 val |= hex_value[(int) *input_line_pointer++];
3d3c5039 4603 }
670a50eb
ILT		 4604 return negative ? -val : val;
4605 }
4606 else
4607 {
4608 ++input_line_pointer;
4609 while (isdigit (*input_line_pointer))
4610 {
4611 val <<= 3;
4612 val |= *input_line_pointer++ - '0';
3d3c5039 4613 }
670a50eb 4614 return negative ? -val : val;
3d3c5039
ILT		 4615 }
4616 }
670a50eb
ILT		 4617 if (!isdigit (*input_line_pointer))
4618 {
4619 printf (" *input_line_pointer == '%c' 0x%02x\n",
4620 *input_line_pointer, *input_line_pointer);
4621 as_warn ("Invalid number");
4622 return -1;
3d3c5039 4623 }
670a50eb
ILT		 4624 while (isdigit (*input_line_pointer))
4625 {
4626 val *= 10;
4627 val += *input_line_pointer++ - '0';
3d3c5039 4628 }
670a50eb 4629 return negative ? -val : val;
3d3c5039
ILT		 4630}
4631
4632/* The .file directive; just like the usual .file directive, but there
4633 is an initial number which is the ECOFF file index. */
4634
4635static void
4636s_file (x)
4637 int x;
4638{
670a50eb 4639 int line;
3d3c5039 4640
670a50eb 4641 line = get_number ();
9a7d824a 4642 s_app_file (0);
3d3c5039
ILT		 4643}
4644
4645
4646/* The .end directive. */
4647
4648static void
4649s_mipsend (x)
4650 int x;
4651{
670a50eb
ILT		 4652 symbolS *p;
4653
4654 if (!is_end_of_line[(unsigned char) *input_line_pointer])
4655 {
4656 p = get_symbol ();
4657 demand_empty_rest_of_line ();
4658 }
4659 else
4660 p = NULL;
4661 if (now_seg != text_section)
4662 as_warn (".end not in text section");
4663 if (!proc_lastP)
4664 {
4665 as_warn (".end and no .ent seen yet.");
4666 return;
3d3c5039
ILT		 4667 }
4668
670a50eb
ILT		 4669 if (p != NULL)
4670 {
4671 assert (S_GET_NAME (p));
4672 if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym)))
4673 as_warn (".end symbol does not match .ent symbol.");
3d3c5039
ILT		 4674 }
4675
670a50eb 4676 proc_lastP->proc_end = (symbolS *) 1;
3d3c5039
ILT		 4677}
4678
4679/* The .aent and .ent directives. */
4680
4681static void
4682s_ent (aent)
4683 int aent;
4684{
670a50eb
ILT		 4685 int number = 0;
4686 procS *procP;
4687 symbolS *symbolP;
4688
4689 symbolP = get_symbol ();
4690 if (*input_line_pointer == ',')
4691 input_line_pointer++;
dd3f1f76 4692 SKIP_WHITESPACE ();
670a50eb
ILT		 4693 if (isdigit (*input_line_pointer) || *input_line_pointer == '-')
4694 number = get_number ();
4695 if (now_seg != text_section)
4696 as_warn (".ent or .aent not in text section.");
4697
4698 if (!aent && proc_lastP && proc_lastP->proc_end == NULL)
4699 as_warn ("missing `.end'");
4700
4701 if (!aent)
4702 {
4703 procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP));
4704 procP->proc_isym = symbolP;
4705 procP->proc_reg_mask = 0;
4706 procP->proc_reg_offset = 0;
4707 procP->proc_fpreg_mask = 0;
4708 procP->proc_fpreg_offset = 0;
4709 procP->proc_frameoffset = 0;
4710 procP->proc_framereg = 0;
4711 procP->proc_pcreg = 0;
4712 procP->proc_end = NULL;
4713 procP->proc_next = NULL;
4714 if (proc_lastP)
4715 proc_lastP->proc_next = procP;
4716 else
4717 proc_rootP = procP;
4718 proc_lastP = procP;
4719 numprocs++;
3d3c5039 4720 }
670a50eb 4721 demand_empty_rest_of_line ();
3d3c5039
ILT		 4722}
4723
4724/* The .frame directive. */
4725
88225433 4726#if 0
3d3c5039
ILT		 4727static void
4728s_frame (x)
670a50eb 4729 int x;
3d3c5039 4730{
670a50eb
ILT		 4731 char str[100];
4732 symbolS *symP;
4733 int frame_reg;
4734 int frame_off;
4735 int pcreg;
4736
4737 frame_reg = tc_get_register ();
4738 if (*input_line_pointer == ',')
4739 input_line_pointer++;
5ac34ac3 4740 frame_off = get_absolute_expression ();
670a50eb
ILT		 4741 if (*input_line_pointer == ',')
4742 input_line_pointer++;
4743 pcreg = tc_get_register ();
4744
4745 /* bob third eye */
4746 assert (proc_rootP);
4747 proc_rootP->proc_framereg = frame_reg;
4748 proc_rootP->proc_frameoffset = frame_off;
4749 proc_rootP->proc_pcreg = pcreg;
4750 /* bob macho .frame */
4751
4752 /* We don't have to write out a frame stab for unoptimized code. */
4753 if (!(frame_reg == 30 && frame_off == 0))
4754 {
4755 if (!proc_lastP)
4756 as_warn ("No .ent for .frame to use.");
4757 (void) sprintf (str, "R%d;%d", frame_reg, frame_off);
4758 symP = symbol_new (str, N_VFP, 0, frag_now);
4759 S_SET_TYPE (symP, N_RMASK);
4760 S_SET_OTHER (symP, 0);
4761 S_SET_DESC (symP, 0);
4762 symP->sy_forward = proc_lastP->proc_isym;
4763 /* bob perhaps I should have used pseudo set */
3d3c5039 4764 }
670a50eb 4765 demand_empty_rest_of_line ();
3d3c5039 4766}
88225433 4767#endif
3d3c5039
ILT		 4768
4769/* The .fmask and .mask directives. */
4770
88225433 4771#if 0
3d3c5039
ILT		 4772static void
4773s_mask (reg_type)
4774 char reg_type;
4775{
670a50eb
ILT		 4776 char str[100], *strP;
4777 symbolS *symP;
4778 int i;
4779 unsigned int mask;
4780 int off;
4781
4782 mask = get_number ();
4783 if (*input_line_pointer == ',')
4784 input_line_pointer++;
4785 off = get_absolute_expression ();
4786
4787 /* bob only for coff */
4788 assert (proc_rootP);
4789 if (reg_type == 'F')
4790 {
4791 proc_rootP->proc_fpreg_mask = mask;
4792 proc_rootP->proc_fpreg_offset = off;
3d3c5039 4793 }
670a50eb
ILT		 4794 else
4795 {
4796 proc_rootP->proc_reg_mask = mask;
4797 proc_rootP->proc_reg_offset = off;
4798 }
4799
4800 /* bob macho .mask + .fmask */
3d3c5039 4801
670a50eb
ILT		 4802 /* We don't have to write out a mask stab if no saved regs. */
4803 if (!(mask == 0))
4804 {
4805 if (!proc_lastP)
4806 as_warn ("No .ent for .mask to use.");
4807 strP = str;
4808 for (i = 0; i < 32; i++)
4809 {
4810 if (mask % 2)
4811 {
4812 sprintf (strP, "%c%d,", reg_type, i);
4813 strP += strlen (strP);
4814 }
3d3c5039 4815 mask /= 2;
670a50eb
ILT		 4816 }
4817 sprintf (strP, ";%d,", off);
4818 symP = symbol_new (str, N_RMASK, 0, frag_now);
4819 S_SET_TYPE (symP, N_RMASK);
4820 S_SET_OTHER (symP, 0);
4821 S_SET_DESC (symP, 0);
4822 symP->sy_forward = proc_lastP->proc_isym;
4823 /* bob perhaps I should have used pseudo set */
3d3c5039 4824 }
3d3c5039 4825}
88225433 4826#endif
3d3c5039
ILT		 4827
4828/* The .loc directive. */
4829
88225433 4830#if 0
3d3c5039
ILT		 4831static void
4832s_loc (x)
4833 int x;
4834{
670a50eb
ILT		 4835 symbolS *symbolP;
4836 int lineno;
4837 int addroff;
3d3c5039 4838
670a50eb 4839 assert (now_seg == text_section);
3d3c5039 4840
670a50eb
ILT		 4841 lineno = get_number ();
4842 addroff = obstack_next_free (&frags) - frag_now->fr_literal;
3d3c5039 4843
670a50eb
ILT		 4844 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
4845 S_SET_TYPE (symbolP, N_SLINE);
4846 S_SET_OTHER (symbolP, 0);
4847 S_SET_DESC (symbolP, lineno);
4848 symbolP->sy_segment = now_seg;
3d3c5039 4849}
88225433 4850#endif
3d3c5039
ILT		 4851
4852#endif /* ! defined (OBJ_ECOFF) */
GDB Binutils - Deliverables
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