Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
148 | /* True if this is a mips16 instruction and if we want the extended | |
149 | form of INSN_MO. */ | |
150 | bfd_boolean use_extend; | |
151 | ||
152 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
153 | unsigned short extend; | |
154 | ||
155 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
156 | a copy of INSN_MO->match with the operands filled in. */ | |
157 | unsigned long insn_opcode; | |
158 | ||
159 | /* The frag that contains the instruction. */ | |
160 | struct frag *frag; | |
161 | ||
162 | /* The offset into FRAG of the first instruction byte. */ | |
163 | long where; | |
164 | ||
165 | /* The relocs associated with the instruction, if any. */ | |
166 | fixS *fixp[3]; | |
167 | ||
a38419a5 RS |
168 | /* True if this entry cannot be moved from its current position. */ |
169 | unsigned int fixed_p : 1; | |
47e39b9d | 170 | |
708587a4 | 171 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
172 | unsigned int noreorder_p : 1; |
173 | ||
2fa15973 RS |
174 | /* True for mips16 instructions that jump to an absolute address. */ |
175 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
176 | |
177 | /* True if this instruction is complete. */ | |
178 | unsigned int complete_p : 1; | |
47e39b9d RS |
179 | }; |
180 | ||
a325df1d TS |
181 | /* The ABI to use. */ |
182 | enum mips_abi_level | |
183 | { | |
184 | NO_ABI = 0, | |
185 | O32_ABI, | |
186 | O64_ABI, | |
187 | N32_ABI, | |
188 | N64_ABI, | |
189 | EABI_ABI | |
190 | }; | |
191 | ||
192 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 193 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 194 | |
143d77c5 EC |
195 | /* Whether or not we have code that can call pic code. */ |
196 | int mips_abicalls = FALSE; | |
197 | ||
aa6975fb ILT |
198 | /* Whether or not we have code which can be put into a shared |
199 | library. */ | |
200 | static bfd_boolean mips_in_shared = TRUE; | |
201 | ||
252b5132 RH |
202 | /* This is the set of options which may be modified by the .set |
203 | pseudo-op. We use a struct so that .set push and .set pop are more | |
204 | reliable. */ | |
205 | ||
e972090a NC |
206 | struct mips_set_options |
207 | { | |
252b5132 RH |
208 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
209 | if it has not been initialized. Changed by `.set mipsN', and the | |
210 | -mipsN command line option, and the default CPU. */ | |
211 | int isa; | |
1f25f5d3 CD |
212 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
213 | if they have not been initialized. Changed by `.set <asename>', by | |
214 | command line options, and based on the default architecture. */ | |
215 | int ase_mips3d; | |
deec1734 | 216 | int ase_mdmx; |
e16bfa71 | 217 | int ase_smartmips; |
74cd071d | 218 | int ase_dsp; |
8b082fb1 | 219 | int ase_dspr2; |
ef2e4d86 | 220 | int ase_mt; |
dec0624d | 221 | int ase_mcu; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
296 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
297 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
298 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
299 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 300 | }; |
252b5132 RH |
301 | |
302 | /* These variables are filled in with the masks of registers used. | |
303 | The object format code reads them and puts them in the appropriate | |
304 | place. */ | |
305 | unsigned long mips_gprmask; | |
306 | unsigned long mips_cprmask[4]; | |
307 | ||
308 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 309 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 310 | |
738f4d98 | 311 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
312 | static int file_ase_mips16; |
313 | ||
3994f87e TS |
314 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
315 | || mips_opts.isa == ISA_MIPS32R2 \ | |
316 | || mips_opts.isa == ISA_MIPS64 \ | |
317 | || mips_opts.isa == ISA_MIPS64R2) | |
318 | ||
df58fc94 RS |
319 | /* True if any microMIPS code was produced. */ |
320 | static int file_ase_micromips; | |
321 | ||
b12dd2e4 CF |
322 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
323 | #ifdef TE_IRIX | |
1180b5a4 | 324 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 325 | #else |
1180b5a4 RS |
326 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
327 | because there's no place for any addend, the only acceptable | |
328 | expression is a bare symbol. */ | |
329 | #define MIPS_JALR_HINT_P(EXPR) \ | |
330 | (!HAVE_IN_PLACE_ADDENDS \ | |
331 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
332 | #endif |
333 | ||
1f25f5d3 CD |
334 | /* True if -mips3d was passed or implied by arguments passed on the |
335 | command line (e.g., by -march). */ | |
336 | static int file_ase_mips3d; | |
337 | ||
deec1734 CD |
338 | /* True if -mdmx was passed or implied by arguments passed on the |
339 | command line (e.g., by -march). */ | |
340 | static int file_ase_mdmx; | |
341 | ||
e16bfa71 TS |
342 | /* True if -msmartmips was passed or implied by arguments passed on the |
343 | command line (e.g., by -march). */ | |
344 | static int file_ase_smartmips; | |
345 | ||
ad3fea08 TS |
346 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
347 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 348 | |
74cd071d CF |
349 | /* True if -mdsp was passed or implied by arguments passed on the |
350 | command line (e.g., by -march). */ | |
351 | static int file_ase_dsp; | |
352 | ||
ad3fea08 TS |
353 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
354 | || mips_opts.isa == ISA_MIPS64R2) | |
355 | ||
65263ce3 TS |
356 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
357 | ||
8b082fb1 TS |
358 | /* True if -mdspr2 was passed or implied by arguments passed on the |
359 | command line (e.g., by -march). */ | |
360 | static int file_ase_dspr2; | |
361 | ||
362 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
363 | || mips_opts.isa == ISA_MIPS64R2) | |
364 | ||
ef2e4d86 CF |
365 | /* True if -mmt was passed or implied by arguments passed on the |
366 | command line (e.g., by -march). */ | |
367 | static int file_ase_mt; | |
368 | ||
ad3fea08 TS |
369 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
370 | || mips_opts.isa == ISA_MIPS64R2) | |
371 | ||
dec0624d MR |
372 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
373 | || mips_opts.isa == ISA_MIPS64R2) | |
374 | ||
ec68c924 | 375 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 376 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 377 | static const char *mips_arch_string; |
ec68c924 EC |
378 | |
379 | /* The argument of the -mtune= flag. The architecture for which we | |
380 | are optimizing. */ | |
381 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 382 | static const char *mips_tune_string; |
ec68c924 | 383 | |
316f5878 | 384 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
385 | static int mips_32bitmode = 0; |
386 | ||
316f5878 RS |
387 | /* True if the given ABI requires 32-bit registers. */ |
388 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
389 | ||
390 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
391 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
392 | ((ABI) == N32_ABI \ | |
393 | || (ABI) == N64_ABI \ | |
316f5878 RS |
394 | || (ABI) == O64_ABI) |
395 | ||
ad3fea08 | 396 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
397 | #define ISA_HAS_64BIT_REGS(ISA) \ |
398 | ((ISA) == ISA_MIPS3 \ | |
399 | || (ISA) == ISA_MIPS4 \ | |
400 | || (ISA) == ISA_MIPS5 \ | |
401 | || (ISA) == ISA_MIPS64 \ | |
402 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 403 | |
ad3fea08 TS |
404 | /* Return true if ISA supports 64 bit wide float registers. */ |
405 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
406 | ((ISA) == ISA_MIPS3 \ | |
407 | || (ISA) == ISA_MIPS4 \ | |
408 | || (ISA) == ISA_MIPS5 \ | |
409 | || (ISA) == ISA_MIPS32R2 \ | |
410 | || (ISA) == ISA_MIPS64 \ | |
411 | || (ISA) == ISA_MIPS64R2) | |
412 | ||
af7ee8bf CD |
413 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
414 | instructions. */ | |
707bfff6 | 415 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
416 | ((ISA) == ISA_MIPS64R2 \ |
417 | || (mips_opts.micromips \ | |
418 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
419 | ) | |
af7ee8bf CD |
420 | |
421 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
422 | instructions. */ | |
707bfff6 TS |
423 | #define ISA_HAS_ROR(ISA) \ |
424 | ((ISA) == ISA_MIPS32R2 \ | |
425 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
426 | || mips_opts.ase_smartmips \ |
427 | || mips_opts.micromips \ | |
428 | ) | |
707bfff6 | 429 | |
7455baf8 TS |
430 | /* Return true if ISA supports single-precision floats in odd registers. */ |
431 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
432 | ((ISA) == ISA_MIPS32 \ | |
433 | || (ISA) == ISA_MIPS32R2 \ | |
434 | || (ISA) == ISA_MIPS64 \ | |
435 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 436 | |
ad3fea08 TS |
437 | /* Return true if ISA supports move to/from high part of a 64-bit |
438 | floating-point register. */ | |
439 | #define ISA_HAS_MXHC1(ISA) \ | |
440 | ((ISA) == ISA_MIPS32R2 \ | |
441 | || (ISA) == ISA_MIPS64R2) | |
442 | ||
e013f690 | 443 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 444 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 445 | |
e013f690 | 446 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 447 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 448 | |
ad3fea08 TS |
449 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
450 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 451 | |
316f5878 | 452 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 453 | |
316f5878 | 454 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 455 | |
3b91255e RS |
456 | /* True if relocations are stored in-place. */ |
457 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
458 | ||
aed1a261 RS |
459 | /* The ABI-derived address size. */ |
460 | #define HAVE_64BIT_ADDRESSES \ | |
461 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
462 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 463 | |
aed1a261 RS |
464 | /* The size of symbolic constants (i.e., expressions of the form |
465 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
466 | #define HAVE_32BIT_SYMBOLS \ | |
467 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
468 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 469 | |
b7c7d6c1 TS |
470 | /* Addresses are loaded in different ways, depending on the address size |
471 | in use. The n32 ABI Documentation also mandates the use of additions | |
472 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 473 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 474 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
475 | |
476 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 477 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
478 | |
479 | #define ADDRESS_LOAD_INSN \ | |
480 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
481 | ||
482 | #define ADDRESS_STORE_INSN \ | |
483 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
484 | ||
a4672219 | 485 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
486 | #define CPU_HAS_MIPS16(cpu) \ |
487 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
488 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 489 | |
2309ddf2 | 490 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
491 | #define CPU_HAS_MICROMIPS(cpu) 0 |
492 | ||
60b63b72 RS |
493 | /* True if CPU has a dror instruction. */ |
494 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
495 | ||
496 | /* True if CPU has a ror instruction. */ | |
497 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
498 | ||
dd3cbb7e NC |
499 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
500 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
501 | ||
b19e8a9b AN |
502 | /* True if CPU does not implement the all the coprocessor insns. For these |
503 | CPUs only those COP insns are accepted that are explicitly marked to be | |
504 | available on the CPU. ISA membership for COP insns is ignored. */ | |
505 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
506 | ||
c8978940 CD |
507 | /* True if mflo and mfhi can be immediately followed by instructions |
508 | which write to the HI and LO registers. | |
509 | ||
510 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
511 | (at least) two instructions between the reads of HI/LO and | |
512 | instructions which write them, and later ISAs do not. Contradicting | |
513 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
514 | the UM for the NEC Vr5000) document needing the instructions between | |
515 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
516 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
517 | earlier-ISA CPUs for which CPU documentation declares that the | |
518 | instructions are really interlocked. */ | |
519 | #define hilo_interlocks \ | |
520 | (mips_opts.isa == ISA_MIPS32 \ | |
521 | || mips_opts.isa == ISA_MIPS32R2 \ | |
522 | || mips_opts.isa == ISA_MIPS64 \ | |
523 | || mips_opts.isa == ISA_MIPS64R2 \ | |
524 | || mips_opts.arch == CPU_R4010 \ | |
525 | || mips_opts.arch == CPU_R10000 \ | |
526 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
527 | || mips_opts.arch == CPU_R14000 \ |
528 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 529 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 530 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 531 | || mips_opts.micromips \ |
c8978940 | 532 | ) |
252b5132 RH |
533 | |
534 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
535 | from the GPRs after they are loaded from memory, and thus does not |
536 | require nops to be inserted. This applies to instructions marked | |
537 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
538 | level I and microMIPS mode instructions are always interlocked. */ |
539 | #define gpr_interlocks \ | |
540 | (mips_opts.isa != ISA_MIPS1 \ | |
541 | || mips_opts.arch == CPU_R3900 \ | |
542 | || mips_opts.micromips \ | |
543 | ) | |
252b5132 | 544 | |
81912461 ILT |
545 | /* Whether the processor uses hardware interlocks to avoid delays |
546 | required by coprocessor instructions, and thus does not require | |
547 | nops to be inserted. This applies to instructions marked | |
548 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
549 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
550 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
551 | levels I, II, and III and microMIPS mode instructions are always |
552 | interlocked. */ | |
bdaaa2e1 | 553 | /* Itbl support may require additional care here. */ |
81912461 ILT |
554 | #define cop_interlocks \ |
555 | ((mips_opts.isa != ISA_MIPS1 \ | |
556 | && mips_opts.isa != ISA_MIPS2 \ | |
557 | && mips_opts.isa != ISA_MIPS3) \ | |
558 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 559 | || mips_opts.micromips \ |
81912461 ILT |
560 | ) |
561 | ||
562 | /* Whether the processor uses hardware interlocks to protect reads | |
563 | from coprocessor registers after they are loaded from memory, and | |
564 | thus does not require nops to be inserted. This applies to | |
565 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
566 | requires at MIPS ISA level I and microMIPS mode instructions are |
567 | always interlocked. */ | |
568 | #define cop_mem_interlocks \ | |
569 | (mips_opts.isa != ISA_MIPS1 \ | |
570 | || mips_opts.micromips \ | |
571 | ) | |
252b5132 | 572 | |
6b76fefe CM |
573 | /* Is this a mfhi or mflo instruction? */ |
574 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
575 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
576 | ||
577 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
578 | or writing the condition code is only possible on the coprocessors and | |
579 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 580 | condition-code flags. */ |
b19e8a9b AN |
581 | #define COP_INSN(PINFO) \ |
582 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
583 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
584 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 585 | |
df58fc94 RS |
586 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
587 | has been selected. This implies, in particular, that addresses of text | |
588 | labels have their LSB set. */ | |
589 | #define HAVE_CODE_COMPRESSION \ | |
590 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
591 | ||
252b5132 RH |
592 | /* MIPS PIC level. */ |
593 | ||
a161fe53 | 594 | enum mips_pic_level mips_pic; |
252b5132 | 595 | |
c9914766 | 596 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 597 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 598 | static int mips_big_got = 0; |
252b5132 RH |
599 | |
600 | /* 1 if trap instructions should used for overflow rather than break | |
601 | instructions. */ | |
c9914766 | 602 | static int mips_trap = 0; |
252b5132 | 603 | |
119d663a | 604 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 605 | by assembling two single width halves into two single width floating |
119d663a NC |
606 | point registers which just happen to alias the double width destination |
607 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 608 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
609 | automatically at assemble time. */ |
610 | static int mips_disable_float_construction; | |
611 | ||
252b5132 RH |
612 | /* Non-zero if any .set noreorder directives were used. */ |
613 | ||
614 | static int mips_any_noreorder; | |
615 | ||
6b76fefe CM |
616 | /* Non-zero if nops should be inserted when the register referenced in |
617 | an mfhi/mflo instruction is read in the next two instructions. */ | |
618 | static int mips_7000_hilo_fix; | |
619 | ||
02ffd3e4 | 620 | /* The size of objects in the small data section. */ |
156c2f8b | 621 | static unsigned int g_switch_value = 8; |
252b5132 RH |
622 | /* Whether the -G option was used. */ |
623 | static int g_switch_seen = 0; | |
624 | ||
625 | #define N_RMASK 0xc4 | |
626 | #define N_VFP 0xd4 | |
627 | ||
628 | /* If we can determine in advance that GP optimization won't be | |
629 | possible, we can skip the relaxation stuff that tries to produce | |
630 | GP-relative references. This makes delay slot optimization work | |
631 | better. | |
632 | ||
633 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
634 | gcc output. It needs to guess right for gcc, otherwise gcc |
635 | will put what it thinks is a GP-relative instruction in a branch | |
636 | delay slot. | |
252b5132 RH |
637 | |
638 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
639 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 640 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
641 | |
642 | /* handle of the OPCODE hash table */ | |
643 | static struct hash_control *op_hash = NULL; | |
644 | ||
645 | /* The opcode hash table we use for the mips16. */ | |
646 | static struct hash_control *mips16_op_hash = NULL; | |
647 | ||
df58fc94 RS |
648 | /* The opcode hash table we use for the microMIPS ASE. */ |
649 | static struct hash_control *micromips_op_hash = NULL; | |
650 | ||
252b5132 RH |
651 | /* This array holds the chars that always start a comment. If the |
652 | pre-processor is disabled, these aren't very useful */ | |
653 | const char comment_chars[] = "#"; | |
654 | ||
655 | /* This array holds the chars that only start a comment at the beginning of | |
656 | a line. If the line seems to have the form '# 123 filename' | |
657 | .line and .file directives will appear in the pre-processed output */ | |
658 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
659 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 660 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
661 | /* Also note that C style comments are always supported. */ |
662 | const char line_comment_chars[] = "#"; | |
663 | ||
bdaaa2e1 | 664 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 665 | const char line_separator_chars[] = ";"; |
252b5132 RH |
666 | |
667 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
668 | const char EXP_CHARS[] = "eE"; | |
669 | ||
670 | /* Chars that mean this number is a floating point constant */ | |
671 | /* As in 0f12.456 */ | |
672 | /* or 0d1.2345e12 */ | |
673 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
674 | ||
675 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
676 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
677 | but nothing is ideal around here. | |
678 | */ | |
679 | ||
680 | static char *insn_error; | |
681 | ||
682 | static int auto_align = 1; | |
683 | ||
684 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
685 | offset in the stack frame from which to restore the $gp register. | |
686 | This is set by the .cprestore pseudo-op, and saved in this | |
687 | variable. */ | |
688 | static offsetT mips_cprestore_offset = -1; | |
689 | ||
67c1ffbe | 690 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 691 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 692 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
693 | static offsetT mips_cpreturn_offset = -1; |
694 | static int mips_cpreturn_register = -1; | |
695 | static int mips_gp_register = GP; | |
def2e0dd | 696 | static int mips_gprel_offset = 0; |
6478892d | 697 | |
7a621144 DJ |
698 | /* Whether mips_cprestore_offset has been set in the current function |
699 | (or whether it has already been warned about, if not). */ | |
700 | static int mips_cprestore_valid = 0; | |
701 | ||
252b5132 RH |
702 | /* This is the register which holds the stack frame, as set by the |
703 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
704 | static int mips_frame_reg = SP; | |
705 | ||
7a621144 DJ |
706 | /* Whether mips_frame_reg has been set in the current function |
707 | (or whether it has already been warned about, if not). */ | |
708 | static int mips_frame_reg_valid = 0; | |
709 | ||
252b5132 RH |
710 | /* To output NOP instructions correctly, we need to keep information |
711 | about the previous two instructions. */ | |
712 | ||
713 | /* Whether we are optimizing. The default value of 2 means to remove | |
714 | unneeded NOPs and swap branch instructions when possible. A value | |
715 | of 1 means to not swap branches. A value of 0 means to always | |
716 | insert NOPs. */ | |
717 | static int mips_optimize = 2; | |
718 | ||
719 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
720 | equivalent to seeing no -g option at all. */ | |
721 | static int mips_debug = 0; | |
722 | ||
7d8e00cf RS |
723 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
724 | #define MAX_VR4130_NOPS 4 | |
725 | ||
726 | /* The maximum number of NOPs needed to fill delay slots. */ | |
727 | #define MAX_DELAY_NOPS 2 | |
728 | ||
729 | /* The maximum number of NOPs needed for any purpose. */ | |
730 | #define MAX_NOPS 4 | |
71400594 RS |
731 | |
732 | /* A list of previous instructions, with index 0 being the most recent. | |
733 | We need to look back MAX_NOPS instructions when filling delay slots | |
734 | or working around processor errata. We need to look back one | |
735 | instruction further if we're thinking about using history[0] to | |
736 | fill a branch delay slot. */ | |
737 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 738 | |
1e915849 | 739 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
740 | static struct mips_cl_insn nop_insn; |
741 | static struct mips_cl_insn mips16_nop_insn; | |
742 | static struct mips_cl_insn micromips_nop16_insn; | |
743 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
744 | |
745 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
746 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
747 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
748 | ||
749 | /* The size of NOP_INSN in bytes. */ | |
750 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 751 | |
252b5132 RH |
752 | /* If this is set, it points to a frag holding nop instructions which |
753 | were inserted before the start of a noreorder section. If those | |
754 | nops turn out to be unnecessary, the size of the frag can be | |
755 | decreased. */ | |
756 | static fragS *prev_nop_frag; | |
757 | ||
758 | /* The number of nop instructions we created in prev_nop_frag. */ | |
759 | static int prev_nop_frag_holds; | |
760 | ||
761 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 762 | prev_nop_frag. */ |
252b5132 RH |
763 | static int prev_nop_frag_required; |
764 | ||
765 | /* The number of instructions we've seen since prev_nop_frag. */ | |
766 | static int prev_nop_frag_since; | |
767 | ||
768 | /* For ECOFF and ELF, relocations against symbols are done in two | |
769 | parts, with a HI relocation and a LO relocation. Each relocation | |
770 | has only 16 bits of space to store an addend. This means that in | |
771 | order for the linker to handle carries correctly, it must be able | |
772 | to locate both the HI and the LO relocation. This means that the | |
773 | relocations must appear in order in the relocation table. | |
774 | ||
775 | In order to implement this, we keep track of each unmatched HI | |
776 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 777 | corresponding LO relocation. */ |
252b5132 | 778 | |
e972090a NC |
779 | struct mips_hi_fixup |
780 | { | |
252b5132 RH |
781 | /* Next HI fixup. */ |
782 | struct mips_hi_fixup *next; | |
783 | /* This fixup. */ | |
784 | fixS *fixp; | |
785 | /* The section this fixup is in. */ | |
786 | segT seg; | |
787 | }; | |
788 | ||
789 | /* The list of unmatched HI relocs. */ | |
790 | ||
791 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
792 | ||
64bdfcaf RS |
793 | /* The frag containing the last explicit relocation operator. |
794 | Null if explicit relocations have not been used. */ | |
795 | ||
796 | static fragS *prev_reloc_op_frag; | |
797 | ||
252b5132 RH |
798 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
799 | ||
800 | #define X ILLEGAL_REG | |
e972090a NC |
801 | static const int mips32_to_16_reg_map[] = |
802 | { | |
252b5132 RH |
803 | X, X, 2, 3, 4, 5, 6, 7, |
804 | X, X, X, X, X, X, X, X, | |
805 | 0, 1, X, X, X, X, X, X, | |
806 | X, X, X, X, X, X, X, X | |
807 | }; | |
808 | #undef X | |
809 | ||
810 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
811 | ||
e972090a NC |
812 | static const unsigned int mips16_to_32_reg_map[] = |
813 | { | |
252b5132 RH |
814 | 16, 17, 2, 3, 4, 5, 6, 7 |
815 | }; | |
60b63b72 | 816 | |
df58fc94 RS |
817 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
818 | ||
819 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
820 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
821 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
822 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
823 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
824 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
825 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
826 | ||
827 | #define X ILLEGAL_REG | |
828 | /* reg type h: 4, 5, 6. */ | |
829 | static const int mips32_to_micromips_reg_h_map[] = | |
830 | { | |
831 | X, X, X, X, 4, 5, 6, X, | |
832 | X, X, X, X, X, X, X, X, | |
833 | X, X, X, X, X, X, X, X, | |
834 | X, X, X, X, X, X, X, X | |
835 | }; | |
836 | ||
837 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
838 | static const int mips32_to_micromips_reg_m_map[] = | |
839 | { | |
840 | 0, X, 2, 3, X, X, X, X, | |
841 | X, X, X, X, X, X, X, X, | |
842 | 4, 1, 5, 6, 7, X, X, X, | |
843 | X, X, X, X, X, X, X, X | |
844 | }; | |
845 | ||
846 | /* reg type q: 0, 2-7. 17. */ | |
847 | static const int mips32_to_micromips_reg_q_map[] = | |
848 | { | |
849 | 0, X, 2, 3, 4, 5, 6, 7, | |
850 | X, X, X, X, X, X, X, X, | |
851 | X, 1, X, X, X, X, X, X, | |
852 | X, X, X, X, X, X, X, X | |
853 | }; | |
854 | ||
855 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
856 | #undef X | |
857 | ||
858 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
859 | ||
860 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
861 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
862 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
863 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
864 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
865 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
866 | ||
867 | /* The microMIPS registers with type h. */ | |
868 | static const unsigned int micromips_to_32_reg_h_map[] = | |
869 | { | |
870 | 5, 5, 6, 4, 4, 4, 4, 4 | |
871 | }; | |
872 | ||
873 | /* The microMIPS registers with type i. */ | |
874 | static const unsigned int micromips_to_32_reg_i_map[] = | |
875 | { | |
876 | 6, 7, 7, 21, 22, 5, 6, 7 | |
877 | }; | |
878 | ||
879 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
880 | ||
881 | /* The microMIPS registers with type m. */ | |
882 | static const unsigned int micromips_to_32_reg_m_map[] = | |
883 | { | |
884 | 0, 17, 2, 3, 16, 18, 19, 20 | |
885 | }; | |
886 | ||
887 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
888 | ||
889 | /* The microMIPS registers with type q. */ | |
890 | static const unsigned int micromips_to_32_reg_q_map[] = | |
891 | { | |
892 | 0, 17, 2, 3, 4, 5, 6, 7 | |
893 | }; | |
894 | ||
895 | /* microMIPS imm type B. */ | |
896 | static const int micromips_imm_b_map[] = | |
897 | { | |
898 | 1, 4, 8, 12, 16, 20, 24, -1 | |
899 | }; | |
900 | ||
901 | /* microMIPS imm type C. */ | |
902 | static const int micromips_imm_c_map[] = | |
903 | { | |
904 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
905 | }; | |
906 | ||
71400594 RS |
907 | /* Classifies the kind of instructions we're interested in when |
908 | implementing -mfix-vr4120. */ | |
c67a084a NC |
909 | enum fix_vr4120_class |
910 | { | |
71400594 RS |
911 | FIX_VR4120_MACC, |
912 | FIX_VR4120_DMACC, | |
913 | FIX_VR4120_MULT, | |
914 | FIX_VR4120_DMULT, | |
915 | FIX_VR4120_DIV, | |
916 | FIX_VR4120_MTHILO, | |
917 | NUM_FIX_VR4120_CLASSES | |
918 | }; | |
919 | ||
c67a084a NC |
920 | /* ...likewise -mfix-loongson2f-jump. */ |
921 | static bfd_boolean mips_fix_loongson2f_jump; | |
922 | ||
923 | /* ...likewise -mfix-loongson2f-nop. */ | |
924 | static bfd_boolean mips_fix_loongson2f_nop; | |
925 | ||
926 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
927 | static bfd_boolean mips_fix_loongson2f; | |
928 | ||
71400594 RS |
929 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
930 | there must be at least one other instruction between an instruction | |
931 | of type X and an instruction of type Y. */ | |
932 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
933 | ||
934 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 935 | static int mips_fix_vr4120; |
4a6a3df4 | 936 | |
7d8e00cf RS |
937 | /* ...likewise -mfix-vr4130. */ |
938 | static int mips_fix_vr4130; | |
939 | ||
6a32d874 CM |
940 | /* ...likewise -mfix-24k. */ |
941 | static int mips_fix_24k; | |
942 | ||
d954098f DD |
943 | /* ...likewise -mfix-cn63xxp1 */ |
944 | static bfd_boolean mips_fix_cn63xxp1; | |
945 | ||
4a6a3df4 AO |
946 | /* We don't relax branches by default, since this causes us to expand |
947 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
948 | fail to compute the offset before expanding the macro to the most | |
949 | efficient expansion. */ | |
950 | ||
951 | static int mips_relax_branch; | |
252b5132 | 952 | \f |
4d7206a2 RS |
953 | /* The expansion of many macros depends on the type of symbol that |
954 | they refer to. For example, when generating position-dependent code, | |
955 | a macro that refers to a symbol may have two different expansions, | |
956 | one which uses GP-relative addresses and one which uses absolute | |
957 | addresses. When generating SVR4-style PIC, a macro may have | |
958 | different expansions for local and global symbols. | |
959 | ||
960 | We handle these situations by generating both sequences and putting | |
961 | them in variant frags. In position-dependent code, the first sequence | |
962 | will be the GP-relative one and the second sequence will be the | |
963 | absolute one. In SVR4 PIC, the first sequence will be for global | |
964 | symbols and the second will be for local symbols. | |
965 | ||
584892a6 RS |
966 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
967 | SECOND are the lengths of the two sequences in bytes. These fields | |
968 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
969 | the subtype has the following flags: | |
4d7206a2 | 970 | |
584892a6 RS |
971 | RELAX_USE_SECOND |
972 | Set if it has been decided that we should use the second | |
973 | sequence instead of the first. | |
974 | ||
975 | RELAX_SECOND_LONGER | |
976 | Set in the first variant frag if the macro's second implementation | |
977 | is longer than its first. This refers to the macro as a whole, | |
978 | not an individual relaxation. | |
979 | ||
980 | RELAX_NOMACRO | |
981 | Set in the first variant frag if the macro appeared in a .set nomacro | |
982 | block and if one alternative requires a warning but the other does not. | |
983 | ||
984 | RELAX_DELAY_SLOT | |
985 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
986 | delay slot. | |
4d7206a2 | 987 | |
df58fc94 RS |
988 | RELAX_DELAY_SLOT_16BIT |
989 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
990 | 16-bit instruction. | |
991 | ||
992 | RELAX_DELAY_SLOT_SIZE_FIRST | |
993 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
994 | the macro is of the wrong size for the branch delay slot. | |
995 | ||
996 | RELAX_DELAY_SLOT_SIZE_SECOND | |
997 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
998 | the macro is of the wrong size for the branch delay slot. | |
999 | ||
4d7206a2 RS |
1000 | The frag's "opcode" points to the first fixup for relaxable code. |
1001 | ||
1002 | Relaxable macros are generated using a sequence such as: | |
1003 | ||
1004 | relax_start (SYMBOL); | |
1005 | ... generate first expansion ... | |
1006 | relax_switch (); | |
1007 | ... generate second expansion ... | |
1008 | relax_end (); | |
1009 | ||
1010 | The code and fixups for the unwanted alternative are discarded | |
1011 | by md_convert_frag. */ | |
584892a6 | 1012 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1013 | |
584892a6 RS |
1014 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1015 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1016 | #define RELAX_USE_SECOND 0x10000 | |
1017 | #define RELAX_SECOND_LONGER 0x20000 | |
1018 | #define RELAX_NOMACRO 0x40000 | |
1019 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1020 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1021 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1022 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1023 | |
4a6a3df4 AO |
1024 | /* Branch without likely bit. If label is out of range, we turn: |
1025 | ||
1026 | beq reg1, reg2, label | |
1027 | delay slot | |
1028 | ||
1029 | into | |
1030 | ||
1031 | bne reg1, reg2, 0f | |
1032 | nop | |
1033 | j label | |
1034 | 0: delay slot | |
1035 | ||
1036 | with the following opcode replacements: | |
1037 | ||
1038 | beq <-> bne | |
1039 | blez <-> bgtz | |
1040 | bltz <-> bgez | |
1041 | bc1f <-> bc1t | |
1042 | ||
1043 | bltzal <-> bgezal (with jal label instead of j label) | |
1044 | ||
1045 | Even though keeping the delay slot instruction in the delay slot of | |
1046 | the branch would be more efficient, it would be very tricky to do | |
1047 | correctly, because we'd have to introduce a variable frag *after* | |
1048 | the delay slot instruction, and expand that instead. Let's do it | |
1049 | the easy way for now, even if the branch-not-taken case now costs | |
1050 | one additional instruction. Out-of-range branches are not supposed | |
1051 | to be common, anyway. | |
1052 | ||
1053 | Branch likely. If label is out of range, we turn: | |
1054 | ||
1055 | beql reg1, reg2, label | |
1056 | delay slot (annulled if branch not taken) | |
1057 | ||
1058 | into | |
1059 | ||
1060 | beql reg1, reg2, 1f | |
1061 | nop | |
1062 | beql $0, $0, 2f | |
1063 | nop | |
1064 | 1: j[al] label | |
1065 | delay slot (executed only if branch taken) | |
1066 | 2: | |
1067 | ||
1068 | It would be possible to generate a shorter sequence by losing the | |
1069 | likely bit, generating something like: | |
b34976b6 | 1070 | |
4a6a3df4 AO |
1071 | bne reg1, reg2, 0f |
1072 | nop | |
1073 | j[al] label | |
1074 | delay slot (executed only if branch taken) | |
1075 | 0: | |
1076 | ||
1077 | beql -> bne | |
1078 | bnel -> beq | |
1079 | blezl -> bgtz | |
1080 | bgtzl -> blez | |
1081 | bltzl -> bgez | |
1082 | bgezl -> bltz | |
1083 | bc1fl -> bc1t | |
1084 | bc1tl -> bc1f | |
1085 | ||
1086 | bltzall -> bgezal (with jal label instead of j label) | |
1087 | bgezall -> bltzal (ditto) | |
1088 | ||
1089 | ||
1090 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1091 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1092 | ((relax_substateT) \ | |
1093 | (0xc0000000 \ | |
1094 | | ((at) & 0x1f) \ | |
1095 | | ((toofar) ? 0x20 : 0) \ | |
1096 | | ((link) ? 0x40 : 0) \ | |
1097 | | ((likely) ? 0x80 : 0) \ | |
1098 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1099 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1100 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1101 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1102 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1103 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1104 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1105 | |
252b5132 RH |
1106 | /* For mips16 code, we use an entirely different form of relaxation. |
1107 | mips16 supports two versions of most instructions which take | |
1108 | immediate values: a small one which takes some small value, and a | |
1109 | larger one which takes a 16 bit value. Since branches also follow | |
1110 | this pattern, relaxing these values is required. | |
1111 | ||
1112 | We can assemble both mips16 and normal MIPS code in a single | |
1113 | object. Therefore, we need to support this type of relaxation at | |
1114 | the same time that we support the relaxation described above. We | |
1115 | use the high bit of the subtype field to distinguish these cases. | |
1116 | ||
1117 | The information we store for this type of relaxation is the | |
1118 | argument code found in the opcode file for this relocation, whether | |
1119 | the user explicitly requested a small or extended form, and whether | |
1120 | the relocation is in a jump or jal delay slot. That tells us the | |
1121 | size of the value, and how it should be stored. We also store | |
1122 | whether the fragment is considered to be extended or not. We also | |
1123 | store whether this is known to be a branch to a different section, | |
1124 | whether we have tried to relax this frag yet, and whether we have | |
1125 | ever extended a PC relative fragment because of a shift count. */ | |
1126 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1127 | (0x80000000 \ | |
1128 | | ((type) & 0xff) \ | |
1129 | | ((small) ? 0x100 : 0) \ | |
1130 | | ((ext) ? 0x200 : 0) \ | |
1131 | | ((dslot) ? 0x400 : 0) \ | |
1132 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1133 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1134 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1135 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1136 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1137 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1138 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1139 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1140 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1141 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1142 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1143 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1144 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1145 | |
df58fc94 RS |
1146 | /* For microMIPS code, we use relaxation similar to one we use for |
1147 | MIPS16 code. Some instructions that take immediate values support | |
1148 | two encodings: a small one which takes some small value, and a | |
1149 | larger one which takes a 16 bit value. As some branches also follow | |
1150 | this pattern, relaxing these values is required. | |
1151 | ||
1152 | We can assemble both microMIPS and normal MIPS code in a single | |
1153 | object. Therefore, we need to support this type of relaxation at | |
1154 | the same time that we support the relaxation described above. We | |
1155 | use one of the high bits of the subtype field to distinguish these | |
1156 | cases. | |
1157 | ||
1158 | The information we store for this type of relaxation is the argument | |
1159 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1160 | selected as the assembler temporary, whether the branch is |
1161 | unconditional, whether it is compact, whether it stores the link | |
1162 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1163 | branches to a sequence of instructions is enabled, and whether the | |
1164 | displacement of a branch is too large to fit as an immediate argument | |
1165 | of a 16-bit and a 32-bit branch, respectively. */ | |
1166 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1167 | relax32, toofar16, toofar32) \ | |
1168 | (0x40000000 \ | |
1169 | | ((type) & 0xff) \ | |
1170 | | (((at) & 0x1f) << 8) \ | |
1171 | | ((uncond) ? 0x2000 : 0) \ | |
1172 | | ((compact) ? 0x4000 : 0) \ | |
1173 | | ((link) ? 0x8000 : 0) \ | |
1174 | | ((relax32) ? 0x10000 : 0) \ | |
1175 | | ((toofar16) ? 0x20000 : 0) \ | |
1176 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1177 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1178 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1179 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1180 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1181 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1182 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1183 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1184 | ||
1185 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1186 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1187 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1188 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1189 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1190 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1191 | |
885add95 CD |
1192 | /* Is the given value a sign-extended 32-bit value? */ |
1193 | #define IS_SEXT_32BIT_NUM(x) \ | |
1194 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1195 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1196 | ||
1197 | /* Is the given value a sign-extended 16-bit value? */ | |
1198 | #define IS_SEXT_16BIT_NUM(x) \ | |
1199 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1200 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1201 | ||
df58fc94 RS |
1202 | /* Is the given value a sign-extended 12-bit value? */ |
1203 | #define IS_SEXT_12BIT_NUM(x) \ | |
1204 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1205 | ||
2051e8c4 MR |
1206 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1207 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1208 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1209 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1210 | ||
bf12938e RS |
1211 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1212 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1213 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1214 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1215 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1216 | ||
1217 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1218 | SHIFT places. */ | |
1219 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1220 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1221 | ||
1222 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1223 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1224 | ||
1225 | include/opcode/mips.h specifies operand fields using the macros | |
1226 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1227 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1228 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1229 | do \ | |
1230 | if (!(MICROMIPS)) \ | |
1231 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1232 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1233 | else \ | |
1234 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1235 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1236 | while (0) | |
bf12938e RS |
1237 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1238 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1239 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1240 | ||
1241 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1242 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1243 | (!(MICROMIPS) \ | |
1244 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1245 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1246 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1247 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1248 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1249 | MIPS16OP_MASK_##FIELD, \ | |
1250 | MIPS16OP_SH_##FIELD) | |
4d7206a2 | 1251 | \f |
df58fc94 RS |
1252 | /* Whether or not we are emitting a branch-likely macro. */ |
1253 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1254 | ||
4d7206a2 RS |
1255 | /* Global variables used when generating relaxable macros. See the |
1256 | comment above RELAX_ENCODE for more details about how relaxation | |
1257 | is used. */ | |
1258 | static struct { | |
1259 | /* 0 if we're not emitting a relaxable macro. | |
1260 | 1 if we're emitting the first of the two relaxation alternatives. | |
1261 | 2 if we're emitting the second alternative. */ | |
1262 | int sequence; | |
1263 | ||
1264 | /* The first relaxable fixup in the current frag. (In other words, | |
1265 | the first fixup that refers to relaxable code.) */ | |
1266 | fixS *first_fixup; | |
1267 | ||
1268 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1269 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1270 | unsigned int sizes[2]; | |
1271 | ||
1272 | /* The symbol on which the choice of sequence depends. */ | |
1273 | symbolS *symbol; | |
1274 | } mips_relax; | |
252b5132 | 1275 | \f |
584892a6 RS |
1276 | /* Global variables used to decide whether a macro needs a warning. */ |
1277 | static struct { | |
1278 | /* True if the macro is in a branch delay slot. */ | |
1279 | bfd_boolean delay_slot_p; | |
1280 | ||
df58fc94 RS |
1281 | /* Set to the length in bytes required if the macro is in a delay slot |
1282 | that requires a specific length of instruction, otherwise zero. */ | |
1283 | unsigned int delay_slot_length; | |
1284 | ||
584892a6 RS |
1285 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1286 | in bytes and sizes[1] is the length of the second alternative. | |
1287 | For non-relaxable macros, both elements give the length of the | |
1288 | macro in bytes. */ | |
1289 | unsigned int sizes[2]; | |
1290 | ||
df58fc94 RS |
1291 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1292 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1293 | is the length of the first instruction of the second alternative. | |
1294 | For non-relaxable macros, both elements give the length of the first | |
1295 | instruction in bytes. | |
1296 | ||
1297 | Set to zero if we haven't yet seen the first instruction. */ | |
1298 | unsigned int first_insn_sizes[2]; | |
1299 | ||
1300 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1301 | first alternative and insns[1] is the number of instructions for the | |
1302 | second alternative. | |
1303 | ||
1304 | For non-relaxable macros, both elements give the number of | |
1305 | instructions for the macro. */ | |
1306 | unsigned int insns[2]; | |
1307 | ||
584892a6 RS |
1308 | /* The first variant frag for this macro. */ |
1309 | fragS *first_frag; | |
1310 | } mips_macro_warning; | |
1311 | \f | |
252b5132 RH |
1312 | /* Prototypes for static functions. */ |
1313 | ||
17a2f251 | 1314 | #define internalError() \ |
252b5132 | 1315 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1316 | |
1317 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1318 | ||
b34976b6 | 1319 | static void append_insn |
df58fc94 RS |
1320 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1321 | bfd_boolean expansionp); | |
7d10b47d | 1322 | static void mips_no_prev_insn (void); |
c67a084a | 1323 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1324 | static void mips16_macro_build |
03ea81db | 1325 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1326 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1327 | static void macro_start (void); |
1328 | static void macro_end (void); | |
17a2f251 TS |
1329 | static void macro (struct mips_cl_insn * ip); |
1330 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1331 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1332 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1333 | static void mips16_immed |
17a2f251 TS |
1334 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1335 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1336 | static size_t my_getSmallExpression |
17a2f251 TS |
1337 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1338 | static void my_getExpression (expressionS *, char *); | |
1339 | static void s_align (int); | |
1340 | static void s_change_sec (int); | |
1341 | static void s_change_section (int); | |
1342 | static void s_cons (int); | |
1343 | static void s_float_cons (int); | |
1344 | static void s_mips_globl (int); | |
1345 | static void s_option (int); | |
1346 | static void s_mipsset (int); | |
1347 | static void s_abicalls (int); | |
1348 | static void s_cpload (int); | |
1349 | static void s_cpsetup (int); | |
1350 | static void s_cplocal (int); | |
1351 | static void s_cprestore (int); | |
1352 | static void s_cpreturn (int); | |
741d6ea8 JM |
1353 | static void s_dtprelword (int); |
1354 | static void s_dtpreldword (int); | |
17a2f251 TS |
1355 | static void s_gpvalue (int); |
1356 | static void s_gpword (int); | |
1357 | static void s_gpdword (int); | |
1358 | static void s_cpadd (int); | |
1359 | static void s_insn (int); | |
1360 | static void md_obj_begin (void); | |
1361 | static void md_obj_end (void); | |
1362 | static void s_mips_ent (int); | |
1363 | static void s_mips_end (int); | |
1364 | static void s_mips_frame (int); | |
1365 | static void s_mips_mask (int reg_type); | |
1366 | static void s_mips_stab (int); | |
1367 | static void s_mips_weakext (int); | |
1368 | static void s_mips_file (int); | |
1369 | static void s_mips_loc (int); | |
1370 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1371 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1372 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1373 | static int validate_micromips_insn (const struct mips_opcode *); |
1374 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1375 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1376 | |
1377 | /* Table and functions used to map between CPU/ISA names, and | |
1378 | ISA levels, and CPU numbers. */ | |
1379 | ||
e972090a NC |
1380 | struct mips_cpu_info |
1381 | { | |
e7af610e | 1382 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1383 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1384 | int isa; /* ISA level. */ |
1385 | int cpu; /* CPU number (default CPU if ISA). */ | |
1386 | }; | |
1387 | ||
ad3fea08 TS |
1388 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1389 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1390 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1391 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1392 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1393 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1394 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1395 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1396 | |
17a2f251 TS |
1397 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1398 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1399 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1400 | \f |
1401 | /* Pseudo-op table. | |
1402 | ||
1403 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1404 | should be defined here, but are currently unsupported: .alias, | |
1405 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1406 | ||
1407 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1408 | specific to the type of debugging information being generated, and | |
1409 | should be defined by the object format: .aent, .begin, .bend, | |
1410 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1411 | .vreg. | |
1412 | ||
1413 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1414 | not MIPS CPU specific, but are also not specific to the object file | |
1415 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1416 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1417 | |
e972090a NC |
1418 | static const pseudo_typeS mips_pseudo_table[] = |
1419 | { | |
beae10d5 | 1420 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1421 | {"option", s_option, 0}, |
1422 | {"set", s_mipsset, 0}, | |
1423 | {"rdata", s_change_sec, 'r'}, | |
1424 | {"sdata", s_change_sec, 's'}, | |
1425 | {"livereg", s_ignore, 0}, | |
1426 | {"abicalls", s_abicalls, 0}, | |
1427 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1428 | {"cpsetup", s_cpsetup, 0}, |
1429 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1430 | {"cprestore", s_cprestore, 0}, |
6478892d | 1431 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1432 | {"dtprelword", s_dtprelword, 0}, |
1433 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1434 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1435 | {"gpword", s_gpword, 0}, |
10181a0d | 1436 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1437 | {"cpadd", s_cpadd, 0}, |
1438 | {"insn", s_insn, 0}, | |
1439 | ||
beae10d5 | 1440 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1441 | chips. */ |
38a57ae7 | 1442 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1443 | {"bss", s_change_sec, 'b'}, |
1444 | {"err", s_err, 0}, | |
1445 | {"half", s_cons, 1}, | |
1446 | {"dword", s_cons, 3}, | |
1447 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1448 | {"origin", s_org, 0}, |
1449 | {"repeat", s_rept, 0}, | |
252b5132 | 1450 | |
998b3c36 MR |
1451 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1452 | {"sbss", s_change_sec, 'B'}, | |
1453 | ||
beae10d5 | 1454 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1455 | here for one reason or another. */ |
1456 | {"align", s_align, 0}, | |
1457 | {"byte", s_cons, 0}, | |
1458 | {"data", s_change_sec, 'd'}, | |
1459 | {"double", s_float_cons, 'd'}, | |
1460 | {"float", s_float_cons, 'f'}, | |
1461 | {"globl", s_mips_globl, 0}, | |
1462 | {"global", s_mips_globl, 0}, | |
1463 | {"hword", s_cons, 1}, | |
1464 | {"int", s_cons, 2}, | |
1465 | {"long", s_cons, 2}, | |
1466 | {"octa", s_cons, 4}, | |
1467 | {"quad", s_cons, 3}, | |
cca86cc8 | 1468 | {"section", s_change_section, 0}, |
252b5132 RH |
1469 | {"short", s_cons, 1}, |
1470 | {"single", s_float_cons, 'f'}, | |
1471 | {"stabn", s_mips_stab, 'n'}, | |
1472 | {"text", s_change_sec, 't'}, | |
1473 | {"word", s_cons, 2}, | |
add56521 | 1474 | |
add56521 | 1475 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1476 | |
43841e91 | 1477 | { NULL, NULL, 0 }, |
252b5132 RH |
1478 | }; |
1479 | ||
e972090a NC |
1480 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1481 | { | |
beae10d5 KH |
1482 | /* These pseudo-ops should be defined by the object file format. |
1483 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1484 | {"aent", s_mips_ent, 1}, |
1485 | {"bgnb", s_ignore, 0}, | |
1486 | {"end", s_mips_end, 0}, | |
1487 | {"endb", s_ignore, 0}, | |
1488 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1489 | {"file", s_mips_file, 0}, |
252b5132 RH |
1490 | {"fmask", s_mips_mask, 'F'}, |
1491 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1492 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1493 | {"mask", s_mips_mask, 'R'}, |
1494 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1495 | { NULL, NULL, 0 }, |
252b5132 RH |
1496 | }; |
1497 | ||
3ae8dd8d MR |
1498 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1499 | purpose of the `.dc.a' internal pseudo-op. */ | |
1500 | ||
1501 | int | |
1502 | mips_address_bytes (void) | |
1503 | { | |
1504 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1505 | } | |
1506 | ||
17a2f251 | 1507 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1508 | |
1509 | void | |
17a2f251 | 1510 | mips_pop_insert (void) |
252b5132 RH |
1511 | { |
1512 | pop_insert (mips_pseudo_table); | |
1513 | if (! ECOFF_DEBUGGING) | |
1514 | pop_insert (mips_nonecoff_pseudo_table); | |
1515 | } | |
1516 | \f | |
1517 | /* Symbols labelling the current insn. */ | |
1518 | ||
e972090a NC |
1519 | struct insn_label_list |
1520 | { | |
252b5132 RH |
1521 | struct insn_label_list *next; |
1522 | symbolS *label; | |
1523 | }; | |
1524 | ||
252b5132 | 1525 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1526 | #define label_list tc_segment_info_data.labels |
252b5132 | 1527 | |
17a2f251 | 1528 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1529 | static void mips_mark_labels (void); |
1530 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1531 | |
1532 | static inline void | |
17a2f251 | 1533 | mips_clear_insn_labels (void) |
252b5132 RH |
1534 | { |
1535 | register struct insn_label_list **pl; | |
a8dbcb85 | 1536 | segment_info_type *si; |
252b5132 | 1537 | |
a8dbcb85 TS |
1538 | if (now_seg) |
1539 | { | |
1540 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1541 | ; | |
1542 | ||
1543 | si = seg_info (now_seg); | |
1544 | *pl = si->label_list; | |
1545 | si->label_list = NULL; | |
1546 | } | |
252b5132 | 1547 | } |
a8dbcb85 | 1548 | |
df58fc94 RS |
1549 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1550 | ||
1551 | static inline void | |
1552 | mips_mark_labels (void) | |
1553 | { | |
1554 | if (HAVE_CODE_COMPRESSION) | |
1555 | mips_compressed_mark_labels (); | |
1556 | } | |
252b5132 RH |
1557 | \f |
1558 | static char *expr_end; | |
1559 | ||
1560 | /* Expressions which appear in instructions. These are set by | |
1561 | mips_ip. */ | |
1562 | ||
1563 | static expressionS imm_expr; | |
5f74bc13 | 1564 | static expressionS imm2_expr; |
252b5132 RH |
1565 | static expressionS offset_expr; |
1566 | ||
1567 | /* Relocs associated with imm_expr and offset_expr. */ | |
1568 | ||
f6688943 TS |
1569 | static bfd_reloc_code_real_type imm_reloc[3] |
1570 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1571 | static bfd_reloc_code_real_type offset_reloc[3] | |
1572 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1573 | |
df58fc94 RS |
1574 | /* This is set to the resulting size of the instruction to be produced |
1575 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1576 | explicit size is supplied. */ | |
252b5132 | 1577 | |
df58fc94 | 1578 | static unsigned int forced_insn_length; |
252b5132 | 1579 | |
7ed4a06a | 1580 | #ifdef OBJ_ELF |
ecb4347a DJ |
1581 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1582 | ECOFF debugging. */ | |
252b5132 RH |
1583 | |
1584 | static segT pdr_seg; | |
7ed4a06a | 1585 | #endif |
252b5132 | 1586 | |
e013f690 TS |
1587 | /* The default target format to use. */ |
1588 | ||
aeffff67 RS |
1589 | #if defined (TE_FreeBSD) |
1590 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1591 | #elif defined (TE_TMIPS) | |
1592 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1593 | #else | |
1594 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1595 | #endif | |
1596 | ||
e013f690 | 1597 | const char * |
17a2f251 | 1598 | mips_target_format (void) |
e013f690 TS |
1599 | { |
1600 | switch (OUTPUT_FLAVOR) | |
1601 | { | |
e013f690 TS |
1602 | case bfd_target_ecoff_flavour: |
1603 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1604 | case bfd_target_coff_flavour: | |
1605 | return "pe-mips"; | |
1606 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1607 | #ifdef TE_VXWORKS |
1608 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1609 | return (target_big_endian | |
1610 | ? "elf32-bigmips-vxworks" | |
1611 | : "elf32-littlemips-vxworks"); | |
1612 | #endif | |
e013f690 | 1613 | return (target_big_endian |
cfe86eaa | 1614 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1615 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1616 | : (HAVE_NEWABI |
aeffff67 RS |
1617 | ? ELF_TARGET ("elf32-n", "big") |
1618 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1619 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1620 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1621 | : (HAVE_NEWABI |
aeffff67 RS |
1622 | ? ELF_TARGET ("elf32-n", "little") |
1623 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1624 | default: |
1625 | abort (); | |
1626 | return NULL; | |
1627 | } | |
1628 | } | |
1629 | ||
df58fc94 RS |
1630 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1631 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1632 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1633 | major opcode) will require further modifications to the opcode | |
1634 | table. */ | |
1635 | ||
1636 | static inline unsigned int | |
1637 | micromips_insn_length (const struct mips_opcode *mo) | |
1638 | { | |
1639 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1640 | } | |
1641 | ||
1e915849 RS |
1642 | /* Return the length of instruction INSN. */ |
1643 | ||
1644 | static inline unsigned int | |
1645 | insn_length (const struct mips_cl_insn *insn) | |
1646 | { | |
df58fc94 RS |
1647 | if (mips_opts.micromips) |
1648 | return micromips_insn_length (insn->insn_mo); | |
1649 | else if (mips_opts.mips16) | |
1650 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1651 | else | |
1e915849 | 1652 | return 4; |
1e915849 RS |
1653 | } |
1654 | ||
1655 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1656 | ||
1657 | static void | |
1658 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1659 | { | |
1660 | size_t i; | |
1661 | ||
1662 | insn->insn_mo = mo; | |
1663 | insn->use_extend = FALSE; | |
1664 | insn->extend = 0; | |
1665 | insn->insn_opcode = mo->match; | |
1666 | insn->frag = NULL; | |
1667 | insn->where = 0; | |
1668 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1669 | insn->fixp[i] = NULL; | |
1670 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1671 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1672 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1673 | insn->complete_p = 0; |
1e915849 RS |
1674 | } |
1675 | ||
df58fc94 | 1676 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1677 | |
1678 | static void | |
df58fc94 | 1679 | mips_record_compressed_mode (void) |
742a56fe RS |
1680 | { |
1681 | segment_info_type *si; | |
1682 | ||
1683 | si = seg_info (now_seg); | |
1684 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1685 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1686 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1687 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1688 | } |
1689 | ||
1e915849 RS |
1690 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1691 | ||
1692 | static void | |
1693 | install_insn (const struct mips_cl_insn *insn) | |
1694 | { | |
1695 | char *f = insn->frag->fr_literal + insn->where; | |
df58fc94 | 1696 | if (!HAVE_CODE_COMPRESSION) |
1e915849 | 1697 | md_number_to_chars (f, insn->insn_opcode, 4); |
df58fc94 RS |
1698 | else if (mips_opts.micromips) |
1699 | { | |
1700 | unsigned int length = insn_length (insn); | |
1701 | if (length == 2) | |
1702 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1703 | else if (length == 4) | |
1704 | { | |
1705 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1706 | f += 2; | |
1707 | md_number_to_chars (f, insn->insn_opcode & 0xffff, 2); | |
1708 | } | |
1709 | else | |
1710 | as_bad (_("48-bit microMIPS instructions are not supported")); | |
1711 | } | |
1e915849 RS |
1712 | else if (insn->mips16_absolute_jump_p) |
1713 | { | |
1714 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1715 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | if (insn->use_extend) | |
1720 | { | |
1721 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1722 | f += 2; | |
1723 | } | |
1724 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1725 | } | |
df58fc94 | 1726 | mips_record_compressed_mode (); |
1e915849 RS |
1727 | } |
1728 | ||
1729 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1730 | and install the opcode in the new location. */ | |
1731 | ||
1732 | static void | |
1733 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1734 | { | |
1735 | size_t i; | |
1736 | ||
1737 | insn->frag = frag; | |
1738 | insn->where = where; | |
1739 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1740 | if (insn->fixp[i] != NULL) | |
1741 | { | |
1742 | insn->fixp[i]->fx_frag = frag; | |
1743 | insn->fixp[i]->fx_where = where; | |
1744 | } | |
1745 | install_insn (insn); | |
1746 | } | |
1747 | ||
1748 | /* Add INSN to the end of the output. */ | |
1749 | ||
1750 | static void | |
1751 | add_fixed_insn (struct mips_cl_insn *insn) | |
1752 | { | |
1753 | char *f = frag_more (insn_length (insn)); | |
1754 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1755 | } | |
1756 | ||
1757 | /* Start a variant frag and move INSN to the start of the variant part, | |
1758 | marking it as fixed. The other arguments are as for frag_var. */ | |
1759 | ||
1760 | static void | |
1761 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1762 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1763 | { | |
1764 | frag_grow (max_chars); | |
1765 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1766 | insn->fixed_p = 1; | |
1767 | frag_var (rs_machine_dependent, max_chars, var, | |
1768 | subtype, symbol, offset, NULL); | |
1769 | } | |
1770 | ||
1771 | /* Insert N copies of INSN into the history buffer, starting at | |
1772 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1773 | ||
1774 | static void | |
1775 | insert_into_history (unsigned int first, unsigned int n, | |
1776 | const struct mips_cl_insn *insn) | |
1777 | { | |
1778 | if (mips_relax.sequence != 2) | |
1779 | { | |
1780 | unsigned int i; | |
1781 | ||
1782 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1783 | if (i >= first + n) | |
1784 | history[i] = history[i - n]; | |
1785 | else | |
1786 | history[i] = *insn; | |
1787 | } | |
1788 | } | |
1789 | ||
71400594 RS |
1790 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1791 | the idea is to make it obvious at a glance that each errata is | |
1792 | included. */ | |
1793 | ||
1794 | static void | |
1795 | init_vr4120_conflicts (void) | |
1796 | { | |
1797 | #define CONFLICT(FIRST, SECOND) \ | |
1798 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1799 | ||
1800 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1801 | CONFLICT (MACC, DIV); | |
1802 | CONFLICT (DMACC, DIV); | |
1803 | ||
1804 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1805 | CONFLICT (DMULT, DMULT); | |
1806 | CONFLICT (DMULT, DMACC); | |
1807 | CONFLICT (DMACC, DMULT); | |
1808 | CONFLICT (DMACC, DMACC); | |
1809 | ||
1810 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1811 | CONFLICT (MACC, MTHILO); | |
1812 | CONFLICT (DMACC, MTHILO); | |
1813 | ||
1814 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1815 | instruction is executed immediately after a MACC or DMACC | |
1816 | instruction, the result of [either instruction] is incorrect." */ | |
1817 | CONFLICT (MACC, MULT); | |
1818 | CONFLICT (MACC, DMULT); | |
1819 | CONFLICT (DMACC, MULT); | |
1820 | CONFLICT (DMACC, DMULT); | |
1821 | ||
1822 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1823 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1824 | DDIV or DDIVU instruction, the result of the MACC or | |
1825 | DMACC instruction is incorrect.". */ | |
1826 | CONFLICT (DMULT, MACC); | |
1827 | CONFLICT (DMULT, DMACC); | |
1828 | CONFLICT (DIV, MACC); | |
1829 | CONFLICT (DIV, DMACC); | |
1830 | ||
1831 | #undef CONFLICT | |
1832 | } | |
1833 | ||
707bfff6 TS |
1834 | struct regname { |
1835 | const char *name; | |
1836 | unsigned int num; | |
1837 | }; | |
1838 | ||
1839 | #define RTYPE_MASK 0x1ff00 | |
1840 | #define RTYPE_NUM 0x00100 | |
1841 | #define RTYPE_FPU 0x00200 | |
1842 | #define RTYPE_FCC 0x00400 | |
1843 | #define RTYPE_VEC 0x00800 | |
1844 | #define RTYPE_GP 0x01000 | |
1845 | #define RTYPE_CP0 0x02000 | |
1846 | #define RTYPE_PC 0x04000 | |
1847 | #define RTYPE_ACC 0x08000 | |
1848 | #define RTYPE_CCC 0x10000 | |
1849 | #define RNUM_MASK 0x000ff | |
1850 | #define RWARN 0x80000 | |
1851 | ||
1852 | #define GENERIC_REGISTER_NUMBERS \ | |
1853 | {"$0", RTYPE_NUM | 0}, \ | |
1854 | {"$1", RTYPE_NUM | 1}, \ | |
1855 | {"$2", RTYPE_NUM | 2}, \ | |
1856 | {"$3", RTYPE_NUM | 3}, \ | |
1857 | {"$4", RTYPE_NUM | 4}, \ | |
1858 | {"$5", RTYPE_NUM | 5}, \ | |
1859 | {"$6", RTYPE_NUM | 6}, \ | |
1860 | {"$7", RTYPE_NUM | 7}, \ | |
1861 | {"$8", RTYPE_NUM | 8}, \ | |
1862 | {"$9", RTYPE_NUM | 9}, \ | |
1863 | {"$10", RTYPE_NUM | 10}, \ | |
1864 | {"$11", RTYPE_NUM | 11}, \ | |
1865 | {"$12", RTYPE_NUM | 12}, \ | |
1866 | {"$13", RTYPE_NUM | 13}, \ | |
1867 | {"$14", RTYPE_NUM | 14}, \ | |
1868 | {"$15", RTYPE_NUM | 15}, \ | |
1869 | {"$16", RTYPE_NUM | 16}, \ | |
1870 | {"$17", RTYPE_NUM | 17}, \ | |
1871 | {"$18", RTYPE_NUM | 18}, \ | |
1872 | {"$19", RTYPE_NUM | 19}, \ | |
1873 | {"$20", RTYPE_NUM | 20}, \ | |
1874 | {"$21", RTYPE_NUM | 21}, \ | |
1875 | {"$22", RTYPE_NUM | 22}, \ | |
1876 | {"$23", RTYPE_NUM | 23}, \ | |
1877 | {"$24", RTYPE_NUM | 24}, \ | |
1878 | {"$25", RTYPE_NUM | 25}, \ | |
1879 | {"$26", RTYPE_NUM | 26}, \ | |
1880 | {"$27", RTYPE_NUM | 27}, \ | |
1881 | {"$28", RTYPE_NUM | 28}, \ | |
1882 | {"$29", RTYPE_NUM | 29}, \ | |
1883 | {"$30", RTYPE_NUM | 30}, \ | |
1884 | {"$31", RTYPE_NUM | 31} | |
1885 | ||
1886 | #define FPU_REGISTER_NAMES \ | |
1887 | {"$f0", RTYPE_FPU | 0}, \ | |
1888 | {"$f1", RTYPE_FPU | 1}, \ | |
1889 | {"$f2", RTYPE_FPU | 2}, \ | |
1890 | {"$f3", RTYPE_FPU | 3}, \ | |
1891 | {"$f4", RTYPE_FPU | 4}, \ | |
1892 | {"$f5", RTYPE_FPU | 5}, \ | |
1893 | {"$f6", RTYPE_FPU | 6}, \ | |
1894 | {"$f7", RTYPE_FPU | 7}, \ | |
1895 | {"$f8", RTYPE_FPU | 8}, \ | |
1896 | {"$f9", RTYPE_FPU | 9}, \ | |
1897 | {"$f10", RTYPE_FPU | 10}, \ | |
1898 | {"$f11", RTYPE_FPU | 11}, \ | |
1899 | {"$f12", RTYPE_FPU | 12}, \ | |
1900 | {"$f13", RTYPE_FPU | 13}, \ | |
1901 | {"$f14", RTYPE_FPU | 14}, \ | |
1902 | {"$f15", RTYPE_FPU | 15}, \ | |
1903 | {"$f16", RTYPE_FPU | 16}, \ | |
1904 | {"$f17", RTYPE_FPU | 17}, \ | |
1905 | {"$f18", RTYPE_FPU | 18}, \ | |
1906 | {"$f19", RTYPE_FPU | 19}, \ | |
1907 | {"$f20", RTYPE_FPU | 20}, \ | |
1908 | {"$f21", RTYPE_FPU | 21}, \ | |
1909 | {"$f22", RTYPE_FPU | 22}, \ | |
1910 | {"$f23", RTYPE_FPU | 23}, \ | |
1911 | {"$f24", RTYPE_FPU | 24}, \ | |
1912 | {"$f25", RTYPE_FPU | 25}, \ | |
1913 | {"$f26", RTYPE_FPU | 26}, \ | |
1914 | {"$f27", RTYPE_FPU | 27}, \ | |
1915 | {"$f28", RTYPE_FPU | 28}, \ | |
1916 | {"$f29", RTYPE_FPU | 29}, \ | |
1917 | {"$f30", RTYPE_FPU | 30}, \ | |
1918 | {"$f31", RTYPE_FPU | 31} | |
1919 | ||
1920 | #define FPU_CONDITION_CODE_NAMES \ | |
1921 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1922 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1923 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1924 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1925 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1926 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1927 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1928 | {"$fcc7", RTYPE_FCC | 7} | |
1929 | ||
1930 | #define COPROC_CONDITION_CODE_NAMES \ | |
1931 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1932 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1933 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1934 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1935 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1936 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1937 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1938 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1939 | ||
1940 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1941 | {"$a4", RTYPE_GP | 8}, \ | |
1942 | {"$a5", RTYPE_GP | 9}, \ | |
1943 | {"$a6", RTYPE_GP | 10}, \ | |
1944 | {"$a7", RTYPE_GP | 11}, \ | |
1945 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1946 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1947 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1948 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1949 | {"$t0", RTYPE_GP | 12}, \ | |
1950 | {"$t1", RTYPE_GP | 13}, \ | |
1951 | {"$t2", RTYPE_GP | 14}, \ | |
1952 | {"$t3", RTYPE_GP | 15} | |
1953 | ||
1954 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1955 | {"$t0", RTYPE_GP | 8}, \ | |
1956 | {"$t1", RTYPE_GP | 9}, \ | |
1957 | {"$t2", RTYPE_GP | 10}, \ | |
1958 | {"$t3", RTYPE_GP | 11}, \ | |
1959 | {"$t4", RTYPE_GP | 12}, \ | |
1960 | {"$t5", RTYPE_GP | 13}, \ | |
1961 | {"$t6", RTYPE_GP | 14}, \ | |
1962 | {"$t7", RTYPE_GP | 15}, \ | |
1963 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1964 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1965 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1966 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1967 | ||
1968 | /* Remaining symbolic register names */ | |
1969 | #define SYMBOLIC_REGISTER_NAMES \ | |
1970 | {"$zero", RTYPE_GP | 0}, \ | |
1971 | {"$at", RTYPE_GP | 1}, \ | |
1972 | {"$AT", RTYPE_GP | 1}, \ | |
1973 | {"$v0", RTYPE_GP | 2}, \ | |
1974 | {"$v1", RTYPE_GP | 3}, \ | |
1975 | {"$a0", RTYPE_GP | 4}, \ | |
1976 | {"$a1", RTYPE_GP | 5}, \ | |
1977 | {"$a2", RTYPE_GP | 6}, \ | |
1978 | {"$a3", RTYPE_GP | 7}, \ | |
1979 | {"$s0", RTYPE_GP | 16}, \ | |
1980 | {"$s1", RTYPE_GP | 17}, \ | |
1981 | {"$s2", RTYPE_GP | 18}, \ | |
1982 | {"$s3", RTYPE_GP | 19}, \ | |
1983 | {"$s4", RTYPE_GP | 20}, \ | |
1984 | {"$s5", RTYPE_GP | 21}, \ | |
1985 | {"$s6", RTYPE_GP | 22}, \ | |
1986 | {"$s7", RTYPE_GP | 23}, \ | |
1987 | {"$t8", RTYPE_GP | 24}, \ | |
1988 | {"$t9", RTYPE_GP | 25}, \ | |
1989 | {"$k0", RTYPE_GP | 26}, \ | |
1990 | {"$kt0", RTYPE_GP | 26}, \ | |
1991 | {"$k1", RTYPE_GP | 27}, \ | |
1992 | {"$kt1", RTYPE_GP | 27}, \ | |
1993 | {"$gp", RTYPE_GP | 28}, \ | |
1994 | {"$sp", RTYPE_GP | 29}, \ | |
1995 | {"$s8", RTYPE_GP | 30}, \ | |
1996 | {"$fp", RTYPE_GP | 30}, \ | |
1997 | {"$ra", RTYPE_GP | 31} | |
1998 | ||
1999 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2000 | {"$pc", RTYPE_PC | 0} | |
2001 | ||
2002 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2003 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2004 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2005 | {"$v2", RTYPE_VEC | 2}, \ | |
2006 | {"$v3", RTYPE_VEC | 3}, \ | |
2007 | {"$v4", RTYPE_VEC | 4}, \ | |
2008 | {"$v5", RTYPE_VEC | 5}, \ | |
2009 | {"$v6", RTYPE_VEC | 6}, \ | |
2010 | {"$v7", RTYPE_VEC | 7}, \ | |
2011 | {"$v8", RTYPE_VEC | 8}, \ | |
2012 | {"$v9", RTYPE_VEC | 9}, \ | |
2013 | {"$v10", RTYPE_VEC | 10}, \ | |
2014 | {"$v11", RTYPE_VEC | 11}, \ | |
2015 | {"$v12", RTYPE_VEC | 12}, \ | |
2016 | {"$v13", RTYPE_VEC | 13}, \ | |
2017 | {"$v14", RTYPE_VEC | 14}, \ | |
2018 | {"$v15", RTYPE_VEC | 15}, \ | |
2019 | {"$v16", RTYPE_VEC | 16}, \ | |
2020 | {"$v17", RTYPE_VEC | 17}, \ | |
2021 | {"$v18", RTYPE_VEC | 18}, \ | |
2022 | {"$v19", RTYPE_VEC | 19}, \ | |
2023 | {"$v20", RTYPE_VEC | 20}, \ | |
2024 | {"$v21", RTYPE_VEC | 21}, \ | |
2025 | {"$v22", RTYPE_VEC | 22}, \ | |
2026 | {"$v23", RTYPE_VEC | 23}, \ | |
2027 | {"$v24", RTYPE_VEC | 24}, \ | |
2028 | {"$v25", RTYPE_VEC | 25}, \ | |
2029 | {"$v26", RTYPE_VEC | 26}, \ | |
2030 | {"$v27", RTYPE_VEC | 27}, \ | |
2031 | {"$v28", RTYPE_VEC | 28}, \ | |
2032 | {"$v29", RTYPE_VEC | 29}, \ | |
2033 | {"$v30", RTYPE_VEC | 30}, \ | |
2034 | {"$v31", RTYPE_VEC | 31} | |
2035 | ||
2036 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2037 | {"$ac0", RTYPE_ACC | 0}, \ | |
2038 | {"$ac1", RTYPE_ACC | 1}, \ | |
2039 | {"$ac2", RTYPE_ACC | 2}, \ | |
2040 | {"$ac3", RTYPE_ACC | 3} | |
2041 | ||
2042 | static const struct regname reg_names[] = { | |
2043 | GENERIC_REGISTER_NUMBERS, | |
2044 | FPU_REGISTER_NAMES, | |
2045 | FPU_CONDITION_CODE_NAMES, | |
2046 | COPROC_CONDITION_CODE_NAMES, | |
2047 | ||
2048 | /* The $txx registers depends on the abi, | |
2049 | these will be added later into the symbol table from | |
2050 | one of the tables below once mips_abi is set after | |
2051 | parsing of arguments from the command line. */ | |
2052 | SYMBOLIC_REGISTER_NAMES, | |
2053 | ||
2054 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2055 | MDMX_VECTOR_REGISTER_NAMES, | |
2056 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2057 | {0, 0} | |
2058 | }; | |
2059 | ||
2060 | static const struct regname reg_names_o32[] = { | |
2061 | O32_SYMBOLIC_REGISTER_NAMES, | |
2062 | {0, 0} | |
2063 | }; | |
2064 | ||
2065 | static const struct regname reg_names_n32n64[] = { | |
2066 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2067 | {0, 0} | |
2068 | }; | |
2069 | ||
df58fc94 RS |
2070 | /* Check if S points at a valid register specifier according to TYPES. |
2071 | If so, then return 1, advance S to consume the specifier and store | |
2072 | the register's number in REGNOP, otherwise return 0. */ | |
2073 | ||
707bfff6 TS |
2074 | static int |
2075 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2076 | { | |
2077 | symbolS *symbolP; | |
2078 | char *e; | |
2079 | char save_c; | |
2080 | int reg = -1; | |
2081 | ||
2082 | /* Find end of name. */ | |
2083 | e = *s; | |
2084 | if (is_name_beginner (*e)) | |
2085 | ++e; | |
2086 | while (is_part_of_name (*e)) | |
2087 | ++e; | |
2088 | ||
2089 | /* Terminate name. */ | |
2090 | save_c = *e; | |
2091 | *e = '\0'; | |
2092 | ||
2093 | /* Look for a register symbol. */ | |
2094 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2095 | { | |
2096 | int r = S_GET_VALUE (symbolP); | |
2097 | if (r & types) | |
2098 | reg = r & RNUM_MASK; | |
2099 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2100 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2101 | reg = (r & RNUM_MASK) - 2; | |
2102 | } | |
2103 | /* Else see if this is a register defined in an itbl entry. */ | |
2104 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2105 | { | |
2106 | char *n = *s; | |
2107 | unsigned long r; | |
2108 | ||
2109 | if (*n == '$') | |
2110 | ++n; | |
2111 | if (itbl_get_reg_val (n, &r)) | |
2112 | reg = r & RNUM_MASK; | |
2113 | } | |
2114 | ||
2115 | /* Advance to next token if a register was recognised. */ | |
2116 | if (reg >= 0) | |
2117 | *s = e; | |
2118 | else if (types & RWARN) | |
20203fb9 | 2119 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2120 | |
2121 | *e = save_c; | |
2122 | if (regnop) | |
2123 | *regnop = reg; | |
2124 | return reg >= 0; | |
2125 | } | |
2126 | ||
df58fc94 RS |
2127 | /* Check if S points at a valid register list according to TYPES. |
2128 | If so, then return 1, advance S to consume the list and store | |
2129 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2130 | otherwise return 0. A valid list comprises a comma-separated | |
2131 | enumeration of valid single registers and/or dash-separated | |
2132 | contiguous register ranges as determined by their numbers. | |
2133 | ||
2134 | As a special exception if one of s0-s7 registers is specified as | |
2135 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2136 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2137 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2138 | |
2139 | static int | |
2140 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2141 | { | |
2142 | unsigned int reglist = 0; | |
2143 | unsigned int lastregno; | |
2144 | bfd_boolean ok = TRUE; | |
2145 | unsigned int regmask; | |
2309ddf2 | 2146 | char *s_endlist = *s; |
df58fc94 | 2147 | char *s_reset = *s; |
2309ddf2 | 2148 | unsigned int regno; |
df58fc94 RS |
2149 | |
2150 | while (reg_lookup (s, types, ®no)) | |
2151 | { | |
2152 | lastregno = regno; | |
2153 | if (**s == '-') | |
2154 | { | |
2155 | (*s)++; | |
2156 | ok = reg_lookup (s, types, &lastregno); | |
2157 | if (ok && lastregno < regno) | |
2158 | ok = FALSE; | |
2159 | if (!ok) | |
2160 | break; | |
2161 | } | |
2162 | ||
2163 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2164 | { | |
2165 | lastregno = S7; | |
2166 | reglist |= 1 << FP; | |
2167 | } | |
2168 | regmask = 1 << lastregno; | |
2169 | regmask = (regmask << 1) - 1; | |
2170 | regmask ^= (1 << regno) - 1; | |
2171 | reglist |= regmask; | |
2172 | ||
2309ddf2 | 2173 | s_endlist = *s; |
df58fc94 RS |
2174 | if (**s != ',') |
2175 | break; | |
2176 | (*s)++; | |
2177 | } | |
2178 | ||
2179 | if (ok) | |
2309ddf2 | 2180 | *s = s_endlist; |
df58fc94 RS |
2181 | else |
2182 | *s = s_reset; | |
2183 | if (reglistp) | |
2184 | *reglistp = reglist; | |
2185 | return ok && reglist != 0; | |
2186 | } | |
2187 | ||
037b32b9 | 2188 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2189 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2190 | |
2191 | static bfd_boolean | |
f79e2745 | 2192 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2193 | { |
2194 | int isa = mips_opts.isa; | |
2195 | int fp_s, fp_d; | |
2196 | ||
2197 | if (mips_opts.ase_mdmx) | |
2198 | isa |= INSN_MDMX; | |
2199 | if (mips_opts.ase_dsp) | |
2200 | isa |= INSN_DSP; | |
2201 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2202 | isa |= INSN_DSP64; | |
2203 | if (mips_opts.ase_dspr2) | |
2204 | isa |= INSN_DSPR2; | |
2205 | if (mips_opts.ase_mt) | |
2206 | isa |= INSN_MT; | |
2207 | if (mips_opts.ase_mips3d) | |
2208 | isa |= INSN_MIPS3D; | |
2209 | if (mips_opts.ase_smartmips) | |
2210 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2211 | if (mips_opts.ase_mcu) |
2212 | isa |= INSN_MCU; | |
037b32b9 | 2213 | |
b19e8a9b AN |
2214 | /* Don't accept instructions based on the ISA if the CPU does not implement |
2215 | all the coprocessor insns. */ | |
2216 | if (NO_ISA_COP (mips_opts.arch) | |
2217 | && COP_INSN (mo->pinfo)) | |
2218 | isa = 0; | |
2219 | ||
037b32b9 AN |
2220 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
2221 | return FALSE; | |
2222 | ||
2223 | /* Check whether the instruction or macro requires single-precision or | |
2224 | double-precision floating-point support. Note that this information is | |
2225 | stored differently in the opcode table for insns and macros. */ | |
2226 | if (mo->pinfo == INSN_MACRO) | |
2227 | { | |
2228 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2229 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | fp_s = mo->pinfo & FP_S; | |
2234 | fp_d = mo->pinfo & FP_D; | |
2235 | } | |
2236 | ||
2237 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2238 | return FALSE; | |
2239 | ||
2240 | if (fp_s && mips_opts.soft_float) | |
2241 | return FALSE; | |
2242 | ||
2243 | return TRUE; | |
2244 | } | |
2245 | ||
2246 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2247 | selected ISA and architecture. */ | |
2248 | ||
2249 | static bfd_boolean | |
2250 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2251 | { | |
2252 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
2253 | } | |
2254 | ||
df58fc94 RS |
2255 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2256 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2257 | ||
2258 | static bfd_boolean | |
2259 | is_size_valid (const struct mips_opcode *mo) | |
2260 | { | |
2261 | if (!mips_opts.micromips) | |
2262 | return TRUE; | |
2263 | ||
2264 | if (!forced_insn_length) | |
2265 | return TRUE; | |
2266 | if (mo->pinfo == INSN_MACRO) | |
2267 | return FALSE; | |
2268 | return forced_insn_length == micromips_insn_length (mo); | |
2269 | } | |
2270 | ||
2271 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2272 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2273 | ||
2274 | static bfd_boolean | |
2275 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2276 | { | |
2277 | if (!mips_opts.micromips) | |
2278 | return TRUE; | |
2279 | ||
2280 | if (mo->pinfo == INSN_MACRO) | |
2281 | return TRUE; | |
2282 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2283 | && micromips_insn_length (mo) != 4) | |
2284 | return FALSE; | |
2285 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2286 | && micromips_insn_length (mo) != 2) | |
2287 | return FALSE; | |
2288 | ||
2289 | return TRUE; | |
2290 | } | |
2291 | ||
707bfff6 TS |
2292 | /* This function is called once, at assembler startup time. It should set up |
2293 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2294 | |
252b5132 | 2295 | void |
17a2f251 | 2296 | md_begin (void) |
252b5132 | 2297 | { |
3994f87e | 2298 | const char *retval = NULL; |
156c2f8b | 2299 | int i = 0; |
252b5132 | 2300 | int broken = 0; |
1f25f5d3 | 2301 | |
0a44bf69 RS |
2302 | if (mips_pic != NO_PIC) |
2303 | { | |
2304 | if (g_switch_seen && g_switch_value != 0) | |
2305 | as_bad (_("-G may not be used in position-independent code")); | |
2306 | g_switch_value = 0; | |
2307 | } | |
2308 | ||
fef14a42 | 2309 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2310 | as_warn (_("Could not set architecture and machine")); |
2311 | ||
252b5132 RH |
2312 | op_hash = hash_new (); |
2313 | ||
2314 | for (i = 0; i < NUMOPCODES;) | |
2315 | { | |
2316 | const char *name = mips_opcodes[i].name; | |
2317 | ||
17a2f251 | 2318 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2319 | if (retval != NULL) |
2320 | { | |
2321 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2322 | mips_opcodes[i].name, retval); | |
2323 | /* Probably a memory allocation problem? Give up now. */ | |
2324 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2325 | } | |
2326 | do | |
2327 | { | |
2328 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2329 | { | |
2330 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2331 | broken = 1; | |
1e915849 RS |
2332 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2333 | { | |
2334 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2335 | if (mips_fix_loongson2f_nop) |
2336 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2337 | nop_insn.fixed_p = 1; |
2338 | } | |
252b5132 RH |
2339 | } |
2340 | ++i; | |
2341 | } | |
2342 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2343 | } | |
2344 | ||
2345 | mips16_op_hash = hash_new (); | |
2346 | ||
2347 | i = 0; | |
2348 | while (i < bfd_mips16_num_opcodes) | |
2349 | { | |
2350 | const char *name = mips16_opcodes[i].name; | |
2351 | ||
17a2f251 | 2352 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2353 | if (retval != NULL) |
2354 | as_fatal (_("internal: can't hash `%s': %s"), | |
2355 | mips16_opcodes[i].name, retval); | |
2356 | do | |
2357 | { | |
2358 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2359 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2360 | != mips16_opcodes[i].match)) | |
2361 | { | |
2362 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2363 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2364 | broken = 1; | |
2365 | } | |
1e915849 RS |
2366 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2367 | { | |
2368 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2369 | mips16_nop_insn.fixed_p = 1; | |
2370 | } | |
252b5132 RH |
2371 | ++i; |
2372 | } | |
2373 | while (i < bfd_mips16_num_opcodes | |
2374 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2375 | } | |
2376 | ||
df58fc94 RS |
2377 | micromips_op_hash = hash_new (); |
2378 | ||
2379 | i = 0; | |
2380 | while (i < bfd_micromips_num_opcodes) | |
2381 | { | |
2382 | const char *name = micromips_opcodes[i].name; | |
2383 | ||
2384 | retval = hash_insert (micromips_op_hash, name, | |
2385 | (void *) µmips_opcodes[i]); | |
2386 | if (retval != NULL) | |
2387 | as_fatal (_("internal: can't hash `%s': %s"), | |
2388 | micromips_opcodes[i].name, retval); | |
2389 | do | |
2390 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2391 | { | |
2392 | struct mips_cl_insn *micromips_nop_insn; | |
2393 | ||
2394 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2395 | broken = 1; | |
2396 | ||
2397 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2398 | micromips_nop_insn = µmips_nop16_insn; | |
2399 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2400 | micromips_nop_insn = µmips_nop32_insn; | |
2401 | else | |
2402 | continue; | |
2403 | ||
2404 | if (micromips_nop_insn->insn_mo == NULL | |
2405 | && strcmp (name, "nop") == 0) | |
2406 | { | |
2407 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2408 | micromips_nop_insn->fixed_p = 1; | |
2409 | } | |
2410 | } | |
2411 | while (++i < bfd_micromips_num_opcodes | |
2412 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2413 | } | |
2414 | ||
252b5132 RH |
2415 | if (broken) |
2416 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2417 | ||
2418 | /* We add all the general register names to the symbol table. This | |
2419 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2420 | for (i = 0; reg_names[i].name; i++) |
2421 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2422 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2423 | &zero_address_frag)); |
2424 | if (HAVE_NEWABI) | |
2425 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2426 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2427 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2428 | &zero_address_frag)); |
707bfff6 TS |
2429 | else |
2430 | for (i = 0; reg_names_o32[i].name; i++) | |
2431 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2432 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2433 | &zero_address_frag)); |
6047c971 | 2434 | |
7d10b47d | 2435 | mips_no_prev_insn (); |
252b5132 RH |
2436 | |
2437 | mips_gprmask = 0; | |
2438 | mips_cprmask[0] = 0; | |
2439 | mips_cprmask[1] = 0; | |
2440 | mips_cprmask[2] = 0; | |
2441 | mips_cprmask[3] = 0; | |
2442 | ||
2443 | /* set the default alignment for the text section (2**2) */ | |
2444 | record_alignment (text_section, 2); | |
2445 | ||
4d0d148d | 2446 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2447 | |
707bfff6 | 2448 | #ifdef OBJ_ELF |
f43abd2b | 2449 | if (IS_ELF) |
252b5132 | 2450 | { |
0a44bf69 RS |
2451 | /* On a native system other than VxWorks, sections must be aligned |
2452 | to 16 byte boundaries. When configured for an embedded ELF | |
2453 | target, we don't bother. */ | |
c41e87e3 CF |
2454 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2455 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2456 | { |
2457 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2458 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2459 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2460 | } | |
2461 | ||
2462 | /* Create a .reginfo section for register masks and a .mdebug | |
2463 | section for debugging information. */ | |
2464 | { | |
2465 | segT seg; | |
2466 | subsegT subseg; | |
2467 | flagword flags; | |
2468 | segT sec; | |
2469 | ||
2470 | seg = now_seg; | |
2471 | subseg = now_subseg; | |
2472 | ||
2473 | /* The ABI says this section should be loaded so that the | |
2474 | running program can access it. However, we don't load it | |
2475 | if we are configured for an embedded target */ | |
2476 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2477 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2478 | flags |= SEC_ALLOC | SEC_LOAD; |
2479 | ||
316f5878 | 2480 | if (mips_abi != N64_ABI) |
252b5132 RH |
2481 | { |
2482 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2483 | ||
195325d2 TS |
2484 | bfd_set_section_flags (stdoutput, sec, flags); |
2485 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2486 | |
252b5132 | 2487 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2488 | } |
2489 | else | |
2490 | { | |
2491 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2492 | .reginfo section. */ | |
2493 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2494 | bfd_set_section_flags (stdoutput, sec, flags); |
2495 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2496 | |
252b5132 RH |
2497 | /* Set up the option header. */ |
2498 | { | |
2499 | Elf_Internal_Options opthdr; | |
2500 | char *f; | |
2501 | ||
2502 | opthdr.kind = ODK_REGINFO; | |
2503 | opthdr.size = (sizeof (Elf_External_Options) | |
2504 | + sizeof (Elf64_External_RegInfo)); | |
2505 | opthdr.section = 0; | |
2506 | opthdr.info = 0; | |
2507 | f = frag_more (sizeof (Elf_External_Options)); | |
2508 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2509 | (Elf_External_Options *) f); | |
2510 | ||
2511 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2512 | } | |
252b5132 RH |
2513 | } |
2514 | ||
2515 | if (ECOFF_DEBUGGING) | |
2516 | { | |
2517 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2518 | (void) bfd_set_section_flags (stdoutput, sec, | |
2519 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2520 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2521 | } | |
f43abd2b | 2522 | else if (mips_flag_pdr) |
ecb4347a DJ |
2523 | { |
2524 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2525 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2526 | SEC_READONLY | SEC_RELOC | |
2527 | | SEC_DEBUGGING); | |
2528 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2529 | } | |
252b5132 RH |
2530 | |
2531 | subseg_set (seg, subseg); | |
2532 | } | |
2533 | } | |
707bfff6 | 2534 | #endif /* OBJ_ELF */ |
252b5132 RH |
2535 | |
2536 | if (! ECOFF_DEBUGGING) | |
2537 | md_obj_begin (); | |
71400594 RS |
2538 | |
2539 | if (mips_fix_vr4120) | |
2540 | init_vr4120_conflicts (); | |
252b5132 RH |
2541 | } |
2542 | ||
2543 | void | |
17a2f251 | 2544 | md_mips_end (void) |
252b5132 | 2545 | { |
02b1ab82 | 2546 | mips_emit_delays (); |
252b5132 RH |
2547 | if (! ECOFF_DEBUGGING) |
2548 | md_obj_end (); | |
2549 | } | |
2550 | ||
2551 | void | |
17a2f251 | 2552 | md_assemble (char *str) |
252b5132 RH |
2553 | { |
2554 | struct mips_cl_insn insn; | |
f6688943 TS |
2555 | bfd_reloc_code_real_type unused_reloc[3] |
2556 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2557 | |
2558 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2559 | imm2_expr.X_op = O_absent; |
252b5132 | 2560 | offset_expr.X_op = O_absent; |
f6688943 TS |
2561 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2562 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2563 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2564 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2565 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2566 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2567 | |
2568 | if (mips_opts.mips16) | |
2569 | mips16_ip (str, &insn); | |
2570 | else | |
2571 | { | |
2572 | mips_ip (str, &insn); | |
beae10d5 KH |
2573 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2574 | str, insn.insn_opcode)); | |
252b5132 RH |
2575 | } |
2576 | ||
2577 | if (insn_error) | |
2578 | { | |
2579 | as_bad ("%s `%s'", insn_error, str); | |
2580 | return; | |
2581 | } | |
2582 | ||
2583 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2584 | { | |
584892a6 | 2585 | macro_start (); |
252b5132 RH |
2586 | if (mips_opts.mips16) |
2587 | mips16_macro (&insn); | |
2588 | else | |
2589 | macro (&insn); | |
584892a6 | 2590 | macro_end (); |
252b5132 RH |
2591 | } |
2592 | else | |
2593 | { | |
2594 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2595 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2596 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2597 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2598 | else |
df58fc94 | 2599 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2600 | } |
2601 | } | |
2602 | ||
738e5348 RS |
2603 | /* Convenience functions for abstracting away the differences between |
2604 | MIPS16 and non-MIPS16 relocations. */ | |
2605 | ||
2606 | static inline bfd_boolean | |
2607 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2608 | { | |
2609 | switch (reloc) | |
2610 | { | |
2611 | case BFD_RELOC_MIPS16_JMP: | |
2612 | case BFD_RELOC_MIPS16_GPREL: | |
2613 | case BFD_RELOC_MIPS16_GOT16: | |
2614 | case BFD_RELOC_MIPS16_CALL16: | |
2615 | case BFD_RELOC_MIPS16_HI16_S: | |
2616 | case BFD_RELOC_MIPS16_HI16: | |
2617 | case BFD_RELOC_MIPS16_LO16: | |
2618 | return TRUE; | |
2619 | ||
2620 | default: | |
2621 | return FALSE; | |
2622 | } | |
2623 | } | |
2624 | ||
df58fc94 RS |
2625 | static inline bfd_boolean |
2626 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2627 | { | |
2628 | switch (reloc) | |
2629 | { | |
2630 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2631 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2632 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2633 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2634 | case BFD_RELOC_MICROMIPS_JMP: | |
2635 | case BFD_RELOC_MICROMIPS_HI16: | |
2636 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2637 | case BFD_RELOC_MICROMIPS_LO16: | |
2638 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2639 | case BFD_RELOC_MICROMIPS_GOT16: | |
2640 | case BFD_RELOC_MICROMIPS_CALL16: | |
2641 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2642 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2643 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2644 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2645 | case BFD_RELOC_MICROMIPS_SUB: | |
2646 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2647 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2648 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2649 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2650 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2651 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2652 | case BFD_RELOC_MICROMIPS_JALR: | |
2653 | return TRUE; | |
2654 | ||
2655 | default: | |
2656 | return FALSE; | |
2657 | } | |
2658 | } | |
2659 | ||
2309ddf2 MR |
2660 | static inline bfd_boolean |
2661 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2662 | { | |
2663 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2664 | } | |
2665 | ||
738e5348 RS |
2666 | static inline bfd_boolean |
2667 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2668 | { | |
2309ddf2 | 2669 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2670 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2671 | } |
2672 | ||
2673 | static inline bfd_boolean | |
2674 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2675 | { | |
2309ddf2 | 2676 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2677 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2678 | } |
2679 | ||
2680 | static inline bfd_boolean | |
2681 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2682 | { | |
2309ddf2 | 2683 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2684 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2685 | } | |
2686 | ||
df58fc94 RS |
2687 | static inline bfd_boolean |
2688 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2689 | { | |
2309ddf2 | 2690 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2691 | } |
2692 | ||
5919d012 | 2693 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2694 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2695 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2696 | |
2697 | static inline bfd_boolean | |
17a2f251 | 2698 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2699 | { |
3b91255e | 2700 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2701 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2702 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2703 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2704 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2705 | } | |
2706 | ||
2707 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2708 | reloc_needs_lo_p. */ | |
2709 | ||
2710 | static inline bfd_reloc_code_real_type | |
2711 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2712 | { | |
df58fc94 RS |
2713 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2714 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2715 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2716 | } |
2717 | ||
2718 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2719 | relocation. */ | |
2720 | ||
2721 | static inline bfd_boolean | |
17a2f251 | 2722 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2723 | { |
2724 | return (fixp->fx_next != NULL | |
738e5348 | 2725 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2726 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2727 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2728 | } | |
2729 | ||
252b5132 RH |
2730 | /* This function returns true if modifying a register requires a |
2731 | delay. */ | |
2732 | ||
2733 | static int | |
17a2f251 | 2734 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2735 | { |
2736 | unsigned long prev_pinfo; | |
2737 | ||
47e39b9d | 2738 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2739 | if (! mips_opts.noreorder |
81912461 ILT |
2740 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2741 | && ! gpr_interlocks) | |
2742 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2743 | && ! cop_interlocks))) | |
252b5132 | 2744 | { |
81912461 ILT |
2745 | /* A load from a coprocessor or from memory. All load delays |
2746 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2747 | /* Itbl support may require additional care here. */ |
252b5132 | 2748 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2749 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2750 | return 1; |
2751 | } | |
2752 | ||
2753 | return 0; | |
2754 | } | |
2755 | ||
404a8071 RS |
2756 | /* Move all labels in insn_labels to the current insertion point. */ |
2757 | ||
2758 | static void | |
2759 | mips_move_labels (void) | |
2760 | { | |
a8dbcb85 | 2761 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2762 | struct insn_label_list *l; |
2763 | valueT val; | |
2764 | ||
a8dbcb85 | 2765 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2766 | { |
9c2799c2 | 2767 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2768 | symbol_set_frag (l->label, frag_now); |
2769 | val = (valueT) frag_now_fix (); | |
df58fc94 RS |
2770 | /* MIPS16/microMIPS text labels are stored as odd. */ |
2771 | if (HAVE_CODE_COMPRESSION) | |
404a8071 RS |
2772 | ++val; |
2773 | S_SET_VALUE (l->label, val); | |
2774 | } | |
2775 | } | |
2776 | ||
5f0fe04b TS |
2777 | static bfd_boolean |
2778 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2779 | { | |
2780 | bfd_boolean linkonce = FALSE; | |
2781 | segT symseg = S_GET_SEGMENT (sym); | |
2782 | ||
2783 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2784 | { | |
2785 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2786 | linkonce = TRUE; | |
2787 | #ifdef OBJ_ELF | |
2788 | /* The GNU toolchain uses an extension for ELF: a section | |
2789 | beginning with the magic string .gnu.linkonce is a | |
2790 | linkonce section. */ | |
2791 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2792 | sizeof ".gnu.linkonce" - 1) == 0) | |
2793 | linkonce = TRUE; | |
2794 | #endif | |
2795 | } | |
2796 | return linkonce; | |
2797 | } | |
2798 | ||
df58fc94 RS |
2799 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2800 | linker to handle them specially, such as generating jalx instructions | |
2801 | when needed. We also make them odd for the duration of the assembly, | |
2802 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2803 | in the adjust_symtab routine, while leaving them marked. This is |
2804 | convenient for the debugger and the disassembler. The linker knows | |
2805 | to make them odd again. */ | |
2806 | ||
2807 | static void | |
df58fc94 | 2808 | mips_compressed_mark_labels (void) |
252b5132 | 2809 | { |
a8dbcb85 TS |
2810 | segment_info_type *si = seg_info (now_seg); |
2811 | struct insn_label_list *l; | |
252b5132 | 2812 | |
df58fc94 | 2813 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2814 | |
2815 | for (l = si->label_list; l != NULL; l = l->next) | |
2816 | { | |
2817 | symbolS *label = l->label; | |
2818 | ||
2819 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2820 | if (IS_ELF) |
df58fc94 RS |
2821 | { |
2822 | if (mips_opts.mips16) | |
2823 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2824 | else | |
2825 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2826 | } | |
252b5132 | 2827 | #endif |
5f0fe04b TS |
2828 | if ((S_GET_VALUE (label) & 1) == 0 |
2829 | /* Don't adjust the address if the label is global or weak, or | |
2830 | in a link-once section, since we'll be emitting symbol reloc | |
2831 | references to it which will be patched up by the linker, and | |
df58fc94 | 2832 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2833 | && ! S_IS_WEAK (label) |
2834 | && ! S_IS_EXTERNAL (label) | |
2835 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2836 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2837 | } |
2838 | } | |
2839 | ||
4d7206a2 RS |
2840 | /* End the current frag. Make it a variant frag and record the |
2841 | relaxation info. */ | |
2842 | ||
2843 | static void | |
2844 | relax_close_frag (void) | |
2845 | { | |
584892a6 | 2846 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2847 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2848 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2849 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2850 | ||
2851 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2852 | mips_relax.first_fixup = 0; | |
2853 | } | |
2854 | ||
2855 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2856 | See the comment above RELAX_ENCODE for more details. */ | |
2857 | ||
2858 | static void | |
2859 | relax_start (symbolS *symbol) | |
2860 | { | |
9c2799c2 | 2861 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2862 | mips_relax.sequence = 1; |
2863 | mips_relax.symbol = symbol; | |
2864 | } | |
2865 | ||
2866 | /* Start generating the second version of a relaxable sequence. | |
2867 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2868 | |
2869 | static void | |
4d7206a2 RS |
2870 | relax_switch (void) |
2871 | { | |
9c2799c2 | 2872 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2873 | mips_relax.sequence = 2; |
2874 | } | |
2875 | ||
2876 | /* End the current relaxable sequence. */ | |
2877 | ||
2878 | static void | |
2879 | relax_end (void) | |
2880 | { | |
9c2799c2 | 2881 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2882 | relax_close_frag (); |
2883 | mips_relax.sequence = 0; | |
2884 | } | |
2885 | ||
11625dd8 RS |
2886 | /* Return true if IP is a delayed branch or jump. */ |
2887 | ||
2888 | static inline bfd_boolean | |
2889 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2890 | { | |
2891 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2892 | | INSN_COND_BRANCH_DELAY | |
2893 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2894 | } | |
2895 | ||
2896 | /* Return true if IP is a compact branch or jump. */ | |
2897 | ||
2898 | static inline bfd_boolean | |
2899 | compact_branch_p (const struct mips_cl_insn *ip) | |
2900 | { | |
2901 | if (mips_opts.mips16) | |
2902 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2903 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2904 | else | |
2905 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2906 | | INSN2_COND_BRANCH)) != 0; | |
2907 | } | |
2908 | ||
2909 | /* Return true if IP is an unconditional branch or jump. */ | |
2910 | ||
2911 | static inline bfd_boolean | |
2912 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2913 | { | |
2914 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2915 | || (mips_opts.mips16 | |
2916 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2917 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2918 | } | |
2919 | ||
2920 | /* Return true if IP is a branch-likely instruction. */ | |
2921 | ||
2922 | static inline bfd_boolean | |
2923 | branch_likely_p (const struct mips_cl_insn *ip) | |
2924 | { | |
2925 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2926 | } | |
2927 | ||
14fe068b RS |
2928 | /* Return the type of nop that should be used to fill the delay slot |
2929 | of delayed branch IP. */ | |
2930 | ||
2931 | static struct mips_cl_insn * | |
2932 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2933 | { | |
2934 | if (mips_opts.micromips | |
2935 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2936 | return µmips_nop32_insn; | |
2937 | return NOP_INSN; | |
2938 | } | |
2939 | ||
2309ddf2 | 2940 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2941 | |
2942 | static unsigned int | |
2943 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2944 | { | |
2309ddf2 | 2945 | unsigned long pinfo2; |
df58fc94 RS |
2946 | unsigned int mask; |
2947 | ||
2948 | mask = 0; | |
df58fc94 RS |
2949 | pinfo2 = ip->insn_mo->pinfo2; |
2950 | if (mips_opts.micromips) | |
2951 | { | |
df58fc94 RS |
2952 | if (pinfo2 & INSN2_MOD_GPR_MD) |
2953 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
2954 | if (pinfo2 & INSN2_MOD_GPR_MF) |
2955 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
2956 | if (pinfo2 & INSN2_MOD_SP) |
2957 | mask |= 1 << SP; | |
2958 | } | |
2959 | return mask; | |
2960 | } | |
2961 | ||
4c260379 RS |
2962 | /* Return the mask of core registers that IP reads. */ |
2963 | ||
2964 | static unsigned int | |
2965 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2966 | { | |
2967 | unsigned long pinfo, pinfo2; | |
2968 | unsigned int mask; | |
2969 | ||
df58fc94 | 2970 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2971 | pinfo = ip->insn_mo->pinfo; |
2972 | pinfo2 = ip->insn_mo->pinfo2; | |
2973 | if (mips_opts.mips16) | |
2974 | { | |
2975 | if (pinfo & MIPS16_INSN_READ_X) | |
2976 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2977 | if (pinfo & MIPS16_INSN_READ_Y) | |
2978 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2979 | if (pinfo & MIPS16_INSN_READ_T) | |
2980 | mask |= 1 << TREG; | |
2981 | if (pinfo & MIPS16_INSN_READ_SP) | |
2982 | mask |= 1 << SP; | |
2983 | if (pinfo & MIPS16_INSN_READ_31) | |
2984 | mask |= 1 << RA; | |
2985 | if (pinfo & MIPS16_INSN_READ_Z) | |
2986 | mask |= 1 << (mips16_to_32_reg_map | |
2987 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2988 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2989 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2990 | } | |
2991 | else | |
2992 | { | |
2993 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 2994 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 2995 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 2996 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 2997 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
2998 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
2999 | if (pinfo2 & INSN2_READ_GP) | |
3000 | mask |= 1 << GP; | |
3001 | if (pinfo2 & INSN2_READ_GPR_31) | |
3002 | mask |= 1 << RA; | |
4c260379 | 3003 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3004 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3005 | } |
2b0c8b40 MR |
3006 | if (mips_opts.micromips) |
3007 | { | |
3008 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3009 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3010 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3011 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3012 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3013 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3014 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3015 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3016 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3017 | { | |
3018 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3019 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3020 | } | |
3021 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3022 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3023 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3024 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3025 | } | |
fe35f09f RS |
3026 | /* Don't include register 0. */ |
3027 | return mask & ~1; | |
4c260379 RS |
3028 | } |
3029 | ||
3030 | /* Return the mask of core registers that IP writes. */ | |
3031 | ||
3032 | static unsigned int | |
3033 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3034 | { | |
3035 | unsigned long pinfo, pinfo2; | |
3036 | unsigned int mask; | |
3037 | ||
df58fc94 | 3038 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3039 | pinfo = ip->insn_mo->pinfo; |
3040 | pinfo2 = ip->insn_mo->pinfo2; | |
3041 | if (mips_opts.mips16) | |
3042 | { | |
3043 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3044 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3045 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3046 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3047 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3048 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3049 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3050 | mask |= 1 << TREG; | |
3051 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3052 | mask |= 1 << SP; | |
3053 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3054 | mask |= 1 << RA; | |
3055 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3056 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3057 | } | |
3058 | else | |
3059 | { | |
3060 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3061 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3062 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3063 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3064 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3065 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3066 | if (pinfo & INSN_WRITE_GPR_31) |
3067 | mask |= 1 << RA; | |
3068 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3069 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3070 | } |
2b0c8b40 MR |
3071 | if (mips_opts.micromips) |
3072 | { | |
3073 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3074 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3075 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3076 | { | |
3077 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3078 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3079 | } | |
3080 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3081 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3082 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3083 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3084 | } | |
fe35f09f RS |
3085 | /* Don't include register 0. */ |
3086 | return mask & ~1; | |
4c260379 RS |
3087 | } |
3088 | ||
3089 | /* Return the mask of floating-point registers that IP reads. */ | |
3090 | ||
3091 | static unsigned int | |
3092 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3093 | { | |
3094 | unsigned long pinfo, pinfo2; | |
3095 | unsigned int mask; | |
3096 | ||
3097 | mask = 0; | |
3098 | pinfo = ip->insn_mo->pinfo; | |
3099 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3100 | if (!mips_opts.mips16) |
df58fc94 RS |
3101 | { |
3102 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3103 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3104 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3105 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3106 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3107 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3108 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3109 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3110 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3111 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3112 | } |
3113 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3114 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3115 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3116 | mask |= mask << 1; | |
3117 | return mask; | |
3118 | } | |
3119 | ||
3120 | /* Return the mask of floating-point registers that IP writes. */ | |
3121 | ||
3122 | static unsigned int | |
3123 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3124 | { | |
3125 | unsigned long pinfo, pinfo2; | |
3126 | unsigned int mask; | |
3127 | ||
3128 | mask = 0; | |
3129 | pinfo = ip->insn_mo->pinfo; | |
3130 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3131 | if (!mips_opts.mips16) |
4c260379 RS |
3132 | { |
3133 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3134 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3135 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3136 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3137 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3138 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3139 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3140 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3141 | } |
3142 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3143 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3144 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3145 | mask |= mask << 1; | |
3146 | return mask; | |
3147 | } | |
3148 | ||
71400594 RS |
3149 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3150 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3151 | by VR4120 errata. */ | |
4d7206a2 | 3152 | |
71400594 RS |
3153 | static unsigned int |
3154 | classify_vr4120_insn (const char *name) | |
252b5132 | 3155 | { |
71400594 RS |
3156 | if (strncmp (name, "macc", 4) == 0) |
3157 | return FIX_VR4120_MACC; | |
3158 | if (strncmp (name, "dmacc", 5) == 0) | |
3159 | return FIX_VR4120_DMACC; | |
3160 | if (strncmp (name, "mult", 4) == 0) | |
3161 | return FIX_VR4120_MULT; | |
3162 | if (strncmp (name, "dmult", 5) == 0) | |
3163 | return FIX_VR4120_DMULT; | |
3164 | if (strstr (name, "div")) | |
3165 | return FIX_VR4120_DIV; | |
3166 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3167 | return FIX_VR4120_MTHILO; | |
3168 | return NUM_FIX_VR4120_CLASSES; | |
3169 | } | |
252b5132 | 3170 | |
ff239038 CM |
3171 | #define INSN_ERET 0x42000018 |
3172 | #define INSN_DERET 0x4200001f | |
3173 | ||
71400594 RS |
3174 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3175 | where INSN1 is the earlier instruction. Return the worst-case value | |
3176 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3177 | |
71400594 RS |
3178 | static unsigned int |
3179 | insns_between (const struct mips_cl_insn *insn1, | |
3180 | const struct mips_cl_insn *insn2) | |
3181 | { | |
3182 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3183 | unsigned int mask; |
71400594 RS |
3184 | |
3185 | /* This function needs to know which pinfo flags are set for INSN2 | |
3186 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3187 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3188 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3189 | pinfo1 = insn1->insn_mo->pinfo; |
3190 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3191 | |
4c260379 RS |
3192 | #define INSN2_USES_GPR(REG) \ |
3193 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3194 | |
3195 | /* For most targets, write-after-read dependencies on the HI and LO | |
3196 | registers must be separated by at least two instructions. */ | |
3197 | if (!hilo_interlocks) | |
252b5132 | 3198 | { |
71400594 RS |
3199 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3200 | return 2; | |
3201 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3202 | return 2; | |
3203 | } | |
3204 | ||
3205 | /* If we're working around r7000 errata, there must be two instructions | |
3206 | between an mfhi or mflo and any instruction that uses the result. */ | |
3207 | if (mips_7000_hilo_fix | |
df58fc94 | 3208 | && !mips_opts.micromips |
71400594 | 3209 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3210 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3211 | return 2; |
3212 | ||
ff239038 CM |
3213 | /* If we're working around 24K errata, one instruction is required |
3214 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3215 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3216 | { |
3217 | if (insn1->insn_opcode == INSN_ERET | |
3218 | || insn1->insn_opcode == INSN_DERET) | |
3219 | { | |
3220 | if (insn2 == NULL | |
3221 | || insn2->insn_opcode == INSN_ERET | |
3222 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3223 | || delayed_branch_p (insn2)) |
ff239038 CM |
3224 | return 1; |
3225 | } | |
3226 | } | |
3227 | ||
71400594 RS |
3228 | /* If working around VR4120 errata, check for combinations that need |
3229 | a single intervening instruction. */ | |
df58fc94 | 3230 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3231 | { |
3232 | unsigned int class1, class2; | |
252b5132 | 3233 | |
71400594 RS |
3234 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3235 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3236 | { |
71400594 RS |
3237 | if (insn2 == NULL) |
3238 | return 1; | |
3239 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3240 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3241 | return 1; | |
252b5132 | 3242 | } |
71400594 RS |
3243 | } |
3244 | ||
df58fc94 | 3245 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3246 | { |
3247 | /* Check for GPR or coprocessor load delays. All such delays | |
3248 | are on the RT register. */ | |
3249 | /* Itbl support may require additional care here. */ | |
3250 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3251 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3252 | { |
71400594 | 3253 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3254 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3255 | return 1; |
3256 | } | |
3257 | ||
3258 | /* Check for generic coprocessor hazards. | |
3259 | ||
3260 | This case is not handled very well. There is no special | |
3261 | knowledge of CP0 handling, and the coprocessors other than | |
3262 | the floating point unit are not distinguished at all. */ | |
3263 | /* Itbl support may require additional care here. FIXME! | |
3264 | Need to modify this to include knowledge about | |
3265 | user specified delays! */ | |
3266 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3267 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3268 | { | |
3269 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3270 | register. There must be a one instruction delay before INSN2 | |
3271 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3272 | mask = fpr_write_mask (insn1); |
3273 | if (mask != 0) | |
252b5132 | 3274 | { |
4c260379 | 3275 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3276 | return 1; |
252b5132 RH |
3277 | } |
3278 | else | |
3279 | { | |
71400594 RS |
3280 | /* Read-after-write dependencies on the control registers |
3281 | require a two-instruction gap. */ | |
3282 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3283 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3284 | return 2; | |
3285 | ||
3286 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3287 | also a coprocessor instruction, assume there must be | |
3288 | a one instruction gap. */ | |
3289 | if (pinfo2 & INSN_COP) | |
3290 | return 1; | |
252b5132 RH |
3291 | } |
3292 | } | |
6b76fefe | 3293 | |
71400594 RS |
3294 | /* Check for read-after-write dependencies on the coprocessor |
3295 | control registers in cases where INSN1 does not need a general | |
3296 | coprocessor delay. This means that INSN1 is a floating point | |
3297 | comparison instruction. */ | |
3298 | /* Itbl support may require additional care here. */ | |
3299 | else if (!cop_interlocks | |
3300 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3301 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3302 | return 1; | |
3303 | } | |
6b76fefe | 3304 | |
4c260379 | 3305 | #undef INSN2_USES_GPR |
6b76fefe | 3306 | |
71400594 RS |
3307 | return 0; |
3308 | } | |
6b76fefe | 3309 | |
7d8e00cf RS |
3310 | /* Return the number of nops that would be needed to work around the |
3311 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3312 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3313 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3314 | |
3315 | static int | |
932d1a1b | 3316 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3317 | const struct mips_cl_insn *insn) |
3318 | { | |
4c260379 RS |
3319 | int i, j; |
3320 | unsigned int mask; | |
7d8e00cf RS |
3321 | |
3322 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3323 | are not affected by the errata. */ | |
3324 | if (insn != 0 | |
3325 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3326 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3327 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3328 | return 0; | |
3329 | ||
3330 | /* Search for the first MFLO or MFHI. */ | |
3331 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3332 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3333 | { |
3334 | /* Extract the destination register. */ | |
4c260379 | 3335 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3336 | |
3337 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3338 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3339 | return 0; |
3340 | ||
3341 | /* ...or if any of the intervening instructions do. */ | |
3342 | for (j = 0; j < i; j++) | |
4c260379 | 3343 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3344 | return 0; |
3345 | ||
932d1a1b RS |
3346 | if (i >= ignore) |
3347 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3348 | } |
3349 | return 0; | |
3350 | } | |
3351 | ||
15be625d CM |
3352 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3353 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3354 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3355 | ||
3356 | /* Return the minimum alignment for this store instruction. */ | |
3357 | ||
3358 | static int | |
3359 | fix_24k_align_to (const struct mips_opcode *mo) | |
3360 | { | |
3361 | if (strcmp (mo->name, "sh") == 0) | |
3362 | return 2; | |
3363 | ||
3364 | if (strcmp (mo->name, "swc1") == 0 | |
3365 | || strcmp (mo->name, "swc2") == 0 | |
3366 | || strcmp (mo->name, "sw") == 0 | |
3367 | || strcmp (mo->name, "sc") == 0 | |
3368 | || strcmp (mo->name, "s.s") == 0) | |
3369 | return 4; | |
3370 | ||
3371 | if (strcmp (mo->name, "sdc1") == 0 | |
3372 | || strcmp (mo->name, "sdc2") == 0 | |
3373 | || strcmp (mo->name, "s.d") == 0) | |
3374 | return 8; | |
3375 | ||
3376 | /* sb, swl, swr */ | |
3377 | return 1; | |
3378 | } | |
3379 | ||
3380 | struct fix_24k_store_info | |
3381 | { | |
3382 | /* Immediate offset, if any, for this store instruction. */ | |
3383 | short off; | |
3384 | /* Alignment required by this store instruction. */ | |
3385 | int align_to; | |
3386 | /* True for register offsets. */ | |
3387 | int register_offset; | |
3388 | }; | |
3389 | ||
3390 | /* Comparison function used by qsort. */ | |
3391 | ||
3392 | static int | |
3393 | fix_24k_sort (const void *a, const void *b) | |
3394 | { | |
3395 | const struct fix_24k_store_info *pos1 = a; | |
3396 | const struct fix_24k_store_info *pos2 = b; | |
3397 | ||
3398 | return (pos1->off - pos2->off); | |
3399 | } | |
3400 | ||
3401 | /* INSN is a store instruction. Try to record the store information | |
3402 | in STINFO. Return false if the information isn't known. */ | |
3403 | ||
3404 | static bfd_boolean | |
3405 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3406 | const struct mips_cl_insn *insn) |
15be625d CM |
3407 | { |
3408 | /* The instruction must have a known offset. */ | |
3409 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3410 | return FALSE; | |
3411 | ||
3412 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3413 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3414 | return TRUE; | |
3415 | } | |
3416 | ||
932d1a1b RS |
3417 | /* Return the number of nops that would be needed to work around the 24k |
3418 | "lost data on stores during refill" errata if instruction INSN | |
3419 | immediately followed the 2 instructions described by HIST. | |
3420 | Ignore hazards that are contained within the first IGNORE | |
3421 | instructions of HIST. | |
3422 | ||
3423 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3424 | for the data cache refills and store data. The following describes | |
3425 | the scenario where the store data could be lost. | |
3426 | ||
3427 | * A data cache miss, due to either a load or a store, causing fill | |
3428 | data to be supplied by the memory subsystem | |
3429 | * The first three doublewords of fill data are returned and written | |
3430 | into the cache | |
3431 | * A sequence of four stores occurs in consecutive cycles around the | |
3432 | final doubleword of the fill: | |
3433 | * Store A | |
3434 | * Store B | |
3435 | * Store C | |
3436 | * Zero, One or more instructions | |
3437 | * Store D | |
3438 | ||
3439 | The four stores A-D must be to different doublewords of the line that | |
3440 | is being filled. The fourth instruction in the sequence above permits | |
3441 | the fill of the final doubleword to be transferred from the FSB into | |
3442 | the cache. In the sequence above, the stores may be either integer | |
3443 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3444 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3445 | different doublewords on the line. If the floating point unit is | |
3446 | running in 1:2 mode, it is not possible to create the sequence above | |
3447 | using only floating point store instructions. | |
15be625d CM |
3448 | |
3449 | In this case, the cache line being filled is incorrectly marked | |
3450 | invalid, thereby losing the data from any store to the line that | |
3451 | occurs between the original miss and the completion of the five | |
3452 | cycle sequence shown above. | |
3453 | ||
932d1a1b | 3454 | The workarounds are: |
15be625d | 3455 | |
932d1a1b RS |
3456 | * Run the data cache in write-through mode. |
3457 | * Insert a non-store instruction between | |
3458 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3459 | |
3460 | static int | |
932d1a1b | 3461 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3462 | const struct mips_cl_insn *insn) |
3463 | { | |
3464 | struct fix_24k_store_info pos[3]; | |
3465 | int align, i, base_offset; | |
3466 | ||
932d1a1b RS |
3467 | if (ignore >= 2) |
3468 | return 0; | |
3469 | ||
ab9794cf RS |
3470 | /* If the previous instruction wasn't a store, there's nothing to |
3471 | worry about. */ | |
15be625d CM |
3472 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3473 | return 0; | |
3474 | ||
ab9794cf RS |
3475 | /* If the instructions after the previous one are unknown, we have |
3476 | to assume the worst. */ | |
3477 | if (!insn) | |
15be625d CM |
3478 | return 1; |
3479 | ||
ab9794cf RS |
3480 | /* Check whether we are dealing with three consecutive stores. */ |
3481 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3482 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3483 | return 0; |
3484 | ||
3485 | /* If we don't know the relationship between the store addresses, | |
3486 | assume the worst. */ | |
ab9794cf | 3487 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3488 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3489 | return 1; | |
3490 | ||
3491 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3492 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3493 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3494 | return 1; | |
3495 | ||
3496 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3497 | ||
3498 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3499 | X bytes and such that the base register + X is known to be aligned | |
3500 | to align bytes. */ | |
3501 | ||
3502 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3503 | align = 8; | |
3504 | else | |
3505 | { | |
3506 | align = pos[0].align_to; | |
3507 | base_offset = pos[0].off; | |
3508 | for (i = 1; i < 3; i++) | |
3509 | if (align < pos[i].align_to) | |
3510 | { | |
3511 | align = pos[i].align_to; | |
3512 | base_offset = pos[i].off; | |
3513 | } | |
3514 | for (i = 0; i < 3; i++) | |
3515 | pos[i].off -= base_offset; | |
3516 | } | |
3517 | ||
3518 | pos[0].off &= ~align + 1; | |
3519 | pos[1].off &= ~align + 1; | |
3520 | pos[2].off &= ~align + 1; | |
3521 | ||
3522 | /* If any two stores write to the same chunk, they also write to the | |
3523 | same doubleword. The offsets are still sorted at this point. */ | |
3524 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3525 | return 0; | |
3526 | ||
3527 | /* A range of at least 9 bytes is needed for the stores to be in | |
3528 | non-overlapping doublewords. */ | |
3529 | if (pos[2].off - pos[0].off <= 8) | |
3530 | return 0; | |
3531 | ||
3532 | if (pos[2].off - pos[1].off >= 24 | |
3533 | || pos[1].off - pos[0].off >= 24 | |
3534 | || pos[2].off - pos[0].off >= 32) | |
3535 | return 0; | |
3536 | ||
3537 | return 1; | |
3538 | } | |
3539 | ||
71400594 | 3540 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3541 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3542 | where HIST[0] is the most recent instruction. Ignore hazards |
3543 | between INSN and the first IGNORE instructions in HIST. | |
3544 | ||
3545 | If INSN is null, return the worse-case number of nops for any | |
3546 | instruction. */ | |
bdaaa2e1 | 3547 | |
71400594 | 3548 | static int |
932d1a1b | 3549 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3550 | const struct mips_cl_insn *insn) |
3551 | { | |
3552 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3553 | |
71400594 | 3554 | nops = 0; |
932d1a1b | 3555 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3556 | { |
91d6fa6a | 3557 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3558 | if (tmp_nops > nops) |
3559 | nops = tmp_nops; | |
3560 | } | |
7d8e00cf | 3561 | |
df58fc94 | 3562 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3563 | { |
932d1a1b | 3564 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3565 | if (tmp_nops > nops) |
3566 | nops = tmp_nops; | |
3567 | } | |
3568 | ||
df58fc94 | 3569 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3570 | { |
932d1a1b | 3571 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3572 | if (tmp_nops > nops) |
3573 | nops = tmp_nops; | |
3574 | } | |
3575 | ||
71400594 RS |
3576 | return nops; |
3577 | } | |
252b5132 | 3578 | |
71400594 | 3579 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3580 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3581 | would be needed after the extended sequence, ignoring hazards |
3582 | in the first IGNORE instructions. */ | |
252b5132 | 3583 | |
71400594 | 3584 | static int |
932d1a1b RS |
3585 | nops_for_sequence (int num_insns, int ignore, |
3586 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3587 | { |
3588 | va_list args; | |
3589 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3590 | struct mips_cl_insn *cursor; | |
3591 | int nops; | |
3592 | ||
91d6fa6a | 3593 | va_start (args, hist); |
71400594 | 3594 | cursor = buffer + num_insns; |
91d6fa6a | 3595 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3596 | while (cursor > buffer) |
3597 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3598 | ||
932d1a1b | 3599 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3600 | va_end (args); |
3601 | return nops; | |
3602 | } | |
252b5132 | 3603 | |
71400594 RS |
3604 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3605 | worst-case delay for the branch target. */ | |
252b5132 | 3606 | |
71400594 | 3607 | static int |
932d1a1b | 3608 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3609 | const struct mips_cl_insn *insn) |
3610 | { | |
3611 | int nops, tmp_nops; | |
60b63b72 | 3612 | |
932d1a1b | 3613 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3614 | if (delayed_branch_p (insn)) |
71400594 | 3615 | { |
932d1a1b | 3616 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3617 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3618 | if (tmp_nops > nops) |
3619 | nops = tmp_nops; | |
3620 | } | |
11625dd8 | 3621 | else if (compact_branch_p (insn)) |
71400594 | 3622 | { |
932d1a1b | 3623 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3624 | if (tmp_nops > nops) |
3625 | nops = tmp_nops; | |
3626 | } | |
3627 | return nops; | |
3628 | } | |
3629 | ||
c67a084a NC |
3630 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3631 | ||
3632 | static void | |
3633 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3634 | { | |
df58fc94 | 3635 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3636 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3637 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3638 | } | |
3639 | ||
3640 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3641 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3642 | ||
3643 | static void | |
3644 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3645 | { | |
df58fc94 | 3646 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3647 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3648 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3649 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3650 | { | |
3651 | int sreg; | |
3652 | expressionS ep; | |
3653 | ||
3654 | if (! mips_opts.at) | |
3655 | return; | |
3656 | ||
df58fc94 | 3657 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3658 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3659 | return; | |
3660 | ||
3661 | ep.X_op = O_constant; | |
3662 | ep.X_add_number = 0xcfff0000; | |
3663 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3664 | ep.X_add_number = 0xffff; | |
3665 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3666 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3667 | } | |
3668 | } | |
3669 | ||
3670 | static void | |
3671 | fix_loongson2f (struct mips_cl_insn * ip) | |
3672 | { | |
3673 | if (mips_fix_loongson2f_nop) | |
3674 | fix_loongson2f_nop (ip); | |
3675 | ||
3676 | if (mips_fix_loongson2f_jump) | |
3677 | fix_loongson2f_jump (ip); | |
3678 | } | |
3679 | ||
a4e06468 RS |
3680 | /* IP is a branch that has a delay slot, and we need to fill it |
3681 | automatically. Return true if we can do that by swapping IP | |
3682 | with the previous instruction. */ | |
3683 | ||
3684 | static bfd_boolean | |
3685 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3686 | { | |
2b0c8b40 | 3687 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3688 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3689 | ||
df58fc94 | 3690 | |
a4e06468 RS |
3691 | /* -O2 and above is required for this optimization. */ |
3692 | if (mips_optimize < 2) | |
3693 | return FALSE; | |
3694 | ||
3695 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3696 | if (mips_opts.nomove) | |
3697 | return FALSE; | |
3698 | ||
3699 | /* We can't swap if the previous instruction's position is fixed. */ | |
3700 | if (history[0].fixed_p) | |
3701 | return FALSE; | |
3702 | ||
3703 | /* If the previous previous insn was in a .set noreorder, we can't | |
3704 | swap. Actually, the MIPS assembler will swap in this situation. | |
3705 | However, gcc configured -with-gnu-as will generate code like | |
3706 | ||
3707 | .set noreorder | |
3708 | lw $4,XXX | |
3709 | .set reorder | |
3710 | INSN | |
3711 | bne $4,$0,foo | |
3712 | ||
3713 | in which we can not swap the bne and INSN. If gcc is not configured | |
3714 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3715 | if (history[1].noreorder_p) | |
3716 | return FALSE; | |
3717 | ||
3718 | /* If the previous instruction had a fixup in mips16 mode, we can not | |
3719 | swap. This normally means that the previous instruction was a 4 | |
3720 | byte branch anyhow. */ | |
3721 | if (mips_opts.mips16 && history[0].fixp[0]) | |
3722 | return FALSE; | |
3723 | ||
3724 | /* If the branch is itself the target of a branch, we can not swap. | |
3725 | We cheat on this; all we check for is whether there is a label on | |
3726 | this instruction. If there are any branches to anything other than | |
3727 | a label, users must use .set noreorder. */ | |
3728 | if (seg_info (now_seg)->label_list) | |
3729 | return FALSE; | |
3730 | ||
3731 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 MR |
3732 | branch's one, we cannot do the swap. This does not apply to |
3733 | MIPS16/microMIPS code, which uses variant frags for different | |
3734 | purposes. */ | |
df58fc94 | 3735 | if (!HAVE_CODE_COMPRESSION |
a4e06468 RS |
3736 | && history[0].frag |
3737 | && history[0].frag->fr_type == rs_machine_dependent) | |
3738 | return FALSE; | |
3739 | ||
bcd530a7 RS |
3740 | /* We do not swap with instructions that cannot architecturally |
3741 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3742 | also refrain from swapping with a trap instruction, since it | |
3743 | complicates trap handlers to have the trap instruction be in | |
3744 | a delay slot. */ | |
a4e06468 | 3745 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3746 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3747 | return FALSE; |
3748 | ||
3749 | /* Check for conflicts between the branch and the instructions | |
3750 | before the candidate delay slot. */ | |
3751 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3752 | return FALSE; | |
3753 | ||
3754 | /* Check for conflicts between the swapped sequence and the | |
3755 | target of the branch. */ | |
3756 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3757 | return FALSE; | |
3758 | ||
3759 | /* If the branch reads a register that the previous | |
3760 | instruction sets, we can not swap. */ | |
3761 | gpr_read = gpr_read_mask (ip); | |
3762 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3763 | if (gpr_read & prev_gpr_write) | |
3764 | return FALSE; | |
3765 | ||
3766 | /* If the branch writes a register that the previous | |
3767 | instruction sets, we can not swap. */ | |
3768 | gpr_write = gpr_write_mask (ip); | |
3769 | if (gpr_write & prev_gpr_write) | |
3770 | return FALSE; | |
3771 | ||
3772 | /* If the branch writes a register that the previous | |
3773 | instruction reads, we can not swap. */ | |
3774 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3775 | if (gpr_write & prev_gpr_read) | |
3776 | return FALSE; | |
3777 | ||
3778 | /* If one instruction sets a condition code and the | |
3779 | other one uses a condition code, we can not swap. */ | |
3780 | pinfo = ip->insn_mo->pinfo; | |
3781 | if ((pinfo & INSN_READ_COND_CODE) | |
3782 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3783 | return FALSE; | |
3784 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3785 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3786 | return FALSE; | |
3787 | ||
3788 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3789 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3790 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3791 | return FALSE; | |
2b0c8b40 MR |
3792 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3793 | return FALSE; | |
a4e06468 | 3794 | |
df58fc94 RS |
3795 | /* If the previous instruction has an incorrect size for a fixed |
3796 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3797 | pinfo2 = ip->insn_mo->pinfo2; |
3798 | if (mips_opts.micromips | |
3799 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3800 | && insn_length (history) != 2) | |
3801 | return FALSE; | |
3802 | if (mips_opts.micromips | |
3803 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3804 | && insn_length (history) != 4) | |
3805 | return FALSE; | |
3806 | ||
a4e06468 RS |
3807 | return TRUE; |
3808 | } | |
3809 | ||
3810 | /* Decide how we should add IP to the instruction stream. */ | |
3811 | ||
3812 | static enum append_method | |
3813 | get_append_method (struct mips_cl_insn *ip) | |
3814 | { | |
3815 | unsigned long pinfo; | |
3816 | ||
3817 | /* The relaxed version of a macro sequence must be inherently | |
3818 | hazard-free. */ | |
3819 | if (mips_relax.sequence == 2) | |
3820 | return APPEND_ADD; | |
3821 | ||
3822 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3823 | if (mips_opts.noreorder) | |
3824 | return APPEND_ADD; | |
3825 | ||
3826 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3827 | if (delayed_branch_p (ip)) |
a4e06468 | 3828 | { |
11625dd8 | 3829 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3830 | return APPEND_SWAP; |
3831 | ||
11625dd8 | 3832 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3833 | if (mips_opts.mips16 |
3834 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3835 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3836 | return APPEND_ADD_COMPACT; | |
3837 | ||
3838 | return APPEND_ADD_WITH_NOP; | |
3839 | } | |
3840 | ||
a4e06468 RS |
3841 | return APPEND_ADD; |
3842 | } | |
3843 | ||
ceb94aa5 RS |
3844 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3845 | Point IP->insn_mo to the new opcode's definition. */ | |
3846 | ||
3847 | static void | |
3848 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3849 | { | |
3850 | const struct mips_opcode *mo, *end; | |
3851 | ||
3852 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3853 | for (mo = ip->insn_mo; mo < end; mo++) | |
3854 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3855 | { | |
3856 | ip->insn_mo = mo; | |
3857 | return; | |
3858 | } | |
3859 | abort (); | |
3860 | } | |
3861 | ||
df58fc94 RS |
3862 | /* For microMIPS macros, we need to generate a local number label |
3863 | as the target of branches. */ | |
3864 | #define MICROMIPS_LABEL_CHAR '\037' | |
3865 | static unsigned long micromips_target_label; | |
3866 | static char micromips_target_name[32]; | |
3867 | ||
3868 | static char * | |
3869 | micromips_label_name (void) | |
3870 | { | |
3871 | char *p = micromips_target_name; | |
3872 | char symbol_name_temporary[24]; | |
3873 | unsigned long l; | |
3874 | int i; | |
3875 | ||
3876 | if (*p) | |
3877 | return p; | |
3878 | ||
3879 | i = 0; | |
3880 | l = micromips_target_label; | |
3881 | #ifdef LOCAL_LABEL_PREFIX | |
3882 | *p++ = LOCAL_LABEL_PREFIX; | |
3883 | #endif | |
3884 | *p++ = 'L'; | |
3885 | *p++ = MICROMIPS_LABEL_CHAR; | |
3886 | do | |
3887 | { | |
3888 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3889 | l /= 10; | |
3890 | } | |
3891 | while (l != 0); | |
3892 | while (i > 0) | |
3893 | *p++ = symbol_name_temporary[--i]; | |
3894 | *p = '\0'; | |
3895 | ||
3896 | return micromips_target_name; | |
3897 | } | |
3898 | ||
3899 | static void | |
3900 | micromips_label_expr (expressionS *label_expr) | |
3901 | { | |
3902 | label_expr->X_op = O_symbol; | |
3903 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3904 | label_expr->X_add_number = 0; | |
3905 | } | |
3906 | ||
3907 | static void | |
3908 | micromips_label_inc (void) | |
3909 | { | |
3910 | micromips_target_label++; | |
3911 | *micromips_target_name = '\0'; | |
3912 | } | |
3913 | ||
3914 | static void | |
3915 | micromips_add_label (void) | |
3916 | { | |
3917 | symbolS *s; | |
3918 | ||
3919 | s = colon (micromips_label_name ()); | |
3920 | micromips_label_inc (); | |
3921 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3922 | if (IS_ELF) | |
3923 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
3924 | #endif | |
3925 | } | |
3926 | ||
3927 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3928 | corresponding to the requested one if any. Otherwise return | |
3929 | the reloc unchanged. */ | |
3930 | ||
3931 | static bfd_reloc_code_real_type | |
3932 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3933 | { | |
3934 | static const bfd_reloc_code_real_type relocs[][2] = | |
3935 | { | |
3936 | /* Keep sorted incrementally by the left-hand key. */ | |
3937 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3938 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3939 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3940 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3941 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3942 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3943 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3944 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3945 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3946 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3947 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3948 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3949 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3950 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3951 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3952 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3953 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3954 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3955 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3956 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3957 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3958 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3959 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3960 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3961 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3962 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3963 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3964 | }; | |
3965 | bfd_reloc_code_real_type r; | |
3966 | size_t i; | |
3967 | ||
3968 | if (!mips_opts.micromips) | |
3969 | return reloc; | |
3970 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
3971 | { | |
3972 | r = relocs[i][0]; | |
3973 | if (r > reloc) | |
3974 | return reloc; | |
3975 | if (r == reloc) | |
3976 | return relocs[i][1]; | |
3977 | } | |
3978 | return reloc; | |
3979 | } | |
3980 | ||
71400594 RS |
3981 | /* Output an instruction. IP is the instruction information. |
3982 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
3983 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
3984 | a macro expansion. */ | |
71400594 RS |
3985 | |
3986 | static void | |
3987 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 3988 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 3989 | { |
14fe068b | 3990 | unsigned long prev_pinfo2, pinfo; |
71400594 | 3991 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3992 | enum append_method method; |
2309ddf2 | 3993 | bfd_boolean relax32; |
2b0c8b40 | 3994 | int branch_disp; |
71400594 | 3995 | |
2309ddf2 | 3996 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
3997 | fix_loongson2f (ip); |
3998 | ||
df58fc94 | 3999 | mips_mark_labels (); |
71400594 | 4000 | |
738f4d98 | 4001 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4002 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4003 | |
df58fc94 | 4004 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4005 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4006 | |
4007 | if (mips_opts.micromips | |
4008 | && !expansionp | |
4009 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4010 | && micromips_insn_length (ip->insn_mo) != 2) | |
4011 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4012 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4013 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4014 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4015 | |
15be625d CM |
4016 | if (address_expr == NULL) |
4017 | ip->complete_p = 1; | |
4018 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
4019 | && address_expr->X_op == O_constant) | |
4020 | { | |
4021 | unsigned int tmp; | |
4022 | ||
4023 | ip->complete_p = 1; | |
4024 | switch (*reloc_type) | |
4025 | { | |
4026 | case BFD_RELOC_32: | |
4027 | ip->insn_opcode |= address_expr->X_add_number; | |
4028 | break; | |
4029 | ||
4030 | case BFD_RELOC_MIPS_HIGHEST: | |
4031 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
4032 | ip->insn_opcode |= tmp & 0xffff; | |
4033 | break; | |
4034 | ||
4035 | case BFD_RELOC_MIPS_HIGHER: | |
4036 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
4037 | ip->insn_opcode |= tmp & 0xffff; | |
4038 | break; | |
4039 | ||
4040 | case BFD_RELOC_HI16_S: | |
4041 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
4042 | ip->insn_opcode |= tmp & 0xffff; | |
4043 | break; | |
4044 | ||
4045 | case BFD_RELOC_HI16: | |
4046 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4047 | break; | |
4048 | ||
4049 | case BFD_RELOC_UNUSED: | |
4050 | case BFD_RELOC_LO16: | |
4051 | case BFD_RELOC_MIPS_GOT_DISP: | |
4052 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4053 | break; | |
4054 | ||
4055 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4056 | { |
4057 | int shift; | |
4058 | ||
4059 | shift = mips_opts.micromips ? 1 : 2; | |
4060 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4061 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4062 | (unsigned long) address_expr->X_add_number); | |
4063 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4064 | & 0x3ffffff); | |
4065 | ip->complete_p = 0; | |
4066 | } | |
15be625d CM |
4067 | break; |
4068 | ||
4069 | case BFD_RELOC_MIPS16_JMP: | |
4070 | if ((address_expr->X_add_number & 3) != 0) | |
4071 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4072 | (unsigned long) address_expr->X_add_number); | |
4073 | ip->insn_opcode |= | |
4074 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4075 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4076 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4077 | ip->complete_p = 0; | |
4078 | break; | |
4079 | ||
4080 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4081 | { |
4082 | int shift; | |
4083 | ||
4084 | shift = mips_opts.micromips ? 1 : 2; | |
4085 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4086 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4087 | (unsigned long) address_expr->X_add_number); | |
4088 | if (!mips_relax_branch) | |
4089 | { | |
4090 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4091 | & ~((1 << (shift + 16)) - 1)) | |
4092 | as_bad (_("branch address range overflow (0x%lx)"), | |
4093 | (unsigned long) address_expr->X_add_number); | |
4094 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4095 | & 0xffff); | |
4096 | } | |
4097 | ip->complete_p = 0; | |
4098 | } | |
15be625d CM |
4099 | break; |
4100 | ||
4101 | default: | |
4102 | internalError (); | |
4103 | } | |
4104 | } | |
4105 | ||
71400594 RS |
4106 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4107 | { | |
4108 | /* There are a lot of optimizations we could do that we don't. | |
4109 | In particular, we do not, in general, reorder instructions. | |
4110 | If you use gcc with optimization, it will reorder | |
4111 | instructions and generally do much more optimization then we | |
4112 | do here; repeating all that work in the assembler would only | |
4113 | benefit hand written assembly code, and does not seem worth | |
4114 | it. */ | |
4115 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4116 | ? nops_for_insn (0, history, NULL) |
4117 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4118 | if (nops > 0) |
252b5132 RH |
4119 | { |
4120 | fragS *old_frag; | |
4121 | unsigned long old_frag_offset; | |
4122 | int i; | |
252b5132 RH |
4123 | |
4124 | old_frag = frag_now; | |
4125 | old_frag_offset = frag_now_fix (); | |
4126 | ||
4127 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4128 | add_fixed_insn (NOP_INSN); |
4129 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4130 | |
4131 | if (listing) | |
4132 | { | |
4133 | listing_prev_line (); | |
4134 | /* We may be at the start of a variant frag. In case we | |
4135 | are, make sure there is enough space for the frag | |
4136 | after the frags created by listing_prev_line. The | |
4137 | argument to frag_grow here must be at least as large | |
4138 | as the argument to all other calls to frag_grow in | |
4139 | this file. We don't have to worry about being in the | |
4140 | middle of a variant frag, because the variants insert | |
4141 | all needed nop instructions themselves. */ | |
4142 | frag_grow (40); | |
4143 | } | |
4144 | ||
404a8071 | 4145 | mips_move_labels (); |
252b5132 RH |
4146 | |
4147 | #ifndef NO_ECOFF_DEBUGGING | |
4148 | if (ECOFF_DEBUGGING) | |
4149 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4150 | #endif | |
4151 | } | |
71400594 RS |
4152 | } |
4153 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4154 | { | |
932d1a1b RS |
4155 | int nops; |
4156 | ||
4157 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4158 | ignoring hazards generated by the first prev_nop_frag_since | |
4159 | instructions. */ | |
4160 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4161 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4162 | |
71400594 RS |
4163 | /* Enforce NOPS as a minimum. */ |
4164 | if (nops > prev_nop_frag_required) | |
4165 | prev_nop_frag_required = nops; | |
252b5132 | 4166 | |
71400594 RS |
4167 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4168 | { | |
4169 | /* Settle for the current number of nops. Update the history | |
4170 | accordingly (for the benefit of any future .set reorder code). */ | |
4171 | prev_nop_frag = NULL; | |
4172 | insert_into_history (prev_nop_frag_since, | |
4173 | prev_nop_frag_holds, NOP_INSN); | |
4174 | } | |
4175 | else | |
4176 | { | |
4177 | /* Allow this instruction to replace one of the nops that was | |
4178 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4179 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4180 | prev_nop_frag_holds--; |
4181 | prev_nop_frag_since++; | |
252b5132 RH |
4182 | } |
4183 | } | |
4184 | ||
a4e06468 | 4185 | method = get_append_method (ip); |
2b0c8b40 | 4186 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4187 | |
58e2ea4d MR |
4188 | #ifdef OBJ_ELF |
4189 | /* The value passed to dwarf2_emit_insn is the distance between | |
4190 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4191 | should be recorded in the debug tables. This is normally the |
4192 | current address. | |
4193 | ||
df58fc94 RS |
4194 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4195 | addresses, so we use -1 for an address higher by one than the | |
4196 | current one. | |
e3a82c8e MR |
4197 | |
4198 | If the instruction produced is a branch that we will swap with | |
4199 | the preceding instruction, then we add the displacement by which | |
4200 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4201 | and for MIPS16/microMIPS code also prevents a debugger from |
4202 | placing a breakpoint in the middle of the branch (and corrupting | |
4203 | code if software breakpoints are used). */ | |
2b0c8b40 | 4204 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4205 | #endif |
4206 | ||
df58fc94 RS |
4207 | relax32 = (mips_relax_branch |
4208 | /* Don't try branch relaxation within .set nomacro, or within | |
4209 | .set noat if we use $at for PIC computations. If it turns | |
4210 | out that the branch was out-of-range, we'll get an error. */ | |
4211 | && !mips_opts.warn_about_macros | |
4212 | && (mips_opts.at || mips_pic == NO_PIC) | |
4213 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4214 | branches. */ | |
40209cad | 4215 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4216 | |
4217 | if (!HAVE_CODE_COMPRESSION | |
4218 | && address_expr | |
4219 | && relax32 | |
0b25d3e6 | 4220 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4221 | && delayed_branch_p (ip)) |
4a6a3df4 | 4222 | { |
895921c9 | 4223 | relaxed_branch = TRUE; |
1e915849 RS |
4224 | add_relaxed_insn (ip, (relaxed_branch_length |
4225 | (NULL, NULL, | |
11625dd8 RS |
4226 | uncond_branch_p (ip) ? -1 |
4227 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4228 | : 0)), 4, |
4229 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4230 | (AT, |
11625dd8 RS |
4231 | uncond_branch_p (ip), |
4232 | branch_likely_p (ip), | |
1e915849 RS |
4233 | pinfo & INSN_WRITE_GPR_31, |
4234 | 0), | |
4235 | address_expr->X_add_symbol, | |
4236 | address_expr->X_add_number); | |
4a6a3df4 AO |
4237 | *reloc_type = BFD_RELOC_UNUSED; |
4238 | } | |
df58fc94 RS |
4239 | else if (mips_opts.micromips |
4240 | && address_expr | |
4241 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4242 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4243 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4244 | /* Don't try branch relaxation when users specify | |
4245 | 16-bit/32-bit instructions. */ | |
4246 | && !forced_insn_length) | |
df58fc94 RS |
4247 | { |
4248 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4249 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4250 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4251 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4252 | int al = pinfo & INSN_WRITE_GPR_31; |
4253 | int length32; | |
4254 | ||
4255 | gas_assert (address_expr != NULL); | |
4256 | gas_assert (!mips_relax.sequence); | |
4257 | ||
2b0c8b40 | 4258 | relaxed_branch = TRUE; |
df58fc94 RS |
4259 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4260 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4261 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4262 | relax32, 0, 0), | |
df58fc94 RS |
4263 | address_expr->X_add_symbol, |
4264 | address_expr->X_add_number); | |
4265 | *reloc_type = BFD_RELOC_UNUSED; | |
4266 | } | |
4267 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4268 | { |
4269 | /* We need to set up a variant frag. */ | |
df58fc94 | 4270 | gas_assert (address_expr != NULL); |
1e915849 RS |
4271 | add_relaxed_insn (ip, 4, 0, |
4272 | RELAX_MIPS16_ENCODE | |
4273 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4274 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4275 | delayed_branch_p (&history[0]), |
1e915849 RS |
4276 | history[0].mips16_absolute_jump_p), |
4277 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4278 | } |
252b5132 RH |
4279 | else if (mips_opts.mips16 |
4280 | && ! ip->use_extend | |
f6688943 | 4281 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 4282 | { |
11625dd8 | 4283 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4284 | /* Make sure there is enough room to swap this instruction with |
4285 | a following jump instruction. */ | |
4286 | frag_grow (6); | |
1e915849 | 4287 | add_fixed_insn (ip); |
252b5132 RH |
4288 | } |
4289 | else | |
4290 | { | |
4291 | if (mips_opts.mips16 | |
4292 | && mips_opts.noreorder | |
11625dd8 | 4293 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4294 | as_warn (_("extended instruction in delay slot")); |
4295 | ||
4d7206a2 RS |
4296 | if (mips_relax.sequence) |
4297 | { | |
4298 | /* If we've reached the end of this frag, turn it into a variant | |
4299 | frag and record the information for the instructions we've | |
4300 | written so far. */ | |
4301 | if (frag_room () < 4) | |
4302 | relax_close_frag (); | |
df58fc94 | 4303 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4304 | } |
4305 | ||
584892a6 | 4306 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4307 | { |
4308 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4309 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4310 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4311 | mips_macro_warning.insns[0]++; | |
4312 | } | |
584892a6 | 4313 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4314 | { |
4315 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4316 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4317 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4318 | mips_macro_warning.insns[1]++; | |
4319 | } | |
584892a6 | 4320 | |
1e915849 RS |
4321 | if (mips_opts.mips16) |
4322 | { | |
4323 | ip->fixed_p = 1; | |
4324 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4325 | } | |
4326 | add_fixed_insn (ip); | |
252b5132 RH |
4327 | } |
4328 | ||
9fe77896 | 4329 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4330 | { |
df58fc94 | 4331 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4332 | reloc_howto_type *howto0; |
9fe77896 RS |
4333 | reloc_howto_type *howto; |
4334 | int i; | |
34ce925e | 4335 | |
df58fc94 RS |
4336 | /* Perform any necessary conversion to microMIPS relocations |
4337 | and find out how many relocations there actually are. */ | |
4338 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4339 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4340 | ||
9fe77896 RS |
4341 | /* In a compound relocation, it is the final (outermost) |
4342 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4343 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4344 | ||
9fe77896 RS |
4345 | if (howto == NULL) |
4346 | { | |
4347 | /* To reproduce this failure try assembling gas/testsuites/ | |
4348 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4349 | assembler. */ | |
df58fc94 RS |
4350 | as_bad (_("Unsupported MIPS relocation number %d"), |
4351 | final_type[i - 1]); | |
9fe77896 RS |
4352 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4353 | } | |
2309ddf2 MR |
4354 | |
4355 | if (i > 1) | |
4356 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4357 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4358 | bfd_get_reloc_size (howto), | |
4359 | address_expr, | |
2309ddf2 MR |
4360 | howto0 && howto0->pc_relative, |
4361 | final_type[0]); | |
9fe77896 RS |
4362 | |
4363 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4364 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4365 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4366 | ||
4367 | /* These relocations can have an addend that won't fit in | |
4368 | 4 octets for 64bit assembly. */ | |
4369 | if (HAVE_64BIT_GPRS | |
4370 | && ! howto->partial_inplace | |
4371 | && (reloc_type[0] == BFD_RELOC_16 | |
4372 | || reloc_type[0] == BFD_RELOC_32 | |
4373 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4374 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4375 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4376 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4377 | || reloc_type[0] == BFD_RELOC_64 | |
4378 | || reloc_type[0] == BFD_RELOC_CTOR | |
4379 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4380 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4381 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4382 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4383 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4384 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4385 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4386 | || hi16_reloc_p (reloc_type[0]) | |
4387 | || lo16_reloc_p (reloc_type[0]))) | |
4388 | ip->fixp[0]->fx_no_overflow = 1; | |
4389 | ||
4390 | if (mips_relax.sequence) | |
4391 | { | |
4392 | if (mips_relax.first_fixup == 0) | |
4393 | mips_relax.first_fixup = ip->fixp[0]; | |
4394 | } | |
4395 | else if (reloc_needs_lo_p (*reloc_type)) | |
4396 | { | |
4397 | struct mips_hi_fixup *hi_fixup; | |
4398 | ||
4399 | /* Reuse the last entry if it already has a matching %lo. */ | |
4400 | hi_fixup = mips_hi_fixup_list; | |
4401 | if (hi_fixup == 0 | |
4402 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4403 | { |
9fe77896 RS |
4404 | hi_fixup = ((struct mips_hi_fixup *) |
4405 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4406 | hi_fixup->next = mips_hi_fixup_list; | |
4407 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4408 | } |
9fe77896 RS |
4409 | hi_fixup->fixp = ip->fixp[0]; |
4410 | hi_fixup->seg = now_seg; | |
4411 | } | |
252b5132 | 4412 | |
9fe77896 RS |
4413 | /* Add fixups for the second and third relocations, if given. |
4414 | Note that the ABI allows the second relocation to be | |
4415 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4416 | moment we only use RSS_UNDEF, but we could add support | |
4417 | for the others if it ever becomes necessary. */ | |
4418 | for (i = 1; i < 3; i++) | |
4419 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4420 | { | |
4421 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4422 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4423 | FALSE, final_type[i]); |
f6688943 | 4424 | |
9fe77896 RS |
4425 | /* Use fx_tcbit to mark compound relocs. */ |
4426 | ip->fixp[0]->fx_tcbit = 1; | |
4427 | ip->fixp[i]->fx_tcbit = 1; | |
4428 | } | |
252b5132 | 4429 | } |
1e915849 | 4430 | install_insn (ip); |
252b5132 RH |
4431 | |
4432 | /* Update the register mask information. */ | |
4c260379 RS |
4433 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4434 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4435 | |
a4e06468 | 4436 | switch (method) |
252b5132 | 4437 | { |
a4e06468 RS |
4438 | case APPEND_ADD: |
4439 | insert_into_history (0, 1, ip); | |
4440 | break; | |
4441 | ||
4442 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4443 | { |
4444 | struct mips_cl_insn *nop; | |
4445 | ||
4446 | insert_into_history (0, 1, ip); | |
4447 | nop = get_delay_slot_nop (ip); | |
4448 | add_fixed_insn (nop); | |
4449 | insert_into_history (0, 1, nop); | |
4450 | if (mips_relax.sequence) | |
4451 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4452 | } | |
a4e06468 RS |
4453 | break; |
4454 | ||
4455 | case APPEND_ADD_COMPACT: | |
4456 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4457 | gas_assert (mips_opts.mips16); | |
4458 | ip->insn_opcode |= 0x0080; | |
4459 | find_altered_mips16_opcode (ip); | |
4460 | install_insn (ip); | |
4461 | insert_into_history (0, 1, ip); | |
4462 | break; | |
4463 | ||
4464 | case APPEND_SWAP: | |
4465 | { | |
4466 | struct mips_cl_insn delay = history[0]; | |
4467 | if (mips_opts.mips16) | |
4468 | { | |
4469 | know (delay.frag == ip->frag); | |
4470 | move_insn (ip, delay.frag, delay.where); | |
4471 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4472 | } | |
4473 | else if (relaxed_branch) | |
4474 | { | |
4475 | /* Add the delay slot instruction to the end of the | |
4476 | current frag and shrink the fixed part of the | |
4477 | original frag. If the branch occupies the tail of | |
4478 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4479 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4480 | if (delay.frag == ip->frag) |
2b0c8b40 | 4481 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4482 | add_fixed_insn (&delay); |
4483 | } | |
4484 | else | |
4485 | { | |
2b0c8b40 MR |
4486 | move_insn (&delay, ip->frag, |
4487 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4488 | move_insn (ip, history[0].frag, history[0].where); |
4489 | } | |
4490 | history[0] = *ip; | |
4491 | delay.fixed_p = 1; | |
4492 | insert_into_history (0, 1, &delay); | |
4493 | } | |
4494 | break; | |
252b5132 RH |
4495 | } |
4496 | ||
13408f1e | 4497 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4498 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4499 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4500 | mips_no_prev_insn (); |
4501 | ||
df58fc94 RS |
4502 | /* We need to emit a label at the end of branch-likely macros. */ |
4503 | if (emit_branch_likely_macro) | |
4504 | { | |
4505 | emit_branch_likely_macro = FALSE; | |
4506 | micromips_add_label (); | |
4507 | } | |
4508 | ||
252b5132 RH |
4509 | /* We just output an insn, so the next one doesn't have a label. */ |
4510 | mips_clear_insn_labels (); | |
252b5132 RH |
4511 | } |
4512 | ||
7d10b47d | 4513 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4514 | |
4515 | static void | |
7d10b47d | 4516 | mips_no_prev_insn (void) |
252b5132 | 4517 | { |
7d10b47d RS |
4518 | prev_nop_frag = NULL; |
4519 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4520 | mips_clear_insn_labels (); |
4521 | } | |
4522 | ||
7d10b47d RS |
4523 | /* This function must be called before we emit something other than |
4524 | instructions. It is like mips_no_prev_insn except that it inserts | |
4525 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4526 | |
7d10b47d RS |
4527 | void |
4528 | mips_emit_delays (void) | |
252b5132 RH |
4529 | { |
4530 | if (! mips_opts.noreorder) | |
4531 | { | |
932d1a1b | 4532 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4533 | if (nops > 0) |
4534 | { | |
7d10b47d RS |
4535 | while (nops-- > 0) |
4536 | add_fixed_insn (NOP_INSN); | |
4537 | mips_move_labels (); | |
4538 | } | |
4539 | } | |
4540 | mips_no_prev_insn (); | |
4541 | } | |
4542 | ||
4543 | /* Start a (possibly nested) noreorder block. */ | |
4544 | ||
4545 | static void | |
4546 | start_noreorder (void) | |
4547 | { | |
4548 | if (mips_opts.noreorder == 0) | |
4549 | { | |
4550 | unsigned int i; | |
4551 | int nops; | |
4552 | ||
4553 | /* None of the instructions before the .set noreorder can be moved. */ | |
4554 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4555 | history[i].fixed_p = 1; | |
4556 | ||
4557 | /* Insert any nops that might be needed between the .set noreorder | |
4558 | block and the previous instructions. We will later remove any | |
4559 | nops that turn out not to be needed. */ | |
932d1a1b | 4560 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4561 | if (nops > 0) |
4562 | { | |
4563 | if (mips_optimize != 0) | |
252b5132 RH |
4564 | { |
4565 | /* Record the frag which holds the nop instructions, so | |
4566 | that we can remove them if we don't need them. */ | |
df58fc94 | 4567 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4568 | prev_nop_frag = frag_now; |
4569 | prev_nop_frag_holds = nops; | |
4570 | prev_nop_frag_required = 0; | |
4571 | prev_nop_frag_since = 0; | |
4572 | } | |
4573 | ||
4574 | for (; nops > 0; --nops) | |
1e915849 | 4575 | add_fixed_insn (NOP_INSN); |
252b5132 | 4576 | |
7d10b47d RS |
4577 | /* Move on to a new frag, so that it is safe to simply |
4578 | decrease the size of prev_nop_frag. */ | |
4579 | frag_wane (frag_now); | |
4580 | frag_new (0); | |
404a8071 | 4581 | mips_move_labels (); |
252b5132 | 4582 | } |
df58fc94 | 4583 | mips_mark_labels (); |
7d10b47d | 4584 | mips_clear_insn_labels (); |
252b5132 | 4585 | } |
7d10b47d RS |
4586 | mips_opts.noreorder++; |
4587 | mips_any_noreorder = 1; | |
4588 | } | |
252b5132 | 4589 | |
7d10b47d | 4590 | /* End a nested noreorder block. */ |
252b5132 | 4591 | |
7d10b47d RS |
4592 | static void |
4593 | end_noreorder (void) | |
4594 | { | |
6a32d874 | 4595 | |
7d10b47d RS |
4596 | mips_opts.noreorder--; |
4597 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4598 | { | |
4599 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4600 | handling nop insertion the .set reorder way. */ | |
4601 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4602 | * NOP_INSN_SIZE); |
7d10b47d RS |
4603 | insert_into_history (prev_nop_frag_since, |
4604 | prev_nop_frag_required, NOP_INSN); | |
4605 | prev_nop_frag = NULL; | |
4606 | } | |
252b5132 RH |
4607 | } |
4608 | ||
584892a6 RS |
4609 | /* Set up global variables for the start of a new macro. */ |
4610 | ||
4611 | static void | |
4612 | macro_start (void) | |
4613 | { | |
4614 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4615 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4616 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4617 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4618 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4619 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4620 | switch (history[0].insn_mo->pinfo2 |
4621 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4622 | { | |
4623 | case INSN2_BRANCH_DELAY_32BIT: | |
4624 | mips_macro_warning.delay_slot_length = 4; | |
4625 | break; | |
4626 | case INSN2_BRANCH_DELAY_16BIT: | |
4627 | mips_macro_warning.delay_slot_length = 2; | |
4628 | break; | |
4629 | default: | |
4630 | mips_macro_warning.delay_slot_length = 0; | |
4631 | break; | |
4632 | } | |
4633 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4634 | } |
4635 | ||
df58fc94 RS |
4636 | /* Given that a macro is longer than one instruction or of the wrong size, |
4637 | return the appropriate warning for it. Return null if no warning is | |
4638 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4639 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4640 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4641 | |
4642 | static const char * | |
4643 | macro_warning (relax_substateT subtype) | |
4644 | { | |
4645 | if (subtype & RELAX_DELAY_SLOT) | |
4646 | return _("Macro instruction expanded into multiple instructions" | |
4647 | " in a branch delay slot"); | |
4648 | else if (subtype & RELAX_NOMACRO) | |
4649 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4650 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4651 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4652 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4653 | ? _("Macro instruction expanded into a wrong size instruction" | |
4654 | " in a 16-bit branch delay slot") | |
4655 | : _("Macro instruction expanded into a wrong size instruction" | |
4656 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4657 | else |
4658 | return 0; | |
4659 | } | |
4660 | ||
4661 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4662 | ||
4663 | static void | |
4664 | macro_end (void) | |
4665 | { | |
df58fc94 RS |
4666 | /* Relaxation warning flags. */ |
4667 | relax_substateT subtype = 0; | |
4668 | ||
4669 | /* Check delay slot size requirements. */ | |
4670 | if (mips_macro_warning.delay_slot_length == 2) | |
4671 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4672 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4673 | { |
df58fc94 RS |
4674 | if (mips_macro_warning.delay_slot_length |
4675 | != mips_macro_warning.first_insn_sizes[0]) | |
4676 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4677 | if (mips_macro_warning.delay_slot_length | |
4678 | != mips_macro_warning.first_insn_sizes[1]) | |
4679 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4680 | } | |
584892a6 | 4681 | |
df58fc94 RS |
4682 | /* Check instruction count requirements. */ |
4683 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4684 | { | |
4685 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4686 | subtype |= RELAX_SECOND_LONGER; |
4687 | if (mips_opts.warn_about_macros) | |
4688 | subtype |= RELAX_NOMACRO; | |
4689 | if (mips_macro_warning.delay_slot_p) | |
4690 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4691 | } |
584892a6 | 4692 | |
df58fc94 RS |
4693 | /* If both alternatives fail to fill a delay slot correctly, |
4694 | emit the warning now. */ | |
4695 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4696 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4697 | { | |
4698 | relax_substateT s; | |
4699 | const char *msg; | |
4700 | ||
4701 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4702 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4703 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4704 | msg = macro_warning (s); | |
4705 | if (msg != NULL) | |
4706 | as_warn ("%s", msg); | |
4707 | subtype &= ~s; | |
4708 | } | |
4709 | ||
4710 | /* If both implementations are longer than 1 instruction, then emit the | |
4711 | warning now. */ | |
4712 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4713 | { | |
4714 | relax_substateT s; | |
4715 | const char *msg; | |
4716 | ||
4717 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4718 | msg = macro_warning (s); | |
4719 | if (msg != NULL) | |
4720 | as_warn ("%s", msg); | |
4721 | subtype &= ~s; | |
584892a6 | 4722 | } |
df58fc94 RS |
4723 | |
4724 | /* If any flags still set, then one implementation might need a warning | |
4725 | and the other either will need one of a different kind or none at all. | |
4726 | Pass any remaining flags over to relaxation. */ | |
4727 | if (mips_macro_warning.first_frag != NULL) | |
4728 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4729 | } |
4730 | ||
df58fc94 RS |
4731 | /* Instruction operand formats used in macros that vary between |
4732 | standard MIPS and microMIPS code. */ | |
4733 | ||
4734 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4735 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4736 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4737 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4738 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4739 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4740 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4741 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4742 | ||
4743 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4744 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4745 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4746 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4747 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4748 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4749 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4750 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4751 | ||
6e1304d8 RS |
4752 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4753 | The first argument in *ARGS will be either the code for a single | |
4754 | relocation or -1 followed by the three codes that make up a | |
4755 | composite relocation. */ | |
4756 | ||
4757 | static void | |
4758 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4759 | { | |
4760 | int i, next; | |
4761 | ||
4762 | next = va_arg (*args, int); | |
4763 | if (next >= 0) | |
4764 | r[0] = (bfd_reloc_code_real_type) next; | |
4765 | else | |
4766 | for (i = 0; i < 3; i++) | |
4767 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4768 | } | |
4769 | ||
252b5132 RH |
4770 | /* Build an instruction created by a macro expansion. This is passed |
4771 | a pointer to the count of instructions created so far, an | |
4772 | expression, the name of the instruction to build, an operand format | |
4773 | string, and corresponding arguments. */ | |
4774 | ||
252b5132 | 4775 | static void |
67c0d1eb | 4776 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4777 | { |
df58fc94 | 4778 | const struct mips_opcode *mo = NULL; |
f6688943 | 4779 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4780 | const struct mips_opcode *amo; |
4781 | struct hash_control *hash; | |
4782 | struct mips_cl_insn insn; | |
252b5132 | 4783 | va_list args; |
252b5132 | 4784 | |
252b5132 | 4785 | va_start (args, fmt); |
252b5132 | 4786 | |
252b5132 RH |
4787 | if (mips_opts.mips16) |
4788 | { | |
03ea81db | 4789 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4790 | va_end (args); |
4791 | return; | |
4792 | } | |
4793 | ||
f6688943 TS |
4794 | r[0] = BFD_RELOC_UNUSED; |
4795 | r[1] = BFD_RELOC_UNUSED; | |
4796 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4797 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4798 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4799 | gas_assert (amo); | |
4800 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4801 | |
df58fc94 | 4802 | do |
8b082fb1 TS |
4803 | { |
4804 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4805 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4806 | We try to match an instruction that fulfils the branch delay | |
4807 | slot instruction length requirement (if any) of the previous | |
4808 | instruction. While doing this we record the first instruction | |
4809 | seen that matches all the other conditions and use it anyway | |
4810 | if the requirement cannot be met; we will issue an appropriate | |
4811 | warning later on. */ | |
4812 | if (strcmp (fmt, amo->args) == 0 | |
4813 | && amo->pinfo != INSN_MACRO | |
4814 | && is_opcode_valid (amo) | |
4815 | && is_size_valid (amo)) | |
4816 | { | |
4817 | if (is_delay_slot_valid (amo)) | |
4818 | { | |
4819 | mo = amo; | |
4820 | break; | |
4821 | } | |
4822 | else if (!mo) | |
4823 | mo = amo; | |
4824 | } | |
8b082fb1 | 4825 | |
df58fc94 RS |
4826 | ++amo; |
4827 | gas_assert (amo->name); | |
252b5132 | 4828 | } |
df58fc94 | 4829 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4830 | |
df58fc94 | 4831 | gas_assert (mo); |
1e915849 | 4832 | create_insn (&insn, mo); |
252b5132 RH |
4833 | for (;;) |
4834 | { | |
4835 | switch (*fmt++) | |
4836 | { | |
4837 | case '\0': | |
4838 | break; | |
4839 | ||
4840 | case ',': | |
4841 | case '(': | |
4842 | case ')': | |
4843 | continue; | |
4844 | ||
5f74bc13 CD |
4845 | case '+': |
4846 | switch (*fmt++) | |
4847 | { | |
4848 | case 'A': | |
4849 | case 'E': | |
df58fc94 RS |
4850 | INSERT_OPERAND (mips_opts.micromips, |
4851 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4852 | continue; |
4853 | ||
4854 | case 'B': | |
4855 | case 'F': | |
4856 | /* Note that in the macro case, these arguments are already | |
4857 | in MSB form. (When handling the instruction in the | |
4858 | non-macro case, these arguments are sizes from which | |
4859 | MSB values must be calculated.) */ | |
df58fc94 RS |
4860 | INSERT_OPERAND (mips_opts.micromips, |
4861 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4862 | continue; |
4863 | ||
4864 | case 'C': | |
4865 | case 'G': | |
4866 | case 'H': | |
4867 | /* Note that in the macro case, these arguments are already | |
4868 | in MSBD form. (When handling the instruction in the | |
4869 | non-macro case, these arguments are sizes from which | |
4870 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4871 | INSERT_OPERAND (mips_opts.micromips, |
4872 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4873 | continue; |
4874 | ||
dd3cbb7e | 4875 | case 'Q': |
df58fc94 RS |
4876 | gas_assert (!mips_opts.micromips); |
4877 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4878 | continue; |
4879 | ||
5f74bc13 CD |
4880 | default: |
4881 | internalError (); | |
4882 | } | |
4883 | continue; | |
4884 | ||
8b082fb1 | 4885 | case '2': |
df58fc94 RS |
4886 | gas_assert (!mips_opts.micromips); |
4887 | INSERT_OPERAND (0, BP, insn, va_arg (args, int)); | |
8b082fb1 TS |
4888 | continue; |
4889 | ||
df58fc94 RS |
4890 | case 'n': |
4891 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4892 | case 't': |
4893 | case 'w': | |
4894 | case 'E': | |
df58fc94 | 4895 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4896 | continue; |
4897 | ||
4898 | case 'c': | |
df58fc94 RS |
4899 | gas_assert (!mips_opts.micromips); |
4900 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4901 | continue; |
4902 | ||
252b5132 | 4903 | case 'W': |
df58fc94 RS |
4904 | gas_assert (!mips_opts.micromips); |
4905 | case 'T': | |
4906 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4907 | continue; |
4908 | ||
252b5132 | 4909 | case 'G': |
df58fc94 RS |
4910 | if (mips_opts.micromips) |
4911 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4912 | else | |
4913 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4914 | continue; | |
4915 | ||
af7ee8bf | 4916 | case 'K': |
df58fc94 RS |
4917 | gas_assert (!mips_opts.micromips); |
4918 | case 'd': | |
4919 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4920 | continue; |
4921 | ||
4372b673 | 4922 | case 'U': |
df58fc94 | 4923 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4924 | { |
4925 | int tmp = va_arg (args, int); | |
4926 | ||
df58fc94 RS |
4927 | INSERT_OPERAND (0, RT, insn, tmp); |
4928 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4929 | } |
df58fc94 | 4930 | continue; |
4372b673 | 4931 | |
252b5132 RH |
4932 | case 'V': |
4933 | case 'S': | |
df58fc94 RS |
4934 | gas_assert (!mips_opts.micromips); |
4935 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4936 | continue; |
4937 | ||
4938 | case 'z': | |
4939 | continue; | |
4940 | ||
4941 | case '<': | |
df58fc94 RS |
4942 | INSERT_OPERAND (mips_opts.micromips, |
4943 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4944 | continue; |
4945 | ||
4946 | case 'D': | |
df58fc94 RS |
4947 | gas_assert (!mips_opts.micromips); |
4948 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4949 | continue; |
4950 | ||
4951 | case 'B': | |
df58fc94 RS |
4952 | gas_assert (!mips_opts.micromips); |
4953 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4954 | continue; |
4955 | ||
4372b673 | 4956 | case 'J': |
df58fc94 RS |
4957 | gas_assert (!mips_opts.micromips); |
4958 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4959 | continue; |
4960 | ||
252b5132 | 4961 | case 'q': |
df58fc94 RS |
4962 | gas_assert (!mips_opts.micromips); |
4963 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4964 | continue; |
4965 | ||
4966 | case 'b': | |
4967 | case 's': | |
4968 | case 'r': | |
4969 | case 'v': | |
df58fc94 | 4970 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
4971 | continue; |
4972 | ||
4973 | case 'i': | |
4974 | case 'j': | |
6e1304d8 | 4975 | macro_read_relocs (&args, r); |
9c2799c2 | 4976 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4977 | || *r == BFD_RELOC_MIPS_HIGHER |
4978 | || *r == BFD_RELOC_HI16_S | |
4979 | || *r == BFD_RELOC_LO16 | |
4980 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4981 | continue; | |
4982 | ||
4983 | case 'o': | |
4984 | macro_read_relocs (&args, r); | |
252b5132 RH |
4985 | continue; |
4986 | ||
4987 | case 'u': | |
6e1304d8 | 4988 | macro_read_relocs (&args, r); |
9c2799c2 | 4989 | gas_assert (ep != NULL |
90ecf173 MR |
4990 | && (ep->X_op == O_constant |
4991 | || (ep->X_op == O_symbol | |
4992 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4993 | || *r == BFD_RELOC_HI16_S | |
4994 | || *r == BFD_RELOC_HI16 | |
4995 | || *r == BFD_RELOC_GPREL16 | |
4996 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
4997 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4998 | continue; |
4999 | ||
5000 | case 'p': | |
9c2799c2 | 5001 | gas_assert (ep != NULL); |
bad36eac | 5002 | |
252b5132 RH |
5003 | /* |
5004 | * This allows macro() to pass an immediate expression for | |
5005 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5006 | * |
5007 | * We don't allow branch relaxation for these branches, as | |
5008 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5009 | */ |
5010 | if (ep->X_op == O_constant) | |
5011 | { | |
df58fc94 RS |
5012 | /* For microMIPS we always use relocations for branches. |
5013 | So we should not resolve immediate values. */ | |
5014 | gas_assert (!mips_opts.micromips); | |
5015 | ||
bad36eac DJ |
5016 | if ((ep->X_add_number & 3) != 0) |
5017 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5018 | (unsigned long) ep->X_add_number); | |
5019 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5020 | as_bad (_("branch address range overflow (0x%lx)"), | |
5021 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5022 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5023 | ep = NULL; | |
5024 | } | |
5025 | else | |
0b25d3e6 | 5026 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5027 | continue; |
5028 | ||
5029 | case 'a': | |
9c2799c2 | 5030 | gas_assert (ep != NULL); |
f6688943 | 5031 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5032 | continue; |
5033 | ||
5034 | case 'C': | |
df58fc94 RS |
5035 | gas_assert (!mips_opts.micromips); |
5036 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5037 | continue; |
5038 | ||
d43b4baf | 5039 | case 'k': |
df58fc94 RS |
5040 | INSERT_OPERAND (mips_opts.micromips, |
5041 | CACHE, insn, va_arg (args, unsigned long)); | |
5042 | continue; | |
5043 | ||
5044 | case '|': | |
5045 | gas_assert (mips_opts.micromips); | |
5046 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5047 | continue; | |
5048 | ||
5049 | case '.': | |
5050 | gas_assert (mips_opts.micromips); | |
5051 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5052 | continue; | |
5053 | ||
dec0624d MR |
5054 | case '\\': |
5055 | INSERT_OPERAND (mips_opts.micromips, | |
5056 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5057 | continue; | |
5058 | ||
df58fc94 | 5059 | case '~': |
dec0624d MR |
5060 | INSERT_OPERAND (mips_opts.micromips, |
5061 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5062 | continue; |
5063 | ||
5064 | case 'N': | |
5065 | gas_assert (mips_opts.micromips); | |
5066 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5067 | continue; | |
5068 | ||
5069 | case 'm': /* Opcode extension character. */ | |
5070 | gas_assert (mips_opts.micromips); | |
5071 | switch (*fmt++) | |
5072 | { | |
5073 | case 'j': | |
5074 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5075 | break; | |
5076 | ||
5077 | case 'p': | |
5078 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5079 | break; | |
5080 | ||
5081 | case 'F': | |
5082 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5083 | break; | |
5084 | ||
5085 | default: | |
5086 | internalError (); | |
5087 | } | |
d43b4baf TS |
5088 | continue; |
5089 | ||
252b5132 RH |
5090 | default: |
5091 | internalError (); | |
5092 | } | |
5093 | break; | |
5094 | } | |
5095 | va_end (args); | |
9c2799c2 | 5096 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5097 | |
df58fc94 | 5098 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5099 | } |
5100 | ||
5101 | static void | |
67c0d1eb | 5102 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5103 | va_list *args) |
252b5132 | 5104 | { |
1e915849 | 5105 | struct mips_opcode *mo; |
252b5132 | 5106 | struct mips_cl_insn insn; |
f6688943 TS |
5107 | bfd_reloc_code_real_type r[3] |
5108 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5109 | |
1e915849 | 5110 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5111 | gas_assert (mo); |
5112 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5113 | |
1e915849 | 5114 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5115 | { |
1e915849 | 5116 | ++mo; |
9c2799c2 NC |
5117 | gas_assert (mo->name); |
5118 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5119 | } |
5120 | ||
1e915849 | 5121 | create_insn (&insn, mo); |
252b5132 RH |
5122 | for (;;) |
5123 | { | |
5124 | int c; | |
5125 | ||
5126 | c = *fmt++; | |
5127 | switch (c) | |
5128 | { | |
5129 | case '\0': | |
5130 | break; | |
5131 | ||
5132 | case ',': | |
5133 | case '(': | |
5134 | case ')': | |
5135 | continue; | |
5136 | ||
5137 | case 'y': | |
5138 | case 'w': | |
03ea81db | 5139 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5140 | continue; |
5141 | ||
5142 | case 'x': | |
5143 | case 'v': | |
03ea81db | 5144 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5145 | continue; |
5146 | ||
5147 | case 'z': | |
03ea81db | 5148 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5149 | continue; |
5150 | ||
5151 | case 'Z': | |
03ea81db | 5152 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5153 | continue; |
5154 | ||
5155 | case '0': | |
5156 | case 'S': | |
5157 | case 'P': | |
5158 | case 'R': | |
5159 | continue; | |
5160 | ||
5161 | case 'X': | |
03ea81db | 5162 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5163 | continue; |
5164 | ||
5165 | case 'Y': | |
5166 | { | |
5167 | int regno; | |
5168 | ||
03ea81db | 5169 | regno = va_arg (*args, int); |
252b5132 | 5170 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5171 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5172 | } |
5173 | continue; | |
5174 | ||
5175 | case '<': | |
5176 | case '>': | |
5177 | case '4': | |
5178 | case '5': | |
5179 | case 'H': | |
5180 | case 'W': | |
5181 | case 'D': | |
5182 | case 'j': | |
5183 | case '8': | |
5184 | case 'V': | |
5185 | case 'C': | |
5186 | case 'U': | |
5187 | case 'k': | |
5188 | case 'K': | |
5189 | case 'p': | |
5190 | case 'q': | |
5191 | { | |
9c2799c2 | 5192 | gas_assert (ep != NULL); |
252b5132 RH |
5193 | |
5194 | if (ep->X_op != O_constant) | |
874e8986 | 5195 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5196 | else |
5197 | { | |
b34976b6 AM |
5198 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
5199 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 5200 | &insn.extend); |
252b5132 | 5201 | ep = NULL; |
f6688943 | 5202 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5203 | } |
5204 | } | |
5205 | continue; | |
5206 | ||
5207 | case '6': | |
03ea81db | 5208 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5209 | continue; |
5210 | } | |
5211 | ||
5212 | break; | |
5213 | } | |
5214 | ||
9c2799c2 | 5215 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5216 | |
df58fc94 | 5217 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5218 | } |
5219 | ||
2051e8c4 MR |
5220 | /* |
5221 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5222 | * higher bits unset. | |
5223 | */ | |
9f872bbe | 5224 | static void |
2051e8c4 MR |
5225 | normalize_constant_expr (expressionS *ex) |
5226 | { | |
9ee2a2d4 | 5227 | if (ex->X_op == O_constant |
2051e8c4 MR |
5228 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5229 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5230 | - 0x80000000); | |
5231 | } | |
5232 | ||
5233 | /* | |
5234 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5235 | * all higher bits unset. | |
5236 | */ | |
5237 | static void | |
5238 | normalize_address_expr (expressionS *ex) | |
5239 | { | |
5240 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5241 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5242 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5243 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5244 | - 0x80000000); | |
5245 | } | |
5246 | ||
438c16b8 TS |
5247 | /* |
5248 | * Generate a "jalr" instruction with a relocation hint to the called | |
5249 | * function. This occurs in NewABI PIC code. | |
5250 | */ | |
5251 | static void | |
df58fc94 | 5252 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5253 | { |
df58fc94 RS |
5254 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5255 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5256 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5257 | const char *jalr; | |
685736be | 5258 | char *f = NULL; |
b34976b6 | 5259 | |
1180b5a4 | 5260 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5261 | { |
cc3d92a5 | 5262 | frag_grow (8); |
f21f8242 AO |
5263 | f = frag_more (0); |
5264 | } | |
df58fc94 RS |
5265 | if (!mips_opts.micromips) |
5266 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
5267 | else | |
5268 | { | |
5269 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5270 | if (MIPS_JALR_HINT_P (ep)) | |
5271 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5272 | else | |
5273 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5274 | } | |
1180b5a4 | 5275 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5276 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5277 | } |
5278 | ||
252b5132 RH |
5279 | /* |
5280 | * Generate a "lui" instruction. | |
5281 | */ | |
5282 | static void | |
67c0d1eb | 5283 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5284 | { |
9c2799c2 | 5285 | gas_assert (! mips_opts.mips16); |
252b5132 | 5286 | |
df58fc94 | 5287 | if (ep->X_op != O_constant) |
252b5132 | 5288 | { |
9c2799c2 | 5289 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5290 | /* _gp_disp is a special case, used from s_cpload. |
5291 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5292 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5293 | || (! HAVE_NEWABI |
aa6975fb ILT |
5294 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5295 | || (! mips_in_shared | |
bbe506e8 TS |
5296 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5297 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5298 | } |
5299 | ||
df58fc94 | 5300 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5301 | } |
5302 | ||
885add95 CD |
5303 | /* Generate a sequence of instructions to do a load or store from a constant |
5304 | offset off of a base register (breg) into/from a target register (treg), | |
5305 | using AT if necessary. */ | |
5306 | static void | |
67c0d1eb RS |
5307 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5308 | int treg, int breg, int dbl) | |
885add95 | 5309 | { |
9c2799c2 | 5310 | gas_assert (ep->X_op == O_constant); |
885add95 | 5311 | |
256ab948 | 5312 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5313 | if (!dbl) |
5314 | normalize_constant_expr (ep); | |
256ab948 | 5315 | |
67c1ffbe | 5316 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5317 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5318 | as_warn (_("operand overflow")); |
5319 | ||
5320 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5321 | { | |
5322 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5323 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5324 | } |
5325 | else | |
5326 | { | |
5327 | /* 32-bit offset, need multiple instructions and AT, like: | |
5328 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5329 | addu $tempreg,$tempreg,$breg | |
5330 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5331 | to handle the complete offset. */ | |
67c0d1eb RS |
5332 | macro_build_lui (ep, AT); |
5333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5334 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5335 | |
741fe287 | 5336 | if (!mips_opts.at) |
8fc2e39e | 5337 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5338 | } |
5339 | } | |
5340 | ||
252b5132 RH |
5341 | /* set_at() |
5342 | * Generates code to set the $at register to true (one) | |
5343 | * if reg is less than the immediate expression. | |
5344 | */ | |
5345 | static void | |
67c0d1eb | 5346 | set_at (int reg, int unsignedp) |
252b5132 RH |
5347 | { |
5348 | if (imm_expr.X_op == O_constant | |
5349 | && imm_expr.X_add_number >= -0x8000 | |
5350 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5351 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5352 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5353 | else |
5354 | { | |
67c0d1eb RS |
5355 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5356 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5357 | } |
5358 | } | |
5359 | ||
5360 | /* Warn if an expression is not a constant. */ | |
5361 | ||
5362 | static void | |
17a2f251 | 5363 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5364 | { |
5365 | if (ex->X_op == O_big) | |
5366 | as_bad (_("unsupported large constant")); | |
5367 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5368 | as_bad (_("Instruction %s requires absolute expression"), |
5369 | ip->insn_mo->name); | |
13757d0c | 5370 | |
9ee2a2d4 MR |
5371 | if (HAVE_32BIT_GPRS) |
5372 | normalize_constant_expr (ex); | |
252b5132 RH |
5373 | } |
5374 | ||
5375 | /* Count the leading zeroes by performing a binary chop. This is a | |
5376 | bulky bit of source, but performance is a LOT better for the | |
5377 | majority of values than a simple loop to count the bits: | |
5378 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5379 | if ((v) & (1 << (31 - lcnt))) | |
5380 | break; | |
5381 | However it is not code size friendly, and the gain will drop a bit | |
5382 | on certain cached systems. | |
5383 | */ | |
5384 | #define COUNT_TOP_ZEROES(v) \ | |
5385 | (((v) & ~0xffff) == 0 \ | |
5386 | ? ((v) & ~0xff) == 0 \ | |
5387 | ? ((v) & ~0xf) == 0 \ | |
5388 | ? ((v) & ~0x3) == 0 \ | |
5389 | ? ((v) & ~0x1) == 0 \ | |
5390 | ? !(v) \ | |
5391 | ? 32 \ | |
5392 | : 31 \ | |
5393 | : 30 \ | |
5394 | : ((v) & ~0x7) == 0 \ | |
5395 | ? 29 \ | |
5396 | : 28 \ | |
5397 | : ((v) & ~0x3f) == 0 \ | |
5398 | ? ((v) & ~0x1f) == 0 \ | |
5399 | ? 27 \ | |
5400 | : 26 \ | |
5401 | : ((v) & ~0x7f) == 0 \ | |
5402 | ? 25 \ | |
5403 | : 24 \ | |
5404 | : ((v) & ~0xfff) == 0 \ | |
5405 | ? ((v) & ~0x3ff) == 0 \ | |
5406 | ? ((v) & ~0x1ff) == 0 \ | |
5407 | ? 23 \ | |
5408 | : 22 \ | |
5409 | : ((v) & ~0x7ff) == 0 \ | |
5410 | ? 21 \ | |
5411 | : 20 \ | |
5412 | : ((v) & ~0x3fff) == 0 \ | |
5413 | ? ((v) & ~0x1fff) == 0 \ | |
5414 | ? 19 \ | |
5415 | : 18 \ | |
5416 | : ((v) & ~0x7fff) == 0 \ | |
5417 | ? 17 \ | |
5418 | : 16 \ | |
5419 | : ((v) & ~0xffffff) == 0 \ | |
5420 | ? ((v) & ~0xfffff) == 0 \ | |
5421 | ? ((v) & ~0x3ffff) == 0 \ | |
5422 | ? ((v) & ~0x1ffff) == 0 \ | |
5423 | ? 15 \ | |
5424 | : 14 \ | |
5425 | : ((v) & ~0x7ffff) == 0 \ | |
5426 | ? 13 \ | |
5427 | : 12 \ | |
5428 | : ((v) & ~0x3fffff) == 0 \ | |
5429 | ? ((v) & ~0x1fffff) == 0 \ | |
5430 | ? 11 \ | |
5431 | : 10 \ | |
5432 | : ((v) & ~0x7fffff) == 0 \ | |
5433 | ? 9 \ | |
5434 | : 8 \ | |
5435 | : ((v) & ~0xfffffff) == 0 \ | |
5436 | ? ((v) & ~0x3ffffff) == 0 \ | |
5437 | ? ((v) & ~0x1ffffff) == 0 \ | |
5438 | ? 7 \ | |
5439 | : 6 \ | |
5440 | : ((v) & ~0x7ffffff) == 0 \ | |
5441 | ? 5 \ | |
5442 | : 4 \ | |
5443 | : ((v) & ~0x3fffffff) == 0 \ | |
5444 | ? ((v) & ~0x1fffffff) == 0 \ | |
5445 | ? 3 \ | |
5446 | : 2 \ | |
5447 | : ((v) & ~0x7fffffff) == 0 \ | |
5448 | ? 1 \ | |
5449 | : 0) | |
5450 | ||
5451 | /* load_register() | |
67c1ffbe | 5452 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5453 | * an absolute expression value into a register. |
5454 | */ | |
5455 | static void | |
67c0d1eb | 5456 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5457 | { |
5458 | int freg; | |
5459 | expressionS hi32, lo32; | |
5460 | ||
5461 | if (ep->X_op != O_big) | |
5462 | { | |
9c2799c2 | 5463 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5464 | |
5465 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5466 | if (!dbl) |
5467 | normalize_constant_expr (ep); | |
256ab948 TS |
5468 | |
5469 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5470 | { |
5471 | /* We can handle 16 bit signed values with an addiu to | |
5472 | $zero. No need to ever use daddiu here, since $zero and | |
5473 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5474 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5475 | return; |
5476 | } | |
5477 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5478 | { | |
5479 | /* We can handle 16 bit unsigned values with an ori to | |
5480 | $zero. */ | |
67c0d1eb | 5481 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5482 | return; |
5483 | } | |
256ab948 | 5484 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5485 | { |
5486 | /* 32 bit values require an lui. */ | |
df58fc94 | 5487 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5488 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5489 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5490 | return; |
5491 | } | |
5492 | } | |
5493 | ||
5494 | /* The value is larger than 32 bits. */ | |
5495 | ||
2051e8c4 | 5496 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5497 | { |
55e08f71 NC |
5498 | char value[32]; |
5499 | ||
5500 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5501 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5502 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5503 | return; |
5504 | } | |
5505 | ||
5506 | if (ep->X_op != O_big) | |
5507 | { | |
5508 | hi32 = *ep; | |
5509 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5510 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5511 | hi32.X_add_number &= 0xffffffff; | |
5512 | lo32 = *ep; | |
5513 | lo32.X_add_number &= 0xffffffff; | |
5514 | } | |
5515 | else | |
5516 | { | |
9c2799c2 | 5517 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5518 | if (ep->X_add_number == 3) |
5519 | generic_bignum[3] = 0; | |
5520 | else if (ep->X_add_number > 4) | |
5521 | as_bad (_("Number larger than 64 bits")); | |
5522 | lo32.X_op = O_constant; | |
5523 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5524 | hi32.X_op = O_constant; | |
5525 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5526 | } | |
5527 | ||
5528 | if (hi32.X_add_number == 0) | |
5529 | freg = 0; | |
5530 | else | |
5531 | { | |
5532 | int shift, bit; | |
5533 | unsigned long hi, lo; | |
5534 | ||
956cd1d6 | 5535 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5536 | { |
5537 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5538 | { | |
67c0d1eb | 5539 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5540 | return; |
5541 | } | |
5542 | if (lo32.X_add_number & 0x80000000) | |
5543 | { | |
df58fc94 | 5544 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5545 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5546 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5547 | return; |
5548 | } | |
5549 | } | |
252b5132 RH |
5550 | |
5551 | /* Check for 16bit shifted constant. We know that hi32 is | |
5552 | non-zero, so start the mask on the first bit of the hi32 | |
5553 | value. */ | |
5554 | shift = 17; | |
5555 | do | |
beae10d5 KH |
5556 | { |
5557 | unsigned long himask, lomask; | |
5558 | ||
5559 | if (shift < 32) | |
5560 | { | |
5561 | himask = 0xffff >> (32 - shift); | |
5562 | lomask = (0xffff << shift) & 0xffffffff; | |
5563 | } | |
5564 | else | |
5565 | { | |
5566 | himask = 0xffff << (shift - 32); | |
5567 | lomask = 0; | |
5568 | } | |
5569 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5570 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5571 | { | |
5572 | expressionS tmp; | |
5573 | ||
5574 | tmp.X_op = O_constant; | |
5575 | if (shift < 32) | |
5576 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5577 | | (lo32.X_add_number >> shift)); | |
5578 | else | |
5579 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5580 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5581 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5582 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5583 | return; |
5584 | } | |
f9419b05 | 5585 | ++shift; |
beae10d5 KH |
5586 | } |
5587 | while (shift <= (64 - 16)); | |
252b5132 RH |
5588 | |
5589 | /* Find the bit number of the lowest one bit, and store the | |
5590 | shifted value in hi/lo. */ | |
5591 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5592 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5593 | if (lo != 0) | |
5594 | { | |
5595 | bit = 0; | |
5596 | while ((lo & 1) == 0) | |
5597 | { | |
5598 | lo >>= 1; | |
5599 | ++bit; | |
5600 | } | |
5601 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5602 | hi >>= bit; | |
5603 | } | |
5604 | else | |
5605 | { | |
5606 | bit = 32; | |
5607 | while ((hi & 1) == 0) | |
5608 | { | |
5609 | hi >>= 1; | |
5610 | ++bit; | |
5611 | } | |
5612 | lo = hi; | |
5613 | hi = 0; | |
5614 | } | |
5615 | ||
5616 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5617 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5618 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5619 | { |
5620 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5621 | if (shift != 0) |
beae10d5 | 5622 | { |
252b5132 RH |
5623 | expressionS tmp; |
5624 | ||
5625 | /* This instruction will set the register to be all | |
5626 | ones. */ | |
beae10d5 KH |
5627 | tmp.X_op = O_constant; |
5628 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5629 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5630 | if (bit != 0) |
5631 | { | |
5632 | bit += shift; | |
df58fc94 | 5633 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5634 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5635 | } |
df58fc94 | 5636 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5637 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5638 | return; |
5639 | } | |
5640 | } | |
252b5132 RH |
5641 | |
5642 | /* Sign extend hi32 before calling load_register, because we can | |
5643 | generally get better code when we load a sign extended value. */ | |
5644 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5645 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5646 | load_register (reg, &hi32, 0); |
252b5132 RH |
5647 | freg = reg; |
5648 | } | |
5649 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5650 | { | |
5651 | if (freg != 0) | |
5652 | { | |
df58fc94 | 5653 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5654 | freg = reg; |
5655 | } | |
5656 | } | |
5657 | else | |
5658 | { | |
5659 | expressionS mid16; | |
5660 | ||
956cd1d6 | 5661 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5662 | { |
df58fc94 RS |
5663 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5664 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5665 | return; |
5666 | } | |
252b5132 RH |
5667 | |
5668 | if (freg != 0) | |
5669 | { | |
df58fc94 | 5670 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5671 | freg = reg; |
5672 | } | |
5673 | mid16 = lo32; | |
5674 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5675 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5676 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5677 | freg = reg; |
5678 | } | |
5679 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5680 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5681 | } |
5682 | ||
269137b2 TS |
5683 | static inline void |
5684 | load_delay_nop (void) | |
5685 | { | |
5686 | if (!gpr_interlocks) | |
5687 | macro_build (NULL, "nop", ""); | |
5688 | } | |
5689 | ||
252b5132 RH |
5690 | /* Load an address into a register. */ |
5691 | ||
5692 | static void | |
67c0d1eb | 5693 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5694 | { |
252b5132 RH |
5695 | if (ep->X_op != O_constant |
5696 | && ep->X_op != O_symbol) | |
5697 | { | |
5698 | as_bad (_("expression too complex")); | |
5699 | ep->X_op = O_constant; | |
5700 | } | |
5701 | ||
5702 | if (ep->X_op == O_constant) | |
5703 | { | |
67c0d1eb | 5704 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5705 | return; |
5706 | } | |
5707 | ||
5708 | if (mips_pic == NO_PIC) | |
5709 | { | |
5710 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5711 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5712 | Otherwise we want |
5713 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5714 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5715 | If we have an addend, we always use the latter form. |
76b3015f | 5716 | |
d6bc6245 TS |
5717 | With 64bit address space and a usable $at we want |
5718 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5719 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5720 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5721 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5722 | dsll32 $reg,0 | |
3a482fd5 | 5723 | daddu $reg,$reg,$at |
76b3015f | 5724 | |
c03099e6 | 5725 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5726 | on superscalar processors. |
5727 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5728 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5729 | dsll $reg,16 | |
5730 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5731 | dsll $reg,16 | |
5732 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5733 | |
5734 | For GP relative symbols in 64bit address space we can use | |
5735 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5736 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5737 | { |
6caf9ef4 TS |
5738 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5739 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5740 | { | |
5741 | relax_start (ep->X_add_symbol); | |
5742 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5743 | mips_gp_register, BFD_RELOC_GPREL16); | |
5744 | relax_switch (); | |
5745 | } | |
d6bc6245 | 5746 | |
741fe287 | 5747 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5748 | { |
df58fc94 RS |
5749 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5750 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5751 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5752 | BFD_RELOC_MIPS_HIGHER); | |
5753 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5754 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5755 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5756 | *used_at = 1; |
5757 | } | |
5758 | else | |
5759 | { | |
df58fc94 | 5760 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5761 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5762 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5763 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5764 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5765 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5766 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5767 | } |
6caf9ef4 TS |
5768 | |
5769 | if (mips_relax.sequence) | |
5770 | relax_end (); | |
d6bc6245 | 5771 | } |
252b5132 RH |
5772 | else |
5773 | { | |
d6bc6245 | 5774 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5775 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5776 | { |
4d7206a2 | 5777 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5778 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5779 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5780 | relax_switch (); |
d6bc6245 | 5781 | } |
67c0d1eb RS |
5782 | macro_build_lui (ep, reg); |
5783 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5784 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5785 | if (mips_relax.sequence) |
5786 | relax_end (); | |
d6bc6245 | 5787 | } |
252b5132 | 5788 | } |
0a44bf69 | 5789 | else if (!mips_big_got) |
252b5132 RH |
5790 | { |
5791 | expressionS ex; | |
5792 | ||
5793 | /* If this is a reference to an external symbol, we want | |
5794 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5795 | Otherwise we want | |
5796 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5797 | nop | |
5798 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5799 | If there is a constant, it must be added in after. |
5800 | ||
ed6fb7bd | 5801 | If we have NewABI, we want |
f5040a92 AO |
5802 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5803 | unless we're referencing a global symbol with a non-zero | |
5804 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5805 | if (HAVE_NEWABI) |
5806 | { | |
f5040a92 AO |
5807 | if (ep->X_add_number) |
5808 | { | |
4d7206a2 | 5809 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5810 | ep->X_add_number = 0; |
4d7206a2 | 5811 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5812 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5813 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5814 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5815 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5816 | ex.X_op = O_constant; | |
67c0d1eb | 5817 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5818 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5819 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5820 | relax_switch (); |
f5040a92 | 5821 | } |
67c0d1eb | 5822 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5823 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5824 | if (mips_relax.sequence) |
5825 | relax_end (); | |
ed6fb7bd SC |
5826 | } |
5827 | else | |
5828 | { | |
f5040a92 AO |
5829 | ex.X_add_number = ep->X_add_number; |
5830 | ep->X_add_number = 0; | |
67c0d1eb RS |
5831 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5832 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5833 | load_delay_nop (); |
4d7206a2 RS |
5834 | relax_start (ep->X_add_symbol); |
5835 | relax_switch (); | |
67c0d1eb | 5836 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5837 | BFD_RELOC_LO16); |
4d7206a2 | 5838 | relax_end (); |
ed6fb7bd | 5839 | |
f5040a92 AO |
5840 | if (ex.X_add_number != 0) |
5841 | { | |
5842 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5843 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5844 | ex.X_op = O_constant; | |
67c0d1eb | 5845 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5846 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5847 | } |
252b5132 RH |
5848 | } |
5849 | } | |
0a44bf69 | 5850 | else if (mips_big_got) |
252b5132 RH |
5851 | { |
5852 | expressionS ex; | |
252b5132 RH |
5853 | |
5854 | /* This is the large GOT case. If this is a reference to an | |
5855 | external symbol, we want | |
5856 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5857 | addu $reg,$reg,$gp | |
5858 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5859 | |
5860 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5861 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5862 | nop | |
5863 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5864 | If there is a constant, it must be added in after. |
f5040a92 AO |
5865 | |
5866 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5867 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5868 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5869 | */ |
438c16b8 TS |
5870 | if (HAVE_NEWABI) |
5871 | { | |
4d7206a2 | 5872 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5873 | ep->X_add_number = 0; |
4d7206a2 | 5874 | relax_start (ep->X_add_symbol); |
df58fc94 | 5875 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5876 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5877 | reg, reg, mips_gp_register); | |
5878 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5879 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5880 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5881 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5882 | else if (ex.X_add_number) | |
5883 | { | |
5884 | ex.X_op = O_constant; | |
67c0d1eb RS |
5885 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5886 | BFD_RELOC_LO16); | |
f5040a92 AO |
5887 | } |
5888 | ||
5889 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5890 | relax_switch (); |
67c0d1eb | 5891 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5892 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5893 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5894 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5895 | relax_end (); |
438c16b8 | 5896 | } |
252b5132 | 5897 | else |
438c16b8 | 5898 | { |
f5040a92 AO |
5899 | ex.X_add_number = ep->X_add_number; |
5900 | ep->X_add_number = 0; | |
4d7206a2 | 5901 | relax_start (ep->X_add_symbol); |
df58fc94 | 5902 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5903 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5904 | reg, reg, mips_gp_register); | |
5905 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5906 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5907 | relax_switch (); |
5908 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5909 | { |
5910 | /* We need a nop before loading from $gp. This special | |
5911 | check is required because the lui which starts the main | |
5912 | instruction stream does not refer to $gp, and so will not | |
5913 | insert the nop which may be required. */ | |
67c0d1eb | 5914 | macro_build (NULL, "nop", ""); |
438c16b8 | 5915 | } |
67c0d1eb | 5916 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5917 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5918 | load_delay_nop (); |
67c0d1eb | 5919 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5920 | BFD_RELOC_LO16); |
4d7206a2 | 5921 | relax_end (); |
438c16b8 | 5922 | |
f5040a92 AO |
5923 | if (ex.X_add_number != 0) |
5924 | { | |
5925 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5926 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5927 | ex.X_op = O_constant; | |
67c0d1eb RS |
5928 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5929 | BFD_RELOC_LO16); | |
f5040a92 | 5930 | } |
252b5132 RH |
5931 | } |
5932 | } | |
252b5132 RH |
5933 | else |
5934 | abort (); | |
8fc2e39e | 5935 | |
741fe287 | 5936 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5937 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5938 | } |
5939 | ||
ea1fb5dc RS |
5940 | /* Move the contents of register SOURCE into register DEST. */ |
5941 | ||
5942 | static void | |
67c0d1eb | 5943 | move_register (int dest, int source) |
ea1fb5dc | 5944 | { |
df58fc94 RS |
5945 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5946 | instruction specifically requires a 32-bit one. */ | |
5947 | if (mips_opts.micromips | |
5948 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
5949 | macro_build (NULL, "move", "mp,mj", dest, source ); | |
5950 | else | |
5951 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5952 | dest, source, 0); | |
ea1fb5dc RS |
5953 | } |
5954 | ||
4d7206a2 | 5955 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5956 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5957 | The two alternatives are: | |
4d7206a2 RS |
5958 | |
5959 | Global symbol Local sybmol | |
5960 | ------------- ------------ | |
5961 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5962 | ... ... | |
5963 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5964 | ||
5965 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5966 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5967 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5968 | |
5969 | static void | |
67c0d1eb | 5970 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5971 | { |
5972 | expressionS global; | |
5973 | ||
5974 | global = *local; | |
5975 | global.X_add_number = 0; | |
5976 | ||
5977 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5978 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5979 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5980 | relax_switch (); |
67c0d1eb RS |
5981 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5982 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5983 | relax_end (); |
5984 | } | |
5985 | ||
5986 | static void | |
67c0d1eb | 5987 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5988 | { |
5989 | expressionS global; | |
5990 | ||
5991 | global.X_op = O_constant; | |
5992 | global.X_op_symbol = NULL; | |
5993 | global.X_add_symbol = NULL; | |
5994 | global.X_add_number = local->X_add_number; | |
5995 | ||
5996 | relax_start (local->X_add_symbol); | |
67c0d1eb | 5997 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
5998 | dest, dest, BFD_RELOC_LO16); |
5999 | relax_switch (); | |
67c0d1eb | 6000 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6001 | relax_end (); |
6002 | } | |
6003 | ||
f6a22291 MR |
6004 | static void |
6005 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6006 | { | |
6007 | expressionS global; | |
6008 | int hold_mips_optimize; | |
6009 | ||
6010 | global.X_op = O_constant; | |
6011 | global.X_op_symbol = NULL; | |
6012 | global.X_add_symbol = NULL; | |
6013 | global.X_add_number = local->X_add_number; | |
6014 | ||
6015 | relax_start (local->X_add_symbol); | |
6016 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6017 | relax_switch (); | |
6018 | /* Set mips_optimize around the lui instruction to avoid | |
6019 | inserting an unnecessary nop after the lw. */ | |
6020 | hold_mips_optimize = mips_optimize; | |
6021 | mips_optimize = 2; | |
6022 | macro_build_lui (&global, tmp); | |
6023 | mips_optimize = hold_mips_optimize; | |
6024 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6025 | relax_end (); | |
6026 | ||
6027 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6028 | } | |
6029 | ||
df58fc94 RS |
6030 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6031 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6032 | is its complementing branch with the original condition negated. | |
6033 | CALL is set if the original branch specified the link operation. | |
6034 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6035 | ||
6036 | Code like this is produced in the noreorder mode: | |
6037 | ||
6038 | BRNEG <args>, 1f | |
6039 | nop | |
6040 | b <sym> | |
6041 | delay slot (executed only if branch taken) | |
6042 | 1: | |
6043 | ||
6044 | or, if CALL is set: | |
6045 | ||
6046 | BRNEG <args>, 1f | |
6047 | nop | |
6048 | bal <sym> | |
6049 | delay slot (executed only if branch taken) | |
6050 | 1: | |
6051 | ||
6052 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6053 | so code produced is simply: | |
6054 | ||
6055 | BR <args>, <sym> | |
6056 | nop | |
6057 | ||
6058 | This function is used when producing code for the microMIPS ASE that | |
6059 | does not implement branch likely instructions in hardware. */ | |
6060 | ||
6061 | static void | |
6062 | macro_build_branch_likely (const char *br, const char *brneg, | |
6063 | int call, expressionS *ep, const char *fmt, | |
6064 | unsigned int sreg, unsigned int treg) | |
6065 | { | |
6066 | int noreorder = mips_opts.noreorder; | |
6067 | expressionS expr1; | |
6068 | ||
6069 | gas_assert (mips_opts.micromips); | |
6070 | start_noreorder (); | |
6071 | if (noreorder) | |
6072 | { | |
6073 | micromips_label_expr (&expr1); | |
6074 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6075 | macro_build (NULL, "nop", ""); | |
6076 | macro_build (ep, call ? "bal" : "b", "p"); | |
6077 | ||
6078 | /* Set to true so that append_insn adds a label. */ | |
6079 | emit_branch_likely_macro = TRUE; | |
6080 | } | |
6081 | else | |
6082 | { | |
6083 | macro_build (ep, br, fmt, sreg, treg); | |
6084 | macro_build (NULL, "nop", ""); | |
6085 | } | |
6086 | end_noreorder (); | |
6087 | } | |
6088 | ||
6089 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6090 | the condition code tested. EP specifies the branch target. */ | |
6091 | ||
6092 | static void | |
6093 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6094 | { | |
6095 | const int call = 0; | |
6096 | const char *brneg; | |
6097 | const char *br; | |
6098 | ||
6099 | switch (type) | |
6100 | { | |
6101 | case M_BC1FL: | |
6102 | br = "bc1f"; | |
6103 | brneg = "bc1t"; | |
6104 | break; | |
6105 | case M_BC1TL: | |
6106 | br = "bc1t"; | |
6107 | brneg = "bc1f"; | |
6108 | break; | |
6109 | case M_BC2FL: | |
6110 | br = "bc2f"; | |
6111 | brneg = "bc2t"; | |
6112 | break; | |
6113 | case M_BC2TL: | |
6114 | br = "bc2t"; | |
6115 | brneg = "bc2f"; | |
6116 | break; | |
6117 | default: | |
6118 | abort (); | |
6119 | } | |
6120 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6121 | } | |
6122 | ||
6123 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6124 | the register tested. EP specifies the branch target. */ | |
6125 | ||
6126 | static void | |
6127 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6128 | { | |
6129 | const char *brneg = NULL; | |
6130 | const char *br; | |
6131 | int call = 0; | |
6132 | ||
6133 | switch (type) | |
6134 | { | |
6135 | case M_BGEZ: | |
6136 | br = "bgez"; | |
6137 | break; | |
6138 | case M_BGEZL: | |
6139 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6140 | brneg = "bltz"; | |
6141 | break; | |
6142 | case M_BGEZALL: | |
6143 | gas_assert (mips_opts.micromips); | |
6144 | br = "bgezals"; | |
6145 | brneg = "bltz"; | |
6146 | call = 1; | |
6147 | break; | |
6148 | case M_BGTZ: | |
6149 | br = "bgtz"; | |
6150 | break; | |
6151 | case M_BGTZL: | |
6152 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6153 | brneg = "blez"; | |
6154 | break; | |
6155 | case M_BLEZ: | |
6156 | br = "blez"; | |
6157 | break; | |
6158 | case M_BLEZL: | |
6159 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6160 | brneg = "bgtz"; | |
6161 | break; | |
6162 | case M_BLTZ: | |
6163 | br = "bltz"; | |
6164 | break; | |
6165 | case M_BLTZL: | |
6166 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6167 | brneg = "bgez"; | |
6168 | break; | |
6169 | case M_BLTZALL: | |
6170 | gas_assert (mips_opts.micromips); | |
6171 | br = "bltzals"; | |
6172 | brneg = "bgez"; | |
6173 | call = 1; | |
6174 | break; | |
6175 | default: | |
6176 | abort (); | |
6177 | } | |
6178 | if (mips_opts.micromips && brneg) | |
6179 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6180 | else | |
6181 | macro_build (ep, br, "s,p", sreg); | |
6182 | } | |
6183 | ||
6184 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6185 | TREG as the registers tested. EP specifies the branch target. */ | |
6186 | ||
6187 | static void | |
6188 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6189 | unsigned int sreg, unsigned int treg) | |
6190 | { | |
6191 | const char *brneg = NULL; | |
6192 | const int call = 0; | |
6193 | const char *br; | |
6194 | ||
6195 | switch (type) | |
6196 | { | |
6197 | case M_BEQ: | |
6198 | case M_BEQ_I: | |
6199 | br = "beq"; | |
6200 | break; | |
6201 | case M_BEQL: | |
6202 | case M_BEQL_I: | |
6203 | br = mips_opts.micromips ? "beq" : "beql"; | |
6204 | brneg = "bne"; | |
6205 | break; | |
6206 | case M_BNE: | |
6207 | case M_BNE_I: | |
6208 | br = "bne"; | |
6209 | break; | |
6210 | case M_BNEL: | |
6211 | case M_BNEL_I: | |
6212 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6213 | brneg = "beq"; | |
6214 | break; | |
6215 | default: | |
6216 | abort (); | |
6217 | } | |
6218 | if (mips_opts.micromips && brneg) | |
6219 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6220 | else | |
6221 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6222 | } | |
6223 | ||
252b5132 RH |
6224 | /* |
6225 | * Build macros | |
6226 | * This routine implements the seemingly endless macro or synthesized | |
6227 | * instructions and addressing modes in the mips assembly language. Many | |
6228 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6229 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6230 | * this verbose method. Others are not simple macros but are more like |
6231 | * optimizing code generation. | |
6232 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6233 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6234 | * The ensuing load upper instructions are ommited. This implies some kind |
6235 | * of global optimization. We currently only optimize within a single macro. | |
6236 | * For many of the load and store macros if the address is specified as a | |
6237 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6238 | * first load register 'at' with zero and use it as the base register. The | |
6239 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6240 | * we're missing. | |
6241 | */ | |
6242 | static void | |
17a2f251 | 6243 | macro (struct mips_cl_insn *ip) |
252b5132 | 6244 | { |
741fe287 MR |
6245 | unsigned int treg, sreg, dreg, breg; |
6246 | unsigned int tempreg; | |
252b5132 | 6247 | int mask; |
43841e91 | 6248 | int used_at = 0; |
df58fc94 | 6249 | expressionS label_expr; |
252b5132 | 6250 | expressionS expr1; |
df58fc94 | 6251 | expressionS *ep; |
252b5132 RH |
6252 | const char *s; |
6253 | const char *s2; | |
6254 | const char *fmt; | |
6255 | int likely = 0; | |
252b5132 | 6256 | int coproc = 0; |
df58fc94 | 6257 | int off12 = 0; |
1abe91b1 | 6258 | int call = 0; |
df58fc94 RS |
6259 | int jals = 0; |
6260 | int dbl = 0; | |
6261 | int imm = 0; | |
6262 | int ust = 0; | |
6263 | int lp = 0; | |
6264 | int ab = 0; | |
252b5132 | 6265 | int off; |
67c0d1eb | 6266 | offsetT maxnum; |
252b5132 | 6267 | bfd_reloc_code_real_type r; |
252b5132 RH |
6268 | int hold_mips_optimize; |
6269 | ||
9c2799c2 | 6270 | gas_assert (! mips_opts.mips16); |
252b5132 | 6271 | |
df58fc94 RS |
6272 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6273 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6274 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6275 | mask = ip->insn_mo->mask; |
6276 | ||
df58fc94 RS |
6277 | label_expr.X_op = O_constant; |
6278 | label_expr.X_op_symbol = NULL; | |
6279 | label_expr.X_add_symbol = NULL; | |
6280 | label_expr.X_add_number = 0; | |
6281 | ||
252b5132 RH |
6282 | expr1.X_op = O_constant; |
6283 | expr1.X_op_symbol = NULL; | |
6284 | expr1.X_add_symbol = NULL; | |
6285 | expr1.X_add_number = 1; | |
6286 | ||
6287 | switch (mask) | |
6288 | { | |
6289 | case M_DABS: | |
6290 | dbl = 1; | |
6291 | case M_ABS: | |
df58fc94 RS |
6292 | /* bgez $a0,1f |
6293 | move v0,$a0 | |
6294 | sub v0,$zero,$a0 | |
6295 | 1: | |
6296 | */ | |
252b5132 | 6297 | |
7d10b47d | 6298 | start_noreorder (); |
252b5132 | 6299 | |
df58fc94 RS |
6300 | if (mips_opts.micromips) |
6301 | micromips_label_expr (&label_expr); | |
6302 | else | |
6303 | label_expr.X_add_number = 8; | |
6304 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6305 | if (dreg == sreg) |
a605d2b3 | 6306 | macro_build (NULL, "nop", ""); |
252b5132 | 6307 | else |
67c0d1eb RS |
6308 | move_register (dreg, sreg); |
6309 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6310 | if (mips_opts.micromips) |
6311 | micromips_add_label (); | |
252b5132 | 6312 | |
7d10b47d | 6313 | end_noreorder (); |
8fc2e39e | 6314 | break; |
252b5132 RH |
6315 | |
6316 | case M_ADD_I: | |
6317 | s = "addi"; | |
6318 | s2 = "add"; | |
6319 | goto do_addi; | |
6320 | case M_ADDU_I: | |
6321 | s = "addiu"; | |
6322 | s2 = "addu"; | |
6323 | goto do_addi; | |
6324 | case M_DADD_I: | |
6325 | dbl = 1; | |
6326 | s = "daddi"; | |
6327 | s2 = "dadd"; | |
df58fc94 RS |
6328 | if (!mips_opts.micromips) |
6329 | goto do_addi; | |
6330 | if (imm_expr.X_op == O_constant | |
6331 | && imm_expr.X_add_number >= -0x200 | |
6332 | && imm_expr.X_add_number < 0x200) | |
6333 | { | |
6334 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6335 | break; | |
6336 | } | |
6337 | goto do_addi_i; | |
252b5132 RH |
6338 | case M_DADDU_I: |
6339 | dbl = 1; | |
6340 | s = "daddiu"; | |
6341 | s2 = "daddu"; | |
6342 | do_addi: | |
6343 | if (imm_expr.X_op == O_constant | |
6344 | && imm_expr.X_add_number >= -0x8000 | |
6345 | && imm_expr.X_add_number < 0x8000) | |
6346 | { | |
67c0d1eb | 6347 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6348 | break; |
252b5132 | 6349 | } |
df58fc94 | 6350 | do_addi_i: |
8fc2e39e | 6351 | used_at = 1; |
67c0d1eb RS |
6352 | load_register (AT, &imm_expr, dbl); |
6353 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6354 | break; |
6355 | ||
6356 | case M_AND_I: | |
6357 | s = "andi"; | |
6358 | s2 = "and"; | |
6359 | goto do_bit; | |
6360 | case M_OR_I: | |
6361 | s = "ori"; | |
6362 | s2 = "or"; | |
6363 | goto do_bit; | |
6364 | case M_NOR_I: | |
6365 | s = ""; | |
6366 | s2 = "nor"; | |
6367 | goto do_bit; | |
6368 | case M_XOR_I: | |
6369 | s = "xori"; | |
6370 | s2 = "xor"; | |
6371 | do_bit: | |
6372 | if (imm_expr.X_op == O_constant | |
6373 | && imm_expr.X_add_number >= 0 | |
6374 | && imm_expr.X_add_number < 0x10000) | |
6375 | { | |
6376 | if (mask != M_NOR_I) | |
67c0d1eb | 6377 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6378 | else |
6379 | { | |
67c0d1eb RS |
6380 | macro_build (&imm_expr, "ori", "t,r,i", |
6381 | treg, sreg, BFD_RELOC_LO16); | |
6382 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6383 | } |
8fc2e39e | 6384 | break; |
252b5132 RH |
6385 | } |
6386 | ||
8fc2e39e | 6387 | used_at = 1; |
67c0d1eb RS |
6388 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6389 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6390 | break; |
6391 | ||
8b082fb1 TS |
6392 | case M_BALIGN: |
6393 | switch (imm_expr.X_add_number) | |
6394 | { | |
6395 | case 0: | |
6396 | macro_build (NULL, "nop", ""); | |
6397 | break; | |
6398 | case 2: | |
6399 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6400 | break; | |
6401 | default: | |
6402 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 6403 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
6404 | break; |
6405 | } | |
6406 | break; | |
6407 | ||
df58fc94 RS |
6408 | case M_BC1FL: |
6409 | case M_BC1TL: | |
6410 | case M_BC2FL: | |
6411 | case M_BC2TL: | |
6412 | gas_assert (mips_opts.micromips); | |
6413 | macro_build_branch_ccl (mask, &offset_expr, | |
6414 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6415 | break; | |
6416 | ||
252b5132 | 6417 | case M_BEQ_I: |
252b5132 | 6418 | case M_BEQL_I: |
252b5132 | 6419 | case M_BNE_I: |
252b5132 | 6420 | case M_BNEL_I: |
252b5132 | 6421 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6422 | treg = 0; |
6423 | else | |
252b5132 | 6424 | { |
df58fc94 RS |
6425 | treg = AT; |
6426 | used_at = 1; | |
6427 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6428 | } |
df58fc94 RS |
6429 | /* Fall through. */ |
6430 | case M_BEQL: | |
6431 | case M_BNEL: | |
6432 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6433 | break; |
6434 | ||
6435 | case M_BGEL: | |
6436 | likely = 1; | |
6437 | case M_BGE: | |
6438 | if (treg == 0) | |
df58fc94 RS |
6439 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6440 | else if (sreg == 0) | |
6441 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6442 | else | |
252b5132 | 6443 | { |
df58fc94 RS |
6444 | used_at = 1; |
6445 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6446 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6447 | &offset_expr, AT, ZERO); | |
252b5132 | 6448 | } |
df58fc94 RS |
6449 | break; |
6450 | ||
6451 | case M_BGEZL: | |
6452 | case M_BGEZALL: | |
6453 | case M_BGTZL: | |
6454 | case M_BLEZL: | |
6455 | case M_BLTZL: | |
6456 | case M_BLTZALL: | |
6457 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6458 | break; |
6459 | ||
6460 | case M_BGTL_I: | |
6461 | likely = 1; | |
6462 | case M_BGT_I: | |
90ecf173 | 6463 | /* Check for > max integer. */ |
252b5132 | 6464 | maxnum = 0x7fffffff; |
ca4e0257 | 6465 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6466 | { |
6467 | maxnum <<= 16; | |
6468 | maxnum |= 0xffff; | |
6469 | maxnum <<= 16; | |
6470 | maxnum |= 0xffff; | |
6471 | } | |
6472 | if (imm_expr.X_op == O_constant | |
6473 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6474 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6475 | { |
6476 | do_false: | |
90ecf173 | 6477 | /* Result is always false. */ |
252b5132 | 6478 | if (! likely) |
a605d2b3 | 6479 | macro_build (NULL, "nop", ""); |
252b5132 | 6480 | else |
df58fc94 | 6481 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6482 | break; |
252b5132 RH |
6483 | } |
6484 | if (imm_expr.X_op != O_constant) | |
6485 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6486 | ++imm_expr.X_add_number; |
252b5132 RH |
6487 | /* FALLTHROUGH */ |
6488 | case M_BGE_I: | |
6489 | case M_BGEL_I: | |
6490 | if (mask == M_BGEL_I) | |
6491 | likely = 1; | |
6492 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6493 | { | |
df58fc94 RS |
6494 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6495 | &offset_expr, sreg); | |
8fc2e39e | 6496 | break; |
252b5132 RH |
6497 | } |
6498 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6499 | { | |
df58fc94 RS |
6500 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6501 | &offset_expr, sreg); | |
8fc2e39e | 6502 | break; |
252b5132 RH |
6503 | } |
6504 | maxnum = 0x7fffffff; | |
ca4e0257 | 6505 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6506 | { |
6507 | maxnum <<= 16; | |
6508 | maxnum |= 0xffff; | |
6509 | maxnum <<= 16; | |
6510 | maxnum |= 0xffff; | |
6511 | } | |
6512 | maxnum = - maxnum - 1; | |
6513 | if (imm_expr.X_op == O_constant | |
6514 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6515 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6516 | { |
6517 | do_true: | |
6518 | /* result is always true */ | |
6519 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6520 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6521 | break; |
252b5132 | 6522 | } |
8fc2e39e | 6523 | used_at = 1; |
67c0d1eb | 6524 | set_at (sreg, 0); |
df58fc94 RS |
6525 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6526 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6527 | break; |
6528 | ||
6529 | case M_BGEUL: | |
6530 | likely = 1; | |
6531 | case M_BGEU: | |
6532 | if (treg == 0) | |
6533 | goto do_true; | |
df58fc94 RS |
6534 | else if (sreg == 0) |
6535 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6536 | &offset_expr, ZERO, treg); | |
6537 | else | |
252b5132 | 6538 | { |
df58fc94 RS |
6539 | used_at = 1; |
6540 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6541 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6542 | &offset_expr, AT, ZERO); | |
252b5132 | 6543 | } |
252b5132 RH |
6544 | break; |
6545 | ||
6546 | case M_BGTUL_I: | |
6547 | likely = 1; | |
6548 | case M_BGTU_I: | |
6549 | if (sreg == 0 | |
ca4e0257 | 6550 | || (HAVE_32BIT_GPRS |
252b5132 | 6551 | && imm_expr.X_op == O_constant |
f01dc953 | 6552 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6553 | goto do_false; |
6554 | if (imm_expr.X_op != O_constant) | |
6555 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6556 | ++imm_expr.X_add_number; |
252b5132 RH |
6557 | /* FALLTHROUGH */ |
6558 | case M_BGEU_I: | |
6559 | case M_BGEUL_I: | |
6560 | if (mask == M_BGEUL_I) | |
6561 | likely = 1; | |
6562 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6563 | goto do_true; | |
df58fc94 RS |
6564 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6565 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6566 | &offset_expr, sreg, ZERO); | |
6567 | else | |
252b5132 | 6568 | { |
df58fc94 RS |
6569 | used_at = 1; |
6570 | set_at (sreg, 1); | |
6571 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6572 | &offset_expr, AT, ZERO); | |
252b5132 | 6573 | } |
252b5132 RH |
6574 | break; |
6575 | ||
6576 | case M_BGTL: | |
6577 | likely = 1; | |
6578 | case M_BGT: | |
6579 | if (treg == 0) | |
df58fc94 RS |
6580 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6581 | else if (sreg == 0) | |
6582 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6583 | else | |
252b5132 | 6584 | { |
df58fc94 RS |
6585 | used_at = 1; |
6586 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6587 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6588 | &offset_expr, AT, ZERO); | |
252b5132 | 6589 | } |
252b5132 RH |
6590 | break; |
6591 | ||
6592 | case M_BGTUL: | |
6593 | likely = 1; | |
6594 | case M_BGTU: | |
6595 | if (treg == 0) | |
df58fc94 RS |
6596 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6597 | &offset_expr, sreg, ZERO); | |
6598 | else if (sreg == 0) | |
6599 | goto do_false; | |
6600 | else | |
252b5132 | 6601 | { |
df58fc94 RS |
6602 | used_at = 1; |
6603 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6604 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6605 | &offset_expr, AT, ZERO); | |
252b5132 | 6606 | } |
252b5132 RH |
6607 | break; |
6608 | ||
6609 | case M_BLEL: | |
6610 | likely = 1; | |
6611 | case M_BLE: | |
6612 | if (treg == 0) | |
df58fc94 RS |
6613 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6614 | else if (sreg == 0) | |
6615 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6616 | else | |
252b5132 | 6617 | { |
df58fc94 RS |
6618 | used_at = 1; |
6619 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6620 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6621 | &offset_expr, AT, ZERO); | |
252b5132 | 6622 | } |
252b5132 RH |
6623 | break; |
6624 | ||
6625 | case M_BLEL_I: | |
6626 | likely = 1; | |
6627 | case M_BLE_I: | |
6628 | maxnum = 0x7fffffff; | |
ca4e0257 | 6629 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6630 | { |
6631 | maxnum <<= 16; | |
6632 | maxnum |= 0xffff; | |
6633 | maxnum <<= 16; | |
6634 | maxnum |= 0xffff; | |
6635 | } | |
6636 | if (imm_expr.X_op == O_constant | |
6637 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6638 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6639 | goto do_true; |
6640 | if (imm_expr.X_op != O_constant) | |
6641 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6642 | ++imm_expr.X_add_number; |
252b5132 RH |
6643 | /* FALLTHROUGH */ |
6644 | case M_BLT_I: | |
6645 | case M_BLTL_I: | |
6646 | if (mask == M_BLTL_I) | |
6647 | likely = 1; | |
6648 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6649 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6650 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6651 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6652 | else | |
252b5132 | 6653 | { |
df58fc94 RS |
6654 | used_at = 1; |
6655 | set_at (sreg, 0); | |
6656 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6657 | &offset_expr, AT, ZERO); | |
252b5132 | 6658 | } |
252b5132 RH |
6659 | break; |
6660 | ||
6661 | case M_BLEUL: | |
6662 | likely = 1; | |
6663 | case M_BLEU: | |
6664 | if (treg == 0) | |
df58fc94 RS |
6665 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6666 | &offset_expr, sreg, ZERO); | |
6667 | else if (sreg == 0) | |
6668 | goto do_true; | |
6669 | else | |
252b5132 | 6670 | { |
df58fc94 RS |
6671 | used_at = 1; |
6672 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6673 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6674 | &offset_expr, AT, ZERO); | |
252b5132 | 6675 | } |
252b5132 RH |
6676 | break; |
6677 | ||
6678 | case M_BLEUL_I: | |
6679 | likely = 1; | |
6680 | case M_BLEU_I: | |
6681 | if (sreg == 0 | |
ca4e0257 | 6682 | || (HAVE_32BIT_GPRS |
252b5132 | 6683 | && imm_expr.X_op == O_constant |
f01dc953 | 6684 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6685 | goto do_true; |
6686 | if (imm_expr.X_op != O_constant) | |
6687 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6688 | ++imm_expr.X_add_number; |
252b5132 RH |
6689 | /* FALLTHROUGH */ |
6690 | case M_BLTU_I: | |
6691 | case M_BLTUL_I: | |
6692 | if (mask == M_BLTUL_I) | |
6693 | likely = 1; | |
6694 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6695 | goto do_false; | |
df58fc94 RS |
6696 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6697 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6698 | &offset_expr, sreg, ZERO); | |
6699 | else | |
252b5132 | 6700 | { |
df58fc94 RS |
6701 | used_at = 1; |
6702 | set_at (sreg, 1); | |
6703 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6704 | &offset_expr, AT, ZERO); | |
252b5132 | 6705 | } |
252b5132 RH |
6706 | break; |
6707 | ||
6708 | case M_BLTL: | |
6709 | likely = 1; | |
6710 | case M_BLT: | |
6711 | if (treg == 0) | |
df58fc94 RS |
6712 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6713 | else if (sreg == 0) | |
6714 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6715 | else | |
252b5132 | 6716 | { |
df58fc94 RS |
6717 | used_at = 1; |
6718 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6719 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6720 | &offset_expr, AT, ZERO); | |
252b5132 | 6721 | } |
252b5132 RH |
6722 | break; |
6723 | ||
6724 | case M_BLTUL: | |
6725 | likely = 1; | |
6726 | case M_BLTU: | |
6727 | if (treg == 0) | |
6728 | goto do_false; | |
df58fc94 RS |
6729 | else if (sreg == 0) |
6730 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6731 | &offset_expr, ZERO, treg); | |
6732 | else | |
252b5132 | 6733 | { |
df58fc94 RS |
6734 | used_at = 1; |
6735 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6736 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6737 | &offset_expr, AT, ZERO); | |
252b5132 | 6738 | } |
252b5132 RH |
6739 | break; |
6740 | ||
5f74bc13 CD |
6741 | case M_DEXT: |
6742 | { | |
d5818fca MR |
6743 | /* Use unsigned arithmetic. */ |
6744 | addressT pos; | |
6745 | addressT size; | |
5f74bc13 | 6746 | |
90ecf173 | 6747 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6748 | { |
6749 | as_bad (_("Unsupported large constant")); | |
6750 | pos = size = 1; | |
6751 | } | |
6752 | else | |
6753 | { | |
d5818fca MR |
6754 | pos = imm_expr.X_add_number; |
6755 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6756 | } |
6757 | ||
6758 | if (pos > 63) | |
6759 | { | |
d5818fca | 6760 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6761 | pos = 1; |
6762 | } | |
90ecf173 | 6763 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6764 | { |
6765 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6766 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6767 | size = 1; |
6768 | } | |
6769 | ||
6770 | if (size <= 32 && pos < 32) | |
6771 | { | |
6772 | s = "dext"; | |
6773 | fmt = "t,r,+A,+C"; | |
6774 | } | |
6775 | else if (size <= 32) | |
6776 | { | |
6777 | s = "dextu"; | |
6778 | fmt = "t,r,+E,+H"; | |
6779 | } | |
6780 | else | |
6781 | { | |
6782 | s = "dextm"; | |
6783 | fmt = "t,r,+A,+G"; | |
6784 | } | |
d5818fca MR |
6785 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6786 | (int) (size - 1)); | |
5f74bc13 | 6787 | } |
8fc2e39e | 6788 | break; |
5f74bc13 CD |
6789 | |
6790 | case M_DINS: | |
6791 | { | |
d5818fca MR |
6792 | /* Use unsigned arithmetic. */ |
6793 | addressT pos; | |
6794 | addressT size; | |
5f74bc13 | 6795 | |
90ecf173 | 6796 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6797 | { |
6798 | as_bad (_("Unsupported large constant")); | |
6799 | pos = size = 1; | |
6800 | } | |
6801 | else | |
6802 | { | |
d5818fca MR |
6803 | pos = imm_expr.X_add_number; |
6804 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6805 | } |
6806 | ||
6807 | if (pos > 63) | |
6808 | { | |
d5818fca | 6809 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6810 | pos = 1; |
6811 | } | |
90ecf173 | 6812 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6813 | { |
6814 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6815 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6816 | size = 1; |
6817 | } | |
6818 | ||
6819 | if (pos < 32 && (pos + size - 1) < 32) | |
6820 | { | |
6821 | s = "dins"; | |
6822 | fmt = "t,r,+A,+B"; | |
6823 | } | |
6824 | else if (pos >= 32) | |
6825 | { | |
6826 | s = "dinsu"; | |
6827 | fmt = "t,r,+E,+F"; | |
6828 | } | |
6829 | else | |
6830 | { | |
6831 | s = "dinsm"; | |
6832 | fmt = "t,r,+A,+F"; | |
6833 | } | |
750bdd57 AS |
6834 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6835 | (int) (pos + size - 1)); | |
5f74bc13 | 6836 | } |
8fc2e39e | 6837 | break; |
5f74bc13 | 6838 | |
252b5132 RH |
6839 | case M_DDIV_3: |
6840 | dbl = 1; | |
6841 | case M_DIV_3: | |
6842 | s = "mflo"; | |
6843 | goto do_div3; | |
6844 | case M_DREM_3: | |
6845 | dbl = 1; | |
6846 | case M_REM_3: | |
6847 | s = "mfhi"; | |
6848 | do_div3: | |
6849 | if (treg == 0) | |
6850 | { | |
6851 | as_warn (_("Divide by zero.")); | |
6852 | if (mips_trap) | |
df58fc94 | 6853 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6854 | else |
df58fc94 | 6855 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6856 | break; |
252b5132 RH |
6857 | } |
6858 | ||
7d10b47d | 6859 | start_noreorder (); |
252b5132 RH |
6860 | if (mips_trap) |
6861 | { | |
df58fc94 | 6862 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6863 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6864 | } |
6865 | else | |
6866 | { | |
df58fc94 RS |
6867 | if (mips_opts.micromips) |
6868 | micromips_label_expr (&label_expr); | |
6869 | else | |
6870 | label_expr.X_add_number = 8; | |
6871 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6872 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6873 | macro_build (NULL, "break", BRK_FMT, 7); |
6874 | if (mips_opts.micromips) | |
6875 | micromips_add_label (); | |
252b5132 RH |
6876 | } |
6877 | expr1.X_add_number = -1; | |
8fc2e39e | 6878 | used_at = 1; |
f6a22291 | 6879 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6880 | if (mips_opts.micromips) |
6881 | micromips_label_expr (&label_expr); | |
6882 | else | |
6883 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6884 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6885 | if (dbl) |
6886 | { | |
6887 | expr1.X_add_number = 1; | |
f6a22291 | 6888 | load_register (AT, &expr1, dbl); |
df58fc94 | 6889 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6890 | } |
6891 | else | |
6892 | { | |
6893 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6894 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6895 | } |
6896 | if (mips_trap) | |
6897 | { | |
df58fc94 | 6898 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6899 | /* We want to close the noreorder block as soon as possible, so |
6900 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6901 | end_noreorder (); |
252b5132 RH |
6902 | } |
6903 | else | |
6904 | { | |
df58fc94 RS |
6905 | if (mips_opts.micromips) |
6906 | micromips_label_expr (&label_expr); | |
6907 | else | |
6908 | label_expr.X_add_number = 8; | |
6909 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6910 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6911 | |
6912 | /* We want to close the noreorder block as soon as possible, so | |
6913 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6914 | end_noreorder (); |
252b5132 | 6915 | |
df58fc94 | 6916 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6917 | } |
df58fc94 RS |
6918 | if (mips_opts.micromips) |
6919 | micromips_add_label (); | |
6920 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6921 | break; |
6922 | ||
6923 | case M_DIV_3I: | |
6924 | s = "div"; | |
6925 | s2 = "mflo"; | |
6926 | goto do_divi; | |
6927 | case M_DIVU_3I: | |
6928 | s = "divu"; | |
6929 | s2 = "mflo"; | |
6930 | goto do_divi; | |
6931 | case M_REM_3I: | |
6932 | s = "div"; | |
6933 | s2 = "mfhi"; | |
6934 | goto do_divi; | |
6935 | case M_REMU_3I: | |
6936 | s = "divu"; | |
6937 | s2 = "mfhi"; | |
6938 | goto do_divi; | |
6939 | case M_DDIV_3I: | |
6940 | dbl = 1; | |
6941 | s = "ddiv"; | |
6942 | s2 = "mflo"; | |
6943 | goto do_divi; | |
6944 | case M_DDIVU_3I: | |
6945 | dbl = 1; | |
6946 | s = "ddivu"; | |
6947 | s2 = "mflo"; | |
6948 | goto do_divi; | |
6949 | case M_DREM_3I: | |
6950 | dbl = 1; | |
6951 | s = "ddiv"; | |
6952 | s2 = "mfhi"; | |
6953 | goto do_divi; | |
6954 | case M_DREMU_3I: | |
6955 | dbl = 1; | |
6956 | s = "ddivu"; | |
6957 | s2 = "mfhi"; | |
6958 | do_divi: | |
6959 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6960 | { | |
6961 | as_warn (_("Divide by zero.")); | |
6962 | if (mips_trap) | |
df58fc94 | 6963 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6964 | else |
df58fc94 | 6965 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6966 | break; |
252b5132 RH |
6967 | } |
6968 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6969 | { | |
6970 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 6971 | move_register (dreg, sreg); |
252b5132 | 6972 | else |
c80c840e | 6973 | move_register (dreg, ZERO); |
8fc2e39e | 6974 | break; |
252b5132 RH |
6975 | } |
6976 | if (imm_expr.X_op == O_constant | |
6977 | && imm_expr.X_add_number == -1 | |
6978 | && s[strlen (s) - 1] != 'u') | |
6979 | { | |
6980 | if (strcmp (s2, "mflo") == 0) | |
6981 | { | |
67c0d1eb | 6982 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
6983 | } |
6984 | else | |
c80c840e | 6985 | move_register (dreg, ZERO); |
8fc2e39e | 6986 | break; |
252b5132 RH |
6987 | } |
6988 | ||
8fc2e39e | 6989 | used_at = 1; |
67c0d1eb RS |
6990 | load_register (AT, &imm_expr, dbl); |
6991 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 6992 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
6993 | break; |
6994 | ||
6995 | case M_DIVU_3: | |
6996 | s = "divu"; | |
6997 | s2 = "mflo"; | |
6998 | goto do_divu3; | |
6999 | case M_REMU_3: | |
7000 | s = "divu"; | |
7001 | s2 = "mfhi"; | |
7002 | goto do_divu3; | |
7003 | case M_DDIVU_3: | |
7004 | s = "ddivu"; | |
7005 | s2 = "mflo"; | |
7006 | goto do_divu3; | |
7007 | case M_DREMU_3: | |
7008 | s = "ddivu"; | |
7009 | s2 = "mfhi"; | |
7010 | do_divu3: | |
7d10b47d | 7011 | start_noreorder (); |
252b5132 RH |
7012 | if (mips_trap) |
7013 | { | |
df58fc94 | 7014 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7015 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7016 | /* We want to close the noreorder block as soon as possible, so |
7017 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7018 | end_noreorder (); |
252b5132 RH |
7019 | } |
7020 | else | |
7021 | { | |
df58fc94 RS |
7022 | if (mips_opts.micromips) |
7023 | micromips_label_expr (&label_expr); | |
7024 | else | |
7025 | label_expr.X_add_number = 8; | |
7026 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7027 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7028 | |
7029 | /* We want to close the noreorder block as soon as possible, so | |
7030 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7031 | end_noreorder (); |
df58fc94 RS |
7032 | macro_build (NULL, "break", BRK_FMT, 7); |
7033 | if (mips_opts.micromips) | |
7034 | micromips_add_label (); | |
252b5132 | 7035 | } |
df58fc94 | 7036 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7037 | break; |
252b5132 | 7038 | |
1abe91b1 MR |
7039 | case M_DLCA_AB: |
7040 | dbl = 1; | |
7041 | case M_LCA_AB: | |
7042 | call = 1; | |
7043 | goto do_la; | |
252b5132 RH |
7044 | case M_DLA_AB: |
7045 | dbl = 1; | |
7046 | case M_LA_AB: | |
1abe91b1 | 7047 | do_la: |
252b5132 RH |
7048 | /* Load the address of a symbol into a register. If breg is not |
7049 | zero, we then add a base register to it. */ | |
7050 | ||
3bec30a8 TS |
7051 | if (dbl && HAVE_32BIT_GPRS) |
7052 | as_warn (_("dla used to load 32-bit register")); | |
7053 | ||
90ecf173 | 7054 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7055 | as_warn (_("la used to load 64-bit address")); |
7056 | ||
0c11417f MR |
7057 | if (offset_expr.X_op == O_constant |
7058 | && offset_expr.X_add_number >= -0x8000 | |
7059 | && offset_expr.X_add_number < 0x8000) | |
7060 | { | |
aed1a261 | 7061 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7062 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7063 | break; |
0c11417f MR |
7064 | } |
7065 | ||
741fe287 | 7066 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7067 | { |
7068 | tempreg = AT; | |
7069 | used_at = 1; | |
7070 | } | |
7071 | else | |
7072 | { | |
7073 | tempreg = treg; | |
afdbd6d0 CD |
7074 | } |
7075 | ||
252b5132 RH |
7076 | if (offset_expr.X_op != O_symbol |
7077 | && offset_expr.X_op != O_constant) | |
7078 | { | |
f71d0d44 | 7079 | as_bad (_("Expression too complex")); |
252b5132 RH |
7080 | offset_expr.X_op = O_constant; |
7081 | } | |
7082 | ||
252b5132 | 7083 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7084 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7085 | else if (mips_pic == NO_PIC) |
7086 | { | |
d6bc6245 | 7087 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7088 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7089 | Otherwise we want |
7090 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7091 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7092 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7093 | so we may as well always use the latter form. |
76b3015f | 7094 | |
6caf9ef4 TS |
7095 | With 64bit address space and a usable $at we want |
7096 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7097 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7098 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7099 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7100 | dsll32 $tempreg,0 | |
7101 | daddu $tempreg,$tempreg,$at | |
7102 | ||
7103 | If $at is already in use, we use a path which is suboptimal | |
7104 | on superscalar processors. | |
7105 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7106 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7107 | dsll $tempreg,16 | |
7108 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7109 | dsll $tempreg,16 | |
7110 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7111 | ||
7112 | For GP relative symbols in 64bit address space we can use | |
7113 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7114 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7115 | { |
6caf9ef4 TS |
7116 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7117 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7118 | { | |
7119 | relax_start (offset_expr.X_add_symbol); | |
7120 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7121 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7122 | relax_switch (); | |
7123 | } | |
d6bc6245 | 7124 | |
741fe287 | 7125 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7126 | { |
df58fc94 | 7127 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7128 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7129 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7130 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7131 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7132 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7133 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7134 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7135 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7136 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7137 | used_at = 1; |
7138 | } | |
7139 | else | |
7140 | { | |
df58fc94 | 7141 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7142 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7143 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7144 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7145 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7146 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7147 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7148 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7149 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7150 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7151 | } |
6caf9ef4 TS |
7152 | |
7153 | if (mips_relax.sequence) | |
7154 | relax_end (); | |
98d3f06f KH |
7155 | } |
7156 | else | |
7157 | { | |
7158 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7159 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7160 | { |
4d7206a2 | 7161 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7162 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7163 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7164 | relax_switch (); |
98d3f06f | 7165 | } |
6943caf0 | 7166 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7167 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7168 | macro_build_lui (&offset_expr, tempreg); |
7169 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7170 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7171 | if (mips_relax.sequence) |
7172 | relax_end (); | |
98d3f06f | 7173 | } |
252b5132 | 7174 | } |
0a44bf69 | 7175 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7176 | { |
9117d219 NC |
7177 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7178 | ||
252b5132 RH |
7179 | /* If this is a reference to an external symbol, and there |
7180 | is no constant, we want | |
7181 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7182 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7183 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7184 | For a local symbol, we want |
7185 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7186 | nop | |
7187 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7188 | ||
7189 | If we have a small constant, and this is a reference to | |
7190 | an external symbol, we want | |
7191 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7192 | nop | |
7193 | addiu $tempreg,$tempreg,<constant> | |
7194 | For a local symbol, we want the same instruction | |
7195 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7196 | addiu instruction. | |
7197 | ||
7198 | If we have a large constant, and this is a reference to | |
7199 | an external symbol, we want | |
7200 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7201 | lui $at,<hiconstant> | |
7202 | addiu $at,$at,<loconstant> | |
7203 | addu $tempreg,$tempreg,$at | |
7204 | For a local symbol, we want the same instruction | |
7205 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7206 | addiu instruction. |
ed6fb7bd SC |
7207 | */ |
7208 | ||
4d7206a2 | 7209 | if (offset_expr.X_add_number == 0) |
252b5132 | 7210 | { |
0a44bf69 RS |
7211 | if (mips_pic == SVR4_PIC |
7212 | && breg == 0 | |
7213 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7214 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7215 | ||
7216 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7217 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7218 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7219 | if (breg != 0) |
252b5132 RH |
7220 | { |
7221 | /* We're going to put in an addu instruction using | |
7222 | tempreg, so we may as well insert the nop right | |
7223 | now. */ | |
269137b2 | 7224 | load_delay_nop (); |
252b5132 | 7225 | } |
4d7206a2 | 7226 | relax_switch (); |
67c0d1eb RS |
7227 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7228 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7229 | load_delay_nop (); |
67c0d1eb RS |
7230 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7231 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7232 | relax_end (); |
252b5132 RH |
7233 | /* FIXME: If breg == 0, and the next instruction uses |
7234 | $tempreg, then if this variant case is used an extra | |
7235 | nop will be generated. */ | |
7236 | } | |
4d7206a2 RS |
7237 | else if (offset_expr.X_add_number >= -0x8000 |
7238 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7239 | { |
67c0d1eb | 7240 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7241 | load_delay_nop (); |
67c0d1eb | 7242 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7243 | } |
7244 | else | |
7245 | { | |
4d7206a2 RS |
7246 | expr1.X_add_number = offset_expr.X_add_number; |
7247 | offset_expr.X_add_number = | |
7248 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 7249 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7250 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7251 | /* If we are going to add in a base register, and the |
7252 | target register and the base register are the same, | |
7253 | then we are using AT as a temporary register. Since | |
7254 | we want to load the constant into AT, we add our | |
7255 | current AT (from the global offset table) and the | |
7256 | register into the register now, and pretend we were | |
7257 | not using a base register. */ | |
67c0d1eb | 7258 | if (breg == treg) |
252b5132 | 7259 | { |
269137b2 | 7260 | load_delay_nop (); |
67c0d1eb | 7261 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7262 | treg, AT, breg); |
252b5132 RH |
7263 | breg = 0; |
7264 | tempreg = treg; | |
252b5132 | 7265 | } |
f6a22291 | 7266 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7267 | used_at = 1; |
7268 | } | |
7269 | } | |
0a44bf69 | 7270 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7271 | { |
67c0d1eb | 7272 | int add_breg_early = 0; |
f5040a92 AO |
7273 | |
7274 | /* If this is a reference to an external, and there is no | |
7275 | constant, or local symbol (*), with or without a | |
7276 | constant, we want | |
7277 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7278 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7279 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7280 | ||
7281 | If we have a small constant, and this is a reference to | |
7282 | an external symbol, we want | |
7283 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7284 | addiu $tempreg,$tempreg,<constant> | |
7285 | ||
7286 | If we have a large constant, and this is a reference to | |
7287 | an external symbol, we want | |
7288 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7289 | lui $at,<hiconstant> | |
7290 | addiu $at,$at,<loconstant> | |
7291 | addu $tempreg,$tempreg,$at | |
7292 | ||
7293 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7294 | local symbols, even though it introduces an additional | |
7295 | instruction. */ | |
7296 | ||
f5040a92 AO |
7297 | if (offset_expr.X_add_number) |
7298 | { | |
4d7206a2 | 7299 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7300 | offset_expr.X_add_number = 0; |
7301 | ||
4d7206a2 | 7302 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7304 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7305 | |
7306 | if (expr1.X_add_number >= -0x8000 | |
7307 | && expr1.X_add_number < 0x8000) | |
7308 | { | |
67c0d1eb RS |
7309 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7310 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7311 | } |
ecd13cd3 | 7312 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7313 | { |
f5040a92 AO |
7314 | /* If we are going to add in a base register, and the |
7315 | target register and the base register are the same, | |
7316 | then we are using AT as a temporary register. Since | |
7317 | we want to load the constant into AT, we add our | |
7318 | current AT (from the global offset table) and the | |
7319 | register into the register now, and pretend we were | |
7320 | not using a base register. */ | |
7321 | if (breg != treg) | |
7322 | dreg = tempreg; | |
7323 | else | |
7324 | { | |
9c2799c2 | 7325 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7326 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7327 | treg, AT, breg); | |
f5040a92 | 7328 | dreg = treg; |
67c0d1eb | 7329 | add_breg_early = 1; |
f5040a92 AO |
7330 | } |
7331 | ||
f6a22291 | 7332 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7334 | dreg, dreg, AT); |
f5040a92 | 7335 | |
f5040a92 AO |
7336 | used_at = 1; |
7337 | } | |
7338 | else | |
7339 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7340 | ||
4d7206a2 | 7341 | relax_switch (); |
f5040a92 AO |
7342 | offset_expr.X_add_number = expr1.X_add_number; |
7343 | ||
67c0d1eb RS |
7344 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7345 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7346 | if (add_breg_early) | |
f5040a92 | 7347 | { |
67c0d1eb | 7348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7349 | treg, tempreg, breg); |
f5040a92 AO |
7350 | breg = 0; |
7351 | tempreg = treg; | |
7352 | } | |
4d7206a2 | 7353 | relax_end (); |
f5040a92 | 7354 | } |
4d7206a2 | 7355 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7356 | { |
4d7206a2 | 7357 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7358 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7359 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7360 | relax_switch (); |
67c0d1eb RS |
7361 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7362 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7363 | relax_end (); |
f5040a92 | 7364 | } |
4d7206a2 | 7365 | else |
f5040a92 | 7366 | { |
67c0d1eb RS |
7367 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7368 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7369 | } |
7370 | } | |
0a44bf69 | 7371 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7372 | { |
67c0d1eb | 7373 | int gpdelay; |
9117d219 NC |
7374 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7375 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7376 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7377 | |
7378 | /* This is the large GOT case. If this is a reference to an | |
7379 | external symbol, and there is no constant, we want | |
7380 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7381 | addu $tempreg,$tempreg,$gp | |
7382 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7383 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7384 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7385 | addu $tempreg,$tempreg,$gp | |
7386 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7387 | For a local symbol, we want |
7388 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7389 | nop | |
7390 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7391 | ||
7392 | If we have a small constant, and this is a reference to | |
7393 | an external symbol, we want | |
7394 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7395 | addu $tempreg,$tempreg,$gp | |
7396 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7397 | nop | |
7398 | addiu $tempreg,$tempreg,<constant> | |
7399 | For a local symbol, we want | |
7400 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7401 | nop | |
7402 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7403 | ||
7404 | If we have a large constant, and this is a reference to | |
7405 | an external symbol, we want | |
7406 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7407 | addu $tempreg,$tempreg,$gp | |
7408 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7409 | lui $at,<hiconstant> | |
7410 | addiu $at,$at,<loconstant> | |
7411 | addu $tempreg,$tempreg,$at | |
7412 | For a local symbol, we want | |
7413 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7414 | lui $at,<hiconstant> | |
7415 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7416 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7417 | */ |
438c16b8 | 7418 | |
252b5132 RH |
7419 | expr1.X_add_number = offset_expr.X_add_number; |
7420 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7421 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7422 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7423 | if (expr1.X_add_number == 0 && breg == 0 |
7424 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7425 | { |
7426 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7427 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7428 | } | |
df58fc94 | 7429 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7430 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7431 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7432 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7433 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7434 | if (expr1.X_add_number == 0) |
7435 | { | |
67c0d1eb | 7436 | if (breg != 0) |
252b5132 RH |
7437 | { |
7438 | /* We're going to put in an addu instruction using | |
7439 | tempreg, so we may as well insert the nop right | |
7440 | now. */ | |
269137b2 | 7441 | load_delay_nop (); |
252b5132 | 7442 | } |
252b5132 RH |
7443 | } |
7444 | else if (expr1.X_add_number >= -0x8000 | |
7445 | && expr1.X_add_number < 0x8000) | |
7446 | { | |
269137b2 | 7447 | load_delay_nop (); |
67c0d1eb | 7448 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7449 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7450 | } |
7451 | else | |
7452 | { | |
252b5132 RH |
7453 | /* If we are going to add in a base register, and the |
7454 | target register and the base register are the same, | |
7455 | then we are using AT as a temporary register. Since | |
7456 | we want to load the constant into AT, we add our | |
7457 | current AT (from the global offset table) and the | |
7458 | register into the register now, and pretend we were | |
7459 | not using a base register. */ | |
7460 | if (breg != treg) | |
67c0d1eb | 7461 | dreg = tempreg; |
252b5132 RH |
7462 | else |
7463 | { | |
9c2799c2 | 7464 | gas_assert (tempreg == AT); |
269137b2 | 7465 | load_delay_nop (); |
67c0d1eb | 7466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7467 | treg, AT, breg); |
252b5132 | 7468 | dreg = treg; |
252b5132 RH |
7469 | } |
7470 | ||
f6a22291 | 7471 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7472 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7473 | |
252b5132 RH |
7474 | used_at = 1; |
7475 | } | |
4d7206a2 RS |
7476 | offset_expr.X_add_number = |
7477 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
7478 | relax_switch (); | |
252b5132 | 7479 | |
67c0d1eb | 7480 | if (gpdelay) |
252b5132 RH |
7481 | { |
7482 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7483 | the first instruction on the main stream does not. */ |
67c0d1eb | 7484 | macro_build (NULL, "nop", ""); |
252b5132 | 7485 | } |
ed6fb7bd | 7486 | |
67c0d1eb RS |
7487 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7488 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7489 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7490 | && expr1.X_add_number < 0x8000) |
7491 | { | |
269137b2 | 7492 | load_delay_nop (); |
67c0d1eb RS |
7493 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7494 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7495 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7496 | register, the external symbol case ended with a load, |
7497 | so if the symbol turns out to not be external, and | |
7498 | the next instruction uses tempreg, an unnecessary nop | |
7499 | will be inserted. */ | |
252b5132 RH |
7500 | } |
7501 | else | |
7502 | { | |
7503 | if (breg == treg) | |
7504 | { | |
7505 | /* We must add in the base register now, as in the | |
f5040a92 | 7506 | external symbol case. */ |
9c2799c2 | 7507 | gas_assert (tempreg == AT); |
269137b2 | 7508 | load_delay_nop (); |
67c0d1eb | 7509 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7510 | treg, AT, breg); |
252b5132 RH |
7511 | tempreg = treg; |
7512 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7513 | it in in both cases. */ |
252b5132 RH |
7514 | breg = 0; |
7515 | } | |
7516 | ||
67c0d1eb RS |
7517 | macro_build_lui (&expr1, AT); |
7518 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7519 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7521 | tempreg, tempreg, AT); |
8fc2e39e | 7522 | used_at = 1; |
252b5132 | 7523 | } |
4d7206a2 | 7524 | relax_end (); |
252b5132 | 7525 | } |
0a44bf69 | 7526 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7527 | { |
f5040a92 AO |
7528 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7529 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7530 | int add_breg_early = 0; |
f5040a92 AO |
7531 | |
7532 | /* This is the large GOT case. If this is a reference to an | |
7533 | external symbol, and there is no constant, we want | |
7534 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7535 | add $tempreg,$tempreg,$gp | |
7536 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7537 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7538 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7539 | add $tempreg,$tempreg,$gp | |
7540 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7541 | ||
7542 | If we have a small constant, and this is a reference to | |
7543 | an external symbol, we want | |
7544 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7545 | add $tempreg,$tempreg,$gp | |
7546 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7547 | addi $tempreg,$tempreg,<constant> | |
7548 | ||
7549 | If we have a large constant, and this is a reference to | |
7550 | an external symbol, we want | |
7551 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7552 | addu $tempreg,$tempreg,$gp | |
7553 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7554 | lui $at,<hiconstant> | |
7555 | addi $at,$at,<loconstant> | |
7556 | add $tempreg,$tempreg,$at | |
7557 | ||
7558 | If we have NewABI, and we know it's a local symbol, we want | |
7559 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7560 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7561 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7562 | ||
4d7206a2 | 7563 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7564 | |
4d7206a2 | 7565 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7566 | offset_expr.X_add_number = 0; |
7567 | ||
1abe91b1 MR |
7568 | if (expr1.X_add_number == 0 && breg == 0 |
7569 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7570 | { |
7571 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7572 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7573 | } | |
df58fc94 | 7574 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7576 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7577 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7578 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7579 | |
7580 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7581 | ; |
f5040a92 AO |
7582 | else if (expr1.X_add_number >= -0x8000 |
7583 | && expr1.X_add_number < 0x8000) | |
7584 | { | |
67c0d1eb | 7585 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7586 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7587 | } |
ecd13cd3 | 7588 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7589 | { |
f5040a92 AO |
7590 | /* If we are going to add in a base register, and the |
7591 | target register and the base register are the same, | |
7592 | then we are using AT as a temporary register. Since | |
7593 | we want to load the constant into AT, we add our | |
7594 | current AT (from the global offset table) and the | |
7595 | register into the register now, and pretend we were | |
7596 | not using a base register. */ | |
7597 | if (breg != treg) | |
7598 | dreg = tempreg; | |
7599 | else | |
7600 | { | |
9c2799c2 | 7601 | gas_assert (tempreg == AT); |
67c0d1eb | 7602 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7603 | treg, AT, breg); |
f5040a92 | 7604 | dreg = treg; |
67c0d1eb | 7605 | add_breg_early = 1; |
f5040a92 AO |
7606 | } |
7607 | ||
f6a22291 | 7608 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7609 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7610 | |
f5040a92 AO |
7611 | used_at = 1; |
7612 | } | |
7613 | else | |
7614 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7615 | ||
4d7206a2 | 7616 | relax_switch (); |
f5040a92 | 7617 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7618 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7619 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7620 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7621 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7622 | if (add_breg_early) | |
f5040a92 | 7623 | { |
67c0d1eb | 7624 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7625 | treg, tempreg, breg); |
f5040a92 AO |
7626 | breg = 0; |
7627 | tempreg = treg; | |
7628 | } | |
4d7206a2 | 7629 | relax_end (); |
f5040a92 | 7630 | } |
252b5132 RH |
7631 | else |
7632 | abort (); | |
7633 | ||
7634 | if (breg != 0) | |
aed1a261 | 7635 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7636 | break; |
7637 | ||
52b6b6b9 | 7638 | case M_MSGSND: |
df58fc94 | 7639 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7640 | { |
7641 | unsigned long temp = (treg << 16) | (0x01); | |
7642 | macro_build (NULL, "c2", "C", temp); | |
7643 | } | |
c7af4273 | 7644 | break; |
52b6b6b9 JM |
7645 | |
7646 | case M_MSGLD: | |
df58fc94 | 7647 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7648 | { |
7649 | unsigned long temp = (0x02); | |
7650 | macro_build (NULL, "c2", "C", temp); | |
7651 | } | |
c7af4273 | 7652 | break; |
52b6b6b9 JM |
7653 | |
7654 | case M_MSGLD_T: | |
df58fc94 | 7655 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7656 | { |
7657 | unsigned long temp = (treg << 16) | (0x02); | |
7658 | macro_build (NULL, "c2", "C", temp); | |
7659 | } | |
c7af4273 | 7660 | break; |
52b6b6b9 JM |
7661 | |
7662 | case M_MSGWAIT: | |
df58fc94 | 7663 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7664 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7665 | break; |
52b6b6b9 JM |
7666 | |
7667 | case M_MSGWAIT_T: | |
df58fc94 | 7668 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7669 | { |
7670 | unsigned long temp = (treg << 16) | 0x03; | |
7671 | macro_build (NULL, "c2", "C", temp); | |
7672 | } | |
c7af4273 | 7673 | break; |
52b6b6b9 | 7674 | |
252b5132 RH |
7675 | case M_J_A: |
7676 | /* The j instruction may not be used in PIC code, since it | |
7677 | requires an absolute address. We convert it to a b | |
7678 | instruction. */ | |
7679 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7680 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7681 | else |
67c0d1eb | 7682 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7683 | break; |
252b5132 RH |
7684 | |
7685 | /* The jal instructions must be handled as macros because when | |
7686 | generating PIC code they expand to multi-instruction | |
7687 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7688 | case M_JALS_1: |
7689 | dreg = RA; | |
7690 | /* Fall through. */ | |
7691 | case M_JALS_2: | |
7692 | gas_assert (mips_opts.micromips); | |
7693 | jals = 1; | |
7694 | goto jal; | |
252b5132 RH |
7695 | case M_JAL_1: |
7696 | dreg = RA; | |
7697 | /* Fall through. */ | |
7698 | case M_JAL_2: | |
df58fc94 | 7699 | jal: |
3e722fb5 | 7700 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7701 | { |
7702 | s = jals ? "jalrs" : "jalr"; | |
7703 | if (mips_opts.micromips && dreg == RA) | |
7704 | macro_build (NULL, s, "mj", sreg); | |
7705 | else | |
7706 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7707 | } | |
0a44bf69 | 7708 | else |
252b5132 | 7709 | { |
df58fc94 RS |
7710 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7711 | && mips_cprestore_offset >= 0); | |
7712 | ||
252b5132 RH |
7713 | if (sreg != PIC_CALL_REG) |
7714 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7715 | |
df58fc94 RS |
7716 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7717 | ? "jalrs" : "jalr"); | |
7718 | if (mips_opts.micromips && dreg == RA) | |
7719 | macro_build (NULL, s, "mj", sreg); | |
7720 | else | |
7721 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7722 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7723 | { |
6478892d TS |
7724 | if (mips_cprestore_offset < 0) |
7725 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7726 | else | |
7727 | { | |
90ecf173 | 7728 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7729 | { |
7730 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7731 | /* Quiet this warning. */ | |
7732 | mips_frame_reg_valid = 1; | |
7733 | } | |
90ecf173 | 7734 | if (!mips_cprestore_valid) |
7a621144 DJ |
7735 | { |
7736 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7737 | /* Quiet this warning. */ | |
7738 | mips_cprestore_valid = 1; | |
7739 | } | |
d3fca0b5 MR |
7740 | if (mips_opts.noreorder) |
7741 | macro_build (NULL, "nop", ""); | |
6478892d | 7742 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7743 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7744 | mips_gp_register, |
256ab948 TS |
7745 | mips_frame_reg, |
7746 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7747 | } |
252b5132 RH |
7748 | } |
7749 | } | |
252b5132 | 7750 | |
8fc2e39e | 7751 | break; |
252b5132 | 7752 | |
df58fc94 RS |
7753 | case M_JALS_A: |
7754 | gas_assert (mips_opts.micromips); | |
7755 | jals = 1; | |
7756 | /* Fall through. */ | |
252b5132 RH |
7757 | case M_JAL_A: |
7758 | if (mips_pic == NO_PIC) | |
df58fc94 | 7759 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7760 | else if (mips_pic == SVR4_PIC) |
7761 | { | |
7762 | /* If this is a reference to an external symbol, and we are | |
7763 | using a small GOT, we want | |
7764 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7765 | nop | |
f9419b05 | 7766 | jalr $ra,$25 |
252b5132 RH |
7767 | nop |
7768 | lw $gp,cprestore($sp) | |
7769 | The cprestore value is set using the .cprestore | |
7770 | pseudo-op. If we are using a big GOT, we want | |
7771 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7772 | addu $25,$25,$gp | |
7773 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7774 | nop | |
f9419b05 | 7775 | jalr $ra,$25 |
252b5132 RH |
7776 | nop |
7777 | lw $gp,cprestore($sp) | |
7778 | If the symbol is not external, we want | |
7779 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7780 | nop | |
7781 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7782 | jalr $ra,$25 |
252b5132 | 7783 | nop |
438c16b8 | 7784 | lw $gp,cprestore($sp) |
f5040a92 AO |
7785 | |
7786 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7787 | sequences above, minus nops, unless the symbol is local, | |
7788 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7789 | GOT_DISP. */ | |
438c16b8 | 7790 | if (HAVE_NEWABI) |
252b5132 | 7791 | { |
90ecf173 | 7792 | if (!mips_big_got) |
f5040a92 | 7793 | { |
4d7206a2 | 7794 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7795 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7796 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7797 | mips_gp_register); |
4d7206a2 | 7798 | relax_switch (); |
67c0d1eb RS |
7799 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7800 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7801 | mips_gp_register); |
7802 | relax_end (); | |
f5040a92 AO |
7803 | } |
7804 | else | |
7805 | { | |
4d7206a2 | 7806 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7807 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7808 | BFD_RELOC_MIPS_CALL_HI16); |
7809 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7810 | PIC_CALL_REG, mips_gp_register); | |
7811 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7812 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7813 | PIC_CALL_REG); | |
4d7206a2 | 7814 | relax_switch (); |
67c0d1eb RS |
7815 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7816 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7817 | mips_gp_register); | |
7818 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7819 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7820 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7821 | relax_end (); |
f5040a92 | 7822 | } |
684022ea | 7823 | |
df58fc94 | 7824 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7825 | } |
7826 | else | |
7827 | { | |
4d7206a2 | 7828 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7829 | if (!mips_big_got) |
438c16b8 | 7830 | { |
67c0d1eb RS |
7831 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7832 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7833 | mips_gp_register); |
269137b2 | 7834 | load_delay_nop (); |
4d7206a2 | 7835 | relax_switch (); |
438c16b8 | 7836 | } |
252b5132 | 7837 | else |
252b5132 | 7838 | { |
67c0d1eb RS |
7839 | int gpdelay; |
7840 | ||
7841 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7842 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7843 | BFD_RELOC_MIPS_CALL_HI16); |
7844 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7845 | PIC_CALL_REG, mips_gp_register); | |
7846 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7847 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7848 | PIC_CALL_REG); | |
269137b2 | 7849 | load_delay_nop (); |
4d7206a2 | 7850 | relax_switch (); |
67c0d1eb RS |
7851 | if (gpdelay) |
7852 | macro_build (NULL, "nop", ""); | |
252b5132 | 7853 | } |
67c0d1eb RS |
7854 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7855 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7856 | mips_gp_register); |
269137b2 | 7857 | load_delay_nop (); |
67c0d1eb RS |
7858 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7859 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7860 | relax_end (); |
df58fc94 | 7861 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7862 | |
6478892d TS |
7863 | if (mips_cprestore_offset < 0) |
7864 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7865 | else | |
7866 | { | |
90ecf173 | 7867 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7868 | { |
7869 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7870 | /* Quiet this warning. */ | |
7871 | mips_frame_reg_valid = 1; | |
7872 | } | |
90ecf173 | 7873 | if (!mips_cprestore_valid) |
7a621144 DJ |
7874 | { |
7875 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7876 | /* Quiet this warning. */ | |
7877 | mips_cprestore_valid = 1; | |
7878 | } | |
6478892d | 7879 | if (mips_opts.noreorder) |
67c0d1eb | 7880 | macro_build (NULL, "nop", ""); |
6478892d | 7881 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7882 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7883 | mips_gp_register, |
256ab948 TS |
7884 | mips_frame_reg, |
7885 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7886 | } |
252b5132 RH |
7887 | } |
7888 | } | |
0a44bf69 RS |
7889 | else if (mips_pic == VXWORKS_PIC) |
7890 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7891 | else |
7892 | abort (); | |
7893 | ||
8fc2e39e | 7894 | break; |
252b5132 | 7895 | |
dec0624d MR |
7896 | case M_ACLR_AB: |
7897 | ab = 1; | |
7898 | case M_ACLR_OB: | |
7899 | s = "aclr"; | |
7900 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7901 | fmt = "\\,~(b)"; | |
7902 | off12 = 1; | |
7903 | goto ld_st; | |
7904 | case M_ASET_AB: | |
7905 | ab = 1; | |
7906 | case M_ASET_OB: | |
7907 | s = "aset"; | |
7908 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7909 | fmt = "\\,~(b)"; | |
7910 | off12 = 1; | |
7911 | goto ld_st; | |
252b5132 | 7912 | case M_LB_AB: |
df58fc94 | 7913 | ab = 1; |
252b5132 | 7914 | s = "lb"; |
df58fc94 | 7915 | fmt = "t,o(b)"; |
252b5132 RH |
7916 | goto ld; |
7917 | case M_LBU_AB: | |
df58fc94 | 7918 | ab = 1; |
252b5132 | 7919 | s = "lbu"; |
df58fc94 | 7920 | fmt = "t,o(b)"; |
252b5132 RH |
7921 | goto ld; |
7922 | case M_LH_AB: | |
df58fc94 | 7923 | ab = 1; |
252b5132 | 7924 | s = "lh"; |
df58fc94 | 7925 | fmt = "t,o(b)"; |
252b5132 RH |
7926 | goto ld; |
7927 | case M_LHU_AB: | |
df58fc94 | 7928 | ab = 1; |
252b5132 | 7929 | s = "lhu"; |
df58fc94 | 7930 | fmt = "t,o(b)"; |
252b5132 RH |
7931 | goto ld; |
7932 | case M_LW_AB: | |
df58fc94 | 7933 | ab = 1; |
252b5132 | 7934 | s = "lw"; |
df58fc94 | 7935 | fmt = "t,o(b)"; |
252b5132 RH |
7936 | goto ld; |
7937 | case M_LWC0_AB: | |
df58fc94 RS |
7938 | ab = 1; |
7939 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7940 | s = "lwc0"; |
df58fc94 | 7941 | fmt = "E,o(b)"; |
bdaaa2e1 | 7942 | /* Itbl support may require additional care here. */ |
252b5132 | 7943 | coproc = 1; |
df58fc94 | 7944 | goto ld_st; |
252b5132 | 7945 | case M_LWC1_AB: |
df58fc94 | 7946 | ab = 1; |
252b5132 | 7947 | s = "lwc1"; |
df58fc94 | 7948 | fmt = "T,o(b)"; |
bdaaa2e1 | 7949 | /* Itbl support may require additional care here. */ |
252b5132 | 7950 | coproc = 1; |
df58fc94 | 7951 | goto ld_st; |
252b5132 | 7952 | case M_LWC2_AB: |
df58fc94 RS |
7953 | ab = 1; |
7954 | case M_LWC2_OB: | |
252b5132 | 7955 | s = "lwc2"; |
df58fc94 RS |
7956 | fmt = COP12_FMT; |
7957 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7958 | /* Itbl support may require additional care here. */ |
252b5132 | 7959 | coproc = 1; |
df58fc94 | 7960 | goto ld_st; |
252b5132 | 7961 | case M_LWC3_AB: |
df58fc94 RS |
7962 | ab = 1; |
7963 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7964 | s = "lwc3"; |
df58fc94 | 7965 | fmt = "E,o(b)"; |
bdaaa2e1 | 7966 | /* Itbl support may require additional care here. */ |
252b5132 | 7967 | coproc = 1; |
df58fc94 | 7968 | goto ld_st; |
252b5132 | 7969 | case M_LWL_AB: |
df58fc94 RS |
7970 | ab = 1; |
7971 | case M_LWL_OB: | |
252b5132 | 7972 | s = "lwl"; |
df58fc94 RS |
7973 | fmt = MEM12_FMT; |
7974 | off12 = mips_opts.micromips; | |
7975 | goto ld_st; | |
252b5132 | 7976 | case M_LWR_AB: |
df58fc94 RS |
7977 | ab = 1; |
7978 | case M_LWR_OB: | |
252b5132 | 7979 | s = "lwr"; |
df58fc94 RS |
7980 | fmt = MEM12_FMT; |
7981 | off12 = mips_opts.micromips; | |
7982 | goto ld_st; | |
252b5132 | 7983 | case M_LDC1_AB: |
df58fc94 | 7984 | ab = 1; |
252b5132 | 7985 | s = "ldc1"; |
df58fc94 | 7986 | fmt = "T,o(b)"; |
bdaaa2e1 | 7987 | /* Itbl support may require additional care here. */ |
252b5132 | 7988 | coproc = 1; |
df58fc94 | 7989 | goto ld_st; |
252b5132 | 7990 | case M_LDC2_AB: |
df58fc94 RS |
7991 | ab = 1; |
7992 | case M_LDC2_OB: | |
252b5132 | 7993 | s = "ldc2"; |
df58fc94 RS |
7994 | fmt = COP12_FMT; |
7995 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7996 | /* Itbl support may require additional care here. */ |
252b5132 | 7997 | coproc = 1; |
df58fc94 | 7998 | goto ld_st; |
252b5132 | 7999 | case M_LDC3_AB: |
df58fc94 | 8000 | ab = 1; |
252b5132 | 8001 | s = "ldc3"; |
df58fc94 | 8002 | fmt = "E,o(b)"; |
bdaaa2e1 | 8003 | /* Itbl support may require additional care here. */ |
252b5132 | 8004 | coproc = 1; |
df58fc94 | 8005 | goto ld_st; |
252b5132 | 8006 | case M_LDL_AB: |
df58fc94 RS |
8007 | ab = 1; |
8008 | case M_LDL_OB: | |
252b5132 | 8009 | s = "ldl"; |
df58fc94 RS |
8010 | fmt = MEM12_FMT; |
8011 | off12 = mips_opts.micromips; | |
8012 | goto ld_st; | |
252b5132 | 8013 | case M_LDR_AB: |
df58fc94 RS |
8014 | ab = 1; |
8015 | case M_LDR_OB: | |
252b5132 | 8016 | s = "ldr"; |
df58fc94 RS |
8017 | fmt = MEM12_FMT; |
8018 | off12 = mips_opts.micromips; | |
8019 | goto ld_st; | |
252b5132 | 8020 | case M_LL_AB: |
df58fc94 RS |
8021 | ab = 1; |
8022 | case M_LL_OB: | |
252b5132 | 8023 | s = "ll"; |
df58fc94 RS |
8024 | fmt = MEM12_FMT; |
8025 | off12 = mips_opts.micromips; | |
252b5132 RH |
8026 | goto ld; |
8027 | case M_LLD_AB: | |
df58fc94 RS |
8028 | ab = 1; |
8029 | case M_LLD_OB: | |
252b5132 | 8030 | s = "lld"; |
df58fc94 RS |
8031 | fmt = MEM12_FMT; |
8032 | off12 = mips_opts.micromips; | |
252b5132 RH |
8033 | goto ld; |
8034 | case M_LWU_AB: | |
df58fc94 RS |
8035 | ab = 1; |
8036 | case M_LWU_OB: | |
252b5132 | 8037 | s = "lwu"; |
df58fc94 RS |
8038 | fmt = MEM12_FMT; |
8039 | off12 = mips_opts.micromips; | |
8040 | goto ld; | |
8041 | case M_LWP_AB: | |
8042 | ab = 1; | |
8043 | case M_LWP_OB: | |
8044 | gas_assert (mips_opts.micromips); | |
8045 | s = "lwp"; | |
8046 | fmt = "t,~(b)"; | |
8047 | off12 = 1; | |
8048 | lp = 1; | |
8049 | goto ld; | |
8050 | case M_LDP_AB: | |
8051 | ab = 1; | |
8052 | case M_LDP_OB: | |
8053 | gas_assert (mips_opts.micromips); | |
8054 | s = "ldp"; | |
8055 | fmt = "t,~(b)"; | |
8056 | off12 = 1; | |
8057 | lp = 1; | |
8058 | goto ld; | |
8059 | case M_LWM_AB: | |
8060 | ab = 1; | |
8061 | case M_LWM_OB: | |
8062 | gas_assert (mips_opts.micromips); | |
8063 | s = "lwm"; | |
8064 | fmt = "n,~(b)"; | |
8065 | off12 = 1; | |
8066 | goto ld_st; | |
8067 | case M_LDM_AB: | |
8068 | ab = 1; | |
8069 | case M_LDM_OB: | |
8070 | gas_assert (mips_opts.micromips); | |
8071 | s = "ldm"; | |
8072 | fmt = "n,~(b)"; | |
8073 | off12 = 1; | |
8074 | goto ld_st; | |
8075 | ||
252b5132 | 8076 | ld: |
df58fc94 RS |
8077 | if (breg == treg + lp) |
8078 | goto ld_st; | |
252b5132 | 8079 | else |
df58fc94 RS |
8080 | tempreg = treg + lp; |
8081 | goto ld_noat; | |
8082 | ||
252b5132 | 8083 | case M_SB_AB: |
df58fc94 | 8084 | ab = 1; |
252b5132 | 8085 | s = "sb"; |
df58fc94 RS |
8086 | fmt = "t,o(b)"; |
8087 | goto ld_st; | |
252b5132 | 8088 | case M_SH_AB: |
df58fc94 | 8089 | ab = 1; |
252b5132 | 8090 | s = "sh"; |
df58fc94 RS |
8091 | fmt = "t,o(b)"; |
8092 | goto ld_st; | |
252b5132 | 8093 | case M_SW_AB: |
df58fc94 | 8094 | ab = 1; |
252b5132 | 8095 | s = "sw"; |
df58fc94 RS |
8096 | fmt = "t,o(b)"; |
8097 | goto ld_st; | |
252b5132 | 8098 | case M_SWC0_AB: |
df58fc94 RS |
8099 | ab = 1; |
8100 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8101 | s = "swc0"; |
df58fc94 | 8102 | fmt = "E,o(b)"; |
bdaaa2e1 | 8103 | /* Itbl support may require additional care here. */ |
252b5132 | 8104 | coproc = 1; |
df58fc94 | 8105 | goto ld_st; |
252b5132 | 8106 | case M_SWC1_AB: |
df58fc94 | 8107 | ab = 1; |
252b5132 | 8108 | s = "swc1"; |
df58fc94 | 8109 | fmt = "T,o(b)"; |
bdaaa2e1 | 8110 | /* Itbl support may require additional care here. */ |
252b5132 | 8111 | coproc = 1; |
df58fc94 | 8112 | goto ld_st; |
252b5132 | 8113 | case M_SWC2_AB: |
df58fc94 RS |
8114 | ab = 1; |
8115 | case M_SWC2_OB: | |
252b5132 | 8116 | s = "swc2"; |
df58fc94 RS |
8117 | fmt = COP12_FMT; |
8118 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8119 | /* Itbl support may require additional care here. */ |
252b5132 | 8120 | coproc = 1; |
df58fc94 | 8121 | goto ld_st; |
252b5132 | 8122 | case M_SWC3_AB: |
df58fc94 RS |
8123 | ab = 1; |
8124 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8125 | s = "swc3"; |
df58fc94 | 8126 | fmt = "E,o(b)"; |
bdaaa2e1 | 8127 | /* Itbl support may require additional care here. */ |
252b5132 | 8128 | coproc = 1; |
df58fc94 | 8129 | goto ld_st; |
252b5132 | 8130 | case M_SWL_AB: |
df58fc94 RS |
8131 | ab = 1; |
8132 | case M_SWL_OB: | |
252b5132 | 8133 | s = "swl"; |
df58fc94 RS |
8134 | fmt = MEM12_FMT; |
8135 | off12 = mips_opts.micromips; | |
8136 | goto ld_st; | |
252b5132 | 8137 | case M_SWR_AB: |
df58fc94 RS |
8138 | ab = 1; |
8139 | case M_SWR_OB: | |
252b5132 | 8140 | s = "swr"; |
df58fc94 RS |
8141 | fmt = MEM12_FMT; |
8142 | off12 = mips_opts.micromips; | |
8143 | goto ld_st; | |
252b5132 | 8144 | case M_SC_AB: |
df58fc94 RS |
8145 | ab = 1; |
8146 | case M_SC_OB: | |
252b5132 | 8147 | s = "sc"; |
df58fc94 RS |
8148 | fmt = MEM12_FMT; |
8149 | off12 = mips_opts.micromips; | |
8150 | goto ld_st; | |
252b5132 | 8151 | case M_SCD_AB: |
df58fc94 RS |
8152 | ab = 1; |
8153 | case M_SCD_OB: | |
252b5132 | 8154 | s = "scd"; |
df58fc94 RS |
8155 | fmt = MEM12_FMT; |
8156 | off12 = mips_opts.micromips; | |
8157 | goto ld_st; | |
d43b4baf | 8158 | case M_CACHE_AB: |
df58fc94 RS |
8159 | ab = 1; |
8160 | case M_CACHE_OB: | |
d43b4baf | 8161 | s = "cache"; |
df58fc94 RS |
8162 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8163 | off12 = mips_opts.micromips; | |
8164 | goto ld_st; | |
3eebd5eb | 8165 | case M_PREF_AB: |
df58fc94 RS |
8166 | ab = 1; |
8167 | case M_PREF_OB: | |
3eebd5eb | 8168 | s = "pref"; |
df58fc94 RS |
8169 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8170 | off12 = mips_opts.micromips; | |
8171 | goto ld_st; | |
252b5132 | 8172 | case M_SDC1_AB: |
df58fc94 | 8173 | ab = 1; |
252b5132 | 8174 | s = "sdc1"; |
df58fc94 | 8175 | fmt = "T,o(b)"; |
252b5132 | 8176 | coproc = 1; |
bdaaa2e1 | 8177 | /* Itbl support may require additional care here. */ |
df58fc94 | 8178 | goto ld_st; |
252b5132 | 8179 | case M_SDC2_AB: |
df58fc94 RS |
8180 | ab = 1; |
8181 | case M_SDC2_OB: | |
252b5132 | 8182 | s = "sdc2"; |
df58fc94 RS |
8183 | fmt = COP12_FMT; |
8184 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8185 | /* Itbl support may require additional care here. */ |
252b5132 | 8186 | coproc = 1; |
df58fc94 | 8187 | goto ld_st; |
252b5132 | 8188 | case M_SDC3_AB: |
df58fc94 RS |
8189 | ab = 1; |
8190 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8191 | s = "sdc3"; |
df58fc94 | 8192 | fmt = "E,o(b)"; |
bdaaa2e1 | 8193 | /* Itbl support may require additional care here. */ |
252b5132 | 8194 | coproc = 1; |
df58fc94 | 8195 | goto ld_st; |
252b5132 | 8196 | case M_SDL_AB: |
df58fc94 RS |
8197 | ab = 1; |
8198 | case M_SDL_OB: | |
252b5132 | 8199 | s = "sdl"; |
df58fc94 RS |
8200 | fmt = MEM12_FMT; |
8201 | off12 = mips_opts.micromips; | |
8202 | goto ld_st; | |
252b5132 | 8203 | case M_SDR_AB: |
df58fc94 RS |
8204 | ab = 1; |
8205 | case M_SDR_OB: | |
252b5132 | 8206 | s = "sdr"; |
df58fc94 RS |
8207 | fmt = MEM12_FMT; |
8208 | off12 = mips_opts.micromips; | |
8209 | goto ld_st; | |
8210 | case M_SWP_AB: | |
8211 | ab = 1; | |
8212 | case M_SWP_OB: | |
8213 | gas_assert (mips_opts.micromips); | |
8214 | s = "swp"; | |
8215 | fmt = "t,~(b)"; | |
8216 | off12 = 1; | |
8217 | goto ld_st; | |
8218 | case M_SDP_AB: | |
8219 | ab = 1; | |
8220 | case M_SDP_OB: | |
8221 | gas_assert (mips_opts.micromips); | |
8222 | s = "sdp"; | |
8223 | fmt = "t,~(b)"; | |
8224 | off12 = 1; | |
8225 | goto ld_st; | |
8226 | case M_SWM_AB: | |
8227 | ab = 1; | |
8228 | case M_SWM_OB: | |
8229 | gas_assert (mips_opts.micromips); | |
8230 | s = "swm"; | |
8231 | fmt = "n,~(b)"; | |
8232 | off12 = 1; | |
8233 | goto ld_st; | |
8234 | case M_SDM_AB: | |
8235 | ab = 1; | |
8236 | case M_SDM_OB: | |
8237 | gas_assert (mips_opts.micromips); | |
8238 | s = "sdm"; | |
8239 | fmt = "n,~(b)"; | |
8240 | off12 = 1; | |
8241 | ||
8242 | ld_st: | |
8fc2e39e TS |
8243 | tempreg = AT; |
8244 | used_at = 1; | |
df58fc94 | 8245 | ld_noat: |
b19e8a9b AN |
8246 | if (coproc |
8247 | && NO_ISA_COP (mips_opts.arch) | |
8248 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
8249 | { | |
f71d0d44 | 8250 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
8251 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
8252 | break; | |
8253 | } | |
8254 | ||
252b5132 RH |
8255 | if (offset_expr.X_op != O_constant |
8256 | && offset_expr.X_op != O_symbol) | |
8257 | { | |
f71d0d44 | 8258 | as_bad (_("Expression too complex")); |
252b5132 RH |
8259 | offset_expr.X_op = O_constant; |
8260 | } | |
8261 | ||
2051e8c4 MR |
8262 | if (HAVE_32BIT_ADDRESSES |
8263 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8264 | { |
8265 | char value [32]; | |
8266 | ||
8267 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8268 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8269 | } |
2051e8c4 | 8270 | |
252b5132 RH |
8271 | /* A constant expression in PIC code can be handled just as it |
8272 | is in non PIC code. */ | |
aed1a261 RS |
8273 | if (offset_expr.X_op == O_constant) |
8274 | { | |
df58fc94 RS |
8275 | int hipart = 0; |
8276 | ||
842f8b2a | 8277 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8278 | normalize_address_expr (&expr1); |
df58fc94 | 8279 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8280 | { |
8281 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8282 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8283 | hipart = 1; |
8284 | } | |
8285 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8286 | { | |
8287 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8288 | & ~(bfd_vma) 0xfff); | |
8289 | hipart = 1; | |
8290 | } | |
8291 | if (hipart) | |
8292 | { | |
842f8b2a MR |
8293 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8294 | if (breg != 0) | |
8295 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8296 | tempreg, tempreg, breg); | |
8297 | breg = tempreg; | |
8298 | } | |
df58fc94 RS |
8299 | if (!off12) |
8300 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
8301 | else | |
8302 | macro_build (NULL, s, fmt, | |
8303 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8304 | } | |
8305 | else if (off12) | |
8306 | { | |
8307 | /* A 12-bit offset field is too narrow to be used for a low-part | |
8308 | relocation, so load the whole address into the auxillary | |
8309 | register. In the case of "A(b)" addresses, we first load | |
8310 | absolute address "A" into the register and then add base | |
8311 | register "b". In the case of "o(b)" addresses, we simply | |
8312 | need to add 16-bit offset "o" to base register "b", and | |
8313 | offset_reloc already contains the relocations associated | |
8314 | with "o". */ | |
8315 | if (ab) | |
8316 | { | |
8317 | load_address (tempreg, &offset_expr, &used_at); | |
8318 | if (breg != 0) | |
8319 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8320 | tempreg, tempreg, breg); | |
8321 | } | |
8322 | else | |
8323 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8324 | tempreg, breg, -1, | |
8325 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8326 | expr1.X_add_number = 0; | |
8327 | macro_build (NULL, s, fmt, | |
8328 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8329 | } |
8330 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8331 | { |
8332 | /* If this is a reference to a GP relative symbol, and there | |
8333 | is no base register, we want | |
cdf6fd85 | 8334 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8335 | Otherwise, if there is no base register, we want |
8336 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8337 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8338 | If we have a constant, we need two instructions anyhow, | |
8339 | so we always use the latter form. | |
8340 | ||
8341 | If we have a base register, and this is a reference to a | |
8342 | GP relative symbol, we want | |
8343 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8344 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8345 | Otherwise we want |
8346 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8347 | addu $tempreg,$tempreg,$breg | |
8348 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8349 | With a constant we always use the latter case. |
76b3015f | 8350 | |
d6bc6245 TS |
8351 | With 64bit address space and no base register and $at usable, |
8352 | we want | |
8353 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8354 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8355 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8356 | dsll32 $tempreg,0 | |
8357 | daddu $tempreg,$at | |
8358 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8359 | If we have a base register, we want | |
8360 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8361 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8362 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8363 | daddu $at,$breg | |
8364 | dsll32 $tempreg,0 | |
8365 | daddu $tempreg,$at | |
8366 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8367 | ||
8368 | Without $at we can't generate the optimal path for superscalar | |
8369 | processors here since this would require two temporary registers. | |
8370 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8371 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8372 | dsll $tempreg,16 | |
8373 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8374 | dsll $tempreg,16 | |
8375 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8376 | If we have a base register, we want | |
8377 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8378 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8379 | dsll $tempreg,16 | |
8380 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8381 | dsll $tempreg,16 | |
8382 | daddu $tempreg,$tempreg,$breg | |
8383 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8384 | |
6caf9ef4 | 8385 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8386 | the same sequence as in 32bit address space. */ |
8387 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8388 | { |
aed1a261 | 8389 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8390 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8391 | { | |
8392 | relax_start (offset_expr.X_add_symbol); | |
8393 | if (breg == 0) | |
8394 | { | |
8395 | macro_build (&offset_expr, s, fmt, treg, | |
8396 | BFD_RELOC_GPREL16, mips_gp_register); | |
8397 | } | |
8398 | else | |
8399 | { | |
8400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8401 | tempreg, breg, mips_gp_register); | |
8402 | macro_build (&offset_expr, s, fmt, treg, | |
8403 | BFD_RELOC_GPREL16, tempreg); | |
8404 | } | |
8405 | relax_switch (); | |
8406 | } | |
d6bc6245 | 8407 | |
741fe287 | 8408 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8409 | { |
df58fc94 | 8410 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8411 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8412 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8413 | BFD_RELOC_HI16_S); |
8414 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8415 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8416 | if (breg != 0) |
67c0d1eb | 8417 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8418 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8419 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8420 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8421 | tempreg); | |
d6bc6245 TS |
8422 | used_at = 1; |
8423 | } | |
8424 | else | |
8425 | { | |
df58fc94 | 8426 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8427 | BFD_RELOC_MIPS_HIGHEST); |
8428 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8429 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8430 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8431 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8432 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8433 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8434 | if (breg != 0) |
67c0d1eb | 8435 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8436 | tempreg, tempreg, breg); |
67c0d1eb | 8437 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8438 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8439 | } |
6caf9ef4 TS |
8440 | |
8441 | if (mips_relax.sequence) | |
8442 | relax_end (); | |
8fc2e39e | 8443 | break; |
d6bc6245 | 8444 | } |
256ab948 | 8445 | |
252b5132 RH |
8446 | if (breg == 0) |
8447 | { | |
67c0d1eb | 8448 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8449 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8450 | { |
4d7206a2 | 8451 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8452 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8453 | mips_gp_register); | |
4d7206a2 | 8454 | relax_switch (); |
252b5132 | 8455 | } |
67c0d1eb RS |
8456 | macro_build_lui (&offset_expr, tempreg); |
8457 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8458 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8459 | if (mips_relax.sequence) |
8460 | relax_end (); | |
252b5132 RH |
8461 | } |
8462 | else | |
8463 | { | |
67c0d1eb | 8464 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8465 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8466 | { |
4d7206a2 | 8467 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8468 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8469 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8470 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8471 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8472 | relax_switch (); |
252b5132 | 8473 | } |
67c0d1eb RS |
8474 | macro_build_lui (&offset_expr, tempreg); |
8475 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8476 | tempreg, tempreg, breg); |
67c0d1eb | 8477 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8478 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8479 | if (mips_relax.sequence) |
8480 | relax_end (); | |
252b5132 RH |
8481 | } |
8482 | } | |
0a44bf69 | 8483 | else if (!mips_big_got) |
252b5132 | 8484 | { |
ed6fb7bd | 8485 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8486 | |
252b5132 RH |
8487 | /* If this is a reference to an external symbol, we want |
8488 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8489 | nop | |
8490 | <op> $treg,0($tempreg) | |
8491 | Otherwise we want | |
8492 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8493 | nop | |
8494 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8495 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8496 | |
8497 | For NewABI, we want | |
8498 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8499 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8500 | ||
252b5132 RH |
8501 | If there is a base register, we add it to $tempreg before |
8502 | the <op>. If there is a constant, we stick it in the | |
8503 | <op> instruction. We don't handle constants larger than | |
8504 | 16 bits, because we have no way to load the upper 16 bits | |
8505 | (actually, we could handle them for the subset of cases | |
8506 | in which we are not using $at). */ | |
9c2799c2 | 8507 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8508 | if (HAVE_NEWABI) |
8509 | { | |
67c0d1eb RS |
8510 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8511 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8512 | if (breg != 0) |
67c0d1eb | 8513 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8514 | tempreg, tempreg, breg); |
67c0d1eb | 8515 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8516 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8517 | break; |
8518 | } | |
252b5132 RH |
8519 | expr1.X_add_number = offset_expr.X_add_number; |
8520 | offset_expr.X_add_number = 0; | |
8521 | if (expr1.X_add_number < -0x8000 | |
8522 | || expr1.X_add_number >= 0x8000) | |
8523 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8524 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8525 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8526 | load_delay_nop (); |
4d7206a2 RS |
8527 | relax_start (offset_expr.X_add_symbol); |
8528 | relax_switch (); | |
67c0d1eb RS |
8529 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8530 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8531 | relax_end (); |
252b5132 | 8532 | if (breg != 0) |
67c0d1eb | 8533 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8534 | tempreg, tempreg, breg); |
67c0d1eb | 8535 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8536 | } |
0a44bf69 | 8537 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8538 | { |
67c0d1eb | 8539 | int gpdelay; |
252b5132 RH |
8540 | |
8541 | /* If this is a reference to an external symbol, we want | |
8542 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8543 | addu $tempreg,$tempreg,$gp | |
8544 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8545 | <op> $treg,0($tempreg) | |
8546 | Otherwise we want | |
8547 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8548 | nop | |
8549 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8550 | <op> $treg,0($tempreg) | |
8551 | If there is a base register, we add it to $tempreg before | |
8552 | the <op>. If there is a constant, we stick it in the | |
8553 | <op> instruction. We don't handle constants larger than | |
8554 | 16 bits, because we have no way to load the upper 16 bits | |
8555 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8556 | in which we are not using $at). */ |
9c2799c2 | 8557 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8558 | expr1.X_add_number = offset_expr.X_add_number; |
8559 | offset_expr.X_add_number = 0; | |
8560 | if (expr1.X_add_number < -0x8000 | |
8561 | || expr1.X_add_number >= 0x8000) | |
8562 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8563 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8564 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8565 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8566 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8568 | mips_gp_register); | |
8569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8570 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8571 | relax_switch (); |
67c0d1eb RS |
8572 | if (gpdelay) |
8573 | macro_build (NULL, "nop", ""); | |
8574 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8575 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8576 | load_delay_nop (); |
67c0d1eb RS |
8577 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8578 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8579 | relax_end (); |
8580 | ||
252b5132 | 8581 | if (breg != 0) |
67c0d1eb | 8582 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8583 | tempreg, tempreg, breg); |
67c0d1eb | 8584 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8585 | } |
0a44bf69 | 8586 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8587 | { |
f5040a92 AO |
8588 | /* If this is a reference to an external symbol, we want |
8589 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8590 | add $tempreg,$tempreg,$gp | |
8591 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8592 | <op> $treg,<ofst>($tempreg) | |
8593 | Otherwise, for local symbols, we want: | |
8594 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8595 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8596 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8597 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8598 | offset_expr.X_add_number = 0; |
8599 | if (expr1.X_add_number < -0x8000 | |
8600 | || expr1.X_add_number >= 0x8000) | |
8601 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8602 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8603 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8604 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8605 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8606 | mips_gp_register); | |
8607 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8608 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8609 | if (breg != 0) |
67c0d1eb | 8610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8611 | tempreg, tempreg, breg); |
67c0d1eb | 8612 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8613 | |
4d7206a2 | 8614 | relax_switch (); |
f5040a92 | 8615 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8616 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8617 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8618 | if (breg != 0) |
67c0d1eb | 8619 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8620 | tempreg, tempreg, breg); |
67c0d1eb | 8621 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8622 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8623 | relax_end (); |
f5040a92 | 8624 | } |
252b5132 RH |
8625 | else |
8626 | abort (); | |
8627 | ||
252b5132 RH |
8628 | break; |
8629 | ||
8630 | case M_LI: | |
8631 | case M_LI_S: | |
67c0d1eb | 8632 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8633 | break; |
252b5132 RH |
8634 | |
8635 | case M_DLI: | |
67c0d1eb | 8636 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8637 | break; |
252b5132 RH |
8638 | |
8639 | case M_LI_SS: | |
8640 | if (imm_expr.X_op == O_constant) | |
8641 | { | |
8fc2e39e | 8642 | used_at = 1; |
67c0d1eb RS |
8643 | load_register (AT, &imm_expr, 0); |
8644 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8645 | break; |
8646 | } | |
8647 | else | |
8648 | { | |
9c2799c2 | 8649 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8650 | && strcmp (segment_name (S_GET_SEGMENT |
8651 | (offset_expr.X_add_symbol)), | |
8652 | ".lit4") == 0 | |
8653 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8654 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8655 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8656 | break; |
252b5132 RH |
8657 | } |
8658 | ||
8659 | case M_LI_D: | |
ca4e0257 RS |
8660 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8661 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8662 | order 32 bits of the value and the low order 32 bits are either | |
8663 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8664 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8665 | { | |
ca4e0257 | 8666 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8667 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8668 | else |
8669 | { | |
8670 | int hreg, lreg; | |
8671 | ||
8672 | if (target_big_endian) | |
8673 | { | |
8674 | hreg = treg; | |
8675 | lreg = treg + 1; | |
8676 | } | |
8677 | else | |
8678 | { | |
8679 | hreg = treg + 1; | |
8680 | lreg = treg; | |
8681 | } | |
8682 | ||
8683 | if (hreg <= 31) | |
67c0d1eb | 8684 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8685 | if (lreg <= 31) |
8686 | { | |
8687 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8688 | move_register (lreg, 0); |
252b5132 RH |
8689 | else |
8690 | { | |
9c2799c2 | 8691 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8692 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8693 | } |
8694 | } | |
8695 | } | |
8fc2e39e | 8696 | break; |
252b5132 RH |
8697 | } |
8698 | ||
8699 | /* We know that sym is in the .rdata section. First we get the | |
8700 | upper 16 bits of the address. */ | |
8701 | if (mips_pic == NO_PIC) | |
8702 | { | |
67c0d1eb | 8703 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8704 | used_at = 1; |
252b5132 | 8705 | } |
0a44bf69 | 8706 | else |
252b5132 | 8707 | { |
67c0d1eb RS |
8708 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8709 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8710 | used_at = 1; |
252b5132 | 8711 | } |
bdaaa2e1 | 8712 | |
252b5132 | 8713 | /* Now we load the register(s). */ |
ca4e0257 | 8714 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8715 | { |
8716 | used_at = 1; | |
8717 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8718 | } | |
252b5132 RH |
8719 | else |
8720 | { | |
8fc2e39e | 8721 | used_at = 1; |
67c0d1eb | 8722 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8723 | if (treg != RA) |
252b5132 RH |
8724 | { |
8725 | /* FIXME: How in the world do we deal with the possible | |
8726 | overflow here? */ | |
8727 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8728 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8729 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8730 | } |
8731 | } | |
252b5132 RH |
8732 | break; |
8733 | ||
8734 | case M_LI_DD: | |
ca4e0257 RS |
8735 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8736 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8737 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8738 | the value and the low order 32 bits are either zero or in | |
8739 | OFFSET_EXPR. */ | |
252b5132 RH |
8740 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8741 | { | |
8fc2e39e | 8742 | used_at = 1; |
67c0d1eb | 8743 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8744 | if (HAVE_64BIT_FPRS) |
8745 | { | |
9c2799c2 | 8746 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8747 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8748 | } |
252b5132 RH |
8749 | else |
8750 | { | |
67c0d1eb | 8751 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8752 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8753 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8754 | else |
8755 | { | |
9c2799c2 | 8756 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8757 | load_register (AT, &offset_expr, 0); |
8758 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8759 | } |
8760 | } | |
8761 | break; | |
8762 | } | |
8763 | ||
9c2799c2 | 8764 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8765 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8766 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8767 | if (strcmp (s, ".lit8") == 0) | |
8768 | { | |
df58fc94 | 8769 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8770 | { |
67c0d1eb | 8771 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8772 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8773 | break; |
252b5132 | 8774 | } |
c9914766 | 8775 | breg = mips_gp_register; |
252b5132 RH |
8776 | r = BFD_RELOC_MIPS_LITERAL; |
8777 | goto dob; | |
8778 | } | |
8779 | else | |
8780 | { | |
9c2799c2 | 8781 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8782 | used_at = 1; |
0a44bf69 | 8783 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8784 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8785 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8786 | else |
8787 | { | |
8788 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8789 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8790 | } |
bdaaa2e1 | 8791 | |
df58fc94 | 8792 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8793 | { |
67c0d1eb RS |
8794 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8795 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8796 | break; |
8797 | } | |
8798 | breg = AT; | |
8799 | r = BFD_RELOC_LO16; | |
8800 | goto dob; | |
8801 | } | |
8802 | ||
8803 | case M_L_DOB: | |
252b5132 RH |
8804 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8805 | to adjust when loading from memory. */ | |
8806 | r = BFD_RELOC_LO16; | |
8807 | dob: | |
df58fc94 | 8808 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8809 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8810 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8811 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8812 | /* FIXME: A possible overflow which I don't know how to deal |
8813 | with. */ | |
8814 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8815 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8816 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8817 | break; |
8818 | ||
c4a68bea | 8819 | case M_S_DOB: |
df58fc94 | 8820 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8821 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8822 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8823 | to adjust when storing to memory. */ | |
8824 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8825 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8826 | offset_expr.X_add_number += 4; | |
8827 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8828 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8829 | break; | |
8830 | ||
252b5132 | 8831 | case M_L_DAB: |
df58fc94 | 8832 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8833 | /* |
8834 | * The MIPS assembler seems to check for X_add_number not | |
8835 | * being double aligned and generating: | |
8836 | * lui at,%hi(foo+1) | |
8837 | * addu at,at,v1 | |
8838 | * addiu at,at,%lo(foo+1) | |
8839 | * lwc1 f2,0(at) | |
8840 | * lwc1 f3,4(at) | |
8841 | * But, the resulting address is the same after relocation so why | |
8842 | * generate the extra instruction? | |
8843 | */ | |
bdaaa2e1 | 8844 | /* Itbl support may require additional care here. */ |
252b5132 | 8845 | coproc = 1; |
df58fc94 | 8846 | fmt = "T,o(b)"; |
e7af610e | 8847 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8848 | { |
8849 | s = "ldc1"; | |
df58fc94 | 8850 | goto ld_st; |
252b5132 | 8851 | } |
252b5132 | 8852 | s = "lwc1"; |
252b5132 RH |
8853 | goto ldd_std; |
8854 | ||
8855 | case M_S_DAB: | |
df58fc94 RS |
8856 | gas_assert (!mips_opts.micromips); |
8857 | /* Itbl support may require additional care here. */ | |
8858 | coproc = 1; | |
8859 | fmt = "T,o(b)"; | |
e7af610e | 8860 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8861 | { |
8862 | s = "sdc1"; | |
df58fc94 | 8863 | goto ld_st; |
252b5132 | 8864 | } |
252b5132 | 8865 | s = "swc1"; |
252b5132 RH |
8866 | goto ldd_std; |
8867 | ||
8868 | case M_LD_AB: | |
df58fc94 | 8869 | fmt = "t,o(b)"; |
ca4e0257 | 8870 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8871 | { |
8872 | s = "ld"; | |
8873 | goto ld; | |
8874 | } | |
252b5132 | 8875 | s = "lw"; |
252b5132 RH |
8876 | goto ldd_std; |
8877 | ||
8878 | case M_SD_AB: | |
df58fc94 | 8879 | fmt = "t,o(b)"; |
ca4e0257 | 8880 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8881 | { |
8882 | s = "sd"; | |
df58fc94 | 8883 | goto ld_st; |
252b5132 | 8884 | } |
252b5132 | 8885 | s = "sw"; |
252b5132 RH |
8886 | |
8887 | ldd_std: | |
8888 | if (offset_expr.X_op != O_symbol | |
8889 | && offset_expr.X_op != O_constant) | |
8890 | { | |
f71d0d44 | 8891 | as_bad (_("Expression too complex")); |
252b5132 RH |
8892 | offset_expr.X_op = O_constant; |
8893 | } | |
8894 | ||
2051e8c4 MR |
8895 | if (HAVE_32BIT_ADDRESSES |
8896 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8897 | { |
8898 | char value [32]; | |
8899 | ||
8900 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8901 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8902 | } |
2051e8c4 | 8903 | |
252b5132 RH |
8904 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8905 | to adjust when loading from memory. We set coproc if we must | |
8906 | load $fn+1 first. */ | |
bdaaa2e1 | 8907 | /* Itbl support may require additional care here. */ |
90ecf173 | 8908 | if (!target_big_endian) |
252b5132 RH |
8909 | coproc = 0; |
8910 | ||
90ecf173 | 8911 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8912 | { |
8913 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8914 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8915 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8916 | If we have a base register, we use this |
8917 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8918 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8919 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8920 | If this is not a GP relative symbol, we want |
8921 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8922 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8923 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8924 | If there is a base register, we add it to $at after the | |
8925 | lui instruction. If there is a constant, we always use | |
8926 | the last case. */ | |
39a59cf8 MR |
8927 | if (offset_expr.X_op == O_symbol |
8928 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8929 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8930 | { |
4d7206a2 | 8931 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8932 | if (breg == 0) |
8933 | { | |
c9914766 | 8934 | tempreg = mips_gp_register; |
252b5132 RH |
8935 | } |
8936 | else | |
8937 | { | |
67c0d1eb | 8938 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8939 | AT, breg, mips_gp_register); |
252b5132 | 8940 | tempreg = AT; |
252b5132 RH |
8941 | used_at = 1; |
8942 | } | |
8943 | ||
beae10d5 | 8944 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8945 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8946 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8947 | offset_expr.X_add_number += 4; |
8948 | ||
8949 | /* Set mips_optimize to 2 to avoid inserting an | |
8950 | undesired nop. */ | |
8951 | hold_mips_optimize = mips_optimize; | |
8952 | mips_optimize = 2; | |
beae10d5 | 8953 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8954 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8955 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8956 | mips_optimize = hold_mips_optimize; |
8957 | ||
4d7206a2 | 8958 | relax_switch (); |
252b5132 | 8959 | |
0970e49e | 8960 | offset_expr.X_add_number -= 4; |
252b5132 | 8961 | } |
8fc2e39e | 8962 | used_at = 1; |
67c0d1eb | 8963 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8964 | if (breg != 0) |
67c0d1eb | 8965 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 8966 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8967 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8968 | BFD_RELOC_LO16, AT); |
252b5132 RH |
8969 | /* FIXME: How do we handle overflow here? */ |
8970 | offset_expr.X_add_number += 4; | |
beae10d5 | 8971 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8972 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8973 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
8974 | if (mips_relax.sequence) |
8975 | relax_end (); | |
bdaaa2e1 | 8976 | } |
0a44bf69 | 8977 | else if (!mips_big_got) |
252b5132 | 8978 | { |
252b5132 RH |
8979 | /* If this is a reference to an external symbol, we want |
8980 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8981 | nop | |
8982 | <op> $treg,0($at) | |
8983 | <op> $treg+1,4($at) | |
8984 | Otherwise we want | |
8985 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8986 | nop | |
8987 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8988 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8989 | If there is a base register we add it to $at before the | |
8990 | lwc1 instructions. If there is a constant we include it | |
8991 | in the lwc1 instructions. */ | |
8992 | used_at = 1; | |
8993 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
8994 | if (expr1.X_add_number < -0x8000 |
8995 | || expr1.X_add_number >= 0x8000 - 4) | |
8996 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8997 | load_got_offset (AT, &offset_expr); |
269137b2 | 8998 | load_delay_nop (); |
252b5132 | 8999 | if (breg != 0) |
67c0d1eb | 9000 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9001 | |
9002 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9003 | nop. */ | |
9004 | hold_mips_optimize = mips_optimize; | |
9005 | mips_optimize = 2; | |
4d7206a2 | 9006 | |
beae10d5 | 9007 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9008 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9009 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9010 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9011 | expr1.X_add_number += 4; |
67c0d1eb RS |
9012 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9013 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9014 | relax_switch (); |
67c0d1eb RS |
9015 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9016 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9017 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9018 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9019 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9020 | relax_end (); |
252b5132 | 9021 | |
4d7206a2 | 9022 | mips_optimize = hold_mips_optimize; |
252b5132 | 9023 | } |
0a44bf69 | 9024 | else if (mips_big_got) |
252b5132 | 9025 | { |
67c0d1eb | 9026 | int gpdelay; |
252b5132 RH |
9027 | |
9028 | /* If this is a reference to an external symbol, we want | |
9029 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9030 | addu $at,$at,$gp | |
9031 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9032 | nop | |
9033 | <op> $treg,0($at) | |
9034 | <op> $treg+1,4($at) | |
9035 | Otherwise we want | |
9036 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9037 | nop | |
9038 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9039 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9040 | If there is a base register we add it to $at before the | |
9041 | lwc1 instructions. If there is a constant we include it | |
9042 | in the lwc1 instructions. */ | |
9043 | used_at = 1; | |
9044 | expr1.X_add_number = offset_expr.X_add_number; | |
9045 | offset_expr.X_add_number = 0; | |
9046 | if (expr1.X_add_number < -0x8000 | |
9047 | || expr1.X_add_number >= 0x8000 - 4) | |
9048 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9049 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9050 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9051 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9052 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9053 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9054 | AT, AT, mips_gp_register); |
67c0d1eb | 9055 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9056 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9057 | load_delay_nop (); |
252b5132 | 9058 | if (breg != 0) |
67c0d1eb | 9059 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9060 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9061 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9062 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9063 | expr1.X_add_number += 4; |
9064 | ||
9065 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9066 | nop. */ | |
9067 | hold_mips_optimize = mips_optimize; | |
9068 | mips_optimize = 2; | |
beae10d5 | 9069 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9070 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9071 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9072 | mips_optimize = hold_mips_optimize; |
9073 | expr1.X_add_number -= 4; | |
9074 | ||
4d7206a2 RS |
9075 | relax_switch (); |
9076 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9077 | if (gpdelay) |
9078 | macro_build (NULL, "nop", ""); | |
9079 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9080 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9081 | load_delay_nop (); |
252b5132 | 9082 | if (breg != 0) |
67c0d1eb | 9083 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9084 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9085 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9086 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9087 | offset_expr.X_add_number += 4; |
252b5132 RH |
9088 | |
9089 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9090 | nop. */ | |
9091 | hold_mips_optimize = mips_optimize; | |
9092 | mips_optimize = 2; | |
beae10d5 | 9093 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9094 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9095 | BFD_RELOC_LO16, AT); | |
252b5132 | 9096 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9097 | relax_end (); |
252b5132 | 9098 | } |
252b5132 RH |
9099 | else |
9100 | abort (); | |
9101 | ||
252b5132 RH |
9102 | break; |
9103 | ||
9104 | case M_LD_OB: | |
704897fb | 9105 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9106 | goto sd_ob; |
9107 | case M_SD_OB: | |
704897fb | 9108 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9109 | sd_ob: |
4614d845 MR |
9110 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9111 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9112 | breg); | |
704897fb MR |
9113 | if (!HAVE_64BIT_GPRS) |
9114 | { | |
9115 | offset_expr.X_add_number += 4; | |
9116 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9117 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9118 | breg); | |
704897fb | 9119 | } |
8fc2e39e | 9120 | break; |
252b5132 RH |
9121 | |
9122 | /* New code added to support COPZ instructions. | |
9123 | This code builds table entries out of the macros in mip_opcodes. | |
9124 | R4000 uses interlocks to handle coproc delays. | |
9125 | Other chips (like the R3000) require nops to be inserted for delays. | |
9126 | ||
f72c8c98 | 9127 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9128 | In order to fill delay slots for non-interlocked chips, |
9129 | we must have a way to specify delays based on the coprocessor. | |
9130 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9131 | What are the side-effects of the cop instruction? | |
9132 | What cache support might we have and what are its effects? | |
9133 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9134 | What registers are read/set/modified? |
252b5132 RH |
9135 | |
9136 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9137 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9138 | |
9139 | case M_COP0: | |
9140 | s = "c0"; | |
9141 | goto copz; | |
9142 | case M_COP1: | |
9143 | s = "c1"; | |
9144 | goto copz; | |
9145 | case M_COP2: | |
9146 | s = "c2"; | |
9147 | goto copz; | |
9148 | case M_COP3: | |
9149 | s = "c3"; | |
9150 | copz: | |
df58fc94 | 9151 | gas_assert (!mips_opts.micromips); |
b19e8a9b AN |
9152 | if (NO_ISA_COP (mips_opts.arch) |
9153 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
9154 | { | |
9155 | as_bad (_("opcode not supported on this processor: %s"), | |
9156 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
9157 | break; | |
9158 | } | |
9159 | ||
252b5132 RH |
9160 | /* For now we just do C (same as Cz). The parameter will be |
9161 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9162 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9163 | break; |
252b5132 | 9164 | |
ea1fb5dc | 9165 | case M_MOVE: |
67c0d1eb | 9166 | move_register (dreg, sreg); |
8fc2e39e | 9167 | break; |
ea1fb5dc | 9168 | |
252b5132 RH |
9169 | case M_DMUL: |
9170 | dbl = 1; | |
9171 | case M_MUL: | |
67c0d1eb | 9172 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9173 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9174 | break; |
252b5132 RH |
9175 | |
9176 | case M_DMUL_I: | |
9177 | dbl = 1; | |
9178 | case M_MUL_I: | |
9179 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9180 | not trying to be that fancy. GCC should do this for us | |
9181 | anyway. */ | |
8fc2e39e | 9182 | used_at = 1; |
67c0d1eb RS |
9183 | load_register (AT, &imm_expr, dbl); |
9184 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9185 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9186 | break; |
9187 | ||
9188 | case M_DMULO_I: | |
9189 | dbl = 1; | |
9190 | case M_MULO_I: | |
9191 | imm = 1; | |
9192 | goto do_mulo; | |
9193 | ||
9194 | case M_DMULO: | |
9195 | dbl = 1; | |
9196 | case M_MULO: | |
9197 | do_mulo: | |
7d10b47d | 9198 | start_noreorder (); |
8fc2e39e | 9199 | used_at = 1; |
252b5132 | 9200 | if (imm) |
67c0d1eb RS |
9201 | load_register (AT, &imm_expr, dbl); |
9202 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9203 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9204 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9205 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9206 | if (mips_trap) |
df58fc94 | 9207 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9208 | else |
9209 | { | |
df58fc94 RS |
9210 | if (mips_opts.micromips) |
9211 | micromips_label_expr (&label_expr); | |
9212 | else | |
9213 | label_expr.X_add_number = 8; | |
9214 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9215 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9216 | macro_build (NULL, "break", BRK_FMT, 6); |
9217 | if (mips_opts.micromips) | |
9218 | micromips_add_label (); | |
252b5132 | 9219 | } |
7d10b47d | 9220 | end_noreorder (); |
df58fc94 | 9221 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9222 | break; |
9223 | ||
9224 | case M_DMULOU_I: | |
9225 | dbl = 1; | |
9226 | case M_MULOU_I: | |
9227 | imm = 1; | |
9228 | goto do_mulou; | |
9229 | ||
9230 | case M_DMULOU: | |
9231 | dbl = 1; | |
9232 | case M_MULOU: | |
9233 | do_mulou: | |
7d10b47d | 9234 | start_noreorder (); |
8fc2e39e | 9235 | used_at = 1; |
252b5132 | 9236 | if (imm) |
67c0d1eb RS |
9237 | load_register (AT, &imm_expr, dbl); |
9238 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9239 | sreg, imm ? AT : treg); |
df58fc94 RS |
9240 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9241 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9242 | if (mips_trap) |
df58fc94 | 9243 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9244 | else |
9245 | { | |
df58fc94 RS |
9246 | if (mips_opts.micromips) |
9247 | micromips_label_expr (&label_expr); | |
9248 | else | |
9249 | label_expr.X_add_number = 8; | |
9250 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9251 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9252 | macro_build (NULL, "break", BRK_FMT, 6); |
9253 | if (mips_opts.micromips) | |
9254 | micromips_add_label (); | |
252b5132 | 9255 | } |
7d10b47d | 9256 | end_noreorder (); |
252b5132 RH |
9257 | break; |
9258 | ||
771c7ce4 | 9259 | case M_DROL: |
fef14a42 | 9260 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9261 | { |
9262 | if (dreg == sreg) | |
9263 | { | |
9264 | tempreg = AT; | |
9265 | used_at = 1; | |
9266 | } | |
9267 | else | |
9268 | { | |
9269 | tempreg = dreg; | |
82dd0097 | 9270 | } |
67c0d1eb RS |
9271 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9272 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9273 | break; |
82dd0097 | 9274 | } |
8fc2e39e | 9275 | used_at = 1; |
c80c840e | 9276 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9277 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9278 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9279 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9280 | break; |
9281 | ||
252b5132 | 9282 | case M_ROL: |
fef14a42 | 9283 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9284 | { |
9285 | if (dreg == sreg) | |
9286 | { | |
9287 | tempreg = AT; | |
9288 | used_at = 1; | |
9289 | } | |
9290 | else | |
9291 | { | |
9292 | tempreg = dreg; | |
82dd0097 | 9293 | } |
67c0d1eb RS |
9294 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9295 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9296 | break; |
82dd0097 | 9297 | } |
8fc2e39e | 9298 | used_at = 1; |
c80c840e | 9299 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9300 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9301 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9302 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9303 | break; |
9304 | ||
771c7ce4 TS |
9305 | case M_DROL_I: |
9306 | { | |
9307 | unsigned int rot; | |
91d6fa6a NC |
9308 | char *l; |
9309 | char *rr; | |
771c7ce4 TS |
9310 | |
9311 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9312 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9313 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9314 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9315 | { |
9316 | rot = (64 - rot) & 0x3f; | |
9317 | if (rot >= 32) | |
df58fc94 | 9318 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9319 | else |
df58fc94 | 9320 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9321 | break; |
60b63b72 | 9322 | } |
483fc7cd | 9323 | if (rot == 0) |
483fc7cd | 9324 | { |
df58fc94 | 9325 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9326 | break; |
483fc7cd | 9327 | } |
82dd0097 | 9328 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9329 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9330 | rot &= 0x1f; |
8fc2e39e | 9331 | used_at = 1; |
df58fc94 RS |
9332 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9333 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9334 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9335 | } |
9336 | break; | |
9337 | ||
252b5132 | 9338 | case M_ROL_I: |
771c7ce4 TS |
9339 | { |
9340 | unsigned int rot; | |
9341 | ||
9342 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9343 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9344 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9345 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9346 | { |
df58fc94 | 9347 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9348 | break; |
60b63b72 | 9349 | } |
483fc7cd | 9350 | if (rot == 0) |
483fc7cd | 9351 | { |
df58fc94 | 9352 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9353 | break; |
483fc7cd | 9354 | } |
8fc2e39e | 9355 | used_at = 1; |
df58fc94 RS |
9356 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9357 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9358 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9359 | } |
9360 | break; | |
9361 | ||
9362 | case M_DROR: | |
fef14a42 | 9363 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9364 | { |
67c0d1eb | 9365 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9366 | break; |
82dd0097 | 9367 | } |
8fc2e39e | 9368 | used_at = 1; |
c80c840e | 9369 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9370 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9371 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9372 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9373 | break; |
9374 | ||
9375 | case M_ROR: | |
fef14a42 | 9376 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9377 | { |
67c0d1eb | 9378 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9379 | break; |
82dd0097 | 9380 | } |
8fc2e39e | 9381 | used_at = 1; |
c80c840e | 9382 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9383 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9384 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9385 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9386 | break; |
9387 | ||
771c7ce4 TS |
9388 | case M_DROR_I: |
9389 | { | |
9390 | unsigned int rot; | |
91d6fa6a NC |
9391 | char *l; |
9392 | char *rr; | |
771c7ce4 TS |
9393 | |
9394 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9395 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9396 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9397 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9398 | { |
9399 | if (rot >= 32) | |
df58fc94 | 9400 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9401 | else |
df58fc94 | 9402 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9403 | break; |
82dd0097 | 9404 | } |
483fc7cd | 9405 | if (rot == 0) |
483fc7cd | 9406 | { |
df58fc94 | 9407 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9408 | break; |
483fc7cd | 9409 | } |
91d6fa6a | 9410 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9411 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9412 | rot &= 0x1f; | |
8fc2e39e | 9413 | used_at = 1; |
df58fc94 RS |
9414 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9415 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9416 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9417 | } |
9418 | break; | |
9419 | ||
252b5132 | 9420 | case M_ROR_I: |
771c7ce4 TS |
9421 | { |
9422 | unsigned int rot; | |
9423 | ||
9424 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9425 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9426 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9427 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9428 | { |
df58fc94 | 9429 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9430 | break; |
82dd0097 | 9431 | } |
483fc7cd | 9432 | if (rot == 0) |
483fc7cd | 9433 | { |
df58fc94 | 9434 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9435 | break; |
483fc7cd | 9436 | } |
8fc2e39e | 9437 | used_at = 1; |
df58fc94 RS |
9438 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9439 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9440 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9441 | } |
252b5132 RH |
9442 | break; |
9443 | ||
252b5132 RH |
9444 | case M_SEQ: |
9445 | if (sreg == 0) | |
67c0d1eb | 9446 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9447 | else if (treg == 0) |
67c0d1eb | 9448 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9449 | else |
9450 | { | |
67c0d1eb RS |
9451 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9452 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9453 | } |
8fc2e39e | 9454 | break; |
252b5132 RH |
9455 | |
9456 | case M_SEQ_I: | |
9457 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9458 | { | |
67c0d1eb | 9459 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9460 | break; |
252b5132 RH |
9461 | } |
9462 | if (sreg == 0) | |
9463 | { | |
9464 | as_warn (_("Instruction %s: result is always false"), | |
9465 | ip->insn_mo->name); | |
67c0d1eb | 9466 | move_register (dreg, 0); |
8fc2e39e | 9467 | break; |
252b5132 | 9468 | } |
dd3cbb7e NC |
9469 | if (CPU_HAS_SEQ (mips_opts.arch) |
9470 | && -512 <= imm_expr.X_add_number | |
9471 | && imm_expr.X_add_number < 512) | |
9472 | { | |
9473 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9474 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9475 | break; |
9476 | } | |
252b5132 RH |
9477 | if (imm_expr.X_op == O_constant |
9478 | && imm_expr.X_add_number >= 0 | |
9479 | && imm_expr.X_add_number < 0x10000) | |
9480 | { | |
67c0d1eb | 9481 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9482 | } |
9483 | else if (imm_expr.X_op == O_constant | |
9484 | && imm_expr.X_add_number > -0x8000 | |
9485 | && imm_expr.X_add_number < 0) | |
9486 | { | |
9487 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9488 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9489 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9490 | } |
dd3cbb7e NC |
9491 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9492 | { | |
9493 | used_at = 1; | |
9494 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9495 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9496 | break; | |
9497 | } | |
252b5132 RH |
9498 | else |
9499 | { | |
67c0d1eb RS |
9500 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9501 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9502 | used_at = 1; |
9503 | } | |
67c0d1eb | 9504 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9505 | break; |
252b5132 RH |
9506 | |
9507 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9508 | s = "slt"; | |
9509 | goto sge; | |
9510 | case M_SGEU: | |
9511 | s = "sltu"; | |
9512 | sge: | |
67c0d1eb RS |
9513 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9514 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9515 | break; |
252b5132 RH |
9516 | |
9517 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9518 | case M_SGEU_I: | |
9519 | if (imm_expr.X_op == O_constant | |
9520 | && imm_expr.X_add_number >= -0x8000 | |
9521 | && imm_expr.X_add_number < 0x8000) | |
9522 | { | |
67c0d1eb RS |
9523 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9524 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9525 | } |
9526 | else | |
9527 | { | |
67c0d1eb RS |
9528 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9529 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9530 | dreg, sreg, AT); | |
252b5132 RH |
9531 | used_at = 1; |
9532 | } | |
67c0d1eb | 9533 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9534 | break; |
252b5132 RH |
9535 | |
9536 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9537 | s = "slt"; | |
9538 | goto sgt; | |
9539 | case M_SGTU: | |
9540 | s = "sltu"; | |
9541 | sgt: | |
67c0d1eb | 9542 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9543 | break; |
252b5132 RH |
9544 | |
9545 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9546 | s = "slt"; | |
9547 | goto sgti; | |
9548 | case M_SGTU_I: | |
9549 | s = "sltu"; | |
9550 | sgti: | |
8fc2e39e | 9551 | used_at = 1; |
67c0d1eb RS |
9552 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9553 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9554 | break; |
9555 | ||
2396cfb9 | 9556 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9557 | s = "slt"; |
9558 | goto sle; | |
9559 | case M_SLEU: | |
9560 | s = "sltu"; | |
9561 | sle: | |
67c0d1eb RS |
9562 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9563 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9564 | break; |
252b5132 | 9565 | |
2396cfb9 | 9566 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9567 | s = "slt"; |
9568 | goto slei; | |
9569 | case M_SLEU_I: | |
9570 | s = "sltu"; | |
9571 | slei: | |
8fc2e39e | 9572 | used_at = 1; |
67c0d1eb RS |
9573 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9574 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9575 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9576 | break; |
9577 | ||
9578 | case M_SLT_I: | |
9579 | if (imm_expr.X_op == O_constant | |
9580 | && imm_expr.X_add_number >= -0x8000 | |
9581 | && imm_expr.X_add_number < 0x8000) | |
9582 | { | |
67c0d1eb | 9583 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9584 | break; |
252b5132 | 9585 | } |
8fc2e39e | 9586 | used_at = 1; |
67c0d1eb RS |
9587 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9588 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9589 | break; |
9590 | ||
9591 | case M_SLTU_I: | |
9592 | if (imm_expr.X_op == O_constant | |
9593 | && imm_expr.X_add_number >= -0x8000 | |
9594 | && imm_expr.X_add_number < 0x8000) | |
9595 | { | |
67c0d1eb | 9596 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9597 | BFD_RELOC_LO16); |
8fc2e39e | 9598 | break; |
252b5132 | 9599 | } |
8fc2e39e | 9600 | used_at = 1; |
67c0d1eb RS |
9601 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9602 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9603 | break; |
9604 | ||
9605 | case M_SNE: | |
9606 | if (sreg == 0) | |
67c0d1eb | 9607 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9608 | else if (treg == 0) |
67c0d1eb | 9609 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9610 | else |
9611 | { | |
67c0d1eb RS |
9612 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9613 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9614 | } |
8fc2e39e | 9615 | break; |
252b5132 RH |
9616 | |
9617 | case M_SNE_I: | |
9618 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9619 | { | |
67c0d1eb | 9620 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9621 | break; |
252b5132 RH |
9622 | } |
9623 | if (sreg == 0) | |
9624 | { | |
9625 | as_warn (_("Instruction %s: result is always true"), | |
9626 | ip->insn_mo->name); | |
67c0d1eb RS |
9627 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9628 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9629 | break; |
252b5132 | 9630 | } |
dd3cbb7e NC |
9631 | if (CPU_HAS_SEQ (mips_opts.arch) |
9632 | && -512 <= imm_expr.X_add_number | |
9633 | && imm_expr.X_add_number < 512) | |
9634 | { | |
9635 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9636 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9637 | break; |
9638 | } | |
252b5132 RH |
9639 | if (imm_expr.X_op == O_constant |
9640 | && imm_expr.X_add_number >= 0 | |
9641 | && imm_expr.X_add_number < 0x10000) | |
9642 | { | |
67c0d1eb | 9643 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9644 | } |
9645 | else if (imm_expr.X_op == O_constant | |
9646 | && imm_expr.X_add_number > -0x8000 | |
9647 | && imm_expr.X_add_number < 0) | |
9648 | { | |
9649 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9650 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9651 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9652 | } |
dd3cbb7e NC |
9653 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9654 | { | |
9655 | used_at = 1; | |
9656 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9657 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9658 | break; | |
9659 | } | |
252b5132 RH |
9660 | else |
9661 | { | |
67c0d1eb RS |
9662 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9663 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9664 | used_at = 1; |
9665 | } | |
67c0d1eb | 9666 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9667 | break; |
252b5132 | 9668 | |
df58fc94 RS |
9669 | case M_SUB_I: |
9670 | s = "addi"; | |
9671 | s2 = "sub"; | |
9672 | goto do_subi; | |
9673 | case M_SUBU_I: | |
9674 | s = "addiu"; | |
9675 | s2 = "subu"; | |
9676 | goto do_subi; | |
252b5132 RH |
9677 | case M_DSUB_I: |
9678 | dbl = 1; | |
df58fc94 RS |
9679 | s = "daddi"; |
9680 | s2 = "dsub"; | |
9681 | if (!mips_opts.micromips) | |
9682 | goto do_subi; | |
252b5132 | 9683 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9684 | && imm_expr.X_add_number > -0x200 |
9685 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9686 | { |
df58fc94 | 9687 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9688 | break; |
252b5132 | 9689 | } |
df58fc94 | 9690 | goto do_subi_i; |
252b5132 RH |
9691 | case M_DSUBU_I: |
9692 | dbl = 1; | |
df58fc94 RS |
9693 | s = "daddiu"; |
9694 | s2 = "dsubu"; | |
9695 | do_subi: | |
252b5132 RH |
9696 | if (imm_expr.X_op == O_constant |
9697 | && imm_expr.X_add_number > -0x8000 | |
9698 | && imm_expr.X_add_number <= 0x8000) | |
9699 | { | |
9700 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9701 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9702 | break; |
252b5132 | 9703 | } |
df58fc94 | 9704 | do_subi_i: |
8fc2e39e | 9705 | used_at = 1; |
67c0d1eb | 9706 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9707 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9708 | break; |
9709 | ||
9710 | case M_TEQ_I: | |
9711 | s = "teq"; | |
9712 | goto trap; | |
9713 | case M_TGE_I: | |
9714 | s = "tge"; | |
9715 | goto trap; | |
9716 | case M_TGEU_I: | |
9717 | s = "tgeu"; | |
9718 | goto trap; | |
9719 | case M_TLT_I: | |
9720 | s = "tlt"; | |
9721 | goto trap; | |
9722 | case M_TLTU_I: | |
9723 | s = "tltu"; | |
9724 | goto trap; | |
9725 | case M_TNE_I: | |
9726 | s = "tne"; | |
9727 | trap: | |
8fc2e39e | 9728 | used_at = 1; |
67c0d1eb RS |
9729 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9730 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9731 | break; |
9732 | ||
252b5132 | 9733 | case M_TRUNCWS: |
43841e91 | 9734 | case M_TRUNCWD: |
df58fc94 | 9735 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9736 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9737 | used_at = 1; |
252b5132 RH |
9738 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9739 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9740 | ||
9741 | /* | |
9742 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9743 | * or is there a reason for it? | |
9744 | */ | |
7d10b47d | 9745 | start_noreorder (); |
67c0d1eb RS |
9746 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9747 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9748 | macro_build (NULL, "nop", ""); | |
252b5132 | 9749 | expr1.X_add_number = 3; |
67c0d1eb | 9750 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9751 | expr1.X_add_number = 2; |
67c0d1eb RS |
9752 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9753 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9754 | macro_build (NULL, "nop", ""); | |
9755 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9756 | dreg, sreg); | |
9757 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9758 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9759 | end_noreorder (); |
252b5132 RH |
9760 | break; |
9761 | ||
df58fc94 RS |
9762 | case M_ULH_A: |
9763 | ab = 1; | |
252b5132 RH |
9764 | case M_ULH: |
9765 | s = "lb"; | |
df58fc94 RS |
9766 | s2 = "lbu"; |
9767 | off = 1; | |
9768 | goto uld_st; | |
9769 | case M_ULHU_A: | |
9770 | ab = 1; | |
252b5132 RH |
9771 | case M_ULHU: |
9772 | s = "lbu"; | |
df58fc94 RS |
9773 | s2 = "lbu"; |
9774 | off = 1; | |
9775 | goto uld_st; | |
9776 | case M_ULW_A: | |
9777 | ab = 1; | |
9778 | case M_ULW: | |
9779 | s = "lwl"; | |
9780 | s2 = "lwr"; | |
9781 | off12 = mips_opts.micromips; | |
9782 | off = 3; | |
9783 | goto uld_st; | |
9784 | case M_ULD_A: | |
9785 | ab = 1; | |
252b5132 RH |
9786 | case M_ULD: |
9787 | s = "ldl"; | |
9788 | s2 = "ldr"; | |
df58fc94 | 9789 | off12 = mips_opts.micromips; |
252b5132 | 9790 | off = 7; |
df58fc94 RS |
9791 | goto uld_st; |
9792 | case M_USH_A: | |
9793 | ab = 1; | |
9794 | case M_USH: | |
9795 | s = "sb"; | |
9796 | s2 = "sb"; | |
9797 | off = 1; | |
9798 | ust = 1; | |
9799 | goto uld_st; | |
9800 | case M_USW_A: | |
9801 | ab = 1; | |
9802 | case M_USW: | |
9803 | s = "swl"; | |
9804 | s2 = "swr"; | |
9805 | off12 = mips_opts.micromips; | |
252b5132 | 9806 | off = 3; |
df58fc94 RS |
9807 | ust = 1; |
9808 | goto uld_st; | |
9809 | case M_USD_A: | |
9810 | ab = 1; | |
9811 | case M_USD: | |
9812 | s = "sdl"; | |
9813 | s2 = "sdr"; | |
9814 | off12 = mips_opts.micromips; | |
9815 | off = 7; | |
9816 | ust = 1; | |
9817 | ||
9818 | uld_st: | |
9819 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9820 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9821 | |
9822 | ep = &offset_expr; | |
9823 | expr1.X_add_number = 0; | |
9824 | if (ab) | |
9825 | { | |
9826 | used_at = 1; | |
9827 | tempreg = AT; | |
9828 | load_address (tempreg, ep, &used_at); | |
9829 | if (breg != 0) | |
9830 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9831 | tempreg, tempreg, breg); | |
9832 | breg = tempreg; | |
9833 | tempreg = treg; | |
9834 | ep = &expr1; | |
9835 | } | |
9836 | else if (off12 | |
9837 | && (offset_expr.X_op != O_constant | |
9838 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9839 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9840 | { | |
9841 | used_at = 1; | |
9842 | tempreg = AT; | |
9843 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9844 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9845 | breg = tempreg; | |
9846 | tempreg = treg; | |
9847 | ep = &expr1; | |
9848 | } | |
9849 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9850 | { |
9851 | used_at = 1; | |
9852 | tempreg = AT; | |
9853 | } | |
252b5132 | 9854 | else |
df58fc94 | 9855 | tempreg = treg; |
af22f5b2 | 9856 | |
df58fc94 RS |
9857 | if (off == 1) |
9858 | goto ulh_sh; | |
252b5132 | 9859 | |
90ecf173 | 9860 | if (!target_big_endian) |
df58fc94 RS |
9861 | ep->X_add_number += off; |
9862 | if (!off12) | |
9863 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9864 | else |
df58fc94 RS |
9865 | macro_build (NULL, s, "t,~(b)", |
9866 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9867 | ||
90ecf173 | 9868 | if (!target_big_endian) |
df58fc94 | 9869 | ep->X_add_number -= off; |
252b5132 | 9870 | else |
df58fc94 RS |
9871 | ep->X_add_number += off; |
9872 | if (!off12) | |
9873 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9874 | else | |
9875 | macro_build (NULL, s2, "t,~(b)", | |
9876 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9877 | |
df58fc94 RS |
9878 | /* If necessary, move the result in tempreg to the final destination. */ |
9879 | if (!ust && treg != tempreg) | |
9880 | { | |
9881 | /* Protect second load's delay slot. */ | |
9882 | load_delay_nop (); | |
9883 | move_register (treg, tempreg); | |
9884 | } | |
8fc2e39e | 9885 | break; |
252b5132 | 9886 | |
df58fc94 | 9887 | ulh_sh: |
d6bc6245 | 9888 | used_at = 1; |
df58fc94 RS |
9889 | if (target_big_endian == ust) |
9890 | ep->X_add_number += off; | |
9891 | tempreg = ust || ab ? treg : AT; | |
9892 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9893 | ||
9894 | /* For halfword transfers we need a temporary register to shuffle | |
9895 | bytes. Unfortunately for M_USH_A we have none available before | |
9896 | the next store as AT holds the base address. We deal with this | |
9897 | case by clobbering TREG and then restoring it as with ULH. */ | |
9898 | tempreg = ust == ab ? treg : AT; | |
9899 | if (ust) | |
9900 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9901 | ||
9902 | if (target_big_endian == ust) | |
9903 | ep->X_add_number -= off; | |
252b5132 | 9904 | else |
df58fc94 RS |
9905 | ep->X_add_number += off; |
9906 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9907 | |
df58fc94 RS |
9908 | /* For M_USH_A re-retrieve the LSB. */ |
9909 | if (ust && ab) | |
9910 | { | |
9911 | if (target_big_endian) | |
9912 | ep->X_add_number += off; | |
9913 | else | |
9914 | ep->X_add_number -= off; | |
9915 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9916 | } | |
9917 | /* For ULH and M_USH_A OR the LSB in. */ | |
9918 | if (!ust || ab) | |
9919 | { | |
9920 | tempreg = !ab ? AT : treg; | |
9921 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9922 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9923 | } | |
252b5132 RH |
9924 | break; |
9925 | ||
9926 | default: | |
9927 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9928 | are added dynamically. */ |
252b5132 RH |
9929 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9930 | break; | |
9931 | } | |
741fe287 | 9932 | if (!mips_opts.at && used_at) |
8fc2e39e | 9933 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9934 | } |
9935 | ||
9936 | /* Implement macros in mips16 mode. */ | |
9937 | ||
9938 | static void | |
17a2f251 | 9939 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9940 | { |
9941 | int mask; | |
9942 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9943 | expressionS expr1; |
9944 | int dbl; | |
9945 | const char *s, *s2, *s3; | |
9946 | ||
9947 | mask = ip->insn_mo->mask; | |
9948 | ||
bf12938e RS |
9949 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9950 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9951 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9952 | |
252b5132 RH |
9953 | expr1.X_op = O_constant; |
9954 | expr1.X_op_symbol = NULL; | |
9955 | expr1.X_add_symbol = NULL; | |
9956 | expr1.X_add_number = 1; | |
9957 | ||
9958 | dbl = 0; | |
9959 | ||
9960 | switch (mask) | |
9961 | { | |
9962 | default: | |
9963 | internalError (); | |
9964 | ||
9965 | case M_DDIV_3: | |
9966 | dbl = 1; | |
9967 | case M_DIV_3: | |
9968 | s = "mflo"; | |
9969 | goto do_div3; | |
9970 | case M_DREM_3: | |
9971 | dbl = 1; | |
9972 | case M_REM_3: | |
9973 | s = "mfhi"; | |
9974 | do_div3: | |
7d10b47d | 9975 | start_noreorder (); |
67c0d1eb | 9976 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 9977 | expr1.X_add_number = 2; |
67c0d1eb RS |
9978 | macro_build (&expr1, "bnez", "x,p", yreg); |
9979 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 9980 | |
252b5132 RH |
9981 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
9982 | since that causes an overflow. We should do that as well, | |
9983 | but I don't see how to do the comparisons without a temporary | |
9984 | register. */ | |
7d10b47d | 9985 | end_noreorder (); |
67c0d1eb | 9986 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
9987 | break; |
9988 | ||
9989 | case M_DIVU_3: | |
9990 | s = "divu"; | |
9991 | s2 = "mflo"; | |
9992 | goto do_divu3; | |
9993 | case M_REMU_3: | |
9994 | s = "divu"; | |
9995 | s2 = "mfhi"; | |
9996 | goto do_divu3; | |
9997 | case M_DDIVU_3: | |
9998 | s = "ddivu"; | |
9999 | s2 = "mflo"; | |
10000 | goto do_divu3; | |
10001 | case M_DREMU_3: | |
10002 | s = "ddivu"; | |
10003 | s2 = "mfhi"; | |
10004 | do_divu3: | |
7d10b47d | 10005 | start_noreorder (); |
67c0d1eb | 10006 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10007 | expr1.X_add_number = 2; |
67c0d1eb RS |
10008 | macro_build (&expr1, "bnez", "x,p", yreg); |
10009 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10010 | end_noreorder (); |
67c0d1eb | 10011 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10012 | break; |
10013 | ||
10014 | case M_DMUL: | |
10015 | dbl = 1; | |
10016 | case M_MUL: | |
67c0d1eb RS |
10017 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10018 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10019 | break; |
252b5132 RH |
10020 | |
10021 | case M_DSUBU_I: | |
10022 | dbl = 1; | |
10023 | goto do_subu; | |
10024 | case M_SUBU_I: | |
10025 | do_subu: | |
10026 | if (imm_expr.X_op != O_constant) | |
10027 | as_bad (_("Unsupported large constant")); | |
10028 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10029 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10030 | break; |
10031 | ||
10032 | case M_SUBU_I_2: | |
10033 | if (imm_expr.X_op != O_constant) | |
10034 | as_bad (_("Unsupported large constant")); | |
10035 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10036 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10037 | break; |
10038 | ||
10039 | case M_DSUBU_I_2: | |
10040 | if (imm_expr.X_op != O_constant) | |
10041 | as_bad (_("Unsupported large constant")); | |
10042 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10043 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10044 | break; |
10045 | ||
10046 | case M_BEQ: | |
10047 | s = "cmp"; | |
10048 | s2 = "bteqz"; | |
10049 | goto do_branch; | |
10050 | case M_BNE: | |
10051 | s = "cmp"; | |
10052 | s2 = "btnez"; | |
10053 | goto do_branch; | |
10054 | case M_BLT: | |
10055 | s = "slt"; | |
10056 | s2 = "btnez"; | |
10057 | goto do_branch; | |
10058 | case M_BLTU: | |
10059 | s = "sltu"; | |
10060 | s2 = "btnez"; | |
10061 | goto do_branch; | |
10062 | case M_BLE: | |
10063 | s = "slt"; | |
10064 | s2 = "bteqz"; | |
10065 | goto do_reverse_branch; | |
10066 | case M_BLEU: | |
10067 | s = "sltu"; | |
10068 | s2 = "bteqz"; | |
10069 | goto do_reverse_branch; | |
10070 | case M_BGE: | |
10071 | s = "slt"; | |
10072 | s2 = "bteqz"; | |
10073 | goto do_branch; | |
10074 | case M_BGEU: | |
10075 | s = "sltu"; | |
10076 | s2 = "bteqz"; | |
10077 | goto do_branch; | |
10078 | case M_BGT: | |
10079 | s = "slt"; | |
10080 | s2 = "btnez"; | |
10081 | goto do_reverse_branch; | |
10082 | case M_BGTU: | |
10083 | s = "sltu"; | |
10084 | s2 = "btnez"; | |
10085 | ||
10086 | do_reverse_branch: | |
10087 | tmp = xreg; | |
10088 | xreg = yreg; | |
10089 | yreg = tmp; | |
10090 | ||
10091 | do_branch: | |
67c0d1eb RS |
10092 | macro_build (NULL, s, "x,y", xreg, yreg); |
10093 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10094 | break; |
10095 | ||
10096 | case M_BEQ_I: | |
10097 | s = "cmpi"; | |
10098 | s2 = "bteqz"; | |
10099 | s3 = "x,U"; | |
10100 | goto do_branch_i; | |
10101 | case M_BNE_I: | |
10102 | s = "cmpi"; | |
10103 | s2 = "btnez"; | |
10104 | s3 = "x,U"; | |
10105 | goto do_branch_i; | |
10106 | case M_BLT_I: | |
10107 | s = "slti"; | |
10108 | s2 = "btnez"; | |
10109 | s3 = "x,8"; | |
10110 | goto do_branch_i; | |
10111 | case M_BLTU_I: | |
10112 | s = "sltiu"; | |
10113 | s2 = "btnez"; | |
10114 | s3 = "x,8"; | |
10115 | goto do_branch_i; | |
10116 | case M_BLE_I: | |
10117 | s = "slti"; | |
10118 | s2 = "btnez"; | |
10119 | s3 = "x,8"; | |
10120 | goto do_addone_branch_i; | |
10121 | case M_BLEU_I: | |
10122 | s = "sltiu"; | |
10123 | s2 = "btnez"; | |
10124 | s3 = "x,8"; | |
10125 | goto do_addone_branch_i; | |
10126 | case M_BGE_I: | |
10127 | s = "slti"; | |
10128 | s2 = "bteqz"; | |
10129 | s3 = "x,8"; | |
10130 | goto do_branch_i; | |
10131 | case M_BGEU_I: | |
10132 | s = "sltiu"; | |
10133 | s2 = "bteqz"; | |
10134 | s3 = "x,8"; | |
10135 | goto do_branch_i; | |
10136 | case M_BGT_I: | |
10137 | s = "slti"; | |
10138 | s2 = "bteqz"; | |
10139 | s3 = "x,8"; | |
10140 | goto do_addone_branch_i; | |
10141 | case M_BGTU_I: | |
10142 | s = "sltiu"; | |
10143 | s2 = "bteqz"; | |
10144 | s3 = "x,8"; | |
10145 | ||
10146 | do_addone_branch_i: | |
10147 | if (imm_expr.X_op != O_constant) | |
10148 | as_bad (_("Unsupported large constant")); | |
10149 | ++imm_expr.X_add_number; | |
10150 | ||
10151 | do_branch_i: | |
67c0d1eb RS |
10152 | macro_build (&imm_expr, s, s3, xreg); |
10153 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10154 | break; |
10155 | ||
10156 | case M_ABS: | |
10157 | expr1.X_add_number = 0; | |
67c0d1eb | 10158 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10159 | if (xreg != yreg) |
67c0d1eb | 10160 | move_register (xreg, yreg); |
252b5132 | 10161 | expr1.X_add_number = 2; |
67c0d1eb RS |
10162 | macro_build (&expr1, "bteqz", "p"); |
10163 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10164 | } |
10165 | } | |
10166 | ||
10167 | /* For consistency checking, verify that all bits are specified either | |
10168 | by the match/mask part of the instruction definition, or by the | |
10169 | operand list. */ | |
10170 | static int | |
17a2f251 | 10171 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10172 | { |
10173 | const char *p = opc->args; | |
10174 | char c; | |
10175 | unsigned long used_bits = opc->mask; | |
10176 | ||
10177 | if ((used_bits & opc->match) != opc->match) | |
10178 | { | |
10179 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10180 | opc->name, opc->args); | |
10181 | return 0; | |
10182 | } | |
10183 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10184 | while (*p) | |
10185 | switch (c = *p++) | |
10186 | { | |
10187 | case ',': break; | |
10188 | case '(': break; | |
10189 | case ')': break; | |
af7ee8bf CD |
10190 | case '+': |
10191 | switch (c = *p++) | |
10192 | { | |
9bcd4f99 TS |
10193 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10194 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10195 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10196 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10197 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10198 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10199 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10200 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10201 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10202 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10203 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10204 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10205 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10206 | case 'I': break; | |
ef2e4d86 CF |
10207 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10208 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10209 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10210 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10211 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10212 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10213 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10214 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10215 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10216 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10217 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10218 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10219 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10220 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10221 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10222 | |
af7ee8bf CD |
10223 | default: |
10224 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10225 | c, opc->name, opc->args); | |
10226 | return 0; | |
10227 | } | |
10228 | break; | |
252b5132 RH |
10229 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10230 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10231 | case 'A': break; | |
4372b673 | 10232 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10233 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10234 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10235 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10236 | case 'F': break; | |
10237 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10238 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10239 | case 'I': break; |
e972090a | 10240 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10241 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10242 | case 'L': break; |
10243 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10244 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10245 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10246 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10247 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10248 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10249 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10250 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10251 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10252 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10253 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10254 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10255 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10256 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10257 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10258 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10259 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10260 | case 'f': break; | |
10261 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10262 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10263 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10264 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10265 | case 'l': break; | |
10266 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10267 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10268 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10269 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10270 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10271 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10272 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10273 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10274 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10275 | case 'x': break; | |
10276 | case 'z': break; | |
10277 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10278 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10279 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10280 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10281 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10282 | case '[': break; | |
10283 | case ']': break; | |
620edafd | 10284 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10285 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10286 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10287 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10288 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10289 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10290 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10291 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10292 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10293 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10294 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10295 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10296 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10297 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10298 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10299 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10300 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10301 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10302 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10303 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10304 | default: |
10305 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10306 | c, opc->name, opc->args); | |
10307 | return 0; | |
10308 | } | |
10309 | #undef USE_BITS | |
10310 | if (used_bits != 0xffffffff) | |
10311 | { | |
10312 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10313 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10314 | return 0; | |
10315 | } | |
10316 | return 1; | |
10317 | } | |
10318 | ||
df58fc94 RS |
10319 | /* For consistency checking, verify that the length implied matches the |
10320 | major opcode and that all bits are specified either by the match/mask | |
10321 | part of the instruction definition, or by the operand list. */ | |
10322 | ||
10323 | static int | |
10324 | validate_micromips_insn (const struct mips_opcode *opc) | |
10325 | { | |
10326 | unsigned long match = opc->match; | |
10327 | unsigned long mask = opc->mask; | |
10328 | const char *p = opc->args; | |
10329 | unsigned long insn_bits; | |
10330 | unsigned long used_bits; | |
10331 | unsigned long major; | |
10332 | unsigned int length; | |
10333 | char e; | |
10334 | char c; | |
10335 | ||
10336 | if ((mask & match) != match) | |
10337 | { | |
10338 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10339 | opc->name, opc->args); | |
10340 | return 0; | |
10341 | } | |
10342 | length = micromips_insn_length (opc); | |
10343 | if (length != 2 && length != 4) | |
10344 | { | |
10345 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10346 | "%s %s"), length, opc->name, opc->args); | |
10347 | return 0; | |
10348 | } | |
10349 | major = match >> (10 + 8 * (length - 2)); | |
10350 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10351 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10352 | { | |
10353 | as_bad (_("Internal error: bad microMIPS opcode " | |
10354 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10355 | return 0; | |
10356 | } | |
10357 | ||
10358 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10359 | insn_bits = 1 << 4 * length; | |
10360 | insn_bits <<= 4 * length; | |
10361 | insn_bits -= 1; | |
10362 | used_bits = mask; | |
10363 | #define USE_BITS(field) \ | |
10364 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10365 | while (*p) | |
10366 | switch (c = *p++) | |
10367 | { | |
10368 | case ',': break; | |
10369 | case '(': break; | |
10370 | case ')': break; | |
10371 | case '+': | |
10372 | e = c; | |
10373 | switch (c = *p++) | |
10374 | { | |
10375 | case 'A': USE_BITS (EXTLSB); break; | |
10376 | case 'B': USE_BITS (INSMSB); break; | |
10377 | case 'C': USE_BITS (EXTMSBD); break; | |
10378 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10379 | case 'E': USE_BITS (EXTLSB); break; | |
10380 | case 'F': USE_BITS (INSMSB); break; | |
10381 | case 'G': USE_BITS (EXTMSBD); break; | |
10382 | case 'H': USE_BITS (EXTMSBD); break; | |
10383 | default: | |
10384 | as_bad (_("Internal error: bad mips opcode " | |
10385 | "(unknown extension operand type `%c%c'): %s %s"), | |
10386 | e, c, opc->name, opc->args); | |
10387 | return 0; | |
10388 | } | |
10389 | break; | |
10390 | case 'm': | |
10391 | e = c; | |
10392 | switch (c = *p++) | |
10393 | { | |
10394 | case 'A': USE_BITS (IMMA); break; | |
10395 | case 'B': USE_BITS (IMMB); break; | |
10396 | case 'C': USE_BITS (IMMC); break; | |
10397 | case 'D': USE_BITS (IMMD); break; | |
10398 | case 'E': USE_BITS (IMME); break; | |
10399 | case 'F': USE_BITS (IMMF); break; | |
10400 | case 'G': USE_BITS (IMMG); break; | |
10401 | case 'H': USE_BITS (IMMH); break; | |
10402 | case 'I': USE_BITS (IMMI); break; | |
10403 | case 'J': USE_BITS (IMMJ); break; | |
10404 | case 'L': USE_BITS (IMML); break; | |
10405 | case 'M': USE_BITS (IMMM); break; | |
10406 | case 'N': USE_BITS (IMMN); break; | |
10407 | case 'O': USE_BITS (IMMO); break; | |
10408 | case 'P': USE_BITS (IMMP); break; | |
10409 | case 'Q': USE_BITS (IMMQ); break; | |
10410 | case 'U': USE_BITS (IMMU); break; | |
10411 | case 'W': USE_BITS (IMMW); break; | |
10412 | case 'X': USE_BITS (IMMX); break; | |
10413 | case 'Y': USE_BITS (IMMY); break; | |
10414 | case 'Z': break; | |
10415 | case 'a': break; | |
10416 | case 'b': USE_BITS (MB); break; | |
10417 | case 'c': USE_BITS (MC); break; | |
10418 | case 'd': USE_BITS (MD); break; | |
10419 | case 'e': USE_BITS (ME); break; | |
10420 | case 'f': USE_BITS (MF); break; | |
10421 | case 'g': USE_BITS (MG); break; | |
10422 | case 'h': USE_BITS (MH); break; | |
10423 | case 'i': USE_BITS (MI); break; | |
10424 | case 'j': USE_BITS (MJ); break; | |
10425 | case 'l': USE_BITS (ML); break; | |
10426 | case 'm': USE_BITS (MM); break; | |
10427 | case 'n': USE_BITS (MN); break; | |
10428 | case 'p': USE_BITS (MP); break; | |
10429 | case 'q': USE_BITS (MQ); break; | |
10430 | case 'r': break; | |
10431 | case 's': break; | |
10432 | case 't': break; | |
10433 | case 'x': break; | |
10434 | case 'y': break; | |
10435 | case 'z': break; | |
10436 | default: | |
10437 | as_bad (_("Internal error: bad mips opcode " | |
10438 | "(unknown extension operand type `%c%c'): %s %s"), | |
10439 | e, c, opc->name, opc->args); | |
10440 | return 0; | |
10441 | } | |
10442 | break; | |
10443 | case '.': USE_BITS (OFFSET10); break; | |
10444 | case '1': USE_BITS (STYPE); break; | |
10445 | case '<': USE_BITS (SHAMT); break; | |
10446 | case '>': USE_BITS (SHAMT); break; | |
10447 | case 'B': USE_BITS (CODE10); break; | |
10448 | case 'C': USE_BITS (COPZ); break; | |
10449 | case 'D': USE_BITS (FD); break; | |
10450 | case 'E': USE_BITS (RT); break; | |
10451 | case 'G': USE_BITS (RS); break; | |
10452 | case 'H': USE_BITS (SEL); break; | |
10453 | case 'K': USE_BITS (RS); break; | |
10454 | case 'M': USE_BITS (CCC); break; | |
10455 | case 'N': USE_BITS (BCC); break; | |
10456 | case 'R': USE_BITS (FR); break; | |
10457 | case 'S': USE_BITS (FS); break; | |
10458 | case 'T': USE_BITS (FT); break; | |
10459 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10460 | case '\\': USE_BITS (3BITPOS); break; |
df58fc94 RS |
10461 | case 'a': USE_BITS (TARGET); break; |
10462 | case 'b': USE_BITS (RS); break; | |
10463 | case 'c': USE_BITS (CODE); break; | |
10464 | case 'd': USE_BITS (RD); break; | |
10465 | case 'h': USE_BITS (PREFX); break; | |
10466 | case 'i': USE_BITS (IMMEDIATE); break; | |
10467 | case 'j': USE_BITS (DELTA); break; | |
10468 | case 'k': USE_BITS (CACHE); break; | |
10469 | case 'n': USE_BITS (RT); break; | |
10470 | case 'o': USE_BITS (DELTA); break; | |
10471 | case 'p': USE_BITS (DELTA); break; | |
10472 | case 'q': USE_BITS (CODE2); break; | |
10473 | case 'r': USE_BITS (RS); break; | |
10474 | case 's': USE_BITS (RS); break; | |
10475 | case 't': USE_BITS (RT); break; | |
10476 | case 'u': USE_BITS (IMMEDIATE); break; | |
10477 | case 'v': USE_BITS (RS); break; | |
10478 | case 'w': USE_BITS (RT); break; | |
10479 | case 'y': USE_BITS (RS3); break; | |
10480 | case 'z': break; | |
10481 | case '|': USE_BITS (TRAP); break; | |
10482 | case '~': USE_BITS (OFFSET12); break; | |
10483 | default: | |
10484 | as_bad (_("Internal error: bad microMIPS opcode " | |
10485 | "(unknown operand type `%c'): %s %s"), | |
10486 | c, opc->name, opc->args); | |
10487 | return 0; | |
10488 | } | |
10489 | #undef USE_BITS | |
10490 | if (used_bits != insn_bits) | |
10491 | { | |
10492 | if (~used_bits & insn_bits) | |
10493 | as_bad (_("Internal error: bad microMIPS opcode " | |
10494 | "(bits 0x%lx undefined): %s %s"), | |
10495 | ~used_bits & insn_bits, opc->name, opc->args); | |
10496 | if (used_bits & ~insn_bits) | |
10497 | as_bad (_("Internal error: bad microMIPS opcode " | |
10498 | "(bits 0x%lx defined): %s %s"), | |
10499 | used_bits & ~insn_bits, opc->name, opc->args); | |
10500 | return 0; | |
10501 | } | |
10502 | return 1; | |
10503 | } | |
10504 | ||
9bcd4f99 TS |
10505 | /* UDI immediates. */ |
10506 | struct mips_immed { | |
10507 | char type; | |
10508 | unsigned int shift; | |
10509 | unsigned long mask; | |
10510 | const char * desc; | |
10511 | }; | |
10512 | ||
10513 | static const struct mips_immed mips_immed[] = { | |
10514 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10515 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10516 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10517 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10518 | { 0,0,0,0 } | |
10519 | }; | |
10520 | ||
7455baf8 TS |
10521 | /* Check whether an odd floating-point register is allowed. */ |
10522 | static int | |
10523 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10524 | { | |
10525 | const char *s = insn->name; | |
10526 | ||
10527 | if (insn->pinfo == INSN_MACRO) | |
10528 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10529 | return 1; | |
10530 | ||
10531 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10532 | { | |
10533 | /* Allow odd registers for single-precision ops. */ | |
10534 | switch (insn->pinfo & (FP_S | FP_D)) | |
10535 | { | |
10536 | case FP_S: | |
10537 | case 0: | |
10538 | return 1; /* both single precision - ok */ | |
10539 | case FP_D: | |
10540 | return 0; /* both double precision - fail */ | |
10541 | default: | |
10542 | break; | |
10543 | } | |
10544 | ||
10545 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10546 | s = strchr (insn->name, '.'); | |
10547 | if (argnum == 2) | |
10548 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10549 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10550 | } | |
10551 | ||
10552 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10553 | if ((insn->pinfo & FP_S) | |
10554 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10555 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10556 | return 1; | |
10557 | ||
10558 | return 0; | |
10559 | } | |
10560 | ||
df58fc94 RS |
10561 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10562 | taking bits from BIT up. */ | |
10563 | static int | |
10564 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10565 | { | |
10566 | return (ep->X_op == O_constant | |
10567 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10568 | && ep->X_add_number >= min << bit | |
10569 | && ep->X_add_number < max << bit); | |
10570 | } | |
10571 | ||
252b5132 RH |
10572 | /* This routine assembles an instruction into its binary format. As a |
10573 | side effect, it sets one of the global variables imm_reloc or | |
10574 | offset_reloc to the type of relocation to do if one of the operands | |
10575 | is an address expression. */ | |
10576 | ||
10577 | static void | |
17a2f251 | 10578 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10579 | { |
df58fc94 RS |
10580 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10581 | bfd_boolean need_delay_slot_ok = TRUE; | |
10582 | struct mips_opcode *firstinsn = NULL; | |
10583 | const struct mips_opcode *past; | |
10584 | struct hash_control *hash; | |
252b5132 RH |
10585 | char *s; |
10586 | const char *args; | |
43841e91 | 10587 | char c = 0; |
252b5132 RH |
10588 | struct mips_opcode *insn; |
10589 | char *argsStart; | |
10590 | unsigned int regno; | |
34224acf | 10591 | unsigned int lastregno; |
df58fc94 | 10592 | unsigned int destregno = 0; |
af7ee8bf | 10593 | unsigned int lastpos = 0; |
071742cf | 10594 | unsigned int limlo, limhi; |
252b5132 | 10595 | char *s_reset; |
74cd071d | 10596 | offsetT min_range, max_range; |
df58fc94 | 10597 | long opend; |
a40bc9dd | 10598 | char *name; |
707bfff6 TS |
10599 | int argnum; |
10600 | unsigned int rtype; | |
df58fc94 | 10601 | char *dot; |
a40bc9dd | 10602 | long end; |
252b5132 RH |
10603 | |
10604 | insn_error = NULL; | |
10605 | ||
df58fc94 RS |
10606 | if (mips_opts.micromips) |
10607 | { | |
10608 | hash = micromips_op_hash; | |
10609 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10610 | } | |
10611 | else | |
10612 | { | |
10613 | hash = op_hash; | |
10614 | past = &mips_opcodes[NUMOPCODES]; | |
10615 | } | |
10616 | forced_insn_length = 0; | |
252b5132 | 10617 | insn = NULL; |
252b5132 | 10618 | |
df58fc94 | 10619 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10620 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10621 | continue; | |
bdaaa2e1 | 10622 | |
a40bc9dd RS |
10623 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10624 | name = alloca (end + 1); | |
10625 | memcpy (name, str, end); | |
10626 | name[end] = '\0'; | |
252b5132 | 10627 | |
df58fc94 RS |
10628 | for (;;) |
10629 | { | |
10630 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10631 | ||
10632 | if (insn != NULL || !mips_opts.micromips) | |
10633 | break; | |
10634 | if (forced_insn_length) | |
10635 | break; | |
10636 | ||
10637 | /* See if there's an instruction size override suffix, | |
10638 | either `16' or `32', at the end of the mnemonic proper, | |
10639 | that defines the operation, i.e. before the first `.' | |
10640 | character if any. Strip it and retry. */ | |
10641 | dot = strchr (name, '.'); | |
10642 | opend = dot != NULL ? dot - name : end; | |
10643 | if (opend < 3) | |
10644 | break; | |
10645 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10646 | forced_insn_length = 2; | |
10647 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10648 | forced_insn_length = 4; | |
10649 | else | |
10650 | break; | |
10651 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10652 | } | |
252b5132 RH |
10653 | if (insn == NULL) |
10654 | { | |
a40bc9dd RS |
10655 | insn_error = _("Unrecognized opcode"); |
10656 | return; | |
252b5132 RH |
10657 | } |
10658 | ||
df58fc94 RS |
10659 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10660 | we make up to two passes over the relevant fragment of the opcode | |
10661 | table. First we try instructions that meet the delay slot's length | |
10662 | requirement. If none matched, then we retry with the remaining ones | |
10663 | and if one matches, then we use it and then issue an appropriate | |
10664 | warning later on. */ | |
a40bc9dd | 10665 | argsStart = s = str + end; |
252b5132 RH |
10666 | for (;;) |
10667 | { | |
df58fc94 RS |
10668 | bfd_boolean delay_slot_ok; |
10669 | bfd_boolean size_ok; | |
b34976b6 | 10670 | bfd_boolean ok; |
252b5132 | 10671 | |
a40bc9dd | 10672 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10673 | |
f79e2745 | 10674 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10675 | size_ok = is_size_valid (insn); |
10676 | delay_slot_ok = is_delay_slot_valid (insn); | |
10677 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10678 | { |
df58fc94 RS |
10679 | firstinsn = insn; |
10680 | wrong_delay_slot_insns = TRUE; | |
10681 | } | |
10682 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10683 | { | |
10684 | static char buf[256]; | |
10685 | ||
10686 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10687 | { |
10688 | ++insn; | |
10689 | continue; | |
10690 | } | |
df58fc94 | 10691 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10692 | { |
df58fc94 RS |
10693 | gas_assert (firstinsn); |
10694 | need_delay_slot_ok = FALSE; | |
10695 | past = insn + 1; | |
10696 | insn = firstinsn; | |
10697 | continue; | |
252b5132 | 10698 | } |
df58fc94 RS |
10699 | |
10700 | if (insn_error) | |
10701 | return; | |
10702 | ||
10703 | if (!ok) | |
10704 | sprintf (buf, _("opcode not supported on this processor: %s (%s)"), | |
10705 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10706 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10707 | else | |
10708 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10709 | 8 * forced_insn_length); | |
10710 | insn_error = buf; | |
10711 | ||
10712 | return; | |
252b5132 RH |
10713 | } |
10714 | ||
1e915849 | 10715 | create_insn (ip, insn); |
268f6bed | 10716 | insn_error = NULL; |
707bfff6 | 10717 | argnum = 1; |
24864476 | 10718 | lastregno = 0xffffffff; |
252b5132 RH |
10719 | for (args = insn->args;; ++args) |
10720 | { | |
deec1734 CD |
10721 | int is_mdmx; |
10722 | ||
ad8d3bb3 | 10723 | s += strspn (s, " \t"); |
deec1734 | 10724 | is_mdmx = 0; |
252b5132 RH |
10725 | switch (*args) |
10726 | { | |
10727 | case '\0': /* end of args */ | |
10728 | if (*s == '\0') | |
10729 | return; | |
10730 | break; | |
10731 | ||
90ecf173 | 10732 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
df58fc94 | 10733 | gas_assert (!mips_opts.micromips); |
8b082fb1 TS |
10734 | my_getExpression (&imm_expr, s); |
10735 | check_absolute_expr (ip, &imm_expr); | |
10736 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10737 | && (unsigned long) imm_expr.X_add_number != 3) | |
10738 | { | |
10739 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10740 | (unsigned long) imm_expr.X_add_number); | |
10741 | } | |
df58fc94 | 10742 | INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); |
8b082fb1 TS |
10743 | imm_expr.X_op = O_absent; |
10744 | s = expr_end; | |
10745 | continue; | |
10746 | ||
90ecf173 | 10747 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
df58fc94 | 10748 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10749 | my_getExpression (&imm_expr, s); |
10750 | check_absolute_expr (ip, &imm_expr); | |
10751 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
10752 | { | |
a9e24354 TS |
10753 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10754 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10755 | } |
df58fc94 | 10756 | INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
10757 | imm_expr.X_op = O_absent; |
10758 | s = expr_end; | |
10759 | continue; | |
10760 | ||
90ecf173 | 10761 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
df58fc94 | 10762 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10763 | my_getExpression (&imm_expr, s); |
10764 | check_absolute_expr (ip, &imm_expr); | |
10765 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
10766 | { | |
a9e24354 TS |
10767 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10768 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10769 | } |
df58fc94 | 10770 | INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
10771 | imm_expr.X_op = O_absent; |
10772 | s = expr_end; | |
10773 | continue; | |
10774 | ||
90ecf173 | 10775 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
df58fc94 | 10776 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10777 | my_getExpression (&imm_expr, s); |
10778 | check_absolute_expr (ip, &imm_expr); | |
10779 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
10780 | { | |
a9e24354 TS |
10781 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10782 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10783 | } |
df58fc94 | 10784 | INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
10785 | imm_expr.X_op = O_absent; |
10786 | s = expr_end; | |
10787 | continue; | |
10788 | ||
90ecf173 | 10789 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
df58fc94 | 10790 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10791 | my_getExpression (&imm_expr, s); |
10792 | check_absolute_expr (ip, &imm_expr); | |
10793 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
10794 | { | |
a9e24354 TS |
10795 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10796 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10797 | } |
df58fc94 | 10798 | INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
10799 | imm_expr.X_op = O_absent; |
10800 | s = expr_end; | |
10801 | continue; | |
10802 | ||
90ecf173 | 10803 | case '7': /* Four DSP accumulators in bits 11,12. */ |
df58fc94 | 10804 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10805 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10806 | s[3] >= '0' && s[3] <= '3') | |
10807 | { | |
10808 | regno = s[3] - '0'; | |
10809 | s += 4; | |
df58fc94 | 10810 | INSERT_OPERAND (0, DSPACC, *ip, regno); |
74cd071d CF |
10811 | continue; |
10812 | } | |
10813 | else | |
10814 | as_bad (_("Invalid dsp acc register")); | |
10815 | break; | |
10816 | ||
90ecf173 | 10817 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
df58fc94 | 10818 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10819 | my_getExpression (&imm_expr, s); |
10820 | check_absolute_expr (ip, &imm_expr); | |
10821 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
10822 | { | |
a9e24354 TS |
10823 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10824 | OP_MASK_WRDSP, | |
10825 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10826 | } |
df58fc94 | 10827 | INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10828 | imm_expr.X_op = O_absent; |
10829 | s = expr_end; | |
10830 | continue; | |
10831 | ||
90ecf173 | 10832 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10833 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10834 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10835 | s[3] >= '0' && s[3] <= '3') | |
10836 | { | |
10837 | regno = s[3] - '0'; | |
10838 | s += 4; | |
df58fc94 | 10839 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10840 | continue; |
10841 | } | |
10842 | else | |
10843 | as_bad (_("Invalid dsp acc register")); | |
10844 | break; | |
10845 | ||
90ecf173 | 10846 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
df58fc94 | 10847 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10848 | my_getExpression (&imm_expr, s); |
10849 | check_absolute_expr (ip, &imm_expr); | |
10850 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
10851 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
10852 | if (imm_expr.X_add_number < min_range || | |
10853 | imm_expr.X_add_number > max_range) | |
10854 | { | |
a9e24354 TS |
10855 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10856 | (long) min_range, (long) max_range, | |
10857 | (long) imm_expr.X_add_number); | |
74cd071d | 10858 | } |
df58fc94 | 10859 | INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
10860 | imm_expr.X_op = O_absent; |
10861 | s = expr_end; | |
10862 | continue; | |
10863 | ||
90ecf173 | 10864 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10865 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10866 | my_getExpression (&imm_expr, s); |
10867 | check_absolute_expr (ip, &imm_expr); | |
10868 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10869 | { | |
a9e24354 TS |
10870 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10871 | OP_MASK_RDDSP, | |
10872 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10873 | } |
df58fc94 | 10874 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10875 | imm_expr.X_op = O_absent; |
10876 | s = expr_end; | |
10877 | continue; | |
10878 | ||
90ecf173 | 10879 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10880 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10881 | my_getExpression (&imm_expr, s); |
10882 | check_absolute_expr (ip, &imm_expr); | |
10883 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10884 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10885 | if (imm_expr.X_add_number < min_range || | |
10886 | imm_expr.X_add_number > max_range) | |
10887 | { | |
a9e24354 TS |
10888 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10889 | (long) min_range, (long) max_range, | |
10890 | (long) imm_expr.X_add_number); | |
74cd071d | 10891 | } |
df58fc94 | 10892 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10893 | imm_expr.X_op = O_absent; |
10894 | s = expr_end; | |
10895 | continue; | |
10896 | ||
90ecf173 | 10897 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
df58fc94 | 10898 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10899 | my_getExpression (&imm_expr, s); |
10900 | check_absolute_expr (ip, &imm_expr); | |
10901 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
10902 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
10903 | if (imm_expr.X_add_number < min_range || | |
10904 | imm_expr.X_add_number > max_range) | |
10905 | { | |
a9e24354 TS |
10906 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10907 | (long) min_range, (long) max_range, | |
10908 | (long) imm_expr.X_add_number); | |
74cd071d | 10909 | } |
df58fc94 | 10910 | INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
10911 | imm_expr.X_op = O_absent; |
10912 | s = expr_end; | |
10913 | continue; | |
10914 | ||
a9e24354 | 10915 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 10916 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10917 | my_getExpression (&imm_expr, s); |
10918 | check_absolute_expr (ip, &imm_expr); | |
10919 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
10920 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
10921 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10922 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10923 | imm_expr.X_op = O_absent; |
10924 | s = expr_end; | |
10925 | continue; | |
10926 | ||
a9e24354 | 10927 | case '$': /* MT load high flag bit. */ |
df58fc94 | 10928 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10929 | my_getExpression (&imm_expr, s); |
10930 | check_absolute_expr (ip, &imm_expr); | |
10931 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
10932 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
10933 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10934 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10935 | imm_expr.X_op = O_absent; |
10936 | s = expr_end; | |
10937 | continue; | |
10938 | ||
90ecf173 | 10939 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 10940 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10941 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10942 | s[3] >= '0' && s[3] <= '3') | |
10943 | { | |
10944 | regno = s[3] - '0'; | |
10945 | s += 4; | |
df58fc94 | 10946 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
10947 | continue; |
10948 | } | |
10949 | else | |
10950 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10951 | break; | |
10952 | ||
90ecf173 | 10953 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 10954 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10955 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10956 | s[3] >= '0' && s[3] <= '3') | |
10957 | { | |
10958 | regno = s[3] - '0'; | |
10959 | s += 4; | |
df58fc94 | 10960 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
10961 | continue; |
10962 | } | |
10963 | else | |
10964 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10965 | break; | |
10966 | ||
dec0624d MR |
10967 | case '\\': /* 3-bit bit position. */ |
10968 | { | |
10969 | unsigned long mask = (!mips_opts.micromips | |
10970 | ? OP_MASK_3BITPOS | |
10971 | : MICROMIPSOP_MASK_3BITPOS); | |
10972 | ||
10973 | my_getExpression (&imm_expr, s); | |
10974 | check_absolute_expr (ip, &imm_expr); | |
10975 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10976 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
10977 | ip->insn_mo->name, | |
10978 | mask, (unsigned long) imm_expr.X_add_number); | |
10979 | INSERT_OPERAND (mips_opts.micromips, | |
10980 | 3BITPOS, *ip, imm_expr.X_add_number); | |
10981 | imm_expr.X_op = O_absent; | |
10982 | s = expr_end; | |
10983 | } | |
10984 | continue; | |
10985 | ||
252b5132 | 10986 | case ',': |
a339155f | 10987 | ++argnum; |
252b5132 RH |
10988 | if (*s++ == *args) |
10989 | continue; | |
10990 | s--; | |
10991 | switch (*++args) | |
10992 | { | |
10993 | case 'r': | |
10994 | case 'v': | |
df58fc94 | 10995 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
10996 | continue; |
10997 | ||
10998 | case 'w': | |
df58fc94 | 10999 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11000 | continue; |
11001 | ||
252b5132 | 11002 | case 'W': |
df58fc94 RS |
11003 | gas_assert (!mips_opts.micromips); |
11004 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11005 | continue; |
11006 | ||
11007 | case 'V': | |
df58fc94 | 11008 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11009 | continue; |
11010 | } | |
11011 | break; | |
11012 | ||
11013 | case '(': | |
11014 | /* Handle optional base register. | |
11015 | Either the base register is omitted or | |
bdaaa2e1 | 11016 | we must have a left paren. */ |
252b5132 RH |
11017 | /* This is dependent on the next operand specifier |
11018 | is a base register specification. */ | |
df58fc94 RS |
11019 | gas_assert (args[1] == 'b' |
11020 | || (mips_opts.micromips | |
11021 | && args[1] == 'm' | |
11022 | && (args[2] == 'l' || args[2] == 'n' | |
11023 | || args[2] == 's' || args[2] == 'a'))); | |
11024 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11025 | return; |
df58fc94 | 11026 | /* Fall through. */ |
252b5132 | 11027 | |
90ecf173 | 11028 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11029 | if (*s++ == *args) |
11030 | continue; | |
11031 | break; | |
11032 | ||
11033 | case '[': /* These must match exactly. */ | |
60b63b72 | 11034 | case ']': |
df58fc94 | 11035 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11036 | if (*s++ == *args) |
11037 | continue; | |
11038 | break; | |
11039 | ||
af7ee8bf CD |
11040 | case '+': /* Opcode extension character. */ |
11041 | switch (*++args) | |
11042 | { | |
9bcd4f99 TS |
11043 | case '1': /* UDI immediates. */ |
11044 | case '2': | |
11045 | case '3': | |
11046 | case '4': | |
df58fc94 | 11047 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11048 | { |
11049 | const struct mips_immed *imm = mips_immed; | |
11050 | ||
11051 | while (imm->type && imm->type != *args) | |
11052 | ++imm; | |
11053 | if (! imm->type) | |
11054 | internalError (); | |
11055 | my_getExpression (&imm_expr, s); | |
11056 | check_absolute_expr (ip, &imm_expr); | |
11057 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11058 | { | |
11059 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11060 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11061 | (unsigned long) imm_expr.X_add_number, | |
11062 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11063 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11064 | } |
11065 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11066 | << imm->shift); | |
11067 | imm_expr.X_op = O_absent; | |
11068 | s = expr_end; | |
11069 | } | |
11070 | continue; | |
90ecf173 | 11071 | |
071742cf CD |
11072 | case 'A': /* ins/ext position, becomes LSB. */ |
11073 | limlo = 0; | |
11074 | limhi = 31; | |
5f74bc13 CD |
11075 | goto do_lsb; |
11076 | case 'E': | |
11077 | limlo = 32; | |
11078 | limhi = 63; | |
11079 | goto do_lsb; | |
90ecf173 | 11080 | do_lsb: |
071742cf CD |
11081 | my_getExpression (&imm_expr, s); |
11082 | check_absolute_expr (ip, &imm_expr); | |
11083 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11084 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11085 | { | |
11086 | as_bad (_("Improper position (%lu)"), | |
11087 | (unsigned long) imm_expr.X_add_number); | |
11088 | imm_expr.X_add_number = limlo; | |
11089 | } | |
11090 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11091 | INSERT_OPERAND (mips_opts.micromips, |
11092 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11093 | imm_expr.X_op = O_absent; |
11094 | s = expr_end; | |
11095 | continue; | |
11096 | ||
11097 | case 'B': /* ins size, becomes MSB. */ | |
11098 | limlo = 1; | |
11099 | limhi = 32; | |
5f74bc13 CD |
11100 | goto do_msb; |
11101 | case 'F': | |
11102 | limlo = 33; | |
11103 | limhi = 64; | |
11104 | goto do_msb; | |
90ecf173 | 11105 | do_msb: |
071742cf CD |
11106 | my_getExpression (&imm_expr, s); |
11107 | check_absolute_expr (ip, &imm_expr); | |
11108 | /* Check for negative input so that small negative numbers | |
11109 | will not succeed incorrectly. The checks against | |
11110 | (pos+size) transitively check "size" itself, | |
11111 | assuming that "pos" is reasonable. */ | |
11112 | if ((long) imm_expr.X_add_number < 0 | |
11113 | || ((unsigned long) imm_expr.X_add_number | |
11114 | + lastpos) < limlo | |
11115 | || ((unsigned long) imm_expr.X_add_number | |
11116 | + lastpos) > limhi) | |
11117 | { | |
11118 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11119 | (unsigned long) imm_expr.X_add_number, | |
11120 | (unsigned long) lastpos); | |
11121 | imm_expr.X_add_number = limlo - lastpos; | |
11122 | } | |
df58fc94 RS |
11123 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11124 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11125 | imm_expr.X_op = O_absent; |
11126 | s = expr_end; | |
11127 | continue; | |
11128 | ||
11129 | case 'C': /* ext size, becomes MSBD. */ | |
11130 | limlo = 1; | |
11131 | limhi = 32; | |
5f74bc13 CD |
11132 | goto do_msbd; |
11133 | case 'G': | |
11134 | limlo = 33; | |
11135 | limhi = 64; | |
11136 | goto do_msbd; | |
11137 | case 'H': | |
11138 | limlo = 33; | |
11139 | limhi = 64; | |
11140 | goto do_msbd; | |
90ecf173 | 11141 | do_msbd: |
071742cf CD |
11142 | my_getExpression (&imm_expr, s); |
11143 | check_absolute_expr (ip, &imm_expr); | |
11144 | /* Check for negative input so that small negative numbers | |
11145 | will not succeed incorrectly. The checks against | |
11146 | (pos+size) transitively check "size" itself, | |
11147 | assuming that "pos" is reasonable. */ | |
11148 | if ((long) imm_expr.X_add_number < 0 | |
11149 | || ((unsigned long) imm_expr.X_add_number | |
11150 | + lastpos) < limlo | |
11151 | || ((unsigned long) imm_expr.X_add_number | |
11152 | + lastpos) > limhi) | |
11153 | { | |
11154 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11155 | (unsigned long) imm_expr.X_add_number, | |
11156 | (unsigned long) lastpos); | |
11157 | imm_expr.X_add_number = limlo - lastpos; | |
11158 | } | |
df58fc94 RS |
11159 | INSERT_OPERAND (mips_opts.micromips, |
11160 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11161 | imm_expr.X_op = O_absent; |
11162 | s = expr_end; | |
11163 | continue; | |
af7ee8bf | 11164 | |
bbcc0807 CD |
11165 | case 'D': |
11166 | /* +D is for disassembly only; never match. */ | |
11167 | break; | |
11168 | ||
5f74bc13 CD |
11169 | case 'I': |
11170 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11171 | my_getExpression (&imm2_expr, s); | |
11172 | if (imm2_expr.X_op != O_big | |
11173 | && imm2_expr.X_op != O_constant) | |
11174 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11175 | if (HAVE_32BIT_GPRS) |
11176 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11177 | s = expr_end; |
11178 | continue; | |
11179 | ||
707bfff6 | 11180 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11181 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11182 | /* +T is for disassembly only; never match. */ |
11183 | break; | |
11184 | ||
707bfff6 | 11185 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11186 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11187 | if (s[0] == '$' && ISDIGIT (s[1])) |
11188 | { | |
11189 | ++s; | |
11190 | regno = 0; | |
11191 | do | |
11192 | { | |
11193 | regno *= 10; | |
11194 | regno += *s - '0'; | |
11195 | ++s; | |
11196 | } | |
11197 | while (ISDIGIT (*s)); | |
11198 | if (regno > 31) | |
11199 | as_bad (_("Invalid register number (%d)"), regno); | |
11200 | else | |
11201 | { | |
df58fc94 | 11202 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11203 | continue; |
11204 | } | |
11205 | } | |
11206 | else | |
11207 | as_bad (_("Invalid coprocessor 0 register number")); | |
11208 | break; | |
11209 | ||
bb35fb24 NC |
11210 | case 'x': |
11211 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11212 | is not in the valid range. */ | |
df58fc94 | 11213 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11214 | my_getExpression (&imm_expr, s); |
11215 | check_absolute_expr (ip, &imm_expr); | |
11216 | if ((unsigned) imm_expr.X_add_number > 31) | |
11217 | { | |
11218 | as_bad (_("Improper bit index (%lu)"), | |
11219 | (unsigned long) imm_expr.X_add_number); | |
11220 | imm_expr.X_add_number = 0; | |
11221 | } | |
df58fc94 | 11222 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11223 | imm_expr.X_op = O_absent; |
11224 | s = expr_end; | |
11225 | continue; | |
11226 | ||
11227 | case 'X': | |
11228 | /* bbit[01] bit index when bbit is used but we generate | |
11229 | bbit[01]32 because the index is over 32. Move to the | |
11230 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11231 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11232 | my_getExpression (&imm_expr, s); |
11233 | check_absolute_expr (ip, &imm_expr); | |
11234 | if ((unsigned) imm_expr.X_add_number < 32 | |
11235 | || (unsigned) imm_expr.X_add_number > 63) | |
11236 | break; | |
df58fc94 | 11237 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11238 | imm_expr.X_op = O_absent; |
11239 | s = expr_end; | |
11240 | continue; | |
11241 | ||
11242 | case 'p': | |
11243 | /* cins, cins32, exts and exts32 position field. Give error | |
11244 | if it's not in the valid range. */ | |
df58fc94 | 11245 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11246 | my_getExpression (&imm_expr, s); |
11247 | check_absolute_expr (ip, &imm_expr); | |
11248 | if ((unsigned) imm_expr.X_add_number > 31) | |
11249 | { | |
11250 | as_bad (_("Improper position (%lu)"), | |
11251 | (unsigned long) imm_expr.X_add_number); | |
11252 | imm_expr.X_add_number = 0; | |
11253 | } | |
11254 | /* Make the pos explicit to simplify +S. */ | |
11255 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11256 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11257 | imm_expr.X_op = O_absent; |
11258 | s = expr_end; | |
11259 | continue; | |
11260 | ||
11261 | case 'P': | |
11262 | /* cins, cins32, exts and exts32 position field. Move to | |
11263 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11264 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11265 | my_getExpression (&imm_expr, s); |
11266 | check_absolute_expr (ip, &imm_expr); | |
11267 | if ((unsigned) imm_expr.X_add_number < 32 | |
11268 | || (unsigned) imm_expr.X_add_number > 63) | |
11269 | break; | |
11270 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11271 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11272 | imm_expr.X_op = O_absent; |
11273 | s = expr_end; | |
11274 | continue; | |
11275 | ||
11276 | case 's': | |
11277 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11278 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11279 | my_getExpression (&imm_expr, s); |
11280 | check_absolute_expr (ip, &imm_expr); | |
11281 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11282 | { | |
11283 | as_bad (_("Improper size (%lu)"), | |
11284 | (unsigned long) imm_expr.X_add_number); | |
11285 | imm_expr.X_add_number = 0; | |
11286 | } | |
df58fc94 | 11287 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11288 | imm_expr.X_op = O_absent; |
11289 | s = expr_end; | |
11290 | continue; | |
11291 | ||
11292 | case 'S': | |
11293 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11294 | length-minus-one field. */ | |
df58fc94 | 11295 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11296 | my_getExpression (&imm_expr, s); |
11297 | check_absolute_expr (ip, &imm_expr); | |
11298 | if ((long) imm_expr.X_add_number < 0 | |
11299 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11300 | { | |
11301 | as_bad (_("Improper size (%lu)"), | |
11302 | (unsigned long) imm_expr.X_add_number); | |
11303 | imm_expr.X_add_number = 0; | |
11304 | } | |
df58fc94 | 11305 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11306 | imm_expr.X_op = O_absent; |
11307 | s = expr_end; | |
11308 | continue; | |
11309 | ||
dd3cbb7e NC |
11310 | case 'Q': |
11311 | /* seqi/snei immediate field. */ | |
df58fc94 | 11312 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11313 | my_getExpression (&imm_expr, s); |
11314 | check_absolute_expr (ip, &imm_expr); | |
11315 | if ((long) imm_expr.X_add_number < -512 | |
11316 | || (long) imm_expr.X_add_number >= 512) | |
11317 | { | |
11318 | as_bad (_("Improper immediate (%ld)"), | |
11319 | (long) imm_expr.X_add_number); | |
11320 | imm_expr.X_add_number = 0; | |
11321 | } | |
df58fc94 | 11322 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11323 | imm_expr.X_op = O_absent; |
11324 | s = expr_end; | |
11325 | continue; | |
11326 | ||
98675402 | 11327 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11328 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11329 | my_getExpression (&imm_expr, s); |
11330 | check_absolute_expr (ip, &imm_expr); | |
11331 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11332 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11333 | if (imm_expr.X_add_number < min_range | |
11334 | || imm_expr.X_add_number > max_range) | |
11335 | { | |
c95354ed | 11336 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11337 | (long) min_range, (long) max_range, |
11338 | (long) imm_expr.X_add_number); | |
11339 | } | |
df58fc94 | 11340 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11341 | imm_expr.X_op = O_absent; |
11342 | s = expr_end; | |
11343 | continue; | |
11344 | ||
11345 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11346 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11347 | my_getExpression (&imm_expr, s); |
11348 | check_absolute_expr (ip, &imm_expr); | |
11349 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11350 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11351 | if (imm_expr.X_add_number < min_range | |
11352 | || imm_expr.X_add_number > max_range) | |
11353 | { | |
c95354ed | 11354 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11355 | (long) min_range, (long) max_range, |
11356 | (long) imm_expr.X_add_number); | |
11357 | } | |
df58fc94 | 11358 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11359 | imm_expr.X_op = O_absent; |
11360 | s = expr_end; | |
11361 | continue; | |
11362 | ||
11363 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11364 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11365 | my_getExpression (&imm_expr, s); |
11366 | check_absolute_expr (ip, &imm_expr); | |
11367 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11368 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11369 | /* We check the offset range before adjusted. */ |
11370 | min_range <<= 4; | |
11371 | max_range <<= 4; | |
98675402 RS |
11372 | if (imm_expr.X_add_number < min_range |
11373 | || imm_expr.X_add_number > max_range) | |
11374 | { | |
c95354ed | 11375 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11376 | (long) min_range, (long) max_range, |
11377 | (long) imm_expr.X_add_number); | |
11378 | } | |
c95354ed MX |
11379 | if (imm_expr.X_add_number & 0xf) |
11380 | { | |
11381 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11382 | (long) imm_expr.X_add_number); | |
11383 | } | |
11384 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11385 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11386 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11387 | imm_expr.X_op = O_absent; |
11388 | s = expr_end; | |
11389 | continue; | |
11390 | ||
11391 | case 'z': | |
df58fc94 | 11392 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11393 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11394 | break; | |
11395 | if (regno == AT && mips_opts.at) | |
11396 | { | |
11397 | if (mips_opts.at == ATREG) | |
11398 | as_warn (_("used $at without \".set noat\"")); | |
11399 | else | |
11400 | as_warn (_("used $%u with \".set at=$%u\""), | |
11401 | regno, mips_opts.at); | |
11402 | } | |
df58fc94 | 11403 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11404 | continue; |
11405 | ||
11406 | case 'Z': | |
df58fc94 | 11407 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11408 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11409 | break; | |
df58fc94 | 11410 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11411 | continue; |
11412 | ||
af7ee8bf | 11413 | default: |
df58fc94 | 11414 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11415 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11416 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11417 | *args, insn->name, insn->args); |
af7ee8bf CD |
11418 | /* Further processing is fruitless. */ |
11419 | return; | |
11420 | } | |
11421 | break; | |
11422 | ||
df58fc94 | 11423 | case '.': /* 10-bit offset. */ |
df58fc94 | 11424 | gas_assert (mips_opts.micromips); |
dec0624d | 11425 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11426 | { |
11427 | int shift = *args == '.' ? 9 : 11; | |
11428 | size_t i; | |
11429 | ||
11430 | /* Check whether there is only a single bracketed expression | |
11431 | left. If so, it must be the base register and the | |
11432 | constant must be zero. */ | |
11433 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11434 | continue; | |
11435 | ||
11436 | /* If this value won't fit into the offset, then go find | |
11437 | a macro that will generate a 16- or 32-bit offset code | |
11438 | pattern. */ | |
11439 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11440 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11441 | || imm_expr.X_add_number >= 1 << shift | |
11442 | || imm_expr.X_add_number < -1 << shift)) | |
11443 | || i > 0) | |
11444 | { | |
11445 | imm_expr.X_op = O_absent; | |
11446 | break; | |
11447 | } | |
11448 | if (shift == 9) | |
11449 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11450 | else | |
dec0624d MR |
11451 | INSERT_OPERAND (mips_opts.micromips, |
11452 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11453 | imm_expr.X_op = O_absent; |
11454 | s = expr_end; | |
11455 | } | |
11456 | continue; | |
11457 | ||
252b5132 RH |
11458 | case '<': /* must be at least one digit */ |
11459 | /* | |
11460 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11461 | * than 31 or less than 0, then the shift amount should be |
11462 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11463 | * We issue a warning and mask out all but the low 5 bits. |
11464 | */ | |
11465 | my_getExpression (&imm_expr, s); | |
11466 | check_absolute_expr (ip, &imm_expr); | |
11467 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11468 | as_warn (_("Improper shift amount (%lu)"), |
11469 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11470 | INSERT_OPERAND (mips_opts.micromips, |
11471 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11472 | imm_expr.X_op = O_absent; |
11473 | s = expr_end; | |
11474 | continue; | |
11475 | ||
11476 | case '>': /* shift amount minus 32 */ | |
11477 | my_getExpression (&imm_expr, s); | |
11478 | check_absolute_expr (ip, &imm_expr); | |
11479 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11480 | || (unsigned long) imm_expr.X_add_number > 63) | |
11481 | break; | |
df58fc94 RS |
11482 | INSERT_OPERAND (mips_opts.micromips, |
11483 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11484 | imm_expr.X_op = O_absent; |
11485 | s = expr_end; | |
11486 | continue; | |
11487 | ||
90ecf173 MR |
11488 | case 'k': /* CACHE code. */ |
11489 | case 'h': /* PREFX code. */ | |
11490 | case '1': /* SYNC type. */ | |
252b5132 RH |
11491 | my_getExpression (&imm_expr, s); |
11492 | check_absolute_expr (ip, &imm_expr); | |
11493 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11494 | as_warn (_("Invalid value for `%s' (%lu)"), |
11495 | ip->insn_mo->name, | |
11496 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11497 | switch (*args) |
d954098f | 11498 | { |
df58fc94 RS |
11499 | case 'k': |
11500 | if (mips_fix_cn63xxp1 | |
11501 | && !mips_opts.micromips | |
11502 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11503 | switch (imm_expr.X_add_number) |
11504 | { | |
11505 | case 5: | |
11506 | case 25: | |
11507 | case 26: | |
11508 | case 27: | |
11509 | case 28: | |
11510 | case 29: | |
11511 | case 30: | |
11512 | case 31: /* These are ok. */ | |
11513 | break; | |
11514 | ||
11515 | default: /* The rest must be changed to 28. */ | |
11516 | imm_expr.X_add_number = 28; | |
11517 | break; | |
11518 | } | |
df58fc94 RS |
11519 | INSERT_OPERAND (mips_opts.micromips, |
11520 | CACHE, *ip, imm_expr.X_add_number); | |
11521 | break; | |
11522 | case 'h': | |
11523 | INSERT_OPERAND (mips_opts.micromips, | |
11524 | PREFX, *ip, imm_expr.X_add_number); | |
11525 | break; | |
11526 | case '1': | |
11527 | INSERT_OPERAND (mips_opts.micromips, | |
11528 | STYPE, *ip, imm_expr.X_add_number); | |
11529 | break; | |
d954098f | 11530 | } |
252b5132 RH |
11531 | imm_expr.X_op = O_absent; |
11532 | s = expr_end; | |
11533 | continue; | |
11534 | ||
90ecf173 | 11535 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11536 | { |
11537 | unsigned long mask = (mips_opts.micromips | |
11538 | ? MICROMIPSOP_MASK_CODE | |
11539 | : OP_MASK_CODE); | |
11540 | ||
11541 | my_getExpression (&imm_expr, s); | |
11542 | check_absolute_expr (ip, &imm_expr); | |
11543 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11544 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11545 | ip->insn_mo->name, | |
11546 | mask, (unsigned long) imm_expr.X_add_number); | |
11547 | INSERT_OPERAND (mips_opts.micromips, | |
11548 | CODE, *ip, imm_expr.X_add_number); | |
11549 | imm_expr.X_op = O_absent; | |
11550 | s = expr_end; | |
11551 | } | |
252b5132 RH |
11552 | continue; |
11553 | ||
90ecf173 | 11554 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11555 | { |
11556 | unsigned long mask = (mips_opts.micromips | |
11557 | ? MICROMIPSOP_MASK_CODE2 | |
11558 | : OP_MASK_CODE2); | |
11559 | ||
11560 | my_getExpression (&imm_expr, s); | |
11561 | check_absolute_expr (ip, &imm_expr); | |
11562 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11563 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11564 | ip->insn_mo->name, | |
11565 | mask, (unsigned long) imm_expr.X_add_number); | |
11566 | INSERT_OPERAND (mips_opts.micromips, | |
11567 | CODE2, *ip, imm_expr.X_add_number); | |
11568 | imm_expr.X_op = O_absent; | |
11569 | s = expr_end; | |
11570 | } | |
252b5132 RH |
11571 | continue; |
11572 | ||
df58fc94 RS |
11573 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11574 | { | |
11575 | unsigned long mask = (mips_opts.micromips | |
11576 | ? MICROMIPSOP_MASK_CODE10 | |
11577 | : OP_MASK_CODE20); | |
11578 | ||
11579 | my_getExpression (&imm_expr, s); | |
11580 | check_absolute_expr (ip, &imm_expr); | |
11581 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11582 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11583 | ip->insn_mo->name, | |
11584 | mask, (unsigned long) imm_expr.X_add_number); | |
11585 | if (mips_opts.micromips) | |
11586 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11587 | else | |
11588 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11589 | imm_expr.X_op = O_absent; | |
11590 | s = expr_end; | |
11591 | } | |
252b5132 RH |
11592 | continue; |
11593 | ||
df58fc94 RS |
11594 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11595 | { | |
11596 | unsigned long mask = (mips_opts.micromips | |
11597 | ? MICROMIPSOP_MASK_COPZ | |
11598 | : OP_MASK_COPZ); | |
11599 | ||
11600 | my_getExpression (&imm_expr, s); | |
11601 | check_absolute_expr (ip, &imm_expr); | |
11602 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11603 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11604 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11605 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11606 | INSERT_OPERAND (mips_opts.micromips, |
11607 | COPZ, *ip, imm_expr.X_add_number); | |
11608 | imm_expr.X_op = O_absent; | |
11609 | s = expr_end; | |
11610 | } | |
beae10d5 | 11611 | continue; |
252b5132 | 11612 | |
df58fc94 RS |
11613 | case 'J': /* 19-bit WAIT code. */ |
11614 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11615 | my_getExpression (&imm_expr, s); |
11616 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11617 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11618 | { |
11619 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11620 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11621 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11622 | } | |
11623 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11624 | imm_expr.X_op = O_absent; |
11625 | s = expr_end; | |
11626 | continue; | |
11627 | ||
707bfff6 | 11628 | case 'P': /* Performance register. */ |
df58fc94 | 11629 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11630 | my_getExpression (&imm_expr, s); |
252b5132 | 11631 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11632 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11633 | as_warn (_("Invalid performance register (%lu)"), |
11634 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11635 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11636 | imm_expr.X_op = O_absent; |
11637 | s = expr_end; | |
11638 | continue; | |
252b5132 | 11639 | |
707bfff6 | 11640 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11641 | { |
11642 | unsigned long opcode = ip->insn_opcode; | |
11643 | unsigned long mask; | |
11644 | unsigned int types; | |
11645 | int cop0; | |
11646 | ||
11647 | if (mips_opts.micromips) | |
11648 | { | |
11649 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11650 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11651 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11652 | opcode &= mask; | |
11653 | switch (opcode) | |
11654 | { | |
11655 | case 0x000000fc: /* mfc0 */ | |
11656 | case 0x000002fc: /* mtc0 */ | |
11657 | case 0x580000fc: /* dmfc0 */ | |
11658 | case 0x580002fc: /* dmtc0 */ | |
11659 | cop0 = 1; | |
11660 | break; | |
11661 | default: | |
11662 | cop0 = 0; | |
11663 | break; | |
11664 | } | |
11665 | } | |
11666 | else | |
11667 | { | |
11668 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11669 | cop0 = opcode == OP_OP_COP0; | |
11670 | } | |
11671 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11672 | ok = reg_lookup (&s, types, ®no); | |
11673 | if (mips_opts.micromips) | |
11674 | INSERT_OPERAND (1, RS, *ip, regno); | |
11675 | else | |
11676 | INSERT_OPERAND (0, RD, *ip, regno); | |
11677 | if (ok) | |
11678 | { | |
11679 | lastregno = regno; | |
11680 | continue; | |
11681 | } | |
11682 | } | |
11683 | break; | |
707bfff6 | 11684 | |
df58fc94 RS |
11685 | case 'y': /* ALNV.PS source register. */ |
11686 | gas_assert (mips_opts.micromips); | |
11687 | goto do_reg; | |
11688 | case 'x': /* Ignore register name. */ | |
11689 | case 'U': /* Destination register (CLO/CLZ). */ | |
11690 | case 'g': /* Coprocessor destination register. */ | |
11691 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11692 | case 'b': /* Base register. */ |
11693 | case 'd': /* Destination register. */ | |
11694 | case 's': /* Source register. */ | |
11695 | case 't': /* Target register. */ | |
11696 | case 'r': /* Both target and source. */ | |
11697 | case 'v': /* Both dest and source. */ | |
11698 | case 'w': /* Both dest and target. */ | |
11699 | case 'E': /* Coprocessor target register. */ | |
11700 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11701 | case 'z': /* Must be zero register. */ |
df58fc94 | 11702 | do_reg: |
90ecf173 | 11703 | s_reset = s; |
707bfff6 TS |
11704 | if (*args == 'E' || *args == 'K') |
11705 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11706 | else | |
11707 | { | |
11708 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11709 | if (regno == AT && mips_opts.at) |
11710 | { | |
11711 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11712 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11713 | else |
f71d0d44 | 11714 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11715 | regno, mips_opts.at); |
11716 | } | |
707bfff6 TS |
11717 | } |
11718 | if (ok) | |
252b5132 | 11719 | { |
252b5132 RH |
11720 | c = *args; |
11721 | if (*s == ' ') | |
f9419b05 | 11722 | ++s; |
252b5132 RH |
11723 | if (args[1] != *s) |
11724 | { | |
11725 | if (c == 'r' || c == 'v' || c == 'w') | |
11726 | { | |
11727 | regno = lastregno; | |
11728 | s = s_reset; | |
f9419b05 | 11729 | ++args; |
252b5132 RH |
11730 | } |
11731 | } | |
11732 | /* 'z' only matches $0. */ | |
11733 | if (c == 'z' && regno != 0) | |
11734 | break; | |
11735 | ||
24864476 | 11736 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11737 | { |
11738 | if (regno == lastregno) | |
90ecf173 MR |
11739 | { |
11740 | insn_error | |
f71d0d44 | 11741 | = _("Source and destination must be different"); |
e7c604dd | 11742 | continue; |
90ecf173 | 11743 | } |
24864476 | 11744 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11745 | { |
11746 | insn_error | |
f71d0d44 | 11747 | = _("A destination register must be supplied"); |
e7c604dd | 11748 | continue; |
90ecf173 | 11749 | } |
e7c604dd | 11750 | } |
90ecf173 MR |
11751 | /* Now that we have assembled one operand, we use the args |
11752 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11753 | switch (c) |
11754 | { | |
11755 | case 'r': | |
11756 | case 's': | |
11757 | case 'v': | |
11758 | case 'b': | |
df58fc94 | 11759 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11760 | break; |
df58fc94 | 11761 | |
af7ee8bf | 11762 | case 'K': |
df58fc94 RS |
11763 | if (mips_opts.micromips) |
11764 | INSERT_OPERAND (1, RS, *ip, regno); | |
11765 | else | |
11766 | INSERT_OPERAND (0, RD, *ip, regno); | |
11767 | break; | |
11768 | ||
11769 | case 'd': | |
ef2e4d86 | 11770 | case 'g': |
df58fc94 | 11771 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11772 | break; |
df58fc94 | 11773 | |
4372b673 | 11774 | case 'U': |
df58fc94 RS |
11775 | gas_assert (!mips_opts.micromips); |
11776 | INSERT_OPERAND (0, RD, *ip, regno); | |
11777 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11778 | break; |
df58fc94 | 11779 | |
252b5132 RH |
11780 | case 'w': |
11781 | case 't': | |
11782 | case 'E': | |
df58fc94 RS |
11783 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11784 | break; | |
11785 | ||
11786 | case 'y': | |
11787 | gas_assert (mips_opts.micromips); | |
11788 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11789 | break; |
df58fc94 | 11790 | |
252b5132 RH |
11791 | case 'x': |
11792 | /* This case exists because on the r3000 trunc | |
11793 | expands into a macro which requires a gp | |
11794 | register. On the r6000 or r4000 it is | |
11795 | assembled into a single instruction which | |
11796 | ignores the register. Thus the insn version | |
11797 | is MIPS_ISA2 and uses 'x', and the macro | |
11798 | version is MIPS_ISA1 and uses 't'. */ | |
11799 | break; | |
df58fc94 | 11800 | |
252b5132 RH |
11801 | case 'z': |
11802 | /* This case is for the div instruction, which | |
11803 | acts differently if the destination argument | |
11804 | is $0. This only matches $0, and is checked | |
11805 | outside the switch. */ | |
11806 | break; | |
252b5132 RH |
11807 | } |
11808 | lastregno = regno; | |
11809 | continue; | |
11810 | } | |
252b5132 RH |
11811 | switch (*args++) |
11812 | { | |
11813 | case 'r': | |
11814 | case 'v': | |
df58fc94 | 11815 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11816 | continue; |
df58fc94 | 11817 | |
252b5132 | 11818 | case 'w': |
df58fc94 | 11819 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11820 | continue; |
11821 | } | |
11822 | break; | |
11823 | ||
deec1734 | 11824 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11825 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11826 | my_getExpression (&imm_expr, s); |
11827 | check_absolute_expr (ip, &imm_expr); | |
11828 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11829 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11830 | (long) imm_expr.X_add_number); |
df58fc94 | 11831 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11832 | imm_expr.X_op = O_absent; |
11833 | s = expr_end; | |
11834 | continue; | |
11835 | ||
11836 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11837 | if (s[0] != '$') | |
11838 | { | |
11839 | /* MDMX Immediate. */ | |
df58fc94 | 11840 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11841 | my_getExpression (&imm_expr, s); |
11842 | check_absolute_expr (ip, &imm_expr); | |
11843 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11844 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11845 | (long) imm_expr.X_add_number); | |
df58fc94 | 11846 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11847 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11848 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11849 | else | |
11850 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11851 | imm_expr.X_op = O_absent; |
11852 | s = expr_end; | |
11853 | continue; | |
11854 | } | |
11855 | /* Not MDMX Immediate. Fall through. */ | |
11856 | case 'X': /* MDMX destination register. */ | |
11857 | case 'Y': /* MDMX source register. */ | |
11858 | case 'Z': /* MDMX target register. */ | |
11859 | is_mdmx = 1; | |
df58fc94 RS |
11860 | case 'W': |
11861 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11862 | case 'D': /* Floating point destination register. */ |
11863 | case 'S': /* Floating point source register. */ | |
11864 | case 'T': /* Floating point target register. */ | |
11865 | case 'R': /* Floating point source register. */ | |
252b5132 | 11866 | case 'V': |
707bfff6 TS |
11867 | rtype = RTYPE_FPU; |
11868 | if (is_mdmx | |
11869 | || (mips_opts.ase_mdmx | |
11870 | && (ip->insn_mo->pinfo & FP_D) | |
11871 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11872 | | INSN_COPROC_MEMORY_DELAY | |
11873 | | INSN_LOAD_COPROC_DELAY | |
11874 | | INSN_LOAD_MEMORY_DELAY | |
11875 | | INSN_STORE_MEMORY)))) | |
11876 | rtype |= RTYPE_VEC; | |
252b5132 | 11877 | s_reset = s; |
707bfff6 | 11878 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11879 | { |
252b5132 | 11880 | if ((regno & 1) != 0 |
ca4e0257 | 11881 | && HAVE_32BIT_FPRS |
90ecf173 | 11882 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11883 | as_warn (_("Float register should be even, was %d"), |
11884 | regno); | |
11885 | ||
11886 | c = *args; | |
11887 | if (*s == ' ') | |
f9419b05 | 11888 | ++s; |
252b5132 RH |
11889 | if (args[1] != *s) |
11890 | { | |
11891 | if (c == 'V' || c == 'W') | |
11892 | { | |
11893 | regno = lastregno; | |
11894 | s = s_reset; | |
f9419b05 | 11895 | ++args; |
252b5132 RH |
11896 | } |
11897 | } | |
11898 | switch (c) | |
11899 | { | |
11900 | case 'D': | |
deec1734 | 11901 | case 'X': |
df58fc94 | 11902 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 11903 | break; |
df58fc94 | 11904 | |
252b5132 RH |
11905 | case 'V': |
11906 | case 'S': | |
deec1734 | 11907 | case 'Y': |
df58fc94 | 11908 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 11909 | break; |
df58fc94 | 11910 | |
deec1734 CD |
11911 | case 'Q': |
11912 | /* This is like 'Z', but also needs to fix the MDMX | |
11913 | vector/scalar select bits. Note that the | |
11914 | scalar immediate case is handled above. */ | |
11915 | if (*s == '[') | |
11916 | { | |
11917 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
11918 | int max_el = (is_qh ? 3 : 7); | |
11919 | s++; | |
11920 | my_getExpression(&imm_expr, s); | |
11921 | check_absolute_expr (ip, &imm_expr); | |
11922 | s = expr_end; | |
11923 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
11924 | as_bad (_("Bad element selector %ld"), |
11925 | (long) imm_expr.X_add_number); | |
deec1734 CD |
11926 | imm_expr.X_add_number &= max_el; |
11927 | ip->insn_opcode |= (imm_expr.X_add_number | |
11928 | << (OP_SH_VSEL + | |
11929 | (is_qh ? 2 : 1))); | |
01a3f561 | 11930 | imm_expr.X_op = O_absent; |
deec1734 | 11931 | if (*s != ']') |
20203fb9 | 11932 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
11933 | else |
11934 | s++; | |
11935 | } | |
11936 | else | |
11937 | { | |
11938 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
11939 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
11940 | << OP_SH_VSEL); | |
11941 | else | |
11942 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
11943 | OP_SH_VSEL); | |
11944 | } | |
90ecf173 | 11945 | /* Fall through. */ |
252b5132 RH |
11946 | case 'W': |
11947 | case 'T': | |
deec1734 | 11948 | case 'Z': |
df58fc94 | 11949 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 11950 | break; |
df58fc94 | 11951 | |
252b5132 | 11952 | case 'R': |
df58fc94 | 11953 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
11954 | break; |
11955 | } | |
11956 | lastregno = regno; | |
11957 | continue; | |
11958 | } | |
11959 | ||
252b5132 RH |
11960 | switch (*args++) |
11961 | { | |
11962 | case 'V': | |
df58fc94 | 11963 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 11964 | continue; |
df58fc94 | 11965 | |
252b5132 | 11966 | case 'W': |
df58fc94 | 11967 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
11968 | continue; |
11969 | } | |
11970 | break; | |
11971 | ||
11972 | case 'I': | |
11973 | my_getExpression (&imm_expr, s); | |
11974 | if (imm_expr.X_op != O_big | |
11975 | && imm_expr.X_op != O_constant) | |
11976 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11977 | if (HAVE_32BIT_GPRS) |
11978 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
11979 | s = expr_end; |
11980 | continue; | |
11981 | ||
11982 | case 'A': | |
11983 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 11984 | normalize_address_expr (&offset_expr); |
f6688943 | 11985 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
11986 | s = expr_end; |
11987 | continue; | |
11988 | ||
11989 | case 'F': | |
11990 | case 'L': | |
11991 | case 'f': | |
11992 | case 'l': | |
11993 | { | |
11994 | int f64; | |
ca4e0257 | 11995 | int using_gprs; |
252b5132 RH |
11996 | char *save_in; |
11997 | char *err; | |
11998 | unsigned char temp[8]; | |
11999 | int len; | |
12000 | unsigned int length; | |
12001 | segT seg; | |
12002 | subsegT subseg; | |
12003 | char *p; | |
12004 | ||
12005 | /* These only appear as the last operand in an | |
12006 | instruction, and every instruction that accepts | |
12007 | them in any variant accepts them in all variants. | |
12008 | This means we don't have to worry about backing out | |
12009 | any changes if the instruction does not match. | |
12010 | ||
12011 | The difference between them is the size of the | |
12012 | floating point constant and where it goes. For 'F' | |
12013 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12014 | is 32 bits. Where the constant is placed is based | |
12015 | on how the MIPS assembler does things: | |
12016 | F -- .rdata | |
12017 | L -- .lit8 | |
12018 | f -- immediate value | |
12019 | l -- .lit4 | |
12020 | ||
12021 | The .lit4 and .lit8 sections are only used if | |
12022 | permitted by the -G argument. | |
12023 | ||
ca4e0257 RS |
12024 | The code below needs to know whether the target register |
12025 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12026 | 'F' are used with GPR-based instructions and 'l' and | |
12027 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12028 | |
12029 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12030 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12031 | |
12032 | save_in = input_line_pointer; | |
12033 | input_line_pointer = s; | |
12034 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12035 | length = len; | |
12036 | s = input_line_pointer; | |
12037 | input_line_pointer = save_in; | |
12038 | if (err != NULL && *err != '\0') | |
12039 | { | |
12040 | as_bad (_("Bad floating point constant: %s"), err); | |
12041 | memset (temp, '\0', sizeof temp); | |
12042 | length = f64 ? 8 : 4; | |
12043 | } | |
12044 | ||
9c2799c2 | 12045 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12046 | |
12047 | if (*args == 'f' | |
12048 | || (*args == 'l' | |
3e722fb5 | 12049 | && (g_switch_value < 4 |
252b5132 RH |
12050 | || (temp[0] == 0 && temp[1] == 0) |
12051 | || (temp[2] == 0 && temp[3] == 0)))) | |
12052 | { | |
12053 | imm_expr.X_op = O_constant; | |
90ecf173 | 12054 | if (!target_big_endian) |
252b5132 RH |
12055 | imm_expr.X_add_number = bfd_getl32 (temp); |
12056 | else | |
12057 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12058 | } | |
12059 | else if (length > 4 | |
90ecf173 | 12060 | && !mips_disable_float_construction |
ca4e0257 RS |
12061 | /* Constants can only be constructed in GPRs and |
12062 | copied to FPRs if the GPRs are at least as wide | |
12063 | as the FPRs. Force the constant into memory if | |
12064 | we are using 64-bit FPRs but the GPRs are only | |
12065 | 32 bits wide. */ | |
12066 | && (using_gprs | |
90ecf173 | 12067 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12068 | && ((temp[0] == 0 && temp[1] == 0) |
12069 | || (temp[2] == 0 && temp[3] == 0)) | |
12070 | && ((temp[4] == 0 && temp[5] == 0) | |
12071 | || (temp[6] == 0 && temp[7] == 0))) | |
12072 | { | |
ca4e0257 | 12073 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12074 | instructions. If using 32-bit registers, set |
12075 | imm_expr to the high order 32 bits and offset_expr to | |
12076 | the low order 32 bits. Otherwise, set imm_expr to | |
12077 | the entire 64 bit constant. */ | |
ca4e0257 | 12078 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12079 | { |
12080 | imm_expr.X_op = O_constant; | |
12081 | offset_expr.X_op = O_constant; | |
90ecf173 | 12082 | if (!target_big_endian) |
252b5132 RH |
12083 | { |
12084 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12085 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12086 | } | |
12087 | else | |
12088 | { | |
12089 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12090 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12091 | } | |
12092 | if (offset_expr.X_add_number == 0) | |
12093 | offset_expr.X_op = O_absent; | |
12094 | } | |
12095 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12096 | { | |
12097 | imm_expr.X_op = O_constant; | |
90ecf173 | 12098 | if (!target_big_endian) |
252b5132 RH |
12099 | imm_expr.X_add_number = bfd_getl64 (temp); |
12100 | else | |
12101 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12102 | } | |
12103 | else | |
12104 | { | |
12105 | imm_expr.X_op = O_big; | |
12106 | imm_expr.X_add_number = 4; | |
90ecf173 | 12107 | if (!target_big_endian) |
252b5132 RH |
12108 | { |
12109 | generic_bignum[0] = bfd_getl16 (temp); | |
12110 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12111 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12112 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12113 | } | |
12114 | else | |
12115 | { | |
12116 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12117 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12118 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12119 | generic_bignum[3] = bfd_getb16 (temp); | |
12120 | } | |
12121 | } | |
12122 | } | |
12123 | else | |
12124 | { | |
12125 | const char *newname; | |
12126 | segT new_seg; | |
12127 | ||
12128 | /* Switch to the right section. */ | |
12129 | seg = now_seg; | |
12130 | subseg = now_subseg; | |
12131 | switch (*args) | |
12132 | { | |
12133 | default: /* unused default case avoids warnings. */ | |
12134 | case 'L': | |
12135 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12136 | if (g_switch_value >= 8) |
252b5132 RH |
12137 | newname = ".lit8"; |
12138 | break; | |
12139 | case 'F': | |
3e722fb5 | 12140 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12141 | break; |
12142 | case 'l': | |
9c2799c2 | 12143 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12144 | newname = ".lit4"; |
12145 | break; | |
12146 | } | |
12147 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12148 | if (IS_ELF) |
252b5132 RH |
12149 | bfd_set_section_flags (stdoutput, new_seg, |
12150 | (SEC_ALLOC | |
12151 | | SEC_LOAD | |
12152 | | SEC_READONLY | |
12153 | | SEC_DATA)); | |
12154 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12155 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12156 | record_alignment (new_seg, 4); |
12157 | else | |
12158 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12159 | if (seg == now_seg) | |
12160 | as_bad (_("Can't use floating point insn in this section")); | |
12161 | ||
df58fc94 RS |
12162 | /* Set the argument to the current address in the |
12163 | section. */ | |
12164 | offset_expr.X_op = O_symbol; | |
12165 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12166 | offset_expr.X_add_number = 0; | |
12167 | ||
12168 | /* Put the floating point number into the section. */ | |
12169 | p = frag_more ((int) length); | |
12170 | memcpy (p, temp, length); | |
12171 | ||
12172 | /* Switch back to the original section. */ | |
12173 | subseg_set (seg, subseg); | |
12174 | } | |
12175 | } | |
12176 | continue; | |
12177 | ||
12178 | case 'i': /* 16-bit unsigned immediate. */ | |
12179 | case 'j': /* 16-bit signed immediate. */ | |
12180 | *imm_reloc = BFD_RELOC_LO16; | |
12181 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12182 | { | |
12183 | int more; | |
12184 | offsetT minval, maxval; | |
12185 | ||
12186 | more = (insn + 1 < past | |
12187 | && strcmp (insn->name, insn[1].name) == 0); | |
12188 | ||
12189 | /* If the expression was written as an unsigned number, | |
12190 | only treat it as signed if there are no more | |
12191 | alternatives. */ | |
12192 | if (more | |
12193 | && *args == 'j' | |
12194 | && sizeof (imm_expr.X_add_number) <= 4 | |
12195 | && imm_expr.X_op == O_constant | |
12196 | && imm_expr.X_add_number < 0 | |
12197 | && imm_expr.X_unsigned | |
12198 | && HAVE_64BIT_GPRS) | |
12199 | break; | |
12200 | ||
12201 | /* For compatibility with older assemblers, we accept | |
12202 | 0x8000-0xffff as signed 16-bit numbers when only | |
12203 | signed numbers are allowed. */ | |
12204 | if (*args == 'i') | |
12205 | minval = 0, maxval = 0xffff; | |
12206 | else if (more) | |
12207 | minval = -0x8000, maxval = 0x7fff; | |
12208 | else | |
12209 | minval = -0x8000, maxval = 0xffff; | |
12210 | ||
12211 | if (imm_expr.X_op != O_constant | |
12212 | || imm_expr.X_add_number < minval | |
12213 | || imm_expr.X_add_number > maxval) | |
12214 | { | |
12215 | if (more) | |
12216 | break; | |
12217 | if (imm_expr.X_op == O_constant | |
12218 | || imm_expr.X_op == O_big) | |
12219 | as_bad (_("Expression out of range")); | |
12220 | } | |
12221 | } | |
12222 | s = expr_end; | |
12223 | continue; | |
12224 | ||
12225 | case 'o': /* 16-bit offset. */ | |
12226 | offset_reloc[0] = BFD_RELOC_LO16; | |
12227 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12228 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12229 | ||
12230 | /* Check whether there is only a single bracketed expression | |
12231 | left. If so, it must be the base register and the | |
12232 | constant must be zero. */ | |
12233 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12234 | { | |
12235 | offset_expr.X_op = O_constant; | |
12236 | offset_expr.X_add_number = 0; | |
12237 | continue; | |
12238 | } | |
12239 | ||
12240 | /* If this value won't fit into a 16 bit offset, then go | |
12241 | find a macro that will generate the 32 bit offset | |
12242 | code pattern. */ | |
12243 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12244 | && (offset_expr.X_op != O_constant | |
12245 | || offset_expr.X_add_number >= 0x8000 | |
12246 | || offset_expr.X_add_number < -0x8000)) | |
12247 | break; | |
12248 | ||
12249 | s = expr_end; | |
12250 | continue; | |
12251 | ||
12252 | case 'p': /* PC-relative offset. */ | |
12253 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12254 | my_getExpression (&offset_expr, s); | |
12255 | s = expr_end; | |
12256 | continue; | |
12257 | ||
12258 | case 'u': /* Upper 16 bits. */ | |
12259 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12260 | && imm_expr.X_op == O_constant | |
12261 | && (imm_expr.X_add_number < 0 | |
12262 | || imm_expr.X_add_number >= 0x10000)) | |
12263 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12264 | (unsigned long) imm_expr.X_add_number); | |
12265 | s = expr_end; | |
12266 | continue; | |
12267 | ||
12268 | case 'a': /* 26-bit address. */ | |
12269 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12270 | my_getExpression (&offset_expr, s); | |
12271 | s = expr_end; | |
12272 | continue; | |
12273 | ||
12274 | case 'N': /* 3-bit branch condition code. */ | |
12275 | case 'M': /* 3-bit compare condition code. */ | |
12276 | rtype = RTYPE_CCC; | |
12277 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12278 | rtype |= RTYPE_FCC; | |
12279 | if (!reg_lookup (&s, rtype, ®no)) | |
12280 | break; | |
12281 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12282 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12283 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12284 | && (regno & 1) != 0) | |
12285 | as_warn (_("Condition code register should be even for %s, " | |
12286 | "was %d"), | |
12287 | str, regno); | |
12288 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12289 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12290 | && (regno & 3) != 0) | |
12291 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12292 | "was %d"), | |
12293 | str, regno); | |
12294 | if (*args == 'N') | |
12295 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12296 | else | |
12297 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12298 | continue; | |
12299 | ||
12300 | case 'H': | |
12301 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12302 | s += 2; | |
12303 | if (ISDIGIT (*s)) | |
12304 | { | |
12305 | c = 0; | |
12306 | do | |
12307 | { | |
12308 | c *= 10; | |
12309 | c += *s - '0'; | |
12310 | ++s; | |
12311 | } | |
12312 | while (ISDIGIT (*s)); | |
12313 | } | |
12314 | else | |
12315 | c = 8; /* Invalid sel value. */ | |
12316 | ||
12317 | if (c > 7) | |
12318 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12319 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12320 | continue; | |
12321 | ||
12322 | case 'e': | |
12323 | gas_assert (!mips_opts.micromips); | |
12324 | /* Must be at least one digit. */ | |
12325 | my_getExpression (&imm_expr, s); | |
12326 | check_absolute_expr (ip, &imm_expr); | |
12327 | ||
12328 | if ((unsigned long) imm_expr.X_add_number | |
12329 | > (unsigned long) OP_MASK_VECBYTE) | |
12330 | { | |
12331 | as_bad (_("bad byte vector index (%ld)"), | |
12332 | (long) imm_expr.X_add_number); | |
12333 | imm_expr.X_add_number = 0; | |
12334 | } | |
12335 | ||
12336 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12337 | imm_expr.X_op = O_absent; | |
12338 | s = expr_end; | |
12339 | continue; | |
12340 | ||
12341 | case '%': | |
12342 | gas_assert (!mips_opts.micromips); | |
12343 | my_getExpression (&imm_expr, s); | |
12344 | check_absolute_expr (ip, &imm_expr); | |
12345 | ||
12346 | if ((unsigned long) imm_expr.X_add_number | |
12347 | > (unsigned long) OP_MASK_VECALIGN) | |
12348 | { | |
12349 | as_bad (_("bad byte vector index (%ld)"), | |
12350 | (long) imm_expr.X_add_number); | |
12351 | imm_expr.X_add_number = 0; | |
12352 | } | |
12353 | ||
12354 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12355 | imm_expr.X_op = O_absent; | |
12356 | s = expr_end; | |
12357 | continue; | |
12358 | ||
12359 | case 'm': /* Opcode extension character. */ | |
12360 | gas_assert (mips_opts.micromips); | |
12361 | c = *++args; | |
12362 | switch (c) | |
12363 | { | |
12364 | case 'r': | |
12365 | if (strncmp (s, "$pc", 3) == 0) | |
12366 | { | |
12367 | s += 3; | |
12368 | continue; | |
12369 | } | |
12370 | break; | |
12371 | ||
12372 | case 'a': | |
12373 | case 'b': | |
12374 | case 'c': | |
12375 | case 'd': | |
12376 | case 'e': | |
12377 | case 'f': | |
12378 | case 'g': | |
12379 | case 'h': | |
12380 | case 'i': | |
12381 | case 'j': | |
12382 | case 'l': | |
12383 | case 'm': | |
12384 | case 'n': | |
12385 | case 'p': | |
12386 | case 'q': | |
12387 | case 's': | |
12388 | case 't': | |
12389 | case 'x': | |
12390 | case 'y': | |
12391 | case 'z': | |
12392 | s_reset = s; | |
12393 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12394 | if (regno == AT && mips_opts.at) | |
12395 | { | |
12396 | if (mips_opts.at == ATREG) | |
12397 | as_warn (_("Used $at without \".set noat\"")); | |
12398 | else | |
12399 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12400 | regno, mips_opts.at); | |
12401 | } | |
12402 | if (!ok) | |
12403 | { | |
12404 | if (c == 'c') | |
12405 | { | |
12406 | gas_assert (args[1] == ','); | |
12407 | regno = lastregno; | |
12408 | ++args; | |
12409 | } | |
12410 | else if (c == 't') | |
12411 | { | |
12412 | gas_assert (args[1] == ','); | |
12413 | ++args; | |
12414 | continue; /* Nothing to do. */ | |
12415 | } | |
12416 | else | |
12417 | break; | |
12418 | } | |
12419 | ||
12420 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12421 | { | |
12422 | if (regno == lastregno) | |
12423 | { | |
12424 | insn_error | |
12425 | = _("Source and destination must be different"); | |
12426 | continue; | |
12427 | } | |
12428 | if (regno == 31 && lastregno == 0xffffffff) | |
12429 | { | |
12430 | insn_error | |
12431 | = _("A destination register must be supplied"); | |
12432 | continue; | |
12433 | } | |
12434 | } | |
12435 | ||
12436 | if (*s == ' ') | |
12437 | ++s; | |
12438 | if (args[1] != *s) | |
12439 | { | |
12440 | if (c == 'e') | |
12441 | { | |
12442 | gas_assert (args[1] == ','); | |
12443 | regno = lastregno; | |
12444 | s = s_reset; | |
12445 | ++args; | |
12446 | } | |
12447 | else if (c == 't') | |
12448 | { | |
12449 | gas_assert (args[1] == ','); | |
12450 | s = s_reset; | |
12451 | ++args; | |
12452 | continue; /* Nothing to do. */ | |
12453 | } | |
12454 | } | |
12455 | ||
12456 | /* Make sure regno is the same as lastregno. */ | |
12457 | if (c == 't' && regno != lastregno) | |
12458 | break; | |
12459 | ||
12460 | /* Make sure regno is the same as destregno. */ | |
12461 | if (c == 'x' && regno != destregno) | |
12462 | break; | |
12463 | ||
12464 | /* We need to save regno, before regno maps to the | |
12465 | microMIPS register encoding. */ | |
12466 | lastregno = regno; | |
12467 | ||
12468 | if (c == 'f') | |
12469 | destregno = regno; | |
12470 | ||
12471 | switch (c) | |
12472 | { | |
12473 | case 'a': | |
12474 | if (regno != GP) | |
12475 | regno = ILLEGAL_REG; | |
12476 | break; | |
12477 | ||
12478 | case 'b': | |
12479 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12480 | break; | |
12481 | ||
12482 | case 'c': | |
12483 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12484 | break; | |
12485 | ||
12486 | case 'd': | |
12487 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12488 | break; | |
12489 | ||
12490 | case 'e': | |
12491 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12492 | break; | |
12493 | ||
12494 | case 'f': | |
12495 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12496 | break; | |
12497 | ||
12498 | case 'g': | |
12499 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12500 | break; | |
12501 | ||
12502 | case 'h': | |
12503 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12504 | break; | |
12505 | ||
12506 | case 'i': | |
12507 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12508 | { | |
12509 | case 4: | |
12510 | if (regno == 21) | |
12511 | regno = 3; | |
12512 | else if (regno == 22) | |
12513 | regno = 4; | |
12514 | else if (regno == 5) | |
12515 | regno = 5; | |
12516 | else if (regno == 6) | |
12517 | regno = 6; | |
12518 | else if (regno == 7) | |
12519 | regno = 7; | |
12520 | else | |
12521 | regno = ILLEGAL_REG; | |
12522 | break; | |
12523 | ||
12524 | case 5: | |
12525 | if (regno == 6) | |
12526 | regno = 0; | |
12527 | else if (regno == 7) | |
12528 | regno = 1; | |
12529 | else | |
12530 | regno = ILLEGAL_REG; | |
12531 | break; | |
12532 | ||
12533 | case 6: | |
12534 | if (regno == 7) | |
12535 | regno = 2; | |
12536 | else | |
12537 | regno = ILLEGAL_REG; | |
12538 | break; | |
12539 | ||
12540 | default: | |
12541 | regno = ILLEGAL_REG; | |
12542 | break; | |
12543 | } | |
12544 | break; | |
12545 | ||
12546 | case 'l': | |
12547 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12548 | break; | |
12549 | ||
12550 | case 'm': | |
12551 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12552 | break; | |
12553 | ||
12554 | case 'n': | |
12555 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12556 | break; | |
12557 | ||
12558 | case 'q': | |
12559 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12560 | break; | |
12561 | ||
12562 | case 's': | |
12563 | if (regno != SP) | |
12564 | regno = ILLEGAL_REG; | |
12565 | break; | |
12566 | ||
12567 | case 'y': | |
12568 | if (regno != 31) | |
12569 | regno = ILLEGAL_REG; | |
12570 | break; | |
12571 | ||
12572 | case 'z': | |
12573 | if (regno != ZERO) | |
12574 | regno = ILLEGAL_REG; | |
12575 | break; | |
12576 | ||
12577 | case 'j': /* Do nothing. */ | |
12578 | case 'p': | |
12579 | case 't': | |
12580 | case 'x': | |
12581 | break; | |
12582 | ||
12583 | default: | |
12584 | internalError (); | |
12585 | } | |
12586 | ||
12587 | if (regno == ILLEGAL_REG) | |
12588 | break; | |
12589 | ||
12590 | switch (c) | |
12591 | { | |
12592 | case 'b': | |
12593 | INSERT_OPERAND (1, MB, *ip, regno); | |
12594 | break; | |
12595 | ||
12596 | case 'c': | |
12597 | INSERT_OPERAND (1, MC, *ip, regno); | |
12598 | break; | |
12599 | ||
12600 | case 'd': | |
12601 | INSERT_OPERAND (1, MD, *ip, regno); | |
12602 | break; | |
12603 | ||
12604 | case 'e': | |
12605 | INSERT_OPERAND (1, ME, *ip, regno); | |
12606 | break; | |
12607 | ||
12608 | case 'f': | |
12609 | INSERT_OPERAND (1, MF, *ip, regno); | |
12610 | break; | |
12611 | ||
12612 | case 'g': | |
12613 | INSERT_OPERAND (1, MG, *ip, regno); | |
12614 | break; | |
12615 | ||
12616 | case 'h': | |
12617 | INSERT_OPERAND (1, MH, *ip, regno); | |
12618 | break; | |
12619 | ||
12620 | case 'i': | |
12621 | INSERT_OPERAND (1, MI, *ip, regno); | |
12622 | break; | |
12623 | ||
12624 | case 'j': | |
12625 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12626 | break; | |
12627 | ||
12628 | case 'l': | |
12629 | INSERT_OPERAND (1, ML, *ip, regno); | |
12630 | break; | |
12631 | ||
12632 | case 'm': | |
12633 | INSERT_OPERAND (1, MM, *ip, regno); | |
12634 | break; | |
12635 | ||
12636 | case 'n': | |
12637 | INSERT_OPERAND (1, MN, *ip, regno); | |
12638 | break; | |
12639 | ||
12640 | case 'p': | |
12641 | INSERT_OPERAND (1, MP, *ip, regno); | |
12642 | break; | |
12643 | ||
12644 | case 'q': | |
12645 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12646 | break; | |
12647 | ||
12648 | case 'a': /* Do nothing. */ | |
12649 | case 's': /* Do nothing. */ | |
12650 | case 't': /* Do nothing. */ | |
12651 | case 'x': /* Do nothing. */ | |
12652 | case 'y': /* Do nothing. */ | |
12653 | case 'z': /* Do nothing. */ | |
12654 | break; | |
12655 | ||
12656 | default: | |
12657 | internalError (); | |
12658 | } | |
12659 | continue; | |
12660 | ||
12661 | case 'A': | |
12662 | { | |
12663 | bfd_reloc_code_real_type r[3]; | |
12664 | expressionS ep; | |
12665 | int imm; | |
12666 | ||
12667 | /* Check whether there is only a single bracketed | |
12668 | expression left. If so, it must be the base register | |
12669 | and the constant must be zero. */ | |
12670 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12671 | { | |
12672 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12673 | continue; | |
12674 | } | |
12675 | ||
12676 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12677 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12678 | break; | |
12679 | ||
12680 | imm = ep.X_add_number >> 2; | |
12681 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12682 | } | |
12683 | s = expr_end; | |
12684 | continue; | |
12685 | ||
12686 | case 'B': | |
12687 | { | |
12688 | bfd_reloc_code_real_type r[3]; | |
12689 | expressionS ep; | |
12690 | int imm; | |
12691 | ||
12692 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12693 | || ep.X_op != O_constant) | |
12694 | break; | |
12695 | ||
12696 | for (imm = 0; imm < 8; imm++) | |
12697 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12698 | break; | |
12699 | if (imm >= 8) | |
12700 | break; | |
12701 | ||
12702 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12703 | } | |
12704 | s = expr_end; | |
12705 | continue; | |
12706 | ||
12707 | case 'C': | |
12708 | { | |
12709 | bfd_reloc_code_real_type r[3]; | |
12710 | expressionS ep; | |
12711 | int imm; | |
12712 | ||
12713 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12714 | || ep.X_op != O_constant) | |
12715 | break; | |
12716 | ||
12717 | for (imm = 0; imm < 16; imm++) | |
12718 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12719 | break; | |
12720 | if (imm >= 16) | |
12721 | break; | |
12722 | ||
12723 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12724 | } | |
12725 | s = expr_end; | |
12726 | continue; | |
12727 | ||
12728 | case 'D': /* pc relative offset */ | |
12729 | case 'E': /* pc relative offset */ | |
12730 | my_getExpression (&offset_expr, s); | |
12731 | if (offset_expr.X_op == O_register) | |
12732 | break; | |
12733 | ||
40209cad MR |
12734 | if (!forced_insn_length) |
12735 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12736 | else if (c == 'D') | |
12737 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12738 | else | |
12739 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12740 | s = expr_end; |
12741 | continue; | |
12742 | ||
12743 | case 'F': | |
12744 | { | |
12745 | bfd_reloc_code_real_type r[3]; | |
12746 | expressionS ep; | |
12747 | int imm; | |
12748 | ||
12749 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12750 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12751 | break; | |
12752 | ||
12753 | imm = ep.X_add_number; | |
12754 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12755 | } | |
12756 | s = expr_end; | |
12757 | continue; | |
12758 | ||
12759 | case 'G': | |
12760 | { | |
12761 | bfd_reloc_code_real_type r[3]; | |
12762 | expressionS ep; | |
12763 | int imm; | |
12764 | ||
12765 | /* Check whether there is only a single bracketed | |
12766 | expression left. If so, it must be the base register | |
12767 | and the constant must be zero. */ | |
12768 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12769 | { | |
12770 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12771 | continue; | |
12772 | } | |
12773 | ||
12774 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12775 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12776 | break; | |
12777 | ||
12778 | imm = ep.X_add_number & 15; | |
12779 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12780 | } | |
12781 | s = expr_end; | |
12782 | continue; | |
12783 | ||
12784 | case 'H': | |
12785 | { | |
12786 | bfd_reloc_code_real_type r[3]; | |
12787 | expressionS ep; | |
12788 | int imm; | |
12789 | ||
12790 | /* Check whether there is only a single bracketed | |
12791 | expression left. If so, it must be the base register | |
12792 | and the constant must be zero. */ | |
12793 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12794 | { | |
12795 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12796 | continue; | |
12797 | } | |
12798 | ||
12799 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12800 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12801 | break; | |
12802 | ||
12803 | imm = ep.X_add_number >> 1; | |
12804 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12805 | } | |
12806 | s = expr_end; | |
12807 | continue; | |
12808 | ||
12809 | case 'I': | |
12810 | { | |
12811 | bfd_reloc_code_real_type r[3]; | |
12812 | expressionS ep; | |
12813 | int imm; | |
12814 | ||
12815 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12816 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12817 | break; | |
12818 | ||
12819 | imm = ep.X_add_number & 127; | |
12820 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12821 | } | |
12822 | s = expr_end; | |
12823 | continue; | |
12824 | ||
12825 | case 'J': | |
12826 | { | |
12827 | bfd_reloc_code_real_type r[3]; | |
12828 | expressionS ep; | |
12829 | int imm; | |
12830 | ||
12831 | /* Check whether there is only a single bracketed | |
12832 | expression left. If so, it must be the base register | |
12833 | and the constant must be zero. */ | |
12834 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12835 | { | |
12836 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12837 | continue; | |
12838 | } | |
12839 | ||
12840 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12841 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12842 | break; | |
12843 | ||
12844 | imm = ep.X_add_number >> 2; | |
12845 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12846 | } | |
12847 | s = expr_end; | |
12848 | continue; | |
12849 | ||
12850 | case 'L': | |
12851 | { | |
12852 | bfd_reloc_code_real_type r[3]; | |
12853 | expressionS ep; | |
12854 | int imm; | |
12855 | ||
12856 | /* Check whether there is only a single bracketed | |
12857 | expression left. If so, it must be the base register | |
12858 | and the constant must be zero. */ | |
12859 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12860 | { | |
12861 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12862 | continue; | |
12863 | } | |
12864 | ||
12865 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12866 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12867 | break; | |
12868 | ||
12869 | imm = ep.X_add_number; | |
12870 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12871 | } | |
12872 | s = expr_end; | |
12873 | continue; | |
12874 | ||
12875 | case 'M': | |
12876 | { | |
12877 | bfd_reloc_code_real_type r[3]; | |
12878 | expressionS ep; | |
12879 | int imm; | |
12880 | ||
12881 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12882 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12883 | break; | |
12884 | ||
12885 | imm = ep.X_add_number & 7; | |
12886 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12887 | } | |
12888 | s = expr_end; | |
12889 | continue; | |
12890 | ||
12891 | case 'N': /* Register list for lwm and swm. */ | |
12892 | { | |
12893 | /* A comma-separated list of registers and/or | |
12894 | dash-separated contiguous ranges including | |
12895 | both ra and a set of one or more registers | |
12896 | starting at s0 up to s3 which have to be | |
12897 | consecutive, e.g.: | |
12898 | ||
12899 | s0, ra | |
12900 | s0, s1, ra, s2, s3 | |
12901 | s0-s2, ra | |
12902 | ||
12903 | and any permutations of these. */ | |
12904 | unsigned int reglist; | |
12905 | int imm; | |
12906 | ||
12907 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
12908 | break; | |
12909 | ||
12910 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
12911 | break; | |
12912 | ||
12913 | reglist = (reglist >> 17) & 7; | |
12914 | reglist += 1; | |
12915 | if ((reglist & -reglist) != reglist) | |
12916 | break; | |
252b5132 | 12917 | |
df58fc94 RS |
12918 | imm = ffs (reglist) - 1; |
12919 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
12920 | } | |
12921 | continue; | |
252b5132 | 12922 | |
df58fc94 RS |
12923 | case 'O': /* sdbbp 4-bit code. */ |
12924 | { | |
12925 | bfd_reloc_code_real_type r[3]; | |
12926 | expressionS ep; | |
12927 | int imm; | |
12928 | ||
12929 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12930 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12931 | break; | |
12932 | ||
12933 | imm = ep.X_add_number; | |
12934 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 12935 | } |
df58fc94 RS |
12936 | s = expr_end; |
12937 | continue; | |
252b5132 | 12938 | |
df58fc94 RS |
12939 | case 'P': |
12940 | { | |
12941 | bfd_reloc_code_real_type r[3]; | |
12942 | expressionS ep; | |
12943 | int imm; | |
5e0116d5 | 12944 | |
df58fc94 RS |
12945 | if (my_getSmallExpression (&ep, r, s) > 0 |
12946 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12947 | break; | |
5e0116d5 | 12948 | |
df58fc94 RS |
12949 | imm = ep.X_add_number >> 2; |
12950 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
12951 | } | |
12952 | s = expr_end; | |
12953 | continue; | |
5e0116d5 | 12954 | |
df58fc94 RS |
12955 | case 'Q': |
12956 | { | |
12957 | bfd_reloc_code_real_type r[3]; | |
12958 | expressionS ep; | |
12959 | int imm; | |
5e0116d5 | 12960 | |
df58fc94 RS |
12961 | if (my_getSmallExpression (&ep, r, s) > 0 |
12962 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
12963 | break; | |
252b5132 | 12964 | |
df58fc94 RS |
12965 | imm = ep.X_add_number >> 2; |
12966 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
12967 | } | |
12968 | s = expr_end; | |
12969 | continue; | |
4614d845 | 12970 | |
df58fc94 RS |
12971 | case 'U': |
12972 | { | |
12973 | bfd_reloc_code_real_type r[3]; | |
12974 | expressionS ep; | |
12975 | int imm; | |
12976 | ||
12977 | /* Check whether there is only a single bracketed | |
12978 | expression left. If so, it must be the base register | |
12979 | and the constant must be zero. */ | |
12980 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12981 | { | |
12982 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
12983 | continue; | |
12984 | } | |
12985 | ||
12986 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12987 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12988 | break; | |
12989 | ||
12990 | imm = ep.X_add_number >> 2; | |
12991 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
12992 | } | |
12993 | s = expr_end; | |
5e0116d5 | 12994 | continue; |
252b5132 | 12995 | |
df58fc94 RS |
12996 | case 'W': |
12997 | { | |
12998 | bfd_reloc_code_real_type r[3]; | |
12999 | expressionS ep; | |
13000 | int imm; | |
252b5132 | 13001 | |
df58fc94 RS |
13002 | if (my_getSmallExpression (&ep, r, s) > 0 |
13003 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13004 | break; | |
252b5132 | 13005 | |
df58fc94 RS |
13006 | imm = ep.X_add_number >> 2; |
13007 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13008 | } | |
13009 | s = expr_end; | |
13010 | continue; | |
252b5132 | 13011 | |
df58fc94 RS |
13012 | case 'X': |
13013 | { | |
13014 | bfd_reloc_code_real_type r[3]; | |
13015 | expressionS ep; | |
13016 | int imm; | |
252b5132 | 13017 | |
df58fc94 RS |
13018 | if (my_getSmallExpression (&ep, r, s) > 0 |
13019 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13020 | break; | |
252b5132 | 13021 | |
df58fc94 RS |
13022 | imm = ep.X_add_number; |
13023 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13024 | } | |
13025 | s = expr_end; | |
13026 | continue; | |
252b5132 | 13027 | |
df58fc94 RS |
13028 | case 'Y': |
13029 | { | |
13030 | bfd_reloc_code_real_type r[3]; | |
13031 | expressionS ep; | |
13032 | int imm; | |
156c2f8b | 13033 | |
df58fc94 RS |
13034 | if (my_getSmallExpression (&ep, r, s) > 0 |
13035 | || expr_const_in_range (&ep, -2, 2, 2) | |
13036 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13037 | break; | |
156c2f8b | 13038 | |
df58fc94 RS |
13039 | imm = ep.X_add_number >> 2; |
13040 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13041 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13042 | } | |
13043 | s = expr_end; | |
13044 | continue; | |
60b63b72 | 13045 | |
df58fc94 RS |
13046 | case 'Z': |
13047 | { | |
13048 | bfd_reloc_code_real_type r[3]; | |
13049 | expressionS ep; | |
13050 | ||
13051 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13052 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13053 | break; | |
13054 | } | |
13055 | s = expr_end; | |
13056 | continue; | |
13057 | ||
13058 | default: | |
13059 | as_bad (_("Internal error: bad microMIPS opcode " | |
13060 | "(unknown extension operand type `m%c'): %s %s"), | |
13061 | *args, insn->name, insn->args); | |
13062 | /* Further processing is fruitless. */ | |
13063 | return; | |
60b63b72 | 13064 | } |
df58fc94 | 13065 | break; |
60b63b72 | 13066 | |
df58fc94 RS |
13067 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13068 | gas_assert (mips_opts.micromips); | |
13069 | { | |
13070 | /* A comma-separated list of registers and/or | |
13071 | dash-separated contiguous ranges including | |
13072 | at least one of ra and a set of one or more | |
13073 | registers starting at s0 up to s7 and then | |
13074 | s8 which have to be consecutive, e.g.: | |
13075 | ||
13076 | ra | |
13077 | s0 | |
13078 | ra, s0, s1, s2 | |
13079 | s0-s8 | |
13080 | s0-s5, ra | |
13081 | ||
13082 | and any permutations of these. */ | |
13083 | unsigned int reglist; | |
13084 | int imm; | |
13085 | int ra; | |
13086 | ||
13087 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13088 | break; | |
13089 | ||
13090 | if ((reglist & 0x3f00ffff) != 0) | |
13091 | break; | |
13092 | ||
13093 | ra = (reglist >> 27) & 0x10; | |
13094 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13095 | reglist += 1; | |
13096 | if ((reglist & -reglist) != reglist) | |
13097 | break; | |
13098 | ||
13099 | imm = (ffs (reglist) - 1) | ra; | |
13100 | INSERT_OPERAND (1, RT, *ip, imm); | |
13101 | imm_expr.X_op = O_absent; | |
13102 | } | |
60b63b72 RS |
13103 | continue; |
13104 | ||
df58fc94 RS |
13105 | case '|': /* 4-bit trap code. */ |
13106 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13107 | my_getExpression (&imm_expr, s); |
13108 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13109 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13110 | > MICROMIPSOP_MASK_TRAP) |
13111 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13112 | (unsigned long) imm_expr.X_add_number, | |
13113 | ip->insn_mo->name); | |
13114 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13115 | imm_expr.X_op = O_absent; |
13116 | s = expr_end; | |
13117 | continue; | |
13118 | ||
252b5132 | 13119 | default: |
f71d0d44 | 13120 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13121 | internalError (); |
13122 | } | |
13123 | break; | |
13124 | } | |
13125 | /* Args don't match. */ | |
df58fc94 RS |
13126 | s = argsStart; |
13127 | insn_error = _("Illegal operands"); | |
13128 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13129 | { |
13130 | ++insn; | |
252b5132 RH |
13131 | continue; |
13132 | } | |
df58fc94 RS |
13133 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13134 | { | |
13135 | gas_assert (firstinsn); | |
13136 | need_delay_slot_ok = FALSE; | |
13137 | past = insn + 1; | |
13138 | insn = firstinsn; | |
13139 | continue; | |
13140 | } | |
252b5132 RH |
13141 | return; |
13142 | } | |
13143 | } | |
13144 | ||
0499d65b TS |
13145 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13146 | ||
252b5132 RH |
13147 | /* This routine assembles an instruction into its binary format when |
13148 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13149 | global variables imm_reloc or offset_reloc to the type of relocation |
13150 | to do if one of the operands is an address expression. It also sets | |
13151 | forced_insn_length to the resulting instruction size in bytes if the | |
13152 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13153 | |
13154 | static void | |
17a2f251 | 13155 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13156 | { |
13157 | char *s; | |
13158 | const char *args; | |
13159 | struct mips_opcode *insn; | |
13160 | char *argsstart; | |
13161 | unsigned int regno; | |
13162 | unsigned int lastregno = 0; | |
13163 | char *s_reset; | |
d6f16593 | 13164 | size_t i; |
252b5132 RH |
13165 | |
13166 | insn_error = NULL; | |
13167 | ||
df58fc94 | 13168 | forced_insn_length = 0; |
252b5132 | 13169 | |
3882b010 | 13170 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13171 | ; |
13172 | switch (*s) | |
13173 | { | |
13174 | case '\0': | |
13175 | break; | |
13176 | ||
13177 | case ' ': | |
13178 | *s++ = '\0'; | |
13179 | break; | |
13180 | ||
13181 | case '.': | |
13182 | if (s[1] == 't' && s[2] == ' ') | |
13183 | { | |
13184 | *s = '\0'; | |
df58fc94 | 13185 | forced_insn_length = 2; |
252b5132 RH |
13186 | s += 3; |
13187 | break; | |
13188 | } | |
13189 | else if (s[1] == 'e' && s[2] == ' ') | |
13190 | { | |
13191 | *s = '\0'; | |
df58fc94 | 13192 | forced_insn_length = 4; |
252b5132 RH |
13193 | s += 3; |
13194 | break; | |
13195 | } | |
13196 | /* Fall through. */ | |
13197 | default: | |
13198 | insn_error = _("unknown opcode"); | |
13199 | return; | |
13200 | } | |
13201 | ||
df58fc94 RS |
13202 | if (mips_opts.noautoextend && !forced_insn_length) |
13203 | forced_insn_length = 2; | |
252b5132 RH |
13204 | |
13205 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13206 | { | |
13207 | insn_error = _("unrecognized opcode"); | |
13208 | return; | |
13209 | } | |
13210 | ||
13211 | argsstart = s; | |
13212 | for (;;) | |
13213 | { | |
9b3f89ee TS |
13214 | bfd_boolean ok; |
13215 | ||
9c2799c2 | 13216 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13217 | |
037b32b9 | 13218 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13219 | if (! ok) |
13220 | { | |
13221 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13222 | && strcmp (insn->name, insn[1].name) == 0) | |
13223 | { | |
13224 | ++insn; | |
13225 | continue; | |
13226 | } | |
13227 | else | |
13228 | { | |
13229 | if (!insn_error) | |
13230 | { | |
13231 | static char buf[100]; | |
13232 | sprintf (buf, | |
13233 | _("opcode not supported on this processor: %s (%s)"), | |
13234 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
13235 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13236 | insn_error = buf; | |
13237 | } | |
13238 | return; | |
13239 | } | |
13240 | } | |
13241 | ||
1e915849 | 13242 | create_insn (ip, insn); |
252b5132 | 13243 | imm_expr.X_op = O_absent; |
f6688943 TS |
13244 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13245 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13246 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13247 | imm2_expr.X_op = O_absent; |
252b5132 | 13248 | offset_expr.X_op = O_absent; |
f6688943 TS |
13249 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13250 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13251 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13252 | for (args = insn->args; 1; ++args) |
13253 | { | |
13254 | int c; | |
13255 | ||
13256 | if (*s == ' ') | |
13257 | ++s; | |
13258 | ||
13259 | /* In this switch statement we call break if we did not find | |
13260 | a match, continue if we did find a match, or return if we | |
13261 | are done. */ | |
13262 | ||
13263 | c = *args; | |
13264 | switch (c) | |
13265 | { | |
13266 | case '\0': | |
13267 | if (*s == '\0') | |
13268 | { | |
13269 | /* Stuff the immediate value in now, if we can. */ | |
13270 | if (imm_expr.X_op == O_constant | |
f6688943 | 13271 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13272 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13273 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13274 | && insn->pinfo != INSN_MACRO) |
13275 | { | |
d6f16593 MR |
13276 | valueT tmp; |
13277 | ||
13278 | switch (*offset_reloc) | |
13279 | { | |
13280 | case BFD_RELOC_MIPS16_HI16_S: | |
13281 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13282 | break; | |
13283 | ||
13284 | case BFD_RELOC_MIPS16_HI16: | |
13285 | tmp = imm_expr.X_add_number >> 16; | |
13286 | break; | |
13287 | ||
13288 | case BFD_RELOC_MIPS16_LO16: | |
13289 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13290 | - 0x8000; | |
13291 | break; | |
13292 | ||
13293 | case BFD_RELOC_UNUSED: | |
13294 | tmp = imm_expr.X_add_number; | |
13295 | break; | |
13296 | ||
13297 | default: | |
13298 | internalError (); | |
13299 | } | |
13300 | *offset_reloc = BFD_RELOC_UNUSED; | |
13301 | ||
c4e7957c | 13302 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
df58fc94 RS |
13303 | tmp, TRUE, forced_insn_length == 2, |
13304 | forced_insn_length == 4, &ip->insn_opcode, | |
252b5132 RH |
13305 | &ip->use_extend, &ip->extend); |
13306 | imm_expr.X_op = O_absent; | |
f6688943 | 13307 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13308 | } |
13309 | ||
13310 | return; | |
13311 | } | |
13312 | break; | |
13313 | ||
13314 | case ',': | |
13315 | if (*s++ == c) | |
13316 | continue; | |
13317 | s--; | |
13318 | switch (*++args) | |
13319 | { | |
13320 | case 'v': | |
bf12938e | 13321 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13322 | continue; |
13323 | case 'w': | |
bf12938e | 13324 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13325 | continue; |
13326 | } | |
13327 | break; | |
13328 | ||
13329 | case '(': | |
13330 | case ')': | |
13331 | if (*s++ == c) | |
13332 | continue; | |
13333 | break; | |
13334 | ||
13335 | case 'v': | |
13336 | case 'w': | |
13337 | if (s[0] != '$') | |
13338 | { | |
13339 | if (c == 'v') | |
bf12938e | 13340 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13341 | else |
bf12938e | 13342 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13343 | ++args; |
13344 | continue; | |
13345 | } | |
13346 | /* Fall through. */ | |
13347 | case 'x': | |
13348 | case 'y': | |
13349 | case 'z': | |
13350 | case 'Z': | |
13351 | case '0': | |
13352 | case 'S': | |
13353 | case 'R': | |
13354 | case 'X': | |
13355 | case 'Y': | |
707bfff6 TS |
13356 | s_reset = s; |
13357 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13358 | { |
707bfff6 | 13359 | if (c == 'v' || c == 'w') |
85b51719 | 13360 | { |
707bfff6 | 13361 | if (c == 'v') |
a9e24354 | 13362 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13363 | else |
a9e24354 | 13364 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13365 | ++args; |
13366 | continue; | |
85b51719 | 13367 | } |
707bfff6 | 13368 | break; |
252b5132 RH |
13369 | } |
13370 | ||
13371 | if (*s == ' ') | |
13372 | ++s; | |
13373 | if (args[1] != *s) | |
13374 | { | |
13375 | if (c == 'v' || c == 'w') | |
13376 | { | |
13377 | regno = mips16_to_32_reg_map[lastregno]; | |
13378 | s = s_reset; | |
f9419b05 | 13379 | ++args; |
252b5132 RH |
13380 | } |
13381 | } | |
13382 | ||
13383 | switch (c) | |
13384 | { | |
13385 | case 'x': | |
13386 | case 'y': | |
13387 | case 'z': | |
13388 | case 'v': | |
13389 | case 'w': | |
13390 | case 'Z': | |
13391 | regno = mips32_to_16_reg_map[regno]; | |
13392 | break; | |
13393 | ||
13394 | case '0': | |
13395 | if (regno != 0) | |
13396 | regno = ILLEGAL_REG; | |
13397 | break; | |
13398 | ||
13399 | case 'S': | |
13400 | if (regno != SP) | |
13401 | regno = ILLEGAL_REG; | |
13402 | break; | |
13403 | ||
13404 | case 'R': | |
13405 | if (regno != RA) | |
13406 | regno = ILLEGAL_REG; | |
13407 | break; | |
13408 | ||
13409 | case 'X': | |
13410 | case 'Y': | |
741fe287 MR |
13411 | if (regno == AT && mips_opts.at) |
13412 | { | |
13413 | if (mips_opts.at == ATREG) | |
13414 | as_warn (_("used $at without \".set noat\"")); | |
13415 | else | |
13416 | as_warn (_("used $%u with \".set at=$%u\""), | |
13417 | regno, mips_opts.at); | |
13418 | } | |
252b5132 RH |
13419 | break; |
13420 | ||
13421 | default: | |
13422 | internalError (); | |
13423 | } | |
13424 | ||
13425 | if (regno == ILLEGAL_REG) | |
13426 | break; | |
13427 | ||
13428 | switch (c) | |
13429 | { | |
13430 | case 'x': | |
13431 | case 'v': | |
bf12938e | 13432 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13433 | break; |
13434 | case 'y': | |
13435 | case 'w': | |
bf12938e | 13436 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13437 | break; |
13438 | case 'z': | |
bf12938e | 13439 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13440 | break; |
13441 | case 'Z': | |
bf12938e | 13442 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13443 | case '0': |
13444 | case 'S': | |
13445 | case 'R': | |
13446 | break; | |
13447 | case 'X': | |
bf12938e | 13448 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13449 | break; |
13450 | case 'Y': | |
13451 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13452 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13453 | break; |
13454 | default: | |
13455 | internalError (); | |
13456 | } | |
13457 | ||
13458 | lastregno = regno; | |
13459 | continue; | |
13460 | ||
13461 | case 'P': | |
13462 | if (strncmp (s, "$pc", 3) == 0) | |
13463 | { | |
13464 | s += 3; | |
13465 | continue; | |
13466 | } | |
13467 | break; | |
13468 | ||
252b5132 RH |
13469 | case '5': |
13470 | case 'H': | |
13471 | case 'W': | |
13472 | case 'D': | |
13473 | case 'j': | |
252b5132 RH |
13474 | case 'V': |
13475 | case 'C': | |
13476 | case 'U': | |
13477 | case 'k': | |
13478 | case 'K': | |
d6f16593 MR |
13479 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13480 | if (i > 0) | |
252b5132 | 13481 | { |
d6f16593 | 13482 | if (imm_expr.X_op != O_constant) |
252b5132 | 13483 | { |
df58fc94 | 13484 | forced_insn_length = 4; |
b34976b6 | 13485 | ip->use_extend = TRUE; |
252b5132 | 13486 | ip->extend = 0; |
252b5132 | 13487 | } |
d6f16593 MR |
13488 | else |
13489 | { | |
13490 | /* We need to relax this instruction. */ | |
13491 | *offset_reloc = *imm_reloc; | |
13492 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13493 | } | |
13494 | s = expr_end; | |
13495 | continue; | |
252b5132 | 13496 | } |
d6f16593 MR |
13497 | *imm_reloc = BFD_RELOC_UNUSED; |
13498 | /* Fall through. */ | |
13499 | case '<': | |
13500 | case '>': | |
13501 | case '[': | |
13502 | case ']': | |
13503 | case '4': | |
13504 | case '8': | |
13505 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13506 | if (imm_expr.X_op == O_register) |
13507 | { | |
13508 | /* What we thought was an expression turned out to | |
13509 | be a register. */ | |
13510 | ||
13511 | if (s[0] == '(' && args[1] == '(') | |
13512 | { | |
13513 | /* It looks like the expression was omitted | |
13514 | before a register indirection, which means | |
13515 | that the expression is implicitly zero. We | |
13516 | still set up imm_expr, so that we handle | |
13517 | explicit extensions correctly. */ | |
13518 | imm_expr.X_op = O_constant; | |
13519 | imm_expr.X_add_number = 0; | |
f6688943 | 13520 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13521 | continue; |
13522 | } | |
13523 | ||
13524 | break; | |
13525 | } | |
13526 | ||
13527 | /* We need to relax this instruction. */ | |
f6688943 | 13528 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13529 | s = expr_end; |
13530 | continue; | |
13531 | ||
13532 | case 'p': | |
13533 | case 'q': | |
13534 | case 'A': | |
13535 | case 'B': | |
13536 | case 'E': | |
13537 | /* We use offset_reloc rather than imm_reloc for the PC | |
13538 | relative operands. This lets macros with both | |
13539 | immediate and address operands work correctly. */ | |
13540 | my_getExpression (&offset_expr, s); | |
13541 | ||
13542 | if (offset_expr.X_op == O_register) | |
13543 | break; | |
13544 | ||
13545 | /* We need to relax this instruction. */ | |
f6688943 | 13546 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13547 | s = expr_end; |
13548 | continue; | |
13549 | ||
13550 | case '6': /* break code */ | |
13551 | my_getExpression (&imm_expr, s); | |
13552 | check_absolute_expr (ip, &imm_expr); | |
13553 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13554 | as_warn (_("Invalid value for `%s' (%lu)"), |
13555 | ip->insn_mo->name, | |
13556 | (unsigned long) imm_expr.X_add_number); | |
13557 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13558 | imm_expr.X_op = O_absent; |
13559 | s = expr_end; | |
13560 | continue; | |
13561 | ||
13562 | case 'a': /* 26 bit address */ | |
13563 | my_getExpression (&offset_expr, s); | |
13564 | s = expr_end; | |
f6688943 | 13565 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13566 | ip->insn_opcode <<= 16; |
13567 | continue; | |
13568 | ||
13569 | case 'l': /* register list for entry macro */ | |
13570 | case 'L': /* register list for exit macro */ | |
13571 | { | |
13572 | int mask; | |
13573 | ||
13574 | if (c == 'l') | |
13575 | mask = 0; | |
13576 | else | |
13577 | mask = 7 << 3; | |
13578 | while (*s != '\0') | |
13579 | { | |
707bfff6 | 13580 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13581 | |
13582 | while (*s == ' ' || *s == ',') | |
13583 | ++s; | |
707bfff6 | 13584 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13585 | freg = 0; |
707bfff6 TS |
13586 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13587 | freg = 1; | |
252b5132 RH |
13588 | else |
13589 | { | |
707bfff6 TS |
13590 | as_bad (_("can't parse register list")); |
13591 | break; | |
252b5132 RH |
13592 | } |
13593 | if (*s == ' ') | |
13594 | ++s; | |
13595 | if (*s != '-') | |
13596 | reg2 = reg1; | |
13597 | else | |
13598 | { | |
13599 | ++s; | |
707bfff6 TS |
13600 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13601 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13602 | { |
707bfff6 TS |
13603 | as_bad (_("invalid register list")); |
13604 | break; | |
252b5132 RH |
13605 | } |
13606 | } | |
13607 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13608 | { | |
13609 | mask &= ~ (7 << 3); | |
13610 | mask |= 5 << 3; | |
13611 | } | |
13612 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13613 | { | |
13614 | mask &= ~ (7 << 3); | |
13615 | mask |= 6 << 3; | |
13616 | } | |
13617 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13618 | mask |= (reg2 - 3) << 3; | |
13619 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13620 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13621 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13622 | mask |= 1; |
13623 | else | |
13624 | { | |
13625 | as_bad (_("invalid register list")); | |
13626 | break; | |
13627 | } | |
13628 | } | |
13629 | /* The mask is filled in in the opcode table for the | |
13630 | benefit of the disassembler. We remove it before | |
13631 | applying the actual mask. */ | |
13632 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13633 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13634 | } | |
13635 | continue; | |
13636 | ||
0499d65b TS |
13637 | case 'm': /* Register list for save insn. */ |
13638 | case 'M': /* Register list for restore insn. */ | |
13639 | { | |
13640 | int opcode = 0; | |
13641 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 13642 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13643 | |
13644 | while (*s != '\0') | |
13645 | { | |
13646 | unsigned int reg1, reg2; | |
13647 | ||
13648 | SKIP_SPACE_TABS (s); | |
13649 | while (*s == ',') | |
13650 | ++s; | |
13651 | SKIP_SPACE_TABS (s); | |
13652 | ||
13653 | my_getExpression (&imm_expr, s); | |
13654 | if (imm_expr.X_op == O_constant) | |
13655 | { | |
13656 | /* Handle the frame size. */ | |
13657 | if (seen_framesz) | |
13658 | { | |
13659 | as_bad (_("more than one frame size in list")); | |
13660 | break; | |
13661 | } | |
13662 | seen_framesz = 1; | |
13663 | framesz = imm_expr.X_add_number; | |
13664 | imm_expr.X_op = O_absent; | |
13665 | s = expr_end; | |
13666 | continue; | |
13667 | } | |
13668 | ||
707bfff6 | 13669 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13670 | { |
13671 | as_bad (_("can't parse register list")); | |
13672 | break; | |
13673 | } | |
0499d65b | 13674 | |
707bfff6 TS |
13675 | while (*s == ' ') |
13676 | ++s; | |
13677 | ||
0499d65b TS |
13678 | if (*s != '-') |
13679 | reg2 = reg1; | |
13680 | else | |
13681 | { | |
13682 | ++s; | |
707bfff6 TS |
13683 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13684 | || reg2 < reg1) | |
0499d65b TS |
13685 | { |
13686 | as_bad (_("can't parse register list")); | |
13687 | break; | |
13688 | } | |
0499d65b TS |
13689 | } |
13690 | ||
13691 | while (reg1 <= reg2) | |
13692 | { | |
13693 | if (reg1 >= 4 && reg1 <= 7) | |
13694 | { | |
3a93f742 | 13695 | if (!seen_framesz) |
0499d65b | 13696 | /* args $a0-$a3 */ |
91d6fa6a | 13697 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13698 | else |
13699 | /* statics $a0-$a3 */ | |
13700 | statics |= 1 << (reg1 - 4); | |
13701 | } | |
13702 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13703 | { | |
13704 | /* $s0-$s8 */ | |
13705 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13706 | } | |
13707 | else if (reg1 == 31) | |
13708 | { | |
13709 | /* Add $ra to insn. */ | |
13710 | opcode |= 0x40; | |
13711 | } | |
13712 | else | |
13713 | { | |
13714 | as_bad (_("unexpected register in list")); | |
13715 | break; | |
13716 | } | |
13717 | if (++reg1 == 24) | |
13718 | reg1 = 30; | |
13719 | } | |
13720 | } | |
13721 | ||
13722 | /* Encode args/statics combination. */ | |
91d6fa6a | 13723 | if (nargs & statics) |
0499d65b | 13724 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13725 | else if (nargs == 0xf) |
0499d65b TS |
13726 | /* All $a0-$a3 are args. */ |
13727 | opcode |= MIPS16_ALL_ARGS << 16; | |
13728 | else if (statics == 0xf) | |
13729 | /* All $a0-$a3 are statics. */ | |
13730 | opcode |= MIPS16_ALL_STATICS << 16; | |
13731 | else | |
13732 | { | |
13733 | int narg = 0, nstat = 0; | |
13734 | ||
13735 | /* Count arg registers. */ | |
91d6fa6a | 13736 | while (nargs & 0x1) |
0499d65b | 13737 | { |
91d6fa6a | 13738 | nargs >>= 1; |
0499d65b TS |
13739 | narg++; |
13740 | } | |
91d6fa6a | 13741 | if (nargs != 0) |
0499d65b TS |
13742 | as_bad (_("invalid arg register list")); |
13743 | ||
13744 | /* Count static registers. */ | |
13745 | while (statics & 0x8) | |
13746 | { | |
13747 | statics = (statics << 1) & 0xf; | |
13748 | nstat++; | |
13749 | } | |
13750 | if (statics != 0) | |
13751 | as_bad (_("invalid static register list")); | |
13752 | ||
13753 | /* Encode args/statics. */ | |
13754 | opcode |= ((narg << 2) | nstat) << 16; | |
13755 | } | |
13756 | ||
13757 | /* Encode $s0/$s1. */ | |
13758 | if (sregs & (1 << 0)) /* $s0 */ | |
13759 | opcode |= 0x20; | |
13760 | if (sregs & (1 << 1)) /* $s1 */ | |
13761 | opcode |= 0x10; | |
13762 | sregs >>= 2; | |
13763 | ||
13764 | if (sregs != 0) | |
13765 | { | |
13766 | /* Count regs $s2-$s8. */ | |
13767 | int nsreg = 0; | |
13768 | while (sregs & 1) | |
13769 | { | |
13770 | sregs >>= 1; | |
13771 | nsreg++; | |
13772 | } | |
13773 | if (sregs != 0) | |
13774 | as_bad (_("invalid static register list")); | |
13775 | /* Encode $s2-$s8. */ | |
13776 | opcode |= nsreg << 24; | |
13777 | } | |
13778 | ||
13779 | /* Encode frame size. */ | |
13780 | if (!seen_framesz) | |
13781 | as_bad (_("missing frame size")); | |
13782 | else if ((framesz & 7) != 0 || framesz < 0 | |
13783 | || framesz > 0xff * 8) | |
13784 | as_bad (_("invalid frame size")); | |
13785 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13786 | { | |
13787 | framesz /= 8; | |
13788 | opcode |= (((framesz & 0xf0) << 16) | |
13789 | | (framesz & 0x0f)); | |
13790 | } | |
13791 | ||
13792 | /* Finally build the instruction. */ | |
13793 | if ((opcode >> 16) != 0 || framesz == 0) | |
13794 | { | |
13795 | ip->use_extend = TRUE; | |
13796 | ip->extend = opcode >> 16; | |
13797 | } | |
13798 | ip->insn_opcode |= opcode & 0x7f; | |
13799 | } | |
13800 | continue; | |
13801 | ||
252b5132 RH |
13802 | case 'e': /* extend code */ |
13803 | my_getExpression (&imm_expr, s); | |
13804 | check_absolute_expr (ip, &imm_expr); | |
13805 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13806 | { | |
13807 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13808 | ip->insn_mo->name, | |
13809 | (unsigned long) imm_expr.X_add_number); | |
13810 | imm_expr.X_add_number &= 0x7ff; | |
13811 | } | |
13812 | ip->insn_opcode |= imm_expr.X_add_number; | |
13813 | imm_expr.X_op = O_absent; | |
13814 | s = expr_end; | |
13815 | continue; | |
13816 | ||
13817 | default: | |
13818 | internalError (); | |
13819 | } | |
13820 | break; | |
13821 | } | |
13822 | ||
13823 | /* Args don't match. */ | |
13824 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13825 | strcmp (insn->name, insn[1].name) == 0) | |
13826 | { | |
13827 | ++insn; | |
13828 | s = argsstart; | |
13829 | continue; | |
13830 | } | |
13831 | ||
13832 | insn_error = _("illegal operands"); | |
13833 | ||
13834 | return; | |
13835 | } | |
13836 | } | |
13837 | ||
13838 | /* This structure holds information we know about a mips16 immediate | |
13839 | argument type. */ | |
13840 | ||
e972090a NC |
13841 | struct mips16_immed_operand |
13842 | { | |
252b5132 RH |
13843 | /* The type code used in the argument string in the opcode table. */ |
13844 | int type; | |
13845 | /* The number of bits in the short form of the opcode. */ | |
13846 | int nbits; | |
13847 | /* The number of bits in the extended form of the opcode. */ | |
13848 | int extbits; | |
13849 | /* The amount by which the short form is shifted when it is used; | |
13850 | for example, the sw instruction has a shift count of 2. */ | |
13851 | int shift; | |
13852 | /* The amount by which the short form is shifted when it is stored | |
13853 | into the instruction code. */ | |
13854 | int op_shift; | |
13855 | /* Non-zero if the short form is unsigned. */ | |
13856 | int unsp; | |
13857 | /* Non-zero if the extended form is unsigned. */ | |
13858 | int extu; | |
13859 | /* Non-zero if the value is PC relative. */ | |
13860 | int pcrel; | |
13861 | }; | |
13862 | ||
13863 | /* The mips16 immediate operand types. */ | |
13864 | ||
13865 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13866 | { | |
13867 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13868 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13869 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13870 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13871 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13872 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13873 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13874 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13875 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13876 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13877 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13878 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13879 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13880 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13881 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13882 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13883 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13884 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13885 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13886 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13887 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13888 | }; | |
13889 | ||
13890 | #define MIPS16_NUM_IMMED \ | |
13891 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13892 | ||
13893 | /* Handle a mips16 instruction with an immediate value. This or's the | |
13894 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
13895 | whether an extended value is needed; if one is needed, it sets | |
13896 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
13897 | If SMALL is true, an unextended opcode was explicitly requested. | |
13898 | If EXT is true, an extended opcode was explicitly requested. If | |
13899 | WARN is true, warn if EXT does not match reality. */ | |
13900 | ||
13901 | static void | |
17a2f251 TS |
13902 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
13903 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
13904 | unsigned long *insn, bfd_boolean *use_extend, | |
13905 | unsigned short *extend) | |
252b5132 | 13906 | { |
3994f87e | 13907 | const struct mips16_immed_operand *op; |
252b5132 | 13908 | int mintiny, maxtiny; |
b34976b6 | 13909 | bfd_boolean needext; |
252b5132 RH |
13910 | |
13911 | op = mips16_immed_operands; | |
13912 | while (op->type != type) | |
13913 | { | |
13914 | ++op; | |
9c2799c2 | 13915 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13916 | } |
13917 | ||
13918 | if (op->unsp) | |
13919 | { | |
13920 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13921 | { | |
13922 | mintiny = 1; | |
13923 | maxtiny = 1 << op->nbits; | |
13924 | } | |
13925 | else | |
13926 | { | |
13927 | mintiny = 0; | |
13928 | maxtiny = (1 << op->nbits) - 1; | |
13929 | } | |
13930 | } | |
13931 | else | |
13932 | { | |
13933 | mintiny = - (1 << (op->nbits - 1)); | |
13934 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13935 | } | |
13936 | ||
13937 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13938 | if (type == 'p' || type == 'q') | |
13939 | val /= 2; | |
13940 | ||
13941 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13942 | || val < (mintiny << op->shift) | |
13943 | || val > (maxtiny << op->shift)) | |
b34976b6 | 13944 | needext = TRUE; |
252b5132 | 13945 | else |
b34976b6 | 13946 | needext = FALSE; |
252b5132 RH |
13947 | |
13948 | if (warn && ext && ! needext) | |
beae10d5 KH |
13949 | as_warn_where (file, line, |
13950 | _("extended operand requested but not required")); | |
252b5132 RH |
13951 | if (small && needext) |
13952 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13953 | ||
13954 | if (small || (! ext && ! needext)) | |
13955 | { | |
13956 | int insnval; | |
13957 | ||
b34976b6 | 13958 | *use_extend = FALSE; |
252b5132 RH |
13959 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
13960 | insnval <<= op->op_shift; | |
13961 | *insn |= insnval; | |
13962 | } | |
13963 | else | |
13964 | { | |
13965 | long minext, maxext; | |
13966 | int extval; | |
13967 | ||
13968 | if (op->extu) | |
13969 | { | |
13970 | minext = 0; | |
13971 | maxext = (1 << op->extbits) - 1; | |
13972 | } | |
13973 | else | |
13974 | { | |
13975 | minext = - (1 << (op->extbits - 1)); | |
13976 | maxext = (1 << (op->extbits - 1)) - 1; | |
13977 | } | |
13978 | if (val < minext || val > maxext) | |
13979 | as_bad_where (file, line, | |
13980 | _("operand value out of range for instruction")); | |
13981 | ||
b34976b6 | 13982 | *use_extend = TRUE; |
252b5132 RH |
13983 | if (op->extbits == 16) |
13984 | { | |
13985 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13986 | val &= 0x1f; | |
13987 | } | |
13988 | else if (op->extbits == 15) | |
13989 | { | |
13990 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13991 | val &= 0xf; | |
13992 | } | |
13993 | else | |
13994 | { | |
13995 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13996 | val = 0; | |
13997 | } | |
13998 | ||
13999 | *extend = (unsigned short) extval; | |
14000 | *insn |= val; | |
14001 | } | |
14002 | } | |
14003 | \f | |
d6f16593 | 14004 | struct percent_op_match |
ad8d3bb3 | 14005 | { |
5e0116d5 RS |
14006 | const char *str; |
14007 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14008 | }; |
14009 | ||
14010 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14011 | { |
5e0116d5 | 14012 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14013 | #ifdef OBJ_ELF |
5e0116d5 RS |
14014 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14015 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14016 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14017 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14018 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14019 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14020 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14021 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14022 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14023 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14024 | {"%half", BFD_RELOC_16}, | |
14025 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14026 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14027 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14028 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14029 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14030 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14031 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14032 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14033 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14034 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14035 | #endif |
5e0116d5 | 14036 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14037 | }; |
14038 | ||
d6f16593 MR |
14039 | static const struct percent_op_match mips16_percent_op[] = |
14040 | { | |
14041 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14042 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14043 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14044 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
14045 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
14046 | }; | |
14047 | ||
252b5132 | 14048 | |
5e0116d5 RS |
14049 | /* Return true if *STR points to a relocation operator. When returning true, |
14050 | move *STR over the operator and store its relocation code in *RELOC. | |
14051 | Leave both *STR and *RELOC alone when returning false. */ | |
14052 | ||
14053 | static bfd_boolean | |
17a2f251 | 14054 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14055 | { |
d6f16593 MR |
14056 | const struct percent_op_match *percent_op; |
14057 | size_t limit, i; | |
14058 | ||
14059 | if (mips_opts.mips16) | |
14060 | { | |
14061 | percent_op = mips16_percent_op; | |
14062 | limit = ARRAY_SIZE (mips16_percent_op); | |
14063 | } | |
14064 | else | |
14065 | { | |
14066 | percent_op = mips_percent_op; | |
14067 | limit = ARRAY_SIZE (mips_percent_op); | |
14068 | } | |
76b3015f | 14069 | |
d6f16593 | 14070 | for (i = 0; i < limit; i++) |
5e0116d5 | 14071 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14072 | { |
3f98094e DJ |
14073 | int len = strlen (percent_op[i].str); |
14074 | ||
14075 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14076 | continue; | |
14077 | ||
5e0116d5 RS |
14078 | *str += strlen (percent_op[i].str); |
14079 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14080 | |
5e0116d5 RS |
14081 | /* Check whether the output BFD supports this relocation. |
14082 | If not, issue an error and fall back on something safe. */ | |
14083 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14084 | { |
20203fb9 | 14085 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14086 | percent_op[i].str); |
01a3f561 | 14087 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14088 | } |
5e0116d5 | 14089 | return TRUE; |
394f9b3a | 14090 | } |
5e0116d5 | 14091 | return FALSE; |
394f9b3a | 14092 | } |
ad8d3bb3 | 14093 | |
ad8d3bb3 | 14094 | |
5e0116d5 RS |
14095 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14096 | expression in *EP and the relocations in the array starting | |
14097 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14098 | |
01a3f561 | 14099 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14100 | |
5e0116d5 | 14101 | static size_t |
17a2f251 TS |
14102 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14103 | char *str) | |
ad8d3bb3 | 14104 | { |
5e0116d5 RS |
14105 | bfd_reloc_code_real_type reversed_reloc[3]; |
14106 | size_t reloc_index, i; | |
09b8f35a RS |
14107 | int crux_depth, str_depth; |
14108 | char *crux; | |
5e0116d5 RS |
14109 | |
14110 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14111 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14112 | of the main expression and with CRUX_DEPTH containing the number | |
14113 | of open brackets at that point. */ | |
14114 | reloc_index = -1; | |
14115 | str_depth = 0; | |
14116 | do | |
fb1b3232 | 14117 | { |
09b8f35a RS |
14118 | reloc_index++; |
14119 | crux = str; | |
14120 | crux_depth = str_depth; | |
14121 | ||
14122 | /* Skip over whitespace and brackets, keeping count of the number | |
14123 | of brackets. */ | |
14124 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14125 | if (*str++ == '(') | |
14126 | str_depth++; | |
5e0116d5 | 14127 | } |
09b8f35a RS |
14128 | while (*str == '%' |
14129 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14130 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14131 | |
09b8f35a | 14132 | my_getExpression (ep, crux); |
5e0116d5 | 14133 | str = expr_end; |
394f9b3a | 14134 | |
5e0116d5 | 14135 | /* Match every open bracket. */ |
09b8f35a | 14136 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14137 | if (*str++ == ')') |
09b8f35a | 14138 | crux_depth--; |
394f9b3a | 14139 | |
09b8f35a | 14140 | if (crux_depth > 0) |
20203fb9 | 14141 | as_bad (_("unclosed '('")); |
394f9b3a | 14142 | |
5e0116d5 | 14143 | expr_end = str; |
252b5132 | 14144 | |
01a3f561 | 14145 | if (reloc_index != 0) |
64bdfcaf RS |
14146 | { |
14147 | prev_reloc_op_frag = frag_now; | |
14148 | for (i = 0; i < reloc_index; i++) | |
14149 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14150 | } | |
fb1b3232 | 14151 | |
5e0116d5 | 14152 | return reloc_index; |
252b5132 RH |
14153 | } |
14154 | ||
14155 | static void | |
17a2f251 | 14156 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14157 | { |
14158 | char *save_in; | |
14159 | ||
14160 | save_in = input_line_pointer; | |
14161 | input_line_pointer = str; | |
14162 | expression (ep); | |
14163 | expr_end = input_line_pointer; | |
14164 | input_line_pointer = save_in; | |
252b5132 RH |
14165 | } |
14166 | ||
252b5132 | 14167 | char * |
17a2f251 | 14168 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14169 | { |
499ac353 | 14170 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14171 | } |
14172 | ||
14173 | void | |
17a2f251 | 14174 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14175 | { |
14176 | if (target_big_endian) | |
14177 | number_to_chars_bigendian (buf, val, n); | |
14178 | else | |
14179 | number_to_chars_littleendian (buf, val, n); | |
14180 | } | |
14181 | \f | |
ae948b86 | 14182 | #ifdef OBJ_ELF |
e013f690 TS |
14183 | static int support_64bit_objects(void) |
14184 | { | |
14185 | const char **list, **l; | |
aa3d8fdf | 14186 | int yes; |
e013f690 TS |
14187 | |
14188 | list = bfd_target_list (); | |
14189 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14190 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14191 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14192 | break; |
aa3d8fdf | 14193 | yes = (*l != NULL); |
e013f690 | 14194 | free (list); |
aa3d8fdf | 14195 | return yes; |
e013f690 | 14196 | } |
ae948b86 | 14197 | #endif /* OBJ_ELF */ |
e013f690 | 14198 | |
78849248 | 14199 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14200 | |
23fce1e3 NC |
14201 | enum options |
14202 | { | |
14203 | OPTION_MARCH = OPTION_MD_BASE, | |
14204 | OPTION_MTUNE, | |
14205 | OPTION_MIPS1, | |
14206 | OPTION_MIPS2, | |
14207 | OPTION_MIPS3, | |
14208 | OPTION_MIPS4, | |
14209 | OPTION_MIPS5, | |
14210 | OPTION_MIPS32, | |
14211 | OPTION_MIPS64, | |
14212 | OPTION_MIPS32R2, | |
14213 | OPTION_MIPS64R2, | |
14214 | OPTION_MIPS16, | |
14215 | OPTION_NO_MIPS16, | |
14216 | OPTION_MIPS3D, | |
14217 | OPTION_NO_MIPS3D, | |
14218 | OPTION_MDMX, | |
14219 | OPTION_NO_MDMX, | |
14220 | OPTION_DSP, | |
14221 | OPTION_NO_DSP, | |
14222 | OPTION_MT, | |
14223 | OPTION_NO_MT, | |
14224 | OPTION_SMARTMIPS, | |
14225 | OPTION_NO_SMARTMIPS, | |
14226 | OPTION_DSPR2, | |
14227 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14228 | OPTION_MICROMIPS, |
14229 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14230 | OPTION_MCU, |
14231 | OPTION_NO_MCU, | |
23fce1e3 NC |
14232 | OPTION_COMPAT_ARCH_BASE, |
14233 | OPTION_M4650, | |
14234 | OPTION_NO_M4650, | |
14235 | OPTION_M4010, | |
14236 | OPTION_NO_M4010, | |
14237 | OPTION_M4100, | |
14238 | OPTION_NO_M4100, | |
14239 | OPTION_M3900, | |
14240 | OPTION_NO_M3900, | |
14241 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14242 | OPTION_MNO_7000_HILO_FIX, |
14243 | OPTION_FIX_24K, | |
14244 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14245 | OPTION_FIX_LOONGSON2F_JUMP, |
14246 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14247 | OPTION_FIX_LOONGSON2F_NOP, | |
14248 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14249 | OPTION_FIX_VR4120, |
14250 | OPTION_NO_FIX_VR4120, | |
14251 | OPTION_FIX_VR4130, | |
14252 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14253 | OPTION_FIX_CN63XXP1, |
14254 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14255 | OPTION_TRAP, |
14256 | OPTION_BREAK, | |
14257 | OPTION_EB, | |
14258 | OPTION_EL, | |
14259 | OPTION_FP32, | |
14260 | OPTION_GP32, | |
14261 | OPTION_CONSTRUCT_FLOATS, | |
14262 | OPTION_NO_CONSTRUCT_FLOATS, | |
14263 | OPTION_FP64, | |
14264 | OPTION_GP64, | |
14265 | OPTION_RELAX_BRANCH, | |
14266 | OPTION_NO_RELAX_BRANCH, | |
14267 | OPTION_MSHARED, | |
14268 | OPTION_MNO_SHARED, | |
14269 | OPTION_MSYM32, | |
14270 | OPTION_MNO_SYM32, | |
14271 | OPTION_SOFT_FLOAT, | |
14272 | OPTION_HARD_FLOAT, | |
14273 | OPTION_SINGLE_FLOAT, | |
14274 | OPTION_DOUBLE_FLOAT, | |
14275 | OPTION_32, | |
14276 | #ifdef OBJ_ELF | |
14277 | OPTION_CALL_SHARED, | |
14278 | OPTION_CALL_NONPIC, | |
14279 | OPTION_NON_SHARED, | |
14280 | OPTION_XGOT, | |
14281 | OPTION_MABI, | |
14282 | OPTION_N32, | |
14283 | OPTION_64, | |
14284 | OPTION_MDEBUG, | |
14285 | OPTION_NO_MDEBUG, | |
14286 | OPTION_PDR, | |
14287 | OPTION_NO_PDR, | |
14288 | OPTION_MVXWORKS_PIC, | |
14289 | #endif /* OBJ_ELF */ | |
14290 | OPTION_END_OF_ENUM | |
14291 | }; | |
14292 | ||
e972090a NC |
14293 | struct option md_longopts[] = |
14294 | { | |
f9b4148d | 14295 | /* Options which specify architecture. */ |
f9b4148d | 14296 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14297 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14298 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14299 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14300 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14301 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14302 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14303 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14304 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14305 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14306 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14307 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14308 | |
14309 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14310 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14311 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14312 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14313 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14314 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14315 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14316 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14317 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14318 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14319 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14320 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14321 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14322 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14323 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14324 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14325 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14326 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14327 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14328 | |
14329 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14330 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14331 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14332 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14333 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14334 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14335 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14336 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14337 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14338 | ||
14339 | /* Options which enable bug fixes. */ | |
f9b4148d | 14340 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14341 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14342 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14343 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14344 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14345 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14346 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14347 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14348 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14349 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14350 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14351 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14352 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14353 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14354 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14355 | |
14356 | /* Miscellaneous options. */ | |
252b5132 RH |
14357 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14358 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14359 | {"break", no_argument, NULL, OPTION_BREAK}, |
14360 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14361 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14362 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14363 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14364 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14365 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14366 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14367 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14368 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14369 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14370 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14371 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14372 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14373 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14374 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14375 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14376 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14377 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14378 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14379 | |
14380 | /* Strictly speaking this next option is ELF specific, | |
14381 | but we allow it for other ports as well in order to | |
14382 | make testing easier. */ | |
14383 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14384 | |
f9b4148d | 14385 | /* ELF-specific options. */ |
156c2f8b | 14386 | #ifdef OBJ_ELF |
156c2f8b NC |
14387 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14388 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14389 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14390 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14391 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14392 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14393 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14394 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14395 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14396 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14397 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14398 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14399 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14400 | #endif /* OBJ_ELF */ |
f9b4148d | 14401 | |
252b5132 RH |
14402 | {NULL, no_argument, NULL, 0} |
14403 | }; | |
156c2f8b | 14404 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14405 | |
316f5878 RS |
14406 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14407 | NEW_VALUE. Warn if another value was already specified. Note: | |
14408 | we have to defer parsing the -march and -mtune arguments in order | |
14409 | to handle 'from-abi' correctly, since the ABI might be specified | |
14410 | in a later argument. */ | |
14411 | ||
14412 | static void | |
17a2f251 | 14413 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14414 | { |
14415 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14416 | as_warn (_("A different %s was already specified, is now %s"), | |
14417 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14418 | new_value); | |
14419 | ||
14420 | *string_ptr = new_value; | |
14421 | } | |
14422 | ||
252b5132 | 14423 | int |
17a2f251 | 14424 | md_parse_option (int c, char *arg) |
252b5132 RH |
14425 | { |
14426 | switch (c) | |
14427 | { | |
119d663a NC |
14428 | case OPTION_CONSTRUCT_FLOATS: |
14429 | mips_disable_float_construction = 0; | |
14430 | break; | |
bdaaa2e1 | 14431 | |
119d663a NC |
14432 | case OPTION_NO_CONSTRUCT_FLOATS: |
14433 | mips_disable_float_construction = 1; | |
14434 | break; | |
bdaaa2e1 | 14435 | |
252b5132 RH |
14436 | case OPTION_TRAP: |
14437 | mips_trap = 1; | |
14438 | break; | |
14439 | ||
14440 | case OPTION_BREAK: | |
14441 | mips_trap = 0; | |
14442 | break; | |
14443 | ||
14444 | case OPTION_EB: | |
14445 | target_big_endian = 1; | |
14446 | break; | |
14447 | ||
14448 | case OPTION_EL: | |
14449 | target_big_endian = 0; | |
14450 | break; | |
14451 | ||
14452 | case 'O': | |
4ffff32f TS |
14453 | if (arg == NULL) |
14454 | mips_optimize = 1; | |
14455 | else if (arg[0] == '0') | |
14456 | mips_optimize = 0; | |
14457 | else if (arg[0] == '1') | |
252b5132 RH |
14458 | mips_optimize = 1; |
14459 | else | |
14460 | mips_optimize = 2; | |
14461 | break; | |
14462 | ||
14463 | case 'g': | |
14464 | if (arg == NULL) | |
14465 | mips_debug = 2; | |
14466 | else | |
14467 | mips_debug = atoi (arg); | |
252b5132 RH |
14468 | break; |
14469 | ||
14470 | case OPTION_MIPS1: | |
316f5878 | 14471 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14472 | break; |
14473 | ||
14474 | case OPTION_MIPS2: | |
316f5878 | 14475 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14476 | break; |
14477 | ||
14478 | case OPTION_MIPS3: | |
316f5878 | 14479 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14480 | break; |
14481 | ||
14482 | case OPTION_MIPS4: | |
316f5878 | 14483 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14484 | break; |
14485 | ||
84ea6cf2 | 14486 | case OPTION_MIPS5: |
316f5878 | 14487 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14488 | break; |
14489 | ||
e7af610e | 14490 | case OPTION_MIPS32: |
316f5878 | 14491 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14492 | break; |
14493 | ||
af7ee8bf CD |
14494 | case OPTION_MIPS32R2: |
14495 | file_mips_isa = ISA_MIPS32R2; | |
14496 | break; | |
14497 | ||
5f74bc13 CD |
14498 | case OPTION_MIPS64R2: |
14499 | file_mips_isa = ISA_MIPS64R2; | |
14500 | break; | |
14501 | ||
84ea6cf2 | 14502 | case OPTION_MIPS64: |
316f5878 | 14503 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14504 | break; |
14505 | ||
ec68c924 | 14506 | case OPTION_MTUNE: |
316f5878 RS |
14507 | mips_set_option_string (&mips_tune_string, arg); |
14508 | break; | |
ec68c924 | 14509 | |
316f5878 RS |
14510 | case OPTION_MARCH: |
14511 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14512 | break; |
14513 | ||
14514 | case OPTION_M4650: | |
316f5878 RS |
14515 | mips_set_option_string (&mips_arch_string, "4650"); |
14516 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14517 | break; |
14518 | ||
14519 | case OPTION_NO_M4650: | |
14520 | break; | |
14521 | ||
14522 | case OPTION_M4010: | |
316f5878 RS |
14523 | mips_set_option_string (&mips_arch_string, "4010"); |
14524 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14525 | break; |
14526 | ||
14527 | case OPTION_NO_M4010: | |
14528 | break; | |
14529 | ||
14530 | case OPTION_M4100: | |
316f5878 RS |
14531 | mips_set_option_string (&mips_arch_string, "4100"); |
14532 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14533 | break; |
14534 | ||
14535 | case OPTION_NO_M4100: | |
14536 | break; | |
14537 | ||
252b5132 | 14538 | case OPTION_M3900: |
316f5878 RS |
14539 | mips_set_option_string (&mips_arch_string, "3900"); |
14540 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14541 | break; |
bdaaa2e1 | 14542 | |
252b5132 RH |
14543 | case OPTION_NO_M3900: |
14544 | break; | |
14545 | ||
deec1734 CD |
14546 | case OPTION_MDMX: |
14547 | mips_opts.ase_mdmx = 1; | |
14548 | break; | |
14549 | ||
14550 | case OPTION_NO_MDMX: | |
14551 | mips_opts.ase_mdmx = 0; | |
14552 | break; | |
14553 | ||
74cd071d CF |
14554 | case OPTION_DSP: |
14555 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14556 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14557 | break; |
14558 | ||
14559 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14560 | mips_opts.ase_dsp = 0; |
14561 | mips_opts.ase_dspr2 = 0; | |
14562 | break; | |
14563 | ||
14564 | case OPTION_DSPR2: | |
14565 | mips_opts.ase_dspr2 = 1; | |
14566 | mips_opts.ase_dsp = 1; | |
14567 | break; | |
14568 | ||
14569 | case OPTION_NO_DSPR2: | |
14570 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14571 | mips_opts.ase_dsp = 0; |
14572 | break; | |
14573 | ||
ef2e4d86 CF |
14574 | case OPTION_MT: |
14575 | mips_opts.ase_mt = 1; | |
14576 | break; | |
14577 | ||
14578 | case OPTION_NO_MT: | |
14579 | mips_opts.ase_mt = 0; | |
14580 | break; | |
14581 | ||
dec0624d MR |
14582 | case OPTION_MCU: |
14583 | mips_opts.ase_mcu = 1; | |
14584 | break; | |
14585 | ||
14586 | case OPTION_NO_MCU: | |
14587 | mips_opts.ase_mcu = 0; | |
14588 | break; | |
14589 | ||
df58fc94 RS |
14590 | case OPTION_MICROMIPS: |
14591 | if (mips_opts.mips16 == 1) | |
14592 | { | |
14593 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14594 | return 0; | |
14595 | } | |
14596 | mips_opts.micromips = 1; | |
14597 | mips_no_prev_insn (); | |
14598 | break; | |
14599 | ||
14600 | case OPTION_NO_MICROMIPS: | |
14601 | mips_opts.micromips = 0; | |
14602 | mips_no_prev_insn (); | |
14603 | break; | |
14604 | ||
252b5132 | 14605 | case OPTION_MIPS16: |
df58fc94 RS |
14606 | if (mips_opts.micromips == 1) |
14607 | { | |
14608 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14609 | return 0; | |
14610 | } | |
252b5132 | 14611 | mips_opts.mips16 = 1; |
7d10b47d | 14612 | mips_no_prev_insn (); |
252b5132 RH |
14613 | break; |
14614 | ||
14615 | case OPTION_NO_MIPS16: | |
14616 | mips_opts.mips16 = 0; | |
7d10b47d | 14617 | mips_no_prev_insn (); |
252b5132 RH |
14618 | break; |
14619 | ||
1f25f5d3 CD |
14620 | case OPTION_MIPS3D: |
14621 | mips_opts.ase_mips3d = 1; | |
14622 | break; | |
14623 | ||
14624 | case OPTION_NO_MIPS3D: | |
14625 | mips_opts.ase_mips3d = 0; | |
14626 | break; | |
14627 | ||
e16bfa71 TS |
14628 | case OPTION_SMARTMIPS: |
14629 | mips_opts.ase_smartmips = 1; | |
14630 | break; | |
14631 | ||
14632 | case OPTION_NO_SMARTMIPS: | |
14633 | mips_opts.ase_smartmips = 0; | |
14634 | break; | |
14635 | ||
6a32d874 CM |
14636 | case OPTION_FIX_24K: |
14637 | mips_fix_24k = 1; | |
14638 | break; | |
14639 | ||
14640 | case OPTION_NO_FIX_24K: | |
14641 | mips_fix_24k = 0; | |
14642 | break; | |
14643 | ||
c67a084a NC |
14644 | case OPTION_FIX_LOONGSON2F_JUMP: |
14645 | mips_fix_loongson2f_jump = TRUE; | |
14646 | break; | |
14647 | ||
14648 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14649 | mips_fix_loongson2f_jump = FALSE; | |
14650 | break; | |
14651 | ||
14652 | case OPTION_FIX_LOONGSON2F_NOP: | |
14653 | mips_fix_loongson2f_nop = TRUE; | |
14654 | break; | |
14655 | ||
14656 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14657 | mips_fix_loongson2f_nop = FALSE; | |
14658 | break; | |
14659 | ||
d766e8ec RS |
14660 | case OPTION_FIX_VR4120: |
14661 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14662 | break; |
14663 | ||
d766e8ec RS |
14664 | case OPTION_NO_FIX_VR4120: |
14665 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14666 | break; |
14667 | ||
7d8e00cf RS |
14668 | case OPTION_FIX_VR4130: |
14669 | mips_fix_vr4130 = 1; | |
14670 | break; | |
14671 | ||
14672 | case OPTION_NO_FIX_VR4130: | |
14673 | mips_fix_vr4130 = 0; | |
14674 | break; | |
14675 | ||
d954098f DD |
14676 | case OPTION_FIX_CN63XXP1: |
14677 | mips_fix_cn63xxp1 = TRUE; | |
14678 | break; | |
14679 | ||
14680 | case OPTION_NO_FIX_CN63XXP1: | |
14681 | mips_fix_cn63xxp1 = FALSE; | |
14682 | break; | |
14683 | ||
4a6a3df4 AO |
14684 | case OPTION_RELAX_BRANCH: |
14685 | mips_relax_branch = 1; | |
14686 | break; | |
14687 | ||
14688 | case OPTION_NO_RELAX_BRANCH: | |
14689 | mips_relax_branch = 0; | |
14690 | break; | |
14691 | ||
aa6975fb ILT |
14692 | case OPTION_MSHARED: |
14693 | mips_in_shared = TRUE; | |
14694 | break; | |
14695 | ||
14696 | case OPTION_MNO_SHARED: | |
14697 | mips_in_shared = FALSE; | |
14698 | break; | |
14699 | ||
aed1a261 RS |
14700 | case OPTION_MSYM32: |
14701 | mips_opts.sym32 = TRUE; | |
14702 | break; | |
14703 | ||
14704 | case OPTION_MNO_SYM32: | |
14705 | mips_opts.sym32 = FALSE; | |
14706 | break; | |
14707 | ||
0f074f60 | 14708 | #ifdef OBJ_ELF |
252b5132 RH |
14709 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14710 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14711 | intended to be compatible with Irix 5. */ | |
14712 | case OPTION_CALL_SHARED: | |
f43abd2b | 14713 | if (!IS_ELF) |
252b5132 RH |
14714 | { |
14715 | as_bad (_("-call_shared is supported only for ELF format")); | |
14716 | return 0; | |
14717 | } | |
14718 | mips_pic = SVR4_PIC; | |
143d77c5 | 14719 | mips_abicalls = TRUE; |
252b5132 RH |
14720 | break; |
14721 | ||
861fb55a DJ |
14722 | case OPTION_CALL_NONPIC: |
14723 | if (!IS_ELF) | |
14724 | { | |
14725 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14726 | return 0; | |
14727 | } | |
14728 | mips_pic = NO_PIC; | |
14729 | mips_abicalls = TRUE; | |
14730 | break; | |
14731 | ||
252b5132 | 14732 | case OPTION_NON_SHARED: |
f43abd2b | 14733 | if (!IS_ELF) |
252b5132 RH |
14734 | { |
14735 | as_bad (_("-non_shared is supported only for ELF format")); | |
14736 | return 0; | |
14737 | } | |
14738 | mips_pic = NO_PIC; | |
143d77c5 | 14739 | mips_abicalls = FALSE; |
252b5132 RH |
14740 | break; |
14741 | ||
44075ae2 TS |
14742 | /* The -xgot option tells the assembler to use 32 bit offsets |
14743 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14744 | compatibility. */ |
14745 | case OPTION_XGOT: | |
14746 | mips_big_got = 1; | |
14747 | break; | |
0f074f60 | 14748 | #endif /* OBJ_ELF */ |
252b5132 RH |
14749 | |
14750 | case 'G': | |
6caf9ef4 TS |
14751 | g_switch_value = atoi (arg); |
14752 | g_switch_seen = 1; | |
252b5132 RH |
14753 | break; |
14754 | ||
34ba82a8 TS |
14755 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14756 | and -mabi=64. */ | |
252b5132 | 14757 | case OPTION_32: |
23fce1e3 NC |
14758 | if (IS_ELF) |
14759 | mips_abi = O32_ABI; | |
14760 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14761 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14762 | break; |
14763 | ||
23fce1e3 | 14764 | #ifdef OBJ_ELF |
e013f690 | 14765 | case OPTION_N32: |
f43abd2b | 14766 | if (!IS_ELF) |
34ba82a8 TS |
14767 | { |
14768 | as_bad (_("-n32 is supported for ELF format only")); | |
14769 | return 0; | |
14770 | } | |
316f5878 | 14771 | mips_abi = N32_ABI; |
e013f690 | 14772 | break; |
252b5132 | 14773 | |
e013f690 | 14774 | case OPTION_64: |
f43abd2b | 14775 | if (!IS_ELF) |
34ba82a8 TS |
14776 | { |
14777 | as_bad (_("-64 is supported for ELF format only")); | |
14778 | return 0; | |
14779 | } | |
316f5878 | 14780 | mips_abi = N64_ABI; |
f43abd2b | 14781 | if (!support_64bit_objects()) |
e013f690 | 14782 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14783 | break; |
ae948b86 | 14784 | #endif /* OBJ_ELF */ |
252b5132 | 14785 | |
c97ef257 | 14786 | case OPTION_GP32: |
a325df1d | 14787 | file_mips_gp32 = 1; |
c97ef257 AH |
14788 | break; |
14789 | ||
14790 | case OPTION_GP64: | |
a325df1d | 14791 | file_mips_gp32 = 0; |
c97ef257 | 14792 | break; |
252b5132 | 14793 | |
ca4e0257 | 14794 | case OPTION_FP32: |
a325df1d | 14795 | file_mips_fp32 = 1; |
316f5878 RS |
14796 | break; |
14797 | ||
14798 | case OPTION_FP64: | |
14799 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14800 | break; |
14801 | ||
037b32b9 AN |
14802 | case OPTION_SINGLE_FLOAT: |
14803 | file_mips_single_float = 1; | |
14804 | break; | |
14805 | ||
14806 | case OPTION_DOUBLE_FLOAT: | |
14807 | file_mips_single_float = 0; | |
14808 | break; | |
14809 | ||
14810 | case OPTION_SOFT_FLOAT: | |
14811 | file_mips_soft_float = 1; | |
14812 | break; | |
14813 | ||
14814 | case OPTION_HARD_FLOAT: | |
14815 | file_mips_soft_float = 0; | |
14816 | break; | |
14817 | ||
ae948b86 | 14818 | #ifdef OBJ_ELF |
252b5132 | 14819 | case OPTION_MABI: |
f43abd2b | 14820 | if (!IS_ELF) |
34ba82a8 TS |
14821 | { |
14822 | as_bad (_("-mabi is supported for ELF format only")); | |
14823 | return 0; | |
14824 | } | |
e013f690 | 14825 | if (strcmp (arg, "32") == 0) |
316f5878 | 14826 | mips_abi = O32_ABI; |
e013f690 | 14827 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14828 | mips_abi = O64_ABI; |
e013f690 | 14829 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14830 | mips_abi = N32_ABI; |
e013f690 TS |
14831 | else if (strcmp (arg, "64") == 0) |
14832 | { | |
316f5878 | 14833 | mips_abi = N64_ABI; |
e013f690 TS |
14834 | if (! support_64bit_objects()) |
14835 | as_fatal (_("No compiled in support for 64 bit object file " | |
14836 | "format")); | |
14837 | } | |
14838 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14839 | mips_abi = EABI_ABI; |
e013f690 | 14840 | else |
da0e507f TS |
14841 | { |
14842 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14843 | return 0; | |
14844 | } | |
252b5132 | 14845 | break; |
e013f690 | 14846 | #endif /* OBJ_ELF */ |
252b5132 | 14847 | |
6b76fefe | 14848 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14849 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14850 | break; |
14851 | ||
9ee72ff1 | 14852 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14853 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14854 | break; |
14855 | ||
ecb4347a DJ |
14856 | #ifdef OBJ_ELF |
14857 | case OPTION_MDEBUG: | |
b34976b6 | 14858 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14859 | break; |
14860 | ||
14861 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14862 | mips_flag_mdebug = FALSE; |
ecb4347a | 14863 | break; |
dcd410fe RO |
14864 | |
14865 | case OPTION_PDR: | |
14866 | mips_flag_pdr = TRUE; | |
14867 | break; | |
14868 | ||
14869 | case OPTION_NO_PDR: | |
14870 | mips_flag_pdr = FALSE; | |
14871 | break; | |
0a44bf69 RS |
14872 | |
14873 | case OPTION_MVXWORKS_PIC: | |
14874 | mips_pic = VXWORKS_PIC; | |
14875 | break; | |
ecb4347a DJ |
14876 | #endif /* OBJ_ELF */ |
14877 | ||
252b5132 RH |
14878 | default: |
14879 | return 0; | |
14880 | } | |
14881 | ||
c67a084a NC |
14882 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14883 | ||
252b5132 RH |
14884 | return 1; |
14885 | } | |
316f5878 RS |
14886 | \f |
14887 | /* Set up globals to generate code for the ISA or processor | |
14888 | described by INFO. */ | |
252b5132 | 14889 | |
252b5132 | 14890 | static void |
17a2f251 | 14891 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 14892 | { |
316f5878 | 14893 | if (info != 0) |
252b5132 | 14894 | { |
fef14a42 TS |
14895 | file_mips_arch = info->cpu; |
14896 | mips_opts.arch = info->cpu; | |
316f5878 | 14897 | mips_opts.isa = info->isa; |
252b5132 | 14898 | } |
252b5132 RH |
14899 | } |
14900 | ||
252b5132 | 14901 | |
316f5878 | 14902 | /* Likewise for tuning. */ |
252b5132 | 14903 | |
316f5878 | 14904 | static void |
17a2f251 | 14905 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14906 | { |
14907 | if (info != 0) | |
fef14a42 | 14908 | mips_tune = info->cpu; |
316f5878 | 14909 | } |
80cc45a5 | 14910 | |
34ba82a8 | 14911 | |
252b5132 | 14912 | void |
17a2f251 | 14913 | mips_after_parse_args (void) |
e9670677 | 14914 | { |
fef14a42 TS |
14915 | const struct mips_cpu_info *arch_info = 0; |
14916 | const struct mips_cpu_info *tune_info = 0; | |
14917 | ||
e9670677 | 14918 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14919 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14920 | { |
6caf9ef4 | 14921 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
14922 | as_bad (_("-G not supported in this configuration.")); |
14923 | g_switch_value = 0; | |
14924 | } | |
14925 | ||
cac012d6 AO |
14926 | if (mips_abi == NO_ABI) |
14927 | mips_abi = MIPS_DEFAULT_ABI; | |
14928 | ||
22923709 RS |
14929 | /* The following code determines the architecture and register size. |
14930 | Similar code was added to GCC 3.3 (see override_options() in | |
14931 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14932 | as much as possible. */ | |
e9670677 | 14933 | |
316f5878 | 14934 | if (mips_arch_string != 0) |
fef14a42 | 14935 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14936 | |
316f5878 | 14937 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 14938 | { |
316f5878 | 14939 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 14940 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14941 | the -march selection (if any). */ |
fef14a42 | 14942 | if (arch_info != 0) |
e9670677 | 14943 | { |
316f5878 RS |
14944 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14945 | There's no harm in specifying both as long as the ISA levels | |
14946 | are the same. */ | |
fef14a42 | 14947 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
14948 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
14949 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 14950 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14951 | } |
316f5878 | 14952 | else |
fef14a42 | 14953 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
14954 | } |
14955 | ||
fef14a42 TS |
14956 | if (arch_info == 0) |
14957 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 14958 | |
fef14a42 | 14959 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14960 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14961 | arch_info->name); |
14962 | ||
14963 | mips_set_architecture (arch_info); | |
14964 | ||
14965 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
14966 | if (mips_tune_string != 0) | |
14967 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14968 | |
fef14a42 TS |
14969 | if (tune_info == 0) |
14970 | mips_set_tune (arch_info); | |
14971 | else | |
14972 | mips_set_tune (tune_info); | |
e9670677 | 14973 | |
316f5878 | 14974 | if (file_mips_gp32 >= 0) |
e9670677 | 14975 | { |
316f5878 RS |
14976 | /* The user specified the size of the integer registers. Make sure |
14977 | it agrees with the ABI and ISA. */ | |
14978 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
14979 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
14980 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14981 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
14982 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14983 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
14984 | } |
14985 | else | |
14986 | { | |
316f5878 RS |
14987 | /* Infer the integer register size from the ABI and processor. |
14988 | Restrict ourselves to 32-bit registers if that's all the | |
14989 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
14990 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14991 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
14992 | } |
14993 | ||
ad3fea08 TS |
14994 | switch (file_mips_fp32) |
14995 | { | |
14996 | default: | |
14997 | case -1: | |
14998 | /* No user specified float register size. | |
14999 | ??? GAS treats single-float processors as though they had 64-bit | |
15000 | float registers (although it complains when double-precision | |
15001 | instructions are used). As things stand, saying they have 32-bit | |
15002 | registers would lead to spurious "register must be even" messages. | |
15003 | So here we assume float registers are never smaller than the | |
15004 | integer ones. */ | |
15005 | if (file_mips_gp32 == 0) | |
15006 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15007 | file_mips_fp32 = 0; | |
15008 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15009 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15010 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15011 | file_mips_fp32 = 0; | |
15012 | else | |
15013 | /* 32-bit float registers. */ | |
15014 | file_mips_fp32 = 1; | |
15015 | break; | |
15016 | ||
15017 | /* The user specified the size of the float registers. Check if it | |
15018 | agrees with the ABI and ISA. */ | |
15019 | case 0: | |
15020 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15021 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15022 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15023 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15024 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15025 | break; | |
15026 | case 1: | |
15027 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15028 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15029 | break; | |
15030 | } | |
e9670677 | 15031 | |
316f5878 | 15032 | /* End of GCC-shared inference code. */ |
e9670677 | 15033 | |
17a2f251 TS |
15034 | /* This flag is set when we have a 64-bit capable CPU but use only |
15035 | 32-bit wide registers. Note that EABI does not use it. */ | |
15036 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15037 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15038 | || mips_abi == O32_ABI)) | |
316f5878 | 15039 | mips_32bitmode = 1; |
e9670677 MR |
15040 | |
15041 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15042 | as_bad (_("trap exception not supported at ISA 1")); | |
15043 | ||
e9670677 MR |
15044 | /* If the selected architecture includes support for ASEs, enable |
15045 | generation of code for them. */ | |
a4672219 | 15046 | if (mips_opts.mips16 == -1) |
fef14a42 | 15047 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15048 | if (mips_opts.micromips == -1) |
15049 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15050 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15051 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15052 | && file_mips_fp32 == 0) ? 1 : 0; |
15053 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15054 | as_bad (_("-mfp32 used with -mips3d")); | |
15055 | ||
ffdefa66 | 15056 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15057 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15058 | && file_mips_fp32 == 0) ? 1 : 0; |
15059 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15060 | as_bad (_("-mfp32 used with -mdmx")); | |
15061 | ||
15062 | if (mips_opts.ase_smartmips == -1) | |
15063 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15064 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15065 | as_warn (_("%s ISA does not support SmartMIPS"), |
15066 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15067 | |
74cd071d | 15068 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15069 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15070 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15071 | as_warn (_("%s ISA does not support DSP ASE"), |
15072 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15073 | |
8b082fb1 TS |
15074 | if (mips_opts.ase_dspr2 == -1) |
15075 | { | |
15076 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15077 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15078 | } | |
15079 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15080 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15081 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15082 | |
ef2e4d86 | 15083 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15084 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15085 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15086 | as_warn (_("%s ISA does not support MT ASE"), |
15087 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15088 | |
dec0624d MR |
15089 | if (mips_opts.ase_mcu == -1) |
15090 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15091 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15092 | as_warn (_("%s ISA does not support MCU ASE"), | |
15093 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15094 | ||
e9670677 | 15095 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15096 | file_ase_mips3d = mips_opts.ase_mips3d; |
15097 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15098 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15099 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15100 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15101 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15102 | mips_opts.gp32 = file_mips_gp32; |
15103 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15104 | mips_opts.soft_float = file_mips_soft_float; |
15105 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15106 | |
ecb4347a DJ |
15107 | if (mips_flag_mdebug < 0) |
15108 | { | |
15109 | #ifdef OBJ_MAYBE_ECOFF | |
15110 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15111 | mips_flag_mdebug = 1; | |
15112 | else | |
15113 | #endif /* OBJ_MAYBE_ECOFF */ | |
15114 | mips_flag_mdebug = 0; | |
15115 | } | |
e9670677 MR |
15116 | } |
15117 | \f | |
15118 | void | |
17a2f251 | 15119 | mips_init_after_args (void) |
252b5132 RH |
15120 | { |
15121 | /* initialize opcodes */ | |
15122 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15123 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15124 | } |
15125 | ||
15126 | long | |
17a2f251 | 15127 | md_pcrel_from (fixS *fixP) |
252b5132 | 15128 | { |
a7ebbfdf TS |
15129 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15130 | switch (fixP->fx_r_type) | |
15131 | { | |
df58fc94 RS |
15132 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15133 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15134 | /* Return the address of the delay slot. */ | |
15135 | return addr + 2; | |
15136 | ||
15137 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15138 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15139 | case BFD_RELOC_16_PCREL_S2: |
15140 | case BFD_RELOC_MIPS_JMP: | |
15141 | /* Return the address of the delay slot. */ | |
15142 | return addr + 4; | |
df58fc94 | 15143 | |
a7ebbfdf | 15144 | default: |
58ea3d6a | 15145 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15146 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15147 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15148 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15149 | return addr; |
15150 | } | |
252b5132 RH |
15151 | } |
15152 | ||
252b5132 RH |
15153 | /* This is called before the symbol table is processed. In order to |
15154 | work with gcc when using mips-tfile, we must keep all local labels. | |
15155 | However, in other cases, we want to discard them. If we were | |
15156 | called with -g, but we didn't see any debugging information, it may | |
15157 | mean that gcc is smuggling debugging information through to | |
15158 | mips-tfile, in which case we must generate all local labels. */ | |
15159 | ||
15160 | void | |
17a2f251 | 15161 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15162 | { |
15163 | #ifndef NO_ECOFF_DEBUGGING | |
15164 | if (ECOFF_DEBUGGING | |
15165 | && mips_debug != 0 | |
15166 | && ! ecoff_debugging_seen) | |
15167 | flag_keep_locals = 1; | |
15168 | #endif | |
15169 | } | |
15170 | ||
3b91255e | 15171 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15172 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15173 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15174 | relocation operators. | |
15175 | ||
15176 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15177 | expression if: | |
15178 | ||
15179 | (a) it refers to the same symbol; and | |
15180 | (b) the offset applied in the %lo() expression is no lower than | |
15181 | the offset applied in the %got() or %hi(). | |
15182 | ||
15183 | (b) allows us to cope with code like: | |
15184 | ||
15185 | lui $4,%hi(foo) | |
15186 | lh $4,%lo(foo+2)($4) | |
15187 | ||
15188 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15189 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15190 | the high 16 bits. | |
15191 | ||
15192 | When several %lo()s match a particular %got() or %hi(), we use the | |
15193 | following rules to distinguish them: | |
15194 | ||
15195 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15196 | higher offsets. | |
15197 | ||
15198 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15199 | that already have a matching %got() or %hi(). | |
15200 | ||
15201 | (3) later %lo()s are better than earlier %lo()s. | |
15202 | ||
15203 | These rules are applied in order. | |
15204 | ||
15205 | (1) means, among other things, that %lo()s with identical offsets are | |
15206 | chosen if they exist. | |
15207 | ||
15208 | (2) means that we won't associate several high-part relocations with | |
15209 | the same low-part relocation unless there's no alternative. Having | |
15210 | several high parts for the same low part is a GNU extension; this rule | |
15211 | allows careful users to avoid it. | |
15212 | ||
15213 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15214 | with the last high-part relocation being at the front of the list. | |
15215 | It therefore makes sense to choose the last matching low-part | |
15216 | relocation, all other things being equal. It's also easier | |
15217 | to code that way. */ | |
252b5132 RH |
15218 | |
15219 | void | |
17a2f251 | 15220 | mips_frob_file (void) |
252b5132 RH |
15221 | { |
15222 | struct mips_hi_fixup *l; | |
35903be0 | 15223 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15224 | |
15225 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15226 | { | |
15227 | segment_info_type *seginfo; | |
3b91255e RS |
15228 | bfd_boolean matched_lo_p; |
15229 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15230 | |
9c2799c2 | 15231 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15232 | |
5919d012 RS |
15233 | /* If a GOT16 relocation turns out to be against a global symbol, |
15234 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15235 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15236 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15237 | continue; | |
15238 | ||
15239 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15240 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15241 | continue; |
15242 | ||
252b5132 | 15243 | seginfo = seg_info (l->seg); |
252b5132 | 15244 | |
3b91255e RS |
15245 | /* Set HI_POS to the position of this relocation in the chain. |
15246 | Set LO_POS to the position of the chosen low-part relocation. | |
15247 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15248 | relocation that matches an immediately-preceding high-part | |
15249 | relocation. */ | |
15250 | hi_pos = NULL; | |
15251 | lo_pos = NULL; | |
15252 | matched_lo_p = FALSE; | |
738e5348 | 15253 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15254 | |
3b91255e RS |
15255 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15256 | { | |
15257 | if (*pos == l->fixp) | |
15258 | hi_pos = pos; | |
15259 | ||
35903be0 | 15260 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15261 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15262 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15263 | && (lo_pos == NULL | |
15264 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15265 | || (!matched_lo_p | |
15266 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15267 | lo_pos = pos; | |
15268 | ||
15269 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15270 | && fixup_has_matching_lo_p (*pos)); | |
15271 | } | |
15272 | ||
15273 | /* If we found a match, remove the high-part relocation from its | |
15274 | current position and insert it before the low-part relocation. | |
15275 | Make the offsets match so that fixup_has_matching_lo_p() | |
15276 | will return true. | |
15277 | ||
15278 | We don't warn about unmatched high-part relocations since some | |
15279 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15280 | instructions. */ | |
15281 | if (lo_pos != NULL) | |
15282 | { | |
15283 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15284 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15285 | { |
3b91255e RS |
15286 | *hi_pos = l->fixp->fx_next; |
15287 | l->fixp->fx_next = *lo_pos; | |
15288 | *lo_pos = l->fixp; | |
252b5132 | 15289 | } |
252b5132 RH |
15290 | } |
15291 | } | |
15292 | } | |
15293 | ||
3e722fb5 | 15294 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15295 | We have to prevent gas from dropping them. */ |
252b5132 | 15296 | |
252b5132 | 15297 | int |
17a2f251 | 15298 | mips_force_relocation (fixS *fixp) |
252b5132 | 15299 | { |
ae6063d4 | 15300 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15301 | return 1; |
15302 | ||
df58fc94 RS |
15303 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15304 | so that the linker relaxation can update targets. */ | |
15305 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15306 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15307 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15308 | return 1; | |
15309 | ||
f6688943 TS |
15310 | if (HAVE_NEWABI |
15311 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15312 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15313 | || hi16_reloc_p (fixp->fx_r_type) |
15314 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15315 | return 1; |
15316 | ||
3e722fb5 | 15317 | return 0; |
252b5132 RH |
15318 | } |
15319 | ||
15320 | /* Apply a fixup to the object file. */ | |
15321 | ||
94f592af | 15322 | void |
55cf6793 | 15323 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15324 | { |
874e8986 | 15325 | bfd_byte *buf; |
98aa84af | 15326 | long insn; |
a7ebbfdf | 15327 | reloc_howto_type *howto; |
252b5132 | 15328 | |
a7ebbfdf TS |
15329 | /* We ignore generic BFD relocations we don't know about. */ |
15330 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15331 | if (! howto) | |
15332 | return; | |
65551fa4 | 15333 | |
df58fc94 RS |
15334 | gas_assert (fixP->fx_size == 2 |
15335 | || fixP->fx_size == 4 | |
90ecf173 MR |
15336 | || fixP->fx_r_type == BFD_RELOC_16 |
15337 | || fixP->fx_r_type == BFD_RELOC_64 | |
15338 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15339 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15340 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15341 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15342 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15343 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15344 | |
a7ebbfdf | 15345 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 15346 | |
df58fc94 RS |
15347 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15348 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15349 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15350 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15351 | |
15352 | /* Don't treat parts of a composite relocation as done. There are two | |
15353 | reasons for this: | |
15354 | ||
15355 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15356 | should nevertheless be emitted if the first part is. | |
15357 | ||
15358 | (2) In normal usage, composite relocations are never assembly-time | |
15359 | constants. The easiest way of dealing with the pathological | |
15360 | exceptions is to generate a relocation against STN_UNDEF and | |
15361 | leave everything up to the linker. */ | |
3994f87e | 15362 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15363 | fixP->fx_done = 1; |
15364 | ||
15365 | switch (fixP->fx_r_type) | |
15366 | { | |
3f98094e DJ |
15367 | case BFD_RELOC_MIPS_TLS_GD: |
15368 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15369 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15370 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15371 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15372 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15373 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
15374 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
15375 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15376 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15377 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15378 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15379 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15380 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15381 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15382 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
3f98094e DJ |
15383 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15384 | /* fall through */ | |
15385 | ||
252b5132 | 15386 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15387 | case BFD_RELOC_MIPS_SHIFT5: |
15388 | case BFD_RELOC_MIPS_SHIFT6: | |
15389 | case BFD_RELOC_MIPS_GOT_DISP: | |
15390 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15391 | case BFD_RELOC_MIPS_GOT_OFST: | |
15392 | case BFD_RELOC_MIPS_SUB: | |
15393 | case BFD_RELOC_MIPS_INSERT_A: | |
15394 | case BFD_RELOC_MIPS_INSERT_B: | |
15395 | case BFD_RELOC_MIPS_DELETE: | |
15396 | case BFD_RELOC_MIPS_HIGHEST: | |
15397 | case BFD_RELOC_MIPS_HIGHER: | |
15398 | case BFD_RELOC_MIPS_SCN_DISP: | |
15399 | case BFD_RELOC_MIPS_REL16: | |
15400 | case BFD_RELOC_MIPS_RELGOT: | |
15401 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15402 | case BFD_RELOC_HI16: |
15403 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15404 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15405 | case BFD_RELOC_MIPS_LITERAL: |
15406 | case BFD_RELOC_MIPS_CALL16: | |
15407 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15408 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15409 | case BFD_RELOC_MIPS_GOT_HI16: |
15410 | case BFD_RELOC_MIPS_GOT_LO16: | |
15411 | case BFD_RELOC_MIPS_CALL_HI16: | |
15412 | case BFD_RELOC_MIPS_CALL_LO16: | |
15413 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15414 | case BFD_RELOC_MIPS16_GOT16: |
15415 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15416 | case BFD_RELOC_MIPS16_HI16: |
15417 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15418 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15419 | case BFD_RELOC_MICROMIPS_JMP: |
15420 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15421 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15422 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15423 | case BFD_RELOC_MICROMIPS_SUB: | |
15424 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15425 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15426 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15427 | case BFD_RELOC_MICROMIPS_JALR: | |
15428 | case BFD_RELOC_MICROMIPS_HI16: | |
15429 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15430 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15431 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15432 | case BFD_RELOC_MICROMIPS_CALL16: | |
15433 | case BFD_RELOC_MICROMIPS_GOT16: | |
15434 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15435 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15436 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15437 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15438 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15439 | break; |
15440 | ||
252b5132 RH |
15441 | case BFD_RELOC_64: |
15442 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15443 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15444 | if (fixP->fx_done) |
252b5132 RH |
15445 | { |
15446 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 15447 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
15448 | else |
15449 | { | |
a7ebbfdf | 15450 | valueT hiv; |
252b5132 | 15451 | |
a7ebbfdf | 15452 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15453 | hiv = 0xffffffff; |
15454 | else | |
15455 | hiv = 0; | |
b215186b | 15456 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 15457 | *valP, 4); |
b215186b | 15458 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 15459 | hiv, 4); |
252b5132 RH |
15460 | } |
15461 | } | |
15462 | break; | |
15463 | ||
056350c6 | 15464 | case BFD_RELOC_RVA: |
252b5132 | 15465 | case BFD_RELOC_32: |
252b5132 RH |
15466 | case BFD_RELOC_16: |
15467 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15468 | value now. This can happen if we have a .word which is not |
15469 | resolved when it appears but is later defined. */ | |
252b5132 | 15470 | if (fixP->fx_done) |
54f4ddb3 | 15471 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
15472 | break; |
15473 | ||
15474 | case BFD_RELOC_LO16: | |
d6f16593 | 15475 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15476 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15477 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15478 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15479 | /* When handling an embedded PIC switch statement, we can wind |
15480 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15481 | if (fixP->fx_done) | |
15482 | { | |
a7ebbfdf | 15483 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15484 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15485 | _("relocation overflow")); | |
df58fc94 RS |
15486 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15487 | Relocations always refer to the second halfword, regardless | |
15488 | of endianness. */ | |
15489 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15490 | buf += 2; |
2132e3a3 | 15491 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
15492 | } |
15493 | break; | |
15494 | ||
15495 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15496 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15497 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15498 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15499 | |
54f4ddb3 TS |
15500 | /* We need to save the bits in the instruction since fixup_segment() |
15501 | might be deleting the relocation entry (i.e., a branch within | |
15502 | the current segment). */ | |
a7ebbfdf | 15503 | if (! fixP->fx_done) |
bb2d6cd7 | 15504 | break; |
252b5132 | 15505 | |
54f4ddb3 | 15506 | /* Update old instruction data. */ |
252b5132 RH |
15507 | if (target_big_endian) |
15508 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
15509 | else | |
15510 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
15511 | ||
a7ebbfdf TS |
15512 | if (*valP + 0x20000 <= 0x3ffff) |
15513 | { | |
15514 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 15515 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15516 | } |
15517 | else if (mips_pic == NO_PIC | |
15518 | && fixP->fx_done | |
15519 | && fixP->fx_frag->fr_address >= text_section->vma | |
15520 | && (fixP->fx_frag->fr_address | |
587aac4e | 15521 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15522 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15523 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15524 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15525 | { |
15526 | /* The branch offset is too large. If this is an | |
15527 | unconditional branch, and we are not generating PIC code, | |
15528 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15529 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15530 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15531 | else |
a7ebbfdf TS |
15532 | insn = 0x08000000; /* j */ |
15533 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15534 | fixP->fx_done = 0; | |
15535 | fixP->fx_addsy = section_symbol (text_section); | |
15536 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 15537 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15538 | } |
15539 | else | |
15540 | { | |
15541 | /* If we got here, we have branch-relaxation disabled, | |
15542 | and there's nothing we can do to fix this instruction | |
15543 | without turning it into a longer sequence. */ | |
15544 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15545 | _("Branch out of range")); | |
252b5132 | 15546 | } |
252b5132 RH |
15547 | break; |
15548 | ||
df58fc94 RS |
15549 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15550 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15551 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15552 | /* We adjust the offset back to even. */ | |
15553 | if ((*valP & 0x1) != 0) | |
15554 | --(*valP); | |
15555 | ||
15556 | if (! fixP->fx_done) | |
15557 | break; | |
15558 | ||
15559 | /* Should never visit here, because we keep the relocation. */ | |
15560 | abort (); | |
15561 | break; | |
15562 | ||
252b5132 RH |
15563 | case BFD_RELOC_VTABLE_INHERIT: |
15564 | fixP->fx_done = 0; | |
15565 | if (fixP->fx_addsy | |
15566 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15567 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15568 | S_SET_WEAK (fixP->fx_addsy); | |
15569 | break; | |
15570 | ||
15571 | case BFD_RELOC_VTABLE_ENTRY: | |
15572 | fixP->fx_done = 0; | |
15573 | break; | |
15574 | ||
15575 | default: | |
15576 | internalError (); | |
15577 | } | |
a7ebbfdf TS |
15578 | |
15579 | /* Remember value for tc_gen_reloc. */ | |
15580 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15581 | } |
15582 | ||
252b5132 | 15583 | static symbolS * |
17a2f251 | 15584 | get_symbol (void) |
252b5132 RH |
15585 | { |
15586 | int c; | |
15587 | char *name; | |
15588 | symbolS *p; | |
15589 | ||
15590 | name = input_line_pointer; | |
15591 | c = get_symbol_end (); | |
15592 | p = (symbolS *) symbol_find_or_make (name); | |
15593 | *input_line_pointer = c; | |
15594 | return p; | |
15595 | } | |
15596 | ||
742a56fe RS |
15597 | /* Align the current frag to a given power of two. If a particular |
15598 | fill byte should be used, FILL points to an integer that contains | |
15599 | that byte, otherwise FILL is null. | |
15600 | ||
15601 | The MIPS assembler also automatically adjusts any preceding | |
15602 | label. */ | |
252b5132 RH |
15603 | |
15604 | static void | |
742a56fe | 15605 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 15606 | { |
7d10b47d | 15607 | mips_emit_delays (); |
df58fc94 | 15608 | mips_record_compressed_mode (); |
742a56fe RS |
15609 | if (fill == NULL && subseg_text_p (now_seg)) |
15610 | frag_align_code (to, 0); | |
15611 | else | |
15612 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
15613 | record_alignment (now_seg, to); |
15614 | if (label != NULL) | |
15615 | { | |
9c2799c2 | 15616 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 15617 | symbol_set_frag (label, frag_now); |
252b5132 RH |
15618 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
15619 | } | |
15620 | } | |
15621 | ||
15622 | /* Align to a given power of two. .align 0 turns off the automatic | |
15623 | alignment used by the data creating pseudo-ops. */ | |
15624 | ||
15625 | static void | |
17a2f251 | 15626 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15627 | { |
742a56fe | 15628 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15629 | long max_alignment = 28; |
252b5132 | 15630 | |
54f4ddb3 | 15631 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15632 | to the aligned address. |
54f4ddb3 | 15633 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15634 | a .align pseudo instruction. |
54f4ddb3 | 15635 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15636 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15637 | We don't. */ |
252b5132 RH |
15638 | |
15639 | temp = get_absolute_expression (); | |
15640 | if (temp > max_alignment) | |
15641 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15642 | else if (temp < 0) | |
15643 | { | |
15644 | as_warn (_("Alignment negative: 0 assumed.")); | |
15645 | temp = 0; | |
15646 | } | |
15647 | if (*input_line_pointer == ',') | |
15648 | { | |
f9419b05 | 15649 | ++input_line_pointer; |
742a56fe RS |
15650 | fill_value = get_absolute_expression (); |
15651 | fill_ptr = &fill_value; | |
252b5132 RH |
15652 | } |
15653 | else | |
742a56fe | 15654 | fill_ptr = 0; |
252b5132 RH |
15655 | if (temp) |
15656 | { | |
a8dbcb85 TS |
15657 | segment_info_type *si = seg_info (now_seg); |
15658 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15659 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15660 | auto_align = 1; |
742a56fe | 15661 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
15662 | } |
15663 | else | |
15664 | { | |
15665 | auto_align = 0; | |
15666 | } | |
15667 | ||
15668 | demand_empty_rest_of_line (); | |
15669 | } | |
15670 | ||
252b5132 | 15671 | static void |
17a2f251 | 15672 | s_change_sec (int sec) |
252b5132 RH |
15673 | { |
15674 | segT seg; | |
15675 | ||
252b5132 RH |
15676 | #ifdef OBJ_ELF |
15677 | /* The ELF backend needs to know that we are changing sections, so | |
15678 | that .previous works correctly. We could do something like check | |
b6ff326e | 15679 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15680 | as it would not be appropriate to use it in the section changing |
15681 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15682 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15683 | if (IS_ELF) |
15684 | obj_elf_section_change_hook (); | |
252b5132 RH |
15685 | #endif |
15686 | ||
7d10b47d | 15687 | mips_emit_delays (); |
6a32d874 | 15688 | |
252b5132 RH |
15689 | switch (sec) |
15690 | { | |
15691 | case 't': | |
15692 | s_text (0); | |
15693 | break; | |
15694 | case 'd': | |
15695 | s_data (0); | |
15696 | break; | |
15697 | case 'b': | |
15698 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15699 | demand_empty_rest_of_line (); | |
15700 | break; | |
15701 | ||
15702 | case 'r': | |
4d0d148d TS |
15703 | seg = subseg_new (RDATA_SECTION_NAME, |
15704 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15705 | if (IS_ELF) |
252b5132 | 15706 | { |
4d0d148d TS |
15707 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15708 | | SEC_READONLY | SEC_RELOC | |
15709 | | SEC_DATA)); | |
c41e87e3 | 15710 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15711 | record_alignment (seg, 4); |
252b5132 | 15712 | } |
4d0d148d | 15713 | demand_empty_rest_of_line (); |
252b5132 RH |
15714 | break; |
15715 | ||
15716 | case 's': | |
4d0d148d | 15717 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15718 | if (IS_ELF) |
252b5132 | 15719 | { |
4d0d148d TS |
15720 | bfd_set_section_flags (stdoutput, seg, |
15721 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15722 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15723 | record_alignment (seg, 4); |
252b5132 | 15724 | } |
4d0d148d TS |
15725 | demand_empty_rest_of_line (); |
15726 | break; | |
998b3c36 MR |
15727 | |
15728 | case 'B': | |
15729 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15730 | if (IS_ELF) | |
15731 | { | |
15732 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15733 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15734 | record_alignment (seg, 4); | |
15735 | } | |
15736 | demand_empty_rest_of_line (); | |
15737 | break; | |
252b5132 RH |
15738 | } |
15739 | ||
15740 | auto_align = 1; | |
15741 | } | |
b34976b6 | 15742 | |
cca86cc8 | 15743 | void |
17a2f251 | 15744 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15745 | { |
7ed4a06a | 15746 | #ifdef OBJ_ELF |
cca86cc8 SC |
15747 | char *section_name; |
15748 | char c; | |
684022ea | 15749 | char next_c = 0; |
cca86cc8 SC |
15750 | int section_type; |
15751 | int section_flag; | |
15752 | int section_entry_size; | |
15753 | int section_alignment; | |
b34976b6 | 15754 | |
f43abd2b | 15755 | if (!IS_ELF) |
7ed4a06a TS |
15756 | return; |
15757 | ||
cca86cc8 SC |
15758 | section_name = input_line_pointer; |
15759 | c = get_symbol_end (); | |
a816d1ed AO |
15760 | if (c) |
15761 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15762 | |
4cf0dd0d TS |
15763 | /* Do we have .section Name<,"flags">? */ |
15764 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15765 | { |
4cf0dd0d TS |
15766 | /* just after name is now '\0'. */ |
15767 | *input_line_pointer = c; | |
cca86cc8 SC |
15768 | input_line_pointer = section_name; |
15769 | obj_elf_section (ignore); | |
15770 | return; | |
15771 | } | |
15772 | input_line_pointer++; | |
15773 | ||
15774 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15775 | if (c == ',') | |
15776 | section_type = get_absolute_expression (); | |
15777 | else | |
15778 | section_type = 0; | |
15779 | if (*input_line_pointer++ == ',') | |
15780 | section_flag = get_absolute_expression (); | |
15781 | else | |
15782 | section_flag = 0; | |
15783 | if (*input_line_pointer++ == ',') | |
15784 | section_entry_size = get_absolute_expression (); | |
15785 | else | |
15786 | section_entry_size = 0; | |
15787 | if (*input_line_pointer++ == ',') | |
15788 | section_alignment = get_absolute_expression (); | |
15789 | else | |
15790 | section_alignment = 0; | |
87975d2a AM |
15791 | /* FIXME: really ignore? */ |
15792 | (void) section_alignment; | |
cca86cc8 | 15793 | |
a816d1ed AO |
15794 | section_name = xstrdup (section_name); |
15795 | ||
8ab8a5c8 RS |
15796 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15797 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15798 | traditionally had to fall back on the more common @progbits instead. | |
15799 | ||
15800 | There's nothing really harmful in this, since bfd will correct | |
15801 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15802 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15803 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15804 | ||
15805 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15806 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15807 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15808 | generic type-checking code. */ | |
15809 | if (section_type == SHT_MIPS_DWARF) | |
15810 | section_type = SHT_PROGBITS; | |
15811 | ||
cca86cc8 SC |
15812 | obj_elf_change_section (section_name, section_type, section_flag, |
15813 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15814 | |
15815 | if (now_seg->name != section_name) | |
15816 | free (section_name); | |
7ed4a06a | 15817 | #endif /* OBJ_ELF */ |
cca86cc8 | 15818 | } |
252b5132 RH |
15819 | |
15820 | void | |
17a2f251 | 15821 | mips_enable_auto_align (void) |
252b5132 RH |
15822 | { |
15823 | auto_align = 1; | |
15824 | } | |
15825 | ||
15826 | static void | |
17a2f251 | 15827 | s_cons (int log_size) |
252b5132 | 15828 | { |
a8dbcb85 TS |
15829 | segment_info_type *si = seg_info (now_seg); |
15830 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15831 | symbolS *label; |
15832 | ||
a8dbcb85 | 15833 | label = l != NULL ? l->label : NULL; |
7d10b47d | 15834 | mips_emit_delays (); |
252b5132 RH |
15835 | if (log_size > 0 && auto_align) |
15836 | mips_align (log_size, 0, label); | |
252b5132 | 15837 | cons (1 << log_size); |
a1facbec | 15838 | mips_clear_insn_labels (); |
252b5132 RH |
15839 | } |
15840 | ||
15841 | static void | |
17a2f251 | 15842 | s_float_cons (int type) |
252b5132 | 15843 | { |
a8dbcb85 TS |
15844 | segment_info_type *si = seg_info (now_seg); |
15845 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15846 | symbolS *label; |
15847 | ||
a8dbcb85 | 15848 | label = l != NULL ? l->label : NULL; |
252b5132 | 15849 | |
7d10b47d | 15850 | mips_emit_delays (); |
252b5132 RH |
15851 | |
15852 | if (auto_align) | |
49309057 ILT |
15853 | { |
15854 | if (type == 'd') | |
15855 | mips_align (3, 0, label); | |
15856 | else | |
15857 | mips_align (2, 0, label); | |
15858 | } | |
252b5132 | 15859 | |
252b5132 | 15860 | float_cons (type); |
a1facbec | 15861 | mips_clear_insn_labels (); |
252b5132 RH |
15862 | } |
15863 | ||
15864 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15865 | permitted to say | |
15866 | .globl foo .text | |
15867 | where foo is an undefined symbol, to mean that foo should be | |
15868 | considered to be the address of a function. */ | |
15869 | ||
15870 | static void | |
17a2f251 | 15871 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15872 | { |
15873 | char *name; | |
15874 | int c; | |
15875 | symbolS *symbolP; | |
15876 | flagword flag; | |
15877 | ||
8a06b769 | 15878 | do |
252b5132 | 15879 | { |
8a06b769 | 15880 | name = input_line_pointer; |
252b5132 | 15881 | c = get_symbol_end (); |
8a06b769 TS |
15882 | symbolP = symbol_find_or_make (name); |
15883 | S_SET_EXTERNAL (symbolP); | |
15884 | ||
252b5132 | 15885 | *input_line_pointer = c; |
8a06b769 | 15886 | SKIP_WHITESPACE (); |
252b5132 | 15887 | |
8a06b769 TS |
15888 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15889 | being a function is apparently labelled as being an object. */ | |
15890 | flag = BSF_OBJECT; | |
252b5132 | 15891 | |
8a06b769 TS |
15892 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15893 | && (*input_line_pointer != ',')) | |
15894 | { | |
15895 | char *secname; | |
15896 | asection *sec; | |
15897 | ||
15898 | secname = input_line_pointer; | |
15899 | c = get_symbol_end (); | |
15900 | sec = bfd_get_section_by_name (stdoutput, secname); | |
15901 | if (sec == NULL) | |
15902 | as_bad (_("%s: no such section"), secname); | |
15903 | *input_line_pointer = c; | |
15904 | ||
15905 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15906 | flag = BSF_FUNCTION; | |
15907 | } | |
15908 | ||
15909 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15910 | ||
15911 | c = *input_line_pointer; | |
15912 | if (c == ',') | |
15913 | { | |
15914 | input_line_pointer++; | |
15915 | SKIP_WHITESPACE (); | |
15916 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15917 | c = '\n'; | |
15918 | } | |
15919 | } | |
15920 | while (c == ','); | |
252b5132 | 15921 | |
252b5132 RH |
15922 | demand_empty_rest_of_line (); |
15923 | } | |
15924 | ||
15925 | static void | |
17a2f251 | 15926 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15927 | { |
15928 | char *opt; | |
15929 | char c; | |
15930 | ||
15931 | opt = input_line_pointer; | |
15932 | c = get_symbol_end (); | |
15933 | ||
15934 | if (*opt == 'O') | |
15935 | { | |
15936 | /* FIXME: What does this mean? */ | |
15937 | } | |
15938 | else if (strncmp (opt, "pic", 3) == 0) | |
15939 | { | |
15940 | int i; | |
15941 | ||
15942 | i = atoi (opt + 3); | |
15943 | if (i == 0) | |
15944 | mips_pic = NO_PIC; | |
15945 | else if (i == 2) | |
143d77c5 | 15946 | { |
252b5132 | 15947 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15948 | mips_abicalls = TRUE; |
15949 | } | |
252b5132 RH |
15950 | else |
15951 | as_bad (_(".option pic%d not supported"), i); | |
15952 | ||
4d0d148d | 15953 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
15954 | { |
15955 | if (g_switch_seen && g_switch_value != 0) | |
15956 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15957 | g_switch_value = 0; | |
15958 | bfd_set_gp_size (stdoutput, 0); | |
15959 | } | |
15960 | } | |
15961 | else | |
15962 | as_warn (_("Unrecognized option \"%s\""), opt); | |
15963 | ||
15964 | *input_line_pointer = c; | |
15965 | demand_empty_rest_of_line (); | |
15966 | } | |
15967 | ||
15968 | /* This structure is used to hold a stack of .set values. */ | |
15969 | ||
e972090a NC |
15970 | struct mips_option_stack |
15971 | { | |
252b5132 RH |
15972 | struct mips_option_stack *next; |
15973 | struct mips_set_options options; | |
15974 | }; | |
15975 | ||
15976 | static struct mips_option_stack *mips_opts_stack; | |
15977 | ||
15978 | /* Handle the .set pseudo-op. */ | |
15979 | ||
15980 | static void | |
17a2f251 | 15981 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15982 | { |
15983 | char *name = input_line_pointer, ch; | |
15984 | ||
15985 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 15986 | ++input_line_pointer; |
252b5132 RH |
15987 | ch = *input_line_pointer; |
15988 | *input_line_pointer = '\0'; | |
15989 | ||
15990 | if (strcmp (name, "reorder") == 0) | |
15991 | { | |
7d10b47d RS |
15992 | if (mips_opts.noreorder) |
15993 | end_noreorder (); | |
252b5132 RH |
15994 | } |
15995 | else if (strcmp (name, "noreorder") == 0) | |
15996 | { | |
7d10b47d RS |
15997 | if (!mips_opts.noreorder) |
15998 | start_noreorder (); | |
252b5132 | 15999 | } |
741fe287 MR |
16000 | else if (strncmp (name, "at=", 3) == 0) |
16001 | { | |
16002 | char *s = name + 3; | |
16003 | ||
16004 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16005 | as_bad (_("Unrecognized register name `%s'"), s); | |
16006 | } | |
252b5132 RH |
16007 | else if (strcmp (name, "at") == 0) |
16008 | { | |
741fe287 | 16009 | mips_opts.at = ATREG; |
252b5132 RH |
16010 | } |
16011 | else if (strcmp (name, "noat") == 0) | |
16012 | { | |
741fe287 | 16013 | mips_opts.at = ZERO; |
252b5132 RH |
16014 | } |
16015 | else if (strcmp (name, "macro") == 0) | |
16016 | { | |
16017 | mips_opts.warn_about_macros = 0; | |
16018 | } | |
16019 | else if (strcmp (name, "nomacro") == 0) | |
16020 | { | |
16021 | if (mips_opts.noreorder == 0) | |
16022 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16023 | mips_opts.warn_about_macros = 1; | |
16024 | } | |
16025 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16026 | { | |
16027 | mips_opts.nomove = 0; | |
16028 | } | |
16029 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16030 | { | |
16031 | mips_opts.nomove = 1; | |
16032 | } | |
16033 | else if (strcmp (name, "bopt") == 0) | |
16034 | { | |
16035 | mips_opts.nobopt = 0; | |
16036 | } | |
16037 | else if (strcmp (name, "nobopt") == 0) | |
16038 | { | |
16039 | mips_opts.nobopt = 1; | |
16040 | } | |
ad3fea08 TS |
16041 | else if (strcmp (name, "gp=default") == 0) |
16042 | mips_opts.gp32 = file_mips_gp32; | |
16043 | else if (strcmp (name, "gp=32") == 0) | |
16044 | mips_opts.gp32 = 1; | |
16045 | else if (strcmp (name, "gp=64") == 0) | |
16046 | { | |
16047 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16048 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16049 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16050 | mips_opts.gp32 = 0; | |
16051 | } | |
16052 | else if (strcmp (name, "fp=default") == 0) | |
16053 | mips_opts.fp32 = file_mips_fp32; | |
16054 | else if (strcmp (name, "fp=32") == 0) | |
16055 | mips_opts.fp32 = 1; | |
16056 | else if (strcmp (name, "fp=64") == 0) | |
16057 | { | |
16058 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16059 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16060 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16061 | mips_opts.fp32 = 0; | |
16062 | } | |
037b32b9 AN |
16063 | else if (strcmp (name, "softfloat") == 0) |
16064 | mips_opts.soft_float = 1; | |
16065 | else if (strcmp (name, "hardfloat") == 0) | |
16066 | mips_opts.soft_float = 0; | |
16067 | else if (strcmp (name, "singlefloat") == 0) | |
16068 | mips_opts.single_float = 1; | |
16069 | else if (strcmp (name, "doublefloat") == 0) | |
16070 | mips_opts.single_float = 0; | |
252b5132 RH |
16071 | else if (strcmp (name, "mips16") == 0 |
16072 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16073 | { |
16074 | if (mips_opts.micromips == 1) | |
16075 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16076 | mips_opts.mips16 = 1; | |
16077 | } | |
252b5132 RH |
16078 | else if (strcmp (name, "nomips16") == 0 |
16079 | || strcmp (name, "noMIPS-16") == 0) | |
16080 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16081 | else if (strcmp (name, "micromips") == 0) |
16082 | { | |
16083 | if (mips_opts.mips16 == 1) | |
16084 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16085 | mips_opts.micromips = 1; | |
16086 | } | |
16087 | else if (strcmp (name, "nomicromips") == 0) | |
16088 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16089 | else if (strcmp (name, "smartmips") == 0) |
16090 | { | |
ad3fea08 | 16091 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16092 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16093 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16094 | mips_opts.ase_smartmips = 1; | |
16095 | } | |
16096 | else if (strcmp (name, "nosmartmips") == 0) | |
16097 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16098 | else if (strcmp (name, "mips3d") == 0) |
16099 | mips_opts.ase_mips3d = 1; | |
16100 | else if (strcmp (name, "nomips3d") == 0) | |
16101 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16102 | else if (strcmp (name, "mdmx") == 0) |
16103 | mips_opts.ase_mdmx = 1; | |
16104 | else if (strcmp (name, "nomdmx") == 0) | |
16105 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16106 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16107 | { |
16108 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16109 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16110 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16111 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16112 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16113 | } |
74cd071d | 16114 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16115 | { |
16116 | mips_opts.ase_dsp = 0; | |
16117 | mips_opts.ase_dspr2 = 0; | |
16118 | } | |
16119 | else if (strcmp (name, "dspr2") == 0) | |
16120 | { | |
16121 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16122 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16123 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16124 | mips_opts.ase_dspr2 = 1; | |
16125 | mips_opts.ase_dsp = 1; | |
16126 | } | |
16127 | else if (strcmp (name, "nodspr2") == 0) | |
16128 | { | |
16129 | mips_opts.ase_dspr2 = 0; | |
16130 | mips_opts.ase_dsp = 0; | |
16131 | } | |
ef2e4d86 | 16132 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16133 | { |
16134 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16135 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16136 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16137 | mips_opts.ase_mt = 1; | |
16138 | } | |
ef2e4d86 CF |
16139 | else if (strcmp (name, "nomt") == 0) |
16140 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16141 | else if (strcmp (name, "mcu") == 0) |
16142 | mips_opts.ase_mcu = 1; | |
16143 | else if (strcmp (name, "nomcu") == 0) | |
16144 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16145 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16146 | { |
af7ee8bf | 16147 | int reset = 0; |
252b5132 | 16148 | |
1a2c1fad CD |
16149 | /* Permit the user to change the ISA and architecture on the fly. |
16150 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16151 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16152 | { |
16153 | reset = 1; | |
16154 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16155 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16156 | } |
16157 | else if (strncmp (name, "arch=", 5) == 0) | |
16158 | { | |
16159 | const struct mips_cpu_info *p; | |
16160 | ||
16161 | p = mips_parse_cpu("internal use", name + 5); | |
16162 | if (!p) | |
16163 | as_bad (_("unknown architecture %s"), name + 5); | |
16164 | else | |
16165 | { | |
16166 | mips_opts.arch = p->cpu; | |
16167 | mips_opts.isa = p->isa; | |
16168 | } | |
16169 | } | |
81a21e38 TS |
16170 | else if (strncmp (name, "mips", 4) == 0) |
16171 | { | |
16172 | const struct mips_cpu_info *p; | |
16173 | ||
16174 | p = mips_parse_cpu("internal use", name); | |
16175 | if (!p) | |
16176 | as_bad (_("unknown ISA level %s"), name + 4); | |
16177 | else | |
16178 | { | |
16179 | mips_opts.arch = p->cpu; | |
16180 | mips_opts.isa = p->isa; | |
16181 | } | |
16182 | } | |
af7ee8bf | 16183 | else |
81a21e38 | 16184 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16185 | |
16186 | switch (mips_opts.isa) | |
98d3f06f KH |
16187 | { |
16188 | case 0: | |
98d3f06f | 16189 | break; |
af7ee8bf CD |
16190 | case ISA_MIPS1: |
16191 | case ISA_MIPS2: | |
16192 | case ISA_MIPS32: | |
16193 | case ISA_MIPS32R2: | |
98d3f06f KH |
16194 | mips_opts.gp32 = 1; |
16195 | mips_opts.fp32 = 1; | |
16196 | break; | |
af7ee8bf CD |
16197 | case ISA_MIPS3: |
16198 | case ISA_MIPS4: | |
16199 | case ISA_MIPS5: | |
16200 | case ISA_MIPS64: | |
5f74bc13 | 16201 | case ISA_MIPS64R2: |
98d3f06f KH |
16202 | mips_opts.gp32 = 0; |
16203 | mips_opts.fp32 = 0; | |
16204 | break; | |
16205 | default: | |
16206 | as_bad (_("unknown ISA level %s"), name + 4); | |
16207 | break; | |
16208 | } | |
af7ee8bf | 16209 | if (reset) |
98d3f06f | 16210 | { |
af7ee8bf CD |
16211 | mips_opts.gp32 = file_mips_gp32; |
16212 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16213 | } |
252b5132 RH |
16214 | } |
16215 | else if (strcmp (name, "autoextend") == 0) | |
16216 | mips_opts.noautoextend = 0; | |
16217 | else if (strcmp (name, "noautoextend") == 0) | |
16218 | mips_opts.noautoextend = 1; | |
16219 | else if (strcmp (name, "push") == 0) | |
16220 | { | |
16221 | struct mips_option_stack *s; | |
16222 | ||
16223 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16224 | s->next = mips_opts_stack; | |
16225 | s->options = mips_opts; | |
16226 | mips_opts_stack = s; | |
16227 | } | |
16228 | else if (strcmp (name, "pop") == 0) | |
16229 | { | |
16230 | struct mips_option_stack *s; | |
16231 | ||
16232 | s = mips_opts_stack; | |
16233 | if (s == NULL) | |
16234 | as_bad (_(".set pop with no .set push")); | |
16235 | else | |
16236 | { | |
16237 | /* If we're changing the reorder mode we need to handle | |
16238 | delay slots correctly. */ | |
16239 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16240 | start_noreorder (); |
252b5132 | 16241 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16242 | end_noreorder (); |
252b5132 RH |
16243 | |
16244 | mips_opts = s->options; | |
16245 | mips_opts_stack = s->next; | |
16246 | free (s); | |
16247 | } | |
16248 | } | |
aed1a261 RS |
16249 | else if (strcmp (name, "sym32") == 0) |
16250 | mips_opts.sym32 = TRUE; | |
16251 | else if (strcmp (name, "nosym32") == 0) | |
16252 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16253 | else if (strchr (name, ',')) |
16254 | { | |
16255 | /* Generic ".set" directive; use the generic handler. */ | |
16256 | *input_line_pointer = ch; | |
16257 | input_line_pointer = name; | |
16258 | s_set (0); | |
16259 | return; | |
16260 | } | |
252b5132 RH |
16261 | else |
16262 | { | |
16263 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16264 | } | |
16265 | *input_line_pointer = ch; | |
16266 | demand_empty_rest_of_line (); | |
16267 | } | |
16268 | ||
16269 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16270 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16271 | ||
16272 | static void | |
17a2f251 | 16273 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16274 | { |
16275 | mips_pic = SVR4_PIC; | |
143d77c5 | 16276 | mips_abicalls = TRUE; |
4d0d148d TS |
16277 | |
16278 | if (g_switch_seen && g_switch_value != 0) | |
16279 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16280 | g_switch_value = 0; | |
16281 | ||
252b5132 RH |
16282 | bfd_set_gp_size (stdoutput, 0); |
16283 | demand_empty_rest_of_line (); | |
16284 | } | |
16285 | ||
16286 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16287 | PIC code. It sets the $gp register for the function based on the | |
16288 | function address, which is in the register named in the argument. | |
16289 | This uses a relocation against _gp_disp, which is handled specially | |
16290 | by the linker. The result is: | |
16291 | lui $gp,%hi(_gp_disp) | |
16292 | addiu $gp,$gp,%lo(_gp_disp) | |
16293 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16294 | The .cpload argument is normally $25 == $t9. |
16295 | ||
16296 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16297 | lui $gp,%hi(__gnu_local_gp) |
16298 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16299 | and the argument is ignored. This saves an instruction, but the |
16300 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16301 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16302 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16303 | |
16304 | static void | |
17a2f251 | 16305 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16306 | { |
16307 | expressionS ex; | |
aa6975fb ILT |
16308 | int reg; |
16309 | int in_shared; | |
252b5132 | 16310 | |
6478892d TS |
16311 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16312 | .cpload is ignored. */ | |
16313 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16314 | { |
16315 | s_ignore (0); | |
16316 | return; | |
16317 | } | |
16318 | ||
d3ecfc59 | 16319 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16320 | if (mips_opts.noreorder == 0) |
16321 | as_warn (_(".cpload not in noreorder section")); | |
16322 | ||
aa6975fb ILT |
16323 | reg = tc_get_register (0); |
16324 | ||
16325 | /* If we need to produce a 64-bit address, we are better off using | |
16326 | the default instruction sequence. */ | |
aed1a261 | 16327 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16328 | |
252b5132 | 16329 | ex.X_op = O_symbol; |
bbe506e8 TS |
16330 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16331 | "__gnu_local_gp"); | |
252b5132 RH |
16332 | ex.X_op_symbol = NULL; |
16333 | ex.X_add_number = 0; | |
16334 | ||
16335 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16336 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16337 | |
584892a6 | 16338 | macro_start (); |
67c0d1eb RS |
16339 | macro_build_lui (&ex, mips_gp_register); |
16340 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16341 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16342 | if (in_shared) |
16343 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16344 | mips_gp_register, reg); | |
584892a6 | 16345 | macro_end (); |
252b5132 RH |
16346 | |
16347 | demand_empty_rest_of_line (); | |
16348 | } | |
16349 | ||
6478892d TS |
16350 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16351 | .cpsetup $reg1, offset|$reg2, label | |
16352 | ||
16353 | If offset is given, this results in: | |
16354 | sd $gp, offset($sp) | |
956cd1d6 | 16355 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16356 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16357 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16358 | |
16359 | If $reg2 is given, this results in: | |
16360 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16361 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16362 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16363 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16364 | $reg1 is normally $25 == $t9. |
16365 | ||
16366 | The -mno-shared option replaces the last three instructions with | |
16367 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16368 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16369 | |
6478892d | 16370 | static void |
17a2f251 | 16371 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16372 | { |
16373 | expressionS ex_off; | |
16374 | expressionS ex_sym; | |
16375 | int reg1; | |
6478892d | 16376 | |
8586fc66 | 16377 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16378 | We also need NewABI support. */ |
16379 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16380 | { | |
16381 | s_ignore (0); | |
16382 | return; | |
16383 | } | |
16384 | ||
16385 | reg1 = tc_get_register (0); | |
16386 | SKIP_WHITESPACE (); | |
16387 | if (*input_line_pointer != ',') | |
16388 | { | |
16389 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16390 | return; | |
16391 | } | |
16392 | else | |
80245285 | 16393 | ++input_line_pointer; |
6478892d TS |
16394 | SKIP_WHITESPACE (); |
16395 | if (*input_line_pointer == '$') | |
80245285 TS |
16396 | { |
16397 | mips_cpreturn_register = tc_get_register (0); | |
16398 | mips_cpreturn_offset = -1; | |
16399 | } | |
6478892d | 16400 | else |
80245285 TS |
16401 | { |
16402 | mips_cpreturn_offset = get_absolute_expression (); | |
16403 | mips_cpreturn_register = -1; | |
16404 | } | |
6478892d TS |
16405 | SKIP_WHITESPACE (); |
16406 | if (*input_line_pointer != ',') | |
16407 | { | |
16408 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16409 | return; | |
16410 | } | |
16411 | else | |
f9419b05 | 16412 | ++input_line_pointer; |
6478892d | 16413 | SKIP_WHITESPACE (); |
f21f8242 | 16414 | expression (&ex_sym); |
6478892d | 16415 | |
584892a6 | 16416 | macro_start (); |
6478892d TS |
16417 | if (mips_cpreturn_register == -1) |
16418 | { | |
16419 | ex_off.X_op = O_constant; | |
16420 | ex_off.X_add_symbol = NULL; | |
16421 | ex_off.X_op_symbol = NULL; | |
16422 | ex_off.X_add_number = mips_cpreturn_offset; | |
16423 | ||
67c0d1eb | 16424 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16425 | BFD_RELOC_LO16, SP); |
6478892d TS |
16426 | } |
16427 | else | |
67c0d1eb | 16428 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16429 | mips_gp_register, 0); |
6478892d | 16430 | |
aed1a261 | 16431 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16432 | { |
df58fc94 | 16433 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16434 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16435 | BFD_RELOC_HI16_S); | |
16436 | ||
16437 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16438 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16439 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16440 | ||
16441 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16442 | mips_gp_register, reg1); | |
16443 | } | |
16444 | else | |
16445 | { | |
16446 | expressionS ex; | |
16447 | ||
16448 | ex.X_op = O_symbol; | |
4184909a | 16449 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16450 | ex.X_op_symbol = NULL; |
16451 | ex.X_add_number = 0; | |
6e1304d8 | 16452 | |
aa6975fb ILT |
16453 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16454 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16455 | ||
16456 | macro_build_lui (&ex, mips_gp_register); | |
16457 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16458 | mips_gp_register, BFD_RELOC_LO16); | |
16459 | } | |
f21f8242 | 16460 | |
584892a6 | 16461 | macro_end (); |
6478892d TS |
16462 | |
16463 | demand_empty_rest_of_line (); | |
16464 | } | |
16465 | ||
16466 | static void | |
17a2f251 | 16467 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16468 | { |
16469 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16470 | .cplocal is ignored. */ |
6478892d TS |
16471 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16472 | { | |
16473 | s_ignore (0); | |
16474 | return; | |
16475 | } | |
16476 | ||
16477 | mips_gp_register = tc_get_register (0); | |
85b51719 | 16478 | demand_empty_rest_of_line (); |
6478892d TS |
16479 | } |
16480 | ||
252b5132 RH |
16481 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16482 | offset from $sp. The offset is remembered, and after making a PIC | |
16483 | call $gp is restored from that location. */ | |
16484 | ||
16485 | static void | |
17a2f251 | 16486 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16487 | { |
16488 | expressionS ex; | |
252b5132 | 16489 | |
6478892d | 16490 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16491 | .cprestore is ignored. */ |
6478892d | 16492 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16493 | { |
16494 | s_ignore (0); | |
16495 | return; | |
16496 | } | |
16497 | ||
16498 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 16499 | mips_cprestore_valid = 1; |
252b5132 RH |
16500 | |
16501 | ex.X_op = O_constant; | |
16502 | ex.X_add_symbol = NULL; | |
16503 | ex.X_op_symbol = NULL; | |
16504 | ex.X_add_number = mips_cprestore_offset; | |
16505 | ||
584892a6 | 16506 | macro_start (); |
67c0d1eb RS |
16507 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16508 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16509 | macro_end (); |
252b5132 RH |
16510 | |
16511 | demand_empty_rest_of_line (); | |
16512 | } | |
16513 | ||
6478892d | 16514 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16515 | was given in the preceding .cpsetup, it results in: |
6478892d | 16516 | ld $gp, offset($sp) |
76b3015f | 16517 | |
6478892d | 16518 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16519 | daddu $gp, $reg2, $0 */ |
16520 | ||
6478892d | 16521 | static void |
17a2f251 | 16522 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16523 | { |
16524 | expressionS ex; | |
6478892d TS |
16525 | |
16526 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16527 | We also need NewABI support. */ | |
16528 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16529 | { | |
16530 | s_ignore (0); | |
16531 | return; | |
16532 | } | |
16533 | ||
584892a6 | 16534 | macro_start (); |
6478892d TS |
16535 | if (mips_cpreturn_register == -1) |
16536 | { | |
16537 | ex.X_op = O_constant; | |
16538 | ex.X_add_symbol = NULL; | |
16539 | ex.X_op_symbol = NULL; | |
16540 | ex.X_add_number = mips_cpreturn_offset; | |
16541 | ||
67c0d1eb | 16542 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16543 | } |
16544 | else | |
67c0d1eb | 16545 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16546 | mips_cpreturn_register, 0); |
584892a6 | 16547 | macro_end (); |
6478892d TS |
16548 | |
16549 | demand_empty_rest_of_line (); | |
16550 | } | |
16551 | ||
741d6ea8 JM |
16552 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
16553 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
16554 | use in DWARF debug information. */ | |
16555 | ||
16556 | static void | |
16557 | s_dtprel_internal (size_t bytes) | |
16558 | { | |
16559 | expressionS ex; | |
16560 | char *p; | |
16561 | ||
16562 | expression (&ex); | |
16563 | ||
16564 | if (ex.X_op != O_symbol) | |
16565 | { | |
16566 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
16567 | ? ".dtpreldword" | |
16568 | : ".dtprelword")); | |
16569 | ignore_rest_of_line (); | |
16570 | } | |
16571 | ||
16572 | p = frag_more (bytes); | |
16573 | md_number_to_chars (p, 0, bytes); | |
16574 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
16575 | (bytes == 8 | |
16576 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
16577 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
16578 | ||
16579 | demand_empty_rest_of_line (); | |
16580 | } | |
16581 | ||
16582 | /* Handle .dtprelword. */ | |
16583 | ||
16584 | static void | |
16585 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16586 | { | |
16587 | s_dtprel_internal (4); | |
16588 | } | |
16589 | ||
16590 | /* Handle .dtpreldword. */ | |
16591 | ||
16592 | static void | |
16593 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16594 | { | |
16595 | s_dtprel_internal (8); | |
16596 | } | |
16597 | ||
6478892d TS |
16598 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16599 | code. It sets the offset to use in gp_rel relocations. */ | |
16600 | ||
16601 | static void | |
17a2f251 | 16602 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16603 | { |
16604 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16605 | We also need NewABI support. */ | |
16606 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16607 | { | |
16608 | s_ignore (0); | |
16609 | return; | |
16610 | } | |
16611 | ||
def2e0dd | 16612 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16613 | |
16614 | demand_empty_rest_of_line (); | |
16615 | } | |
16616 | ||
252b5132 RH |
16617 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16618 | code. It generates a 32 bit GP relative reloc. */ | |
16619 | ||
16620 | static void | |
17a2f251 | 16621 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16622 | { |
a8dbcb85 TS |
16623 | segment_info_type *si; |
16624 | struct insn_label_list *l; | |
252b5132 RH |
16625 | symbolS *label; |
16626 | expressionS ex; | |
16627 | char *p; | |
16628 | ||
16629 | /* When not generating PIC code, this is treated as .word. */ | |
16630 | if (mips_pic != SVR4_PIC) | |
16631 | { | |
16632 | s_cons (2); | |
16633 | return; | |
16634 | } | |
16635 | ||
a8dbcb85 TS |
16636 | si = seg_info (now_seg); |
16637 | l = si->label_list; | |
16638 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16639 | mips_emit_delays (); |
252b5132 RH |
16640 | if (auto_align) |
16641 | mips_align (2, 0, label); | |
252b5132 RH |
16642 | |
16643 | expression (&ex); | |
a1facbec | 16644 | mips_clear_insn_labels (); |
252b5132 RH |
16645 | |
16646 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16647 | { | |
16648 | as_bad (_("Unsupported use of .gpword")); | |
16649 | ignore_rest_of_line (); | |
16650 | } | |
16651 | ||
16652 | p = frag_more (4); | |
17a2f251 | 16653 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16654 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16655 | BFD_RELOC_GPREL32); |
252b5132 RH |
16656 | |
16657 | demand_empty_rest_of_line (); | |
16658 | } | |
16659 | ||
10181a0d | 16660 | static void |
17a2f251 | 16661 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16662 | { |
a8dbcb85 TS |
16663 | segment_info_type *si; |
16664 | struct insn_label_list *l; | |
10181a0d AO |
16665 | symbolS *label; |
16666 | expressionS ex; | |
16667 | char *p; | |
16668 | ||
16669 | /* When not generating PIC code, this is treated as .dword. */ | |
16670 | if (mips_pic != SVR4_PIC) | |
16671 | { | |
16672 | s_cons (3); | |
16673 | return; | |
16674 | } | |
16675 | ||
a8dbcb85 TS |
16676 | si = seg_info (now_seg); |
16677 | l = si->label_list; | |
16678 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16679 | mips_emit_delays (); |
10181a0d AO |
16680 | if (auto_align) |
16681 | mips_align (3, 0, label); | |
10181a0d AO |
16682 | |
16683 | expression (&ex); | |
a1facbec | 16684 | mips_clear_insn_labels (); |
10181a0d AO |
16685 | |
16686 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16687 | { | |
16688 | as_bad (_("Unsupported use of .gpdword")); | |
16689 | ignore_rest_of_line (); | |
16690 | } | |
16691 | ||
16692 | p = frag_more (8); | |
17a2f251 | 16693 | md_number_to_chars (p, 0, 8); |
a105a300 | 16694 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16695 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16696 | |
16697 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16698 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16699 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16700 | |
16701 | demand_empty_rest_of_line (); | |
16702 | } | |
16703 | ||
252b5132 RH |
16704 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16705 | tables in SVR4 PIC code. */ | |
16706 | ||
16707 | static void | |
17a2f251 | 16708 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16709 | { |
252b5132 RH |
16710 | int reg; |
16711 | ||
10181a0d AO |
16712 | /* This is ignored when not generating SVR4 PIC code. */ |
16713 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16714 | { |
16715 | s_ignore (0); | |
16716 | return; | |
16717 | } | |
16718 | ||
16719 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16720 | macro_start (); |
252b5132 | 16721 | reg = tc_get_register (0); |
67c0d1eb | 16722 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16723 | macro_end (); |
252b5132 | 16724 | |
bdaaa2e1 | 16725 | demand_empty_rest_of_line (); |
252b5132 RH |
16726 | } |
16727 | ||
16728 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16729 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16730 | such as generating jalx instructions when needed. We also make |
16731 | them odd for the duration of the assembly, in order to generate the | |
16732 | right sort of code. We will make them even in the adjust_symtab | |
16733 | routine, while leaving them marked. This is convenient for the | |
16734 | debugger and the disassembler. The linker knows to make them odd | |
16735 | again. */ | |
16736 | ||
16737 | static void | |
17a2f251 | 16738 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16739 | { |
df58fc94 | 16740 | mips_mark_labels (); |
252b5132 RH |
16741 | |
16742 | demand_empty_rest_of_line (); | |
16743 | } | |
16744 | ||
16745 | /* Handle a .stabn directive. We need these in order to mark a label | |
16746 | as being a mips16 text label correctly. Sometimes the compiler | |
16747 | will emit a label, followed by a .stabn, and then switch sections. | |
16748 | If the label and .stabn are in mips16 mode, then the label is | |
16749 | really a mips16 text label. */ | |
16750 | ||
16751 | static void | |
17a2f251 | 16752 | s_mips_stab (int type) |
252b5132 | 16753 | { |
f9419b05 | 16754 | if (type == 'n') |
df58fc94 | 16755 | mips_mark_labels (); |
252b5132 RH |
16756 | |
16757 | s_stab (type); | |
16758 | } | |
16759 | ||
54f4ddb3 | 16760 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16761 | |
16762 | static void | |
17a2f251 | 16763 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16764 | { |
16765 | char *name; | |
16766 | int c; | |
16767 | symbolS *symbolP; | |
16768 | expressionS exp; | |
16769 | ||
16770 | name = input_line_pointer; | |
16771 | c = get_symbol_end (); | |
16772 | symbolP = symbol_find_or_make (name); | |
16773 | S_SET_WEAK (symbolP); | |
16774 | *input_line_pointer = c; | |
16775 | ||
16776 | SKIP_WHITESPACE (); | |
16777 | ||
16778 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16779 | { | |
16780 | if (S_IS_DEFINED (symbolP)) | |
16781 | { | |
20203fb9 | 16782 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16783 | S_GET_NAME (symbolP)); |
16784 | ignore_rest_of_line (); | |
16785 | return; | |
16786 | } | |
bdaaa2e1 | 16787 | |
252b5132 RH |
16788 | if (*input_line_pointer == ',') |
16789 | { | |
16790 | ++input_line_pointer; | |
16791 | SKIP_WHITESPACE (); | |
16792 | } | |
bdaaa2e1 | 16793 | |
252b5132 RH |
16794 | expression (&exp); |
16795 | if (exp.X_op != O_symbol) | |
16796 | { | |
20203fb9 | 16797 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16798 | ignore_rest_of_line (); |
252b5132 RH |
16799 | return; |
16800 | } | |
49309057 | 16801 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16802 | } |
16803 | ||
16804 | demand_empty_rest_of_line (); | |
16805 | } | |
16806 | ||
16807 | /* Parse a register string into a number. Called from the ECOFF code | |
16808 | to parse .frame. The argument is non-zero if this is the frame | |
16809 | register, so that we can record it in mips_frame_reg. */ | |
16810 | ||
16811 | int | |
17a2f251 | 16812 | tc_get_register (int frame) |
252b5132 | 16813 | { |
707bfff6 | 16814 | unsigned int reg; |
252b5132 RH |
16815 | |
16816 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16817 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16818 | reg = 0; | |
252b5132 | 16819 | if (frame) |
7a621144 DJ |
16820 | { |
16821 | mips_frame_reg = reg != 0 ? reg : SP; | |
16822 | mips_frame_reg_valid = 1; | |
16823 | mips_cprestore_valid = 0; | |
16824 | } | |
252b5132 RH |
16825 | return reg; |
16826 | } | |
16827 | ||
16828 | valueT | |
17a2f251 | 16829 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16830 | { |
16831 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16832 | ||
b4c71f56 TS |
16833 | if (IS_ELF) |
16834 | { | |
16835 | /* We don't need to align ELF sections to the full alignment. | |
16836 | However, Irix 5 may prefer that we align them at least to a 16 | |
16837 | byte boundary. We don't bother to align the sections if we | |
16838 | are targeted for an embedded system. */ | |
c41e87e3 | 16839 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
16840 | return addr; |
16841 | if (align > 4) | |
16842 | align = 4; | |
16843 | } | |
252b5132 RH |
16844 | |
16845 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
16846 | } | |
16847 | ||
16848 | /* Utility routine, called from above as well. If called while the | |
16849 | input file is still being read, it's only an approximation. (For | |
16850 | example, a symbol may later become defined which appeared to be | |
16851 | undefined earlier.) */ | |
16852 | ||
16853 | static int | |
17a2f251 | 16854 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16855 | { |
16856 | if (sym == 0) | |
16857 | return 0; | |
16858 | ||
4d0d148d | 16859 | if (g_switch_value > 0) |
252b5132 RH |
16860 | { |
16861 | const char *symname; | |
16862 | int change; | |
16863 | ||
c9914766 | 16864 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16865 | register. It can be if it is smaller than the -G size or if |
16866 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16867 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16868 | they can. */ |
16869 | symname = S_GET_NAME (sym); | |
16870 | if (symname != (const char *) NULL | |
16871 | && (strcmp (symname, "eprol") == 0 | |
16872 | || strcmp (symname, "etext") == 0 | |
16873 | || strcmp (symname, "_gp") == 0 | |
16874 | || strcmp (symname, "edata") == 0 | |
16875 | || strcmp (symname, "_fbss") == 0 | |
16876 | || strcmp (symname, "_fdata") == 0 | |
16877 | || strcmp (symname, "_ftext") == 0 | |
16878 | || strcmp (symname, "end") == 0 | |
16879 | || strcmp (symname, "_gp_disp") == 0)) | |
16880 | change = 1; | |
16881 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16882 | && (0 | |
16883 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16884 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16885 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16886 | <= g_switch_value)) | |
252b5132 RH |
16887 | #endif |
16888 | /* We must defer this decision until after the whole | |
16889 | file has been read, since there might be a .extern | |
16890 | after the first use of this symbol. */ | |
16891 | || (before_relaxing | |
16892 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16893 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16894 | #endif |
16895 | && S_GET_VALUE (sym) == 0) | |
16896 | || (S_GET_VALUE (sym) != 0 | |
16897 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16898 | change = 0; | |
16899 | else | |
16900 | { | |
16901 | const char *segname; | |
16902 | ||
16903 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16904 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16905 | && strcmp (segname, ".lit4") != 0); |
16906 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16907 | && strcmp (segname, ".sbss") != 0 |
16908 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16909 | && strncmp (segname, ".sbss.", 6) != 0 |
16910 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16911 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16912 | } |
16913 | return change; | |
16914 | } | |
16915 | else | |
c9914766 | 16916 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16917 | return 1; |
16918 | } | |
16919 | ||
5919d012 RS |
16920 | |
16921 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16922 | ||
16923 | static bfd_boolean | |
17a2f251 | 16924 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16925 | { |
16926 | asection *symsec; | |
5919d012 RS |
16927 | |
16928 | /* Handle the case of a symbol equated to another symbol. */ | |
16929 | while (symbol_equated_reloc_p (sym)) | |
16930 | { | |
16931 | symbolS *n; | |
16932 | ||
5f0fe04b | 16933 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16934 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16935 | if (n == sym) | |
16936 | break; | |
16937 | sym = n; | |
16938 | } | |
16939 | ||
df1f3cda DD |
16940 | if (symbol_section_p (sym)) |
16941 | return TRUE; | |
16942 | ||
5919d012 RS |
16943 | symsec = S_GET_SEGMENT (sym); |
16944 | ||
5919d012 RS |
16945 | /* This must duplicate the test in adjust_reloc_syms. */ |
16946 | return (symsec != &bfd_und_section | |
16947 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
16948 | && !bfd_is_com_section (symsec) |
16949 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
16950 | #ifdef OBJ_ELF |
16951 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 16952 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
16953 | #endif |
16954 | ); | |
16955 | } | |
16956 | ||
16957 | ||
252b5132 RH |
16958 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16959 | extended opcode. SEC is the section the frag is in. */ | |
16960 | ||
16961 | static int | |
17a2f251 | 16962 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16963 | { |
16964 | int type; | |
3994f87e | 16965 | const struct mips16_immed_operand *op; |
252b5132 RH |
16966 | offsetT val; |
16967 | int mintiny, maxtiny; | |
16968 | segT symsec; | |
98aa84af | 16969 | fragS *sym_frag; |
252b5132 RH |
16970 | |
16971 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16972 | return 0; | |
16973 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16974 | return 1; | |
16975 | ||
16976 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
16977 | op = mips16_immed_operands; | |
16978 | while (op->type != type) | |
16979 | { | |
16980 | ++op; | |
9c2799c2 | 16981 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
16982 | } |
16983 | ||
16984 | if (op->unsp) | |
16985 | { | |
16986 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
16987 | { | |
16988 | mintiny = 1; | |
16989 | maxtiny = 1 << op->nbits; | |
16990 | } | |
16991 | else | |
16992 | { | |
16993 | mintiny = 0; | |
16994 | maxtiny = (1 << op->nbits) - 1; | |
16995 | } | |
16996 | } | |
16997 | else | |
16998 | { | |
16999 | mintiny = - (1 << (op->nbits - 1)); | |
17000 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17001 | } | |
17002 | ||
98aa84af | 17003 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17004 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17005 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17006 | |
17007 | if (op->pcrel) | |
17008 | { | |
17009 | addressT addr; | |
17010 | ||
17011 | /* We won't have the section when we are called from | |
17012 | mips_relax_frag. However, we will always have been called | |
17013 | from md_estimate_size_before_relax first. If this is a | |
17014 | branch to a different section, we mark it as such. If SEC is | |
17015 | NULL, and the frag is not marked, then it must be a branch to | |
17016 | the same section. */ | |
17017 | if (sec == NULL) | |
17018 | { | |
17019 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17020 | return 1; | |
17021 | } | |
17022 | else | |
17023 | { | |
98aa84af | 17024 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17025 | if (symsec != sec) |
17026 | { | |
17027 | fragp->fr_subtype = | |
17028 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17029 | ||
17030 | /* FIXME: We should support this, and let the linker | |
17031 | catch branches and loads that are out of range. */ | |
17032 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17033 | _("unsupported PC relative reference to different section")); | |
17034 | ||
17035 | return 1; | |
17036 | } | |
98aa84af AM |
17037 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17038 | /* Assume non-extended on the first relaxation pass. | |
17039 | The address we have calculated will be bogus if this is | |
17040 | a forward branch to another frag, as the forward frag | |
17041 | will have fr_address == 0. */ | |
17042 | return 0; | |
252b5132 RH |
17043 | } |
17044 | ||
17045 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17046 | the same section. If the relax_marker of the symbol fragment |
17047 | differs from the relax_marker of this fragment, we have not | |
17048 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17049 | in STRETCH in order to get a better estimate of the address. |
17050 | This particularly matters because of the shift bits. */ | |
17051 | if (stretch != 0 | |
98aa84af | 17052 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17053 | { |
17054 | fragS *f; | |
17055 | ||
17056 | /* Adjust stretch for any alignment frag. Note that if have | |
17057 | been expanding the earlier code, the symbol may be | |
17058 | defined in what appears to be an earlier frag. FIXME: | |
17059 | This doesn't handle the fr_subtype field, which specifies | |
17060 | a maximum number of bytes to skip when doing an | |
17061 | alignment. */ | |
98aa84af | 17062 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17063 | { |
17064 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17065 | { | |
17066 | if (stretch < 0) | |
17067 | stretch = - ((- stretch) | |
17068 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17069 | else | |
17070 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17071 | if (stretch == 0) | |
17072 | break; | |
17073 | } | |
17074 | } | |
17075 | if (f != NULL) | |
17076 | val += stretch; | |
17077 | } | |
17078 | ||
17079 | addr = fragp->fr_address + fragp->fr_fix; | |
17080 | ||
17081 | /* The base address rules are complicated. The base address of | |
17082 | a branch is the following instruction. The base address of a | |
17083 | PC relative load or add is the instruction itself, but if it | |
17084 | is in a delay slot (in which case it can not be extended) use | |
17085 | the address of the instruction whose delay slot it is in. */ | |
17086 | if (type == 'p' || type == 'q') | |
17087 | { | |
17088 | addr += 2; | |
17089 | ||
17090 | /* If we are currently assuming that this frag should be | |
17091 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17092 | higher. */ |
252b5132 RH |
17093 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17094 | addr += 2; | |
17095 | ||
17096 | /* Ignore the low bit in the target, since it will be set | |
17097 | for a text label. */ | |
17098 | if ((val & 1) != 0) | |
17099 | --val; | |
17100 | } | |
17101 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17102 | addr -= 4; | |
17103 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17104 | addr -= 2; | |
17105 | ||
17106 | val -= addr & ~ ((1 << op->shift) - 1); | |
17107 | ||
17108 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17109 | if (type == 'p' || type == 'q') | |
17110 | val /= 2; | |
17111 | ||
17112 | /* If any of the shifted bits are set, we must use an extended | |
17113 | opcode. If the address depends on the size of this | |
17114 | instruction, this can lead to a loop, so we arrange to always | |
17115 | use an extended opcode. We only check this when we are in | |
17116 | the main relaxation loop, when SEC is NULL. */ | |
17117 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17118 | { | |
17119 | fragp->fr_subtype = | |
17120 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17121 | return 1; | |
17122 | } | |
17123 | ||
17124 | /* If we are about to mark a frag as extended because the value | |
17125 | is precisely maxtiny + 1, then there is a chance of an | |
17126 | infinite loop as in the following code: | |
17127 | la $4,foo | |
17128 | .skip 1020 | |
17129 | .align 2 | |
17130 | foo: | |
17131 | In this case when the la is extended, foo is 0x3fc bytes | |
17132 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17133 | the la must be extended. To avoid this loop, we mark the | |
17134 | frag as extended if it was small, and is about to become | |
17135 | extended with a value of maxtiny + 1. */ | |
17136 | if (val == ((maxtiny + 1) << op->shift) | |
17137 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17138 | && sec == NULL) | |
17139 | { | |
17140 | fragp->fr_subtype = | |
17141 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17142 | return 1; | |
17143 | } | |
17144 | } | |
17145 | else if (symsec != absolute_section && sec != NULL) | |
17146 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17147 | ||
17148 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17149 | || val < (mintiny << op->shift) | |
17150 | || val > (maxtiny << op->shift)) | |
17151 | return 1; | |
17152 | else | |
17153 | return 0; | |
17154 | } | |
17155 | ||
4a6a3df4 AO |
17156 | /* Compute the length of a branch sequence, and adjust the |
17157 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17158 | worst-case length is computed, with UPDATE being used to indicate | |
17159 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17160 | branch is to be computed. */ | |
17161 | static int | |
17a2f251 | 17162 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17163 | { |
b34976b6 | 17164 | bfd_boolean toofar; |
4a6a3df4 AO |
17165 | int length; |
17166 | ||
17167 | if (fragp | |
17168 | && S_IS_DEFINED (fragp->fr_symbol) | |
17169 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17170 | { | |
17171 | addressT addr; | |
17172 | offsetT val; | |
17173 | ||
17174 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17175 | ||
17176 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17177 | ||
17178 | val -= addr; | |
17179 | ||
17180 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17181 | } | |
17182 | else if (fragp) | |
17183 | /* If the symbol is not defined or it's in a different segment, | |
17184 | assume the user knows what's going on and emit a short | |
17185 | branch. */ | |
b34976b6 | 17186 | toofar = FALSE; |
4a6a3df4 | 17187 | else |
b34976b6 | 17188 | toofar = TRUE; |
4a6a3df4 AO |
17189 | |
17190 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17191 | fragp->fr_subtype | |
66b3e8da MR |
17192 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17193 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17194 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17195 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17196 | toofar); | |
17197 | ||
17198 | length = 4; | |
17199 | if (toofar) | |
17200 | { | |
17201 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17202 | length += 8; | |
17203 | ||
17204 | if (mips_pic != NO_PIC) | |
17205 | { | |
17206 | /* Additional space for PIC loading of target address. */ | |
17207 | length += 8; | |
17208 | if (mips_opts.isa == ISA_MIPS1) | |
17209 | /* Additional space for $at-stabilizing nop. */ | |
17210 | length += 4; | |
17211 | } | |
17212 | ||
17213 | /* If branch is conditional. */ | |
17214 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17215 | length += 8; | |
17216 | } | |
b34976b6 | 17217 | |
4a6a3df4 AO |
17218 | return length; |
17219 | } | |
17220 | ||
df58fc94 RS |
17221 | /* Compute the length of a branch sequence, and adjust the |
17222 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17223 | worst-case length is computed, with UPDATE being used to indicate | |
17224 | whether an unconditional (-1), or regular (0) branch is to be | |
17225 | computed. */ | |
17226 | ||
17227 | static int | |
17228 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17229 | { | |
17230 | bfd_boolean toofar; | |
17231 | int length; | |
17232 | ||
17233 | if (fragp | |
17234 | && S_IS_DEFINED (fragp->fr_symbol) | |
17235 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17236 | { | |
17237 | addressT addr; | |
17238 | offsetT val; | |
17239 | ||
17240 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17241 | /* Ignore the low bit in the target, since it will be set | |
17242 | for a text label. */ | |
17243 | if ((val & 1) != 0) | |
17244 | --val; | |
17245 | ||
17246 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17247 | ||
17248 | val -= addr; | |
17249 | ||
17250 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17251 | } | |
17252 | else if (fragp) | |
17253 | /* If the symbol is not defined or it's in a different segment, | |
17254 | assume the user knows what's going on and emit a short | |
17255 | branch. */ | |
17256 | toofar = FALSE; | |
17257 | else | |
17258 | toofar = TRUE; | |
17259 | ||
17260 | if (fragp && update | |
17261 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17262 | fragp->fr_subtype = (toofar | |
17263 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17264 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17265 | ||
17266 | length = 4; | |
17267 | if (toofar) | |
17268 | { | |
17269 | bfd_boolean compact_known = fragp != NULL; | |
17270 | bfd_boolean compact = FALSE; | |
17271 | bfd_boolean uncond; | |
17272 | ||
17273 | if (compact_known) | |
17274 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17275 | if (fragp) | |
17276 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17277 | else | |
17278 | uncond = update < 0; | |
17279 | ||
17280 | /* If label is out of range, we turn branch <br>: | |
17281 | ||
17282 | <br> label # 4 bytes | |
17283 | 0: | |
17284 | ||
17285 | into: | |
17286 | ||
17287 | j label # 4 bytes | |
17288 | nop # 2 bytes if compact && !PIC | |
17289 | 0: | |
17290 | */ | |
17291 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17292 | length += 2; | |
17293 | ||
17294 | /* If assembling PIC code, we further turn: | |
17295 | ||
17296 | j label # 4 bytes | |
17297 | ||
17298 | into: | |
17299 | ||
17300 | lw/ld at, %got(label)(gp) # 4 bytes | |
17301 | d/addiu at, %lo(label) # 4 bytes | |
17302 | jr/c at # 2 bytes | |
17303 | */ | |
17304 | if (mips_pic != NO_PIC) | |
17305 | length += 6; | |
17306 | ||
17307 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17308 | ||
17309 | <brneg> 0f # 4 bytes | |
17310 | nop # 2 bytes if !compact | |
17311 | */ | |
17312 | if (!uncond) | |
17313 | length += (compact_known && compact) ? 4 : 6; | |
17314 | } | |
17315 | ||
17316 | return length; | |
17317 | } | |
17318 | ||
17319 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17320 | bit accordingly. */ | |
17321 | ||
17322 | static int | |
17323 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17324 | { | |
17325 | bfd_boolean toofar; | |
17326 | ||
df58fc94 RS |
17327 | if (fragp |
17328 | && S_IS_DEFINED (fragp->fr_symbol) | |
17329 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17330 | { | |
17331 | addressT addr; | |
17332 | offsetT val; | |
17333 | int type; | |
17334 | ||
17335 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17336 | /* Ignore the low bit in the target, since it will be set | |
17337 | for a text label. */ | |
17338 | if ((val & 1) != 0) | |
17339 | --val; | |
17340 | ||
17341 | /* Assume this is a 2-byte branch. */ | |
17342 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17343 | ||
17344 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17345 | long branches. */ | |
17346 | ||
17347 | val -= addr; | |
17348 | ||
17349 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17350 | if (type == 'D') | |
17351 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17352 | else if (type == 'E') | |
17353 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17354 | else | |
17355 | abort (); | |
17356 | } | |
17357 | else | |
17358 | /* If the symbol is not defined or it's in a different segment, | |
17359 | we emit a normal 32-bit branch. */ | |
17360 | toofar = TRUE; | |
17361 | ||
17362 | if (fragp && update | |
17363 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17364 | fragp->fr_subtype | |
17365 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17366 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17367 | ||
17368 | if (toofar) | |
17369 | return 4; | |
17370 | ||
17371 | return 2; | |
17372 | } | |
17373 | ||
252b5132 RH |
17374 | /* Estimate the size of a frag before relaxing. Unless this is the |
17375 | mips16, we are not really relaxing here, and the final size is | |
17376 | encoded in the subtype information. For the mips16, we have to | |
17377 | decide whether we are using an extended opcode or not. */ | |
17378 | ||
252b5132 | 17379 | int |
17a2f251 | 17380 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17381 | { |
5919d012 | 17382 | int change; |
252b5132 | 17383 | |
4a6a3df4 AO |
17384 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17385 | { | |
17386 | ||
b34976b6 AM |
17387 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17388 | ||
4a6a3df4 AO |
17389 | return fragp->fr_var; |
17390 | } | |
17391 | ||
252b5132 | 17392 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17393 | /* We don't want to modify the EXTENDED bit here; it might get us |
17394 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17395 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17396 | |
df58fc94 RS |
17397 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17398 | { | |
17399 | int length = 4; | |
17400 | ||
17401 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17402 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17403 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17404 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17405 | fragp->fr_var = length; | |
17406 | ||
17407 | return length; | |
17408 | } | |
17409 | ||
252b5132 | 17410 | if (mips_pic == NO_PIC) |
5919d012 | 17411 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17412 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17413 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17414 | else if (mips_pic == VXWORKS_PIC) |
17415 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17416 | change = 0; | |
252b5132 RH |
17417 | else |
17418 | abort (); | |
17419 | ||
17420 | if (change) | |
17421 | { | |
4d7206a2 | 17422 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17423 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17424 | } |
4d7206a2 RS |
17425 | else |
17426 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17427 | } |
17428 | ||
17429 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17430 | should be converted into a reloc against a section. */ |
252b5132 RH |
17431 | |
17432 | int | |
17a2f251 | 17433 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17434 | { |
252b5132 RH |
17435 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17436 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17437 | return 0; | |
a161fe53 | 17438 | |
252b5132 RH |
17439 | if (fixp->fx_addsy == NULL) |
17440 | return 1; | |
a161fe53 | 17441 | |
de7e6852 RS |
17442 | /* If symbol SYM is in a mergeable section, relocations of the form |
17443 | SYM + 0 can usually be made section-relative. The mergeable data | |
17444 | is then identified by the section offset rather than by the symbol. | |
17445 | ||
17446 | However, if we're generating REL LO16 relocations, the offset is split | |
17447 | between the LO16 and parterning high part relocation. The linker will | |
17448 | need to recalculate the complete offset in order to correctly identify | |
17449 | the merge data. | |
17450 | ||
17451 | The linker has traditionally not looked for the parterning high part | |
17452 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17453 | placed anywhere. Rather than break backwards compatibility by changing | |
17454 | this, it seems better not to force the issue, and instead keep the | |
17455 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17456 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17457 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17458 | && HAVE_IN_PLACE_ADDENDS |
17459 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17460 | return 0; | |
17461 | ||
ce70d90a MR |
17462 | /* There is no place to store an in-place offset for JALR relocations. |
17463 | Likewise an in-range offset of PC-relative relocations may overflow | |
17464 | the in-place relocatable field if recalculated against the start | |
17465 | address of the symbol's containing section. */ | |
17466 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17467 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17468 | return 0; |
17469 | ||
252b5132 | 17470 | #ifdef OBJ_ELF |
b314ec0e RS |
17471 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17472 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17473 | relocations against MIPS16 functions; in this case, the stub becomes | |
17474 | the function's canonical address. | |
17475 | ||
17476 | Floating-point stubs are stored in unique .mips16.call.* or | |
17477 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17478 | the first relocation in section S must be against F; this is how the | |
17479 | linker determines the target function. All relocations that might | |
17480 | resolve to T must also be against F. We therefore have the following | |
17481 | restrictions, which are given in an intentionally-redundant way: | |
17482 | ||
17483 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17484 | symbols. | |
17485 | ||
17486 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17487 | if that stub might be used. | |
17488 | ||
17489 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17490 | symbols. | |
17491 | ||
17492 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17493 | that stub might be used. | |
17494 | ||
17495 | There is a further restriction: | |
17496 | ||
df58fc94 RS |
17497 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17498 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17499 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17500 | encode the low bit. |
17501 | ||
df58fc94 RS |
17502 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17503 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17504 | such relocations on REL targets. | |
b314ec0e RS |
17505 | |
17506 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17507 | relocation against some symbol R, no relocation against R may be | |
17508 | reduced. (Note that this deals with (2) as well as (1) because | |
17509 | relocations against global symbols will never be reduced on ELF | |
17510 | targets.) This approach is a little simpler than trying to detect | |
17511 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17512 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17513 | if (IS_ELF |
b314ec0e | 17514 | && fixp->fx_subsy == NULL |
30c09090 | 17515 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17516 | || *symbol_get_tc (fixp->fx_addsy) |
17517 | || (HAVE_IN_PLACE_ADDENDS | |
17518 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17519 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17520 | return 0; |
17521 | #endif | |
a161fe53 | 17522 | |
252b5132 RH |
17523 | return 1; |
17524 | } | |
17525 | ||
17526 | /* Translate internal representation of relocation info to BFD target | |
17527 | format. */ | |
17528 | ||
17529 | arelent ** | |
17a2f251 | 17530 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17531 | { |
17532 | static arelent *retval[4]; | |
17533 | arelent *reloc; | |
17534 | bfd_reloc_code_real_type code; | |
17535 | ||
4b0cff4e TS |
17536 | memset (retval, 0, sizeof(retval)); |
17537 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17538 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17539 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17540 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17541 | ||
bad36eac DJ |
17542 | if (fixp->fx_pcrel) |
17543 | { | |
df58fc94 RS |
17544 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17545 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17546 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17547 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17548 | |
17549 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17550 | Relocations want only the symbol offset. */ | |
17551 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17552 | if (!IS_ELF) |
bad36eac DJ |
17553 | { |
17554 | /* A gruesome hack which is a result of the gruesome gas | |
17555 | reloc handling. What's worse, for COFF (as opposed to | |
17556 | ECOFF), we might need yet another copy of reloc->address. | |
17557 | See bfd_install_relocation. */ | |
17558 | reloc->addend += reloc->address; | |
17559 | } | |
17560 | } | |
17561 | else | |
17562 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17563 | |
438c16b8 TS |
17564 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17565 | entry to be used in the relocation's section offset. */ | |
17566 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17567 | { |
17568 | reloc->address = reloc->addend; | |
17569 | reloc->addend = 0; | |
17570 | } | |
17571 | ||
252b5132 | 17572 | code = fixp->fx_r_type; |
252b5132 | 17573 | |
bad36eac | 17574 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17575 | if (reloc->howto == NULL) |
17576 | { | |
17577 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17578 | _("Can not represent %s relocation in this object file format"), | |
17579 | bfd_get_reloc_code_name (code)); | |
17580 | retval[0] = NULL; | |
17581 | } | |
17582 | ||
17583 | return retval; | |
17584 | } | |
17585 | ||
17586 | /* Relax a machine dependent frag. This returns the amount by which | |
17587 | the current size of the frag should change. */ | |
17588 | ||
17589 | int | |
17a2f251 | 17590 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17591 | { |
4a6a3df4 AO |
17592 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17593 | { | |
17594 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17595 | |
17596 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17597 | |
17598 | return fragp->fr_var - old_var; | |
17599 | } | |
17600 | ||
df58fc94 RS |
17601 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17602 | { | |
17603 | offsetT old_var = fragp->fr_var; | |
17604 | offsetT new_var = 4; | |
17605 | ||
17606 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17607 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17608 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17609 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17610 | fragp->fr_var = new_var; | |
17611 | ||
17612 | return new_var - old_var; | |
17613 | } | |
17614 | ||
252b5132 RH |
17615 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17616 | return 0; | |
17617 | ||
c4e7957c | 17618 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17619 | { |
17620 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17621 | return 0; | |
17622 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17623 | return 2; | |
17624 | } | |
17625 | else | |
17626 | { | |
17627 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17628 | return 0; | |
17629 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17630 | return -2; | |
17631 | } | |
17632 | ||
17633 | return 0; | |
17634 | } | |
17635 | ||
17636 | /* Convert a machine dependent frag. */ | |
17637 | ||
17638 | void | |
17a2f251 | 17639 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17640 | { |
4a6a3df4 AO |
17641 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17642 | { | |
17643 | bfd_byte *buf; | |
17644 | unsigned long insn; | |
17645 | expressionS exp; | |
17646 | fixS *fixp; | |
b34976b6 | 17647 | |
4a6a3df4 AO |
17648 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
17649 | ||
17650 | if (target_big_endian) | |
17651 | insn = bfd_getb32 (buf); | |
17652 | else | |
17653 | insn = bfd_getl32 (buf); | |
b34976b6 | 17654 | |
4a6a3df4 AO |
17655 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17656 | { | |
17657 | /* We generate a fixup instead of applying it right now | |
17658 | because, if there are linker relaxations, we're going to | |
17659 | need the relocations. */ | |
17660 | exp.X_op = O_symbol; | |
17661 | exp.X_add_symbol = fragp->fr_symbol; | |
17662 | exp.X_add_number = fragp->fr_offset; | |
17663 | ||
17664 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17665 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
17666 | fixp->fx_file = fragp->fr_file; |
17667 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17668 | |
2132e3a3 | 17669 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17670 | buf += 4; |
17671 | } | |
17672 | else | |
17673 | { | |
17674 | int i; | |
17675 | ||
17676 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17677 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17678 | |
17679 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17680 | goto uncond; | |
17681 | ||
17682 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17683 | { | |
17684 | /* Reverse the branch. */ | |
17685 | switch ((insn >> 28) & 0xf) | |
17686 | { | |
17687 | case 4: | |
17688 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17689 | have the condition reversed by tweaking a single | |
17690 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17691 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17692 | insn ^= 0x00010000; |
17693 | break; | |
17694 | ||
17695 | case 0: | |
17696 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17697 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17698 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17699 | insn ^= 0x00010000; |
17700 | break; | |
b34976b6 | 17701 | |
4a6a3df4 AO |
17702 | case 1: |
17703 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17704 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17705 | insn ^= 0x04000000; |
17706 | break; | |
17707 | ||
17708 | default: | |
17709 | abort (); | |
17710 | } | |
17711 | } | |
17712 | ||
17713 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17714 | { | |
17715 | /* Clear the and-link bit. */ | |
9c2799c2 | 17716 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17717 | |
54f4ddb3 TS |
17718 | /* bltzal 0x04100000 bgezal 0x04110000 |
17719 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17720 | insn &= ~0x00100000; |
17721 | } | |
17722 | ||
17723 | /* Branch over the branch (if the branch was likely) or the | |
17724 | full jump (not likely case). Compute the offset from the | |
17725 | current instruction to branch to. */ | |
17726 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17727 | i = 16; | |
17728 | else | |
17729 | { | |
17730 | /* How many bytes in instructions we've already emitted? */ | |
17731 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17732 | /* How many bytes in instructions from here to the end? */ | |
17733 | i = fragp->fr_var - i; | |
17734 | } | |
17735 | /* Convert to instruction count. */ | |
17736 | i >>= 2; | |
17737 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17738 | i--; |
4a6a3df4 AO |
17739 | insn |= i; |
17740 | /* Branch over the jump. */ | |
2132e3a3 | 17741 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17742 | buf += 4; |
17743 | ||
54f4ddb3 | 17744 | /* nop */ |
2132e3a3 | 17745 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17746 | buf += 4; |
17747 | ||
17748 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17749 | { | |
17750 | /* beql $0, $0, 2f */ | |
17751 | insn = 0x50000000; | |
17752 | /* Compute the PC offset from the current instruction to | |
17753 | the end of the variable frag. */ | |
17754 | /* How many bytes in instructions we've already emitted? */ | |
17755 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17756 | /* How many bytes in instructions from here to the end? */ | |
17757 | i = fragp->fr_var - i; | |
17758 | /* Convert to instruction count. */ | |
17759 | i >>= 2; | |
17760 | /* Don't decrement i, because we want to branch over the | |
17761 | delay slot. */ | |
17762 | ||
17763 | insn |= i; | |
2132e3a3 | 17764 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17765 | buf += 4; |
17766 | ||
2132e3a3 | 17767 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17768 | buf += 4; |
17769 | } | |
17770 | ||
17771 | uncond: | |
17772 | if (mips_pic == NO_PIC) | |
17773 | { | |
17774 | /* j or jal. */ | |
17775 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17776 | ? 0x0c000000 : 0x08000000); | |
17777 | exp.X_op = O_symbol; | |
17778 | exp.X_add_symbol = fragp->fr_symbol; | |
17779 | exp.X_add_number = fragp->fr_offset; | |
17780 | ||
17781 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17782 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
17783 | fixp->fx_file = fragp->fr_file; |
17784 | fixp->fx_line = fragp->fr_line; | |
17785 | ||
2132e3a3 | 17786 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17787 | buf += 4; |
17788 | } | |
17789 | else | |
17790 | { | |
66b3e8da MR |
17791 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17792 | ||
4a6a3df4 | 17793 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17794 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17795 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17796 | exp.X_op = O_symbol; |
17797 | exp.X_add_symbol = fragp->fr_symbol; | |
17798 | exp.X_add_number = fragp->fr_offset; | |
17799 | ||
17800 | if (fragp->fr_offset) | |
17801 | { | |
17802 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17803 | exp.X_add_number = 0; | |
17804 | } | |
17805 | ||
17806 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17807 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
17808 | fixp->fx_file = fragp->fr_file; |
17809 | fixp->fx_line = fragp->fr_line; | |
17810 | ||
2132e3a3 | 17811 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 17812 | buf += 4; |
b34976b6 | 17813 | |
4a6a3df4 AO |
17814 | if (mips_opts.isa == ISA_MIPS1) |
17815 | { | |
17816 | /* nop */ | |
2132e3a3 | 17817 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17818 | buf += 4; |
17819 | } | |
17820 | ||
17821 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17822 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17823 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
17824 | |
17825 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17826 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
17827 | fixp->fx_file = fragp->fr_file; |
17828 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17829 | |
2132e3a3 | 17830 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17831 | buf += 4; |
17832 | ||
17833 | /* j(al)r $at. */ | |
17834 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17835 | insn = 0x0000f809; |
4a6a3df4 | 17836 | else |
66b3e8da MR |
17837 | insn = 0x00000008; |
17838 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17839 | |
2132e3a3 | 17840 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17841 | buf += 4; |
17842 | } | |
17843 | } | |
17844 | ||
9c2799c2 | 17845 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
17846 | + fragp->fr_fix + fragp->fr_var); |
17847 | ||
17848 | fragp->fr_fix += fragp->fr_var; | |
17849 | ||
17850 | return; | |
17851 | } | |
17852 | ||
df58fc94 RS |
17853 | /* Relax microMIPS branches. */ |
17854 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17855 | { | |
17856 | bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
17857 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17858 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17859 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17860 | bfd_boolean short_ds; |
df58fc94 RS |
17861 | unsigned long insn; |
17862 | expressionS exp; | |
17863 | fixS *fixp; | |
17864 | ||
17865 | exp.X_op = O_symbol; | |
17866 | exp.X_add_symbol = fragp->fr_symbol; | |
17867 | exp.X_add_number = fragp->fr_offset; | |
17868 | ||
17869 | fragp->fr_fix += fragp->fr_var; | |
17870 | ||
17871 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17872 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17873 | { | |
17874 | /* We generate a fixup instead of applying it right now, | |
17875 | because if there is linker relaxation, we're going to | |
17876 | need the relocations. */ | |
17877 | if (type == 'D') | |
17878 | fixp = fix_new_exp (fragp, | |
17879 | buf - (bfd_byte *) fragp->fr_literal, | |
17880 | 2, &exp, TRUE, | |
17881 | BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
17882 | else if (type == 'E') | |
17883 | fixp = fix_new_exp (fragp, | |
17884 | buf - (bfd_byte *) fragp->fr_literal, | |
17885 | 2, &exp, TRUE, | |
17886 | BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
17887 | else | |
17888 | abort (); | |
17889 | ||
17890 | fixp->fx_file = fragp->fr_file; | |
17891 | fixp->fx_line = fragp->fr_line; | |
17892 | ||
17893 | /* These relocations can have an addend that won't fit in | |
17894 | 2 octets. */ | |
17895 | fixp->fx_no_overflow = 1; | |
17896 | ||
17897 | return; | |
17898 | } | |
17899 | ||
2309ddf2 | 17900 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17901 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17902 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17903 | { | |
17904 | /* We generate a fixup instead of applying it right now, | |
17905 | because if there is linker relaxation, we're going to | |
17906 | need the relocations. */ | |
17907 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17908 | 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17909 | fixp->fx_file = fragp->fr_file; | |
17910 | fixp->fx_line = fragp->fr_line; | |
17911 | ||
17912 | if (type == 0) | |
17913 | return; | |
17914 | } | |
17915 | ||
17916 | /* Relax 16-bit branches to 32-bit branches. */ | |
17917 | if (type != 0) | |
17918 | { | |
17919 | if (target_big_endian) | |
17920 | insn = bfd_getb16 (buf); | |
17921 | else | |
17922 | insn = bfd_getl16 (buf); | |
17923 | ||
17924 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17925 | insn = 0x94000000; /* beq */ | |
17926 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17927 | { | |
17928 | unsigned long regno; | |
17929 | ||
17930 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17931 | regno = micromips_to_32_reg_d_map [regno]; | |
17932 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17933 | insn |= regno << MICROMIPSOP_SH_RS; | |
17934 | } | |
17935 | else | |
17936 | abort (); | |
17937 | ||
17938 | /* Nothing else to do, just write it out. */ | |
17939 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
17940 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17941 | { | |
17942 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17943 | buf += 2; | |
17944 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17945 | buf += 2; | |
17946 | ||
17947 | gas_assert (buf == ((bfd_byte *) fragp->fr_literal | |
17948 | + fragp->fr_fix)); | |
17949 | return; | |
17950 | } | |
17951 | } | |
17952 | else | |
17953 | { | |
17954 | unsigned long next; | |
17955 | ||
17956 | if (target_big_endian) | |
17957 | { | |
17958 | insn = bfd_getb16 (buf); | |
17959 | next = bfd_getb16 (buf + 2); | |
17960 | } | |
17961 | else | |
17962 | { | |
17963 | insn = bfd_getl16 (buf); | |
17964 | next = bfd_getl16 (buf + 2); | |
17965 | } | |
17966 | insn = (insn << 16) | next; | |
17967 | } | |
17968 | ||
17969 | /* Relax 32-bit branches to a sequence of instructions. */ | |
17970 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17971 | _("Relaxed out-of-range branch into a jump")); | |
17972 | ||
2309ddf2 MR |
17973 | /* Set the short-delay-slot bit. */ |
17974 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
17975 | |
17976 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
17977 | { | |
17978 | symbolS *l; | |
17979 | ||
17980 | /* Reverse the branch. */ | |
17981 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
17982 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
17983 | insn ^= 0x20000000; | |
17984 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
17985 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
17986 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
17987 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
17988 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
17989 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
17990 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
17991 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
17992 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
17993 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
17994 | insn ^= 0x00400000; | |
17995 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
17996 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
17997 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
17998 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
17999 | insn ^= 0x00200000; | |
18000 | else | |
18001 | abort (); | |
18002 | ||
18003 | if (al) | |
18004 | { | |
18005 | /* Clear the and-link and short-delay-slot bits. */ | |
18006 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18007 | ||
18008 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18009 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18010 | insn &= ~0x02200000; | |
18011 | } | |
18012 | ||
18013 | /* Make a label at the end for use with the branch. */ | |
18014 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18015 | micromips_label_inc (); | |
18016 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18017 | if (IS_ELF) | |
18018 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18019 | #endif | |
18020 | ||
18021 | /* Refer to it. */ | |
18022 | fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18023 | 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
18024 | fixp->fx_file = fragp->fr_file; | |
18025 | fixp->fx_line = fragp->fr_line; | |
18026 | ||
18027 | /* Branch over the jump. */ | |
18028 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18029 | buf += 2; | |
18030 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18031 | buf += 2; | |
18032 | ||
18033 | if (!compact) | |
18034 | { | |
18035 | /* nop */ | |
18036 | insn = 0x0c00; | |
18037 | md_number_to_chars ((char *) buf, insn, 2); | |
18038 | buf += 2; | |
18039 | } | |
18040 | } | |
18041 | ||
18042 | if (mips_pic == NO_PIC) | |
18043 | { | |
2309ddf2 MR |
18044 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18045 | ||
df58fc94 RS |
18046 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18047 | insn = al ? jal : 0xd4000000; | |
18048 | ||
18049 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18050 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP); | |
18051 | fixp->fx_file = fragp->fr_file; | |
18052 | fixp->fx_line = fragp->fr_line; | |
18053 | ||
18054 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18055 | buf += 2; | |
18056 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18057 | buf += 2; | |
18058 | ||
18059 | if (compact) | |
18060 | { | |
18061 | /* nop */ | |
18062 | insn = 0x0c00; | |
18063 | md_number_to_chars ((char *) buf, insn, 2); | |
18064 | buf += 2; | |
18065 | } | |
18066 | } | |
18067 | else | |
18068 | { | |
18069 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18070 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18071 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18072 | |
18073 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18074 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18075 | insn |= at << MICROMIPSOP_SH_RT; | |
18076 | ||
18077 | if (exp.X_add_number) | |
18078 | { | |
18079 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18080 | exp.X_add_number = 0; | |
18081 | } | |
18082 | ||
18083 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18084 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
18085 | fixp->fx_file = fragp->fr_file; | |
18086 | fixp->fx_line = fragp->fr_line; | |
18087 | ||
18088 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18089 | buf += 2; | |
18090 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18091 | buf += 2; | |
18092 | ||
18093 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18094 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18095 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18096 | ||
18097 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18098 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16); | |
18099 | fixp->fx_file = fragp->fr_file; | |
18100 | fixp->fx_line = fragp->fr_line; | |
18101 | ||
18102 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18103 | buf += 2; | |
18104 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18105 | buf += 2; | |
18106 | ||
18107 | /* jr/jrc/jalr/jalrs $at */ | |
18108 | insn = al ? jalr : jr; | |
18109 | insn |= at << MICROMIPSOP_SH_MJ; | |
18110 | ||
18111 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18112 | buf += 2; | |
18113 | } | |
18114 | ||
18115 | gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix); | |
18116 | return; | |
18117 | } | |
18118 | ||
252b5132 RH |
18119 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18120 | { | |
18121 | int type; | |
3994f87e | 18122 | const struct mips16_immed_operand *op; |
b34976b6 | 18123 | bfd_boolean small, ext; |
252b5132 RH |
18124 | offsetT val; |
18125 | bfd_byte *buf; | |
18126 | unsigned long insn; | |
b34976b6 | 18127 | bfd_boolean use_extend; |
252b5132 RH |
18128 | unsigned short extend; |
18129 | ||
18130 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18131 | op = mips16_immed_operands; | |
18132 | while (op->type != type) | |
18133 | ++op; | |
18134 | ||
18135 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18136 | { | |
b34976b6 AM |
18137 | small = FALSE; |
18138 | ext = TRUE; | |
252b5132 RH |
18139 | } |
18140 | else | |
18141 | { | |
b34976b6 AM |
18142 | small = TRUE; |
18143 | ext = FALSE; | |
252b5132 RH |
18144 | } |
18145 | ||
5f5f22c0 | 18146 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18147 | if (op->pcrel) |
18148 | { | |
18149 | addressT addr; | |
18150 | ||
18151 | addr = fragp->fr_address + fragp->fr_fix; | |
18152 | ||
18153 | /* The rules for the base address of a PC relative reloc are | |
18154 | complicated; see mips16_extended_frag. */ | |
18155 | if (type == 'p' || type == 'q') | |
18156 | { | |
18157 | addr += 2; | |
18158 | if (ext) | |
18159 | addr += 2; | |
18160 | /* Ignore the low bit in the target, since it will be | |
18161 | set for a text label. */ | |
18162 | if ((val & 1) != 0) | |
18163 | --val; | |
18164 | } | |
18165 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18166 | addr -= 4; | |
18167 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18168 | addr -= 2; | |
18169 | ||
18170 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18171 | val -= addr; | |
18172 | ||
18173 | /* Make sure the section winds up with the alignment we have | |
18174 | assumed. */ | |
18175 | if (op->shift > 0) | |
18176 | record_alignment (asec, op->shift); | |
18177 | } | |
18178 | ||
18179 | if (ext | |
18180 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18181 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18182 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18183 | _("extended instruction in delay slot")); | |
18184 | ||
18185 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
18186 | ||
18187 | if (target_big_endian) | |
18188 | insn = bfd_getb16 (buf); | |
18189 | else | |
18190 | insn = bfd_getl16 (buf); | |
18191 | ||
18192 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
18193 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
18194 | small, ext, &insn, &use_extend, &extend); | |
18195 | ||
18196 | if (use_extend) | |
18197 | { | |
2132e3a3 | 18198 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
18199 | fragp->fr_fix += 2; |
18200 | buf += 2; | |
18201 | } | |
18202 | ||
2132e3a3 | 18203 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
18204 | fragp->fr_fix += 2; |
18205 | buf += 2; | |
18206 | } | |
18207 | else | |
18208 | { | |
df58fc94 RS |
18209 | relax_substateT subtype = fragp->fr_subtype; |
18210 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18211 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18212 | int first, second; |
18213 | fixS *fixp; | |
252b5132 | 18214 | |
df58fc94 RS |
18215 | first = RELAX_FIRST (subtype); |
18216 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18217 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18218 | |
df58fc94 RS |
18219 | /* If the delay slot chosen does not match the size of the instruction, |
18220 | then emit a warning. */ | |
18221 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18222 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18223 | { | |
18224 | relax_substateT s; | |
18225 | const char *msg; | |
18226 | ||
18227 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18228 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18229 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18230 | msg = macro_warning (s); | |
18231 | if (msg != NULL) | |
18232 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18233 | subtype &= ~s; | |
18234 | } | |
18235 | ||
584892a6 | 18236 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18237 | if (use_second == second_longer) |
584892a6 | 18238 | { |
df58fc94 RS |
18239 | relax_substateT s; |
18240 | const char *msg; | |
18241 | ||
18242 | s = (subtype | |
18243 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18244 | msg = macro_warning (s); | |
18245 | if (msg != NULL) | |
18246 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18247 | subtype &= ~s; | |
584892a6 RS |
18248 | } |
18249 | ||
4d7206a2 RS |
18250 | /* Go through all the fixups for the first sequence. Disable them |
18251 | (by marking them as done) if we're going to use the second | |
18252 | sequence instead. */ | |
18253 | while (fixp | |
18254 | && fixp->fx_frag == fragp | |
18255 | && fixp->fx_where < fragp->fr_fix - second) | |
18256 | { | |
df58fc94 | 18257 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18258 | fixp->fx_done = 1; |
18259 | fixp = fixp->fx_next; | |
18260 | } | |
252b5132 | 18261 | |
4d7206a2 RS |
18262 | /* Go through the fixups for the second sequence. Disable them if |
18263 | we're going to use the first sequence, otherwise adjust their | |
18264 | addresses to account for the relaxation. */ | |
18265 | while (fixp && fixp->fx_frag == fragp) | |
18266 | { | |
df58fc94 | 18267 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18268 | fixp->fx_where -= first; |
18269 | else | |
18270 | fixp->fx_done = 1; | |
18271 | fixp = fixp->fx_next; | |
18272 | } | |
18273 | ||
18274 | /* Now modify the frag contents. */ | |
df58fc94 | 18275 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18276 | { |
18277 | char *start; | |
18278 | ||
18279 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18280 | memmove (start, start + first, second); | |
18281 | fragp->fr_fix -= first; | |
18282 | } | |
18283 | else | |
18284 | fragp->fr_fix -= second; | |
252b5132 RH |
18285 | } |
18286 | } | |
18287 | ||
18288 | #ifdef OBJ_ELF | |
18289 | ||
18290 | /* This function is called after the relocs have been generated. | |
18291 | We've been storing mips16 text labels as odd. Here we convert them | |
18292 | back to even for the convenience of the debugger. */ | |
18293 | ||
18294 | void | |
17a2f251 | 18295 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18296 | { |
18297 | asymbol **syms; | |
18298 | unsigned int count, i; | |
18299 | ||
f43abd2b | 18300 | if (!IS_ELF) |
252b5132 RH |
18301 | return; |
18302 | ||
18303 | syms = bfd_get_outsymbols (stdoutput); | |
18304 | count = bfd_get_symcount (stdoutput); | |
18305 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18306 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18307 | && ((*syms)->value & 1) != 0) | |
18308 | { | |
18309 | (*syms)->value &= ~1; | |
18310 | /* If the symbol has an odd size, it was probably computed | |
18311 | incorrectly, so adjust that as well. */ | |
18312 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18313 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18314 | } | |
252b5132 RH |
18315 | } |
18316 | ||
18317 | #endif | |
18318 | ||
a1facbec MR |
18319 | /* This function is called whenever a label is defined, including fake |
18320 | labels instantiated off the dot special symbol. It is used when | |
18321 | handling branch delays; if a branch has a label, we assume we cannot | |
18322 | move it. This also bumps the value of the symbol by 1 in compressed | |
18323 | code. */ | |
252b5132 RH |
18324 | |
18325 | void | |
a1facbec | 18326 | mips_record_label (symbolS *sym) |
252b5132 | 18327 | { |
a8dbcb85 | 18328 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18329 | struct insn_label_list *l; |
18330 | ||
18331 | if (free_insn_labels == NULL) | |
18332 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18333 | else | |
18334 | { | |
18335 | l = free_insn_labels; | |
18336 | free_insn_labels = l->next; | |
18337 | } | |
18338 | ||
18339 | l->label = sym; | |
a8dbcb85 TS |
18340 | l->next = si->label_list; |
18341 | si->label_list = l; | |
a1facbec | 18342 | } |
07a53e5c | 18343 | |
a1facbec MR |
18344 | /* This function is called as tc_frob_label() whenever a label is defined |
18345 | and adds a DWARF-2 record we only want for true labels. */ | |
18346 | ||
18347 | void | |
18348 | mips_define_label (symbolS *sym) | |
18349 | { | |
18350 | mips_record_label (sym); | |
07a53e5c RH |
18351 | #ifdef OBJ_ELF |
18352 | dwarf2_emit_label (sym); | |
18353 | #endif | |
252b5132 RH |
18354 | } |
18355 | \f | |
18356 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18357 | ||
18358 | /* Some special processing for a MIPS ELF file. */ | |
18359 | ||
18360 | void | |
17a2f251 | 18361 | mips_elf_final_processing (void) |
252b5132 RH |
18362 | { |
18363 | /* Write out the register information. */ | |
316f5878 | 18364 | if (mips_abi != N64_ABI) |
252b5132 RH |
18365 | { |
18366 | Elf32_RegInfo s; | |
18367 | ||
18368 | s.ri_gprmask = mips_gprmask; | |
18369 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18370 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18371 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18372 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18373 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18374 | ||
18375 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18376 | ((Elf32_External_RegInfo *) | |
18377 | mips_regmask_frag)); | |
18378 | } | |
18379 | else | |
18380 | { | |
18381 | Elf64_Internal_RegInfo s; | |
18382 | ||
18383 | s.ri_gprmask = mips_gprmask; | |
18384 | s.ri_pad = 0; | |
18385 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18386 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18387 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18388 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18389 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18390 | ||
18391 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18392 | ((Elf64_External_RegInfo *) | |
18393 | mips_regmask_frag)); | |
18394 | } | |
18395 | ||
18396 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18397 | sort of BFD interface for this. */ | |
18398 | if (mips_any_noreorder) | |
18399 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18400 | if (mips_pic != NO_PIC) | |
143d77c5 | 18401 | { |
252b5132 | 18402 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18403 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18404 | } | |
18405 | if (mips_abicalls) | |
18406 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18407 | |
98d3f06f | 18408 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18409 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18410 | file_ase_dsp is true. */ | |
8b082fb1 | 18411 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18412 | /* We may need to define a new flag for MT ASE, and set this flag when |
18413 | file_ase_mt is true. */ | |
a4672219 TS |
18414 | if (file_ase_mips16) |
18415 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18416 | if (file_ase_micromips) |
18417 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18418 | #if 0 /* XXX FIXME */ |
18419 | if (file_ase_mips3d) | |
18420 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18421 | #endif | |
deec1734 CD |
18422 | if (file_ase_mdmx) |
18423 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18424 | |
bdaaa2e1 | 18425 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18426 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18427 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18428 | else if (mips_abi == O64_ABI) |
252b5132 | 18429 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18430 | else if (mips_abi == EABI_ABI) |
252b5132 | 18431 | { |
316f5878 | 18432 | if (!file_mips_gp32) |
252b5132 RH |
18433 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18434 | else | |
18435 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18436 | } | |
316f5878 | 18437 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18438 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18439 | ||
c9914766 | 18440 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18441 | |
18442 | if (mips_32bitmode) | |
18443 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18444 | |
18445 | #if 0 /* XXX FIXME */ | |
18446 | /* 32 bit code with 64 bit FP registers. */ | |
18447 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18448 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18449 | #endif | |
252b5132 RH |
18450 | } |
18451 | ||
18452 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18453 | \f | |
beae10d5 | 18454 | typedef struct proc { |
9b2f1d35 EC |
18455 | symbolS *func_sym; |
18456 | symbolS *func_end_sym; | |
beae10d5 KH |
18457 | unsigned long reg_mask; |
18458 | unsigned long reg_offset; | |
18459 | unsigned long fpreg_mask; | |
18460 | unsigned long fpreg_offset; | |
18461 | unsigned long frame_offset; | |
18462 | unsigned long frame_reg; | |
18463 | unsigned long pc_reg; | |
18464 | } procS; | |
252b5132 RH |
18465 | |
18466 | static procS cur_proc; | |
18467 | static procS *cur_proc_ptr; | |
18468 | static int numprocs; | |
18469 | ||
df58fc94 RS |
18470 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18471 | as "2", and a normal nop as "0". */ | |
18472 | ||
18473 | #define NOP_OPCODE_MIPS 0 | |
18474 | #define NOP_OPCODE_MIPS16 1 | |
18475 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18476 | |
18477 | char | |
18478 | mips_nop_opcode (void) | |
18479 | { | |
df58fc94 RS |
18480 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18481 | return NOP_OPCODE_MICROMIPS; | |
18482 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18483 | return NOP_OPCODE_MIPS16; | |
18484 | else | |
18485 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18486 | } |
18487 | ||
df58fc94 RS |
18488 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18489 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18490 | |
0a9ef439 | 18491 | void |
17a2f251 | 18492 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18493 | { |
df58fc94 | 18494 | char nop_opcode; |
742a56fe | 18495 | char *p; |
c67a084a NC |
18496 | int bytes, size, excess; |
18497 | valueT opcode; | |
742a56fe | 18498 | |
0a9ef439 RH |
18499 | if (fragp->fr_type != rs_align_code) |
18500 | return; | |
18501 | ||
742a56fe | 18502 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18503 | nop_opcode = *p; |
18504 | switch (nop_opcode) | |
a19d8eb0 | 18505 | { |
df58fc94 RS |
18506 | case NOP_OPCODE_MICROMIPS: |
18507 | opcode = micromips_nop32_insn.insn_opcode; | |
18508 | size = 4; | |
18509 | break; | |
18510 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18511 | opcode = mips16_nop_insn.insn_opcode; |
18512 | size = 2; | |
df58fc94 RS |
18513 | break; |
18514 | case NOP_OPCODE_MIPS: | |
18515 | default: | |
c67a084a NC |
18516 | opcode = nop_insn.insn_opcode; |
18517 | size = 4; | |
df58fc94 | 18518 | break; |
c67a084a | 18519 | } |
a19d8eb0 | 18520 | |
c67a084a NC |
18521 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18522 | excess = bytes % size; | |
df58fc94 RS |
18523 | |
18524 | /* Handle the leading part if we're not inserting a whole number of | |
18525 | instructions, and make it the end of the fixed part of the frag. | |
18526 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18527 | and use zeroes otherwise. */ | |
18528 | gas_assert (excess < 4); | |
18529 | fragp->fr_fix += excess; | |
18530 | switch (excess) | |
c67a084a | 18531 | { |
df58fc94 RS |
18532 | case 3: |
18533 | *p++ = '\0'; | |
18534 | /* Fall through. */ | |
18535 | case 2: | |
18536 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18537 | { | |
18538 | md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2); | |
18539 | p += 2; | |
18540 | break; | |
18541 | } | |
18542 | *p++ = '\0'; | |
18543 | /* Fall through. */ | |
18544 | case 1: | |
18545 | *p++ = '\0'; | |
18546 | /* Fall through. */ | |
18547 | case 0: | |
18548 | break; | |
a19d8eb0 | 18549 | } |
c67a084a NC |
18550 | |
18551 | md_number_to_chars (p, opcode, size); | |
18552 | fragp->fr_var = size; | |
a19d8eb0 CP |
18553 | } |
18554 | ||
252b5132 | 18555 | static void |
17a2f251 | 18556 | md_obj_begin (void) |
252b5132 RH |
18557 | { |
18558 | } | |
18559 | ||
18560 | static void | |
17a2f251 | 18561 | md_obj_end (void) |
252b5132 | 18562 | { |
54f4ddb3 | 18563 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18564 | if (cur_proc_ptr) |
9a41af64 | 18565 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18566 | } |
18567 | ||
18568 | static long | |
17a2f251 | 18569 | get_number (void) |
252b5132 RH |
18570 | { |
18571 | int negative = 0; | |
18572 | long val = 0; | |
18573 | ||
18574 | if (*input_line_pointer == '-') | |
18575 | { | |
18576 | ++input_line_pointer; | |
18577 | negative = 1; | |
18578 | } | |
3882b010 | 18579 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18580 | as_bad (_("expected simple number")); |
252b5132 RH |
18581 | if (input_line_pointer[0] == '0') |
18582 | { | |
18583 | if (input_line_pointer[1] == 'x') | |
18584 | { | |
18585 | input_line_pointer += 2; | |
3882b010 | 18586 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18587 | { |
18588 | val <<= 4; | |
18589 | val |= hex_value (*input_line_pointer++); | |
18590 | } | |
18591 | return negative ? -val : val; | |
18592 | } | |
18593 | else | |
18594 | { | |
18595 | ++input_line_pointer; | |
3882b010 | 18596 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18597 | { |
18598 | val <<= 3; | |
18599 | val |= *input_line_pointer++ - '0'; | |
18600 | } | |
18601 | return negative ? -val : val; | |
18602 | } | |
18603 | } | |
3882b010 | 18604 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18605 | { |
18606 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18607 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18608 | as_warn (_("invalid number")); |
252b5132 RH |
18609 | return -1; |
18610 | } | |
3882b010 | 18611 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18612 | { |
18613 | val *= 10; | |
18614 | val += *input_line_pointer++ - '0'; | |
18615 | } | |
18616 | return negative ? -val : val; | |
18617 | } | |
18618 | ||
18619 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18620 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18621 | case .file implies DWARF-2. */ | |
18622 | ||
18623 | static void | |
17a2f251 | 18624 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18625 | { |
ecb4347a DJ |
18626 | static int first_file_directive = 0; |
18627 | ||
c5dd6aab DJ |
18628 | if (ECOFF_DEBUGGING) |
18629 | { | |
18630 | get_number (); | |
18631 | s_app_file (0); | |
18632 | } | |
18633 | else | |
ecb4347a DJ |
18634 | { |
18635 | char *filename; | |
18636 | ||
18637 | filename = dwarf2_directive_file (0); | |
18638 | ||
18639 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18640 | directive even for stabs output. Make sure that this | |
18641 | ".file" is handled. Note that you need a version of GCC | |
18642 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18643 | if (filename != NULL && ! first_file_directive) | |
18644 | { | |
18645 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18646 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18647 | } |
18648 | first_file_directive = 1; | |
18649 | } | |
c5dd6aab DJ |
18650 | } |
18651 | ||
18652 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18653 | |
18654 | static void | |
17a2f251 | 18655 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18656 | { |
c5dd6aab DJ |
18657 | if (!ECOFF_DEBUGGING) |
18658 | dwarf2_directive_loc (0); | |
252b5132 RH |
18659 | } |
18660 | ||
252b5132 RH |
18661 | /* The .end directive. */ |
18662 | ||
18663 | static void | |
17a2f251 | 18664 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18665 | { |
18666 | symbolS *p; | |
252b5132 | 18667 | |
7a621144 DJ |
18668 | /* Following functions need their own .frame and .cprestore directives. */ |
18669 | mips_frame_reg_valid = 0; | |
18670 | mips_cprestore_valid = 0; | |
18671 | ||
252b5132 RH |
18672 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18673 | { | |
18674 | p = get_symbol (); | |
18675 | demand_empty_rest_of_line (); | |
18676 | } | |
18677 | else | |
18678 | p = NULL; | |
18679 | ||
14949570 | 18680 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18681 | as_warn (_(".end not in text section")); |
18682 | ||
18683 | if (!cur_proc_ptr) | |
18684 | { | |
18685 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18686 | demand_empty_rest_of_line (); | |
18687 | return; | |
18688 | } | |
18689 | ||
18690 | if (p != NULL) | |
18691 | { | |
9c2799c2 | 18692 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18693 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18694 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18695 | |
18696 | if (debug_type == DEBUG_STABS) | |
18697 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18698 | S_GET_NAME (p)); | |
252b5132 RH |
18699 | } |
18700 | else | |
18701 | as_warn (_(".end directive missing or unknown symbol")); | |
18702 | ||
2132e3a3 | 18703 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18704 | /* Create an expression to calculate the size of the function. */ |
18705 | if (p && cur_proc_ptr) | |
18706 | { | |
18707 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18708 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18709 | ||
18710 | obj->size = exp; | |
18711 | exp->X_op = O_subtract; | |
18712 | exp->X_add_symbol = symbol_temp_new_now (); | |
18713 | exp->X_op_symbol = p; | |
18714 | exp->X_add_number = 0; | |
18715 | ||
18716 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18717 | } | |
18718 | ||
ecb4347a | 18719 | /* Generate a .pdr section. */ |
f43abd2b | 18720 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18721 | { |
18722 | segT saved_seg = now_seg; | |
18723 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18724 | expressionS exp; |
18725 | char *fragp; | |
252b5132 | 18726 | |
252b5132 | 18727 | #ifdef md_flush_pending_output |
ecb4347a | 18728 | md_flush_pending_output (); |
252b5132 RH |
18729 | #endif |
18730 | ||
9c2799c2 | 18731 | gas_assert (pdr_seg); |
ecb4347a | 18732 | subseg_set (pdr_seg, 0); |
252b5132 | 18733 | |
ecb4347a DJ |
18734 | /* Write the symbol. */ |
18735 | exp.X_op = O_symbol; | |
18736 | exp.X_add_symbol = p; | |
18737 | exp.X_add_number = 0; | |
18738 | emit_expr (&exp, 4); | |
252b5132 | 18739 | |
ecb4347a | 18740 | fragp = frag_more (7 * 4); |
252b5132 | 18741 | |
17a2f251 TS |
18742 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18743 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18744 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18745 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18746 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18747 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18748 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18749 | |
ecb4347a DJ |
18750 | subseg_set (saved_seg, saved_subseg); |
18751 | } | |
18752 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18753 | |
18754 | cur_proc_ptr = NULL; | |
18755 | } | |
18756 | ||
18757 | /* The .aent and .ent directives. */ | |
18758 | ||
18759 | static void | |
17a2f251 | 18760 | s_mips_ent (int aent) |
252b5132 | 18761 | { |
252b5132 | 18762 | symbolS *symbolP; |
252b5132 RH |
18763 | |
18764 | symbolP = get_symbol (); | |
18765 | if (*input_line_pointer == ',') | |
f9419b05 | 18766 | ++input_line_pointer; |
252b5132 | 18767 | SKIP_WHITESPACE (); |
3882b010 | 18768 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18769 | || *input_line_pointer == '-') |
874e8986 | 18770 | get_number (); |
252b5132 | 18771 | |
14949570 | 18772 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18773 | as_warn (_(".ent or .aent not in text section.")); |
18774 | ||
18775 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18776 | as_warn (_("missing .end")); |
252b5132 RH |
18777 | |
18778 | if (!aent) | |
18779 | { | |
7a621144 DJ |
18780 | /* This function needs its own .frame and .cprestore directives. */ |
18781 | mips_frame_reg_valid = 0; | |
18782 | mips_cprestore_valid = 0; | |
18783 | ||
252b5132 RH |
18784 | cur_proc_ptr = &cur_proc; |
18785 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18786 | ||
9b2f1d35 | 18787 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18788 | |
f9419b05 | 18789 | ++numprocs; |
ecb4347a DJ |
18790 | |
18791 | if (debug_type == DEBUG_STABS) | |
18792 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18793 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18794 | } |
18795 | ||
7c0fc524 MR |
18796 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18797 | ||
252b5132 RH |
18798 | demand_empty_rest_of_line (); |
18799 | } | |
18800 | ||
18801 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18802 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18803 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18804 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18805 | symbol table (in the mdebug section). */ |
18806 | ||
18807 | static void | |
17a2f251 | 18808 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18809 | { |
ecb4347a | 18810 | #ifdef OBJ_ELF |
f43abd2b | 18811 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18812 | { |
18813 | long val; | |
252b5132 | 18814 | |
ecb4347a DJ |
18815 | if (cur_proc_ptr == (procS *) NULL) |
18816 | { | |
18817 | as_warn (_(".frame outside of .ent")); | |
18818 | demand_empty_rest_of_line (); | |
18819 | return; | |
18820 | } | |
252b5132 | 18821 | |
ecb4347a DJ |
18822 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18823 | ||
18824 | SKIP_WHITESPACE (); | |
18825 | if (*input_line_pointer++ != ',' | |
18826 | || get_absolute_expression_and_terminator (&val) != ',') | |
18827 | { | |
18828 | as_warn (_("Bad .frame directive")); | |
18829 | --input_line_pointer; | |
18830 | demand_empty_rest_of_line (); | |
18831 | return; | |
18832 | } | |
252b5132 | 18833 | |
ecb4347a DJ |
18834 | cur_proc_ptr->frame_offset = val; |
18835 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18836 | |
252b5132 | 18837 | demand_empty_rest_of_line (); |
252b5132 | 18838 | } |
ecb4347a DJ |
18839 | else |
18840 | #endif /* OBJ_ELF */ | |
18841 | s_ignore (ignore); | |
252b5132 RH |
18842 | } |
18843 | ||
bdaaa2e1 KH |
18844 | /* The .fmask and .mask directives. If the mdebug section is present |
18845 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18846 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18847 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18848 | make reference to the ecoff symbol table (in the mdebug section). */ |
18849 | ||
18850 | static void | |
17a2f251 | 18851 | s_mips_mask (int reg_type) |
252b5132 | 18852 | { |
ecb4347a | 18853 | #ifdef OBJ_ELF |
f43abd2b | 18854 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18855 | { |
ecb4347a | 18856 | long mask, off; |
252b5132 | 18857 | |
ecb4347a DJ |
18858 | if (cur_proc_ptr == (procS *) NULL) |
18859 | { | |
18860 | as_warn (_(".mask/.fmask outside of .ent")); | |
18861 | demand_empty_rest_of_line (); | |
18862 | return; | |
18863 | } | |
252b5132 | 18864 | |
ecb4347a DJ |
18865 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18866 | { | |
18867 | as_warn (_("Bad .mask/.fmask directive")); | |
18868 | --input_line_pointer; | |
18869 | demand_empty_rest_of_line (); | |
18870 | return; | |
18871 | } | |
252b5132 | 18872 | |
ecb4347a DJ |
18873 | off = get_absolute_expression (); |
18874 | ||
18875 | if (reg_type == 'F') | |
18876 | { | |
18877 | cur_proc_ptr->fpreg_mask = mask; | |
18878 | cur_proc_ptr->fpreg_offset = off; | |
18879 | } | |
18880 | else | |
18881 | { | |
18882 | cur_proc_ptr->reg_mask = mask; | |
18883 | cur_proc_ptr->reg_offset = off; | |
18884 | } | |
18885 | ||
18886 | demand_empty_rest_of_line (); | |
252b5132 RH |
18887 | } |
18888 | else | |
ecb4347a DJ |
18889 | #endif /* OBJ_ELF */ |
18890 | s_ignore (reg_type); | |
252b5132 RH |
18891 | } |
18892 | ||
316f5878 RS |
18893 | /* A table describing all the processors gas knows about. Names are |
18894 | matched in the order listed. | |
e7af610e | 18895 | |
316f5878 RS |
18896 | To ease comparison, please keep this table in the same order as |
18897 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18898 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18899 | { | |
316f5878 | 18900 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18901 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18902 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18903 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18904 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18905 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18906 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18907 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18908 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18909 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18910 | |
18911 | /* MIPS I */ | |
ad3fea08 TS |
18912 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18913 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18914 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18915 | |
18916 | /* MIPS II */ | |
ad3fea08 | 18917 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18918 | |
18919 | /* MIPS III */ | |
ad3fea08 TS |
18920 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
18921 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
18922 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
18923 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
18924 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
18925 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
18926 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
18927 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
18928 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
18929 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
18930 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
18931 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
18932 | /* ST Microelectronics Loongson 2E and 2F cores */ |
18933 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
18934 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18935 | |
18936 | /* MIPS IV */ | |
ad3fea08 TS |
18937 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
18938 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
18939 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
18940 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
18941 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
18942 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
18943 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
18944 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
18945 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
18946 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
18947 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
18948 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
18949 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
18950 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
18951 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
18952 | |
18953 | /* MIPS 32 */ | |
ad3fea08 TS |
18954 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
18955 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18956 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18957 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
18958 | ||
18959 | /* MIPS 32 Release 2 */ | |
18960 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18961 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18962 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18963 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18964 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18965 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18966 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18967 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18968 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18969 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18970 | /* Deprecated forms of the above. */ | |
18971 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18972 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18973 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 18974 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18975 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18976 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18977 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18978 | /* Deprecated forms of the above. */ | |
18979 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 18980 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18981 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
18982 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18983 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18984 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18985 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18986 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18987 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18988 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18989 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18990 | /* Deprecated forms of the above. */ | |
18991 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18992 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18993 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18994 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18995 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
18996 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18997 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18998 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18999 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19000 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19001 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19002 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19003 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19004 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19005 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19006 | /* Deprecated forms of the above. */ | |
19007 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19008 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19009 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19010 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19011 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19012 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19013 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19014 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19015 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19016 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19017 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19018 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19019 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19020 | |
316f5878 | 19021 | /* MIPS 64 */ |
ad3fea08 TS |
19022 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19023 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19024 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19025 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19026 | |
c7a23324 | 19027 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19028 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19029 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19030 | /* Broadcom SB-1A CPU core */ |
19031 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19032 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19033 | |
19034 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19035 | |
ed163775 MR |
19036 | /* MIPS 64 Release 2 */ |
19037 | ||
967344c6 AN |
19038 | /* Cavium Networks Octeon CPU core */ |
19039 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
19040 | ||
52b6b6b9 JM |
19041 | /* RMI Xlr */ |
19042 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19043 | ||
316f5878 RS |
19044 | /* End marker */ |
19045 | { NULL, 0, 0, 0 } | |
19046 | }; | |
e7af610e | 19047 | |
84ea6cf2 | 19048 | |
316f5878 RS |
19049 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19050 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19051 | |
316f5878 | 19052 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19053 | |
b34976b6 | 19054 | static bfd_boolean |
17a2f251 | 19055 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19056 | { |
19057 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19058 | given++, canonical++; | |
19059 | ||
19060 | return ((*given == 0 && *canonical == 0) | |
19061 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19062 | } | |
19063 | ||
19064 | ||
19065 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19066 | CPU name. We've traditionally allowed a lot of variation here. | |
19067 | ||
19068 | Note: this function is shared between GCC and GAS. */ | |
19069 | ||
b34976b6 | 19070 | static bfd_boolean |
17a2f251 | 19071 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19072 | { |
19073 | /* First see if the name matches exactly, or with a final "000" | |
19074 | turned into "k". */ | |
19075 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19076 | return TRUE; |
316f5878 RS |
19077 | |
19078 | /* If not, try comparing based on numerical designation alone. | |
19079 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19080 | if (TOLOWER (*given) == 'r') | |
19081 | given++; | |
19082 | if (!ISDIGIT (*given)) | |
b34976b6 | 19083 | return FALSE; |
316f5878 RS |
19084 | |
19085 | /* Skip over some well-known prefixes in the canonical name, | |
19086 | hoping to find a number there too. */ | |
19087 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19088 | canonical += 2; | |
19089 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19090 | canonical += 2; | |
19091 | else if (TOLOWER (canonical[0]) == 'r') | |
19092 | canonical += 1; | |
19093 | ||
19094 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19095 | } | |
19096 | ||
19097 | ||
19098 | /* Parse an option that takes the name of a processor as its argument. | |
19099 | OPTION is the name of the option and CPU_STRING is the argument. | |
19100 | Return the corresponding processor enumeration if the CPU_STRING is | |
19101 | recognized, otherwise report an error and return null. | |
19102 | ||
19103 | A similar function exists in GCC. */ | |
e7af610e NC |
19104 | |
19105 | static const struct mips_cpu_info * | |
17a2f251 | 19106 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19107 | { |
316f5878 | 19108 | const struct mips_cpu_info *p; |
e7af610e | 19109 | |
316f5878 RS |
19110 | /* 'from-abi' selects the most compatible architecture for the given |
19111 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19112 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19113 | version. Look first at the -mgp options, if given, otherwise base | |
19114 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19115 | |
316f5878 RS |
19116 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19117 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19118 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19119 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19120 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19121 | { | |
19122 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19123 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19124 | ||
19125 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19126 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19127 | ||
19128 | if (file_mips_gp32 >= 0) | |
19129 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19130 | ||
19131 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19132 | ? ISA_MIPS3 | |
19133 | : ISA_MIPS1); | |
19134 | } | |
19135 | ||
19136 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19137 | if (strcasecmp (cpu_string, "default") == 0) | |
19138 | return 0; | |
19139 | ||
19140 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19141 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19142 | return p; | |
19143 | ||
20203fb9 | 19144 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19145 | return 0; |
e7af610e NC |
19146 | } |
19147 | ||
316f5878 RS |
19148 | /* Return the canonical processor information for ISA (a member of the |
19149 | ISA_MIPS* enumeration). */ | |
19150 | ||
e7af610e | 19151 | static const struct mips_cpu_info * |
17a2f251 | 19152 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19153 | { |
19154 | int i; | |
19155 | ||
19156 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19157 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19158 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19159 | return (&mips_cpu_info_table[i]); |
19160 | ||
e972090a | 19161 | return NULL; |
e7af610e | 19162 | } |
fef14a42 TS |
19163 | |
19164 | static const struct mips_cpu_info * | |
17a2f251 | 19165 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19166 | { |
19167 | int i; | |
19168 | ||
19169 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19170 | if (arch == mips_cpu_info_table[i].cpu) | |
19171 | return (&mips_cpu_info_table[i]); | |
19172 | ||
19173 | return NULL; | |
19174 | } | |
316f5878 RS |
19175 | \f |
19176 | static void | |
17a2f251 | 19177 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19178 | { |
19179 | if (*first_p) | |
19180 | { | |
19181 | fprintf (stream, "%24s", ""); | |
19182 | *col_p = 24; | |
19183 | } | |
19184 | else | |
19185 | { | |
19186 | fprintf (stream, ", "); | |
19187 | *col_p += 2; | |
19188 | } | |
e7af610e | 19189 | |
316f5878 RS |
19190 | if (*col_p + strlen (string) > 72) |
19191 | { | |
19192 | fprintf (stream, "\n%24s", ""); | |
19193 | *col_p = 24; | |
19194 | } | |
19195 | ||
19196 | fprintf (stream, "%s", string); | |
19197 | *col_p += strlen (string); | |
19198 | ||
19199 | *first_p = 0; | |
19200 | } | |
19201 | ||
19202 | void | |
17a2f251 | 19203 | md_show_usage (FILE *stream) |
e7af610e | 19204 | { |
316f5878 RS |
19205 | int column, first; |
19206 | size_t i; | |
19207 | ||
19208 | fprintf (stream, _("\ | |
19209 | MIPS options:\n\ | |
316f5878 RS |
19210 | -EB generate big endian output\n\ |
19211 | -EL generate little endian output\n\ | |
19212 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19213 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19214 | implicitly with the gp register [default 8]\n")); | |
19215 | fprintf (stream, _("\ | |
19216 | -mips1 generate MIPS ISA I instructions\n\ | |
19217 | -mips2 generate MIPS ISA II instructions\n\ | |
19218 | -mips3 generate MIPS ISA III instructions\n\ | |
19219 | -mips4 generate MIPS ISA IV instructions\n\ | |
19220 | -mips5 generate MIPS ISA V instructions\n\ | |
19221 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19222 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19223 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19224 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19225 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19226 | ||
19227 | first = 1; | |
e7af610e NC |
19228 | |
19229 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19230 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19231 | show (stream, "from-abi", &column, &first); | |
19232 | fputc ('\n', stream); | |
e7af610e | 19233 | |
316f5878 RS |
19234 | fprintf (stream, _("\ |
19235 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19236 | -no-mCPU don't generate code specific to CPU.\n\ | |
19237 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19238 | ||
19239 | first = 1; | |
19240 | ||
19241 | show (stream, "3900", &column, &first); | |
19242 | show (stream, "4010", &column, &first); | |
19243 | show (stream, "4100", &column, &first); | |
19244 | show (stream, "4650", &column, &first); | |
19245 | fputc ('\n', stream); | |
19246 | ||
19247 | fprintf (stream, _("\ | |
19248 | -mips16 generate mips16 instructions\n\ | |
19249 | -no-mips16 do not generate mips16 instructions\n")); | |
19250 | fprintf (stream, _("\ | |
df58fc94 RS |
19251 | -mmicromips generate microMIPS instructions\n\ |
19252 | -mno-micromips do not generate microMIPS instructions\n")); | |
19253 | fprintf (stream, _("\ | |
e16bfa71 TS |
19254 | -msmartmips generate smartmips instructions\n\ |
19255 | -mno-smartmips do not generate smartmips instructions\n")); | |
19256 | fprintf (stream, _("\ | |
74cd071d CF |
19257 | -mdsp generate DSP instructions\n\ |
19258 | -mno-dsp do not generate DSP instructions\n")); | |
19259 | fprintf (stream, _("\ | |
8b082fb1 TS |
19260 | -mdspr2 generate DSP R2 instructions\n\ |
19261 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19262 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19263 | -mmt generate MT instructions\n\ |
19264 | -mno-mt do not generate MT instructions\n")); | |
19265 | fprintf (stream, _("\ | |
dec0624d MR |
19266 | -mmcu generate MCU instructions\n\ |
19267 | -mno-mcu do not generate MCU instructions\n")); | |
19268 | fprintf (stream, _("\ | |
c67a084a NC |
19269 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19270 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19271 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19272 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19273 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19274 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19275 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19276 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19277 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19278 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19279 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19280 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19281 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19282 | fprintf (stream, _("\ |
19283 | -mhard-float allow floating-point instructions\n\ | |
19284 | -msoft-float do not allow floating-point instructions\n\ | |
19285 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19286 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19287 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19288 | )); | |
316f5878 RS |
19289 | #ifdef OBJ_ELF |
19290 | fprintf (stream, _("\ | |
19291 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19292 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19293 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19294 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19295 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19296 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19297 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19298 | position dependent (non shared) code\n\ |
316f5878 RS |
19299 | -mabi=ABI create ABI conformant object file for:\n")); |
19300 | ||
19301 | first = 1; | |
19302 | ||
19303 | show (stream, "32", &column, &first); | |
19304 | show (stream, "o64", &column, &first); | |
19305 | show (stream, "n32", &column, &first); | |
19306 | show (stream, "64", &column, &first); | |
19307 | show (stream, "eabi", &column, &first); | |
19308 | ||
19309 | fputc ('\n', stream); | |
19310 | ||
19311 | fprintf (stream, _("\ | |
19312 | -32 create o32 ABI object file (default)\n\ | |
19313 | -n32 create n32 ABI object file\n\ | |
19314 | -64 create 64 ABI object file\n")); | |
19315 | #endif | |
e7af610e | 19316 | } |
14e777e0 | 19317 | |
1575952e | 19318 | #ifdef TE_IRIX |
14e777e0 | 19319 | enum dwarf2_format |
413a266c | 19320 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19321 | { |
369943fe | 19322 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19323 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19324 | else |
19325 | return dwarf2_format_32bit; | |
19326 | } | |
1575952e | 19327 | #endif |
73369e65 EC |
19328 | |
19329 | int | |
19330 | mips_dwarf2_addr_size (void) | |
19331 | { | |
6b6b3450 | 19332 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19333 | return 8; |
73369e65 EC |
19334 | else |
19335 | return 4; | |
19336 | } | |
5862107c EC |
19337 | |
19338 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19339 | void | |
19340 | mips_cfi_frame_initial_instructions (void) | |
19341 | { | |
19342 | cfi_add_CFA_def_cfa_register (SP); | |
19343 | } | |
19344 | ||
707bfff6 TS |
19345 | int |
19346 | tc_mips_regname_to_dw2regnum (char *regname) | |
19347 | { | |
19348 | unsigned int regnum = -1; | |
19349 | unsigned int reg; | |
19350 | ||
19351 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19352 | regnum = reg; | |
19353 | ||
19354 | return regnum; | |
19355 | } |