Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
98d3f06f | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
252b5132 RH |
105 | /* The name of the readonly data section. */ |
106 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
107 | ? ".data" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
109 | ? ".rdata" \ | |
056350c6 NC |
110 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
111 | ? ".rdata" \ | |
252b5132 RH |
112 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
113 | ? ".rodata" \ | |
114 | : (abort (), "")) | |
115 | ||
a325df1d TS |
116 | /* The ABI to use. */ |
117 | enum mips_abi_level | |
118 | { | |
119 | NO_ABI = 0, | |
120 | O32_ABI, | |
121 | O64_ABI, | |
122 | N32_ABI, | |
123 | N64_ABI, | |
124 | EABI_ABI | |
125 | }; | |
126 | ||
127 | /* MIPS ABI we are using for this output file. */ | |
128 | static enum mips_abi_level file_mips_abi = NO_ABI; | |
129 | ||
252b5132 RH |
130 | /* This is the set of options which may be modified by the .set |
131 | pseudo-op. We use a struct so that .set push and .set pop are more | |
132 | reliable. */ | |
133 | ||
e972090a NC |
134 | struct mips_set_options |
135 | { | |
252b5132 RH |
136 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
137 | if it has not been initialized. Changed by `.set mipsN', and the | |
138 | -mipsN command line option, and the default CPU. */ | |
139 | int isa; | |
1f25f5d3 CD |
140 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
141 | if they have not been initialized. Changed by `.set <asename>', by | |
142 | command line options, and based on the default architecture. */ | |
143 | int ase_mips3d; | |
deec1734 | 144 | int ase_mdmx; |
252b5132 RH |
145 | /* Whether we are assembling for the mips16 processor. 0 if we are |
146 | not, 1 if we are, and -1 if the value has not been initialized. | |
147 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
148 | -nomips16 command line options, and the default CPU. */ | |
149 | int mips16; | |
150 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
151 | reorder' and `.set noreorder'. */ | |
152 | int noreorder; | |
153 | /* Non-zero if we should not permit the $at ($1) register to be used | |
154 | in instructions. Changed by `.set at' and `.set noat'. */ | |
155 | int noat; | |
156 | /* Non-zero if we should warn when a macro instruction expands into | |
157 | more than one machine instruction. Changed by `.set nomacro' and | |
158 | `.set macro'. */ | |
159 | int warn_about_macros; | |
160 | /* Non-zero if we should not move instructions. Changed by `.set | |
161 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
162 | int nomove; | |
163 | /* Non-zero if we should not optimize branches by moving the target | |
164 | of the branch into the delay slot. Actually, we don't perform | |
165 | this optimization anyhow. Changed by `.set bopt' and `.set | |
166 | nobopt'. */ | |
167 | int nobopt; | |
168 | /* Non-zero if we should not autoextend mips16 instructions. | |
169 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
170 | int noautoextend; | |
a325df1d TS |
171 | /* Restrict general purpose registers and floating point registers |
172 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
173 | is passed but can changed if the assembler code uses .set mipsN. */ | |
174 | int gp32; | |
175 | int fp32; | |
176 | /* The ABI currently in use. This is changed by .set mipsN to loosen | |
177 | restrictions and doesn't affect the whole file. */ | |
178 | enum mips_abi_level abi; | |
252b5132 RH |
179 | }; |
180 | ||
a325df1d | 181 | /* True if -mgp32 was passed. */ |
a8e8e863 | 182 | static int file_mips_gp32 = -1; |
a325df1d TS |
183 | |
184 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 185 | static int file_mips_fp32 = -1; |
a325df1d | 186 | |
252b5132 | 187 | /* This is the struct we use to hold the current set of options. Note |
e7af610e NC |
188 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
189 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 190 | |
e972090a NC |
191 | static struct mips_set_options mips_opts = |
192 | { | |
deec1734 | 193 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI |
e7af610e | 194 | }; |
252b5132 RH |
195 | |
196 | /* These variables are filled in with the masks of registers used. | |
197 | The object format code reads them and puts them in the appropriate | |
198 | place. */ | |
199 | unsigned long mips_gprmask; | |
200 | unsigned long mips_cprmask[4]; | |
201 | ||
202 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 203 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 204 | |
1f25f5d3 CD |
205 | /* True if -mips3d was passed or implied by arguments passed on the |
206 | command line (e.g., by -march). */ | |
207 | static int file_ase_mips3d; | |
208 | ||
deec1734 CD |
209 | /* True if -mdmx was passed or implied by arguments passed on the |
210 | command line (e.g., by -march). */ | |
211 | static int file_ase_mdmx; | |
212 | ||
ec68c924 | 213 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 214 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 215 | |
ec68c924 EC |
216 | /* The argument of the -march= flag. The architecture we are assembling. */ |
217 | static int mips_arch = CPU_UNKNOWN; | |
218 | ||
219 | /* The argument of the -mtune= flag. The architecture for which we | |
220 | are optimizing. */ | |
221 | static int mips_tune = CPU_UNKNOWN; | |
222 | ||
2f4dcb11 | 223 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
224 | static int mips_eabi64 = 0; |
225 | ||
226 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 227 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
228 | static int mips_32bitmode = 0; |
229 | ||
9ce8a5dd GRK |
230 | /* Some ISA's have delay slots for instructions which read or write |
231 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 232 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
233 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
234 | delay slot in this ISA. The uses of this macro assume that any | |
235 | ISA that has delay slots for one of these, has them for all. They | |
236 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 237 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 238 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
239 | (ISA) == ISA_MIPS1 \ |
240 | || (ISA) == ISA_MIPS2 \ | |
241 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
242 | ) |
243 | ||
bdaaa2e1 | 244 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 245 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
246 | (ISA) == ISA_MIPS3 \ |
247 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 248 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 249 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
250 | ) |
251 | ||
e013f690 | 252 | #define HAVE_32BIT_GPRS \ |
a325df1d TS |
253 | (mips_opts.gp32 \ |
254 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 255 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 256 | |
e013f690 | 257 | #define HAVE_32BIT_FPRS \ |
a325df1d TS |
258 | (mips_opts.fp32 \ |
259 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 260 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
261 | |
262 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
263 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
264 | ||
a325df1d | 265 | #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI) |
e013f690 | 266 | |
a325df1d | 267 | #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI) |
e013f690 TS |
268 | |
269 | /* We can only have 64bit addresses if the object file format | |
270 | supports it. */ | |
afdbd6d0 CD |
271 | #define HAVE_32BIT_ADDRESSES \ |
272 | (HAVE_32BIT_GPRS \ | |
273 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
274 | || ! HAVE_64BIT_OBJECTS) \ | |
275 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
276 | |
277 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 278 | |
1f25f5d3 CD |
279 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
280 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
281 | ) | |
282 | ||
deec1734 CD |
283 | /* Return true if the given CPU supports the MDMX ASE. */ |
284 | #define CPU_HAS_MDMX(cpu) (0 \ | |
285 | ) | |
286 | ||
bdaaa2e1 | 287 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 288 | reads from the HI and LO registers, and thus does not |
ec68c924 | 289 | require nops to be inserted. */ |
252b5132 | 290 | |
ec68c924 | 291 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
0a758a12 | 292 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
293 | ) |
294 | ||
295 | /* Whether the processor uses hardware interlocks to protect reads | |
296 | from the GPRs, and thus does not require nops to be inserted. */ | |
297 | #define gpr_interlocks \ | |
e7af610e | 298 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 299 | || mips_arch == CPU_R3900) |
252b5132 RH |
300 | |
301 | /* As with other "interlocks" this is used by hardware that has FP | |
302 | (co-processor) interlocks. */ | |
bdaaa2e1 | 303 | /* Itbl support may require additional care here. */ |
ec68c924 | 304 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
0a758a12 | 305 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
306 | ) |
307 | ||
6b76fefe CM |
308 | /* Is this a mfhi or mflo instruction? */ |
309 | #define MF_HILO_INSN(PINFO) \ | |
310 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
311 | ||
252b5132 RH |
312 | /* MIPS PIC level. */ |
313 | ||
e972090a NC |
314 | enum mips_pic_level |
315 | { | |
252b5132 RH |
316 | /* Do not generate PIC code. */ |
317 | NO_PIC, | |
318 | ||
319 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
320 | not sure what it is supposed to do. */ | |
321 | IRIX4_PIC, | |
322 | ||
323 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
324 | SVR4_PIC, | |
325 | ||
326 | /* Generate PIC code without using a global offset table: the data | |
327 | segment has a maximum size of 64K, all data references are off | |
328 | the $gp register, and all text references are PC relative. This | |
329 | is used on some embedded systems. */ | |
330 | EMBEDDED_PIC | |
331 | }; | |
332 | ||
333 | static enum mips_pic_level mips_pic; | |
334 | ||
39c0a331 L |
335 | /* Warn about all NOPS that the assembler generates. */ |
336 | static int warn_nops = 0; | |
337 | ||
c9914766 | 338 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 339 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 340 | static int mips_big_got = 0; |
252b5132 RH |
341 | |
342 | /* 1 if trap instructions should used for overflow rather than break | |
343 | instructions. */ | |
c9914766 | 344 | static int mips_trap = 0; |
252b5132 | 345 | |
119d663a | 346 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 347 | by assembling two single width halves into two single width floating |
119d663a NC |
348 | point registers which just happen to alias the double width destination |
349 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 350 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
351 | automatically at assemble time. */ |
352 | static int mips_disable_float_construction; | |
353 | ||
252b5132 RH |
354 | /* Non-zero if any .set noreorder directives were used. */ |
355 | ||
356 | static int mips_any_noreorder; | |
357 | ||
6b76fefe CM |
358 | /* Non-zero if nops should be inserted when the register referenced in |
359 | an mfhi/mflo instruction is read in the next two instructions. */ | |
360 | static int mips_7000_hilo_fix; | |
361 | ||
252b5132 | 362 | /* The size of the small data section. */ |
156c2f8b | 363 | static unsigned int g_switch_value = 8; |
252b5132 RH |
364 | /* Whether the -G option was used. */ |
365 | static int g_switch_seen = 0; | |
366 | ||
367 | #define N_RMASK 0xc4 | |
368 | #define N_VFP 0xd4 | |
369 | ||
370 | /* If we can determine in advance that GP optimization won't be | |
371 | possible, we can skip the relaxation stuff that tries to produce | |
372 | GP-relative references. This makes delay slot optimization work | |
373 | better. | |
374 | ||
375 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
376 | gcc output. It needs to guess right for gcc, otherwise gcc |
377 | will put what it thinks is a GP-relative instruction in a branch | |
378 | delay slot. | |
252b5132 RH |
379 | |
380 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
381 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
382 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
383 | ||
384 | /* handle of the OPCODE hash table */ | |
385 | static struct hash_control *op_hash = NULL; | |
386 | ||
387 | /* The opcode hash table we use for the mips16. */ | |
388 | static struct hash_control *mips16_op_hash = NULL; | |
389 | ||
390 | /* This array holds the chars that always start a comment. If the | |
391 | pre-processor is disabled, these aren't very useful */ | |
392 | const char comment_chars[] = "#"; | |
393 | ||
394 | /* This array holds the chars that only start a comment at the beginning of | |
395 | a line. If the line seems to have the form '# 123 filename' | |
396 | .line and .file directives will appear in the pre-processed output */ | |
397 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
398 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 399 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
400 | /* Also note that C style comments are always supported. */ |
401 | const char line_comment_chars[] = "#"; | |
402 | ||
bdaaa2e1 | 403 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 404 | const char line_separator_chars[] = ";"; |
252b5132 RH |
405 | |
406 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
407 | const char EXP_CHARS[] = "eE"; | |
408 | ||
409 | /* Chars that mean this number is a floating point constant */ | |
410 | /* As in 0f12.456 */ | |
411 | /* or 0d1.2345e12 */ | |
412 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
413 | ||
414 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
415 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
416 | but nothing is ideal around here. | |
417 | */ | |
418 | ||
419 | static char *insn_error; | |
420 | ||
421 | static int auto_align = 1; | |
422 | ||
423 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
424 | offset in the stack frame from which to restore the $gp register. | |
425 | This is set by the .cprestore pseudo-op, and saved in this | |
426 | variable. */ | |
427 | static offsetT mips_cprestore_offset = -1; | |
428 | ||
6478892d TS |
429 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
430 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 431 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
432 | static offsetT mips_cpreturn_offset = -1; |
433 | static int mips_cpreturn_register = -1; | |
434 | static int mips_gp_register = GP; | |
def2e0dd | 435 | static int mips_gprel_offset = 0; |
6478892d | 436 | |
7a621144 DJ |
437 | /* Whether mips_cprestore_offset has been set in the current function |
438 | (or whether it has already been warned about, if not). */ | |
439 | static int mips_cprestore_valid = 0; | |
440 | ||
252b5132 RH |
441 | /* This is the register which holds the stack frame, as set by the |
442 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
443 | static int mips_frame_reg = SP; | |
444 | ||
7a621144 DJ |
445 | /* Whether mips_frame_reg has been set in the current function |
446 | (or whether it has already been warned about, if not). */ | |
447 | static int mips_frame_reg_valid = 0; | |
448 | ||
252b5132 RH |
449 | /* To output NOP instructions correctly, we need to keep information |
450 | about the previous two instructions. */ | |
451 | ||
452 | /* Whether we are optimizing. The default value of 2 means to remove | |
453 | unneeded NOPs and swap branch instructions when possible. A value | |
454 | of 1 means to not swap branches. A value of 0 means to always | |
455 | insert NOPs. */ | |
456 | static int mips_optimize = 2; | |
457 | ||
458 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
459 | equivalent to seeing no -g option at all. */ | |
460 | static int mips_debug = 0; | |
461 | ||
462 | /* The previous instruction. */ | |
463 | static struct mips_cl_insn prev_insn; | |
464 | ||
465 | /* The instruction before prev_insn. */ | |
466 | static struct mips_cl_insn prev_prev_insn; | |
467 | ||
468 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
469 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 470 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
471 | |
472 | /* Non-zero if prev_insn is valid. */ | |
473 | static int prev_insn_valid; | |
474 | ||
475 | /* The frag for the previous instruction. */ | |
476 | static struct frag *prev_insn_frag; | |
477 | ||
478 | /* The offset into prev_insn_frag for the previous instruction. */ | |
479 | static long prev_insn_where; | |
480 | ||
481 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 482 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
483 | |
484 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 485 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
486 | |
487 | /* Non-zero if the previous instruction was in a delay slot. */ | |
488 | static int prev_insn_is_delay_slot; | |
489 | ||
490 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
491 | static int prev_insn_unreordered; | |
492 | ||
493 | /* Non-zero if the previous instruction uses an extend opcode (if | |
494 | mips16). */ | |
495 | static int prev_insn_extended; | |
496 | ||
497 | /* Non-zero if the previous previous instruction was in a .set | |
498 | noreorder. */ | |
499 | static int prev_prev_insn_unreordered; | |
500 | ||
501 | /* If this is set, it points to a frag holding nop instructions which | |
502 | were inserted before the start of a noreorder section. If those | |
503 | nops turn out to be unnecessary, the size of the frag can be | |
504 | decreased. */ | |
505 | static fragS *prev_nop_frag; | |
506 | ||
507 | /* The number of nop instructions we created in prev_nop_frag. */ | |
508 | static int prev_nop_frag_holds; | |
509 | ||
510 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 511 | prev_nop_frag. */ |
252b5132 RH |
512 | static int prev_nop_frag_required; |
513 | ||
514 | /* The number of instructions we've seen since prev_nop_frag. */ | |
515 | static int prev_nop_frag_since; | |
516 | ||
517 | /* For ECOFF and ELF, relocations against symbols are done in two | |
518 | parts, with a HI relocation and a LO relocation. Each relocation | |
519 | has only 16 bits of space to store an addend. This means that in | |
520 | order for the linker to handle carries correctly, it must be able | |
521 | to locate both the HI and the LO relocation. This means that the | |
522 | relocations must appear in order in the relocation table. | |
523 | ||
524 | In order to implement this, we keep track of each unmatched HI | |
525 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 526 | corresponding LO relocation. */ |
252b5132 | 527 | |
e972090a NC |
528 | struct mips_hi_fixup |
529 | { | |
252b5132 RH |
530 | /* Next HI fixup. */ |
531 | struct mips_hi_fixup *next; | |
532 | /* This fixup. */ | |
533 | fixS *fixp; | |
534 | /* The section this fixup is in. */ | |
535 | segT seg; | |
536 | }; | |
537 | ||
538 | /* The list of unmatched HI relocs. */ | |
539 | ||
540 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
541 | ||
542 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
543 | ||
544 | #define X ILLEGAL_REG | |
e972090a NC |
545 | static const int mips32_to_16_reg_map[] = |
546 | { | |
252b5132 RH |
547 | X, X, 2, 3, 4, 5, 6, 7, |
548 | X, X, X, X, X, X, X, X, | |
549 | 0, 1, X, X, X, X, X, X, | |
550 | X, X, X, X, X, X, X, X | |
551 | }; | |
552 | #undef X | |
553 | ||
554 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
555 | ||
e972090a NC |
556 | static const unsigned int mips16_to_32_reg_map[] = |
557 | { | |
252b5132 RH |
558 | 16, 17, 2, 3, 4, 5, 6, 7 |
559 | }; | |
560 | \f | |
561 | /* Since the MIPS does not have multiple forms of PC relative | |
562 | instructions, we do not have to do relaxing as is done on other | |
563 | platforms. However, we do have to handle GP relative addressing | |
564 | correctly, which turns out to be a similar problem. | |
565 | ||
566 | Every macro that refers to a symbol can occur in (at least) two | |
567 | forms, one with GP relative addressing and one without. For | |
568 | example, loading a global variable into a register generally uses | |
569 | a macro instruction like this: | |
570 | lw $4,i | |
571 | If i can be addressed off the GP register (this is true if it is in | |
572 | the .sbss or .sdata section, or if it is known to be smaller than | |
573 | the -G argument) this will generate the following instruction: | |
574 | lw $4,i($gp) | |
575 | This instruction will use a GPREL reloc. If i can not be addressed | |
576 | off the GP register, the following instruction sequence will be used: | |
577 | lui $at,i | |
578 | lw $4,i($at) | |
579 | In this case the first instruction will have a HI16 reloc, and the | |
580 | second reloc will have a LO16 reloc. Both relocs will be against | |
581 | the symbol i. | |
582 | ||
583 | The issue here is that we may not know whether i is GP addressable | |
584 | until after we see the instruction that uses it. Therefore, we | |
585 | want to be able to choose the final instruction sequence only at | |
586 | the end of the assembly. This is similar to the way other | |
587 | platforms choose the size of a PC relative instruction only at the | |
588 | end of assembly. | |
589 | ||
590 | When generating position independent code we do not use GP | |
591 | addressing in quite the same way, but the issue still arises as | |
592 | external symbols and local symbols must be handled differently. | |
593 | ||
594 | We handle these issues by actually generating both possible | |
595 | instruction sequences. The longer one is put in a frag_var with | |
596 | type rs_machine_dependent. We encode what to do with the frag in | |
597 | the subtype field. We encode (1) the number of existing bytes to | |
598 | replace, (2) the number of new bytes to use, (3) the offset from | |
599 | the start of the existing bytes to the first reloc we must generate | |
600 | (that is, the offset is applied from the start of the existing | |
601 | bytes after they are replaced by the new bytes, if any), (4) the | |
602 | offset from the start of the existing bytes to the second reloc, | |
603 | (5) whether a third reloc is needed (the third reloc is always four | |
604 | bytes after the second reloc), and (6) whether to warn if this | |
605 | variant is used (this is sometimes needed if .set nomacro or .set | |
606 | noat is in effect). All these numbers are reasonably small. | |
607 | ||
608 | Generating two instruction sequences must be handled carefully to | |
609 | ensure that delay slots are handled correctly. Fortunately, there | |
610 | are a limited number of cases. When the second instruction | |
611 | sequence is generated, append_insn is directed to maintain the | |
612 | existing delay slot information, so it continues to apply to any | |
613 | code after the second instruction sequence. This means that the | |
614 | second instruction sequence must not impose any requirements not | |
615 | required by the first instruction sequence. | |
616 | ||
617 | These variant frags are then handled in functions called by the | |
618 | machine independent code. md_estimate_size_before_relax returns | |
619 | the final size of the frag. md_convert_frag sets up the final form | |
620 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
621 | one if needed. */ | |
622 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
623 | ((relax_substateT) \ | |
624 | (((old) << 23) \ | |
625 | | ((new) << 16) \ | |
626 | | (((reloc1) + 64) << 9) \ | |
627 | | (((reloc2) + 64) << 2) \ | |
628 | | ((reloc3) ? (1 << 1) : 0) \ | |
629 | | ((warn) ? 1 : 0))) | |
630 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
631 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
632 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
633 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
634 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
635 | #define RELAX_WARN(i) ((i) & 1) | |
636 | ||
637 | /* For mips16 code, we use an entirely different form of relaxation. | |
638 | mips16 supports two versions of most instructions which take | |
639 | immediate values: a small one which takes some small value, and a | |
640 | larger one which takes a 16 bit value. Since branches also follow | |
641 | this pattern, relaxing these values is required. | |
642 | ||
643 | We can assemble both mips16 and normal MIPS code in a single | |
644 | object. Therefore, we need to support this type of relaxation at | |
645 | the same time that we support the relaxation described above. We | |
646 | use the high bit of the subtype field to distinguish these cases. | |
647 | ||
648 | The information we store for this type of relaxation is the | |
649 | argument code found in the opcode file for this relocation, whether | |
650 | the user explicitly requested a small or extended form, and whether | |
651 | the relocation is in a jump or jal delay slot. That tells us the | |
652 | size of the value, and how it should be stored. We also store | |
653 | whether the fragment is considered to be extended or not. We also | |
654 | store whether this is known to be a branch to a different section, | |
655 | whether we have tried to relax this frag yet, and whether we have | |
656 | ever extended a PC relative fragment because of a shift count. */ | |
657 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
658 | (0x80000000 \ | |
659 | | ((type) & 0xff) \ | |
660 | | ((small) ? 0x100 : 0) \ | |
661 | | ((ext) ? 0x200 : 0) \ | |
662 | | ((dslot) ? 0x400 : 0) \ | |
663 | | ((jal_dslot) ? 0x800 : 0)) | |
664 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
665 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
666 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
667 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
668 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
669 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
670 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
671 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
672 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
673 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
674 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
675 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
676 | \f | |
677 | /* Prototypes for static functions. */ | |
678 | ||
679 | #ifdef __STDC__ | |
680 | #define internalError() \ | |
681 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
682 | #else | |
683 | #define internalError() as_fatal (_("MIPS internal Error")); | |
684 | #endif | |
685 | ||
686 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
687 | ||
688 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
689 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 690 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
691 | static void mips16_mark_labels PARAMS ((void)); |
692 | static void append_insn PARAMS ((char *place, | |
693 | struct mips_cl_insn * ip, | |
694 | expressionS * p, | |
f6688943 | 695 | bfd_reloc_code_real_type *r, |
252b5132 RH |
696 | boolean)); |
697 | static void mips_no_prev_insn PARAMS ((int)); | |
698 | static void mips_emit_delays PARAMS ((boolean)); | |
699 | #ifdef USE_STDARG | |
700 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
701 | const char *name, const char *fmt, | |
702 | ...)); | |
703 | #else | |
704 | static void macro_build (); | |
705 | #endif | |
706 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
707 | const char *, const char *, | |
708 | va_list)); | |
438c16b8 | 709 | static void macro_build_jalr PARAMS ((int, expressionS *)); |
252b5132 RH |
710 | static void macro_build_lui PARAMS ((char *place, int *counter, |
711 | expressionS * ep, int regnum)); | |
712 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
713 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
714 | expressionS *)); | |
715 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
c9914766 | 716 | static void load_address PARAMS ((int *, int, expressionS *, int *)); |
ea1fb5dc | 717 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
718 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
719 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
720 | #ifdef LOSING_COMPILER | |
721 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
722 | #endif | |
723 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
724 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
725 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
726 | boolean, boolean, unsigned long *, | |
727 | boolean *, unsigned short *)); | |
394f9b3a | 728 | static int my_getPercentOp PARAMS ((char **, unsigned int *, int *)); |
ad8d3bb3 TS |
729 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
730 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
731 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
ae948b86 | 732 | #ifdef OBJ_ELF |
e013f690 | 733 | static int support_64bit_objects PARAMS((void)); |
ae948b86 | 734 | #endif |
252b5132 RH |
735 | static symbolS *get_symbol PARAMS ((void)); |
736 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
737 | static void s_align PARAMS ((int)); | |
738 | static void s_change_sec PARAMS ((int)); | |
739 | static void s_cons PARAMS ((int)); | |
740 | static void s_float_cons PARAMS ((int)); | |
741 | static void s_mips_globl PARAMS ((int)); | |
742 | static void s_option PARAMS ((int)); | |
743 | static void s_mipsset PARAMS ((int)); | |
744 | static void s_abicalls PARAMS ((int)); | |
745 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
746 | static void s_cpsetup PARAMS ((int)); |
747 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 748 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
749 | static void s_cpreturn PARAMS ((int)); |
750 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
751 | static void s_gpword PARAMS ((int)); |
752 | static void s_cpadd PARAMS ((int)); | |
753 | static void s_insn PARAMS ((int)); | |
754 | static void md_obj_begin PARAMS ((void)); | |
755 | static void md_obj_end PARAMS ((void)); | |
756 | static long get_number PARAMS ((void)); | |
757 | static void s_mips_ent PARAMS ((int)); | |
758 | static void s_mips_end PARAMS ((int)); | |
759 | static void s_mips_frame PARAMS ((int)); | |
760 | static void s_mips_mask PARAMS ((int)); | |
761 | static void s_mips_stab PARAMS ((int)); | |
762 | static void s_mips_weakext PARAMS ((int)); | |
763 | static void s_file PARAMS ((int)); | |
764 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
765 | static const char *mips_isa_to_str PARAMS ((int)); |
766 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 767 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e87a0284 | 768 | static void show PARAMS ((FILE *, char *, int *, int *)); |
add55e1f RS |
769 | #ifdef OBJ_ELF |
770 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); | |
771 | #endif | |
e7af610e | 772 | |
ad8d3bb3 | 773 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 774 | |
ad8d3bb3 | 775 | enum small_ex_type |
fb1b3232 TS |
776 | { |
777 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
778 | S_EX_REGISTER, |
779 | ||
780 | /* Direct relocation creation by %percent_op(). */ | |
781 | S_EX_HALF, | |
fb1b3232 | 782 | S_EX_HI, |
ad8d3bb3 TS |
783 | S_EX_LO, |
784 | S_EX_GP_REL, | |
785 | S_EX_GOT, | |
786 | S_EX_CALL16, | |
787 | S_EX_GOT_DISP, | |
788 | S_EX_GOT_PAGE, | |
789 | S_EX_GOT_OFST, | |
790 | S_EX_GOT_HI, | |
791 | S_EX_GOT_LO, | |
792 | S_EX_NEG, | |
fb1b3232 TS |
793 | S_EX_HIGHER, |
794 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
795 | S_EX_CALL_HI, |
796 | S_EX_CALL_LO | |
fb1b3232 TS |
797 | }; |
798 | ||
e7af610e NC |
799 | /* Table and functions used to map between CPU/ISA names, and |
800 | ISA levels, and CPU numbers. */ | |
801 | ||
e972090a NC |
802 | struct mips_cpu_info |
803 | { | |
e7af610e NC |
804 | const char *name; /* CPU or ISA name. */ |
805 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
806 | int isa; /* ISA level. */ | |
807 | int cpu; /* CPU number (default CPU if ISA). */ | |
808 | }; | |
809 | ||
810 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
811 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
812 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
813 | \f |
814 | /* Pseudo-op table. | |
815 | ||
816 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
817 | should be defined here, but are currently unsupported: .alias, | |
818 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
819 | ||
820 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
821 | specific to the type of debugging information being generated, and | |
822 | should be defined by the object format: .aent, .begin, .bend, | |
823 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
824 | .vreg. | |
825 | ||
826 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
827 | not MIPS CPU specific, but are also not specific to the object file | |
828 | format. This file is probably the best place to define them, but | |
829 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
830 | .struct. */ | |
831 | ||
e972090a NC |
832 | static const pseudo_typeS mips_pseudo_table[] = |
833 | { | |
beae10d5 | 834 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
835 | {"option", s_option, 0}, |
836 | {"set", s_mipsset, 0}, | |
837 | {"rdata", s_change_sec, 'r'}, | |
838 | {"sdata", s_change_sec, 's'}, | |
839 | {"livereg", s_ignore, 0}, | |
840 | {"abicalls", s_abicalls, 0}, | |
841 | {"cpload", s_cpload, 0}, | |
6478892d TS |
842 | {"cpsetup", s_cpsetup, 0}, |
843 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 844 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
845 | {"cpreturn", s_cpreturn, 0}, |
846 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
847 | {"gpword", s_gpword, 0}, |
848 | {"cpadd", s_cpadd, 0}, | |
849 | {"insn", s_insn, 0}, | |
850 | ||
beae10d5 | 851 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
852 | chips. */ |
853 | {"asciiz", stringer, 1}, | |
854 | {"bss", s_change_sec, 'b'}, | |
855 | {"err", s_err, 0}, | |
856 | {"half", s_cons, 1}, | |
857 | {"dword", s_cons, 3}, | |
858 | {"weakext", s_mips_weakext, 0}, | |
859 | ||
beae10d5 | 860 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
861 | here for one reason or another. */ |
862 | {"align", s_align, 0}, | |
863 | {"byte", s_cons, 0}, | |
864 | {"data", s_change_sec, 'd'}, | |
865 | {"double", s_float_cons, 'd'}, | |
866 | {"float", s_float_cons, 'f'}, | |
867 | {"globl", s_mips_globl, 0}, | |
868 | {"global", s_mips_globl, 0}, | |
869 | {"hword", s_cons, 1}, | |
870 | {"int", s_cons, 2}, | |
871 | {"long", s_cons, 2}, | |
872 | {"octa", s_cons, 4}, | |
873 | {"quad", s_cons, 3}, | |
874 | {"short", s_cons, 1}, | |
875 | {"single", s_float_cons, 'f'}, | |
876 | {"stabn", s_mips_stab, 'n'}, | |
877 | {"text", s_change_sec, 't'}, | |
878 | {"word", s_cons, 2}, | |
add56521 L |
879 | |
880 | #ifdef MIPS_STABS_ELF | |
881 | { "extern", ecoff_directive_extern, 0}, | |
882 | #endif | |
883 | ||
43841e91 | 884 | { NULL, NULL, 0 }, |
252b5132 RH |
885 | }; |
886 | ||
e972090a NC |
887 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
888 | { | |
beae10d5 KH |
889 | /* These pseudo-ops should be defined by the object file format. |
890 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
891 | {"aent", s_mips_ent, 1}, |
892 | {"bgnb", s_ignore, 0}, | |
893 | {"end", s_mips_end, 0}, | |
894 | {"endb", s_ignore, 0}, | |
895 | {"ent", s_mips_ent, 0}, | |
896 | {"file", s_file, 0}, | |
897 | {"fmask", s_mips_mask, 'F'}, | |
898 | {"frame", s_mips_frame, 0}, | |
899 | {"loc", s_ignore, 0}, | |
900 | {"mask", s_mips_mask, 'R'}, | |
901 | {"verstamp", s_ignore, 0}, | |
43841e91 | 902 | { NULL, NULL, 0 }, |
252b5132 RH |
903 | }; |
904 | ||
905 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
906 | ||
907 | void | |
908 | mips_pop_insert () | |
909 | { | |
910 | pop_insert (mips_pseudo_table); | |
911 | if (! ECOFF_DEBUGGING) | |
912 | pop_insert (mips_nonecoff_pseudo_table); | |
913 | } | |
914 | \f | |
915 | /* Symbols labelling the current insn. */ | |
916 | ||
e972090a NC |
917 | struct insn_label_list |
918 | { | |
252b5132 RH |
919 | struct insn_label_list *next; |
920 | symbolS *label; | |
921 | }; | |
922 | ||
923 | static struct insn_label_list *insn_labels; | |
924 | static struct insn_label_list *free_insn_labels; | |
925 | ||
926 | static void mips_clear_insn_labels PARAMS ((void)); | |
927 | ||
928 | static inline void | |
929 | mips_clear_insn_labels () | |
930 | { | |
931 | register struct insn_label_list **pl; | |
932 | ||
933 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
934 | ; | |
935 | *pl = insn_labels; | |
936 | insn_labels = NULL; | |
937 | } | |
938 | \f | |
939 | static char *expr_end; | |
940 | ||
941 | /* Expressions which appear in instructions. These are set by | |
942 | mips_ip. */ | |
943 | ||
944 | static expressionS imm_expr; | |
945 | static expressionS offset_expr; | |
946 | ||
947 | /* Relocs associated with imm_expr and offset_expr. */ | |
948 | ||
f6688943 TS |
949 | static bfd_reloc_code_real_type imm_reloc[3] |
950 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
951 | static bfd_reloc_code_real_type offset_reloc[3] | |
952 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
953 | |
954 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
955 | ||
956 | static boolean imm_unmatched_hi; | |
957 | ||
958 | /* These are set by mips16_ip if an explicit extension is used. */ | |
959 | ||
960 | static boolean mips16_small, mips16_ext; | |
961 | ||
962 | #ifdef MIPS_STABS_ELF | |
963 | /* The pdr segment for per procedure frame/regmask info */ | |
964 | ||
965 | static segT pdr_seg; | |
966 | #endif | |
967 | ||
e7af610e NC |
968 | static const char * |
969 | mips_isa_to_str (isa) | |
970 | int isa; | |
971 | { | |
972 | const struct mips_cpu_info *ci; | |
973 | static char s[20]; | |
974 | ||
975 | ci = mips_cpu_info_from_isa (isa); | |
976 | if (ci != NULL) | |
977 | return (ci->name); | |
978 | ||
979 | sprintf (s, "ISA#%d", isa); | |
980 | return s; | |
981 | } | |
982 | ||
983 | static const char * | |
156c2f8b NC |
984 | mips_cpu_to_str (cpu) |
985 | int cpu; | |
986 | { | |
e7af610e | 987 | const struct mips_cpu_info *ci; |
156c2f8b | 988 | static char s[16]; |
e7af610e NC |
989 | |
990 | ci = mips_cpu_info_from_cpu (cpu); | |
991 | if (ci != NULL) | |
992 | return (ci->name); | |
993 | ||
994 | sprintf (s, "CPU#%d", cpu); | |
995 | return s; | |
156c2f8b NC |
996 | } |
997 | ||
e013f690 TS |
998 | /* The default target format to use. */ |
999 | ||
1000 | const char * | |
1001 | mips_target_format () | |
1002 | { | |
1003 | switch (OUTPUT_FLAVOR) | |
1004 | { | |
1005 | case bfd_target_aout_flavour: | |
1006 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1007 | case bfd_target_ecoff_flavour: | |
1008 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1009 | case bfd_target_coff_flavour: | |
1010 | return "pe-mips"; | |
1011 | case bfd_target_elf_flavour: | |
1012 | #ifdef TE_TMIPS | |
1013 | /* This is traditional mips */ | |
1014 | return (target_big_endian | |
1015 | ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips" | |
1016 | : "elf32-tradbigmips") | |
1017 | : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips" | |
1018 | : "elf32-tradlittlemips")); | |
1019 | #else | |
1020 | return (target_big_endian | |
1021 | ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips") | |
1022 | : (HAVE_64BIT_OBJECTS ? "elf64-littlemips" | |
1023 | : "elf32-littlemips")); | |
1024 | #endif | |
1025 | default: | |
1026 | abort (); | |
1027 | return NULL; | |
1028 | } | |
1029 | } | |
1030 | ||
156c2f8b NC |
1031 | /* This function is called once, at assembler startup time. It should |
1032 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1033 | ||
252b5132 RH |
1034 | void |
1035 | md_begin () | |
1036 | { | |
252b5132 | 1037 | register const char *retval = NULL; |
156c2f8b | 1038 | int i = 0; |
252b5132 RH |
1039 | const char *cpu; |
1040 | char *a = NULL; | |
1041 | int broken = 0; | |
1042 | int mips_isa_from_cpu; | |
e7af610e NC |
1043 | int target_cpu_had_mips16 = 0; |
1044 | const struct mips_cpu_info *ci; | |
252b5132 | 1045 | |
056350c6 NC |
1046 | /* GP relative stuff not working for PE */ |
1047 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
1048 | && g_switch_value != 0) | |
1049 | { | |
1050 | if (g_switch_seen) | |
1051 | as_bad (_("-G not supported in this configuration.")); | |
1052 | g_switch_value = 0; | |
1053 | } | |
1054 | ||
252b5132 RH |
1055 | cpu = TARGET_CPU; |
1056 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
1057 | { | |
1058 | a = xmalloc (sizeof TARGET_CPU); | |
1059 | strcpy (a, TARGET_CPU); | |
1060 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
1061 | cpu = a; | |
1062 | } | |
1063 | ||
e7af610e | 1064 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 1065 | { |
e7af610e NC |
1066 | target_cpu_had_mips16 = 1; |
1067 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
1068 | } |
1069 | ||
e7af610e NC |
1070 | if (mips_opts.mips16 < 0) |
1071 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 1072 | |
6dce9e24 TS |
1073 | /* Backward compatibility for historic -mcpu= option. Check for |
1074 | incompatible options, warn if -mcpu is used. */ | |
1075 | if (mips_cpu != CPU_UNKNOWN | |
1076 | && mips_arch != CPU_UNKNOWN | |
1077 | && mips_cpu != mips_arch) | |
1078 | { | |
1079 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
1080 | "Use -mtune instead of -mcpu.")); | |
1081 | } | |
1082 | ||
1083 | if (mips_cpu != CPU_UNKNOWN | |
1084 | && mips_tune != CPU_UNKNOWN | |
1085 | && mips_cpu != mips_tune) | |
1086 | { | |
1087 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
1088 | "Use -march instead of -mcpu.")); | |
1089 | } | |
1090 | ||
a8e8e863 DJ |
1091 | #if 1 |
1092 | /* For backward compatibility, let -mipsN set various defaults. */ | |
1093 | /* This code should go away, to be replaced with something rather more | |
1094 | draconian. Until GCC 3.1 has been released for some reasonable | |
1095 | amount of time, however, we need to support this. */ | |
1096 | if (mips_opts.isa != ISA_UNKNOWN) | |
1097 | { | |
1098 | /* Translate -mipsN to the appropriate settings of file_mips_gp32 | |
1099 | and file_mips_fp32. Tag binaries as using the mipsN ISA. */ | |
1100 | if (file_mips_gp32 < 0) | |
1101 | { | |
1102 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1103 | file_mips_gp32 = 0; | |
1104 | else | |
1105 | file_mips_gp32 = 1; | |
1106 | } | |
1107 | if (file_mips_fp32 < 0) | |
1108 | { | |
1109 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1110 | file_mips_fp32 = 0; | |
1111 | else | |
1112 | file_mips_fp32 = 1; | |
1113 | } | |
1114 | ||
1115 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1116 | assert (ci != NULL); | |
1117 | /* -mipsN has higher priority than -mcpu but lower than -march. */ | |
1118 | if (mips_arch == CPU_UNKNOWN) | |
1119 | mips_arch = ci->cpu; | |
1120 | ||
1121 | /* Default mips_abi. */ | |
1122 | if (mips_opts.abi == NO_ABI) | |
1123 | { | |
1124 | if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2) | |
1125 | mips_opts.abi = O32_ABI; | |
1126 | else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4) | |
1127 | mips_opts.abi = O64_ABI; | |
1128 | } | |
1129 | } | |
1130 | ||
6dce9e24 TS |
1131 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) |
1132 | { | |
1133 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1134 | assert (ci != NULL); | |
1135 | mips_arch = ci->cpu; | |
1136 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1137 | "-mtune instead.")); | |
1138 | } | |
1139 | ||
a8e8e863 DJ |
1140 | /* Set tune from -mcpu, not from -mipsN. */ |
1141 | if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1142 | { | |
1143 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1144 | assert (ci != NULL); | |
1145 | mips_tune = ci->cpu; | |
1146 | } | |
1147 | ||
ec68c924 | 1148 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
1149 | specified on the command line, or some other value if one was. |
1150 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1151 | the command line, or will be set otherwise if one was. */ | |
a8e8e863 DJ |
1152 | |
1153 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) | |
1154 | /* Handled above. */; | |
1155 | #else | |
1156 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1157 | { | |
1158 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1159 | assert (ci != NULL); | |
1160 | mips_arch = ci->cpu; | |
1161 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1162 | "-mtune instead.")); | |
1163 | } | |
1164 | ||
1165 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was | |
1166 | specified on the command line, or some other value if one was. | |
1167 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1168 | the command line, or will be set otherwise if one was. */ | |
1169 | ||
ec68c924 | 1170 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 1171 | { |
1ff54a84 TS |
1172 | /* We have to check if the isa is the default isa of arch. Otherwise |
1173 | we'll get invalid object file headers. */ | |
1174 | ci = mips_cpu_info_from_cpu (mips_arch); | |
1175 | assert (ci != NULL); | |
1176 | if (mips_opts.isa != ci->isa) | |
1177 | { | |
1178 | /* This really should be an error instead of a warning, but old | |
1179 | compilers only have -mcpu which sets both arch and tune. For | |
1180 | now, we discard arch and preserve tune. */ | |
1181 | as_warn (_("The -march option is incompatible to -mipsN and " | |
1182 | "therefore ignored.")); | |
1183 | if (mips_tune == CPU_UNKNOWN) | |
1184 | mips_tune = mips_arch; | |
1185 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1186 | assert (ci != NULL); | |
1187 | mips_arch = ci->cpu; | |
1188 | } | |
252b5132 | 1189 | } |
a8e8e863 | 1190 | #endif |
ec68c924 | 1191 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1192 | { |
ec68c924 EC |
1193 | /* We have ARCH, we need ISA. */ |
1194 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1195 | assert (ci != NULL); |
1196 | mips_opts.isa = ci->isa; | |
1197 | } | |
ec68c924 | 1198 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1199 | { |
ec68c924 | 1200 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1201 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1202 | assert (ci != NULL); | |
ec68c924 EC |
1203 | mips_arch = ci->cpu; |
1204 | } | |
e7af610e NC |
1205 | else |
1206 | { | |
ec68c924 | 1207 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1208 | ci = mips_cpu_info_from_name (cpu); |
1209 | if (ci == NULL) | |
beae10d5 | 1210 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1211 | assert (ci != NULL); |
1212 | mips_opts.isa = ci->isa; | |
ec68c924 | 1213 | mips_arch = ci->cpu; |
252b5132 RH |
1214 | } |
1215 | ||
ec68c924 EC |
1216 | if (mips_tune == CPU_UNKNOWN) |
1217 | mips_tune = mips_arch; | |
1218 | ||
1219 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1220 | assert (ci != NULL); |
1221 | mips_isa_from_cpu = ci->isa; | |
1222 | ||
252b5132 | 1223 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1224 | if necessary. */ |
252b5132 RH |
1225 | cpu = NULL; |
1226 | if (a != NULL) | |
1227 | { | |
156c2f8b NC |
1228 | free (a); |
1229 | a = NULL; | |
252b5132 RH |
1230 | } |
1231 | ||
e7af610e | 1232 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1233 | as_bad (_("trap exception not supported at ISA 1")); |
1234 | ||
1235 | /* Set the EABI kind based on the ISA before the user gets | |
1236 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1237 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1238 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
a325df1d | 1239 | && mips_opts.abi == EABI_ABI) |
252b5132 RH |
1240 | mips_eabi64 = 1; |
1241 | ||
e7af610e NC |
1242 | /* If they asked for mips1 or mips2 and a cpu that is |
1243 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1244 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1245 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1246 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1247 | mips_32bitmode = 1; | |
252b5132 | 1248 | |
1f25f5d3 CD |
1249 | /* If the selected architecture includes support for ASEs, enable |
1250 | generation of code for them. */ | |
1251 | if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch)) | |
1252 | mips_opts.ase_mips3d = 1; | |
deec1734 CD |
1253 | if (mips_opts.ase_mdmx == -1 && CPU_HAS_MDMX (mips_arch)) |
1254 | mips_opts.ase_mdmx = 1; | |
1f25f5d3 | 1255 | |
ec68c924 | 1256 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1257 | as_warn (_("Could not set architecture and machine")); |
1258 | ||
a8e8e863 DJ |
1259 | if (file_mips_gp32 < 0) |
1260 | file_mips_gp32 = 0; | |
1261 | if (file_mips_fp32 < 0) | |
1262 | file_mips_fp32 = 0; | |
1263 | ||
252b5132 | 1264 | file_mips_isa = mips_opts.isa; |
a325df1d | 1265 | file_mips_abi = mips_opts.abi; |
1f25f5d3 | 1266 | file_ase_mips3d = mips_opts.ase_mips3d; |
deec1734 | 1267 | file_ase_mdmx = mips_opts.ase_mdmx; |
a325df1d TS |
1268 | mips_opts.gp32 = file_mips_gp32; |
1269 | mips_opts.fp32 = file_mips_fp32; | |
252b5132 | 1270 | |
438c16b8 TS |
1271 | if (HAVE_NEWABI) |
1272 | mips_big_got = 1; | |
1273 | ||
252b5132 RH |
1274 | op_hash = hash_new (); |
1275 | ||
1276 | for (i = 0; i < NUMOPCODES;) | |
1277 | { | |
1278 | const char *name = mips_opcodes[i].name; | |
1279 | ||
1280 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1281 | if (retval != NULL) | |
1282 | { | |
1283 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1284 | mips_opcodes[i].name, retval); | |
1285 | /* Probably a memory allocation problem? Give up now. */ | |
1286 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1287 | } | |
1288 | do | |
1289 | { | |
1290 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1291 | { | |
1292 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1293 | broken = 1; | |
1294 | } | |
1295 | ++i; | |
1296 | } | |
1297 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1298 | } | |
1299 | ||
1300 | mips16_op_hash = hash_new (); | |
1301 | ||
1302 | i = 0; | |
1303 | while (i < bfd_mips16_num_opcodes) | |
1304 | { | |
1305 | const char *name = mips16_opcodes[i].name; | |
1306 | ||
1307 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1308 | if (retval != NULL) | |
1309 | as_fatal (_("internal: can't hash `%s': %s"), | |
1310 | mips16_opcodes[i].name, retval); | |
1311 | do | |
1312 | { | |
1313 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1314 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1315 | != mips16_opcodes[i].match)) | |
1316 | { | |
1317 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1318 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1319 | broken = 1; | |
1320 | } | |
1321 | ++i; | |
1322 | } | |
1323 | while (i < bfd_mips16_num_opcodes | |
1324 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1325 | } | |
1326 | ||
1327 | if (broken) | |
1328 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1329 | ||
1330 | /* We add all the general register names to the symbol table. This | |
1331 | helps us detect invalid uses of them. */ | |
1332 | for (i = 0; i < 32; i++) | |
1333 | { | |
1334 | char buf[5]; | |
1335 | ||
1336 | sprintf (buf, "$%d", i); | |
1337 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1338 | &zero_address_frag)); | |
1339 | } | |
1340 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1341 | &zero_address_frag)); | |
1342 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1343 | &zero_address_frag)); | |
1344 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1345 | &zero_address_frag)); | |
1346 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1347 | &zero_address_frag)); | |
1348 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1349 | &zero_address_frag)); | |
1350 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1351 | &zero_address_frag)); | |
1352 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1353 | &zero_address_frag)); | |
1354 | ||
1355 | mips_no_prev_insn (false); | |
1356 | ||
1357 | mips_gprmask = 0; | |
1358 | mips_cprmask[0] = 0; | |
1359 | mips_cprmask[1] = 0; | |
1360 | mips_cprmask[2] = 0; | |
1361 | mips_cprmask[3] = 0; | |
1362 | ||
1363 | /* set the default alignment for the text section (2**2) */ | |
1364 | record_alignment (text_section, 2); | |
1365 | ||
1366 | if (USE_GLOBAL_POINTER_OPT) | |
1367 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1368 | ||
1369 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1370 | { | |
1371 | /* On a native system, sections must be aligned to 16 byte | |
1372 | boundaries. When configured for an embedded ELF target, we | |
1373 | don't bother. */ | |
1374 | if (strcmp (TARGET_OS, "elf") != 0) | |
1375 | { | |
1376 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1377 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1378 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1379 | } | |
1380 | ||
1381 | /* Create a .reginfo section for register masks and a .mdebug | |
1382 | section for debugging information. */ | |
1383 | { | |
1384 | segT seg; | |
1385 | subsegT subseg; | |
1386 | flagword flags; | |
1387 | segT sec; | |
1388 | ||
1389 | seg = now_seg; | |
1390 | subseg = now_subseg; | |
1391 | ||
1392 | /* The ABI says this section should be loaded so that the | |
1393 | running program can access it. However, we don't load it | |
1394 | if we are configured for an embedded target */ | |
1395 | flags = SEC_READONLY | SEC_DATA; | |
1396 | if (strcmp (TARGET_OS, "elf") != 0) | |
1397 | flags |= SEC_ALLOC | SEC_LOAD; | |
1398 | ||
195325d2 | 1399 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
1400 | { |
1401 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1402 | ||
195325d2 TS |
1403 | bfd_set_section_flags (stdoutput, sec, flags); |
1404 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1405 | |
252b5132 RH |
1406 | #ifdef OBJ_ELF |
1407 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1408 | #endif | |
1409 | } | |
1410 | else | |
1411 | { | |
1412 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1413 | .reginfo section. */ | |
1414 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1415 | bfd_set_section_flags (stdoutput, sec, flags); |
1416 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1417 | |
1418 | #ifdef OBJ_ELF | |
1419 | /* Set up the option header. */ | |
1420 | { | |
1421 | Elf_Internal_Options opthdr; | |
1422 | char *f; | |
1423 | ||
1424 | opthdr.kind = ODK_REGINFO; | |
1425 | opthdr.size = (sizeof (Elf_External_Options) | |
1426 | + sizeof (Elf64_External_RegInfo)); | |
1427 | opthdr.section = 0; | |
1428 | opthdr.info = 0; | |
1429 | f = frag_more (sizeof (Elf_External_Options)); | |
1430 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1431 | (Elf_External_Options *) f); | |
1432 | ||
1433 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1434 | } | |
1435 | #endif | |
1436 | } | |
1437 | ||
1438 | if (ECOFF_DEBUGGING) | |
1439 | { | |
1440 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1441 | (void) bfd_set_section_flags (stdoutput, sec, | |
1442 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1443 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1444 | } | |
1445 | ||
1446 | #ifdef MIPS_STABS_ELF | |
1447 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1448 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1449 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1450 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1451 | #endif | |
1452 | ||
1453 | subseg_set (seg, subseg); | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | if (! ECOFF_DEBUGGING) | |
1458 | md_obj_begin (); | |
1459 | } | |
1460 | ||
1461 | void | |
1462 | md_mips_end () | |
1463 | { | |
1464 | if (! ECOFF_DEBUGGING) | |
1465 | md_obj_end (); | |
1466 | } | |
1467 | ||
1468 | void | |
1469 | md_assemble (str) | |
1470 | char *str; | |
1471 | { | |
1472 | struct mips_cl_insn insn; | |
f6688943 TS |
1473 | bfd_reloc_code_real_type unused_reloc[3] |
1474 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1475 | |
1476 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1477 | imm_unmatched_hi = false; |
1478 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1479 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1480 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1481 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1482 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1483 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1484 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1485 | |
1486 | if (mips_opts.mips16) | |
1487 | mips16_ip (str, &insn); | |
1488 | else | |
1489 | { | |
1490 | mips_ip (str, &insn); | |
beae10d5 KH |
1491 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1492 | str, insn.insn_opcode)); | |
252b5132 RH |
1493 | } |
1494 | ||
1495 | if (insn_error) | |
1496 | { | |
1497 | as_bad ("%s `%s'", insn_error, str); | |
1498 | return; | |
1499 | } | |
1500 | ||
1501 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1502 | { | |
1503 | if (mips_opts.mips16) | |
1504 | mips16_macro (&insn); | |
1505 | else | |
1506 | macro (&insn); | |
1507 | } | |
1508 | else | |
1509 | { | |
1510 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1511 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1512 | else if (offset_expr.X_op != O_absent) |
c4e7957c | 1513 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
252b5132 | 1514 | else |
c4e7957c | 1515 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1516 | } |
1517 | } | |
1518 | ||
1519 | /* See whether instruction IP reads register REG. CLASS is the type | |
1520 | of register. */ | |
1521 | ||
1522 | static int | |
1523 | insn_uses_reg (ip, reg, class) | |
1524 | struct mips_cl_insn *ip; | |
1525 | unsigned int reg; | |
1526 | enum mips_regclass class; | |
1527 | { | |
1528 | if (class == MIPS16_REG) | |
1529 | { | |
1530 | assert (mips_opts.mips16); | |
1531 | reg = mips16_to_32_reg_map[reg]; | |
1532 | class = MIPS_GR_REG; | |
1533 | } | |
1534 | ||
1535 | /* Don't report on general register 0, since it never changes. */ | |
1536 | if (class == MIPS_GR_REG && reg == 0) | |
1537 | return 0; | |
1538 | ||
1539 | if (class == MIPS_FP_REG) | |
1540 | { | |
1541 | assert (! mips_opts.mips16); | |
1542 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1543 | This is not optimal, because it will introduce an unnecessary | |
1544 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1545 | need to distinguish reading both $f0 and $f1 or just one of | |
1546 | them. Note that we don't have to check the other way, | |
1547 | because there is no instruction that sets both $f0 and $f1 | |
1548 | and requires a delay. */ | |
1549 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1550 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1551 | == (reg &~ (unsigned) 1))) | |
1552 | return 1; | |
1553 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1554 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1555 | == (reg &~ (unsigned) 1))) | |
1556 | return 1; | |
1557 | } | |
1558 | else if (! mips_opts.mips16) | |
1559 | { | |
1560 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1561 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1562 | return 1; | |
1563 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1564 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1565 | return 1; | |
1566 | } | |
1567 | else | |
1568 | { | |
1569 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1570 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1571 | & MIPS16OP_MASK_RX)] | |
1572 | == reg)) | |
1573 | return 1; | |
1574 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1575 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1576 | & MIPS16OP_MASK_RY)] | |
1577 | == reg)) | |
1578 | return 1; | |
1579 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1580 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1581 | & MIPS16OP_MASK_MOVE32Z)] | |
1582 | == reg)) | |
1583 | return 1; | |
1584 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1585 | return 1; | |
1586 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1587 | return 1; | |
1588 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1589 | return 1; | |
1590 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1591 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1592 | & MIPS16OP_MASK_REGR32) == reg) | |
1593 | return 1; | |
1594 | } | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | /* This function returns true if modifying a register requires a | |
1600 | delay. */ | |
1601 | ||
1602 | static int | |
1603 | reg_needs_delay (reg) | |
156c2f8b | 1604 | unsigned int reg; |
252b5132 RH |
1605 | { |
1606 | unsigned long prev_pinfo; | |
1607 | ||
1608 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1609 | if (! mips_opts.noreorder | |
9ce8a5dd | 1610 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1611 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1612 | || (! gpr_interlocks | |
1613 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1614 | { | |
1615 | /* A load from a coprocessor or from memory. All load | |
1616 | delays delay the use of general register rt for one | |
1617 | instruction on the r3000. The r6000 and r4000 use | |
1618 | interlocks. */ | |
bdaaa2e1 | 1619 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1620 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1621 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1622 | return 1; | |
1623 | } | |
1624 | ||
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1629 | handle them specially, such as generating jalx instructions when | |
1630 | needed. We also make them odd for the duration of the assembly, in | |
1631 | order to generate the right sort of code. We will make them even | |
1632 | in the adjust_symtab routine, while leaving them marked. This is | |
1633 | convenient for the debugger and the disassembler. The linker knows | |
1634 | to make them odd again. */ | |
1635 | ||
1636 | static void | |
1637 | mips16_mark_labels () | |
1638 | { | |
1639 | if (mips_opts.mips16) | |
1640 | { | |
1641 | struct insn_label_list *l; | |
98aa84af | 1642 | valueT val; |
252b5132 RH |
1643 | |
1644 | for (l = insn_labels; l != NULL; l = l->next) | |
1645 | { | |
1646 | #ifdef OBJ_ELF | |
1647 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1648 | S_SET_OTHER (l->label, STO_MIPS16); | |
1649 | #endif | |
98aa84af AM |
1650 | val = S_GET_VALUE (l->label); |
1651 | if ((val & 1) == 0) | |
1652 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1653 | } |
1654 | } | |
1655 | } | |
1656 | ||
1657 | /* Output an instruction. PLACE is where to put the instruction; if | |
1658 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1659 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1660 | used with RELOC_TYPE. */ | |
1661 | ||
1662 | static void | |
1663 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1664 | char *place; | |
1665 | struct mips_cl_insn *ip; | |
1666 | expressionS *address_expr; | |
f6688943 | 1667 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1668 | boolean unmatched_hi; |
1669 | { | |
1670 | register unsigned long prev_pinfo, pinfo; | |
1671 | char *f; | |
f6688943 | 1672 | fixS *fixp[3]; |
252b5132 RH |
1673 | int nops = 0; |
1674 | ||
1675 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1676 | mips16_mark_labels (); |
252b5132 RH |
1677 | |
1678 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1679 | pinfo = ip->insn_mo->pinfo; | |
1680 | ||
1681 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1682 | { | |
1683 | int prev_prev_nop; | |
1684 | ||
1685 | /* If the previous insn required any delay slots, see if we need | |
1686 | to insert a NOP or two. There are eight kinds of possible | |
1687 | hazards, of which an instruction can have at most one type. | |
1688 | (1) a load from memory delay | |
1689 | (2) a load from a coprocessor delay | |
1690 | (3) an unconditional branch delay | |
1691 | (4) a conditional branch delay | |
1692 | (5) a move to coprocessor register delay | |
1693 | (6) a load coprocessor register from memory delay | |
1694 | (7) a coprocessor condition code delay | |
1695 | (8) a HI/LO special register delay | |
1696 | ||
1697 | There are a lot of optimizations we could do that we don't. | |
1698 | In particular, we do not, in general, reorder instructions. | |
1699 | If you use gcc with optimization, it will reorder | |
1700 | instructions and generally do much more optimization then we | |
1701 | do here; repeating all that work in the assembler would only | |
1702 | benefit hand written assembly code, and does not seem worth | |
1703 | it. */ | |
1704 | ||
1705 | /* This is how a NOP is emitted. */ | |
1706 | #define emit_nop() \ | |
1707 | (mips_opts.mips16 \ | |
1708 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1709 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1710 | ||
1711 | /* The previous insn might require a delay slot, depending upon | |
1712 | the contents of the current insn. */ | |
1713 | if (! mips_opts.mips16 | |
9ce8a5dd | 1714 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1715 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1716 | && ! cop_interlocks) | |
1717 | || (! gpr_interlocks | |
1718 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1719 | { | |
1720 | /* A load from a coprocessor or from memory. All load | |
1721 | delays delay the use of general register rt for one | |
1722 | instruction on the r3000. The r6000 and r4000 use | |
1723 | interlocks. */ | |
beae10d5 | 1724 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1725 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1726 | if (mips_optimize == 0 | |
1727 | || insn_uses_reg (ip, | |
1728 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1729 | & OP_MASK_RT), | |
1730 | MIPS_GR_REG)) | |
1731 | ++nops; | |
1732 | } | |
1733 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1734 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1735 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1736 | && ! cop_interlocks) |
e7af610e | 1737 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1738 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1739 | { | |
1740 | /* A generic coprocessor delay. The previous instruction | |
1741 | modified a coprocessor general or control register. If | |
1742 | it modified a control register, we need to avoid any | |
1743 | coprocessor instruction (this is probably not always | |
1744 | required, but it sometimes is). If it modified a general | |
1745 | register, we avoid using that register. | |
1746 | ||
1747 | On the r6000 and r4000 loading a coprocessor register | |
1748 | from memory is interlocked, and does not require a delay. | |
1749 | ||
1750 | This case is not handled very well. There is no special | |
1751 | knowledge of CP0 handling, and the coprocessors other | |
1752 | than the floating point unit are not distinguished at | |
1753 | all. */ | |
1754 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1755 | Need to modify this to include knowledge about |
252b5132 RH |
1756 | user specified delays! */ |
1757 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1758 | { | |
1759 | if (mips_optimize == 0 | |
1760 | || insn_uses_reg (ip, | |
1761 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1762 | & OP_MASK_FT), | |
1763 | MIPS_FP_REG)) | |
1764 | ++nops; | |
1765 | } | |
1766 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1767 | { | |
1768 | if (mips_optimize == 0 | |
1769 | || insn_uses_reg (ip, | |
1770 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1771 | & OP_MASK_FS), | |
1772 | MIPS_FP_REG)) | |
1773 | ++nops; | |
1774 | } | |
1775 | else | |
1776 | { | |
1777 | /* We don't know exactly what the previous instruction | |
1778 | does. If the current instruction uses a coprocessor | |
1779 | register, we must insert a NOP. If previous | |
1780 | instruction may set the condition codes, and the | |
1781 | current instruction uses them, we must insert two | |
1782 | NOPS. */ | |
bdaaa2e1 | 1783 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1784 | if (mips_optimize == 0 |
1785 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1786 | && (pinfo & INSN_READ_COND_CODE))) | |
1787 | nops += 2; | |
1788 | else if (pinfo & INSN_COP) | |
1789 | ++nops; | |
1790 | } | |
1791 | } | |
1792 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1793 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1794 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1795 | && ! cop_interlocks) | |
1796 | { | |
1797 | /* The previous instruction sets the coprocessor condition | |
1798 | codes, but does not require a general coprocessor delay | |
1799 | (this means it is a floating point comparison | |
1800 | instruction). If this instruction uses the condition | |
1801 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1802 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1803 | if (mips_optimize == 0 |
1804 | || (pinfo & INSN_READ_COND_CODE)) | |
1805 | ++nops; | |
1806 | } | |
6b76fefe CM |
1807 | |
1808 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1809 | previous insn was an mfhi/mflo and the current insn | |
1810 | reads the register that the mfhi/mflo wrote to, then | |
1811 | insert two nops. */ | |
1812 | ||
1813 | else if (mips_7000_hilo_fix | |
1814 | && MF_HILO_INSN (prev_pinfo) | |
1815 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1816 | & OP_MASK_RD), |
1817 | MIPS_GR_REG)) | |
6b76fefe CM |
1818 | { |
1819 | nops += 2; | |
1820 | } | |
1821 | ||
1822 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1823 | 2nd previous insn was an mfhi/mflo and the current insn | |
1824 | reads the register that the mfhi/mflo wrote to, then | |
1825 | insert one nop. */ | |
1826 | ||
1827 | else if (mips_7000_hilo_fix | |
1828 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1829 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1830 | & OP_MASK_RD), | |
1831 | MIPS_GR_REG)) | |
bdaaa2e1 | 1832 | |
6b76fefe | 1833 | { |
f9419b05 | 1834 | ++nops; |
6b76fefe | 1835 | } |
bdaaa2e1 | 1836 | |
252b5132 RH |
1837 | else if (prev_pinfo & INSN_READ_LO) |
1838 | { | |
1839 | /* The previous instruction reads the LO register; if the | |
1840 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1841 | insert two NOPS. Some newer processors have interlocks. |
1842 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1843 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1844 | though the tx39's divide insns still do require the |
1845 | delay. */ | |
252b5132 | 1846 | if (! (hilo_interlocks |
ec68c924 | 1847 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1848 | && (mips_optimize == 0 |
1849 | || (pinfo & INSN_WRITE_LO))) | |
1850 | nops += 2; | |
1851 | /* Most mips16 branch insns don't have a delay slot. | |
1852 | If a read from LO is immediately followed by a branch | |
1853 | to a write to LO we have a read followed by a write | |
1854 | less than 2 insns away. We assume the target of | |
1855 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1856 | between a read and an immediately following branch. */ |
252b5132 RH |
1857 | else if (mips_opts.mips16 |
1858 | && (mips_optimize == 0 | |
1859 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1860 | ++nops; |
252b5132 RH |
1861 | } |
1862 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1863 | { | |
1864 | /* The previous instruction reads the HI register; if the | |
1865 | current instruction writes to the HI register, we must | |
1866 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1867 | Also the note tx39's multiply above. */ |
252b5132 | 1868 | if (! (hilo_interlocks |
ec68c924 | 1869 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1870 | && (mips_optimize == 0 |
1871 | || (pinfo & INSN_WRITE_HI))) | |
1872 | nops += 2; | |
1873 | /* Most mips16 branch insns don't have a delay slot. | |
1874 | If a read from HI is immediately followed by a branch | |
1875 | to a write to HI we have a read followed by a write | |
1876 | less than 2 insns away. We assume the target of | |
1877 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1878 | between a read and an immediately following branch. */ |
252b5132 RH |
1879 | else if (mips_opts.mips16 |
1880 | && (mips_optimize == 0 | |
1881 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1882 | ++nops; |
252b5132 RH |
1883 | } |
1884 | ||
1885 | /* If the previous instruction was in a noreorder section, then | |
1886 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1887 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1888 | if (prev_insn_unreordered) |
1889 | nops = 0; | |
1890 | ||
1891 | /* There are two cases which require two intervening | |
1892 | instructions: 1) setting the condition codes using a move to | |
1893 | coprocessor instruction which requires a general coprocessor | |
1894 | delay and then reading the condition codes 2) reading the HI | |
1895 | or LO register and then writing to it (except on processors | |
1896 | which have interlocks). If we are not already emitting a NOP | |
1897 | instruction, we must check for these cases compared to the | |
1898 | instruction previous to the previous instruction. */ | |
1899 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1900 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1901 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1902 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1903 | && (pinfo & INSN_READ_COND_CODE) | |
1904 | && ! cop_interlocks) | |
1905 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1906 | && (pinfo & INSN_WRITE_LO) | |
1907 | && ! (hilo_interlocks | |
ec68c924 | 1908 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1909 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1910 | && (pinfo & INSN_WRITE_HI) | |
1911 | && ! (hilo_interlocks | |
ec68c924 | 1912 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1913 | prev_prev_nop = 1; |
1914 | else | |
1915 | prev_prev_nop = 0; | |
1916 | ||
1917 | if (prev_prev_insn_unreordered) | |
1918 | prev_prev_nop = 0; | |
1919 | ||
1920 | if (prev_prev_nop && nops == 0) | |
1921 | ++nops; | |
1922 | ||
1923 | /* If we are being given a nop instruction, don't bother with | |
1924 | one of the nops we would otherwise output. This will only | |
1925 | happen when a nop instruction is used with mips_optimize set | |
1926 | to 0. */ | |
1927 | if (nops > 0 | |
1928 | && ! mips_opts.noreorder | |
156c2f8b | 1929 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1930 | --nops; |
1931 | ||
1932 | /* Now emit the right number of NOP instructions. */ | |
1933 | if (nops > 0 && ! mips_opts.noreorder) | |
1934 | { | |
1935 | fragS *old_frag; | |
1936 | unsigned long old_frag_offset; | |
1937 | int i; | |
1938 | struct insn_label_list *l; | |
1939 | ||
1940 | old_frag = frag_now; | |
1941 | old_frag_offset = frag_now_fix (); | |
1942 | ||
1943 | for (i = 0; i < nops; i++) | |
1944 | emit_nop (); | |
1945 | ||
1946 | if (listing) | |
1947 | { | |
1948 | listing_prev_line (); | |
1949 | /* We may be at the start of a variant frag. In case we | |
1950 | are, make sure there is enough space for the frag | |
1951 | after the frags created by listing_prev_line. The | |
1952 | argument to frag_grow here must be at least as large | |
1953 | as the argument to all other calls to frag_grow in | |
1954 | this file. We don't have to worry about being in the | |
1955 | middle of a variant frag, because the variants insert | |
1956 | all needed nop instructions themselves. */ | |
1957 | frag_grow (40); | |
1958 | } | |
1959 | ||
1960 | for (l = insn_labels; l != NULL; l = l->next) | |
1961 | { | |
98aa84af AM |
1962 | valueT val; |
1963 | ||
252b5132 | 1964 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1965 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1966 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1967 | /* mips16 text labels are stored as odd. */ |
1968 | if (mips_opts.mips16) | |
f9419b05 | 1969 | ++val; |
98aa84af | 1970 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1971 | } |
1972 | ||
1973 | #ifndef NO_ECOFF_DEBUGGING | |
1974 | if (ECOFF_DEBUGGING) | |
1975 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1976 | #endif | |
1977 | } | |
1978 | else if (prev_nop_frag != NULL) | |
1979 | { | |
1980 | /* We have a frag holding nops we may be able to remove. If | |
1981 | we don't need any nops, we can decrease the size of | |
1982 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1983 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1984 | if (prev_nop_frag_since == 0) |
1985 | { | |
1986 | if (nops == 0) | |
1987 | { | |
1988 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1989 | --prev_nop_frag_holds; | |
1990 | } | |
1991 | else | |
1992 | prev_nop_frag_required += nops; | |
1993 | } | |
1994 | else | |
1995 | { | |
1996 | if (prev_prev_nop == 0) | |
1997 | { | |
1998 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1999 | --prev_nop_frag_holds; | |
2000 | } | |
2001 | else | |
2002 | ++prev_nop_frag_required; | |
2003 | } | |
2004 | ||
2005 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2006 | prev_nop_frag = NULL; | |
2007 | ||
2008 | ++prev_nop_frag_since; | |
2009 | ||
2010 | /* Sanity check: by the time we reach the second instruction | |
2011 | after prev_nop_frag, we should have used up all the nops | |
2012 | one way or another. */ | |
2013 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2014 | } | |
2015 | } | |
2016 | ||
f6688943 | 2017 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
2018 | { |
2019 | /* We need to set up a variant frag. */ | |
2020 | assert (mips_opts.mips16 && address_expr != NULL); | |
2021 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2022 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2023 | mips16_small, mips16_ext, |
2024 | (prev_pinfo | |
2025 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2026 | (*prev_insn_reloc_type |
252b5132 | 2027 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2028 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2029 | } |
2030 | else if (place != NULL) | |
2031 | f = place; | |
2032 | else if (mips_opts.mips16 | |
2033 | && ! ip->use_extend | |
f6688943 | 2034 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2035 | { |
2036 | /* Make sure there is enough room to swap this instruction with | |
2037 | a following jump instruction. */ | |
2038 | frag_grow (6); | |
2039 | f = frag_more (2); | |
2040 | } | |
2041 | else | |
2042 | { | |
2043 | if (mips_opts.mips16 | |
2044 | && mips_opts.noreorder | |
2045 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2046 | as_warn (_("extended instruction in delay slot")); | |
2047 | ||
2048 | f = frag_more (4); | |
2049 | } | |
2050 | ||
f6688943 TS |
2051 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2052 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2053 | { |
2054 | if (address_expr->X_op == O_constant) | |
2055 | { | |
4db1a35d | 2056 | valueT tmp; |
f6688943 TS |
2057 | |
2058 | switch (*reloc_type) | |
252b5132 RH |
2059 | { |
2060 | case BFD_RELOC_32: | |
2061 | ip->insn_opcode |= address_expr->X_add_number; | |
2062 | break; | |
2063 | ||
f6688943 TS |
2064 | case BFD_RELOC_MIPS_HIGHEST: |
2065 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2066 | tmp >>= 16; | |
2067 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2068 | break; | |
2069 | ||
2070 | case BFD_RELOC_MIPS_HIGHER: | |
2071 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2072 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2073 | break; | |
2074 | ||
2075 | case BFD_RELOC_HI16_S: | |
2076 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2077 | >> 16) & 0xffff; | |
2078 | break; | |
2079 | ||
2080 | case BFD_RELOC_HI16: | |
2081 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2082 | break; | |
2083 | ||
252b5132 RH |
2084 | case BFD_RELOC_LO16: |
2085 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
2086 | break; | |
2087 | ||
2088 | case BFD_RELOC_MIPS_JMP: | |
2089 | if ((address_expr->X_add_number & 3) != 0) | |
2090 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2091 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2092 | if (address_expr->X_add_number & ~0xfffffff |
2093 | || address_expr->X_add_number > 0x7fffffc) | |
2094 | as_bad (_("jump address range overflow (0x%lx)"), | |
2095 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2096 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2097 | break; | |
2098 | ||
2099 | case BFD_RELOC_MIPS16_JMP: | |
2100 | if ((address_expr->X_add_number & 3) != 0) | |
2101 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2102 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2103 | if (address_expr->X_add_number & ~0xfffffff |
2104 | || address_expr->X_add_number > 0x7fffffc) | |
2105 | as_bad (_("jump address range overflow (0x%lx)"), | |
2106 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2107 | ip->insn_opcode |= |
2108 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2109 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2110 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2111 | break; | |
2112 | ||
cb56d3d3 | 2113 | case BFD_RELOC_16_PCREL: |
233b8738 | 2114 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
2115 | break; |
2116 | ||
252b5132 RH |
2117 | case BFD_RELOC_16_PCREL_S2: |
2118 | goto need_reloc; | |
2119 | ||
2120 | default: | |
2121 | internalError (); | |
2122 | } | |
2123 | } | |
2124 | else | |
2125 | { | |
2126 | need_reloc: | |
f6688943 | 2127 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2128 | if (place == NULL) |
2129 | { | |
f6688943 TS |
2130 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2131 | address_expr, | |
2132 | (*reloc_type == BFD_RELOC_16_PCREL | |
2133 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
2134 | reloc_type[0]); | |
2135 | ||
b6ff326e | 2136 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2137 | 4 octets for 64bit assembly. */ |
2138 | if (HAVE_64BIT_GPRS && | |
2139 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
2140 | || *reloc_type == BFD_RELOC_32 |
2141 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2142 | || *reloc_type == BFD_RELOC_HI16_S | |
2143 | || *reloc_type == BFD_RELOC_LO16 | |
2144 | || *reloc_type == BFD_RELOC_GPREL16 | |
2145 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2146 | || *reloc_type == BFD_RELOC_GPREL32 | |
2147 | || *reloc_type == BFD_RELOC_64 | |
2148 | || *reloc_type == BFD_RELOC_CTOR | |
2149 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2150 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2151 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2152 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2153 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2154 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2155 | fixp[0]->fx_no_overflow = 1; |
2156 | ||
252b5132 RH |
2157 | if (unmatched_hi) |
2158 | { | |
2159 | struct mips_hi_fixup *hi_fixup; | |
2160 | ||
f6688943 | 2161 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2162 | hi_fixup = ((struct mips_hi_fixup *) |
2163 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2164 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2165 | hi_fixup->seg = now_seg; |
2166 | hi_fixup->next = mips_hi_fixup_list; | |
2167 | mips_hi_fixup_list = hi_fixup; | |
2168 | } | |
f6688943 TS |
2169 | |
2170 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2171 | { | |
2172 | /* FIXME: This symbol can be one of | |
2173 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2174 | address_expr->X_op = O_absent; | |
2175 | address_expr->X_add_symbol = 0; | |
2176 | address_expr->X_add_number = 0; | |
2177 | ||
2178 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2179 | 4, address_expr, false, | |
2180 | reloc_type[1]); | |
2181 | ||
b6ff326e | 2182 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2183 | 4 octets for 64bit assembly. */ |
2184 | if (HAVE_64BIT_GPRS && | |
2185 | (*reloc_type == BFD_RELOC_16 | |
2186 | || *reloc_type == BFD_RELOC_32 | |
2187 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2188 | || *reloc_type == BFD_RELOC_HI16_S | |
2189 | || *reloc_type == BFD_RELOC_LO16 | |
2190 | || *reloc_type == BFD_RELOC_GPREL16 | |
2191 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2192 | || *reloc_type == BFD_RELOC_GPREL32 | |
2193 | || *reloc_type == BFD_RELOC_64 | |
2194 | || *reloc_type == BFD_RELOC_CTOR | |
2195 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2196 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2197 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2198 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2199 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2200 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2201 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
2202 | |
2203 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2204 | { | |
2205 | address_expr->X_op = O_absent; | |
2206 | address_expr->X_add_symbol = 0; | |
2207 | address_expr->X_add_number = 0; | |
2208 | ||
2209 | fixp[2] = fix_new_exp (frag_now, | |
2210 | f - frag_now->fr_literal, 4, | |
2211 | address_expr, false, | |
2212 | reloc_type[2]); | |
2213 | ||
b6ff326e | 2214 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2215 | 4 octets for 64bit assembly. */ |
2216 | if (HAVE_64BIT_GPRS && | |
2217 | (*reloc_type == BFD_RELOC_16 | |
2218 | || *reloc_type == BFD_RELOC_32 | |
2219 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2220 | || *reloc_type == BFD_RELOC_HI16_S | |
2221 | || *reloc_type == BFD_RELOC_LO16 | |
2222 | || *reloc_type == BFD_RELOC_GPREL16 | |
2223 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2224 | || *reloc_type == BFD_RELOC_GPREL32 | |
2225 | || *reloc_type == BFD_RELOC_64 | |
2226 | || *reloc_type == BFD_RELOC_CTOR | |
2227 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2228 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2229 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2230 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2231 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2232 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2233 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2234 | } |
2235 | } | |
252b5132 RH |
2236 | } |
2237 | } | |
2238 | } | |
2239 | ||
2240 | if (! mips_opts.mips16) | |
2241 | md_number_to_chars (f, ip->insn_opcode, 4); | |
f6688943 | 2242 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2243 | { |
2244 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2245 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2246 | } | |
2247 | else | |
2248 | { | |
2249 | if (ip->use_extend) | |
2250 | { | |
2251 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2252 | f += 2; | |
2253 | } | |
2254 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2255 | } | |
2256 | ||
2257 | /* Update the register mask information. */ | |
2258 | if (! mips_opts.mips16) | |
2259 | { | |
2260 | if (pinfo & INSN_WRITE_GPR_D) | |
2261 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2262 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2263 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2264 | if (pinfo & INSN_READ_GPR_S) | |
2265 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2266 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2267 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2268 | if (pinfo & INSN_WRITE_FPR_D) |
2269 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2270 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2271 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2272 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2273 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2274 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2275 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2276 | if (pinfo & INSN_COP) | |
2277 | { | |
bdaaa2e1 KH |
2278 | /* We don't keep enough information to sort these cases out. |
2279 | The itbl support does keep this information however, although | |
2280 | we currently don't support itbl fprmats as part of the cop | |
2281 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2282 | } |
2283 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2284 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2285 | } |
2286 | else | |
2287 | { | |
2288 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2289 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2290 | & MIPS16OP_MASK_RX); | |
2291 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2292 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2293 | & MIPS16OP_MASK_RY); | |
2294 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2295 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2296 | & MIPS16OP_MASK_RZ); | |
2297 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2298 | mips_gprmask |= 1 << TREG; | |
2299 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2300 | mips_gprmask |= 1 << SP; | |
2301 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2302 | mips_gprmask |= 1 << RA; | |
2303 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2304 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2305 | if (pinfo & MIPS16_INSN_READ_Z) | |
2306 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2307 | & MIPS16OP_MASK_MOVE32Z); | |
2308 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2309 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2310 | & MIPS16OP_MASK_REGR32); | |
2311 | } | |
2312 | ||
2313 | if (place == NULL && ! mips_opts.noreorder) | |
2314 | { | |
2315 | /* Filling the branch delay slot is more complex. We try to | |
2316 | switch the branch with the previous instruction, which we can | |
2317 | do if the previous instruction does not set up a condition | |
2318 | that the branch tests and if the branch is not itself the | |
2319 | target of any branch. */ | |
2320 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2321 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2322 | { | |
2323 | if (mips_optimize < 2 | |
2324 | /* If we have seen .set volatile or .set nomove, don't | |
2325 | optimize. */ | |
2326 | || mips_opts.nomove != 0 | |
2327 | /* If we had to emit any NOP instructions, then we | |
2328 | already know we can not swap. */ | |
2329 | || nops != 0 | |
2330 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2331 | swap. */ |
252b5132 RH |
2332 | || ! prev_insn_valid |
2333 | /* If the previous insn is already in a branch delay | |
2334 | slot, then we can not swap. */ | |
2335 | || prev_insn_is_delay_slot | |
2336 | /* If the previous previous insn was in a .set | |
2337 | noreorder, we can't swap. Actually, the MIPS | |
2338 | assembler will swap in this situation. However, gcc | |
2339 | configured -with-gnu-as will generate code like | |
2340 | .set noreorder | |
2341 | lw $4,XXX | |
2342 | .set reorder | |
2343 | INSN | |
2344 | bne $4,$0,foo | |
2345 | in which we can not swap the bne and INSN. If gcc is | |
2346 | not configured -with-gnu-as, it does not output the | |
2347 | .set pseudo-ops. We don't have to check | |
2348 | prev_insn_unreordered, because prev_insn_valid will | |
2349 | be 0 in that case. We don't want to use | |
2350 | prev_prev_insn_valid, because we do want to be able | |
2351 | to swap at the start of a function. */ | |
2352 | || prev_prev_insn_unreordered | |
2353 | /* If the branch is itself the target of a branch, we | |
2354 | can not swap. We cheat on this; all we check for is | |
2355 | whether there is a label on this instruction. If | |
2356 | there are any branches to anything other than a | |
2357 | label, users must use .set noreorder. */ | |
2358 | || insn_labels != NULL | |
2359 | /* If the previous instruction is in a variant frag, we | |
2360 | can not do the swap. This does not apply to the | |
2361 | mips16, which uses variant frags for different | |
2362 | purposes. */ | |
2363 | || (! mips_opts.mips16 | |
2364 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2365 | /* If the branch reads the condition codes, we don't | |
2366 | even try to swap, because in the sequence | |
2367 | ctc1 $X,$31 | |
2368 | INSN | |
2369 | INSN | |
2370 | bc1t LABEL | |
2371 | we can not swap, and I don't feel like handling that | |
2372 | case. */ | |
2373 | || (! mips_opts.mips16 | |
9ce8a5dd | 2374 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2375 | && (pinfo & INSN_READ_COND_CODE)) |
2376 | /* We can not swap with an instruction that requires a | |
2377 | delay slot, becase the target of the branch might | |
2378 | interfere with that instruction. */ | |
2379 | || (! mips_opts.mips16 | |
9ce8a5dd | 2380 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2381 | && (prev_pinfo |
bdaaa2e1 | 2382 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2383 | & (INSN_LOAD_COPROC_DELAY |
2384 | | INSN_COPROC_MOVE_DELAY | |
2385 | | INSN_WRITE_COND_CODE))) | |
2386 | || (! (hilo_interlocks | |
ec68c924 | 2387 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2388 | && (prev_pinfo |
2389 | & (INSN_READ_LO | |
2390 | | INSN_READ_HI))) | |
2391 | || (! mips_opts.mips16 | |
2392 | && ! gpr_interlocks | |
2393 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2394 | || (! mips_opts.mips16 | |
e7af610e | 2395 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2396 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2397 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2398 | /* We can not swap with a branch instruction. */ | |
2399 | || (prev_pinfo | |
2400 | & (INSN_UNCOND_BRANCH_DELAY | |
2401 | | INSN_COND_BRANCH_DELAY | |
2402 | | INSN_COND_BRANCH_LIKELY)) | |
2403 | /* We do not swap with a trap instruction, since it | |
2404 | complicates trap handlers to have the trap | |
2405 | instruction be in a delay slot. */ | |
2406 | || (prev_pinfo & INSN_TRAP) | |
2407 | /* If the branch reads a register that the previous | |
2408 | instruction sets, we can not swap. */ | |
2409 | || (! mips_opts.mips16 | |
2410 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2411 | && insn_uses_reg (ip, | |
2412 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2413 | & OP_MASK_RT), | |
2414 | MIPS_GR_REG)) | |
2415 | || (! mips_opts.mips16 | |
2416 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2417 | && insn_uses_reg (ip, | |
2418 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2419 | & OP_MASK_RD), | |
2420 | MIPS_GR_REG)) | |
2421 | || (mips_opts.mips16 | |
2422 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2423 | && insn_uses_reg (ip, | |
2424 | ((prev_insn.insn_opcode | |
2425 | >> MIPS16OP_SH_RX) | |
2426 | & MIPS16OP_MASK_RX), | |
2427 | MIPS16_REG)) | |
2428 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2429 | && insn_uses_reg (ip, | |
2430 | ((prev_insn.insn_opcode | |
2431 | >> MIPS16OP_SH_RY) | |
2432 | & MIPS16OP_MASK_RY), | |
2433 | MIPS16_REG)) | |
2434 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2435 | && insn_uses_reg (ip, | |
2436 | ((prev_insn.insn_opcode | |
2437 | >> MIPS16OP_SH_RZ) | |
2438 | & MIPS16OP_MASK_RZ), | |
2439 | MIPS16_REG)) | |
2440 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2441 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2442 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2443 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2444 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2445 | && insn_uses_reg (ip, | |
2446 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2447 | insn_opcode), | |
2448 | MIPS_GR_REG)))) | |
2449 | /* If the branch writes a register that the previous | |
2450 | instruction sets, we can not swap (we know that | |
2451 | branches write only to RD or to $31). */ | |
2452 | || (! mips_opts.mips16 | |
2453 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2454 | && (((pinfo & INSN_WRITE_GPR_D) | |
2455 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2456 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2457 | || ((pinfo & INSN_WRITE_GPR_31) | |
2458 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2459 | & OP_MASK_RT) | |
f9419b05 | 2460 | == RA)))) |
252b5132 RH |
2461 | || (! mips_opts.mips16 |
2462 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2463 | && (((pinfo & INSN_WRITE_GPR_D) | |
2464 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2465 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2466 | || ((pinfo & INSN_WRITE_GPR_31) | |
2467 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2468 | & OP_MASK_RD) | |
f9419b05 | 2469 | == RA)))) |
252b5132 RH |
2470 | || (mips_opts.mips16 |
2471 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2472 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2473 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2474 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2475 | == RA)))) | |
2476 | /* If the branch writes a register that the previous | |
2477 | instruction reads, we can not swap (we know that | |
2478 | branches only write to RD or to $31). */ | |
2479 | || (! mips_opts.mips16 | |
2480 | && (pinfo & INSN_WRITE_GPR_D) | |
2481 | && insn_uses_reg (&prev_insn, | |
2482 | ((ip->insn_opcode >> OP_SH_RD) | |
2483 | & OP_MASK_RD), | |
2484 | MIPS_GR_REG)) | |
2485 | || (! mips_opts.mips16 | |
2486 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2487 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2488 | || (mips_opts.mips16 |
2489 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2490 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2491 | /* If we are generating embedded PIC code, the branch | |
2492 | might be expanded into a sequence which uses $at, so | |
2493 | we can't swap with an instruction which reads it. */ | |
2494 | || (mips_pic == EMBEDDED_PIC | |
2495 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2496 | /* If the previous previous instruction has a load | |
2497 | delay, and sets a register that the branch reads, we | |
2498 | can not swap. */ | |
2499 | || (! mips_opts.mips16 | |
9ce8a5dd | 2500 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2501 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2502 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2503 | || (! gpr_interlocks | |
2504 | && (prev_prev_insn.insn_mo->pinfo | |
2505 | & INSN_LOAD_MEMORY_DELAY))) | |
2506 | && insn_uses_reg (ip, | |
2507 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2508 | & OP_MASK_RT), | |
2509 | MIPS_GR_REG)) | |
2510 | /* If one instruction sets a condition code and the | |
2511 | other one uses a condition code, we can not swap. */ | |
2512 | || ((pinfo & INSN_READ_COND_CODE) | |
2513 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2514 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2515 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2516 | /* If the previous instruction uses the PC, we can not | |
2517 | swap. */ | |
2518 | || (mips_opts.mips16 | |
2519 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2520 | /* If the previous instruction was extended, we can not | |
2521 | swap. */ | |
2522 | || (mips_opts.mips16 && prev_insn_extended) | |
2523 | /* If the previous instruction had a fixup in mips16 | |
2524 | mode, we can not swap. This normally means that the | |
2525 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2526 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2527 | /* If the previous instruction is a sync, sync.l, or |
2528 | sync.p, we can not swap. */ | |
f173e82e | 2529 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2530 | { |
2531 | /* We could do even better for unconditional branches to | |
2532 | portions of this object file; we could pick up the | |
2533 | instruction at the destination, put it in the delay | |
2534 | slot, and bump the destination address. */ | |
2535 | emit_nop (); | |
2536 | /* Update the previous insn information. */ | |
2537 | prev_prev_insn = *ip; | |
2538 | prev_insn.insn_mo = &dummy_opcode; | |
2539 | } | |
2540 | else | |
2541 | { | |
2542 | /* It looks like we can actually do the swap. */ | |
2543 | if (! mips_opts.mips16) | |
2544 | { | |
2545 | char *prev_f; | |
2546 | char temp[4]; | |
2547 | ||
2548 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2549 | memcpy (temp, prev_f, 4); | |
2550 | memcpy (prev_f, f, 4); | |
2551 | memcpy (f, temp, 4); | |
f6688943 TS |
2552 | if (prev_insn_fixp[0]) |
2553 | { | |
2554 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2555 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2556 | } | |
2557 | if (prev_insn_fixp[1]) | |
2558 | { | |
2559 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2560 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2561 | } | |
2562 | if (prev_insn_fixp[2]) | |
252b5132 | 2563 | { |
f6688943 TS |
2564 | prev_insn_fixp[2]->fx_frag = frag_now; |
2565 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2566 | } |
f6688943 | 2567 | if (fixp[0]) |
252b5132 | 2568 | { |
f6688943 TS |
2569 | fixp[0]->fx_frag = prev_insn_frag; |
2570 | fixp[0]->fx_where = prev_insn_where; | |
2571 | } | |
2572 | if (fixp[1]) | |
2573 | { | |
2574 | fixp[1]->fx_frag = prev_insn_frag; | |
2575 | fixp[1]->fx_where = prev_insn_where; | |
2576 | } | |
2577 | if (fixp[2]) | |
2578 | { | |
2579 | fixp[2]->fx_frag = prev_insn_frag; | |
2580 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2581 | } |
2582 | } | |
2583 | else | |
2584 | { | |
2585 | char *prev_f; | |
2586 | char temp[2]; | |
2587 | ||
f6688943 TS |
2588 | assert (prev_insn_fixp[0] == NULL); |
2589 | assert (prev_insn_fixp[1] == NULL); | |
2590 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2591 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2592 | memcpy (temp, prev_f, 2); | |
2593 | memcpy (prev_f, f, 2); | |
f6688943 | 2594 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2595 | { |
f6688943 | 2596 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2597 | memcpy (f, temp, 2); |
2598 | } | |
2599 | else | |
2600 | { | |
2601 | memcpy (f, f + 2, 2); | |
2602 | memcpy (f + 2, temp, 2); | |
2603 | } | |
f6688943 TS |
2604 | if (fixp[0]) |
2605 | { | |
2606 | fixp[0]->fx_frag = prev_insn_frag; | |
2607 | fixp[0]->fx_where = prev_insn_where; | |
2608 | } | |
2609 | if (fixp[1]) | |
2610 | { | |
2611 | fixp[1]->fx_frag = prev_insn_frag; | |
2612 | fixp[1]->fx_where = prev_insn_where; | |
2613 | } | |
2614 | if (fixp[2]) | |
252b5132 | 2615 | { |
f6688943 TS |
2616 | fixp[2]->fx_frag = prev_insn_frag; |
2617 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2618 | } |
2619 | } | |
2620 | ||
2621 | /* Update the previous insn information; leave prev_insn | |
2622 | unchanged. */ | |
2623 | prev_prev_insn = *ip; | |
2624 | } | |
2625 | prev_insn_is_delay_slot = 1; | |
2626 | ||
2627 | /* If that was an unconditional branch, forget the previous | |
2628 | insn information. */ | |
2629 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2630 | { | |
2631 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2632 | prev_insn.insn_mo = &dummy_opcode; | |
2633 | } | |
2634 | ||
f6688943 TS |
2635 | prev_insn_fixp[0] = NULL; |
2636 | prev_insn_fixp[1] = NULL; | |
2637 | prev_insn_fixp[2] = NULL; | |
2638 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2639 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2640 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2641 | prev_insn_extended = 0; |
2642 | } | |
2643 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2644 | { | |
2645 | /* We don't yet optimize a branch likely. What we should do | |
2646 | is look at the target, copy the instruction found there | |
2647 | into the delay slot, and increment the branch to jump to | |
2648 | the next instruction. */ | |
2649 | emit_nop (); | |
2650 | /* Update the previous insn information. */ | |
2651 | prev_prev_insn = *ip; | |
2652 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2653 | prev_insn_fixp[0] = NULL; |
2654 | prev_insn_fixp[1] = NULL; | |
2655 | prev_insn_fixp[2] = NULL; | |
2656 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2657 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2658 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2659 | prev_insn_extended = 0; |
2660 | } | |
2661 | else | |
2662 | { | |
2663 | /* Update the previous insn information. */ | |
2664 | if (nops > 0) | |
2665 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2666 | else | |
2667 | prev_prev_insn = prev_insn; | |
2668 | prev_insn = *ip; | |
2669 | ||
2670 | /* Any time we see a branch, we always fill the delay slot | |
2671 | immediately; since this insn is not a branch, we know it | |
2672 | is not in a delay slot. */ | |
2673 | prev_insn_is_delay_slot = 0; | |
2674 | ||
f6688943 TS |
2675 | prev_insn_fixp[0] = fixp[0]; |
2676 | prev_insn_fixp[1] = fixp[1]; | |
2677 | prev_insn_fixp[2] = fixp[2]; | |
2678 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2679 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2680 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2681 | if (mips_opts.mips16) |
2682 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2683 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2684 | } |
2685 | ||
2686 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2687 | prev_insn_unreordered = 0; | |
2688 | prev_insn_frag = frag_now; | |
2689 | prev_insn_where = f - frag_now->fr_literal; | |
2690 | prev_insn_valid = 1; | |
2691 | } | |
2692 | else if (place == NULL) | |
2693 | { | |
2694 | /* We need to record a bit of information even when we are not | |
2695 | reordering, in order to determine the base address for mips16 | |
2696 | PC relative relocs. */ | |
2697 | prev_prev_insn = prev_insn; | |
2698 | prev_insn = *ip; | |
f6688943 TS |
2699 | prev_insn_reloc_type[0] = reloc_type[0]; |
2700 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2701 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2702 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2703 | prev_insn_unreordered = 1; | |
2704 | } | |
2705 | ||
2706 | /* We just output an insn, so the next one doesn't have a label. */ | |
2707 | mips_clear_insn_labels (); | |
2708 | ||
2709 | /* We must ensure that a fixup associated with an unmatched %hi | |
2710 | reloc does not become a variant frag. Otherwise, the | |
2711 | rearrangement of %hi relocs in frob_file may confuse | |
2712 | tc_gen_reloc. */ | |
2713 | if (unmatched_hi) | |
2714 | { | |
2715 | frag_wane (frag_now); | |
2716 | frag_new (0); | |
2717 | } | |
2718 | } | |
2719 | ||
2720 | /* This function forgets that there was any previous instruction or | |
2721 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2722 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2723 | |
2724 | static void | |
2725 | mips_no_prev_insn (preserve) | |
2726 | int preserve; | |
2727 | { | |
2728 | if (! preserve) | |
2729 | { | |
2730 | prev_insn.insn_mo = &dummy_opcode; | |
2731 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2732 | prev_nop_frag = NULL; | |
2733 | prev_nop_frag_holds = 0; | |
2734 | prev_nop_frag_required = 0; | |
2735 | prev_nop_frag_since = 0; | |
2736 | } | |
2737 | prev_insn_valid = 0; | |
2738 | prev_insn_is_delay_slot = 0; | |
2739 | prev_insn_unreordered = 0; | |
2740 | prev_insn_extended = 0; | |
f6688943 TS |
2741 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2742 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2743 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2744 | prev_prev_insn_unreordered = 0; |
2745 | mips_clear_insn_labels (); | |
2746 | } | |
2747 | ||
2748 | /* This function must be called whenever we turn on noreorder or emit | |
2749 | something other than instructions. It inserts any NOPS which might | |
2750 | be needed by the previous instruction, and clears the information | |
2751 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2752 | instructions are to follow. */ |
252b5132 RH |
2753 | |
2754 | static void | |
2755 | mips_emit_delays (insns) | |
2756 | boolean insns; | |
2757 | { | |
2758 | if (! mips_opts.noreorder) | |
2759 | { | |
2760 | int nops; | |
2761 | ||
2762 | nops = 0; | |
2763 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2764 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2765 | && (! cop_interlocks |
2766 | && (prev_insn.insn_mo->pinfo | |
2767 | & (INSN_LOAD_COPROC_DELAY | |
2768 | | INSN_COPROC_MOVE_DELAY | |
2769 | | INSN_WRITE_COND_CODE)))) | |
2770 | || (! hilo_interlocks | |
2771 | && (prev_insn.insn_mo->pinfo | |
2772 | & (INSN_READ_LO | |
2773 | | INSN_READ_HI))) | |
2774 | || (! mips_opts.mips16 | |
2775 | && ! gpr_interlocks | |
bdaaa2e1 | 2776 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2777 | & INSN_LOAD_MEMORY_DELAY)) |
2778 | || (! mips_opts.mips16 | |
e7af610e | 2779 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2780 | && (prev_insn.insn_mo->pinfo |
2781 | & INSN_COPROC_MEMORY_DELAY))) | |
2782 | { | |
beae10d5 | 2783 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2784 | ++nops; |
2785 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2786 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2787 | && (! cop_interlocks |
2788 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2789 | || (! hilo_interlocks | |
2790 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2791 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2792 | ++nops; | |
2793 | ||
2794 | if (prev_insn_unreordered) | |
2795 | nops = 0; | |
2796 | } | |
2797 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2798 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2799 | && (! cop_interlocks |
2800 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2801 | || (! hilo_interlocks | |
2802 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2803 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2804 | { | |
beae10d5 | 2805 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2806 | if (! prev_prev_insn_unreordered) |
2807 | ++nops; | |
2808 | } | |
2809 | ||
2810 | if (nops > 0) | |
2811 | { | |
2812 | struct insn_label_list *l; | |
2813 | ||
2814 | if (insns) | |
2815 | { | |
2816 | /* Record the frag which holds the nop instructions, so | |
2817 | that we can remove them if we don't need them. */ | |
2818 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2819 | prev_nop_frag = frag_now; | |
2820 | prev_nop_frag_holds = nops; | |
2821 | prev_nop_frag_required = 0; | |
2822 | prev_nop_frag_since = 0; | |
2823 | } | |
2824 | ||
2825 | for (; nops > 0; --nops) | |
2826 | emit_nop (); | |
2827 | ||
2828 | if (insns) | |
2829 | { | |
2830 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2831 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2832 | frag_wane (frag_now); |
2833 | frag_new (0); | |
2834 | } | |
2835 | ||
2836 | for (l = insn_labels; l != NULL; l = l->next) | |
2837 | { | |
98aa84af AM |
2838 | valueT val; |
2839 | ||
252b5132 | 2840 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2841 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2842 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2843 | /* mips16 text labels are stored as odd. */ |
2844 | if (mips_opts.mips16) | |
f9419b05 | 2845 | ++val; |
98aa84af | 2846 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2847 | } |
2848 | } | |
2849 | } | |
2850 | ||
2851 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2852 | if (insns) |
252b5132 RH |
2853 | mips16_mark_labels (); |
2854 | ||
2855 | mips_no_prev_insn (insns); | |
2856 | } | |
2857 | ||
2858 | /* Build an instruction created by a macro expansion. This is passed | |
2859 | a pointer to the count of instructions created so far, an | |
2860 | expression, the name of the instruction to build, an operand format | |
2861 | string, and corresponding arguments. */ | |
2862 | ||
2863 | #ifdef USE_STDARG | |
2864 | static void | |
2865 | macro_build (char *place, | |
2866 | int *counter, | |
2867 | expressionS * ep, | |
2868 | const char *name, | |
2869 | const char *fmt, | |
2870 | ...) | |
2871 | #else | |
2872 | static void | |
2873 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2874 | char *place; | |
2875 | int *counter; | |
2876 | expressionS *ep; | |
2877 | const char *name; | |
2878 | const char *fmt; | |
2879 | va_dcl | |
2880 | #endif | |
2881 | { | |
2882 | struct mips_cl_insn insn; | |
f6688943 | 2883 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2884 | va_list args; |
252b5132 RH |
2885 | |
2886 | #ifdef USE_STDARG | |
2887 | va_start (args, fmt); | |
2888 | #else | |
2889 | va_start (args); | |
2890 | #endif | |
2891 | ||
2892 | /* | |
2893 | * If the macro is about to expand into a second instruction, | |
2894 | * print a warning if needed. We need to pass ip as a parameter | |
2895 | * to generate a better warning message here... | |
2896 | */ | |
2897 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2898 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2899 | ||
80cc45a5 EC |
2900 | /* |
2901 | * If the macro is about to expand into a second instruction, | |
2902 | * and it is in a delay slot, print a warning. | |
2903 | */ | |
2904 | if (place == NULL | |
2905 | && *counter == 1 | |
2906 | && mips_opts.noreorder | |
2907 | && (prev_prev_insn.insn_mo->pinfo | |
2908 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2909 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2910 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2911 | ||
252b5132 | 2912 | if (place == NULL) |
f9419b05 | 2913 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2914 | |
2915 | if (mips_opts.mips16) | |
2916 | { | |
2917 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2918 | va_end (args); | |
2919 | return; | |
2920 | } | |
2921 | ||
f6688943 TS |
2922 | r[0] = BFD_RELOC_UNUSED; |
2923 | r[1] = BFD_RELOC_UNUSED; | |
2924 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2925 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2926 | assert (insn.insn_mo); | |
2927 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2928 | ||
2929 | /* Search until we get a match for NAME. */ | |
2930 | while (1) | |
2931 | { | |
deec1734 CD |
2932 | /* It is assumed here that macros will never generate |
2933 | MDMX or MIPS-3D instructions. */ | |
252b5132 RH |
2934 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2935 | && insn.insn_mo->pinfo != INSN_MACRO | |
af55c2e6 | 2936 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2937 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2938 | break; |
2939 | ||
2940 | ++insn.insn_mo; | |
2941 | assert (insn.insn_mo->name); | |
2942 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2943 | } | |
2944 | ||
2945 | insn.insn_opcode = insn.insn_mo->match; | |
2946 | for (;;) | |
2947 | { | |
2948 | switch (*fmt++) | |
2949 | { | |
2950 | case '\0': | |
2951 | break; | |
2952 | ||
2953 | case ',': | |
2954 | case '(': | |
2955 | case ')': | |
2956 | continue; | |
2957 | ||
2958 | case 't': | |
2959 | case 'w': | |
2960 | case 'E': | |
38487616 | 2961 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2962 | continue; |
2963 | ||
2964 | case 'c': | |
38487616 TS |
2965 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2966 | continue; | |
2967 | ||
252b5132 RH |
2968 | case 'T': |
2969 | case 'W': | |
38487616 | 2970 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2971 | continue; |
2972 | ||
2973 | case 'd': | |
2974 | case 'G': | |
38487616 | 2975 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2976 | continue; |
2977 | ||
4372b673 NC |
2978 | case 'U': |
2979 | { | |
2980 | int tmp = va_arg (args, int); | |
2981 | ||
38487616 TS |
2982 | insn.insn_opcode |= tmp << OP_SH_RT; |
2983 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2984 | continue; |
4372b673 NC |
2985 | } |
2986 | ||
252b5132 RH |
2987 | case 'V': |
2988 | case 'S': | |
38487616 | 2989 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2990 | continue; |
2991 | ||
2992 | case 'z': | |
2993 | continue; | |
2994 | ||
2995 | case '<': | |
38487616 | 2996 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2997 | continue; |
2998 | ||
2999 | case 'D': | |
38487616 | 3000 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3001 | continue; |
3002 | ||
3003 | case 'B': | |
38487616 | 3004 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3005 | continue; |
3006 | ||
4372b673 | 3007 | case 'J': |
38487616 | 3008 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3009 | continue; |
3010 | ||
252b5132 | 3011 | case 'q': |
38487616 | 3012 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3013 | continue; |
3014 | ||
3015 | case 'b': | |
3016 | case 's': | |
3017 | case 'r': | |
3018 | case 'v': | |
38487616 | 3019 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3020 | continue; |
3021 | ||
3022 | case 'i': | |
3023 | case 'j': | |
3024 | case 'o': | |
f6688943 | 3025 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3026 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3027 | || *r == BFD_RELOC_MIPS_LITERAL |
3028 | || *r == BFD_RELOC_MIPS_HIGHER | |
3029 | || *r == BFD_RELOC_HI16_S | |
3030 | || *r == BFD_RELOC_LO16 | |
3031 | || *r == BFD_RELOC_MIPS_GOT16 | |
3032 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3033 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3034 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3035 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3036 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3037 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3038 | || (ep->X_op == O_subtract |
f6688943 | 3039 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3040 | continue; |
3041 | ||
3042 | case 'u': | |
f6688943 | 3043 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3044 | assert (ep != NULL |
3045 | && (ep->X_op == O_constant | |
3046 | || (ep->X_op == O_symbol | |
f6688943 TS |
3047 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3048 | || *r == BFD_RELOC_HI16_S | |
3049 | || *r == BFD_RELOC_HI16 | |
3050 | || *r == BFD_RELOC_GPREL16 | |
3051 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3052 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3053 | || (ep->X_op == O_subtract |
f6688943 | 3054 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3055 | continue; |
3056 | ||
3057 | case 'p': | |
3058 | assert (ep != NULL); | |
3059 | /* | |
3060 | * This allows macro() to pass an immediate expression for | |
3061 | * creating short branches without creating a symbol. | |
3062 | * Note that the expression still might come from the assembly | |
3063 | * input, in which case the value is not checked for range nor | |
3064 | * is a relocation entry generated (yuck). | |
3065 | */ | |
3066 | if (ep->X_op == O_constant) | |
3067 | { | |
3068 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3069 | ep = NULL; | |
3070 | } | |
3071 | else | |
cb56d3d3 | 3072 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 3073 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 3074 | else |
f6688943 | 3075 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
3076 | continue; |
3077 | ||
3078 | case 'a': | |
3079 | assert (ep != NULL); | |
f6688943 | 3080 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3081 | continue; |
3082 | ||
3083 | case 'C': | |
3084 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3085 | continue; | |
3086 | ||
3087 | default: | |
3088 | internalError (); | |
3089 | } | |
3090 | break; | |
3091 | } | |
3092 | va_end (args); | |
f6688943 | 3093 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3094 | |
3095 | append_insn (place, &insn, ep, r, false); | |
3096 | } | |
3097 | ||
3098 | static void | |
3099 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3100 | char *place; | |
43841e91 | 3101 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3102 | expressionS *ep; |
3103 | const char *name; | |
3104 | const char *fmt; | |
3105 | va_list args; | |
3106 | { | |
3107 | struct mips_cl_insn insn; | |
f6688943 TS |
3108 | bfd_reloc_code_real_type r[3] |
3109 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3110 | |
252b5132 RH |
3111 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3112 | assert (insn.insn_mo); | |
3113 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3114 | ||
3115 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3116 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3117 | { | |
3118 | ++insn.insn_mo; | |
3119 | assert (insn.insn_mo->name); | |
3120 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3121 | } | |
3122 | ||
3123 | insn.insn_opcode = insn.insn_mo->match; | |
3124 | insn.use_extend = false; | |
3125 | ||
3126 | for (;;) | |
3127 | { | |
3128 | int c; | |
3129 | ||
3130 | c = *fmt++; | |
3131 | switch (c) | |
3132 | { | |
3133 | case '\0': | |
3134 | break; | |
3135 | ||
3136 | case ',': | |
3137 | case '(': | |
3138 | case ')': | |
3139 | continue; | |
3140 | ||
3141 | case 'y': | |
3142 | case 'w': | |
3143 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3144 | continue; | |
3145 | ||
3146 | case 'x': | |
3147 | case 'v': | |
3148 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3149 | continue; | |
3150 | ||
3151 | case 'z': | |
3152 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3153 | continue; | |
3154 | ||
3155 | case 'Z': | |
3156 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3157 | continue; | |
3158 | ||
3159 | case '0': | |
3160 | case 'S': | |
3161 | case 'P': | |
3162 | case 'R': | |
3163 | continue; | |
3164 | ||
3165 | case 'X': | |
3166 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3167 | continue; | |
3168 | ||
3169 | case 'Y': | |
3170 | { | |
3171 | int regno; | |
3172 | ||
3173 | regno = va_arg (args, int); | |
3174 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3175 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3176 | } | |
3177 | continue; | |
3178 | ||
3179 | case '<': | |
3180 | case '>': | |
3181 | case '4': | |
3182 | case '5': | |
3183 | case 'H': | |
3184 | case 'W': | |
3185 | case 'D': | |
3186 | case 'j': | |
3187 | case '8': | |
3188 | case 'V': | |
3189 | case 'C': | |
3190 | case 'U': | |
3191 | case 'k': | |
3192 | case 'K': | |
3193 | case 'p': | |
3194 | case 'q': | |
3195 | { | |
3196 | assert (ep != NULL); | |
3197 | ||
3198 | if (ep->X_op != O_constant) | |
874e8986 | 3199 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3200 | else |
3201 | { | |
c4e7957c TS |
3202 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
3203 | false, &insn.insn_opcode, &insn.use_extend, | |
3204 | &insn.extend); | |
252b5132 | 3205 | ep = NULL; |
f6688943 | 3206 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3207 | } |
3208 | } | |
3209 | continue; | |
3210 | ||
3211 | case '6': | |
3212 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3213 | continue; | |
3214 | } | |
3215 | ||
3216 | break; | |
3217 | } | |
3218 | ||
f6688943 | 3219 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3220 | |
3221 | append_insn (place, &insn, ep, r, false); | |
3222 | } | |
3223 | ||
438c16b8 TS |
3224 | /* |
3225 | * Generate a "jalr" instruction with a relocation hint to the called | |
3226 | * function. This occurs in NewABI PIC code. | |
3227 | */ | |
3228 | static void | |
3229 | macro_build_jalr (icnt, ep) | |
3230 | int icnt; | |
3231 | expressionS *ep; | |
3232 | { | |
3233 | if (HAVE_NEWABI) | |
3234 | frag_more (0); | |
3235 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", | |
3236 | RA, PIC_CALL_REG); | |
3237 | if (HAVE_NEWABI) | |
3238 | fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR); | |
3239 | } | |
3240 | ||
252b5132 RH |
3241 | /* |
3242 | * Generate a "lui" instruction. | |
3243 | */ | |
3244 | static void | |
3245 | macro_build_lui (place, counter, ep, regnum) | |
3246 | char *place; | |
3247 | int *counter; | |
3248 | expressionS *ep; | |
3249 | int regnum; | |
3250 | { | |
3251 | expressionS high_expr; | |
3252 | struct mips_cl_insn insn; | |
f6688943 TS |
3253 | bfd_reloc_code_real_type r[3] |
3254 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3255 | CONST char *name = "lui"; |
3256 | CONST char *fmt = "t,u"; | |
3257 | ||
3258 | assert (! mips_opts.mips16); | |
3259 | ||
3260 | if (place == NULL) | |
3261 | high_expr = *ep; | |
3262 | else | |
3263 | { | |
3264 | high_expr.X_op = O_constant; | |
3265 | high_expr.X_add_number = ep->X_add_number; | |
3266 | } | |
3267 | ||
3268 | if (high_expr.X_op == O_constant) | |
3269 | { | |
3270 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3271 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3272 | >> 16) & 0xffff; | |
f6688943 | 3273 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3274 | } |
f6688943 | 3275 | else if (! HAVE_NEWABI) |
252b5132 RH |
3276 | { |
3277 | assert (ep->X_op == O_symbol); | |
3278 | /* _gp_disp is a special case, used from s_cpload. */ | |
3279 | assert (mips_pic == NO_PIC | |
3280 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3281 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3282 | } |
3283 | ||
3284 | /* | |
3285 | * If the macro is about to expand into a second instruction, | |
3286 | * print a warning if needed. We need to pass ip as a parameter | |
3287 | * to generate a better warning message here... | |
3288 | */ | |
3289 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3290 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3291 | ||
3292 | if (place == NULL) | |
f9419b05 | 3293 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3294 | |
3295 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3296 | assert (insn.insn_mo); | |
3297 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3298 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3299 | ||
3300 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3301 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3302 | { |
3303 | insn.insn_opcode |= high_expr.X_add_number; | |
3304 | append_insn (place, &insn, NULL, r, false); | |
3305 | } | |
3306 | else | |
3307 | append_insn (place, &insn, &high_expr, r, false); | |
3308 | } | |
3309 | ||
3310 | /* set_at() | |
3311 | * Generates code to set the $at register to true (one) | |
3312 | * if reg is less than the immediate expression. | |
3313 | */ | |
3314 | static void | |
3315 | set_at (counter, reg, unsignedp) | |
3316 | int *counter; | |
3317 | int reg; | |
3318 | int unsignedp; | |
3319 | { | |
3320 | if (imm_expr.X_op == O_constant | |
3321 | && imm_expr.X_add_number >= -0x8000 | |
3322 | && imm_expr.X_add_number < 0x8000) | |
3323 | macro_build ((char *) NULL, counter, &imm_expr, | |
3324 | unsignedp ? "sltiu" : "slti", | |
3325 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3326 | else | |
3327 | { | |
4d34fb5f | 3328 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3329 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3330 | unsignedp ? "sltu" : "slt", |
3331 | "d,v,t", AT, reg, AT); | |
3332 | } | |
3333 | } | |
3334 | ||
3335 | /* Warn if an expression is not a constant. */ | |
3336 | ||
3337 | static void | |
3338 | check_absolute_expr (ip, ex) | |
3339 | struct mips_cl_insn *ip; | |
3340 | expressionS *ex; | |
3341 | { | |
3342 | if (ex->X_op == O_big) | |
3343 | as_bad (_("unsupported large constant")); | |
3344 | else if (ex->X_op != O_constant) | |
3345 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3346 | } | |
3347 | ||
3348 | /* Count the leading zeroes by performing a binary chop. This is a | |
3349 | bulky bit of source, but performance is a LOT better for the | |
3350 | majority of values than a simple loop to count the bits: | |
3351 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3352 | if ((v) & (1 << (31 - lcnt))) | |
3353 | break; | |
3354 | However it is not code size friendly, and the gain will drop a bit | |
3355 | on certain cached systems. | |
3356 | */ | |
3357 | #define COUNT_TOP_ZEROES(v) \ | |
3358 | (((v) & ~0xffff) == 0 \ | |
3359 | ? ((v) & ~0xff) == 0 \ | |
3360 | ? ((v) & ~0xf) == 0 \ | |
3361 | ? ((v) & ~0x3) == 0 \ | |
3362 | ? ((v) & ~0x1) == 0 \ | |
3363 | ? !(v) \ | |
3364 | ? 32 \ | |
3365 | : 31 \ | |
3366 | : 30 \ | |
3367 | : ((v) & ~0x7) == 0 \ | |
3368 | ? 29 \ | |
3369 | : 28 \ | |
3370 | : ((v) & ~0x3f) == 0 \ | |
3371 | ? ((v) & ~0x1f) == 0 \ | |
3372 | ? 27 \ | |
3373 | : 26 \ | |
3374 | : ((v) & ~0x7f) == 0 \ | |
3375 | ? 25 \ | |
3376 | : 24 \ | |
3377 | : ((v) & ~0xfff) == 0 \ | |
3378 | ? ((v) & ~0x3ff) == 0 \ | |
3379 | ? ((v) & ~0x1ff) == 0 \ | |
3380 | ? 23 \ | |
3381 | : 22 \ | |
3382 | : ((v) & ~0x7ff) == 0 \ | |
3383 | ? 21 \ | |
3384 | : 20 \ | |
3385 | : ((v) & ~0x3fff) == 0 \ | |
3386 | ? ((v) & ~0x1fff) == 0 \ | |
3387 | ? 19 \ | |
3388 | : 18 \ | |
3389 | : ((v) & ~0x7fff) == 0 \ | |
3390 | ? 17 \ | |
3391 | : 16 \ | |
3392 | : ((v) & ~0xffffff) == 0 \ | |
3393 | ? ((v) & ~0xfffff) == 0 \ | |
3394 | ? ((v) & ~0x3ffff) == 0 \ | |
3395 | ? ((v) & ~0x1ffff) == 0 \ | |
3396 | ? 15 \ | |
3397 | : 14 \ | |
3398 | : ((v) & ~0x7ffff) == 0 \ | |
3399 | ? 13 \ | |
3400 | : 12 \ | |
3401 | : ((v) & ~0x3fffff) == 0 \ | |
3402 | ? ((v) & ~0x1fffff) == 0 \ | |
3403 | ? 11 \ | |
3404 | : 10 \ | |
3405 | : ((v) & ~0x7fffff) == 0 \ | |
3406 | ? 9 \ | |
3407 | : 8 \ | |
3408 | : ((v) & ~0xfffffff) == 0 \ | |
3409 | ? ((v) & ~0x3ffffff) == 0 \ | |
3410 | ? ((v) & ~0x1ffffff) == 0 \ | |
3411 | ? 7 \ | |
3412 | : 6 \ | |
3413 | : ((v) & ~0x7ffffff) == 0 \ | |
3414 | ? 5 \ | |
3415 | : 4 \ | |
3416 | : ((v) & ~0x3fffffff) == 0 \ | |
3417 | ? ((v) & ~0x1fffffff) == 0 \ | |
3418 | ? 3 \ | |
3419 | : 2 \ | |
3420 | : ((v) & ~0x7fffffff) == 0 \ | |
3421 | ? 1 \ | |
3422 | : 0) | |
3423 | ||
6373ee54 CD |
3424 | /* Is the given value a sign-extended 32-bit value? */ |
3425 | #define IS_SEXT_32BIT_NUM(x) \ | |
3426 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
3427 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
3428 | ||
252b5132 RH |
3429 | /* load_register() |
3430 | * This routine generates the least number of instructions neccessary to load | |
3431 | * an absolute expression value into a register. | |
3432 | */ | |
3433 | static void | |
3434 | load_register (counter, reg, ep, dbl) | |
3435 | int *counter; | |
3436 | int reg; | |
3437 | expressionS *ep; | |
3438 | int dbl; | |
3439 | { | |
3440 | int freg; | |
3441 | expressionS hi32, lo32; | |
3442 | ||
3443 | if (ep->X_op != O_big) | |
3444 | { | |
3445 | assert (ep->X_op == O_constant); | |
3446 | if (ep->X_add_number < 0x8000 | |
3447 | && (ep->X_add_number >= 0 | |
3448 | || (ep->X_add_number >= -0x8000 | |
3449 | && (! dbl | |
3450 | || ! ep->X_unsigned | |
3451 | || sizeof (ep->X_add_number) > 4)))) | |
3452 | { | |
3453 | /* We can handle 16 bit signed values with an addiu to | |
3454 | $zero. No need to ever use daddiu here, since $zero and | |
3455 | the result are always correct in 32 bit mode. */ | |
3456 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3457 | (int) BFD_RELOC_LO16); | |
3458 | return; | |
3459 | } | |
3460 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3461 | { | |
3462 | /* We can handle 16 bit unsigned values with an ori to | |
3463 | $zero. */ | |
3464 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3465 | (int) BFD_RELOC_LO16); | |
3466 | return; | |
3467 | } | |
6373ee54 | 3468 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3469 | && (! dbl |
3470 | || ! ep->X_unsigned | |
3471 | || sizeof (ep->X_add_number) > 4 | |
3472 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3473 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3474 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3475 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3476 | && ! dbl |
3477 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3478 | == ~ (offsetT) 0xffffffff))) | |
3479 | { | |
3480 | /* 32 bit values require an lui. */ | |
3481 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3482 | (int) BFD_RELOC_HI16); | |
3483 | if ((ep->X_add_number & 0xffff) != 0) | |
3484 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3485 | (int) BFD_RELOC_LO16); | |
3486 | return; | |
3487 | } | |
3488 | } | |
3489 | ||
3490 | /* The value is larger than 32 bits. */ | |
3491 | ||
ca4e0257 | 3492 | if (HAVE_32BIT_GPRS) |
252b5132 | 3493 | { |
956cd1d6 TS |
3494 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3495 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3496 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3497 | (int) BFD_RELOC_LO16); | |
3498 | return; | |
3499 | } | |
3500 | ||
3501 | if (ep->X_op != O_big) | |
3502 | { | |
3503 | hi32 = *ep; | |
3504 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3505 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3506 | hi32.X_add_number &= 0xffffffff; | |
3507 | lo32 = *ep; | |
3508 | lo32.X_add_number &= 0xffffffff; | |
3509 | } | |
3510 | else | |
3511 | { | |
3512 | assert (ep->X_add_number > 2); | |
3513 | if (ep->X_add_number == 3) | |
3514 | generic_bignum[3] = 0; | |
3515 | else if (ep->X_add_number > 4) | |
3516 | as_bad (_("Number larger than 64 bits")); | |
3517 | lo32.X_op = O_constant; | |
3518 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3519 | hi32.X_op = O_constant; | |
3520 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3521 | } | |
3522 | ||
3523 | if (hi32.X_add_number == 0) | |
3524 | freg = 0; | |
3525 | else | |
3526 | { | |
3527 | int shift, bit; | |
3528 | unsigned long hi, lo; | |
3529 | ||
956cd1d6 | 3530 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3531 | { |
3532 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3533 | { | |
3534 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3535 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3536 | return; |
3537 | } | |
3538 | if (lo32.X_add_number & 0x80000000) | |
3539 | { | |
3540 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3541 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3542 | if (lo32.X_add_number & 0xffff) |
3543 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3544 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3545 | return; |
3546 | } | |
3547 | } | |
252b5132 RH |
3548 | |
3549 | /* Check for 16bit shifted constant. We know that hi32 is | |
3550 | non-zero, so start the mask on the first bit of the hi32 | |
3551 | value. */ | |
3552 | shift = 17; | |
3553 | do | |
beae10d5 KH |
3554 | { |
3555 | unsigned long himask, lomask; | |
3556 | ||
3557 | if (shift < 32) | |
3558 | { | |
3559 | himask = 0xffff >> (32 - shift); | |
3560 | lomask = (0xffff << shift) & 0xffffffff; | |
3561 | } | |
3562 | else | |
3563 | { | |
3564 | himask = 0xffff << (shift - 32); | |
3565 | lomask = 0; | |
3566 | } | |
3567 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3568 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3569 | { | |
3570 | expressionS tmp; | |
3571 | ||
3572 | tmp.X_op = O_constant; | |
3573 | if (shift < 32) | |
3574 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3575 | | (lo32.X_add_number >> shift)); | |
3576 | else | |
3577 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3578 | macro_build ((char *) NULL, counter, &tmp, | |
3579 | "ori", "t,r,i", reg, 0, | |
3580 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3581 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3582 | (shift >= 32) ? "dsll32" : "dsll", |
3583 | "d,w,<", reg, reg, | |
3584 | (shift >= 32) ? shift - 32 : shift); | |
3585 | return; | |
3586 | } | |
f9419b05 | 3587 | ++shift; |
beae10d5 KH |
3588 | } |
3589 | while (shift <= (64 - 16)); | |
252b5132 RH |
3590 | |
3591 | /* Find the bit number of the lowest one bit, and store the | |
3592 | shifted value in hi/lo. */ | |
3593 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3594 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3595 | if (lo != 0) | |
3596 | { | |
3597 | bit = 0; | |
3598 | while ((lo & 1) == 0) | |
3599 | { | |
3600 | lo >>= 1; | |
3601 | ++bit; | |
3602 | } | |
3603 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3604 | hi >>= bit; | |
3605 | } | |
3606 | else | |
3607 | { | |
3608 | bit = 32; | |
3609 | while ((hi & 1) == 0) | |
3610 | { | |
3611 | hi >>= 1; | |
3612 | ++bit; | |
3613 | } | |
3614 | lo = hi; | |
3615 | hi = 0; | |
3616 | } | |
3617 | ||
3618 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3619 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3620 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3621 | { |
3622 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3623 | if (shift != 0) |
beae10d5 | 3624 | { |
252b5132 RH |
3625 | expressionS tmp; |
3626 | ||
3627 | /* This instruction will set the register to be all | |
3628 | ones. */ | |
beae10d5 KH |
3629 | tmp.X_op = O_constant; |
3630 | tmp.X_add_number = (offsetT) -1; | |
3631 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3632 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3633 | if (bit != 0) |
3634 | { | |
3635 | bit += shift; | |
2396cfb9 | 3636 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3637 | (bit >= 32) ? "dsll32" : "dsll", |
3638 | "d,w,<", reg, reg, | |
3639 | (bit >= 32) ? bit - 32 : bit); | |
3640 | } | |
2396cfb9 | 3641 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3642 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3643 | "d,w,<", reg, reg, |
252b5132 | 3644 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3645 | return; |
3646 | } | |
3647 | } | |
252b5132 RH |
3648 | |
3649 | /* Sign extend hi32 before calling load_register, because we can | |
3650 | generally get better code when we load a sign extended value. */ | |
3651 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3652 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3653 | load_register (counter, reg, &hi32, 0); |
3654 | freg = reg; | |
3655 | } | |
3656 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3657 | { | |
3658 | if (freg != 0) | |
3659 | { | |
2396cfb9 TS |
3660 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3661 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3662 | freg = reg; |
3663 | } | |
3664 | } | |
3665 | else | |
3666 | { | |
3667 | expressionS mid16; | |
3668 | ||
956cd1d6 | 3669 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3670 | { |
252b5132 RH |
3671 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3672 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3673 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3674 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3675 | return; |
3676 | } | |
252b5132 RH |
3677 | |
3678 | if (freg != 0) | |
3679 | { | |
956cd1d6 TS |
3680 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3681 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3682 | freg = reg; |
3683 | } | |
3684 | mid16 = lo32; | |
3685 | mid16.X_add_number >>= 16; | |
3686 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3687 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3688 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3689 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3690 | freg = reg; |
3691 | } | |
3692 | if ((lo32.X_add_number & 0xffff) != 0) | |
3693 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3694 | (int) BFD_RELOC_LO16); | |
3695 | } | |
3696 | ||
3697 | /* Load an address into a register. */ | |
3698 | ||
3699 | static void | |
c9914766 | 3700 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3701 | int *counter; |
3702 | int reg; | |
3703 | expressionS *ep; | |
d6bc6245 | 3704 | int *used_at; |
252b5132 | 3705 | { |
f9419b05 | 3706 | char *p = NULL; |
252b5132 RH |
3707 | |
3708 | if (ep->X_op != O_constant | |
3709 | && ep->X_op != O_symbol) | |
3710 | { | |
3711 | as_bad (_("expression too complex")); | |
3712 | ep->X_op = O_constant; | |
3713 | } | |
3714 | ||
3715 | if (ep->X_op == O_constant) | |
3716 | { | |
c9914766 | 3717 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3718 | return; |
3719 | } | |
3720 | ||
3721 | if (mips_pic == NO_PIC) | |
3722 | { | |
3723 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3724 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3725 | Otherwise we want |
3726 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3727 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3728 | If we have an addend, we always use the latter form. |
76b3015f | 3729 | |
d6bc6245 TS |
3730 | With 64bit address space and a usable $at we want |
3731 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3732 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3733 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3734 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3735 | dsll32 $reg,0 | |
3736 | dadd $reg,$reg,$at | |
76b3015f | 3737 | |
d6bc6245 TS |
3738 | If $at is already in use, we use an path which is suboptimal |
3739 | on superscalar processors. | |
3740 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3741 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3742 | dsll $reg,16 | |
3743 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3744 | dsll $reg,16 | |
3745 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3746 | */ | |
c9914766 | 3747 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3748 | { |
d6bc6245 TS |
3749 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3750 | hold the data for such large chunks. */ | |
3751 | ||
3752 | if (*used_at == 0) | |
3753 | { | |
3754 | macro_build (p, counter, ep, "lui", "t,u", | |
3755 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3756 | macro_build (p, counter, ep, "lui", "t,u", | |
3757 | AT, (int) BFD_RELOC_HI16_S); | |
3758 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3759 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3760 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3761 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3762 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3763 | "d,w,<", reg, reg, 0); | |
3764 | macro_build (p, counter, (expressionS *) NULL, "dadd", | |
3765 | "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3766 | *used_at = 1; |
3767 | } | |
3768 | else | |
3769 | { | |
3770 | macro_build (p, counter, ep, "lui", "t,u", | |
3771 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3772 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3773 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3774 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3775 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3776 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3777 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3778 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3779 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3780 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3781 | reg, reg, (int) BFD_RELOC_LO16); | |
3782 | } | |
3783 | } | |
252b5132 RH |
3784 | else |
3785 | { | |
d6bc6245 TS |
3786 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3787 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3788 | { | |
3789 | frag_grow (20); | |
3790 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3791 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
3792 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3793 | p = frag_var (rs_machine_dependent, 8, 0, |
3794 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3795 | mips_opts.warn_about_macros), | |
956cd1d6 | 3796 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3797 | } |
3798 | macro_build_lui (p, counter, ep, reg); | |
3799 | if (p != NULL) | |
3800 | p += 4; | |
c9914766 TS |
3801 | macro_build (p, counter, ep, |
3802 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
d6bc6245 TS |
3803 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3804 | } | |
252b5132 RH |
3805 | } |
3806 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3807 | { | |
3808 | expressionS ex; | |
3809 | ||
3810 | /* If this is a reference to an external symbol, we want | |
3811 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3812 | Otherwise we want | |
3813 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3814 | nop | |
3815 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3816 | If there is a constant, it must be added in after. */ | |
3817 | ex.X_add_number = ep->X_add_number; | |
3818 | ep->X_add_number = 0; | |
3819 | frag_grow (20); | |
3820 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3821 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", |
3822 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
3823 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
3824 | p = frag_var (rs_machine_dependent, 4, 0, | |
3825 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3826 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3827 | macro_build (p, counter, ep, | |
ca4e0257 | 3828 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3829 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3830 | if (ex.X_add_number != 0) | |
3831 | { | |
3832 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3833 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3834 | ex.X_op = O_constant; | |
3835 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3836 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3837 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3838 | } | |
3839 | } | |
3840 | else if (mips_pic == SVR4_PIC) | |
3841 | { | |
3842 | expressionS ex; | |
3843 | int off; | |
3844 | ||
3845 | /* This is the large GOT case. If this is a reference to an | |
3846 | external symbol, we want | |
3847 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3848 | addu $reg,$reg,$gp | |
3849 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3850 | Otherwise, for a reference to a local symbol, we want | |
3851 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3852 | nop | |
3853 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
438c16b8 TS |
3854 | If we have NewABI, we want |
3855 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
3856 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
252b5132 RH |
3857 | If there is a constant, it must be added in after. */ |
3858 | ex.X_add_number = ep->X_add_number; | |
3859 | ep->X_add_number = 0; | |
438c16b8 TS |
3860 | if (HAVE_NEWABI) |
3861 | { | |
3862 | macro_build ((char *) NULL, counter, ep, | |
3863 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3864 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
3865 | macro_build (p, counter, ep, | |
3866 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", | |
3867 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); | |
3868 | } | |
252b5132 | 3869 | else |
438c16b8 TS |
3870 | { |
3871 | if (reg_needs_delay (mips_gp_register)) | |
3872 | off = 4; | |
3873 | else | |
3874 | off = 0; | |
3875 | frag_grow (32); | |
3876 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3877 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3878 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3879 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, | |
3880 | reg, mips_gp_register); | |
3881 | macro_build ((char *) NULL, counter, ep, | |
3882 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
3883 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3884 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3885 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3886 | mips_opts.warn_about_macros), | |
3887 | ep->X_add_symbol, 0, NULL); | |
3888 | if (off > 0) | |
3889 | { | |
3890 | /* We need a nop before loading from $gp. This special | |
3891 | check is required because the lui which starts the main | |
3892 | instruction stream does not refer to $gp, and so will not | |
3893 | insert the nop which may be required. */ | |
3894 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3895 | p += 4; | |
3896 | } | |
3897 | macro_build (p, counter, ep, | |
3898 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3899 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3900 | p += 4; | |
252b5132 RH |
3901 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
3902 | p += 4; | |
438c16b8 TS |
3903 | macro_build (p, counter, ep, |
3904 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3905 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
252b5132 | 3906 | } |
438c16b8 | 3907 | |
252b5132 RH |
3908 | if (ex.X_add_number != 0) |
3909 | { | |
3910 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3911 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3912 | ex.X_op = O_constant; | |
f7ea7ef2 TS |
3913 | macro_build ((char *) NULL, counter, &ex, |
3914 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
252b5132 RH |
3915 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3916 | } | |
3917 | } | |
3918 | else if (mips_pic == EMBEDDED_PIC) | |
3919 | { | |
3920 | /* We always do | |
cdf6fd85 | 3921 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 TS |
3922 | */ |
3923 | macro_build ((char *) NULL, counter, ep, | |
3924 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3925 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
3926 | } |
3927 | else | |
3928 | abort (); | |
3929 | } | |
3930 | ||
ea1fb5dc RS |
3931 | /* Move the contents of register SOURCE into register DEST. */ |
3932 | ||
3933 | static void | |
3934 | move_register (counter, dest, source) | |
3935 | int *counter; | |
3936 | int dest; | |
3937 | int source; | |
3938 | { | |
3939 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3940 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3941 | "d,v,t", dest, source, 0); | |
3942 | } | |
3943 | ||
252b5132 RH |
3944 | /* |
3945 | * Build macros | |
3946 | * This routine implements the seemingly endless macro or synthesized | |
3947 | * instructions and addressing modes in the mips assembly language. Many | |
3948 | * of these macros are simple and are similar to each other. These could | |
3949 | * probably be handled by some kind of table or grammer aproach instead of | |
3950 | * this verbose method. Others are not simple macros but are more like | |
3951 | * optimizing code generation. | |
3952 | * One interesting optimization is when several store macros appear | |
3953 | * consecutivly that would load AT with the upper half of the same address. | |
3954 | * The ensuing load upper instructions are ommited. This implies some kind | |
3955 | * of global optimization. We currently only optimize within a single macro. | |
3956 | * For many of the load and store macros if the address is specified as a | |
3957 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3958 | * first load register 'at' with zero and use it as the base register. The | |
3959 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3960 | * we're missing. | |
3961 | */ | |
3962 | static void | |
3963 | macro (ip) | |
3964 | struct mips_cl_insn *ip; | |
3965 | { | |
3966 | register int treg, sreg, dreg, breg; | |
3967 | int tempreg; | |
3968 | int mask; | |
3969 | int icnt = 0; | |
43841e91 | 3970 | int used_at = 0; |
252b5132 RH |
3971 | expressionS expr1; |
3972 | const char *s; | |
3973 | const char *s2; | |
3974 | const char *fmt; | |
3975 | int likely = 0; | |
3976 | int dbl = 0; | |
3977 | int coproc = 0; | |
3978 | int lr = 0; | |
3979 | int imm = 0; | |
3980 | offsetT maxnum; | |
3981 | int off; | |
3982 | bfd_reloc_code_real_type r; | |
252b5132 RH |
3983 | int hold_mips_optimize; |
3984 | ||
3985 | assert (! mips_opts.mips16); | |
3986 | ||
3987 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3988 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3989 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3990 | mask = ip->insn_mo->mask; | |
3991 | ||
3992 | expr1.X_op = O_constant; | |
3993 | expr1.X_op_symbol = NULL; | |
3994 | expr1.X_add_symbol = NULL; | |
3995 | expr1.X_add_number = 1; | |
3996 | ||
3997 | switch (mask) | |
3998 | { | |
3999 | case M_DABS: | |
4000 | dbl = 1; | |
4001 | case M_ABS: | |
4002 | /* bgez $a0,.+12 | |
4003 | move v0,$a0 | |
4004 | sub v0,$zero,$a0 | |
4005 | */ | |
4006 | ||
4007 | mips_emit_delays (true); | |
4008 | ++mips_opts.noreorder; | |
4009 | mips_any_noreorder = 1; | |
4010 | ||
4011 | expr1.X_add_number = 8; | |
4012 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4013 | if (dreg == sreg) | |
2396cfb9 TS |
4014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4015 | 0); | |
252b5132 | 4016 | else |
ea1fb5dc | 4017 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4018 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4019 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4020 | |
4021 | --mips_opts.noreorder; | |
4022 | return; | |
4023 | ||
4024 | case M_ADD_I: | |
4025 | s = "addi"; | |
4026 | s2 = "add"; | |
4027 | goto do_addi; | |
4028 | case M_ADDU_I: | |
4029 | s = "addiu"; | |
4030 | s2 = "addu"; | |
4031 | goto do_addi; | |
4032 | case M_DADD_I: | |
4033 | dbl = 1; | |
4034 | s = "daddi"; | |
4035 | s2 = "dadd"; | |
4036 | goto do_addi; | |
4037 | case M_DADDU_I: | |
4038 | dbl = 1; | |
4039 | s = "daddiu"; | |
4040 | s2 = "daddu"; | |
4041 | do_addi: | |
4042 | if (imm_expr.X_op == O_constant | |
4043 | && imm_expr.X_add_number >= -0x8000 | |
4044 | && imm_expr.X_add_number < 0x8000) | |
4045 | { | |
4046 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4047 | (int) BFD_RELOC_LO16); | |
4048 | return; | |
4049 | } | |
4050 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4051 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4052 | treg, sreg, AT); | |
252b5132 RH |
4053 | break; |
4054 | ||
4055 | case M_AND_I: | |
4056 | s = "andi"; | |
4057 | s2 = "and"; | |
4058 | goto do_bit; | |
4059 | case M_OR_I: | |
4060 | s = "ori"; | |
4061 | s2 = "or"; | |
4062 | goto do_bit; | |
4063 | case M_NOR_I: | |
4064 | s = ""; | |
4065 | s2 = "nor"; | |
4066 | goto do_bit; | |
4067 | case M_XOR_I: | |
4068 | s = "xori"; | |
4069 | s2 = "xor"; | |
4070 | do_bit: | |
4071 | if (imm_expr.X_op == O_constant | |
4072 | && imm_expr.X_add_number >= 0 | |
4073 | && imm_expr.X_add_number < 0x10000) | |
4074 | { | |
4075 | if (mask != M_NOR_I) | |
4076 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4077 | sreg, (int) BFD_RELOC_LO16); | |
4078 | else | |
4079 | { | |
4080 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4081 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4082 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4083 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4084 | } |
4085 | return; | |
4086 | } | |
4087 | ||
d6bc6245 | 4088 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4089 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4090 | treg, sreg, AT); | |
252b5132 RH |
4091 | break; |
4092 | ||
4093 | case M_BEQ_I: | |
4094 | s = "beq"; | |
4095 | goto beq_i; | |
4096 | case M_BEQL_I: | |
4097 | s = "beql"; | |
4098 | likely = 1; | |
4099 | goto beq_i; | |
4100 | case M_BNE_I: | |
4101 | s = "bne"; | |
4102 | goto beq_i; | |
4103 | case M_BNEL_I: | |
4104 | s = "bnel"; | |
4105 | likely = 1; | |
4106 | beq_i: | |
4107 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4108 | { | |
4109 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4110 | 0); | |
4111 | return; | |
4112 | } | |
4d34fb5f | 4113 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4114 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4115 | break; | |
4116 | ||
4117 | case M_BGEL: | |
4118 | likely = 1; | |
4119 | case M_BGE: | |
4120 | if (treg == 0) | |
4121 | { | |
4122 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4123 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4124 | return; |
4125 | } | |
4126 | if (sreg == 0) | |
4127 | { | |
4128 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4129 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4130 | return; |
4131 | } | |
2396cfb9 TS |
4132 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4133 | AT, sreg, treg); | |
252b5132 | 4134 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4135 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4136 | break; |
4137 | ||
4138 | case M_BGTL_I: | |
4139 | likely = 1; | |
4140 | case M_BGT_I: | |
4141 | /* check for > max integer */ | |
4142 | maxnum = 0x7fffffff; | |
ca4e0257 | 4143 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4144 | { |
4145 | maxnum <<= 16; | |
4146 | maxnum |= 0xffff; | |
4147 | maxnum <<= 16; | |
4148 | maxnum |= 0xffff; | |
4149 | } | |
4150 | if (imm_expr.X_op == O_constant | |
4151 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4152 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4153 | { |
4154 | do_false: | |
4155 | /* result is always false */ | |
4156 | if (! likely) | |
4157 | { | |
39c0a331 L |
4158 | if (warn_nops) |
4159 | as_warn (_("Branch %s is always false (nop)"), | |
4160 | ip->insn_mo->name); | |
2396cfb9 TS |
4161 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4162 | "", 0); | |
252b5132 RH |
4163 | } |
4164 | else | |
4165 | { | |
39c0a331 L |
4166 | if (warn_nops) |
4167 | as_warn (_("Branch likely %s is always false"), | |
4168 | ip->insn_mo->name); | |
252b5132 RH |
4169 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4170 | "s,t,p", 0, 0); | |
4171 | } | |
4172 | return; | |
4173 | } | |
4174 | if (imm_expr.X_op != O_constant) | |
4175 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4176 | ++imm_expr.X_add_number; |
252b5132 RH |
4177 | /* FALLTHROUGH */ |
4178 | case M_BGE_I: | |
4179 | case M_BGEL_I: | |
4180 | if (mask == M_BGEL_I) | |
4181 | likely = 1; | |
4182 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4183 | { | |
4184 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4185 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4186 | return; |
4187 | } | |
4188 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4189 | { | |
4190 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4191 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4192 | return; |
4193 | } | |
4194 | maxnum = 0x7fffffff; | |
ca4e0257 | 4195 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4196 | { |
4197 | maxnum <<= 16; | |
4198 | maxnum |= 0xffff; | |
4199 | maxnum <<= 16; | |
4200 | maxnum |= 0xffff; | |
4201 | } | |
4202 | maxnum = - maxnum - 1; | |
4203 | if (imm_expr.X_op == O_constant | |
4204 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4205 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4206 | { |
4207 | do_true: | |
4208 | /* result is always true */ | |
4209 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4210 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4211 | return; | |
4212 | } | |
4213 | set_at (&icnt, sreg, 0); | |
4214 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4215 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4216 | break; |
4217 | ||
4218 | case M_BGEUL: | |
4219 | likely = 1; | |
4220 | case M_BGEU: | |
4221 | if (treg == 0) | |
4222 | goto do_true; | |
4223 | if (sreg == 0) | |
4224 | { | |
4225 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4226 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4227 | return; |
4228 | } | |
2396cfb9 TS |
4229 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4230 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4231 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4232 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4233 | break; |
4234 | ||
4235 | case M_BGTUL_I: | |
4236 | likely = 1; | |
4237 | case M_BGTU_I: | |
4238 | if (sreg == 0 | |
ca4e0257 | 4239 | || (HAVE_32BIT_GPRS |
252b5132 | 4240 | && imm_expr.X_op == O_constant |
956cd1d6 | 4241 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4242 | goto do_false; |
4243 | if (imm_expr.X_op != O_constant) | |
4244 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4245 | ++imm_expr.X_add_number; |
252b5132 RH |
4246 | /* FALLTHROUGH */ |
4247 | case M_BGEU_I: | |
4248 | case M_BGEUL_I: | |
4249 | if (mask == M_BGEUL_I) | |
4250 | likely = 1; | |
4251 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4252 | goto do_true; | |
4253 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4254 | { | |
4255 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4256 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4257 | return; |
4258 | } | |
4259 | set_at (&icnt, sreg, 1); | |
4260 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4261 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4262 | break; |
4263 | ||
4264 | case M_BGTL: | |
4265 | likely = 1; | |
4266 | case M_BGT: | |
4267 | if (treg == 0) | |
4268 | { | |
4269 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4270 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4271 | return; |
4272 | } | |
4273 | if (sreg == 0) | |
4274 | { | |
4275 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4276 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4277 | return; |
4278 | } | |
2396cfb9 TS |
4279 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4280 | AT, treg, sreg); | |
252b5132 | 4281 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4282 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4283 | break; |
4284 | ||
4285 | case M_BGTUL: | |
4286 | likely = 1; | |
4287 | case M_BGTU: | |
4288 | if (treg == 0) | |
4289 | { | |
4290 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4291 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4292 | return; |
4293 | } | |
4294 | if (sreg == 0) | |
4295 | goto do_false; | |
2396cfb9 TS |
4296 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4297 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4298 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4299 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4300 | break; |
4301 | ||
4302 | case M_BLEL: | |
4303 | likely = 1; | |
4304 | case M_BLE: | |
4305 | if (treg == 0) | |
4306 | { | |
4307 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4308 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4309 | return; |
4310 | } | |
4311 | if (sreg == 0) | |
4312 | { | |
4313 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4314 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4315 | return; |
4316 | } | |
2396cfb9 TS |
4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4318 | AT, treg, sreg); | |
252b5132 | 4319 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4320 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4321 | break; |
4322 | ||
4323 | case M_BLEL_I: | |
4324 | likely = 1; | |
4325 | case M_BLE_I: | |
4326 | maxnum = 0x7fffffff; | |
ca4e0257 | 4327 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4328 | { |
4329 | maxnum <<= 16; | |
4330 | maxnum |= 0xffff; | |
4331 | maxnum <<= 16; | |
4332 | maxnum |= 0xffff; | |
4333 | } | |
4334 | if (imm_expr.X_op == O_constant | |
4335 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4336 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4337 | goto do_true; |
4338 | if (imm_expr.X_op != O_constant) | |
4339 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4340 | ++imm_expr.X_add_number; |
252b5132 RH |
4341 | /* FALLTHROUGH */ |
4342 | case M_BLT_I: | |
4343 | case M_BLTL_I: | |
4344 | if (mask == M_BLTL_I) | |
4345 | likely = 1; | |
4346 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4347 | { | |
4348 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4349 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4350 | return; |
4351 | } | |
4352 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4353 | { | |
4354 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4355 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4356 | return; |
4357 | } | |
4358 | set_at (&icnt, sreg, 0); | |
4359 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4360 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4361 | break; |
4362 | ||
4363 | case M_BLEUL: | |
4364 | likely = 1; | |
4365 | case M_BLEU: | |
4366 | if (treg == 0) | |
4367 | { | |
4368 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4369 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4370 | return; |
4371 | } | |
4372 | if (sreg == 0) | |
4373 | goto do_true; | |
2396cfb9 TS |
4374 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4375 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4376 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4377 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4378 | break; |
4379 | ||
4380 | case M_BLEUL_I: | |
4381 | likely = 1; | |
4382 | case M_BLEU_I: | |
4383 | if (sreg == 0 | |
ca4e0257 | 4384 | || (HAVE_32BIT_GPRS |
252b5132 | 4385 | && imm_expr.X_op == O_constant |
956cd1d6 | 4386 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4387 | goto do_true; |
4388 | if (imm_expr.X_op != O_constant) | |
4389 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4390 | ++imm_expr.X_add_number; |
252b5132 RH |
4391 | /* FALLTHROUGH */ |
4392 | case M_BLTU_I: | |
4393 | case M_BLTUL_I: | |
4394 | if (mask == M_BLTUL_I) | |
4395 | likely = 1; | |
4396 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4397 | goto do_false; | |
4398 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4399 | { | |
4400 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4401 | likely ? "beql" : "beq", | |
4402 | "s,t,p", sreg, 0); | |
4403 | return; | |
4404 | } | |
4405 | set_at (&icnt, sreg, 1); | |
4406 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4407 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4408 | break; |
4409 | ||
4410 | case M_BLTL: | |
4411 | likely = 1; | |
4412 | case M_BLT: | |
4413 | if (treg == 0) | |
4414 | { | |
4415 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4416 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4417 | return; |
4418 | } | |
4419 | if (sreg == 0) | |
4420 | { | |
4421 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4422 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4423 | return; |
4424 | } | |
2396cfb9 TS |
4425 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4426 | AT, sreg, treg); | |
252b5132 | 4427 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4428 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4429 | break; |
4430 | ||
4431 | case M_BLTUL: | |
4432 | likely = 1; | |
4433 | case M_BLTU: | |
4434 | if (treg == 0) | |
4435 | goto do_false; | |
4436 | if (sreg == 0) | |
4437 | { | |
4438 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4439 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4440 | return; |
4441 | } | |
2396cfb9 TS |
4442 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4443 | "d,v,t", AT, sreg, | |
252b5132 RH |
4444 | treg); |
4445 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4446 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4447 | break; |
4448 | ||
4449 | case M_DDIV_3: | |
4450 | dbl = 1; | |
4451 | case M_DIV_3: | |
4452 | s = "mflo"; | |
4453 | goto do_div3; | |
4454 | case M_DREM_3: | |
4455 | dbl = 1; | |
4456 | case M_REM_3: | |
4457 | s = "mfhi"; | |
4458 | do_div3: | |
4459 | if (treg == 0) | |
4460 | { | |
4461 | as_warn (_("Divide by zero.")); | |
4462 | if (mips_trap) | |
2396cfb9 TS |
4463 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4464 | "s,t", 0, 0); | |
252b5132 | 4465 | else |
2396cfb9 TS |
4466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4467 | "c", 7); | |
252b5132 RH |
4468 | return; |
4469 | } | |
4470 | ||
4471 | mips_emit_delays (true); | |
4472 | ++mips_opts.noreorder; | |
4473 | mips_any_noreorder = 1; | |
4474 | if (mips_trap) | |
4475 | { | |
2396cfb9 TS |
4476 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4477 | "s,t", treg, 0); | |
4478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 4479 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4480 | } |
4481 | else | |
4482 | { | |
4483 | expr1.X_add_number = 8; | |
4484 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4485 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4486 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4487 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4488 | "c", 7); | |
252b5132 RH |
4489 | } |
4490 | expr1.X_add_number = -1; | |
4491 | macro_build ((char *) NULL, &icnt, &expr1, | |
4492 | dbl ? "daddiu" : "addiu", | |
4493 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4494 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4495 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4496 | if (dbl) | |
4497 | { | |
4498 | expr1.X_add_number = 1; | |
4499 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4500 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4501 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4502 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4503 | } |
4504 | else | |
4505 | { | |
4506 | expr1.X_add_number = 0x80000000; | |
4507 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4508 | (int) BFD_RELOC_HI16); | |
4509 | } | |
4510 | if (mips_trap) | |
4511 | { | |
2396cfb9 TS |
4512 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4513 | "s,t", sreg, AT); | |
252b5132 RH |
4514 | /* We want to close the noreorder block as soon as possible, so |
4515 | that later insns are available for delay slot filling. */ | |
4516 | --mips_opts.noreorder; | |
4517 | } | |
4518 | else | |
4519 | { | |
4520 | expr1.X_add_number = 8; | |
4521 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4522 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4523 | 0); | |
252b5132 RH |
4524 | |
4525 | /* We want to close the noreorder block as soon as possible, so | |
4526 | that later insns are available for delay slot filling. */ | |
4527 | --mips_opts.noreorder; | |
4528 | ||
2396cfb9 TS |
4529 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4530 | "c", 6); | |
252b5132 | 4531 | } |
2396cfb9 | 4532 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4533 | break; |
4534 | ||
4535 | case M_DIV_3I: | |
4536 | s = "div"; | |
4537 | s2 = "mflo"; | |
4538 | goto do_divi; | |
4539 | case M_DIVU_3I: | |
4540 | s = "divu"; | |
4541 | s2 = "mflo"; | |
4542 | goto do_divi; | |
4543 | case M_REM_3I: | |
4544 | s = "div"; | |
4545 | s2 = "mfhi"; | |
4546 | goto do_divi; | |
4547 | case M_REMU_3I: | |
4548 | s = "divu"; | |
4549 | s2 = "mfhi"; | |
4550 | goto do_divi; | |
4551 | case M_DDIV_3I: | |
4552 | dbl = 1; | |
4553 | s = "ddiv"; | |
4554 | s2 = "mflo"; | |
4555 | goto do_divi; | |
4556 | case M_DDIVU_3I: | |
4557 | dbl = 1; | |
4558 | s = "ddivu"; | |
4559 | s2 = "mflo"; | |
4560 | goto do_divi; | |
4561 | case M_DREM_3I: | |
4562 | dbl = 1; | |
4563 | s = "ddiv"; | |
4564 | s2 = "mfhi"; | |
4565 | goto do_divi; | |
4566 | case M_DREMU_3I: | |
4567 | dbl = 1; | |
4568 | s = "ddivu"; | |
4569 | s2 = "mfhi"; | |
4570 | do_divi: | |
4571 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4572 | { | |
4573 | as_warn (_("Divide by zero.")); | |
4574 | if (mips_trap) | |
2396cfb9 TS |
4575 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4576 | "s,t", 0, 0); | |
252b5132 | 4577 | else |
2396cfb9 TS |
4578 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4579 | "c", 7); | |
252b5132 RH |
4580 | return; |
4581 | } | |
4582 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4583 | { | |
4584 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4585 | move_register (&icnt, dreg, sreg); |
252b5132 | 4586 | else |
ea1fb5dc | 4587 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4588 | return; |
4589 | } | |
4590 | if (imm_expr.X_op == O_constant | |
4591 | && imm_expr.X_add_number == -1 | |
4592 | && s[strlen (s) - 1] != 'u') | |
4593 | { | |
4594 | if (strcmp (s2, "mflo") == 0) | |
4595 | { | |
2396cfb9 TS |
4596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4597 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4598 | } |
4599 | else | |
ea1fb5dc | 4600 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4601 | return; |
4602 | } | |
4603 | ||
4604 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4606 | sreg, AT); | |
4607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4608 | break; |
4609 | ||
4610 | case M_DIVU_3: | |
4611 | s = "divu"; | |
4612 | s2 = "mflo"; | |
4613 | goto do_divu3; | |
4614 | case M_REMU_3: | |
4615 | s = "divu"; | |
4616 | s2 = "mfhi"; | |
4617 | goto do_divu3; | |
4618 | case M_DDIVU_3: | |
4619 | s = "ddivu"; | |
4620 | s2 = "mflo"; | |
4621 | goto do_divu3; | |
4622 | case M_DREMU_3: | |
4623 | s = "ddivu"; | |
4624 | s2 = "mfhi"; | |
4625 | do_divu3: | |
4626 | mips_emit_delays (true); | |
4627 | ++mips_opts.noreorder; | |
4628 | mips_any_noreorder = 1; | |
4629 | if (mips_trap) | |
4630 | { | |
2396cfb9 TS |
4631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4632 | "s,t", treg, 0); | |
4633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", | |
4634 | sreg, treg); | |
252b5132 RH |
4635 | /* We want to close the noreorder block as soon as possible, so |
4636 | that later insns are available for delay slot filling. */ | |
4637 | --mips_opts.noreorder; | |
4638 | } | |
4639 | else | |
4640 | { | |
4641 | expr1.X_add_number = 8; | |
4642 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4644 | sreg, treg); | |
252b5132 RH |
4645 | |
4646 | /* We want to close the noreorder block as soon as possible, so | |
4647 | that later insns are available for delay slot filling. */ | |
4648 | --mips_opts.noreorder; | |
2396cfb9 TS |
4649 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4650 | "c", 7); | |
252b5132 | 4651 | } |
2396cfb9 | 4652 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4653 | return; |
4654 | ||
4655 | case M_DLA_AB: | |
4656 | dbl = 1; | |
4657 | case M_LA_AB: | |
4658 | /* Load the address of a symbol into a register. If breg is not | |
4659 | zero, we then add a base register to it. */ | |
4660 | ||
3bec30a8 TS |
4661 | if (dbl && HAVE_32BIT_GPRS) |
4662 | as_warn (_("dla used to load 32-bit register")); | |
4663 | ||
c90bbe5b | 4664 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4665 | as_warn (_("la used to load 64-bit address")); |
4666 | ||
afdbd6d0 CD |
4667 | if (treg == breg) |
4668 | { | |
4669 | tempreg = AT; | |
4670 | used_at = 1; | |
4671 | } | |
4672 | else | |
4673 | { | |
4674 | tempreg = treg; | |
4675 | used_at = 0; | |
4676 | } | |
4677 | ||
252b5132 RH |
4678 | /* When generating embedded PIC code, we permit expressions of |
4679 | the form | |
afdbd6d0 CD |
4680 | la $treg,foo-bar |
4681 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4682 | where bar is an address in the current section. These are used |
252b5132 RH |
4683 | when getting the addresses of functions. We don't permit |
4684 | X_add_number to be non-zero, because if the symbol is | |
4685 | external the relaxing code needs to know that any addend is | |
4686 | purely the offset to X_op_symbol. */ | |
4687 | if (mips_pic == EMBEDDED_PIC | |
4688 | && offset_expr.X_op == O_subtract | |
49309057 | 4689 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4690 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4691 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4692 | && (S_GET_SEGMENT | |
4693 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4694 | ->X_add_symbol) | |
bb2d6cd7 | 4695 | == now_seg))) |
bb2d6cd7 GK |
4696 | && (offset_expr.X_add_number == 0 |
4697 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4698 | { |
afdbd6d0 CD |
4699 | if (breg == 0) |
4700 | { | |
4701 | tempreg = treg; | |
4702 | used_at = 0; | |
4703 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4704 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4705 | } | |
4706 | else | |
4707 | { | |
4708 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4709 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4710 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4711 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4712 | "d,v,t", tempreg, tempreg, breg); |
4713 | } | |
252b5132 | 4714 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4715 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4716 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4717 | if (! used_at) | |
4718 | return; | |
4719 | break; | |
252b5132 RH |
4720 | } |
4721 | ||
4722 | if (offset_expr.X_op != O_symbol | |
4723 | && offset_expr.X_op != O_constant) | |
4724 | { | |
4725 | as_bad (_("expression too complex")); | |
4726 | offset_expr.X_op = O_constant; | |
4727 | } | |
4728 | ||
252b5132 | 4729 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4730 | load_register (&icnt, tempreg, &offset_expr, |
4731 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4732 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4733 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4734 | else if (mips_pic == NO_PIC) |
4735 | { | |
d6bc6245 | 4736 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4737 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4738 | Otherwise we want |
4739 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4740 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4741 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4742 | so we may as well always use the latter form. |
76b3015f | 4743 | |
d6bc6245 TS |
4744 | With 64bit address space and a usable $at we want |
4745 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4746 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4747 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4748 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4749 | dsll32 $tempreg,0 | |
4750 | dadd $tempreg,$tempreg,$at | |
76b3015f | 4751 | |
d6bc6245 TS |
4752 | If $at is already in use, we use an path which is suboptimal |
4753 | on superscalar processors. | |
4754 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4755 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4756 | dsll $tempreg,16 | |
4757 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4758 | dsll $tempreg,16 | |
4759 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4760 | */ | |
f9419b05 | 4761 | char *p = NULL; |
d6bc6245 | 4762 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4763 | { |
d6bc6245 TS |
4764 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4765 | hold the data for such large chunks. */ | |
4766 | ||
98d3f06f KH |
4767 | if (used_at == 0) |
4768 | { | |
4769 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4770 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4771 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4772 | AT, (int) BFD_RELOC_HI16_S); | |
4773 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4774 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4775 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4776 | AT, AT, (int) BFD_RELOC_LO16); | |
4777 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4778 | "d,w,<", tempreg, tempreg, 0); | |
4779 | macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t", | |
4780 | tempreg, tempreg, AT); | |
4781 | used_at = 1; | |
4782 | } | |
4783 | else | |
4784 | { | |
4785 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4786 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4787 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4788 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4789 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4790 | tempreg, tempreg, 16); | |
4791 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4792 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4793 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4794 | tempreg, tempreg, 16); | |
4795 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4796 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4797 | } | |
4798 | } | |
4799 | else | |
4800 | { | |
4801 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4802 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4803 | { | |
4804 | frag_grow (20); | |
4805 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
c9914766 TS |
4806 | "t,r,j", tempreg, mips_gp_register, |
4807 | (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4808 | p = frag_var (rs_machine_dependent, 8, 0, |
4809 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4810 | mips_opts.warn_about_macros), | |
4811 | offset_expr.X_add_symbol, 0, NULL); | |
4812 | } | |
4813 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4814 | if (p != NULL) | |
4815 | p += 4; | |
4816 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4817 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4818 | } | |
252b5132 RH |
4819 | } |
4820 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4821 | { | |
9117d219 NC |
4822 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4823 | ||
252b5132 RH |
4824 | /* If this is a reference to an external symbol, and there |
4825 | is no constant, we want | |
4826 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4827 | or if tempreg is PIC_CALL_REG |
4828 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4829 | For a local symbol, we want |
4830 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4831 | nop | |
4832 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4833 | ||
4834 | If we have a small constant, and this is a reference to | |
4835 | an external symbol, we want | |
4836 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4837 | nop | |
4838 | addiu $tempreg,$tempreg,<constant> | |
4839 | For a local symbol, we want the same instruction | |
4840 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4841 | addiu instruction. | |
4842 | ||
4843 | If we have a large constant, and this is a reference to | |
4844 | an external symbol, we want | |
4845 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4846 | lui $at,<hiconstant> | |
4847 | addiu $at,$at,<loconstant> | |
4848 | addu $tempreg,$tempreg,$at | |
4849 | For a local symbol, we want the same instruction | |
4850 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4851 | addiu instruction. */ | |
4852 | expr1.X_add_number = offset_expr.X_add_number; | |
4853 | offset_expr.X_add_number = 0; | |
4854 | frag_grow (32); | |
9117d219 NC |
4855 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4856 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4d34fb5f TS |
4857 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4858 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
c9914766 | 4859 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
4860 | if (expr1.X_add_number == 0) |
4861 | { | |
4862 | int off; | |
f9419b05 | 4863 | char *p; |
252b5132 RH |
4864 | |
4865 | if (breg == 0) | |
4866 | off = 0; | |
4867 | else | |
4868 | { | |
4869 | /* We're going to put in an addu instruction using | |
4870 | tempreg, so we may as well insert the nop right | |
4871 | now. */ | |
4872 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4873 | "nop", ""); | |
4874 | off = 4; | |
4875 | } | |
4876 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4877 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4878 | (breg == 0 | |
4879 | ? mips_opts.warn_about_macros | |
4880 | : 0)), | |
c4e7957c | 4881 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4882 | if (breg == 0) |
4883 | { | |
4884 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4885 | p += 4; | |
4886 | } | |
4887 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4888 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4889 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4890 | /* FIXME: If breg == 0, and the next instruction uses | |
4891 | $tempreg, then if this variant case is used an extra | |
4892 | nop will be generated. */ | |
4893 | } | |
4894 | else if (expr1.X_add_number >= -0x8000 | |
4895 | && expr1.X_add_number < 0x8000) | |
4896 | { | |
4897 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4898 | "nop", ""); | |
4899 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4900 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 4901 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
4902 | frag_var (rs_machine_dependent, 0, 0, |
4903 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4904 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4905 | } |
4906 | else | |
4907 | { | |
4908 | int off1; | |
4909 | ||
4910 | /* If we are going to add in a base register, and the | |
4911 | target register and the base register are the same, | |
4912 | then we are using AT as a temporary register. Since | |
4913 | we want to load the constant into AT, we add our | |
4914 | current AT (from the global offset table) and the | |
4915 | register into the register now, and pretend we were | |
4916 | not using a base register. */ | |
4917 | if (breg != treg) | |
4918 | off1 = 0; | |
4919 | else | |
4920 | { | |
4921 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4922 | "nop", ""); | |
4923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4924 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4925 | "d,v,t", treg, AT, breg); |
4926 | breg = 0; | |
4927 | tempreg = treg; | |
4928 | off1 = -8; | |
4929 | } | |
4930 | ||
4931 | /* Set mips_optimize around the lui instruction to avoid | |
4932 | inserting an unnecessary nop after the lw. */ | |
4933 | hold_mips_optimize = mips_optimize; | |
4934 | mips_optimize = 2; | |
c4e7957c | 4935 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4936 | mips_optimize = hold_mips_optimize; |
4937 | ||
4938 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4939 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4940 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4941 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4942 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 4943 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
4944 | frag_var (rs_machine_dependent, 0, 0, |
4945 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4946 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4947 | used_at = 1; |
4948 | } | |
4949 | } | |
4950 | else if (mips_pic == SVR4_PIC) | |
4951 | { | |
4952 | int gpdel; | |
f9419b05 | 4953 | char *p; |
9117d219 NC |
4954 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4955 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4956 | |
4957 | /* This is the large GOT case. If this is a reference to an | |
4958 | external symbol, and there is no constant, we want | |
4959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4960 | addu $tempreg,$tempreg,$gp | |
4961 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4962 | or if tempreg is PIC_CALL_REG |
4963 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4964 | addu $tempreg,$tempreg,$gp | |
4965 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4966 | For a local symbol, we want |
4967 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4968 | nop | |
4969 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4970 | ||
4971 | If we have a small constant, and this is a reference to | |
4972 | an external symbol, we want | |
4973 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4974 | addu $tempreg,$tempreg,$gp | |
4975 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4976 | nop | |
4977 | addiu $tempreg,$tempreg,<constant> | |
4978 | For a local symbol, we want | |
4979 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4980 | nop | |
4981 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4982 | ||
4983 | If we have a large constant, and this is a reference to | |
4984 | an external symbol, we want | |
4985 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4986 | addu $tempreg,$tempreg,$gp | |
4987 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4988 | lui $at,<hiconstant> | |
4989 | addiu $at,$at,<loconstant> | |
4990 | addu $tempreg,$tempreg,$at | |
4991 | For a local symbol, we want | |
4992 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4993 | lui $at,<hiconstant> | |
4994 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4995 | addu $tempreg,$tempreg,$at | |
438c16b8 TS |
4996 | |
4997 | For NewABI, we want for data addresses | |
4998 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4999 | If tempreg is PIC_CALL_REG pointing to a external symbol, we want | |
5000 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5001 | */ | |
5002 | if (HAVE_NEWABI) | |
5003 | { | |
5004 | int reloc_type = (tempreg == PIC_CALL_REG | |
5005 | ? BFD_RELOC_MIPS_CALL16 | |
5006 | : BFD_RELOC_MIPS_GOT_DISP); | |
5007 | ||
5008 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5009 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5010 | "t,o(b)", tempreg, reloc_type, mips_gp_register); | |
5011 | ||
5012 | if (breg != 0) | |
5013 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5014 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5015 | "d,v,t", treg, tempreg, breg); | |
5016 | ||
5017 | if (! used_at) | |
5018 | return; | |
5019 | ||
5020 | break; | |
5021 | } | |
252b5132 RH |
5022 | expr1.X_add_number = offset_expr.X_add_number; |
5023 | offset_expr.X_add_number = 0; | |
5024 | frag_grow (52); | |
f7ea7ef2 | 5025 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5026 | gpdel = 4; |
5027 | else | |
5028 | gpdel = 0; | |
9117d219 NC |
5029 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5030 | { | |
5031 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5032 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5033 | } | |
252b5132 | 5034 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5035 | tempreg, lui_reloc_type); |
252b5132 | 5036 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 5037 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5038 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5039 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 5040 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 5041 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5042 | if (expr1.X_add_number == 0) |
5043 | { | |
5044 | int off; | |
5045 | ||
5046 | if (breg == 0) | |
5047 | off = 0; | |
5048 | else | |
5049 | { | |
5050 | /* We're going to put in an addu instruction using | |
5051 | tempreg, so we may as well insert the nop right | |
5052 | now. */ | |
5053 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5054 | "nop", ""); | |
5055 | off = 4; | |
5056 | } | |
5057 | ||
5058 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5059 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5060 | 8 + gpdel, 0, | |
5061 | (breg == 0 | |
5062 | ? mips_opts.warn_about_macros | |
5063 | : 0)), | |
c4e7957c | 5064 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5065 | } |
5066 | else if (expr1.X_add_number >= -0x8000 | |
5067 | && expr1.X_add_number < 0x8000) | |
5068 | { | |
5069 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5070 | "nop", ""); | |
5071 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5072 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5073 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5074 | ||
5075 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5076 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5077 | (breg == 0 | |
5078 | ? mips_opts.warn_about_macros | |
5079 | : 0)), | |
c4e7957c | 5080 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5081 | } |
5082 | else | |
5083 | { | |
5084 | int adj, dreg; | |
5085 | ||
5086 | /* If we are going to add in a base register, and the | |
5087 | target register and the base register are the same, | |
5088 | then we are using AT as a temporary register. Since | |
5089 | we want to load the constant into AT, we add our | |
5090 | current AT (from the global offset table) and the | |
5091 | register into the register now, and pretend we were | |
5092 | not using a base register. */ | |
5093 | if (breg != treg) | |
5094 | { | |
5095 | adj = 0; | |
5096 | dreg = tempreg; | |
5097 | } | |
5098 | else | |
5099 | { | |
5100 | assert (tempreg == AT); | |
5101 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5102 | "nop", ""); | |
5103 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5104 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5105 | "d,v,t", treg, AT, breg); |
5106 | dreg = treg; | |
5107 | adj = 8; | |
5108 | } | |
5109 | ||
5110 | /* Set mips_optimize around the lui instruction to avoid | |
5111 | inserting an unnecessary nop after the lw. */ | |
5112 | hold_mips_optimize = mips_optimize; | |
5113 | mips_optimize = 2; | |
c4e7957c | 5114 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5115 | mips_optimize = hold_mips_optimize; |
5116 | ||
5117 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5118 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5119 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5120 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5121 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5122 | "d,v,t", dreg, dreg, AT); |
5123 | ||
5124 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5125 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5126 | 8 + gpdel, 0, | |
5127 | (breg == 0 | |
5128 | ? mips_opts.warn_about_macros | |
5129 | : 0)), | |
c4e7957c | 5130 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5131 | |
5132 | used_at = 1; | |
5133 | } | |
5134 | ||
5135 | if (gpdel > 0) | |
5136 | { | |
5137 | /* This is needed because this instruction uses $gp, but | |
5138 | the first instruction on the main stream does not. */ | |
5139 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5140 | p += 4; | |
5141 | } | |
5142 | macro_build (p, &icnt, &offset_expr, | |
4d34fb5f | 5143 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5144 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
5145 | mips_gp_register); | |
252b5132 RH |
5146 | p += 4; |
5147 | if (expr1.X_add_number >= -0x8000 | |
5148 | && expr1.X_add_number < 0x8000) | |
5149 | { | |
5150 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5151 | p += 4; | |
5152 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5153 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5154 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5155 | /* FIXME: If add_number is 0, and there was no base | |
5156 | register, the external symbol case ended with a load, | |
5157 | so if the symbol turns out to not be external, and | |
5158 | the next instruction uses tempreg, an unnecessary nop | |
5159 | will be inserted. */ | |
5160 | } | |
5161 | else | |
5162 | { | |
5163 | if (breg == treg) | |
5164 | { | |
5165 | /* We must add in the base register now, as in the | |
5166 | external symbol case. */ | |
5167 | assert (tempreg == AT); | |
5168 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5169 | p += 4; | |
5170 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5171 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5172 | "d,v,t", treg, AT, breg); |
5173 | p += 4; | |
5174 | tempreg = treg; | |
5175 | /* We set breg to 0 because we have arranged to add | |
5176 | it in in both cases. */ | |
5177 | breg = 0; | |
5178 | } | |
5179 | ||
5180 | macro_build_lui (p, &icnt, &expr1, AT); | |
5181 | p += 4; | |
5182 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5183 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5184 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5185 | p += 4; | |
5186 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5187 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5188 | "d,v,t", tempreg, tempreg, AT); |
5189 | p += 4; | |
5190 | } | |
5191 | } | |
5192 | else if (mips_pic == EMBEDDED_PIC) | |
5193 | { | |
5194 | /* We use | |
cdf6fd85 | 5195 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5196 | */ |
5197 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5198 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
5199 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5200 | } |
5201 | else | |
5202 | abort (); | |
5203 | ||
5204 | if (breg != 0) | |
4d34fb5f TS |
5205 | { |
5206 | char *s; | |
5207 | ||
5208 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5209 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5210 | else | |
5211 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5212 | ||
5213 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5214 | "d,v,t", treg, tempreg, breg); | |
5215 | } | |
252b5132 RH |
5216 | |
5217 | if (! used_at) | |
5218 | return; | |
5219 | ||
5220 | break; | |
5221 | ||
5222 | case M_J_A: | |
5223 | /* The j instruction may not be used in PIC code, since it | |
5224 | requires an absolute address. We convert it to a b | |
5225 | instruction. */ | |
5226 | if (mips_pic == NO_PIC) | |
5227 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5228 | else | |
5229 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5230 | return; | |
5231 | ||
5232 | /* The jal instructions must be handled as macros because when | |
5233 | generating PIC code they expand to multi-instruction | |
5234 | sequences. Normally they are simple instructions. */ | |
5235 | case M_JAL_1: | |
5236 | dreg = RA; | |
5237 | /* Fall through. */ | |
5238 | case M_JAL_2: | |
5239 | if (mips_pic == NO_PIC | |
5240 | || mips_pic == EMBEDDED_PIC) | |
5241 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5242 | "d,s", dreg, sreg); | |
5243 | else if (mips_pic == SVR4_PIC) | |
5244 | { | |
5245 | if (sreg != PIC_CALL_REG) | |
5246 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5247 | |
252b5132 RH |
5248 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5249 | "d,s", dreg, sreg); | |
6478892d | 5250 | if (! HAVE_NEWABI) |
252b5132 | 5251 | { |
6478892d TS |
5252 | if (mips_cprestore_offset < 0) |
5253 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5254 | else | |
5255 | { | |
7a621144 DJ |
5256 | if (! mips_frame_reg_valid) |
5257 | { | |
5258 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5259 | /* Quiet this warning. */ | |
5260 | mips_frame_reg_valid = 1; | |
5261 | } | |
5262 | if (! mips_cprestore_valid) | |
5263 | { | |
5264 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5265 | /* Quiet this warning. */ | |
5266 | mips_cprestore_valid = 1; | |
5267 | } | |
6478892d TS |
5268 | expr1.X_add_number = mips_cprestore_offset; |
5269 | macro_build ((char *) NULL, &icnt, &expr1, | |
5270 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
c9914766 TS |
5271 | mips_gp_register, (int) BFD_RELOC_LO16, |
5272 | mips_frame_reg); | |
6478892d | 5273 | } |
252b5132 RH |
5274 | } |
5275 | } | |
5276 | else | |
5277 | abort (); | |
5278 | ||
5279 | return; | |
5280 | ||
5281 | case M_JAL_A: | |
5282 | if (mips_pic == NO_PIC) | |
5283 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5284 | else if (mips_pic == SVR4_PIC) | |
5285 | { | |
f9419b05 TS |
5286 | char *p; |
5287 | ||
252b5132 RH |
5288 | /* If this is a reference to an external symbol, and we are |
5289 | using a small GOT, we want | |
5290 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5291 | nop | |
f9419b05 | 5292 | jalr $ra,$25 |
252b5132 RH |
5293 | nop |
5294 | lw $gp,cprestore($sp) | |
5295 | The cprestore value is set using the .cprestore | |
5296 | pseudo-op. If we are using a big GOT, we want | |
5297 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5298 | addu $25,$25,$gp | |
5299 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5300 | nop | |
f9419b05 | 5301 | jalr $ra,$25 |
252b5132 RH |
5302 | nop |
5303 | lw $gp,cprestore($sp) | |
5304 | If the symbol is not external, we want | |
5305 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5306 | nop | |
5307 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5308 | jalr $ra,$25 |
252b5132 | 5309 | nop |
438c16b8 TS |
5310 | lw $gp,cprestore($sp) |
5311 | For NewABI, we want | |
5312 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5313 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) | |
5314 | */ | |
5315 | if (HAVE_NEWABI) | |
252b5132 RH |
5316 | { |
5317 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5318 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 | 5319 | "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5320 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
5321 | macro_build_jalr (icnt, &offset_expr); | |
252b5132 RH |
5322 | } |
5323 | else | |
5324 | { | |
438c16b8 TS |
5325 | frag_grow (40); |
5326 | if (! mips_big_got) | |
5327 | { | |
5328 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5329 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5330 | "t,o(b)", PIC_CALL_REG, | |
5331 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
5332 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5333 | "nop", ""); | |
5334 | p = frag_var (rs_machine_dependent, 4, 0, | |
5335 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5336 | offset_expr.X_add_symbol, 0, NULL); | |
5337 | } | |
252b5132 | 5338 | else |
252b5132 | 5339 | { |
438c16b8 TS |
5340 | int gpdel; |
5341 | ||
5342 | if (reg_needs_delay (mips_gp_register)) | |
5343 | gpdel = 4; | |
5344 | else | |
5345 | gpdel = 0; | |
5346 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5347 | "t,u", PIC_CALL_REG, | |
5348 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5349 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5350 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5351 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, | |
5352 | mips_gp_register); | |
5353 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5354 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5355 | "t,o(b)", PIC_CALL_REG, | |
5356 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5357 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5358 | "nop", ""); | |
5359 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5360 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5361 | 8 + gpdel, 0, 0), | |
5362 | offset_expr.X_add_symbol, 0, NULL); | |
5363 | if (gpdel > 0) | |
5364 | { | |
5365 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5366 | p += 4; | |
5367 | } | |
5368 | macro_build (p, &icnt, &offset_expr, | |
5369 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5370 | "t,o(b)", PIC_CALL_REG, | |
5371 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5372 | p += 4; | |
252b5132 RH |
5373 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5374 | p += 4; | |
5375 | } | |
5376 | macro_build (p, &icnt, &offset_expr, | |
438c16b8 TS |
5377 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
5378 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
5379 | (int) BFD_RELOC_LO16); | |
5380 | macro_build_jalr (icnt, &offset_expr); | |
5381 | ||
6478892d TS |
5382 | if (mips_cprestore_offset < 0) |
5383 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5384 | else | |
5385 | { | |
7a621144 DJ |
5386 | if (! mips_frame_reg_valid) |
5387 | { | |
5388 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5389 | /* Quiet this warning. */ | |
5390 | mips_frame_reg_valid = 1; | |
5391 | } | |
5392 | if (! mips_cprestore_valid) | |
5393 | { | |
5394 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5395 | /* Quiet this warning. */ | |
5396 | mips_cprestore_valid = 1; | |
5397 | } | |
6478892d TS |
5398 | if (mips_opts.noreorder) |
5399 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5400 | "nop", ""); |
6478892d TS |
5401 | expr1.X_add_number = mips_cprestore_offset; |
5402 | macro_build ((char *) NULL, &icnt, &expr1, | |
5403 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
c9914766 TS |
5404 | mips_gp_register, (int) BFD_RELOC_LO16, |
5405 | mips_frame_reg); | |
6478892d | 5406 | } |
252b5132 RH |
5407 | } |
5408 | } | |
5409 | else if (mips_pic == EMBEDDED_PIC) | |
5410 | { | |
5411 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5412 | /* The linker may expand the call to a longer sequence which | |
5413 | uses $at, so we must break rather than return. */ | |
5414 | break; | |
5415 | } | |
5416 | else | |
5417 | abort (); | |
5418 | ||
5419 | return; | |
5420 | ||
5421 | case M_LB_AB: | |
5422 | s = "lb"; | |
5423 | goto ld; | |
5424 | case M_LBU_AB: | |
5425 | s = "lbu"; | |
5426 | goto ld; | |
5427 | case M_LH_AB: | |
5428 | s = "lh"; | |
5429 | goto ld; | |
5430 | case M_LHU_AB: | |
5431 | s = "lhu"; | |
5432 | goto ld; | |
5433 | case M_LW_AB: | |
5434 | s = "lw"; | |
5435 | goto ld; | |
5436 | case M_LWC0_AB: | |
5437 | s = "lwc0"; | |
bdaaa2e1 | 5438 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5439 | coproc = 1; |
5440 | goto ld; | |
5441 | case M_LWC1_AB: | |
5442 | s = "lwc1"; | |
bdaaa2e1 | 5443 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5444 | coproc = 1; |
5445 | goto ld; | |
5446 | case M_LWC2_AB: | |
5447 | s = "lwc2"; | |
bdaaa2e1 | 5448 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5449 | coproc = 1; |
5450 | goto ld; | |
5451 | case M_LWC3_AB: | |
5452 | s = "lwc3"; | |
bdaaa2e1 | 5453 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5454 | coproc = 1; |
5455 | goto ld; | |
5456 | case M_LWL_AB: | |
5457 | s = "lwl"; | |
5458 | lr = 1; | |
5459 | goto ld; | |
5460 | case M_LWR_AB: | |
5461 | s = "lwr"; | |
5462 | lr = 1; | |
5463 | goto ld; | |
5464 | case M_LDC1_AB: | |
ec68c924 | 5465 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5466 | { |
5467 | as_bad (_("opcode not supported on this processor")); | |
5468 | return; | |
5469 | } | |
5470 | s = "ldc1"; | |
bdaaa2e1 | 5471 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5472 | coproc = 1; |
5473 | goto ld; | |
5474 | case M_LDC2_AB: | |
5475 | s = "ldc2"; | |
bdaaa2e1 | 5476 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5477 | coproc = 1; |
5478 | goto ld; | |
5479 | case M_LDC3_AB: | |
5480 | s = "ldc3"; | |
bdaaa2e1 | 5481 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5482 | coproc = 1; |
5483 | goto ld; | |
5484 | case M_LDL_AB: | |
5485 | s = "ldl"; | |
5486 | lr = 1; | |
5487 | goto ld; | |
5488 | case M_LDR_AB: | |
5489 | s = "ldr"; | |
5490 | lr = 1; | |
5491 | goto ld; | |
5492 | case M_LL_AB: | |
5493 | s = "ll"; | |
5494 | goto ld; | |
5495 | case M_LLD_AB: | |
5496 | s = "lld"; | |
5497 | goto ld; | |
5498 | case M_LWU_AB: | |
5499 | s = "lwu"; | |
5500 | ld: | |
5501 | if (breg == treg || coproc || lr) | |
5502 | { | |
5503 | tempreg = AT; | |
5504 | used_at = 1; | |
5505 | } | |
5506 | else | |
5507 | { | |
5508 | tempreg = treg; | |
5509 | used_at = 0; | |
5510 | } | |
5511 | goto ld_st; | |
5512 | case M_SB_AB: | |
5513 | s = "sb"; | |
5514 | goto st; | |
5515 | case M_SH_AB: | |
5516 | s = "sh"; | |
5517 | goto st; | |
5518 | case M_SW_AB: | |
5519 | s = "sw"; | |
5520 | goto st; | |
5521 | case M_SWC0_AB: | |
5522 | s = "swc0"; | |
bdaaa2e1 | 5523 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5524 | coproc = 1; |
5525 | goto st; | |
5526 | case M_SWC1_AB: | |
5527 | s = "swc1"; | |
bdaaa2e1 | 5528 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5529 | coproc = 1; |
5530 | goto st; | |
5531 | case M_SWC2_AB: | |
5532 | s = "swc2"; | |
bdaaa2e1 | 5533 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5534 | coproc = 1; |
5535 | goto st; | |
5536 | case M_SWC3_AB: | |
5537 | s = "swc3"; | |
bdaaa2e1 | 5538 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5539 | coproc = 1; |
5540 | goto st; | |
5541 | case M_SWL_AB: | |
5542 | s = "swl"; | |
5543 | goto st; | |
5544 | case M_SWR_AB: | |
5545 | s = "swr"; | |
5546 | goto st; | |
5547 | case M_SC_AB: | |
5548 | s = "sc"; | |
5549 | goto st; | |
5550 | case M_SCD_AB: | |
5551 | s = "scd"; | |
5552 | goto st; | |
5553 | case M_SDC1_AB: | |
ec68c924 | 5554 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5555 | { |
5556 | as_bad (_("opcode not supported on this processor")); | |
5557 | return; | |
5558 | } | |
5559 | s = "sdc1"; | |
5560 | coproc = 1; | |
bdaaa2e1 | 5561 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5562 | goto st; |
5563 | case M_SDC2_AB: | |
5564 | s = "sdc2"; | |
bdaaa2e1 | 5565 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5566 | coproc = 1; |
5567 | goto st; | |
5568 | case M_SDC3_AB: | |
5569 | s = "sdc3"; | |
bdaaa2e1 | 5570 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5571 | coproc = 1; |
5572 | goto st; | |
5573 | case M_SDL_AB: | |
5574 | s = "sdl"; | |
5575 | goto st; | |
5576 | case M_SDR_AB: | |
5577 | s = "sdr"; | |
5578 | st: | |
5579 | tempreg = AT; | |
5580 | used_at = 1; | |
5581 | ld_st: | |
bdaaa2e1 | 5582 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5583 | if (mask == M_LWC1_AB |
5584 | || mask == M_SWC1_AB | |
5585 | || mask == M_LDC1_AB | |
5586 | || mask == M_SDC1_AB | |
5587 | || mask == M_L_DAB | |
5588 | || mask == M_S_DAB) | |
5589 | fmt = "T,o(b)"; | |
5590 | else if (coproc) | |
5591 | fmt = "E,o(b)"; | |
5592 | else | |
5593 | fmt = "t,o(b)"; | |
5594 | ||
afdbd6d0 CD |
5595 | /* For embedded PIC, we allow loads where the offset is calculated |
5596 | by subtracting a symbol in the current segment from an unknown | |
5597 | symbol, relative to a base register, e.g.: | |
5598 | <op> $treg, <sym>-<localsym>($breg) | |
5599 | This is used by the compiler for switch statements. */ | |
76b3015f | 5600 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5601 | && offset_expr.X_op == O_subtract |
5602 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5603 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5604 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5605 | && (S_GET_SEGMENT | |
5606 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5607 | ->X_add_symbol) | |
5608 | == now_seg))) | |
5609 | && breg != 0 | |
5610 | && (offset_expr.X_add_number == 0 | |
5611 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5612 | { | |
5613 | /* For this case, we output the instructions: | |
5614 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5615 | addiu $tempreg,$tempreg,$breg | |
5616 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5617 | If the relocation would fit entirely in 16 bits, it would be | |
5618 | nice to emit: | |
5619 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5620 | instead, but that seems quite difficult. */ | |
5621 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5622 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5624 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5625 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5626 | ? "addu" : "daddu"), | |
5627 | "d,v,t", tempreg, tempreg, breg); | |
5628 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5629 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5630 | if (! used_at) | |
5631 | return; | |
5632 | break; | |
5633 | } | |
5634 | ||
252b5132 RH |
5635 | if (offset_expr.X_op != O_constant |
5636 | && offset_expr.X_op != O_symbol) | |
5637 | { | |
5638 | as_bad (_("expression too complex")); | |
5639 | offset_expr.X_op = O_constant; | |
5640 | } | |
5641 | ||
5642 | /* A constant expression in PIC code can be handled just as it | |
5643 | is in non PIC code. */ | |
5644 | if (mips_pic == NO_PIC | |
5645 | || offset_expr.X_op == O_constant) | |
5646 | { | |
f9419b05 TS |
5647 | char *p; |
5648 | ||
252b5132 RH |
5649 | /* If this is a reference to a GP relative symbol, and there |
5650 | is no base register, we want | |
cdf6fd85 | 5651 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5652 | Otherwise, if there is no base register, we want |
5653 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5654 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5655 | If we have a constant, we need two instructions anyhow, | |
5656 | so we always use the latter form. | |
5657 | ||
5658 | If we have a base register, and this is a reference to a | |
5659 | GP relative symbol, we want | |
5660 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5661 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5662 | Otherwise we want |
5663 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5664 | addu $tempreg,$tempreg,$breg | |
5665 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5666 | With a constant we always use the latter case. |
76b3015f | 5667 | |
d6bc6245 TS |
5668 | With 64bit address space and no base register and $at usable, |
5669 | we want | |
5670 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5671 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5672 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5673 | dsll32 $tempreg,0 | |
5674 | daddu $tempreg,$at | |
5675 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5676 | If we have a base register, we want | |
5677 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5678 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5679 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5680 | daddu $at,$breg | |
5681 | dsll32 $tempreg,0 | |
5682 | daddu $tempreg,$at | |
5683 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5684 | ||
5685 | Without $at we can't generate the optimal path for superscalar | |
5686 | processors here since this would require two temporary registers. | |
5687 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5688 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5689 | dsll $tempreg,16 | |
5690 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5691 | dsll $tempreg,16 | |
5692 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5693 | If we have a base register, we want | |
5694 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5695 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5696 | dsll $tempreg,16 | |
5697 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5698 | dsll $tempreg,16 | |
5699 | daddu $tempreg,$tempreg,$breg | |
5700 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5701 | |
5702 | If we have 64-bit addresses, as an optimization, for | |
5703 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5704 | addresses) we fall back to the 32-bit address generation | |
5705 | mechanism since it is more efficient. This code should | |
5706 | probably attempt to generate 64-bit constants more | |
5707 | efficiently in general. | |
d6bc6245 | 5708 | */ |
6373ee54 CD |
5709 | if (HAVE_64BIT_ADDRESSES |
5710 | && !(offset_expr.X_op == O_constant | |
5711 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number))) | |
d6bc6245 TS |
5712 | { |
5713 | p = NULL; | |
5714 | ||
5715 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5716 | hold the data for such large chunks. */ | |
5717 | ||
5718 | if (used_at == 0) | |
5719 | { | |
5720 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5721 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5722 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5723 | AT, (int) BFD_RELOC_HI16_S); | |
5724 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5725 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5726 | if (breg != 0) | |
2396cfb9 TS |
5727 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5728 | "d,v,t", AT, AT, breg); | |
5729 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5730 | "d,w,<", tempreg, tempreg, 0); | |
5731 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5732 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5733 | macro_build (p, &icnt, &offset_expr, s, |
5734 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5735 | used_at = 1; | |
5736 | } | |
5737 | else | |
5738 | { | |
5739 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5740 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5741 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5742 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5743 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5744 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5745 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5746 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5747 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5748 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5749 | if (breg != 0) |
2396cfb9 TS |
5750 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5751 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5752 | macro_build (p, &icnt, &offset_expr, s, |
5753 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5754 | } | |
5755 | ||
5756 | return; | |
5757 | } | |
76b3015f | 5758 | |
252b5132 RH |
5759 | if (breg == 0) |
5760 | { | |
e7d556df | 5761 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5762 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5763 | p = NULL; | |
5764 | else | |
5765 | { | |
5766 | frag_grow (20); | |
5767 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
5768 | treg, (int) BFD_RELOC_GPREL16, |
5769 | mips_gp_register); | |
252b5132 RH |
5770 | p = frag_var (rs_machine_dependent, 8, 0, |
5771 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5772 | (mips_opts.warn_about_macros | |
5773 | || (used_at | |
5774 | && mips_opts.noat))), | |
956cd1d6 | 5775 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5776 | used_at = 0; |
5777 | } | |
5778 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5779 | if (p != NULL) | |
5780 | p += 4; | |
5781 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5782 | (int) BFD_RELOC_LO16, tempreg); | |
5783 | } | |
5784 | else | |
5785 | { | |
e7d556df | 5786 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5787 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5788 | p = NULL; | |
5789 | else | |
5790 | { | |
5791 | frag_grow (28); | |
5792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5793 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5794 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5795 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5796 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5797 | p = frag_var (rs_machine_dependent, 12, 0, |
5798 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5799 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5800 | } |
5801 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5802 | if (p != NULL) | |
5803 | p += 4; | |
5804 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5805 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5806 | "d,v,t", tempreg, tempreg, breg); |
5807 | if (p != NULL) | |
5808 | p += 4; | |
5809 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5810 | (int) BFD_RELOC_LO16, tempreg); | |
5811 | } | |
5812 | } | |
5813 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5814 | { | |
f9419b05 TS |
5815 | char *p; |
5816 | ||
252b5132 RH |
5817 | /* If this is a reference to an external symbol, we want |
5818 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5819 | nop | |
5820 | <op> $treg,0($tempreg) | |
5821 | Otherwise we want | |
5822 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5823 | nop | |
5824 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5825 | <op> $treg,0($tempreg) | |
5826 | If there is a base register, we add it to $tempreg before | |
5827 | the <op>. If there is a constant, we stick it in the | |
5828 | <op> instruction. We don't handle constants larger than | |
5829 | 16 bits, because we have no way to load the upper 16 bits | |
5830 | (actually, we could handle them for the subset of cases | |
5831 | in which we are not using $at). */ | |
5832 | assert (offset_expr.X_op == O_symbol); | |
5833 | expr1.X_add_number = offset_expr.X_add_number; | |
5834 | offset_expr.X_add_number = 0; | |
5835 | if (expr1.X_add_number < -0x8000 | |
5836 | || expr1.X_add_number >= 0x8000) | |
5837 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5838 | frag_grow (20); | |
5839 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5840 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
5841 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 5842 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 5843 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5844 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5845 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5846 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5847 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5848 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5849 | if (breg != 0) | |
5850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5851 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5852 | "d,v,t", tempreg, tempreg, breg); |
5853 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5854 | (int) BFD_RELOC_LO16, tempreg); | |
5855 | } | |
5856 | else if (mips_pic == SVR4_PIC) | |
5857 | { | |
5858 | int gpdel; | |
f9419b05 | 5859 | char *p; |
252b5132 RH |
5860 | |
5861 | /* If this is a reference to an external symbol, we want | |
5862 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5863 | addu $tempreg,$tempreg,$gp | |
5864 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5865 | <op> $treg,0($tempreg) | |
5866 | Otherwise we want | |
5867 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5868 | nop | |
5869 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5870 | <op> $treg,0($tempreg) | |
5871 | If there is a base register, we add it to $tempreg before | |
5872 | the <op>. If there is a constant, we stick it in the | |
5873 | <op> instruction. We don't handle constants larger than | |
5874 | 16 bits, because we have no way to load the upper 16 bits | |
5875 | (actually, we could handle them for the subset of cases | |
438c16b8 TS |
5876 | in which we are not using $at). |
5877 | ||
5878 | For NewABI, we want | |
5879 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5880 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5881 | <op> $treg,0($tempreg) | |
5882 | */ | |
252b5132 RH |
5883 | assert (offset_expr.X_op == O_symbol); |
5884 | expr1.X_add_number = offset_expr.X_add_number; | |
5885 | offset_expr.X_add_number = 0; | |
5886 | if (expr1.X_add_number < -0x8000 | |
5887 | || expr1.X_add_number >= 0x8000) | |
5888 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
438c16b8 TS |
5889 | if (HAVE_NEWABI) |
5890 | { | |
5891 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5892 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5893 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
5894 | mips_gp_register); | |
5895 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5896 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
5897 | "t,r,j", tempreg, tempreg, | |
5898 | BFD_RELOC_MIPS_GOT_OFST); | |
5899 | if (breg != 0) | |
5900 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5901 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5902 | "d,v,t", tempreg, tempreg, breg); | |
5903 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5904 | (int) BFD_RELOC_LO16, tempreg); | |
5905 | ||
5906 | if (! used_at) | |
5907 | return; | |
5908 | ||
5909 | break; | |
5910 | } | |
f7ea7ef2 | 5911 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5912 | gpdel = 4; |
5913 | else | |
5914 | gpdel = 0; | |
5915 | frag_grow (36); | |
5916 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5917 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5918 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5919 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5920 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5921 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 5922 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5923 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5924 | tempreg); | |
5925 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5926 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 5927 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5928 | if (gpdel > 0) |
5929 | { | |
5930 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5931 | p += 4; | |
5932 | } | |
5933 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5934 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5935 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
5936 | mips_gp_register); | |
252b5132 RH |
5937 | p += 4; |
5938 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5939 | p += 4; | |
5940 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5941 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5942 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5943 | if (breg != 0) | |
5944 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5945 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5946 | "d,v,t", tempreg, tempreg, breg); |
5947 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5948 | (int) BFD_RELOC_LO16, tempreg); | |
5949 | } | |
5950 | else if (mips_pic == EMBEDDED_PIC) | |
5951 | { | |
5952 | /* If there is no base register, we want | |
cdf6fd85 | 5953 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5954 | If there is a base register, we want |
5955 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5956 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5957 | */ |
5958 | assert (offset_expr.X_op == O_symbol); | |
5959 | if (breg == 0) | |
5960 | { | |
5961 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 5962 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
5963 | used_at = 0; |
5964 | } | |
5965 | else | |
5966 | { | |
5967 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5968 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5969 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5970 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5971 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5972 | } |
5973 | } | |
5974 | else | |
5975 | abort (); | |
5976 | ||
5977 | if (! used_at) | |
5978 | return; | |
5979 | ||
5980 | break; | |
5981 | ||
5982 | case M_LI: | |
5983 | case M_LI_S: | |
5984 | load_register (&icnt, treg, &imm_expr, 0); | |
5985 | return; | |
5986 | ||
5987 | case M_DLI: | |
5988 | load_register (&icnt, treg, &imm_expr, 1); | |
5989 | return; | |
5990 | ||
5991 | case M_LI_SS: | |
5992 | if (imm_expr.X_op == O_constant) | |
5993 | { | |
5994 | load_register (&icnt, AT, &imm_expr, 0); | |
5995 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5996 | "mtc1", "t,G", AT, treg); | |
5997 | break; | |
5998 | } | |
5999 | else | |
6000 | { | |
6001 | assert (offset_expr.X_op == O_symbol | |
6002 | && strcmp (segment_name (S_GET_SEGMENT | |
6003 | (offset_expr.X_add_symbol)), | |
6004 | ".lit4") == 0 | |
6005 | && offset_expr.X_add_number == 0); | |
6006 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 6007 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6008 | return; |
6009 | } | |
6010 | ||
6011 | case M_LI_D: | |
ca4e0257 RS |
6012 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6013 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6014 | order 32 bits of the value and the low order 32 bits are either | |
6015 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6016 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6017 | { | |
ca4e0257 | 6018 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6019 | load_register (&icnt, treg, &imm_expr, 1); |
6020 | else | |
6021 | { | |
6022 | int hreg, lreg; | |
6023 | ||
6024 | if (target_big_endian) | |
6025 | { | |
6026 | hreg = treg; | |
6027 | lreg = treg + 1; | |
6028 | } | |
6029 | else | |
6030 | { | |
6031 | hreg = treg + 1; | |
6032 | lreg = treg; | |
6033 | } | |
6034 | ||
6035 | if (hreg <= 31) | |
6036 | load_register (&icnt, hreg, &imm_expr, 0); | |
6037 | if (lreg <= 31) | |
6038 | { | |
6039 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6040 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6041 | else |
6042 | { | |
6043 | assert (offset_expr.X_op == O_constant); | |
6044 | load_register (&icnt, lreg, &offset_expr, 0); | |
6045 | } | |
6046 | } | |
6047 | } | |
6048 | return; | |
6049 | } | |
6050 | ||
6051 | /* We know that sym is in the .rdata section. First we get the | |
6052 | upper 16 bits of the address. */ | |
6053 | if (mips_pic == NO_PIC) | |
6054 | { | |
956cd1d6 | 6055 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6056 | } |
6057 | else if (mips_pic == SVR4_PIC) | |
6058 | { | |
6059 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6060 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6061 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6062 | mips_gp_register); | |
252b5132 RH |
6063 | } |
6064 | else if (mips_pic == EMBEDDED_PIC) | |
6065 | { | |
6066 | /* For embedded PIC we pick up the entire address off $gp in | |
6067 | a single instruction. */ | |
6068 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6069 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
6070 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6071 | offset_expr.X_op = O_constant; |
6072 | offset_expr.X_add_number = 0; | |
6073 | } | |
6074 | else | |
6075 | abort (); | |
bdaaa2e1 | 6076 | |
252b5132 | 6077 | /* Now we load the register(s). */ |
ca4e0257 | 6078 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6079 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6080 | treg, (int) BFD_RELOC_LO16, AT); | |
6081 | else | |
6082 | { | |
6083 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6084 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6085 | if (treg != RA) |
252b5132 RH |
6086 | { |
6087 | /* FIXME: How in the world do we deal with the possible | |
6088 | overflow here? */ | |
6089 | offset_expr.X_add_number += 4; | |
6090 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6091 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6092 | } | |
6093 | } | |
6094 | ||
6095 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6096 | does not become a variant frag. */ | |
6097 | frag_wane (frag_now); | |
6098 | frag_new (0); | |
6099 | ||
6100 | break; | |
6101 | ||
6102 | case M_LI_DD: | |
ca4e0257 RS |
6103 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6104 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6105 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6106 | the value and the low order 32 bits are either zero or in | |
6107 | OFFSET_EXPR. */ | |
252b5132 RH |
6108 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6109 | { | |
ca4e0257 RS |
6110 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6111 | if (HAVE_64BIT_FPRS) | |
6112 | { | |
6113 | assert (HAVE_64BIT_GPRS); | |
6114 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6115 | "dmtc1", "t,S", AT, treg); | |
6116 | } | |
252b5132 RH |
6117 | else |
6118 | { | |
6119 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6120 | "mtc1", "t,G", AT, treg + 1); | |
6121 | if (offset_expr.X_op == O_absent) | |
6122 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6123 | "mtc1", "t,G", 0, treg); | |
6124 | else | |
6125 | { | |
6126 | assert (offset_expr.X_op == O_constant); | |
6127 | load_register (&icnt, AT, &offset_expr, 0); | |
6128 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6129 | "mtc1", "t,G", AT, treg); | |
6130 | } | |
6131 | } | |
6132 | break; | |
6133 | } | |
6134 | ||
6135 | assert (offset_expr.X_op == O_symbol | |
6136 | && offset_expr.X_add_number == 0); | |
6137 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6138 | if (strcmp (s, ".lit8") == 0) | |
6139 | { | |
e7af610e | 6140 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6141 | { |
6142 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6143 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6144 | mips_gp_register); | |
252b5132 RH |
6145 | return; |
6146 | } | |
c9914766 | 6147 | breg = mips_gp_register; |
252b5132 RH |
6148 | r = BFD_RELOC_MIPS_LITERAL; |
6149 | goto dob; | |
6150 | } | |
6151 | else | |
6152 | { | |
6153 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6154 | if (mips_pic == SVR4_PIC) | |
6155 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6156 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6157 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6158 | mips_gp_register); | |
252b5132 RH |
6159 | else |
6160 | { | |
6161 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6162 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6163 | } |
bdaaa2e1 | 6164 | |
e7af610e | 6165 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6166 | { |
6167 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6168 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6169 | ||
6170 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6171 | that this does not become a variant frag. */ | |
6172 | frag_wane (frag_now); | |
6173 | frag_new (0); | |
6174 | ||
6175 | break; | |
6176 | } | |
6177 | breg = AT; | |
6178 | r = BFD_RELOC_LO16; | |
6179 | goto dob; | |
6180 | } | |
6181 | ||
6182 | case M_L_DOB: | |
ec68c924 | 6183 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6184 | { |
6185 | as_bad (_("opcode not supported on this processor")); | |
6186 | return; | |
6187 | } | |
6188 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6189 | to adjust when loading from memory. */ | |
6190 | r = BFD_RELOC_LO16; | |
6191 | dob: | |
e7af610e | 6192 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6193 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6194 | target_big_endian ? treg + 1 : treg, | |
6195 | (int) r, breg); | |
6196 | /* FIXME: A possible overflow which I don't know how to deal | |
6197 | with. */ | |
6198 | offset_expr.X_add_number += 4; | |
6199 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6200 | target_big_endian ? treg : treg + 1, | |
6201 | (int) r, breg); | |
6202 | ||
6203 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6204 | does not become a variant frag. */ | |
6205 | frag_wane (frag_now); | |
6206 | frag_new (0); | |
6207 | ||
6208 | if (breg != AT) | |
6209 | return; | |
6210 | break; | |
6211 | ||
6212 | case M_L_DAB: | |
6213 | /* | |
6214 | * The MIPS assembler seems to check for X_add_number not | |
6215 | * being double aligned and generating: | |
6216 | * lui at,%hi(foo+1) | |
6217 | * addu at,at,v1 | |
6218 | * addiu at,at,%lo(foo+1) | |
6219 | * lwc1 f2,0(at) | |
6220 | * lwc1 f3,4(at) | |
6221 | * But, the resulting address is the same after relocation so why | |
6222 | * generate the extra instruction? | |
6223 | */ | |
ec68c924 | 6224 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6225 | { |
6226 | as_bad (_("opcode not supported on this processor")); | |
6227 | return; | |
6228 | } | |
bdaaa2e1 | 6229 | /* Itbl support may require additional care here. */ |
252b5132 | 6230 | coproc = 1; |
e7af610e | 6231 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6232 | { |
6233 | s = "ldc1"; | |
6234 | goto ld; | |
6235 | } | |
6236 | ||
6237 | s = "lwc1"; | |
6238 | fmt = "T,o(b)"; | |
6239 | goto ldd_std; | |
6240 | ||
6241 | case M_S_DAB: | |
ec68c924 | 6242 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6243 | { |
6244 | as_bad (_("opcode not supported on this processor")); | |
6245 | return; | |
6246 | } | |
6247 | ||
e7af610e | 6248 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6249 | { |
6250 | s = "sdc1"; | |
6251 | goto st; | |
6252 | } | |
6253 | ||
6254 | s = "swc1"; | |
6255 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6256 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6257 | coproc = 1; |
6258 | goto ldd_std; | |
6259 | ||
6260 | case M_LD_AB: | |
ca4e0257 | 6261 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6262 | { |
6263 | s = "ld"; | |
6264 | goto ld; | |
6265 | } | |
6266 | ||
6267 | s = "lw"; | |
6268 | fmt = "t,o(b)"; | |
6269 | goto ldd_std; | |
6270 | ||
6271 | case M_SD_AB: | |
ca4e0257 | 6272 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6273 | { |
6274 | s = "sd"; | |
6275 | goto st; | |
6276 | } | |
6277 | ||
6278 | s = "sw"; | |
6279 | fmt = "t,o(b)"; | |
6280 | ||
6281 | ldd_std: | |
afdbd6d0 CD |
6282 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6283 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6284 | This is not currently done by the compiler, and assembly coders | |
6285 | writing embedded-pic code can cope. */ | |
6286 | ||
252b5132 RH |
6287 | if (offset_expr.X_op != O_symbol |
6288 | && offset_expr.X_op != O_constant) | |
6289 | { | |
6290 | as_bad (_("expression too complex")); | |
6291 | offset_expr.X_op = O_constant; | |
6292 | } | |
6293 | ||
6294 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6295 | to adjust when loading from memory. We set coproc if we must | |
6296 | load $fn+1 first. */ | |
bdaaa2e1 | 6297 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6298 | if (! target_big_endian) |
6299 | coproc = 0; | |
6300 | ||
6301 | if (mips_pic == NO_PIC | |
6302 | || offset_expr.X_op == O_constant) | |
6303 | { | |
f9419b05 TS |
6304 | char *p; |
6305 | ||
252b5132 | 6306 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6307 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6308 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6309 | If we have a base register, we use this |
6310 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6311 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6312 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6313 | If this is not a GP relative symbol, we want |
6314 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6315 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6316 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6317 | If there is a base register, we add it to $at after the | |
6318 | lui instruction. If there is a constant, we always use | |
6319 | the last case. */ | |
e7d556df | 6320 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6321 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6322 | { | |
6323 | p = NULL; | |
6324 | used_at = 1; | |
6325 | } | |
6326 | else | |
6327 | { | |
6328 | int off; | |
6329 | ||
6330 | if (breg == 0) | |
6331 | { | |
6332 | frag_grow (28); | |
c9914766 | 6333 | tempreg = mips_gp_register; |
252b5132 RH |
6334 | off = 0; |
6335 | used_at = 0; | |
6336 | } | |
6337 | else | |
6338 | { | |
6339 | frag_grow (36); | |
6340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6341 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6342 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6343 | tempreg = AT; |
6344 | off = 4; | |
6345 | used_at = 1; | |
6346 | } | |
6347 | ||
beae10d5 | 6348 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6349 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6350 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6351 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6352 | offset_expr.X_add_number += 4; |
6353 | ||
6354 | /* Set mips_optimize to 2 to avoid inserting an | |
6355 | undesired nop. */ | |
6356 | hold_mips_optimize = mips_optimize; | |
6357 | mips_optimize = 2; | |
beae10d5 | 6358 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6359 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6360 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6361 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6362 | mips_optimize = hold_mips_optimize; |
6363 | ||
6364 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6365 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6366 | used_at && mips_opts.noat), | |
956cd1d6 | 6367 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6368 | |
6369 | /* We just generated two relocs. When tc_gen_reloc | |
6370 | handles this case, it will skip the first reloc and | |
6371 | handle the second. The second reloc already has an | |
6372 | extra addend of 4, which we added above. We must | |
6373 | subtract it out, and then subtract another 4 to make | |
6374 | the first reloc come out right. The second reloc | |
6375 | will come out right because we are going to add 4 to | |
6376 | offset_expr when we build its instruction below. | |
6377 | ||
6378 | If we have a symbol, then we don't want to include | |
6379 | the offset, because it will wind up being included | |
6380 | when we generate the reloc. */ | |
6381 | ||
6382 | if (offset_expr.X_op == O_constant) | |
6383 | offset_expr.X_add_number -= 8; | |
6384 | else | |
6385 | { | |
6386 | offset_expr.X_add_number = -4; | |
6387 | offset_expr.X_op = O_constant; | |
6388 | } | |
6389 | } | |
6390 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6391 | if (p != NULL) | |
6392 | p += 4; | |
6393 | if (breg != 0) | |
6394 | { | |
6395 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6396 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6397 | "d,v,t", AT, breg, AT); |
6398 | if (p != NULL) | |
6399 | p += 4; | |
6400 | } | |
beae10d5 | 6401 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6402 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6403 | coproc ? treg + 1 : treg, | |
6404 | (int) BFD_RELOC_LO16, AT); | |
6405 | if (p != NULL) | |
6406 | p += 4; | |
6407 | /* FIXME: How do we handle overflow here? */ | |
6408 | offset_expr.X_add_number += 4; | |
beae10d5 | 6409 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6410 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6411 | coproc ? treg : treg + 1, | |
6412 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6413 | } |
252b5132 RH |
6414 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6415 | { | |
6416 | int off; | |
6417 | ||
6418 | /* If this is a reference to an external symbol, we want | |
6419 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6420 | nop | |
6421 | <op> $treg,0($at) | |
6422 | <op> $treg+1,4($at) | |
6423 | Otherwise we want | |
6424 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6425 | nop | |
6426 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6427 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6428 | If there is a base register we add it to $at before the | |
6429 | lwc1 instructions. If there is a constant we include it | |
6430 | in the lwc1 instructions. */ | |
6431 | used_at = 1; | |
6432 | expr1.X_add_number = offset_expr.X_add_number; | |
6433 | offset_expr.X_add_number = 0; | |
6434 | if (expr1.X_add_number < -0x8000 | |
6435 | || expr1.X_add_number >= 0x8000 - 4) | |
6436 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6437 | if (breg == 0) | |
6438 | off = 0; | |
6439 | else | |
6440 | off = 4; | |
6441 | frag_grow (24 + off); | |
6442 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6443 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
6444 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6445 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6446 | if (breg != 0) | |
6447 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6448 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6449 | "d,v,t", AT, breg, AT); |
beae10d5 | 6450 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6451 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6452 | coproc ? treg + 1 : treg, | |
6453 | (int) BFD_RELOC_LO16, AT); | |
6454 | expr1.X_add_number += 4; | |
6455 | ||
6456 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6457 | nop. */ | |
6458 | hold_mips_optimize = mips_optimize; | |
6459 | mips_optimize = 2; | |
beae10d5 | 6460 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6461 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6462 | coproc ? treg : treg + 1, | |
6463 | (int) BFD_RELOC_LO16, AT); | |
6464 | mips_optimize = hold_mips_optimize; | |
6465 | ||
6466 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6467 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6468 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6469 | } |
6470 | else if (mips_pic == SVR4_PIC) | |
6471 | { | |
6472 | int gpdel, off; | |
f9419b05 | 6473 | char *p; |
252b5132 RH |
6474 | |
6475 | /* If this is a reference to an external symbol, we want | |
6476 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6477 | addu $at,$at,$gp | |
6478 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6479 | nop | |
6480 | <op> $treg,0($at) | |
6481 | <op> $treg+1,4($at) | |
6482 | Otherwise we want | |
6483 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6484 | nop | |
6485 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6486 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6487 | If there is a base register we add it to $at before the | |
6488 | lwc1 instructions. If there is a constant we include it | |
6489 | in the lwc1 instructions. */ | |
6490 | used_at = 1; | |
6491 | expr1.X_add_number = offset_expr.X_add_number; | |
6492 | offset_expr.X_add_number = 0; | |
6493 | if (expr1.X_add_number < -0x8000 | |
6494 | || expr1.X_add_number >= 0x8000 - 4) | |
6495 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6496 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6497 | gpdel = 4; |
6498 | else | |
6499 | gpdel = 0; | |
6500 | if (breg == 0) | |
6501 | off = 0; | |
6502 | else | |
6503 | off = 4; | |
6504 | frag_grow (56); | |
6505 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6506 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6507 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6508 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6509 | "d,v,t", AT, AT, mips_gp_register); |
252b5132 | 6510 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6511 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6512 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6513 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6514 | if (breg != 0) | |
6515 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6516 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6517 | "d,v,t", AT, breg, AT); |
beae10d5 | 6518 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6519 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6520 | coproc ? treg + 1 : treg, | |
6521 | (int) BFD_RELOC_LO16, AT); | |
6522 | expr1.X_add_number += 4; | |
6523 | ||
6524 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6525 | nop. */ | |
6526 | hold_mips_optimize = mips_optimize; | |
6527 | mips_optimize = 2; | |
beae10d5 | 6528 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6529 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6530 | coproc ? treg : treg + 1, | |
6531 | (int) BFD_RELOC_LO16, AT); | |
6532 | mips_optimize = hold_mips_optimize; | |
6533 | expr1.X_add_number -= 4; | |
6534 | ||
6535 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6536 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6537 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6538 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6539 | if (gpdel > 0) |
6540 | { | |
6541 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6542 | p += 4; | |
6543 | } | |
6544 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6545 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6546 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6547 | mips_gp_register); | |
252b5132 RH |
6548 | p += 4; |
6549 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6550 | p += 4; | |
6551 | if (breg != 0) | |
6552 | { | |
6553 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6554 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6555 | "d,v,t", AT, breg, AT); |
6556 | p += 4; | |
6557 | } | |
beae10d5 | 6558 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6559 | macro_build (p, &icnt, &expr1, s, fmt, |
6560 | coproc ? treg + 1 : treg, | |
6561 | (int) BFD_RELOC_LO16, AT); | |
6562 | p += 4; | |
6563 | expr1.X_add_number += 4; | |
6564 | ||
6565 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6566 | nop. */ | |
6567 | hold_mips_optimize = mips_optimize; | |
6568 | mips_optimize = 2; | |
beae10d5 | 6569 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6570 | macro_build (p, &icnt, &expr1, s, fmt, |
6571 | coproc ? treg : treg + 1, | |
6572 | (int) BFD_RELOC_LO16, AT); | |
6573 | mips_optimize = hold_mips_optimize; | |
6574 | } | |
6575 | else if (mips_pic == EMBEDDED_PIC) | |
6576 | { | |
6577 | /* If there is no base register, we use | |
cdf6fd85 TS |
6578 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6579 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6580 | If we have a base register, we use |
6581 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6582 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6583 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6584 | */ |
6585 | if (breg == 0) | |
6586 | { | |
c9914766 | 6587 | tempreg = mips_gp_register; |
252b5132 RH |
6588 | used_at = 0; |
6589 | } | |
6590 | else | |
6591 | { | |
6592 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6593 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6594 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6595 | tempreg = AT; |
6596 | used_at = 1; | |
6597 | } | |
6598 | ||
beae10d5 | 6599 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6600 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6601 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6602 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6603 | offset_expr.X_add_number += 4; |
beae10d5 | 6604 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6605 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6606 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6607 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6608 | } |
6609 | else | |
6610 | abort (); | |
6611 | ||
6612 | if (! used_at) | |
6613 | return; | |
6614 | ||
6615 | break; | |
6616 | ||
6617 | case M_LD_OB: | |
6618 | s = "lw"; | |
6619 | goto sd_ob; | |
6620 | case M_SD_OB: | |
6621 | s = "sw"; | |
6622 | sd_ob: | |
ca4e0257 | 6623 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6624 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6625 | (int) BFD_RELOC_LO16, breg); | |
6626 | offset_expr.X_add_number += 4; | |
6627 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6628 | (int) BFD_RELOC_LO16, breg); | |
6629 | return; | |
6630 | ||
6631 | /* New code added to support COPZ instructions. | |
6632 | This code builds table entries out of the macros in mip_opcodes. | |
6633 | R4000 uses interlocks to handle coproc delays. | |
6634 | Other chips (like the R3000) require nops to be inserted for delays. | |
6635 | ||
f72c8c98 | 6636 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6637 | In order to fill delay slots for non-interlocked chips, |
6638 | we must have a way to specify delays based on the coprocessor. | |
6639 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6640 | What are the side-effects of the cop instruction? | |
6641 | What cache support might we have and what are its effects? | |
6642 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6643 | What registers are read/set/modified? |
252b5132 RH |
6644 | |
6645 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6646 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6647 | |
6648 | case M_COP0: | |
6649 | s = "c0"; | |
6650 | goto copz; | |
6651 | case M_COP1: | |
6652 | s = "c1"; | |
6653 | goto copz; | |
6654 | case M_COP2: | |
6655 | s = "c2"; | |
6656 | goto copz; | |
6657 | case M_COP3: | |
6658 | s = "c3"; | |
6659 | copz: | |
6660 | /* For now we just do C (same as Cz). The parameter will be | |
6661 | stored in insn_opcode by mips_ip. */ | |
6662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6663 | ip->insn_opcode); | |
6664 | return; | |
6665 | ||
ea1fb5dc RS |
6666 | case M_MOVE: |
6667 | move_register (&icnt, dreg, sreg); | |
6668 | return; | |
6669 | ||
252b5132 RH |
6670 | #ifdef LOSING_COMPILER |
6671 | default: | |
6672 | /* Try and see if this is a new itbl instruction. | |
6673 | This code builds table entries out of the macros in mip_opcodes. | |
6674 | FIXME: For now we just assemble the expression and pass it's | |
6675 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6676 | We may want to have the assembler assemble this value, |
252b5132 RH |
6677 | so that we gain the assembler's knowledge of delay slots, |
6678 | symbols, etc. | |
6679 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6680 | if (itbl_have_entries |
252b5132 | 6681 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6682 | { |
252b5132 RH |
6683 | s = ip->insn_mo->name; |
6684 | s2 = "cop3"; | |
6685 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6686 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6687 | return; | |
beae10d5 | 6688 | } |
252b5132 RH |
6689 | macro2 (ip); |
6690 | return; | |
6691 | } | |
6692 | if (mips_opts.noat) | |
6693 | as_warn (_("Macro used $at after \".set noat\"")); | |
6694 | } | |
bdaaa2e1 | 6695 | |
252b5132 RH |
6696 | static void |
6697 | macro2 (ip) | |
6698 | struct mips_cl_insn *ip; | |
6699 | { | |
6700 | register int treg, sreg, dreg, breg; | |
6701 | int tempreg; | |
6702 | int mask; | |
6703 | int icnt = 0; | |
6704 | int used_at; | |
6705 | expressionS expr1; | |
6706 | const char *s; | |
6707 | const char *s2; | |
6708 | const char *fmt; | |
6709 | int likely = 0; | |
6710 | int dbl = 0; | |
6711 | int coproc = 0; | |
6712 | int lr = 0; | |
6713 | int imm = 0; | |
6714 | int off; | |
6715 | offsetT maxnum; | |
6716 | bfd_reloc_code_real_type r; | |
6717 | char *p; | |
bdaaa2e1 | 6718 | |
252b5132 RH |
6719 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6720 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6721 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6722 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6723 | |
252b5132 RH |
6724 | expr1.X_op = O_constant; |
6725 | expr1.X_op_symbol = NULL; | |
6726 | expr1.X_add_symbol = NULL; | |
6727 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6728 | |
252b5132 RH |
6729 | switch (mask) |
6730 | { | |
6731 | #endif /* LOSING_COMPILER */ | |
6732 | ||
6733 | case M_DMUL: | |
6734 | dbl = 1; | |
6735 | case M_MUL: | |
2396cfb9 TS |
6736 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6737 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6738 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6739 | dreg); | |
252b5132 RH |
6740 | return; |
6741 | ||
6742 | case M_DMUL_I: | |
6743 | dbl = 1; | |
6744 | case M_MUL_I: | |
6745 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6746 | not trying to be that fancy. GCC should do this for us | |
6747 | anyway. */ | |
6748 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6750 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6751 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6752 | dreg); | |
252b5132 RH |
6753 | break; |
6754 | ||
6755 | case M_DMULO_I: | |
6756 | dbl = 1; | |
6757 | case M_MULO_I: | |
6758 | imm = 1; | |
6759 | goto do_mulo; | |
6760 | ||
6761 | case M_DMULO: | |
6762 | dbl = 1; | |
6763 | case M_MULO: | |
6764 | do_mulo: | |
6765 | mips_emit_delays (true); | |
6766 | ++mips_opts.noreorder; | |
6767 | mips_any_noreorder = 1; | |
6768 | if (imm) | |
6769 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6770 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6771 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6772 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6773 | dreg); | |
6774 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 6775 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
6776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6777 | AT); | |
252b5132 | 6778 | if (mips_trap) |
2396cfb9 TS |
6779 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6780 | dreg, AT); | |
252b5132 RH |
6781 | else |
6782 | { | |
6783 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6784 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6785 | AT); | |
6786 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6787 | 0); | |
6788 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6789 | "c", 6); | |
252b5132 RH |
6790 | } |
6791 | --mips_opts.noreorder; | |
2396cfb9 | 6792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6793 | break; |
6794 | ||
6795 | case M_DMULOU_I: | |
6796 | dbl = 1; | |
6797 | case M_MULOU_I: | |
6798 | imm = 1; | |
6799 | goto do_mulou; | |
6800 | ||
6801 | case M_DMULOU: | |
6802 | dbl = 1; | |
6803 | case M_MULOU: | |
6804 | do_mulou: | |
6805 | mips_emit_delays (true); | |
6806 | ++mips_opts.noreorder; | |
6807 | mips_any_noreorder = 1; | |
6808 | if (imm) | |
6809 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6810 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6811 | dbl ? "dmultu" : "multu", |
6812 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6813 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6814 | AT); | |
6815 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6816 | dreg); | |
252b5132 | 6817 | if (mips_trap) |
2396cfb9 TS |
6818 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6819 | AT, 0); | |
252b5132 RH |
6820 | else |
6821 | { | |
6822 | expr1.X_add_number = 8; | |
6823 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6824 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6825 | 0); | |
6826 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6827 | "c", 6); | |
252b5132 RH |
6828 | } |
6829 | --mips_opts.noreorder; | |
6830 | break; | |
6831 | ||
771c7ce4 TS |
6832 | case M_DROL: |
6833 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6834 | "d,v,t", AT, 0, treg); | |
6835 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6836 | "d,t,s", AT, sreg, AT); | |
6837 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6838 | "d,t,s", dreg, sreg, treg); | |
6839 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6840 | "d,v,t", dreg, dreg, AT); | |
6841 | break; | |
6842 | ||
252b5132 | 6843 | case M_ROL: |
2396cfb9 TS |
6844 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6845 | "d,v,t", AT, 0, treg); | |
6846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6847 | "d,t,s", AT, sreg, AT); | |
6848 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6849 | "d,t,s", dreg, sreg, treg); | |
6850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6851 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6852 | break; |
6853 | ||
771c7ce4 TS |
6854 | case M_DROL_I: |
6855 | { | |
6856 | unsigned int rot; | |
6857 | char *l, *r; | |
6858 | ||
6859 | if (imm_expr.X_op != O_constant) | |
6860 | as_bad (_("rotate count too large")); | |
6861 | rot = imm_expr.X_add_number & 0x3f; | |
6862 | if (! rot) | |
6863 | break; | |
6864 | l = (rot < 0x20) ? "dsll" : "dsll32"; | |
6865 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6866 | rot &= 0x1f; | |
6867 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6868 | "d,w,<", AT, sreg, rot); | |
6869 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6870 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6871 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6872 | "d,v,t", dreg, dreg, AT); | |
6873 | } | |
6874 | break; | |
6875 | ||
252b5132 | 6876 | case M_ROL_I: |
771c7ce4 TS |
6877 | { |
6878 | unsigned int rot; | |
6879 | ||
6880 | if (imm_expr.X_op != O_constant) | |
6881 | as_bad (_("rotate count too large")); | |
6882 | rot = imm_expr.X_add_number & 0x1f; | |
6883 | if (! rot) | |
6884 | break; | |
6885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6886 | "d,w,<", AT, sreg, rot); | |
6887 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6888 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6890 | "d,v,t", dreg, dreg, AT); | |
6891 | } | |
6892 | break; | |
6893 | ||
6894 | case M_DROR: | |
6895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6896 | "d,v,t", AT, 0, treg); | |
6897 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6898 | "d,t,s", AT, sreg, AT); | |
6899 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6900 | "d,t,s", dreg, sreg, treg); | |
6901 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6902 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6903 | break; |
6904 | ||
6905 | case M_ROR: | |
2396cfb9 TS |
6906 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6907 | "d,v,t", AT, 0, treg); | |
6908 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6909 | "d,t,s", AT, sreg, AT); | |
6910 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6911 | "d,t,s", dreg, sreg, treg); | |
6912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6913 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6914 | break; |
6915 | ||
771c7ce4 TS |
6916 | case M_DROR_I: |
6917 | { | |
6918 | unsigned int rot; | |
6919 | char *l, *r; | |
6920 | ||
6921 | if (imm_expr.X_op != O_constant) | |
6922 | as_bad (_("rotate count too large")); | |
6923 | rot = imm_expr.X_add_number & 0x3f; | |
6924 | if (! rot) | |
6925 | break; | |
6926 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; | |
6927 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6928 | rot &= 0x1f; | |
6929 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6930 | "d,w,<", AT, sreg, rot); | |
6931 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6932 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6933 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6934 | "d,v,t", dreg, dreg, AT); | |
6935 | } | |
6936 | break; | |
6937 | ||
252b5132 | 6938 | case M_ROR_I: |
771c7ce4 TS |
6939 | { |
6940 | unsigned int rot; | |
6941 | ||
6942 | if (imm_expr.X_op != O_constant) | |
6943 | as_bad (_("rotate count too large")); | |
6944 | rot = imm_expr.X_add_number & 0x1f; | |
6945 | if (! rot) | |
6946 | break; | |
6947 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6948 | "d,w,<", AT, sreg, rot); | |
6949 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6950 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6951 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6952 | "d,v,t", dreg, dreg, AT); | |
6953 | } | |
252b5132 RH |
6954 | break; |
6955 | ||
6956 | case M_S_DOB: | |
ec68c924 | 6957 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6958 | { |
6959 | as_bad (_("opcode not supported on this processor")); | |
6960 | return; | |
6961 | } | |
e7af610e | 6962 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6963 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6964 | to adjust when storing to memory. */ | |
6965 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6966 | target_big_endian ? treg + 1 : treg, | |
6967 | (int) BFD_RELOC_LO16, breg); | |
6968 | offset_expr.X_add_number += 4; | |
6969 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6970 | target_big_endian ? treg : treg + 1, | |
6971 | (int) BFD_RELOC_LO16, breg); | |
6972 | return; | |
6973 | ||
6974 | case M_SEQ: | |
6975 | if (sreg == 0) | |
6976 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6977 | treg, (int) BFD_RELOC_LO16); | |
6978 | else if (treg == 0) | |
6979 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6980 | sreg, (int) BFD_RELOC_LO16); | |
6981 | else | |
6982 | { | |
2396cfb9 TS |
6983 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6984 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
6985 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6986 | dreg, (int) BFD_RELOC_LO16); | |
6987 | } | |
6988 | return; | |
6989 | ||
6990 | case M_SEQ_I: | |
6991 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6992 | { | |
6993 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6994 | sreg, (int) BFD_RELOC_LO16); | |
6995 | return; | |
6996 | } | |
6997 | if (sreg == 0) | |
6998 | { | |
6999 | as_warn (_("Instruction %s: result is always false"), | |
7000 | ip->insn_mo->name); | |
ea1fb5dc | 7001 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7002 | return; |
7003 | } | |
7004 | if (imm_expr.X_op == O_constant | |
7005 | && imm_expr.X_add_number >= 0 | |
7006 | && imm_expr.X_add_number < 0x10000) | |
7007 | { | |
7008 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
7009 | sreg, (int) BFD_RELOC_LO16); | |
7010 | used_at = 0; | |
7011 | } | |
7012 | else if (imm_expr.X_op == O_constant | |
7013 | && imm_expr.X_add_number > -0x8000 | |
7014 | && imm_expr.X_add_number < 0) | |
7015 | { | |
7016 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7017 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7018 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7019 | "t,r,j", dreg, sreg, |
7020 | (int) BFD_RELOC_LO16); | |
7021 | used_at = 0; | |
7022 | } | |
7023 | else | |
7024 | { | |
4d34fb5f | 7025 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7027 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7028 | used_at = 1; |
7029 | } | |
7030 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7031 | (int) BFD_RELOC_LO16); | |
7032 | if (used_at) | |
7033 | break; | |
7034 | return; | |
7035 | ||
7036 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7037 | s = "slt"; | |
7038 | goto sge; | |
7039 | case M_SGEU: | |
7040 | s = "sltu"; | |
7041 | sge: | |
2396cfb9 TS |
7042 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7043 | dreg, sreg, treg); | |
252b5132 RH |
7044 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7045 | (int) BFD_RELOC_LO16); | |
7046 | return; | |
7047 | ||
7048 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7049 | case M_SGEU_I: | |
7050 | if (imm_expr.X_op == O_constant | |
7051 | && imm_expr.X_add_number >= -0x8000 | |
7052 | && imm_expr.X_add_number < 0x8000) | |
7053 | { | |
7054 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7055 | mask == M_SGE_I ? "slti" : "sltiu", | |
7056 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7057 | used_at = 0; | |
7058 | } | |
7059 | else | |
7060 | { | |
4d34fb5f | 7061 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7063 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7064 | AT); | |
252b5132 RH |
7065 | used_at = 1; |
7066 | } | |
7067 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7068 | (int) BFD_RELOC_LO16); | |
7069 | if (used_at) | |
7070 | break; | |
7071 | return; | |
7072 | ||
7073 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7074 | s = "slt"; | |
7075 | goto sgt; | |
7076 | case M_SGTU: | |
7077 | s = "sltu"; | |
7078 | sgt: | |
2396cfb9 TS |
7079 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7080 | dreg, treg, sreg); | |
252b5132 RH |
7081 | return; |
7082 | ||
7083 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7084 | s = "slt"; | |
7085 | goto sgti; | |
7086 | case M_SGTU_I: | |
7087 | s = "sltu"; | |
7088 | sgti: | |
4d34fb5f | 7089 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7090 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7091 | dreg, AT, sreg); | |
252b5132 RH |
7092 | break; |
7093 | ||
2396cfb9 | 7094 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7095 | s = "slt"; |
7096 | goto sle; | |
7097 | case M_SLEU: | |
7098 | s = "sltu"; | |
7099 | sle: | |
2396cfb9 TS |
7100 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7101 | dreg, treg, sreg); | |
252b5132 RH |
7102 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7103 | (int) BFD_RELOC_LO16); | |
7104 | return; | |
7105 | ||
2396cfb9 | 7106 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7107 | s = "slt"; |
7108 | goto slei; | |
7109 | case M_SLEU_I: | |
7110 | s = "sltu"; | |
7111 | slei: | |
4d34fb5f | 7112 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7114 | dreg, AT, sreg); | |
252b5132 RH |
7115 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7116 | (int) BFD_RELOC_LO16); | |
7117 | break; | |
7118 | ||
7119 | case M_SLT_I: | |
7120 | if (imm_expr.X_op == O_constant | |
7121 | && imm_expr.X_add_number >= -0x8000 | |
7122 | && imm_expr.X_add_number < 0x8000) | |
7123 | { | |
7124 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7125 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7126 | return; | |
7127 | } | |
4d34fb5f | 7128 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7129 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7130 | dreg, sreg, AT); | |
252b5132 RH |
7131 | break; |
7132 | ||
7133 | case M_SLTU_I: | |
7134 | if (imm_expr.X_op == O_constant | |
7135 | && imm_expr.X_add_number >= -0x8000 | |
7136 | && imm_expr.X_add_number < 0x8000) | |
7137 | { | |
7138 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7139 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7140 | return; | |
7141 | } | |
4d34fb5f | 7142 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7143 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7144 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7145 | break; |
7146 | ||
7147 | case M_SNE: | |
7148 | if (sreg == 0) | |
2396cfb9 TS |
7149 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7150 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7151 | else if (treg == 0) |
2396cfb9 TS |
7152 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7153 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7154 | else |
7155 | { | |
2396cfb9 TS |
7156 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7157 | "d,v,t", dreg, sreg, treg); | |
7158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7159 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7160 | } |
7161 | return; | |
7162 | ||
7163 | case M_SNE_I: | |
7164 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7165 | { | |
2396cfb9 TS |
7166 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7167 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7168 | return; |
7169 | } | |
7170 | if (sreg == 0) | |
7171 | { | |
7172 | as_warn (_("Instruction %s: result is always true"), | |
7173 | ip->insn_mo->name); | |
7174 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7175 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7176 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7177 | return; | |
7178 | } | |
7179 | if (imm_expr.X_op == O_constant | |
7180 | && imm_expr.X_add_number >= 0 | |
7181 | && imm_expr.X_add_number < 0x10000) | |
7182 | { | |
7183 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7184 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7185 | used_at = 0; | |
7186 | } | |
7187 | else if (imm_expr.X_op == O_constant | |
7188 | && imm_expr.X_add_number > -0x8000 | |
7189 | && imm_expr.X_add_number < 0) | |
7190 | { | |
7191 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7192 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7193 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7194 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7195 | used_at = 0; | |
7196 | } | |
7197 | else | |
7198 | { | |
4d34fb5f | 7199 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7201 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7202 | used_at = 1; |
7203 | } | |
2396cfb9 TS |
7204 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7205 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7206 | if (used_at) |
7207 | break; | |
7208 | return; | |
7209 | ||
7210 | case M_DSUB_I: | |
7211 | dbl = 1; | |
7212 | case M_SUB_I: | |
7213 | if (imm_expr.X_op == O_constant | |
7214 | && imm_expr.X_add_number > -0x8000 | |
7215 | && imm_expr.X_add_number <= 0x8000) | |
7216 | { | |
7217 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7218 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7219 | dbl ? "daddi" : "addi", | |
7220 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7221 | return; | |
7222 | } | |
7223 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7224 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7225 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7226 | break; |
7227 | ||
7228 | case M_DSUBU_I: | |
7229 | dbl = 1; | |
7230 | case M_SUBU_I: | |
7231 | if (imm_expr.X_op == O_constant | |
7232 | && imm_expr.X_add_number > -0x8000 | |
7233 | && imm_expr.X_add_number <= 0x8000) | |
7234 | { | |
7235 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7236 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7237 | dbl ? "daddiu" : "addiu", | |
7238 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7239 | return; | |
7240 | } | |
7241 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7242 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7243 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7244 | break; |
7245 | ||
7246 | case M_TEQ_I: | |
7247 | s = "teq"; | |
7248 | goto trap; | |
7249 | case M_TGE_I: | |
7250 | s = "tge"; | |
7251 | goto trap; | |
7252 | case M_TGEU_I: | |
7253 | s = "tgeu"; | |
7254 | goto trap; | |
7255 | case M_TLT_I: | |
7256 | s = "tlt"; | |
7257 | goto trap; | |
7258 | case M_TLTU_I: | |
7259 | s = "tltu"; | |
7260 | goto trap; | |
7261 | case M_TNE_I: | |
7262 | s = "tne"; | |
7263 | trap: | |
4d34fb5f | 7264 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7265 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7266 | AT); | |
252b5132 RH |
7267 | break; |
7268 | ||
252b5132 | 7269 | case M_TRUNCWS: |
43841e91 | 7270 | case M_TRUNCWD: |
e7af610e | 7271 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7272 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7273 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7274 | ||
7275 | /* | |
7276 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7277 | * or is there a reason for it? | |
7278 | */ | |
7279 | mips_emit_delays (true); | |
7280 | ++mips_opts.noreorder; | |
7281 | mips_any_noreorder = 1; | |
2396cfb9 | 7282 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7283 | treg, RA); |
2396cfb9 | 7284 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7285 | treg, RA); |
2396cfb9 | 7286 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7287 | expr1.X_add_number = 3; |
7288 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7289 | (int) BFD_RELOC_LO16); | |
7290 | expr1.X_add_number = 2; | |
7291 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7292 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7293 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7294 | AT, RA); |
2396cfb9 TS |
7295 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7296 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7297 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7299 | treg, RA); |
2396cfb9 | 7300 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7301 | --mips_opts.noreorder; |
7302 | break; | |
7303 | ||
7304 | case M_ULH: | |
7305 | s = "lb"; | |
7306 | goto ulh; | |
7307 | case M_ULHU: | |
7308 | s = "lbu"; | |
7309 | ulh: | |
7310 | if (offset_expr.X_add_number >= 0x7fff) | |
7311 | as_bad (_("operand overflow")); | |
7312 | /* avoid load delay */ | |
7313 | if (! target_big_endian) | |
f9419b05 | 7314 | ++offset_expr.X_add_number; |
252b5132 RH |
7315 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7316 | (int) BFD_RELOC_LO16, breg); | |
7317 | if (! target_big_endian) | |
f9419b05 | 7318 | --offset_expr.X_add_number; |
252b5132 | 7319 | else |
f9419b05 | 7320 | ++offset_expr.X_add_number; |
252b5132 RH |
7321 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
7322 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7323 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7324 | treg, treg, 8); | |
7325 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7326 | treg, treg, AT); | |
252b5132 RH |
7327 | break; |
7328 | ||
7329 | case M_ULD: | |
7330 | s = "ldl"; | |
7331 | s2 = "ldr"; | |
7332 | off = 7; | |
7333 | goto ulw; | |
7334 | case M_ULW: | |
7335 | s = "lwl"; | |
7336 | s2 = "lwr"; | |
7337 | off = 3; | |
7338 | ulw: | |
7339 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7340 | as_bad (_("operand overflow")); | |
7341 | if (! target_big_endian) | |
7342 | offset_expr.X_add_number += off; | |
7343 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7344 | (int) BFD_RELOC_LO16, breg); | |
7345 | if (! target_big_endian) | |
7346 | offset_expr.X_add_number -= off; | |
7347 | else | |
7348 | offset_expr.X_add_number += off; | |
7349 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7350 | (int) BFD_RELOC_LO16, breg); | |
7351 | return; | |
7352 | ||
7353 | case M_ULD_A: | |
7354 | s = "ldl"; | |
7355 | s2 = "ldr"; | |
7356 | off = 7; | |
7357 | goto ulwa; | |
7358 | case M_ULW_A: | |
7359 | s = "lwl"; | |
7360 | s2 = "lwr"; | |
7361 | off = 3; | |
7362 | ulwa: | |
d6bc6245 | 7363 | used_at = 1; |
c9914766 | 7364 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7365 | if (breg != 0) |
7366 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7367 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7368 | "d,v,t", AT, AT, breg); |
7369 | if (! target_big_endian) | |
7370 | expr1.X_add_number = off; | |
7371 | else | |
7372 | expr1.X_add_number = 0; | |
7373 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7374 | (int) BFD_RELOC_LO16, AT); | |
7375 | if (! target_big_endian) | |
7376 | expr1.X_add_number = 0; | |
7377 | else | |
7378 | expr1.X_add_number = off; | |
7379 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7380 | (int) BFD_RELOC_LO16, AT); | |
7381 | break; | |
7382 | ||
7383 | case M_ULH_A: | |
7384 | case M_ULHU_A: | |
d6bc6245 | 7385 | used_at = 1; |
c9914766 | 7386 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7387 | if (breg != 0) |
7388 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7389 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7390 | "d,v,t", AT, AT, breg); |
7391 | if (target_big_endian) | |
7392 | expr1.X_add_number = 0; | |
7393 | macro_build ((char *) NULL, &icnt, &expr1, | |
7394 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7395 | (int) BFD_RELOC_LO16, AT); | |
7396 | if (target_big_endian) | |
7397 | expr1.X_add_number = 1; | |
7398 | else | |
7399 | expr1.X_add_number = 0; | |
7400 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7401 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7402 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7403 | treg, treg, 8); | |
7404 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7405 | treg, treg, AT); | |
252b5132 RH |
7406 | break; |
7407 | ||
7408 | case M_USH: | |
7409 | if (offset_expr.X_add_number >= 0x7fff) | |
7410 | as_bad (_("operand overflow")); | |
7411 | if (target_big_endian) | |
f9419b05 | 7412 | ++offset_expr.X_add_number; |
252b5132 RH |
7413 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7414 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7415 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7416 | AT, treg, 8); | |
252b5132 | 7417 | if (target_big_endian) |
f9419b05 | 7418 | --offset_expr.X_add_number; |
252b5132 | 7419 | else |
f9419b05 | 7420 | ++offset_expr.X_add_number; |
252b5132 RH |
7421 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7422 | (int) BFD_RELOC_LO16, breg); | |
7423 | break; | |
7424 | ||
7425 | case M_USD: | |
7426 | s = "sdl"; | |
7427 | s2 = "sdr"; | |
7428 | off = 7; | |
7429 | goto usw; | |
7430 | case M_USW: | |
7431 | s = "swl"; | |
7432 | s2 = "swr"; | |
7433 | off = 3; | |
7434 | usw: | |
7435 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7436 | as_bad (_("operand overflow")); | |
7437 | if (! target_big_endian) | |
7438 | offset_expr.X_add_number += off; | |
7439 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7440 | (int) BFD_RELOC_LO16, breg); | |
7441 | if (! target_big_endian) | |
7442 | offset_expr.X_add_number -= off; | |
7443 | else | |
7444 | offset_expr.X_add_number += off; | |
7445 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7446 | (int) BFD_RELOC_LO16, breg); | |
7447 | return; | |
7448 | ||
7449 | case M_USD_A: | |
7450 | s = "sdl"; | |
7451 | s2 = "sdr"; | |
7452 | off = 7; | |
7453 | goto uswa; | |
7454 | case M_USW_A: | |
7455 | s = "swl"; | |
7456 | s2 = "swr"; | |
7457 | off = 3; | |
7458 | uswa: | |
d6bc6245 | 7459 | used_at = 1; |
c9914766 | 7460 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7461 | if (breg != 0) |
7462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7463 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7464 | "d,v,t", AT, AT, breg); |
7465 | if (! target_big_endian) | |
7466 | expr1.X_add_number = off; | |
7467 | else | |
7468 | expr1.X_add_number = 0; | |
7469 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7470 | (int) BFD_RELOC_LO16, AT); | |
7471 | if (! target_big_endian) | |
7472 | expr1.X_add_number = 0; | |
7473 | else | |
7474 | expr1.X_add_number = off; | |
7475 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7476 | (int) BFD_RELOC_LO16, AT); | |
7477 | break; | |
7478 | ||
7479 | case M_USH_A: | |
d6bc6245 | 7480 | used_at = 1; |
c9914766 | 7481 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7482 | if (breg != 0) |
7483 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7484 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7485 | "d,v,t", AT, AT, breg); |
7486 | if (! target_big_endian) | |
7487 | expr1.X_add_number = 0; | |
7488 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7489 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7490 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7491 | treg, treg, 8); | |
252b5132 RH |
7492 | if (! target_big_endian) |
7493 | expr1.X_add_number = 1; | |
7494 | else | |
7495 | expr1.X_add_number = 0; | |
7496 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7497 | (int) BFD_RELOC_LO16, AT); | |
7498 | if (! target_big_endian) | |
7499 | expr1.X_add_number = 0; | |
7500 | else | |
7501 | expr1.X_add_number = 1; | |
7502 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7503 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7504 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7505 | treg, treg, 8); | |
7506 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7507 | treg, treg, AT); | |
252b5132 RH |
7508 | break; |
7509 | ||
7510 | default: | |
7511 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7512 | are added dynamically. */ |
252b5132 RH |
7513 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7514 | break; | |
7515 | } | |
7516 | if (mips_opts.noat) | |
7517 | as_warn (_("Macro used $at after \".set noat\"")); | |
7518 | } | |
7519 | ||
7520 | /* Implement macros in mips16 mode. */ | |
7521 | ||
7522 | static void | |
7523 | mips16_macro (ip) | |
7524 | struct mips_cl_insn *ip; | |
7525 | { | |
7526 | int mask; | |
7527 | int xreg, yreg, zreg, tmp; | |
7528 | int icnt; | |
7529 | expressionS expr1; | |
7530 | int dbl; | |
7531 | const char *s, *s2, *s3; | |
7532 | ||
7533 | mask = ip->insn_mo->mask; | |
7534 | ||
7535 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7536 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7537 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7538 | ||
7539 | icnt = 0; | |
7540 | ||
7541 | expr1.X_op = O_constant; | |
7542 | expr1.X_op_symbol = NULL; | |
7543 | expr1.X_add_symbol = NULL; | |
7544 | expr1.X_add_number = 1; | |
7545 | ||
7546 | dbl = 0; | |
7547 | ||
7548 | switch (mask) | |
7549 | { | |
7550 | default: | |
7551 | internalError (); | |
7552 | ||
7553 | case M_DDIV_3: | |
7554 | dbl = 1; | |
7555 | case M_DIV_3: | |
7556 | s = "mflo"; | |
7557 | goto do_div3; | |
7558 | case M_DREM_3: | |
7559 | dbl = 1; | |
7560 | case M_REM_3: | |
7561 | s = "mfhi"; | |
7562 | do_div3: | |
7563 | mips_emit_delays (true); | |
7564 | ++mips_opts.noreorder; | |
7565 | mips_any_noreorder = 1; | |
2396cfb9 | 7566 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7567 | dbl ? "ddiv" : "div", |
7568 | "0,x,y", xreg, yreg); | |
7569 | expr1.X_add_number = 2; | |
7570 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7571 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7572 | 7); | |
bdaaa2e1 | 7573 | |
252b5132 RH |
7574 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7575 | since that causes an overflow. We should do that as well, | |
7576 | but I don't see how to do the comparisons without a temporary | |
7577 | register. */ | |
7578 | --mips_opts.noreorder; | |
2396cfb9 | 7579 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7580 | break; |
7581 | ||
7582 | case M_DIVU_3: | |
7583 | s = "divu"; | |
7584 | s2 = "mflo"; | |
7585 | goto do_divu3; | |
7586 | case M_REMU_3: | |
7587 | s = "divu"; | |
7588 | s2 = "mfhi"; | |
7589 | goto do_divu3; | |
7590 | case M_DDIVU_3: | |
7591 | s = "ddivu"; | |
7592 | s2 = "mflo"; | |
7593 | goto do_divu3; | |
7594 | case M_DREMU_3: | |
7595 | s = "ddivu"; | |
7596 | s2 = "mfhi"; | |
7597 | do_divu3: | |
7598 | mips_emit_delays (true); | |
7599 | ++mips_opts.noreorder; | |
7600 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7601 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7602 | xreg, yreg); | |
252b5132 RH |
7603 | expr1.X_add_number = 2; |
7604 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7606 | "6", 7); | |
252b5132 | 7607 | --mips_opts.noreorder; |
2396cfb9 | 7608 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7609 | break; |
7610 | ||
7611 | case M_DMUL: | |
7612 | dbl = 1; | |
7613 | case M_MUL: | |
2396cfb9 | 7614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7615 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7617 | zreg); | |
252b5132 RH |
7618 | return; |
7619 | ||
7620 | case M_DSUBU_I: | |
7621 | dbl = 1; | |
7622 | goto do_subu; | |
7623 | case M_SUBU_I: | |
7624 | do_subu: | |
7625 | if (imm_expr.X_op != O_constant) | |
7626 | as_bad (_("Unsupported large constant")); | |
7627 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7628 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7629 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7630 | break; |
7631 | ||
7632 | case M_SUBU_I_2: | |
7633 | if (imm_expr.X_op != O_constant) | |
7634 | as_bad (_("Unsupported large constant")); | |
7635 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7636 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7637 | "x,k", xreg); | |
7638 | break; | |
7639 | ||
7640 | case M_DSUBU_I_2: | |
7641 | if (imm_expr.X_op != O_constant) | |
7642 | as_bad (_("Unsupported large constant")); | |
7643 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7644 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7645 | "y,j", yreg); | |
7646 | break; | |
7647 | ||
7648 | case M_BEQ: | |
7649 | s = "cmp"; | |
7650 | s2 = "bteqz"; | |
7651 | goto do_branch; | |
7652 | case M_BNE: | |
7653 | s = "cmp"; | |
7654 | s2 = "btnez"; | |
7655 | goto do_branch; | |
7656 | case M_BLT: | |
7657 | s = "slt"; | |
7658 | s2 = "btnez"; | |
7659 | goto do_branch; | |
7660 | case M_BLTU: | |
7661 | s = "sltu"; | |
7662 | s2 = "btnez"; | |
7663 | goto do_branch; | |
7664 | case M_BLE: | |
7665 | s = "slt"; | |
7666 | s2 = "bteqz"; | |
7667 | goto do_reverse_branch; | |
7668 | case M_BLEU: | |
7669 | s = "sltu"; | |
7670 | s2 = "bteqz"; | |
7671 | goto do_reverse_branch; | |
7672 | case M_BGE: | |
7673 | s = "slt"; | |
7674 | s2 = "bteqz"; | |
7675 | goto do_branch; | |
7676 | case M_BGEU: | |
7677 | s = "sltu"; | |
7678 | s2 = "bteqz"; | |
7679 | goto do_branch; | |
7680 | case M_BGT: | |
7681 | s = "slt"; | |
7682 | s2 = "btnez"; | |
7683 | goto do_reverse_branch; | |
7684 | case M_BGTU: | |
7685 | s = "sltu"; | |
7686 | s2 = "btnez"; | |
7687 | ||
7688 | do_reverse_branch: | |
7689 | tmp = xreg; | |
7690 | xreg = yreg; | |
7691 | yreg = tmp; | |
7692 | ||
7693 | do_branch: | |
7694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7695 | xreg, yreg); | |
7696 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7697 | break; | |
7698 | ||
7699 | case M_BEQ_I: | |
7700 | s = "cmpi"; | |
7701 | s2 = "bteqz"; | |
7702 | s3 = "x,U"; | |
7703 | goto do_branch_i; | |
7704 | case M_BNE_I: | |
7705 | s = "cmpi"; | |
7706 | s2 = "btnez"; | |
7707 | s3 = "x,U"; | |
7708 | goto do_branch_i; | |
7709 | case M_BLT_I: | |
7710 | s = "slti"; | |
7711 | s2 = "btnez"; | |
7712 | s3 = "x,8"; | |
7713 | goto do_branch_i; | |
7714 | case M_BLTU_I: | |
7715 | s = "sltiu"; | |
7716 | s2 = "btnez"; | |
7717 | s3 = "x,8"; | |
7718 | goto do_branch_i; | |
7719 | case M_BLE_I: | |
7720 | s = "slti"; | |
7721 | s2 = "btnez"; | |
7722 | s3 = "x,8"; | |
7723 | goto do_addone_branch_i; | |
7724 | case M_BLEU_I: | |
7725 | s = "sltiu"; | |
7726 | s2 = "btnez"; | |
7727 | s3 = "x,8"; | |
7728 | goto do_addone_branch_i; | |
7729 | case M_BGE_I: | |
7730 | s = "slti"; | |
7731 | s2 = "bteqz"; | |
7732 | s3 = "x,8"; | |
7733 | goto do_branch_i; | |
7734 | case M_BGEU_I: | |
7735 | s = "sltiu"; | |
7736 | s2 = "bteqz"; | |
7737 | s3 = "x,8"; | |
7738 | goto do_branch_i; | |
7739 | case M_BGT_I: | |
7740 | s = "slti"; | |
7741 | s2 = "bteqz"; | |
7742 | s3 = "x,8"; | |
7743 | goto do_addone_branch_i; | |
7744 | case M_BGTU_I: | |
7745 | s = "sltiu"; | |
7746 | s2 = "bteqz"; | |
7747 | s3 = "x,8"; | |
7748 | ||
7749 | do_addone_branch_i: | |
7750 | if (imm_expr.X_op != O_constant) | |
7751 | as_bad (_("Unsupported large constant")); | |
7752 | ++imm_expr.X_add_number; | |
7753 | ||
7754 | do_branch_i: | |
7755 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7756 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7757 | break; | |
7758 | ||
7759 | case M_ABS: | |
7760 | expr1.X_add_number = 0; | |
98d3f06f | 7761 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7762 | if (xreg != yreg) |
ea1fb5dc | 7763 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7764 | expr1.X_add_number = 2; |
7765 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7766 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7767 | "neg", "x,w", xreg, xreg); | |
7768 | } | |
7769 | } | |
7770 | ||
7771 | /* For consistency checking, verify that all bits are specified either | |
7772 | by the match/mask part of the instruction definition, or by the | |
7773 | operand list. */ | |
7774 | static int | |
7775 | validate_mips_insn (opc) | |
7776 | const struct mips_opcode *opc; | |
7777 | { | |
7778 | const char *p = opc->args; | |
7779 | char c; | |
7780 | unsigned long used_bits = opc->mask; | |
7781 | ||
7782 | if ((used_bits & opc->match) != opc->match) | |
7783 | { | |
7784 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7785 | opc->name, opc->args); | |
7786 | return 0; | |
7787 | } | |
7788 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7789 | while (*p) | |
7790 | switch (c = *p++) | |
7791 | { | |
7792 | case ',': break; | |
7793 | case '(': break; | |
7794 | case ')': break; | |
7795 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7796 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7797 | case 'A': break; | |
4372b673 | 7798 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7799 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7800 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7801 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7802 | case 'F': break; | |
7803 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7804 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7805 | case 'I': break; |
e972090a | 7806 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7807 | case 'L': break; |
7808 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7809 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7810 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7811 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7812 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7813 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7814 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7815 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7816 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7817 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7818 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7819 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7820 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7821 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7822 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7823 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7824 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7825 | case 'f': break; | |
7826 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7827 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7828 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7829 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7830 | case 'l': break; | |
7831 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7832 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7833 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7834 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7835 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7836 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7837 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7838 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7839 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7840 | case 'x': break; | |
7841 | case 'z': break; | |
7842 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7843 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7844 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7845 | default: |
7846 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7847 | c, opc->name, opc->args); | |
7848 | return 0; | |
7849 | } | |
7850 | #undef USE_BITS | |
7851 | if (used_bits != 0xffffffff) | |
7852 | { | |
7853 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7854 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7855 | return 0; | |
7856 | } | |
7857 | return 1; | |
7858 | } | |
7859 | ||
7860 | /* This routine assembles an instruction into its binary format. As a | |
7861 | side effect, it sets one of the global variables imm_reloc or | |
7862 | offset_reloc to the type of relocation to do if one of the operands | |
7863 | is an address expression. */ | |
7864 | ||
7865 | static void | |
7866 | mips_ip (str, ip) | |
7867 | char *str; | |
7868 | struct mips_cl_insn *ip; | |
7869 | { | |
7870 | char *s; | |
7871 | const char *args; | |
43841e91 | 7872 | char c = 0; |
252b5132 RH |
7873 | struct mips_opcode *insn; |
7874 | char *argsStart; | |
7875 | unsigned int regno; | |
7876 | unsigned int lastregno = 0; | |
7877 | char *s_reset; | |
7878 | char save_c = 0; | |
252b5132 RH |
7879 | |
7880 | insn_error = NULL; | |
7881 | ||
7882 | /* If the instruction contains a '.', we first try to match an instruction | |
7883 | including the '.'. Then we try again without the '.'. */ | |
7884 | insn = NULL; | |
3882b010 | 7885 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7886 | continue; |
7887 | ||
7888 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7889 | the call to hash_find. Save the character we replaced just in case we | |
7890 | have to re-parse the instruction. */ | |
3882b010 | 7891 | if (ISSPACE (*s)) |
252b5132 RH |
7892 | { |
7893 | save_c = *s; | |
7894 | *s++ = '\0'; | |
7895 | } | |
bdaaa2e1 | 7896 | |
252b5132 RH |
7897 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7898 | ||
7899 | /* If we didn't find the instruction in the opcode table, try again, but | |
7900 | this time with just the instruction up to, but not including the | |
7901 | first '.'. */ | |
7902 | if (insn == NULL) | |
7903 | { | |
bdaaa2e1 | 7904 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7905 | if (save_c) |
7906 | *(--s) = save_c; | |
7907 | ||
7908 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7909 | for (s = str; |
7910 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7911 | ++s) | |
252b5132 RH |
7912 | continue; |
7913 | ||
7914 | /* If we did not find a '.', then we can quit now. */ | |
7915 | if (*s != '.') | |
7916 | { | |
7917 | insn_error = "unrecognized opcode"; | |
7918 | return; | |
7919 | } | |
7920 | ||
7921 | /* Lookup the instruction in the hash table. */ | |
7922 | *s++ = '\0'; | |
7923 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7924 | { | |
7925 | insn_error = "unrecognized opcode"; | |
7926 | return; | |
7927 | } | |
252b5132 RH |
7928 | } |
7929 | ||
7930 | argsStart = s; | |
7931 | for (;;) | |
7932 | { | |
252b5132 RH |
7933 | boolean ok; |
7934 | ||
7935 | assert (strcmp (insn->name, str) == 0); | |
7936 | ||
1f25f5d3 CD |
7937 | if (OPCODE_IS_MEMBER (insn, |
7938 | (mips_opts.isa | |
deec1734 | 7939 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7940 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 7941 | mips_arch)) |
252b5132 | 7942 | ok = true; |
bdaaa2e1 | 7943 | else |
252b5132 | 7944 | ok = false; |
bdaaa2e1 | 7945 | |
252b5132 RH |
7946 | if (insn->pinfo != INSN_MACRO) |
7947 | { | |
ec68c924 | 7948 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7949 | ok = false; |
7950 | } | |
7951 | ||
7952 | if (! ok) | |
7953 | { | |
7954 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7955 | && strcmp (insn->name, insn[1].name) == 0) | |
7956 | { | |
7957 | ++insn; | |
7958 | continue; | |
7959 | } | |
252b5132 | 7960 | else |
beae10d5 | 7961 | { |
268f6bed L |
7962 | if (!insn_error) |
7963 | { | |
7964 | static char buf[100]; | |
7965 | sprintf (buf, | |
7966 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7967 | mips_cpu_to_str (mips_arch), |
268f6bed | 7968 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7969 | |
268f6bed L |
7970 | insn_error = buf; |
7971 | } | |
7972 | if (save_c) | |
7973 | *(--s) = save_c; | |
2bd7f1f3 | 7974 | return; |
252b5132 | 7975 | } |
252b5132 RH |
7976 | } |
7977 | ||
7978 | ip->insn_mo = insn; | |
7979 | ip->insn_opcode = insn->match; | |
268f6bed | 7980 | insn_error = NULL; |
252b5132 RH |
7981 | for (args = insn->args;; ++args) |
7982 | { | |
deec1734 CD |
7983 | int is_mdmx; |
7984 | ||
ad8d3bb3 | 7985 | s += strspn (s, " \t"); |
deec1734 | 7986 | is_mdmx = 0; |
252b5132 RH |
7987 | switch (*args) |
7988 | { | |
7989 | case '\0': /* end of args */ | |
7990 | if (*s == '\0') | |
7991 | return; | |
7992 | break; | |
7993 | ||
7994 | case ',': | |
7995 | if (*s++ == *args) | |
7996 | continue; | |
7997 | s--; | |
7998 | switch (*++args) | |
7999 | { | |
8000 | case 'r': | |
8001 | case 'v': | |
38487616 | 8002 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8003 | continue; |
8004 | ||
8005 | case 'w': | |
38487616 TS |
8006 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8007 | continue; | |
8008 | ||
252b5132 | 8009 | case 'W': |
38487616 | 8010 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8011 | continue; |
8012 | ||
8013 | case 'V': | |
38487616 | 8014 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8015 | continue; |
8016 | } | |
8017 | break; | |
8018 | ||
8019 | case '(': | |
8020 | /* Handle optional base register. | |
8021 | Either the base register is omitted or | |
bdaaa2e1 | 8022 | we must have a left paren. */ |
252b5132 RH |
8023 | /* This is dependent on the next operand specifier |
8024 | is a base register specification. */ | |
8025 | assert (args[1] == 'b' || args[1] == '5' | |
8026 | || args[1] == '-' || args[1] == '4'); | |
8027 | if (*s == '\0') | |
8028 | return; | |
8029 | ||
8030 | case ')': /* these must match exactly */ | |
8031 | if (*s++ == *args) | |
8032 | continue; | |
8033 | break; | |
8034 | ||
8035 | case '<': /* must be at least one digit */ | |
8036 | /* | |
8037 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8038 | * than 31 or less than 0, then the shift amount should be |
8039 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8040 | * We issue a warning and mask out all but the low 5 bits. |
8041 | */ | |
8042 | my_getExpression (&imm_expr, s); | |
8043 | check_absolute_expr (ip, &imm_expr); | |
8044 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8045 | { | |
8046 | as_warn (_("Improper shift amount (%ld)"), | |
8047 | (long) imm_expr.X_add_number); | |
38487616 | 8048 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8049 | } |
38487616 | 8050 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8051 | imm_expr.X_op = O_absent; |
8052 | s = expr_end; | |
8053 | continue; | |
8054 | ||
8055 | case '>': /* shift amount minus 32 */ | |
8056 | my_getExpression (&imm_expr, s); | |
8057 | check_absolute_expr (ip, &imm_expr); | |
8058 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8059 | || (unsigned long) imm_expr.X_add_number > 63) | |
8060 | break; | |
38487616 | 8061 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8062 | imm_expr.X_op = O_absent; |
8063 | s = expr_end; | |
8064 | continue; | |
8065 | ||
252b5132 RH |
8066 | case 'k': /* cache code */ |
8067 | case 'h': /* prefx code */ | |
8068 | my_getExpression (&imm_expr, s); | |
8069 | check_absolute_expr (ip, &imm_expr); | |
8070 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8071 | { | |
8072 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8073 | ip->insn_mo->name, | |
8074 | (unsigned long) imm_expr.X_add_number); | |
8075 | imm_expr.X_add_number &= 0x1f; | |
8076 | } | |
8077 | if (*args == 'k') | |
8078 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8079 | else | |
8080 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8081 | imm_expr.X_op = O_absent; | |
8082 | s = expr_end; | |
8083 | continue; | |
8084 | ||
8085 | case 'c': /* break code */ | |
8086 | my_getExpression (&imm_expr, s); | |
8087 | check_absolute_expr (ip, &imm_expr); | |
8088 | if ((unsigned) imm_expr.X_add_number > 1023) | |
8089 | { | |
8090 | as_warn (_("Illegal break code (%ld)"), | |
8091 | (long) imm_expr.X_add_number); | |
38487616 | 8092 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8093 | } |
38487616 | 8094 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8095 | imm_expr.X_op = O_absent; |
8096 | s = expr_end; | |
8097 | continue; | |
8098 | ||
8099 | case 'q': /* lower break code */ | |
8100 | my_getExpression (&imm_expr, s); | |
8101 | check_absolute_expr (ip, &imm_expr); | |
8102 | if ((unsigned) imm_expr.X_add_number > 1023) | |
8103 | { | |
8104 | as_warn (_("Illegal lower break code (%ld)"), | |
8105 | (long) imm_expr.X_add_number); | |
38487616 | 8106 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8107 | } |
38487616 | 8108 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8109 | imm_expr.X_op = O_absent; |
8110 | s = expr_end; | |
8111 | continue; | |
8112 | ||
4372b673 | 8113 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8114 | my_getExpression (&imm_expr, s); |
156c2f8b | 8115 | check_absolute_expr (ip, &imm_expr); |
38487616 | 8116 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 8117 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 8118 | (long) imm_expr.X_add_number); |
38487616 | 8119 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8120 | imm_expr.X_op = O_absent; |
8121 | s = expr_end; | |
8122 | continue; | |
8123 | ||
98d3f06f | 8124 | case 'C': /* Coprocessor code */ |
beae10d5 | 8125 | my_getExpression (&imm_expr, s); |
252b5132 | 8126 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8127 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8128 | { |
beae10d5 | 8129 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 8130 | (long) imm_expr.X_add_number); |
98d3f06f | 8131 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8132 | } |
beae10d5 KH |
8133 | ip->insn_opcode |= imm_expr.X_add_number; |
8134 | imm_expr.X_op = O_absent; | |
8135 | s = expr_end; | |
8136 | continue; | |
252b5132 | 8137 | |
4372b673 NC |
8138 | case 'J': /* 19-bit wait code. */ |
8139 | my_getExpression (&imm_expr, s); | |
8140 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 8141 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
8142 | as_warn (_("Illegal 19-bit code (%ld)"), |
8143 | (long) imm_expr.X_add_number); | |
38487616 | 8144 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8145 | imm_expr.X_op = O_absent; |
8146 | s = expr_end; | |
8147 | continue; | |
8148 | ||
252b5132 | 8149 | case 'P': /* Performance register */ |
beae10d5 | 8150 | my_getExpression (&imm_expr, s); |
252b5132 | 8151 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8152 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8153 | { |
38487616 | 8154 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 8155 | (long) imm_expr.X_add_number); |
38487616 | 8156 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8157 | } |
38487616 | 8158 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8159 | imm_expr.X_op = O_absent; |
8160 | s = expr_end; | |
8161 | continue; | |
252b5132 RH |
8162 | |
8163 | case 'b': /* base register */ | |
8164 | case 'd': /* destination register */ | |
8165 | case 's': /* source register */ | |
8166 | case 't': /* target register */ | |
8167 | case 'r': /* both target and source */ | |
8168 | case 'v': /* both dest and source */ | |
8169 | case 'w': /* both dest and target */ | |
8170 | case 'E': /* coprocessor target register */ | |
8171 | case 'G': /* coprocessor destination register */ | |
8172 | case 'x': /* ignore register name */ | |
8173 | case 'z': /* must be zero register */ | |
4372b673 | 8174 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8175 | s_reset = s; |
8176 | if (s[0] == '$') | |
8177 | { | |
8178 | ||
3882b010 | 8179 | if (ISDIGIT (s[1])) |
252b5132 RH |
8180 | { |
8181 | ++s; | |
8182 | regno = 0; | |
8183 | do | |
8184 | { | |
8185 | regno *= 10; | |
8186 | regno += *s - '0'; | |
8187 | ++s; | |
8188 | } | |
3882b010 | 8189 | while (ISDIGIT (*s)); |
252b5132 RH |
8190 | if (regno > 31) |
8191 | as_bad (_("Invalid register number (%d)"), regno); | |
8192 | } | |
8193 | else if (*args == 'E' || *args == 'G') | |
8194 | goto notreg; | |
8195 | else | |
8196 | { | |
8197 | if (s[1] == 'f' && s[2] == 'p') | |
8198 | { | |
8199 | s += 3; | |
8200 | regno = FP; | |
8201 | } | |
8202 | else if (s[1] == 's' && s[2] == 'p') | |
8203 | { | |
8204 | s += 3; | |
8205 | regno = SP; | |
8206 | } | |
8207 | else if (s[1] == 'g' && s[2] == 'p') | |
8208 | { | |
8209 | s += 3; | |
8210 | regno = GP; | |
8211 | } | |
8212 | else if (s[1] == 'a' && s[2] == 't') | |
8213 | { | |
8214 | s += 3; | |
8215 | regno = AT; | |
8216 | } | |
8217 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8218 | { | |
8219 | s += 4; | |
8220 | regno = KT0; | |
8221 | } | |
8222 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8223 | { | |
8224 | s += 4; | |
8225 | regno = KT1; | |
8226 | } | |
8227 | else if (itbl_have_entries) | |
8228 | { | |
8229 | char *p, *n; | |
d7ba4a77 | 8230 | unsigned long r; |
252b5132 | 8231 | |
d7ba4a77 | 8232 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8233 | n = itbl_get_field (&p); /* n is name */ |
8234 | ||
d7ba4a77 ILT |
8235 | /* See if this is a register defined in an |
8236 | itbl entry. */ | |
8237 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8238 | { |
8239 | /* Get_field advances to the start of | |
8240 | the next field, so we need to back | |
d7ba4a77 | 8241 | rack to the end of the last field. */ |
bdaaa2e1 | 8242 | if (p) |
252b5132 | 8243 | s = p - 1; |
bdaaa2e1 | 8244 | else |
d7ba4a77 | 8245 | s = strchr (s, '\0'); |
252b5132 RH |
8246 | regno = r; |
8247 | } | |
8248 | else | |
8249 | goto notreg; | |
beae10d5 | 8250 | } |
252b5132 RH |
8251 | else |
8252 | goto notreg; | |
8253 | } | |
8254 | if (regno == AT | |
8255 | && ! mips_opts.noat | |
8256 | && *args != 'E' | |
8257 | && *args != 'G') | |
8258 | as_warn (_("Used $at without \".set noat\"")); | |
8259 | c = *args; | |
8260 | if (*s == ' ') | |
f9419b05 | 8261 | ++s; |
252b5132 RH |
8262 | if (args[1] != *s) |
8263 | { | |
8264 | if (c == 'r' || c == 'v' || c == 'w') | |
8265 | { | |
8266 | regno = lastregno; | |
8267 | s = s_reset; | |
f9419b05 | 8268 | ++args; |
252b5132 RH |
8269 | } |
8270 | } | |
8271 | /* 'z' only matches $0. */ | |
8272 | if (c == 'z' && regno != 0) | |
8273 | break; | |
8274 | ||
bdaaa2e1 KH |
8275 | /* Now that we have assembled one operand, we use the args string |
8276 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8277 | switch (c) |
8278 | { | |
8279 | case 'r': | |
8280 | case 's': | |
8281 | case 'v': | |
8282 | case 'b': | |
38487616 | 8283 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8284 | break; |
8285 | case 'd': | |
8286 | case 'G': | |
38487616 | 8287 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8288 | break; |
4372b673 | 8289 | case 'U': |
38487616 TS |
8290 | ip->insn_opcode |= regno << OP_SH_RD; |
8291 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8292 | break; |
252b5132 RH |
8293 | case 'w': |
8294 | case 't': | |
8295 | case 'E': | |
38487616 | 8296 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8297 | break; |
8298 | case 'x': | |
8299 | /* This case exists because on the r3000 trunc | |
8300 | expands into a macro which requires a gp | |
8301 | register. On the r6000 or r4000 it is | |
8302 | assembled into a single instruction which | |
8303 | ignores the register. Thus the insn version | |
8304 | is MIPS_ISA2 and uses 'x', and the macro | |
8305 | version is MIPS_ISA1 and uses 't'. */ | |
8306 | break; | |
8307 | case 'z': | |
8308 | /* This case is for the div instruction, which | |
8309 | acts differently if the destination argument | |
8310 | is $0. This only matches $0, and is checked | |
8311 | outside the switch. */ | |
8312 | break; | |
8313 | case 'D': | |
8314 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8315 | break; | |
8316 | /* What about all other operands like 'i', which | |
8317 | can be specified in the opcode table? */ | |
8318 | } | |
8319 | lastregno = regno; | |
8320 | continue; | |
8321 | } | |
8322 | notreg: | |
8323 | switch (*args++) | |
8324 | { | |
8325 | case 'r': | |
8326 | case 'v': | |
38487616 | 8327 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8328 | continue; |
8329 | case 'w': | |
38487616 | 8330 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8331 | continue; |
8332 | } | |
8333 | break; | |
8334 | ||
deec1734 CD |
8335 | case 'O': /* MDMX alignment immediate constant. */ |
8336 | my_getExpression (&imm_expr, s); | |
8337 | check_absolute_expr (ip, &imm_expr); | |
8338 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8339 | { | |
8340 | as_warn ("Improper align amount (%ld), using low bits", | |
8341 | (long) imm_expr.X_add_number); | |
8342 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8343 | } | |
8344 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8345 | imm_expr.X_op = O_absent; | |
8346 | s = expr_end; | |
8347 | continue; | |
8348 | ||
8349 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8350 | if (s[0] != '$') | |
8351 | { | |
8352 | /* MDMX Immediate. */ | |
8353 | my_getExpression (&imm_expr, s); | |
8354 | check_absolute_expr (ip, &imm_expr); | |
8355 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8356 | { | |
8357 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8358 | (long) imm_expr.X_add_number); | |
8359 | imm_expr.X_add_number &= OP_MASK_FT; | |
8360 | } | |
8361 | imm_expr.X_add_number &= OP_MASK_FT; | |
8362 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8363 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8364 | else | |
8365 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8366 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8367 | imm_expr.X_op = O_absent; | |
8368 | s = expr_end; | |
8369 | continue; | |
8370 | } | |
8371 | /* Not MDMX Immediate. Fall through. */ | |
8372 | case 'X': /* MDMX destination register. */ | |
8373 | case 'Y': /* MDMX source register. */ | |
8374 | case 'Z': /* MDMX target register. */ | |
8375 | is_mdmx = 1; | |
252b5132 RH |
8376 | case 'D': /* floating point destination register */ |
8377 | case 'S': /* floating point source register */ | |
8378 | case 'T': /* floating point target register */ | |
8379 | case 'R': /* floating point source register */ | |
8380 | case 'V': | |
8381 | case 'W': | |
8382 | s_reset = s; | |
deec1734 CD |
8383 | /* Accept $fN for FP and MDMX register numbers, and in |
8384 | addition accept $vN for MDMX register numbers. */ | |
8385 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8386 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8387 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8388 | { |
8389 | s += 2; | |
8390 | regno = 0; | |
8391 | do | |
8392 | { | |
8393 | regno *= 10; | |
8394 | regno += *s - '0'; | |
8395 | ++s; | |
8396 | } | |
3882b010 | 8397 | while (ISDIGIT (*s)); |
252b5132 RH |
8398 | |
8399 | if (regno > 31) | |
8400 | as_bad (_("Invalid float register number (%d)"), regno); | |
8401 | ||
8402 | if ((regno & 1) != 0 | |
ca4e0257 | 8403 | && HAVE_32BIT_FPRS |
252b5132 RH |
8404 | && ! (strcmp (str, "mtc1") == 0 |
8405 | || strcmp (str, "mfc1") == 0 | |
8406 | || strcmp (str, "lwc1") == 0 | |
8407 | || strcmp (str, "swc1") == 0 | |
8408 | || strcmp (str, "l.s") == 0 | |
8409 | || strcmp (str, "s.s") == 0)) | |
8410 | as_warn (_("Float register should be even, was %d"), | |
8411 | regno); | |
8412 | ||
8413 | c = *args; | |
8414 | if (*s == ' ') | |
f9419b05 | 8415 | ++s; |
252b5132 RH |
8416 | if (args[1] != *s) |
8417 | { | |
8418 | if (c == 'V' || c == 'W') | |
8419 | { | |
8420 | regno = lastregno; | |
8421 | s = s_reset; | |
f9419b05 | 8422 | ++args; |
252b5132 RH |
8423 | } |
8424 | } | |
8425 | switch (c) | |
8426 | { | |
8427 | case 'D': | |
deec1734 | 8428 | case 'X': |
38487616 | 8429 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8430 | break; |
8431 | case 'V': | |
8432 | case 'S': | |
deec1734 | 8433 | case 'Y': |
38487616 | 8434 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8435 | break; |
deec1734 CD |
8436 | case 'Q': |
8437 | /* This is like 'Z', but also needs to fix the MDMX | |
8438 | vector/scalar select bits. Note that the | |
8439 | scalar immediate case is handled above. */ | |
8440 | if (*s == '[') | |
8441 | { | |
8442 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8443 | int max_el = (is_qh ? 3 : 7); | |
8444 | s++; | |
8445 | my_getExpression(&imm_expr, s); | |
8446 | check_absolute_expr (ip, &imm_expr); | |
8447 | s = expr_end; | |
8448 | if (imm_expr.X_add_number > max_el) | |
8449 | as_bad(_("Bad element selector %ld"), | |
8450 | (long) imm_expr.X_add_number); | |
8451 | imm_expr.X_add_number &= max_el; | |
8452 | ip->insn_opcode |= (imm_expr.X_add_number | |
8453 | << (OP_SH_VSEL + | |
8454 | (is_qh ? 2 : 1))); | |
8455 | if (*s != ']') | |
8456 | as_warn(_("Expecting ']' found '%s'"), s); | |
8457 | else | |
8458 | s++; | |
8459 | } | |
8460 | else | |
8461 | { | |
8462 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8463 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8464 | << OP_SH_VSEL); | |
8465 | else | |
8466 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8467 | OP_SH_VSEL); | |
8468 | } | |
8469 | /* Fall through */ | |
252b5132 RH |
8470 | case 'W': |
8471 | case 'T': | |
deec1734 | 8472 | case 'Z': |
38487616 | 8473 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8474 | break; |
8475 | case 'R': | |
38487616 | 8476 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8477 | break; |
8478 | } | |
8479 | lastregno = regno; | |
8480 | continue; | |
8481 | } | |
8482 | ||
252b5132 RH |
8483 | switch (*args++) |
8484 | { | |
8485 | case 'V': | |
38487616 | 8486 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8487 | continue; |
8488 | case 'W': | |
38487616 | 8489 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8490 | continue; |
8491 | } | |
8492 | break; | |
8493 | ||
8494 | case 'I': | |
8495 | my_getExpression (&imm_expr, s); | |
8496 | if (imm_expr.X_op != O_big | |
8497 | && imm_expr.X_op != O_constant) | |
8498 | insn_error = _("absolute expression required"); | |
8499 | s = expr_end; | |
8500 | continue; | |
8501 | ||
8502 | case 'A': | |
8503 | my_getExpression (&offset_expr, s); | |
f6688943 | 8504 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8505 | s = expr_end; |
8506 | continue; | |
8507 | ||
8508 | case 'F': | |
8509 | case 'L': | |
8510 | case 'f': | |
8511 | case 'l': | |
8512 | { | |
8513 | int f64; | |
ca4e0257 | 8514 | int using_gprs; |
252b5132 RH |
8515 | char *save_in; |
8516 | char *err; | |
8517 | unsigned char temp[8]; | |
8518 | int len; | |
8519 | unsigned int length; | |
8520 | segT seg; | |
8521 | subsegT subseg; | |
8522 | char *p; | |
8523 | ||
8524 | /* These only appear as the last operand in an | |
8525 | instruction, and every instruction that accepts | |
8526 | them in any variant accepts them in all variants. | |
8527 | This means we don't have to worry about backing out | |
8528 | any changes if the instruction does not match. | |
8529 | ||
8530 | The difference between them is the size of the | |
8531 | floating point constant and where it goes. For 'F' | |
8532 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8533 | is 32 bits. Where the constant is placed is based | |
8534 | on how the MIPS assembler does things: | |
8535 | F -- .rdata | |
8536 | L -- .lit8 | |
8537 | f -- immediate value | |
8538 | l -- .lit4 | |
8539 | ||
8540 | The .lit4 and .lit8 sections are only used if | |
8541 | permitted by the -G argument. | |
8542 | ||
8543 | When generating embedded PIC code, we use the | |
8544 | .lit8 section but not the .lit4 section (we can do | |
8545 | .lit4 inline easily; we need to put .lit8 | |
8546 | somewhere in the data segment, and using .lit8 | |
8547 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8548 | .lit8 entries). |
8549 | ||
8550 | The code below needs to know whether the target register | |
8551 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8552 | 'F' are used with GPR-based instructions and 'l' and | |
8553 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8554 | |
8555 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8556 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8557 | |
8558 | save_in = input_line_pointer; | |
8559 | input_line_pointer = s; | |
8560 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8561 | length = len; | |
8562 | s = input_line_pointer; | |
8563 | input_line_pointer = save_in; | |
8564 | if (err != NULL && *err != '\0') | |
8565 | { | |
8566 | as_bad (_("Bad floating point constant: %s"), err); | |
8567 | memset (temp, '\0', sizeof temp); | |
8568 | length = f64 ? 8 : 4; | |
8569 | } | |
8570 | ||
156c2f8b | 8571 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8572 | |
8573 | if (*args == 'f' | |
8574 | || (*args == 'l' | |
8575 | && (! USE_GLOBAL_POINTER_OPT | |
8576 | || mips_pic == EMBEDDED_PIC | |
8577 | || g_switch_value < 4 | |
8578 | || (temp[0] == 0 && temp[1] == 0) | |
8579 | || (temp[2] == 0 && temp[3] == 0)))) | |
8580 | { | |
8581 | imm_expr.X_op = O_constant; | |
8582 | if (! target_big_endian) | |
8583 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8584 | else | |
8585 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8586 | } | |
8587 | else if (length > 4 | |
119d663a | 8588 | && ! mips_disable_float_construction |
ca4e0257 RS |
8589 | /* Constants can only be constructed in GPRs and |
8590 | copied to FPRs if the GPRs are at least as wide | |
8591 | as the FPRs. Force the constant into memory if | |
8592 | we are using 64-bit FPRs but the GPRs are only | |
8593 | 32 bits wide. */ | |
8594 | && (using_gprs | |
8595 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8596 | && ((temp[0] == 0 && temp[1] == 0) |
8597 | || (temp[2] == 0 && temp[3] == 0)) | |
8598 | && ((temp[4] == 0 && temp[5] == 0) | |
8599 | || (temp[6] == 0 && temp[7] == 0))) | |
8600 | { | |
ca4e0257 RS |
8601 | /* The value is simple enough to load with a couple of |
8602 | instructions. If using 32-bit registers, set | |
8603 | imm_expr to the high order 32 bits and offset_expr to | |
8604 | the low order 32 bits. Otherwise, set imm_expr to | |
8605 | the entire 64 bit constant. */ | |
8606 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8607 | { |
8608 | imm_expr.X_op = O_constant; | |
8609 | offset_expr.X_op = O_constant; | |
8610 | if (! target_big_endian) | |
8611 | { | |
8612 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8613 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8614 | } | |
8615 | else | |
8616 | { | |
8617 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8618 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8619 | } | |
8620 | if (offset_expr.X_add_number == 0) | |
8621 | offset_expr.X_op = O_absent; | |
8622 | } | |
8623 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8624 | { | |
8625 | imm_expr.X_op = O_constant; | |
8626 | if (! target_big_endian) | |
8627 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8628 | else | |
8629 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8630 | } | |
8631 | else | |
8632 | { | |
8633 | imm_expr.X_op = O_big; | |
8634 | imm_expr.X_add_number = 4; | |
8635 | if (! target_big_endian) | |
8636 | { | |
8637 | generic_bignum[0] = bfd_getl16 (temp); | |
8638 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8639 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8640 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8641 | } | |
8642 | else | |
8643 | { | |
8644 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8645 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8646 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8647 | generic_bignum[3] = bfd_getb16 (temp); | |
8648 | } | |
8649 | } | |
8650 | } | |
8651 | else | |
8652 | { | |
8653 | const char *newname; | |
8654 | segT new_seg; | |
8655 | ||
8656 | /* Switch to the right section. */ | |
8657 | seg = now_seg; | |
8658 | subseg = now_subseg; | |
8659 | switch (*args) | |
8660 | { | |
8661 | default: /* unused default case avoids warnings. */ | |
8662 | case 'L': | |
8663 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8664 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8665 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8666 | newname = ".lit8"; |
8667 | break; | |
8668 | case 'F': | |
bb2d6cd7 GK |
8669 | if (mips_pic == EMBEDDED_PIC) |
8670 | newname = ".lit8"; | |
8671 | else | |
8672 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8673 | break; |
8674 | case 'l': | |
8675 | assert (!USE_GLOBAL_POINTER_OPT | |
8676 | || g_switch_value >= 4); | |
8677 | newname = ".lit4"; | |
8678 | break; | |
8679 | } | |
8680 | new_seg = subseg_new (newname, (subsegT) 0); | |
8681 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8682 | bfd_set_section_flags (stdoutput, new_seg, | |
8683 | (SEC_ALLOC | |
8684 | | SEC_LOAD | |
8685 | | SEC_READONLY | |
8686 | | SEC_DATA)); | |
8687 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8688 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8689 | && strcmp (TARGET_OS, "elf") != 0) | |
8690 | record_alignment (new_seg, 4); | |
8691 | else | |
8692 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8693 | if (seg == now_seg) | |
8694 | as_bad (_("Can't use floating point insn in this section")); | |
8695 | ||
8696 | /* Set the argument to the current address in the | |
8697 | section. */ | |
8698 | offset_expr.X_op = O_symbol; | |
8699 | offset_expr.X_add_symbol = | |
8700 | symbol_new ("L0\001", now_seg, | |
8701 | (valueT) frag_now_fix (), frag_now); | |
8702 | offset_expr.X_add_number = 0; | |
8703 | ||
8704 | /* Put the floating point number into the section. */ | |
8705 | p = frag_more ((int) length); | |
8706 | memcpy (p, temp, length); | |
8707 | ||
8708 | /* Switch back to the original section. */ | |
8709 | subseg_set (seg, subseg); | |
8710 | } | |
8711 | } | |
8712 | continue; | |
8713 | ||
8714 | case 'i': /* 16 bit unsigned immediate */ | |
8715 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8716 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8717 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8718 | if (c != S_EX_NONE) |
252b5132 | 8719 | { |
fb1b3232 | 8720 | if (c != S_EX_LO) |
252b5132 RH |
8721 | { |
8722 | if (imm_expr.X_op == O_constant) | |
8723 | imm_expr.X_add_number = | |
8724 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8725 | #ifdef OBJ_ELF |
fb1b3232 | 8726 | else if (c == S_EX_HIGHEST) |
98d3f06f | 8727 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8728 | else if (c == S_EX_HIGHER) |
98d3f06f | 8729 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8730 | else if (c == S_EX_GP_REL) |
8731 | { | |
8732 | /* This occurs in NewABI only. */ | |
8733 | c = my_getSmallExpression (&imm_expr, s); | |
8734 | if (c != S_EX_NEG) | |
8735 | as_bad (_("bad composition of relocations")); | |
8736 | else | |
8737 | { | |
8738 | c = my_getSmallExpression (&imm_expr, s); | |
8739 | if (c != S_EX_LO) | |
8740 | as_bad (_("bad composition of relocations")); | |
8741 | else | |
8742 | { | |
8743 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8744 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8745 | imm_reloc[2] = BFD_RELOC_LO16; | |
8746 | } | |
8747 | } | |
8748 | } | |
8749 | #endif | |
fb1b3232 | 8750 | else if (c == S_EX_HI) |
252b5132 | 8751 | { |
f6688943 | 8752 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8753 | imm_unmatched_hi = true; |
8754 | } | |
8755 | else | |
f6688943 | 8756 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8757 | } |
8758 | else if (imm_expr.X_op == O_constant) | |
8759 | imm_expr.X_add_number &= 0xffff; | |
8760 | } | |
8761 | if (*args == 'i') | |
8762 | { | |
fb1b3232 | 8763 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8764 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8765 | || imm_expr.X_add_number >= 0x10000) |
8766 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8767 | { |
8768 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8769 | !strcmp (insn->name, insn[1].name)) | |
8770 | break; | |
2ae7e77b AH |
8771 | if (imm_expr.X_op == O_constant |
8772 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8773 | as_bad (_("16 bit expression not in range 0..65535")); |
8774 | } | |
8775 | } | |
8776 | else | |
8777 | { | |
8778 | int more; | |
8779 | offsetT max; | |
8780 | ||
8781 | /* The upper bound should be 0x8000, but | |
8782 | unfortunately the MIPS assembler accepts numbers | |
8783 | from 0x8000 to 0xffff and sign extends them, and | |
8784 | we want to be compatible. We only permit this | |
8785 | extended range for an instruction which does not | |
8786 | provide any further alternates, since those | |
8787 | alternates may handle other cases. People should | |
8788 | use the numbers they mean, rather than relying on | |
8789 | a mysterious sign extension. */ | |
8790 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8791 | strcmp (insn->name, insn[1].name) == 0); | |
8792 | if (more) | |
8793 | max = 0x8000; | |
8794 | else | |
8795 | max = 0x10000; | |
fb1b3232 | 8796 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8797 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8798 | || imm_expr.X_add_number >= max) |
8799 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8800 | || (more |
8801 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8802 | && HAVE_64BIT_GPRS |
252b5132 RH |
8803 | && imm_expr.X_unsigned |
8804 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8805 | { | |
8806 | if (more) | |
8807 | break; | |
2ae7e77b AH |
8808 | if (imm_expr.X_op == O_constant |
8809 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8810 | as_bad (_("16 bit expression not in range -32768..32767")); |
8811 | } | |
8812 | } | |
8813 | s = expr_end; | |
8814 | continue; | |
8815 | ||
8816 | case 'o': /* 16 bit offset */ | |
8817 | c = my_getSmallExpression (&offset_expr, s); | |
8818 | ||
8819 | /* If this value won't fit into a 16 bit offset, then go | |
8820 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8821 | code pattern. */ |
fb1b3232 | 8822 | if (c == S_EX_NONE |
252b5132 RH |
8823 | && (offset_expr.X_op != O_constant |
8824 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8825 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8826 | break; |
8827 | ||
fb1b3232 | 8828 | if (c == S_EX_HI) |
252b5132 RH |
8829 | { |
8830 | if (offset_expr.X_op != O_constant) | |
8831 | break; | |
8832 | offset_expr.X_add_number = | |
8833 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8834 | } | |
f6688943 | 8835 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8836 | s = expr_end; |
8837 | continue; | |
8838 | ||
8839 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8840 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8841 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8842 | else |
f6688943 | 8843 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8844 | my_getExpression (&offset_expr, s); |
8845 | s = expr_end; | |
8846 | continue; | |
8847 | ||
8848 | case 'u': /* upper 16 bits */ | |
8849 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8850 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8851 | if (c != S_EX_NONE) |
252b5132 | 8852 | { |
fb1b3232 | 8853 | if (c != S_EX_LO) |
252b5132 RH |
8854 | { |
8855 | if (imm_expr.X_op == O_constant) | |
8856 | imm_expr.X_add_number = | |
8857 | (imm_expr.X_add_number >> 16) & 0xffff; | |
fb1b3232 | 8858 | else if (c == S_EX_HI) |
252b5132 | 8859 | { |
f6688943 | 8860 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8861 | imm_unmatched_hi = true; |
8862 | } | |
645dc66c TS |
8863 | #ifdef OBJ_ELF |
8864 | else if (c == S_EX_HIGHEST) | |
98d3f06f | 8865 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
ad8d3bb3 TS |
8866 | else if (c == S_EX_GP_REL) |
8867 | { | |
8868 | /* This occurs in NewABI only. */ | |
8869 | c = my_getSmallExpression (&imm_expr, s); | |
8870 | if (c != S_EX_NEG) | |
8871 | as_bad (_("bad composition of relocations")); | |
8872 | else | |
8873 | { | |
8874 | c = my_getSmallExpression (&imm_expr, s); | |
8875 | if (c != S_EX_HI) | |
8876 | as_bad (_("bad composition of relocations")); | |
8877 | else | |
8878 | { | |
8879 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8880 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8881 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8882 | } | |
8883 | } | |
8884 | } | |
8885 | #endif | |
252b5132 | 8886 | else |
f6688943 | 8887 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8888 | } |
8889 | else if (imm_expr.X_op == O_constant) | |
8890 | imm_expr.X_add_number &= 0xffff; | |
8891 | } | |
8892 | if (imm_expr.X_op == O_constant | |
8893 | && (imm_expr.X_add_number < 0 | |
8894 | || imm_expr.X_add_number >= 0x10000)) | |
8895 | as_bad (_("lui expression not in range 0..65535")); | |
8896 | s = expr_end; | |
8897 | continue; | |
8898 | ||
8899 | case 'a': /* 26 bit address */ | |
8900 | my_getExpression (&offset_expr, s); | |
8901 | s = expr_end; | |
f6688943 | 8902 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8903 | continue; |
8904 | ||
8905 | case 'N': /* 3 bit branch condition code */ | |
8906 | case 'M': /* 3 bit compare condition code */ | |
8907 | if (strncmp (s, "$fcc", 4) != 0) | |
8908 | break; | |
8909 | s += 4; | |
8910 | regno = 0; | |
8911 | do | |
8912 | { | |
8913 | regno *= 10; | |
8914 | regno += *s - '0'; | |
8915 | ++s; | |
8916 | } | |
3882b010 | 8917 | while (ISDIGIT (*s)); |
252b5132 RH |
8918 | if (regno > 7) |
8919 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8920 | if (*args == 'N') | |
8921 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8922 | else | |
8923 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8924 | continue; |
252b5132 | 8925 | |
156c2f8b NC |
8926 | case 'H': |
8927 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8928 | s += 2; | |
3882b010 | 8929 | if (ISDIGIT (*s)) |
156c2f8b NC |
8930 | { |
8931 | c = 0; | |
8932 | do | |
8933 | { | |
8934 | c *= 10; | |
8935 | c += *s - '0'; | |
8936 | ++s; | |
8937 | } | |
3882b010 | 8938 | while (ISDIGIT (*s)); |
156c2f8b NC |
8939 | } |
8940 | else | |
8941 | c = 8; /* Invalid sel value. */ | |
8942 | ||
8943 | if (c > 7) | |
8944 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8945 | ip->insn_opcode |= c; | |
8946 | continue; | |
8947 | ||
252b5132 RH |
8948 | default: |
8949 | as_bad (_("bad char = '%c'\n"), *args); | |
8950 | internalError (); | |
8951 | } | |
8952 | break; | |
8953 | } | |
8954 | /* Args don't match. */ | |
8955 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8956 | !strcmp (insn->name, insn[1].name)) | |
8957 | { | |
8958 | ++insn; | |
8959 | s = argsStart; | |
268f6bed | 8960 | insn_error = _("illegal operands"); |
252b5132 RH |
8961 | continue; |
8962 | } | |
268f6bed L |
8963 | if (save_c) |
8964 | *(--s) = save_c; | |
252b5132 RH |
8965 | insn_error = _("illegal operands"); |
8966 | return; | |
8967 | } | |
8968 | } | |
8969 | ||
8970 | /* This routine assembles an instruction into its binary format when | |
8971 | assembling for the mips16. As a side effect, it sets one of the | |
8972 | global variables imm_reloc or offset_reloc to the type of | |
8973 | relocation to do if one of the operands is an address expression. | |
8974 | It also sets mips16_small and mips16_ext if the user explicitly | |
8975 | requested a small or extended instruction. */ | |
8976 | ||
8977 | static void | |
8978 | mips16_ip (str, ip) | |
8979 | char *str; | |
8980 | struct mips_cl_insn *ip; | |
8981 | { | |
8982 | char *s; | |
8983 | const char *args; | |
8984 | struct mips_opcode *insn; | |
8985 | char *argsstart; | |
8986 | unsigned int regno; | |
8987 | unsigned int lastregno = 0; | |
8988 | char *s_reset; | |
8989 | ||
8990 | insn_error = NULL; | |
8991 | ||
8992 | mips16_small = false; | |
8993 | mips16_ext = false; | |
8994 | ||
3882b010 | 8995 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8996 | ; |
8997 | switch (*s) | |
8998 | { | |
8999 | case '\0': | |
9000 | break; | |
9001 | ||
9002 | case ' ': | |
9003 | *s++ = '\0'; | |
9004 | break; | |
9005 | ||
9006 | case '.': | |
9007 | if (s[1] == 't' && s[2] == ' ') | |
9008 | { | |
9009 | *s = '\0'; | |
9010 | mips16_small = true; | |
9011 | s += 3; | |
9012 | break; | |
9013 | } | |
9014 | else if (s[1] == 'e' && s[2] == ' ') | |
9015 | { | |
9016 | *s = '\0'; | |
9017 | mips16_ext = true; | |
9018 | s += 3; | |
9019 | break; | |
9020 | } | |
9021 | /* Fall through. */ | |
9022 | default: | |
9023 | insn_error = _("unknown opcode"); | |
9024 | return; | |
9025 | } | |
9026 | ||
9027 | if (mips_opts.noautoextend && ! mips16_ext) | |
9028 | mips16_small = true; | |
9029 | ||
9030 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9031 | { | |
9032 | insn_error = _("unrecognized opcode"); | |
9033 | return; | |
9034 | } | |
9035 | ||
9036 | argsstart = s; | |
9037 | for (;;) | |
9038 | { | |
9039 | assert (strcmp (insn->name, str) == 0); | |
9040 | ||
9041 | ip->insn_mo = insn; | |
9042 | ip->insn_opcode = insn->match; | |
9043 | ip->use_extend = false; | |
9044 | imm_expr.X_op = O_absent; | |
f6688943 TS |
9045 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9046 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9047 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9048 | offset_expr.X_op = O_absent; |
f6688943 TS |
9049 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9050 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9051 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9052 | for (args = insn->args; 1; ++args) |
9053 | { | |
9054 | int c; | |
9055 | ||
9056 | if (*s == ' ') | |
9057 | ++s; | |
9058 | ||
9059 | /* In this switch statement we call break if we did not find | |
9060 | a match, continue if we did find a match, or return if we | |
9061 | are done. */ | |
9062 | ||
9063 | c = *args; | |
9064 | switch (c) | |
9065 | { | |
9066 | case '\0': | |
9067 | if (*s == '\0') | |
9068 | { | |
9069 | /* Stuff the immediate value in now, if we can. */ | |
9070 | if (imm_expr.X_op == O_constant | |
f6688943 | 9071 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9072 | && insn->pinfo != INSN_MACRO) |
9073 | { | |
c4e7957c | 9074 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
9075 | imm_expr.X_add_number, true, mips16_small, |
9076 | mips16_ext, &ip->insn_opcode, | |
9077 | &ip->use_extend, &ip->extend); | |
9078 | imm_expr.X_op = O_absent; | |
f6688943 | 9079 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9080 | } |
9081 | ||
9082 | return; | |
9083 | } | |
9084 | break; | |
9085 | ||
9086 | case ',': | |
9087 | if (*s++ == c) | |
9088 | continue; | |
9089 | s--; | |
9090 | switch (*++args) | |
9091 | { | |
9092 | case 'v': | |
9093 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9094 | continue; | |
9095 | case 'w': | |
9096 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9097 | continue; | |
9098 | } | |
9099 | break; | |
9100 | ||
9101 | case '(': | |
9102 | case ')': | |
9103 | if (*s++ == c) | |
9104 | continue; | |
9105 | break; | |
9106 | ||
9107 | case 'v': | |
9108 | case 'w': | |
9109 | if (s[0] != '$') | |
9110 | { | |
9111 | if (c == 'v') | |
9112 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9113 | else | |
9114 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9115 | ++args; | |
9116 | continue; | |
9117 | } | |
9118 | /* Fall through. */ | |
9119 | case 'x': | |
9120 | case 'y': | |
9121 | case 'z': | |
9122 | case 'Z': | |
9123 | case '0': | |
9124 | case 'S': | |
9125 | case 'R': | |
9126 | case 'X': | |
9127 | case 'Y': | |
9128 | if (s[0] != '$') | |
9129 | break; | |
9130 | s_reset = s; | |
3882b010 | 9131 | if (ISDIGIT (s[1])) |
252b5132 RH |
9132 | { |
9133 | ++s; | |
9134 | regno = 0; | |
9135 | do | |
9136 | { | |
9137 | regno *= 10; | |
9138 | regno += *s - '0'; | |
9139 | ++s; | |
9140 | } | |
3882b010 | 9141 | while (ISDIGIT (*s)); |
252b5132 RH |
9142 | if (regno > 31) |
9143 | { | |
9144 | as_bad (_("invalid register number (%d)"), regno); | |
9145 | regno = 2; | |
9146 | } | |
9147 | } | |
9148 | else | |
9149 | { | |
9150 | if (s[1] == 'f' && s[2] == 'p') | |
9151 | { | |
9152 | s += 3; | |
9153 | regno = FP; | |
9154 | } | |
9155 | else if (s[1] == 's' && s[2] == 'p') | |
9156 | { | |
9157 | s += 3; | |
9158 | regno = SP; | |
9159 | } | |
9160 | else if (s[1] == 'g' && s[2] == 'p') | |
9161 | { | |
9162 | s += 3; | |
9163 | regno = GP; | |
9164 | } | |
9165 | else if (s[1] == 'a' && s[2] == 't') | |
9166 | { | |
9167 | s += 3; | |
9168 | regno = AT; | |
9169 | } | |
9170 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9171 | { | |
9172 | s += 4; | |
9173 | regno = KT0; | |
9174 | } | |
9175 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9176 | { | |
9177 | s += 4; | |
9178 | regno = KT1; | |
9179 | } | |
9180 | else | |
9181 | break; | |
9182 | } | |
9183 | ||
9184 | if (*s == ' ') | |
9185 | ++s; | |
9186 | if (args[1] != *s) | |
9187 | { | |
9188 | if (c == 'v' || c == 'w') | |
9189 | { | |
9190 | regno = mips16_to_32_reg_map[lastregno]; | |
9191 | s = s_reset; | |
f9419b05 | 9192 | ++args; |
252b5132 RH |
9193 | } |
9194 | } | |
9195 | ||
9196 | switch (c) | |
9197 | { | |
9198 | case 'x': | |
9199 | case 'y': | |
9200 | case 'z': | |
9201 | case 'v': | |
9202 | case 'w': | |
9203 | case 'Z': | |
9204 | regno = mips32_to_16_reg_map[regno]; | |
9205 | break; | |
9206 | ||
9207 | case '0': | |
9208 | if (regno != 0) | |
9209 | regno = ILLEGAL_REG; | |
9210 | break; | |
9211 | ||
9212 | case 'S': | |
9213 | if (regno != SP) | |
9214 | regno = ILLEGAL_REG; | |
9215 | break; | |
9216 | ||
9217 | case 'R': | |
9218 | if (regno != RA) | |
9219 | regno = ILLEGAL_REG; | |
9220 | break; | |
9221 | ||
9222 | case 'X': | |
9223 | case 'Y': | |
9224 | if (regno == AT && ! mips_opts.noat) | |
9225 | as_warn (_("used $at without \".set noat\"")); | |
9226 | break; | |
9227 | ||
9228 | default: | |
9229 | internalError (); | |
9230 | } | |
9231 | ||
9232 | if (regno == ILLEGAL_REG) | |
9233 | break; | |
9234 | ||
9235 | switch (c) | |
9236 | { | |
9237 | case 'x': | |
9238 | case 'v': | |
9239 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9240 | break; | |
9241 | case 'y': | |
9242 | case 'w': | |
9243 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9244 | break; | |
9245 | case 'z': | |
9246 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9247 | break; | |
9248 | case 'Z': | |
9249 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9250 | case '0': | |
9251 | case 'S': | |
9252 | case 'R': | |
9253 | break; | |
9254 | case 'X': | |
9255 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9256 | break; | |
9257 | case 'Y': | |
9258 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9259 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9260 | break; | |
9261 | default: | |
9262 | internalError (); | |
9263 | } | |
9264 | ||
9265 | lastregno = regno; | |
9266 | continue; | |
9267 | ||
9268 | case 'P': | |
9269 | if (strncmp (s, "$pc", 3) == 0) | |
9270 | { | |
9271 | s += 3; | |
9272 | continue; | |
9273 | } | |
9274 | break; | |
9275 | ||
9276 | case '<': | |
9277 | case '>': | |
9278 | case '[': | |
9279 | case ']': | |
9280 | case '4': | |
9281 | case '5': | |
9282 | case 'H': | |
9283 | case 'W': | |
9284 | case 'D': | |
9285 | case 'j': | |
9286 | case '8': | |
9287 | case 'V': | |
9288 | case 'C': | |
9289 | case 'U': | |
9290 | case 'k': | |
9291 | case 'K': | |
9292 | if (s[0] == '%' | |
9293 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9294 | { | |
9295 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9296 | and generate the appropriate reloc. If the text | |
9297 | inside %gprel is not a symbol name with an | |
9298 | optional offset, then we generate a normal reloc | |
9299 | and will probably fail later. */ | |
9300 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9301 | if (imm_expr.X_op == O_symbol) | |
9302 | { | |
9303 | mips16_ext = true; | |
f6688943 | 9304 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
9305 | s = expr_end; |
9306 | ip->use_extend = true; | |
9307 | ip->extend = 0; | |
9308 | continue; | |
9309 | } | |
9310 | } | |
9311 | else | |
9312 | { | |
9313 | /* Just pick up a normal expression. */ | |
9314 | my_getExpression (&imm_expr, s); | |
9315 | } | |
9316 | ||
9317 | if (imm_expr.X_op == O_register) | |
9318 | { | |
9319 | /* What we thought was an expression turned out to | |
9320 | be a register. */ | |
9321 | ||
9322 | if (s[0] == '(' && args[1] == '(') | |
9323 | { | |
9324 | /* It looks like the expression was omitted | |
9325 | before a register indirection, which means | |
9326 | that the expression is implicitly zero. We | |
9327 | still set up imm_expr, so that we handle | |
9328 | explicit extensions correctly. */ | |
9329 | imm_expr.X_op = O_constant; | |
9330 | imm_expr.X_add_number = 0; | |
f6688943 | 9331 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9332 | continue; |
9333 | } | |
9334 | ||
9335 | break; | |
9336 | } | |
9337 | ||
9338 | /* We need to relax this instruction. */ | |
f6688943 | 9339 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9340 | s = expr_end; |
9341 | continue; | |
9342 | ||
9343 | case 'p': | |
9344 | case 'q': | |
9345 | case 'A': | |
9346 | case 'B': | |
9347 | case 'E': | |
9348 | /* We use offset_reloc rather than imm_reloc for the PC | |
9349 | relative operands. This lets macros with both | |
9350 | immediate and address operands work correctly. */ | |
9351 | my_getExpression (&offset_expr, s); | |
9352 | ||
9353 | if (offset_expr.X_op == O_register) | |
9354 | break; | |
9355 | ||
9356 | /* We need to relax this instruction. */ | |
f6688943 | 9357 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9358 | s = expr_end; |
9359 | continue; | |
9360 | ||
9361 | case '6': /* break code */ | |
9362 | my_getExpression (&imm_expr, s); | |
9363 | check_absolute_expr (ip, &imm_expr); | |
9364 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9365 | { | |
9366 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9367 | ip->insn_mo->name, | |
9368 | (unsigned long) imm_expr.X_add_number); | |
9369 | imm_expr.X_add_number &= 0x3f; | |
9370 | } | |
9371 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9372 | imm_expr.X_op = O_absent; | |
9373 | s = expr_end; | |
9374 | continue; | |
9375 | ||
9376 | case 'a': /* 26 bit address */ | |
9377 | my_getExpression (&offset_expr, s); | |
9378 | s = expr_end; | |
f6688943 | 9379 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9380 | ip->insn_opcode <<= 16; |
9381 | continue; | |
9382 | ||
9383 | case 'l': /* register list for entry macro */ | |
9384 | case 'L': /* register list for exit macro */ | |
9385 | { | |
9386 | int mask; | |
9387 | ||
9388 | if (c == 'l') | |
9389 | mask = 0; | |
9390 | else | |
9391 | mask = 7 << 3; | |
9392 | while (*s != '\0') | |
9393 | { | |
9394 | int freg, reg1, reg2; | |
9395 | ||
9396 | while (*s == ' ' || *s == ',') | |
9397 | ++s; | |
9398 | if (*s != '$') | |
9399 | { | |
9400 | as_bad (_("can't parse register list")); | |
9401 | break; | |
9402 | } | |
9403 | ++s; | |
9404 | if (*s != 'f') | |
9405 | freg = 0; | |
9406 | else | |
9407 | { | |
9408 | freg = 1; | |
9409 | ++s; | |
9410 | } | |
9411 | reg1 = 0; | |
3882b010 | 9412 | while (ISDIGIT (*s)) |
252b5132 RH |
9413 | { |
9414 | reg1 *= 10; | |
9415 | reg1 += *s - '0'; | |
9416 | ++s; | |
9417 | } | |
9418 | if (*s == ' ') | |
9419 | ++s; | |
9420 | if (*s != '-') | |
9421 | reg2 = reg1; | |
9422 | else | |
9423 | { | |
9424 | ++s; | |
9425 | if (*s != '$') | |
9426 | break; | |
9427 | ++s; | |
9428 | if (freg) | |
9429 | { | |
9430 | if (*s == 'f') | |
9431 | ++s; | |
9432 | else | |
9433 | { | |
9434 | as_bad (_("invalid register list")); | |
9435 | break; | |
9436 | } | |
9437 | } | |
9438 | reg2 = 0; | |
3882b010 | 9439 | while (ISDIGIT (*s)) |
252b5132 RH |
9440 | { |
9441 | reg2 *= 10; | |
9442 | reg2 += *s - '0'; | |
9443 | ++s; | |
9444 | } | |
9445 | } | |
9446 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9447 | { | |
9448 | mask &= ~ (7 << 3); | |
9449 | mask |= 5 << 3; | |
9450 | } | |
9451 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9452 | { | |
9453 | mask &= ~ (7 << 3); | |
9454 | mask |= 6 << 3; | |
9455 | } | |
9456 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9457 | mask |= (reg2 - 3) << 3; | |
9458 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9459 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9460 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9461 | mask |= 1; |
9462 | else | |
9463 | { | |
9464 | as_bad (_("invalid register list")); | |
9465 | break; | |
9466 | } | |
9467 | } | |
9468 | /* The mask is filled in in the opcode table for the | |
9469 | benefit of the disassembler. We remove it before | |
9470 | applying the actual mask. */ | |
9471 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9472 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9473 | } | |
9474 | continue; | |
9475 | ||
9476 | case 'e': /* extend code */ | |
9477 | my_getExpression (&imm_expr, s); | |
9478 | check_absolute_expr (ip, &imm_expr); | |
9479 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9480 | { | |
9481 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9482 | ip->insn_mo->name, | |
9483 | (unsigned long) imm_expr.X_add_number); | |
9484 | imm_expr.X_add_number &= 0x7ff; | |
9485 | } | |
9486 | ip->insn_opcode |= imm_expr.X_add_number; | |
9487 | imm_expr.X_op = O_absent; | |
9488 | s = expr_end; | |
9489 | continue; | |
9490 | ||
9491 | default: | |
9492 | internalError (); | |
9493 | } | |
9494 | break; | |
9495 | } | |
9496 | ||
9497 | /* Args don't match. */ | |
9498 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9499 | strcmp (insn->name, insn[1].name) == 0) | |
9500 | { | |
9501 | ++insn; | |
9502 | s = argsstart; | |
9503 | continue; | |
9504 | } | |
9505 | ||
9506 | insn_error = _("illegal operands"); | |
9507 | ||
9508 | return; | |
9509 | } | |
9510 | } | |
9511 | ||
9512 | /* This structure holds information we know about a mips16 immediate | |
9513 | argument type. */ | |
9514 | ||
e972090a NC |
9515 | struct mips16_immed_operand |
9516 | { | |
252b5132 RH |
9517 | /* The type code used in the argument string in the opcode table. */ |
9518 | int type; | |
9519 | /* The number of bits in the short form of the opcode. */ | |
9520 | int nbits; | |
9521 | /* The number of bits in the extended form of the opcode. */ | |
9522 | int extbits; | |
9523 | /* The amount by which the short form is shifted when it is used; | |
9524 | for example, the sw instruction has a shift count of 2. */ | |
9525 | int shift; | |
9526 | /* The amount by which the short form is shifted when it is stored | |
9527 | into the instruction code. */ | |
9528 | int op_shift; | |
9529 | /* Non-zero if the short form is unsigned. */ | |
9530 | int unsp; | |
9531 | /* Non-zero if the extended form is unsigned. */ | |
9532 | int extu; | |
9533 | /* Non-zero if the value is PC relative. */ | |
9534 | int pcrel; | |
9535 | }; | |
9536 | ||
9537 | /* The mips16 immediate operand types. */ | |
9538 | ||
9539 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9540 | { | |
9541 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9542 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9543 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9544 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9545 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9546 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9547 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9548 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9549 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9550 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9551 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9552 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9553 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9554 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9555 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9556 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9557 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9558 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9559 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9560 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9561 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9562 | }; | |
9563 | ||
9564 | #define MIPS16_NUM_IMMED \ | |
9565 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9566 | ||
9567 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9568 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9569 | whether an extended value is needed; if one is needed, it sets | |
9570 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9571 | If SMALL is true, an unextended opcode was explicitly requested. | |
9572 | If EXT is true, an extended opcode was explicitly requested. If | |
9573 | WARN is true, warn if EXT does not match reality. */ | |
9574 | ||
9575 | static void | |
9576 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9577 | extend) | |
9578 | char *file; | |
9579 | unsigned int line; | |
9580 | int type; | |
9581 | offsetT val; | |
9582 | boolean warn; | |
9583 | boolean small; | |
9584 | boolean ext; | |
9585 | unsigned long *insn; | |
9586 | boolean *use_extend; | |
9587 | unsigned short *extend; | |
9588 | { | |
9589 | register const struct mips16_immed_operand *op; | |
9590 | int mintiny, maxtiny; | |
9591 | boolean needext; | |
9592 | ||
9593 | op = mips16_immed_operands; | |
9594 | while (op->type != type) | |
9595 | { | |
9596 | ++op; | |
9597 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9598 | } | |
9599 | ||
9600 | if (op->unsp) | |
9601 | { | |
9602 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9603 | { | |
9604 | mintiny = 1; | |
9605 | maxtiny = 1 << op->nbits; | |
9606 | } | |
9607 | else | |
9608 | { | |
9609 | mintiny = 0; | |
9610 | maxtiny = (1 << op->nbits) - 1; | |
9611 | } | |
9612 | } | |
9613 | else | |
9614 | { | |
9615 | mintiny = - (1 << (op->nbits - 1)); | |
9616 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9617 | } | |
9618 | ||
9619 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9620 | if (type == 'p' || type == 'q') | |
9621 | val /= 2; | |
9622 | ||
9623 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9624 | || val < (mintiny << op->shift) | |
9625 | || val > (maxtiny << op->shift)) | |
9626 | needext = true; | |
9627 | else | |
9628 | needext = false; | |
9629 | ||
9630 | if (warn && ext && ! needext) | |
beae10d5 KH |
9631 | as_warn_where (file, line, |
9632 | _("extended operand requested but not required")); | |
252b5132 RH |
9633 | if (small && needext) |
9634 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9635 | ||
9636 | if (small || (! ext && ! needext)) | |
9637 | { | |
9638 | int insnval; | |
9639 | ||
9640 | *use_extend = false; | |
9641 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9642 | insnval <<= op->op_shift; | |
9643 | *insn |= insnval; | |
9644 | } | |
9645 | else | |
9646 | { | |
9647 | long minext, maxext; | |
9648 | int extval; | |
9649 | ||
9650 | if (op->extu) | |
9651 | { | |
9652 | minext = 0; | |
9653 | maxext = (1 << op->extbits) - 1; | |
9654 | } | |
9655 | else | |
9656 | { | |
9657 | minext = - (1 << (op->extbits - 1)); | |
9658 | maxext = (1 << (op->extbits - 1)) - 1; | |
9659 | } | |
9660 | if (val < minext || val > maxext) | |
9661 | as_bad_where (file, line, | |
9662 | _("operand value out of range for instruction")); | |
9663 | ||
9664 | *use_extend = true; | |
9665 | if (op->extbits == 16) | |
9666 | { | |
9667 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9668 | val &= 0x1f; | |
9669 | } | |
9670 | else if (op->extbits == 15) | |
9671 | { | |
9672 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9673 | val &= 0xf; | |
9674 | } | |
9675 | else | |
9676 | { | |
9677 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9678 | val = 0; | |
9679 | } | |
9680 | ||
9681 | *extend = (unsigned short) extval; | |
9682 | *insn |= val; | |
9683 | } | |
9684 | } | |
9685 | \f | |
ad8d3bb3 TS |
9686 | static struct percent_op_match |
9687 | { | |
9688 | const char *str; | |
9689 | const enum small_ex_type type; | |
9690 | } percent_op[] = | |
9691 | { | |
ad8d3bb3 TS |
9692 | {"%lo", S_EX_LO}, |
9693 | #ifdef OBJ_ELF | |
394f9b3a TS |
9694 | {"%call_hi", S_EX_CALL_HI}, |
9695 | {"%call_lo", S_EX_CALL_LO}, | |
ad8d3bb3 TS |
9696 | {"%call16", S_EX_CALL16}, |
9697 | {"%got_disp", S_EX_GOT_DISP}, | |
9698 | {"%got_page", S_EX_GOT_PAGE}, | |
9699 | {"%got_ofst", S_EX_GOT_OFST}, | |
9700 | {"%got_hi", S_EX_GOT_HI}, | |
9701 | {"%got_lo", S_EX_GOT_LO}, | |
394f9b3a TS |
9702 | {"%got", S_EX_GOT}, |
9703 | {"%gp_rel", S_EX_GP_REL}, | |
9704 | {"%half", S_EX_HALF}, | |
ad8d3bb3 | 9705 | {"%highest", S_EX_HIGHEST}, |
394f9b3a TS |
9706 | {"%higher", S_EX_HIGHER}, |
9707 | {"%neg", S_EX_NEG}, | |
ad8d3bb3 | 9708 | #endif |
394f9b3a | 9709 | {"%hi", S_EX_HI} |
ad8d3bb3 TS |
9710 | }; |
9711 | ||
9712 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9713 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9714 | can be nested, this is handled by blanking the innermost, parsing the | |
9715 | rest by subsequent calls. */ | |
252b5132 RH |
9716 | |
9717 | static int | |
ad8d3bb3 TS |
9718 | my_getSmallParser (str, len, nestlevel) |
9719 | char **str; | |
9720 | unsigned int *len; | |
9721 | int *nestlevel; | |
252b5132 | 9722 | { |
ad8d3bb3 TS |
9723 | *len = 0; |
9724 | *str += strspn (*str, " \t"); | |
394f9b3a | 9725 | /* Check for expression in parentheses. */ |
ad8d3bb3 | 9726 | if (**str == '(') |
252b5132 | 9727 | { |
ad8d3bb3 TS |
9728 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9729 | char *e; | |
9730 | ||
9731 | /* Check for base register. */ | |
9732 | if (b[0] == '$') | |
9733 | { | |
9734 | if (strchr (b, ')') | |
9735 | && (e = b + strcspn (b, ") \t")) | |
9736 | && e - b > 1 && e - b < 4) | |
9737 | { | |
98d3f06f KH |
9738 | if ((e - b == 3 |
9739 | && ((b[1] == 'f' && b[2] == 'p') | |
9740 | || (b[1] == 's' && b[2] == 'p') | |
9741 | || (b[1] == 'g' && b[2] == 'p') | |
9742 | || (b[1] == 'a' && b[2] == 't') | |
9743 | || (ISDIGIT (b[1]) | |
9744 | && ISDIGIT (b[2])))) | |
9745 | || (ISDIGIT (b[1]))) | |
9746 | { | |
9747 | *len = strcspn (*str, ")") + 1; | |
9748 | return S_EX_REGISTER; | |
9749 | } | |
ad8d3bb3 TS |
9750 | } |
9751 | } | |
394f9b3a | 9752 | /* Check for percent_op (in parentheses). */ |
ad8d3bb3 TS |
9753 | else if (b[0] == '%') |
9754 | { | |
9755 | *str = b; | |
394f9b3a | 9756 | return my_getPercentOp (str, len, nestlevel); |
ad8d3bb3 | 9757 | } |
76b3015f | 9758 | |
394f9b3a TS |
9759 | /* Some other expression in the parentheses, which can contain |
9760 | parentheses itself. Attempt to find the matching one. */ | |
9761 | { | |
9762 | int pcnt = 1; | |
9763 | char *s; | |
9764 | ||
9765 | *len = 1; | |
9766 | for (s = *str + 1; *s && pcnt; s++, (*len)++) | |
9767 | { | |
9768 | if (*s == '(') | |
f9419b05 | 9769 | ++pcnt; |
394f9b3a | 9770 | else if (*s == ')') |
f9419b05 | 9771 | --pcnt; |
394f9b3a TS |
9772 | } |
9773 | } | |
fb1b3232 | 9774 | } |
394f9b3a | 9775 | /* Check for percent_op (outside of parentheses). */ |
ad8d3bb3 | 9776 | else if (*str[0] == '%') |
394f9b3a TS |
9777 | return my_getPercentOp (str, len, nestlevel); |
9778 | ||
9779 | /* Any other expression. */ | |
9780 | return S_EX_NONE; | |
9781 | } | |
ad8d3bb3 | 9782 | |
394f9b3a TS |
9783 | static int |
9784 | my_getPercentOp (str, len, nestlevel) | |
9785 | char **str; | |
9786 | unsigned int *len; | |
9787 | int *nestlevel; | |
9788 | { | |
9789 | char *tmp = *str + 1; | |
9790 | unsigned int i = 0; | |
ad8d3bb3 | 9791 | |
394f9b3a TS |
9792 | while (ISALPHA (*tmp) || *tmp == '_') |
9793 | { | |
9794 | *tmp = TOLOWER (*tmp); | |
9795 | tmp++; | |
9796 | } | |
9797 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9798 | { | |
9799 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
98d3f06f | 9800 | i++; |
394f9b3a | 9801 | else |
ad8d3bb3 | 9802 | { |
394f9b3a | 9803 | int type = percent_op[i].type; |
ad8d3bb3 | 9804 | |
394f9b3a TS |
9805 | /* Only %hi and %lo are allowed for OldABI. */ |
9806 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9807 | return S_EX_NONE; | |
ad8d3bb3 | 9808 | |
394f9b3a | 9809 | *len = strlen (percent_op[i].str); |
f9419b05 | 9810 | ++(*nestlevel); |
394f9b3a | 9811 | return type; |
ad8d3bb3 | 9812 | } |
fb1b3232 | 9813 | } |
ad8d3bb3 TS |
9814 | return S_EX_NONE; |
9815 | } | |
9816 | ||
9817 | static int | |
9818 | my_getSmallExpression (ep, str) | |
9819 | expressionS *ep; | |
9820 | char *str; | |
9821 | { | |
9822 | static char *oldstr = NULL; | |
9823 | int c = S_EX_NONE; | |
9824 | int oldc; | |
394f9b3a | 9825 | int nestlevel = -1; |
ad8d3bb3 TS |
9826 | unsigned int len; |
9827 | ||
394f9b3a TS |
9828 | /* Don't update oldstr if the last call had nested percent_op's. We need |
9829 | it to parse the outer ones later. */ | |
ad8d3bb3 TS |
9830 | if (! oldstr) |
9831 | oldstr = str; | |
76b3015f | 9832 | |
ad8d3bb3 | 9833 | do |
fb1b3232 | 9834 | { |
ad8d3bb3 | 9835 | oldc = c; |
394f9b3a | 9836 | c = my_getSmallParser (&str, &len, &nestlevel); |
ad8d3bb3 TS |
9837 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
9838 | str += len; | |
fb1b3232 | 9839 | } |
ad8d3bb3 TS |
9840 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9841 | ||
394f9b3a | 9842 | if (nestlevel >= 0) |
fb1b3232 | 9843 | { |
394f9b3a TS |
9844 | /* A percent_op was encountered. Don't try to get an expression if |
9845 | it is already blanked out. */ | |
ad8d3bb3 TS |
9846 | if (*(str + strspn (str + 1, " )")) != ')') |
9847 | { | |
9848 | char save; | |
9849 | ||
394f9b3a | 9850 | /* Let my_getExpression() stop at the closing parenthesis. */ |
ad8d3bb3 TS |
9851 | save = *(str + len); |
9852 | *(str + len) = '\0'; | |
9853 | my_getExpression (ep, str); | |
9854 | *(str + len) = save; | |
9855 | } | |
394f9b3a | 9856 | if (nestlevel > 0) |
ad8d3bb3 | 9857 | { |
394f9b3a TS |
9858 | /* Blank out including the % sign and the proper matching |
9859 | parenthesis. */ | |
9860 | int pcnt = 1; | |
9861 | char *s = strrchr (oldstr, '%'); | |
9862 | char *end; | |
9863 | ||
9864 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) | |
9865 | { | |
9866 | if (*end == '(') | |
f9419b05 | 9867 | ++pcnt; |
394f9b3a | 9868 | else if (*end == ')') |
f9419b05 | 9869 | --pcnt; |
394f9b3a TS |
9870 | } |
9871 | ||
9872 | memset (s, ' ', end - s); | |
ad8d3bb3 TS |
9873 | str = oldstr; |
9874 | } | |
9875 | else | |
394f9b3a TS |
9876 | expr_end = str + len; |
9877 | ||
ad8d3bb3 | 9878 | c = oldc; |
fb1b3232 | 9879 | } |
ad8d3bb3 | 9880 | else if (c == S_EX_NONE) |
fb1b3232 | 9881 | { |
ad8d3bb3 | 9882 | my_getExpression (ep, str); |
fb1b3232 | 9883 | } |
ad8d3bb3 | 9884 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9885 | { |
ad8d3bb3 TS |
9886 | ep->X_op = O_constant; |
9887 | expr_end = str; | |
9888 | ep->X_add_symbol = NULL; | |
9889 | ep->X_op_symbol = NULL; | |
9890 | ep->X_add_number = 0; | |
fb1b3232 | 9891 | } |
fb1b3232 TS |
9892 | else |
9893 | { | |
98d3f06f | 9894 | as_fatal (_("internal error")); |
fb1b3232 | 9895 | } |
252b5132 | 9896 | |
394f9b3a TS |
9897 | if (nestlevel <= 0) |
9898 | /* All percent_op's have been handled. */ | |
ad8d3bb3 | 9899 | oldstr = NULL; |
fb1b3232 | 9900 | |
fb1b3232 | 9901 | return c; |
252b5132 RH |
9902 | } |
9903 | ||
9904 | static void | |
9905 | my_getExpression (ep, str) | |
9906 | expressionS *ep; | |
9907 | char *str; | |
9908 | { | |
9909 | char *save_in; | |
98aa84af | 9910 | valueT val; |
252b5132 RH |
9911 | |
9912 | save_in = input_line_pointer; | |
9913 | input_line_pointer = str; | |
9914 | expression (ep); | |
9915 | expr_end = input_line_pointer; | |
9916 | input_line_pointer = save_in; | |
9917 | ||
9918 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9919 | then we bump the value of the symbol by 1 since that is how other | |
9920 | text symbols are handled. We don't bother to handle complex | |
9921 | expressions, just `.' plus or minus a constant. */ | |
9922 | if (mips_opts.mips16 | |
9923 | && ep->X_op == O_symbol | |
9924 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9925 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9926 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9927 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9928 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9929 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9930 | } |
9931 | ||
9932 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9933 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9934 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9935 | returned, or NULL on OK. */ |
9936 | ||
9937 | char * | |
9938 | md_atof (type, litP, sizeP) | |
9939 | int type; | |
9940 | char *litP; | |
9941 | int *sizeP; | |
9942 | { | |
9943 | int prec; | |
9944 | LITTLENUM_TYPE words[4]; | |
9945 | char *t; | |
9946 | int i; | |
9947 | ||
9948 | switch (type) | |
9949 | { | |
9950 | case 'f': | |
9951 | prec = 2; | |
9952 | break; | |
9953 | ||
9954 | case 'd': | |
9955 | prec = 4; | |
9956 | break; | |
9957 | ||
9958 | default: | |
9959 | *sizeP = 0; | |
9960 | return _("bad call to md_atof"); | |
9961 | } | |
9962 | ||
9963 | t = atof_ieee (input_line_pointer, type, words); | |
9964 | if (t) | |
9965 | input_line_pointer = t; | |
9966 | ||
9967 | *sizeP = prec * 2; | |
9968 | ||
9969 | if (! target_big_endian) | |
9970 | { | |
9971 | for (i = prec - 1; i >= 0; i--) | |
9972 | { | |
9973 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9974 | litP += 2; | |
9975 | } | |
9976 | } | |
9977 | else | |
9978 | { | |
9979 | for (i = 0; i < prec; i++) | |
9980 | { | |
9981 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9982 | litP += 2; | |
9983 | } | |
9984 | } | |
bdaaa2e1 | 9985 | |
252b5132 RH |
9986 | return NULL; |
9987 | } | |
9988 | ||
9989 | void | |
9990 | md_number_to_chars (buf, val, n) | |
9991 | char *buf; | |
9992 | valueT val; | |
9993 | int n; | |
9994 | { | |
9995 | if (target_big_endian) | |
9996 | number_to_chars_bigendian (buf, val, n); | |
9997 | else | |
9998 | number_to_chars_littleendian (buf, val, n); | |
9999 | } | |
10000 | \f | |
ae948b86 | 10001 | #ifdef OBJ_ELF |
e013f690 TS |
10002 | static int support_64bit_objects(void) |
10003 | { | |
10004 | const char **list, **l; | |
10005 | ||
10006 | list = bfd_target_list (); | |
10007 | for (l = list; *l != NULL; l++) | |
10008 | #ifdef TE_TMIPS | |
10009 | /* This is traditional mips */ | |
10010 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10011 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10012 | #else | |
10013 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10014 | || strcmp (*l, "elf64-littlemips") == 0) | |
10015 | #endif | |
10016 | break; | |
10017 | free (list); | |
10018 | return (*l != NULL); | |
10019 | } | |
ae948b86 | 10020 | #endif /* OBJ_ELF */ |
e013f690 | 10021 | |
39c0a331 | 10022 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 10023 | |
e972090a NC |
10024 | struct option md_longopts[] = |
10025 | { | |
252b5132 RH |
10026 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
10027 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
10028 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
10029 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
10030 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
10031 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
10032 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
10033 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
10034 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
10035 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
10036 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
10037 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
10038 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
10039 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
10040 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
10041 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 10042 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 10043 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
10044 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10045 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 10046 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
10047 | {"break", no_argument, NULL, OPTION_BREAK}, |
10048 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 10049 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 10050 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 10051 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 10052 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 10053 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 10054 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 10055 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 10056 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 10057 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 10058 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
9ee72ff1 TS |
10059 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
10060 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10061 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
ae948b86 TS |
10062 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
10063 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
10064 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 10065 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 10066 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 10067 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 10068 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 10069 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 10070 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 10071 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 10072 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 10073 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
ae948b86 TS |
10074 | #define OPTION_MCPU (OPTION_MD_BASE + 23) |
10075 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
10076 | #define OPTION_M4650 (OPTION_MD_BASE + 24) | |
10077 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10078 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
10079 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10080 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
10081 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10082 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
10083 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10084 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
10085 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10086 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
10087 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10088 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
10089 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10090 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
10091 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10092 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
10093 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
10094 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
10095 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10096 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
10097 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
deec1734 CD |
10098 | #define OPTION_MDMX (OPTION_MD_BASE + 35) |
10099 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10100 | #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) | |
10101 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
156c2f8b | 10102 | #ifdef OBJ_ELF |
deec1734 | 10103 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 37) |
156c2f8b | 10104 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10105 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10106 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10107 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10108 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10109 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10110 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10111 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10112 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10113 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10114 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10115 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10116 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10117 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10118 | {"64", no_argument, NULL, OPTION_64}, |
ae948b86 | 10119 | #endif /* OBJ_ELF */ |
252b5132 RH |
10120 | {NULL, no_argument, NULL, 0} |
10121 | }; | |
156c2f8b | 10122 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
10123 | |
10124 | int | |
10125 | md_parse_option (c, arg) | |
10126 | int c; | |
10127 | char *arg; | |
10128 | { | |
10129 | switch (c) | |
10130 | { | |
119d663a NC |
10131 | case OPTION_CONSTRUCT_FLOATS: |
10132 | mips_disable_float_construction = 0; | |
10133 | break; | |
bdaaa2e1 | 10134 | |
119d663a NC |
10135 | case OPTION_NO_CONSTRUCT_FLOATS: |
10136 | mips_disable_float_construction = 1; | |
10137 | break; | |
bdaaa2e1 | 10138 | |
252b5132 RH |
10139 | case OPTION_TRAP: |
10140 | mips_trap = 1; | |
10141 | break; | |
10142 | ||
10143 | case OPTION_BREAK: | |
10144 | mips_trap = 0; | |
10145 | break; | |
10146 | ||
10147 | case OPTION_EB: | |
10148 | target_big_endian = 1; | |
10149 | break; | |
10150 | ||
10151 | case OPTION_EL: | |
10152 | target_big_endian = 0; | |
10153 | break; | |
10154 | ||
39c0a331 L |
10155 | case 'n': |
10156 | warn_nops = 1; | |
10157 | break; | |
10158 | ||
252b5132 RH |
10159 | case 'O': |
10160 | if (arg && arg[1] == '0') | |
10161 | mips_optimize = 1; | |
10162 | else | |
10163 | mips_optimize = 2; | |
10164 | break; | |
10165 | ||
10166 | case 'g': | |
10167 | if (arg == NULL) | |
10168 | mips_debug = 2; | |
10169 | else | |
10170 | mips_debug = atoi (arg); | |
10171 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10172 | optimizations which limit full symbolic debugging. We take | |
10173 | that to be equivalent to -O0. */ | |
10174 | if (mips_debug == 2) | |
10175 | mips_optimize = 1; | |
10176 | break; | |
10177 | ||
10178 | case OPTION_MIPS1: | |
e7af610e | 10179 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
10180 | break; |
10181 | ||
10182 | case OPTION_MIPS2: | |
e7af610e | 10183 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
10184 | break; |
10185 | ||
10186 | case OPTION_MIPS3: | |
e7af610e | 10187 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
10188 | break; |
10189 | ||
10190 | case OPTION_MIPS4: | |
e7af610e NC |
10191 | mips_opts.isa = ISA_MIPS4; |
10192 | break; | |
10193 | ||
84ea6cf2 NC |
10194 | case OPTION_MIPS5: |
10195 | mips_opts.isa = ISA_MIPS5; | |
10196 | break; | |
10197 | ||
e7af610e NC |
10198 | case OPTION_MIPS32: |
10199 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
10200 | break; |
10201 | ||
84ea6cf2 NC |
10202 | case OPTION_MIPS64: |
10203 | mips_opts.isa = ISA_MIPS64; | |
10204 | break; | |
10205 | ||
ec68c924 EC |
10206 | case OPTION_MTUNE: |
10207 | case OPTION_MARCH: | |
252b5132 RH |
10208 | case OPTION_MCPU: |
10209 | { | |
ec68c924 EC |
10210 | int cpu = CPU_UNKNOWN; |
10211 | ||
e7af610e | 10212 | /* Identify the processor type. */ |
ec68c924 | 10213 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 10214 | { |
e7af610e | 10215 | const struct mips_cpu_info *ci; |
252b5132 | 10216 | |
e7af610e NC |
10217 | ci = mips_cpu_info_from_name (arg); |
10218 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
10219 | { |
10220 | switch (c) | |
10221 | { | |
10222 | case OPTION_MTUNE: | |
10223 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
10224 | break; | |
10225 | case OPTION_MARCH: | |
10226 | as_fatal (_("invalid architecture -march=%s"), arg); | |
10227 | break; | |
10228 | case OPTION_MCPU: | |
10229 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
10230 | break; | |
10231 | } | |
10232 | } | |
e7af610e | 10233 | else |
98d3f06f | 10234 | cpu = ci->cpu; |
ec68c924 EC |
10235 | } |
10236 | ||
10237 | switch (c) | |
10238 | { | |
10239 | case OPTION_MTUNE: | |
6dce9e24 | 10240 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
98d3f06f KH |
10241 | as_warn (_("A different -mtune= was already specified, is now " |
10242 | "-mtune=%s"), arg); | |
ec68c924 EC |
10243 | mips_tune = cpu; |
10244 | break; | |
10245 | case OPTION_MARCH: | |
6dce9e24 | 10246 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
98d3f06f KH |
10247 | as_warn (_("A different -march= was already specified, is now " |
10248 | "-march=%s"), arg); | |
ec68c924 EC |
10249 | mips_arch = cpu; |
10250 | break; | |
10251 | case OPTION_MCPU: | |
6dce9e24 | 10252 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
98d3f06f KH |
10253 | as_warn (_("A different -mcpu= was already specified, is now " |
10254 | "-mcpu=%s"), arg); | |
ec68c924 | 10255 | mips_cpu = cpu; |
252b5132 RH |
10256 | } |
10257 | } | |
10258 | break; | |
10259 | ||
10260 | case OPTION_M4650: | |
6dce9e24 TS |
10261 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
10262 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
98d3f06f KH |
10263 | as_warn (_("A different -march= or -mtune= was already specified, " |
10264 | "is now -m4650")); | |
ec68c924 EC |
10265 | mips_arch = CPU_R4650; |
10266 | mips_tune = CPU_R4650; | |
252b5132 RH |
10267 | break; |
10268 | ||
10269 | case OPTION_NO_M4650: | |
10270 | break; | |
10271 | ||
10272 | case OPTION_M4010: | |
6dce9e24 TS |
10273 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
10274 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
98d3f06f KH |
10275 | as_warn (_("A different -march= or -mtune= was already specified, " |
10276 | "is now -m4010")); | |
ec68c924 EC |
10277 | mips_arch = CPU_R4010; |
10278 | mips_tune = CPU_R4010; | |
252b5132 RH |
10279 | break; |
10280 | ||
10281 | case OPTION_NO_M4010: | |
10282 | break; | |
10283 | ||
10284 | case OPTION_M4100: | |
6dce9e24 TS |
10285 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
10286 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
98d3f06f KH |
10287 | as_warn (_("A different -march= or -mtune= was already specified, " |
10288 | "is now -m4100")); | |
ec68c924 EC |
10289 | mips_arch = CPU_VR4100; |
10290 | mips_tune = CPU_VR4100; | |
252b5132 RH |
10291 | break; |
10292 | ||
10293 | case OPTION_NO_M4100: | |
10294 | break; | |
10295 | ||
252b5132 | 10296 | case OPTION_M3900: |
6dce9e24 TS |
10297 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
10298 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
98d3f06f KH |
10299 | as_warn (_("A different -march= or -mtune= was already specified, " |
10300 | "is now -m3900")); | |
ec68c924 EC |
10301 | mips_arch = CPU_R3900; |
10302 | mips_tune = CPU_R3900; | |
252b5132 | 10303 | break; |
bdaaa2e1 | 10304 | |
252b5132 RH |
10305 | case OPTION_NO_M3900: |
10306 | break; | |
10307 | ||
deec1734 CD |
10308 | case OPTION_MDMX: |
10309 | mips_opts.ase_mdmx = 1; | |
10310 | break; | |
10311 | ||
10312 | case OPTION_NO_MDMX: | |
10313 | mips_opts.ase_mdmx = 0; | |
10314 | break; | |
10315 | ||
252b5132 RH |
10316 | case OPTION_MIPS16: |
10317 | mips_opts.mips16 = 1; | |
10318 | mips_no_prev_insn (false); | |
10319 | break; | |
10320 | ||
10321 | case OPTION_NO_MIPS16: | |
10322 | mips_opts.mips16 = 0; | |
10323 | mips_no_prev_insn (false); | |
10324 | break; | |
10325 | ||
1f25f5d3 CD |
10326 | case OPTION_MIPS3D: |
10327 | mips_opts.ase_mips3d = 1; | |
10328 | break; | |
10329 | ||
10330 | case OPTION_NO_MIPS3D: | |
10331 | mips_opts.ase_mips3d = 0; | |
10332 | break; | |
10333 | ||
252b5132 RH |
10334 | case OPTION_MEMBEDDED_PIC: |
10335 | mips_pic = EMBEDDED_PIC; | |
10336 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10337 | { | |
10338 | as_bad (_("-G may not be used with embedded PIC code")); | |
10339 | return 0; | |
10340 | } | |
10341 | g_switch_value = 0x7fffffff; | |
10342 | break; | |
10343 | ||
0f074f60 | 10344 | #ifdef OBJ_ELF |
252b5132 RH |
10345 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10346 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10347 | intended to be compatible with Irix 5. */ | |
10348 | case OPTION_CALL_SHARED: | |
10349 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10350 | { | |
10351 | as_bad (_("-call_shared is supported only for ELF format")); | |
10352 | return 0; | |
10353 | } | |
10354 | mips_pic = SVR4_PIC; | |
10355 | if (g_switch_seen && g_switch_value != 0) | |
10356 | { | |
10357 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10358 | return 0; | |
10359 | } | |
10360 | g_switch_value = 0; | |
10361 | break; | |
10362 | ||
10363 | case OPTION_NON_SHARED: | |
10364 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10365 | { | |
10366 | as_bad (_("-non_shared is supported only for ELF format")); | |
10367 | return 0; | |
10368 | } | |
10369 | mips_pic = NO_PIC; | |
10370 | break; | |
10371 | ||
10372 | /* The -xgot option tells the assembler to use 32 offsets when | |
10373 | accessing the got in SVR4_PIC mode. It is for Irix | |
10374 | compatibility. */ | |
10375 | case OPTION_XGOT: | |
10376 | mips_big_got = 1; | |
10377 | break; | |
0f074f60 | 10378 | #endif /* OBJ_ELF */ |
252b5132 RH |
10379 | |
10380 | case 'G': | |
10381 | if (! USE_GLOBAL_POINTER_OPT) | |
10382 | { | |
10383 | as_bad (_("-G is not supported for this configuration")); | |
10384 | return 0; | |
10385 | } | |
10386 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10387 | { | |
10388 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10389 | return 0; | |
10390 | } | |
10391 | else | |
10392 | g_switch_value = atoi (arg); | |
10393 | g_switch_seen = 1; | |
10394 | break; | |
10395 | ||
0f074f60 | 10396 | #ifdef OBJ_ELF |
34ba82a8 TS |
10397 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10398 | and -mabi=64. */ | |
252b5132 | 10399 | case OPTION_32: |
34ba82a8 TS |
10400 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10401 | { | |
10402 | as_bad (_("-32 is supported for ELF format only")); | |
10403 | return 0; | |
10404 | } | |
a325df1d | 10405 | mips_opts.abi = O32_ABI; |
252b5132 RH |
10406 | break; |
10407 | ||
e013f690 | 10408 | case OPTION_N32: |
34ba82a8 TS |
10409 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10410 | { | |
10411 | as_bad (_("-n32 is supported for ELF format only")); | |
10412 | return 0; | |
10413 | } | |
a325df1d | 10414 | mips_opts.abi = N32_ABI; |
e013f690 | 10415 | break; |
252b5132 | 10416 | |
e013f690 | 10417 | case OPTION_64: |
34ba82a8 TS |
10418 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10419 | { | |
10420 | as_bad (_("-64 is supported for ELF format only")); | |
10421 | return 0; | |
10422 | } | |
a325df1d | 10423 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10424 | if (! support_64bit_objects()) |
10425 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10426 | break; |
ae948b86 | 10427 | #endif /* OBJ_ELF */ |
252b5132 | 10428 | |
c97ef257 | 10429 | case OPTION_GP32: |
a325df1d TS |
10430 | file_mips_gp32 = 1; |
10431 | if (mips_opts.abi != O32_ABI) | |
10432 | mips_opts.abi = NO_ABI; | |
c97ef257 AH |
10433 | break; |
10434 | ||
10435 | case OPTION_GP64: | |
a325df1d TS |
10436 | file_mips_gp32 = 0; |
10437 | if (mips_opts.abi == O32_ABI) | |
10438 | mips_opts.abi = NO_ABI; | |
c97ef257 | 10439 | break; |
252b5132 | 10440 | |
ca4e0257 | 10441 | case OPTION_FP32: |
a325df1d TS |
10442 | file_mips_fp32 = 1; |
10443 | if (mips_opts.abi != O32_ABI) | |
10444 | mips_opts.abi = NO_ABI; | |
ca4e0257 RS |
10445 | break; |
10446 | ||
ae948b86 | 10447 | #ifdef OBJ_ELF |
252b5132 | 10448 | case OPTION_MABI: |
34ba82a8 TS |
10449 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10450 | { | |
10451 | as_bad (_("-mabi is supported for ELF format only")); | |
10452 | return 0; | |
10453 | } | |
e013f690 | 10454 | if (strcmp (arg, "32") == 0) |
a325df1d | 10455 | mips_opts.abi = O32_ABI; |
e013f690 | 10456 | else if (strcmp (arg, "o64") == 0) |
a325df1d | 10457 | mips_opts.abi = O64_ABI; |
e013f690 | 10458 | else if (strcmp (arg, "n32") == 0) |
a325df1d | 10459 | mips_opts.abi = N32_ABI; |
e013f690 TS |
10460 | else if (strcmp (arg, "64") == 0) |
10461 | { | |
a325df1d | 10462 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10463 | if (! support_64bit_objects()) |
10464 | as_fatal (_("No compiled in support for 64 bit object file " | |
10465 | "format")); | |
10466 | } | |
10467 | else if (strcmp (arg, "eabi") == 0) | |
a325df1d | 10468 | mips_opts.abi = EABI_ABI; |
e013f690 | 10469 | else |
da0e507f TS |
10470 | { |
10471 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10472 | return 0; | |
10473 | } | |
252b5132 | 10474 | break; |
e013f690 | 10475 | #endif /* OBJ_ELF */ |
252b5132 | 10476 | |
6b76fefe CM |
10477 | case OPTION_M7000_HILO_FIX: |
10478 | mips_7000_hilo_fix = true; | |
10479 | break; | |
10480 | ||
9ee72ff1 | 10481 | case OPTION_MNO_7000_HILO_FIX: |
6b76fefe CM |
10482 | mips_7000_hilo_fix = false; |
10483 | break; | |
10484 | ||
252b5132 RH |
10485 | default: |
10486 | return 0; | |
10487 | } | |
10488 | ||
10489 | return 1; | |
10490 | } | |
10491 | ||
252b5132 RH |
10492 | static void |
10493 | show (stream, string, col_p, first_p) | |
10494 | FILE *stream; | |
10495 | char *string; | |
10496 | int *col_p; | |
10497 | int *first_p; | |
10498 | { | |
10499 | if (*first_p) | |
10500 | { | |
10501 | fprintf (stream, "%24s", ""); | |
10502 | *col_p = 24; | |
10503 | } | |
10504 | else | |
10505 | { | |
10506 | fprintf (stream, ", "); | |
10507 | *col_p += 2; | |
10508 | } | |
10509 | ||
10510 | if (*col_p + strlen (string) > 72) | |
10511 | { | |
10512 | fprintf (stream, "\n%24s", ""); | |
10513 | *col_p = 24; | |
10514 | } | |
10515 | ||
10516 | fprintf (stream, "%s", string); | |
10517 | *col_p += strlen (string); | |
10518 | ||
10519 | *first_p = 0; | |
10520 | } | |
10521 | ||
252b5132 RH |
10522 | void |
10523 | md_show_usage (stream) | |
10524 | FILE *stream; | |
10525 | { | |
10526 | int column, first; | |
10527 | ||
beae10d5 | 10528 | fprintf (stream, _("\ |
252b5132 RH |
10529 | MIPS options:\n\ |
10530 | -membedded-pic generate embedded position independent code\n\ | |
10531 | -EB generate big endian output\n\ | |
10532 | -EL generate little endian output\n\ | |
9a41af64 | 10533 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
10534 | -G NUM allow referencing objects up to NUM bytes\n\ |
10535 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 10536 | fprintf (stream, _("\ |
252b5132 RH |
10537 | -mips1 generate MIPS ISA I instructions\n\ |
10538 | -mips2 generate MIPS ISA II instructions\n\ | |
10539 | -mips3 generate MIPS ISA III instructions\n\ | |
10540 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 10541 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 10542 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 10543 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 10544 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
10545 | |
10546 | first = 1; | |
10547 | ||
10548 | show (stream, "2000", &column, &first); | |
10549 | show (stream, "3000", &column, &first); | |
10550 | show (stream, "3900", &column, &first); | |
10551 | show (stream, "4000", &column, &first); | |
10552 | show (stream, "4010", &column, &first); | |
10553 | show (stream, "4100", &column, &first); | |
10554 | show (stream, "4111", &column, &first); | |
10555 | show (stream, "4300", &column, &first); | |
10556 | show (stream, "4400", &column, &first); | |
10557 | show (stream, "4600", &column, &first); | |
10558 | show (stream, "4650", &column, &first); | |
10559 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
10560 | show (stream, "5200", &column, &first); |
10561 | show (stream, "5230", &column, &first); | |
10562 | show (stream, "5231", &column, &first); | |
10563 | show (stream, "5261", &column, &first); | |
10564 | show (stream, "5721", &column, &first); | |
252b5132 RH |
10565 | show (stream, "6000", &column, &first); |
10566 | show (stream, "8000", &column, &first); | |
10567 | show (stream, "10000", &column, &first); | |
d1cf510e | 10568 | show (stream, "12000", &column, &first); |
2e4acd24 | 10569 | show (stream, "sb1", &column, &first); |
252b5132 RH |
10570 | fputc ('\n', stream); |
10571 | ||
10572 | fprintf (stream, _("\ | |
ec68c924 | 10573 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
10574 | -no-mCPU don't generate code specific to CPU.\n\ |
10575 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
10576 | ||
10577 | first = 1; | |
10578 | ||
10579 | show (stream, "3900", &column, &first); | |
10580 | show (stream, "4010", &column, &first); | |
10581 | show (stream, "4100", &column, &first); | |
10582 | show (stream, "4650", &column, &first); | |
10583 | fputc ('\n', stream); | |
10584 | ||
beae10d5 | 10585 | fprintf (stream, _("\ |
252b5132 RH |
10586 | -mips16 generate mips16 instructions\n\ |
10587 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 10588 | fprintf (stream, _("\ |
ca4e0257 RS |
10589 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
10590 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
10591 | -O0 remove unneeded NOPs, do not swap branches\n\ |
10592 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 10593 | -n warn about NOPs generated from macros\n\ |
119d663a | 10594 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
10595 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
10596 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
10597 | #ifdef OBJ_ELF | |
beae10d5 | 10598 | fprintf (stream, _("\ |
252b5132 RH |
10599 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
10600 | -non_shared do not generate position independent code\n\ | |
10601 | -xgot assume a 32 bit GOT\n\ | |
34ba82a8 TS |
10602 | -mabi=ABI create ABI conformant object file for:\n")); |
10603 | ||
10604 | first = 1; | |
10605 | ||
10606 | show (stream, "32", &column, &first); | |
10607 | show (stream, "o64", &column, &first); | |
10608 | show (stream, "n32", &column, &first); | |
10609 | show (stream, "64", &column, &first); | |
10610 | show (stream, "eabi", &column, &first); | |
80cc45a5 | 10611 | |
34ba82a8 TS |
10612 | fputc ('\n', stream); |
10613 | ||
10614 | fprintf (stream, _("\ | |
e013f690 TS |
10615 | -32 create o32 ABI object file (default)\n\ |
10616 | -n32 create n32 ABI object file\n\ | |
10617 | -64 create 64 ABI object file\n")); | |
252b5132 RH |
10618 | #endif |
10619 | } | |
10620 | \f | |
10621 | void | |
10622 | mips_init_after_args () | |
10623 | { | |
10624 | /* initialize opcodes */ | |
10625 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10626 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10627 | } |
10628 | ||
10629 | long | |
10630 | md_pcrel_from (fixP) | |
10631 | fixS *fixP; | |
10632 | { | |
10633 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10634 | && fixP->fx_addsy != (symbolS *) NULL | |
10635 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10636 | { | |
6478892d TS |
10637 | /* This makes a branch to an undefined symbol be a branch to the |
10638 | current location. */ | |
cb56d3d3 | 10639 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 10640 | return 4; |
cb56d3d3 | 10641 | else |
6478892d | 10642 | return 1; |
252b5132 RH |
10643 | } |
10644 | ||
c9914766 | 10645 | /* Return the address of the delay slot. */ |
252b5132 RH |
10646 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
10647 | } | |
10648 | ||
252b5132 RH |
10649 | /* This is called before the symbol table is processed. In order to |
10650 | work with gcc when using mips-tfile, we must keep all local labels. | |
10651 | However, in other cases, we want to discard them. If we were | |
10652 | called with -g, but we didn't see any debugging information, it may | |
10653 | mean that gcc is smuggling debugging information through to | |
10654 | mips-tfile, in which case we must generate all local labels. */ | |
10655 | ||
10656 | void | |
10657 | mips_frob_file_before_adjust () | |
10658 | { | |
10659 | #ifndef NO_ECOFF_DEBUGGING | |
10660 | if (ECOFF_DEBUGGING | |
10661 | && mips_debug != 0 | |
10662 | && ! ecoff_debugging_seen) | |
10663 | flag_keep_locals = 1; | |
10664 | #endif | |
10665 | } | |
10666 | ||
10667 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10668 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10669 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10670 | explicit use of the %hi modifier. */ | |
10671 | ||
10672 | void | |
10673 | mips_frob_file () | |
10674 | { | |
10675 | struct mips_hi_fixup *l; | |
10676 | ||
10677 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10678 | { | |
10679 | segment_info_type *seginfo; | |
10680 | int pass; | |
10681 | ||
10682 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10683 | ||
10684 | /* Check quickly whether the next fixup happens to be a matching | |
10685 | %lo. */ | |
10686 | if (l->fixp->fx_next != NULL | |
10687 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10688 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10689 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10690 | continue; | |
10691 | ||
10692 | /* Look through the fixups for this segment for a matching %lo. | |
10693 | When we find one, move the %hi just in front of it. We do | |
10694 | this in two passes. In the first pass, we try to find a | |
10695 | unique %lo. In the second pass, we permit multiple %hi | |
10696 | relocs for a single %lo (this is a GNU extension). */ | |
10697 | seginfo = seg_info (l->seg); | |
10698 | for (pass = 0; pass < 2; pass++) | |
10699 | { | |
10700 | fixS *f, *prev; | |
10701 | ||
10702 | prev = NULL; | |
10703 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10704 | { | |
10705 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10706 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10707 | && f->fx_addsy == l->fixp->fx_addsy | |
10708 | && f->fx_offset == l->fixp->fx_offset | |
10709 | && (pass == 1 | |
10710 | || prev == NULL | |
10711 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10712 | || prev->fx_addsy != f->fx_addsy | |
10713 | || prev->fx_offset != f->fx_offset)) | |
10714 | { | |
10715 | fixS **pf; | |
10716 | ||
10717 | /* Move l->fixp before f. */ | |
10718 | for (pf = &seginfo->fix_root; | |
10719 | *pf != l->fixp; | |
10720 | pf = &(*pf)->fx_next) | |
10721 | assert (*pf != NULL); | |
10722 | ||
10723 | *pf = l->fixp->fx_next; | |
10724 | ||
10725 | l->fixp->fx_next = f; | |
10726 | if (prev == NULL) | |
10727 | seginfo->fix_root = l->fixp; | |
10728 | else | |
10729 | prev->fx_next = l->fixp; | |
10730 | ||
10731 | break; | |
10732 | } | |
10733 | ||
10734 | prev = f; | |
10735 | } | |
10736 | ||
10737 | if (f != NULL) | |
10738 | break; | |
10739 | ||
10740 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10741 | can leave a %hi without a %lo. */ | |
10742 | if (pass == 1) | |
10743 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10744 | _("Unmatched %%hi reloc")); | |
10745 | #endif | |
10746 | } | |
10747 | } | |
10748 | } | |
10749 | ||
10750 | /* When generating embedded PIC code we need to use a special | |
10751 | relocation to represent the difference of two symbols in the .text | |
10752 | section (switch tables use a difference of this sort). See | |
10753 | include/coff/mips.h for details. This macro checks whether this | |
10754 | fixup requires the special reloc. */ | |
10755 | #define SWITCH_TABLE(fixp) \ | |
10756 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10757 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10758 | && (fixp)->fx_addsy != NULL \ |
10759 | && (fixp)->fx_subsy != NULL \ | |
10760 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10761 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10762 | ||
10763 | /* When generating embedded PIC code we must keep all PC relative | |
10764 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10765 | to keep relocations for switch table entries. |
10766 | ||
10767 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10768 | We have to prevent gas from dropping them. */ | |
252b5132 | 10769 | |
252b5132 RH |
10770 | int |
10771 | mips_force_relocation (fixp) | |
10772 | fixS *fixp; | |
10773 | { | |
10774 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10775 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10776 | return 1; | |
10777 | ||
f6688943 TS |
10778 | if (HAVE_NEWABI |
10779 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10780 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10781 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10782 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10783 | return 1; | |
10784 | ||
252b5132 RH |
10785 | return (mips_pic == EMBEDDED_PIC |
10786 | && (fixp->fx_pcrel | |
10787 | || SWITCH_TABLE (fixp) | |
10788 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10789 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10790 | } | |
10791 | ||
add55e1f RS |
10792 | #ifdef OBJ_ELF |
10793 | static int | |
10794 | mips_need_elf_addend_fixup (fixP) | |
10795 | fixS *fixP; | |
10796 | { | |
2d2bf3e0 CD |
10797 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
10798 | return 1; | |
b25a253c CD |
10799 | if (mips_pic == EMBEDDED_PIC |
10800 | && S_IS_WEAK (fixP->fx_addsy)) | |
10801 | return 1; | |
10802 | if (mips_pic != EMBEDDED_PIC | |
10803 | && (S_IS_WEAK (fixP->fx_addsy) | |
10804 | || S_IS_EXTERN (fixP->fx_addsy)) | |
2d2bf3e0 CD |
10805 | && !S_IS_COMMON (fixP->fx_addsy)) |
10806 | return 1; | |
10807 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
10808 | && (((bfd_get_section_flags (stdoutput, | |
10809 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10810 | & SEC_LINK_ONCE) != 0) | |
10811 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10812 | ".gnu.linkonce", | |
10813 | sizeof (".gnu.linkonce") - 1))) | |
10814 | return 1; | |
10815 | return 0; | |
add55e1f RS |
10816 | } |
10817 | #endif | |
10818 | ||
252b5132 RH |
10819 | /* Apply a fixup to the object file. */ |
10820 | ||
94f592af NC |
10821 | void |
10822 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 10823 | fixS *fixP; |
98d3f06f | 10824 | valueT *valP; |
94f592af | 10825 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 10826 | { |
874e8986 | 10827 | bfd_byte *buf; |
98aa84af AM |
10828 | long insn; |
10829 | valueT value; | |
252b5132 RH |
10830 | |
10831 | assert (fixP->fx_size == 4 | |
10832 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10833 | || fixP->fx_r_type == BFD_RELOC_32 |
10834 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10835 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10836 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10837 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 10838 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 10839 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 10840 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10841 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10842 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10843 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10844 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10845 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10846 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10847 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 | 10848 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
438c16b8 TS |
10849 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
10850 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); | |
252b5132 | 10851 | |
98d3f06f | 10852 | value = *valP; |
252b5132 RH |
10853 | |
10854 | /* If we aren't adjusting this fixup to be against the section | |
10855 | symbol, we need to adjust the value. */ | |
10856 | #ifdef OBJ_ELF | |
10857 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10858 | { |
add55e1f | 10859 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af AM |
10860 | { |
10861 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
94f592af | 10862 | |
98aa84af | 10863 | value -= symval; |
add55e1f | 10864 | if (value != 0 && ! fixP->fx_pcrel) |
98aa84af AM |
10865 | { |
10866 | /* In this case, the bfd_install_relocation routine will | |
10867 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10868 | the addend to appear in the object file. */ |
98aa84af | 10869 | value -= symval; |
7461da6e RS |
10870 | |
10871 | /* Make sure the addend is still non-zero. If it became zero | |
10872 | after the last operation, set it to a spurious value and | |
10873 | subtract the same value from the object file's contents. */ | |
10874 | if (value == 0) | |
10875 | { | |
10876 | value = 8; | |
10877 | ||
10878 | /* The in-place addends for LO16 relocations are signed; | |
10879 | leave the matching HI16 in-place addends as zero. */ | |
10880 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10881 | { | |
10882 | reloc_howto_type *howto; | |
10883 | bfd_vma contents, mask, field; | |
10884 | ||
10885 | howto = bfd_reloc_type_lookup (stdoutput, | |
10886 | fixP->fx_r_type); | |
10887 | ||
10888 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
10889 | + fixP->fx_where, | |
10890 | fixP->fx_size * 8, | |
10891 | target_big_endian); | |
10892 | ||
10893 | /* MASK has bits set where the relocation should go. | |
10894 | FIELD is -value, shifted into the appropriate place | |
10895 | for this relocation. */ | |
10896 | mask = 1 << (howto->bitsize - 1); | |
10897 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10898 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10899 | ||
10900 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10901 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10902 | fixP->fx_size * 8, | |
10903 | target_big_endian); | |
10904 | } | |
10905 | } | |
98aa84af AM |
10906 | } |
10907 | } | |
252b5132 | 10908 | |
bb2d6cd7 GK |
10909 | /* This code was generated using trial and error and so is |
10910 | fragile and not trustworthy. If you change it, you should | |
10911 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10912 | they still pass. */ | |
10913 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10914 | { | |
10915 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10916 | ||
10917 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10918 | This gives the right results, but it can't possibly | |
10919 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10920 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10921 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10922 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10923 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10924 | } | |
10925 | } | |
10926 | #endif | |
252b5132 | 10927 | |
94f592af | 10928 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 RH |
10929 | |
10930 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
10931 | fixP->fx_done = 1; | |
10932 | ||
10933 | switch (fixP->fx_r_type) | |
10934 | { | |
10935 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10936 | case BFD_RELOC_MIPS_SHIFT5: |
10937 | case BFD_RELOC_MIPS_SHIFT6: | |
10938 | case BFD_RELOC_MIPS_GOT_DISP: | |
10939 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10940 | case BFD_RELOC_MIPS_GOT_OFST: | |
10941 | case BFD_RELOC_MIPS_SUB: | |
10942 | case BFD_RELOC_MIPS_INSERT_A: | |
10943 | case BFD_RELOC_MIPS_INSERT_B: | |
10944 | case BFD_RELOC_MIPS_DELETE: | |
10945 | case BFD_RELOC_MIPS_HIGHEST: | |
10946 | case BFD_RELOC_MIPS_HIGHER: | |
10947 | case BFD_RELOC_MIPS_SCN_DISP: | |
10948 | case BFD_RELOC_MIPS_REL16: | |
10949 | case BFD_RELOC_MIPS_RELGOT: | |
10950 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10951 | case BFD_RELOC_HI16: |
10952 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10953 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10954 | case BFD_RELOC_MIPS_LITERAL: |
10955 | case BFD_RELOC_MIPS_CALL16: | |
10956 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10957 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10958 | case BFD_RELOC_MIPS_GOT_HI16: |
10959 | case BFD_RELOC_MIPS_GOT_LO16: | |
10960 | case BFD_RELOC_MIPS_CALL_HI16: | |
10961 | case BFD_RELOC_MIPS_CALL_LO16: | |
10962 | case BFD_RELOC_MIPS16_GPREL: | |
10963 | if (fixP->fx_pcrel) | |
10964 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10965 | _("Invalid PC relative reloc")); | |
10966 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10967 | break; | |
10968 | ||
10969 | case BFD_RELOC_MIPS16_JMP: | |
10970 | /* We currently always generate a reloc against a symbol, which | |
10971 | means that we don't want an addend even if the symbol is | |
10972 | defined. */ | |
10973 | fixP->fx_addnumber = 0; | |
10974 | break; | |
10975 | ||
10976 | case BFD_RELOC_PCREL_HI16_S: | |
10977 | /* The addend for this is tricky if it is internal, so we just | |
10978 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10979 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10980 | && !fixP->fx_done |
10981 | && value != 0) | |
10982 | break; | |
10983 | if (fixP->fx_addsy | |
10984 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10985 | { |
10986 | /* For an external symbol adjust by the address to make it | |
10987 | pcrel_offset. We use the address of the RELLO reloc | |
10988 | which follows this one. */ | |
10989 | value += (fixP->fx_next->fx_frag->fr_address | |
10990 | + fixP->fx_next->fx_where); | |
10991 | } | |
e7d556df | 10992 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 10993 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10994 | if (target_big_endian) |
10995 | buf += 2; | |
874e8986 | 10996 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10997 | break; |
10998 | ||
10999 | case BFD_RELOC_PCREL_LO16: | |
11000 | /* The addend for this is tricky if it is internal, so we just | |
11001 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 11002 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
11003 | && !fixP->fx_done |
11004 | && value != 0) | |
11005 | break; | |
11006 | if (fixP->fx_addsy | |
11007 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 11008 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 11009 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11010 | if (target_big_endian) |
11011 | buf += 2; | |
874e8986 | 11012 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11013 | break; |
11014 | ||
11015 | case BFD_RELOC_64: | |
11016 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11017 | extended value if we are only 32 bits. */ | |
11018 | if (fixP->fx_done | |
11019 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11020 | { | |
11021 | if (8 <= sizeof (valueT)) | |
11022 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11023 | value, 8); | |
11024 | else | |
11025 | { | |
11026 | long w1, w2; | |
11027 | long hiv; | |
11028 | ||
11029 | w1 = w2 = fixP->fx_where; | |
11030 | if (target_big_endian) | |
11031 | w1 += 4; | |
11032 | else | |
11033 | w2 += 4; | |
11034 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
11035 | if ((value & 0x80000000) != 0) | |
11036 | hiv = 0xffffffff; | |
11037 | else | |
11038 | hiv = 0; | |
11039 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
11040 | } | |
11041 | } | |
11042 | break; | |
11043 | ||
056350c6 | 11044 | case BFD_RELOC_RVA: |
252b5132 RH |
11045 | case BFD_RELOC_32: |
11046 | /* If we are deleting this reloc entry, we must fill in the | |
11047 | value now. This can happen if we have a .word which is not | |
11048 | resolved when it appears but is later defined. We also need | |
11049 | to fill in the value if this is an embedded PIC switch table | |
11050 | entry. */ | |
11051 | if (fixP->fx_done | |
11052 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11053 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11054 | value, 4); | |
11055 | break; | |
11056 | ||
11057 | case BFD_RELOC_16: | |
11058 | /* If we are deleting this reloc entry, we must fill in the | |
11059 | value now. */ | |
11060 | assert (fixP->fx_size == 2); | |
11061 | if (fixP->fx_done) | |
11062 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11063 | value, 2); | |
11064 | break; | |
11065 | ||
11066 | case BFD_RELOC_LO16: | |
11067 | /* When handling an embedded PIC switch statement, we can wind | |
11068 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11069 | if (fixP->fx_done) | |
11070 | { | |
98aa84af | 11071 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
11072 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11073 | _("relocation overflow")); | |
874e8986 | 11074 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11075 | if (target_big_endian) |
11076 | buf += 2; | |
874e8986 | 11077 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11078 | } |
11079 | break; | |
11080 | ||
11081 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
11082 | if ((value & 0x3) != 0) |
11083 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11084 | _("Branch to odd address (%lx)"), (long) value); | |
11085 | ||
11086 | /* Fall through. */ | |
11087 | ||
11088 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
11089 | /* |
11090 | * We need to save the bits in the instruction since fixup_segment() | |
11091 | * might be deleting the relocation entry (i.e., a branch within | |
11092 | * the current segment). | |
11093 | */ | |
bb2d6cd7 GK |
11094 | if (!fixP->fx_done && value != 0) |
11095 | break; | |
11096 | /* If 'value' is zero, the remaining reloc code won't actually | |
11097 | do the store, so it must be done here. This is probably | |
11098 | a bug somewhere. */ | |
b25a253c CD |
11099 | if (!fixP->fx_done |
11100 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
11101 | || fixP->fx_addsy == NULL /* ??? */ | |
11102 | || ! S_IS_DEFINED (fixP->fx_addsy))) | |
bb2d6cd7 | 11103 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 11104 | |
98aa84af | 11105 | value = (offsetT) value >> 2; |
252b5132 RH |
11106 | |
11107 | /* update old instruction data */ | |
874e8986 | 11108 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
11109 | if (target_big_endian) |
11110 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11111 | else | |
11112 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11113 | ||
98aa84af | 11114 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
11115 | insn |= value & 0xffff; |
11116 | else | |
11117 | { | |
11118 | /* The branch offset is too large. If this is an | |
11119 | unconditional branch, and we are not generating PIC code, | |
11120 | we can convert it to an absolute jump instruction. */ | |
11121 | if (mips_pic == NO_PIC | |
11122 | && fixP->fx_done | |
11123 | && fixP->fx_frag->fr_address >= text_section->vma | |
11124 | && (fixP->fx_frag->fr_address | |
11125 | < text_section->vma + text_section->_raw_size) | |
11126 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11127 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11128 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
11129 | { | |
11130 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
11131 | insn = 0x0c000000; /* jal */ | |
11132 | else | |
11133 | insn = 0x08000000; /* j */ | |
11134 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11135 | fixP->fx_done = 0; | |
11136 | fixP->fx_addsy = section_symbol (text_section); | |
11137 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
11138 | } | |
11139 | else | |
11140 | { | |
11141 | /* FIXME. It would be possible in principle to handle | |
11142 | conditional branches which overflow. They could be | |
11143 | transformed into a branch around a jump. This would | |
11144 | require setting up variant frags for each different | |
11145 | branch type. The native MIPS assembler attempts to | |
11146 | handle these cases, but it appears to do it | |
11147 | incorrectly. */ | |
11148 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11149 | _("Branch out of range")); | |
11150 | } | |
11151 | } | |
11152 | ||
11153 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11154 | break; | |
11155 | ||
11156 | case BFD_RELOC_VTABLE_INHERIT: | |
11157 | fixP->fx_done = 0; | |
11158 | if (fixP->fx_addsy | |
11159 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11160 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11161 | S_SET_WEAK (fixP->fx_addsy); | |
11162 | break; | |
11163 | ||
11164 | case BFD_RELOC_VTABLE_ENTRY: | |
11165 | fixP->fx_done = 0; | |
11166 | break; | |
11167 | ||
11168 | default: | |
11169 | internalError (); | |
11170 | } | |
252b5132 RH |
11171 | } |
11172 | ||
11173 | #if 0 | |
11174 | void | |
11175 | printInsn (oc) | |
11176 | unsigned long oc; | |
11177 | { | |
11178 | const struct mips_opcode *p; | |
11179 | int treg, sreg, dreg, shamt; | |
11180 | short imm; | |
11181 | const char *args; | |
11182 | int i; | |
11183 | ||
11184 | for (i = 0; i < NUMOPCODES; ++i) | |
11185 | { | |
11186 | p = &mips_opcodes[i]; | |
11187 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11188 | { | |
11189 | printf ("%08lx %s\t", oc, p->name); | |
11190 | treg = (oc >> 16) & 0x1f; | |
11191 | sreg = (oc >> 21) & 0x1f; | |
11192 | dreg = (oc >> 11) & 0x1f; | |
11193 | shamt = (oc >> 6) & 0x1f; | |
11194 | imm = oc; | |
11195 | for (args = p->args;; ++args) | |
11196 | { | |
11197 | switch (*args) | |
11198 | { | |
11199 | case '\0': | |
11200 | printf ("\n"); | |
11201 | break; | |
11202 | ||
11203 | case ',': | |
11204 | case '(': | |
11205 | case ')': | |
11206 | printf ("%c", *args); | |
11207 | continue; | |
11208 | ||
11209 | case 'r': | |
11210 | assert (treg == sreg); | |
11211 | printf ("$%d,$%d", treg, sreg); | |
11212 | continue; | |
11213 | ||
11214 | case 'd': | |
11215 | case 'G': | |
11216 | printf ("$%d", dreg); | |
11217 | continue; | |
11218 | ||
11219 | case 't': | |
11220 | case 'E': | |
11221 | printf ("$%d", treg); | |
11222 | continue; | |
11223 | ||
11224 | case 'k': | |
11225 | printf ("0x%x", treg); | |
11226 | continue; | |
11227 | ||
11228 | case 'b': | |
11229 | case 's': | |
11230 | printf ("$%d", sreg); | |
11231 | continue; | |
11232 | ||
11233 | case 'a': | |
11234 | printf ("0x%08lx", oc & 0x1ffffff); | |
11235 | continue; | |
11236 | ||
11237 | case 'i': | |
11238 | case 'j': | |
11239 | case 'o': | |
11240 | case 'u': | |
11241 | printf ("%d", imm); | |
11242 | continue; | |
11243 | ||
11244 | case '<': | |
11245 | case '>': | |
11246 | printf ("$%d", shamt); | |
11247 | continue; | |
11248 | ||
11249 | default: | |
11250 | internalError (); | |
11251 | } | |
11252 | break; | |
11253 | } | |
11254 | return; | |
11255 | } | |
11256 | } | |
11257 | printf (_("%08lx UNDEFINED\n"), oc); | |
11258 | } | |
11259 | #endif | |
11260 | ||
11261 | static symbolS * | |
11262 | get_symbol () | |
11263 | { | |
11264 | int c; | |
11265 | char *name; | |
11266 | symbolS *p; | |
11267 | ||
11268 | name = input_line_pointer; | |
11269 | c = get_symbol_end (); | |
11270 | p = (symbolS *) symbol_find_or_make (name); | |
11271 | *input_line_pointer = c; | |
11272 | return p; | |
11273 | } | |
11274 | ||
11275 | /* Align the current frag to a given power of two. The MIPS assembler | |
11276 | also automatically adjusts any preceding label. */ | |
11277 | ||
11278 | static void | |
11279 | mips_align (to, fill, label) | |
11280 | int to; | |
11281 | int fill; | |
11282 | symbolS *label; | |
11283 | { | |
11284 | mips_emit_delays (false); | |
11285 | frag_align (to, fill, 0); | |
11286 | record_alignment (now_seg, to); | |
11287 | if (label != NULL) | |
11288 | { | |
11289 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11290 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11291 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11292 | } | |
11293 | } | |
11294 | ||
11295 | /* Align to a given power of two. .align 0 turns off the automatic | |
11296 | alignment used by the data creating pseudo-ops. */ | |
11297 | ||
11298 | static void | |
11299 | s_align (x) | |
43841e91 | 11300 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11301 | { |
11302 | register int temp; | |
11303 | register long temp_fill; | |
11304 | long max_alignment = 15; | |
11305 | ||
11306 | /* | |
11307 | ||
11308 | o Note that the assembler pulls down any immediately preceeding label | |
11309 | to the aligned address. | |
11310 | o It's not documented but auto alignment is reinstated by | |
11311 | a .align pseudo instruction. | |
11312 | o Note also that after auto alignment is turned off the mips assembler | |
11313 | issues an error on attempt to assemble an improperly aligned data item. | |
11314 | We don't. | |
11315 | ||
11316 | */ | |
11317 | ||
11318 | temp = get_absolute_expression (); | |
11319 | if (temp > max_alignment) | |
11320 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11321 | else if (temp < 0) | |
11322 | { | |
11323 | as_warn (_("Alignment negative: 0 assumed.")); | |
11324 | temp = 0; | |
11325 | } | |
11326 | if (*input_line_pointer == ',') | |
11327 | { | |
f9419b05 | 11328 | ++input_line_pointer; |
252b5132 RH |
11329 | temp_fill = get_absolute_expression (); |
11330 | } | |
11331 | else | |
11332 | temp_fill = 0; | |
11333 | if (temp) | |
11334 | { | |
11335 | auto_align = 1; | |
11336 | mips_align (temp, (int) temp_fill, | |
11337 | insn_labels != NULL ? insn_labels->label : NULL); | |
11338 | } | |
11339 | else | |
11340 | { | |
11341 | auto_align = 0; | |
11342 | } | |
11343 | ||
11344 | demand_empty_rest_of_line (); | |
11345 | } | |
11346 | ||
11347 | void | |
11348 | mips_flush_pending_output () | |
11349 | { | |
11350 | mips_emit_delays (false); | |
11351 | mips_clear_insn_labels (); | |
11352 | } | |
11353 | ||
11354 | static void | |
11355 | s_change_sec (sec) | |
11356 | int sec; | |
11357 | { | |
11358 | segT seg; | |
11359 | ||
11360 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11361 | .sdata and .sbss sections. We change the .data and .rdata | |
11362 | pseudo-ops to use .sdata. */ | |
11363 | if (mips_pic == EMBEDDED_PIC | |
11364 | && (sec == 'd' || sec == 'r')) | |
11365 | sec = 's'; | |
11366 | ||
11367 | #ifdef OBJ_ELF | |
11368 | /* The ELF backend needs to know that we are changing sections, so | |
11369 | that .previous works correctly. We could do something like check | |
b6ff326e | 11370 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11371 | as it would not be appropriate to use it in the section changing |
11372 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11373 | This should be cleaner, somehow. */ | |
11374 | obj_elf_section_change_hook (); | |
11375 | #endif | |
11376 | ||
11377 | mips_emit_delays (false); | |
11378 | switch (sec) | |
11379 | { | |
11380 | case 't': | |
11381 | s_text (0); | |
11382 | break; | |
11383 | case 'd': | |
11384 | s_data (0); | |
11385 | break; | |
11386 | case 'b': | |
11387 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11388 | demand_empty_rest_of_line (); | |
11389 | break; | |
11390 | ||
11391 | case 'r': | |
11392 | if (USE_GLOBAL_POINTER_OPT) | |
11393 | { | |
11394 | seg = subseg_new (RDATA_SECTION_NAME, | |
11395 | (subsegT) get_absolute_expression ()); | |
11396 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11397 | { | |
11398 | bfd_set_section_flags (stdoutput, seg, | |
11399 | (SEC_ALLOC | |
11400 | | SEC_LOAD | |
11401 | | SEC_READONLY | |
11402 | | SEC_RELOC | |
11403 | | SEC_DATA)); | |
11404 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11405 | record_alignment (seg, 4); |
252b5132 RH |
11406 | } |
11407 | demand_empty_rest_of_line (); | |
11408 | } | |
11409 | else | |
11410 | { | |
11411 | as_bad (_("No read only data section in this object file format")); | |
11412 | demand_empty_rest_of_line (); | |
11413 | return; | |
11414 | } | |
11415 | break; | |
11416 | ||
11417 | case 's': | |
11418 | if (USE_GLOBAL_POINTER_OPT) | |
11419 | { | |
11420 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11421 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11422 | { | |
11423 | bfd_set_section_flags (stdoutput, seg, | |
11424 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11425 | | SEC_DATA); | |
11426 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11427 | record_alignment (seg, 4); |
252b5132 RH |
11428 | } |
11429 | demand_empty_rest_of_line (); | |
11430 | break; | |
11431 | } | |
11432 | else | |
11433 | { | |
11434 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11435 | demand_empty_rest_of_line (); | |
11436 | return; | |
11437 | } | |
11438 | } | |
11439 | ||
11440 | auto_align = 1; | |
11441 | } | |
11442 | ||
11443 | void | |
11444 | mips_enable_auto_align () | |
11445 | { | |
11446 | auto_align = 1; | |
11447 | } | |
11448 | ||
11449 | static void | |
11450 | s_cons (log_size) | |
11451 | int log_size; | |
11452 | { | |
11453 | symbolS *label; | |
11454 | ||
11455 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11456 | mips_emit_delays (false); | |
11457 | if (log_size > 0 && auto_align) | |
11458 | mips_align (log_size, 0, label); | |
11459 | mips_clear_insn_labels (); | |
11460 | cons (1 << log_size); | |
11461 | } | |
11462 | ||
11463 | static void | |
11464 | s_float_cons (type) | |
11465 | int type; | |
11466 | { | |
11467 | symbolS *label; | |
11468 | ||
11469 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11470 | ||
11471 | mips_emit_delays (false); | |
11472 | ||
11473 | if (auto_align) | |
49309057 ILT |
11474 | { |
11475 | if (type == 'd') | |
11476 | mips_align (3, 0, label); | |
11477 | else | |
11478 | mips_align (2, 0, label); | |
11479 | } | |
252b5132 RH |
11480 | |
11481 | mips_clear_insn_labels (); | |
11482 | ||
11483 | float_cons (type); | |
11484 | } | |
11485 | ||
11486 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11487 | permitted to say | |
11488 | .globl foo .text | |
11489 | where foo is an undefined symbol, to mean that foo should be | |
11490 | considered to be the address of a function. */ | |
11491 | ||
11492 | static void | |
11493 | s_mips_globl (x) | |
43841e91 | 11494 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11495 | { |
11496 | char *name; | |
11497 | int c; | |
11498 | symbolS *symbolP; | |
11499 | flagword flag; | |
11500 | ||
11501 | name = input_line_pointer; | |
11502 | c = get_symbol_end (); | |
11503 | symbolP = symbol_find_or_make (name); | |
11504 | *input_line_pointer = c; | |
11505 | SKIP_WHITESPACE (); | |
11506 | ||
11507 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11508 | being a function is apparently labelled as being an object. */ | |
11509 | flag = BSF_OBJECT; | |
11510 | ||
11511 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11512 | { | |
11513 | char *secname; | |
11514 | asection *sec; | |
11515 | ||
11516 | secname = input_line_pointer; | |
11517 | c = get_symbol_end (); | |
11518 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11519 | if (sec == NULL) | |
11520 | as_bad (_("%s: no such section"), secname); | |
11521 | *input_line_pointer = c; | |
11522 | ||
11523 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11524 | flag = BSF_FUNCTION; | |
11525 | } | |
11526 | ||
49309057 | 11527 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11528 | |
11529 | S_SET_EXTERNAL (symbolP); | |
11530 | demand_empty_rest_of_line (); | |
11531 | } | |
11532 | ||
11533 | static void | |
11534 | s_option (x) | |
43841e91 | 11535 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11536 | { |
11537 | char *opt; | |
11538 | char c; | |
11539 | ||
11540 | opt = input_line_pointer; | |
11541 | c = get_symbol_end (); | |
11542 | ||
11543 | if (*opt == 'O') | |
11544 | { | |
11545 | /* FIXME: What does this mean? */ | |
11546 | } | |
11547 | else if (strncmp (opt, "pic", 3) == 0) | |
11548 | { | |
11549 | int i; | |
11550 | ||
11551 | i = atoi (opt + 3); | |
11552 | if (i == 0) | |
11553 | mips_pic = NO_PIC; | |
11554 | else if (i == 2) | |
11555 | mips_pic = SVR4_PIC; | |
11556 | else | |
11557 | as_bad (_(".option pic%d not supported"), i); | |
11558 | ||
11559 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11560 | { | |
11561 | if (g_switch_seen && g_switch_value != 0) | |
11562 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11563 | g_switch_value = 0; | |
11564 | bfd_set_gp_size (stdoutput, 0); | |
11565 | } | |
11566 | } | |
11567 | else | |
11568 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11569 | ||
11570 | *input_line_pointer = c; | |
11571 | demand_empty_rest_of_line (); | |
11572 | } | |
11573 | ||
11574 | /* This structure is used to hold a stack of .set values. */ | |
11575 | ||
e972090a NC |
11576 | struct mips_option_stack |
11577 | { | |
252b5132 RH |
11578 | struct mips_option_stack *next; |
11579 | struct mips_set_options options; | |
11580 | }; | |
11581 | ||
11582 | static struct mips_option_stack *mips_opts_stack; | |
11583 | ||
11584 | /* Handle the .set pseudo-op. */ | |
11585 | ||
11586 | static void | |
11587 | s_mipsset (x) | |
43841e91 | 11588 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11589 | { |
11590 | char *name = input_line_pointer, ch; | |
11591 | ||
11592 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11593 | ++input_line_pointer; |
252b5132 RH |
11594 | ch = *input_line_pointer; |
11595 | *input_line_pointer = '\0'; | |
11596 | ||
11597 | if (strcmp (name, "reorder") == 0) | |
11598 | { | |
11599 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11600 | { | |
11601 | /* If we still have pending nops, we can discard them. The | |
11602 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11603 | needed. */ |
252b5132 RH |
11604 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11605 | * (mips_opts.mips16 ? 2 : 4)); | |
11606 | prev_nop_frag = NULL; | |
11607 | } | |
11608 | mips_opts.noreorder = 0; | |
11609 | } | |
11610 | else if (strcmp (name, "noreorder") == 0) | |
11611 | { | |
11612 | mips_emit_delays (true); | |
11613 | mips_opts.noreorder = 1; | |
11614 | mips_any_noreorder = 1; | |
11615 | } | |
11616 | else if (strcmp (name, "at") == 0) | |
11617 | { | |
11618 | mips_opts.noat = 0; | |
11619 | } | |
11620 | else if (strcmp (name, "noat") == 0) | |
11621 | { | |
11622 | mips_opts.noat = 1; | |
11623 | } | |
11624 | else if (strcmp (name, "macro") == 0) | |
11625 | { | |
11626 | mips_opts.warn_about_macros = 0; | |
11627 | } | |
11628 | else if (strcmp (name, "nomacro") == 0) | |
11629 | { | |
11630 | if (mips_opts.noreorder == 0) | |
11631 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11632 | mips_opts.warn_about_macros = 1; | |
11633 | } | |
11634 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11635 | { | |
11636 | mips_opts.nomove = 0; | |
11637 | } | |
11638 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11639 | { | |
11640 | mips_opts.nomove = 1; | |
11641 | } | |
11642 | else if (strcmp (name, "bopt") == 0) | |
11643 | { | |
11644 | mips_opts.nobopt = 0; | |
11645 | } | |
11646 | else if (strcmp (name, "nobopt") == 0) | |
11647 | { | |
11648 | mips_opts.nobopt = 1; | |
11649 | } | |
deec1734 CD |
11650 | else if (strcmp (name, "mdmx") == 0) |
11651 | mips_opts.ase_mdmx = 1; | |
11652 | else if (strcmp (name, "nomdmx") == 0) | |
11653 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
11654 | else if (strcmp (name, "mips16") == 0 |
11655 | || strcmp (name, "MIPS-16") == 0) | |
11656 | mips_opts.mips16 = 1; | |
11657 | else if (strcmp (name, "nomips16") == 0 | |
11658 | || strcmp (name, "noMIPS-16") == 0) | |
11659 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11660 | else if (strcmp (name, "mips3d") == 0) |
11661 | mips_opts.ase_mips3d = 1; | |
11662 | else if (strcmp (name, "nomips3d") == 0) | |
11663 | mips_opts.ase_mips3d = 0; | |
252b5132 RH |
11664 | else if (strncmp (name, "mips", 4) == 0) |
11665 | { | |
11666 | int isa; | |
11667 | ||
11668 | /* Permit the user to change the ISA on the fly. Needless to | |
11669 | say, misuse can cause serious problems. */ | |
11670 | isa = atoi (name + 4); | |
553178e4 | 11671 | switch (isa) |
98d3f06f KH |
11672 | { |
11673 | case 0: | |
11674 | mips_opts.gp32 = file_mips_gp32; | |
11675 | mips_opts.fp32 = file_mips_fp32; | |
11676 | mips_opts.abi = file_mips_abi; | |
11677 | break; | |
11678 | case 1: | |
11679 | case 2: | |
11680 | case 32: | |
11681 | mips_opts.gp32 = 1; | |
11682 | mips_opts.fp32 = 1; | |
11683 | break; | |
11684 | case 3: | |
11685 | case 4: | |
11686 | case 5: | |
11687 | case 64: | |
11688 | /* Loosen ABI register width restriction. */ | |
11689 | if (mips_opts.abi == O32_ABI) | |
11690 | mips_opts.abi = NO_ABI; | |
11691 | mips_opts.gp32 = 0; | |
11692 | mips_opts.fp32 = 0; | |
11693 | break; | |
11694 | default: | |
11695 | as_bad (_("unknown ISA level %s"), name + 4); | |
11696 | break; | |
11697 | } | |
553178e4 | 11698 | |
e7af610e | 11699 | switch (isa) |
98d3f06f KH |
11700 | { |
11701 | case 0: mips_opts.isa = file_mips_isa; break; | |
11702 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11703 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11704 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
11705 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
11706 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
11707 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
11708 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
11709 | default: as_bad (_("unknown ISA level %s"), name + 4); break; | |
11710 | } | |
252b5132 RH |
11711 | } |
11712 | else if (strcmp (name, "autoextend") == 0) | |
11713 | mips_opts.noautoextend = 0; | |
11714 | else if (strcmp (name, "noautoextend") == 0) | |
11715 | mips_opts.noautoextend = 1; | |
11716 | else if (strcmp (name, "push") == 0) | |
11717 | { | |
11718 | struct mips_option_stack *s; | |
11719 | ||
11720 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11721 | s->next = mips_opts_stack; | |
11722 | s->options = mips_opts; | |
11723 | mips_opts_stack = s; | |
11724 | } | |
11725 | else if (strcmp (name, "pop") == 0) | |
11726 | { | |
11727 | struct mips_option_stack *s; | |
11728 | ||
11729 | s = mips_opts_stack; | |
11730 | if (s == NULL) | |
11731 | as_bad (_(".set pop with no .set push")); | |
11732 | else | |
11733 | { | |
11734 | /* If we're changing the reorder mode we need to handle | |
11735 | delay slots correctly. */ | |
11736 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11737 | mips_emit_delays (true); | |
11738 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11739 | { | |
11740 | if (prev_nop_frag != NULL) | |
11741 | { | |
11742 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11743 | * (mips_opts.mips16 ? 2 : 4)); | |
11744 | prev_nop_frag = NULL; | |
11745 | } | |
11746 | } | |
11747 | ||
11748 | mips_opts = s->options; | |
11749 | mips_opts_stack = s->next; | |
11750 | free (s); | |
11751 | } | |
11752 | } | |
11753 | else | |
11754 | { | |
11755 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11756 | } | |
11757 | *input_line_pointer = ch; | |
11758 | demand_empty_rest_of_line (); | |
11759 | } | |
11760 | ||
11761 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11762 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11763 | ||
11764 | static void | |
11765 | s_abicalls (ignore) | |
43841e91 | 11766 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11767 | { |
11768 | mips_pic = SVR4_PIC; | |
11769 | if (USE_GLOBAL_POINTER_OPT) | |
11770 | { | |
11771 | if (g_switch_seen && g_switch_value != 0) | |
11772 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11773 | g_switch_value = 0; | |
11774 | } | |
11775 | bfd_set_gp_size (stdoutput, 0); | |
11776 | demand_empty_rest_of_line (); | |
11777 | } | |
11778 | ||
11779 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11780 | PIC code. It sets the $gp register for the function based on the | |
11781 | function address, which is in the register named in the argument. | |
11782 | This uses a relocation against _gp_disp, which is handled specially | |
11783 | by the linker. The result is: | |
11784 | lui $gp,%hi(_gp_disp) | |
11785 | addiu $gp,$gp,%lo(_gp_disp) | |
11786 | addu $gp,$gp,.cpload argument | |
11787 | The .cpload argument is normally $25 == $t9. */ | |
11788 | ||
11789 | static void | |
11790 | s_cpload (ignore) | |
43841e91 | 11791 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11792 | { |
11793 | expressionS ex; | |
11794 | int icnt = 0; | |
11795 | ||
6478892d TS |
11796 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11797 | .cpload is ignored. */ | |
11798 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11799 | { |
11800 | s_ignore (0); | |
11801 | return; | |
11802 | } | |
11803 | ||
d3ecfc59 | 11804 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11805 | if (mips_opts.noreorder == 0) |
11806 | as_warn (_(".cpload not in noreorder section")); | |
11807 | ||
11808 | ex.X_op = O_symbol; | |
11809 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11810 | ex.X_op_symbol = NULL; | |
11811 | ex.X_add_number = 0; | |
11812 | ||
11813 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11814 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11815 | |
c9914766 TS |
11816 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
11817 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
11818 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
11819 | |
11820 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 11821 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
11822 | |
11823 | demand_empty_rest_of_line (); | |
11824 | } | |
11825 | ||
6478892d TS |
11826 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11827 | .cpsetup $reg1, offset|$reg2, label | |
11828 | ||
11829 | If offset is given, this results in: | |
11830 | sd $gp, offset($sp) | |
956cd1d6 TS |
11831 | lui $gp, %hi(%neg(%gp_rel(label))) |
11832 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11833 | addu $gp, $gp, $reg1 |
11834 | ||
11835 | If $reg2 is given, this results in: | |
11836 | daddu $reg2, $gp, $0 | |
956cd1d6 TS |
11837 | lui $gp, %hi(%neg(%gp_rel(label))) |
11838 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11839 | addu $gp, $gp, $reg1 |
11840 | */ | |
11841 | static void | |
11842 | s_cpsetup (ignore) | |
11843 | int ignore ATTRIBUTE_UNUSED; | |
11844 | { | |
11845 | expressionS ex_off; | |
11846 | expressionS ex_sym; | |
11847 | int reg1; | |
11848 | int icnt = 0; | |
11849 | char *sym; | |
11850 | ||
8586fc66 | 11851 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11852 | We also need NewABI support. */ |
11853 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11854 | { | |
11855 | s_ignore (0); | |
11856 | return; | |
11857 | } | |
11858 | ||
11859 | reg1 = tc_get_register (0); | |
11860 | SKIP_WHITESPACE (); | |
11861 | if (*input_line_pointer != ',') | |
11862 | { | |
11863 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11864 | return; | |
11865 | } | |
11866 | else | |
11867 | input_line_pointer++; | |
11868 | SKIP_WHITESPACE (); | |
11869 | if (*input_line_pointer == '$') | |
11870 | mips_cpreturn_register = tc_get_register (0); | |
11871 | else | |
11872 | mips_cpreturn_offset = get_absolute_expression (); | |
11873 | SKIP_WHITESPACE (); | |
11874 | if (*input_line_pointer != ',') | |
11875 | { | |
11876 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11877 | return; | |
11878 | } | |
11879 | else | |
f9419b05 | 11880 | ++input_line_pointer; |
6478892d TS |
11881 | SKIP_WHITESPACE (); |
11882 | sym = input_line_pointer; | |
11883 | while (ISALNUM (*input_line_pointer)) | |
f9419b05 | 11884 | ++input_line_pointer; |
6478892d TS |
11885 | *input_line_pointer = 0; |
11886 | ||
11887 | ex_sym.X_op = O_symbol; | |
11888 | ex_sym.X_add_symbol = symbol_find_or_make (sym); | |
11889 | ex_sym.X_op_symbol = NULL; | |
11890 | ex_sym.X_add_number = 0; | |
11891 | ||
11892 | if (mips_cpreturn_register == -1) | |
11893 | { | |
11894 | ex_off.X_op = O_constant; | |
11895 | ex_off.X_add_symbol = NULL; | |
11896 | ex_off.X_op_symbol = NULL; | |
11897 | ex_off.X_add_number = mips_cpreturn_offset; | |
11898 | ||
11899 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11900 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11901 | } | |
11902 | else | |
11903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11904 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11905 | ||
11906 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, | |
11907 | (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11908 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11909 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
6478892d TS |
11910 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
11911 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11912 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11913 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16); | |
11914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
11915 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
11916 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
11917 | |
11918 | demand_empty_rest_of_line (); | |
11919 | } | |
11920 | ||
11921 | static void | |
11922 | s_cplocal (ignore) | |
11923 | int ignore ATTRIBUTE_UNUSED; | |
11924 | { | |
11925 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11926 | .cplocal is ignored. */ | |
11927 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11928 | { | |
11929 | s_ignore (0); | |
11930 | return; | |
11931 | } | |
11932 | ||
11933 | mips_gp_register = tc_get_register (0); | |
11934 | } | |
11935 | ||
252b5132 RH |
11936 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11937 | offset from $sp. The offset is remembered, and after making a PIC | |
11938 | call $gp is restored from that location. */ | |
11939 | ||
11940 | static void | |
11941 | s_cprestore (ignore) | |
43841e91 | 11942 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11943 | { |
11944 | expressionS ex; | |
11945 | int icnt = 0; | |
11946 | ||
6478892d | 11947 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11948 | .cprestore is ignored. */ |
6478892d | 11949 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11950 | { |
11951 | s_ignore (0); | |
11952 | return; | |
11953 | } | |
11954 | ||
11955 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11956 | mips_cprestore_valid = 1; |
252b5132 RH |
11957 | |
11958 | ex.X_op = O_constant; | |
11959 | ex.X_add_symbol = NULL; | |
11960 | ex.X_op_symbol = NULL; | |
11961 | ex.X_add_number = mips_cprestore_offset; | |
11962 | ||
c9914766 TS |
11963 | macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
11964 | "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
252b5132 RH |
11965 | |
11966 | demand_empty_rest_of_line (); | |
11967 | } | |
11968 | ||
6478892d TS |
11969 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11970 | was given in the preceeding .gpsetup, it results in: | |
11971 | ld $gp, offset($sp) | |
76b3015f | 11972 | |
6478892d TS |
11973 | If a register $reg2 was given there, it results in: |
11974 | daddiu $gp, $gp, $reg2 | |
11975 | */ | |
11976 | static void | |
11977 | s_cpreturn (ignore) | |
11978 | int ignore ATTRIBUTE_UNUSED; | |
11979 | { | |
11980 | expressionS ex; | |
11981 | int icnt = 0; | |
11982 | ||
11983 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11984 | We also need NewABI support. */ | |
11985 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11986 | { | |
11987 | s_ignore (0); | |
11988 | return; | |
11989 | } | |
11990 | ||
11991 | if (mips_cpreturn_register == -1) | |
11992 | { | |
11993 | ex.X_op = O_constant; | |
11994 | ex.X_add_symbol = NULL; | |
11995 | ex.X_op_symbol = NULL; | |
11996 | ex.X_add_number = mips_cpreturn_offset; | |
11997 | ||
11998 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11999 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
12000 | } | |
12001 | else | |
12002 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12003 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
12004 | ||
12005 | demand_empty_rest_of_line (); | |
12006 | } | |
12007 | ||
12008 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12009 | code. It sets the offset to use in gp_rel relocations. */ | |
12010 | ||
12011 | static void | |
12012 | s_gpvalue (ignore) | |
12013 | int ignore ATTRIBUTE_UNUSED; | |
12014 | { | |
12015 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12016 | We also need NewABI support. */ | |
12017 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12018 | { | |
12019 | s_ignore (0); | |
12020 | return; | |
12021 | } | |
12022 | ||
def2e0dd | 12023 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12024 | |
12025 | demand_empty_rest_of_line (); | |
12026 | } | |
12027 | ||
252b5132 RH |
12028 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12029 | code. It generates a 32 bit GP relative reloc. */ | |
12030 | ||
12031 | static void | |
12032 | s_gpword (ignore) | |
43841e91 | 12033 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12034 | { |
12035 | symbolS *label; | |
12036 | expressionS ex; | |
12037 | char *p; | |
12038 | ||
12039 | /* When not generating PIC code, this is treated as .word. */ | |
12040 | if (mips_pic != SVR4_PIC) | |
12041 | { | |
12042 | s_cons (2); | |
12043 | return; | |
12044 | } | |
12045 | ||
12046 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
12047 | mips_emit_delays (true); | |
12048 | if (auto_align) | |
12049 | mips_align (2, 0, label); | |
12050 | mips_clear_insn_labels (); | |
12051 | ||
12052 | expression (&ex); | |
12053 | ||
12054 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12055 | { | |
12056 | as_bad (_("Unsupported use of .gpword")); | |
12057 | ignore_rest_of_line (); | |
12058 | } | |
12059 | ||
12060 | p = frag_more (4); | |
12061 | md_number_to_chars (p, (valueT) 0, 4); | |
c9914766 | 12062 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, |
cdf6fd85 | 12063 | BFD_RELOC_GPREL32); |
252b5132 RH |
12064 | |
12065 | demand_empty_rest_of_line (); | |
12066 | } | |
12067 | ||
12068 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
12069 | tables in SVR4 PIC code. */ | |
12070 | ||
12071 | static void | |
12072 | s_cpadd (ignore) | |
43841e91 | 12073 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12074 | { |
12075 | int icnt = 0; | |
12076 | int reg; | |
12077 | ||
6478892d TS |
12078 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
12079 | code. */ | |
12080 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12081 | { |
12082 | s_ignore (0); | |
12083 | return; | |
12084 | } | |
12085 | ||
12086 | /* Add $gp to the register named as an argument. */ | |
12087 | reg = tc_get_register (0); | |
12088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 12089 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 12090 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12091 | |
bdaaa2e1 | 12092 | demand_empty_rest_of_line (); |
252b5132 RH |
12093 | } |
12094 | ||
12095 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12096 | mips16 mode. This permits the linker to handle them specially, | |
12097 | such as generating jalx instructions when needed. We also make | |
12098 | them odd for the duration of the assembly, in order to generate the | |
12099 | right sort of code. We will make them even in the adjust_symtab | |
12100 | routine, while leaving them marked. This is convenient for the | |
12101 | debugger and the disassembler. The linker knows to make them odd | |
12102 | again. */ | |
12103 | ||
12104 | static void | |
12105 | s_insn (ignore) | |
43841e91 | 12106 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12107 | { |
f9419b05 | 12108 | mips16_mark_labels (); |
252b5132 RH |
12109 | |
12110 | demand_empty_rest_of_line (); | |
12111 | } | |
12112 | ||
12113 | /* Handle a .stabn directive. We need these in order to mark a label | |
12114 | as being a mips16 text label correctly. Sometimes the compiler | |
12115 | will emit a label, followed by a .stabn, and then switch sections. | |
12116 | If the label and .stabn are in mips16 mode, then the label is | |
12117 | really a mips16 text label. */ | |
12118 | ||
12119 | static void | |
12120 | s_mips_stab (type) | |
12121 | int type; | |
12122 | { | |
f9419b05 | 12123 | if (type == 'n') |
252b5132 RH |
12124 | mips16_mark_labels (); |
12125 | ||
12126 | s_stab (type); | |
12127 | } | |
12128 | ||
12129 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12130 | */ | |
12131 | ||
12132 | static void | |
12133 | s_mips_weakext (ignore) | |
43841e91 | 12134 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12135 | { |
12136 | char *name; | |
12137 | int c; | |
12138 | symbolS *symbolP; | |
12139 | expressionS exp; | |
12140 | ||
12141 | name = input_line_pointer; | |
12142 | c = get_symbol_end (); | |
12143 | symbolP = symbol_find_or_make (name); | |
12144 | S_SET_WEAK (symbolP); | |
12145 | *input_line_pointer = c; | |
12146 | ||
12147 | SKIP_WHITESPACE (); | |
12148 | ||
12149 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12150 | { | |
12151 | if (S_IS_DEFINED (symbolP)) | |
12152 | { | |
956cd1d6 | 12153 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12154 | S_GET_NAME (symbolP)); |
12155 | ignore_rest_of_line (); | |
12156 | return; | |
12157 | } | |
bdaaa2e1 | 12158 | |
252b5132 RH |
12159 | if (*input_line_pointer == ',') |
12160 | { | |
12161 | ++input_line_pointer; | |
12162 | SKIP_WHITESPACE (); | |
12163 | } | |
bdaaa2e1 | 12164 | |
252b5132 RH |
12165 | expression (&exp); |
12166 | if (exp.X_op != O_symbol) | |
12167 | { | |
12168 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12169 | ignore_rest_of_line (); |
252b5132 RH |
12170 | return; |
12171 | } | |
49309057 | 12172 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12173 | } |
12174 | ||
12175 | demand_empty_rest_of_line (); | |
12176 | } | |
12177 | ||
12178 | /* Parse a register string into a number. Called from the ECOFF code | |
12179 | to parse .frame. The argument is non-zero if this is the frame | |
12180 | register, so that we can record it in mips_frame_reg. */ | |
12181 | ||
12182 | int | |
12183 | tc_get_register (frame) | |
12184 | int frame; | |
12185 | { | |
12186 | int reg; | |
12187 | ||
12188 | SKIP_WHITESPACE (); | |
12189 | if (*input_line_pointer++ != '$') | |
12190 | { | |
12191 | as_warn (_("expected `$'")); | |
12192 | reg = 0; | |
12193 | } | |
3882b010 | 12194 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12195 | { |
12196 | reg = get_absolute_expression (); | |
12197 | if (reg < 0 || reg >= 32) | |
12198 | { | |
12199 | as_warn (_("Bad register number")); | |
12200 | reg = 0; | |
12201 | } | |
12202 | } | |
12203 | else | |
12204 | { | |
12205 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
12206 | reg = FP; | |
12207 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
12208 | reg = SP; | |
12209 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
12210 | reg = GP; | |
12211 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
12212 | reg = AT; | |
12213 | else | |
12214 | { | |
12215 | as_warn (_("Unrecognized register name")); | |
12216 | reg = 0; | |
12217 | } | |
12218 | input_line_pointer += 2; | |
12219 | } | |
12220 | if (frame) | |
7a621144 DJ |
12221 | { |
12222 | mips_frame_reg = reg != 0 ? reg : SP; | |
12223 | mips_frame_reg_valid = 1; | |
12224 | mips_cprestore_valid = 0; | |
12225 | } | |
252b5132 RH |
12226 | return reg; |
12227 | } | |
12228 | ||
12229 | valueT | |
12230 | md_section_align (seg, addr) | |
12231 | asection *seg; | |
12232 | valueT addr; | |
12233 | { | |
12234 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12235 | ||
12236 | #ifdef OBJ_ELF | |
12237 | /* We don't need to align ELF sections to the full alignment. | |
12238 | However, Irix 5 may prefer that we align them at least to a 16 | |
12239 | byte boundary. We don't bother to align the sections if we are | |
12240 | targeted for an embedded system. */ | |
12241 | if (strcmp (TARGET_OS, "elf") == 0) | |
12242 | return addr; | |
12243 | if (align > 4) | |
12244 | align = 4; | |
12245 | #endif | |
12246 | ||
12247 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12248 | } | |
12249 | ||
12250 | /* Utility routine, called from above as well. If called while the | |
12251 | input file is still being read, it's only an approximation. (For | |
12252 | example, a symbol may later become defined which appeared to be | |
12253 | undefined earlier.) */ | |
12254 | ||
12255 | static int | |
12256 | nopic_need_relax (sym, before_relaxing) | |
12257 | symbolS *sym; | |
12258 | int before_relaxing; | |
12259 | { | |
12260 | if (sym == 0) | |
12261 | return 0; | |
12262 | ||
6478892d | 12263 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12264 | { |
12265 | const char *symname; | |
12266 | int change; | |
12267 | ||
c9914766 | 12268 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12269 | register. It can be if it is smaller than the -G size or if |
12270 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12271 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12272 | they can. */ |
12273 | symname = S_GET_NAME (sym); | |
12274 | if (symname != (const char *) NULL | |
12275 | && (strcmp (symname, "eprol") == 0 | |
12276 | || strcmp (symname, "etext") == 0 | |
12277 | || strcmp (symname, "_gp") == 0 | |
12278 | || strcmp (symname, "edata") == 0 | |
12279 | || strcmp (symname, "_fbss") == 0 | |
12280 | || strcmp (symname, "_fdata") == 0 | |
12281 | || strcmp (symname, "_ftext") == 0 | |
12282 | || strcmp (symname, "end") == 0 | |
12283 | || strcmp (symname, "_gp_disp") == 0)) | |
12284 | change = 1; | |
12285 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12286 | && (0 | |
12287 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12288 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12289 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12290 | <= g_switch_value)) | |
252b5132 RH |
12291 | #endif |
12292 | /* We must defer this decision until after the whole | |
12293 | file has been read, since there might be a .extern | |
12294 | after the first use of this symbol. */ | |
12295 | || (before_relaxing | |
12296 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12297 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12298 | #endif |
12299 | && S_GET_VALUE (sym) == 0) | |
12300 | || (S_GET_VALUE (sym) != 0 | |
12301 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12302 | change = 0; | |
12303 | else | |
12304 | { | |
12305 | const char *segname; | |
12306 | ||
12307 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12308 | assert (strcmp (segname, ".lit8") != 0 | |
12309 | && strcmp (segname, ".lit4") != 0); | |
12310 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12311 | && strcmp (segname, ".sbss") != 0 |
12312 | && strncmp (segname, ".sdata.", 7) != 0 | |
12313 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12314 | } |
12315 | return change; | |
12316 | } | |
12317 | else | |
c9914766 | 12318 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12319 | return 1; |
12320 | } | |
12321 | ||
12322 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
12323 | extended opcode. SEC is the section the frag is in. */ | |
12324 | ||
12325 | static int | |
12326 | mips16_extended_frag (fragp, sec, stretch) | |
12327 | fragS *fragp; | |
12328 | asection *sec; | |
12329 | long stretch; | |
12330 | { | |
12331 | int type; | |
12332 | register const struct mips16_immed_operand *op; | |
12333 | offsetT val; | |
12334 | int mintiny, maxtiny; | |
12335 | segT symsec; | |
98aa84af | 12336 | fragS *sym_frag; |
252b5132 RH |
12337 | |
12338 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12339 | return 0; | |
12340 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12341 | return 1; | |
12342 | ||
12343 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12344 | op = mips16_immed_operands; | |
12345 | while (op->type != type) | |
12346 | { | |
12347 | ++op; | |
12348 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12349 | } | |
12350 | ||
12351 | if (op->unsp) | |
12352 | { | |
12353 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12354 | { | |
12355 | mintiny = 1; | |
12356 | maxtiny = 1 << op->nbits; | |
12357 | } | |
12358 | else | |
12359 | { | |
12360 | mintiny = 0; | |
12361 | maxtiny = (1 << op->nbits) - 1; | |
12362 | } | |
12363 | } | |
12364 | else | |
12365 | { | |
12366 | mintiny = - (1 << (op->nbits - 1)); | |
12367 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12368 | } | |
12369 | ||
98aa84af | 12370 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12371 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12372 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12373 | |
12374 | if (op->pcrel) | |
12375 | { | |
12376 | addressT addr; | |
12377 | ||
12378 | /* We won't have the section when we are called from | |
12379 | mips_relax_frag. However, we will always have been called | |
12380 | from md_estimate_size_before_relax first. If this is a | |
12381 | branch to a different section, we mark it as such. If SEC is | |
12382 | NULL, and the frag is not marked, then it must be a branch to | |
12383 | the same section. */ | |
12384 | if (sec == NULL) | |
12385 | { | |
12386 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12387 | return 1; | |
12388 | } | |
12389 | else | |
12390 | { | |
98aa84af | 12391 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12392 | if (symsec != sec) |
12393 | { | |
12394 | fragp->fr_subtype = | |
12395 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12396 | ||
12397 | /* FIXME: We should support this, and let the linker | |
12398 | catch branches and loads that are out of range. */ | |
12399 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12400 | _("unsupported PC relative reference to different section")); | |
12401 | ||
12402 | return 1; | |
12403 | } | |
98aa84af AM |
12404 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12405 | /* Assume non-extended on the first relaxation pass. | |
12406 | The address we have calculated will be bogus if this is | |
12407 | a forward branch to another frag, as the forward frag | |
12408 | will have fr_address == 0. */ | |
12409 | return 0; | |
252b5132 RH |
12410 | } |
12411 | ||
12412 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12413 | the same section. If the relax_marker of the symbol fragment |
12414 | differs from the relax_marker of this fragment, we have not | |
12415 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12416 | in STRETCH in order to get a better estimate of the address. |
12417 | This particularly matters because of the shift bits. */ | |
12418 | if (stretch != 0 | |
98aa84af | 12419 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12420 | { |
12421 | fragS *f; | |
12422 | ||
12423 | /* Adjust stretch for any alignment frag. Note that if have | |
12424 | been expanding the earlier code, the symbol may be | |
12425 | defined in what appears to be an earlier frag. FIXME: | |
12426 | This doesn't handle the fr_subtype field, which specifies | |
12427 | a maximum number of bytes to skip when doing an | |
12428 | alignment. */ | |
98aa84af | 12429 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12430 | { |
12431 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12432 | { | |
12433 | if (stretch < 0) | |
12434 | stretch = - ((- stretch) | |
12435 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12436 | else | |
12437 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12438 | if (stretch == 0) | |
12439 | break; | |
12440 | } | |
12441 | } | |
12442 | if (f != NULL) | |
12443 | val += stretch; | |
12444 | } | |
12445 | ||
12446 | addr = fragp->fr_address + fragp->fr_fix; | |
12447 | ||
12448 | /* The base address rules are complicated. The base address of | |
12449 | a branch is the following instruction. The base address of a | |
12450 | PC relative load or add is the instruction itself, but if it | |
12451 | is in a delay slot (in which case it can not be extended) use | |
12452 | the address of the instruction whose delay slot it is in. */ | |
12453 | if (type == 'p' || type == 'q') | |
12454 | { | |
12455 | addr += 2; | |
12456 | ||
12457 | /* If we are currently assuming that this frag should be | |
12458 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12459 | higher. */ |
252b5132 RH |
12460 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12461 | addr += 2; | |
12462 | ||
12463 | /* Ignore the low bit in the target, since it will be set | |
12464 | for a text label. */ | |
12465 | if ((val & 1) != 0) | |
12466 | --val; | |
12467 | } | |
12468 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12469 | addr -= 4; | |
12470 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12471 | addr -= 2; | |
12472 | ||
12473 | val -= addr & ~ ((1 << op->shift) - 1); | |
12474 | ||
12475 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12476 | if (type == 'p' || type == 'q') | |
12477 | val /= 2; | |
12478 | ||
12479 | /* If any of the shifted bits are set, we must use an extended | |
12480 | opcode. If the address depends on the size of this | |
12481 | instruction, this can lead to a loop, so we arrange to always | |
12482 | use an extended opcode. We only check this when we are in | |
12483 | the main relaxation loop, when SEC is NULL. */ | |
12484 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12485 | { | |
12486 | fragp->fr_subtype = | |
12487 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12488 | return 1; | |
12489 | } | |
12490 | ||
12491 | /* If we are about to mark a frag as extended because the value | |
12492 | is precisely maxtiny + 1, then there is a chance of an | |
12493 | infinite loop as in the following code: | |
12494 | la $4,foo | |
12495 | .skip 1020 | |
12496 | .align 2 | |
12497 | foo: | |
12498 | In this case when the la is extended, foo is 0x3fc bytes | |
12499 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12500 | the la must be extended. To avoid this loop, we mark the | |
12501 | frag as extended if it was small, and is about to become | |
12502 | extended with a value of maxtiny + 1. */ | |
12503 | if (val == ((maxtiny + 1) << op->shift) | |
12504 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12505 | && sec == NULL) | |
12506 | { | |
12507 | fragp->fr_subtype = | |
12508 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12509 | return 1; | |
12510 | } | |
12511 | } | |
12512 | else if (symsec != absolute_section && sec != NULL) | |
12513 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12514 | ||
12515 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12516 | || val < (mintiny << op->shift) | |
12517 | || val > (maxtiny << op->shift)) | |
12518 | return 1; | |
12519 | else | |
12520 | return 0; | |
12521 | } | |
12522 | ||
12523 | /* Estimate the size of a frag before relaxing. Unless this is the | |
12524 | mips16, we are not really relaxing here, and the final size is | |
12525 | encoded in the subtype information. For the mips16, we have to | |
12526 | decide whether we are using an extended opcode or not. */ | |
12527 | ||
252b5132 RH |
12528 | int |
12529 | md_estimate_size_before_relax (fragp, segtype) | |
12530 | fragS *fragp; | |
12531 | asection *segtype; | |
12532 | { | |
43841e91 | 12533 | int change = 0; |
8614eeee | 12534 | boolean linkonce = false; |
252b5132 RH |
12535 | |
12536 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
177b4a6a AO |
12537 | /* We don't want to modify the EXTENDED bit here; it might get us |
12538 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12539 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12540 | |
12541 | if (mips_pic == NO_PIC) | |
12542 | { | |
12543 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
12544 | } | |
12545 | else if (mips_pic == SVR4_PIC) | |
12546 | { | |
12547 | symbolS *sym; | |
12548 | asection *symsec; | |
12549 | ||
12550 | sym = fragp->fr_symbol; | |
12551 | ||
12552 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 12553 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
12554 | { |
12555 | symbolS *n; | |
12556 | ||
12557 | /* It's possible to get a loop here in a badly written | |
12558 | program. */ | |
49309057 | 12559 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
12560 | if (n == sym) |
12561 | break; | |
12562 | sym = n; | |
12563 | } | |
12564 | ||
12565 | symsec = S_GET_SEGMENT (sym); | |
12566 | ||
8614eeee UC |
12567 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
12568 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
12569 | { |
12570 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12571 | != 0) | |
12572 | linkonce = true; | |
12573 | ||
12574 | /* The GNU toolchain uses an extension for ELF: a section | |
12575 | beginning with the magic string .gnu.linkonce is a linkonce | |
12576 | section. */ | |
12577 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12578 | sizeof ".gnu.linkonce" - 1) == 0) | |
12579 | linkonce = true; | |
12580 | } | |
8614eeee | 12581 | |
252b5132 RH |
12582 | /* This must duplicate the test in adjust_reloc_syms. */ |
12583 | change = (symsec != &bfd_und_section | |
12584 | && symsec != &bfd_abs_section | |
426b0403 | 12585 | && ! bfd_is_com_section (symsec) |
8614eeee | 12586 | && !linkonce |
426b0403 | 12587 | #ifdef OBJ_ELF |
ea4ff978 | 12588 | /* A global or weak symbol is treated as external. */ |
9151e8bf | 12589 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
b25a253c CD |
12590 | || (! S_IS_WEAK (sym) |
12591 | && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC))) | |
426b0403 AM |
12592 | #endif |
12593 | ); | |
252b5132 RH |
12594 | } |
12595 | else | |
12596 | abort (); | |
12597 | ||
12598 | if (change) | |
12599 | { | |
12600 | /* Record the offset to the first reloc in the fr_opcode field. | |
12601 | This lets md_convert_frag and tc_gen_reloc know that the code | |
12602 | must be expanded. */ | |
12603 | fragp->fr_opcode = (fragp->fr_literal | |
12604 | + fragp->fr_fix | |
12605 | - RELAX_OLD (fragp->fr_subtype) | |
12606 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
12607 | /* FIXME: This really needs as_warn_where. */ | |
12608 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
12609 | as_warn (_("AT used after \".set noat\" or macro used after " |
12610 | "\".set nomacro\"")); | |
12611 | ||
12612 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
12613 | } |
12614 | ||
9a41af64 | 12615 | return 0; |
252b5132 RH |
12616 | } |
12617 | ||
12618 | /* This is called to see whether a reloc against a defined symbol | |
12619 | should be converted into a reloc against a section. Don't adjust | |
12620 | MIPS16 jump relocations, so we don't have to worry about the format | |
12621 | of the offset in the .o file. Don't adjust relocations against | |
12622 | mips16 symbols, so that the linker can find them if it needs to set | |
12623 | up a stub. */ | |
12624 | ||
12625 | int | |
12626 | mips_fix_adjustable (fixp) | |
12627 | fixS *fixp; | |
12628 | { | |
ea4ff978 L |
12629 | #ifdef OBJ_ELF |
12630 | /* Prevent all adjustments to global symbols. */ | |
46bac6de | 12631 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
b25a253c | 12632 | && mips_pic != EMBEDDED_PIC |
46bac6de | 12633 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) |
ea4ff978 L |
12634 | return 0; |
12635 | #endif | |
252b5132 RH |
12636 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12637 | return 0; | |
12638 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12639 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12640 | return 0; | |
12641 | if (fixp->fx_addsy == NULL) | |
12642 | return 1; | |
12643 | #ifdef OBJ_ELF | |
12644 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12645 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12646 | && fixp->fx_subsy == NULL) | |
12647 | return 0; | |
12648 | #endif | |
12649 | return 1; | |
12650 | } | |
12651 | ||
12652 | /* Translate internal representation of relocation info to BFD target | |
12653 | format. */ | |
12654 | ||
12655 | arelent ** | |
12656 | tc_gen_reloc (section, fixp) | |
43841e91 | 12657 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
12658 | fixS *fixp; |
12659 | { | |
12660 | static arelent *retval[4]; | |
12661 | arelent *reloc; | |
12662 | bfd_reloc_code_real_type code; | |
12663 | ||
12664 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
12665 | retval[1] = NULL; | |
12666 | ||
49309057 ILT |
12667 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12668 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12669 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12670 | ||
12671 | if (mips_pic == EMBEDDED_PIC | |
12672 | && SWITCH_TABLE (fixp)) | |
12673 | { | |
12674 | /* For a switch table entry we use a special reloc. The addend | |
12675 | is actually the difference between the reloc address and the | |
12676 | subtrahend. */ | |
12677 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12678 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12679 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12680 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12681 | } | |
12682 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
12683 | { | |
4514d474 CD |
12684 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12685 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12686 | else |
4514d474 CD |
12687 | { |
12688 | /* We use a special addend for an internal RELLO reloc. */ | |
12689 | if (symbol_section_p (fixp->fx_addsy)) | |
12690 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12691 | else | |
12692 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12693 | } | |
252b5132 RH |
12694 | } |
12695 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12696 | { | |
12697 | assert (fixp->fx_next != NULL | |
12698 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
12699 | |
12700 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 12701 | accordingly. */ |
4514d474 CD |
12702 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12703 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 12704 | else |
4514d474 CD |
12705 | { |
12706 | /* We use a special addend for an internal RELHI reloc. */ | |
12707 | if (symbol_section_p (fixp->fx_addsy)) | |
12708 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
12709 | + fixp->fx_next->fx_where | |
12710 | - S_GET_VALUE (fixp->fx_subsy)); | |
12711 | else | |
12712 | reloc->addend = (fixp->fx_addnumber | |
12713 | + fixp->fx_next->fx_frag->fr_address | |
12714 | + fixp->fx_next->fx_where); | |
12715 | } | |
252b5132 | 12716 | } |
4514d474 CD |
12717 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12718 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12719 | else |
12720 | { | |
12721 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12722 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12723 | handling. */ | |
12724 | reloc->addend = reloc->address; | |
12725 | else | |
12726 | reloc->addend = -reloc->address; | |
12727 | } | |
12728 | ||
12729 | /* If this is a variant frag, we may need to adjust the existing | |
12730 | reloc and generate a new one. */ | |
12731 | if (fixp->fx_frag->fr_opcode != NULL | |
cdf6fd85 | 12732 | && (fixp->fx_r_type == BFD_RELOC_GPREL16 |
252b5132 RH |
12733 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
12734 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12735 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12736 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12737 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d TS |
12738 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
12739 | && ! HAVE_NEWABI) | |
252b5132 RH |
12740 | { |
12741 | arelent *reloc2; | |
12742 | ||
12743 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12744 | ||
12745 | /* If this is not the last reloc in this frag, then we have two | |
12746 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12747 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12748 | the second one handle all of them. */ | |
12749 | if (fixp->fx_next != NULL | |
12750 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12751 | { | |
cdf6fd85 TS |
12752 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12753 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
12754 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
12755 | && (fixp->fx_next->fx_r_type | |
12756 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12757 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12758 | && (fixp->fx_next->fx_r_type | |
12759 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12760 | retval[0] = NULL; | |
12761 | return retval; | |
12762 | } | |
12763 | ||
12764 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12765 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12766 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12767 | retval[2] = NULL; | |
49309057 ILT |
12768 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12769 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12770 | reloc2->address = (reloc->address |
12771 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12772 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12773 | reloc2->addend = fixp->fx_addnumber; | |
12774 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12775 | assert (reloc2->howto != NULL); | |
12776 | ||
12777 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12778 | { | |
12779 | arelent *reloc3; | |
12780 | ||
12781 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12782 | retval[3] = NULL; | |
12783 | *reloc3 = *reloc2; | |
12784 | reloc3->address += 4; | |
12785 | } | |
12786 | ||
12787 | if (mips_pic == NO_PIC) | |
12788 | { | |
cdf6fd85 | 12789 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
12790 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
12791 | } | |
12792 | else if (mips_pic == SVR4_PIC) | |
12793 | { | |
12794 | switch (fixp->fx_r_type) | |
12795 | { | |
12796 | default: | |
12797 | abort (); | |
12798 | case BFD_RELOC_MIPS_GOT16: | |
12799 | break; | |
12800 | case BFD_RELOC_MIPS_CALL16: | |
12801 | case BFD_RELOC_MIPS_GOT_LO16: | |
12802 | case BFD_RELOC_MIPS_CALL_LO16: | |
12803 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12804 | break; | |
12805 | } | |
12806 | } | |
12807 | else | |
12808 | abort (); | |
12809 | } | |
12810 | ||
438c16b8 TS |
12811 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12812 | entry to be used in the relocation's section offset. */ | |
12813 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12814 | { |
12815 | reloc->address = reloc->addend; | |
12816 | reloc->addend = 0; | |
12817 | } | |
12818 | ||
12819 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12820 | fixup_segment converted a non-PC relative reloc into a PC | |
12821 | relative reloc. In such a case, we need to convert the reloc | |
12822 | code. */ | |
12823 | code = fixp->fx_r_type; | |
12824 | if (fixp->fx_pcrel) | |
12825 | { | |
12826 | switch (code) | |
12827 | { | |
12828 | case BFD_RELOC_8: | |
12829 | code = BFD_RELOC_8_PCREL; | |
12830 | break; | |
12831 | case BFD_RELOC_16: | |
12832 | code = BFD_RELOC_16_PCREL; | |
12833 | break; | |
12834 | case BFD_RELOC_32: | |
12835 | code = BFD_RELOC_32_PCREL; | |
12836 | break; | |
12837 | case BFD_RELOC_64: | |
12838 | code = BFD_RELOC_64_PCREL; | |
12839 | break; | |
12840 | case BFD_RELOC_8_PCREL: | |
12841 | case BFD_RELOC_16_PCREL: | |
12842 | case BFD_RELOC_32_PCREL: | |
12843 | case BFD_RELOC_64_PCREL: | |
12844 | case BFD_RELOC_16_PCREL_S2: | |
12845 | case BFD_RELOC_PCREL_HI16_S: | |
12846 | case BFD_RELOC_PCREL_LO16: | |
12847 | break; | |
12848 | default: | |
12849 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12850 | _("Cannot make %s relocation PC relative"), | |
12851 | bfd_get_reloc_code_name (code)); | |
12852 | } | |
12853 | } | |
12854 | ||
add55e1f RS |
12855 | #ifdef OBJ_ELF |
12856 | /* md_apply_fix3 has a double-subtraction hack to get | |
12857 | bfd_install_relocation to behave nicely. GPREL relocations are | |
12858 | handled correctly without this hack, so undo it here. We can't | |
12859 | stop md_apply_fix3 from subtracting twice in the first place since | |
12860 | the fake addend is required for variant frags above. */ | |
12861 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
d11008e1 | 12862 | && code == BFD_RELOC_GPREL16 |
add55e1f RS |
12863 | && reloc->addend != 0 |
12864 | && mips_need_elf_addend_fixup (fixp)) | |
12865 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
12866 | #endif | |
12867 | ||
252b5132 RH |
12868 | /* To support a PC relative reloc when generating embedded PIC code |
12869 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12870 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12871 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12872 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12873 | && code == BFD_RELOC_16_PCREL_S2 |
12874 | && mips_pic != EMBEDDED_PIC) | |
12875 | reloc->howto = NULL; | |
12876 | else | |
12877 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12878 | ||
12879 | if (reloc->howto == NULL) | |
12880 | { | |
12881 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12882 | _("Can not represent %s relocation in this object file format"), | |
12883 | bfd_get_reloc_code_name (code)); | |
12884 | retval[0] = NULL; | |
12885 | } | |
12886 | ||
12887 | return retval; | |
12888 | } | |
12889 | ||
12890 | /* Relax a machine dependent frag. This returns the amount by which | |
12891 | the current size of the frag should change. */ | |
12892 | ||
12893 | int | |
12894 | mips_relax_frag (fragp, stretch) | |
12895 | fragS *fragp; | |
12896 | long stretch; | |
12897 | { | |
12898 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12899 | return 0; | |
12900 | ||
c4e7957c | 12901 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12902 | { |
12903 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12904 | return 0; | |
12905 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12906 | return 2; | |
12907 | } | |
12908 | else | |
12909 | { | |
12910 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12911 | return 0; | |
12912 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12913 | return -2; | |
12914 | } | |
12915 | ||
12916 | return 0; | |
12917 | } | |
12918 | ||
12919 | /* Convert a machine dependent frag. */ | |
12920 | ||
12921 | void | |
12922 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12923 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12924 | segT asec; |
12925 | fragS *fragp; | |
12926 | { | |
12927 | int old, new; | |
12928 | char *fixptr; | |
12929 | ||
12930 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12931 | { | |
12932 | int type; | |
12933 | register const struct mips16_immed_operand *op; | |
12934 | boolean small, ext; | |
12935 | offsetT val; | |
12936 | bfd_byte *buf; | |
12937 | unsigned long insn; | |
12938 | boolean use_extend; | |
12939 | unsigned short extend; | |
12940 | ||
12941 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12942 | op = mips16_immed_operands; | |
12943 | while (op->type != type) | |
12944 | ++op; | |
12945 | ||
12946 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12947 | { | |
12948 | small = false; | |
12949 | ext = true; | |
12950 | } | |
12951 | else | |
12952 | { | |
12953 | small = true; | |
12954 | ext = false; | |
12955 | } | |
12956 | ||
6386f3a7 | 12957 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12958 | val = S_GET_VALUE (fragp->fr_symbol); |
12959 | if (op->pcrel) | |
12960 | { | |
12961 | addressT addr; | |
12962 | ||
12963 | addr = fragp->fr_address + fragp->fr_fix; | |
12964 | ||
12965 | /* The rules for the base address of a PC relative reloc are | |
12966 | complicated; see mips16_extended_frag. */ | |
12967 | if (type == 'p' || type == 'q') | |
12968 | { | |
12969 | addr += 2; | |
12970 | if (ext) | |
12971 | addr += 2; | |
12972 | /* Ignore the low bit in the target, since it will be | |
12973 | set for a text label. */ | |
12974 | if ((val & 1) != 0) | |
12975 | --val; | |
12976 | } | |
12977 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12978 | addr -= 4; | |
12979 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12980 | addr -= 2; | |
12981 | ||
12982 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12983 | val -= addr; | |
12984 | ||
12985 | /* Make sure the section winds up with the alignment we have | |
12986 | assumed. */ | |
12987 | if (op->shift > 0) | |
12988 | record_alignment (asec, op->shift); | |
12989 | } | |
12990 | ||
12991 | if (ext | |
12992 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12993 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12994 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12995 | _("extended instruction in delay slot")); | |
12996 | ||
12997 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
12998 | ||
12999 | if (target_big_endian) | |
13000 | insn = bfd_getb16 (buf); | |
13001 | else | |
13002 | insn = bfd_getl16 (buf); | |
13003 | ||
13004 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13005 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13006 | small, ext, &insn, &use_extend, &extend); | |
13007 | ||
13008 | if (use_extend) | |
13009 | { | |
874e8986 | 13010 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13011 | fragp->fr_fix += 2; |
13012 | buf += 2; | |
13013 | } | |
13014 | ||
874e8986 | 13015 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13016 | fragp->fr_fix += 2; |
13017 | buf += 2; | |
13018 | } | |
13019 | else | |
13020 | { | |
13021 | if (fragp->fr_opcode == NULL) | |
13022 | return; | |
13023 | ||
13024 | old = RELAX_OLD (fragp->fr_subtype); | |
13025 | new = RELAX_NEW (fragp->fr_subtype); | |
13026 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13027 | ||
13028 | if (new > 0) | |
13029 | memcpy (fixptr - old, fixptr, new); | |
13030 | ||
13031 | fragp->fr_fix += new - old; | |
13032 | } | |
13033 | } | |
13034 | ||
13035 | #ifdef OBJ_ELF | |
13036 | ||
13037 | /* This function is called after the relocs have been generated. | |
13038 | We've been storing mips16 text labels as odd. Here we convert them | |
13039 | back to even for the convenience of the debugger. */ | |
13040 | ||
13041 | void | |
13042 | mips_frob_file_after_relocs () | |
13043 | { | |
13044 | asymbol **syms; | |
13045 | unsigned int count, i; | |
13046 | ||
13047 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13048 | return; | |
13049 | ||
13050 | syms = bfd_get_outsymbols (stdoutput); | |
13051 | count = bfd_get_symcount (stdoutput); | |
13052 | for (i = 0; i < count; i++, syms++) | |
13053 | { | |
13054 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13055 | && ((*syms)->value & 1) != 0) | |
13056 | { | |
13057 | (*syms)->value &= ~1; | |
13058 | /* If the symbol has an odd size, it was probably computed | |
13059 | incorrectly, so adjust that as well. */ | |
13060 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13061 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13062 | } | |
13063 | } | |
13064 | } | |
13065 | ||
13066 | #endif | |
13067 | ||
13068 | /* This function is called whenever a label is defined. It is used | |
13069 | when handling branch delays; if a branch has a label, we assume we | |
13070 | can not move it. */ | |
13071 | ||
13072 | void | |
13073 | mips_define_label (sym) | |
13074 | symbolS *sym; | |
13075 | { | |
13076 | struct insn_label_list *l; | |
13077 | ||
13078 | if (free_insn_labels == NULL) | |
13079 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13080 | else | |
13081 | { | |
13082 | l = free_insn_labels; | |
13083 | free_insn_labels = l->next; | |
13084 | } | |
13085 | ||
13086 | l->label = sym; | |
13087 | l->next = insn_labels; | |
13088 | insn_labels = l; | |
13089 | } | |
13090 | \f | |
13091 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13092 | ||
13093 | /* Some special processing for a MIPS ELF file. */ | |
13094 | ||
13095 | void | |
13096 | mips_elf_final_processing () | |
13097 | { | |
13098 | /* Write out the register information. */ | |
195325d2 | 13099 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
13100 | { |
13101 | Elf32_RegInfo s; | |
13102 | ||
13103 | s.ri_gprmask = mips_gprmask; | |
13104 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13105 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13106 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13107 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13108 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13109 | ||
13110 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13111 | ((Elf32_External_RegInfo *) | |
13112 | mips_regmask_frag)); | |
13113 | } | |
13114 | else | |
13115 | { | |
13116 | Elf64_Internal_RegInfo s; | |
13117 | ||
13118 | s.ri_gprmask = mips_gprmask; | |
13119 | s.ri_pad = 0; | |
13120 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13121 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13122 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13123 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13124 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13125 | ||
13126 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13127 | ((Elf64_External_RegInfo *) | |
13128 | mips_regmask_frag)); | |
13129 | } | |
13130 | ||
13131 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13132 | sort of BFD interface for this. */ | |
13133 | if (mips_any_noreorder) | |
13134 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13135 | if (mips_pic != NO_PIC) | |
13136 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
13137 | ||
98d3f06f | 13138 | /* Set MIPS ELF flags for ASEs. */ |
1f25f5d3 CD |
13139 | #if 0 /* XXX FIXME */ |
13140 | if (file_ase_mips3d) | |
13141 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13142 | #endif | |
deec1734 CD |
13143 | if (file_ase_mdmx) |
13144 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13145 | |
bdaaa2e1 | 13146 | /* Set the MIPS ELF ABI flags. */ |
a325df1d | 13147 | if (file_mips_abi == NO_ABI) |
252b5132 | 13148 | ; |
a325df1d | 13149 | else if (file_mips_abi == O32_ABI) |
252b5132 | 13150 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
a325df1d | 13151 | else if (file_mips_abi == O64_ABI) |
252b5132 | 13152 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
a325df1d | 13153 | else if (file_mips_abi == EABI_ABI) |
252b5132 RH |
13154 | { |
13155 | if (mips_eabi64) | |
13156 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
13157 | else | |
13158 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13159 | } | |
a325df1d | 13160 | else if (file_mips_abi == N32_ABI) |
be00bddd TS |
13161 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13162 | ||
c9914766 | 13163 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13164 | |
13165 | if (mips_32bitmode) | |
13166 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13167 | } | |
13168 | ||
13169 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13170 | \f | |
beae10d5 KH |
13171 | typedef struct proc { |
13172 | symbolS *isym; | |
13173 | unsigned long reg_mask; | |
13174 | unsigned long reg_offset; | |
13175 | unsigned long fpreg_mask; | |
13176 | unsigned long fpreg_offset; | |
13177 | unsigned long frame_offset; | |
13178 | unsigned long frame_reg; | |
13179 | unsigned long pc_reg; | |
13180 | } procS; | |
252b5132 RH |
13181 | |
13182 | static procS cur_proc; | |
13183 | static procS *cur_proc_ptr; | |
13184 | static int numprocs; | |
13185 | ||
0a9ef439 | 13186 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13187 | |
0a9ef439 RH |
13188 | void |
13189 | mips_handle_align (fragp) | |
13190 | fragS *fragp; | |
a19d8eb0 | 13191 | { |
0a9ef439 RH |
13192 | if (fragp->fr_type != rs_align_code) |
13193 | return; | |
13194 | ||
13195 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13196 | { |
13197 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13198 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13199 | ||
0a9ef439 RH |
13200 | int bytes; |
13201 | char *p; | |
a19d8eb0 | 13202 | |
0a9ef439 RH |
13203 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13204 | p = fragp->fr_literal + fragp->fr_fix; | |
13205 | ||
13206 | if (bytes & 1) | |
13207 | { | |
13208 | *p++ = 0; | |
f9419b05 | 13209 | fragp->fr_fix++; |
0a9ef439 RH |
13210 | } |
13211 | ||
13212 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13213 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13214 | } |
13215 | ||
0a9ef439 | 13216 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13217 | } |
13218 | ||
252b5132 RH |
13219 | static void |
13220 | md_obj_begin () | |
13221 | { | |
13222 | } | |
13223 | ||
13224 | static void | |
13225 | md_obj_end () | |
13226 | { | |
13227 | /* check for premature end, nesting errors, etc */ | |
13228 | if (cur_proc_ptr) | |
9a41af64 | 13229 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13230 | } |
13231 | ||
13232 | static long | |
13233 | get_number () | |
13234 | { | |
13235 | int negative = 0; | |
13236 | long val = 0; | |
13237 | ||
13238 | if (*input_line_pointer == '-') | |
13239 | { | |
13240 | ++input_line_pointer; | |
13241 | negative = 1; | |
13242 | } | |
3882b010 | 13243 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13244 | as_bad (_("expected simple number")); |
252b5132 RH |
13245 | if (input_line_pointer[0] == '0') |
13246 | { | |
13247 | if (input_line_pointer[1] == 'x') | |
13248 | { | |
13249 | input_line_pointer += 2; | |
3882b010 | 13250 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13251 | { |
13252 | val <<= 4; | |
13253 | val |= hex_value (*input_line_pointer++); | |
13254 | } | |
13255 | return negative ? -val : val; | |
13256 | } | |
13257 | else | |
13258 | { | |
13259 | ++input_line_pointer; | |
3882b010 | 13260 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13261 | { |
13262 | val <<= 3; | |
13263 | val |= *input_line_pointer++ - '0'; | |
13264 | } | |
13265 | return negative ? -val : val; | |
13266 | } | |
13267 | } | |
3882b010 | 13268 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13269 | { |
13270 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13271 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13272 | as_warn (_("invalid number")); |
252b5132 RH |
13273 | return -1; |
13274 | } | |
3882b010 | 13275 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13276 | { |
13277 | val *= 10; | |
13278 | val += *input_line_pointer++ - '0'; | |
13279 | } | |
13280 | return negative ? -val : val; | |
13281 | } | |
13282 | ||
13283 | /* The .file directive; just like the usual .file directive, but there | |
13284 | is an initial number which is the ECOFF file index. */ | |
13285 | ||
13286 | static void | |
13287 | s_file (x) | |
43841e91 | 13288 | int x ATTRIBUTE_UNUSED; |
252b5132 | 13289 | { |
874e8986 | 13290 | get_number (); |
252b5132 RH |
13291 | s_app_file (0); |
13292 | } | |
13293 | ||
252b5132 RH |
13294 | /* The .end directive. */ |
13295 | ||
13296 | static void | |
13297 | s_mips_end (x) | |
43841e91 | 13298 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
13299 | { |
13300 | symbolS *p; | |
13301 | int maybe_text; | |
13302 | ||
7a621144 DJ |
13303 | /* Following functions need their own .frame and .cprestore directives. */ |
13304 | mips_frame_reg_valid = 0; | |
13305 | mips_cprestore_valid = 0; | |
13306 | ||
252b5132 RH |
13307 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13308 | { | |
13309 | p = get_symbol (); | |
13310 | demand_empty_rest_of_line (); | |
13311 | } | |
13312 | else | |
13313 | p = NULL; | |
13314 | ||
13315 | #ifdef BFD_ASSEMBLER | |
13316 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13317 | maybe_text = 1; | |
13318 | else | |
13319 | maybe_text = 0; | |
13320 | #else | |
13321 | if (now_seg != data_section && now_seg != bss_section) | |
13322 | maybe_text = 1; | |
13323 | else | |
13324 | maybe_text = 0; | |
13325 | #endif | |
13326 | ||
13327 | if (!maybe_text) | |
13328 | as_warn (_(".end not in text section")); | |
13329 | ||
13330 | if (!cur_proc_ptr) | |
13331 | { | |
13332 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13333 | demand_empty_rest_of_line (); | |
13334 | return; | |
13335 | } | |
13336 | ||
13337 | if (p != NULL) | |
13338 | { | |
13339 | assert (S_GET_NAME (p)); | |
13340 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13341 | as_warn (_(".end symbol does not match .ent symbol.")); | |
13342 | } | |
13343 | else | |
13344 | as_warn (_(".end directive missing or unknown symbol")); | |
13345 | ||
13346 | #ifdef MIPS_STABS_ELF | |
13347 | { | |
13348 | segT saved_seg = now_seg; | |
13349 | subsegT saved_subseg = now_subseg; | |
252b5132 | 13350 | valueT dot; |
252b5132 RH |
13351 | expressionS exp; |
13352 | char *fragp; | |
13353 | ||
13354 | dot = frag_now_fix (); | |
13355 | ||
13356 | #ifdef md_flush_pending_output | |
13357 | md_flush_pending_output (); | |
13358 | #endif | |
13359 | ||
13360 | assert (pdr_seg); | |
13361 | subseg_set (pdr_seg, 0); | |
13362 | ||
beae10d5 | 13363 | /* Write the symbol. */ |
252b5132 RH |
13364 | exp.X_op = O_symbol; |
13365 | exp.X_add_symbol = p; | |
13366 | exp.X_add_number = 0; | |
13367 | emit_expr (&exp, 4); | |
13368 | ||
beae10d5 | 13369 | fragp = frag_more (7 * 4); |
252b5132 | 13370 | |
beae10d5 KH |
13371 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
13372 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
13373 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
13374 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
13375 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
13376 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
13377 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
13378 | |
13379 | subseg_set (saved_seg, saved_subseg); | |
13380 | } | |
f9419b05 | 13381 | #endif /* MIPS_STABS_ELF */ |
252b5132 RH |
13382 | |
13383 | cur_proc_ptr = NULL; | |
13384 | } | |
13385 | ||
13386 | /* The .aent and .ent directives. */ | |
13387 | ||
13388 | static void | |
13389 | s_mips_ent (aent) | |
13390 | int aent; | |
13391 | { | |
252b5132 RH |
13392 | symbolS *symbolP; |
13393 | int maybe_text; | |
13394 | ||
13395 | symbolP = get_symbol (); | |
13396 | if (*input_line_pointer == ',') | |
f9419b05 | 13397 | ++input_line_pointer; |
252b5132 | 13398 | SKIP_WHITESPACE (); |
3882b010 | 13399 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13400 | || *input_line_pointer == '-') |
874e8986 | 13401 | get_number (); |
252b5132 RH |
13402 | |
13403 | #ifdef BFD_ASSEMBLER | |
13404 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13405 | maybe_text = 1; | |
13406 | else | |
13407 | maybe_text = 0; | |
13408 | #else | |
13409 | if (now_seg != data_section && now_seg != bss_section) | |
13410 | maybe_text = 1; | |
13411 | else | |
13412 | maybe_text = 0; | |
13413 | #endif | |
13414 | ||
13415 | if (!maybe_text) | |
13416 | as_warn (_(".ent or .aent not in text section.")); | |
13417 | ||
13418 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13419 | as_warn (_("missing .end")); |
252b5132 RH |
13420 | |
13421 | if (!aent) | |
13422 | { | |
7a621144 DJ |
13423 | /* This function needs its own .frame and .cprestore directives. */ |
13424 | mips_frame_reg_valid = 0; | |
13425 | mips_cprestore_valid = 0; | |
13426 | ||
252b5132 RH |
13427 | cur_proc_ptr = &cur_proc; |
13428 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13429 | ||
13430 | cur_proc_ptr->isym = symbolP; | |
13431 | ||
49309057 | 13432 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13433 | |
f9419b05 | 13434 | ++numprocs; |
252b5132 RH |
13435 | } |
13436 | ||
13437 | demand_empty_rest_of_line (); | |
13438 | } | |
13439 | ||
13440 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13441 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13442 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13443 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13444 | symbol table (in the mdebug section). */ |
13445 | ||
13446 | static void | |
13447 | s_mips_frame (ignore) | |
2b3c5a5d | 13448 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
13449 | { |
13450 | #ifdef MIPS_STABS_ELF | |
13451 | ||
13452 | long val; | |
13453 | ||
beae10d5 | 13454 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
13455 | { |
13456 | as_warn (_(".frame outside of .ent")); | |
13457 | demand_empty_rest_of_line (); | |
13458 | return; | |
13459 | } | |
13460 | ||
13461 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
13462 | ||
13463 | SKIP_WHITESPACE (); | |
13464 | if (*input_line_pointer++ != ',' | |
13465 | || get_absolute_expression_and_terminator (&val) != ',') | |
13466 | { | |
13467 | as_warn (_("Bad .frame directive")); | |
13468 | --input_line_pointer; | |
13469 | demand_empty_rest_of_line (); | |
13470 | return; | |
13471 | } | |
13472 | ||
13473 | cur_proc_ptr->frame_offset = val; | |
13474 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
13475 | ||
13476 | demand_empty_rest_of_line (); | |
13477 | #else | |
13478 | s_ignore (ignore); | |
13479 | #endif /* MIPS_STABS_ELF */ | |
13480 | } | |
13481 | ||
bdaaa2e1 KH |
13482 | /* The .fmask and .mask directives. If the mdebug section is present |
13483 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13484 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13485 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13486 | make reference to the ecoff symbol table (in the mdebug section). */ |
13487 | ||
13488 | static void | |
13489 | s_mips_mask (reg_type) | |
13490 | char reg_type; | |
13491 | { | |
13492 | #ifdef MIPS_STABS_ELF | |
13493 | long mask, off; | |
bdaaa2e1 | 13494 | |
252b5132 RH |
13495 | if (cur_proc_ptr == (procS *) NULL) |
13496 | { | |
13497 | as_warn (_(".mask/.fmask outside of .ent")); | |
13498 | demand_empty_rest_of_line (); | |
13499 | return; | |
13500 | } | |
13501 | ||
13502 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
13503 | { | |
13504 | as_warn (_("Bad .mask/.fmask directive")); | |
13505 | --input_line_pointer; | |
13506 | demand_empty_rest_of_line (); | |
13507 | return; | |
13508 | } | |
13509 | ||
13510 | off = get_absolute_expression (); | |
13511 | ||
13512 | if (reg_type == 'F') | |
13513 | { | |
13514 | cur_proc_ptr->fpreg_mask = mask; | |
13515 | cur_proc_ptr->fpreg_offset = off; | |
13516 | } | |
13517 | else | |
13518 | { | |
13519 | cur_proc_ptr->reg_mask = mask; | |
13520 | cur_proc_ptr->reg_offset = off; | |
13521 | } | |
13522 | ||
13523 | demand_empty_rest_of_line (); | |
13524 | #else | |
13525 | s_ignore (reg_type); | |
13526 | #endif /* MIPS_STABS_ELF */ | |
13527 | } | |
13528 | ||
13529 | /* The .loc directive. */ | |
13530 | ||
13531 | #if 0 | |
13532 | static void | |
13533 | s_loc (x) | |
13534 | int x; | |
13535 | { | |
13536 | symbolS *symbolP; | |
13537 | int lineno; | |
13538 | int addroff; | |
13539 | ||
13540 | assert (now_seg == text_section); | |
13541 | ||
13542 | lineno = get_number (); | |
13543 | addroff = frag_now_fix (); | |
13544 | ||
13545 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13546 | S_SET_TYPE (symbolP, N_SLINE); | |
13547 | S_SET_OTHER (symbolP, 0); | |
13548 | S_SET_DESC (symbolP, lineno); | |
13549 | symbolP->sy_segment = now_seg; | |
13550 | } | |
13551 | #endif | |
e7af610e NC |
13552 | |
13553 | /* CPU name/ISA/number mapping table. | |
13554 | ||
13555 | Entries are grouped by type. The first matching CPU or ISA entry | |
13556 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
13557 | for that type. Entries after that within the type are sorted | |
13558 | alphabetically. | |
13559 | ||
13560 | Case is ignored in comparison, so put the canonical entry in the | |
13561 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
13562 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13563 | { | |
e7af610e NC |
13564 | /* MIPS1 ISA */ |
13565 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
13566 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
13567 | ||
13568 | /* MIPS2 ISA */ | |
13569 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
13570 | ||
13571 | /* MIPS3 ISA */ | |
13572 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
13573 | ||
13574 | /* MIPS4 ISA */ | |
13575 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
13576 | ||
84ea6cf2 NC |
13577 | /* MIPS5 ISA */ |
13578 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
13579 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
13580 | ||
e7af610e NC |
13581 | /* MIPS32 ISA */ |
13582 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
3c02b2ab | 13583 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
e7af610e | 13584 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
3c02b2ab EC |
13585 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
13586 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13587 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13588 | ||
13589 | /* For historical reasons. */ | |
13590 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, | |
e7af610e | 13591 | |
84ea6cf2 | 13592 | /* MIPS64 ISA */ |
3c02b2ab | 13593 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
84ea6cf2 | 13594 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
3c02b2ab EC |
13595 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
13596 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
13597 | |
13598 | /* R2000 CPU */ | |
13599 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13600 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13601 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13602 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13603 | ||
13604 | /* R3000 CPU */ | |
13605 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13606 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13607 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13608 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13609 | ||
13610 | /* TX3900 CPU */ | |
13611 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
13612 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 13613 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
13614 | |
13615 | /* R4000 CPU */ | |
13616 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13617 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13618 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
13619 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
13620 | ||
13621 | /* R4010 CPU */ | |
13622 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13623 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13624 | ||
13625 | /* R4400 CPU */ | |
13626 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13627 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13628 | ||
13629 | /* R4600 CPU */ | |
13630 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13631 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13632 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13633 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13634 | ||
13635 | /* R4650 CPU */ | |
13636 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13637 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13638 | ||
13639 | /* R6000 CPU */ | |
13640 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13641 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13642 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13643 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13644 | ||
13645 | /* R8000 CPU */ | |
13646 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13647 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13648 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13649 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13650 | ||
13651 | /* R10000 CPU */ | |
13652 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13653 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13654 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13655 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13656 | ||
d1cf510e NC |
13657 | /* R12000 CPU */ |
13658 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13659 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13660 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13661 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13662 | ||
e7af610e NC |
13663 | /* VR4100 CPU */ |
13664 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13665 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13666 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13667 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13668 | ||
13669 | /* VR4111 CPU */ | |
13670 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13671 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13672 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13673 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13674 | ||
13675 | /* VR4300 CPU */ | |
13676 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13677 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13678 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13679 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13680 | ||
13681 | /* VR5000 CPU */ | |
13682 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13683 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13684 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
13685 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13686 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13687 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 13688 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13689 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13690 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13691 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13692 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13693 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13694 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13695 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13696 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
13697 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
13698 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
13699 | ||
2e4acd24 | 13700 | /* Broadcom SB-1 CPU */ |
c6c98b38 | 13701 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, |
e972090a | 13702 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
13703 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
13704 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
13705 | ||
beae10d5 | 13706 | /* End marker. */ |
e7af610e NC |
13707 | { NULL, 0, 0, 0, }, |
13708 | }; | |
13709 | ||
13710 | static const struct mips_cpu_info * | |
13711 | mips_cpu_info_from_name (name) | |
13712 | const char *name; | |
13713 | { | |
13714 | int i; | |
13715 | ||
13716 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 13717 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
13718 | return (&mips_cpu_info_table[i]); |
13719 | ||
e972090a | 13720 | return NULL; |
e7af610e NC |
13721 | } |
13722 | ||
13723 | static const struct mips_cpu_info * | |
13724 | mips_cpu_info_from_isa (isa) | |
13725 | int isa; | |
13726 | { | |
13727 | int i; | |
13728 | ||
13729 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13730 | if (mips_cpu_info_table[i].is_isa | |
13731 | && isa == mips_cpu_info_table[i].isa) | |
13732 | return (&mips_cpu_info_table[i]); | |
13733 | ||
e972090a | 13734 | return NULL; |
e7af610e NC |
13735 | } |
13736 | ||
13737 | static const struct mips_cpu_info * | |
13738 | mips_cpu_info_from_cpu (cpu) | |
13739 | int cpu; | |
13740 | { | |
13741 | int i; | |
13742 | ||
13743 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13744 | if (!mips_cpu_info_table[i].is_isa | |
13745 | && cpu == mips_cpu_info_table[i].cpu) | |
13746 | return (&mips_cpu_info_table[i]); | |
13747 | ||
e972090a | 13748 | return NULL; |
e7af610e | 13749 | } |