Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
ef2e4d86 | 198 | int ase_mt; |
252b5132 RH |
199 | /* Whether we are assembling for the mips16 processor. 0 if we are |
200 | not, 1 if we are, and -1 if the value has not been initialized. | |
201 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
202 | -nomips16 command line options, and the default CPU. */ | |
203 | int mips16; | |
204 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
205 | reorder' and `.set noreorder'. */ | |
206 | int noreorder; | |
207 | /* Non-zero if we should not permit the $at ($1) register to be used | |
208 | in instructions. Changed by `.set at' and `.set noat'. */ | |
209 | int noat; | |
210 | /* Non-zero if we should warn when a macro instruction expands into | |
211 | more than one machine instruction. Changed by `.set nomacro' and | |
212 | `.set macro'. */ | |
213 | int warn_about_macros; | |
214 | /* Non-zero if we should not move instructions. Changed by `.set | |
215 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
216 | int nomove; | |
217 | /* Non-zero if we should not optimize branches by moving the target | |
218 | of the branch into the delay slot. Actually, we don't perform | |
219 | this optimization anyhow. Changed by `.set bopt' and `.set | |
220 | nobopt'. */ | |
221 | int nobopt; | |
222 | /* Non-zero if we should not autoextend mips16 instructions. | |
223 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
224 | int noautoextend; | |
a325df1d TS |
225 | /* Restrict general purpose registers and floating point registers |
226 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
227 | is passed but can changed if the assembler code uses .set mipsN. */ | |
228 | int gp32; | |
229 | int fp32; | |
fef14a42 TS |
230 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
231 | command line option, and the default CPU. */ | |
232 | int arch; | |
aed1a261 RS |
233 | /* True if ".set sym32" is in effect. */ |
234 | bfd_boolean sym32; | |
252b5132 RH |
235 | }; |
236 | ||
a325df1d | 237 | /* True if -mgp32 was passed. */ |
a8e8e863 | 238 | static int file_mips_gp32 = -1; |
a325df1d TS |
239 | |
240 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 241 | static int file_mips_fp32 = -1; |
a325df1d | 242 | |
252b5132 | 243 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 244 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 245 | -1 to indicate that they have not been initialized. */ |
252b5132 | 246 | |
e972090a NC |
247 | static struct mips_set_options mips_opts = |
248 | { | |
e16bfa71 | 249 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 250 | }; |
252b5132 RH |
251 | |
252 | /* These variables are filled in with the masks of registers used. | |
253 | The object format code reads them and puts them in the appropriate | |
254 | place. */ | |
255 | unsigned long mips_gprmask; | |
256 | unsigned long mips_cprmask[4]; | |
257 | ||
258 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 259 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 260 | |
a4672219 TS |
261 | /* True if -mips16 was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips16; | |
264 | ||
1f25f5d3 CD |
265 | /* True if -mips3d was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mips3d; | |
268 | ||
deec1734 CD |
269 | /* True if -mdmx was passed or implied by arguments passed on the |
270 | command line (e.g., by -march). */ | |
271 | static int file_ase_mdmx; | |
272 | ||
e16bfa71 TS |
273 | /* True if -msmartmips was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_smartmips; | |
276 | ||
277 | #define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ | |
278 | || mips_opts.isa == ISA_MIPS32R2) | |
279 | ||
74cd071d CF |
280 | /* True if -mdsp was passed or implied by arguments passed on the |
281 | command line (e.g., by -march). */ | |
282 | static int file_ase_dsp; | |
283 | ||
ef2e4d86 CF |
284 | /* True if -mmt was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_mt; | |
287 | ||
ec68c924 | 288 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 289 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 290 | static const char *mips_arch_string; |
ec68c924 EC |
291 | |
292 | /* The argument of the -mtune= flag. The architecture for which we | |
293 | are optimizing. */ | |
294 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 295 | static const char *mips_tune_string; |
ec68c924 | 296 | |
316f5878 | 297 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
298 | static int mips_32bitmode = 0; |
299 | ||
316f5878 RS |
300 | /* True if the given ABI requires 32-bit registers. */ |
301 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
302 | ||
303 | /* Likewise 64-bit registers. */ | |
304 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
305 | ((ABI) == N32_ABI \ | |
306 | || (ABI) == N64_ABI \ | |
307 | || (ABI) == O64_ABI) | |
308 | ||
bdaaa2e1 | 309 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 310 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
311 | (ISA) == ISA_MIPS3 \ |
312 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 313 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 314 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 315 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
316 | ) |
317 | ||
af7ee8bf CD |
318 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
319 | instructions. */ | |
320 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 321 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
322 | ) |
323 | ||
324 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
325 | instructions. */ | |
326 | #define ISA_HAS_ROR(ISA) ( \ | |
327 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 328 | || (ISA) == ISA_MIPS64R2 \ |
e16bfa71 | 329 | || mips_opts.ase_smartmips \ |
af7ee8bf CD |
330 | ) |
331 | ||
e013f690 | 332 | #define HAVE_32BIT_GPRS \ |
316f5878 | 333 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 334 | |
e013f690 | 335 | #define HAVE_32BIT_FPRS \ |
316f5878 | 336 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
337 | |
338 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
339 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
340 | ||
316f5878 | 341 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 342 | |
316f5878 | 343 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 344 | |
3b91255e RS |
345 | /* True if relocations are stored in-place. */ |
346 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
347 | ||
aed1a261 RS |
348 | /* The ABI-derived address size. */ |
349 | #define HAVE_64BIT_ADDRESSES \ | |
350 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
351 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 352 | |
aed1a261 RS |
353 | /* The size of symbolic constants (i.e., expressions of the form |
354 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
355 | #define HAVE_32BIT_SYMBOLS \ | |
356 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
357 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 358 | |
b7c7d6c1 TS |
359 | /* Addresses are loaded in different ways, depending on the address size |
360 | in use. The n32 ABI Documentation also mandates the use of additions | |
361 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 362 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 363 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
364 | |
365 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 366 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
367 | |
368 | #define ADDRESS_LOAD_INSN \ | |
369 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
370 | ||
371 | #define ADDRESS_STORE_INSN \ | |
372 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
373 | ||
a4672219 | 374 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
375 | #define CPU_HAS_MIPS16(cpu) \ |
376 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
377 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 378 | |
1f25f5d3 CD |
379 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
380 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
381 | ) | |
382 | ||
deec1734 | 383 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 384 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
385 | ) |
386 | ||
74cd071d CF |
387 | /* Return true if the given CPU supports the DSP ASE. */ |
388 | #define CPU_HAS_DSP(cpu) (FALSE \ | |
389 | ) | |
390 | ||
ef2e4d86 CF |
391 | /* Return true if the given CPU supports the MT ASE. */ |
392 | #define CPU_HAS_MT(cpu) (FALSE \ | |
393 | ) | |
394 | ||
60b63b72 RS |
395 | /* True if CPU has a dror instruction. */ |
396 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
397 | ||
398 | /* True if CPU has a ror instruction. */ | |
399 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
400 | ||
c8978940 CD |
401 | /* True if mflo and mfhi can be immediately followed by instructions |
402 | which write to the HI and LO registers. | |
403 | ||
404 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
405 | (at least) two instructions between the reads of HI/LO and | |
406 | instructions which write them, and later ISAs do not. Contradicting | |
407 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
408 | the UM for the NEC Vr5000) document needing the instructions between | |
409 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
410 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
411 | earlier-ISA CPUs for which CPU documentation declares that the | |
412 | instructions are really interlocked. */ | |
413 | #define hilo_interlocks \ | |
414 | (mips_opts.isa == ISA_MIPS32 \ | |
415 | || mips_opts.isa == ISA_MIPS32R2 \ | |
416 | || mips_opts.isa == ISA_MIPS64 \ | |
417 | || mips_opts.isa == ISA_MIPS64R2 \ | |
418 | || mips_opts.arch == CPU_R4010 \ | |
419 | || mips_opts.arch == CPU_R10000 \ | |
420 | || mips_opts.arch == CPU_R12000 \ | |
421 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
422 | || mips_opts.arch == CPU_VR5500 \ |
423 | ) | |
252b5132 RH |
424 | |
425 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
426 | from the GPRs after they are loaded from memory, and thus does not |
427 | require nops to be inserted. This applies to instructions marked | |
428 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
429 | level I. */ | |
252b5132 | 430 | #define gpr_interlocks \ |
e7af610e | 431 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 432 | || mips_opts.arch == CPU_R3900) |
252b5132 | 433 | |
81912461 ILT |
434 | /* Whether the processor uses hardware interlocks to avoid delays |
435 | required by coprocessor instructions, and thus does not require | |
436 | nops to be inserted. This applies to instructions marked | |
437 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
438 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
439 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
440 | levels I, II, and III. */ | |
bdaaa2e1 | 441 | /* Itbl support may require additional care here. */ |
81912461 ILT |
442 | #define cop_interlocks \ |
443 | ((mips_opts.isa != ISA_MIPS1 \ | |
444 | && mips_opts.isa != ISA_MIPS2 \ | |
445 | && mips_opts.isa != ISA_MIPS3) \ | |
446 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
447 | ) |
448 | ||
449 | /* Whether the processor uses hardware interlocks to protect reads | |
450 | from coprocessor registers after they are loaded from memory, and | |
451 | thus does not require nops to be inserted. This applies to | |
452 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
453 | requires at MIPS ISA level I. */ | |
454 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 455 | |
6b76fefe CM |
456 | /* Is this a mfhi or mflo instruction? */ |
457 | #define MF_HILO_INSN(PINFO) \ | |
458 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
459 | ||
252b5132 RH |
460 | /* MIPS PIC level. */ |
461 | ||
a161fe53 | 462 | enum mips_pic_level mips_pic; |
252b5132 | 463 | |
c9914766 | 464 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 465 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 466 | static int mips_big_got = 0; |
252b5132 RH |
467 | |
468 | /* 1 if trap instructions should used for overflow rather than break | |
469 | instructions. */ | |
c9914766 | 470 | static int mips_trap = 0; |
252b5132 | 471 | |
119d663a | 472 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 473 | by assembling two single width halves into two single width floating |
119d663a NC |
474 | point registers which just happen to alias the double width destination |
475 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 476 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
477 | automatically at assemble time. */ |
478 | static int mips_disable_float_construction; | |
479 | ||
252b5132 RH |
480 | /* Non-zero if any .set noreorder directives were used. */ |
481 | ||
482 | static int mips_any_noreorder; | |
483 | ||
6b76fefe CM |
484 | /* Non-zero if nops should be inserted when the register referenced in |
485 | an mfhi/mflo instruction is read in the next two instructions. */ | |
486 | static int mips_7000_hilo_fix; | |
487 | ||
252b5132 | 488 | /* The size of the small data section. */ |
156c2f8b | 489 | static unsigned int g_switch_value = 8; |
252b5132 RH |
490 | /* Whether the -G option was used. */ |
491 | static int g_switch_seen = 0; | |
492 | ||
493 | #define N_RMASK 0xc4 | |
494 | #define N_VFP 0xd4 | |
495 | ||
496 | /* If we can determine in advance that GP optimization won't be | |
497 | possible, we can skip the relaxation stuff that tries to produce | |
498 | GP-relative references. This makes delay slot optimization work | |
499 | better. | |
500 | ||
501 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
502 | gcc output. It needs to guess right for gcc, otherwise gcc |
503 | will put what it thinks is a GP-relative instruction in a branch | |
504 | delay slot. | |
252b5132 RH |
505 | |
506 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
507 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 508 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
509 | |
510 | /* handle of the OPCODE hash table */ | |
511 | static struct hash_control *op_hash = NULL; | |
512 | ||
513 | /* The opcode hash table we use for the mips16. */ | |
514 | static struct hash_control *mips16_op_hash = NULL; | |
515 | ||
516 | /* This array holds the chars that always start a comment. If the | |
517 | pre-processor is disabled, these aren't very useful */ | |
518 | const char comment_chars[] = "#"; | |
519 | ||
520 | /* This array holds the chars that only start a comment at the beginning of | |
521 | a line. If the line seems to have the form '# 123 filename' | |
522 | .line and .file directives will appear in the pre-processed output */ | |
523 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
524 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 525 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
526 | /* Also note that C style comments are always supported. */ |
527 | const char line_comment_chars[] = "#"; | |
528 | ||
bdaaa2e1 | 529 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 530 | const char line_separator_chars[] = ";"; |
252b5132 RH |
531 | |
532 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
533 | const char EXP_CHARS[] = "eE"; | |
534 | ||
535 | /* Chars that mean this number is a floating point constant */ | |
536 | /* As in 0f12.456 */ | |
537 | /* or 0d1.2345e12 */ | |
538 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
539 | ||
540 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
541 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
542 | but nothing is ideal around here. | |
543 | */ | |
544 | ||
545 | static char *insn_error; | |
546 | ||
547 | static int auto_align = 1; | |
548 | ||
549 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
550 | offset in the stack frame from which to restore the $gp register. | |
551 | This is set by the .cprestore pseudo-op, and saved in this | |
552 | variable. */ | |
553 | static offsetT mips_cprestore_offset = -1; | |
554 | ||
67c1ffbe | 555 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 556 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 557 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
558 | static offsetT mips_cpreturn_offset = -1; |
559 | static int mips_cpreturn_register = -1; | |
560 | static int mips_gp_register = GP; | |
def2e0dd | 561 | static int mips_gprel_offset = 0; |
6478892d | 562 | |
7a621144 DJ |
563 | /* Whether mips_cprestore_offset has been set in the current function |
564 | (or whether it has already been warned about, if not). */ | |
565 | static int mips_cprestore_valid = 0; | |
566 | ||
252b5132 RH |
567 | /* This is the register which holds the stack frame, as set by the |
568 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
569 | static int mips_frame_reg = SP; | |
570 | ||
7a621144 DJ |
571 | /* Whether mips_frame_reg has been set in the current function |
572 | (or whether it has already been warned about, if not). */ | |
573 | static int mips_frame_reg_valid = 0; | |
574 | ||
252b5132 RH |
575 | /* To output NOP instructions correctly, we need to keep information |
576 | about the previous two instructions. */ | |
577 | ||
578 | /* Whether we are optimizing. The default value of 2 means to remove | |
579 | unneeded NOPs and swap branch instructions when possible. A value | |
580 | of 1 means to not swap branches. A value of 0 means to always | |
581 | insert NOPs. */ | |
582 | static int mips_optimize = 2; | |
583 | ||
584 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
585 | equivalent to seeing no -g option at all. */ | |
586 | static int mips_debug = 0; | |
587 | ||
7d8e00cf RS |
588 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
589 | #define MAX_VR4130_NOPS 4 | |
590 | ||
591 | /* The maximum number of NOPs needed to fill delay slots. */ | |
592 | #define MAX_DELAY_NOPS 2 | |
593 | ||
594 | /* The maximum number of NOPs needed for any purpose. */ | |
595 | #define MAX_NOPS 4 | |
71400594 RS |
596 | |
597 | /* A list of previous instructions, with index 0 being the most recent. | |
598 | We need to look back MAX_NOPS instructions when filling delay slots | |
599 | or working around processor errata. We need to look back one | |
600 | instruction further if we're thinking about using history[0] to | |
601 | fill a branch delay slot. */ | |
602 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 603 | |
1e915849 RS |
604 | /* Nop instructions used by emit_nop. */ |
605 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
606 | ||
607 | /* The appropriate nop for the current mode. */ | |
608 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 609 | |
252b5132 RH |
610 | /* If this is set, it points to a frag holding nop instructions which |
611 | were inserted before the start of a noreorder section. If those | |
612 | nops turn out to be unnecessary, the size of the frag can be | |
613 | decreased. */ | |
614 | static fragS *prev_nop_frag; | |
615 | ||
616 | /* The number of nop instructions we created in prev_nop_frag. */ | |
617 | static int prev_nop_frag_holds; | |
618 | ||
619 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 620 | prev_nop_frag. */ |
252b5132 RH |
621 | static int prev_nop_frag_required; |
622 | ||
623 | /* The number of instructions we've seen since prev_nop_frag. */ | |
624 | static int prev_nop_frag_since; | |
625 | ||
626 | /* For ECOFF and ELF, relocations against symbols are done in two | |
627 | parts, with a HI relocation and a LO relocation. Each relocation | |
628 | has only 16 bits of space to store an addend. This means that in | |
629 | order for the linker to handle carries correctly, it must be able | |
630 | to locate both the HI and the LO relocation. This means that the | |
631 | relocations must appear in order in the relocation table. | |
632 | ||
633 | In order to implement this, we keep track of each unmatched HI | |
634 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 635 | corresponding LO relocation. */ |
252b5132 | 636 | |
e972090a NC |
637 | struct mips_hi_fixup |
638 | { | |
252b5132 RH |
639 | /* Next HI fixup. */ |
640 | struct mips_hi_fixup *next; | |
641 | /* This fixup. */ | |
642 | fixS *fixp; | |
643 | /* The section this fixup is in. */ | |
644 | segT seg; | |
645 | }; | |
646 | ||
647 | /* The list of unmatched HI relocs. */ | |
648 | ||
649 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
650 | ||
64bdfcaf RS |
651 | /* The frag containing the last explicit relocation operator. |
652 | Null if explicit relocations have not been used. */ | |
653 | ||
654 | static fragS *prev_reloc_op_frag; | |
655 | ||
252b5132 RH |
656 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
657 | ||
658 | #define X ILLEGAL_REG | |
e972090a NC |
659 | static const int mips32_to_16_reg_map[] = |
660 | { | |
252b5132 RH |
661 | X, X, 2, 3, 4, 5, 6, 7, |
662 | X, X, X, X, X, X, X, X, | |
663 | 0, 1, X, X, X, X, X, X, | |
664 | X, X, X, X, X, X, X, X | |
665 | }; | |
666 | #undef X | |
667 | ||
668 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
669 | ||
e972090a NC |
670 | static const unsigned int mips16_to_32_reg_map[] = |
671 | { | |
252b5132 RH |
672 | 16, 17, 2, 3, 4, 5, 6, 7 |
673 | }; | |
60b63b72 | 674 | |
71400594 RS |
675 | /* Classifies the kind of instructions we're interested in when |
676 | implementing -mfix-vr4120. */ | |
677 | enum fix_vr4120_class { | |
678 | FIX_VR4120_MACC, | |
679 | FIX_VR4120_DMACC, | |
680 | FIX_VR4120_MULT, | |
681 | FIX_VR4120_DMULT, | |
682 | FIX_VR4120_DIV, | |
683 | FIX_VR4120_MTHILO, | |
684 | NUM_FIX_VR4120_CLASSES | |
685 | }; | |
686 | ||
687 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
688 | there must be at least one other instruction between an instruction | |
689 | of type X and an instruction of type Y. */ | |
690 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
691 | ||
692 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 693 | static int mips_fix_vr4120; |
4a6a3df4 | 694 | |
7d8e00cf RS |
695 | /* ...likewise -mfix-vr4130. */ |
696 | static int mips_fix_vr4130; | |
697 | ||
4a6a3df4 AO |
698 | /* We don't relax branches by default, since this causes us to expand |
699 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
700 | fail to compute the offset before expanding the macro to the most | |
701 | efficient expansion. */ | |
702 | ||
703 | static int mips_relax_branch; | |
252b5132 | 704 | \f |
4d7206a2 RS |
705 | /* The expansion of many macros depends on the type of symbol that |
706 | they refer to. For example, when generating position-dependent code, | |
707 | a macro that refers to a symbol may have two different expansions, | |
708 | one which uses GP-relative addresses and one which uses absolute | |
709 | addresses. When generating SVR4-style PIC, a macro may have | |
710 | different expansions for local and global symbols. | |
711 | ||
712 | We handle these situations by generating both sequences and putting | |
713 | them in variant frags. In position-dependent code, the first sequence | |
714 | will be the GP-relative one and the second sequence will be the | |
715 | absolute one. In SVR4 PIC, the first sequence will be for global | |
716 | symbols and the second will be for local symbols. | |
717 | ||
584892a6 RS |
718 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
719 | SECOND are the lengths of the two sequences in bytes. These fields | |
720 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
721 | the subtype has the following flags: | |
4d7206a2 | 722 | |
584892a6 RS |
723 | RELAX_USE_SECOND |
724 | Set if it has been decided that we should use the second | |
725 | sequence instead of the first. | |
726 | ||
727 | RELAX_SECOND_LONGER | |
728 | Set in the first variant frag if the macro's second implementation | |
729 | is longer than its first. This refers to the macro as a whole, | |
730 | not an individual relaxation. | |
731 | ||
732 | RELAX_NOMACRO | |
733 | Set in the first variant frag if the macro appeared in a .set nomacro | |
734 | block and if one alternative requires a warning but the other does not. | |
735 | ||
736 | RELAX_DELAY_SLOT | |
737 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
738 | delay slot. | |
4d7206a2 RS |
739 | |
740 | The frag's "opcode" points to the first fixup for relaxable code. | |
741 | ||
742 | Relaxable macros are generated using a sequence such as: | |
743 | ||
744 | relax_start (SYMBOL); | |
745 | ... generate first expansion ... | |
746 | relax_switch (); | |
747 | ... generate second expansion ... | |
748 | relax_end (); | |
749 | ||
750 | The code and fixups for the unwanted alternative are discarded | |
751 | by md_convert_frag. */ | |
584892a6 | 752 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 753 | |
584892a6 RS |
754 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
755 | #define RELAX_SECOND(X) ((X) & 0xff) | |
756 | #define RELAX_USE_SECOND 0x10000 | |
757 | #define RELAX_SECOND_LONGER 0x20000 | |
758 | #define RELAX_NOMACRO 0x40000 | |
759 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 760 | |
4a6a3df4 AO |
761 | /* Branch without likely bit. If label is out of range, we turn: |
762 | ||
763 | beq reg1, reg2, label | |
764 | delay slot | |
765 | ||
766 | into | |
767 | ||
768 | bne reg1, reg2, 0f | |
769 | nop | |
770 | j label | |
771 | 0: delay slot | |
772 | ||
773 | with the following opcode replacements: | |
774 | ||
775 | beq <-> bne | |
776 | blez <-> bgtz | |
777 | bltz <-> bgez | |
778 | bc1f <-> bc1t | |
779 | ||
780 | bltzal <-> bgezal (with jal label instead of j label) | |
781 | ||
782 | Even though keeping the delay slot instruction in the delay slot of | |
783 | the branch would be more efficient, it would be very tricky to do | |
784 | correctly, because we'd have to introduce a variable frag *after* | |
785 | the delay slot instruction, and expand that instead. Let's do it | |
786 | the easy way for now, even if the branch-not-taken case now costs | |
787 | one additional instruction. Out-of-range branches are not supposed | |
788 | to be common, anyway. | |
789 | ||
790 | Branch likely. If label is out of range, we turn: | |
791 | ||
792 | beql reg1, reg2, label | |
793 | delay slot (annulled if branch not taken) | |
794 | ||
795 | into | |
796 | ||
797 | beql reg1, reg2, 1f | |
798 | nop | |
799 | beql $0, $0, 2f | |
800 | nop | |
801 | 1: j[al] label | |
802 | delay slot (executed only if branch taken) | |
803 | 2: | |
804 | ||
805 | It would be possible to generate a shorter sequence by losing the | |
806 | likely bit, generating something like: | |
b34976b6 | 807 | |
4a6a3df4 AO |
808 | bne reg1, reg2, 0f |
809 | nop | |
810 | j[al] label | |
811 | delay slot (executed only if branch taken) | |
812 | 0: | |
813 | ||
814 | beql -> bne | |
815 | bnel -> beq | |
816 | blezl -> bgtz | |
817 | bgtzl -> blez | |
818 | bltzl -> bgez | |
819 | bgezl -> bltz | |
820 | bc1fl -> bc1t | |
821 | bc1tl -> bc1f | |
822 | ||
823 | bltzall -> bgezal (with jal label instead of j label) | |
824 | bgezall -> bltzal (ditto) | |
825 | ||
826 | ||
827 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 828 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
829 | ((relax_substateT) \ |
830 | (0xc0000000 \ | |
831 | | ((toofar) ? 1 : 0) \ | |
832 | | ((link) ? 2 : 0) \ | |
833 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 834 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 835 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
836 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
837 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
838 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 839 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 840 | |
252b5132 RH |
841 | /* For mips16 code, we use an entirely different form of relaxation. |
842 | mips16 supports two versions of most instructions which take | |
843 | immediate values: a small one which takes some small value, and a | |
844 | larger one which takes a 16 bit value. Since branches also follow | |
845 | this pattern, relaxing these values is required. | |
846 | ||
847 | We can assemble both mips16 and normal MIPS code in a single | |
848 | object. Therefore, we need to support this type of relaxation at | |
849 | the same time that we support the relaxation described above. We | |
850 | use the high bit of the subtype field to distinguish these cases. | |
851 | ||
852 | The information we store for this type of relaxation is the | |
853 | argument code found in the opcode file for this relocation, whether | |
854 | the user explicitly requested a small or extended form, and whether | |
855 | the relocation is in a jump or jal delay slot. That tells us the | |
856 | size of the value, and how it should be stored. We also store | |
857 | whether the fragment is considered to be extended or not. We also | |
858 | store whether this is known to be a branch to a different section, | |
859 | whether we have tried to relax this frag yet, and whether we have | |
860 | ever extended a PC relative fragment because of a shift count. */ | |
861 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
862 | (0x80000000 \ | |
863 | | ((type) & 0xff) \ | |
864 | | ((small) ? 0x100 : 0) \ | |
865 | | ((ext) ? 0x200 : 0) \ | |
866 | | ((dslot) ? 0x400 : 0) \ | |
867 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 868 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
869 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
870 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
871 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
872 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
873 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
874 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
875 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
876 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
877 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
878 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
879 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
880 | |
881 | /* Is the given value a sign-extended 32-bit value? */ | |
882 | #define IS_SEXT_32BIT_NUM(x) \ | |
883 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
884 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
885 | ||
886 | /* Is the given value a sign-extended 16-bit value? */ | |
887 | #define IS_SEXT_16BIT_NUM(x) \ | |
888 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
889 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
890 | ||
2051e8c4 MR |
891 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
892 | #define IS_ZEXT_32BIT_NUM(x) \ | |
893 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
894 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
895 | ||
bf12938e RS |
896 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
897 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
898 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
899 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
900 | | (((VALUE) & (MASK)) << (SHIFT))) | |
901 | ||
902 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
903 | SHIFT places. */ | |
904 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
905 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
906 | ||
907 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
908 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
909 | ||
910 | include/opcode/mips.h specifies operand fields using the macros | |
911 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
912 | with "MIPS16OP" instead of "OP". */ | |
913 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
914 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
915 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
916 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
917 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
918 | ||
919 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
920 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
921 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
922 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
923 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
924 | MIPS16OP_MASK_##FIELD, \ | |
925 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
926 | \f |
927 | /* Global variables used when generating relaxable macros. See the | |
928 | comment above RELAX_ENCODE for more details about how relaxation | |
929 | is used. */ | |
930 | static struct { | |
931 | /* 0 if we're not emitting a relaxable macro. | |
932 | 1 if we're emitting the first of the two relaxation alternatives. | |
933 | 2 if we're emitting the second alternative. */ | |
934 | int sequence; | |
935 | ||
936 | /* The first relaxable fixup in the current frag. (In other words, | |
937 | the first fixup that refers to relaxable code.) */ | |
938 | fixS *first_fixup; | |
939 | ||
940 | /* sizes[0] says how many bytes of the first alternative are stored in | |
941 | the current frag. Likewise sizes[1] for the second alternative. */ | |
942 | unsigned int sizes[2]; | |
943 | ||
944 | /* The symbol on which the choice of sequence depends. */ | |
945 | symbolS *symbol; | |
946 | } mips_relax; | |
252b5132 | 947 | \f |
584892a6 RS |
948 | /* Global variables used to decide whether a macro needs a warning. */ |
949 | static struct { | |
950 | /* True if the macro is in a branch delay slot. */ | |
951 | bfd_boolean delay_slot_p; | |
952 | ||
953 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
954 | in bytes and sizes[1] is the length of the second alternative. | |
955 | For non-relaxable macros, both elements give the length of the | |
956 | macro in bytes. */ | |
957 | unsigned int sizes[2]; | |
958 | ||
959 | /* The first variant frag for this macro. */ | |
960 | fragS *first_frag; | |
961 | } mips_macro_warning; | |
962 | \f | |
252b5132 RH |
963 | /* Prototypes for static functions. */ |
964 | ||
17a2f251 | 965 | #define internalError() \ |
252b5132 | 966 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
967 | |
968 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
969 | ||
b34976b6 | 970 | static void append_insn |
4d7206a2 | 971 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 972 | static void mips_no_prev_insn (void); |
b34976b6 | 973 | static void mips16_macro_build |
67c0d1eb RS |
974 | (expressionS *, const char *, const char *, va_list); |
975 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
976 | static void macro_start (void); |
977 | static void macro_end (void); | |
17a2f251 TS |
978 | static void macro (struct mips_cl_insn * ip); |
979 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 980 | #ifdef LOSING_COMPILER |
17a2f251 | 981 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 982 | #endif |
17a2f251 TS |
983 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
984 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 985 | static void mips16_immed |
17a2f251 TS |
986 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
987 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 988 | static size_t my_getSmallExpression |
17a2f251 TS |
989 | (expressionS *, bfd_reloc_code_real_type *, char *); |
990 | static void my_getExpression (expressionS *, char *); | |
991 | static void s_align (int); | |
992 | static void s_change_sec (int); | |
993 | static void s_change_section (int); | |
994 | static void s_cons (int); | |
995 | static void s_float_cons (int); | |
996 | static void s_mips_globl (int); | |
997 | static void s_option (int); | |
998 | static void s_mipsset (int); | |
999 | static void s_abicalls (int); | |
1000 | static void s_cpload (int); | |
1001 | static void s_cpsetup (int); | |
1002 | static void s_cplocal (int); | |
1003 | static void s_cprestore (int); | |
1004 | static void s_cpreturn (int); | |
1005 | static void s_gpvalue (int); | |
1006 | static void s_gpword (int); | |
1007 | static void s_gpdword (int); | |
1008 | static void s_cpadd (int); | |
1009 | static void s_insn (int); | |
1010 | static void md_obj_begin (void); | |
1011 | static void md_obj_end (void); | |
1012 | static void s_mips_ent (int); | |
1013 | static void s_mips_end (int); | |
1014 | static void s_mips_frame (int); | |
1015 | static void s_mips_mask (int reg_type); | |
1016 | static void s_mips_stab (int); | |
1017 | static void s_mips_weakext (int); | |
1018 | static void s_mips_file (int); | |
1019 | static void s_mips_loc (int); | |
1020 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1021 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1022 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1023 | |
1024 | /* Table and functions used to map between CPU/ISA names, and | |
1025 | ISA levels, and CPU numbers. */ | |
1026 | ||
e972090a NC |
1027 | struct mips_cpu_info |
1028 | { | |
e7af610e NC |
1029 | const char *name; /* CPU or ISA name. */ |
1030 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
1031 | int isa; /* ISA level. */ | |
1032 | int cpu; /* CPU number (default CPU if ISA). */ | |
1033 | }; | |
1034 | ||
17a2f251 TS |
1035 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1036 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1037 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1038 | \f |
1039 | /* Pseudo-op table. | |
1040 | ||
1041 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1042 | should be defined here, but are currently unsupported: .alias, | |
1043 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1044 | ||
1045 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1046 | specific to the type of debugging information being generated, and | |
1047 | should be defined by the object format: .aent, .begin, .bend, | |
1048 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1049 | .vreg. | |
1050 | ||
1051 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1052 | not MIPS CPU specific, but are also not specific to the object file | |
1053 | format. This file is probably the best place to define them, but | |
1054 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1055 | .struct. */ | |
1056 | ||
e972090a NC |
1057 | static const pseudo_typeS mips_pseudo_table[] = |
1058 | { | |
beae10d5 | 1059 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1060 | {"option", s_option, 0}, |
1061 | {"set", s_mipsset, 0}, | |
1062 | {"rdata", s_change_sec, 'r'}, | |
1063 | {"sdata", s_change_sec, 's'}, | |
1064 | {"livereg", s_ignore, 0}, | |
1065 | {"abicalls", s_abicalls, 0}, | |
1066 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1067 | {"cpsetup", s_cpsetup, 0}, |
1068 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1069 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1070 | {"cpreturn", s_cpreturn, 0}, |
1071 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1072 | {"gpword", s_gpword, 0}, |
10181a0d | 1073 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1074 | {"cpadd", s_cpadd, 0}, |
1075 | {"insn", s_insn, 0}, | |
1076 | ||
beae10d5 | 1077 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1078 | chips. */ |
1079 | {"asciiz", stringer, 1}, | |
1080 | {"bss", s_change_sec, 'b'}, | |
1081 | {"err", s_err, 0}, | |
1082 | {"half", s_cons, 1}, | |
1083 | {"dword", s_cons, 3}, | |
1084 | {"weakext", s_mips_weakext, 0}, | |
1085 | ||
beae10d5 | 1086 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1087 | here for one reason or another. */ |
1088 | {"align", s_align, 0}, | |
1089 | {"byte", s_cons, 0}, | |
1090 | {"data", s_change_sec, 'd'}, | |
1091 | {"double", s_float_cons, 'd'}, | |
1092 | {"float", s_float_cons, 'f'}, | |
1093 | {"globl", s_mips_globl, 0}, | |
1094 | {"global", s_mips_globl, 0}, | |
1095 | {"hword", s_cons, 1}, | |
1096 | {"int", s_cons, 2}, | |
1097 | {"long", s_cons, 2}, | |
1098 | {"octa", s_cons, 4}, | |
1099 | {"quad", s_cons, 3}, | |
cca86cc8 | 1100 | {"section", s_change_section, 0}, |
252b5132 RH |
1101 | {"short", s_cons, 1}, |
1102 | {"single", s_float_cons, 'f'}, | |
1103 | {"stabn", s_mips_stab, 'n'}, | |
1104 | {"text", s_change_sec, 't'}, | |
1105 | {"word", s_cons, 2}, | |
add56521 | 1106 | |
add56521 | 1107 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1108 | |
43841e91 | 1109 | { NULL, NULL, 0 }, |
252b5132 RH |
1110 | }; |
1111 | ||
e972090a NC |
1112 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1113 | { | |
beae10d5 KH |
1114 | /* These pseudo-ops should be defined by the object file format. |
1115 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1116 | {"aent", s_mips_ent, 1}, |
1117 | {"bgnb", s_ignore, 0}, | |
1118 | {"end", s_mips_end, 0}, | |
1119 | {"endb", s_ignore, 0}, | |
1120 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1121 | {"file", s_mips_file, 0}, |
252b5132 RH |
1122 | {"fmask", s_mips_mask, 'F'}, |
1123 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1124 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1125 | {"mask", s_mips_mask, 'R'}, |
1126 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1127 | { NULL, NULL, 0 }, |
252b5132 RH |
1128 | }; |
1129 | ||
17a2f251 | 1130 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1131 | |
1132 | void | |
17a2f251 | 1133 | mips_pop_insert (void) |
252b5132 RH |
1134 | { |
1135 | pop_insert (mips_pseudo_table); | |
1136 | if (! ECOFF_DEBUGGING) | |
1137 | pop_insert (mips_nonecoff_pseudo_table); | |
1138 | } | |
1139 | \f | |
1140 | /* Symbols labelling the current insn. */ | |
1141 | ||
e972090a NC |
1142 | struct insn_label_list |
1143 | { | |
252b5132 RH |
1144 | struct insn_label_list *next; |
1145 | symbolS *label; | |
1146 | }; | |
1147 | ||
1148 | static struct insn_label_list *insn_labels; | |
1149 | static struct insn_label_list *free_insn_labels; | |
1150 | ||
17a2f251 | 1151 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1152 | |
1153 | static inline void | |
17a2f251 | 1154 | mips_clear_insn_labels (void) |
252b5132 RH |
1155 | { |
1156 | register struct insn_label_list **pl; | |
1157 | ||
1158 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1159 | ; | |
1160 | *pl = insn_labels; | |
1161 | insn_labels = NULL; | |
1162 | } | |
1163 | \f | |
1164 | static char *expr_end; | |
1165 | ||
1166 | /* Expressions which appear in instructions. These are set by | |
1167 | mips_ip. */ | |
1168 | ||
1169 | static expressionS imm_expr; | |
5f74bc13 | 1170 | static expressionS imm2_expr; |
252b5132 RH |
1171 | static expressionS offset_expr; |
1172 | ||
1173 | /* Relocs associated with imm_expr and offset_expr. */ | |
1174 | ||
f6688943 TS |
1175 | static bfd_reloc_code_real_type imm_reloc[3] |
1176 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1177 | static bfd_reloc_code_real_type offset_reloc[3] | |
1178 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1179 | |
252b5132 RH |
1180 | /* These are set by mips16_ip if an explicit extension is used. */ |
1181 | ||
b34976b6 | 1182 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1183 | |
7ed4a06a | 1184 | #ifdef OBJ_ELF |
ecb4347a DJ |
1185 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1186 | ECOFF debugging. */ | |
252b5132 RH |
1187 | |
1188 | static segT pdr_seg; | |
7ed4a06a | 1189 | #endif |
252b5132 | 1190 | |
e013f690 TS |
1191 | /* The default target format to use. */ |
1192 | ||
1193 | const char * | |
17a2f251 | 1194 | mips_target_format (void) |
e013f690 TS |
1195 | { |
1196 | switch (OUTPUT_FLAVOR) | |
1197 | { | |
e013f690 TS |
1198 | case bfd_target_ecoff_flavour: |
1199 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1200 | case bfd_target_coff_flavour: | |
1201 | return "pe-mips"; | |
1202 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1203 | #ifdef TE_VXWORKS |
1204 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1205 | return (target_big_endian | |
1206 | ? "elf32-bigmips-vxworks" | |
1207 | : "elf32-littlemips-vxworks"); | |
1208 | #endif | |
e013f690 | 1209 | #ifdef TE_TMIPS |
cfe86eaa | 1210 | /* This is traditional mips. */ |
e013f690 | 1211 | return (target_big_endian |
cfe86eaa TS |
1212 | ? (HAVE_64BIT_OBJECTS |
1213 | ? "elf64-tradbigmips" | |
1214 | : (HAVE_NEWABI | |
1215 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1216 | : (HAVE_64BIT_OBJECTS | |
1217 | ? "elf64-tradlittlemips" | |
1218 | : (HAVE_NEWABI | |
1219 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1220 | #else |
1221 | return (target_big_endian | |
cfe86eaa TS |
1222 | ? (HAVE_64BIT_OBJECTS |
1223 | ? "elf64-bigmips" | |
1224 | : (HAVE_NEWABI | |
1225 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1226 | : (HAVE_64BIT_OBJECTS | |
1227 | ? "elf64-littlemips" | |
1228 | : (HAVE_NEWABI | |
1229 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1230 | #endif |
1231 | default: | |
1232 | abort (); | |
1233 | return NULL; | |
1234 | } | |
1235 | } | |
1236 | ||
1e915849 RS |
1237 | /* Return the length of instruction INSN. */ |
1238 | ||
1239 | static inline unsigned int | |
1240 | insn_length (const struct mips_cl_insn *insn) | |
1241 | { | |
1242 | if (!mips_opts.mips16) | |
1243 | return 4; | |
1244 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1245 | } | |
1246 | ||
1247 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1248 | ||
1249 | static void | |
1250 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1251 | { | |
1252 | size_t i; | |
1253 | ||
1254 | insn->insn_mo = mo; | |
1255 | insn->use_extend = FALSE; | |
1256 | insn->extend = 0; | |
1257 | insn->insn_opcode = mo->match; | |
1258 | insn->frag = NULL; | |
1259 | insn->where = 0; | |
1260 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1261 | insn->fixp[i] = NULL; | |
1262 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1263 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1264 | insn->mips16_absolute_jump_p = 0; | |
1265 | } | |
1266 | ||
1267 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1268 | ||
1269 | static void | |
1270 | install_insn (const struct mips_cl_insn *insn) | |
1271 | { | |
1272 | char *f = insn->frag->fr_literal + insn->where; | |
1273 | if (!mips_opts.mips16) | |
1274 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1275 | else if (insn->mips16_absolute_jump_p) | |
1276 | { | |
1277 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1278 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1279 | } | |
1280 | else | |
1281 | { | |
1282 | if (insn->use_extend) | |
1283 | { | |
1284 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1285 | f += 2; | |
1286 | } | |
1287 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1292 | and install the opcode in the new location. */ | |
1293 | ||
1294 | static void | |
1295 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1296 | { | |
1297 | size_t i; | |
1298 | ||
1299 | insn->frag = frag; | |
1300 | insn->where = where; | |
1301 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1302 | if (insn->fixp[i] != NULL) | |
1303 | { | |
1304 | insn->fixp[i]->fx_frag = frag; | |
1305 | insn->fixp[i]->fx_where = where; | |
1306 | } | |
1307 | install_insn (insn); | |
1308 | } | |
1309 | ||
1310 | /* Add INSN to the end of the output. */ | |
1311 | ||
1312 | static void | |
1313 | add_fixed_insn (struct mips_cl_insn *insn) | |
1314 | { | |
1315 | char *f = frag_more (insn_length (insn)); | |
1316 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1317 | } | |
1318 | ||
1319 | /* Start a variant frag and move INSN to the start of the variant part, | |
1320 | marking it as fixed. The other arguments are as for frag_var. */ | |
1321 | ||
1322 | static void | |
1323 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1324 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1325 | { | |
1326 | frag_grow (max_chars); | |
1327 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1328 | insn->fixed_p = 1; | |
1329 | frag_var (rs_machine_dependent, max_chars, var, | |
1330 | subtype, symbol, offset, NULL); | |
1331 | } | |
1332 | ||
1333 | /* Insert N copies of INSN into the history buffer, starting at | |
1334 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1335 | ||
1336 | static void | |
1337 | insert_into_history (unsigned int first, unsigned int n, | |
1338 | const struct mips_cl_insn *insn) | |
1339 | { | |
1340 | if (mips_relax.sequence != 2) | |
1341 | { | |
1342 | unsigned int i; | |
1343 | ||
1344 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1345 | if (i >= first + n) | |
1346 | history[i] = history[i - n]; | |
1347 | else | |
1348 | history[i] = *insn; | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1353 | ||
1354 | static void | |
1355 | emit_nop (void) | |
1356 | { | |
1357 | add_fixed_insn (NOP_INSN); | |
1358 | insert_into_history (0, 1, NOP_INSN); | |
1359 | } | |
1360 | ||
71400594 RS |
1361 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1362 | the idea is to make it obvious at a glance that each errata is | |
1363 | included. */ | |
1364 | ||
1365 | static void | |
1366 | init_vr4120_conflicts (void) | |
1367 | { | |
1368 | #define CONFLICT(FIRST, SECOND) \ | |
1369 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1370 | ||
1371 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1372 | CONFLICT (MACC, DIV); | |
1373 | CONFLICT (DMACC, DIV); | |
1374 | ||
1375 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1376 | CONFLICT (DMULT, DMULT); | |
1377 | CONFLICT (DMULT, DMACC); | |
1378 | CONFLICT (DMACC, DMULT); | |
1379 | CONFLICT (DMACC, DMACC); | |
1380 | ||
1381 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1382 | CONFLICT (MACC, MTHILO); | |
1383 | CONFLICT (DMACC, MTHILO); | |
1384 | ||
1385 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1386 | instruction is executed immediately after a MACC or DMACC | |
1387 | instruction, the result of [either instruction] is incorrect." */ | |
1388 | CONFLICT (MACC, MULT); | |
1389 | CONFLICT (MACC, DMULT); | |
1390 | CONFLICT (DMACC, MULT); | |
1391 | CONFLICT (DMACC, DMULT); | |
1392 | ||
1393 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1394 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1395 | DDIV or DDIVU instruction, the result of the MACC or | |
1396 | DMACC instruction is incorrect.". */ | |
1397 | CONFLICT (DMULT, MACC); | |
1398 | CONFLICT (DMULT, DMACC); | |
1399 | CONFLICT (DIV, MACC); | |
1400 | CONFLICT (DIV, DMACC); | |
1401 | ||
1402 | #undef CONFLICT | |
1403 | } | |
1404 | ||
156c2f8b NC |
1405 | /* This function is called once, at assembler startup time. It should |
1406 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1407 | ||
252b5132 | 1408 | void |
17a2f251 | 1409 | md_begin (void) |
252b5132 | 1410 | { |
252b5132 | 1411 | register const char *retval = NULL; |
156c2f8b | 1412 | int i = 0; |
252b5132 | 1413 | int broken = 0; |
1f25f5d3 | 1414 | |
0a44bf69 RS |
1415 | if (mips_pic != NO_PIC) |
1416 | { | |
1417 | if (g_switch_seen && g_switch_value != 0) | |
1418 | as_bad (_("-G may not be used in position-independent code")); | |
1419 | g_switch_value = 0; | |
1420 | } | |
1421 | ||
fef14a42 | 1422 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1423 | as_warn (_("Could not set architecture and machine")); |
1424 | ||
252b5132 RH |
1425 | op_hash = hash_new (); |
1426 | ||
1427 | for (i = 0; i < NUMOPCODES;) | |
1428 | { | |
1429 | const char *name = mips_opcodes[i].name; | |
1430 | ||
17a2f251 | 1431 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1432 | if (retval != NULL) |
1433 | { | |
1434 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1435 | mips_opcodes[i].name, retval); | |
1436 | /* Probably a memory allocation problem? Give up now. */ | |
1437 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1438 | } | |
1439 | do | |
1440 | { | |
1441 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1442 | { | |
1443 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1444 | broken = 1; | |
1e915849 RS |
1445 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1446 | { | |
1447 | create_insn (&nop_insn, mips_opcodes + i); | |
1448 | nop_insn.fixed_p = 1; | |
1449 | } | |
252b5132 RH |
1450 | } |
1451 | ++i; | |
1452 | } | |
1453 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1454 | } | |
1455 | ||
1456 | mips16_op_hash = hash_new (); | |
1457 | ||
1458 | i = 0; | |
1459 | while (i < bfd_mips16_num_opcodes) | |
1460 | { | |
1461 | const char *name = mips16_opcodes[i].name; | |
1462 | ||
17a2f251 | 1463 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1464 | if (retval != NULL) |
1465 | as_fatal (_("internal: can't hash `%s': %s"), | |
1466 | mips16_opcodes[i].name, retval); | |
1467 | do | |
1468 | { | |
1469 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1470 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1471 | != mips16_opcodes[i].match)) | |
1472 | { | |
1473 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1474 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1475 | broken = 1; | |
1476 | } | |
1e915849 RS |
1477 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1478 | { | |
1479 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1480 | mips16_nop_insn.fixed_p = 1; | |
1481 | } | |
252b5132 RH |
1482 | ++i; |
1483 | } | |
1484 | while (i < bfd_mips16_num_opcodes | |
1485 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1486 | } | |
1487 | ||
1488 | if (broken) | |
1489 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1490 | ||
1491 | /* We add all the general register names to the symbol table. This | |
1492 | helps us detect invalid uses of them. */ | |
1493 | for (i = 0; i < 32; i++) | |
1494 | { | |
1495 | char buf[5]; | |
1496 | ||
1497 | sprintf (buf, "$%d", i); | |
1498 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1499 | &zero_address_frag)); | |
1500 | } | |
76db943d TS |
1501 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1502 | &zero_address_frag)); | |
252b5132 RH |
1503 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1504 | &zero_address_frag)); | |
1505 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1506 | &zero_address_frag)); | |
1507 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1508 | &zero_address_frag)); | |
1509 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1510 | &zero_address_frag)); | |
1511 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1512 | &zero_address_frag)); | |
1513 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1514 | &zero_address_frag)); | |
85b51719 TS |
1515 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1516 | &zero_address_frag)); | |
252b5132 RH |
1517 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1518 | &zero_address_frag)); | |
1519 | ||
6047c971 AO |
1520 | /* If we don't add these register names to the symbol table, they |
1521 | may end up being added as regular symbols by operand(), and then | |
1522 | make it to the object file as undefined in case they're not | |
1523 | regarded as local symbols. They're local in o32, since `$' is a | |
1524 | local symbol prefix, but not in n32 or n64. */ | |
1525 | for (i = 0; i < 8; i++) | |
1526 | { | |
1527 | char buf[6]; | |
1528 | ||
1529 | sprintf (buf, "$fcc%i", i); | |
1530 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1531 | &zero_address_frag)); | |
1532 | } | |
1533 | ||
7d10b47d | 1534 | mips_no_prev_insn (); |
252b5132 RH |
1535 | |
1536 | mips_gprmask = 0; | |
1537 | mips_cprmask[0] = 0; | |
1538 | mips_cprmask[1] = 0; | |
1539 | mips_cprmask[2] = 0; | |
1540 | mips_cprmask[3] = 0; | |
1541 | ||
1542 | /* set the default alignment for the text section (2**2) */ | |
1543 | record_alignment (text_section, 2); | |
1544 | ||
4d0d148d | 1545 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1546 | |
1547 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1548 | { | |
0a44bf69 RS |
1549 | /* On a native system other than VxWorks, sections must be aligned |
1550 | to 16 byte boundaries. When configured for an embedded ELF | |
1551 | target, we don't bother. */ | |
1552 | if (strcmp (TARGET_OS, "elf") != 0 | |
1553 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1554 | { |
1555 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1556 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1557 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1558 | } | |
1559 | ||
1560 | /* Create a .reginfo section for register masks and a .mdebug | |
1561 | section for debugging information. */ | |
1562 | { | |
1563 | segT seg; | |
1564 | subsegT subseg; | |
1565 | flagword flags; | |
1566 | segT sec; | |
1567 | ||
1568 | seg = now_seg; | |
1569 | subseg = now_subseg; | |
1570 | ||
1571 | /* The ABI says this section should be loaded so that the | |
1572 | running program can access it. However, we don't load it | |
1573 | if we are configured for an embedded target */ | |
1574 | flags = SEC_READONLY | SEC_DATA; | |
1575 | if (strcmp (TARGET_OS, "elf") != 0) | |
1576 | flags |= SEC_ALLOC | SEC_LOAD; | |
1577 | ||
316f5878 | 1578 | if (mips_abi != N64_ABI) |
252b5132 RH |
1579 | { |
1580 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1581 | ||
195325d2 TS |
1582 | bfd_set_section_flags (stdoutput, sec, flags); |
1583 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1584 | |
252b5132 RH |
1585 | #ifdef OBJ_ELF |
1586 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1587 | #endif | |
1588 | } | |
1589 | else | |
1590 | { | |
1591 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1592 | .reginfo section. */ | |
1593 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1594 | bfd_set_section_flags (stdoutput, sec, flags); |
1595 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1596 | |
1597 | #ifdef OBJ_ELF | |
1598 | /* Set up the option header. */ | |
1599 | { | |
1600 | Elf_Internal_Options opthdr; | |
1601 | char *f; | |
1602 | ||
1603 | opthdr.kind = ODK_REGINFO; | |
1604 | opthdr.size = (sizeof (Elf_External_Options) | |
1605 | + sizeof (Elf64_External_RegInfo)); | |
1606 | opthdr.section = 0; | |
1607 | opthdr.info = 0; | |
1608 | f = frag_more (sizeof (Elf_External_Options)); | |
1609 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1610 | (Elf_External_Options *) f); | |
1611 | ||
1612 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1613 | } | |
1614 | #endif | |
1615 | } | |
1616 | ||
1617 | if (ECOFF_DEBUGGING) | |
1618 | { | |
1619 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1620 | (void) bfd_set_section_flags (stdoutput, sec, | |
1621 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1622 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1623 | } | |
ecb4347a | 1624 | #ifdef OBJ_ELF |
dcd410fe | 1625 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1626 | { |
1627 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1628 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1629 | SEC_READONLY | SEC_RELOC | |
1630 | | SEC_DEBUGGING); | |
1631 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1632 | } | |
252b5132 RH |
1633 | #endif |
1634 | ||
1635 | subseg_set (seg, subseg); | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | if (! ECOFF_DEBUGGING) | |
1640 | md_obj_begin (); | |
71400594 RS |
1641 | |
1642 | if (mips_fix_vr4120) | |
1643 | init_vr4120_conflicts (); | |
252b5132 RH |
1644 | } |
1645 | ||
1646 | void | |
17a2f251 | 1647 | md_mips_end (void) |
252b5132 RH |
1648 | { |
1649 | if (! ECOFF_DEBUGGING) | |
1650 | md_obj_end (); | |
1651 | } | |
1652 | ||
1653 | void | |
17a2f251 | 1654 | md_assemble (char *str) |
252b5132 RH |
1655 | { |
1656 | struct mips_cl_insn insn; | |
f6688943 TS |
1657 | bfd_reloc_code_real_type unused_reloc[3] |
1658 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1659 | |
1660 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1661 | imm2_expr.X_op = O_absent; |
252b5132 | 1662 | offset_expr.X_op = O_absent; |
f6688943 TS |
1663 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1664 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1665 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1666 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1667 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1668 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1669 | |
1670 | if (mips_opts.mips16) | |
1671 | mips16_ip (str, &insn); | |
1672 | else | |
1673 | { | |
1674 | mips_ip (str, &insn); | |
beae10d5 KH |
1675 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1676 | str, insn.insn_opcode)); | |
252b5132 RH |
1677 | } |
1678 | ||
1679 | if (insn_error) | |
1680 | { | |
1681 | as_bad ("%s `%s'", insn_error, str); | |
1682 | return; | |
1683 | } | |
1684 | ||
1685 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1686 | { | |
584892a6 | 1687 | macro_start (); |
252b5132 RH |
1688 | if (mips_opts.mips16) |
1689 | mips16_macro (&insn); | |
1690 | else | |
1691 | macro (&insn); | |
584892a6 | 1692 | macro_end (); |
252b5132 RH |
1693 | } |
1694 | else | |
1695 | { | |
1696 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1697 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1698 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1699 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1700 | else |
4d7206a2 | 1701 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1702 | } |
1703 | } | |
1704 | ||
5919d012 | 1705 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
1706 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
1707 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
1708 | |
1709 | static inline bfd_boolean | |
17a2f251 | 1710 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1711 | { |
3b91255e RS |
1712 | return (HAVE_IN_PLACE_ADDENDS |
1713 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
1714 | || reloc == BFD_RELOC_MIPS16_HI16_S |
1715 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
1716 | all GOT16 relocations evaluate to "G". */ | |
1717 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
1718 | } |
1719 | ||
1720 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1721 | relocation. */ | |
1722 | ||
1723 | static inline bfd_boolean | |
17a2f251 | 1724 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1725 | { |
1726 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1727 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1728 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1729 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1730 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1731 | } | |
1732 | ||
252b5132 RH |
1733 | /* See whether instruction IP reads register REG. CLASS is the type |
1734 | of register. */ | |
1735 | ||
1736 | static int | |
71400594 | 1737 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1738 | enum mips_regclass class) |
252b5132 RH |
1739 | { |
1740 | if (class == MIPS16_REG) | |
1741 | { | |
1742 | assert (mips_opts.mips16); | |
1743 | reg = mips16_to_32_reg_map[reg]; | |
1744 | class = MIPS_GR_REG; | |
1745 | } | |
1746 | ||
85b51719 TS |
1747 | /* Don't report on general register ZERO, since it never changes. */ |
1748 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1749 | return 0; |
1750 | ||
1751 | if (class == MIPS_FP_REG) | |
1752 | { | |
1753 | assert (! mips_opts.mips16); | |
1754 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1755 | This is not optimal, because it will introduce an unnecessary | |
1756 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1757 | need to distinguish reading both $f0 and $f1 or just one of | |
1758 | them. Note that we don't have to check the other way, | |
1759 | because there is no instruction that sets both $f0 and $f1 | |
1760 | and requires a delay. */ | |
1761 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1762 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1763 | == (reg &~ (unsigned) 1))) |
1764 | return 1; | |
1765 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1766 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1767 | == (reg &~ (unsigned) 1))) |
1768 | return 1; | |
1769 | } | |
1770 | else if (! mips_opts.mips16) | |
1771 | { | |
1772 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1773 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1774 | return 1; |
1775 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1776 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1777 | return 1; |
1778 | } | |
1779 | else | |
1780 | { | |
1781 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1782 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1783 | return 1; |
1784 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1785 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1786 | return 1; |
1787 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1788 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1789 | == reg)) |
1790 | return 1; | |
1791 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1792 | return 1; | |
1793 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1794 | return 1; | |
1795 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1796 | return 1; | |
1797 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1798 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1799 | return 1; |
1800 | } | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | /* This function returns true if modifying a register requires a | |
1806 | delay. */ | |
1807 | ||
1808 | static int | |
17a2f251 | 1809 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1810 | { |
1811 | unsigned long prev_pinfo; | |
1812 | ||
47e39b9d | 1813 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1814 | if (! mips_opts.noreorder |
81912461 ILT |
1815 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1816 | && ! gpr_interlocks) | |
1817 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1818 | && ! cop_interlocks))) | |
252b5132 | 1819 | { |
81912461 ILT |
1820 | /* A load from a coprocessor or from memory. All load delays |
1821 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1822 | /* Itbl support may require additional care here. */ |
252b5132 | 1823 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1824 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1825 | return 1; |
1826 | } | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
404a8071 RS |
1831 | /* Move all labels in insn_labels to the current insertion point. */ |
1832 | ||
1833 | static void | |
1834 | mips_move_labels (void) | |
1835 | { | |
1836 | struct insn_label_list *l; | |
1837 | valueT val; | |
1838 | ||
1839 | for (l = insn_labels; l != NULL; l = l->next) | |
1840 | { | |
1841 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1842 | symbol_set_frag (l->label, frag_now); | |
1843 | val = (valueT) frag_now_fix (); | |
1844 | /* mips16 text labels are stored as odd. */ | |
1845 | if (mips_opts.mips16) | |
1846 | ++val; | |
1847 | S_SET_VALUE (l->label, val); | |
1848 | } | |
1849 | } | |
1850 | ||
252b5132 RH |
1851 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1852 | handle them specially, such as generating jalx instructions when | |
1853 | needed. We also make them odd for the duration of the assembly, in | |
1854 | order to generate the right sort of code. We will make them even | |
1855 | in the adjust_symtab routine, while leaving them marked. This is | |
1856 | convenient for the debugger and the disassembler. The linker knows | |
1857 | to make them odd again. */ | |
1858 | ||
1859 | static void | |
17a2f251 | 1860 | mips16_mark_labels (void) |
252b5132 RH |
1861 | { |
1862 | if (mips_opts.mips16) | |
1863 | { | |
1864 | struct insn_label_list *l; | |
98aa84af | 1865 | valueT val; |
252b5132 RH |
1866 | |
1867 | for (l = insn_labels; l != NULL; l = l->next) | |
1868 | { | |
1869 | #ifdef OBJ_ELF | |
1870 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1871 | S_SET_OTHER (l->label, STO_MIPS16); | |
1872 | #endif | |
98aa84af AM |
1873 | val = S_GET_VALUE (l->label); |
1874 | if ((val & 1) == 0) | |
1875 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1876 | } |
1877 | } | |
1878 | } | |
1879 | ||
4d7206a2 RS |
1880 | /* End the current frag. Make it a variant frag and record the |
1881 | relaxation info. */ | |
1882 | ||
1883 | static void | |
1884 | relax_close_frag (void) | |
1885 | { | |
584892a6 | 1886 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1887 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1888 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1889 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1890 | ||
1891 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1892 | mips_relax.first_fixup = 0; | |
1893 | } | |
1894 | ||
1895 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1896 | See the comment above RELAX_ENCODE for more details. */ | |
1897 | ||
1898 | static void | |
1899 | relax_start (symbolS *symbol) | |
1900 | { | |
1901 | assert (mips_relax.sequence == 0); | |
1902 | mips_relax.sequence = 1; | |
1903 | mips_relax.symbol = symbol; | |
1904 | } | |
1905 | ||
1906 | /* Start generating the second version of a relaxable sequence. | |
1907 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1908 | |
1909 | static void | |
4d7206a2 RS |
1910 | relax_switch (void) |
1911 | { | |
1912 | assert (mips_relax.sequence == 1); | |
1913 | mips_relax.sequence = 2; | |
1914 | } | |
1915 | ||
1916 | /* End the current relaxable sequence. */ | |
1917 | ||
1918 | static void | |
1919 | relax_end (void) | |
1920 | { | |
1921 | assert (mips_relax.sequence == 2); | |
1922 | relax_close_frag (); | |
1923 | mips_relax.sequence = 0; | |
1924 | } | |
1925 | ||
71400594 RS |
1926 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1927 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1928 | by VR4120 errata. */ | |
4d7206a2 | 1929 | |
71400594 RS |
1930 | static unsigned int |
1931 | classify_vr4120_insn (const char *name) | |
252b5132 | 1932 | { |
71400594 RS |
1933 | if (strncmp (name, "macc", 4) == 0) |
1934 | return FIX_VR4120_MACC; | |
1935 | if (strncmp (name, "dmacc", 5) == 0) | |
1936 | return FIX_VR4120_DMACC; | |
1937 | if (strncmp (name, "mult", 4) == 0) | |
1938 | return FIX_VR4120_MULT; | |
1939 | if (strncmp (name, "dmult", 5) == 0) | |
1940 | return FIX_VR4120_DMULT; | |
1941 | if (strstr (name, "div")) | |
1942 | return FIX_VR4120_DIV; | |
1943 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1944 | return FIX_VR4120_MTHILO; | |
1945 | return NUM_FIX_VR4120_CLASSES; | |
1946 | } | |
252b5132 | 1947 | |
71400594 RS |
1948 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1949 | where INSN1 is the earlier instruction. Return the worst-case value | |
1950 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1951 | |
71400594 RS |
1952 | static unsigned int |
1953 | insns_between (const struct mips_cl_insn *insn1, | |
1954 | const struct mips_cl_insn *insn2) | |
1955 | { | |
1956 | unsigned long pinfo1, pinfo2; | |
1957 | ||
1958 | /* This function needs to know which pinfo flags are set for INSN2 | |
1959 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1960 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1961 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1962 | pinfo1 = insn1->insn_mo->pinfo; | |
1963 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1964 | |
71400594 RS |
1965 | #define INSN2_USES_REG(REG, CLASS) \ |
1966 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1967 | ||
1968 | /* For most targets, write-after-read dependencies on the HI and LO | |
1969 | registers must be separated by at least two instructions. */ | |
1970 | if (!hilo_interlocks) | |
252b5132 | 1971 | { |
71400594 RS |
1972 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1973 | return 2; | |
1974 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1975 | return 2; | |
1976 | } | |
1977 | ||
1978 | /* If we're working around r7000 errata, there must be two instructions | |
1979 | between an mfhi or mflo and any instruction that uses the result. */ | |
1980 | if (mips_7000_hilo_fix | |
1981 | && MF_HILO_INSN (pinfo1) | |
1982 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1983 | return 2; | |
1984 | ||
1985 | /* If working around VR4120 errata, check for combinations that need | |
1986 | a single intervening instruction. */ | |
1987 | if (mips_fix_vr4120) | |
1988 | { | |
1989 | unsigned int class1, class2; | |
252b5132 | 1990 | |
71400594 RS |
1991 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1992 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1993 | { |
71400594 RS |
1994 | if (insn2 == NULL) |
1995 | return 1; | |
1996 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1997 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1998 | return 1; | |
252b5132 | 1999 | } |
71400594 RS |
2000 | } |
2001 | ||
2002 | if (!mips_opts.mips16) | |
2003 | { | |
2004 | /* Check for GPR or coprocessor load delays. All such delays | |
2005 | are on the RT register. */ | |
2006 | /* Itbl support may require additional care here. */ | |
2007 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2008 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2009 | { |
71400594 RS |
2010 | know (pinfo1 & INSN_WRITE_GPR_T); |
2011 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2012 | return 1; | |
2013 | } | |
2014 | ||
2015 | /* Check for generic coprocessor hazards. | |
2016 | ||
2017 | This case is not handled very well. There is no special | |
2018 | knowledge of CP0 handling, and the coprocessors other than | |
2019 | the floating point unit are not distinguished at all. */ | |
2020 | /* Itbl support may require additional care here. FIXME! | |
2021 | Need to modify this to include knowledge about | |
2022 | user specified delays! */ | |
2023 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2024 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2025 | { | |
2026 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2027 | register. There must be a one instruction delay before INSN2 | |
2028 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2029 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2030 | { |
71400594 RS |
2031 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2032 | return 1; | |
252b5132 | 2033 | } |
71400594 | 2034 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2035 | { |
71400594 RS |
2036 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2037 | return 1; | |
252b5132 RH |
2038 | } |
2039 | else | |
2040 | { | |
71400594 RS |
2041 | /* Read-after-write dependencies on the control registers |
2042 | require a two-instruction gap. */ | |
2043 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2044 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2045 | return 2; | |
2046 | ||
2047 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2048 | also a coprocessor instruction, assume there must be | |
2049 | a one instruction gap. */ | |
2050 | if (pinfo2 & INSN_COP) | |
2051 | return 1; | |
252b5132 RH |
2052 | } |
2053 | } | |
6b76fefe | 2054 | |
71400594 RS |
2055 | /* Check for read-after-write dependencies on the coprocessor |
2056 | control registers in cases where INSN1 does not need a general | |
2057 | coprocessor delay. This means that INSN1 is a floating point | |
2058 | comparison instruction. */ | |
2059 | /* Itbl support may require additional care here. */ | |
2060 | else if (!cop_interlocks | |
2061 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2062 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2063 | return 1; | |
2064 | } | |
6b76fefe | 2065 | |
71400594 | 2066 | #undef INSN2_USES_REG |
6b76fefe | 2067 | |
71400594 RS |
2068 | return 0; |
2069 | } | |
6b76fefe | 2070 | |
7d8e00cf RS |
2071 | /* Return the number of nops that would be needed to work around the |
2072 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2073 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2074 | ||
2075 | static int | |
2076 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2077 | const struct mips_cl_insn *insn) | |
2078 | { | |
2079 | int i, j, reg; | |
2080 | ||
2081 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2082 | are not affected by the errata. */ | |
2083 | if (insn != 0 | |
2084 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2085 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2086 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2087 | return 0; | |
2088 | ||
2089 | /* Search for the first MFLO or MFHI. */ | |
2090 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2091 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2092 | { | |
2093 | /* Extract the destination register. */ | |
2094 | if (mips_opts.mips16) | |
2095 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2096 | else | |
2097 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2098 | ||
2099 | /* No nops are needed if INSN reads that register. */ | |
2100 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2101 | return 0; | |
2102 | ||
2103 | /* ...or if any of the intervening instructions do. */ | |
2104 | for (j = 0; j < i; j++) | |
2105 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2106 | return 0; | |
2107 | ||
2108 | return MAX_VR4130_NOPS - i; | |
2109 | } | |
2110 | return 0; | |
2111 | } | |
2112 | ||
71400594 RS |
2113 | /* Return the number of nops that would be needed if instruction INSN |
2114 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2115 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2116 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2117 | |
71400594 RS |
2118 | static int |
2119 | nops_for_insn (const struct mips_cl_insn *history, | |
2120 | const struct mips_cl_insn *insn) | |
2121 | { | |
2122 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2123 | |
71400594 | 2124 | nops = 0; |
7d8e00cf | 2125 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2126 | if (!history[i].noreorder_p) |
2127 | { | |
2128 | tmp_nops = insns_between (history + i, insn) - i; | |
2129 | if (tmp_nops > nops) | |
2130 | nops = tmp_nops; | |
2131 | } | |
7d8e00cf RS |
2132 | |
2133 | if (mips_fix_vr4130) | |
2134 | { | |
2135 | tmp_nops = nops_for_vr4130 (history, insn); | |
2136 | if (tmp_nops > nops) | |
2137 | nops = tmp_nops; | |
2138 | } | |
2139 | ||
71400594 RS |
2140 | return nops; |
2141 | } | |
252b5132 | 2142 | |
71400594 RS |
2143 | /* The variable arguments provide NUM_INSNS extra instructions that |
2144 | might be added to HISTORY. Return the largest number of nops that | |
2145 | would be needed after the extended sequence. */ | |
252b5132 | 2146 | |
71400594 RS |
2147 | static int |
2148 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2149 | { | |
2150 | va_list args; | |
2151 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2152 | struct mips_cl_insn *cursor; | |
2153 | int nops; | |
2154 | ||
2155 | va_start (args, history); | |
2156 | cursor = buffer + num_insns; | |
2157 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2158 | while (cursor > buffer) | |
2159 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2160 | ||
2161 | nops = nops_for_insn (buffer, NULL); | |
2162 | va_end (args); | |
2163 | return nops; | |
2164 | } | |
252b5132 | 2165 | |
71400594 RS |
2166 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2167 | worst-case delay for the branch target. */ | |
252b5132 | 2168 | |
71400594 RS |
2169 | static int |
2170 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2171 | const struct mips_cl_insn *insn) | |
2172 | { | |
2173 | int nops, tmp_nops; | |
60b63b72 | 2174 | |
71400594 RS |
2175 | nops = nops_for_insn (history, insn); |
2176 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2177 | | INSN_COND_BRANCH_DELAY | |
2178 | | INSN_COND_BRANCH_LIKELY)) | |
2179 | { | |
2180 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2181 | if (tmp_nops > nops) | |
2182 | nops = tmp_nops; | |
2183 | } | |
2184 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2185 | { | |
2186 | tmp_nops = nops_for_sequence (1, history, insn); | |
2187 | if (tmp_nops > nops) | |
2188 | nops = tmp_nops; | |
2189 | } | |
2190 | return nops; | |
2191 | } | |
2192 | ||
2193 | /* Output an instruction. IP is the instruction information. | |
2194 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2195 | RELOC_TYPE. */ | |
2196 | ||
2197 | static void | |
2198 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2199 | bfd_reloc_code_real_type *reloc_type) | |
2200 | { | |
2201 | register unsigned long prev_pinfo, pinfo; | |
2202 | relax_stateT prev_insn_frag_type = 0; | |
2203 | bfd_boolean relaxed_branch = FALSE; | |
2204 | ||
2205 | /* Mark instruction labels in mips16 mode. */ | |
2206 | mips16_mark_labels (); | |
2207 | ||
2208 | prev_pinfo = history[0].insn_mo->pinfo; | |
2209 | pinfo = ip->insn_mo->pinfo; | |
2210 | ||
2211 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2212 | { | |
2213 | /* There are a lot of optimizations we could do that we don't. | |
2214 | In particular, we do not, in general, reorder instructions. | |
2215 | If you use gcc with optimization, it will reorder | |
2216 | instructions and generally do much more optimization then we | |
2217 | do here; repeating all that work in the assembler would only | |
2218 | benefit hand written assembly code, and does not seem worth | |
2219 | it. */ | |
2220 | int nops = (mips_optimize == 0 | |
2221 | ? nops_for_insn (history, NULL) | |
2222 | : nops_for_insn_or_target (history, ip)); | |
2223 | if (nops > 0) | |
252b5132 RH |
2224 | { |
2225 | fragS *old_frag; | |
2226 | unsigned long old_frag_offset; | |
2227 | int i; | |
252b5132 RH |
2228 | |
2229 | old_frag = frag_now; | |
2230 | old_frag_offset = frag_now_fix (); | |
2231 | ||
2232 | for (i = 0; i < nops; i++) | |
2233 | emit_nop (); | |
2234 | ||
2235 | if (listing) | |
2236 | { | |
2237 | listing_prev_line (); | |
2238 | /* We may be at the start of a variant frag. In case we | |
2239 | are, make sure there is enough space for the frag | |
2240 | after the frags created by listing_prev_line. The | |
2241 | argument to frag_grow here must be at least as large | |
2242 | as the argument to all other calls to frag_grow in | |
2243 | this file. We don't have to worry about being in the | |
2244 | middle of a variant frag, because the variants insert | |
2245 | all needed nop instructions themselves. */ | |
2246 | frag_grow (40); | |
2247 | } | |
2248 | ||
404a8071 | 2249 | mips_move_labels (); |
252b5132 RH |
2250 | |
2251 | #ifndef NO_ECOFF_DEBUGGING | |
2252 | if (ECOFF_DEBUGGING) | |
2253 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2254 | #endif | |
2255 | } | |
71400594 RS |
2256 | } |
2257 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2258 | { | |
2259 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2260 | int nops = nops_for_insn_or_target (history, ip); | |
2261 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2262 | |
71400594 RS |
2263 | /* Enforce NOPS as a minimum. */ |
2264 | if (nops > prev_nop_frag_required) | |
2265 | prev_nop_frag_required = nops; | |
252b5132 | 2266 | |
71400594 RS |
2267 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2268 | { | |
2269 | /* Settle for the current number of nops. Update the history | |
2270 | accordingly (for the benefit of any future .set reorder code). */ | |
2271 | prev_nop_frag = NULL; | |
2272 | insert_into_history (prev_nop_frag_since, | |
2273 | prev_nop_frag_holds, NOP_INSN); | |
2274 | } | |
2275 | else | |
2276 | { | |
2277 | /* Allow this instruction to replace one of the nops that was | |
2278 | tentatively added to prev_nop_frag. */ | |
2279 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2280 | prev_nop_frag_holds--; | |
2281 | prev_nop_frag_since++; | |
252b5132 RH |
2282 | } |
2283 | } | |
2284 | ||
58e2ea4d MR |
2285 | #ifdef OBJ_ELF |
2286 | /* The value passed to dwarf2_emit_insn is the distance between | |
2287 | the beginning of the current instruction and the address that | |
2288 | should be recorded in the debug tables. For MIPS16 debug info | |
2289 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2290 | address higher by one than the current. */ | |
2291 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2292 | #endif | |
2293 | ||
895921c9 | 2294 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2295 | if (history[0].frag) |
2296 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2297 | |
4d7206a2 | 2298 | if (address_expr |
0b25d3e6 | 2299 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2300 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2301 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2302 | && mips_relax_branch | |
2303 | /* Don't try branch relaxation within .set nomacro, or within | |
2304 | .set noat if we use $at for PIC computations. If it turns | |
2305 | out that the branch was out-of-range, we'll get an error. */ | |
2306 | && !mips_opts.warn_about_macros | |
2307 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2308 | && !mips_opts.mips16) | |
2309 | { | |
895921c9 | 2310 | relaxed_branch = TRUE; |
1e915849 RS |
2311 | add_relaxed_insn (ip, (relaxed_branch_length |
2312 | (NULL, NULL, | |
2313 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2314 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2315 | : 0)), 4, | |
2316 | RELAX_BRANCH_ENCODE | |
2317 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2318 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2319 | pinfo & INSN_WRITE_GPR_31, | |
2320 | 0), | |
2321 | address_expr->X_add_symbol, | |
2322 | address_expr->X_add_number); | |
4a6a3df4 AO |
2323 | *reloc_type = BFD_RELOC_UNUSED; |
2324 | } | |
2325 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2326 | { |
2327 | /* We need to set up a variant frag. */ | |
2328 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2329 | add_relaxed_insn (ip, 4, 0, |
2330 | RELAX_MIPS16_ENCODE | |
2331 | (*reloc_type - BFD_RELOC_UNUSED, | |
2332 | mips16_small, mips16_ext, | |
2333 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2334 | history[0].mips16_absolute_jump_p), | |
2335 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2336 | } |
252b5132 RH |
2337 | else if (mips_opts.mips16 |
2338 | && ! ip->use_extend | |
f6688943 | 2339 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2340 | { |
b8ee1a6e DU |
2341 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2342 | /* Make sure there is enough room to swap this instruction with | |
2343 | a following jump instruction. */ | |
2344 | frag_grow (6); | |
1e915849 | 2345 | add_fixed_insn (ip); |
252b5132 RH |
2346 | } |
2347 | else | |
2348 | { | |
2349 | if (mips_opts.mips16 | |
2350 | && mips_opts.noreorder | |
2351 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2352 | as_warn (_("extended instruction in delay slot")); | |
2353 | ||
4d7206a2 RS |
2354 | if (mips_relax.sequence) |
2355 | { | |
2356 | /* If we've reached the end of this frag, turn it into a variant | |
2357 | frag and record the information for the instructions we've | |
2358 | written so far. */ | |
2359 | if (frag_room () < 4) | |
2360 | relax_close_frag (); | |
2361 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2362 | } | |
2363 | ||
584892a6 RS |
2364 | if (mips_relax.sequence != 2) |
2365 | mips_macro_warning.sizes[0] += 4; | |
2366 | if (mips_relax.sequence != 1) | |
2367 | mips_macro_warning.sizes[1] += 4; | |
2368 | ||
1e915849 RS |
2369 | if (mips_opts.mips16) |
2370 | { | |
2371 | ip->fixed_p = 1; | |
2372 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2373 | } | |
2374 | add_fixed_insn (ip); | |
252b5132 RH |
2375 | } |
2376 | ||
01a3f561 | 2377 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2378 | { |
2379 | if (address_expr->X_op == O_constant) | |
2380 | { | |
f17c130b | 2381 | unsigned int tmp; |
f6688943 TS |
2382 | |
2383 | switch (*reloc_type) | |
252b5132 RH |
2384 | { |
2385 | case BFD_RELOC_32: | |
2386 | ip->insn_opcode |= address_expr->X_add_number; | |
2387 | break; | |
2388 | ||
f6688943 | 2389 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2390 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2391 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2392 | break; |
2393 | ||
2394 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2395 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2396 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2397 | break; |
2398 | ||
2399 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2400 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2401 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2402 | break; |
2403 | ||
2404 | case BFD_RELOC_HI16: | |
2405 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2406 | break; | |
2407 | ||
01a3f561 | 2408 | case BFD_RELOC_UNUSED: |
252b5132 | 2409 | case BFD_RELOC_LO16: |
ed6fb7bd | 2410 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2411 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2412 | break; | |
2413 | ||
2414 | case BFD_RELOC_MIPS_JMP: | |
2415 | if ((address_expr->X_add_number & 3) != 0) | |
2416 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2417 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2418 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2419 | as_bad (_("jump address range overflow (0x%lx)"), |
2420 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2421 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2422 | break; | |
2423 | ||
2424 | case BFD_RELOC_MIPS16_JMP: | |
2425 | if ((address_expr->X_add_number & 3) != 0) | |
2426 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2427 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2428 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2429 | as_bad (_("jump address range overflow (0x%lx)"), |
2430 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2431 | ip->insn_opcode |= |
2432 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2433 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2434 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2435 | break; | |
2436 | ||
252b5132 | 2437 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2438 | if ((address_expr->X_add_number & 3) != 0) |
2439 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2440 | (unsigned long) address_expr->X_add_number); | |
2441 | if (mips_relax_branch) | |
2442 | goto need_reloc; | |
2443 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2444 | as_bad (_("branch address range overflow (0x%lx)"), | |
2445 | (unsigned long) address_expr->X_add_number); | |
2446 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2447 | break; | |
252b5132 RH |
2448 | |
2449 | default: | |
2450 | internalError (); | |
2451 | } | |
2452 | } | |
01a3f561 | 2453 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2454 | need_reloc: |
4d7206a2 RS |
2455 | { |
2456 | reloc_howto_type *howto; | |
2457 | int i; | |
34ce925e | 2458 | |
4d7206a2 RS |
2459 | /* In a compound relocation, it is the final (outermost) |
2460 | operator that determines the relocated field. */ | |
2461 | for (i = 1; i < 3; i++) | |
2462 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2463 | break; | |
34ce925e | 2464 | |
4d7206a2 | 2465 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2466 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2467 | bfd_get_reloc_size (howto), | |
2468 | address_expr, | |
2469 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2470 | reloc_type[0]); | |
4d7206a2 RS |
2471 | |
2472 | /* These relocations can have an addend that won't fit in | |
2473 | 4 octets for 64bit assembly. */ | |
2474 | if (HAVE_64BIT_GPRS | |
2475 | && ! howto->partial_inplace | |
2476 | && (reloc_type[0] == BFD_RELOC_16 | |
2477 | || reloc_type[0] == BFD_RELOC_32 | |
2478 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2479 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2480 | || reloc_type[0] == BFD_RELOC_LO16 | |
2481 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2482 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2483 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2484 | || reloc_type[0] == BFD_RELOC_64 | |
2485 | || reloc_type[0] == BFD_RELOC_CTOR | |
2486 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2487 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2488 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2489 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2490 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2491 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2492 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2493 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2494 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2495 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2496 | |
2497 | if (mips_relax.sequence) | |
2498 | { | |
2499 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2500 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2501 | } |
2502 | else if (reloc_needs_lo_p (*reloc_type)) | |
2503 | { | |
2504 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2505 | |
4d7206a2 RS |
2506 | /* Reuse the last entry if it already has a matching %lo. */ |
2507 | hi_fixup = mips_hi_fixup_list; | |
2508 | if (hi_fixup == 0 | |
2509 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2510 | { | |
2511 | hi_fixup = ((struct mips_hi_fixup *) | |
2512 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2513 | hi_fixup->next = mips_hi_fixup_list; | |
2514 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2515 | } |
1e915849 | 2516 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2517 | hi_fixup->seg = now_seg; |
2518 | } | |
f6688943 | 2519 | |
4d7206a2 RS |
2520 | /* Add fixups for the second and third relocations, if given. |
2521 | Note that the ABI allows the second relocation to be | |
2522 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2523 | moment we only use RSS_UNDEF, but we could add support | |
2524 | for the others if it ever becomes necessary. */ | |
2525 | for (i = 1; i < 3; i++) | |
2526 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2527 | { | |
1e915849 RS |
2528 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2529 | ip->fixp[0]->fx_size, NULL, 0, | |
2530 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2531 | |
2532 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2533 | ip->fixp[0]->fx_tcbit = 1; |
2534 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2535 | } |
252b5132 RH |
2536 | } |
2537 | } | |
1e915849 | 2538 | install_insn (ip); |
252b5132 RH |
2539 | |
2540 | /* Update the register mask information. */ | |
2541 | if (! mips_opts.mips16) | |
2542 | { | |
2543 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2544 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2545 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2546 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2547 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2548 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2549 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2550 | mips_gprmask |= 1 << RA; |
252b5132 | 2551 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2552 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2553 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2554 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2555 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2556 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2557 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2558 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2559 | if (pinfo & INSN_COP) |
2560 | { | |
bdaaa2e1 KH |
2561 | /* We don't keep enough information to sort these cases out. |
2562 | The itbl support does keep this information however, although | |
2563 | we currently don't support itbl fprmats as part of the cop | |
2564 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2565 | } |
2566 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2567 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2568 | } |
2569 | else | |
2570 | { | |
2571 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2572 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2573 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2574 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2575 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2576 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2577 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2578 | mips_gprmask |= 1 << TREG; | |
2579 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2580 | mips_gprmask |= 1 << SP; | |
2581 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2582 | mips_gprmask |= 1 << RA; | |
2583 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2584 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2585 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2586 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2587 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2588 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2589 | } |
2590 | ||
4d7206a2 | 2591 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2592 | { |
2593 | /* Filling the branch delay slot is more complex. We try to | |
2594 | switch the branch with the previous instruction, which we can | |
2595 | do if the previous instruction does not set up a condition | |
2596 | that the branch tests and if the branch is not itself the | |
2597 | target of any branch. */ | |
2598 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2599 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2600 | { | |
2601 | if (mips_optimize < 2 | |
2602 | /* If we have seen .set volatile or .set nomove, don't | |
2603 | optimize. */ | |
2604 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2605 | /* We can't swap if the previous instruction's position |
2606 | is fixed. */ | |
2607 | || history[0].fixed_p | |
252b5132 RH |
2608 | /* If the previous previous insn was in a .set |
2609 | noreorder, we can't swap. Actually, the MIPS | |
2610 | assembler will swap in this situation. However, gcc | |
2611 | configured -with-gnu-as will generate code like | |
2612 | .set noreorder | |
2613 | lw $4,XXX | |
2614 | .set reorder | |
2615 | INSN | |
2616 | bne $4,$0,foo | |
2617 | in which we can not swap the bne and INSN. If gcc is | |
2618 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2619 | .set pseudo-ops. */ |
47e39b9d | 2620 | || history[1].noreorder_p |
252b5132 RH |
2621 | /* If the branch is itself the target of a branch, we |
2622 | can not swap. We cheat on this; all we check for is | |
2623 | whether there is a label on this instruction. If | |
2624 | there are any branches to anything other than a | |
2625 | label, users must use .set noreorder. */ | |
2626 | || insn_labels != NULL | |
895921c9 MR |
2627 | /* If the previous instruction is in a variant frag |
2628 | other than this branch's one, we cannot do the swap. | |
2629 | This does not apply to the mips16, which uses variant | |
2630 | frags for different purposes. */ | |
252b5132 | 2631 | || (! mips_opts.mips16 |
895921c9 | 2632 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2633 | /* Check for conflicts between the branch and the instructions |
2634 | before the candidate delay slot. */ | |
2635 | || nops_for_insn (history + 1, ip) > 0 | |
2636 | /* Check for conflicts between the swapped sequence and the | |
2637 | target of the branch. */ | |
2638 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2639 | /* We do not swap with a trap instruction, since it |
2640 | complicates trap handlers to have the trap | |
2641 | instruction be in a delay slot. */ | |
2642 | || (prev_pinfo & INSN_TRAP) | |
2643 | /* If the branch reads a register that the previous | |
2644 | instruction sets, we can not swap. */ | |
2645 | || (! mips_opts.mips16 | |
2646 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2647 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2648 | MIPS_GR_REG)) |
2649 | || (! mips_opts.mips16 | |
2650 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2651 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2652 | MIPS_GR_REG)) |
2653 | || (mips_opts.mips16 | |
2654 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2655 | && (insn_uses_reg |
2656 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2657 | MIPS16_REG))) | |
252b5132 | 2658 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2659 | && (insn_uses_reg |
2660 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2661 | MIPS16_REG))) | |
252b5132 | 2662 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2663 | && (insn_uses_reg |
2664 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2665 | MIPS16_REG))) | |
252b5132 RH |
2666 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2667 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2668 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2669 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2670 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2671 | && insn_uses_reg (ip, | |
47e39b9d RS |
2672 | MIPS16OP_EXTRACT_REG32R |
2673 | (history[0].insn_opcode), | |
252b5132 RH |
2674 | MIPS_GR_REG)))) |
2675 | /* If the branch writes a register that the previous | |
2676 | instruction sets, we can not swap (we know that | |
2677 | branches write only to RD or to $31). */ | |
2678 | || (! mips_opts.mips16 | |
2679 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2680 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2681 | && (EXTRACT_OPERAND (RT, history[0]) |
2682 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2683 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2684 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2685 | || (! mips_opts.mips16 |
2686 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2687 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2688 | && (EXTRACT_OPERAND (RD, history[0]) |
2689 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2690 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2691 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2692 | || (mips_opts.mips16 |
2693 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2694 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2695 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2696 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2697 | == RA)))) |
2698 | /* If the branch writes a register that the previous | |
2699 | instruction reads, we can not swap (we know that | |
2700 | branches only write to RD or to $31). */ | |
2701 | || (! mips_opts.mips16 | |
2702 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2703 | && insn_uses_reg (&history[0], |
bf12938e | 2704 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2705 | MIPS_GR_REG)) |
2706 | || (! mips_opts.mips16 | |
2707 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2708 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2709 | || (mips_opts.mips16 |
2710 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2711 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2712 | /* If one instruction sets a condition code and the |
2713 | other one uses a condition code, we can not swap. */ | |
2714 | || ((pinfo & INSN_READ_COND_CODE) | |
2715 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2716 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2717 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2718 | /* If the previous instruction uses the PC, we can not | |
2719 | swap. */ | |
2720 | || (mips_opts.mips16 | |
2721 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2722 | /* If the previous instruction had a fixup in mips16 |
2723 | mode, we can not swap. This normally means that the | |
2724 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2725 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2726 | /* If the previous instruction is a sync, sync.l, or |
2727 | sync.p, we can not swap. */ | |
f173e82e | 2728 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 2729 | { |
29024861 DU |
2730 | if (mips_opts.mips16 |
2731 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2732 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
2733 | && (mips_opts.isa == ISA_MIPS32 | |
2734 | || mips_opts.isa == ISA_MIPS32R2 | |
2735 | || mips_opts.isa == ISA_MIPS64 | |
2736 | || mips_opts.isa == ISA_MIPS64R2)) | |
2737 | { | |
2738 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
2739 | ip->insn_opcode |= 0x0080; | |
2740 | install_insn (ip); | |
2741 | insert_into_history (0, 1, ip); | |
2742 | } | |
2743 | else | |
2744 | { | |
2745 | /* We could do even better for unconditional branches to | |
2746 | portions of this object file; we could pick up the | |
2747 | instruction at the destination, put it in the delay | |
2748 | slot, and bump the destination address. */ | |
2749 | insert_into_history (0, 1, ip); | |
2750 | emit_nop (); | |
2751 | } | |
2752 | ||
dd22970f ILT |
2753 | if (mips_relax.sequence) |
2754 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2755 | } |
2756 | else | |
2757 | { | |
2758 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2759 | struct mips_cl_insn delay = history[0]; |
2760 | if (mips_opts.mips16) | |
252b5132 | 2761 | { |
b8ee1a6e DU |
2762 | know (delay.frag == ip->frag); |
2763 | move_insn (ip, delay.frag, delay.where); | |
2764 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
2765 | } |
2766 | else if (relaxed_branch) | |
2767 | { | |
2768 | /* Add the delay slot instruction to the end of the | |
2769 | current frag and shrink the fixed part of the | |
2770 | original frag. If the branch occupies the tail of | |
2771 | the latter, move it backwards to cover the gap. */ | |
2772 | delay.frag->fr_fix -= 4; | |
2773 | if (delay.frag == ip->frag) | |
2774 | move_insn (ip, ip->frag, ip->where - 4); | |
2775 | add_fixed_insn (&delay); | |
252b5132 RH |
2776 | } |
2777 | else | |
2778 | { | |
1e915849 RS |
2779 | move_insn (&delay, ip->frag, ip->where); |
2780 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2781 | } |
1e915849 RS |
2782 | history[0] = *ip; |
2783 | delay.fixed_p = 1; | |
2784 | insert_into_history (0, 1, &delay); | |
252b5132 | 2785 | } |
252b5132 RH |
2786 | |
2787 | /* If that was an unconditional branch, forget the previous | |
2788 | insn information. */ | |
2789 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2790 | mips_no_prev_insn (); |
252b5132 RH |
2791 | } |
2792 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2793 | { | |
2794 | /* We don't yet optimize a branch likely. What we should do | |
2795 | is look at the target, copy the instruction found there | |
2796 | into the delay slot, and increment the branch to jump to | |
2797 | the next instruction. */ | |
1e915849 | 2798 | insert_into_history (0, 1, ip); |
252b5132 | 2799 | emit_nop (); |
252b5132 RH |
2800 | } |
2801 | else | |
1e915849 | 2802 | insert_into_history (0, 1, ip); |
252b5132 | 2803 | } |
1e915849 RS |
2804 | else |
2805 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2806 | |
2807 | /* We just output an insn, so the next one doesn't have a label. */ | |
2808 | mips_clear_insn_labels (); | |
252b5132 RH |
2809 | } |
2810 | ||
7d10b47d | 2811 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2812 | |
2813 | static void | |
7d10b47d | 2814 | mips_no_prev_insn (void) |
252b5132 | 2815 | { |
7d10b47d RS |
2816 | prev_nop_frag = NULL; |
2817 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2818 | mips_clear_insn_labels (); |
2819 | } | |
2820 | ||
7d10b47d RS |
2821 | /* This function must be called before we emit something other than |
2822 | instructions. It is like mips_no_prev_insn except that it inserts | |
2823 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2824 | |
7d10b47d RS |
2825 | void |
2826 | mips_emit_delays (void) | |
252b5132 RH |
2827 | { |
2828 | if (! mips_opts.noreorder) | |
2829 | { | |
71400594 | 2830 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2831 | if (nops > 0) |
2832 | { | |
7d10b47d RS |
2833 | while (nops-- > 0) |
2834 | add_fixed_insn (NOP_INSN); | |
2835 | mips_move_labels (); | |
2836 | } | |
2837 | } | |
2838 | mips_no_prev_insn (); | |
2839 | } | |
2840 | ||
2841 | /* Start a (possibly nested) noreorder block. */ | |
2842 | ||
2843 | static void | |
2844 | start_noreorder (void) | |
2845 | { | |
2846 | if (mips_opts.noreorder == 0) | |
2847 | { | |
2848 | unsigned int i; | |
2849 | int nops; | |
2850 | ||
2851 | /* None of the instructions before the .set noreorder can be moved. */ | |
2852 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2853 | history[i].fixed_p = 1; | |
2854 | ||
2855 | /* Insert any nops that might be needed between the .set noreorder | |
2856 | block and the previous instructions. We will later remove any | |
2857 | nops that turn out not to be needed. */ | |
2858 | nops = nops_for_insn (history, NULL); | |
2859 | if (nops > 0) | |
2860 | { | |
2861 | if (mips_optimize != 0) | |
252b5132 RH |
2862 | { |
2863 | /* Record the frag which holds the nop instructions, so | |
2864 | that we can remove them if we don't need them. */ | |
2865 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2866 | prev_nop_frag = frag_now; | |
2867 | prev_nop_frag_holds = nops; | |
2868 | prev_nop_frag_required = 0; | |
2869 | prev_nop_frag_since = 0; | |
2870 | } | |
2871 | ||
2872 | for (; nops > 0; --nops) | |
1e915849 | 2873 | add_fixed_insn (NOP_INSN); |
252b5132 | 2874 | |
7d10b47d RS |
2875 | /* Move on to a new frag, so that it is safe to simply |
2876 | decrease the size of prev_nop_frag. */ | |
2877 | frag_wane (frag_now); | |
2878 | frag_new (0); | |
404a8071 | 2879 | mips_move_labels (); |
252b5132 | 2880 | } |
7d10b47d RS |
2881 | mips16_mark_labels (); |
2882 | mips_clear_insn_labels (); | |
252b5132 | 2883 | } |
7d10b47d RS |
2884 | mips_opts.noreorder++; |
2885 | mips_any_noreorder = 1; | |
2886 | } | |
252b5132 | 2887 | |
7d10b47d | 2888 | /* End a nested noreorder block. */ |
252b5132 | 2889 | |
7d10b47d RS |
2890 | static void |
2891 | end_noreorder (void) | |
2892 | { | |
2893 | mips_opts.noreorder--; | |
2894 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2895 | { | |
2896 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2897 | handling nop insertion the .set reorder way. */ | |
2898 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2899 | * (mips_opts.mips16 ? 2 : 4)); | |
2900 | insert_into_history (prev_nop_frag_since, | |
2901 | prev_nop_frag_required, NOP_INSN); | |
2902 | prev_nop_frag = NULL; | |
2903 | } | |
252b5132 RH |
2904 | } |
2905 | ||
584892a6 RS |
2906 | /* Set up global variables for the start of a new macro. */ |
2907 | ||
2908 | static void | |
2909 | macro_start (void) | |
2910 | { | |
2911 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2912 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2913 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2914 | & (INSN_UNCOND_BRANCH_DELAY |
2915 | | INSN_COND_BRANCH_DELAY | |
2916 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2917 | } | |
2918 | ||
2919 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2920 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2921 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2922 | ||
2923 | static const char * | |
2924 | macro_warning (relax_substateT subtype) | |
2925 | { | |
2926 | if (subtype & RELAX_DELAY_SLOT) | |
2927 | return _("Macro instruction expanded into multiple instructions" | |
2928 | " in a branch delay slot"); | |
2929 | else if (subtype & RELAX_NOMACRO) | |
2930 | return _("Macro instruction expanded into multiple instructions"); | |
2931 | else | |
2932 | return 0; | |
2933 | } | |
2934 | ||
2935 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2936 | ||
2937 | static void | |
2938 | macro_end (void) | |
2939 | { | |
2940 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2941 | { | |
2942 | relax_substateT subtype; | |
2943 | ||
2944 | /* Set up the relaxation warning flags. */ | |
2945 | subtype = 0; | |
2946 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2947 | subtype |= RELAX_SECOND_LONGER; | |
2948 | if (mips_opts.warn_about_macros) | |
2949 | subtype |= RELAX_NOMACRO; | |
2950 | if (mips_macro_warning.delay_slot_p) | |
2951 | subtype |= RELAX_DELAY_SLOT; | |
2952 | ||
2953 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2954 | { | |
2955 | /* Either the macro has a single implementation or both | |
2956 | implementations are longer than 4 bytes. Emit the | |
2957 | warning now. */ | |
2958 | const char *msg = macro_warning (subtype); | |
2959 | if (msg != 0) | |
2960 | as_warn (msg); | |
2961 | } | |
2962 | else | |
2963 | { | |
2964 | /* One implementation might need a warning but the other | |
2965 | definitely doesn't. */ | |
2966 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2967 | } | |
2968 | } | |
2969 | } | |
2970 | ||
6e1304d8 RS |
2971 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2972 | The first argument in *ARGS will be either the code for a single | |
2973 | relocation or -1 followed by the three codes that make up a | |
2974 | composite relocation. */ | |
2975 | ||
2976 | static void | |
2977 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2978 | { | |
2979 | int i, next; | |
2980 | ||
2981 | next = va_arg (*args, int); | |
2982 | if (next >= 0) | |
2983 | r[0] = (bfd_reloc_code_real_type) next; | |
2984 | else | |
2985 | for (i = 0; i < 3; i++) | |
2986 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2987 | } | |
2988 | ||
252b5132 RH |
2989 | /* Build an instruction created by a macro expansion. This is passed |
2990 | a pointer to the count of instructions created so far, an | |
2991 | expression, the name of the instruction to build, an operand format | |
2992 | string, and corresponding arguments. */ | |
2993 | ||
252b5132 | 2994 | static void |
67c0d1eb | 2995 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2996 | { |
1e915849 | 2997 | const struct mips_opcode *mo; |
252b5132 | 2998 | struct mips_cl_insn insn; |
f6688943 | 2999 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3000 | va_list args; |
252b5132 | 3001 | |
252b5132 | 3002 | va_start (args, fmt); |
252b5132 | 3003 | |
252b5132 RH |
3004 | if (mips_opts.mips16) |
3005 | { | |
67c0d1eb | 3006 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3007 | va_end (args); |
3008 | return; | |
3009 | } | |
3010 | ||
f6688943 TS |
3011 | r[0] = BFD_RELOC_UNUSED; |
3012 | r[1] = BFD_RELOC_UNUSED; | |
3013 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3014 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3015 | assert (mo); | |
3016 | assert (strcmp (name, mo->name) == 0); | |
3017 | ||
3018 | /* Search until we get a match for NAME. It is assumed here that | |
3019 | macros will never generate MDMX or MIPS-3D instructions. */ | |
3020 | while (strcmp (fmt, mo->args) != 0 | |
3021 | || mo->pinfo == INSN_MACRO | |
3022 | || !OPCODE_IS_MEMBER (mo, | |
3023 | (mips_opts.isa | |
e16bfa71 TS |
3024 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
3025 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 3026 | mips_opts.arch) |
1e915849 RS |
3027 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
3028 | { | |
3029 | ++mo; | |
3030 | assert (mo->name); | |
3031 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3032 | } |
3033 | ||
1e915849 | 3034 | create_insn (&insn, mo); |
252b5132 RH |
3035 | for (;;) |
3036 | { | |
3037 | switch (*fmt++) | |
3038 | { | |
3039 | case '\0': | |
3040 | break; | |
3041 | ||
3042 | case ',': | |
3043 | case '(': | |
3044 | case ')': | |
3045 | continue; | |
3046 | ||
5f74bc13 CD |
3047 | case '+': |
3048 | switch (*fmt++) | |
3049 | { | |
3050 | case 'A': | |
3051 | case 'E': | |
bf12938e | 3052 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3053 | continue; |
3054 | ||
3055 | case 'B': | |
3056 | case 'F': | |
3057 | /* Note that in the macro case, these arguments are already | |
3058 | in MSB form. (When handling the instruction in the | |
3059 | non-macro case, these arguments are sizes from which | |
3060 | MSB values must be calculated.) */ | |
bf12938e | 3061 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3062 | continue; |
3063 | ||
3064 | case 'C': | |
3065 | case 'G': | |
3066 | case 'H': | |
3067 | /* Note that in the macro case, these arguments are already | |
3068 | in MSBD form. (When handling the instruction in the | |
3069 | non-macro case, these arguments are sizes from which | |
3070 | MSBD values must be calculated.) */ | |
bf12938e | 3071 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3072 | continue; |
3073 | ||
3074 | default: | |
3075 | internalError (); | |
3076 | } | |
3077 | continue; | |
3078 | ||
252b5132 RH |
3079 | case 't': |
3080 | case 'w': | |
3081 | case 'E': | |
bf12938e | 3082 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3083 | continue; |
3084 | ||
3085 | case 'c': | |
bf12938e | 3086 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3087 | continue; |
3088 | ||
252b5132 RH |
3089 | case 'T': |
3090 | case 'W': | |
bf12938e | 3091 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3092 | continue; |
3093 | ||
3094 | case 'd': | |
3095 | case 'G': | |
af7ee8bf | 3096 | case 'K': |
bf12938e | 3097 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3098 | continue; |
3099 | ||
4372b673 NC |
3100 | case 'U': |
3101 | { | |
3102 | int tmp = va_arg (args, int); | |
3103 | ||
bf12938e RS |
3104 | INSERT_OPERAND (RT, insn, tmp); |
3105 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3106 | continue; |
4372b673 NC |
3107 | } |
3108 | ||
252b5132 RH |
3109 | case 'V': |
3110 | case 'S': | |
bf12938e | 3111 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3112 | continue; |
3113 | ||
3114 | case 'z': | |
3115 | continue; | |
3116 | ||
3117 | case '<': | |
bf12938e | 3118 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3119 | continue; |
3120 | ||
3121 | case 'D': | |
bf12938e | 3122 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3123 | continue; |
3124 | ||
3125 | case 'B': | |
bf12938e | 3126 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3127 | continue; |
3128 | ||
4372b673 | 3129 | case 'J': |
bf12938e | 3130 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3131 | continue; |
3132 | ||
252b5132 | 3133 | case 'q': |
bf12938e | 3134 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3135 | continue; |
3136 | ||
3137 | case 'b': | |
3138 | case 's': | |
3139 | case 'r': | |
3140 | case 'v': | |
bf12938e | 3141 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3142 | continue; |
3143 | ||
3144 | case 'i': | |
3145 | case 'j': | |
3146 | case 'o': | |
6e1304d8 | 3147 | macro_read_relocs (&args, r); |
cdf6fd85 | 3148 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3149 | || *r == BFD_RELOC_MIPS_LITERAL |
3150 | || *r == BFD_RELOC_MIPS_HIGHER | |
3151 | || *r == BFD_RELOC_HI16_S | |
3152 | || *r == BFD_RELOC_LO16 | |
3153 | || *r == BFD_RELOC_MIPS_GOT16 | |
3154 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3155 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3156 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3157 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3158 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3159 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3160 | continue; |
3161 | ||
3162 | case 'u': | |
6e1304d8 | 3163 | macro_read_relocs (&args, r); |
252b5132 RH |
3164 | assert (ep != NULL |
3165 | && (ep->X_op == O_constant | |
3166 | || (ep->X_op == O_symbol | |
f6688943 TS |
3167 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3168 | || *r == BFD_RELOC_HI16_S | |
3169 | || *r == BFD_RELOC_HI16 | |
3170 | || *r == BFD_RELOC_GPREL16 | |
3171 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3172 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3173 | continue; |
3174 | ||
3175 | case 'p': | |
3176 | assert (ep != NULL); | |
bad36eac | 3177 | |
252b5132 RH |
3178 | /* |
3179 | * This allows macro() to pass an immediate expression for | |
3180 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3181 | * |
3182 | * We don't allow branch relaxation for these branches, as | |
3183 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3184 | */ |
3185 | if (ep->X_op == O_constant) | |
3186 | { | |
bad36eac DJ |
3187 | if ((ep->X_add_number & 3) != 0) |
3188 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3189 | (unsigned long) ep->X_add_number); | |
3190 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3191 | as_bad (_("branch address range overflow (0x%lx)"), | |
3192 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3193 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3194 | ep = NULL; | |
3195 | } | |
3196 | else | |
0b25d3e6 | 3197 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3198 | continue; |
3199 | ||
3200 | case 'a': | |
3201 | assert (ep != NULL); | |
f6688943 | 3202 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3203 | continue; |
3204 | ||
3205 | case 'C': | |
3206 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3207 | continue; | |
3208 | ||
d43b4baf TS |
3209 | case 'k': |
3210 | insn.insn_opcode |= va_arg (args, unsigned long) << OP_SH_CACHE; | |
3211 | continue; | |
3212 | ||
252b5132 RH |
3213 | default: |
3214 | internalError (); | |
3215 | } | |
3216 | break; | |
3217 | } | |
3218 | va_end (args); | |
f6688943 | 3219 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3220 | |
4d7206a2 | 3221 | append_insn (&insn, ep, r); |
252b5132 RH |
3222 | } |
3223 | ||
3224 | static void | |
67c0d1eb | 3225 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3226 | va_list args) |
252b5132 | 3227 | { |
1e915849 | 3228 | struct mips_opcode *mo; |
252b5132 | 3229 | struct mips_cl_insn insn; |
f6688943 TS |
3230 | bfd_reloc_code_real_type r[3] |
3231 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3232 | |
1e915849 RS |
3233 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3234 | assert (mo); | |
3235 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3236 | |
1e915849 | 3237 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3238 | { |
1e915849 RS |
3239 | ++mo; |
3240 | assert (mo->name); | |
3241 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3242 | } |
3243 | ||
1e915849 | 3244 | create_insn (&insn, mo); |
252b5132 RH |
3245 | for (;;) |
3246 | { | |
3247 | int c; | |
3248 | ||
3249 | c = *fmt++; | |
3250 | switch (c) | |
3251 | { | |
3252 | case '\0': | |
3253 | break; | |
3254 | ||
3255 | case ',': | |
3256 | case '(': | |
3257 | case ')': | |
3258 | continue; | |
3259 | ||
3260 | case 'y': | |
3261 | case 'w': | |
bf12938e | 3262 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3263 | continue; |
3264 | ||
3265 | case 'x': | |
3266 | case 'v': | |
bf12938e | 3267 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3268 | continue; |
3269 | ||
3270 | case 'z': | |
bf12938e | 3271 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3272 | continue; |
3273 | ||
3274 | case 'Z': | |
bf12938e | 3275 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3276 | continue; |
3277 | ||
3278 | case '0': | |
3279 | case 'S': | |
3280 | case 'P': | |
3281 | case 'R': | |
3282 | continue; | |
3283 | ||
3284 | case 'X': | |
bf12938e | 3285 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3286 | continue; |
3287 | ||
3288 | case 'Y': | |
3289 | { | |
3290 | int regno; | |
3291 | ||
3292 | regno = va_arg (args, int); | |
3293 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3294 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3295 | } | |
3296 | continue; | |
3297 | ||
3298 | case '<': | |
3299 | case '>': | |
3300 | case '4': | |
3301 | case '5': | |
3302 | case 'H': | |
3303 | case 'W': | |
3304 | case 'D': | |
3305 | case 'j': | |
3306 | case '8': | |
3307 | case 'V': | |
3308 | case 'C': | |
3309 | case 'U': | |
3310 | case 'k': | |
3311 | case 'K': | |
3312 | case 'p': | |
3313 | case 'q': | |
3314 | { | |
3315 | assert (ep != NULL); | |
3316 | ||
3317 | if (ep->X_op != O_constant) | |
874e8986 | 3318 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3319 | else |
3320 | { | |
b34976b6 AM |
3321 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3322 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3323 | &insn.extend); |
252b5132 | 3324 | ep = NULL; |
f6688943 | 3325 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3326 | } |
3327 | } | |
3328 | continue; | |
3329 | ||
3330 | case '6': | |
bf12938e | 3331 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3332 | continue; |
3333 | } | |
3334 | ||
3335 | break; | |
3336 | } | |
3337 | ||
f6688943 | 3338 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3339 | |
4d7206a2 | 3340 | append_insn (&insn, ep, r); |
252b5132 RH |
3341 | } |
3342 | ||
2051e8c4 MR |
3343 | /* |
3344 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3345 | * higher bits unset. | |
3346 | */ | |
9f872bbe | 3347 | static void |
2051e8c4 MR |
3348 | normalize_constant_expr (expressionS *ex) |
3349 | { | |
9ee2a2d4 | 3350 | if (ex->X_op == O_constant |
2051e8c4 MR |
3351 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3352 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3353 | - 0x80000000); | |
3354 | } | |
3355 | ||
3356 | /* | |
3357 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3358 | * all higher bits unset. | |
3359 | */ | |
3360 | static void | |
3361 | normalize_address_expr (expressionS *ex) | |
3362 | { | |
3363 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3364 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3365 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3366 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3367 | - 0x80000000); | |
3368 | } | |
3369 | ||
438c16b8 TS |
3370 | /* |
3371 | * Generate a "jalr" instruction with a relocation hint to the called | |
3372 | * function. This occurs in NewABI PIC code. | |
3373 | */ | |
3374 | static void | |
67c0d1eb | 3375 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3376 | { |
685736be | 3377 | char *f = NULL; |
b34976b6 | 3378 | |
438c16b8 | 3379 | if (HAVE_NEWABI) |
f21f8242 | 3380 | { |
cc3d92a5 | 3381 | frag_grow (8); |
f21f8242 AO |
3382 | f = frag_more (0); |
3383 | } | |
67c0d1eb | 3384 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3385 | if (HAVE_NEWABI) |
f21f8242 | 3386 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3387 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3388 | } |
3389 | ||
252b5132 RH |
3390 | /* |
3391 | * Generate a "lui" instruction. | |
3392 | */ | |
3393 | static void | |
67c0d1eb | 3394 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3395 | { |
3396 | expressionS high_expr; | |
1e915849 | 3397 | const struct mips_opcode *mo; |
252b5132 | 3398 | struct mips_cl_insn insn; |
f6688943 TS |
3399 | bfd_reloc_code_real_type r[3] |
3400 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3401 | const char *name = "lui"; |
3402 | const char *fmt = "t,u"; | |
252b5132 RH |
3403 | |
3404 | assert (! mips_opts.mips16); | |
3405 | ||
4d7206a2 | 3406 | high_expr = *ep; |
252b5132 RH |
3407 | |
3408 | if (high_expr.X_op == O_constant) | |
3409 | { | |
3410 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3411 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3412 | >> 16) & 0xffff; | |
f6688943 | 3413 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3414 | } |
78e1bb40 | 3415 | else |
252b5132 RH |
3416 | { |
3417 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3418 | /* _gp_disp is a special case, used from s_cpload. |
3419 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3420 | assert (mips_pic == NO_PIC |
78e1bb40 | 3421 | || (! HAVE_NEWABI |
aa6975fb ILT |
3422 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3423 | || (! mips_in_shared | |
bbe506e8 TS |
3424 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3425 | "__gnu_local_gp") == 0)); | |
f6688943 | 3426 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3427 | } |
3428 | ||
1e915849 RS |
3429 | mo = hash_find (op_hash, name); |
3430 | assert (strcmp (name, mo->name) == 0); | |
3431 | assert (strcmp (fmt, mo->args) == 0); | |
3432 | create_insn (&insn, mo); | |
252b5132 | 3433 | |
bf12938e RS |
3434 | insn.insn_opcode = insn.insn_mo->match; |
3435 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3436 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3437 | { |
3438 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3439 | append_insn (&insn, NULL, r); |
252b5132 RH |
3440 | } |
3441 | else | |
4d7206a2 | 3442 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3443 | } |
3444 | ||
885add95 CD |
3445 | /* Generate a sequence of instructions to do a load or store from a constant |
3446 | offset off of a base register (breg) into/from a target register (treg), | |
3447 | using AT if necessary. */ | |
3448 | static void | |
67c0d1eb RS |
3449 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3450 | int treg, int breg, int dbl) | |
885add95 CD |
3451 | { |
3452 | assert (ep->X_op == O_constant); | |
3453 | ||
256ab948 | 3454 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3455 | if (!dbl) |
3456 | normalize_constant_expr (ep); | |
256ab948 | 3457 | |
67c1ffbe | 3458 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3459 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3460 | as_warn (_("operand overflow")); |
3461 | ||
3462 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3463 | { | |
3464 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3465 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3466 | } |
3467 | else | |
3468 | { | |
3469 | /* 32-bit offset, need multiple instructions and AT, like: | |
3470 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3471 | addu $tempreg,$tempreg,$breg | |
3472 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3473 | to handle the complete offset. */ | |
67c0d1eb RS |
3474 | macro_build_lui (ep, AT); |
3475 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3476 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3477 | |
3478 | if (mips_opts.noat) | |
8fc2e39e | 3479 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3480 | } |
3481 | } | |
3482 | ||
252b5132 RH |
3483 | /* set_at() |
3484 | * Generates code to set the $at register to true (one) | |
3485 | * if reg is less than the immediate expression. | |
3486 | */ | |
3487 | static void | |
67c0d1eb | 3488 | set_at (int reg, int unsignedp) |
252b5132 RH |
3489 | { |
3490 | if (imm_expr.X_op == O_constant | |
3491 | && imm_expr.X_add_number >= -0x8000 | |
3492 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3493 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3494 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3495 | else |
3496 | { | |
67c0d1eb RS |
3497 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3498 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3499 | } |
3500 | } | |
3501 | ||
3502 | /* Warn if an expression is not a constant. */ | |
3503 | ||
3504 | static void | |
17a2f251 | 3505 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3506 | { |
3507 | if (ex->X_op == O_big) | |
3508 | as_bad (_("unsupported large constant")); | |
3509 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3510 | as_bad (_("Instruction %s requires absolute expression"), |
3511 | ip->insn_mo->name); | |
13757d0c | 3512 | |
9ee2a2d4 MR |
3513 | if (HAVE_32BIT_GPRS) |
3514 | normalize_constant_expr (ex); | |
252b5132 RH |
3515 | } |
3516 | ||
3517 | /* Count the leading zeroes by performing a binary chop. This is a | |
3518 | bulky bit of source, but performance is a LOT better for the | |
3519 | majority of values than a simple loop to count the bits: | |
3520 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3521 | if ((v) & (1 << (31 - lcnt))) | |
3522 | break; | |
3523 | However it is not code size friendly, and the gain will drop a bit | |
3524 | on certain cached systems. | |
3525 | */ | |
3526 | #define COUNT_TOP_ZEROES(v) \ | |
3527 | (((v) & ~0xffff) == 0 \ | |
3528 | ? ((v) & ~0xff) == 0 \ | |
3529 | ? ((v) & ~0xf) == 0 \ | |
3530 | ? ((v) & ~0x3) == 0 \ | |
3531 | ? ((v) & ~0x1) == 0 \ | |
3532 | ? !(v) \ | |
3533 | ? 32 \ | |
3534 | : 31 \ | |
3535 | : 30 \ | |
3536 | : ((v) & ~0x7) == 0 \ | |
3537 | ? 29 \ | |
3538 | : 28 \ | |
3539 | : ((v) & ~0x3f) == 0 \ | |
3540 | ? ((v) & ~0x1f) == 0 \ | |
3541 | ? 27 \ | |
3542 | : 26 \ | |
3543 | : ((v) & ~0x7f) == 0 \ | |
3544 | ? 25 \ | |
3545 | : 24 \ | |
3546 | : ((v) & ~0xfff) == 0 \ | |
3547 | ? ((v) & ~0x3ff) == 0 \ | |
3548 | ? ((v) & ~0x1ff) == 0 \ | |
3549 | ? 23 \ | |
3550 | : 22 \ | |
3551 | : ((v) & ~0x7ff) == 0 \ | |
3552 | ? 21 \ | |
3553 | : 20 \ | |
3554 | : ((v) & ~0x3fff) == 0 \ | |
3555 | ? ((v) & ~0x1fff) == 0 \ | |
3556 | ? 19 \ | |
3557 | : 18 \ | |
3558 | : ((v) & ~0x7fff) == 0 \ | |
3559 | ? 17 \ | |
3560 | : 16 \ | |
3561 | : ((v) & ~0xffffff) == 0 \ | |
3562 | ? ((v) & ~0xfffff) == 0 \ | |
3563 | ? ((v) & ~0x3ffff) == 0 \ | |
3564 | ? ((v) & ~0x1ffff) == 0 \ | |
3565 | ? 15 \ | |
3566 | : 14 \ | |
3567 | : ((v) & ~0x7ffff) == 0 \ | |
3568 | ? 13 \ | |
3569 | : 12 \ | |
3570 | : ((v) & ~0x3fffff) == 0 \ | |
3571 | ? ((v) & ~0x1fffff) == 0 \ | |
3572 | ? 11 \ | |
3573 | : 10 \ | |
3574 | : ((v) & ~0x7fffff) == 0 \ | |
3575 | ? 9 \ | |
3576 | : 8 \ | |
3577 | : ((v) & ~0xfffffff) == 0 \ | |
3578 | ? ((v) & ~0x3ffffff) == 0 \ | |
3579 | ? ((v) & ~0x1ffffff) == 0 \ | |
3580 | ? 7 \ | |
3581 | : 6 \ | |
3582 | : ((v) & ~0x7ffffff) == 0 \ | |
3583 | ? 5 \ | |
3584 | : 4 \ | |
3585 | : ((v) & ~0x3fffffff) == 0 \ | |
3586 | ? ((v) & ~0x1fffffff) == 0 \ | |
3587 | ? 3 \ | |
3588 | : 2 \ | |
3589 | : ((v) & ~0x7fffffff) == 0 \ | |
3590 | ? 1 \ | |
3591 | : 0) | |
3592 | ||
3593 | /* load_register() | |
67c1ffbe | 3594 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3595 | * an absolute expression value into a register. |
3596 | */ | |
3597 | static void | |
67c0d1eb | 3598 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3599 | { |
3600 | int freg; | |
3601 | expressionS hi32, lo32; | |
3602 | ||
3603 | if (ep->X_op != O_big) | |
3604 | { | |
3605 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3606 | |
3607 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3608 | if (!dbl) |
3609 | normalize_constant_expr (ep); | |
256ab948 TS |
3610 | |
3611 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3612 | { |
3613 | /* We can handle 16 bit signed values with an addiu to | |
3614 | $zero. No need to ever use daddiu here, since $zero and | |
3615 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3616 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3617 | return; |
3618 | } | |
3619 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3620 | { | |
3621 | /* We can handle 16 bit unsigned values with an ori to | |
3622 | $zero. */ | |
67c0d1eb | 3623 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3624 | return; |
3625 | } | |
256ab948 | 3626 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3627 | { |
3628 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3629 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3630 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3631 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3632 | return; |
3633 | } | |
3634 | } | |
3635 | ||
3636 | /* The value is larger than 32 bits. */ | |
3637 | ||
2051e8c4 | 3638 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3639 | { |
55e08f71 NC |
3640 | char value[32]; |
3641 | ||
3642 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3643 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3644 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3645 | return; |
3646 | } | |
3647 | ||
3648 | if (ep->X_op != O_big) | |
3649 | { | |
3650 | hi32 = *ep; | |
3651 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3652 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3653 | hi32.X_add_number &= 0xffffffff; | |
3654 | lo32 = *ep; | |
3655 | lo32.X_add_number &= 0xffffffff; | |
3656 | } | |
3657 | else | |
3658 | { | |
3659 | assert (ep->X_add_number > 2); | |
3660 | if (ep->X_add_number == 3) | |
3661 | generic_bignum[3] = 0; | |
3662 | else if (ep->X_add_number > 4) | |
3663 | as_bad (_("Number larger than 64 bits")); | |
3664 | lo32.X_op = O_constant; | |
3665 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3666 | hi32.X_op = O_constant; | |
3667 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3668 | } | |
3669 | ||
3670 | if (hi32.X_add_number == 0) | |
3671 | freg = 0; | |
3672 | else | |
3673 | { | |
3674 | int shift, bit; | |
3675 | unsigned long hi, lo; | |
3676 | ||
956cd1d6 | 3677 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3678 | { |
3679 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3680 | { | |
67c0d1eb | 3681 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3682 | return; |
3683 | } | |
3684 | if (lo32.X_add_number & 0x80000000) | |
3685 | { | |
67c0d1eb | 3686 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3687 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3688 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3689 | return; |
3690 | } | |
3691 | } | |
252b5132 RH |
3692 | |
3693 | /* Check for 16bit shifted constant. We know that hi32 is | |
3694 | non-zero, so start the mask on the first bit of the hi32 | |
3695 | value. */ | |
3696 | shift = 17; | |
3697 | do | |
beae10d5 KH |
3698 | { |
3699 | unsigned long himask, lomask; | |
3700 | ||
3701 | if (shift < 32) | |
3702 | { | |
3703 | himask = 0xffff >> (32 - shift); | |
3704 | lomask = (0xffff << shift) & 0xffffffff; | |
3705 | } | |
3706 | else | |
3707 | { | |
3708 | himask = 0xffff << (shift - 32); | |
3709 | lomask = 0; | |
3710 | } | |
3711 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3712 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3713 | { | |
3714 | expressionS tmp; | |
3715 | ||
3716 | tmp.X_op = O_constant; | |
3717 | if (shift < 32) | |
3718 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3719 | | (lo32.X_add_number >> shift)); | |
3720 | else | |
3721 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3722 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3723 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3724 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3725 | return; |
3726 | } | |
f9419b05 | 3727 | ++shift; |
beae10d5 KH |
3728 | } |
3729 | while (shift <= (64 - 16)); | |
252b5132 RH |
3730 | |
3731 | /* Find the bit number of the lowest one bit, and store the | |
3732 | shifted value in hi/lo. */ | |
3733 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3734 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3735 | if (lo != 0) | |
3736 | { | |
3737 | bit = 0; | |
3738 | while ((lo & 1) == 0) | |
3739 | { | |
3740 | lo >>= 1; | |
3741 | ++bit; | |
3742 | } | |
3743 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3744 | hi >>= bit; | |
3745 | } | |
3746 | else | |
3747 | { | |
3748 | bit = 32; | |
3749 | while ((hi & 1) == 0) | |
3750 | { | |
3751 | hi >>= 1; | |
3752 | ++bit; | |
3753 | } | |
3754 | lo = hi; | |
3755 | hi = 0; | |
3756 | } | |
3757 | ||
3758 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3759 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3760 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3761 | { |
3762 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3763 | if (shift != 0) |
beae10d5 | 3764 | { |
252b5132 RH |
3765 | expressionS tmp; |
3766 | ||
3767 | /* This instruction will set the register to be all | |
3768 | ones. */ | |
beae10d5 KH |
3769 | tmp.X_op = O_constant; |
3770 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3771 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3772 | if (bit != 0) |
3773 | { | |
3774 | bit += shift; | |
67c0d1eb RS |
3775 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3776 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3777 | } |
67c0d1eb RS |
3778 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3779 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3780 | return; |
3781 | } | |
3782 | } | |
252b5132 RH |
3783 | |
3784 | /* Sign extend hi32 before calling load_register, because we can | |
3785 | generally get better code when we load a sign extended value. */ | |
3786 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3787 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3788 | load_register (reg, &hi32, 0); |
252b5132 RH |
3789 | freg = reg; |
3790 | } | |
3791 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3792 | { | |
3793 | if (freg != 0) | |
3794 | { | |
67c0d1eb | 3795 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3796 | freg = reg; |
3797 | } | |
3798 | } | |
3799 | else | |
3800 | { | |
3801 | expressionS mid16; | |
3802 | ||
956cd1d6 | 3803 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3804 | { |
67c0d1eb RS |
3805 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3806 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3807 | return; |
3808 | } | |
252b5132 RH |
3809 | |
3810 | if (freg != 0) | |
3811 | { | |
67c0d1eb | 3812 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3813 | freg = reg; |
3814 | } | |
3815 | mid16 = lo32; | |
3816 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3817 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3818 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3819 | freg = reg; |
3820 | } | |
3821 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3822 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3823 | } |
3824 | ||
269137b2 TS |
3825 | static inline void |
3826 | load_delay_nop (void) | |
3827 | { | |
3828 | if (!gpr_interlocks) | |
3829 | macro_build (NULL, "nop", ""); | |
3830 | } | |
3831 | ||
252b5132 RH |
3832 | /* Load an address into a register. */ |
3833 | ||
3834 | static void | |
67c0d1eb | 3835 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3836 | { |
252b5132 RH |
3837 | if (ep->X_op != O_constant |
3838 | && ep->X_op != O_symbol) | |
3839 | { | |
3840 | as_bad (_("expression too complex")); | |
3841 | ep->X_op = O_constant; | |
3842 | } | |
3843 | ||
3844 | if (ep->X_op == O_constant) | |
3845 | { | |
67c0d1eb | 3846 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3847 | return; |
3848 | } | |
3849 | ||
3850 | if (mips_pic == NO_PIC) | |
3851 | { | |
3852 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3853 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3854 | Otherwise we want |
3855 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3856 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3857 | If we have an addend, we always use the latter form. |
76b3015f | 3858 | |
d6bc6245 TS |
3859 | With 64bit address space and a usable $at we want |
3860 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3861 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3862 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3863 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3864 | dsll32 $reg,0 | |
3a482fd5 | 3865 | daddu $reg,$reg,$at |
76b3015f | 3866 | |
c03099e6 | 3867 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3868 | on superscalar processors. |
3869 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3870 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3871 | dsll $reg,16 | |
3872 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3873 | dsll $reg,16 | |
3874 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3875 | |
3876 | For GP relative symbols in 64bit address space we can use | |
3877 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3878 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3879 | { |
6caf9ef4 TS |
3880 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3881 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3882 | { | |
3883 | relax_start (ep->X_add_symbol); | |
3884 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3885 | mips_gp_register, BFD_RELOC_GPREL16); | |
3886 | relax_switch (); | |
3887 | } | |
d6bc6245 | 3888 | |
b8285c27 | 3889 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3890 | { |
67c0d1eb RS |
3891 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3892 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3893 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3894 | BFD_RELOC_MIPS_HIGHER); | |
3895 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3896 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3897 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3898 | *used_at = 1; |
3899 | } | |
3900 | else | |
3901 | { | |
67c0d1eb RS |
3902 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3903 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3904 | BFD_RELOC_MIPS_HIGHER); | |
3905 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3906 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3907 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3908 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3909 | } |
6caf9ef4 TS |
3910 | |
3911 | if (mips_relax.sequence) | |
3912 | relax_end (); | |
d6bc6245 | 3913 | } |
252b5132 RH |
3914 | else |
3915 | { | |
d6bc6245 | 3916 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3917 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3918 | { |
4d7206a2 | 3919 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3920 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3921 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3922 | relax_switch (); |
d6bc6245 | 3923 | } |
67c0d1eb RS |
3924 | macro_build_lui (ep, reg); |
3925 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3926 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3927 | if (mips_relax.sequence) |
3928 | relax_end (); | |
d6bc6245 | 3929 | } |
252b5132 | 3930 | } |
0a44bf69 | 3931 | else if (!mips_big_got) |
252b5132 RH |
3932 | { |
3933 | expressionS ex; | |
3934 | ||
3935 | /* If this is a reference to an external symbol, we want | |
3936 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3937 | Otherwise we want | |
3938 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3939 | nop | |
3940 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3941 | If there is a constant, it must be added in after. |
3942 | ||
ed6fb7bd | 3943 | If we have NewABI, we want |
f5040a92 AO |
3944 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3945 | unless we're referencing a global symbol with a non-zero | |
3946 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3947 | if (HAVE_NEWABI) |
3948 | { | |
f5040a92 AO |
3949 | if (ep->X_add_number) |
3950 | { | |
4d7206a2 | 3951 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3952 | ep->X_add_number = 0; |
4d7206a2 | 3953 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3954 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3955 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3956 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3957 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3958 | ex.X_op = O_constant; | |
67c0d1eb | 3959 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3960 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3961 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3962 | relax_switch (); |
f5040a92 | 3963 | } |
67c0d1eb | 3964 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3965 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3966 | if (mips_relax.sequence) |
3967 | relax_end (); | |
ed6fb7bd SC |
3968 | } |
3969 | else | |
3970 | { | |
f5040a92 AO |
3971 | ex.X_add_number = ep->X_add_number; |
3972 | ep->X_add_number = 0; | |
67c0d1eb RS |
3973 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3974 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3975 | load_delay_nop (); |
4d7206a2 RS |
3976 | relax_start (ep->X_add_symbol); |
3977 | relax_switch (); | |
67c0d1eb | 3978 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3979 | BFD_RELOC_LO16); |
4d7206a2 | 3980 | relax_end (); |
ed6fb7bd | 3981 | |
f5040a92 AO |
3982 | if (ex.X_add_number != 0) |
3983 | { | |
3984 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3985 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3986 | ex.X_op = O_constant; | |
67c0d1eb | 3987 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3988 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3989 | } |
252b5132 RH |
3990 | } |
3991 | } | |
0a44bf69 | 3992 | else if (mips_big_got) |
252b5132 RH |
3993 | { |
3994 | expressionS ex; | |
252b5132 RH |
3995 | |
3996 | /* This is the large GOT case. If this is a reference to an | |
3997 | external symbol, we want | |
3998 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3999 | addu $reg,$reg,$gp | |
4000 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4001 | |
4002 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4003 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4004 | nop | |
4005 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4006 | If there is a constant, it must be added in after. |
f5040a92 AO |
4007 | |
4008 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4009 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4010 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4011 | */ |
438c16b8 TS |
4012 | if (HAVE_NEWABI) |
4013 | { | |
4d7206a2 | 4014 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4015 | ep->X_add_number = 0; |
4d7206a2 | 4016 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4017 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4018 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4019 | reg, reg, mips_gp_register); | |
4020 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4021 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4022 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4023 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4024 | else if (ex.X_add_number) | |
4025 | { | |
4026 | ex.X_op = O_constant; | |
67c0d1eb RS |
4027 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4028 | BFD_RELOC_LO16); | |
f5040a92 AO |
4029 | } |
4030 | ||
4031 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4032 | relax_switch (); |
67c0d1eb | 4033 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4034 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4035 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4036 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4037 | relax_end (); |
438c16b8 | 4038 | } |
252b5132 | 4039 | else |
438c16b8 | 4040 | { |
f5040a92 AO |
4041 | ex.X_add_number = ep->X_add_number; |
4042 | ep->X_add_number = 0; | |
4d7206a2 | 4043 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4044 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4045 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4046 | reg, reg, mips_gp_register); | |
4047 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4048 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4049 | relax_switch (); |
4050 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4051 | { |
4052 | /* We need a nop before loading from $gp. This special | |
4053 | check is required because the lui which starts the main | |
4054 | instruction stream does not refer to $gp, and so will not | |
4055 | insert the nop which may be required. */ | |
67c0d1eb | 4056 | macro_build (NULL, "nop", ""); |
438c16b8 | 4057 | } |
67c0d1eb | 4058 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4059 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4060 | load_delay_nop (); |
67c0d1eb | 4061 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4062 | BFD_RELOC_LO16); |
4d7206a2 | 4063 | relax_end (); |
438c16b8 | 4064 | |
f5040a92 AO |
4065 | if (ex.X_add_number != 0) |
4066 | { | |
4067 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4068 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4069 | ex.X_op = O_constant; | |
67c0d1eb RS |
4070 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4071 | BFD_RELOC_LO16); | |
f5040a92 | 4072 | } |
252b5132 RH |
4073 | } |
4074 | } | |
252b5132 RH |
4075 | else |
4076 | abort (); | |
8fc2e39e TS |
4077 | |
4078 | if (mips_opts.noat && *used_at == 1) | |
4079 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4080 | } |
4081 | ||
ea1fb5dc RS |
4082 | /* Move the contents of register SOURCE into register DEST. */ |
4083 | ||
4084 | static void | |
67c0d1eb | 4085 | move_register (int dest, int source) |
ea1fb5dc | 4086 | { |
67c0d1eb RS |
4087 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4088 | dest, source, 0); | |
ea1fb5dc RS |
4089 | } |
4090 | ||
4d7206a2 | 4091 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4092 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4093 | The two alternatives are: | |
4d7206a2 RS |
4094 | |
4095 | Global symbol Local sybmol | |
4096 | ------------- ------------ | |
4097 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4098 | ... ... | |
4099 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4100 | ||
4101 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4102 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4103 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4104 | |
4105 | static void | |
67c0d1eb | 4106 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4107 | { |
4108 | expressionS global; | |
4109 | ||
4110 | global = *local; | |
4111 | global.X_add_number = 0; | |
4112 | ||
4113 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4114 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4115 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4116 | relax_switch (); |
67c0d1eb RS |
4117 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4118 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4119 | relax_end (); |
4120 | } | |
4121 | ||
4122 | static void | |
67c0d1eb | 4123 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4124 | { |
4125 | expressionS global; | |
4126 | ||
4127 | global.X_op = O_constant; | |
4128 | global.X_op_symbol = NULL; | |
4129 | global.X_add_symbol = NULL; | |
4130 | global.X_add_number = local->X_add_number; | |
4131 | ||
4132 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4133 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4134 | dest, dest, BFD_RELOC_LO16); |
4135 | relax_switch (); | |
67c0d1eb | 4136 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4137 | relax_end (); |
4138 | } | |
4139 | ||
f6a22291 MR |
4140 | static void |
4141 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4142 | { | |
4143 | expressionS global; | |
4144 | int hold_mips_optimize; | |
4145 | ||
4146 | global.X_op = O_constant; | |
4147 | global.X_op_symbol = NULL; | |
4148 | global.X_add_symbol = NULL; | |
4149 | global.X_add_number = local->X_add_number; | |
4150 | ||
4151 | relax_start (local->X_add_symbol); | |
4152 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4153 | relax_switch (); | |
4154 | /* Set mips_optimize around the lui instruction to avoid | |
4155 | inserting an unnecessary nop after the lw. */ | |
4156 | hold_mips_optimize = mips_optimize; | |
4157 | mips_optimize = 2; | |
4158 | macro_build_lui (&global, tmp); | |
4159 | mips_optimize = hold_mips_optimize; | |
4160 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4161 | relax_end (); | |
4162 | ||
4163 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4164 | } | |
4165 | ||
252b5132 RH |
4166 | /* |
4167 | * Build macros | |
4168 | * This routine implements the seemingly endless macro or synthesized | |
4169 | * instructions and addressing modes in the mips assembly language. Many | |
4170 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4171 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4172 | * this verbose method. Others are not simple macros but are more like |
4173 | * optimizing code generation. | |
4174 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4175 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4176 | * The ensuing load upper instructions are ommited. This implies some kind |
4177 | * of global optimization. We currently only optimize within a single macro. | |
4178 | * For many of the load and store macros if the address is specified as a | |
4179 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4180 | * first load register 'at' with zero and use it as the base register. The | |
4181 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4182 | * we're missing. | |
4183 | */ | |
4184 | static void | |
17a2f251 | 4185 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4186 | { |
4187 | register int treg, sreg, dreg, breg; | |
4188 | int tempreg; | |
4189 | int mask; | |
43841e91 | 4190 | int used_at = 0; |
252b5132 RH |
4191 | expressionS expr1; |
4192 | const char *s; | |
4193 | const char *s2; | |
4194 | const char *fmt; | |
4195 | int likely = 0; | |
4196 | int dbl = 0; | |
4197 | int coproc = 0; | |
4198 | int lr = 0; | |
4199 | int imm = 0; | |
1abe91b1 | 4200 | int call = 0; |
252b5132 | 4201 | int off; |
67c0d1eb | 4202 | offsetT maxnum; |
252b5132 | 4203 | bfd_reloc_code_real_type r; |
252b5132 RH |
4204 | int hold_mips_optimize; |
4205 | ||
4206 | assert (! mips_opts.mips16); | |
4207 | ||
4208 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4209 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4210 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4211 | mask = ip->insn_mo->mask; | |
4212 | ||
4213 | expr1.X_op = O_constant; | |
4214 | expr1.X_op_symbol = NULL; | |
4215 | expr1.X_add_symbol = NULL; | |
4216 | expr1.X_add_number = 1; | |
4217 | ||
4218 | switch (mask) | |
4219 | { | |
4220 | case M_DABS: | |
4221 | dbl = 1; | |
4222 | case M_ABS: | |
4223 | /* bgez $a0,.+12 | |
4224 | move v0,$a0 | |
4225 | sub v0,$zero,$a0 | |
4226 | */ | |
4227 | ||
7d10b47d | 4228 | start_noreorder (); |
252b5132 RH |
4229 | |
4230 | expr1.X_add_number = 8; | |
67c0d1eb | 4231 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4232 | if (dreg == sreg) |
67c0d1eb | 4233 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4234 | else |
67c0d1eb RS |
4235 | move_register (dreg, sreg); |
4236 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4237 | |
7d10b47d | 4238 | end_noreorder (); |
8fc2e39e | 4239 | break; |
252b5132 RH |
4240 | |
4241 | case M_ADD_I: | |
4242 | s = "addi"; | |
4243 | s2 = "add"; | |
4244 | goto do_addi; | |
4245 | case M_ADDU_I: | |
4246 | s = "addiu"; | |
4247 | s2 = "addu"; | |
4248 | goto do_addi; | |
4249 | case M_DADD_I: | |
4250 | dbl = 1; | |
4251 | s = "daddi"; | |
4252 | s2 = "dadd"; | |
4253 | goto do_addi; | |
4254 | case M_DADDU_I: | |
4255 | dbl = 1; | |
4256 | s = "daddiu"; | |
4257 | s2 = "daddu"; | |
4258 | do_addi: | |
4259 | if (imm_expr.X_op == O_constant | |
4260 | && imm_expr.X_add_number >= -0x8000 | |
4261 | && imm_expr.X_add_number < 0x8000) | |
4262 | { | |
67c0d1eb | 4263 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4264 | break; |
252b5132 | 4265 | } |
8fc2e39e | 4266 | used_at = 1; |
67c0d1eb RS |
4267 | load_register (AT, &imm_expr, dbl); |
4268 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4269 | break; |
4270 | ||
4271 | case M_AND_I: | |
4272 | s = "andi"; | |
4273 | s2 = "and"; | |
4274 | goto do_bit; | |
4275 | case M_OR_I: | |
4276 | s = "ori"; | |
4277 | s2 = "or"; | |
4278 | goto do_bit; | |
4279 | case M_NOR_I: | |
4280 | s = ""; | |
4281 | s2 = "nor"; | |
4282 | goto do_bit; | |
4283 | case M_XOR_I: | |
4284 | s = "xori"; | |
4285 | s2 = "xor"; | |
4286 | do_bit: | |
4287 | if (imm_expr.X_op == O_constant | |
4288 | && imm_expr.X_add_number >= 0 | |
4289 | && imm_expr.X_add_number < 0x10000) | |
4290 | { | |
4291 | if (mask != M_NOR_I) | |
67c0d1eb | 4292 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4293 | else |
4294 | { | |
67c0d1eb RS |
4295 | macro_build (&imm_expr, "ori", "t,r,i", |
4296 | treg, sreg, BFD_RELOC_LO16); | |
4297 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4298 | } |
8fc2e39e | 4299 | break; |
252b5132 RH |
4300 | } |
4301 | ||
8fc2e39e | 4302 | used_at = 1; |
67c0d1eb RS |
4303 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4304 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4305 | break; |
4306 | ||
4307 | case M_BEQ_I: | |
4308 | s = "beq"; | |
4309 | goto beq_i; | |
4310 | case M_BEQL_I: | |
4311 | s = "beql"; | |
4312 | likely = 1; | |
4313 | goto beq_i; | |
4314 | case M_BNE_I: | |
4315 | s = "bne"; | |
4316 | goto beq_i; | |
4317 | case M_BNEL_I: | |
4318 | s = "bnel"; | |
4319 | likely = 1; | |
4320 | beq_i: | |
4321 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4322 | { | |
67c0d1eb | 4323 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4324 | break; |
252b5132 | 4325 | } |
8fc2e39e | 4326 | used_at = 1; |
67c0d1eb RS |
4327 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4328 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4329 | break; |
4330 | ||
4331 | case M_BGEL: | |
4332 | likely = 1; | |
4333 | case M_BGE: | |
4334 | if (treg == 0) | |
4335 | { | |
67c0d1eb | 4336 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4337 | break; |
252b5132 RH |
4338 | } |
4339 | if (sreg == 0) | |
4340 | { | |
67c0d1eb | 4341 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4342 | break; |
252b5132 | 4343 | } |
8fc2e39e | 4344 | used_at = 1; |
67c0d1eb RS |
4345 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4346 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4347 | break; |
4348 | ||
4349 | case M_BGTL_I: | |
4350 | likely = 1; | |
4351 | case M_BGT_I: | |
4352 | /* check for > max integer */ | |
4353 | maxnum = 0x7fffffff; | |
ca4e0257 | 4354 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4355 | { |
4356 | maxnum <<= 16; | |
4357 | maxnum |= 0xffff; | |
4358 | maxnum <<= 16; | |
4359 | maxnum |= 0xffff; | |
4360 | } | |
4361 | if (imm_expr.X_op == O_constant | |
4362 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4363 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4364 | { |
4365 | do_false: | |
4366 | /* result is always false */ | |
4367 | if (! likely) | |
67c0d1eb | 4368 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4369 | else |
67c0d1eb | 4370 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4371 | break; |
252b5132 RH |
4372 | } |
4373 | if (imm_expr.X_op != O_constant) | |
4374 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4375 | ++imm_expr.X_add_number; |
252b5132 RH |
4376 | /* FALLTHROUGH */ |
4377 | case M_BGE_I: | |
4378 | case M_BGEL_I: | |
4379 | if (mask == M_BGEL_I) | |
4380 | likely = 1; | |
4381 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4382 | { | |
67c0d1eb | 4383 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4384 | break; |
252b5132 RH |
4385 | } |
4386 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4387 | { | |
67c0d1eb | 4388 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4389 | break; |
252b5132 RH |
4390 | } |
4391 | maxnum = 0x7fffffff; | |
ca4e0257 | 4392 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4393 | { |
4394 | maxnum <<= 16; | |
4395 | maxnum |= 0xffff; | |
4396 | maxnum <<= 16; | |
4397 | maxnum |= 0xffff; | |
4398 | } | |
4399 | maxnum = - maxnum - 1; | |
4400 | if (imm_expr.X_op == O_constant | |
4401 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4402 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4403 | { |
4404 | do_true: | |
4405 | /* result is always true */ | |
4406 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4407 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4408 | break; |
252b5132 | 4409 | } |
8fc2e39e | 4410 | used_at = 1; |
67c0d1eb RS |
4411 | set_at (sreg, 0); |
4412 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4413 | break; |
4414 | ||
4415 | case M_BGEUL: | |
4416 | likely = 1; | |
4417 | case M_BGEU: | |
4418 | if (treg == 0) | |
4419 | goto do_true; | |
4420 | if (sreg == 0) | |
4421 | { | |
67c0d1eb | 4422 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4423 | "s,t,p", 0, treg); |
8fc2e39e | 4424 | break; |
252b5132 | 4425 | } |
8fc2e39e | 4426 | used_at = 1; |
67c0d1eb RS |
4427 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4428 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4429 | break; |
4430 | ||
4431 | case M_BGTUL_I: | |
4432 | likely = 1; | |
4433 | case M_BGTU_I: | |
4434 | if (sreg == 0 | |
ca4e0257 | 4435 | || (HAVE_32BIT_GPRS |
252b5132 | 4436 | && imm_expr.X_op == O_constant |
956cd1d6 | 4437 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4438 | goto do_false; |
4439 | if (imm_expr.X_op != O_constant) | |
4440 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4441 | ++imm_expr.X_add_number; |
252b5132 RH |
4442 | /* FALLTHROUGH */ |
4443 | case M_BGEU_I: | |
4444 | case M_BGEUL_I: | |
4445 | if (mask == M_BGEUL_I) | |
4446 | likely = 1; | |
4447 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4448 | goto do_true; | |
4449 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4450 | { | |
67c0d1eb | 4451 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4452 | "s,t,p", sreg, 0); |
8fc2e39e | 4453 | break; |
252b5132 | 4454 | } |
8fc2e39e | 4455 | used_at = 1; |
67c0d1eb RS |
4456 | set_at (sreg, 1); |
4457 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4458 | break; |
4459 | ||
4460 | case M_BGTL: | |
4461 | likely = 1; | |
4462 | case M_BGT: | |
4463 | if (treg == 0) | |
4464 | { | |
67c0d1eb | 4465 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4466 | break; |
252b5132 RH |
4467 | } |
4468 | if (sreg == 0) | |
4469 | { | |
67c0d1eb | 4470 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4471 | break; |
252b5132 | 4472 | } |
8fc2e39e | 4473 | used_at = 1; |
67c0d1eb RS |
4474 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4475 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4476 | break; |
4477 | ||
4478 | case M_BGTUL: | |
4479 | likely = 1; | |
4480 | case M_BGTU: | |
4481 | if (treg == 0) | |
4482 | { | |
67c0d1eb | 4483 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4484 | "s,t,p", sreg, 0); |
8fc2e39e | 4485 | break; |
252b5132 RH |
4486 | } |
4487 | if (sreg == 0) | |
4488 | goto do_false; | |
8fc2e39e | 4489 | used_at = 1; |
67c0d1eb RS |
4490 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4491 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4492 | break; |
4493 | ||
4494 | case M_BLEL: | |
4495 | likely = 1; | |
4496 | case M_BLE: | |
4497 | if (treg == 0) | |
4498 | { | |
67c0d1eb | 4499 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4500 | break; |
252b5132 RH |
4501 | } |
4502 | if (sreg == 0) | |
4503 | { | |
67c0d1eb | 4504 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4505 | break; |
252b5132 | 4506 | } |
8fc2e39e | 4507 | used_at = 1; |
67c0d1eb RS |
4508 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4509 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4510 | break; |
4511 | ||
4512 | case M_BLEL_I: | |
4513 | likely = 1; | |
4514 | case M_BLE_I: | |
4515 | maxnum = 0x7fffffff; | |
ca4e0257 | 4516 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4517 | { |
4518 | maxnum <<= 16; | |
4519 | maxnum |= 0xffff; | |
4520 | maxnum <<= 16; | |
4521 | maxnum |= 0xffff; | |
4522 | } | |
4523 | if (imm_expr.X_op == O_constant | |
4524 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4525 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4526 | goto do_true; |
4527 | if (imm_expr.X_op != O_constant) | |
4528 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4529 | ++imm_expr.X_add_number; |
252b5132 RH |
4530 | /* FALLTHROUGH */ |
4531 | case M_BLT_I: | |
4532 | case M_BLTL_I: | |
4533 | if (mask == M_BLTL_I) | |
4534 | likely = 1; | |
4535 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4536 | { | |
67c0d1eb | 4537 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4538 | break; |
252b5132 RH |
4539 | } |
4540 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4541 | { | |
67c0d1eb | 4542 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4543 | break; |
252b5132 | 4544 | } |
8fc2e39e | 4545 | used_at = 1; |
67c0d1eb RS |
4546 | set_at (sreg, 0); |
4547 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4548 | break; |
4549 | ||
4550 | case M_BLEUL: | |
4551 | likely = 1; | |
4552 | case M_BLEU: | |
4553 | if (treg == 0) | |
4554 | { | |
67c0d1eb | 4555 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4556 | "s,t,p", sreg, 0); |
8fc2e39e | 4557 | break; |
252b5132 RH |
4558 | } |
4559 | if (sreg == 0) | |
4560 | goto do_true; | |
8fc2e39e | 4561 | used_at = 1; |
67c0d1eb RS |
4562 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4563 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4564 | break; |
4565 | ||
4566 | case M_BLEUL_I: | |
4567 | likely = 1; | |
4568 | case M_BLEU_I: | |
4569 | if (sreg == 0 | |
ca4e0257 | 4570 | || (HAVE_32BIT_GPRS |
252b5132 | 4571 | && imm_expr.X_op == O_constant |
956cd1d6 | 4572 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4573 | goto do_true; |
4574 | if (imm_expr.X_op != O_constant) | |
4575 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4576 | ++imm_expr.X_add_number; |
252b5132 RH |
4577 | /* FALLTHROUGH */ |
4578 | case M_BLTU_I: | |
4579 | case M_BLTUL_I: | |
4580 | if (mask == M_BLTUL_I) | |
4581 | likely = 1; | |
4582 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4583 | goto do_false; | |
4584 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4585 | { | |
67c0d1eb | 4586 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4587 | "s,t,p", sreg, 0); |
8fc2e39e | 4588 | break; |
252b5132 | 4589 | } |
8fc2e39e | 4590 | used_at = 1; |
67c0d1eb RS |
4591 | set_at (sreg, 1); |
4592 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4593 | break; |
4594 | ||
4595 | case M_BLTL: | |
4596 | likely = 1; | |
4597 | case M_BLT: | |
4598 | if (treg == 0) | |
4599 | { | |
67c0d1eb | 4600 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4601 | break; |
252b5132 RH |
4602 | } |
4603 | if (sreg == 0) | |
4604 | { | |
67c0d1eb | 4605 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4606 | break; |
252b5132 | 4607 | } |
8fc2e39e | 4608 | used_at = 1; |
67c0d1eb RS |
4609 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4610 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4611 | break; |
4612 | ||
4613 | case M_BLTUL: | |
4614 | likely = 1; | |
4615 | case M_BLTU: | |
4616 | if (treg == 0) | |
4617 | goto do_false; | |
4618 | if (sreg == 0) | |
4619 | { | |
67c0d1eb | 4620 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4621 | "s,t,p", 0, treg); |
8fc2e39e | 4622 | break; |
252b5132 | 4623 | } |
8fc2e39e | 4624 | used_at = 1; |
67c0d1eb RS |
4625 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4626 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4627 | break; |
4628 | ||
5f74bc13 CD |
4629 | case M_DEXT: |
4630 | { | |
4631 | unsigned long pos; | |
4632 | unsigned long size; | |
4633 | ||
4634 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4635 | { | |
4636 | as_bad (_("Unsupported large constant")); | |
4637 | pos = size = 1; | |
4638 | } | |
4639 | else | |
4640 | { | |
4641 | pos = (unsigned long) imm_expr.X_add_number; | |
4642 | size = (unsigned long) imm2_expr.X_add_number; | |
4643 | } | |
4644 | ||
4645 | if (pos > 63) | |
4646 | { | |
4647 | as_bad (_("Improper position (%lu)"), pos); | |
4648 | pos = 1; | |
4649 | } | |
4650 | if (size == 0 || size > 64 | |
4651 | || (pos + size - 1) > 63) | |
4652 | { | |
4653 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4654 | size, pos); | |
4655 | size = 1; | |
4656 | } | |
4657 | ||
4658 | if (size <= 32 && pos < 32) | |
4659 | { | |
4660 | s = "dext"; | |
4661 | fmt = "t,r,+A,+C"; | |
4662 | } | |
4663 | else if (size <= 32) | |
4664 | { | |
4665 | s = "dextu"; | |
4666 | fmt = "t,r,+E,+H"; | |
4667 | } | |
4668 | else | |
4669 | { | |
4670 | s = "dextm"; | |
4671 | fmt = "t,r,+A,+G"; | |
4672 | } | |
67c0d1eb | 4673 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4674 | } |
8fc2e39e | 4675 | break; |
5f74bc13 CD |
4676 | |
4677 | case M_DINS: | |
4678 | { | |
4679 | unsigned long pos; | |
4680 | unsigned long size; | |
4681 | ||
4682 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4683 | { | |
4684 | as_bad (_("Unsupported large constant")); | |
4685 | pos = size = 1; | |
4686 | } | |
4687 | else | |
4688 | { | |
4689 | pos = (unsigned long) imm_expr.X_add_number; | |
4690 | size = (unsigned long) imm2_expr.X_add_number; | |
4691 | } | |
4692 | ||
4693 | if (pos > 63) | |
4694 | { | |
4695 | as_bad (_("Improper position (%lu)"), pos); | |
4696 | pos = 1; | |
4697 | } | |
4698 | if (size == 0 || size > 64 | |
4699 | || (pos + size - 1) > 63) | |
4700 | { | |
4701 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4702 | size, pos); | |
4703 | size = 1; | |
4704 | } | |
4705 | ||
4706 | if (pos < 32 && (pos + size - 1) < 32) | |
4707 | { | |
4708 | s = "dins"; | |
4709 | fmt = "t,r,+A,+B"; | |
4710 | } | |
4711 | else if (pos >= 32) | |
4712 | { | |
4713 | s = "dinsu"; | |
4714 | fmt = "t,r,+E,+F"; | |
4715 | } | |
4716 | else | |
4717 | { | |
4718 | s = "dinsm"; | |
4719 | fmt = "t,r,+A,+F"; | |
4720 | } | |
67c0d1eb RS |
4721 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4722 | pos + size - 1); | |
5f74bc13 | 4723 | } |
8fc2e39e | 4724 | break; |
5f74bc13 | 4725 | |
252b5132 RH |
4726 | case M_DDIV_3: |
4727 | dbl = 1; | |
4728 | case M_DIV_3: | |
4729 | s = "mflo"; | |
4730 | goto do_div3; | |
4731 | case M_DREM_3: | |
4732 | dbl = 1; | |
4733 | case M_REM_3: | |
4734 | s = "mfhi"; | |
4735 | do_div3: | |
4736 | if (treg == 0) | |
4737 | { | |
4738 | as_warn (_("Divide by zero.")); | |
4739 | if (mips_trap) | |
67c0d1eb | 4740 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4741 | else |
67c0d1eb | 4742 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4743 | break; |
252b5132 RH |
4744 | } |
4745 | ||
7d10b47d | 4746 | start_noreorder (); |
252b5132 RH |
4747 | if (mips_trap) |
4748 | { | |
67c0d1eb RS |
4749 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4750 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4751 | } |
4752 | else | |
4753 | { | |
4754 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4755 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4756 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4757 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4758 | } |
4759 | expr1.X_add_number = -1; | |
8fc2e39e | 4760 | used_at = 1; |
f6a22291 | 4761 | load_register (AT, &expr1, dbl); |
252b5132 | 4762 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4763 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4764 | if (dbl) |
4765 | { | |
4766 | expr1.X_add_number = 1; | |
f6a22291 | 4767 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4768 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4769 | } |
4770 | else | |
4771 | { | |
4772 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4773 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4774 | } |
4775 | if (mips_trap) | |
4776 | { | |
67c0d1eb | 4777 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4778 | /* We want to close the noreorder block as soon as possible, so |
4779 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4780 | end_noreorder (); |
252b5132 RH |
4781 | } |
4782 | else | |
4783 | { | |
4784 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4785 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4786 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4787 | |
4788 | /* We want to close the noreorder block as soon as possible, so | |
4789 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4790 | end_noreorder (); |
252b5132 | 4791 | |
67c0d1eb | 4792 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4793 | } |
67c0d1eb | 4794 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4795 | break; |
4796 | ||
4797 | case M_DIV_3I: | |
4798 | s = "div"; | |
4799 | s2 = "mflo"; | |
4800 | goto do_divi; | |
4801 | case M_DIVU_3I: | |
4802 | s = "divu"; | |
4803 | s2 = "mflo"; | |
4804 | goto do_divi; | |
4805 | case M_REM_3I: | |
4806 | s = "div"; | |
4807 | s2 = "mfhi"; | |
4808 | goto do_divi; | |
4809 | case M_REMU_3I: | |
4810 | s = "divu"; | |
4811 | s2 = "mfhi"; | |
4812 | goto do_divi; | |
4813 | case M_DDIV_3I: | |
4814 | dbl = 1; | |
4815 | s = "ddiv"; | |
4816 | s2 = "mflo"; | |
4817 | goto do_divi; | |
4818 | case M_DDIVU_3I: | |
4819 | dbl = 1; | |
4820 | s = "ddivu"; | |
4821 | s2 = "mflo"; | |
4822 | goto do_divi; | |
4823 | case M_DREM_3I: | |
4824 | dbl = 1; | |
4825 | s = "ddiv"; | |
4826 | s2 = "mfhi"; | |
4827 | goto do_divi; | |
4828 | case M_DREMU_3I: | |
4829 | dbl = 1; | |
4830 | s = "ddivu"; | |
4831 | s2 = "mfhi"; | |
4832 | do_divi: | |
4833 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4834 | { | |
4835 | as_warn (_("Divide by zero.")); | |
4836 | if (mips_trap) | |
67c0d1eb | 4837 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4838 | else |
67c0d1eb | 4839 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4840 | break; |
252b5132 RH |
4841 | } |
4842 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4843 | { | |
4844 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4845 | move_register (dreg, sreg); |
252b5132 | 4846 | else |
67c0d1eb | 4847 | move_register (dreg, 0); |
8fc2e39e | 4848 | break; |
252b5132 RH |
4849 | } |
4850 | if (imm_expr.X_op == O_constant | |
4851 | && imm_expr.X_add_number == -1 | |
4852 | && s[strlen (s) - 1] != 'u') | |
4853 | { | |
4854 | if (strcmp (s2, "mflo") == 0) | |
4855 | { | |
67c0d1eb | 4856 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4857 | } |
4858 | else | |
67c0d1eb | 4859 | move_register (dreg, 0); |
8fc2e39e | 4860 | break; |
252b5132 RH |
4861 | } |
4862 | ||
8fc2e39e | 4863 | used_at = 1; |
67c0d1eb RS |
4864 | load_register (AT, &imm_expr, dbl); |
4865 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4866 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4867 | break; |
4868 | ||
4869 | case M_DIVU_3: | |
4870 | s = "divu"; | |
4871 | s2 = "mflo"; | |
4872 | goto do_divu3; | |
4873 | case M_REMU_3: | |
4874 | s = "divu"; | |
4875 | s2 = "mfhi"; | |
4876 | goto do_divu3; | |
4877 | case M_DDIVU_3: | |
4878 | s = "ddivu"; | |
4879 | s2 = "mflo"; | |
4880 | goto do_divu3; | |
4881 | case M_DREMU_3: | |
4882 | s = "ddivu"; | |
4883 | s2 = "mfhi"; | |
4884 | do_divu3: | |
7d10b47d | 4885 | start_noreorder (); |
252b5132 RH |
4886 | if (mips_trap) |
4887 | { | |
67c0d1eb RS |
4888 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4889 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4890 | /* We want to close the noreorder block as soon as possible, so |
4891 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4892 | end_noreorder (); |
252b5132 RH |
4893 | } |
4894 | else | |
4895 | { | |
4896 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4897 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4898 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4899 | |
4900 | /* We want to close the noreorder block as soon as possible, so | |
4901 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4902 | end_noreorder (); |
67c0d1eb | 4903 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4904 | } |
67c0d1eb | 4905 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4906 | break; |
252b5132 | 4907 | |
1abe91b1 MR |
4908 | case M_DLCA_AB: |
4909 | dbl = 1; | |
4910 | case M_LCA_AB: | |
4911 | call = 1; | |
4912 | goto do_la; | |
252b5132 RH |
4913 | case M_DLA_AB: |
4914 | dbl = 1; | |
4915 | case M_LA_AB: | |
1abe91b1 | 4916 | do_la: |
252b5132 RH |
4917 | /* Load the address of a symbol into a register. If breg is not |
4918 | zero, we then add a base register to it. */ | |
4919 | ||
3bec30a8 TS |
4920 | if (dbl && HAVE_32BIT_GPRS) |
4921 | as_warn (_("dla used to load 32-bit register")); | |
4922 | ||
c90bbe5b | 4923 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4924 | as_warn (_("la used to load 64-bit address")); |
4925 | ||
0c11417f MR |
4926 | if (offset_expr.X_op == O_constant |
4927 | && offset_expr.X_add_number >= -0x8000 | |
4928 | && offset_expr.X_add_number < 0x8000) | |
4929 | { | |
aed1a261 | 4930 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4931 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4932 | break; |
0c11417f MR |
4933 | } |
4934 | ||
b8285c27 | 4935 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4936 | { |
4937 | tempreg = AT; | |
4938 | used_at = 1; | |
4939 | } | |
4940 | else | |
4941 | { | |
4942 | tempreg = treg; | |
afdbd6d0 CD |
4943 | } |
4944 | ||
252b5132 RH |
4945 | if (offset_expr.X_op != O_symbol |
4946 | && offset_expr.X_op != O_constant) | |
4947 | { | |
4948 | as_bad (_("expression too complex")); | |
4949 | offset_expr.X_op = O_constant; | |
4950 | } | |
4951 | ||
252b5132 | 4952 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4953 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4954 | else if (mips_pic == NO_PIC) |
4955 | { | |
d6bc6245 | 4956 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4957 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4958 | Otherwise we want |
4959 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4960 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4961 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4962 | so we may as well always use the latter form. |
76b3015f | 4963 | |
6caf9ef4 TS |
4964 | With 64bit address space and a usable $at we want |
4965 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4966 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4967 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4968 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4969 | dsll32 $tempreg,0 | |
4970 | daddu $tempreg,$tempreg,$at | |
4971 | ||
4972 | If $at is already in use, we use a path which is suboptimal | |
4973 | on superscalar processors. | |
4974 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4975 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4976 | dsll $tempreg,16 | |
4977 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4978 | dsll $tempreg,16 | |
4979 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4980 | ||
4981 | For GP relative symbols in 64bit address space we can use | |
4982 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4983 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4984 | { |
6caf9ef4 TS |
4985 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4986 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4987 | { | |
4988 | relax_start (offset_expr.X_add_symbol); | |
4989 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4990 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4991 | relax_switch (); | |
4992 | } | |
d6bc6245 | 4993 | |
b8285c27 | 4994 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4995 | { |
67c0d1eb | 4996 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4997 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4998 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4999 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5000 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5001 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5002 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5003 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5004 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5005 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5006 | used_at = 1; |
5007 | } | |
5008 | else | |
5009 | { | |
67c0d1eb | 5010 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5011 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5012 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5013 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5014 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5015 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5016 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5017 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5018 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5019 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5020 | } |
6caf9ef4 TS |
5021 | |
5022 | if (mips_relax.sequence) | |
5023 | relax_end (); | |
98d3f06f KH |
5024 | } |
5025 | else | |
5026 | { | |
5027 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5028 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5029 | { |
4d7206a2 | 5030 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5031 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5032 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5033 | relax_switch (); |
98d3f06f | 5034 | } |
6943caf0 ILT |
5035 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5036 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5037 | macro_build_lui (&offset_expr, tempreg); |
5038 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5039 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5040 | if (mips_relax.sequence) |
5041 | relax_end (); | |
98d3f06f | 5042 | } |
252b5132 | 5043 | } |
0a44bf69 | 5044 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5045 | { |
9117d219 NC |
5046 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5047 | ||
252b5132 RH |
5048 | /* If this is a reference to an external symbol, and there |
5049 | is no constant, we want | |
5050 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5051 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5052 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5053 | For a local symbol, we want |
5054 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5055 | nop | |
5056 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5057 | ||
5058 | If we have a small constant, and this is a reference to | |
5059 | an external symbol, we want | |
5060 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5061 | nop | |
5062 | addiu $tempreg,$tempreg,<constant> | |
5063 | For a local symbol, we want the same instruction | |
5064 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5065 | addiu instruction. | |
5066 | ||
5067 | If we have a large constant, and this is a reference to | |
5068 | an external symbol, we want | |
5069 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5070 | lui $at,<hiconstant> | |
5071 | addiu $at,$at,<loconstant> | |
5072 | addu $tempreg,$tempreg,$at | |
5073 | For a local symbol, we want the same instruction | |
5074 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5075 | addiu instruction. |
ed6fb7bd SC |
5076 | */ |
5077 | ||
4d7206a2 | 5078 | if (offset_expr.X_add_number == 0) |
252b5132 | 5079 | { |
0a44bf69 RS |
5080 | if (mips_pic == SVR4_PIC |
5081 | && breg == 0 | |
5082 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5083 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5084 | ||
5085 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5086 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5087 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5088 | if (breg != 0) |
252b5132 RH |
5089 | { |
5090 | /* We're going to put in an addu instruction using | |
5091 | tempreg, so we may as well insert the nop right | |
5092 | now. */ | |
269137b2 | 5093 | load_delay_nop (); |
252b5132 | 5094 | } |
4d7206a2 | 5095 | relax_switch (); |
67c0d1eb RS |
5096 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5097 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5098 | load_delay_nop (); |
67c0d1eb RS |
5099 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5100 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5101 | relax_end (); |
252b5132 RH |
5102 | /* FIXME: If breg == 0, and the next instruction uses |
5103 | $tempreg, then if this variant case is used an extra | |
5104 | nop will be generated. */ | |
5105 | } | |
4d7206a2 RS |
5106 | else if (offset_expr.X_add_number >= -0x8000 |
5107 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5108 | { |
67c0d1eb | 5109 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5110 | load_delay_nop (); |
67c0d1eb | 5111 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5112 | } |
5113 | else | |
5114 | { | |
4d7206a2 RS |
5115 | expr1.X_add_number = offset_expr.X_add_number; |
5116 | offset_expr.X_add_number = | |
5117 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5118 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5119 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5120 | /* If we are going to add in a base register, and the |
5121 | target register and the base register are the same, | |
5122 | then we are using AT as a temporary register. Since | |
5123 | we want to load the constant into AT, we add our | |
5124 | current AT (from the global offset table) and the | |
5125 | register into the register now, and pretend we were | |
5126 | not using a base register. */ | |
67c0d1eb | 5127 | if (breg == treg) |
252b5132 | 5128 | { |
269137b2 | 5129 | load_delay_nop (); |
67c0d1eb | 5130 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5131 | treg, AT, breg); |
252b5132 RH |
5132 | breg = 0; |
5133 | tempreg = treg; | |
252b5132 | 5134 | } |
f6a22291 | 5135 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5136 | used_at = 1; |
5137 | } | |
5138 | } | |
0a44bf69 | 5139 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5140 | { |
67c0d1eb | 5141 | int add_breg_early = 0; |
f5040a92 AO |
5142 | |
5143 | /* If this is a reference to an external, and there is no | |
5144 | constant, or local symbol (*), with or without a | |
5145 | constant, we want | |
5146 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5147 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5148 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5149 | ||
5150 | If we have a small constant, and this is a reference to | |
5151 | an external symbol, we want | |
5152 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5153 | addiu $tempreg,$tempreg,<constant> | |
5154 | ||
5155 | If we have a large constant, and this is a reference to | |
5156 | an external symbol, we want | |
5157 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5158 | lui $at,<hiconstant> | |
5159 | addiu $at,$at,<loconstant> | |
5160 | addu $tempreg,$tempreg,$at | |
5161 | ||
5162 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5163 | local symbols, even though it introduces an additional | |
5164 | instruction. */ | |
5165 | ||
f5040a92 AO |
5166 | if (offset_expr.X_add_number) |
5167 | { | |
4d7206a2 | 5168 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5169 | offset_expr.X_add_number = 0; |
5170 | ||
4d7206a2 | 5171 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5172 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5173 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5174 | |
5175 | if (expr1.X_add_number >= -0x8000 | |
5176 | && expr1.X_add_number < 0x8000) | |
5177 | { | |
67c0d1eb RS |
5178 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5179 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5180 | } |
ecd13cd3 | 5181 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5182 | { |
5183 | int dreg; | |
5184 | ||
5185 | /* If we are going to add in a base register, and the | |
5186 | target register and the base register are the same, | |
5187 | then we are using AT as a temporary register. Since | |
5188 | we want to load the constant into AT, we add our | |
5189 | current AT (from the global offset table) and the | |
5190 | register into the register now, and pretend we were | |
5191 | not using a base register. */ | |
5192 | if (breg != treg) | |
5193 | dreg = tempreg; | |
5194 | else | |
5195 | { | |
5196 | assert (tempreg == AT); | |
67c0d1eb RS |
5197 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5198 | treg, AT, breg); | |
f5040a92 | 5199 | dreg = treg; |
67c0d1eb | 5200 | add_breg_early = 1; |
f5040a92 AO |
5201 | } |
5202 | ||
f6a22291 | 5203 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5204 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5205 | dreg, dreg, AT); |
f5040a92 | 5206 | |
f5040a92 AO |
5207 | used_at = 1; |
5208 | } | |
5209 | else | |
5210 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5211 | ||
4d7206a2 | 5212 | relax_switch (); |
f5040a92 AO |
5213 | offset_expr.X_add_number = expr1.X_add_number; |
5214 | ||
67c0d1eb RS |
5215 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5216 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5217 | if (add_breg_early) | |
f5040a92 | 5218 | { |
67c0d1eb | 5219 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5220 | treg, tempreg, breg); |
f5040a92 AO |
5221 | breg = 0; |
5222 | tempreg = treg; | |
5223 | } | |
4d7206a2 | 5224 | relax_end (); |
f5040a92 | 5225 | } |
4d7206a2 | 5226 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5227 | { |
4d7206a2 | 5228 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5229 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5230 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5231 | relax_switch (); |
67c0d1eb RS |
5232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5233 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5234 | relax_end (); |
f5040a92 | 5235 | } |
4d7206a2 | 5236 | else |
f5040a92 | 5237 | { |
67c0d1eb RS |
5238 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5239 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5240 | } |
5241 | } | |
0a44bf69 | 5242 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5243 | { |
67c0d1eb | 5244 | int gpdelay; |
9117d219 NC |
5245 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5246 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5247 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5248 | |
5249 | /* This is the large GOT case. If this is a reference to an | |
5250 | external symbol, and there is no constant, we want | |
5251 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5252 | addu $tempreg,$tempreg,$gp | |
5253 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5254 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5255 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5256 | addu $tempreg,$tempreg,$gp | |
5257 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5258 | For a local symbol, we want |
5259 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5260 | nop | |
5261 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5262 | ||
5263 | If we have a small constant, and this is a reference to | |
5264 | an external symbol, we want | |
5265 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5266 | addu $tempreg,$tempreg,$gp | |
5267 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5268 | nop | |
5269 | addiu $tempreg,$tempreg,<constant> | |
5270 | For a local symbol, we want | |
5271 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5272 | nop | |
5273 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5274 | ||
5275 | If we have a large constant, and this is a reference to | |
5276 | an external symbol, we want | |
5277 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5278 | addu $tempreg,$tempreg,$gp | |
5279 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5280 | lui $at,<hiconstant> | |
5281 | addiu $at,$at,<loconstant> | |
5282 | addu $tempreg,$tempreg,$at | |
5283 | For a local symbol, we want | |
5284 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5285 | lui $at,<hiconstant> | |
5286 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5287 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5288 | */ |
438c16b8 | 5289 | |
252b5132 RH |
5290 | expr1.X_add_number = offset_expr.X_add_number; |
5291 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5292 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5293 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5294 | if (expr1.X_add_number == 0 && breg == 0 |
5295 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5296 | { |
5297 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5298 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5299 | } | |
67c0d1eb RS |
5300 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5301 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5302 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5304 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5305 | if (expr1.X_add_number == 0) |
5306 | { | |
67c0d1eb | 5307 | if (breg != 0) |
252b5132 RH |
5308 | { |
5309 | /* We're going to put in an addu instruction using | |
5310 | tempreg, so we may as well insert the nop right | |
5311 | now. */ | |
269137b2 | 5312 | load_delay_nop (); |
252b5132 | 5313 | } |
252b5132 RH |
5314 | } |
5315 | else if (expr1.X_add_number >= -0x8000 | |
5316 | && expr1.X_add_number < 0x8000) | |
5317 | { | |
269137b2 | 5318 | load_delay_nop (); |
67c0d1eb | 5319 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5320 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5321 | } |
5322 | else | |
5323 | { | |
67c0d1eb | 5324 | int dreg; |
252b5132 RH |
5325 | |
5326 | /* If we are going to add in a base register, and the | |
5327 | target register and the base register are the same, | |
5328 | then we are using AT as a temporary register. Since | |
5329 | we want to load the constant into AT, we add our | |
5330 | current AT (from the global offset table) and the | |
5331 | register into the register now, and pretend we were | |
5332 | not using a base register. */ | |
5333 | if (breg != treg) | |
67c0d1eb | 5334 | dreg = tempreg; |
252b5132 RH |
5335 | else |
5336 | { | |
5337 | assert (tempreg == AT); | |
269137b2 | 5338 | load_delay_nop (); |
67c0d1eb | 5339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5340 | treg, AT, breg); |
252b5132 | 5341 | dreg = treg; |
252b5132 RH |
5342 | } |
5343 | ||
f6a22291 | 5344 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5345 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5346 | |
252b5132 RH |
5347 | used_at = 1; |
5348 | } | |
4d7206a2 RS |
5349 | offset_expr.X_add_number = |
5350 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5351 | relax_switch (); | |
252b5132 | 5352 | |
67c0d1eb | 5353 | if (gpdelay) |
252b5132 RH |
5354 | { |
5355 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5356 | the first instruction on the main stream does not. */ |
67c0d1eb | 5357 | macro_build (NULL, "nop", ""); |
252b5132 | 5358 | } |
ed6fb7bd | 5359 | |
67c0d1eb RS |
5360 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5361 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5362 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5363 | && expr1.X_add_number < 0x8000) |
5364 | { | |
269137b2 | 5365 | load_delay_nop (); |
67c0d1eb RS |
5366 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5367 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5368 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5369 | register, the external symbol case ended with a load, |
5370 | so if the symbol turns out to not be external, and | |
5371 | the next instruction uses tempreg, an unnecessary nop | |
5372 | will be inserted. */ | |
252b5132 RH |
5373 | } |
5374 | else | |
5375 | { | |
5376 | if (breg == treg) | |
5377 | { | |
5378 | /* We must add in the base register now, as in the | |
f5040a92 | 5379 | external symbol case. */ |
252b5132 | 5380 | assert (tempreg == AT); |
269137b2 | 5381 | load_delay_nop (); |
67c0d1eb | 5382 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5383 | treg, AT, breg); |
252b5132 RH |
5384 | tempreg = treg; |
5385 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5386 | it in in both cases. */ |
252b5132 RH |
5387 | breg = 0; |
5388 | } | |
5389 | ||
67c0d1eb RS |
5390 | macro_build_lui (&expr1, AT); |
5391 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5392 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5393 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5394 | tempreg, tempreg, AT); |
8fc2e39e | 5395 | used_at = 1; |
252b5132 | 5396 | } |
4d7206a2 | 5397 | relax_end (); |
252b5132 | 5398 | } |
0a44bf69 | 5399 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5400 | { |
f5040a92 AO |
5401 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5402 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5403 | int add_breg_early = 0; |
f5040a92 AO |
5404 | |
5405 | /* This is the large GOT case. If this is a reference to an | |
5406 | external symbol, and there is no constant, we want | |
5407 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5408 | add $tempreg,$tempreg,$gp | |
5409 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5410 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5411 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5412 | add $tempreg,$tempreg,$gp | |
5413 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5414 | ||
5415 | If we have a small constant, and this is a reference to | |
5416 | an external symbol, we want | |
5417 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5418 | add $tempreg,$tempreg,$gp | |
5419 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5420 | addi $tempreg,$tempreg,<constant> | |
5421 | ||
5422 | If we have a large constant, and this is a reference to | |
5423 | an external symbol, we want | |
5424 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5425 | addu $tempreg,$tempreg,$gp | |
5426 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5427 | lui $at,<hiconstant> | |
5428 | addi $at,$at,<loconstant> | |
5429 | add $tempreg,$tempreg,$at | |
5430 | ||
5431 | If we have NewABI, and we know it's a local symbol, we want | |
5432 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5433 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5434 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5435 | ||
4d7206a2 | 5436 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5437 | |
4d7206a2 | 5438 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5439 | offset_expr.X_add_number = 0; |
5440 | ||
1abe91b1 MR |
5441 | if (expr1.X_add_number == 0 && breg == 0 |
5442 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5443 | { |
5444 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5445 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5446 | } | |
67c0d1eb RS |
5447 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5448 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5449 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5450 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5451 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5452 | |
5453 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5454 | ; |
f5040a92 AO |
5455 | else if (expr1.X_add_number >= -0x8000 |
5456 | && expr1.X_add_number < 0x8000) | |
5457 | { | |
67c0d1eb | 5458 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5459 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5460 | } |
ecd13cd3 | 5461 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5462 | { |
5463 | int dreg; | |
5464 | ||
5465 | /* If we are going to add in a base register, and the | |
5466 | target register and the base register are the same, | |
5467 | then we are using AT as a temporary register. Since | |
5468 | we want to load the constant into AT, we add our | |
5469 | current AT (from the global offset table) and the | |
5470 | register into the register now, and pretend we were | |
5471 | not using a base register. */ | |
5472 | if (breg != treg) | |
5473 | dreg = tempreg; | |
5474 | else | |
5475 | { | |
5476 | assert (tempreg == AT); | |
67c0d1eb | 5477 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5478 | treg, AT, breg); |
f5040a92 | 5479 | dreg = treg; |
67c0d1eb | 5480 | add_breg_early = 1; |
f5040a92 AO |
5481 | } |
5482 | ||
f6a22291 | 5483 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5484 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5485 | |
f5040a92 AO |
5486 | used_at = 1; |
5487 | } | |
5488 | else | |
5489 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5490 | ||
4d7206a2 | 5491 | relax_switch (); |
f5040a92 | 5492 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5493 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5494 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5495 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5496 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5497 | if (add_breg_early) | |
f5040a92 | 5498 | { |
67c0d1eb | 5499 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5500 | treg, tempreg, breg); |
f5040a92 AO |
5501 | breg = 0; |
5502 | tempreg = treg; | |
5503 | } | |
4d7206a2 | 5504 | relax_end (); |
f5040a92 | 5505 | } |
252b5132 RH |
5506 | else |
5507 | abort (); | |
5508 | ||
5509 | if (breg != 0) | |
aed1a261 | 5510 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5511 | break; |
5512 | ||
5513 | case M_J_A: | |
5514 | /* The j instruction may not be used in PIC code, since it | |
5515 | requires an absolute address. We convert it to a b | |
5516 | instruction. */ | |
5517 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5518 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5519 | else |
67c0d1eb | 5520 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5521 | break; |
252b5132 RH |
5522 | |
5523 | /* The jal instructions must be handled as macros because when | |
5524 | generating PIC code they expand to multi-instruction | |
5525 | sequences. Normally they are simple instructions. */ | |
5526 | case M_JAL_1: | |
5527 | dreg = RA; | |
5528 | /* Fall through. */ | |
5529 | case M_JAL_2: | |
3e722fb5 | 5530 | if (mips_pic == NO_PIC) |
67c0d1eb | 5531 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5532 | else |
252b5132 RH |
5533 | { |
5534 | if (sreg != PIC_CALL_REG) | |
5535 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5536 | |
67c0d1eb | 5537 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5538 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5539 | { |
6478892d TS |
5540 | if (mips_cprestore_offset < 0) |
5541 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5542 | else | |
5543 | { | |
7a621144 DJ |
5544 | if (! mips_frame_reg_valid) |
5545 | { | |
5546 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5547 | /* Quiet this warning. */ | |
5548 | mips_frame_reg_valid = 1; | |
5549 | } | |
5550 | if (! mips_cprestore_valid) | |
5551 | { | |
5552 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5553 | /* Quiet this warning. */ | |
5554 | mips_cprestore_valid = 1; | |
5555 | } | |
6478892d | 5556 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5557 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5558 | mips_gp_register, |
256ab948 TS |
5559 | mips_frame_reg, |
5560 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5561 | } |
252b5132 RH |
5562 | } |
5563 | } | |
252b5132 | 5564 | |
8fc2e39e | 5565 | break; |
252b5132 RH |
5566 | |
5567 | case M_JAL_A: | |
5568 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5569 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5570 | else if (mips_pic == SVR4_PIC) |
5571 | { | |
5572 | /* If this is a reference to an external symbol, and we are | |
5573 | using a small GOT, we want | |
5574 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5575 | nop | |
f9419b05 | 5576 | jalr $ra,$25 |
252b5132 RH |
5577 | nop |
5578 | lw $gp,cprestore($sp) | |
5579 | The cprestore value is set using the .cprestore | |
5580 | pseudo-op. If we are using a big GOT, we want | |
5581 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5582 | addu $25,$25,$gp | |
5583 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5584 | nop | |
f9419b05 | 5585 | jalr $ra,$25 |
252b5132 RH |
5586 | nop |
5587 | lw $gp,cprestore($sp) | |
5588 | If the symbol is not external, we want | |
5589 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5590 | nop | |
5591 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5592 | jalr $ra,$25 |
252b5132 | 5593 | nop |
438c16b8 | 5594 | lw $gp,cprestore($sp) |
f5040a92 AO |
5595 | |
5596 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5597 | sequences above, minus nops, unless the symbol is local, | |
5598 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5599 | GOT_DISP. */ | |
438c16b8 | 5600 | if (HAVE_NEWABI) |
252b5132 | 5601 | { |
f5040a92 AO |
5602 | if (! mips_big_got) |
5603 | { | |
4d7206a2 | 5604 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5605 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5606 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5607 | mips_gp_register); |
4d7206a2 | 5608 | relax_switch (); |
67c0d1eb RS |
5609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5610 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5611 | mips_gp_register); |
5612 | relax_end (); | |
f5040a92 AO |
5613 | } |
5614 | else | |
5615 | { | |
4d7206a2 | 5616 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5617 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5618 | BFD_RELOC_MIPS_CALL_HI16); | |
5619 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5620 | PIC_CALL_REG, mips_gp_register); | |
5621 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5622 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5623 | PIC_CALL_REG); | |
4d7206a2 | 5624 | relax_switch (); |
67c0d1eb RS |
5625 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5626 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5627 | mips_gp_register); | |
5628 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5629 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5630 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5631 | relax_end (); |
f5040a92 | 5632 | } |
684022ea | 5633 | |
67c0d1eb | 5634 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5635 | } |
5636 | else | |
5637 | { | |
4d7206a2 | 5638 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5639 | if (! mips_big_got) |
5640 | { | |
67c0d1eb RS |
5641 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5642 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5643 | mips_gp_register); |
269137b2 | 5644 | load_delay_nop (); |
4d7206a2 | 5645 | relax_switch (); |
438c16b8 | 5646 | } |
252b5132 | 5647 | else |
252b5132 | 5648 | { |
67c0d1eb RS |
5649 | int gpdelay; |
5650 | ||
5651 | gpdelay = reg_needs_delay (mips_gp_register); | |
5652 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5653 | BFD_RELOC_MIPS_CALL_HI16); | |
5654 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5655 | PIC_CALL_REG, mips_gp_register); | |
5656 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5657 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5658 | PIC_CALL_REG); | |
269137b2 | 5659 | load_delay_nop (); |
4d7206a2 | 5660 | relax_switch (); |
67c0d1eb RS |
5661 | if (gpdelay) |
5662 | macro_build (NULL, "nop", ""); | |
252b5132 | 5663 | } |
67c0d1eb RS |
5664 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5665 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5666 | mips_gp_register); |
269137b2 | 5667 | load_delay_nop (); |
67c0d1eb RS |
5668 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5669 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5670 | relax_end (); |
67c0d1eb | 5671 | macro_build_jalr (&offset_expr); |
438c16b8 | 5672 | |
6478892d TS |
5673 | if (mips_cprestore_offset < 0) |
5674 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5675 | else | |
5676 | { | |
7a621144 DJ |
5677 | if (! mips_frame_reg_valid) |
5678 | { | |
5679 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5680 | /* Quiet this warning. */ | |
5681 | mips_frame_reg_valid = 1; | |
5682 | } | |
5683 | if (! mips_cprestore_valid) | |
5684 | { | |
5685 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5686 | /* Quiet this warning. */ | |
5687 | mips_cprestore_valid = 1; | |
5688 | } | |
6478892d | 5689 | if (mips_opts.noreorder) |
67c0d1eb | 5690 | macro_build (NULL, "nop", ""); |
6478892d | 5691 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5692 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5693 | mips_gp_register, |
256ab948 TS |
5694 | mips_frame_reg, |
5695 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5696 | } |
252b5132 RH |
5697 | } |
5698 | } | |
0a44bf69 RS |
5699 | else if (mips_pic == VXWORKS_PIC) |
5700 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
5701 | else |
5702 | abort (); | |
5703 | ||
8fc2e39e | 5704 | break; |
252b5132 RH |
5705 | |
5706 | case M_LB_AB: | |
5707 | s = "lb"; | |
5708 | goto ld; | |
5709 | case M_LBU_AB: | |
5710 | s = "lbu"; | |
5711 | goto ld; | |
5712 | case M_LH_AB: | |
5713 | s = "lh"; | |
5714 | goto ld; | |
5715 | case M_LHU_AB: | |
5716 | s = "lhu"; | |
5717 | goto ld; | |
5718 | case M_LW_AB: | |
5719 | s = "lw"; | |
5720 | goto ld; | |
5721 | case M_LWC0_AB: | |
5722 | s = "lwc0"; | |
bdaaa2e1 | 5723 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5724 | coproc = 1; |
5725 | goto ld; | |
5726 | case M_LWC1_AB: | |
5727 | s = "lwc1"; | |
bdaaa2e1 | 5728 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5729 | coproc = 1; |
5730 | goto ld; | |
5731 | case M_LWC2_AB: | |
5732 | s = "lwc2"; | |
bdaaa2e1 | 5733 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5734 | coproc = 1; |
5735 | goto ld; | |
5736 | case M_LWC3_AB: | |
5737 | s = "lwc3"; | |
bdaaa2e1 | 5738 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5739 | coproc = 1; |
5740 | goto ld; | |
5741 | case M_LWL_AB: | |
5742 | s = "lwl"; | |
5743 | lr = 1; | |
5744 | goto ld; | |
5745 | case M_LWR_AB: | |
5746 | s = "lwr"; | |
5747 | lr = 1; | |
5748 | goto ld; | |
5749 | case M_LDC1_AB: | |
fef14a42 | 5750 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5751 | { |
5752 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5753 | break; |
252b5132 RH |
5754 | } |
5755 | s = "ldc1"; | |
bdaaa2e1 | 5756 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5757 | coproc = 1; |
5758 | goto ld; | |
5759 | case M_LDC2_AB: | |
5760 | s = "ldc2"; | |
bdaaa2e1 | 5761 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5762 | coproc = 1; |
5763 | goto ld; | |
5764 | case M_LDC3_AB: | |
5765 | s = "ldc3"; | |
bdaaa2e1 | 5766 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5767 | coproc = 1; |
5768 | goto ld; | |
5769 | case M_LDL_AB: | |
5770 | s = "ldl"; | |
5771 | lr = 1; | |
5772 | goto ld; | |
5773 | case M_LDR_AB: | |
5774 | s = "ldr"; | |
5775 | lr = 1; | |
5776 | goto ld; | |
5777 | case M_LL_AB: | |
5778 | s = "ll"; | |
5779 | goto ld; | |
5780 | case M_LLD_AB: | |
5781 | s = "lld"; | |
5782 | goto ld; | |
5783 | case M_LWU_AB: | |
5784 | s = "lwu"; | |
5785 | ld: | |
8fc2e39e | 5786 | if (breg == treg || coproc || lr) |
252b5132 RH |
5787 | { |
5788 | tempreg = AT; | |
5789 | used_at = 1; | |
5790 | } | |
5791 | else | |
5792 | { | |
5793 | tempreg = treg; | |
252b5132 RH |
5794 | } |
5795 | goto ld_st; | |
5796 | case M_SB_AB: | |
5797 | s = "sb"; | |
5798 | goto st; | |
5799 | case M_SH_AB: | |
5800 | s = "sh"; | |
5801 | goto st; | |
5802 | case M_SW_AB: | |
5803 | s = "sw"; | |
5804 | goto st; | |
5805 | case M_SWC0_AB: | |
5806 | s = "swc0"; | |
bdaaa2e1 | 5807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5808 | coproc = 1; |
5809 | goto st; | |
5810 | case M_SWC1_AB: | |
5811 | s = "swc1"; | |
bdaaa2e1 | 5812 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5813 | coproc = 1; |
5814 | goto st; | |
5815 | case M_SWC2_AB: | |
5816 | s = "swc2"; | |
bdaaa2e1 | 5817 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5818 | coproc = 1; |
5819 | goto st; | |
5820 | case M_SWC3_AB: | |
5821 | s = "swc3"; | |
bdaaa2e1 | 5822 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5823 | coproc = 1; |
5824 | goto st; | |
5825 | case M_SWL_AB: | |
5826 | s = "swl"; | |
5827 | goto st; | |
5828 | case M_SWR_AB: | |
5829 | s = "swr"; | |
5830 | goto st; | |
5831 | case M_SC_AB: | |
5832 | s = "sc"; | |
5833 | goto st; | |
5834 | case M_SCD_AB: | |
5835 | s = "scd"; | |
5836 | goto st; | |
d43b4baf TS |
5837 | case M_CACHE_AB: |
5838 | s = "cache"; | |
5839 | goto st; | |
252b5132 | 5840 | case M_SDC1_AB: |
fef14a42 | 5841 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5842 | { |
5843 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5844 | break; |
252b5132 RH |
5845 | } |
5846 | s = "sdc1"; | |
5847 | coproc = 1; | |
bdaaa2e1 | 5848 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5849 | goto st; |
5850 | case M_SDC2_AB: | |
5851 | s = "sdc2"; | |
bdaaa2e1 | 5852 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5853 | coproc = 1; |
5854 | goto st; | |
5855 | case M_SDC3_AB: | |
5856 | s = "sdc3"; | |
bdaaa2e1 | 5857 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5858 | coproc = 1; |
5859 | goto st; | |
5860 | case M_SDL_AB: | |
5861 | s = "sdl"; | |
5862 | goto st; | |
5863 | case M_SDR_AB: | |
5864 | s = "sdr"; | |
5865 | st: | |
8fc2e39e TS |
5866 | tempreg = AT; |
5867 | used_at = 1; | |
252b5132 | 5868 | ld_st: |
bdaaa2e1 | 5869 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5870 | if (mask == M_LWC1_AB |
5871 | || mask == M_SWC1_AB | |
5872 | || mask == M_LDC1_AB | |
5873 | || mask == M_SDC1_AB | |
5874 | || mask == M_L_DAB | |
5875 | || mask == M_S_DAB) | |
5876 | fmt = "T,o(b)"; | |
d43b4baf TS |
5877 | else if (mask == M_CACHE_AB) |
5878 | fmt = "k,o(b)"; | |
252b5132 RH |
5879 | else if (coproc) |
5880 | fmt = "E,o(b)"; | |
5881 | else | |
5882 | fmt = "t,o(b)"; | |
5883 | ||
5884 | if (offset_expr.X_op != O_constant | |
5885 | && offset_expr.X_op != O_symbol) | |
5886 | { | |
5887 | as_bad (_("expression too complex")); | |
5888 | offset_expr.X_op = O_constant; | |
5889 | } | |
5890 | ||
2051e8c4 MR |
5891 | if (HAVE_32BIT_ADDRESSES |
5892 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
5893 | { |
5894 | char value [32]; | |
5895 | ||
5896 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 5897 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 5898 | } |
2051e8c4 | 5899 | |
252b5132 RH |
5900 | /* A constant expression in PIC code can be handled just as it |
5901 | is in non PIC code. */ | |
aed1a261 RS |
5902 | if (offset_expr.X_op == O_constant) |
5903 | { | |
aed1a261 RS |
5904 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
5905 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 5906 | normalize_address_expr (&expr1); |
aed1a261 RS |
5907 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
5908 | if (breg != 0) | |
5909 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5910 | tempreg, tempreg, breg); | |
5911 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5912 | } | |
5913 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5914 | { |
5915 | /* If this is a reference to a GP relative symbol, and there | |
5916 | is no base register, we want | |
cdf6fd85 | 5917 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5918 | Otherwise, if there is no base register, we want |
5919 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5920 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5921 | If we have a constant, we need two instructions anyhow, | |
5922 | so we always use the latter form. | |
5923 | ||
5924 | If we have a base register, and this is a reference to a | |
5925 | GP relative symbol, we want | |
5926 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5927 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5928 | Otherwise we want |
5929 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5930 | addu $tempreg,$tempreg,$breg | |
5931 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5932 | With a constant we always use the latter case. |
76b3015f | 5933 | |
d6bc6245 TS |
5934 | With 64bit address space and no base register and $at usable, |
5935 | we want | |
5936 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5937 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5938 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5939 | dsll32 $tempreg,0 | |
5940 | daddu $tempreg,$at | |
5941 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5942 | If we have a base register, we want | |
5943 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5944 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5945 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5946 | daddu $at,$breg | |
5947 | dsll32 $tempreg,0 | |
5948 | daddu $tempreg,$at | |
5949 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5950 | ||
5951 | Without $at we can't generate the optimal path for superscalar | |
5952 | processors here since this would require two temporary registers. | |
5953 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5954 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5955 | dsll $tempreg,16 | |
5956 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5957 | dsll $tempreg,16 | |
5958 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5959 | If we have a base register, we want | |
5960 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5961 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5962 | dsll $tempreg,16 | |
5963 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5964 | dsll $tempreg,16 | |
5965 | daddu $tempreg,$tempreg,$breg | |
5966 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5967 | |
6caf9ef4 | 5968 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5969 | the same sequence as in 32bit address space. */ |
5970 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5971 | { |
aed1a261 | 5972 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5973 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5974 | { | |
5975 | relax_start (offset_expr.X_add_symbol); | |
5976 | if (breg == 0) | |
5977 | { | |
5978 | macro_build (&offset_expr, s, fmt, treg, | |
5979 | BFD_RELOC_GPREL16, mips_gp_register); | |
5980 | } | |
5981 | else | |
5982 | { | |
5983 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5984 | tempreg, breg, mips_gp_register); | |
5985 | macro_build (&offset_expr, s, fmt, treg, | |
5986 | BFD_RELOC_GPREL16, tempreg); | |
5987 | } | |
5988 | relax_switch (); | |
5989 | } | |
d6bc6245 | 5990 | |
b8285c27 | 5991 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5992 | { |
67c0d1eb RS |
5993 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5994 | BFD_RELOC_MIPS_HIGHEST); | |
5995 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5996 | BFD_RELOC_HI16_S); | |
5997 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5998 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5999 | if (breg != 0) |
67c0d1eb RS |
6000 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6001 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6002 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6003 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6004 | tempreg); | |
d6bc6245 TS |
6005 | used_at = 1; |
6006 | } | |
6007 | else | |
6008 | { | |
67c0d1eb RS |
6009 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6010 | BFD_RELOC_MIPS_HIGHEST); | |
6011 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6012 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6013 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6014 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6015 | tempreg, BFD_RELOC_HI16_S); | |
6016 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6017 | if (breg != 0) |
67c0d1eb | 6018 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6019 | tempreg, tempreg, breg); |
67c0d1eb | 6020 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6021 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6022 | } |
6caf9ef4 TS |
6023 | |
6024 | if (mips_relax.sequence) | |
6025 | relax_end (); | |
8fc2e39e | 6026 | break; |
d6bc6245 | 6027 | } |
256ab948 | 6028 | |
252b5132 RH |
6029 | if (breg == 0) |
6030 | { | |
67c0d1eb | 6031 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6032 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6033 | { |
4d7206a2 | 6034 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6035 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6036 | mips_gp_register); | |
4d7206a2 | 6037 | relax_switch (); |
252b5132 | 6038 | } |
67c0d1eb RS |
6039 | macro_build_lui (&offset_expr, tempreg); |
6040 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6041 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6042 | if (mips_relax.sequence) |
6043 | relax_end (); | |
252b5132 RH |
6044 | } |
6045 | else | |
6046 | { | |
67c0d1eb | 6047 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6048 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6049 | { |
4d7206a2 | 6050 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6051 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6052 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6053 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6054 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6055 | relax_switch (); |
252b5132 | 6056 | } |
67c0d1eb RS |
6057 | macro_build_lui (&offset_expr, tempreg); |
6058 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6059 | tempreg, tempreg, breg); |
67c0d1eb | 6060 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6061 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6062 | if (mips_relax.sequence) |
6063 | relax_end (); | |
252b5132 RH |
6064 | } |
6065 | } | |
0a44bf69 | 6066 | else if (!mips_big_got) |
252b5132 | 6067 | { |
ed6fb7bd | 6068 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6069 | |
252b5132 RH |
6070 | /* If this is a reference to an external symbol, we want |
6071 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6072 | nop | |
6073 | <op> $treg,0($tempreg) | |
6074 | Otherwise we want | |
6075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6076 | nop | |
6077 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6078 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6079 | |
6080 | For NewABI, we want | |
6081 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6082 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6083 | ||
252b5132 RH |
6084 | If there is a base register, we add it to $tempreg before |
6085 | the <op>. If there is a constant, we stick it in the | |
6086 | <op> instruction. We don't handle constants larger than | |
6087 | 16 bits, because we have no way to load the upper 16 bits | |
6088 | (actually, we could handle them for the subset of cases | |
6089 | in which we are not using $at). */ | |
6090 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6091 | if (HAVE_NEWABI) |
6092 | { | |
67c0d1eb RS |
6093 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6094 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6095 | if (breg != 0) |
67c0d1eb | 6096 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6097 | tempreg, tempreg, breg); |
67c0d1eb | 6098 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6099 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6100 | break; |
6101 | } | |
252b5132 RH |
6102 | expr1.X_add_number = offset_expr.X_add_number; |
6103 | offset_expr.X_add_number = 0; | |
6104 | if (expr1.X_add_number < -0x8000 | |
6105 | || expr1.X_add_number >= 0x8000) | |
6106 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6107 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6108 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6109 | load_delay_nop (); |
4d7206a2 RS |
6110 | relax_start (offset_expr.X_add_symbol); |
6111 | relax_switch (); | |
67c0d1eb RS |
6112 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6113 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6114 | relax_end (); |
252b5132 | 6115 | if (breg != 0) |
67c0d1eb | 6116 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6117 | tempreg, tempreg, breg); |
67c0d1eb | 6118 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6119 | } |
0a44bf69 | 6120 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6121 | { |
67c0d1eb | 6122 | int gpdelay; |
252b5132 RH |
6123 | |
6124 | /* If this is a reference to an external symbol, we want | |
6125 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6126 | addu $tempreg,$tempreg,$gp | |
6127 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6128 | <op> $treg,0($tempreg) | |
6129 | Otherwise we want | |
6130 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6131 | nop | |
6132 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6133 | <op> $treg,0($tempreg) | |
6134 | If there is a base register, we add it to $tempreg before | |
6135 | the <op>. If there is a constant, we stick it in the | |
6136 | <op> instruction. We don't handle constants larger than | |
6137 | 16 bits, because we have no way to load the upper 16 bits | |
6138 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6139 | in which we are not using $at). */ |
252b5132 RH |
6140 | assert (offset_expr.X_op == O_symbol); |
6141 | expr1.X_add_number = offset_expr.X_add_number; | |
6142 | offset_expr.X_add_number = 0; | |
6143 | if (expr1.X_add_number < -0x8000 | |
6144 | || expr1.X_add_number >= 0x8000) | |
6145 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6146 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6147 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6148 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6149 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6150 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6151 | mips_gp_register); | |
6152 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6153 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6154 | relax_switch (); |
67c0d1eb RS |
6155 | if (gpdelay) |
6156 | macro_build (NULL, "nop", ""); | |
6157 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6158 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6159 | load_delay_nop (); |
67c0d1eb RS |
6160 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6161 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6162 | relax_end (); |
6163 | ||
252b5132 | 6164 | if (breg != 0) |
67c0d1eb | 6165 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6166 | tempreg, tempreg, breg); |
67c0d1eb | 6167 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6168 | } |
0a44bf69 | 6169 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6170 | { |
f5040a92 AO |
6171 | /* If this is a reference to an external symbol, we want |
6172 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6173 | add $tempreg,$tempreg,$gp | |
6174 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6175 | <op> $treg,<ofst>($tempreg) | |
6176 | Otherwise, for local symbols, we want: | |
6177 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6178 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6179 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6180 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6181 | offset_expr.X_add_number = 0; |
6182 | if (expr1.X_add_number < -0x8000 | |
6183 | || expr1.X_add_number >= 0x8000) | |
6184 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6185 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6186 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6187 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6188 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6189 | mips_gp_register); | |
6190 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6191 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6192 | if (breg != 0) |
67c0d1eb | 6193 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6194 | tempreg, tempreg, breg); |
67c0d1eb | 6195 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6196 | |
4d7206a2 | 6197 | relax_switch (); |
f5040a92 | 6198 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6199 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6200 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6201 | if (breg != 0) |
67c0d1eb | 6202 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6203 | tempreg, tempreg, breg); |
67c0d1eb | 6204 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6205 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6206 | relax_end (); |
f5040a92 | 6207 | } |
252b5132 RH |
6208 | else |
6209 | abort (); | |
6210 | ||
252b5132 RH |
6211 | break; |
6212 | ||
6213 | case M_LI: | |
6214 | case M_LI_S: | |
67c0d1eb | 6215 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6216 | break; |
252b5132 RH |
6217 | |
6218 | case M_DLI: | |
67c0d1eb | 6219 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6220 | break; |
252b5132 RH |
6221 | |
6222 | case M_LI_SS: | |
6223 | if (imm_expr.X_op == O_constant) | |
6224 | { | |
8fc2e39e | 6225 | used_at = 1; |
67c0d1eb RS |
6226 | load_register (AT, &imm_expr, 0); |
6227 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6228 | break; |
6229 | } | |
6230 | else | |
6231 | { | |
6232 | assert (offset_expr.X_op == O_symbol | |
6233 | && strcmp (segment_name (S_GET_SEGMENT | |
6234 | (offset_expr.X_add_symbol)), | |
6235 | ".lit4") == 0 | |
6236 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6237 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6238 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6239 | break; |
252b5132 RH |
6240 | } |
6241 | ||
6242 | case M_LI_D: | |
ca4e0257 RS |
6243 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6244 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6245 | order 32 bits of the value and the low order 32 bits are either | |
6246 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6247 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6248 | { | |
ca4e0257 | 6249 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6250 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6251 | else |
6252 | { | |
6253 | int hreg, lreg; | |
6254 | ||
6255 | if (target_big_endian) | |
6256 | { | |
6257 | hreg = treg; | |
6258 | lreg = treg + 1; | |
6259 | } | |
6260 | else | |
6261 | { | |
6262 | hreg = treg + 1; | |
6263 | lreg = treg; | |
6264 | } | |
6265 | ||
6266 | if (hreg <= 31) | |
67c0d1eb | 6267 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6268 | if (lreg <= 31) |
6269 | { | |
6270 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6271 | move_register (lreg, 0); |
252b5132 RH |
6272 | else |
6273 | { | |
6274 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6275 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6276 | } |
6277 | } | |
6278 | } | |
8fc2e39e | 6279 | break; |
252b5132 RH |
6280 | } |
6281 | ||
6282 | /* We know that sym is in the .rdata section. First we get the | |
6283 | upper 16 bits of the address. */ | |
6284 | if (mips_pic == NO_PIC) | |
6285 | { | |
67c0d1eb | 6286 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6287 | used_at = 1; |
252b5132 | 6288 | } |
0a44bf69 | 6289 | else |
252b5132 | 6290 | { |
67c0d1eb RS |
6291 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6292 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6293 | used_at = 1; |
252b5132 | 6294 | } |
bdaaa2e1 | 6295 | |
252b5132 | 6296 | /* Now we load the register(s). */ |
ca4e0257 | 6297 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6298 | { |
6299 | used_at = 1; | |
6300 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6301 | } | |
252b5132 RH |
6302 | else |
6303 | { | |
8fc2e39e | 6304 | used_at = 1; |
67c0d1eb | 6305 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6306 | if (treg != RA) |
252b5132 RH |
6307 | { |
6308 | /* FIXME: How in the world do we deal with the possible | |
6309 | overflow here? */ | |
6310 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6311 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6312 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6313 | } |
6314 | } | |
252b5132 RH |
6315 | break; |
6316 | ||
6317 | case M_LI_DD: | |
ca4e0257 RS |
6318 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6319 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6320 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6321 | the value and the low order 32 bits are either zero or in | |
6322 | OFFSET_EXPR. */ | |
252b5132 RH |
6323 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6324 | { | |
8fc2e39e | 6325 | used_at = 1; |
67c0d1eb | 6326 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6327 | if (HAVE_64BIT_FPRS) |
6328 | { | |
6329 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6330 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6331 | } |
252b5132 RH |
6332 | else |
6333 | { | |
67c0d1eb | 6334 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6335 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6336 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6337 | else |
6338 | { | |
6339 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6340 | load_register (AT, &offset_expr, 0); |
6341 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6342 | } |
6343 | } | |
6344 | break; | |
6345 | } | |
6346 | ||
6347 | assert (offset_expr.X_op == O_symbol | |
6348 | && offset_expr.X_add_number == 0); | |
6349 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6350 | if (strcmp (s, ".lit8") == 0) | |
6351 | { | |
e7af610e | 6352 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6353 | { |
67c0d1eb | 6354 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6355 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6356 | break; |
252b5132 | 6357 | } |
c9914766 | 6358 | breg = mips_gp_register; |
252b5132 RH |
6359 | r = BFD_RELOC_MIPS_LITERAL; |
6360 | goto dob; | |
6361 | } | |
6362 | else | |
6363 | { | |
6364 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6365 | used_at = 1; |
0a44bf69 | 6366 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6367 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6368 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6369 | else |
6370 | { | |
6371 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6372 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6373 | } |
bdaaa2e1 | 6374 | |
e7af610e | 6375 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6376 | { |
67c0d1eb RS |
6377 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6378 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6379 | break; |
6380 | } | |
6381 | breg = AT; | |
6382 | r = BFD_RELOC_LO16; | |
6383 | goto dob; | |
6384 | } | |
6385 | ||
6386 | case M_L_DOB: | |
fef14a42 | 6387 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6388 | { |
6389 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6390 | break; |
252b5132 RH |
6391 | } |
6392 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6393 | to adjust when loading from memory. */ | |
6394 | r = BFD_RELOC_LO16; | |
6395 | dob: | |
e7af610e | 6396 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6397 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6398 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6399 | /* FIXME: A possible overflow which I don't know how to deal |
6400 | with. */ | |
6401 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6402 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6403 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6404 | break; |
6405 | ||
6406 | case M_L_DAB: | |
6407 | /* | |
6408 | * The MIPS assembler seems to check for X_add_number not | |
6409 | * being double aligned and generating: | |
6410 | * lui at,%hi(foo+1) | |
6411 | * addu at,at,v1 | |
6412 | * addiu at,at,%lo(foo+1) | |
6413 | * lwc1 f2,0(at) | |
6414 | * lwc1 f3,4(at) | |
6415 | * But, the resulting address is the same after relocation so why | |
6416 | * generate the extra instruction? | |
6417 | */ | |
fef14a42 | 6418 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6419 | { |
6420 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6421 | break; |
252b5132 | 6422 | } |
bdaaa2e1 | 6423 | /* Itbl support may require additional care here. */ |
252b5132 | 6424 | coproc = 1; |
e7af610e | 6425 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6426 | { |
6427 | s = "ldc1"; | |
6428 | goto ld; | |
6429 | } | |
6430 | ||
6431 | s = "lwc1"; | |
6432 | fmt = "T,o(b)"; | |
6433 | goto ldd_std; | |
6434 | ||
6435 | case M_S_DAB: | |
fef14a42 | 6436 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6437 | { |
6438 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6439 | break; |
252b5132 RH |
6440 | } |
6441 | ||
e7af610e | 6442 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6443 | { |
6444 | s = "sdc1"; | |
6445 | goto st; | |
6446 | } | |
6447 | ||
6448 | s = "swc1"; | |
6449 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6450 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6451 | coproc = 1; |
6452 | goto ldd_std; | |
6453 | ||
6454 | case M_LD_AB: | |
ca4e0257 | 6455 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6456 | { |
6457 | s = "ld"; | |
6458 | goto ld; | |
6459 | } | |
6460 | ||
6461 | s = "lw"; | |
6462 | fmt = "t,o(b)"; | |
6463 | goto ldd_std; | |
6464 | ||
6465 | case M_SD_AB: | |
ca4e0257 | 6466 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6467 | { |
6468 | s = "sd"; | |
6469 | goto st; | |
6470 | } | |
6471 | ||
6472 | s = "sw"; | |
6473 | fmt = "t,o(b)"; | |
6474 | ||
6475 | ldd_std: | |
6476 | if (offset_expr.X_op != O_symbol | |
6477 | && offset_expr.X_op != O_constant) | |
6478 | { | |
6479 | as_bad (_("expression too complex")); | |
6480 | offset_expr.X_op = O_constant; | |
6481 | } | |
6482 | ||
2051e8c4 MR |
6483 | if (HAVE_32BIT_ADDRESSES |
6484 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6485 | { |
6486 | char value [32]; | |
6487 | ||
6488 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6489 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6490 | } |
2051e8c4 | 6491 | |
252b5132 RH |
6492 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6493 | to adjust when loading from memory. We set coproc if we must | |
6494 | load $fn+1 first. */ | |
bdaaa2e1 | 6495 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6496 | if (! target_big_endian) |
6497 | coproc = 0; | |
6498 | ||
6499 | if (mips_pic == NO_PIC | |
6500 | || offset_expr.X_op == O_constant) | |
6501 | { | |
6502 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6503 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6504 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6505 | If we have a base register, we use this |
6506 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6507 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6508 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6509 | If this is not a GP relative symbol, we want |
6510 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6511 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6512 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6513 | If there is a base register, we add it to $at after the | |
6514 | lui instruction. If there is a constant, we always use | |
6515 | the last case. */ | |
39a59cf8 MR |
6516 | if (offset_expr.X_op == O_symbol |
6517 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6518 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6519 | { |
4d7206a2 | 6520 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6521 | if (breg == 0) |
6522 | { | |
c9914766 | 6523 | tempreg = mips_gp_register; |
252b5132 RH |
6524 | } |
6525 | else | |
6526 | { | |
67c0d1eb | 6527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6528 | AT, breg, mips_gp_register); |
252b5132 | 6529 | tempreg = AT; |
252b5132 RH |
6530 | used_at = 1; |
6531 | } | |
6532 | ||
beae10d5 | 6533 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6534 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6535 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6536 | offset_expr.X_add_number += 4; |
6537 | ||
6538 | /* Set mips_optimize to 2 to avoid inserting an | |
6539 | undesired nop. */ | |
6540 | hold_mips_optimize = mips_optimize; | |
6541 | mips_optimize = 2; | |
beae10d5 | 6542 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6543 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6544 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6545 | mips_optimize = hold_mips_optimize; |
6546 | ||
4d7206a2 | 6547 | relax_switch (); |
252b5132 RH |
6548 | |
6549 | /* We just generated two relocs. When tc_gen_reloc | |
6550 | handles this case, it will skip the first reloc and | |
6551 | handle the second. The second reloc already has an | |
6552 | extra addend of 4, which we added above. We must | |
6553 | subtract it out, and then subtract another 4 to make | |
6554 | the first reloc come out right. The second reloc | |
6555 | will come out right because we are going to add 4 to | |
6556 | offset_expr when we build its instruction below. | |
6557 | ||
6558 | If we have a symbol, then we don't want to include | |
6559 | the offset, because it will wind up being included | |
6560 | when we generate the reloc. */ | |
6561 | ||
6562 | if (offset_expr.X_op == O_constant) | |
6563 | offset_expr.X_add_number -= 8; | |
6564 | else | |
6565 | { | |
6566 | offset_expr.X_add_number = -4; | |
6567 | offset_expr.X_op = O_constant; | |
6568 | } | |
6569 | } | |
8fc2e39e | 6570 | used_at = 1; |
67c0d1eb | 6571 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6572 | if (breg != 0) |
67c0d1eb | 6573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6574 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6575 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6576 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6577 | /* FIXME: How do we handle overflow here? */ |
6578 | offset_expr.X_add_number += 4; | |
beae10d5 | 6579 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6580 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6581 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6582 | if (mips_relax.sequence) |
6583 | relax_end (); | |
bdaaa2e1 | 6584 | } |
0a44bf69 | 6585 | else if (!mips_big_got) |
252b5132 | 6586 | { |
252b5132 RH |
6587 | /* If this is a reference to an external symbol, we want |
6588 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6589 | nop | |
6590 | <op> $treg,0($at) | |
6591 | <op> $treg+1,4($at) | |
6592 | Otherwise we want | |
6593 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6594 | nop | |
6595 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6596 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6597 | If there is a base register we add it to $at before the | |
6598 | lwc1 instructions. If there is a constant we include it | |
6599 | in the lwc1 instructions. */ | |
6600 | used_at = 1; | |
6601 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6602 | if (expr1.X_add_number < -0x8000 |
6603 | || expr1.X_add_number >= 0x8000 - 4) | |
6604 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6605 | load_got_offset (AT, &offset_expr); |
269137b2 | 6606 | load_delay_nop (); |
252b5132 | 6607 | if (breg != 0) |
67c0d1eb | 6608 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6609 | |
6610 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6611 | nop. */ | |
6612 | hold_mips_optimize = mips_optimize; | |
6613 | mips_optimize = 2; | |
4d7206a2 | 6614 | |
beae10d5 | 6615 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6616 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6617 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6618 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6619 | expr1.X_add_number += 4; |
67c0d1eb RS |
6620 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6621 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6622 | relax_switch (); |
67c0d1eb RS |
6623 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6624 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6625 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6626 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6627 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6628 | relax_end (); |
252b5132 | 6629 | |
4d7206a2 | 6630 | mips_optimize = hold_mips_optimize; |
252b5132 | 6631 | } |
0a44bf69 | 6632 | else if (mips_big_got) |
252b5132 | 6633 | { |
67c0d1eb | 6634 | int gpdelay; |
252b5132 RH |
6635 | |
6636 | /* If this is a reference to an external symbol, we want | |
6637 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6638 | addu $at,$at,$gp | |
6639 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6640 | nop | |
6641 | <op> $treg,0($at) | |
6642 | <op> $treg+1,4($at) | |
6643 | Otherwise we want | |
6644 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6645 | nop | |
6646 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6647 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6648 | If there is a base register we add it to $at before the | |
6649 | lwc1 instructions. If there is a constant we include it | |
6650 | in the lwc1 instructions. */ | |
6651 | used_at = 1; | |
6652 | expr1.X_add_number = offset_expr.X_add_number; | |
6653 | offset_expr.X_add_number = 0; | |
6654 | if (expr1.X_add_number < -0x8000 | |
6655 | || expr1.X_add_number >= 0x8000 - 4) | |
6656 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6657 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6658 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6659 | macro_build (&offset_expr, "lui", "t,u", |
6660 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6661 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6662 | AT, AT, mips_gp_register); |
67c0d1eb | 6663 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6664 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6665 | load_delay_nop (); |
252b5132 | 6666 | if (breg != 0) |
67c0d1eb | 6667 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6668 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6669 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6670 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6671 | expr1.X_add_number += 4; |
6672 | ||
6673 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6674 | nop. */ | |
6675 | hold_mips_optimize = mips_optimize; | |
6676 | mips_optimize = 2; | |
beae10d5 | 6677 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6678 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6679 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6680 | mips_optimize = hold_mips_optimize; |
6681 | expr1.X_add_number -= 4; | |
6682 | ||
4d7206a2 RS |
6683 | relax_switch (); |
6684 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6685 | if (gpdelay) |
6686 | macro_build (NULL, "nop", ""); | |
6687 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6688 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6689 | load_delay_nop (); |
252b5132 | 6690 | if (breg != 0) |
67c0d1eb | 6691 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6692 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6693 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6694 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6695 | offset_expr.X_add_number += 4; |
252b5132 RH |
6696 | |
6697 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6698 | nop. */ | |
6699 | hold_mips_optimize = mips_optimize; | |
6700 | mips_optimize = 2; | |
beae10d5 | 6701 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6702 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6703 | BFD_RELOC_LO16, AT); | |
252b5132 | 6704 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6705 | relax_end (); |
252b5132 | 6706 | } |
252b5132 RH |
6707 | else |
6708 | abort (); | |
6709 | ||
252b5132 RH |
6710 | break; |
6711 | ||
6712 | case M_LD_OB: | |
6713 | s = "lw"; | |
6714 | goto sd_ob; | |
6715 | case M_SD_OB: | |
6716 | s = "sw"; | |
6717 | sd_ob: | |
ca4e0257 | 6718 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6719 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6720 | offset_expr.X_add_number += 4; |
67c0d1eb | 6721 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6722 | break; |
252b5132 RH |
6723 | |
6724 | /* New code added to support COPZ instructions. | |
6725 | This code builds table entries out of the macros in mip_opcodes. | |
6726 | R4000 uses interlocks to handle coproc delays. | |
6727 | Other chips (like the R3000) require nops to be inserted for delays. | |
6728 | ||
f72c8c98 | 6729 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6730 | In order to fill delay slots for non-interlocked chips, |
6731 | we must have a way to specify delays based on the coprocessor. | |
6732 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6733 | What are the side-effects of the cop instruction? | |
6734 | What cache support might we have and what are its effects? | |
6735 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6736 | What registers are read/set/modified? |
252b5132 RH |
6737 | |
6738 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6739 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6740 | |
6741 | case M_COP0: | |
6742 | s = "c0"; | |
6743 | goto copz; | |
6744 | case M_COP1: | |
6745 | s = "c1"; | |
6746 | goto copz; | |
6747 | case M_COP2: | |
6748 | s = "c2"; | |
6749 | goto copz; | |
6750 | case M_COP3: | |
6751 | s = "c3"; | |
6752 | copz: | |
6753 | /* For now we just do C (same as Cz). The parameter will be | |
6754 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6755 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6756 | break; |
252b5132 | 6757 | |
ea1fb5dc | 6758 | case M_MOVE: |
67c0d1eb | 6759 | move_register (dreg, sreg); |
8fc2e39e | 6760 | break; |
ea1fb5dc | 6761 | |
252b5132 RH |
6762 | #ifdef LOSING_COMPILER |
6763 | default: | |
6764 | /* Try and see if this is a new itbl instruction. | |
6765 | This code builds table entries out of the macros in mip_opcodes. | |
6766 | FIXME: For now we just assemble the expression and pass it's | |
6767 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6768 | We may want to have the assembler assemble this value, |
252b5132 RH |
6769 | so that we gain the assembler's knowledge of delay slots, |
6770 | symbols, etc. | |
6771 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6772 | if (itbl_have_entries |
252b5132 | 6773 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6774 | { |
252b5132 RH |
6775 | s = ip->insn_mo->name; |
6776 | s2 = "cop3"; | |
6777 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6778 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6779 | break; |
beae10d5 | 6780 | } |
252b5132 | 6781 | macro2 (ip); |
8fc2e39e | 6782 | break; |
252b5132 | 6783 | } |
8fc2e39e TS |
6784 | if (mips_opts.noat && used_at) |
6785 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6786 | } |
bdaaa2e1 | 6787 | |
252b5132 | 6788 | static void |
17a2f251 | 6789 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6790 | { |
6791 | register int treg, sreg, dreg, breg; | |
6792 | int tempreg; | |
6793 | int mask; | |
252b5132 RH |
6794 | int used_at; |
6795 | expressionS expr1; | |
6796 | const char *s; | |
6797 | const char *s2; | |
6798 | const char *fmt; | |
6799 | int likely = 0; | |
6800 | int dbl = 0; | |
6801 | int coproc = 0; | |
6802 | int lr = 0; | |
6803 | int imm = 0; | |
6804 | int off; | |
6805 | offsetT maxnum; | |
6806 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6807 | |
252b5132 RH |
6808 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6809 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6810 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6811 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6812 | |
252b5132 RH |
6813 | expr1.X_op = O_constant; |
6814 | expr1.X_op_symbol = NULL; | |
6815 | expr1.X_add_symbol = NULL; | |
6816 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6817 | |
252b5132 RH |
6818 | switch (mask) |
6819 | { | |
6820 | #endif /* LOSING_COMPILER */ | |
6821 | ||
6822 | case M_DMUL: | |
6823 | dbl = 1; | |
6824 | case M_MUL: | |
67c0d1eb RS |
6825 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6826 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6827 | break; |
252b5132 RH |
6828 | |
6829 | case M_DMUL_I: | |
6830 | dbl = 1; | |
6831 | case M_MUL_I: | |
6832 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6833 | not trying to be that fancy. GCC should do this for us | |
6834 | anyway. */ | |
8fc2e39e | 6835 | used_at = 1; |
67c0d1eb RS |
6836 | load_register (AT, &imm_expr, dbl); |
6837 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6838 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6839 | break; |
6840 | ||
6841 | case M_DMULO_I: | |
6842 | dbl = 1; | |
6843 | case M_MULO_I: | |
6844 | imm = 1; | |
6845 | goto do_mulo; | |
6846 | ||
6847 | case M_DMULO: | |
6848 | dbl = 1; | |
6849 | case M_MULO: | |
6850 | do_mulo: | |
7d10b47d | 6851 | start_noreorder (); |
8fc2e39e | 6852 | used_at = 1; |
252b5132 | 6853 | if (imm) |
67c0d1eb RS |
6854 | load_register (AT, &imm_expr, dbl); |
6855 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6856 | macro_build (NULL, "mflo", "d", dreg); | |
6857 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6858 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6859 | if (mips_trap) |
67c0d1eb | 6860 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6861 | else |
6862 | { | |
6863 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6864 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6865 | macro_build (NULL, "nop", "", 0); | |
6866 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6867 | } |
7d10b47d | 6868 | end_noreorder (); |
67c0d1eb | 6869 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6870 | break; |
6871 | ||
6872 | case M_DMULOU_I: | |
6873 | dbl = 1; | |
6874 | case M_MULOU_I: | |
6875 | imm = 1; | |
6876 | goto do_mulou; | |
6877 | ||
6878 | case M_DMULOU: | |
6879 | dbl = 1; | |
6880 | case M_MULOU: | |
6881 | do_mulou: | |
7d10b47d | 6882 | start_noreorder (); |
8fc2e39e | 6883 | used_at = 1; |
252b5132 | 6884 | if (imm) |
67c0d1eb RS |
6885 | load_register (AT, &imm_expr, dbl); |
6886 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6887 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6888 | macro_build (NULL, "mfhi", "d", AT); |
6889 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6890 | if (mips_trap) |
67c0d1eb | 6891 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6892 | else |
6893 | { | |
6894 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6895 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6896 | macro_build (NULL, "nop", "", 0); | |
6897 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6898 | } |
7d10b47d | 6899 | end_noreorder (); |
252b5132 RH |
6900 | break; |
6901 | ||
771c7ce4 | 6902 | case M_DROL: |
fef14a42 | 6903 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6904 | { |
6905 | if (dreg == sreg) | |
6906 | { | |
6907 | tempreg = AT; | |
6908 | used_at = 1; | |
6909 | } | |
6910 | else | |
6911 | { | |
6912 | tempreg = dreg; | |
82dd0097 | 6913 | } |
67c0d1eb RS |
6914 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6915 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6916 | break; |
82dd0097 | 6917 | } |
8fc2e39e | 6918 | used_at = 1; |
67c0d1eb RS |
6919 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6920 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6921 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6922 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6923 | break; |
6924 | ||
252b5132 | 6925 | case M_ROL: |
fef14a42 | 6926 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6927 | { |
6928 | if (dreg == sreg) | |
6929 | { | |
6930 | tempreg = AT; | |
6931 | used_at = 1; | |
6932 | } | |
6933 | else | |
6934 | { | |
6935 | tempreg = dreg; | |
82dd0097 | 6936 | } |
67c0d1eb RS |
6937 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6938 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6939 | break; |
82dd0097 | 6940 | } |
8fc2e39e | 6941 | used_at = 1; |
67c0d1eb RS |
6942 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6943 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6944 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6945 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6946 | break; |
6947 | ||
771c7ce4 TS |
6948 | case M_DROL_I: |
6949 | { | |
6950 | unsigned int rot; | |
82dd0097 | 6951 | char *l, *r; |
771c7ce4 TS |
6952 | |
6953 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6954 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6955 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6956 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6957 | { |
6958 | rot = (64 - rot) & 0x3f; | |
6959 | if (rot >= 32) | |
67c0d1eb | 6960 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6961 | else |
67c0d1eb | 6962 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6963 | break; |
60b63b72 | 6964 | } |
483fc7cd | 6965 | if (rot == 0) |
483fc7cd | 6966 | { |
67c0d1eb | 6967 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6968 | break; |
483fc7cd | 6969 | } |
82dd0097 CD |
6970 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6971 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6972 | rot &= 0x1f; | |
8fc2e39e | 6973 | used_at = 1; |
67c0d1eb RS |
6974 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6975 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6976 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6977 | } |
6978 | break; | |
6979 | ||
252b5132 | 6980 | case M_ROL_I: |
771c7ce4 TS |
6981 | { |
6982 | unsigned int rot; | |
6983 | ||
6984 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6985 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6986 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6987 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6988 | { |
67c0d1eb | 6989 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6990 | break; |
60b63b72 | 6991 | } |
483fc7cd | 6992 | if (rot == 0) |
483fc7cd | 6993 | { |
67c0d1eb | 6994 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6995 | break; |
483fc7cd | 6996 | } |
8fc2e39e | 6997 | used_at = 1; |
67c0d1eb RS |
6998 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6999 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7000 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7001 | } |
7002 | break; | |
7003 | ||
7004 | case M_DROR: | |
fef14a42 | 7005 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7006 | { |
67c0d1eb | 7007 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7008 | break; |
82dd0097 | 7009 | } |
8fc2e39e | 7010 | used_at = 1; |
67c0d1eb RS |
7011 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7012 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7013 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7014 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7015 | break; |
7016 | ||
7017 | case M_ROR: | |
fef14a42 | 7018 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7019 | { |
67c0d1eb | 7020 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7021 | break; |
82dd0097 | 7022 | } |
8fc2e39e | 7023 | used_at = 1; |
67c0d1eb RS |
7024 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7025 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7026 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7027 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7028 | break; |
7029 | ||
771c7ce4 TS |
7030 | case M_DROR_I: |
7031 | { | |
7032 | unsigned int rot; | |
82dd0097 | 7033 | char *l, *r; |
771c7ce4 TS |
7034 | |
7035 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7036 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7037 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7038 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7039 | { |
7040 | if (rot >= 32) | |
67c0d1eb | 7041 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7042 | else |
67c0d1eb | 7043 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7044 | break; |
82dd0097 | 7045 | } |
483fc7cd | 7046 | if (rot == 0) |
483fc7cd | 7047 | { |
67c0d1eb | 7048 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7049 | break; |
483fc7cd | 7050 | } |
82dd0097 CD |
7051 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7052 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7053 | rot &= 0x1f; | |
8fc2e39e | 7054 | used_at = 1; |
67c0d1eb RS |
7055 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7056 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7057 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7058 | } |
7059 | break; | |
7060 | ||
252b5132 | 7061 | case M_ROR_I: |
771c7ce4 TS |
7062 | { |
7063 | unsigned int rot; | |
7064 | ||
7065 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7066 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7067 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7068 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7069 | { |
67c0d1eb | 7070 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7071 | break; |
82dd0097 | 7072 | } |
483fc7cd | 7073 | if (rot == 0) |
483fc7cd | 7074 | { |
67c0d1eb | 7075 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7076 | break; |
483fc7cd | 7077 | } |
8fc2e39e | 7078 | used_at = 1; |
67c0d1eb RS |
7079 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7080 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7081 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7082 | } |
252b5132 RH |
7083 | break; |
7084 | ||
7085 | case M_S_DOB: | |
fef14a42 | 7086 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7087 | { |
7088 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7089 | break; |
252b5132 | 7090 | } |
e7af610e | 7091 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7092 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7093 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7094 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7095 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7096 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7097 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7098 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7099 | break; |
252b5132 RH |
7100 | |
7101 | case M_SEQ: | |
7102 | if (sreg == 0) | |
67c0d1eb | 7103 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7104 | else if (treg == 0) |
67c0d1eb | 7105 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7106 | else |
7107 | { | |
67c0d1eb RS |
7108 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7109 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7110 | } |
8fc2e39e | 7111 | break; |
252b5132 RH |
7112 | |
7113 | case M_SEQ_I: | |
7114 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7115 | { | |
67c0d1eb | 7116 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7117 | break; |
252b5132 RH |
7118 | } |
7119 | if (sreg == 0) | |
7120 | { | |
7121 | as_warn (_("Instruction %s: result is always false"), | |
7122 | ip->insn_mo->name); | |
67c0d1eb | 7123 | move_register (dreg, 0); |
8fc2e39e | 7124 | break; |
252b5132 RH |
7125 | } |
7126 | if (imm_expr.X_op == O_constant | |
7127 | && imm_expr.X_add_number >= 0 | |
7128 | && imm_expr.X_add_number < 0x10000) | |
7129 | { | |
67c0d1eb | 7130 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7131 | } |
7132 | else if (imm_expr.X_op == O_constant | |
7133 | && imm_expr.X_add_number > -0x8000 | |
7134 | && imm_expr.X_add_number < 0) | |
7135 | { | |
7136 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7137 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7138 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7139 | } |
7140 | else | |
7141 | { | |
67c0d1eb RS |
7142 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7143 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7144 | used_at = 1; |
7145 | } | |
67c0d1eb | 7146 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7147 | break; |
252b5132 RH |
7148 | |
7149 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7150 | s = "slt"; | |
7151 | goto sge; | |
7152 | case M_SGEU: | |
7153 | s = "sltu"; | |
7154 | sge: | |
67c0d1eb RS |
7155 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7156 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7157 | break; |
252b5132 RH |
7158 | |
7159 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7160 | case M_SGEU_I: | |
7161 | if (imm_expr.X_op == O_constant | |
7162 | && imm_expr.X_add_number >= -0x8000 | |
7163 | && imm_expr.X_add_number < 0x8000) | |
7164 | { | |
67c0d1eb RS |
7165 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7166 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7167 | } |
7168 | else | |
7169 | { | |
67c0d1eb RS |
7170 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7171 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7172 | dreg, sreg, AT); | |
252b5132 RH |
7173 | used_at = 1; |
7174 | } | |
67c0d1eb | 7175 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7176 | break; |
252b5132 RH |
7177 | |
7178 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7179 | s = "slt"; | |
7180 | goto sgt; | |
7181 | case M_SGTU: | |
7182 | s = "sltu"; | |
7183 | sgt: | |
67c0d1eb | 7184 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7185 | break; |
252b5132 RH |
7186 | |
7187 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7188 | s = "slt"; | |
7189 | goto sgti; | |
7190 | case M_SGTU_I: | |
7191 | s = "sltu"; | |
7192 | sgti: | |
8fc2e39e | 7193 | used_at = 1; |
67c0d1eb RS |
7194 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7195 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7196 | break; |
7197 | ||
2396cfb9 | 7198 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7199 | s = "slt"; |
7200 | goto sle; | |
7201 | case M_SLEU: | |
7202 | s = "sltu"; | |
7203 | sle: | |
67c0d1eb RS |
7204 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7205 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7206 | break; |
252b5132 | 7207 | |
2396cfb9 | 7208 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7209 | s = "slt"; |
7210 | goto slei; | |
7211 | case M_SLEU_I: | |
7212 | s = "sltu"; | |
7213 | slei: | |
8fc2e39e | 7214 | used_at = 1; |
67c0d1eb RS |
7215 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7216 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7217 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7218 | break; |
7219 | ||
7220 | case M_SLT_I: | |
7221 | if (imm_expr.X_op == O_constant | |
7222 | && imm_expr.X_add_number >= -0x8000 | |
7223 | && imm_expr.X_add_number < 0x8000) | |
7224 | { | |
67c0d1eb | 7225 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7226 | break; |
252b5132 | 7227 | } |
8fc2e39e | 7228 | used_at = 1; |
67c0d1eb RS |
7229 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7230 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7231 | break; |
7232 | ||
7233 | case M_SLTU_I: | |
7234 | if (imm_expr.X_op == O_constant | |
7235 | && imm_expr.X_add_number >= -0x8000 | |
7236 | && imm_expr.X_add_number < 0x8000) | |
7237 | { | |
67c0d1eb | 7238 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7239 | BFD_RELOC_LO16); |
8fc2e39e | 7240 | break; |
252b5132 | 7241 | } |
8fc2e39e | 7242 | used_at = 1; |
67c0d1eb RS |
7243 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7244 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7245 | break; |
7246 | ||
7247 | case M_SNE: | |
7248 | if (sreg == 0) | |
67c0d1eb | 7249 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7250 | else if (treg == 0) |
67c0d1eb | 7251 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7252 | else |
7253 | { | |
67c0d1eb RS |
7254 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7255 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7256 | } |
8fc2e39e | 7257 | break; |
252b5132 RH |
7258 | |
7259 | case M_SNE_I: | |
7260 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7261 | { | |
67c0d1eb | 7262 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7263 | break; |
252b5132 RH |
7264 | } |
7265 | if (sreg == 0) | |
7266 | { | |
7267 | as_warn (_("Instruction %s: result is always true"), | |
7268 | ip->insn_mo->name); | |
67c0d1eb RS |
7269 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7270 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7271 | break; |
252b5132 RH |
7272 | } |
7273 | if (imm_expr.X_op == O_constant | |
7274 | && imm_expr.X_add_number >= 0 | |
7275 | && imm_expr.X_add_number < 0x10000) | |
7276 | { | |
67c0d1eb | 7277 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7278 | } |
7279 | else if (imm_expr.X_op == O_constant | |
7280 | && imm_expr.X_add_number > -0x8000 | |
7281 | && imm_expr.X_add_number < 0) | |
7282 | { | |
7283 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7284 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7285 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7286 | } |
7287 | else | |
7288 | { | |
67c0d1eb RS |
7289 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7290 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7291 | used_at = 1; |
7292 | } | |
67c0d1eb | 7293 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7294 | break; |
252b5132 RH |
7295 | |
7296 | case M_DSUB_I: | |
7297 | dbl = 1; | |
7298 | case M_SUB_I: | |
7299 | if (imm_expr.X_op == O_constant | |
7300 | && imm_expr.X_add_number > -0x8000 | |
7301 | && imm_expr.X_add_number <= 0x8000) | |
7302 | { | |
7303 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7304 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7305 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7306 | break; |
252b5132 | 7307 | } |
8fc2e39e | 7308 | used_at = 1; |
67c0d1eb RS |
7309 | load_register (AT, &imm_expr, dbl); |
7310 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7311 | break; |
7312 | ||
7313 | case M_DSUBU_I: | |
7314 | dbl = 1; | |
7315 | case M_SUBU_I: | |
7316 | if (imm_expr.X_op == O_constant | |
7317 | && imm_expr.X_add_number > -0x8000 | |
7318 | && imm_expr.X_add_number <= 0x8000) | |
7319 | { | |
7320 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7321 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7322 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7323 | break; |
252b5132 | 7324 | } |
8fc2e39e | 7325 | used_at = 1; |
67c0d1eb RS |
7326 | load_register (AT, &imm_expr, dbl); |
7327 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7328 | break; |
7329 | ||
7330 | case M_TEQ_I: | |
7331 | s = "teq"; | |
7332 | goto trap; | |
7333 | case M_TGE_I: | |
7334 | s = "tge"; | |
7335 | goto trap; | |
7336 | case M_TGEU_I: | |
7337 | s = "tgeu"; | |
7338 | goto trap; | |
7339 | case M_TLT_I: | |
7340 | s = "tlt"; | |
7341 | goto trap; | |
7342 | case M_TLTU_I: | |
7343 | s = "tltu"; | |
7344 | goto trap; | |
7345 | case M_TNE_I: | |
7346 | s = "tne"; | |
7347 | trap: | |
8fc2e39e | 7348 | used_at = 1; |
67c0d1eb RS |
7349 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7350 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7351 | break; |
7352 | ||
252b5132 | 7353 | case M_TRUNCWS: |
43841e91 | 7354 | case M_TRUNCWD: |
e7af610e | 7355 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7356 | used_at = 1; |
252b5132 RH |
7357 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7358 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7359 | ||
7360 | /* | |
7361 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7362 | * or is there a reason for it? | |
7363 | */ | |
7d10b47d | 7364 | start_noreorder (); |
67c0d1eb RS |
7365 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7366 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7367 | macro_build (NULL, "nop", ""); | |
252b5132 | 7368 | expr1.X_add_number = 3; |
67c0d1eb | 7369 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7370 | expr1.X_add_number = 2; |
67c0d1eb RS |
7371 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7372 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7373 | macro_build (NULL, "nop", ""); | |
7374 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7375 | dreg, sreg); | |
7376 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7377 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7378 | end_noreorder (); |
252b5132 RH |
7379 | break; |
7380 | ||
7381 | case M_ULH: | |
7382 | s = "lb"; | |
7383 | goto ulh; | |
7384 | case M_ULHU: | |
7385 | s = "lbu"; | |
7386 | ulh: | |
8fc2e39e | 7387 | used_at = 1; |
252b5132 RH |
7388 | if (offset_expr.X_add_number >= 0x7fff) |
7389 | as_bad (_("operand overflow")); | |
252b5132 | 7390 | if (! target_big_endian) |
f9419b05 | 7391 | ++offset_expr.X_add_number; |
67c0d1eb | 7392 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7393 | if (! target_big_endian) |
f9419b05 | 7394 | --offset_expr.X_add_number; |
252b5132 | 7395 | else |
f9419b05 | 7396 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7397 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7398 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7399 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7400 | break; |
7401 | ||
7402 | case M_ULD: | |
7403 | s = "ldl"; | |
7404 | s2 = "ldr"; | |
7405 | off = 7; | |
7406 | goto ulw; | |
7407 | case M_ULW: | |
7408 | s = "lwl"; | |
7409 | s2 = "lwr"; | |
7410 | off = 3; | |
7411 | ulw: | |
7412 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7413 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7414 | if (treg != breg) |
7415 | tempreg = treg; | |
7416 | else | |
8fc2e39e TS |
7417 | { |
7418 | used_at = 1; | |
7419 | tempreg = AT; | |
7420 | } | |
252b5132 RH |
7421 | if (! target_big_endian) |
7422 | offset_expr.X_add_number += off; | |
67c0d1eb | 7423 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7424 | if (! target_big_endian) |
7425 | offset_expr.X_add_number -= off; | |
7426 | else | |
7427 | offset_expr.X_add_number += off; | |
67c0d1eb | 7428 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7429 | |
7430 | /* If necessary, move the result in tempreg the final destination. */ | |
7431 | if (treg == tempreg) | |
8fc2e39e | 7432 | break; |
af22f5b2 | 7433 | /* Protect second load's delay slot. */ |
017315e4 | 7434 | load_delay_nop (); |
67c0d1eb | 7435 | move_register (treg, tempreg); |
af22f5b2 | 7436 | break; |
252b5132 RH |
7437 | |
7438 | case M_ULD_A: | |
7439 | s = "ldl"; | |
7440 | s2 = "ldr"; | |
7441 | off = 7; | |
7442 | goto ulwa; | |
7443 | case M_ULW_A: | |
7444 | s = "lwl"; | |
7445 | s2 = "lwr"; | |
7446 | off = 3; | |
7447 | ulwa: | |
d6bc6245 | 7448 | used_at = 1; |
67c0d1eb | 7449 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7450 | if (breg != 0) |
67c0d1eb | 7451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7452 | if (! target_big_endian) |
7453 | expr1.X_add_number = off; | |
7454 | else | |
7455 | expr1.X_add_number = 0; | |
67c0d1eb | 7456 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7457 | if (! target_big_endian) |
7458 | expr1.X_add_number = 0; | |
7459 | else | |
7460 | expr1.X_add_number = off; | |
67c0d1eb | 7461 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7462 | break; |
7463 | ||
7464 | case M_ULH_A: | |
7465 | case M_ULHU_A: | |
d6bc6245 | 7466 | used_at = 1; |
67c0d1eb | 7467 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7468 | if (breg != 0) |
67c0d1eb | 7469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7470 | if (target_big_endian) |
7471 | expr1.X_add_number = 0; | |
67c0d1eb | 7472 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7473 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7474 | if (target_big_endian) |
7475 | expr1.X_add_number = 1; | |
7476 | else | |
7477 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7478 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7479 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7480 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7481 | break; |
7482 | ||
7483 | case M_USH: | |
8fc2e39e | 7484 | used_at = 1; |
252b5132 RH |
7485 | if (offset_expr.X_add_number >= 0x7fff) |
7486 | as_bad (_("operand overflow")); | |
7487 | if (target_big_endian) | |
f9419b05 | 7488 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7489 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7490 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7491 | if (target_big_endian) |
f9419b05 | 7492 | --offset_expr.X_add_number; |
252b5132 | 7493 | else |
f9419b05 | 7494 | ++offset_expr.X_add_number; |
67c0d1eb | 7495 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7496 | break; |
7497 | ||
7498 | case M_USD: | |
7499 | s = "sdl"; | |
7500 | s2 = "sdr"; | |
7501 | off = 7; | |
7502 | goto usw; | |
7503 | case M_USW: | |
7504 | s = "swl"; | |
7505 | s2 = "swr"; | |
7506 | off = 3; | |
7507 | usw: | |
7508 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7509 | as_bad (_("operand overflow")); | |
7510 | if (! target_big_endian) | |
7511 | offset_expr.X_add_number += off; | |
67c0d1eb | 7512 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7513 | if (! target_big_endian) |
7514 | offset_expr.X_add_number -= off; | |
7515 | else | |
7516 | offset_expr.X_add_number += off; | |
67c0d1eb | 7517 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7518 | break; |
252b5132 RH |
7519 | |
7520 | case M_USD_A: | |
7521 | s = "sdl"; | |
7522 | s2 = "sdr"; | |
7523 | off = 7; | |
7524 | goto uswa; | |
7525 | case M_USW_A: | |
7526 | s = "swl"; | |
7527 | s2 = "swr"; | |
7528 | off = 3; | |
7529 | uswa: | |
d6bc6245 | 7530 | used_at = 1; |
67c0d1eb | 7531 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7532 | if (breg != 0) |
67c0d1eb | 7533 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7534 | if (! target_big_endian) |
7535 | expr1.X_add_number = off; | |
7536 | else | |
7537 | expr1.X_add_number = 0; | |
67c0d1eb | 7538 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7539 | if (! target_big_endian) |
7540 | expr1.X_add_number = 0; | |
7541 | else | |
7542 | expr1.X_add_number = off; | |
67c0d1eb | 7543 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7544 | break; |
7545 | ||
7546 | case M_USH_A: | |
d6bc6245 | 7547 | used_at = 1; |
67c0d1eb | 7548 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7549 | if (breg != 0) |
67c0d1eb | 7550 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7551 | if (! target_big_endian) |
7552 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7553 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7554 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7555 | if (! target_big_endian) |
7556 | expr1.X_add_number = 1; | |
7557 | else | |
7558 | expr1.X_add_number = 0; | |
67c0d1eb | 7559 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7560 | if (! target_big_endian) |
7561 | expr1.X_add_number = 0; | |
7562 | else | |
7563 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7564 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7565 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7566 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7567 | break; |
7568 | ||
7569 | default: | |
7570 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7571 | are added dynamically. */ |
252b5132 RH |
7572 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7573 | break; | |
7574 | } | |
8fc2e39e TS |
7575 | if (mips_opts.noat && used_at) |
7576 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7577 | } |
7578 | ||
7579 | /* Implement macros in mips16 mode. */ | |
7580 | ||
7581 | static void | |
17a2f251 | 7582 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7583 | { |
7584 | int mask; | |
7585 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7586 | expressionS expr1; |
7587 | int dbl; | |
7588 | const char *s, *s2, *s3; | |
7589 | ||
7590 | mask = ip->insn_mo->mask; | |
7591 | ||
bf12938e RS |
7592 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7593 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7594 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7595 | |
252b5132 RH |
7596 | expr1.X_op = O_constant; |
7597 | expr1.X_op_symbol = NULL; | |
7598 | expr1.X_add_symbol = NULL; | |
7599 | expr1.X_add_number = 1; | |
7600 | ||
7601 | dbl = 0; | |
7602 | ||
7603 | switch (mask) | |
7604 | { | |
7605 | default: | |
7606 | internalError (); | |
7607 | ||
7608 | case M_DDIV_3: | |
7609 | dbl = 1; | |
7610 | case M_DIV_3: | |
7611 | s = "mflo"; | |
7612 | goto do_div3; | |
7613 | case M_DREM_3: | |
7614 | dbl = 1; | |
7615 | case M_REM_3: | |
7616 | s = "mfhi"; | |
7617 | do_div3: | |
7d10b47d | 7618 | start_noreorder (); |
67c0d1eb | 7619 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7620 | expr1.X_add_number = 2; |
67c0d1eb RS |
7621 | macro_build (&expr1, "bnez", "x,p", yreg); |
7622 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7623 | |
252b5132 RH |
7624 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7625 | since that causes an overflow. We should do that as well, | |
7626 | but I don't see how to do the comparisons without a temporary | |
7627 | register. */ | |
7d10b47d | 7628 | end_noreorder (); |
67c0d1eb | 7629 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7630 | break; |
7631 | ||
7632 | case M_DIVU_3: | |
7633 | s = "divu"; | |
7634 | s2 = "mflo"; | |
7635 | goto do_divu3; | |
7636 | case M_REMU_3: | |
7637 | s = "divu"; | |
7638 | s2 = "mfhi"; | |
7639 | goto do_divu3; | |
7640 | case M_DDIVU_3: | |
7641 | s = "ddivu"; | |
7642 | s2 = "mflo"; | |
7643 | goto do_divu3; | |
7644 | case M_DREMU_3: | |
7645 | s = "ddivu"; | |
7646 | s2 = "mfhi"; | |
7647 | do_divu3: | |
7d10b47d | 7648 | start_noreorder (); |
67c0d1eb | 7649 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7650 | expr1.X_add_number = 2; |
67c0d1eb RS |
7651 | macro_build (&expr1, "bnez", "x,p", yreg); |
7652 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7653 | end_noreorder (); |
67c0d1eb | 7654 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7655 | break; |
7656 | ||
7657 | case M_DMUL: | |
7658 | dbl = 1; | |
7659 | case M_MUL: | |
67c0d1eb RS |
7660 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7661 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7662 | break; |
252b5132 RH |
7663 | |
7664 | case M_DSUBU_I: | |
7665 | dbl = 1; | |
7666 | goto do_subu; | |
7667 | case M_SUBU_I: | |
7668 | do_subu: | |
7669 | if (imm_expr.X_op != O_constant) | |
7670 | as_bad (_("Unsupported large constant")); | |
7671 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7672 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7673 | break; |
7674 | ||
7675 | case M_SUBU_I_2: | |
7676 | if (imm_expr.X_op != O_constant) | |
7677 | as_bad (_("Unsupported large constant")); | |
7678 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7679 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7680 | break; |
7681 | ||
7682 | case M_DSUBU_I_2: | |
7683 | if (imm_expr.X_op != O_constant) | |
7684 | as_bad (_("Unsupported large constant")); | |
7685 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7686 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7687 | break; |
7688 | ||
7689 | case M_BEQ: | |
7690 | s = "cmp"; | |
7691 | s2 = "bteqz"; | |
7692 | goto do_branch; | |
7693 | case M_BNE: | |
7694 | s = "cmp"; | |
7695 | s2 = "btnez"; | |
7696 | goto do_branch; | |
7697 | case M_BLT: | |
7698 | s = "slt"; | |
7699 | s2 = "btnez"; | |
7700 | goto do_branch; | |
7701 | case M_BLTU: | |
7702 | s = "sltu"; | |
7703 | s2 = "btnez"; | |
7704 | goto do_branch; | |
7705 | case M_BLE: | |
7706 | s = "slt"; | |
7707 | s2 = "bteqz"; | |
7708 | goto do_reverse_branch; | |
7709 | case M_BLEU: | |
7710 | s = "sltu"; | |
7711 | s2 = "bteqz"; | |
7712 | goto do_reverse_branch; | |
7713 | case M_BGE: | |
7714 | s = "slt"; | |
7715 | s2 = "bteqz"; | |
7716 | goto do_branch; | |
7717 | case M_BGEU: | |
7718 | s = "sltu"; | |
7719 | s2 = "bteqz"; | |
7720 | goto do_branch; | |
7721 | case M_BGT: | |
7722 | s = "slt"; | |
7723 | s2 = "btnez"; | |
7724 | goto do_reverse_branch; | |
7725 | case M_BGTU: | |
7726 | s = "sltu"; | |
7727 | s2 = "btnez"; | |
7728 | ||
7729 | do_reverse_branch: | |
7730 | tmp = xreg; | |
7731 | xreg = yreg; | |
7732 | yreg = tmp; | |
7733 | ||
7734 | do_branch: | |
67c0d1eb RS |
7735 | macro_build (NULL, s, "x,y", xreg, yreg); |
7736 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7737 | break; |
7738 | ||
7739 | case M_BEQ_I: | |
7740 | s = "cmpi"; | |
7741 | s2 = "bteqz"; | |
7742 | s3 = "x,U"; | |
7743 | goto do_branch_i; | |
7744 | case M_BNE_I: | |
7745 | s = "cmpi"; | |
7746 | s2 = "btnez"; | |
7747 | s3 = "x,U"; | |
7748 | goto do_branch_i; | |
7749 | case M_BLT_I: | |
7750 | s = "slti"; | |
7751 | s2 = "btnez"; | |
7752 | s3 = "x,8"; | |
7753 | goto do_branch_i; | |
7754 | case M_BLTU_I: | |
7755 | s = "sltiu"; | |
7756 | s2 = "btnez"; | |
7757 | s3 = "x,8"; | |
7758 | goto do_branch_i; | |
7759 | case M_BLE_I: | |
7760 | s = "slti"; | |
7761 | s2 = "btnez"; | |
7762 | s3 = "x,8"; | |
7763 | goto do_addone_branch_i; | |
7764 | case M_BLEU_I: | |
7765 | s = "sltiu"; | |
7766 | s2 = "btnez"; | |
7767 | s3 = "x,8"; | |
7768 | goto do_addone_branch_i; | |
7769 | case M_BGE_I: | |
7770 | s = "slti"; | |
7771 | s2 = "bteqz"; | |
7772 | s3 = "x,8"; | |
7773 | goto do_branch_i; | |
7774 | case M_BGEU_I: | |
7775 | s = "sltiu"; | |
7776 | s2 = "bteqz"; | |
7777 | s3 = "x,8"; | |
7778 | goto do_branch_i; | |
7779 | case M_BGT_I: | |
7780 | s = "slti"; | |
7781 | s2 = "bteqz"; | |
7782 | s3 = "x,8"; | |
7783 | goto do_addone_branch_i; | |
7784 | case M_BGTU_I: | |
7785 | s = "sltiu"; | |
7786 | s2 = "bteqz"; | |
7787 | s3 = "x,8"; | |
7788 | ||
7789 | do_addone_branch_i: | |
7790 | if (imm_expr.X_op != O_constant) | |
7791 | as_bad (_("Unsupported large constant")); | |
7792 | ++imm_expr.X_add_number; | |
7793 | ||
7794 | do_branch_i: | |
67c0d1eb RS |
7795 | macro_build (&imm_expr, s, s3, xreg); |
7796 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7797 | break; |
7798 | ||
7799 | case M_ABS: | |
7800 | expr1.X_add_number = 0; | |
67c0d1eb | 7801 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7802 | if (xreg != yreg) |
67c0d1eb | 7803 | move_register (xreg, yreg); |
252b5132 | 7804 | expr1.X_add_number = 2; |
67c0d1eb RS |
7805 | macro_build (&expr1, "bteqz", "p"); |
7806 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7807 | } |
7808 | } | |
7809 | ||
7810 | /* For consistency checking, verify that all bits are specified either | |
7811 | by the match/mask part of the instruction definition, or by the | |
7812 | operand list. */ | |
7813 | static int | |
17a2f251 | 7814 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7815 | { |
7816 | const char *p = opc->args; | |
7817 | char c; | |
7818 | unsigned long used_bits = opc->mask; | |
7819 | ||
7820 | if ((used_bits & opc->match) != opc->match) | |
7821 | { | |
7822 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7823 | opc->name, opc->args); | |
7824 | return 0; | |
7825 | } | |
7826 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7827 | while (*p) | |
7828 | switch (c = *p++) | |
7829 | { | |
7830 | case ',': break; | |
7831 | case '(': break; | |
7832 | case ')': break; | |
af7ee8bf CD |
7833 | case '+': |
7834 | switch (c = *p++) | |
7835 | { | |
9bcd4f99 TS |
7836 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
7837 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
7838 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
7839 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
7840 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7841 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7842 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7843 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7844 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7845 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7846 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7847 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7848 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7849 | case 'I': break; | |
ef2e4d86 CF |
7850 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
7851 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
7852 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
7853 | default: |
7854 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7855 | c, opc->name, opc->args); | |
7856 | return 0; | |
7857 | } | |
7858 | break; | |
252b5132 RH |
7859 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7860 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7861 | case 'A': break; | |
4372b673 | 7862 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7863 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7864 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7865 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7866 | case 'F': break; | |
7867 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7868 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7869 | case 'I': break; |
e972090a | 7870 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7871 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7872 | case 'L': break; |
7873 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7874 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7875 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7876 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7877 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7878 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7879 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7880 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7881 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7882 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7883 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7884 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7885 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7886 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7887 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7888 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7889 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7890 | case 'f': break; | |
7891 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7892 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7893 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7894 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7895 | case 'l': break; | |
7896 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7897 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7898 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7899 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7900 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7901 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7902 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7903 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7904 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7905 | case 'x': break; | |
7906 | case 'z': break; | |
7907 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7908 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7909 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7910 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7911 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7912 | case '[': break; | |
7913 | case ']': break; | |
74cd071d CF |
7914 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
7915 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
7916 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
7917 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7918 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
7919 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
7920 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
7921 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
7922 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
7923 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
7924 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
7925 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
7926 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
7927 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
7928 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
7929 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
7930 | default: |
7931 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7932 | c, opc->name, opc->args); | |
7933 | return 0; | |
7934 | } | |
7935 | #undef USE_BITS | |
7936 | if (used_bits != 0xffffffff) | |
7937 | { | |
7938 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7939 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7940 | return 0; | |
7941 | } | |
7942 | return 1; | |
7943 | } | |
7944 | ||
9bcd4f99 TS |
7945 | /* UDI immediates. */ |
7946 | struct mips_immed { | |
7947 | char type; | |
7948 | unsigned int shift; | |
7949 | unsigned long mask; | |
7950 | const char * desc; | |
7951 | }; | |
7952 | ||
7953 | static const struct mips_immed mips_immed[] = { | |
7954 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
7955 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
7956 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
7957 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
7958 | { 0,0,0,0 } | |
7959 | }; | |
7960 | ||
252b5132 RH |
7961 | /* This routine assembles an instruction into its binary format. As a |
7962 | side effect, it sets one of the global variables imm_reloc or | |
7963 | offset_reloc to the type of relocation to do if one of the operands | |
7964 | is an address expression. */ | |
7965 | ||
7966 | static void | |
17a2f251 | 7967 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7968 | { |
7969 | char *s; | |
7970 | const char *args; | |
43841e91 | 7971 | char c = 0; |
252b5132 RH |
7972 | struct mips_opcode *insn; |
7973 | char *argsStart; | |
7974 | unsigned int regno; | |
7975 | unsigned int lastregno = 0; | |
af7ee8bf | 7976 | unsigned int lastpos = 0; |
071742cf | 7977 | unsigned int limlo, limhi; |
252b5132 RH |
7978 | char *s_reset; |
7979 | char save_c = 0; | |
74cd071d | 7980 | offsetT min_range, max_range; |
252b5132 RH |
7981 | |
7982 | insn_error = NULL; | |
7983 | ||
7984 | /* If the instruction contains a '.', we first try to match an instruction | |
7985 | including the '.'. Then we try again without the '.'. */ | |
7986 | insn = NULL; | |
3882b010 | 7987 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7988 | continue; |
7989 | ||
7990 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7991 | the call to hash_find. Save the character we replaced just in case we | |
7992 | have to re-parse the instruction. */ | |
3882b010 | 7993 | if (ISSPACE (*s)) |
252b5132 RH |
7994 | { |
7995 | save_c = *s; | |
7996 | *s++ = '\0'; | |
7997 | } | |
bdaaa2e1 | 7998 | |
252b5132 RH |
7999 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8000 | ||
8001 | /* If we didn't find the instruction in the opcode table, try again, but | |
8002 | this time with just the instruction up to, but not including the | |
8003 | first '.'. */ | |
8004 | if (insn == NULL) | |
8005 | { | |
bdaaa2e1 | 8006 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8007 | if (save_c) |
8008 | *(--s) = save_c; | |
8009 | ||
8010 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8011 | for (s = str; |
8012 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8013 | ++s) | |
252b5132 RH |
8014 | continue; |
8015 | ||
8016 | /* If we did not find a '.', then we can quit now. */ | |
8017 | if (*s != '.') | |
8018 | { | |
8019 | insn_error = "unrecognized opcode"; | |
8020 | return; | |
8021 | } | |
8022 | ||
8023 | /* Lookup the instruction in the hash table. */ | |
8024 | *s++ = '\0'; | |
8025 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8026 | { | |
8027 | insn_error = "unrecognized opcode"; | |
8028 | return; | |
8029 | } | |
252b5132 RH |
8030 | } |
8031 | ||
8032 | argsStart = s; | |
8033 | for (;;) | |
8034 | { | |
b34976b6 | 8035 | bfd_boolean ok; |
252b5132 RH |
8036 | |
8037 | assert (strcmp (insn->name, str) == 0); | |
8038 | ||
1f25f5d3 CD |
8039 | if (OPCODE_IS_MEMBER (insn, |
8040 | (mips_opts.isa | |
3396de36 | 8041 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8042 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8043 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
ef2e4d86 | 8044 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8045 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8046 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8047 | mips_opts.arch)) |
b34976b6 | 8048 | ok = TRUE; |
bdaaa2e1 | 8049 | else |
b34976b6 | 8050 | ok = FALSE; |
bdaaa2e1 | 8051 | |
252b5132 RH |
8052 | if (insn->pinfo != INSN_MACRO) |
8053 | { | |
fef14a42 | 8054 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8055 | ok = FALSE; |
252b5132 RH |
8056 | } |
8057 | ||
8058 | if (! ok) | |
8059 | { | |
8060 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8061 | && strcmp (insn->name, insn[1].name) == 0) | |
8062 | { | |
8063 | ++insn; | |
8064 | continue; | |
8065 | } | |
252b5132 | 8066 | else |
beae10d5 | 8067 | { |
268f6bed L |
8068 | if (!insn_error) |
8069 | { | |
8070 | static char buf[100]; | |
fef14a42 TS |
8071 | sprintf (buf, |
8072 | _("opcode not supported on this processor: %s (%s)"), | |
8073 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8074 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8075 | insn_error = buf; |
8076 | } | |
8077 | if (save_c) | |
8078 | *(--s) = save_c; | |
2bd7f1f3 | 8079 | return; |
252b5132 | 8080 | } |
252b5132 RH |
8081 | } |
8082 | ||
1e915849 | 8083 | create_insn (ip, insn); |
268f6bed | 8084 | insn_error = NULL; |
252b5132 RH |
8085 | for (args = insn->args;; ++args) |
8086 | { | |
deec1734 CD |
8087 | int is_mdmx; |
8088 | ||
ad8d3bb3 | 8089 | s += strspn (s, " \t"); |
deec1734 | 8090 | is_mdmx = 0; |
252b5132 RH |
8091 | switch (*args) |
8092 | { | |
8093 | case '\0': /* end of args */ | |
8094 | if (*s == '\0') | |
8095 | return; | |
8096 | break; | |
8097 | ||
74cd071d CF |
8098 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8099 | my_getExpression (&imm_expr, s); | |
8100 | check_absolute_expr (ip, &imm_expr); | |
8101 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8102 | { | |
8103 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8104 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
8105 | imm_expr.X_add_number &= OP_MASK_SA3; | |
8106 | } | |
8107 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3; | |
8108 | imm_expr.X_op = O_absent; | |
8109 | s = expr_end; | |
8110 | continue; | |
8111 | ||
8112 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8113 | my_getExpression (&imm_expr, s); | |
8114 | check_absolute_expr (ip, &imm_expr); | |
8115 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8116 | { | |
8117 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8118 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
8119 | imm_expr.X_add_number &= OP_MASK_SA4; | |
8120 | } | |
8121 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4; | |
8122 | imm_expr.X_op = O_absent; | |
8123 | s = expr_end; | |
8124 | continue; | |
8125 | ||
8126 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8127 | my_getExpression (&imm_expr, s); | |
8128 | check_absolute_expr (ip, &imm_expr); | |
8129 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8130 | { | |
8131 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8132 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
8133 | imm_expr.X_add_number &= OP_MASK_IMM8; | |
8134 | } | |
8135 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8; | |
8136 | imm_expr.X_op = O_absent; | |
8137 | s = expr_end; | |
8138 | continue; | |
8139 | ||
8140 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8141 | my_getExpression (&imm_expr, s); | |
8142 | check_absolute_expr (ip, &imm_expr); | |
8143 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8144 | { | |
8145 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8146 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
8147 | imm_expr.X_add_number &= OP_MASK_RS; | |
8148 | } | |
8149 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS; | |
8150 | imm_expr.X_op = O_absent; | |
8151 | s = expr_end; | |
8152 | continue; | |
8153 | ||
8154 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8155 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8156 | s[3] >= '0' && s[3] <= '3') | |
8157 | { | |
8158 | regno = s[3] - '0'; | |
8159 | s += 4; | |
8160 | ip->insn_opcode |= regno << OP_SH_DSPACC; | |
8161 | continue; | |
8162 | } | |
8163 | else | |
8164 | as_bad (_("Invalid dsp acc register")); | |
8165 | break; | |
8166 | ||
8167 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8168 | my_getExpression (&imm_expr, s); | |
8169 | check_absolute_expr (ip, &imm_expr); | |
8170 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8171 | { | |
8172 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8173 | OP_MASK_WRDSP, | |
8174 | (unsigned long) imm_expr.X_add_number); | |
8175 | imm_expr.X_add_number &= OP_MASK_WRDSP; | |
8176 | } | |
8177 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP; | |
8178 | imm_expr.X_op = O_absent; | |
8179 | s = expr_end; | |
8180 | continue; | |
8181 | ||
8182 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8183 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8184 | s[3] >= '0' && s[3] <= '3') | |
8185 | { | |
8186 | regno = s[3] - '0'; | |
8187 | s += 4; | |
8188 | ip->insn_opcode |= regno << OP_SH_DSPACC_S; | |
8189 | continue; | |
8190 | } | |
8191 | else | |
8192 | as_bad (_("Invalid dsp acc register")); | |
8193 | break; | |
8194 | ||
8195 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8196 | my_getExpression (&imm_expr, s); | |
8197 | check_absolute_expr (ip, &imm_expr); | |
8198 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8199 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8200 | if (imm_expr.X_add_number < min_range || | |
8201 | imm_expr.X_add_number > max_range) | |
8202 | { | |
8203 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8204 | (long) min_range, (long) max_range, | |
8205 | (long) imm_expr.X_add_number); | |
8206 | } | |
8207 | imm_expr.X_add_number &= OP_MASK_DSPSFT; | |
8208 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8209 | << OP_SH_DSPSFT); | |
8210 | imm_expr.X_op = O_absent; | |
8211 | s = expr_end; | |
8212 | continue; | |
8213 | ||
8214 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8215 | my_getExpression (&imm_expr, s); | |
8216 | check_absolute_expr (ip, &imm_expr); | |
8217 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8218 | { | |
8219 | as_warn (_("DSP immediate not in range 0..%d (%lu)"), | |
8220 | OP_MASK_RDDSP, | |
8221 | (unsigned long) imm_expr.X_add_number); | |
8222 | imm_expr.X_add_number &= OP_MASK_RDDSP; | |
8223 | } | |
8224 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP; | |
8225 | imm_expr.X_op = O_absent; | |
8226 | s = expr_end; | |
8227 | continue; | |
8228 | ||
8229 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8230 | my_getExpression (&imm_expr, s); | |
8231 | check_absolute_expr (ip, &imm_expr); | |
8232 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8233 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8234 | if (imm_expr.X_add_number < min_range || | |
8235 | imm_expr.X_add_number > max_range) | |
8236 | { | |
8237 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8238 | (long) min_range, (long) max_range, | |
8239 | (long) imm_expr.X_add_number); | |
8240 | } | |
8241 | imm_expr.X_add_number &= OP_MASK_DSPSFT_7; | |
8242 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8243 | << OP_SH_DSPSFT_7); | |
8244 | imm_expr.X_op = O_absent; | |
8245 | s = expr_end; | |
8246 | continue; | |
8247 | ||
8248 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8249 | my_getExpression (&imm_expr, s); | |
8250 | check_absolute_expr (ip, &imm_expr); | |
8251 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8252 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8253 | if (imm_expr.X_add_number < min_range || | |
8254 | imm_expr.X_add_number > max_range) | |
8255 | { | |
8256 | as_warn (_("DSP immediate not in range %ld..%ld (%ld)"), | |
8257 | (long) min_range, (long) max_range, | |
8258 | (long) imm_expr.X_add_number); | |
8259 | } | |
8260 | imm_expr.X_add_number &= OP_MASK_IMM10; | |
8261 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8262 | << OP_SH_IMM10); | |
8263 | imm_expr.X_op = O_absent; | |
8264 | s = expr_end; | |
8265 | continue; | |
8266 | ||
ef2e4d86 CF |
8267 | case '!': /* mt 1-bit unsigned immediate in bit 5 */ |
8268 | my_getExpression (&imm_expr, s); | |
8269 | check_absolute_expr (ip, &imm_expr); | |
8270 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
8271 | { | |
8272 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8273 | OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number); | |
8274 | imm_expr.X_add_number &= OP_MASK_MT_U; | |
8275 | } | |
8276 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U; | |
8277 | imm_expr.X_op = O_absent; | |
8278 | s = expr_end; | |
8279 | continue; | |
8280 | ||
8281 | case '$': /* mt 1-bit unsigned immediate in bit 4 */ | |
8282 | my_getExpression (&imm_expr, s); | |
8283 | check_absolute_expr (ip, &imm_expr); | |
8284 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
8285 | { | |
8286 | as_warn (_("MT immediate not in range 0..%d (%lu)"), | |
8287 | OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number); | |
8288 | imm_expr.X_add_number &= OP_MASK_MT_H; | |
8289 | } | |
8290 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H; | |
8291 | imm_expr.X_op = O_absent; | |
8292 | s = expr_end; | |
8293 | continue; | |
8294 | ||
8295 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8296 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8297 | s[3] >= '0' && s[3] <= '3') | |
8298 | { | |
8299 | regno = s[3] - '0'; | |
8300 | s += 4; | |
8301 | ip->insn_opcode |= regno << OP_SH_MTACC_T; | |
8302 | continue; | |
8303 | } | |
8304 | else | |
8305 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8306 | break; | |
8307 | ||
8308 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8309 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8310 | s[3] >= '0' && s[3] <= '3') | |
8311 | { | |
8312 | regno = s[3] - '0'; | |
8313 | s += 4; | |
8314 | ip->insn_opcode |= regno << OP_SH_MTACC_D; | |
8315 | continue; | |
8316 | } | |
8317 | else | |
8318 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8319 | break; | |
8320 | ||
252b5132 RH |
8321 | case ',': |
8322 | if (*s++ == *args) | |
8323 | continue; | |
8324 | s--; | |
8325 | switch (*++args) | |
8326 | { | |
8327 | case 'r': | |
8328 | case 'v': | |
bf12938e | 8329 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8330 | continue; |
8331 | ||
8332 | case 'w': | |
bf12938e | 8333 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8334 | continue; |
8335 | ||
252b5132 | 8336 | case 'W': |
bf12938e | 8337 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8338 | continue; |
8339 | ||
8340 | case 'V': | |
bf12938e | 8341 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8342 | continue; |
8343 | } | |
8344 | break; | |
8345 | ||
8346 | case '(': | |
8347 | /* Handle optional base register. | |
8348 | Either the base register is omitted or | |
bdaaa2e1 | 8349 | we must have a left paren. */ |
252b5132 RH |
8350 | /* This is dependent on the next operand specifier |
8351 | is a base register specification. */ | |
8352 | assert (args[1] == 'b' || args[1] == '5' | |
8353 | || args[1] == '-' || args[1] == '4'); | |
8354 | if (*s == '\0') | |
8355 | return; | |
8356 | ||
8357 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8358 | case '[': |
8359 | case ']': | |
252b5132 RH |
8360 | if (*s++ == *args) |
8361 | continue; | |
8362 | break; | |
8363 | ||
af7ee8bf CD |
8364 | case '+': /* Opcode extension character. */ |
8365 | switch (*++args) | |
8366 | { | |
9bcd4f99 TS |
8367 | case '1': /* UDI immediates. */ |
8368 | case '2': | |
8369 | case '3': | |
8370 | case '4': | |
8371 | { | |
8372 | const struct mips_immed *imm = mips_immed; | |
8373 | ||
8374 | while (imm->type && imm->type != *args) | |
8375 | ++imm; | |
8376 | if (! imm->type) | |
8377 | internalError (); | |
8378 | my_getExpression (&imm_expr, s); | |
8379 | check_absolute_expr (ip, &imm_expr); | |
8380 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8381 | { | |
8382 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8383 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8384 | (unsigned long) imm_expr.X_add_number, | |
8385 | (unsigned long) imm_expr.X_add_number); | |
8386 | imm_expr.X_add_number &= imm->mask; | |
8387 | } | |
8388 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8389 | << imm->shift); | |
8390 | imm_expr.X_op = O_absent; | |
8391 | s = expr_end; | |
8392 | } | |
8393 | continue; | |
8394 | ||
071742cf CD |
8395 | case 'A': /* ins/ext position, becomes LSB. */ |
8396 | limlo = 0; | |
8397 | limhi = 31; | |
5f74bc13 CD |
8398 | goto do_lsb; |
8399 | case 'E': | |
8400 | limlo = 32; | |
8401 | limhi = 63; | |
8402 | goto do_lsb; | |
8403 | do_lsb: | |
071742cf CD |
8404 | my_getExpression (&imm_expr, s); |
8405 | check_absolute_expr (ip, &imm_expr); | |
8406 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8407 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8408 | { | |
8409 | as_bad (_("Improper position (%lu)"), | |
8410 | (unsigned long) imm_expr.X_add_number); | |
8411 | imm_expr.X_add_number = limlo; | |
8412 | } | |
8413 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8414 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8415 | imm_expr.X_op = O_absent; |
8416 | s = expr_end; | |
8417 | continue; | |
8418 | ||
8419 | case 'B': /* ins size, becomes MSB. */ | |
8420 | limlo = 1; | |
8421 | limhi = 32; | |
5f74bc13 CD |
8422 | goto do_msb; |
8423 | case 'F': | |
8424 | limlo = 33; | |
8425 | limhi = 64; | |
8426 | goto do_msb; | |
8427 | do_msb: | |
071742cf CD |
8428 | my_getExpression (&imm_expr, s); |
8429 | check_absolute_expr (ip, &imm_expr); | |
8430 | /* Check for negative input so that small negative numbers | |
8431 | will not succeed incorrectly. The checks against | |
8432 | (pos+size) transitively check "size" itself, | |
8433 | assuming that "pos" is reasonable. */ | |
8434 | if ((long) imm_expr.X_add_number < 0 | |
8435 | || ((unsigned long) imm_expr.X_add_number | |
8436 | + lastpos) < limlo | |
8437 | || ((unsigned long) imm_expr.X_add_number | |
8438 | + lastpos) > limhi) | |
8439 | { | |
8440 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8441 | (unsigned long) imm_expr.X_add_number, | |
8442 | (unsigned long) lastpos); | |
8443 | imm_expr.X_add_number = limlo - lastpos; | |
8444 | } | |
bf12938e RS |
8445 | INSERT_OPERAND (INSMSB, *ip, |
8446 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8447 | imm_expr.X_op = O_absent; |
8448 | s = expr_end; | |
8449 | continue; | |
8450 | ||
8451 | case 'C': /* ext size, becomes MSBD. */ | |
8452 | limlo = 1; | |
8453 | limhi = 32; | |
5f74bc13 CD |
8454 | goto do_msbd; |
8455 | case 'G': | |
8456 | limlo = 33; | |
8457 | limhi = 64; | |
8458 | goto do_msbd; | |
8459 | case 'H': | |
8460 | limlo = 33; | |
8461 | limhi = 64; | |
8462 | goto do_msbd; | |
8463 | do_msbd: | |
071742cf CD |
8464 | my_getExpression (&imm_expr, s); |
8465 | check_absolute_expr (ip, &imm_expr); | |
8466 | /* Check for negative input so that small negative numbers | |
8467 | will not succeed incorrectly. The checks against | |
8468 | (pos+size) transitively check "size" itself, | |
8469 | assuming that "pos" is reasonable. */ | |
8470 | if ((long) imm_expr.X_add_number < 0 | |
8471 | || ((unsigned long) imm_expr.X_add_number | |
8472 | + lastpos) < limlo | |
8473 | || ((unsigned long) imm_expr.X_add_number | |
8474 | + lastpos) > limhi) | |
8475 | { | |
8476 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8477 | (unsigned long) imm_expr.X_add_number, | |
8478 | (unsigned long) lastpos); | |
8479 | imm_expr.X_add_number = limlo - lastpos; | |
8480 | } | |
bf12938e | 8481 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8482 | imm_expr.X_op = O_absent; |
8483 | s = expr_end; | |
8484 | continue; | |
af7ee8bf | 8485 | |
bbcc0807 CD |
8486 | case 'D': |
8487 | /* +D is for disassembly only; never match. */ | |
8488 | break; | |
8489 | ||
5f74bc13 CD |
8490 | case 'I': |
8491 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8492 | my_getExpression (&imm2_expr, s); | |
8493 | if (imm2_expr.X_op != O_big | |
8494 | && imm2_expr.X_op != O_constant) | |
8495 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8496 | if (HAVE_32BIT_GPRS) |
8497 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8498 | s = expr_end; |
8499 | continue; | |
8500 | ||
ef2e4d86 CF |
8501 | case 'T': /* Coprocessor register */ |
8502 | /* +T is for disassembly only; never match. */ | |
8503 | break; | |
8504 | ||
8505 | case 't': /* Coprocessor register number */ | |
8506 | if (s[0] == '$' && ISDIGIT (s[1])) | |
8507 | { | |
8508 | ++s; | |
8509 | regno = 0; | |
8510 | do | |
8511 | { | |
8512 | regno *= 10; | |
8513 | regno += *s - '0'; | |
8514 | ++s; | |
8515 | } | |
8516 | while (ISDIGIT (*s)); | |
8517 | if (regno > 31) | |
8518 | as_bad (_("Invalid register number (%d)"), regno); | |
8519 | else | |
8520 | { | |
8521 | ip->insn_opcode |= regno << OP_SH_RT; | |
8522 | continue; | |
8523 | } | |
8524 | } | |
8525 | else | |
8526 | as_bad (_("Invalid coprocessor 0 register number")); | |
8527 | break; | |
8528 | ||
af7ee8bf CD |
8529 | default: |
8530 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8531 | *args, insn->name, insn->args); | |
8532 | /* Further processing is fruitless. */ | |
8533 | return; | |
8534 | } | |
8535 | break; | |
8536 | ||
252b5132 RH |
8537 | case '<': /* must be at least one digit */ |
8538 | /* | |
8539 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8540 | * than 31 or less than 0, then the shift amount should be |
8541 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8542 | * We issue a warning and mask out all but the low 5 bits. |
8543 | */ | |
8544 | my_getExpression (&imm_expr, s); | |
8545 | check_absolute_expr (ip, &imm_expr); | |
8546 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8547 | as_warn (_("Improper shift amount (%lu)"), |
8548 | (unsigned long) imm_expr.X_add_number); | |
8549 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8550 | imm_expr.X_op = O_absent; |
8551 | s = expr_end; | |
8552 | continue; | |
8553 | ||
8554 | case '>': /* shift amount minus 32 */ | |
8555 | my_getExpression (&imm_expr, s); | |
8556 | check_absolute_expr (ip, &imm_expr); | |
8557 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8558 | || (unsigned long) imm_expr.X_add_number > 63) | |
8559 | break; | |
bf12938e | 8560 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8561 | imm_expr.X_op = O_absent; |
8562 | s = expr_end; | |
8563 | continue; | |
8564 | ||
252b5132 RH |
8565 | case 'k': /* cache code */ |
8566 | case 'h': /* prefx code */ | |
8567 | my_getExpression (&imm_expr, s); | |
8568 | check_absolute_expr (ip, &imm_expr); | |
8569 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8570 | as_warn (_("Invalid value for `%s' (%lu)"), |
8571 | ip->insn_mo->name, | |
8572 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8573 | if (*args == 'k') |
bf12938e | 8574 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8575 | else |
bf12938e | 8576 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8577 | imm_expr.X_op = O_absent; |
8578 | s = expr_end; | |
8579 | continue; | |
8580 | ||
8581 | case 'c': /* break code */ | |
8582 | my_getExpression (&imm_expr, s); | |
8583 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8584 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8585 | as_warn (_("Illegal break code (%lu)"), |
8586 | (unsigned long) imm_expr.X_add_number); | |
8587 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8588 | imm_expr.X_op = O_absent; |
8589 | s = expr_end; | |
8590 | continue; | |
8591 | ||
8592 | case 'q': /* lower break code */ | |
8593 | my_getExpression (&imm_expr, s); | |
8594 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8595 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8596 | as_warn (_("Illegal lower break code (%lu)"), |
8597 | (unsigned long) imm_expr.X_add_number); | |
8598 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8599 | imm_expr.X_op = O_absent; |
8600 | s = expr_end; | |
8601 | continue; | |
8602 | ||
4372b673 | 8603 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8604 | my_getExpression (&imm_expr, s); |
156c2f8b | 8605 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8606 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8607 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8608 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8609 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8610 | imm_expr.X_op = O_absent; |
8611 | s = expr_end; | |
8612 | continue; | |
8613 | ||
98d3f06f | 8614 | case 'C': /* Coprocessor code */ |
beae10d5 | 8615 | my_getExpression (&imm_expr, s); |
252b5132 | 8616 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8617 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8618 | { |
793b27f4 TS |
8619 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8620 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8621 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8622 | } |
beae10d5 KH |
8623 | ip->insn_opcode |= imm_expr.X_add_number; |
8624 | imm_expr.X_op = O_absent; | |
8625 | s = expr_end; | |
8626 | continue; | |
252b5132 | 8627 | |
4372b673 NC |
8628 | case 'J': /* 19-bit wait code. */ |
8629 | my_getExpression (&imm_expr, s); | |
8630 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8631 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8632 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8633 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8634 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8635 | imm_expr.X_op = O_absent; |
8636 | s = expr_end; | |
8637 | continue; | |
8638 | ||
252b5132 | 8639 | case 'P': /* Performance register */ |
beae10d5 | 8640 | my_getExpression (&imm_expr, s); |
252b5132 | 8641 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8642 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8643 | as_warn (_("Invalid performance register (%lu)"), |
8644 | (unsigned long) imm_expr.X_add_number); | |
8645 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8646 | imm_expr.X_op = O_absent; |
8647 | s = expr_end; | |
8648 | continue; | |
252b5132 RH |
8649 | |
8650 | case 'b': /* base register */ | |
8651 | case 'd': /* destination register */ | |
8652 | case 's': /* source register */ | |
8653 | case 't': /* target register */ | |
8654 | case 'r': /* both target and source */ | |
8655 | case 'v': /* both dest and source */ | |
8656 | case 'w': /* both dest and target */ | |
8657 | case 'E': /* coprocessor target register */ | |
8658 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8659 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8660 | case 'x': /* ignore register name */ |
8661 | case 'z': /* must be zero register */ | |
4372b673 | 8662 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 8663 | case 'g': /* coprocessor destination register */ |
252b5132 RH |
8664 | s_reset = s; |
8665 | if (s[0] == '$') | |
8666 | { | |
3882b010 | 8667 | if (ISDIGIT (s[1])) |
252b5132 RH |
8668 | { |
8669 | ++s; | |
8670 | regno = 0; | |
8671 | do | |
8672 | { | |
8673 | regno *= 10; | |
8674 | regno += *s - '0'; | |
8675 | ++s; | |
8676 | } | |
3882b010 | 8677 | while (ISDIGIT (*s)); |
252b5132 RH |
8678 | if (regno > 31) |
8679 | as_bad (_("Invalid register number (%d)"), regno); | |
8680 | } | |
af7ee8bf | 8681 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8682 | goto notreg; |
8683 | else | |
8684 | { | |
76db943d TS |
8685 | if (s[1] == 'r' && s[2] == 'a') |
8686 | { | |
8687 | s += 3; | |
8688 | regno = RA; | |
8689 | } | |
8690 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8691 | { |
8692 | s += 3; | |
8693 | regno = FP; | |
8694 | } | |
8695 | else if (s[1] == 's' && s[2] == 'p') | |
8696 | { | |
8697 | s += 3; | |
8698 | regno = SP; | |
8699 | } | |
8700 | else if (s[1] == 'g' && s[2] == 'p') | |
8701 | { | |
8702 | s += 3; | |
8703 | regno = GP; | |
8704 | } | |
8705 | else if (s[1] == 'a' && s[2] == 't') | |
8706 | { | |
8707 | s += 3; | |
8708 | regno = AT; | |
8709 | } | |
8710 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8711 | { | |
8712 | s += 4; | |
8713 | regno = KT0; | |
8714 | } | |
8715 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8716 | { | |
8717 | s += 4; | |
8718 | regno = KT1; | |
8719 | } | |
85b51719 TS |
8720 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8721 | { | |
8722 | s += 5; | |
8723 | regno = ZERO; | |
8724 | } | |
252b5132 RH |
8725 | else if (itbl_have_entries) |
8726 | { | |
8727 | char *p, *n; | |
d7ba4a77 | 8728 | unsigned long r; |
252b5132 | 8729 | |
d7ba4a77 | 8730 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8731 | n = itbl_get_field (&p); /* n is name */ |
8732 | ||
d7ba4a77 ILT |
8733 | /* See if this is a register defined in an |
8734 | itbl entry. */ | |
8735 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8736 | { |
8737 | /* Get_field advances to the start of | |
8738 | the next field, so we need to back | |
d7ba4a77 | 8739 | rack to the end of the last field. */ |
bdaaa2e1 | 8740 | if (p) |
252b5132 | 8741 | s = p - 1; |
bdaaa2e1 | 8742 | else |
d7ba4a77 | 8743 | s = strchr (s, '\0'); |
252b5132 RH |
8744 | regno = r; |
8745 | } | |
8746 | else | |
8747 | goto notreg; | |
beae10d5 | 8748 | } |
252b5132 RH |
8749 | else |
8750 | goto notreg; | |
8751 | } | |
8752 | if (regno == AT | |
8753 | && ! mips_opts.noat | |
8754 | && *args != 'E' | |
af7ee8bf CD |
8755 | && *args != 'G' |
8756 | && *args != 'K') | |
252b5132 RH |
8757 | as_warn (_("Used $at without \".set noat\"")); |
8758 | c = *args; | |
8759 | if (*s == ' ') | |
f9419b05 | 8760 | ++s; |
252b5132 RH |
8761 | if (args[1] != *s) |
8762 | { | |
8763 | if (c == 'r' || c == 'v' || c == 'w') | |
8764 | { | |
8765 | regno = lastregno; | |
8766 | s = s_reset; | |
f9419b05 | 8767 | ++args; |
252b5132 RH |
8768 | } |
8769 | } | |
8770 | /* 'z' only matches $0. */ | |
8771 | if (c == 'z' && regno != 0) | |
8772 | break; | |
8773 | ||
bdaaa2e1 KH |
8774 | /* Now that we have assembled one operand, we use the args string |
8775 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8776 | switch (c) |
8777 | { | |
8778 | case 'r': | |
8779 | case 's': | |
8780 | case 'v': | |
8781 | case 'b': | |
bf12938e | 8782 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8783 | break; |
8784 | case 'd': | |
8785 | case 'G': | |
af7ee8bf | 8786 | case 'K': |
ef2e4d86 | 8787 | case 'g': |
bf12938e | 8788 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8789 | break; |
4372b673 | 8790 | case 'U': |
bf12938e RS |
8791 | INSERT_OPERAND (RD, *ip, regno); |
8792 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8793 | break; |
252b5132 RH |
8794 | case 'w': |
8795 | case 't': | |
8796 | case 'E': | |
bf12938e | 8797 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8798 | break; |
8799 | case 'x': | |
8800 | /* This case exists because on the r3000 trunc | |
8801 | expands into a macro which requires a gp | |
8802 | register. On the r6000 or r4000 it is | |
8803 | assembled into a single instruction which | |
8804 | ignores the register. Thus the insn version | |
8805 | is MIPS_ISA2 and uses 'x', and the macro | |
8806 | version is MIPS_ISA1 and uses 't'. */ | |
8807 | break; | |
8808 | case 'z': | |
8809 | /* This case is for the div instruction, which | |
8810 | acts differently if the destination argument | |
8811 | is $0. This only matches $0, and is checked | |
8812 | outside the switch. */ | |
8813 | break; | |
8814 | case 'D': | |
8815 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8816 | break; | |
8817 | /* What about all other operands like 'i', which | |
8818 | can be specified in the opcode table? */ | |
8819 | } | |
8820 | lastregno = regno; | |
8821 | continue; | |
8822 | } | |
8823 | notreg: | |
8824 | switch (*args++) | |
8825 | { | |
8826 | case 'r': | |
8827 | case 'v': | |
bf12938e | 8828 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8829 | continue; |
8830 | case 'w': | |
bf12938e | 8831 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8832 | continue; |
8833 | } | |
8834 | break; | |
8835 | ||
deec1734 CD |
8836 | case 'O': /* MDMX alignment immediate constant. */ |
8837 | my_getExpression (&imm_expr, s); | |
8838 | check_absolute_expr (ip, &imm_expr); | |
8839 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8840 | as_warn ("Improper align amount (%ld), using low bits", |
8841 | (long) imm_expr.X_add_number); | |
8842 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8843 | imm_expr.X_op = O_absent; |
8844 | s = expr_end; | |
8845 | continue; | |
8846 | ||
8847 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8848 | if (s[0] != '$') | |
8849 | { | |
8850 | /* MDMX Immediate. */ | |
8851 | my_getExpression (&imm_expr, s); | |
8852 | check_absolute_expr (ip, &imm_expr); | |
8853 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8854 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8855 | (long) imm_expr.X_add_number); | |
8856 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8857 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8858 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8859 | else | |
8860 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8861 | imm_expr.X_op = O_absent; |
8862 | s = expr_end; | |
8863 | continue; | |
8864 | } | |
8865 | /* Not MDMX Immediate. Fall through. */ | |
8866 | case 'X': /* MDMX destination register. */ | |
8867 | case 'Y': /* MDMX source register. */ | |
8868 | case 'Z': /* MDMX target register. */ | |
8869 | is_mdmx = 1; | |
252b5132 RH |
8870 | case 'D': /* floating point destination register */ |
8871 | case 'S': /* floating point source register */ | |
8872 | case 'T': /* floating point target register */ | |
8873 | case 'R': /* floating point source register */ | |
8874 | case 'V': | |
8875 | case 'W': | |
8876 | s_reset = s; | |
deec1734 CD |
8877 | /* Accept $fN for FP and MDMX register numbers, and in |
8878 | addition accept $vN for MDMX register numbers. */ | |
8879 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8880 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8881 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8882 | { |
8883 | s += 2; | |
8884 | regno = 0; | |
8885 | do | |
8886 | { | |
8887 | regno *= 10; | |
8888 | regno += *s - '0'; | |
8889 | ++s; | |
8890 | } | |
3882b010 | 8891 | while (ISDIGIT (*s)); |
252b5132 RH |
8892 | |
8893 | if (regno > 31) | |
8894 | as_bad (_("Invalid float register number (%d)"), regno); | |
8895 | ||
8896 | if ((regno & 1) != 0 | |
ca4e0257 | 8897 | && HAVE_32BIT_FPRS |
252b5132 RH |
8898 | && ! (strcmp (str, "mtc1") == 0 |
8899 | || strcmp (str, "mfc1") == 0 | |
8900 | || strcmp (str, "lwc1") == 0 | |
8901 | || strcmp (str, "swc1") == 0 | |
8902 | || strcmp (str, "l.s") == 0 | |
ef2e4d86 CF |
8903 | || strcmp (str, "s.s") == 0 |
8904 | || strcmp (str, "mftc1") == 0 | |
8905 | || strcmp (str, "mfthc1") == 0 | |
8906 | || strcmp (str, "cftc1") == 0 | |
8907 | || strcmp (str, "mttc1") == 0 | |
8908 | || strcmp (str, "mtthc1") == 0 | |
8909 | || strcmp (str, "cttc1") == 0)) | |
252b5132 RH |
8910 | as_warn (_("Float register should be even, was %d"), |
8911 | regno); | |
8912 | ||
8913 | c = *args; | |
8914 | if (*s == ' ') | |
f9419b05 | 8915 | ++s; |
252b5132 RH |
8916 | if (args[1] != *s) |
8917 | { | |
8918 | if (c == 'V' || c == 'W') | |
8919 | { | |
8920 | regno = lastregno; | |
8921 | s = s_reset; | |
f9419b05 | 8922 | ++args; |
252b5132 RH |
8923 | } |
8924 | } | |
8925 | switch (c) | |
8926 | { | |
8927 | case 'D': | |
deec1734 | 8928 | case 'X': |
bf12938e | 8929 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8930 | break; |
8931 | case 'V': | |
8932 | case 'S': | |
deec1734 | 8933 | case 'Y': |
bf12938e | 8934 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8935 | break; |
deec1734 CD |
8936 | case 'Q': |
8937 | /* This is like 'Z', but also needs to fix the MDMX | |
8938 | vector/scalar select bits. Note that the | |
8939 | scalar immediate case is handled above. */ | |
8940 | if (*s == '[') | |
8941 | { | |
8942 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8943 | int max_el = (is_qh ? 3 : 7); | |
8944 | s++; | |
8945 | my_getExpression(&imm_expr, s); | |
8946 | check_absolute_expr (ip, &imm_expr); | |
8947 | s = expr_end; | |
8948 | if (imm_expr.X_add_number > max_el) | |
8949 | as_bad(_("Bad element selector %ld"), | |
8950 | (long) imm_expr.X_add_number); | |
8951 | imm_expr.X_add_number &= max_el; | |
8952 | ip->insn_opcode |= (imm_expr.X_add_number | |
8953 | << (OP_SH_VSEL + | |
8954 | (is_qh ? 2 : 1))); | |
01a3f561 | 8955 | imm_expr.X_op = O_absent; |
deec1734 CD |
8956 | if (*s != ']') |
8957 | as_warn(_("Expecting ']' found '%s'"), s); | |
8958 | else | |
8959 | s++; | |
8960 | } | |
8961 | else | |
8962 | { | |
8963 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8964 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8965 | << OP_SH_VSEL); | |
8966 | else | |
8967 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8968 | OP_SH_VSEL); | |
8969 | } | |
8970 | /* Fall through */ | |
252b5132 RH |
8971 | case 'W': |
8972 | case 'T': | |
deec1734 | 8973 | case 'Z': |
bf12938e | 8974 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8975 | break; |
8976 | case 'R': | |
bf12938e | 8977 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8978 | break; |
8979 | } | |
8980 | lastregno = regno; | |
8981 | continue; | |
8982 | } | |
8983 | ||
252b5132 RH |
8984 | switch (*args++) |
8985 | { | |
8986 | case 'V': | |
bf12938e | 8987 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8988 | continue; |
8989 | case 'W': | |
bf12938e | 8990 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8991 | continue; |
8992 | } | |
8993 | break; | |
8994 | ||
8995 | case 'I': | |
8996 | my_getExpression (&imm_expr, s); | |
8997 | if (imm_expr.X_op != O_big | |
8998 | && imm_expr.X_op != O_constant) | |
8999 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9000 | if (HAVE_32BIT_GPRS) |
9001 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9002 | s = expr_end; |
9003 | continue; | |
9004 | ||
9005 | case 'A': | |
9006 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9007 | normalize_address_expr (&offset_expr); |
f6688943 | 9008 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9009 | s = expr_end; |
9010 | continue; | |
9011 | ||
9012 | case 'F': | |
9013 | case 'L': | |
9014 | case 'f': | |
9015 | case 'l': | |
9016 | { | |
9017 | int f64; | |
ca4e0257 | 9018 | int using_gprs; |
252b5132 RH |
9019 | char *save_in; |
9020 | char *err; | |
9021 | unsigned char temp[8]; | |
9022 | int len; | |
9023 | unsigned int length; | |
9024 | segT seg; | |
9025 | subsegT subseg; | |
9026 | char *p; | |
9027 | ||
9028 | /* These only appear as the last operand in an | |
9029 | instruction, and every instruction that accepts | |
9030 | them in any variant accepts them in all variants. | |
9031 | This means we don't have to worry about backing out | |
9032 | any changes if the instruction does not match. | |
9033 | ||
9034 | The difference between them is the size of the | |
9035 | floating point constant and where it goes. For 'F' | |
9036 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9037 | is 32 bits. Where the constant is placed is based | |
9038 | on how the MIPS assembler does things: | |
9039 | F -- .rdata | |
9040 | L -- .lit8 | |
9041 | f -- immediate value | |
9042 | l -- .lit4 | |
9043 | ||
9044 | The .lit4 and .lit8 sections are only used if | |
9045 | permitted by the -G argument. | |
9046 | ||
ca4e0257 RS |
9047 | The code below needs to know whether the target register |
9048 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9049 | 'F' are used with GPR-based instructions and 'l' and | |
9050 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9051 | |
9052 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9053 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9054 | |
9055 | save_in = input_line_pointer; | |
9056 | input_line_pointer = s; | |
9057 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9058 | length = len; | |
9059 | s = input_line_pointer; | |
9060 | input_line_pointer = save_in; | |
9061 | if (err != NULL && *err != '\0') | |
9062 | { | |
9063 | as_bad (_("Bad floating point constant: %s"), err); | |
9064 | memset (temp, '\0', sizeof temp); | |
9065 | length = f64 ? 8 : 4; | |
9066 | } | |
9067 | ||
156c2f8b | 9068 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9069 | |
9070 | if (*args == 'f' | |
9071 | || (*args == 'l' | |
3e722fb5 | 9072 | && (g_switch_value < 4 |
252b5132 RH |
9073 | || (temp[0] == 0 && temp[1] == 0) |
9074 | || (temp[2] == 0 && temp[3] == 0)))) | |
9075 | { | |
9076 | imm_expr.X_op = O_constant; | |
9077 | if (! target_big_endian) | |
9078 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9079 | else | |
9080 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9081 | } | |
9082 | else if (length > 4 | |
119d663a | 9083 | && ! mips_disable_float_construction |
ca4e0257 RS |
9084 | /* Constants can only be constructed in GPRs and |
9085 | copied to FPRs if the GPRs are at least as wide | |
9086 | as the FPRs. Force the constant into memory if | |
9087 | we are using 64-bit FPRs but the GPRs are only | |
9088 | 32 bits wide. */ | |
9089 | && (using_gprs | |
9090 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9091 | && ((temp[0] == 0 && temp[1] == 0) |
9092 | || (temp[2] == 0 && temp[3] == 0)) | |
9093 | && ((temp[4] == 0 && temp[5] == 0) | |
9094 | || (temp[6] == 0 && temp[7] == 0))) | |
9095 | { | |
ca4e0257 RS |
9096 | /* The value is simple enough to load with a couple of |
9097 | instructions. If using 32-bit registers, set | |
9098 | imm_expr to the high order 32 bits and offset_expr to | |
9099 | the low order 32 bits. Otherwise, set imm_expr to | |
9100 | the entire 64 bit constant. */ | |
9101 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9102 | { |
9103 | imm_expr.X_op = O_constant; | |
9104 | offset_expr.X_op = O_constant; | |
9105 | if (! target_big_endian) | |
9106 | { | |
9107 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9108 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9109 | } | |
9110 | else | |
9111 | { | |
9112 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9113 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9114 | } | |
9115 | if (offset_expr.X_add_number == 0) | |
9116 | offset_expr.X_op = O_absent; | |
9117 | } | |
9118 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9119 | { | |
9120 | imm_expr.X_op = O_constant; | |
9121 | if (! target_big_endian) | |
9122 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9123 | else | |
9124 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9125 | } | |
9126 | else | |
9127 | { | |
9128 | imm_expr.X_op = O_big; | |
9129 | imm_expr.X_add_number = 4; | |
9130 | if (! target_big_endian) | |
9131 | { | |
9132 | generic_bignum[0] = bfd_getl16 (temp); | |
9133 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9134 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9135 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9136 | } | |
9137 | else | |
9138 | { | |
9139 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9140 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9141 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9142 | generic_bignum[3] = bfd_getb16 (temp); | |
9143 | } | |
9144 | } | |
9145 | } | |
9146 | else | |
9147 | { | |
9148 | const char *newname; | |
9149 | segT new_seg; | |
9150 | ||
9151 | /* Switch to the right section. */ | |
9152 | seg = now_seg; | |
9153 | subseg = now_subseg; | |
9154 | switch (*args) | |
9155 | { | |
9156 | default: /* unused default case avoids warnings. */ | |
9157 | case 'L': | |
9158 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9159 | if (g_switch_value >= 8) |
252b5132 RH |
9160 | newname = ".lit8"; |
9161 | break; | |
9162 | case 'F': | |
3e722fb5 | 9163 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9164 | break; |
9165 | case 'l': | |
4d0d148d | 9166 | assert (g_switch_value >= 4); |
252b5132 RH |
9167 | newname = ".lit4"; |
9168 | break; | |
9169 | } | |
9170 | new_seg = subseg_new (newname, (subsegT) 0); | |
9171 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9172 | bfd_set_section_flags (stdoutput, new_seg, | |
9173 | (SEC_ALLOC | |
9174 | | SEC_LOAD | |
9175 | | SEC_READONLY | |
9176 | | SEC_DATA)); | |
9177 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9178 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9179 | && strcmp (TARGET_OS, "elf") != 0) | |
9180 | record_alignment (new_seg, 4); | |
9181 | else | |
9182 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9183 | if (seg == now_seg) | |
9184 | as_bad (_("Can't use floating point insn in this section")); | |
9185 | ||
9186 | /* Set the argument to the current address in the | |
9187 | section. */ | |
9188 | offset_expr.X_op = O_symbol; | |
9189 | offset_expr.X_add_symbol = | |
9190 | symbol_new ("L0\001", now_seg, | |
9191 | (valueT) frag_now_fix (), frag_now); | |
9192 | offset_expr.X_add_number = 0; | |
9193 | ||
9194 | /* Put the floating point number into the section. */ | |
9195 | p = frag_more ((int) length); | |
9196 | memcpy (p, temp, length); | |
9197 | ||
9198 | /* Switch back to the original section. */ | |
9199 | subseg_set (seg, subseg); | |
9200 | } | |
9201 | } | |
9202 | continue; | |
9203 | ||
9204 | case 'i': /* 16 bit unsigned immediate */ | |
9205 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9206 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9207 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9208 | { |
9209 | int more; | |
5e0116d5 RS |
9210 | offsetT minval, maxval; |
9211 | ||
9212 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9213 | && strcmp (insn->name, insn[1].name) == 0); | |
9214 | ||
9215 | /* If the expression was written as an unsigned number, | |
9216 | only treat it as signed if there are no more | |
9217 | alternatives. */ | |
9218 | if (more | |
9219 | && *args == 'j' | |
9220 | && sizeof (imm_expr.X_add_number) <= 4 | |
9221 | && imm_expr.X_op == O_constant | |
9222 | && imm_expr.X_add_number < 0 | |
9223 | && imm_expr.X_unsigned | |
9224 | && HAVE_64BIT_GPRS) | |
9225 | break; | |
9226 | ||
9227 | /* For compatibility with older assemblers, we accept | |
9228 | 0x8000-0xffff as signed 16-bit numbers when only | |
9229 | signed numbers are allowed. */ | |
9230 | if (*args == 'i') | |
9231 | minval = 0, maxval = 0xffff; | |
9232 | else if (more) | |
9233 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9234 | else |
5e0116d5 RS |
9235 | minval = -0x8000, maxval = 0xffff; |
9236 | ||
9237 | if (imm_expr.X_op != O_constant | |
9238 | || imm_expr.X_add_number < minval | |
9239 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9240 | { |
9241 | if (more) | |
9242 | break; | |
2ae7e77b AH |
9243 | if (imm_expr.X_op == O_constant |
9244 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9245 | as_bad (_("expression out of range")); |
252b5132 RH |
9246 | } |
9247 | } | |
9248 | s = expr_end; | |
9249 | continue; | |
9250 | ||
9251 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9252 | /* Check whether there is only a single bracketed expression |
9253 | left. If so, it must be the base register and the | |
9254 | constant must be zero. */ | |
9255 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9256 | { | |
9257 | offset_expr.X_op = O_constant; | |
9258 | offset_expr.X_add_number = 0; | |
9259 | continue; | |
9260 | } | |
252b5132 RH |
9261 | |
9262 | /* If this value won't fit into a 16 bit offset, then go | |
9263 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9264 | code pattern. */ |
5e0116d5 | 9265 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9266 | && (offset_expr.X_op != O_constant |
9267 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9268 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9269 | break; |
9270 | ||
252b5132 RH |
9271 | s = expr_end; |
9272 | continue; | |
9273 | ||
9274 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9275 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9276 | my_getExpression (&offset_expr, s); |
9277 | s = expr_end; | |
9278 | continue; | |
9279 | ||
9280 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9281 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9282 | && imm_expr.X_op == O_constant | |
9283 | && (imm_expr.X_add_number < 0 | |
9284 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9285 | as_bad (_("lui expression not in range 0..65535")); |
9286 | s = expr_end; | |
9287 | continue; | |
9288 | ||
9289 | case 'a': /* 26 bit address */ | |
9290 | my_getExpression (&offset_expr, s); | |
9291 | s = expr_end; | |
f6688943 | 9292 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9293 | continue; |
9294 | ||
9295 | case 'N': /* 3 bit branch condition code */ | |
9296 | case 'M': /* 3 bit compare condition code */ | |
9297 | if (strncmp (s, "$fcc", 4) != 0) | |
9298 | break; | |
9299 | s += 4; | |
9300 | regno = 0; | |
9301 | do | |
9302 | { | |
9303 | regno *= 10; | |
9304 | regno += *s - '0'; | |
9305 | ++s; | |
9306 | } | |
3882b010 | 9307 | while (ISDIGIT (*s)); |
252b5132 | 9308 | if (regno > 7) |
30c378fd CD |
9309 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9310 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9311 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9312 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9313 | && (regno & 1) != 0) | |
9314 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9315 | str, regno); | |
9316 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9317 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9318 | && (regno & 3) != 0) | |
9319 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9320 | str, regno); | |
252b5132 | 9321 | if (*args == 'N') |
bf12938e | 9322 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9323 | else |
bf12938e | 9324 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9325 | continue; |
252b5132 | 9326 | |
156c2f8b NC |
9327 | case 'H': |
9328 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9329 | s += 2; | |
3882b010 | 9330 | if (ISDIGIT (*s)) |
156c2f8b NC |
9331 | { |
9332 | c = 0; | |
9333 | do | |
9334 | { | |
9335 | c *= 10; | |
9336 | c += *s - '0'; | |
9337 | ++s; | |
9338 | } | |
3882b010 | 9339 | while (ISDIGIT (*s)); |
156c2f8b NC |
9340 | } |
9341 | else | |
9342 | c = 8; /* Invalid sel value. */ | |
9343 | ||
9344 | if (c > 7) | |
9345 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9346 | ip->insn_opcode |= c; | |
9347 | continue; | |
9348 | ||
60b63b72 RS |
9349 | case 'e': |
9350 | /* Must be at least one digit. */ | |
9351 | my_getExpression (&imm_expr, s); | |
9352 | check_absolute_expr (ip, &imm_expr); | |
9353 | ||
9354 | if ((unsigned long) imm_expr.X_add_number | |
9355 | > (unsigned long) OP_MASK_VECBYTE) | |
9356 | { | |
9357 | as_bad (_("bad byte vector index (%ld)"), | |
9358 | (long) imm_expr.X_add_number); | |
9359 | imm_expr.X_add_number = 0; | |
9360 | } | |
9361 | ||
bf12938e | 9362 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9363 | imm_expr.X_op = O_absent; |
9364 | s = expr_end; | |
9365 | continue; | |
9366 | ||
9367 | case '%': | |
9368 | my_getExpression (&imm_expr, s); | |
9369 | check_absolute_expr (ip, &imm_expr); | |
9370 | ||
9371 | if ((unsigned long) imm_expr.X_add_number | |
9372 | > (unsigned long) OP_MASK_VECALIGN) | |
9373 | { | |
9374 | as_bad (_("bad byte vector index (%ld)"), | |
9375 | (long) imm_expr.X_add_number); | |
9376 | imm_expr.X_add_number = 0; | |
9377 | } | |
9378 | ||
bf12938e | 9379 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9380 | imm_expr.X_op = O_absent; |
9381 | s = expr_end; | |
9382 | continue; | |
9383 | ||
252b5132 RH |
9384 | default: |
9385 | as_bad (_("bad char = '%c'\n"), *args); | |
9386 | internalError (); | |
9387 | } | |
9388 | break; | |
9389 | } | |
9390 | /* Args don't match. */ | |
9391 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9392 | !strcmp (insn->name, insn[1].name)) | |
9393 | { | |
9394 | ++insn; | |
9395 | s = argsStart; | |
268f6bed | 9396 | insn_error = _("illegal operands"); |
252b5132 RH |
9397 | continue; |
9398 | } | |
268f6bed L |
9399 | if (save_c) |
9400 | *(--s) = save_c; | |
252b5132 RH |
9401 | insn_error = _("illegal operands"); |
9402 | return; | |
9403 | } | |
9404 | } | |
9405 | ||
0499d65b TS |
9406 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9407 | ||
252b5132 RH |
9408 | /* This routine assembles an instruction into its binary format when |
9409 | assembling for the mips16. As a side effect, it sets one of the | |
9410 | global variables imm_reloc or offset_reloc to the type of | |
9411 | relocation to do if one of the operands is an address expression. | |
9412 | It also sets mips16_small and mips16_ext if the user explicitly | |
9413 | requested a small or extended instruction. */ | |
9414 | ||
9415 | static void | |
17a2f251 | 9416 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9417 | { |
9418 | char *s; | |
9419 | const char *args; | |
9420 | struct mips_opcode *insn; | |
9421 | char *argsstart; | |
9422 | unsigned int regno; | |
9423 | unsigned int lastregno = 0; | |
9424 | char *s_reset; | |
d6f16593 | 9425 | size_t i; |
252b5132 RH |
9426 | |
9427 | insn_error = NULL; | |
9428 | ||
b34976b6 AM |
9429 | mips16_small = FALSE; |
9430 | mips16_ext = FALSE; | |
252b5132 | 9431 | |
3882b010 | 9432 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9433 | ; |
9434 | switch (*s) | |
9435 | { | |
9436 | case '\0': | |
9437 | break; | |
9438 | ||
9439 | case ' ': | |
9440 | *s++ = '\0'; | |
9441 | break; | |
9442 | ||
9443 | case '.': | |
9444 | if (s[1] == 't' && s[2] == ' ') | |
9445 | { | |
9446 | *s = '\0'; | |
b34976b6 | 9447 | mips16_small = TRUE; |
252b5132 RH |
9448 | s += 3; |
9449 | break; | |
9450 | } | |
9451 | else if (s[1] == 'e' && s[2] == ' ') | |
9452 | { | |
9453 | *s = '\0'; | |
b34976b6 | 9454 | mips16_ext = TRUE; |
252b5132 RH |
9455 | s += 3; |
9456 | break; | |
9457 | } | |
9458 | /* Fall through. */ | |
9459 | default: | |
9460 | insn_error = _("unknown opcode"); | |
9461 | return; | |
9462 | } | |
9463 | ||
9464 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9465 | mips16_small = TRUE; |
252b5132 RH |
9466 | |
9467 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9468 | { | |
9469 | insn_error = _("unrecognized opcode"); | |
9470 | return; | |
9471 | } | |
9472 | ||
9473 | argsstart = s; | |
9474 | for (;;) | |
9475 | { | |
9476 | assert (strcmp (insn->name, str) == 0); | |
9477 | ||
1e915849 | 9478 | create_insn (ip, insn); |
252b5132 | 9479 | imm_expr.X_op = O_absent; |
f6688943 TS |
9480 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9481 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9482 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9483 | imm2_expr.X_op = O_absent; |
252b5132 | 9484 | offset_expr.X_op = O_absent; |
f6688943 TS |
9485 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9486 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9487 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9488 | for (args = insn->args; 1; ++args) |
9489 | { | |
9490 | int c; | |
9491 | ||
9492 | if (*s == ' ') | |
9493 | ++s; | |
9494 | ||
9495 | /* In this switch statement we call break if we did not find | |
9496 | a match, continue if we did find a match, or return if we | |
9497 | are done. */ | |
9498 | ||
9499 | c = *args; | |
9500 | switch (c) | |
9501 | { | |
9502 | case '\0': | |
9503 | if (*s == '\0') | |
9504 | { | |
9505 | /* Stuff the immediate value in now, if we can. */ | |
9506 | if (imm_expr.X_op == O_constant | |
f6688943 | 9507 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9508 | && insn->pinfo != INSN_MACRO) |
9509 | { | |
d6f16593 MR |
9510 | valueT tmp; |
9511 | ||
9512 | switch (*offset_reloc) | |
9513 | { | |
9514 | case BFD_RELOC_MIPS16_HI16_S: | |
9515 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9516 | break; | |
9517 | ||
9518 | case BFD_RELOC_MIPS16_HI16: | |
9519 | tmp = imm_expr.X_add_number >> 16; | |
9520 | break; | |
9521 | ||
9522 | case BFD_RELOC_MIPS16_LO16: | |
9523 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9524 | - 0x8000; | |
9525 | break; | |
9526 | ||
9527 | case BFD_RELOC_UNUSED: | |
9528 | tmp = imm_expr.X_add_number; | |
9529 | break; | |
9530 | ||
9531 | default: | |
9532 | internalError (); | |
9533 | } | |
9534 | *offset_reloc = BFD_RELOC_UNUSED; | |
9535 | ||
c4e7957c | 9536 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9537 | tmp, TRUE, mips16_small, |
252b5132 RH |
9538 | mips16_ext, &ip->insn_opcode, |
9539 | &ip->use_extend, &ip->extend); | |
9540 | imm_expr.X_op = O_absent; | |
f6688943 | 9541 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9542 | } |
9543 | ||
9544 | return; | |
9545 | } | |
9546 | break; | |
9547 | ||
9548 | case ',': | |
9549 | if (*s++ == c) | |
9550 | continue; | |
9551 | s--; | |
9552 | switch (*++args) | |
9553 | { | |
9554 | case 'v': | |
bf12938e | 9555 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9556 | continue; |
9557 | case 'w': | |
bf12938e | 9558 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9559 | continue; |
9560 | } | |
9561 | break; | |
9562 | ||
9563 | case '(': | |
9564 | case ')': | |
9565 | if (*s++ == c) | |
9566 | continue; | |
9567 | break; | |
9568 | ||
9569 | case 'v': | |
9570 | case 'w': | |
9571 | if (s[0] != '$') | |
9572 | { | |
9573 | if (c == 'v') | |
bf12938e | 9574 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9575 | else |
bf12938e | 9576 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9577 | ++args; |
9578 | continue; | |
9579 | } | |
9580 | /* Fall through. */ | |
9581 | case 'x': | |
9582 | case 'y': | |
9583 | case 'z': | |
9584 | case 'Z': | |
9585 | case '0': | |
9586 | case 'S': | |
9587 | case 'R': | |
9588 | case 'X': | |
9589 | case 'Y': | |
9590 | if (s[0] != '$') | |
9591 | break; | |
9592 | s_reset = s; | |
3882b010 | 9593 | if (ISDIGIT (s[1])) |
252b5132 RH |
9594 | { |
9595 | ++s; | |
9596 | regno = 0; | |
9597 | do | |
9598 | { | |
9599 | regno *= 10; | |
9600 | regno += *s - '0'; | |
9601 | ++s; | |
9602 | } | |
3882b010 | 9603 | while (ISDIGIT (*s)); |
252b5132 RH |
9604 | if (regno > 31) |
9605 | { | |
9606 | as_bad (_("invalid register number (%d)"), regno); | |
9607 | regno = 2; | |
9608 | } | |
9609 | } | |
9610 | else | |
9611 | { | |
76db943d TS |
9612 | if (s[1] == 'r' && s[2] == 'a') |
9613 | { | |
9614 | s += 3; | |
9615 | regno = RA; | |
9616 | } | |
9617 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9618 | { |
9619 | s += 3; | |
9620 | regno = FP; | |
9621 | } | |
9622 | else if (s[1] == 's' && s[2] == 'p') | |
9623 | { | |
9624 | s += 3; | |
9625 | regno = SP; | |
9626 | } | |
9627 | else if (s[1] == 'g' && s[2] == 'p') | |
9628 | { | |
9629 | s += 3; | |
9630 | regno = GP; | |
9631 | } | |
9632 | else if (s[1] == 'a' && s[2] == 't') | |
9633 | { | |
9634 | s += 3; | |
9635 | regno = AT; | |
9636 | } | |
9637 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9638 | { | |
9639 | s += 4; | |
9640 | regno = KT0; | |
9641 | } | |
9642 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9643 | { | |
9644 | s += 4; | |
9645 | regno = KT1; | |
9646 | } | |
85b51719 TS |
9647 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9648 | { | |
9649 | s += 5; | |
9650 | regno = ZERO; | |
9651 | } | |
252b5132 RH |
9652 | else |
9653 | break; | |
9654 | } | |
9655 | ||
9656 | if (*s == ' ') | |
9657 | ++s; | |
9658 | if (args[1] != *s) | |
9659 | { | |
9660 | if (c == 'v' || c == 'w') | |
9661 | { | |
9662 | regno = mips16_to_32_reg_map[lastregno]; | |
9663 | s = s_reset; | |
f9419b05 | 9664 | ++args; |
252b5132 RH |
9665 | } |
9666 | } | |
9667 | ||
9668 | switch (c) | |
9669 | { | |
9670 | case 'x': | |
9671 | case 'y': | |
9672 | case 'z': | |
9673 | case 'v': | |
9674 | case 'w': | |
9675 | case 'Z': | |
9676 | regno = mips32_to_16_reg_map[regno]; | |
9677 | break; | |
9678 | ||
9679 | case '0': | |
9680 | if (regno != 0) | |
9681 | regno = ILLEGAL_REG; | |
9682 | break; | |
9683 | ||
9684 | case 'S': | |
9685 | if (regno != SP) | |
9686 | regno = ILLEGAL_REG; | |
9687 | break; | |
9688 | ||
9689 | case 'R': | |
9690 | if (regno != RA) | |
9691 | regno = ILLEGAL_REG; | |
9692 | break; | |
9693 | ||
9694 | case 'X': | |
9695 | case 'Y': | |
9696 | if (regno == AT && ! mips_opts.noat) | |
9697 | as_warn (_("used $at without \".set noat\"")); | |
9698 | break; | |
9699 | ||
9700 | default: | |
9701 | internalError (); | |
9702 | } | |
9703 | ||
9704 | if (regno == ILLEGAL_REG) | |
9705 | break; | |
9706 | ||
9707 | switch (c) | |
9708 | { | |
9709 | case 'x': | |
9710 | case 'v': | |
bf12938e | 9711 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9712 | break; |
9713 | case 'y': | |
9714 | case 'w': | |
bf12938e | 9715 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9716 | break; |
9717 | case 'z': | |
bf12938e | 9718 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9719 | break; |
9720 | case 'Z': | |
bf12938e | 9721 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9722 | case '0': |
9723 | case 'S': | |
9724 | case 'R': | |
9725 | break; | |
9726 | case 'X': | |
bf12938e | 9727 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9728 | break; |
9729 | case 'Y': | |
9730 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9731 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9732 | break; |
9733 | default: | |
9734 | internalError (); | |
9735 | } | |
9736 | ||
9737 | lastregno = regno; | |
9738 | continue; | |
9739 | ||
9740 | case 'P': | |
9741 | if (strncmp (s, "$pc", 3) == 0) | |
9742 | { | |
9743 | s += 3; | |
9744 | continue; | |
9745 | } | |
9746 | break; | |
9747 | ||
252b5132 RH |
9748 | case '5': |
9749 | case 'H': | |
9750 | case 'W': | |
9751 | case 'D': | |
9752 | case 'j': | |
252b5132 RH |
9753 | case 'V': |
9754 | case 'C': | |
9755 | case 'U': | |
9756 | case 'k': | |
9757 | case 'K': | |
d6f16593 MR |
9758 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9759 | if (i > 0) | |
252b5132 | 9760 | { |
d6f16593 | 9761 | if (imm_expr.X_op != O_constant) |
252b5132 | 9762 | { |
b34976b6 | 9763 | mips16_ext = TRUE; |
b34976b6 | 9764 | ip->use_extend = TRUE; |
252b5132 | 9765 | ip->extend = 0; |
252b5132 | 9766 | } |
d6f16593 MR |
9767 | else |
9768 | { | |
9769 | /* We need to relax this instruction. */ | |
9770 | *offset_reloc = *imm_reloc; | |
9771 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9772 | } | |
9773 | s = expr_end; | |
9774 | continue; | |
252b5132 | 9775 | } |
d6f16593 MR |
9776 | *imm_reloc = BFD_RELOC_UNUSED; |
9777 | /* Fall through. */ | |
9778 | case '<': | |
9779 | case '>': | |
9780 | case '[': | |
9781 | case ']': | |
9782 | case '4': | |
9783 | case '8': | |
9784 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9785 | if (imm_expr.X_op == O_register) |
9786 | { | |
9787 | /* What we thought was an expression turned out to | |
9788 | be a register. */ | |
9789 | ||
9790 | if (s[0] == '(' && args[1] == '(') | |
9791 | { | |
9792 | /* It looks like the expression was omitted | |
9793 | before a register indirection, which means | |
9794 | that the expression is implicitly zero. We | |
9795 | still set up imm_expr, so that we handle | |
9796 | explicit extensions correctly. */ | |
9797 | imm_expr.X_op = O_constant; | |
9798 | imm_expr.X_add_number = 0; | |
f6688943 | 9799 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9800 | continue; |
9801 | } | |
9802 | ||
9803 | break; | |
9804 | } | |
9805 | ||
9806 | /* We need to relax this instruction. */ | |
f6688943 | 9807 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9808 | s = expr_end; |
9809 | continue; | |
9810 | ||
9811 | case 'p': | |
9812 | case 'q': | |
9813 | case 'A': | |
9814 | case 'B': | |
9815 | case 'E': | |
9816 | /* We use offset_reloc rather than imm_reloc for the PC | |
9817 | relative operands. This lets macros with both | |
9818 | immediate and address operands work correctly. */ | |
9819 | my_getExpression (&offset_expr, s); | |
9820 | ||
9821 | if (offset_expr.X_op == O_register) | |
9822 | break; | |
9823 | ||
9824 | /* We need to relax this instruction. */ | |
f6688943 | 9825 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9826 | s = expr_end; |
9827 | continue; | |
9828 | ||
9829 | case '6': /* break code */ | |
9830 | my_getExpression (&imm_expr, s); | |
9831 | check_absolute_expr (ip, &imm_expr); | |
9832 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9833 | as_warn (_("Invalid value for `%s' (%lu)"), |
9834 | ip->insn_mo->name, | |
9835 | (unsigned long) imm_expr.X_add_number); | |
9836 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9837 | imm_expr.X_op = O_absent; |
9838 | s = expr_end; | |
9839 | continue; | |
9840 | ||
9841 | case 'a': /* 26 bit address */ | |
9842 | my_getExpression (&offset_expr, s); | |
9843 | s = expr_end; | |
f6688943 | 9844 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9845 | ip->insn_opcode <<= 16; |
9846 | continue; | |
9847 | ||
9848 | case 'l': /* register list for entry macro */ | |
9849 | case 'L': /* register list for exit macro */ | |
9850 | { | |
9851 | int mask; | |
9852 | ||
9853 | if (c == 'l') | |
9854 | mask = 0; | |
9855 | else | |
9856 | mask = 7 << 3; | |
9857 | while (*s != '\0') | |
9858 | { | |
9859 | int freg, reg1, reg2; | |
9860 | ||
9861 | while (*s == ' ' || *s == ',') | |
9862 | ++s; | |
9863 | if (*s != '$') | |
9864 | { | |
9865 | as_bad (_("can't parse register list")); | |
9866 | break; | |
9867 | } | |
9868 | ++s; | |
9869 | if (*s != 'f') | |
9870 | freg = 0; | |
9871 | else | |
9872 | { | |
9873 | freg = 1; | |
9874 | ++s; | |
9875 | } | |
9876 | reg1 = 0; | |
3882b010 | 9877 | while (ISDIGIT (*s)) |
252b5132 RH |
9878 | { |
9879 | reg1 *= 10; | |
9880 | reg1 += *s - '0'; | |
9881 | ++s; | |
9882 | } | |
9883 | if (*s == ' ') | |
9884 | ++s; | |
9885 | if (*s != '-') | |
9886 | reg2 = reg1; | |
9887 | else | |
9888 | { | |
9889 | ++s; | |
9890 | if (*s != '$') | |
9891 | break; | |
9892 | ++s; | |
9893 | if (freg) | |
9894 | { | |
9895 | if (*s == 'f') | |
9896 | ++s; | |
9897 | else | |
9898 | { | |
9899 | as_bad (_("invalid register list")); | |
9900 | break; | |
9901 | } | |
9902 | } | |
9903 | reg2 = 0; | |
3882b010 | 9904 | while (ISDIGIT (*s)) |
252b5132 RH |
9905 | { |
9906 | reg2 *= 10; | |
9907 | reg2 += *s - '0'; | |
9908 | ++s; | |
9909 | } | |
9910 | } | |
9911 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9912 | { | |
9913 | mask &= ~ (7 << 3); | |
9914 | mask |= 5 << 3; | |
9915 | } | |
9916 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9917 | { | |
9918 | mask &= ~ (7 << 3); | |
9919 | mask |= 6 << 3; | |
9920 | } | |
9921 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9922 | mask |= (reg2 - 3) << 3; | |
9923 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9924 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9925 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9926 | mask |= 1; |
9927 | else | |
9928 | { | |
9929 | as_bad (_("invalid register list")); | |
9930 | break; | |
9931 | } | |
9932 | } | |
9933 | /* The mask is filled in in the opcode table for the | |
9934 | benefit of the disassembler. We remove it before | |
9935 | applying the actual mask. */ | |
9936 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9937 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9938 | } | |
9939 | continue; | |
9940 | ||
0499d65b TS |
9941 | case 'm': /* Register list for save insn. */ |
9942 | case 'M': /* Register list for restore insn. */ | |
9943 | { | |
9944 | int opcode = 0; | |
9945 | int framesz = 0, seen_framesz = 0; | |
9946 | int args = 0, statics = 0, sregs = 0; | |
9947 | ||
9948 | while (*s != '\0') | |
9949 | { | |
9950 | unsigned int reg1, reg2; | |
9951 | ||
9952 | SKIP_SPACE_TABS (s); | |
9953 | while (*s == ',') | |
9954 | ++s; | |
9955 | SKIP_SPACE_TABS (s); | |
9956 | ||
9957 | my_getExpression (&imm_expr, s); | |
9958 | if (imm_expr.X_op == O_constant) | |
9959 | { | |
9960 | /* Handle the frame size. */ | |
9961 | if (seen_framesz) | |
9962 | { | |
9963 | as_bad (_("more than one frame size in list")); | |
9964 | break; | |
9965 | } | |
9966 | seen_framesz = 1; | |
9967 | framesz = imm_expr.X_add_number; | |
9968 | imm_expr.X_op = O_absent; | |
9969 | s = expr_end; | |
9970 | continue; | |
9971 | } | |
9972 | ||
9973 | if (*s != '$') | |
9974 | { | |
9975 | as_bad (_("can't parse register list")); | |
9976 | break; | |
9977 | } | |
9978 | ++s; | |
9979 | ||
9980 | reg1 = 0; | |
9981 | while (ISDIGIT (*s)) | |
9982 | { | |
9983 | reg1 *= 10; | |
9984 | reg1 += *s - '0'; | |
9985 | ++s; | |
9986 | } | |
9987 | SKIP_SPACE_TABS (s); | |
9988 | if (*s != '-') | |
9989 | reg2 = reg1; | |
9990 | else | |
9991 | { | |
9992 | ++s; | |
9993 | if (*s != '$') | |
9994 | { | |
9995 | as_bad (_("can't parse register list")); | |
9996 | break; | |
9997 | } | |
9998 | ++s; | |
9999 | reg2 = 0; | |
10000 | while (ISDIGIT (*s)) | |
10001 | { | |
10002 | reg2 *= 10; | |
10003 | reg2 += *s - '0'; | |
10004 | ++s; | |
10005 | } | |
10006 | } | |
10007 | ||
10008 | while (reg1 <= reg2) | |
10009 | { | |
10010 | if (reg1 >= 4 && reg1 <= 7) | |
10011 | { | |
10012 | if (c == 'm' && !seen_framesz) | |
10013 | /* args $a0-$a3 */ | |
10014 | args |= 1 << (reg1 - 4); | |
10015 | else | |
10016 | /* statics $a0-$a3 */ | |
10017 | statics |= 1 << (reg1 - 4); | |
10018 | } | |
10019 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10020 | { | |
10021 | /* $s0-$s8 */ | |
10022 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10023 | } | |
10024 | else if (reg1 == 31) | |
10025 | { | |
10026 | /* Add $ra to insn. */ | |
10027 | opcode |= 0x40; | |
10028 | } | |
10029 | else | |
10030 | { | |
10031 | as_bad (_("unexpected register in list")); | |
10032 | break; | |
10033 | } | |
10034 | if (++reg1 == 24) | |
10035 | reg1 = 30; | |
10036 | } | |
10037 | } | |
10038 | ||
10039 | /* Encode args/statics combination. */ | |
10040 | if (args & statics) | |
10041 | as_bad (_("arg/static registers overlap")); | |
10042 | else if (args == 0xf) | |
10043 | /* All $a0-$a3 are args. */ | |
10044 | opcode |= MIPS16_ALL_ARGS << 16; | |
10045 | else if (statics == 0xf) | |
10046 | /* All $a0-$a3 are statics. */ | |
10047 | opcode |= MIPS16_ALL_STATICS << 16; | |
10048 | else | |
10049 | { | |
10050 | int narg = 0, nstat = 0; | |
10051 | ||
10052 | /* Count arg registers. */ | |
10053 | while (args & 0x1) | |
10054 | { | |
10055 | args >>= 1; | |
10056 | narg++; | |
10057 | } | |
10058 | if (args != 0) | |
10059 | as_bad (_("invalid arg register list")); | |
10060 | ||
10061 | /* Count static registers. */ | |
10062 | while (statics & 0x8) | |
10063 | { | |
10064 | statics = (statics << 1) & 0xf; | |
10065 | nstat++; | |
10066 | } | |
10067 | if (statics != 0) | |
10068 | as_bad (_("invalid static register list")); | |
10069 | ||
10070 | /* Encode args/statics. */ | |
10071 | opcode |= ((narg << 2) | nstat) << 16; | |
10072 | } | |
10073 | ||
10074 | /* Encode $s0/$s1. */ | |
10075 | if (sregs & (1 << 0)) /* $s0 */ | |
10076 | opcode |= 0x20; | |
10077 | if (sregs & (1 << 1)) /* $s1 */ | |
10078 | opcode |= 0x10; | |
10079 | sregs >>= 2; | |
10080 | ||
10081 | if (sregs != 0) | |
10082 | { | |
10083 | /* Count regs $s2-$s8. */ | |
10084 | int nsreg = 0; | |
10085 | while (sregs & 1) | |
10086 | { | |
10087 | sregs >>= 1; | |
10088 | nsreg++; | |
10089 | } | |
10090 | if (sregs != 0) | |
10091 | as_bad (_("invalid static register list")); | |
10092 | /* Encode $s2-$s8. */ | |
10093 | opcode |= nsreg << 24; | |
10094 | } | |
10095 | ||
10096 | /* Encode frame size. */ | |
10097 | if (!seen_framesz) | |
10098 | as_bad (_("missing frame size")); | |
10099 | else if ((framesz & 7) != 0 || framesz < 0 | |
10100 | || framesz > 0xff * 8) | |
10101 | as_bad (_("invalid frame size")); | |
10102 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10103 | { | |
10104 | framesz /= 8; | |
10105 | opcode |= (((framesz & 0xf0) << 16) | |
10106 | | (framesz & 0x0f)); | |
10107 | } | |
10108 | ||
10109 | /* Finally build the instruction. */ | |
10110 | if ((opcode >> 16) != 0 || framesz == 0) | |
10111 | { | |
10112 | ip->use_extend = TRUE; | |
10113 | ip->extend = opcode >> 16; | |
10114 | } | |
10115 | ip->insn_opcode |= opcode & 0x7f; | |
10116 | } | |
10117 | continue; | |
10118 | ||
252b5132 RH |
10119 | case 'e': /* extend code */ |
10120 | my_getExpression (&imm_expr, s); | |
10121 | check_absolute_expr (ip, &imm_expr); | |
10122 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10123 | { | |
10124 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10125 | ip->insn_mo->name, | |
10126 | (unsigned long) imm_expr.X_add_number); | |
10127 | imm_expr.X_add_number &= 0x7ff; | |
10128 | } | |
10129 | ip->insn_opcode |= imm_expr.X_add_number; | |
10130 | imm_expr.X_op = O_absent; | |
10131 | s = expr_end; | |
10132 | continue; | |
10133 | ||
10134 | default: | |
10135 | internalError (); | |
10136 | } | |
10137 | break; | |
10138 | } | |
10139 | ||
10140 | /* Args don't match. */ | |
10141 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10142 | strcmp (insn->name, insn[1].name) == 0) | |
10143 | { | |
10144 | ++insn; | |
10145 | s = argsstart; | |
10146 | continue; | |
10147 | } | |
10148 | ||
10149 | insn_error = _("illegal operands"); | |
10150 | ||
10151 | return; | |
10152 | } | |
10153 | } | |
10154 | ||
10155 | /* This structure holds information we know about a mips16 immediate | |
10156 | argument type. */ | |
10157 | ||
e972090a NC |
10158 | struct mips16_immed_operand |
10159 | { | |
252b5132 RH |
10160 | /* The type code used in the argument string in the opcode table. */ |
10161 | int type; | |
10162 | /* The number of bits in the short form of the opcode. */ | |
10163 | int nbits; | |
10164 | /* The number of bits in the extended form of the opcode. */ | |
10165 | int extbits; | |
10166 | /* The amount by which the short form is shifted when it is used; | |
10167 | for example, the sw instruction has a shift count of 2. */ | |
10168 | int shift; | |
10169 | /* The amount by which the short form is shifted when it is stored | |
10170 | into the instruction code. */ | |
10171 | int op_shift; | |
10172 | /* Non-zero if the short form is unsigned. */ | |
10173 | int unsp; | |
10174 | /* Non-zero if the extended form is unsigned. */ | |
10175 | int extu; | |
10176 | /* Non-zero if the value is PC relative. */ | |
10177 | int pcrel; | |
10178 | }; | |
10179 | ||
10180 | /* The mips16 immediate operand types. */ | |
10181 | ||
10182 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10183 | { | |
10184 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10185 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10186 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10187 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10188 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10189 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10190 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10191 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10192 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10193 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10194 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10195 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10196 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10197 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10198 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10199 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10200 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10201 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10202 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10203 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10204 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10205 | }; | |
10206 | ||
10207 | #define MIPS16_NUM_IMMED \ | |
10208 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10209 | ||
10210 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10211 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10212 | whether an extended value is needed; if one is needed, it sets | |
10213 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10214 | If SMALL is true, an unextended opcode was explicitly requested. | |
10215 | If EXT is true, an extended opcode was explicitly requested. If | |
10216 | WARN is true, warn if EXT does not match reality. */ | |
10217 | ||
10218 | static void | |
17a2f251 TS |
10219 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10220 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10221 | unsigned long *insn, bfd_boolean *use_extend, | |
10222 | unsigned short *extend) | |
252b5132 RH |
10223 | { |
10224 | register const struct mips16_immed_operand *op; | |
10225 | int mintiny, maxtiny; | |
b34976b6 | 10226 | bfd_boolean needext; |
252b5132 RH |
10227 | |
10228 | op = mips16_immed_operands; | |
10229 | while (op->type != type) | |
10230 | { | |
10231 | ++op; | |
10232 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10233 | } | |
10234 | ||
10235 | if (op->unsp) | |
10236 | { | |
10237 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10238 | { | |
10239 | mintiny = 1; | |
10240 | maxtiny = 1 << op->nbits; | |
10241 | } | |
10242 | else | |
10243 | { | |
10244 | mintiny = 0; | |
10245 | maxtiny = (1 << op->nbits) - 1; | |
10246 | } | |
10247 | } | |
10248 | else | |
10249 | { | |
10250 | mintiny = - (1 << (op->nbits - 1)); | |
10251 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10252 | } | |
10253 | ||
10254 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10255 | if (type == 'p' || type == 'q') | |
10256 | val /= 2; | |
10257 | ||
10258 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10259 | || val < (mintiny << op->shift) | |
10260 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10261 | needext = TRUE; |
252b5132 | 10262 | else |
b34976b6 | 10263 | needext = FALSE; |
252b5132 RH |
10264 | |
10265 | if (warn && ext && ! needext) | |
beae10d5 KH |
10266 | as_warn_where (file, line, |
10267 | _("extended operand requested but not required")); | |
252b5132 RH |
10268 | if (small && needext) |
10269 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10270 | ||
10271 | if (small || (! ext && ! needext)) | |
10272 | { | |
10273 | int insnval; | |
10274 | ||
b34976b6 | 10275 | *use_extend = FALSE; |
252b5132 RH |
10276 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10277 | insnval <<= op->op_shift; | |
10278 | *insn |= insnval; | |
10279 | } | |
10280 | else | |
10281 | { | |
10282 | long minext, maxext; | |
10283 | int extval; | |
10284 | ||
10285 | if (op->extu) | |
10286 | { | |
10287 | minext = 0; | |
10288 | maxext = (1 << op->extbits) - 1; | |
10289 | } | |
10290 | else | |
10291 | { | |
10292 | minext = - (1 << (op->extbits - 1)); | |
10293 | maxext = (1 << (op->extbits - 1)) - 1; | |
10294 | } | |
10295 | if (val < minext || val > maxext) | |
10296 | as_bad_where (file, line, | |
10297 | _("operand value out of range for instruction")); | |
10298 | ||
b34976b6 | 10299 | *use_extend = TRUE; |
252b5132 RH |
10300 | if (op->extbits == 16) |
10301 | { | |
10302 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10303 | val &= 0x1f; | |
10304 | } | |
10305 | else if (op->extbits == 15) | |
10306 | { | |
10307 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10308 | val &= 0xf; | |
10309 | } | |
10310 | else | |
10311 | { | |
10312 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10313 | val = 0; | |
10314 | } | |
10315 | ||
10316 | *extend = (unsigned short) extval; | |
10317 | *insn |= val; | |
10318 | } | |
10319 | } | |
10320 | \f | |
d6f16593 | 10321 | struct percent_op_match |
ad8d3bb3 | 10322 | { |
5e0116d5 RS |
10323 | const char *str; |
10324 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10325 | }; |
10326 | ||
10327 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10328 | { |
5e0116d5 | 10329 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10330 | #ifdef OBJ_ELF |
5e0116d5 RS |
10331 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10332 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10333 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10334 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10335 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10336 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10337 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10338 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10339 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10340 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10341 | {"%half", BFD_RELOC_16}, | |
10342 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10343 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10344 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10345 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10346 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10347 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10348 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10349 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10350 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10351 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10352 | #endif |
5e0116d5 | 10353 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10354 | }; |
10355 | ||
d6f16593 MR |
10356 | static const struct percent_op_match mips16_percent_op[] = |
10357 | { | |
10358 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10359 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10360 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10361 | }; | |
10362 | ||
252b5132 | 10363 | |
5e0116d5 RS |
10364 | /* Return true if *STR points to a relocation operator. When returning true, |
10365 | move *STR over the operator and store its relocation code in *RELOC. | |
10366 | Leave both *STR and *RELOC alone when returning false. */ | |
10367 | ||
10368 | static bfd_boolean | |
17a2f251 | 10369 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10370 | { |
d6f16593 MR |
10371 | const struct percent_op_match *percent_op; |
10372 | size_t limit, i; | |
10373 | ||
10374 | if (mips_opts.mips16) | |
10375 | { | |
10376 | percent_op = mips16_percent_op; | |
10377 | limit = ARRAY_SIZE (mips16_percent_op); | |
10378 | } | |
10379 | else | |
10380 | { | |
10381 | percent_op = mips_percent_op; | |
10382 | limit = ARRAY_SIZE (mips_percent_op); | |
10383 | } | |
76b3015f | 10384 | |
d6f16593 | 10385 | for (i = 0; i < limit; i++) |
5e0116d5 | 10386 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10387 | { |
3f98094e DJ |
10388 | int len = strlen (percent_op[i].str); |
10389 | ||
10390 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10391 | continue; | |
10392 | ||
5e0116d5 RS |
10393 | *str += strlen (percent_op[i].str); |
10394 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10395 | |
5e0116d5 RS |
10396 | /* Check whether the output BFD supports this relocation. |
10397 | If not, issue an error and fall back on something safe. */ | |
10398 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10399 | { |
5e0116d5 RS |
10400 | as_bad ("relocation %s isn't supported by the current ABI", |
10401 | percent_op[i].str); | |
01a3f561 | 10402 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10403 | } |
5e0116d5 | 10404 | return TRUE; |
394f9b3a | 10405 | } |
5e0116d5 | 10406 | return FALSE; |
394f9b3a | 10407 | } |
ad8d3bb3 | 10408 | |
ad8d3bb3 | 10409 | |
5e0116d5 RS |
10410 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10411 | expression in *EP and the relocations in the array starting | |
10412 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10413 | |
01a3f561 | 10414 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10415 | |
5e0116d5 | 10416 | static size_t |
17a2f251 TS |
10417 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10418 | char *str) | |
ad8d3bb3 | 10419 | { |
5e0116d5 RS |
10420 | bfd_reloc_code_real_type reversed_reloc[3]; |
10421 | size_t reloc_index, i; | |
09b8f35a RS |
10422 | int crux_depth, str_depth; |
10423 | char *crux; | |
5e0116d5 RS |
10424 | |
10425 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10426 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10427 | of the main expression and with CRUX_DEPTH containing the number | |
10428 | of open brackets at that point. */ | |
10429 | reloc_index = -1; | |
10430 | str_depth = 0; | |
10431 | do | |
fb1b3232 | 10432 | { |
09b8f35a RS |
10433 | reloc_index++; |
10434 | crux = str; | |
10435 | crux_depth = str_depth; | |
10436 | ||
10437 | /* Skip over whitespace and brackets, keeping count of the number | |
10438 | of brackets. */ | |
10439 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10440 | if (*str++ == '(') | |
10441 | str_depth++; | |
5e0116d5 | 10442 | } |
09b8f35a RS |
10443 | while (*str == '%' |
10444 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10445 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10446 | |
09b8f35a | 10447 | my_getExpression (ep, crux); |
5e0116d5 | 10448 | str = expr_end; |
394f9b3a | 10449 | |
5e0116d5 | 10450 | /* Match every open bracket. */ |
09b8f35a | 10451 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10452 | if (*str++ == ')') |
09b8f35a | 10453 | crux_depth--; |
394f9b3a | 10454 | |
09b8f35a | 10455 | if (crux_depth > 0) |
5e0116d5 | 10456 | as_bad ("unclosed '('"); |
394f9b3a | 10457 | |
5e0116d5 | 10458 | expr_end = str; |
252b5132 | 10459 | |
01a3f561 | 10460 | if (reloc_index != 0) |
64bdfcaf RS |
10461 | { |
10462 | prev_reloc_op_frag = frag_now; | |
10463 | for (i = 0; i < reloc_index; i++) | |
10464 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10465 | } | |
fb1b3232 | 10466 | |
5e0116d5 | 10467 | return reloc_index; |
252b5132 RH |
10468 | } |
10469 | ||
10470 | static void | |
17a2f251 | 10471 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10472 | { |
10473 | char *save_in; | |
98aa84af | 10474 | valueT val; |
252b5132 RH |
10475 | |
10476 | save_in = input_line_pointer; | |
10477 | input_line_pointer = str; | |
10478 | expression (ep); | |
10479 | expr_end = input_line_pointer; | |
10480 | input_line_pointer = save_in; | |
10481 | ||
10482 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10483 | then we bump the value of the symbol by 1 since that is how other | |
10484 | text symbols are handled. We don't bother to handle complex | |
10485 | expressions, just `.' plus or minus a constant. */ | |
10486 | if (mips_opts.mips16 | |
10487 | && ep->X_op == O_symbol | |
10488 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10489 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10490 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10491 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10492 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10493 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10494 | } |
10495 | ||
10496 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10497 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10498 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10499 | returned, or NULL on OK. */ |
10500 | ||
10501 | char * | |
17a2f251 | 10502 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10503 | { |
10504 | int prec; | |
10505 | LITTLENUM_TYPE words[4]; | |
10506 | char *t; | |
10507 | int i; | |
10508 | ||
10509 | switch (type) | |
10510 | { | |
10511 | case 'f': | |
10512 | prec = 2; | |
10513 | break; | |
10514 | ||
10515 | case 'd': | |
10516 | prec = 4; | |
10517 | break; | |
10518 | ||
10519 | default: | |
10520 | *sizeP = 0; | |
10521 | return _("bad call to md_atof"); | |
10522 | } | |
10523 | ||
10524 | t = atof_ieee (input_line_pointer, type, words); | |
10525 | if (t) | |
10526 | input_line_pointer = t; | |
10527 | ||
10528 | *sizeP = prec * 2; | |
10529 | ||
10530 | if (! target_big_endian) | |
10531 | { | |
10532 | for (i = prec - 1; i >= 0; i--) | |
10533 | { | |
17a2f251 | 10534 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10535 | litP += 2; |
10536 | } | |
10537 | } | |
10538 | else | |
10539 | { | |
10540 | for (i = 0; i < prec; i++) | |
10541 | { | |
17a2f251 | 10542 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10543 | litP += 2; |
10544 | } | |
10545 | } | |
bdaaa2e1 | 10546 | |
252b5132 RH |
10547 | return NULL; |
10548 | } | |
10549 | ||
10550 | void | |
17a2f251 | 10551 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10552 | { |
10553 | if (target_big_endian) | |
10554 | number_to_chars_bigendian (buf, val, n); | |
10555 | else | |
10556 | number_to_chars_littleendian (buf, val, n); | |
10557 | } | |
10558 | \f | |
ae948b86 | 10559 | #ifdef OBJ_ELF |
e013f690 TS |
10560 | static int support_64bit_objects(void) |
10561 | { | |
10562 | const char **list, **l; | |
aa3d8fdf | 10563 | int yes; |
e013f690 TS |
10564 | |
10565 | list = bfd_target_list (); | |
10566 | for (l = list; *l != NULL; l++) | |
10567 | #ifdef TE_TMIPS | |
10568 | /* This is traditional mips */ | |
10569 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10570 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10571 | #else | |
10572 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10573 | || strcmp (*l, "elf64-littlemips") == 0) | |
10574 | #endif | |
10575 | break; | |
aa3d8fdf | 10576 | yes = (*l != NULL); |
e013f690 | 10577 | free (list); |
aa3d8fdf | 10578 | return yes; |
e013f690 | 10579 | } |
ae948b86 | 10580 | #endif /* OBJ_ELF */ |
e013f690 | 10581 | |
78849248 | 10582 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10583 | |
e972090a NC |
10584 | struct option md_longopts[] = |
10585 | { | |
f9b4148d CD |
10586 | /* Options which specify architecture. */ |
10587 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10588 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10589 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10590 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10591 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10592 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10593 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10594 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10595 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10596 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10597 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10598 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10599 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10600 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10601 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10602 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10603 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10604 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10605 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10606 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10607 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10608 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10609 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10610 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10611 | |
10612 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10613 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10614 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10615 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10616 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10617 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10618 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10619 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10620 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10621 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10622 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10623 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10624 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10625 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10626 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10627 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10628 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10629 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10630 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10631 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10632 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10633 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10634 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10635 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10636 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10637 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
f9b4148d CD |
10638 | |
10639 | /* Old-style architecture options. Don't add more of these. */ | |
e16bfa71 | 10640 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12) |
f9b4148d CD |
10641 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10642 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10643 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10644 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10645 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10646 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10647 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10648 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10649 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10650 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10651 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10652 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10653 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10654 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10655 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10656 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10657 | ||
10658 | /* Options which enable bug fixes. */ | |
10659 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10660 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10661 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10662 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10663 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10664 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10665 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10666 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10667 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10668 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10669 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10670 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10671 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10672 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10673 | |
10674 | /* Miscellaneous options. */ | |
7d8e00cf | 10675 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10676 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10677 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10678 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10679 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10680 | {"break", no_argument, NULL, OPTION_BREAK}, |
10681 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10682 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10683 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10684 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10685 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10686 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10687 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10688 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10689 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10690 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10691 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10692 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10693 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10694 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10695 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10696 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10697 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10698 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10699 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10700 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10701 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10702 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10703 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10704 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10705 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10706 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10707 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10708 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10709 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10710 | |
10711 | /* ELF-specific options. */ | |
156c2f8b | 10712 | #ifdef OBJ_ELF |
aed1a261 | 10713 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10714 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10715 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10716 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10717 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10718 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10719 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10720 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10721 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10722 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10723 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10724 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10725 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10726 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10727 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10728 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10729 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10730 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10731 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10732 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10733 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10734 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10735 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10736 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10737 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10738 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10739 | #endif /* OBJ_ELF */ |
f9b4148d | 10740 | |
252b5132 RH |
10741 | {NULL, no_argument, NULL, 0} |
10742 | }; | |
156c2f8b | 10743 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10744 | |
316f5878 RS |
10745 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10746 | NEW_VALUE. Warn if another value was already specified. Note: | |
10747 | we have to defer parsing the -march and -mtune arguments in order | |
10748 | to handle 'from-abi' correctly, since the ABI might be specified | |
10749 | in a later argument. */ | |
10750 | ||
10751 | static void | |
17a2f251 | 10752 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10753 | { |
10754 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10755 | as_warn (_("A different %s was already specified, is now %s"), | |
10756 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10757 | new_value); | |
10758 | ||
10759 | *string_ptr = new_value; | |
10760 | } | |
10761 | ||
252b5132 | 10762 | int |
17a2f251 | 10763 | md_parse_option (int c, char *arg) |
252b5132 RH |
10764 | { |
10765 | switch (c) | |
10766 | { | |
119d663a NC |
10767 | case OPTION_CONSTRUCT_FLOATS: |
10768 | mips_disable_float_construction = 0; | |
10769 | break; | |
bdaaa2e1 | 10770 | |
119d663a NC |
10771 | case OPTION_NO_CONSTRUCT_FLOATS: |
10772 | mips_disable_float_construction = 1; | |
10773 | break; | |
bdaaa2e1 | 10774 | |
252b5132 RH |
10775 | case OPTION_TRAP: |
10776 | mips_trap = 1; | |
10777 | break; | |
10778 | ||
10779 | case OPTION_BREAK: | |
10780 | mips_trap = 0; | |
10781 | break; | |
10782 | ||
10783 | case OPTION_EB: | |
10784 | target_big_endian = 1; | |
10785 | break; | |
10786 | ||
10787 | case OPTION_EL: | |
10788 | target_big_endian = 0; | |
10789 | break; | |
10790 | ||
10791 | case 'O': | |
10792 | if (arg && arg[1] == '0') | |
10793 | mips_optimize = 1; | |
10794 | else | |
10795 | mips_optimize = 2; | |
10796 | break; | |
10797 | ||
10798 | case 'g': | |
10799 | if (arg == NULL) | |
10800 | mips_debug = 2; | |
10801 | else | |
10802 | mips_debug = atoi (arg); | |
10803 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10804 | optimizations which limit full symbolic debugging. We take | |
10805 | that to be equivalent to -O0. */ | |
10806 | if (mips_debug == 2) | |
10807 | mips_optimize = 1; | |
10808 | break; | |
10809 | ||
10810 | case OPTION_MIPS1: | |
316f5878 | 10811 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10812 | break; |
10813 | ||
10814 | case OPTION_MIPS2: | |
316f5878 | 10815 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10816 | break; |
10817 | ||
10818 | case OPTION_MIPS3: | |
316f5878 | 10819 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10820 | break; |
10821 | ||
10822 | case OPTION_MIPS4: | |
316f5878 | 10823 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10824 | break; |
10825 | ||
84ea6cf2 | 10826 | case OPTION_MIPS5: |
316f5878 | 10827 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10828 | break; |
10829 | ||
e7af610e | 10830 | case OPTION_MIPS32: |
316f5878 | 10831 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10832 | break; |
10833 | ||
af7ee8bf CD |
10834 | case OPTION_MIPS32R2: |
10835 | file_mips_isa = ISA_MIPS32R2; | |
10836 | break; | |
10837 | ||
5f74bc13 CD |
10838 | case OPTION_MIPS64R2: |
10839 | file_mips_isa = ISA_MIPS64R2; | |
10840 | break; | |
10841 | ||
84ea6cf2 | 10842 | case OPTION_MIPS64: |
316f5878 | 10843 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10844 | break; |
10845 | ||
ec68c924 | 10846 | case OPTION_MTUNE: |
316f5878 RS |
10847 | mips_set_option_string (&mips_tune_string, arg); |
10848 | break; | |
ec68c924 | 10849 | |
316f5878 RS |
10850 | case OPTION_MARCH: |
10851 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10852 | break; |
10853 | ||
10854 | case OPTION_M4650: | |
316f5878 RS |
10855 | mips_set_option_string (&mips_arch_string, "4650"); |
10856 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10857 | break; |
10858 | ||
10859 | case OPTION_NO_M4650: | |
10860 | break; | |
10861 | ||
10862 | case OPTION_M4010: | |
316f5878 RS |
10863 | mips_set_option_string (&mips_arch_string, "4010"); |
10864 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10865 | break; |
10866 | ||
10867 | case OPTION_NO_M4010: | |
10868 | break; | |
10869 | ||
10870 | case OPTION_M4100: | |
316f5878 RS |
10871 | mips_set_option_string (&mips_arch_string, "4100"); |
10872 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10873 | break; |
10874 | ||
10875 | case OPTION_NO_M4100: | |
10876 | break; | |
10877 | ||
252b5132 | 10878 | case OPTION_M3900: |
316f5878 RS |
10879 | mips_set_option_string (&mips_arch_string, "3900"); |
10880 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10881 | break; |
bdaaa2e1 | 10882 | |
252b5132 RH |
10883 | case OPTION_NO_M3900: |
10884 | break; | |
10885 | ||
deec1734 CD |
10886 | case OPTION_MDMX: |
10887 | mips_opts.ase_mdmx = 1; | |
10888 | break; | |
10889 | ||
10890 | case OPTION_NO_MDMX: | |
10891 | mips_opts.ase_mdmx = 0; | |
10892 | break; | |
10893 | ||
74cd071d CF |
10894 | case OPTION_DSP: |
10895 | mips_opts.ase_dsp = 1; | |
10896 | break; | |
10897 | ||
10898 | case OPTION_NO_DSP: | |
10899 | mips_opts.ase_dsp = 0; | |
10900 | break; | |
10901 | ||
ef2e4d86 CF |
10902 | case OPTION_MT: |
10903 | mips_opts.ase_mt = 1; | |
10904 | break; | |
10905 | ||
10906 | case OPTION_NO_MT: | |
10907 | mips_opts.ase_mt = 0; | |
10908 | break; | |
10909 | ||
252b5132 RH |
10910 | case OPTION_MIPS16: |
10911 | mips_opts.mips16 = 1; | |
7d10b47d | 10912 | mips_no_prev_insn (); |
252b5132 RH |
10913 | break; |
10914 | ||
10915 | case OPTION_NO_MIPS16: | |
10916 | mips_opts.mips16 = 0; | |
7d10b47d | 10917 | mips_no_prev_insn (); |
252b5132 RH |
10918 | break; |
10919 | ||
1f25f5d3 CD |
10920 | case OPTION_MIPS3D: |
10921 | mips_opts.ase_mips3d = 1; | |
10922 | break; | |
10923 | ||
10924 | case OPTION_NO_MIPS3D: | |
10925 | mips_opts.ase_mips3d = 0; | |
10926 | break; | |
10927 | ||
e16bfa71 TS |
10928 | case OPTION_SMARTMIPS: |
10929 | mips_opts.ase_smartmips = 1; | |
10930 | break; | |
10931 | ||
10932 | case OPTION_NO_SMARTMIPS: | |
10933 | mips_opts.ase_smartmips = 0; | |
10934 | break; | |
10935 | ||
d766e8ec RS |
10936 | case OPTION_FIX_VR4120: |
10937 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10938 | break; |
10939 | ||
d766e8ec RS |
10940 | case OPTION_NO_FIX_VR4120: |
10941 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10942 | break; |
10943 | ||
7d8e00cf RS |
10944 | case OPTION_FIX_VR4130: |
10945 | mips_fix_vr4130 = 1; | |
10946 | break; | |
10947 | ||
10948 | case OPTION_NO_FIX_VR4130: | |
10949 | mips_fix_vr4130 = 0; | |
10950 | break; | |
10951 | ||
4a6a3df4 AO |
10952 | case OPTION_RELAX_BRANCH: |
10953 | mips_relax_branch = 1; | |
10954 | break; | |
10955 | ||
10956 | case OPTION_NO_RELAX_BRANCH: | |
10957 | mips_relax_branch = 0; | |
10958 | break; | |
10959 | ||
aa6975fb ILT |
10960 | case OPTION_MSHARED: |
10961 | mips_in_shared = TRUE; | |
10962 | break; | |
10963 | ||
10964 | case OPTION_MNO_SHARED: | |
10965 | mips_in_shared = FALSE; | |
10966 | break; | |
10967 | ||
aed1a261 RS |
10968 | case OPTION_MSYM32: |
10969 | mips_opts.sym32 = TRUE; | |
10970 | break; | |
10971 | ||
10972 | case OPTION_MNO_SYM32: | |
10973 | mips_opts.sym32 = FALSE; | |
10974 | break; | |
10975 | ||
0f074f60 | 10976 | #ifdef OBJ_ELF |
252b5132 RH |
10977 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10978 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10979 | intended to be compatible with Irix 5. */ | |
10980 | case OPTION_CALL_SHARED: | |
10981 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10982 | { | |
10983 | as_bad (_("-call_shared is supported only for ELF format")); | |
10984 | return 0; | |
10985 | } | |
10986 | mips_pic = SVR4_PIC; | |
143d77c5 | 10987 | mips_abicalls = TRUE; |
252b5132 RH |
10988 | break; |
10989 | ||
10990 | case OPTION_NON_SHARED: | |
10991 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10992 | { | |
10993 | as_bad (_("-non_shared is supported only for ELF format")); | |
10994 | return 0; | |
10995 | } | |
10996 | mips_pic = NO_PIC; | |
143d77c5 | 10997 | mips_abicalls = FALSE; |
252b5132 RH |
10998 | break; |
10999 | ||
44075ae2 TS |
11000 | /* The -xgot option tells the assembler to use 32 bit offsets |
11001 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11002 | compatibility. */ |
11003 | case OPTION_XGOT: | |
11004 | mips_big_got = 1; | |
11005 | break; | |
0f074f60 | 11006 | #endif /* OBJ_ELF */ |
252b5132 RH |
11007 | |
11008 | case 'G': | |
6caf9ef4 TS |
11009 | g_switch_value = atoi (arg); |
11010 | g_switch_seen = 1; | |
252b5132 RH |
11011 | break; |
11012 | ||
0f074f60 | 11013 | #ifdef OBJ_ELF |
34ba82a8 TS |
11014 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11015 | and -mabi=64. */ | |
252b5132 | 11016 | case OPTION_32: |
34ba82a8 TS |
11017 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11018 | { | |
11019 | as_bad (_("-32 is supported for ELF format only")); | |
11020 | return 0; | |
11021 | } | |
316f5878 | 11022 | mips_abi = O32_ABI; |
252b5132 RH |
11023 | break; |
11024 | ||
e013f690 | 11025 | case OPTION_N32: |
34ba82a8 TS |
11026 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11027 | { | |
11028 | as_bad (_("-n32 is supported for ELF format only")); | |
11029 | return 0; | |
11030 | } | |
316f5878 | 11031 | mips_abi = N32_ABI; |
e013f690 | 11032 | break; |
252b5132 | 11033 | |
e013f690 | 11034 | case OPTION_64: |
34ba82a8 TS |
11035 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11036 | { | |
11037 | as_bad (_("-64 is supported for ELF format only")); | |
11038 | return 0; | |
11039 | } | |
316f5878 | 11040 | mips_abi = N64_ABI; |
e013f690 TS |
11041 | if (! support_64bit_objects()) |
11042 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11043 | break; |
ae948b86 | 11044 | #endif /* OBJ_ELF */ |
252b5132 | 11045 | |
c97ef257 | 11046 | case OPTION_GP32: |
a325df1d | 11047 | file_mips_gp32 = 1; |
c97ef257 AH |
11048 | break; |
11049 | ||
11050 | case OPTION_GP64: | |
a325df1d | 11051 | file_mips_gp32 = 0; |
c97ef257 | 11052 | break; |
252b5132 | 11053 | |
ca4e0257 | 11054 | case OPTION_FP32: |
a325df1d | 11055 | file_mips_fp32 = 1; |
316f5878 RS |
11056 | break; |
11057 | ||
11058 | case OPTION_FP64: | |
11059 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11060 | break; |
11061 | ||
ae948b86 | 11062 | #ifdef OBJ_ELF |
252b5132 | 11063 | case OPTION_MABI: |
34ba82a8 TS |
11064 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11065 | { | |
11066 | as_bad (_("-mabi is supported for ELF format only")); | |
11067 | return 0; | |
11068 | } | |
e013f690 | 11069 | if (strcmp (arg, "32") == 0) |
316f5878 | 11070 | mips_abi = O32_ABI; |
e013f690 | 11071 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11072 | mips_abi = O64_ABI; |
e013f690 | 11073 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11074 | mips_abi = N32_ABI; |
e013f690 TS |
11075 | else if (strcmp (arg, "64") == 0) |
11076 | { | |
316f5878 | 11077 | mips_abi = N64_ABI; |
e013f690 TS |
11078 | if (! support_64bit_objects()) |
11079 | as_fatal (_("No compiled in support for 64 bit object file " | |
11080 | "format")); | |
11081 | } | |
11082 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11083 | mips_abi = EABI_ABI; |
e013f690 | 11084 | else |
da0e507f TS |
11085 | { |
11086 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11087 | return 0; | |
11088 | } | |
252b5132 | 11089 | break; |
e013f690 | 11090 | #endif /* OBJ_ELF */ |
252b5132 | 11091 | |
6b76fefe | 11092 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11093 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11094 | break; |
11095 | ||
9ee72ff1 | 11096 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11097 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11098 | break; |
11099 | ||
ecb4347a DJ |
11100 | #ifdef OBJ_ELF |
11101 | case OPTION_MDEBUG: | |
b34976b6 | 11102 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11103 | break; |
11104 | ||
11105 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11106 | mips_flag_mdebug = FALSE; |
ecb4347a | 11107 | break; |
dcd410fe RO |
11108 | |
11109 | case OPTION_PDR: | |
11110 | mips_flag_pdr = TRUE; | |
11111 | break; | |
11112 | ||
11113 | case OPTION_NO_PDR: | |
11114 | mips_flag_pdr = FALSE; | |
11115 | break; | |
0a44bf69 RS |
11116 | |
11117 | case OPTION_MVXWORKS_PIC: | |
11118 | mips_pic = VXWORKS_PIC; | |
11119 | break; | |
ecb4347a DJ |
11120 | #endif /* OBJ_ELF */ |
11121 | ||
252b5132 RH |
11122 | default: |
11123 | return 0; | |
11124 | } | |
11125 | ||
11126 | return 1; | |
11127 | } | |
316f5878 RS |
11128 | \f |
11129 | /* Set up globals to generate code for the ISA or processor | |
11130 | described by INFO. */ | |
252b5132 | 11131 | |
252b5132 | 11132 | static void |
17a2f251 | 11133 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11134 | { |
316f5878 | 11135 | if (info != 0) |
252b5132 | 11136 | { |
fef14a42 TS |
11137 | file_mips_arch = info->cpu; |
11138 | mips_opts.arch = info->cpu; | |
316f5878 | 11139 | mips_opts.isa = info->isa; |
252b5132 | 11140 | } |
252b5132 RH |
11141 | } |
11142 | ||
252b5132 | 11143 | |
316f5878 | 11144 | /* Likewise for tuning. */ |
252b5132 | 11145 | |
316f5878 | 11146 | static void |
17a2f251 | 11147 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11148 | { |
11149 | if (info != 0) | |
fef14a42 | 11150 | mips_tune = info->cpu; |
316f5878 | 11151 | } |
80cc45a5 | 11152 | |
34ba82a8 | 11153 | |
252b5132 | 11154 | void |
17a2f251 | 11155 | mips_after_parse_args (void) |
e9670677 | 11156 | { |
fef14a42 TS |
11157 | const struct mips_cpu_info *arch_info = 0; |
11158 | const struct mips_cpu_info *tune_info = 0; | |
11159 | ||
e9670677 | 11160 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11161 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11162 | { |
6caf9ef4 | 11163 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11164 | as_bad (_("-G not supported in this configuration.")); |
11165 | g_switch_value = 0; | |
11166 | } | |
11167 | ||
cac012d6 AO |
11168 | if (mips_abi == NO_ABI) |
11169 | mips_abi = MIPS_DEFAULT_ABI; | |
11170 | ||
22923709 RS |
11171 | /* The following code determines the architecture and register size. |
11172 | Similar code was added to GCC 3.3 (see override_options() in | |
11173 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11174 | as much as possible. */ | |
e9670677 | 11175 | |
316f5878 | 11176 | if (mips_arch_string != 0) |
fef14a42 | 11177 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11178 | |
316f5878 | 11179 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11180 | { |
316f5878 | 11181 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11182 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11183 | the -march selection (if any). */ |
fef14a42 | 11184 | if (arch_info != 0) |
e9670677 | 11185 | { |
316f5878 RS |
11186 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11187 | There's no harm in specifying both as long as the ISA levels | |
11188 | are the same. */ | |
fef14a42 | 11189 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11190 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11191 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11192 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11193 | } |
316f5878 | 11194 | else |
fef14a42 | 11195 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11196 | } |
11197 | ||
fef14a42 TS |
11198 | if (arch_info == 0) |
11199 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11200 | |
fef14a42 | 11201 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11202 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11203 | arch_info->name); |
11204 | ||
11205 | mips_set_architecture (arch_info); | |
11206 | ||
11207 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11208 | if (mips_tune_string != 0) | |
11209 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11210 | |
fef14a42 TS |
11211 | if (tune_info == 0) |
11212 | mips_set_tune (arch_info); | |
11213 | else | |
11214 | mips_set_tune (tune_info); | |
e9670677 | 11215 | |
316f5878 | 11216 | if (file_mips_gp32 >= 0) |
e9670677 | 11217 | { |
316f5878 RS |
11218 | /* The user specified the size of the integer registers. Make sure |
11219 | it agrees with the ABI and ISA. */ | |
11220 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11221 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11222 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11223 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11224 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11225 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11226 | } |
11227 | else | |
11228 | { | |
316f5878 RS |
11229 | /* Infer the integer register size from the ABI and processor. |
11230 | Restrict ourselves to 32-bit registers if that's all the | |
11231 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11232 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11233 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11234 | } |
11235 | ||
316f5878 RS |
11236 | /* ??? GAS treats single-float processors as though they had 64-bit |
11237 | float registers (although it complains when double-precision | |
11238 | instructions are used). As things stand, saying they have 32-bit | |
11239 | registers would lead to spurious "register must be even" messages. | |
11240 | So here we assume float registers are always the same size as | |
11241 | integer ones, unless the user says otherwise. */ | |
11242 | if (file_mips_fp32 < 0) | |
11243 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 11244 | |
316f5878 | 11245 | /* End of GCC-shared inference code. */ |
e9670677 | 11246 | |
17a2f251 TS |
11247 | /* This flag is set when we have a 64-bit capable CPU but use only |
11248 | 32-bit wide registers. Note that EABI does not use it. */ | |
11249 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11250 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11251 | || mips_abi == O32_ABI)) | |
316f5878 | 11252 | mips_32bitmode = 1; |
e9670677 MR |
11253 | |
11254 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11255 | as_bad (_("trap exception not supported at ISA 1")); | |
11256 | ||
e9670677 MR |
11257 | /* If the selected architecture includes support for ASEs, enable |
11258 | generation of code for them. */ | |
a4672219 | 11259 | if (mips_opts.mips16 == -1) |
fef14a42 | 11260 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11261 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 11262 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11263 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 11264 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
74cd071d CF |
11265 | if (mips_opts.ase_dsp == -1) |
11266 | mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0; | |
ef2e4d86 CF |
11267 | if (mips_opts.ase_mt == -1) |
11268 | mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0; | |
e9670677 | 11269 | |
e9670677 | 11270 | file_mips_isa = mips_opts.isa; |
a4672219 | 11271 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11272 | file_ase_mips3d = mips_opts.ase_mips3d; |
11273 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11274 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11275 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 11276 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11277 | mips_opts.gp32 = file_mips_gp32; |
11278 | mips_opts.fp32 = file_mips_fp32; | |
11279 | ||
ecb4347a DJ |
11280 | if (mips_flag_mdebug < 0) |
11281 | { | |
11282 | #ifdef OBJ_MAYBE_ECOFF | |
11283 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11284 | mips_flag_mdebug = 1; | |
11285 | else | |
11286 | #endif /* OBJ_MAYBE_ECOFF */ | |
11287 | mips_flag_mdebug = 0; | |
11288 | } | |
e9670677 MR |
11289 | } |
11290 | \f | |
11291 | void | |
17a2f251 | 11292 | mips_init_after_args (void) |
252b5132 RH |
11293 | { |
11294 | /* initialize opcodes */ | |
11295 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11296 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11297 | } |
11298 | ||
11299 | long | |
17a2f251 | 11300 | md_pcrel_from (fixS *fixP) |
252b5132 | 11301 | { |
a7ebbfdf TS |
11302 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11303 | switch (fixP->fx_r_type) | |
11304 | { | |
11305 | case BFD_RELOC_16_PCREL_S2: | |
11306 | case BFD_RELOC_MIPS_JMP: | |
11307 | /* Return the address of the delay slot. */ | |
11308 | return addr + 4; | |
11309 | default: | |
11310 | return addr; | |
11311 | } | |
252b5132 RH |
11312 | } |
11313 | ||
252b5132 RH |
11314 | /* This is called before the symbol table is processed. In order to |
11315 | work with gcc when using mips-tfile, we must keep all local labels. | |
11316 | However, in other cases, we want to discard them. If we were | |
11317 | called with -g, but we didn't see any debugging information, it may | |
11318 | mean that gcc is smuggling debugging information through to | |
11319 | mips-tfile, in which case we must generate all local labels. */ | |
11320 | ||
11321 | void | |
17a2f251 | 11322 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11323 | { |
11324 | #ifndef NO_ECOFF_DEBUGGING | |
11325 | if (ECOFF_DEBUGGING | |
11326 | && mips_debug != 0 | |
11327 | && ! ecoff_debugging_seen) | |
11328 | flag_keep_locals = 1; | |
11329 | #endif | |
11330 | } | |
11331 | ||
3b91255e | 11332 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11333 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11334 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11335 | relocation operators. | |
11336 | ||
11337 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11338 | expression if: | |
11339 | ||
11340 | (a) it refers to the same symbol; and | |
11341 | (b) the offset applied in the %lo() expression is no lower than | |
11342 | the offset applied in the %got() or %hi(). | |
11343 | ||
11344 | (b) allows us to cope with code like: | |
11345 | ||
11346 | lui $4,%hi(foo) | |
11347 | lh $4,%lo(foo+2)($4) | |
11348 | ||
11349 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11350 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11351 | the high 16 bits. | |
11352 | ||
11353 | When several %lo()s match a particular %got() or %hi(), we use the | |
11354 | following rules to distinguish them: | |
11355 | ||
11356 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11357 | higher offsets. | |
11358 | ||
11359 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11360 | that already have a matching %got() or %hi(). | |
11361 | ||
11362 | (3) later %lo()s are better than earlier %lo()s. | |
11363 | ||
11364 | These rules are applied in order. | |
11365 | ||
11366 | (1) means, among other things, that %lo()s with identical offsets are | |
11367 | chosen if they exist. | |
11368 | ||
11369 | (2) means that we won't associate several high-part relocations with | |
11370 | the same low-part relocation unless there's no alternative. Having | |
11371 | several high parts for the same low part is a GNU extension; this rule | |
11372 | allows careful users to avoid it. | |
11373 | ||
11374 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11375 | with the last high-part relocation being at the front of the list. | |
11376 | It therefore makes sense to choose the last matching low-part | |
11377 | relocation, all other things being equal. It's also easier | |
11378 | to code that way. */ | |
252b5132 RH |
11379 | |
11380 | void | |
17a2f251 | 11381 | mips_frob_file (void) |
252b5132 RH |
11382 | { |
11383 | struct mips_hi_fixup *l; | |
11384 | ||
11385 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11386 | { | |
11387 | segment_info_type *seginfo; | |
3b91255e RS |
11388 | bfd_boolean matched_lo_p; |
11389 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11390 | |
5919d012 | 11391 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11392 | |
5919d012 RS |
11393 | /* If a GOT16 relocation turns out to be against a global symbol, |
11394 | there isn't supposed to be a matching LO. */ | |
11395 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11396 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11397 | continue; | |
11398 | ||
11399 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11400 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11401 | continue; |
11402 | ||
252b5132 | 11403 | seginfo = seg_info (l->seg); |
252b5132 | 11404 | |
3b91255e RS |
11405 | /* Set HI_POS to the position of this relocation in the chain. |
11406 | Set LO_POS to the position of the chosen low-part relocation. | |
11407 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11408 | relocation that matches an immediately-preceding high-part | |
11409 | relocation. */ | |
11410 | hi_pos = NULL; | |
11411 | lo_pos = NULL; | |
11412 | matched_lo_p = FALSE; | |
11413 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11414 | { | |
11415 | if (*pos == l->fixp) | |
11416 | hi_pos = pos; | |
11417 | ||
704803a9 MR |
11418 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11419 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11420 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11421 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11422 | && (lo_pos == NULL | |
11423 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11424 | || (!matched_lo_p | |
11425 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11426 | lo_pos = pos; | |
11427 | ||
11428 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11429 | && fixup_has_matching_lo_p (*pos)); | |
11430 | } | |
11431 | ||
11432 | /* If we found a match, remove the high-part relocation from its | |
11433 | current position and insert it before the low-part relocation. | |
11434 | Make the offsets match so that fixup_has_matching_lo_p() | |
11435 | will return true. | |
11436 | ||
11437 | We don't warn about unmatched high-part relocations since some | |
11438 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11439 | instructions. */ | |
11440 | if (lo_pos != NULL) | |
11441 | { | |
11442 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11443 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11444 | { |
3b91255e RS |
11445 | *hi_pos = l->fixp->fx_next; |
11446 | l->fixp->fx_next = *lo_pos; | |
11447 | *lo_pos = l->fixp; | |
252b5132 | 11448 | } |
252b5132 RH |
11449 | } |
11450 | } | |
11451 | } | |
11452 | ||
3e722fb5 | 11453 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11454 | We have to prevent gas from dropping them. */ |
252b5132 | 11455 | |
252b5132 | 11456 | int |
17a2f251 | 11457 | mips_force_relocation (fixS *fixp) |
252b5132 | 11458 | { |
ae6063d4 | 11459 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11460 | return 1; |
11461 | ||
f6688943 TS |
11462 | if (HAVE_NEWABI |
11463 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11464 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11465 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11466 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11467 | return 1; | |
11468 | ||
3e722fb5 | 11469 | return 0; |
252b5132 RH |
11470 | } |
11471 | ||
11472 | /* Apply a fixup to the object file. */ | |
11473 | ||
94f592af | 11474 | void |
55cf6793 | 11475 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11476 | { |
874e8986 | 11477 | bfd_byte *buf; |
98aa84af | 11478 | long insn; |
a7ebbfdf | 11479 | reloc_howto_type *howto; |
252b5132 | 11480 | |
a7ebbfdf TS |
11481 | /* We ignore generic BFD relocations we don't know about. */ |
11482 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11483 | if (! howto) | |
11484 | return; | |
65551fa4 | 11485 | |
252b5132 RH |
11486 | assert (fixP->fx_size == 4 |
11487 | || fixP->fx_r_type == BFD_RELOC_16 | |
11488 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11489 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11490 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11491 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11492 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11493 | |
a7ebbfdf | 11494 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11495 | |
bad36eac | 11496 | assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11497 | |
11498 | /* Don't treat parts of a composite relocation as done. There are two | |
11499 | reasons for this: | |
11500 | ||
11501 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11502 | should nevertheless be emitted if the first part is. | |
11503 | ||
11504 | (2) In normal usage, composite relocations are never assembly-time | |
11505 | constants. The easiest way of dealing with the pathological | |
11506 | exceptions is to generate a relocation against STN_UNDEF and | |
11507 | leave everything up to the linker. */ | |
bad36eac | 11508 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11509 | fixP->fx_done = 1; |
11510 | ||
11511 | switch (fixP->fx_r_type) | |
11512 | { | |
3f98094e DJ |
11513 | case BFD_RELOC_MIPS_TLS_GD: |
11514 | case BFD_RELOC_MIPS_TLS_LDM: | |
11515 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11516 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11517 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11518 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11519 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11520 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11521 | /* fall through */ | |
11522 | ||
252b5132 | 11523 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11524 | case BFD_RELOC_MIPS_SHIFT5: |
11525 | case BFD_RELOC_MIPS_SHIFT6: | |
11526 | case BFD_RELOC_MIPS_GOT_DISP: | |
11527 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11528 | case BFD_RELOC_MIPS_GOT_OFST: | |
11529 | case BFD_RELOC_MIPS_SUB: | |
11530 | case BFD_RELOC_MIPS_INSERT_A: | |
11531 | case BFD_RELOC_MIPS_INSERT_B: | |
11532 | case BFD_RELOC_MIPS_DELETE: | |
11533 | case BFD_RELOC_MIPS_HIGHEST: | |
11534 | case BFD_RELOC_MIPS_HIGHER: | |
11535 | case BFD_RELOC_MIPS_SCN_DISP: | |
11536 | case BFD_RELOC_MIPS_REL16: | |
11537 | case BFD_RELOC_MIPS_RELGOT: | |
11538 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11539 | case BFD_RELOC_HI16: |
11540 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11541 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11542 | case BFD_RELOC_MIPS_LITERAL: |
11543 | case BFD_RELOC_MIPS_CALL16: | |
11544 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11545 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11546 | case BFD_RELOC_MIPS_GOT_HI16: |
11547 | case BFD_RELOC_MIPS_GOT_LO16: | |
11548 | case BFD_RELOC_MIPS_CALL_HI16: | |
11549 | case BFD_RELOC_MIPS_CALL_LO16: | |
11550 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11551 | case BFD_RELOC_MIPS16_HI16: |
11552 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 RH |
11553 | /* Nothing needed to do. The value comes from the reloc entry */ |
11554 | break; | |
11555 | ||
11556 | case BFD_RELOC_MIPS16_JMP: | |
11557 | /* We currently always generate a reloc against a symbol, which | |
11558 | means that we don't want an addend even if the symbol is | |
11559 | defined. */ | |
a7ebbfdf | 11560 | *valP = 0; |
252b5132 RH |
11561 | break; |
11562 | ||
252b5132 RH |
11563 | case BFD_RELOC_64: |
11564 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11565 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11566 | if (fixP->fx_done) |
252b5132 RH |
11567 | { |
11568 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11569 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11570 | else |
11571 | { | |
a7ebbfdf | 11572 | valueT hiv; |
252b5132 | 11573 | |
a7ebbfdf | 11574 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11575 | hiv = 0xffffffff; |
11576 | else | |
11577 | hiv = 0; | |
b215186b | 11578 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11579 | *valP, 4); |
b215186b | 11580 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11581 | hiv, 4); |
252b5132 RH |
11582 | } |
11583 | } | |
11584 | break; | |
11585 | ||
056350c6 | 11586 | case BFD_RELOC_RVA: |
252b5132 RH |
11587 | case BFD_RELOC_32: |
11588 | /* If we are deleting this reloc entry, we must fill in the | |
11589 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11590 | resolved when it appears but is later defined. */ |
11591 | if (fixP->fx_done) | |
2132e3a3 | 11592 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11593 | break; |
11594 | ||
11595 | case BFD_RELOC_16: | |
11596 | /* If we are deleting this reloc entry, we must fill in the | |
11597 | value now. */ | |
252b5132 | 11598 | if (fixP->fx_done) |
2132e3a3 | 11599 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11600 | break; |
11601 | ||
11602 | case BFD_RELOC_LO16: | |
d6f16593 | 11603 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11604 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11605 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11606 | /* When handling an embedded PIC switch statement, we can wind |
11607 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11608 | if (fixP->fx_done) | |
11609 | { | |
a7ebbfdf | 11610 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11611 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11612 | _("relocation overflow")); | |
252b5132 RH |
11613 | if (target_big_endian) |
11614 | buf += 2; | |
2132e3a3 | 11615 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11616 | } |
11617 | break; | |
11618 | ||
11619 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11620 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11621 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11622 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11623 | |
252b5132 RH |
11624 | /* |
11625 | * We need to save the bits in the instruction since fixup_segment() | |
11626 | * might be deleting the relocation entry (i.e., a branch within | |
11627 | * the current segment). | |
11628 | */ | |
a7ebbfdf | 11629 | if (! fixP->fx_done) |
bb2d6cd7 | 11630 | break; |
252b5132 RH |
11631 | |
11632 | /* update old instruction data */ | |
252b5132 RH |
11633 | if (target_big_endian) |
11634 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11635 | else | |
11636 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11637 | ||
a7ebbfdf TS |
11638 | if (*valP + 0x20000 <= 0x3ffff) |
11639 | { | |
11640 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11641 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11642 | } |
11643 | else if (mips_pic == NO_PIC | |
11644 | && fixP->fx_done | |
11645 | && fixP->fx_frag->fr_address >= text_section->vma | |
11646 | && (fixP->fx_frag->fr_address | |
587aac4e | 11647 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11648 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11649 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11650 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11651 | { |
11652 | /* The branch offset is too large. If this is an | |
11653 | unconditional branch, and we are not generating PIC code, | |
11654 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11655 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11656 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11657 | else |
a7ebbfdf TS |
11658 | insn = 0x08000000; /* j */ |
11659 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11660 | fixP->fx_done = 0; | |
11661 | fixP->fx_addsy = section_symbol (text_section); | |
11662 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11663 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11664 | } |
11665 | else | |
11666 | { | |
11667 | /* If we got here, we have branch-relaxation disabled, | |
11668 | and there's nothing we can do to fix this instruction | |
11669 | without turning it into a longer sequence. */ | |
11670 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11671 | _("Branch out of range")); | |
252b5132 | 11672 | } |
252b5132 RH |
11673 | break; |
11674 | ||
11675 | case BFD_RELOC_VTABLE_INHERIT: | |
11676 | fixP->fx_done = 0; | |
11677 | if (fixP->fx_addsy | |
11678 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11679 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11680 | S_SET_WEAK (fixP->fx_addsy); | |
11681 | break; | |
11682 | ||
11683 | case BFD_RELOC_VTABLE_ENTRY: | |
11684 | fixP->fx_done = 0; | |
11685 | break; | |
11686 | ||
11687 | default: | |
11688 | internalError (); | |
11689 | } | |
a7ebbfdf TS |
11690 | |
11691 | /* Remember value for tc_gen_reloc. */ | |
11692 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11693 | } |
11694 | ||
252b5132 | 11695 | static symbolS * |
17a2f251 | 11696 | get_symbol (void) |
252b5132 RH |
11697 | { |
11698 | int c; | |
11699 | char *name; | |
11700 | symbolS *p; | |
11701 | ||
11702 | name = input_line_pointer; | |
11703 | c = get_symbol_end (); | |
11704 | p = (symbolS *) symbol_find_or_make (name); | |
11705 | *input_line_pointer = c; | |
11706 | return p; | |
11707 | } | |
11708 | ||
11709 | /* Align the current frag to a given power of two. The MIPS assembler | |
11710 | also automatically adjusts any preceding label. */ | |
11711 | ||
11712 | static void | |
17a2f251 | 11713 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11714 | { |
7d10b47d | 11715 | mips_emit_delays (); |
252b5132 RH |
11716 | frag_align (to, fill, 0); |
11717 | record_alignment (now_seg, to); | |
11718 | if (label != NULL) | |
11719 | { | |
11720 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11721 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11722 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11723 | } | |
11724 | } | |
11725 | ||
11726 | /* Align to a given power of two. .align 0 turns off the automatic | |
11727 | alignment used by the data creating pseudo-ops. */ | |
11728 | ||
11729 | static void | |
17a2f251 | 11730 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11731 | { |
11732 | register int temp; | |
11733 | register long temp_fill; | |
11734 | long max_alignment = 15; | |
11735 | ||
11736 | /* | |
11737 | ||
67c1ffbe | 11738 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11739 | to the aligned address. |
11740 | o It's not documented but auto alignment is reinstated by | |
11741 | a .align pseudo instruction. | |
11742 | o Note also that after auto alignment is turned off the mips assembler | |
11743 | issues an error on attempt to assemble an improperly aligned data item. | |
11744 | We don't. | |
11745 | ||
11746 | */ | |
11747 | ||
11748 | temp = get_absolute_expression (); | |
11749 | if (temp > max_alignment) | |
11750 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11751 | else if (temp < 0) | |
11752 | { | |
11753 | as_warn (_("Alignment negative: 0 assumed.")); | |
11754 | temp = 0; | |
11755 | } | |
11756 | if (*input_line_pointer == ',') | |
11757 | { | |
f9419b05 | 11758 | ++input_line_pointer; |
252b5132 RH |
11759 | temp_fill = get_absolute_expression (); |
11760 | } | |
11761 | else | |
11762 | temp_fill = 0; | |
11763 | if (temp) | |
11764 | { | |
11765 | auto_align = 1; | |
11766 | mips_align (temp, (int) temp_fill, | |
11767 | insn_labels != NULL ? insn_labels->label : NULL); | |
11768 | } | |
11769 | else | |
11770 | { | |
11771 | auto_align = 0; | |
11772 | } | |
11773 | ||
11774 | demand_empty_rest_of_line (); | |
11775 | } | |
11776 | ||
252b5132 | 11777 | static void |
17a2f251 | 11778 | s_change_sec (int sec) |
252b5132 RH |
11779 | { |
11780 | segT seg; | |
11781 | ||
252b5132 RH |
11782 | #ifdef OBJ_ELF |
11783 | /* The ELF backend needs to know that we are changing sections, so | |
11784 | that .previous works correctly. We could do something like check | |
b6ff326e | 11785 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11786 | as it would not be appropriate to use it in the section changing |
11787 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11788 | This should be cleaner, somehow. */ | |
11789 | obj_elf_section_change_hook (); | |
11790 | #endif | |
11791 | ||
7d10b47d | 11792 | mips_emit_delays (); |
252b5132 RH |
11793 | switch (sec) |
11794 | { | |
11795 | case 't': | |
11796 | s_text (0); | |
11797 | break; | |
11798 | case 'd': | |
11799 | s_data (0); | |
11800 | break; | |
11801 | case 'b': | |
11802 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11803 | demand_empty_rest_of_line (); | |
11804 | break; | |
11805 | ||
11806 | case 'r': | |
4d0d148d TS |
11807 | seg = subseg_new (RDATA_SECTION_NAME, |
11808 | (subsegT) get_absolute_expression ()); | |
11809 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11810 | { |
4d0d148d TS |
11811 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11812 | | SEC_READONLY | SEC_RELOC | |
11813 | | SEC_DATA)); | |
11814 | if (strcmp (TARGET_OS, "elf") != 0) | |
11815 | record_alignment (seg, 4); | |
252b5132 | 11816 | } |
4d0d148d | 11817 | demand_empty_rest_of_line (); |
252b5132 RH |
11818 | break; |
11819 | ||
11820 | case 's': | |
4d0d148d TS |
11821 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11822 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11823 | { |
4d0d148d TS |
11824 | bfd_set_section_flags (stdoutput, seg, |
11825 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11826 | if (strcmp (TARGET_OS, "elf") != 0) | |
11827 | record_alignment (seg, 4); | |
252b5132 | 11828 | } |
4d0d148d TS |
11829 | demand_empty_rest_of_line (); |
11830 | break; | |
252b5132 RH |
11831 | } |
11832 | ||
11833 | auto_align = 1; | |
11834 | } | |
b34976b6 | 11835 | |
cca86cc8 | 11836 | void |
17a2f251 | 11837 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11838 | { |
7ed4a06a | 11839 | #ifdef OBJ_ELF |
cca86cc8 SC |
11840 | char *section_name; |
11841 | char c; | |
684022ea | 11842 | char next_c = 0; |
cca86cc8 SC |
11843 | int section_type; |
11844 | int section_flag; | |
11845 | int section_entry_size; | |
11846 | int section_alignment; | |
b34976b6 | 11847 | |
7ed4a06a TS |
11848 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11849 | return; | |
11850 | ||
cca86cc8 SC |
11851 | section_name = input_line_pointer; |
11852 | c = get_symbol_end (); | |
a816d1ed AO |
11853 | if (c) |
11854 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11855 | |
4cf0dd0d TS |
11856 | /* Do we have .section Name<,"flags">? */ |
11857 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11858 | { |
4cf0dd0d TS |
11859 | /* just after name is now '\0'. */ |
11860 | *input_line_pointer = c; | |
cca86cc8 SC |
11861 | input_line_pointer = section_name; |
11862 | obj_elf_section (ignore); | |
11863 | return; | |
11864 | } | |
11865 | input_line_pointer++; | |
11866 | ||
11867 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11868 | if (c == ',') | |
11869 | section_type = get_absolute_expression (); | |
11870 | else | |
11871 | section_type = 0; | |
11872 | if (*input_line_pointer++ == ',') | |
11873 | section_flag = get_absolute_expression (); | |
11874 | else | |
11875 | section_flag = 0; | |
11876 | if (*input_line_pointer++ == ',') | |
11877 | section_entry_size = get_absolute_expression (); | |
11878 | else | |
11879 | section_entry_size = 0; | |
11880 | if (*input_line_pointer++ == ',') | |
11881 | section_alignment = get_absolute_expression (); | |
11882 | else | |
11883 | section_alignment = 0; | |
11884 | ||
a816d1ed AO |
11885 | section_name = xstrdup (section_name); |
11886 | ||
8ab8a5c8 RS |
11887 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11888 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11889 | traditionally had to fall back on the more common @progbits instead. | |
11890 | ||
11891 | There's nothing really harmful in this, since bfd will correct | |
11892 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 11893 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
11894 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
11895 | ||
11896 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11897 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11898 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11899 | generic type-checking code. */ | |
11900 | if (section_type == SHT_MIPS_DWARF) | |
11901 | section_type = SHT_PROGBITS; | |
11902 | ||
cca86cc8 SC |
11903 | obj_elf_change_section (section_name, section_type, section_flag, |
11904 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11905 | |
11906 | if (now_seg->name != section_name) | |
11907 | free (section_name); | |
7ed4a06a | 11908 | #endif /* OBJ_ELF */ |
cca86cc8 | 11909 | } |
252b5132 RH |
11910 | |
11911 | void | |
17a2f251 | 11912 | mips_enable_auto_align (void) |
252b5132 RH |
11913 | { |
11914 | auto_align = 1; | |
11915 | } | |
11916 | ||
11917 | static void | |
17a2f251 | 11918 | s_cons (int log_size) |
252b5132 RH |
11919 | { |
11920 | symbolS *label; | |
11921 | ||
11922 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11923 | mips_emit_delays (); |
252b5132 RH |
11924 | if (log_size > 0 && auto_align) |
11925 | mips_align (log_size, 0, label); | |
11926 | mips_clear_insn_labels (); | |
11927 | cons (1 << log_size); | |
11928 | } | |
11929 | ||
11930 | static void | |
17a2f251 | 11931 | s_float_cons (int type) |
252b5132 RH |
11932 | { |
11933 | symbolS *label; | |
11934 | ||
11935 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11936 | ||
7d10b47d | 11937 | mips_emit_delays (); |
252b5132 RH |
11938 | |
11939 | if (auto_align) | |
49309057 ILT |
11940 | { |
11941 | if (type == 'd') | |
11942 | mips_align (3, 0, label); | |
11943 | else | |
11944 | mips_align (2, 0, label); | |
11945 | } | |
252b5132 RH |
11946 | |
11947 | mips_clear_insn_labels (); | |
11948 | ||
11949 | float_cons (type); | |
11950 | } | |
11951 | ||
11952 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11953 | permitted to say | |
11954 | .globl foo .text | |
11955 | where foo is an undefined symbol, to mean that foo should be | |
11956 | considered to be the address of a function. */ | |
11957 | ||
11958 | static void | |
17a2f251 | 11959 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11960 | { |
11961 | char *name; | |
11962 | int c; | |
11963 | symbolS *symbolP; | |
11964 | flagword flag; | |
11965 | ||
8a06b769 | 11966 | do |
252b5132 | 11967 | { |
8a06b769 | 11968 | name = input_line_pointer; |
252b5132 | 11969 | c = get_symbol_end (); |
8a06b769 TS |
11970 | symbolP = symbol_find_or_make (name); |
11971 | S_SET_EXTERNAL (symbolP); | |
11972 | ||
252b5132 | 11973 | *input_line_pointer = c; |
8a06b769 | 11974 | SKIP_WHITESPACE (); |
252b5132 | 11975 | |
8a06b769 TS |
11976 | /* On Irix 5, every global symbol that is not explicitly labelled as |
11977 | being a function is apparently labelled as being an object. */ | |
11978 | flag = BSF_OBJECT; | |
252b5132 | 11979 | |
8a06b769 TS |
11980 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
11981 | && (*input_line_pointer != ',')) | |
11982 | { | |
11983 | char *secname; | |
11984 | asection *sec; | |
11985 | ||
11986 | secname = input_line_pointer; | |
11987 | c = get_symbol_end (); | |
11988 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11989 | if (sec == NULL) | |
11990 | as_bad (_("%s: no such section"), secname); | |
11991 | *input_line_pointer = c; | |
11992 | ||
11993 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11994 | flag = BSF_FUNCTION; | |
11995 | } | |
11996 | ||
11997 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
11998 | ||
11999 | c = *input_line_pointer; | |
12000 | if (c == ',') | |
12001 | { | |
12002 | input_line_pointer++; | |
12003 | SKIP_WHITESPACE (); | |
12004 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12005 | c = '\n'; | |
12006 | } | |
12007 | } | |
12008 | while (c == ','); | |
252b5132 | 12009 | |
252b5132 RH |
12010 | demand_empty_rest_of_line (); |
12011 | } | |
12012 | ||
12013 | static void | |
17a2f251 | 12014 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12015 | { |
12016 | char *opt; | |
12017 | char c; | |
12018 | ||
12019 | opt = input_line_pointer; | |
12020 | c = get_symbol_end (); | |
12021 | ||
12022 | if (*opt == 'O') | |
12023 | { | |
12024 | /* FIXME: What does this mean? */ | |
12025 | } | |
12026 | else if (strncmp (opt, "pic", 3) == 0) | |
12027 | { | |
12028 | int i; | |
12029 | ||
12030 | i = atoi (opt + 3); | |
12031 | if (i == 0) | |
12032 | mips_pic = NO_PIC; | |
12033 | else if (i == 2) | |
143d77c5 | 12034 | { |
252b5132 | 12035 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12036 | mips_abicalls = TRUE; |
12037 | } | |
252b5132 RH |
12038 | else |
12039 | as_bad (_(".option pic%d not supported"), i); | |
12040 | ||
4d0d148d | 12041 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12042 | { |
12043 | if (g_switch_seen && g_switch_value != 0) | |
12044 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12045 | g_switch_value = 0; | |
12046 | bfd_set_gp_size (stdoutput, 0); | |
12047 | } | |
12048 | } | |
12049 | else | |
12050 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12051 | ||
12052 | *input_line_pointer = c; | |
12053 | demand_empty_rest_of_line (); | |
12054 | } | |
12055 | ||
12056 | /* This structure is used to hold a stack of .set values. */ | |
12057 | ||
e972090a NC |
12058 | struct mips_option_stack |
12059 | { | |
252b5132 RH |
12060 | struct mips_option_stack *next; |
12061 | struct mips_set_options options; | |
12062 | }; | |
12063 | ||
12064 | static struct mips_option_stack *mips_opts_stack; | |
12065 | ||
12066 | /* Handle the .set pseudo-op. */ | |
12067 | ||
12068 | static void | |
17a2f251 | 12069 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12070 | { |
12071 | char *name = input_line_pointer, ch; | |
12072 | ||
12073 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12074 | ++input_line_pointer; |
252b5132 RH |
12075 | ch = *input_line_pointer; |
12076 | *input_line_pointer = '\0'; | |
12077 | ||
12078 | if (strcmp (name, "reorder") == 0) | |
12079 | { | |
7d10b47d RS |
12080 | if (mips_opts.noreorder) |
12081 | end_noreorder (); | |
252b5132 RH |
12082 | } |
12083 | else if (strcmp (name, "noreorder") == 0) | |
12084 | { | |
7d10b47d RS |
12085 | if (!mips_opts.noreorder) |
12086 | start_noreorder (); | |
252b5132 RH |
12087 | } |
12088 | else if (strcmp (name, "at") == 0) | |
12089 | { | |
12090 | mips_opts.noat = 0; | |
12091 | } | |
12092 | else if (strcmp (name, "noat") == 0) | |
12093 | { | |
12094 | mips_opts.noat = 1; | |
12095 | } | |
12096 | else if (strcmp (name, "macro") == 0) | |
12097 | { | |
12098 | mips_opts.warn_about_macros = 0; | |
12099 | } | |
12100 | else if (strcmp (name, "nomacro") == 0) | |
12101 | { | |
12102 | if (mips_opts.noreorder == 0) | |
12103 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12104 | mips_opts.warn_about_macros = 1; | |
12105 | } | |
12106 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12107 | { | |
12108 | mips_opts.nomove = 0; | |
12109 | } | |
12110 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12111 | { | |
12112 | mips_opts.nomove = 1; | |
12113 | } | |
12114 | else if (strcmp (name, "bopt") == 0) | |
12115 | { | |
12116 | mips_opts.nobopt = 0; | |
12117 | } | |
12118 | else if (strcmp (name, "nobopt") == 0) | |
12119 | { | |
12120 | mips_opts.nobopt = 1; | |
12121 | } | |
12122 | else if (strcmp (name, "mips16") == 0 | |
12123 | || strcmp (name, "MIPS-16") == 0) | |
12124 | mips_opts.mips16 = 1; | |
12125 | else if (strcmp (name, "nomips16") == 0 | |
12126 | || strcmp (name, "noMIPS-16") == 0) | |
12127 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12128 | else if (strcmp (name, "smartmips") == 0) |
12129 | { | |
12130 | if (!ISA_SUPPORT_SMARTMIPS) | |
12131 | as_warn ("%s ISA does not support SmartMIPS ASE", | |
12132 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12133 | mips_opts.ase_smartmips = 1; | |
12134 | } | |
12135 | else if (strcmp (name, "nosmartmips") == 0) | |
12136 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12137 | else if (strcmp (name, "mips3d") == 0) |
12138 | mips_opts.ase_mips3d = 1; | |
12139 | else if (strcmp (name, "nomips3d") == 0) | |
12140 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12141 | else if (strcmp (name, "mdmx") == 0) |
12142 | mips_opts.ase_mdmx = 1; | |
12143 | else if (strcmp (name, "nomdmx") == 0) | |
12144 | mips_opts.ase_mdmx = 0; | |
74cd071d CF |
12145 | else if (strcmp (name, "dsp") == 0) |
12146 | mips_opts.ase_dsp = 1; | |
12147 | else if (strcmp (name, "nodsp") == 0) | |
12148 | mips_opts.ase_dsp = 0; | |
ef2e4d86 CF |
12149 | else if (strcmp (name, "mt") == 0) |
12150 | mips_opts.ase_mt = 1; | |
12151 | else if (strcmp (name, "nomt") == 0) | |
12152 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12153 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12154 | { |
af7ee8bf | 12155 | int reset = 0; |
252b5132 | 12156 | |
1a2c1fad CD |
12157 | /* Permit the user to change the ISA and architecture on the fly. |
12158 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12159 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12160 | { |
12161 | reset = 1; | |
12162 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12163 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12164 | } |
12165 | else if (strncmp (name, "arch=", 5) == 0) | |
12166 | { | |
12167 | const struct mips_cpu_info *p; | |
12168 | ||
12169 | p = mips_parse_cpu("internal use", name + 5); | |
12170 | if (!p) | |
12171 | as_bad (_("unknown architecture %s"), name + 5); | |
12172 | else | |
12173 | { | |
12174 | mips_opts.arch = p->cpu; | |
12175 | mips_opts.isa = p->isa; | |
12176 | } | |
12177 | } | |
81a21e38 TS |
12178 | else if (strncmp (name, "mips", 4) == 0) |
12179 | { | |
12180 | const struct mips_cpu_info *p; | |
12181 | ||
12182 | p = mips_parse_cpu("internal use", name); | |
12183 | if (!p) | |
12184 | as_bad (_("unknown ISA level %s"), name + 4); | |
12185 | else | |
12186 | { | |
12187 | mips_opts.arch = p->cpu; | |
12188 | mips_opts.isa = p->isa; | |
12189 | } | |
12190 | } | |
af7ee8bf | 12191 | else |
81a21e38 | 12192 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12193 | |
12194 | switch (mips_opts.isa) | |
98d3f06f KH |
12195 | { |
12196 | case 0: | |
98d3f06f | 12197 | break; |
af7ee8bf CD |
12198 | case ISA_MIPS1: |
12199 | case ISA_MIPS2: | |
12200 | case ISA_MIPS32: | |
12201 | case ISA_MIPS32R2: | |
98d3f06f KH |
12202 | mips_opts.gp32 = 1; |
12203 | mips_opts.fp32 = 1; | |
12204 | break; | |
af7ee8bf CD |
12205 | case ISA_MIPS3: |
12206 | case ISA_MIPS4: | |
12207 | case ISA_MIPS5: | |
12208 | case ISA_MIPS64: | |
5f74bc13 | 12209 | case ISA_MIPS64R2: |
98d3f06f KH |
12210 | mips_opts.gp32 = 0; |
12211 | mips_opts.fp32 = 0; | |
12212 | break; | |
12213 | default: | |
12214 | as_bad (_("unknown ISA level %s"), name + 4); | |
12215 | break; | |
12216 | } | |
af7ee8bf | 12217 | if (reset) |
98d3f06f | 12218 | { |
af7ee8bf CD |
12219 | mips_opts.gp32 = file_mips_gp32; |
12220 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12221 | } |
252b5132 RH |
12222 | } |
12223 | else if (strcmp (name, "autoextend") == 0) | |
12224 | mips_opts.noautoextend = 0; | |
12225 | else if (strcmp (name, "noautoextend") == 0) | |
12226 | mips_opts.noautoextend = 1; | |
12227 | else if (strcmp (name, "push") == 0) | |
12228 | { | |
12229 | struct mips_option_stack *s; | |
12230 | ||
12231 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12232 | s->next = mips_opts_stack; | |
12233 | s->options = mips_opts; | |
12234 | mips_opts_stack = s; | |
12235 | } | |
12236 | else if (strcmp (name, "pop") == 0) | |
12237 | { | |
12238 | struct mips_option_stack *s; | |
12239 | ||
12240 | s = mips_opts_stack; | |
12241 | if (s == NULL) | |
12242 | as_bad (_(".set pop with no .set push")); | |
12243 | else | |
12244 | { | |
12245 | /* If we're changing the reorder mode we need to handle | |
12246 | delay slots correctly. */ | |
12247 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12248 | start_noreorder (); |
252b5132 | 12249 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12250 | end_noreorder (); |
252b5132 RH |
12251 | |
12252 | mips_opts = s->options; | |
12253 | mips_opts_stack = s->next; | |
12254 | free (s); | |
12255 | } | |
12256 | } | |
aed1a261 RS |
12257 | else if (strcmp (name, "sym32") == 0) |
12258 | mips_opts.sym32 = TRUE; | |
12259 | else if (strcmp (name, "nosym32") == 0) | |
12260 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12261 | else |
12262 | { | |
12263 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12264 | } | |
12265 | *input_line_pointer = ch; | |
12266 | demand_empty_rest_of_line (); | |
12267 | } | |
12268 | ||
12269 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12270 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12271 | ||
12272 | static void | |
17a2f251 | 12273 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12274 | { |
12275 | mips_pic = SVR4_PIC; | |
143d77c5 | 12276 | mips_abicalls = TRUE; |
4d0d148d TS |
12277 | |
12278 | if (g_switch_seen && g_switch_value != 0) | |
12279 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12280 | g_switch_value = 0; | |
12281 | ||
252b5132 RH |
12282 | bfd_set_gp_size (stdoutput, 0); |
12283 | demand_empty_rest_of_line (); | |
12284 | } | |
12285 | ||
12286 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12287 | PIC code. It sets the $gp register for the function based on the | |
12288 | function address, which is in the register named in the argument. | |
12289 | This uses a relocation against _gp_disp, which is handled specially | |
12290 | by the linker. The result is: | |
12291 | lui $gp,%hi(_gp_disp) | |
12292 | addiu $gp,$gp,%lo(_gp_disp) | |
12293 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12294 | The .cpload argument is normally $25 == $t9. |
12295 | ||
12296 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12297 | lui $gp,%hi(__gnu_local_gp) |
12298 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12299 | and the argument is ignored. This saves an instruction, but the |
12300 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12301 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12302 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12303 | |
12304 | static void | |
17a2f251 | 12305 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12306 | { |
12307 | expressionS ex; | |
aa6975fb ILT |
12308 | int reg; |
12309 | int in_shared; | |
252b5132 | 12310 | |
6478892d TS |
12311 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12312 | .cpload is ignored. */ | |
12313 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12314 | { |
12315 | s_ignore (0); | |
12316 | return; | |
12317 | } | |
12318 | ||
d3ecfc59 | 12319 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12320 | if (mips_opts.noreorder == 0) |
12321 | as_warn (_(".cpload not in noreorder section")); | |
12322 | ||
aa6975fb ILT |
12323 | reg = tc_get_register (0); |
12324 | ||
12325 | /* If we need to produce a 64-bit address, we are better off using | |
12326 | the default instruction sequence. */ | |
aed1a261 | 12327 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12328 | |
252b5132 | 12329 | ex.X_op = O_symbol; |
bbe506e8 TS |
12330 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12331 | "__gnu_local_gp"); | |
252b5132 RH |
12332 | ex.X_op_symbol = NULL; |
12333 | ex.X_add_number = 0; | |
12334 | ||
12335 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12336 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12337 | |
584892a6 | 12338 | macro_start (); |
67c0d1eb RS |
12339 | macro_build_lui (&ex, mips_gp_register); |
12340 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12341 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12342 | if (in_shared) |
12343 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12344 | mips_gp_register, reg); | |
584892a6 | 12345 | macro_end (); |
252b5132 RH |
12346 | |
12347 | demand_empty_rest_of_line (); | |
12348 | } | |
12349 | ||
6478892d TS |
12350 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12351 | .cpsetup $reg1, offset|$reg2, label | |
12352 | ||
12353 | If offset is given, this results in: | |
12354 | sd $gp, offset($sp) | |
956cd1d6 | 12355 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12356 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12357 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12358 | |
12359 | If $reg2 is given, this results in: | |
12360 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12361 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12362 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12363 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12364 | $reg1 is normally $25 == $t9. |
12365 | ||
12366 | The -mno-shared option replaces the last three instructions with | |
12367 | lui $gp,%hi(_gp) | |
12368 | addiu $gp,$gp,%lo(_gp) | |
12369 | */ | |
12370 | ||
6478892d | 12371 | static void |
17a2f251 | 12372 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12373 | { |
12374 | expressionS ex_off; | |
12375 | expressionS ex_sym; | |
12376 | int reg1; | |
6478892d | 12377 | |
8586fc66 | 12378 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12379 | We also need NewABI support. */ |
12380 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12381 | { | |
12382 | s_ignore (0); | |
12383 | return; | |
12384 | } | |
12385 | ||
12386 | reg1 = tc_get_register (0); | |
12387 | SKIP_WHITESPACE (); | |
12388 | if (*input_line_pointer != ',') | |
12389 | { | |
12390 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12391 | return; | |
12392 | } | |
12393 | else | |
80245285 | 12394 | ++input_line_pointer; |
6478892d TS |
12395 | SKIP_WHITESPACE (); |
12396 | if (*input_line_pointer == '$') | |
80245285 TS |
12397 | { |
12398 | mips_cpreturn_register = tc_get_register (0); | |
12399 | mips_cpreturn_offset = -1; | |
12400 | } | |
6478892d | 12401 | else |
80245285 TS |
12402 | { |
12403 | mips_cpreturn_offset = get_absolute_expression (); | |
12404 | mips_cpreturn_register = -1; | |
12405 | } | |
6478892d TS |
12406 | SKIP_WHITESPACE (); |
12407 | if (*input_line_pointer != ',') | |
12408 | { | |
12409 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12410 | return; | |
12411 | } | |
12412 | else | |
f9419b05 | 12413 | ++input_line_pointer; |
6478892d | 12414 | SKIP_WHITESPACE (); |
f21f8242 | 12415 | expression (&ex_sym); |
6478892d | 12416 | |
584892a6 | 12417 | macro_start (); |
6478892d TS |
12418 | if (mips_cpreturn_register == -1) |
12419 | { | |
12420 | ex_off.X_op = O_constant; | |
12421 | ex_off.X_add_symbol = NULL; | |
12422 | ex_off.X_op_symbol = NULL; | |
12423 | ex_off.X_add_number = mips_cpreturn_offset; | |
12424 | ||
67c0d1eb | 12425 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12426 | BFD_RELOC_LO16, SP); |
6478892d TS |
12427 | } |
12428 | else | |
67c0d1eb | 12429 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12430 | mips_gp_register, 0); |
6478892d | 12431 | |
aed1a261 | 12432 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12433 | { |
12434 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12435 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12436 | BFD_RELOC_HI16_S); | |
12437 | ||
12438 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12439 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12440 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12441 | ||
12442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12443 | mips_gp_register, reg1); | |
12444 | } | |
12445 | else | |
12446 | { | |
12447 | expressionS ex; | |
12448 | ||
12449 | ex.X_op = O_symbol; | |
4184909a | 12450 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12451 | ex.X_op_symbol = NULL; |
12452 | ex.X_add_number = 0; | |
6e1304d8 | 12453 | |
aa6975fb ILT |
12454 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12455 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12456 | ||
12457 | macro_build_lui (&ex, mips_gp_register); | |
12458 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12459 | mips_gp_register, BFD_RELOC_LO16); | |
12460 | } | |
f21f8242 | 12461 | |
584892a6 | 12462 | macro_end (); |
6478892d TS |
12463 | |
12464 | demand_empty_rest_of_line (); | |
12465 | } | |
12466 | ||
12467 | static void | |
17a2f251 | 12468 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12469 | { |
12470 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12471 | .cplocal is ignored. */ | |
12472 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12473 | { | |
12474 | s_ignore (0); | |
12475 | return; | |
12476 | } | |
12477 | ||
12478 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12479 | demand_empty_rest_of_line (); |
6478892d TS |
12480 | } |
12481 | ||
252b5132 RH |
12482 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12483 | offset from $sp. The offset is remembered, and after making a PIC | |
12484 | call $gp is restored from that location. */ | |
12485 | ||
12486 | static void | |
17a2f251 | 12487 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12488 | { |
12489 | expressionS ex; | |
252b5132 | 12490 | |
6478892d | 12491 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12492 | .cprestore is ignored. */ |
6478892d | 12493 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12494 | { |
12495 | s_ignore (0); | |
12496 | return; | |
12497 | } | |
12498 | ||
12499 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12500 | mips_cprestore_valid = 1; |
252b5132 RH |
12501 | |
12502 | ex.X_op = O_constant; | |
12503 | ex.X_add_symbol = NULL; | |
12504 | ex.X_op_symbol = NULL; | |
12505 | ex.X_add_number = mips_cprestore_offset; | |
12506 | ||
584892a6 | 12507 | macro_start (); |
67c0d1eb RS |
12508 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12509 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12510 | macro_end (); |
252b5132 RH |
12511 | |
12512 | demand_empty_rest_of_line (); | |
12513 | } | |
12514 | ||
6478892d | 12515 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12516 | was given in the preceding .cpsetup, it results in: |
6478892d | 12517 | ld $gp, offset($sp) |
76b3015f | 12518 | |
6478892d | 12519 | If a register $reg2 was given there, it results in: |
609f23f4 | 12520 | daddu $gp, $reg2, $0 |
6478892d TS |
12521 | */ |
12522 | static void | |
17a2f251 | 12523 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12524 | { |
12525 | expressionS ex; | |
6478892d TS |
12526 | |
12527 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12528 | We also need NewABI support. */ | |
12529 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12530 | { | |
12531 | s_ignore (0); | |
12532 | return; | |
12533 | } | |
12534 | ||
584892a6 | 12535 | macro_start (); |
6478892d TS |
12536 | if (mips_cpreturn_register == -1) |
12537 | { | |
12538 | ex.X_op = O_constant; | |
12539 | ex.X_add_symbol = NULL; | |
12540 | ex.X_op_symbol = NULL; | |
12541 | ex.X_add_number = mips_cpreturn_offset; | |
12542 | ||
67c0d1eb | 12543 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12544 | } |
12545 | else | |
67c0d1eb | 12546 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12547 | mips_cpreturn_register, 0); |
584892a6 | 12548 | macro_end (); |
6478892d TS |
12549 | |
12550 | demand_empty_rest_of_line (); | |
12551 | } | |
12552 | ||
12553 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12554 | code. It sets the offset to use in gp_rel relocations. */ | |
12555 | ||
12556 | static void | |
17a2f251 | 12557 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12558 | { |
12559 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12560 | We also need NewABI support. */ | |
12561 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12562 | { | |
12563 | s_ignore (0); | |
12564 | return; | |
12565 | } | |
12566 | ||
def2e0dd | 12567 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12568 | |
12569 | demand_empty_rest_of_line (); | |
12570 | } | |
12571 | ||
252b5132 RH |
12572 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12573 | code. It generates a 32 bit GP relative reloc. */ | |
12574 | ||
12575 | static void | |
17a2f251 | 12576 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12577 | { |
12578 | symbolS *label; | |
12579 | expressionS ex; | |
12580 | char *p; | |
12581 | ||
12582 | /* When not generating PIC code, this is treated as .word. */ | |
12583 | if (mips_pic != SVR4_PIC) | |
12584 | { | |
12585 | s_cons (2); | |
12586 | return; | |
12587 | } | |
12588 | ||
12589 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12590 | mips_emit_delays (); |
252b5132 RH |
12591 | if (auto_align) |
12592 | mips_align (2, 0, label); | |
12593 | mips_clear_insn_labels (); | |
12594 | ||
12595 | expression (&ex); | |
12596 | ||
12597 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12598 | { | |
12599 | as_bad (_("Unsupported use of .gpword")); | |
12600 | ignore_rest_of_line (); | |
12601 | } | |
12602 | ||
12603 | p = frag_more (4); | |
17a2f251 | 12604 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12605 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12606 | BFD_RELOC_GPREL32); |
252b5132 RH |
12607 | |
12608 | demand_empty_rest_of_line (); | |
12609 | } | |
12610 | ||
10181a0d | 12611 | static void |
17a2f251 | 12612 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12613 | { |
12614 | symbolS *label; | |
12615 | expressionS ex; | |
12616 | char *p; | |
12617 | ||
12618 | /* When not generating PIC code, this is treated as .dword. */ | |
12619 | if (mips_pic != SVR4_PIC) | |
12620 | { | |
12621 | s_cons (3); | |
12622 | return; | |
12623 | } | |
12624 | ||
12625 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12626 | mips_emit_delays (); |
10181a0d AO |
12627 | if (auto_align) |
12628 | mips_align (3, 0, label); | |
12629 | mips_clear_insn_labels (); | |
12630 | ||
12631 | expression (&ex); | |
12632 | ||
12633 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12634 | { | |
12635 | as_bad (_("Unsupported use of .gpdword")); | |
12636 | ignore_rest_of_line (); | |
12637 | } | |
12638 | ||
12639 | p = frag_more (8); | |
17a2f251 | 12640 | md_number_to_chars (p, 0, 8); |
a105a300 | 12641 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12642 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12643 | |
12644 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12645 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12646 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12647 | |
12648 | demand_empty_rest_of_line (); | |
12649 | } | |
12650 | ||
252b5132 RH |
12651 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12652 | tables in SVR4 PIC code. */ | |
12653 | ||
12654 | static void | |
17a2f251 | 12655 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12656 | { |
252b5132 RH |
12657 | int reg; |
12658 | ||
10181a0d AO |
12659 | /* This is ignored when not generating SVR4 PIC code. */ |
12660 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12661 | { |
12662 | s_ignore (0); | |
12663 | return; | |
12664 | } | |
12665 | ||
12666 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12667 | macro_start (); |
252b5132 | 12668 | reg = tc_get_register (0); |
67c0d1eb | 12669 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12670 | macro_end (); |
252b5132 | 12671 | |
bdaaa2e1 | 12672 | demand_empty_rest_of_line (); |
252b5132 RH |
12673 | } |
12674 | ||
12675 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12676 | mips16 mode. This permits the linker to handle them specially, | |
12677 | such as generating jalx instructions when needed. We also make | |
12678 | them odd for the duration of the assembly, in order to generate the | |
12679 | right sort of code. We will make them even in the adjust_symtab | |
12680 | routine, while leaving them marked. This is convenient for the | |
12681 | debugger and the disassembler. The linker knows to make them odd | |
12682 | again. */ | |
12683 | ||
12684 | static void | |
17a2f251 | 12685 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12686 | { |
f9419b05 | 12687 | mips16_mark_labels (); |
252b5132 RH |
12688 | |
12689 | demand_empty_rest_of_line (); | |
12690 | } | |
12691 | ||
12692 | /* Handle a .stabn directive. We need these in order to mark a label | |
12693 | as being a mips16 text label correctly. Sometimes the compiler | |
12694 | will emit a label, followed by a .stabn, and then switch sections. | |
12695 | If the label and .stabn are in mips16 mode, then the label is | |
12696 | really a mips16 text label. */ | |
12697 | ||
12698 | static void | |
17a2f251 | 12699 | s_mips_stab (int type) |
252b5132 | 12700 | { |
f9419b05 | 12701 | if (type == 'n') |
252b5132 RH |
12702 | mips16_mark_labels (); |
12703 | ||
12704 | s_stab (type); | |
12705 | } | |
12706 | ||
12707 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12708 | */ | |
12709 | ||
12710 | static void | |
17a2f251 | 12711 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12712 | { |
12713 | char *name; | |
12714 | int c; | |
12715 | symbolS *symbolP; | |
12716 | expressionS exp; | |
12717 | ||
12718 | name = input_line_pointer; | |
12719 | c = get_symbol_end (); | |
12720 | symbolP = symbol_find_or_make (name); | |
12721 | S_SET_WEAK (symbolP); | |
12722 | *input_line_pointer = c; | |
12723 | ||
12724 | SKIP_WHITESPACE (); | |
12725 | ||
12726 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12727 | { | |
12728 | if (S_IS_DEFINED (symbolP)) | |
12729 | { | |
956cd1d6 | 12730 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12731 | S_GET_NAME (symbolP)); |
12732 | ignore_rest_of_line (); | |
12733 | return; | |
12734 | } | |
bdaaa2e1 | 12735 | |
252b5132 RH |
12736 | if (*input_line_pointer == ',') |
12737 | { | |
12738 | ++input_line_pointer; | |
12739 | SKIP_WHITESPACE (); | |
12740 | } | |
bdaaa2e1 | 12741 | |
252b5132 RH |
12742 | expression (&exp); |
12743 | if (exp.X_op != O_symbol) | |
12744 | { | |
12745 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12746 | ignore_rest_of_line (); |
252b5132 RH |
12747 | return; |
12748 | } | |
49309057 | 12749 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12750 | } |
12751 | ||
12752 | demand_empty_rest_of_line (); | |
12753 | } | |
12754 | ||
12755 | /* Parse a register string into a number. Called from the ECOFF code | |
12756 | to parse .frame. The argument is non-zero if this is the frame | |
12757 | register, so that we can record it in mips_frame_reg. */ | |
12758 | ||
12759 | int | |
17a2f251 | 12760 | tc_get_register (int frame) |
252b5132 RH |
12761 | { |
12762 | int reg; | |
12763 | ||
12764 | SKIP_WHITESPACE (); | |
12765 | if (*input_line_pointer++ != '$') | |
12766 | { | |
12767 | as_warn (_("expected `$'")); | |
85b51719 | 12768 | reg = ZERO; |
252b5132 | 12769 | } |
3882b010 | 12770 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12771 | { |
12772 | reg = get_absolute_expression (); | |
12773 | if (reg < 0 || reg >= 32) | |
12774 | { | |
12775 | as_warn (_("Bad register number")); | |
85b51719 | 12776 | reg = ZERO; |
252b5132 RH |
12777 | } |
12778 | } | |
12779 | else | |
12780 | { | |
76db943d | 12781 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12782 | { |
12783 | reg = RA; | |
12784 | input_line_pointer += 2; | |
12785 | } | |
76db943d | 12786 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12787 | { |
12788 | reg = FP; | |
12789 | input_line_pointer += 2; | |
12790 | } | |
252b5132 | 12791 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12792 | { |
12793 | reg = SP; | |
12794 | input_line_pointer += 2; | |
12795 | } | |
252b5132 | 12796 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12797 | { |
12798 | reg = GP; | |
12799 | input_line_pointer += 2; | |
12800 | } | |
252b5132 | 12801 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12802 | { |
12803 | reg = AT; | |
12804 | input_line_pointer += 2; | |
12805 | } | |
12806 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12807 | { | |
12808 | reg = KT0; | |
12809 | input_line_pointer += 3; | |
12810 | } | |
12811 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12812 | { | |
12813 | reg = KT1; | |
12814 | input_line_pointer += 3; | |
12815 | } | |
12816 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12817 | { | |
12818 | reg = ZERO; | |
12819 | input_line_pointer += 4; | |
12820 | } | |
252b5132 RH |
12821 | else |
12822 | { | |
12823 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12824 | reg = ZERO; |
12825 | while (ISALNUM(*input_line_pointer)) | |
12826 | input_line_pointer++; | |
252b5132 | 12827 | } |
252b5132 RH |
12828 | } |
12829 | if (frame) | |
7a621144 DJ |
12830 | { |
12831 | mips_frame_reg = reg != 0 ? reg : SP; | |
12832 | mips_frame_reg_valid = 1; | |
12833 | mips_cprestore_valid = 0; | |
12834 | } | |
252b5132 RH |
12835 | return reg; |
12836 | } | |
12837 | ||
12838 | valueT | |
17a2f251 | 12839 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12840 | { |
12841 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12842 | ||
12843 | #ifdef OBJ_ELF | |
12844 | /* We don't need to align ELF sections to the full alignment. | |
12845 | However, Irix 5 may prefer that we align them at least to a 16 | |
12846 | byte boundary. We don't bother to align the sections if we are | |
12847 | targeted for an embedded system. */ | |
12848 | if (strcmp (TARGET_OS, "elf") == 0) | |
12849 | return addr; | |
12850 | if (align > 4) | |
12851 | align = 4; | |
12852 | #endif | |
12853 | ||
12854 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12855 | } | |
12856 | ||
12857 | /* Utility routine, called from above as well. If called while the | |
12858 | input file is still being read, it's only an approximation. (For | |
12859 | example, a symbol may later become defined which appeared to be | |
12860 | undefined earlier.) */ | |
12861 | ||
12862 | static int | |
17a2f251 | 12863 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12864 | { |
12865 | if (sym == 0) | |
12866 | return 0; | |
12867 | ||
4d0d148d | 12868 | if (g_switch_value > 0) |
252b5132 RH |
12869 | { |
12870 | const char *symname; | |
12871 | int change; | |
12872 | ||
c9914766 | 12873 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12874 | register. It can be if it is smaller than the -G size or if |
12875 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12876 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12877 | they can. */ |
12878 | symname = S_GET_NAME (sym); | |
12879 | if (symname != (const char *) NULL | |
12880 | && (strcmp (symname, "eprol") == 0 | |
12881 | || strcmp (symname, "etext") == 0 | |
12882 | || strcmp (symname, "_gp") == 0 | |
12883 | || strcmp (symname, "edata") == 0 | |
12884 | || strcmp (symname, "_fbss") == 0 | |
12885 | || strcmp (symname, "_fdata") == 0 | |
12886 | || strcmp (symname, "_ftext") == 0 | |
12887 | || strcmp (symname, "end") == 0 | |
12888 | || strcmp (symname, "_gp_disp") == 0)) | |
12889 | change = 1; | |
12890 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12891 | && (0 | |
12892 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12893 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12894 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12895 | <= g_switch_value)) | |
252b5132 RH |
12896 | #endif |
12897 | /* We must defer this decision until after the whole | |
12898 | file has been read, since there might be a .extern | |
12899 | after the first use of this symbol. */ | |
12900 | || (before_relaxing | |
12901 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12902 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12903 | #endif |
12904 | && S_GET_VALUE (sym) == 0) | |
12905 | || (S_GET_VALUE (sym) != 0 | |
12906 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12907 | change = 0; | |
12908 | else | |
12909 | { | |
12910 | const char *segname; | |
12911 | ||
12912 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12913 | assert (strcmp (segname, ".lit8") != 0 | |
12914 | && strcmp (segname, ".lit4") != 0); | |
12915 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12916 | && strcmp (segname, ".sbss") != 0 |
12917 | && strncmp (segname, ".sdata.", 7) != 0 | |
12918 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12919 | } |
12920 | return change; | |
12921 | } | |
12922 | else | |
c9914766 | 12923 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12924 | return 1; |
12925 | } | |
12926 | ||
5919d012 RS |
12927 | |
12928 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12929 | ||
12930 | static bfd_boolean | |
17a2f251 | 12931 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12932 | { |
12933 | asection *symsec; | |
12934 | bfd_boolean linkonce; | |
12935 | ||
12936 | /* Handle the case of a symbol equated to another symbol. */ | |
12937 | while (symbol_equated_reloc_p (sym)) | |
12938 | { | |
12939 | symbolS *n; | |
12940 | ||
12941 | /* It's possible to get a loop here in a badly written | |
12942 | program. */ | |
12943 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12944 | if (n == sym) | |
12945 | break; | |
12946 | sym = n; | |
12947 | } | |
12948 | ||
12949 | symsec = S_GET_SEGMENT (sym); | |
12950 | ||
12951 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12952 | linkonce = FALSE; | |
12953 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12954 | { | |
12955 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12956 | != 0) | |
12957 | linkonce = TRUE; | |
12958 | ||
12959 | /* The GNU toolchain uses an extension for ELF: a section | |
12960 | beginning with the magic string .gnu.linkonce is a linkonce | |
12961 | section. */ | |
12962 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12963 | sizeof ".gnu.linkonce" - 1) == 0) | |
12964 | linkonce = TRUE; | |
12965 | } | |
12966 | ||
12967 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12968 | return (symsec != &bfd_und_section | |
12969 | && symsec != &bfd_abs_section | |
12970 | && ! bfd_is_com_section (symsec) | |
12971 | && !linkonce | |
12972 | #ifdef OBJ_ELF | |
12973 | /* A global or weak symbol is treated as external. */ | |
12974 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12975 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12976 | #endif |
12977 | ); | |
12978 | } | |
12979 | ||
12980 | ||
252b5132 RH |
12981 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12982 | extended opcode. SEC is the section the frag is in. */ | |
12983 | ||
12984 | static int | |
17a2f251 | 12985 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12986 | { |
12987 | int type; | |
12988 | register const struct mips16_immed_operand *op; | |
12989 | offsetT val; | |
12990 | int mintiny, maxtiny; | |
12991 | segT symsec; | |
98aa84af | 12992 | fragS *sym_frag; |
252b5132 RH |
12993 | |
12994 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12995 | return 0; | |
12996 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12997 | return 1; | |
12998 | ||
12999 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13000 | op = mips16_immed_operands; | |
13001 | while (op->type != type) | |
13002 | { | |
13003 | ++op; | |
13004 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13005 | } | |
13006 | ||
13007 | if (op->unsp) | |
13008 | { | |
13009 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13010 | { | |
13011 | mintiny = 1; | |
13012 | maxtiny = 1 << op->nbits; | |
13013 | } | |
13014 | else | |
13015 | { | |
13016 | mintiny = 0; | |
13017 | maxtiny = (1 << op->nbits) - 1; | |
13018 | } | |
13019 | } | |
13020 | else | |
13021 | { | |
13022 | mintiny = - (1 << (op->nbits - 1)); | |
13023 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13024 | } | |
13025 | ||
98aa84af | 13026 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13027 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13028 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13029 | |
13030 | if (op->pcrel) | |
13031 | { | |
13032 | addressT addr; | |
13033 | ||
13034 | /* We won't have the section when we are called from | |
13035 | mips_relax_frag. However, we will always have been called | |
13036 | from md_estimate_size_before_relax first. If this is a | |
13037 | branch to a different section, we mark it as such. If SEC is | |
13038 | NULL, and the frag is not marked, then it must be a branch to | |
13039 | the same section. */ | |
13040 | if (sec == NULL) | |
13041 | { | |
13042 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13043 | return 1; | |
13044 | } | |
13045 | else | |
13046 | { | |
98aa84af | 13047 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13048 | if (symsec != sec) |
13049 | { | |
13050 | fragp->fr_subtype = | |
13051 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13052 | ||
13053 | /* FIXME: We should support this, and let the linker | |
13054 | catch branches and loads that are out of range. */ | |
13055 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13056 | _("unsupported PC relative reference to different section")); | |
13057 | ||
13058 | return 1; | |
13059 | } | |
98aa84af AM |
13060 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13061 | /* Assume non-extended on the first relaxation pass. | |
13062 | The address we have calculated will be bogus if this is | |
13063 | a forward branch to another frag, as the forward frag | |
13064 | will have fr_address == 0. */ | |
13065 | return 0; | |
252b5132 RH |
13066 | } |
13067 | ||
13068 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13069 | the same section. If the relax_marker of the symbol fragment |
13070 | differs from the relax_marker of this fragment, we have not | |
13071 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13072 | in STRETCH in order to get a better estimate of the address. |
13073 | This particularly matters because of the shift bits. */ | |
13074 | if (stretch != 0 | |
98aa84af | 13075 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13076 | { |
13077 | fragS *f; | |
13078 | ||
13079 | /* Adjust stretch for any alignment frag. Note that if have | |
13080 | been expanding the earlier code, the symbol may be | |
13081 | defined in what appears to be an earlier frag. FIXME: | |
13082 | This doesn't handle the fr_subtype field, which specifies | |
13083 | a maximum number of bytes to skip when doing an | |
13084 | alignment. */ | |
98aa84af | 13085 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13086 | { |
13087 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13088 | { | |
13089 | if (stretch < 0) | |
13090 | stretch = - ((- stretch) | |
13091 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13092 | else | |
13093 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13094 | if (stretch == 0) | |
13095 | break; | |
13096 | } | |
13097 | } | |
13098 | if (f != NULL) | |
13099 | val += stretch; | |
13100 | } | |
13101 | ||
13102 | addr = fragp->fr_address + fragp->fr_fix; | |
13103 | ||
13104 | /* The base address rules are complicated. The base address of | |
13105 | a branch is the following instruction. The base address of a | |
13106 | PC relative load or add is the instruction itself, but if it | |
13107 | is in a delay slot (in which case it can not be extended) use | |
13108 | the address of the instruction whose delay slot it is in. */ | |
13109 | if (type == 'p' || type == 'q') | |
13110 | { | |
13111 | addr += 2; | |
13112 | ||
13113 | /* If we are currently assuming that this frag should be | |
13114 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13115 | higher. */ |
252b5132 RH |
13116 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13117 | addr += 2; | |
13118 | ||
13119 | /* Ignore the low bit in the target, since it will be set | |
13120 | for a text label. */ | |
13121 | if ((val & 1) != 0) | |
13122 | --val; | |
13123 | } | |
13124 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13125 | addr -= 4; | |
13126 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13127 | addr -= 2; | |
13128 | ||
13129 | val -= addr & ~ ((1 << op->shift) - 1); | |
13130 | ||
13131 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13132 | if (type == 'p' || type == 'q') | |
13133 | val /= 2; | |
13134 | ||
13135 | /* If any of the shifted bits are set, we must use an extended | |
13136 | opcode. If the address depends on the size of this | |
13137 | instruction, this can lead to a loop, so we arrange to always | |
13138 | use an extended opcode. We only check this when we are in | |
13139 | the main relaxation loop, when SEC is NULL. */ | |
13140 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13141 | { | |
13142 | fragp->fr_subtype = | |
13143 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13144 | return 1; | |
13145 | } | |
13146 | ||
13147 | /* If we are about to mark a frag as extended because the value | |
13148 | is precisely maxtiny + 1, then there is a chance of an | |
13149 | infinite loop as in the following code: | |
13150 | la $4,foo | |
13151 | .skip 1020 | |
13152 | .align 2 | |
13153 | foo: | |
13154 | In this case when the la is extended, foo is 0x3fc bytes | |
13155 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13156 | the la must be extended. To avoid this loop, we mark the | |
13157 | frag as extended if it was small, and is about to become | |
13158 | extended with a value of maxtiny + 1. */ | |
13159 | if (val == ((maxtiny + 1) << op->shift) | |
13160 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13161 | && sec == NULL) | |
13162 | { | |
13163 | fragp->fr_subtype = | |
13164 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13165 | return 1; | |
13166 | } | |
13167 | } | |
13168 | else if (symsec != absolute_section && sec != NULL) | |
13169 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13170 | ||
13171 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13172 | || val < (mintiny << op->shift) | |
13173 | || val > (maxtiny << op->shift)) | |
13174 | return 1; | |
13175 | else | |
13176 | return 0; | |
13177 | } | |
13178 | ||
4a6a3df4 AO |
13179 | /* Compute the length of a branch sequence, and adjust the |
13180 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13181 | worst-case length is computed, with UPDATE being used to indicate | |
13182 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13183 | branch is to be computed. */ | |
13184 | static int | |
17a2f251 | 13185 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13186 | { |
b34976b6 | 13187 | bfd_boolean toofar; |
4a6a3df4 AO |
13188 | int length; |
13189 | ||
13190 | if (fragp | |
13191 | && S_IS_DEFINED (fragp->fr_symbol) | |
13192 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13193 | { | |
13194 | addressT addr; | |
13195 | offsetT val; | |
13196 | ||
13197 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13198 | ||
13199 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13200 | ||
13201 | val -= addr; | |
13202 | ||
13203 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13204 | } | |
13205 | else if (fragp) | |
13206 | /* If the symbol is not defined or it's in a different segment, | |
13207 | assume the user knows what's going on and emit a short | |
13208 | branch. */ | |
b34976b6 | 13209 | toofar = FALSE; |
4a6a3df4 | 13210 | else |
b34976b6 | 13211 | toofar = TRUE; |
4a6a3df4 AO |
13212 | |
13213 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13214 | fragp->fr_subtype | |
af6ae2ad | 13215 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13216 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13217 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13218 | toofar); | |
13219 | ||
13220 | length = 4; | |
13221 | if (toofar) | |
13222 | { | |
13223 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13224 | length += 8; | |
13225 | ||
13226 | if (mips_pic != NO_PIC) | |
13227 | { | |
13228 | /* Additional space for PIC loading of target address. */ | |
13229 | length += 8; | |
13230 | if (mips_opts.isa == ISA_MIPS1) | |
13231 | /* Additional space for $at-stabilizing nop. */ | |
13232 | length += 4; | |
13233 | } | |
13234 | ||
13235 | /* If branch is conditional. */ | |
13236 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13237 | length += 8; | |
13238 | } | |
b34976b6 | 13239 | |
4a6a3df4 AO |
13240 | return length; |
13241 | } | |
13242 | ||
252b5132 RH |
13243 | /* Estimate the size of a frag before relaxing. Unless this is the |
13244 | mips16, we are not really relaxing here, and the final size is | |
13245 | encoded in the subtype information. For the mips16, we have to | |
13246 | decide whether we are using an extended opcode or not. */ | |
13247 | ||
252b5132 | 13248 | int |
17a2f251 | 13249 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13250 | { |
5919d012 | 13251 | int change; |
252b5132 | 13252 | |
4a6a3df4 AO |
13253 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13254 | { | |
13255 | ||
b34976b6 AM |
13256 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13257 | ||
4a6a3df4 AO |
13258 | return fragp->fr_var; |
13259 | } | |
13260 | ||
252b5132 | 13261 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13262 | /* We don't want to modify the EXTENDED bit here; it might get us |
13263 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13264 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13265 | |
13266 | if (mips_pic == NO_PIC) | |
5919d012 | 13267 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13268 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13269 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13270 | else if (mips_pic == VXWORKS_PIC) |
13271 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13272 | change = 0; | |
252b5132 RH |
13273 | else |
13274 | abort (); | |
13275 | ||
13276 | if (change) | |
13277 | { | |
4d7206a2 | 13278 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13279 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13280 | } |
4d7206a2 RS |
13281 | else |
13282 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13283 | } |
13284 | ||
13285 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13286 | should be converted into a reloc against a section. */ |
252b5132 RH |
13287 | |
13288 | int | |
17a2f251 | 13289 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13290 | { |
de7e6852 RS |
13291 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
13292 | about the format of the offset in the .o file. */ | |
252b5132 RH |
13293 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
13294 | return 0; | |
a161fe53 | 13295 | |
252b5132 RH |
13296 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13297 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13298 | return 0; | |
a161fe53 | 13299 | |
252b5132 RH |
13300 | if (fixp->fx_addsy == NULL) |
13301 | return 1; | |
a161fe53 | 13302 | |
de7e6852 RS |
13303 | /* If symbol SYM is in a mergeable section, relocations of the form |
13304 | SYM + 0 can usually be made section-relative. The mergeable data | |
13305 | is then identified by the section offset rather than by the symbol. | |
13306 | ||
13307 | However, if we're generating REL LO16 relocations, the offset is split | |
13308 | between the LO16 and parterning high part relocation. The linker will | |
13309 | need to recalculate the complete offset in order to correctly identify | |
13310 | the merge data. | |
13311 | ||
13312 | The linker has traditionally not looked for the parterning high part | |
13313 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13314 | placed anywhere. Rather than break backwards compatibility by changing | |
13315 | this, it seems better not to force the issue, and instead keep the | |
13316 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13317 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13318 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13319 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13320 | && HAVE_IN_PLACE_ADDENDS |
13321 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13322 | return 0; | |
13323 | ||
252b5132 | 13324 | #ifdef OBJ_ELF |
de7e6852 RS |
13325 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13326 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
13327 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
13328 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13329 | && fixp->fx_subsy == NULL) | |
13330 | return 0; | |
13331 | #endif | |
a161fe53 | 13332 | |
252b5132 RH |
13333 | return 1; |
13334 | } | |
13335 | ||
13336 | /* Translate internal representation of relocation info to BFD target | |
13337 | format. */ | |
13338 | ||
13339 | arelent ** | |
17a2f251 | 13340 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13341 | { |
13342 | static arelent *retval[4]; | |
13343 | arelent *reloc; | |
13344 | bfd_reloc_code_real_type code; | |
13345 | ||
4b0cff4e TS |
13346 | memset (retval, 0, sizeof(retval)); |
13347 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13348 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13349 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13350 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13351 | ||
bad36eac DJ |
13352 | if (fixp->fx_pcrel) |
13353 | { | |
13354 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13355 | ||
13356 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13357 | Relocations want only the symbol offset. */ | |
13358 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13359 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13360 | { | |
13361 | /* A gruesome hack which is a result of the gruesome gas | |
13362 | reloc handling. What's worse, for COFF (as opposed to | |
13363 | ECOFF), we might need yet another copy of reloc->address. | |
13364 | See bfd_install_relocation. */ | |
13365 | reloc->addend += reloc->address; | |
13366 | } | |
13367 | } | |
13368 | else | |
13369 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13370 | |
438c16b8 TS |
13371 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13372 | entry to be used in the relocation's section offset. */ | |
13373 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13374 | { |
13375 | reloc->address = reloc->addend; | |
13376 | reloc->addend = 0; | |
13377 | } | |
13378 | ||
252b5132 | 13379 | code = fixp->fx_r_type; |
252b5132 | 13380 | |
bad36eac | 13381 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13382 | if (reloc->howto == NULL) |
13383 | { | |
13384 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13385 | _("Can not represent %s relocation in this object file format"), | |
13386 | bfd_get_reloc_code_name (code)); | |
13387 | retval[0] = NULL; | |
13388 | } | |
13389 | ||
13390 | return retval; | |
13391 | } | |
13392 | ||
13393 | /* Relax a machine dependent frag. This returns the amount by which | |
13394 | the current size of the frag should change. */ | |
13395 | ||
13396 | int | |
17a2f251 | 13397 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13398 | { |
4a6a3df4 AO |
13399 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13400 | { | |
13401 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13402 | |
13403 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13404 | |
13405 | return fragp->fr_var - old_var; | |
13406 | } | |
13407 | ||
252b5132 RH |
13408 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13409 | return 0; | |
13410 | ||
c4e7957c | 13411 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13412 | { |
13413 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13414 | return 0; | |
13415 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13416 | return 2; | |
13417 | } | |
13418 | else | |
13419 | { | |
13420 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13421 | return 0; | |
13422 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13423 | return -2; | |
13424 | } | |
13425 | ||
13426 | return 0; | |
13427 | } | |
13428 | ||
13429 | /* Convert a machine dependent frag. */ | |
13430 | ||
13431 | void | |
17a2f251 | 13432 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13433 | { |
4a6a3df4 AO |
13434 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13435 | { | |
13436 | bfd_byte *buf; | |
13437 | unsigned long insn; | |
13438 | expressionS exp; | |
13439 | fixS *fixp; | |
b34976b6 | 13440 | |
4a6a3df4 AO |
13441 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13442 | ||
13443 | if (target_big_endian) | |
13444 | insn = bfd_getb32 (buf); | |
13445 | else | |
13446 | insn = bfd_getl32 (buf); | |
b34976b6 | 13447 | |
4a6a3df4 AO |
13448 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13449 | { | |
13450 | /* We generate a fixup instead of applying it right now | |
13451 | because, if there are linker relaxations, we're going to | |
13452 | need the relocations. */ | |
13453 | exp.X_op = O_symbol; | |
13454 | exp.X_add_symbol = fragp->fr_symbol; | |
13455 | exp.X_add_number = fragp->fr_offset; | |
13456 | ||
13457 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
bad36eac | 13458 | 4, &exp, 1, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13459 | fixp->fx_file = fragp->fr_file; |
13460 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13461 | |
2132e3a3 | 13462 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13463 | buf += 4; |
13464 | } | |
13465 | else | |
13466 | { | |
13467 | int i; | |
13468 | ||
13469 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13470 | _("relaxed out-of-range branch into a jump")); | |
13471 | ||
13472 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13473 | goto uncond; | |
13474 | ||
13475 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13476 | { | |
13477 | /* Reverse the branch. */ | |
13478 | switch ((insn >> 28) & 0xf) | |
13479 | { | |
13480 | case 4: | |
13481 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13482 | have the condition reversed by tweaking a single | |
13483 | bit, and their opcodes all have 0x4???????. */ | |
13484 | assert ((insn & 0xf1000000) == 0x41000000); | |
13485 | insn ^= 0x00010000; | |
13486 | break; | |
13487 | ||
13488 | case 0: | |
13489 | /* bltz 0x04000000 bgez 0x04010000 | |
13490 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13491 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13492 | insn ^= 0x00010000; | |
13493 | break; | |
b34976b6 | 13494 | |
4a6a3df4 AO |
13495 | case 1: |
13496 | /* beq 0x10000000 bne 0x14000000 | |
13497 | blez 0x18000000 bgtz 0x1c000000 */ | |
13498 | insn ^= 0x04000000; | |
13499 | break; | |
13500 | ||
13501 | default: | |
13502 | abort (); | |
13503 | } | |
13504 | } | |
13505 | ||
13506 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13507 | { | |
13508 | /* Clear the and-link bit. */ | |
13509 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13510 | ||
13511 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13512 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13513 | insn &= ~0x00100000; | |
13514 | } | |
13515 | ||
13516 | /* Branch over the branch (if the branch was likely) or the | |
13517 | full jump (not likely case). Compute the offset from the | |
13518 | current instruction to branch to. */ | |
13519 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13520 | i = 16; | |
13521 | else | |
13522 | { | |
13523 | /* How many bytes in instructions we've already emitted? */ | |
13524 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13525 | /* How many bytes in instructions from here to the end? */ | |
13526 | i = fragp->fr_var - i; | |
13527 | } | |
13528 | /* Convert to instruction count. */ | |
13529 | i >>= 2; | |
13530 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13531 | i--; |
4a6a3df4 AO |
13532 | insn |= i; |
13533 | /* Branch over the jump. */ | |
2132e3a3 | 13534 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13535 | buf += 4; |
13536 | ||
13537 | /* Nop */ | |
2132e3a3 | 13538 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13539 | buf += 4; |
13540 | ||
13541 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13542 | { | |
13543 | /* beql $0, $0, 2f */ | |
13544 | insn = 0x50000000; | |
13545 | /* Compute the PC offset from the current instruction to | |
13546 | the end of the variable frag. */ | |
13547 | /* How many bytes in instructions we've already emitted? */ | |
13548 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13549 | /* How many bytes in instructions from here to the end? */ | |
13550 | i = fragp->fr_var - i; | |
13551 | /* Convert to instruction count. */ | |
13552 | i >>= 2; | |
13553 | /* Don't decrement i, because we want to branch over the | |
13554 | delay slot. */ | |
13555 | ||
13556 | insn |= i; | |
2132e3a3 | 13557 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13558 | buf += 4; |
13559 | ||
2132e3a3 | 13560 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13561 | buf += 4; |
13562 | } | |
13563 | ||
13564 | uncond: | |
13565 | if (mips_pic == NO_PIC) | |
13566 | { | |
13567 | /* j or jal. */ | |
13568 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13569 | ? 0x0c000000 : 0x08000000); | |
13570 | exp.X_op = O_symbol; | |
13571 | exp.X_add_symbol = fragp->fr_symbol; | |
13572 | exp.X_add_number = fragp->fr_offset; | |
13573 | ||
13574 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13575 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13576 | fixp->fx_file = fragp->fr_file; | |
13577 | fixp->fx_line = fragp->fr_line; | |
13578 | ||
2132e3a3 | 13579 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13580 | buf += 4; |
13581 | } | |
13582 | else | |
13583 | { | |
13584 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13585 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13586 | exp.X_op = O_symbol; | |
13587 | exp.X_add_symbol = fragp->fr_symbol; | |
13588 | exp.X_add_number = fragp->fr_offset; | |
13589 | ||
13590 | if (fragp->fr_offset) | |
13591 | { | |
13592 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13593 | exp.X_add_number = 0; | |
13594 | } | |
13595 | ||
13596 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13597 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13598 | fixp->fx_file = fragp->fr_file; | |
13599 | fixp->fx_line = fragp->fr_line; | |
13600 | ||
2132e3a3 | 13601 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13602 | buf += 4; |
b34976b6 | 13603 | |
4a6a3df4 AO |
13604 | if (mips_opts.isa == ISA_MIPS1) |
13605 | { | |
13606 | /* nop */ | |
2132e3a3 | 13607 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13608 | buf += 4; |
13609 | } | |
13610 | ||
13611 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13612 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13613 | ||
13614 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13615 | 4, &exp, 0, BFD_RELOC_LO16); | |
13616 | fixp->fx_file = fragp->fr_file; | |
13617 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13618 | |
2132e3a3 | 13619 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13620 | buf += 4; |
13621 | ||
13622 | /* j(al)r $at. */ | |
13623 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13624 | insn = 0x0020f809; | |
13625 | else | |
13626 | insn = 0x00200008; | |
13627 | ||
2132e3a3 | 13628 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13629 | buf += 4; |
13630 | } | |
13631 | } | |
13632 | ||
13633 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13634 | + fragp->fr_fix + fragp->fr_var); | |
13635 | ||
13636 | fragp->fr_fix += fragp->fr_var; | |
13637 | ||
13638 | return; | |
13639 | } | |
13640 | ||
252b5132 RH |
13641 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13642 | { | |
13643 | int type; | |
13644 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13645 | bfd_boolean small, ext; |
252b5132 RH |
13646 | offsetT val; |
13647 | bfd_byte *buf; | |
13648 | unsigned long insn; | |
b34976b6 | 13649 | bfd_boolean use_extend; |
252b5132 RH |
13650 | unsigned short extend; |
13651 | ||
13652 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13653 | op = mips16_immed_operands; | |
13654 | while (op->type != type) | |
13655 | ++op; | |
13656 | ||
13657 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13658 | { | |
b34976b6 AM |
13659 | small = FALSE; |
13660 | ext = TRUE; | |
252b5132 RH |
13661 | } |
13662 | else | |
13663 | { | |
b34976b6 AM |
13664 | small = TRUE; |
13665 | ext = FALSE; | |
252b5132 RH |
13666 | } |
13667 | ||
6386f3a7 | 13668 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13669 | val = S_GET_VALUE (fragp->fr_symbol); |
13670 | if (op->pcrel) | |
13671 | { | |
13672 | addressT addr; | |
13673 | ||
13674 | addr = fragp->fr_address + fragp->fr_fix; | |
13675 | ||
13676 | /* The rules for the base address of a PC relative reloc are | |
13677 | complicated; see mips16_extended_frag. */ | |
13678 | if (type == 'p' || type == 'q') | |
13679 | { | |
13680 | addr += 2; | |
13681 | if (ext) | |
13682 | addr += 2; | |
13683 | /* Ignore the low bit in the target, since it will be | |
13684 | set for a text label. */ | |
13685 | if ((val & 1) != 0) | |
13686 | --val; | |
13687 | } | |
13688 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13689 | addr -= 4; | |
13690 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13691 | addr -= 2; | |
13692 | ||
13693 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13694 | val -= addr; | |
13695 | ||
13696 | /* Make sure the section winds up with the alignment we have | |
13697 | assumed. */ | |
13698 | if (op->shift > 0) | |
13699 | record_alignment (asec, op->shift); | |
13700 | } | |
13701 | ||
13702 | if (ext | |
13703 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13704 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13705 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13706 | _("extended instruction in delay slot")); | |
13707 | ||
13708 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13709 | ||
13710 | if (target_big_endian) | |
13711 | insn = bfd_getb16 (buf); | |
13712 | else | |
13713 | insn = bfd_getl16 (buf); | |
13714 | ||
13715 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13716 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13717 | small, ext, &insn, &use_extend, &extend); | |
13718 | ||
13719 | if (use_extend) | |
13720 | { | |
2132e3a3 | 13721 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13722 | fragp->fr_fix += 2; |
13723 | buf += 2; | |
13724 | } | |
13725 | ||
2132e3a3 | 13726 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13727 | fragp->fr_fix += 2; |
13728 | buf += 2; | |
13729 | } | |
13730 | else | |
13731 | { | |
4d7206a2 RS |
13732 | int first, second; |
13733 | fixS *fixp; | |
252b5132 | 13734 | |
4d7206a2 RS |
13735 | first = RELAX_FIRST (fragp->fr_subtype); |
13736 | second = RELAX_SECOND (fragp->fr_subtype); | |
13737 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13738 | |
584892a6 RS |
13739 | /* Possibly emit a warning if we've chosen the longer option. */ |
13740 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13741 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13742 | { | |
13743 | const char *msg = macro_warning (fragp->fr_subtype); | |
13744 | if (msg != 0) | |
13745 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13746 | } | |
13747 | ||
4d7206a2 RS |
13748 | /* Go through all the fixups for the first sequence. Disable them |
13749 | (by marking them as done) if we're going to use the second | |
13750 | sequence instead. */ | |
13751 | while (fixp | |
13752 | && fixp->fx_frag == fragp | |
13753 | && fixp->fx_where < fragp->fr_fix - second) | |
13754 | { | |
13755 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13756 | fixp->fx_done = 1; | |
13757 | fixp = fixp->fx_next; | |
13758 | } | |
252b5132 | 13759 | |
4d7206a2 RS |
13760 | /* Go through the fixups for the second sequence. Disable them if |
13761 | we're going to use the first sequence, otherwise adjust their | |
13762 | addresses to account for the relaxation. */ | |
13763 | while (fixp && fixp->fx_frag == fragp) | |
13764 | { | |
13765 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13766 | fixp->fx_where -= first; | |
13767 | else | |
13768 | fixp->fx_done = 1; | |
13769 | fixp = fixp->fx_next; | |
13770 | } | |
13771 | ||
13772 | /* Now modify the frag contents. */ | |
13773 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13774 | { | |
13775 | char *start; | |
13776 | ||
13777 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13778 | memmove (start, start + first, second); | |
13779 | fragp->fr_fix -= first; | |
13780 | } | |
13781 | else | |
13782 | fragp->fr_fix -= second; | |
252b5132 RH |
13783 | } |
13784 | } | |
13785 | ||
13786 | #ifdef OBJ_ELF | |
13787 | ||
13788 | /* This function is called after the relocs have been generated. | |
13789 | We've been storing mips16 text labels as odd. Here we convert them | |
13790 | back to even for the convenience of the debugger. */ | |
13791 | ||
13792 | void | |
17a2f251 | 13793 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13794 | { |
13795 | asymbol **syms; | |
13796 | unsigned int count, i; | |
13797 | ||
13798 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13799 | return; | |
13800 | ||
13801 | syms = bfd_get_outsymbols (stdoutput); | |
13802 | count = bfd_get_symcount (stdoutput); | |
13803 | for (i = 0; i < count; i++, syms++) | |
13804 | { | |
13805 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13806 | && ((*syms)->value & 1) != 0) | |
13807 | { | |
13808 | (*syms)->value &= ~1; | |
13809 | /* If the symbol has an odd size, it was probably computed | |
13810 | incorrectly, so adjust that as well. */ | |
13811 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13812 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13813 | } | |
13814 | } | |
13815 | } | |
13816 | ||
13817 | #endif | |
13818 | ||
13819 | /* This function is called whenever a label is defined. It is used | |
13820 | when handling branch delays; if a branch has a label, we assume we | |
13821 | can not move it. */ | |
13822 | ||
13823 | void | |
17a2f251 | 13824 | mips_define_label (symbolS *sym) |
252b5132 RH |
13825 | { |
13826 | struct insn_label_list *l; | |
13827 | ||
13828 | if (free_insn_labels == NULL) | |
13829 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13830 | else | |
13831 | { | |
13832 | l = free_insn_labels; | |
13833 | free_insn_labels = l->next; | |
13834 | } | |
13835 | ||
13836 | l->label = sym; | |
13837 | l->next = insn_labels; | |
13838 | insn_labels = l; | |
07a53e5c RH |
13839 | |
13840 | #ifdef OBJ_ELF | |
13841 | dwarf2_emit_label (sym); | |
13842 | #endif | |
252b5132 RH |
13843 | } |
13844 | \f | |
13845 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13846 | ||
13847 | /* Some special processing for a MIPS ELF file. */ | |
13848 | ||
13849 | void | |
17a2f251 | 13850 | mips_elf_final_processing (void) |
252b5132 RH |
13851 | { |
13852 | /* Write out the register information. */ | |
316f5878 | 13853 | if (mips_abi != N64_ABI) |
252b5132 RH |
13854 | { |
13855 | Elf32_RegInfo s; | |
13856 | ||
13857 | s.ri_gprmask = mips_gprmask; | |
13858 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13859 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13860 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13861 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13862 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13863 | ||
13864 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13865 | ((Elf32_External_RegInfo *) | |
13866 | mips_regmask_frag)); | |
13867 | } | |
13868 | else | |
13869 | { | |
13870 | Elf64_Internal_RegInfo s; | |
13871 | ||
13872 | s.ri_gprmask = mips_gprmask; | |
13873 | s.ri_pad = 0; | |
13874 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13875 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13876 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13877 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13878 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13879 | ||
13880 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13881 | ((Elf64_External_RegInfo *) | |
13882 | mips_regmask_frag)); | |
13883 | } | |
13884 | ||
13885 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13886 | sort of BFD interface for this. */ | |
13887 | if (mips_any_noreorder) | |
13888 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13889 | if (mips_pic != NO_PIC) | |
143d77c5 | 13890 | { |
252b5132 | 13891 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13892 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13893 | } | |
13894 | if (mips_abicalls) | |
13895 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13896 | |
98d3f06f | 13897 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
13898 | /* We may need to define a new flag for DSP ASE, and set this flag when |
13899 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
13900 | /* We may need to define a new flag for MT ASE, and set this flag when |
13901 | file_ase_mt is true. */ | |
a4672219 TS |
13902 | if (file_ase_mips16) |
13903 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13904 | #if 0 /* XXX FIXME */ |
13905 | if (file_ase_mips3d) | |
13906 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13907 | #endif | |
deec1734 CD |
13908 | if (file_ase_mdmx) |
13909 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13910 | |
bdaaa2e1 | 13911 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13912 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13913 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13914 | else if (mips_abi == O64_ABI) |
252b5132 | 13915 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13916 | else if (mips_abi == EABI_ABI) |
252b5132 | 13917 | { |
316f5878 | 13918 | if (!file_mips_gp32) |
252b5132 RH |
13919 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13920 | else | |
13921 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13922 | } | |
316f5878 | 13923 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13924 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13925 | ||
c9914766 | 13926 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13927 | |
13928 | if (mips_32bitmode) | |
13929 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13930 | } | |
13931 | ||
13932 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13933 | \f | |
beae10d5 | 13934 | typedef struct proc { |
9b2f1d35 EC |
13935 | symbolS *func_sym; |
13936 | symbolS *func_end_sym; | |
beae10d5 KH |
13937 | unsigned long reg_mask; |
13938 | unsigned long reg_offset; | |
13939 | unsigned long fpreg_mask; | |
13940 | unsigned long fpreg_offset; | |
13941 | unsigned long frame_offset; | |
13942 | unsigned long frame_reg; | |
13943 | unsigned long pc_reg; | |
13944 | } procS; | |
252b5132 RH |
13945 | |
13946 | static procS cur_proc; | |
13947 | static procS *cur_proc_ptr; | |
13948 | static int numprocs; | |
13949 | ||
0a9ef439 | 13950 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13951 | |
0a9ef439 | 13952 | void |
17a2f251 | 13953 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13954 | { |
0a9ef439 RH |
13955 | if (fragp->fr_type != rs_align_code) |
13956 | return; | |
13957 | ||
13958 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13959 | { |
13960 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13961 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13962 | ||
0a9ef439 RH |
13963 | int bytes; |
13964 | char *p; | |
a19d8eb0 | 13965 | |
0a9ef439 RH |
13966 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13967 | p = fragp->fr_literal + fragp->fr_fix; | |
13968 | ||
13969 | if (bytes & 1) | |
13970 | { | |
13971 | *p++ = 0; | |
f9419b05 | 13972 | fragp->fr_fix++; |
0a9ef439 RH |
13973 | } |
13974 | ||
13975 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13976 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13977 | } |
13978 | ||
0a9ef439 | 13979 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13980 | } |
13981 | ||
252b5132 | 13982 | static void |
17a2f251 | 13983 | md_obj_begin (void) |
252b5132 RH |
13984 | { |
13985 | } | |
13986 | ||
13987 | static void | |
17a2f251 | 13988 | md_obj_end (void) |
252b5132 RH |
13989 | { |
13990 | /* check for premature end, nesting errors, etc */ | |
13991 | if (cur_proc_ptr) | |
9a41af64 | 13992 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13993 | } |
13994 | ||
13995 | static long | |
17a2f251 | 13996 | get_number (void) |
252b5132 RH |
13997 | { |
13998 | int negative = 0; | |
13999 | long val = 0; | |
14000 | ||
14001 | if (*input_line_pointer == '-') | |
14002 | { | |
14003 | ++input_line_pointer; | |
14004 | negative = 1; | |
14005 | } | |
3882b010 | 14006 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14007 | as_bad (_("expected simple number")); |
252b5132 RH |
14008 | if (input_line_pointer[0] == '0') |
14009 | { | |
14010 | if (input_line_pointer[1] == 'x') | |
14011 | { | |
14012 | input_line_pointer += 2; | |
3882b010 | 14013 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14014 | { |
14015 | val <<= 4; | |
14016 | val |= hex_value (*input_line_pointer++); | |
14017 | } | |
14018 | return negative ? -val : val; | |
14019 | } | |
14020 | else | |
14021 | { | |
14022 | ++input_line_pointer; | |
3882b010 | 14023 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14024 | { |
14025 | val <<= 3; | |
14026 | val |= *input_line_pointer++ - '0'; | |
14027 | } | |
14028 | return negative ? -val : val; | |
14029 | } | |
14030 | } | |
3882b010 | 14031 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14032 | { |
14033 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14034 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14035 | as_warn (_("invalid number")); |
252b5132 RH |
14036 | return -1; |
14037 | } | |
3882b010 | 14038 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14039 | { |
14040 | val *= 10; | |
14041 | val += *input_line_pointer++ - '0'; | |
14042 | } | |
14043 | return negative ? -val : val; | |
14044 | } | |
14045 | ||
14046 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14047 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14048 | case .file implies DWARF-2. */ | |
14049 | ||
14050 | static void | |
17a2f251 | 14051 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14052 | { |
ecb4347a DJ |
14053 | static int first_file_directive = 0; |
14054 | ||
c5dd6aab DJ |
14055 | if (ECOFF_DEBUGGING) |
14056 | { | |
14057 | get_number (); | |
14058 | s_app_file (0); | |
14059 | } | |
14060 | else | |
ecb4347a DJ |
14061 | { |
14062 | char *filename; | |
14063 | ||
14064 | filename = dwarf2_directive_file (0); | |
14065 | ||
14066 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14067 | directive even for stabs output. Make sure that this | |
14068 | ".file" is handled. Note that you need a version of GCC | |
14069 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14070 | if (filename != NULL && ! first_file_directive) | |
14071 | { | |
14072 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14073 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14074 | } |
14075 | first_file_directive = 1; | |
14076 | } | |
c5dd6aab DJ |
14077 | } |
14078 | ||
14079 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14080 | |
14081 | static void | |
17a2f251 | 14082 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14083 | { |
c5dd6aab DJ |
14084 | if (!ECOFF_DEBUGGING) |
14085 | dwarf2_directive_loc (0); | |
252b5132 RH |
14086 | } |
14087 | ||
252b5132 RH |
14088 | /* The .end directive. */ |
14089 | ||
14090 | static void | |
17a2f251 | 14091 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14092 | { |
14093 | symbolS *p; | |
252b5132 | 14094 | |
7a621144 DJ |
14095 | /* Following functions need their own .frame and .cprestore directives. */ |
14096 | mips_frame_reg_valid = 0; | |
14097 | mips_cprestore_valid = 0; | |
14098 | ||
252b5132 RH |
14099 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14100 | { | |
14101 | p = get_symbol (); | |
14102 | demand_empty_rest_of_line (); | |
14103 | } | |
14104 | else | |
14105 | p = NULL; | |
14106 | ||
14949570 | 14107 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14108 | as_warn (_(".end not in text section")); |
14109 | ||
14110 | if (!cur_proc_ptr) | |
14111 | { | |
14112 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14113 | demand_empty_rest_of_line (); | |
14114 | return; | |
14115 | } | |
14116 | ||
14117 | if (p != NULL) | |
14118 | { | |
14119 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14120 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14121 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14122 | |
14123 | if (debug_type == DEBUG_STABS) | |
14124 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14125 | S_GET_NAME (p)); | |
252b5132 RH |
14126 | } |
14127 | else | |
14128 | as_warn (_(".end directive missing or unknown symbol")); | |
14129 | ||
2132e3a3 | 14130 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14131 | /* Create an expression to calculate the size of the function. */ |
14132 | if (p && cur_proc_ptr) | |
14133 | { | |
14134 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14135 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14136 | ||
14137 | obj->size = exp; | |
14138 | exp->X_op = O_subtract; | |
14139 | exp->X_add_symbol = symbol_temp_new_now (); | |
14140 | exp->X_op_symbol = p; | |
14141 | exp->X_add_number = 0; | |
14142 | ||
14143 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14144 | } | |
14145 | ||
ecb4347a | 14146 | /* Generate a .pdr section. */ |
dcd410fe RO |
14147 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14148 | && mips_flag_pdr) | |
ecb4347a DJ |
14149 | { |
14150 | segT saved_seg = now_seg; | |
14151 | subsegT saved_subseg = now_subseg; | |
14152 | valueT dot; | |
14153 | expressionS exp; | |
14154 | char *fragp; | |
252b5132 | 14155 | |
ecb4347a | 14156 | dot = frag_now_fix (); |
252b5132 RH |
14157 | |
14158 | #ifdef md_flush_pending_output | |
ecb4347a | 14159 | md_flush_pending_output (); |
252b5132 RH |
14160 | #endif |
14161 | ||
ecb4347a DJ |
14162 | assert (pdr_seg); |
14163 | subseg_set (pdr_seg, 0); | |
252b5132 | 14164 | |
ecb4347a DJ |
14165 | /* Write the symbol. */ |
14166 | exp.X_op = O_symbol; | |
14167 | exp.X_add_symbol = p; | |
14168 | exp.X_add_number = 0; | |
14169 | emit_expr (&exp, 4); | |
252b5132 | 14170 | |
ecb4347a | 14171 | fragp = frag_more (7 * 4); |
252b5132 | 14172 | |
17a2f251 TS |
14173 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14174 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14175 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14176 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14177 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14178 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14179 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14180 | |
ecb4347a DJ |
14181 | subseg_set (saved_seg, saved_subseg); |
14182 | } | |
14183 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14184 | |
14185 | cur_proc_ptr = NULL; | |
14186 | } | |
14187 | ||
14188 | /* The .aent and .ent directives. */ | |
14189 | ||
14190 | static void | |
17a2f251 | 14191 | s_mips_ent (int aent) |
252b5132 | 14192 | { |
252b5132 | 14193 | symbolS *symbolP; |
252b5132 RH |
14194 | |
14195 | symbolP = get_symbol (); | |
14196 | if (*input_line_pointer == ',') | |
f9419b05 | 14197 | ++input_line_pointer; |
252b5132 | 14198 | SKIP_WHITESPACE (); |
3882b010 | 14199 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14200 | || *input_line_pointer == '-') |
874e8986 | 14201 | get_number (); |
252b5132 | 14202 | |
14949570 | 14203 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14204 | as_warn (_(".ent or .aent not in text section.")); |
14205 | ||
14206 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14207 | as_warn (_("missing .end")); |
252b5132 RH |
14208 | |
14209 | if (!aent) | |
14210 | { | |
7a621144 DJ |
14211 | /* This function needs its own .frame and .cprestore directives. */ |
14212 | mips_frame_reg_valid = 0; | |
14213 | mips_cprestore_valid = 0; | |
14214 | ||
252b5132 RH |
14215 | cur_proc_ptr = &cur_proc; |
14216 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14217 | ||
9b2f1d35 | 14218 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14219 | |
49309057 | 14220 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14221 | |
f9419b05 | 14222 | ++numprocs; |
ecb4347a DJ |
14223 | |
14224 | if (debug_type == DEBUG_STABS) | |
14225 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14226 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14227 | } |
14228 | ||
14229 | demand_empty_rest_of_line (); | |
14230 | } | |
14231 | ||
14232 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14233 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14234 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14235 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14236 | symbol table (in the mdebug section). */ |
14237 | ||
14238 | static void | |
17a2f251 | 14239 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14240 | { |
ecb4347a DJ |
14241 | #ifdef OBJ_ELF |
14242 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14243 | { | |
14244 | long val; | |
252b5132 | 14245 | |
ecb4347a DJ |
14246 | if (cur_proc_ptr == (procS *) NULL) |
14247 | { | |
14248 | as_warn (_(".frame outside of .ent")); | |
14249 | demand_empty_rest_of_line (); | |
14250 | return; | |
14251 | } | |
252b5132 | 14252 | |
ecb4347a DJ |
14253 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14254 | ||
14255 | SKIP_WHITESPACE (); | |
14256 | if (*input_line_pointer++ != ',' | |
14257 | || get_absolute_expression_and_terminator (&val) != ',') | |
14258 | { | |
14259 | as_warn (_("Bad .frame directive")); | |
14260 | --input_line_pointer; | |
14261 | demand_empty_rest_of_line (); | |
14262 | return; | |
14263 | } | |
252b5132 | 14264 | |
ecb4347a DJ |
14265 | cur_proc_ptr->frame_offset = val; |
14266 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14267 | |
252b5132 | 14268 | demand_empty_rest_of_line (); |
252b5132 | 14269 | } |
ecb4347a DJ |
14270 | else |
14271 | #endif /* OBJ_ELF */ | |
14272 | s_ignore (ignore); | |
252b5132 RH |
14273 | } |
14274 | ||
bdaaa2e1 KH |
14275 | /* The .fmask and .mask directives. If the mdebug section is present |
14276 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14277 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14278 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14279 | make reference to the ecoff symbol table (in the mdebug section). */ |
14280 | ||
14281 | static void | |
17a2f251 | 14282 | s_mips_mask (int reg_type) |
252b5132 | 14283 | { |
ecb4347a DJ |
14284 | #ifdef OBJ_ELF |
14285 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14286 | { |
ecb4347a | 14287 | long mask, off; |
252b5132 | 14288 | |
ecb4347a DJ |
14289 | if (cur_proc_ptr == (procS *) NULL) |
14290 | { | |
14291 | as_warn (_(".mask/.fmask outside of .ent")); | |
14292 | demand_empty_rest_of_line (); | |
14293 | return; | |
14294 | } | |
252b5132 | 14295 | |
ecb4347a DJ |
14296 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14297 | { | |
14298 | as_warn (_("Bad .mask/.fmask directive")); | |
14299 | --input_line_pointer; | |
14300 | demand_empty_rest_of_line (); | |
14301 | return; | |
14302 | } | |
252b5132 | 14303 | |
ecb4347a DJ |
14304 | off = get_absolute_expression (); |
14305 | ||
14306 | if (reg_type == 'F') | |
14307 | { | |
14308 | cur_proc_ptr->fpreg_mask = mask; | |
14309 | cur_proc_ptr->fpreg_offset = off; | |
14310 | } | |
14311 | else | |
14312 | { | |
14313 | cur_proc_ptr->reg_mask = mask; | |
14314 | cur_proc_ptr->reg_offset = off; | |
14315 | } | |
14316 | ||
14317 | demand_empty_rest_of_line (); | |
252b5132 RH |
14318 | } |
14319 | else | |
ecb4347a DJ |
14320 | #endif /* OBJ_ELF */ |
14321 | s_ignore (reg_type); | |
252b5132 RH |
14322 | } |
14323 | ||
316f5878 RS |
14324 | /* A table describing all the processors gas knows about. Names are |
14325 | matched in the order listed. | |
e7af610e | 14326 | |
316f5878 RS |
14327 | To ease comparison, please keep this table in the same order as |
14328 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14329 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14330 | { | |
316f5878 RS |
14331 | /* Entries for generic ISAs */ |
14332 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14333 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14334 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14335 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14336 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14337 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14338 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14339 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14340 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14341 | |
14342 | /* MIPS I */ | |
14343 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14344 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14345 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14346 | ||
14347 | /* MIPS II */ | |
14348 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14349 | ||
14350 | /* MIPS III */ | |
14351 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14352 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14353 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14354 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14355 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14356 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14357 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14358 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14359 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14360 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14361 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14362 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14363 | ||
14364 | /* MIPS IV */ | |
14365 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14366 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14367 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14368 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14369 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14370 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14371 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14372 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14373 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14374 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14375 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 14376 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 14377 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
14378 | |
14379 | /* MIPS 32 */ | |
fef14a42 | 14380 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14381 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14382 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14383 | |
32b26a03 MR |
14384 | /* MIPS32 Release 2 */ |
14385 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14386 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14387 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14388 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14389 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14390 | ||
316f5878 RS |
14391 | /* MIPS 64 */ |
14392 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
ff324200 | 14393 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, |
316f5878 | 14394 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
e7af610e | 14395 | |
c7a23324 | 14396 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14397 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14398 | |
316f5878 RS |
14399 | /* End marker */ |
14400 | { NULL, 0, 0, 0 } | |
14401 | }; | |
e7af610e | 14402 | |
84ea6cf2 | 14403 | |
316f5878 RS |
14404 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14405 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14406 | |
316f5878 | 14407 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14408 | |
b34976b6 | 14409 | static bfd_boolean |
17a2f251 | 14410 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14411 | { |
14412 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14413 | given++, canonical++; | |
14414 | ||
14415 | return ((*given == 0 && *canonical == 0) | |
14416 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14417 | } | |
14418 | ||
14419 | ||
14420 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14421 | CPU name. We've traditionally allowed a lot of variation here. | |
14422 | ||
14423 | Note: this function is shared between GCC and GAS. */ | |
14424 | ||
b34976b6 | 14425 | static bfd_boolean |
17a2f251 | 14426 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14427 | { |
14428 | /* First see if the name matches exactly, or with a final "000" | |
14429 | turned into "k". */ | |
14430 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14431 | return TRUE; |
316f5878 RS |
14432 | |
14433 | /* If not, try comparing based on numerical designation alone. | |
14434 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14435 | if (TOLOWER (*given) == 'r') | |
14436 | given++; | |
14437 | if (!ISDIGIT (*given)) | |
b34976b6 | 14438 | return FALSE; |
316f5878 RS |
14439 | |
14440 | /* Skip over some well-known prefixes in the canonical name, | |
14441 | hoping to find a number there too. */ | |
14442 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14443 | canonical += 2; | |
14444 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14445 | canonical += 2; | |
14446 | else if (TOLOWER (canonical[0]) == 'r') | |
14447 | canonical += 1; | |
14448 | ||
14449 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14450 | } | |
14451 | ||
14452 | ||
14453 | /* Parse an option that takes the name of a processor as its argument. | |
14454 | OPTION is the name of the option and CPU_STRING is the argument. | |
14455 | Return the corresponding processor enumeration if the CPU_STRING is | |
14456 | recognized, otherwise report an error and return null. | |
14457 | ||
14458 | A similar function exists in GCC. */ | |
e7af610e NC |
14459 | |
14460 | static const struct mips_cpu_info * | |
17a2f251 | 14461 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14462 | { |
316f5878 | 14463 | const struct mips_cpu_info *p; |
e7af610e | 14464 | |
316f5878 RS |
14465 | /* 'from-abi' selects the most compatible architecture for the given |
14466 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14467 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14468 | version. Look first at the -mgp options, if given, otherwise base | |
14469 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14470 | |
316f5878 RS |
14471 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14472 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14473 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14474 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14475 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14476 | { | |
14477 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14478 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14479 | ||
14480 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14481 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14482 | ||
14483 | if (file_mips_gp32 >= 0) | |
14484 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14485 | ||
14486 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14487 | ? ISA_MIPS3 | |
14488 | : ISA_MIPS1); | |
14489 | } | |
14490 | ||
14491 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14492 | if (strcasecmp (cpu_string, "default") == 0) | |
14493 | return 0; | |
14494 | ||
14495 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14496 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14497 | return p; | |
14498 | ||
14499 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14500 | return 0; | |
e7af610e NC |
14501 | } |
14502 | ||
316f5878 RS |
14503 | /* Return the canonical processor information for ISA (a member of the |
14504 | ISA_MIPS* enumeration). */ | |
14505 | ||
e7af610e | 14506 | static const struct mips_cpu_info * |
17a2f251 | 14507 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14508 | { |
14509 | int i; | |
14510 | ||
14511 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14512 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14513 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14514 | return (&mips_cpu_info_table[i]); |
14515 | ||
e972090a | 14516 | return NULL; |
e7af610e | 14517 | } |
fef14a42 TS |
14518 | |
14519 | static const struct mips_cpu_info * | |
17a2f251 | 14520 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14521 | { |
14522 | int i; | |
14523 | ||
14524 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14525 | if (arch == mips_cpu_info_table[i].cpu) | |
14526 | return (&mips_cpu_info_table[i]); | |
14527 | ||
14528 | return NULL; | |
14529 | } | |
316f5878 RS |
14530 | \f |
14531 | static void | |
17a2f251 | 14532 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14533 | { |
14534 | if (*first_p) | |
14535 | { | |
14536 | fprintf (stream, "%24s", ""); | |
14537 | *col_p = 24; | |
14538 | } | |
14539 | else | |
14540 | { | |
14541 | fprintf (stream, ", "); | |
14542 | *col_p += 2; | |
14543 | } | |
e7af610e | 14544 | |
316f5878 RS |
14545 | if (*col_p + strlen (string) > 72) |
14546 | { | |
14547 | fprintf (stream, "\n%24s", ""); | |
14548 | *col_p = 24; | |
14549 | } | |
14550 | ||
14551 | fprintf (stream, "%s", string); | |
14552 | *col_p += strlen (string); | |
14553 | ||
14554 | *first_p = 0; | |
14555 | } | |
14556 | ||
14557 | void | |
17a2f251 | 14558 | md_show_usage (FILE *stream) |
e7af610e | 14559 | { |
316f5878 RS |
14560 | int column, first; |
14561 | size_t i; | |
14562 | ||
14563 | fprintf (stream, _("\ | |
14564 | MIPS options:\n\ | |
316f5878 RS |
14565 | -EB generate big endian output\n\ |
14566 | -EL generate little endian output\n\ | |
14567 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14568 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14569 | implicitly with the gp register [default 8]\n")); | |
14570 | fprintf (stream, _("\ | |
14571 | -mips1 generate MIPS ISA I instructions\n\ | |
14572 | -mips2 generate MIPS ISA II instructions\n\ | |
14573 | -mips3 generate MIPS ISA III instructions\n\ | |
14574 | -mips4 generate MIPS ISA IV instructions\n\ | |
14575 | -mips5 generate MIPS ISA V instructions\n\ | |
14576 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14577 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14578 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14579 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14580 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14581 | ||
14582 | first = 1; | |
e7af610e NC |
14583 | |
14584 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14585 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14586 | show (stream, "from-abi", &column, &first); | |
14587 | fputc ('\n', stream); | |
e7af610e | 14588 | |
316f5878 RS |
14589 | fprintf (stream, _("\ |
14590 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14591 | -no-mCPU don't generate code specific to CPU.\n\ | |
14592 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14593 | ||
14594 | first = 1; | |
14595 | ||
14596 | show (stream, "3900", &column, &first); | |
14597 | show (stream, "4010", &column, &first); | |
14598 | show (stream, "4100", &column, &first); | |
14599 | show (stream, "4650", &column, &first); | |
14600 | fputc ('\n', stream); | |
14601 | ||
14602 | fprintf (stream, _("\ | |
14603 | -mips16 generate mips16 instructions\n\ | |
14604 | -no-mips16 do not generate mips16 instructions\n")); | |
14605 | fprintf (stream, _("\ | |
e16bfa71 TS |
14606 | -msmartmips generate smartmips instructions\n\ |
14607 | -mno-smartmips do not generate smartmips instructions\n")); | |
14608 | fprintf (stream, _("\ | |
74cd071d CF |
14609 | -mdsp generate DSP instructions\n\ |
14610 | -mno-dsp do not generate DSP instructions\n")); | |
14611 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14612 | -mmt generate MT instructions\n\ |
14613 | -mno-mt do not generate MT instructions\n")); | |
14614 | fprintf (stream, _("\ | |
d766e8ec | 14615 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14616 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14617 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14618 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14619 | -mno-shared optimize output for executables\n\ |
14620 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14621 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14622 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14623 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14624 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14625 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14626 | #ifdef OBJ_ELF | |
14627 | fprintf (stream, _("\ | |
14628 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14629 | -non_shared do not generate position independent code\n\ | |
14630 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14631 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14632 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14633 | non-shared code\n\ | |
316f5878 RS |
14634 | -mabi=ABI create ABI conformant object file for:\n")); |
14635 | ||
14636 | first = 1; | |
14637 | ||
14638 | show (stream, "32", &column, &first); | |
14639 | show (stream, "o64", &column, &first); | |
14640 | show (stream, "n32", &column, &first); | |
14641 | show (stream, "64", &column, &first); | |
14642 | show (stream, "eabi", &column, &first); | |
14643 | ||
14644 | fputc ('\n', stream); | |
14645 | ||
14646 | fprintf (stream, _("\ | |
14647 | -32 create o32 ABI object file (default)\n\ | |
14648 | -n32 create n32 ABI object file\n\ | |
14649 | -64 create 64 ABI object file\n")); | |
14650 | #endif | |
e7af610e | 14651 | } |
14e777e0 KB |
14652 | |
14653 | enum dwarf2_format | |
17a2f251 | 14654 | mips_dwarf2_format (void) |
14e777e0 KB |
14655 | { |
14656 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14657 | { |
14658 | #ifdef TE_IRIX | |
14659 | return dwarf2_format_64bit_irix; | |
14660 | #else | |
14661 | return dwarf2_format_64bit; | |
14662 | #endif | |
14663 | } | |
14e777e0 KB |
14664 | else |
14665 | return dwarf2_format_32bit; | |
14666 | } | |
73369e65 EC |
14667 | |
14668 | int | |
14669 | mips_dwarf2_addr_size (void) | |
14670 | { | |
14671 | if (mips_abi == N64_ABI) | |
14672 | return 8; | |
73369e65 EC |
14673 | else |
14674 | return 4; | |
14675 | } | |
5862107c EC |
14676 | |
14677 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14678 | void | |
14679 | mips_cfi_frame_initial_instructions (void) | |
14680 | { | |
14681 | cfi_add_CFA_def_cfa_register (SP); | |
14682 | } | |
14683 |