Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
50 | #undef OBJ_PROCESS_STAB | |
51 | #undef OUTPUT_FLAVOR | |
52 | #undef S_GET_ALIGN | |
53 | #undef S_GET_SIZE | |
54 | #undef S_SET_ALIGN | |
55 | #undef S_SET_SIZE | |
56 | #undef TARGET_SYMBOL_FIELDS | |
57 | #undef obj_frob_file | |
cc5703cd | 58 | #undef obj_frob_file_after_relocs |
739708fa KR |
59 | #undef obj_frob_symbol |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | ||
63 | #include "obj-elf.h" | |
64 | /* Fix any of them that we actually care about. */ | |
65 | #undef OUTPUT_FLAVOR | |
66 | #define OUTPUT_FLAVOR mips_output_flavor() | |
67 | #endif | |
68 | ||
69 | #if defined (OBJ_ELF) | |
f2a663d3 | 70 | #include "elf/mips.h" |
1dc1e798 | 71 | #endif |
f2a663d3 | 72 | |
739708fa | 73 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 74 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
75 | #define ECOFF_DEBUGGING 0 |
76 | #endif | |
77 | ||
22ba90ce ILT |
78 | #include "ecoff.h" |
79 | ||
a8aed9dd | 80 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 81 | static char *mips_regmask_frag; |
a8aed9dd | 82 | #endif |
f2a663d3 | 83 | |
3d3c5039 | 84 | #define AT 1 |
cc5703cd | 85 | #define TREG 24 |
9226253a | 86 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
87 | #define KT0 26 |
88 | #define KT1 27 | |
670a50eb | 89 | #define GP 28 |
9226253a ILT |
90 | #define SP 29 |
91 | #define FP 30 | |
3d3c5039 ILT |
92 | #define RA 31 |
93 | ||
cc5703cd ILT |
94 | #define ILLEGAL_REG (32) |
95 | ||
1dc1e798 | 96 | extern int target_big_endian; |
88225433 | 97 | |
7f9880e5 ILT |
98 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
99 | 32 bit ABI. This has no meaning for ECOFF. */ | |
100 | static int mips_64; | |
101 | ||
04cb3372 | 102 | /* The default target format to use. */ |
1dc1e798 KR |
103 | const char * |
104 | mips_target_format () | |
105 | { | |
106 | switch (OUTPUT_FLAVOR) | |
107 | { | |
108 | case bfd_target_aout_flavour: | |
109 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
110 | case bfd_target_ecoff_flavour: | |
111 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
112 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
113 | return (target_big_endian |
114 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
115 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
116 | default: |
117 | abort (); | |
118 | } | |
119 | } | |
04cb3372 | 120 | |
d2c71068 | 121 | /* The name of the readonly data section. */ |
1dc1e798 KR |
122 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
123 | ? ".data" \ | |
124 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
125 | ? ".rdata" \ | |
126 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
127 | ? ".rodata" \ | |
128 | : (abort (), "")) | |
d2c71068 | 129 | |
1aa6938e ILT |
130 | /* These variables are filled in with the masks of registers used. |
131 | The object format code reads them and puts them in the appropriate | |
132 | place. */ | |
133 | unsigned long mips_gprmask; | |
134 | unsigned long mips_cprmask[4]; | |
135 | ||
1051c97f ILT |
136 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
137 | temporarily using .set mipsN). */ | |
8358c818 ILT |
138 | static int mips_isa = -1; |
139 | ||
1051c97f ILT |
140 | /* MIPS ISA we are using for this output file. */ |
141 | static int file_mips_isa; | |
142 | ||
cc5703cd ILT |
143 | /* Whether we are assembling for the mips16 processor. */ |
144 | static int mips16 = -1; | |
145 | ||
8c63448a | 146 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 147 | static int mips_cpu = -1; |
8c63448a | 148 | |
b2b8c24e ILT |
149 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
150 | static int mips_4650 = -1; | |
151 | ||
e532b44c ILT |
152 | /* Whether the 4010 instructions are permitted. */ |
153 | static int mips_4010 = -1; | |
154 | ||
c625fc23 JSC |
155 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
156 | static int mips_4100 = -1; | |
157 | ||
276c2d7d GRK |
158 | /* start-sanitize-r5900 */ |
159 | /* Whether Toshiba r5900 instructions are permitted. */ | |
160 | static int mips_5900 = -1; | |
161 | /* end-sanitize-r5900 */ | |
162 | ||
e532b44c ILT |
163 | /* Whether the processor uses hardware interlocks, and thus does not |
164 | require nops to be inserted. */ | |
165 | static int interlocks = -1; | |
166 | ||
344a8d61 JSC |
167 | /* As with "interlocks" this is used by hardware that has FP |
168 | (co-processor) interlocks. */ | |
efec4a28 | 169 | /* Itbl support may require additional care here. */ |
344a8d61 JSC |
170 | static int cop_interlocks = -1; |
171 | ||
d9aba805 ILT |
172 | /* MIPS PIC level. */ |
173 | ||
174 | enum mips_pic_level | |
175 | { | |
176 | /* Do not generate PIC code. */ | |
177 | NO_PIC, | |
178 | ||
179 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
180 | not sure what it is supposed to do. */ | |
181 | IRIX4_PIC, | |
182 | ||
183 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
184 | SVR4_PIC, | |
185 | ||
186 | /* Generate PIC code without using a global offset table: the data | |
187 | segment has a maximum size of 64K, all data references are off | |
188 | the $gp register, and all text references are PC relative. This | |
189 | is used on some embedded systems. */ | |
190 | EMBEDDED_PIC | |
191 | }; | |
192 | ||
193 | static enum mips_pic_level mips_pic; | |
9226253a | 194 | |
fb251650 ILT |
195 | /* 1 if we should generate 32 bit offsets from the GP register in |
196 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
197 | static int mips_big_got; | |
198 | ||
8ea7f4e8 ILT |
199 | /* 1 if trap instructions should used for overflow rather than break |
200 | instructions. */ | |
201 | static int mips_trap; | |
202 | ||
cc5703cd ILT |
203 | /* 1 if we should autoextend mips16 instructions. */ |
204 | static int mips16_autoextend = 1; | |
205 | ||
3d3c5039 ILT |
206 | static int mips_warn_about_macros; |
207 | static int mips_noreorder; | |
0dd2d296 | 208 | static int mips_any_noreorder; |
3d3c5039 ILT |
209 | static int mips_nomove; |
210 | static int mips_noat; | |
211 | static int mips_nobopt; | |
212 | ||
670a50eb ILT |
213 | /* The size of the small data section. */ |
214 | static int g_switch_value = 8; | |
42562568 ILT |
215 | /* Whether the -G option was used. */ |
216 | static int g_switch_seen = 0; | |
670a50eb | 217 | |
3d3c5039 ILT |
218 | #define N_RMASK 0xc4 |
219 | #define N_VFP 0xd4 | |
220 | ||
d8a1c247 KR |
221 | /* If we can determine in advance that GP optimization won't be |
222 | possible, we can skip the relaxation stuff that tries to produce | |
223 | GP-relative references. This makes delay slot optimization work | |
224 | better. | |
225 | ||
226 | This function can only provide a guess, but it seems to work for | |
227 | gcc output. If it guesses wrong, the only loss should be in | |
228 | efficiency; it shouldn't introduce any bugs. | |
229 | ||
230 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
231 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
232 | static int nopic_need_relax PARAMS ((symbolS *)); | |
233 | ||
3d3c5039 ILT |
234 | /* handle of the OPCODE hash table */ |
235 | static struct hash_control *op_hash = NULL; | |
236 | ||
cc5703cd ILT |
237 | /* The opcode hash table we use for the mips16. */ |
238 | static struct hash_control *mips16_op_hash = NULL; | |
239 | ||
3d3c5039 ILT |
240 | /* This array holds the chars that always start a comment. If the |
241 | pre-processor is disabled, these aren't very useful */ | |
242 | const char comment_chars[] = "#"; | |
243 | ||
244 | /* This array holds the chars that only start a comment at the beginning of | |
245 | a line. If the line seems to have the form '# 123 filename' | |
246 | .line and .file directives will appear in the pre-processed output */ | |
247 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
248 | first line of the input file. This is because the compiler outputs | |
249 | #NO_APP at the beginning of its output. */ | |
250 | /* Also note that C style comments are always supported. */ | |
251 | const char line_comment_chars[] = "#"; | |
252 | ||
253 | /* This array holds machine specific line separator characters. */ | |
254 | const char line_separator_chars[] = ""; | |
255 | ||
256 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
257 | const char EXP_CHARS[] = "eE"; | |
258 | ||
259 | /* Chars that mean this number is a floating point constant */ | |
260 | /* As in 0f12.456 */ | |
261 | /* or 0d1.2345e12 */ | |
262 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
263 | ||
264 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
265 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
266 | but nothing is ideal around here. | |
267 | */ | |
268 | ||
670a50eb | 269 | static char *insn_error; |
3d3c5039 | 270 | |
3d3c5039 | 271 | static int auto_align = 1; |
becfe05e | 272 | |
9226253a ILT |
273 | /* When outputting SVR4 PIC code, the assembler needs to know the |
274 | offset in the stack frame from which to restore the $gp register. | |
275 | This is set by the .cprestore pseudo-op, and saved in this | |
276 | variable. */ | |
0dd2d296 ILT |
277 | static offsetT mips_cprestore_offset = -1; |
278 | ||
279 | /* This is the register which holds the stack frame, as set by the | |
280 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
281 | static int mips_frame_reg = SP; | |
9226253a | 282 | |
becfe05e ILT |
283 | /* To output NOP instructions correctly, we need to keep information |
284 | about the previous two instructions. */ | |
285 | ||
0aa07269 ILT |
286 | /* Whether we are optimizing. The default value of 2 means to remove |
287 | unneeded NOPs and swap branch instructions when possible. A value | |
288 | of 1 means to not swap branches. A value of 0 means to always | |
289 | insert NOPs. */ | |
290 | static int mips_optimize = 2; | |
4e95866e | 291 | |
22ba90ce ILT |
292 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
293 | equivalent to seeing no -g option at all. */ | |
294 | static int mips_debug = 0; | |
295 | ||
becfe05e ILT |
296 | /* The previous instruction. */ |
297 | static struct mips_cl_insn prev_insn; | |
298 | ||
299 | /* The instruction before prev_insn. */ | |
300 | static struct mips_cl_insn prev_prev_insn; | |
301 | ||
302 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
303 | point the insn_mo field at this dummy integer. */ | |
304 | static const struct mips_opcode dummy_opcode = { 0 }; | |
305 | ||
306 | /* Non-zero if prev_insn is valid. */ | |
307 | static int prev_insn_valid; | |
308 | ||
309 | /* The frag for the previous instruction. */ | |
310 | static struct frag *prev_insn_frag; | |
311 | ||
312 | /* The offset into prev_insn_frag for the previous instruction. */ | |
313 | static long prev_insn_where; | |
314 | ||
a677feeb ILT |
315 | /* The reloc type for the previous instruction, if any. */ |
316 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
317 | ||
becfe05e ILT |
318 | /* The reloc for the previous instruction, if any. */ |
319 | static fixS *prev_insn_fixp; | |
320 | ||
321 | /* Non-zero if the previous instruction was in a delay slot. */ | |
322 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
323 | |
324 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
325 | static int prev_insn_unreordered; | |
326 | ||
cc5703cd ILT |
327 | /* Non-zero if the previous instruction uses an extend opcode (if |
328 | mips16). */ | |
329 | static int prev_insn_extended; | |
330 | ||
4e95866e ILT |
331 | /* Non-zero if the previous previous instruction was in a .set |
332 | noreorder. */ | |
333 | static int prev_prev_insn_unreordered; | |
867a58b3 | 334 | |
4a1cb507 ILT |
335 | /* If this is set, it points to a frag holding nop instructions which |
336 | were inserted before the start of a noreorder section. If those | |
337 | nops turn out to be unnecessary, the size of the frag can be | |
338 | decreased. */ | |
339 | static fragS *prev_nop_frag; | |
340 | ||
341 | /* The number of nop instructions we created in prev_nop_frag. */ | |
342 | static int prev_nop_frag_holds; | |
343 | ||
344 | /* The number of nop instructions that we know we need in | |
345 | prev_nop_frag. */ | |
346 | static int prev_nop_frag_required; | |
347 | ||
348 | /* The number of instructions we've seen since prev_nop_frag. */ | |
349 | static int prev_nop_frag_since; | |
350 | ||
867a58b3 ILT |
351 | /* For ECOFF and ELF, relocations against symbols are done in two |
352 | parts, with a HI relocation and a LO relocation. Each relocation | |
353 | has only 16 bits of space to store an addend. This means that in | |
354 | order for the linker to handle carries correctly, it must be able | |
355 | to locate both the HI and the LO relocation. This means that the | |
356 | relocations must appear in order in the relocation table. | |
357 | ||
358 | In order to implement this, we keep track of each unmatched HI | |
359 | relocation. We then sort them so that they immediately precede the | |
360 | corresponding LO relocation. */ | |
361 | ||
362 | struct mips_hi_fixup | |
363 | { | |
364 | /* Next HI fixup. */ | |
365 | struct mips_hi_fixup *next; | |
366 | /* This fixup. */ | |
367 | fixS *fixp; | |
368 | /* The section this fixup is in. */ | |
369 | segT seg; | |
370 | }; | |
371 | ||
372 | /* The list of unmatched HI relocs. */ | |
373 | ||
374 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
375 | |
376 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
377 | ||
378 | #define X ILLEGAL_REG | |
379 | static const int mips32_to_16_reg_map[] = | |
380 | { | |
381 | X, X, 2, 3, 4, 5, 6, 7, | |
382 | X, X, X, X, X, X, X, X, | |
383 | 0, 1, X, X, X, X, X, X, | |
384 | X, X, X, X, X, X, X, X | |
385 | }; | |
386 | #undef X | |
387 | ||
388 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
389 | ||
390 | static const int mips16_to_32_reg_map[] = | |
391 | { | |
392 | 16, 17, 2, 3, 4, 5, 6, 7 | |
393 | }; | |
3d3c5039 | 394 | \f |
0dd2d296 ILT |
395 | /* Since the MIPS does not have multiple forms of PC relative |
396 | instructions, we do not have to do relaxing as is done on other | |
397 | platforms. However, we do have to handle GP relative addressing | |
398 | correctly, which turns out to be a similar problem. | |
399 | ||
400 | Every macro that refers to a symbol can occur in (at least) two | |
401 | forms, one with GP relative addressing and one without. For | |
402 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 403 | a macro instruction like this: |
0dd2d296 ILT |
404 | lw $4,i |
405 | If i can be addressed off the GP register (this is true if it is in | |
406 | the .sbss or .sdata section, or if it is known to be smaller than | |
407 | the -G argument) this will generate the following instruction: | |
408 | lw $4,i($gp) | |
409 | This instruction will use a GPREL reloc. If i can not be addressed | |
410 | off the GP register, the following instruction sequence will be used: | |
411 | lui $at,i | |
412 | lw $4,i($at) | |
413 | In this case the first instruction will have a HI16 reloc, and the | |
414 | second reloc will have a LO16 reloc. Both relocs will be against | |
415 | the symbol i. | |
416 | ||
417 | The issue here is that we may not know whether i is GP addressable | |
418 | until after we see the instruction that uses it. Therefore, we | |
419 | want to be able to choose the final instruction sequence only at | |
420 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 421 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
422 | end of assembly. |
423 | ||
424 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
425 | addressing in quite the same way, but the issue still arises as |
426 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
427 | |
428 | We handle these issues by actually generating both possible | |
429 | instruction sequences. The longer one is put in a frag_var with | |
430 | type rs_machine_dependent. We encode what to do with the frag in | |
431 | the subtype field. We encode (1) the number of existing bytes to | |
432 | replace, (2) the number of new bytes to use, (3) the offset from | |
433 | the start of the existing bytes to the first reloc we must generate | |
434 | (that is, the offset is applied from the start of the existing | |
435 | bytes after they are replaced by the new bytes, if any), (4) the | |
436 | offset from the start of the existing bytes to the second reloc, | |
437 | (5) whether a third reloc is needed (the third reloc is always four | |
438 | bytes after the second reloc), and (6) whether to warn if this | |
439 | variant is used (this is sometimes needed if .set nomacro or .set | |
440 | noat is in effect). All these numbers are reasonably small. | |
441 | ||
442 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
443 | ensure that delay slots are handled correctly. Fortunately, there |
444 | are a limited number of cases. When the second instruction | |
445 | sequence is generated, append_insn is directed to maintain the | |
446 | existing delay slot information, so it continues to apply to any | |
447 | code after the second instruction sequence. This means that the | |
448 | second instruction sequence must not impose any requirements not | |
449 | required by the first instruction sequence. | |
0dd2d296 ILT |
450 | |
451 | These variant frags are then handled in functions called by the | |
452 | machine independent code. md_estimate_size_before_relax returns | |
453 | the final size of the frag. md_convert_frag sets up the final form | |
454 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
455 | one if needed. */ | |
456 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
457 | ((relax_substateT) \ | |
cc5703cd | 458 | (((old) << 23) \ |
0dd2d296 ILT |
459 | | ((new) << 16) \ |
460 | | (((reloc1) + 64) << 9) \ | |
461 | | (((reloc2) + 64) << 2) \ | |
462 | | ((reloc3) ? (1 << 1) : 0) \ | |
463 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
464 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
465 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
466 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
467 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
468 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
469 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
470 | |
471 | /* For mips16 code, we use an entirely different form of relaxation. | |
472 | mips16 supports two versions of most instructions which take | |
473 | immediate values: a small one which takes some small value, and a | |
474 | larger one which takes a 16 bit value. Since branches also follow | |
475 | this pattern, relaxing these values is required. | |
476 | ||
477 | We can assemble both mips16 and normal MIPS code in a single | |
478 | object. Therefore, we need to support this type of relaxation at | |
479 | the same time that we support the relaxation described above. We | |
480 | use the high bit of the subtype field to distinguish these cases. | |
481 | ||
a677feeb ILT |
482 | The information we store for this type of relaxation is the |
483 | argument code found in the opcode file for this relocation, whether | |
484 | the user explicitly requested a small or extended form, and whether | |
485 | the relocation is in a jump or jal delay slot. That tells us the | |
486 | size of the value, and how it should be stored. We also store | |
487 | whether the fragment is considered to be extended or not. We also | |
488 | store whether this is known to be a branch to a different section, | |
489 | whether we have tried to relax this frag yet, and whether we have | |
490 | ever extended a PC relative fragment because of a shift count. */ | |
491 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
492 | (0x80000000 \ | |
493 | | ((type) & 0xff) \ | |
494 | | ((small) ? 0x100 : 0) \ | |
495 | | ((ext) ? 0x200 : 0) \ | |
496 | | ((dslot) ? 0x400 : 0) \ | |
497 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
498 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
499 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
500 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
501 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
502 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
503 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
504 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
505 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
506 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
507 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
508 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
509 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 510 | \f |
3d3c5039 ILT |
511 | /* Prototypes for static functions. */ |
512 | ||
513 | #ifdef __STDC__ | |
514 | #define internalError() \ | |
515 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
516 | #else | |
517 | #define internalError() as_fatal ("MIPS internal Error"); | |
518 | #endif | |
519 | ||
cc5703cd ILT |
520 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
521 | ||
becfe05e | 522 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 523 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 524 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
525 | static void append_insn PARAMS ((char *place, |
526 | struct mips_cl_insn * ip, | |
670a50eb | 527 | expressionS * p, |
867a58b3 ILT |
528 | bfd_reloc_code_real_type r, |
529 | boolean)); | |
4a1cb507 | 530 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 531 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 532 | #ifdef USE_STDARG |
0dd2d296 | 533 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
534 | const char *name, const char *fmt, |
535 | ...)); | |
c625fc23 JSC |
536 | #else |
537 | static void macro_build (); | |
538 | #endif | |
cc5703cd ILT |
539 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
540 | const char *, const char *, | |
541 | va_list)); | |
0dd2d296 ILT |
542 | static void macro_build_lui PARAMS ((char *place, int *counter, |
543 | expressionS * ep, int regnum)); | |
6e8dda9c | 544 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 545 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 546 | expressionS *)); |
d8a1c247 | 547 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 548 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 549 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 550 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
551 | #ifdef LOSING_COMPILER |
552 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
553 | #endif | |
670a50eb | 554 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 555 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
556 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
557 | boolean, boolean, unsigned long *, | |
558 | boolean *, unsigned short *)); | |
670a50eb ILT |
559 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
560 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 561 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 562 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
563 | static void s_align PARAMS ((int)); |
564 | static void s_change_sec PARAMS ((int)); | |
565 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 566 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 567 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
568 | static void s_option PARAMS ((int)); |
569 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
570 | static void s_abicalls PARAMS ((int)); |
571 | static void s_cpload PARAMS ((int)); | |
572 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
573 | static void s_gpword PARAMS ((int)); |
574 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 575 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
576 | static void md_obj_begin PARAMS ((void)); |
577 | static void md_obj_end PARAMS ((void)); | |
578 | static long get_number PARAMS ((void)); | |
579 | static void s_ent PARAMS ((int)); | |
580 | static void s_mipsend PARAMS ((int)); | |
581 | static void s_file PARAMS ((int)); | |
cc5703cd | 582 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
583 | \f |
584 | /* Pseudo-op table. | |
585 | ||
586 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
587 | should be defined here, but are currently unsupported: .alias, | |
588 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
589 | ||
590 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
591 | specific to the type of debugging information being generated, and | |
592 | should be defined by the object format: .aent, .begin, .bend, | |
593 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
594 | .vreg. | |
595 | ||
596 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
597 | not MIPS CPU specific, but are also not specific to the object file | |
598 | format. This file is probably the best place to define them, but | |
599 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
600 | .struct, .weakext. */ | |
601 | ||
739708fa | 602 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 603 | { |
670a50eb ILT |
604 | /* MIPS specific pseudo-ops. */ |
605 | {"option", s_option, 0}, | |
606 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
607 | {"rdata", s_change_sec, 'r'}, |
608 | {"sdata", s_change_sec, 's'}, | |
609 | {"livereg", s_ignore, 0}, | |
739708fa KR |
610 | {"abicalls", s_abicalls, 0}, |
611 | {"cpload", s_cpload, 0}, | |
612 | {"cprestore", s_cprestore, 0}, | |
613 | {"gpword", s_gpword, 0}, | |
614 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 615 | {"insn", s_insn, 0}, |
3d3c5039 | 616 | |
670a50eb | 617 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 618 | chips. */ |
739708fa | 619 | {"asciiz", stringer, 1}, |
670a50eb ILT |
620 | {"bss", s_change_sec, 'b'}, |
621 | {"err", s_err, 0}, | |
622 | {"half", s_cons, 1}, | |
52aa70b5 | 623 | {"dword", s_cons, 3}, |
3d3c5039 | 624 | |
670a50eb | 625 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 626 | here for one reason or another. */ |
670a50eb ILT |
627 | {"align", s_align, 0}, |
628 | {"byte", s_cons, 0}, | |
629 | {"data", s_change_sec, 'd'}, | |
becfe05e | 630 | {"double", s_float_cons, 'd'}, |
becfe05e | 631 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
632 | {"globl", s_mips_globl, 0}, |
633 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
634 | {"hword", s_cons, 1}, |
635 | {"int", s_cons, 2}, | |
636 | {"long", s_cons, 2}, | |
637 | {"octa", s_cons, 4}, | |
638 | {"quad", s_cons, 3}, | |
639 | {"short", s_cons, 1}, | |
640 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
641 | {"text", s_change_sec, 't'}, |
642 | {"word", s_cons, 2}, | |
739708fa KR |
643 | { 0 }, |
644 | }; | |
3d3c5039 | 645 | |
739708fa | 646 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 647 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 648 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 649 | {"aent", s_ent, 1}, |
9226253a | 650 | {"bgnb", s_ignore, 0}, |
670a50eb | 651 | {"end", s_mipsend, 0}, |
9226253a | 652 | {"endb", s_ignore, 0}, |
670a50eb ILT |
653 | {"ent", s_ent, 0}, |
654 | {"file", s_file, 0}, | |
655 | {"fmask", s_ignore, 'F'}, | |
656 | {"frame", s_ignore, 0}, | |
657 | {"loc", s_ignore, 0}, | |
658 | {"mask", s_ignore, 'R'}, | |
659 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
660 | { 0 }, |
661 | }; | |
61420a20 | 662 | |
739708fa KR |
663 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
664 | ||
665 | void | |
666 | mips_pop_insert () | |
667 | { | |
668 | pop_insert (mips_pseudo_table); | |
669 | if (! ECOFF_DEBUGGING) | |
670 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 671 | } |
3d3c5039 | 672 | \f |
fbcfacb7 ILT |
673 | /* Symbols labelling the current insn. */ |
674 | ||
675 | struct insn_label_list | |
676 | { | |
677 | struct insn_label_list *next; | |
678 | symbolS *label; | |
679 | }; | |
680 | ||
681 | static struct insn_label_list *insn_labels; | |
682 | static struct insn_label_list *free_insn_labels; | |
683 | ||
684 | static void mips_clear_insn_labels PARAMS ((void)); | |
685 | ||
686 | static inline void | |
687 | mips_clear_insn_labels () | |
688 | { | |
689 | register struct insn_label_list **pl; | |
690 | ||
691 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
692 | ; | |
693 | *pl = insn_labels; | |
694 | insn_labels = NULL; | |
695 | } | |
696 | \f | |
3d3c5039 ILT |
697 | static char *expr_end; |
698 | ||
867a58b3 ILT |
699 | /* Expressions which appear in instructions. These are set by |
700 | mips_ip. */ | |
701 | ||
3d3c5039 ILT |
702 | static expressionS imm_expr; |
703 | static expressionS offset_expr; | |
867a58b3 ILT |
704 | |
705 | /* Relocs associated with imm_expr and offset_expr. */ | |
706 | ||
3d3c5039 ILT |
707 | static bfd_reloc_code_real_type imm_reloc; |
708 | static bfd_reloc_code_real_type offset_reloc; | |
709 | ||
867a58b3 ILT |
710 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
711 | ||
712 | static boolean imm_unmatched_hi; | |
713 | ||
8728fa92 ILT |
714 | /* These are set by mips16_ip if an explicit extension is used. */ |
715 | ||
716 | static boolean mips16_small, mips16_ext; | |
717 | ||
3d3c5039 ILT |
718 | /* |
719 | * This function is called once, at assembler startup time. It should | |
720 | * set up all the tables, etc. that the MD part of the assembler will need. | |
721 | */ | |
722 | void | |
670a50eb | 723 | md_begin () |
3d3c5039 | 724 | { |
0dd2d296 | 725 | boolean ok = false; |
604633ae | 726 | register const char *retval = NULL; |
670a50eb | 727 | register unsigned int i = 0; |
3d3c5039 | 728 | |
8358c818 ILT |
729 | if (mips_isa == -1) |
730 | { | |
8c63448a ILT |
731 | const char *cpu; |
732 | char *a = NULL; | |
733 | ||
734 | cpu = TARGET_CPU; | |
735 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
736 | { | |
737 | a = xmalloc (sizeof TARGET_CPU); | |
738 | strcpy (a, TARGET_CPU); | |
739 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
740 | cpu = a; | |
741 | } | |
742 | ||
743 | if (strcmp (cpu, "mips") == 0) | |
744 | { | |
745 | mips_isa = 1; | |
4bb0cc41 ILT |
746 | if (mips_cpu == -1) |
747 | mips_cpu = 3000; | |
8c63448a ILT |
748 | } |
749 | else if (strcmp (cpu, "r6000") == 0 | |
750 | || strcmp (cpu, "mips2") == 0) | |
751 | { | |
752 | mips_isa = 2; | |
4bb0cc41 ILT |
753 | if (mips_cpu == -1) |
754 | mips_cpu = 6000; | |
8c63448a ILT |
755 | } |
756 | else if (strcmp (cpu, "mips64") == 0 | |
757 | || strcmp (cpu, "r4000") == 0 | |
758 | || strcmp (cpu, "mips3") == 0) | |
759 | { | |
760 | mips_isa = 3; | |
4bb0cc41 ILT |
761 | if (mips_cpu == -1) |
762 | mips_cpu = 4000; | |
8c63448a ILT |
763 | } |
764 | else if (strcmp (cpu, "r4400") == 0) | |
765 | { | |
766 | mips_isa = 3; | |
4bb0cc41 ILT |
767 | if (mips_cpu == -1) |
768 | mips_cpu = 4400; | |
8c63448a ILT |
769 | } |
770 | else if (strcmp (cpu, "mips64orion") == 0 | |
771 | || strcmp (cpu, "r4600") == 0) | |
772 | { | |
773 | mips_isa = 3; | |
4bb0cc41 ILT |
774 | if (mips_cpu == -1) |
775 | mips_cpu = 4600; | |
8c63448a | 776 | } |
b2b8c24e ILT |
777 | else if (strcmp (cpu, "r4650") == 0) |
778 | { | |
779 | mips_isa = 3; | |
780 | if (mips_cpu == -1) | |
781 | mips_cpu = 4650; | |
782 | if (mips_4650 == -1) | |
783 | mips_4650 = 1; | |
784 | } | |
c625fc23 JSC |
785 | else if (strcmp (cpu, "mips64vr4300") == 0) |
786 | { | |
787 | mips_isa = 3; | |
788 | if (mips_cpu == -1) | |
789 | mips_cpu = 4300; | |
790 | } | |
791 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
792 | { | |
793 | mips_isa = 3; | |
794 | if (mips_cpu == -1) | |
795 | mips_cpu = 4100; | |
796 | if (mips_4100 == -1) | |
797 | mips_4100 = 1; | |
798 | } | |
e532b44c ILT |
799 | else if (strcmp (cpu, "r4010") == 0) |
800 | { | |
801 | mips_isa = 2; | |
802 | if (mips_cpu == -1) | |
803 | mips_cpu = 4010; | |
804 | if (mips_4010 == -1) | |
805 | mips_4010 = 1; | |
806 | } | |
517078c1 ILT |
807 | else if (strcmp (cpu, "r5000") == 0 |
808 | || strcmp (cpu, "mips64vr5000") == 0) | |
809 | { | |
810 | mips_isa = 4; | |
811 | if (mips_cpu == -1) | |
812 | mips_cpu = 5000; | |
813 | } | |
276c2d7d GRK |
814 | /* start-sanitize-r5900 */ |
815 | else if (strcmp (cpu, "r5900") == 0 | |
816 | || strcmp (cpu, "mips64vr5900") == 0 | |
817 | || strcmp (cpu, "mips64vr5900el") == 0) | |
818 | { | |
819 | mips_isa = 3; | |
820 | if (mips_cpu == -1) | |
821 | mips_cpu = 5900; | |
16262668 | 822 | if (mips_5900 == -1) |
276c2d7d GRK |
823 | mips_5900 = 1; |
824 | } | |
825 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
826 | else if (strcmp (cpu, "r8000") == 0 |
827 | || strcmp (cpu, "mips4") == 0) | |
828 | { | |
829 | mips_isa = 4; | |
830 | if (mips_cpu == -1) | |
831 | mips_cpu = 8000; | |
832 | } | |
833 | else if (strcmp (cpu, "r10000") == 0) | |
834 | { | |
835 | mips_isa = 4; | |
836 | if (mips_cpu == -1) | |
837 | mips_cpu = 10000; | |
838 | } | |
cc5703cd ILT |
839 | else if (strcmp (cpu, "mips16") == 0) |
840 | { | |
841 | mips_isa = 3; | |
842 | if (mips_cpu == -1) | |
843 | mips_cpu = 0; /* FIXME */ | |
844 | } | |
8358c818 | 845 | else |
8c63448a ILT |
846 | { |
847 | mips_isa = 1; | |
4bb0cc41 ILT |
848 | if (mips_cpu == -1) |
849 | mips_cpu = 3000; | |
8c63448a ILT |
850 | } |
851 | ||
852 | if (a != NULL) | |
853 | free (a); | |
8358c818 ILT |
854 | } |
855 | ||
cc5703cd ILT |
856 | if (mips16 < 0) |
857 | { | |
858 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
859 | mips16 = 1; | |
860 | else | |
861 | mips16 = 0; | |
862 | } | |
863 | ||
b2b8c24e ILT |
864 | if (mips_4650 < 0) |
865 | mips_4650 = 0; | |
866 | ||
e532b44c ILT |
867 | if (mips_4010 < 0) |
868 | mips_4010 = 0; | |
869 | ||
c625fc23 JSC |
870 | if (mips_4100 < 0) |
871 | mips_4100 = 0; | |
872 | ||
276c2d7d GRK |
873 | /* start-sanitize-r5900 */ |
874 | if (mips_5900 < 0) | |
875 | mips_5900 = 0; | |
876 | /* end-sanitize-r5900 */ | |
877 | ||
c36a90ef | 878 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
879 | interlocks = 1; |
880 | else | |
881 | interlocks = 0; | |
882 | ||
efec4a28 | 883 | /* Itbl support may require additional care here. */ |
ca296aab | 884 | if (mips_cpu == 4300) |
344a8d61 JSC |
885 | cop_interlocks = 1; |
886 | else | |
887 | cop_interlocks = 0; | |
888 | ||
8ea7f4e8 ILT |
889 | if (mips_isa < 2 && mips_trap) |
890 | as_bad ("trap exception not supported at ISA 1"); | |
891 | ||
97f99d11 ILT |
892 | switch (mips_isa) |
893 | { | |
894 | case 1: | |
895 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
896 | break; | |
897 | case 2: | |
898 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
899 | break; | |
900 | case 3: | |
901 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
902 | break; | |
d8a1c247 KR |
903 | case 4: |
904 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
905 | break; | |
97f99d11 ILT |
906 | } |
907 | if (! ok) | |
908 | as_warn ("Could not set architecture and machine"); | |
909 | ||
1051c97f ILT |
910 | file_mips_isa = mips_isa; |
911 | ||
13fe1379 ILT |
912 | op_hash = hash_new (); |
913 | ||
670a50eb ILT |
914 | for (i = 0; i < NUMOPCODES;) |
915 | { | |
916 | const char *name = mips_opcodes[i].name; | |
917 | ||
604633ae | 918 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 919 | if (retval != NULL) |
670a50eb ILT |
920 | { |
921 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
922 | mips_opcodes[i].name, retval); | |
923 | as_fatal ("Broken assembler. No assembly attempted."); | |
924 | } | |
925 | do | |
926 | { | |
8358c818 ILT |
927 | if (mips_opcodes[i].pinfo != INSN_MACRO |
928 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
929 | != mips_opcodes[i].match)) | |
670a50eb ILT |
930 | { |
931 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
932 | mips_opcodes[i].name, mips_opcodes[i].args); | |
933 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 934 | } |
670a50eb ILT |
935 | ++i; |
936 | } | |
937 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
938 | } |
939 | ||
cc5703cd ILT |
940 | mips16_op_hash = hash_new (); |
941 | ||
942 | i = 0; | |
943 | while (i < bfd_mips16_num_opcodes) | |
944 | { | |
945 | const char *name = mips16_opcodes[i].name; | |
946 | ||
947 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
948 | if (retval != NULL) | |
949 | as_fatal ("internal error: can't hash `%s': %s\n", | |
950 | mips16_opcodes[i].name, retval); | |
951 | do | |
952 | { | |
953 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
954 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
955 | != mips16_opcodes[i].match)) | |
956 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
957 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
958 | ++i; | |
959 | } | |
960 | while (i < bfd_mips16_num_opcodes | |
961 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
962 | } | |
963 | ||
ebf28372 ILT |
964 | /* We add all the general register names to the symbol table. This |
965 | helps us detect invalid uses of them. */ | |
966 | for (i = 0; i < 32; i++) | |
967 | { | |
968 | char buf[5]; | |
969 | ||
970 | sprintf (buf, "$%d", i); | |
971 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
972 | &zero_address_frag)); | |
973 | } | |
974 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
975 | &zero_address_frag)); | |
976 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
977 | &zero_address_frag)); | |
978 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
979 | &zero_address_frag)); | |
980 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
981 | &zero_address_frag)); | |
982 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
983 | &zero_address_frag)); | |
984 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
985 | &zero_address_frag)); | |
986 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
987 | &zero_address_frag)); | |
988 | ||
4a1cb507 | 989 | mips_no_prev_insn (false); |
becfe05e | 990 | |
1aa6938e ILT |
991 | mips_gprmask = 0; |
992 | mips_cprmask[0] = 0; | |
993 | mips_cprmask[1] = 0; | |
994 | mips_cprmask[2] = 0; | |
995 | mips_cprmask[3] = 0; | |
996 | ||
8358c818 | 997 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 998 | record_alignment (text_section, 2); |
8358c818 | 999 | |
1dc1e798 KR |
1000 | if (USE_GLOBAL_POINTER_OPT) |
1001 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1002 | |
1dc1e798 KR |
1003 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1004 | { | |
08e17202 ILT |
1005 | /* On a native system, sections must be aligned to 16 byte |
1006 | boundaries. When configured for an embedded ELF target, we | |
1007 | don't bother. */ | |
1008 | if (strcmp (TARGET_OS, "elf") != 0) | |
1009 | { | |
1010 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1011 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1012 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1013 | } | |
1dc1e798 KR |
1014 | |
1015 | /* Create a .reginfo section for register masks and a .mdebug | |
1016 | section for debugging information. */ | |
1017 | { | |
1018 | segT seg; | |
1019 | subsegT subseg; | |
b3a64736 | 1020 | flagword flags; |
1dc1e798 KR |
1021 | segT sec; |
1022 | ||
1023 | seg = now_seg; | |
1024 | subseg = now_subseg; | |
1dc1e798 | 1025 | |
b3a64736 ILT |
1026 | /* The ABI says this section should be loaded so that the |
1027 | running program can access it. However, we don't load it | |
1028 | if we are configured for an embedded target */ | |
1029 | flags = SEC_READONLY | SEC_DATA; | |
1030 | if (strcmp (TARGET_OS, "elf") != 0) | |
1031 | flags |= SEC_ALLOC | SEC_LOAD; | |
1032 | ||
87178180 ILT |
1033 | if (! mips_64) |
1034 | { | |
1035 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1036 | |
b3a64736 ILT |
1037 | |
1038 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1039 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1040 | ||
f2a663d3 | 1041 | #ifdef OBJ_ELF |
87178180 | 1042 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1043 | #endif |
87178180 ILT |
1044 | } |
1045 | else | |
1046 | { | |
1047 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1048 | .reginfo section. */ | |
1049 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1050 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1051 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1052 | ||
1053 | #ifdef OBJ_ELF | |
1054 | /* Set up the option header. */ | |
1055 | { | |
1056 | Elf_Internal_Options opthdr; | |
1057 | char *f; | |
1058 | ||
1059 | opthdr.kind = ODK_REGINFO; | |
1060 | opthdr.size = (sizeof (Elf_External_Options) | |
1061 | + sizeof (Elf64_External_RegInfo)); | |
1062 | opthdr.section = 0; | |
1063 | opthdr.info = 0; | |
1064 | f = frag_more (sizeof (Elf_External_Options)); | |
1065 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1066 | (Elf_External_Options *) f); | |
1067 | ||
1068 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1069 | } | |
1070 | #endif | |
1071 | } | |
f2a663d3 | 1072 | |
739708fa KR |
1073 | if (ECOFF_DEBUGGING) |
1074 | { | |
1075 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1076 | (void) bfd_set_section_flags (stdoutput, sec, | |
1077 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1078 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1079 | } | |
0dd2d296 | 1080 | |
1dc1e798 KR |
1081 | subseg_set (seg, subseg); |
1082 | } | |
1083 | } | |
f2a663d3 | 1084 | |
739708fa KR |
1085 | if (! ECOFF_DEBUGGING) |
1086 | md_obj_begin (); | |
3d3c5039 ILT |
1087 | } |
1088 | ||
1089 | void | |
13fe1379 | 1090 | md_mips_end () |
3d3c5039 | 1091 | { |
739708fa KR |
1092 | if (! ECOFF_DEBUGGING) |
1093 | md_obj_end (); | |
3d3c5039 ILT |
1094 | } |
1095 | ||
1096 | void | |
670a50eb ILT |
1097 | md_assemble (str) |
1098 | char *str; | |
3d3c5039 | 1099 | { |
670a50eb | 1100 | struct mips_cl_insn insn; |
3d3c5039 | 1101 | |
5ac34ac3 | 1102 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1103 | imm_reloc = BFD_RELOC_UNUSED; |
1104 | imm_unmatched_hi = false; | |
5ac34ac3 | 1105 | offset_expr.X_op = O_absent; |
867a58b3 | 1106 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1107 | |
cc5703cd ILT |
1108 | if (mips16) |
1109 | mips16_ip (str, &insn); | |
1110 | else | |
efec4a28 | 1111 | { |
cc5703cd | 1112 | mips_ip (str, &insn); |
efec4a28 DP |
1113 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1114 | str, insn.insn_opcode)); | |
1115 | } | |
cc5703cd | 1116 | |
670a50eb ILT |
1117 | if (insn_error) |
1118 | { | |
1119 | as_bad ("%s `%s'", insn_error, str); | |
1120 | return; | |
1121 | } | |
cc5703cd | 1122 | |
670a50eb ILT |
1123 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1124 | { | |
cc5703cd ILT |
1125 | if (mips16) |
1126 | mips16_macro (&insn); | |
1127 | else | |
1128 | macro (&insn); | |
3d3c5039 | 1129 | } |
670a50eb ILT |
1130 | else |
1131 | { | |
5ac34ac3 | 1132 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1133 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1134 | imm_unmatched_hi); | |
5ac34ac3 | 1135 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1136 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1137 | else |
867a58b3 | 1138 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1139 | } |
1140 | } | |
1141 | ||
cc5703cd ILT |
1142 | /* See whether instruction IP reads register REG. CLASS is the type |
1143 | of register. */ | |
becfe05e ILT |
1144 | |
1145 | static int | |
cc5703cd | 1146 | insn_uses_reg (ip, reg, class) |
becfe05e | 1147 | struct mips_cl_insn *ip; |
604633ae | 1148 | unsigned int reg; |
cc5703cd | 1149 | enum mips_regclass class; |
becfe05e | 1150 | { |
cc5703cd ILT |
1151 | if (class == MIPS16_REG) |
1152 | { | |
1153 | assert (mips16); | |
1154 | reg = mips16_to_32_reg_map[reg]; | |
1155 | class = MIPS_GR_REG; | |
1156 | } | |
1157 | ||
becfe05e | 1158 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1159 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1160 | return 0; |
1161 | ||
cc5703cd | 1162 | if (class == MIPS_FP_REG) |
becfe05e | 1163 | { |
cc5703cd | 1164 | assert (! mips16); |
becfe05e ILT |
1165 | /* If we are called with either $f0 or $f1, we must check $f0. |
1166 | This is not optimal, because it will introduce an unnecessary | |
1167 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1168 | need to distinguish reading both $f0 and $f1 or just one of | |
1169 | them. Note that we don't have to check the other way, | |
1170 | because there is no instruction that sets both $f0 and $f1 | |
1171 | and requires a delay. */ | |
1172 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1173 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1174 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1175 | return 1; |
1176 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1177 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1178 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1179 | return 1; |
1180 | } | |
cc5703cd | 1181 | else if (! mips16) |
becfe05e ILT |
1182 | { |
1183 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1184 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1185 | return 1; | |
1186 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1187 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1188 | return 1; | |
1189 | } | |
cc5703cd ILT |
1190 | else |
1191 | { | |
1192 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1193 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1194 | return 1; | |
1195 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1196 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1197 | return 1; | |
1198 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1199 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1200 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1201 | return 1; | |
1202 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1203 | return 1; | |
1204 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1205 | return 1; | |
1206 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1207 | return 1; | |
1208 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1209 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1210 | & MIPS16OP_MASK_REGR32) == reg) | |
1211 | return 1; | |
1212 | } | |
becfe05e ILT |
1213 | |
1214 | return 0; | |
1215 | } | |
1216 | ||
fb251650 ILT |
1217 | /* This function returns true if modifying a register requires a |
1218 | delay. */ | |
1219 | ||
1220 | static int | |
1221 | reg_needs_delay (reg) | |
1222 | int reg; | |
1223 | { | |
1224 | unsigned long prev_pinfo; | |
1225 | ||
1226 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1227 | if (! mips_noreorder | |
1228 | && mips_isa < 4 | |
1229 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1230 | || (mips_isa < 2 | |
1231 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1232 | { | |
1233 | /* A load from a coprocessor or from memory. All load | |
1234 | delays delay the use of general register rt for one | |
1235 | instruction on the r3000. The r6000 and r4000 use | |
1236 | interlocks. */ | |
efec4a28 | 1237 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1238 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1239 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1240 | return 1; | |
1241 | } | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
0dd2d296 ILT |
1246 | /* Output an instruction. PLACE is where to put the instruction; if |
1247 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1248 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1249 | used with RELOC_TYPE. */ | |
3d3c5039 | 1250 | |
3d3c5039 | 1251 | static void |
867a58b3 | 1252 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1253 | char *place; |
670a50eb ILT |
1254 | struct mips_cl_insn *ip; |
1255 | expressionS *address_expr; | |
1256 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1257 | boolean unmatched_hi; |
3d3c5039 | 1258 | { |
1aa6938e | 1259 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1260 | char *f; |
becfe05e ILT |
1261 | fixS *fixp; |
1262 | int nops = 0; | |
3d3c5039 | 1263 | |
fbcfacb7 ILT |
1264 | /* Mark instruction labels in mips16 mode. This permits the linker |
1265 | to handle them specially, such as generating jalx instructions | |
1266 | when needed. We also make them odd for the duration of the | |
1267 | assembly, in order to generate the right sort of code. We will | |
1268 | make them even in the adjust_symtab routine, while leaving them | |
1269 | marked. This is convenient for the debugger and the | |
1270 | disassembler. The linker knows to make them odd again. */ | |
1271 | if (mips16) | |
1272 | { | |
1273 | struct insn_label_list *l; | |
1274 | ||
1275 | for (l = insn_labels; l != NULL; l = l->next) | |
1276 | { | |
1277 | #ifdef S_SET_OTHER | |
1278 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1279 | S_SET_OTHER (l->label, STO_MIPS16); | |
1280 | #endif | |
1281 | ++l->label->sy_value.X_add_number; | |
1282 | } | |
1283 | } | |
1284 | ||
1aa6938e ILT |
1285 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1286 | pinfo = ip->insn_mo->pinfo; | |
1287 | ||
4a1cb507 | 1288 | if (place == NULL && (! mips_noreorder || prev_nop_frag != NULL)) |
becfe05e | 1289 | { |
4a1cb507 ILT |
1290 | int prev_prev_nop; |
1291 | ||
becfe05e | 1292 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1293 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1294 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1295 | (1) a load from memory delay |
1296 | (2) a load from a coprocessor delay | |
1297 | (3) an unconditional branch delay | |
1298 | (4) a conditional branch delay | |
1299 | (5) a move to coprocessor register delay | |
1300 | (6) a load coprocessor register from memory delay | |
1301 | (7) a coprocessor condition code delay | |
1302 | (8) a HI/LO special register delay | |
becfe05e ILT |
1303 | |
1304 | There are a lot of optimizations we could do that we don't. | |
1305 | In particular, we do not, in general, reorder instructions. | |
1306 | If you use gcc with optimization, it will reorder | |
1307 | instructions and generally do much more optimization then we | |
1308 | do here; repeating all that work in the assembler would only | |
1309 | benefit hand written assembly code, and does not seem worth | |
1310 | it. */ | |
1311 | ||
1312 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1313 | #define emit_nop() \ |
1314 | (mips16 \ | |
1315 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1316 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1317 | |
1318 | /* The previous insn might require a delay slot, depending upon | |
1319 | the contents of the current insn. */ | |
cc5703cd ILT |
1320 | if (! mips16 |
1321 | && mips_isa < 4 | |
5af96dce ILT |
1322 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1323 | && ! cop_interlocks) | |
d8a1c247 KR |
1324 | || (mips_isa < 2 |
1325 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1326 | { |
1327 | /* A load from a coprocessor or from memory. All load | |
1328 | delays delay the use of general register rt for one | |
1329 | instruction on the r3000. The r6000 and r4000 use | |
1330 | interlocks. */ | |
efec4a28 | 1331 | /* Itbl support may require additional care here. */ |
1aa6938e | 1332 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1333 | if (mips_optimize == 0 |
1334 | || insn_uses_reg (ip, | |
1335 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1336 | & OP_MASK_RT), | |
cc5703cd | 1337 | MIPS_GR_REG)) |
becfe05e ILT |
1338 | ++nops; |
1339 | } | |
cc5703cd ILT |
1340 | else if (! mips16 |
1341 | && mips_isa < 4 | |
5af96dce ILT |
1342 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1343 | && ! cop_interlocks) | |
d8a1c247 KR |
1344 | || (mips_isa < 2 |
1345 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1346 | { |
1347 | /* A generic coprocessor delay. The previous instruction | |
1348 | modified a coprocessor general or control register. If | |
1349 | it modified a control register, we need to avoid any | |
1350 | coprocessor instruction (this is probably not always | |
1351 | required, but it sometimes is). If it modified a general | |
1352 | register, we avoid using that register. | |
1353 | ||
8358c818 ILT |
1354 | On the r6000 and r4000 loading a coprocessor register |
1355 | from memory is interlocked, and does not require a delay. | |
1356 | ||
becfe05e ILT |
1357 | This case is not handled very well. There is no special |
1358 | knowledge of CP0 handling, and the coprocessors other | |
1359 | than the floating point unit are not distinguished at | |
1360 | all. */ | |
efec4a28 DP |
1361 | /* Itbl support may require additional care here. FIXME! |
1362 | Need to modify this to include knowledge about | |
1363 | user specified delays! */ | |
1aa6938e | 1364 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1365 | { |
0aa07269 ILT |
1366 | if (mips_optimize == 0 |
1367 | || insn_uses_reg (ip, | |
8358c818 ILT |
1368 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1369 | & OP_MASK_FT), | |
cc5703cd | 1370 | MIPS_FP_REG)) |
becfe05e ILT |
1371 | ++nops; |
1372 | } | |
1aa6938e | 1373 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1374 | { |
0aa07269 ILT |
1375 | if (mips_optimize == 0 |
1376 | || insn_uses_reg (ip, | |
8358c818 ILT |
1377 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1378 | & OP_MASK_FS), | |
cc5703cd | 1379 | MIPS_FP_REG)) |
becfe05e ILT |
1380 | ++nops; |
1381 | } | |
1382 | else | |
1383 | { | |
1384 | /* We don't know exactly what the previous instruction | |
1385 | does. If the current instruction uses a coprocessor | |
1386 | register, we must insert a NOP. If previous | |
1387 | instruction may set the condition codes, and the | |
1388 | current instruction uses them, we must insert two | |
1389 | NOPS. */ | |
efec4a28 | 1390 | /* Itbl support may require additional care here. */ |
0aa07269 | 1391 | if (mips_optimize == 0 |
1aa6938e ILT |
1392 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1393 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1394 | nops += 2; |
1aa6938e | 1395 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1396 | ++nops; |
1397 | } | |
1398 | } | |
cc5703cd ILT |
1399 | else if (! mips16 |
1400 | && mips_isa < 4 | |
344a8d61 JSC |
1401 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1402 | && ! cop_interlocks) | |
becfe05e ILT |
1403 | { |
1404 | /* The previous instruction sets the coprocessor condition | |
1405 | codes, but does not require a general coprocessor delay | |
1406 | (this means it is a floating point comparison | |
1407 | instruction). If this instruction uses the condition | |
1408 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1409 | /* Itbl support may require additional care here. */ |
0aa07269 | 1410 | if (mips_optimize == 0 |
1aa6938e | 1411 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1412 | ++nops; |
1413 | } | |
1aa6938e | 1414 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1415 | { |
1416 | /* The previous instruction reads the LO register; if the | |
1417 | current instruction writes to the LO register, we must | |
517078c1 | 1418 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1419 | if (! interlocks |
b2b8c24e ILT |
1420 | && (mips_optimize == 0 |
1421 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1422 | nops += 2; |
1423 | } | |
1424 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1425 | { | |
1426 | /* The previous instruction reads the HI register; if the | |
1427 | current instruction writes to the HI register, we must | |
517078c1 | 1428 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1429 | if (! interlocks |
b2b8c24e ILT |
1430 | && (mips_optimize == 0 |
1431 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1432 | nops += 2; |
1433 | } | |
1434 | ||
4a1cb507 ILT |
1435 | /* If the previous instruction was in a noreorder section, then |
1436 | we don't want to insert the nop after all. */ | |
efec4a28 | 1437 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1438 | if (prev_insn_unreordered) |
1439 | nops = 0; | |
1440 | ||
becfe05e ILT |
1441 | /* There are two cases which require two intervening |
1442 | instructions: 1) setting the condition codes using a move to | |
1443 | coprocessor instruction which requires a general coprocessor | |
1444 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1445 | or LO register and then writing to it (except on processors |
1446 | which have interlocks). If we are not already emitting a NOP | |
1447 | instruction, we must check for these cases compared to the | |
1448 | instruction previous to the previous instruction. */ | |
4a1cb507 ILT |
1449 | if ((! mips16 |
1450 | && mips_isa < 4 | |
1451 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) | |
1452 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1453 | && (pinfo & INSN_READ_COND_CODE) | |
1454 | && ! cop_interlocks) | |
1455 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1456 | && (pinfo & INSN_WRITE_LO) | |
1457 | && ! interlocks) | |
1458 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1459 | && (pinfo & INSN_WRITE_HI) | |
1460 | && ! interlocks)) | |
1461 | prev_prev_nop = 1; | |
1462 | else | |
1463 | prev_prev_nop = 0; | |
1464 | ||
1465 | if (prev_prev_insn_unreordered) | |
1466 | prev_prev_nop = 0; | |
1467 | ||
1468 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1469 | ++nops; |
1470 | ||
0dd2d296 ILT |
1471 | /* If we are being given a nop instruction, don't bother with |
1472 | one of the nops we would otherwise output. This will only | |
1473 | happen when a nop instruction is used with mips_optimize set | |
1474 | to 0. */ | |
4a1cb507 ILT |
1475 | if (nops > 0 |
1476 | && ! mips_noreorder | |
1477 | && ip->insn_opcode == (mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1478 | --nops; |
1479 | ||
becfe05e | 1480 | /* Now emit the right number of NOP instructions. */ |
4a1cb507 | 1481 | if (nops > 0 && ! mips_noreorder) |
becfe05e | 1482 | { |
5af96dce ILT |
1483 | fragS *old_frag; |
1484 | unsigned long old_frag_offset; | |
8c63448a | 1485 | int i; |
fbcfacb7 | 1486 | struct insn_label_list *l; |
8c63448a | 1487 | |
5af96dce ILT |
1488 | old_frag = frag_now; |
1489 | old_frag_offset = frag_now_fix (); | |
1490 | ||
8c63448a | 1491 | for (i = 0; i < nops; i++) |
becfe05e | 1492 | emit_nop (); |
5af96dce | 1493 | |
af255ca0 | 1494 | if (listing) |
546f5536 ILT |
1495 | { |
1496 | listing_prev_line (); | |
1497 | /* We may be at the start of a variant frag. In case we | |
1498 | are, make sure there is enough space for the frag | |
1499 | after the frags created by listing_prev_line. The | |
1500 | argument to frag_grow here must be at least as large | |
1501 | as the argument to all other calls to frag_grow in | |
1502 | this file. We don't have to worry about being in the | |
1503 | middle of a variant frag, because the variants insert | |
1504 | all needed nop instructions themselves. */ | |
1505 | frag_grow (40); | |
1506 | } | |
5af96dce | 1507 | |
fbcfacb7 | 1508 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1509 | { |
fbcfacb7 ILT |
1510 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1511 | l->label->sy_frag = frag_now; | |
1512 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1513 | /* mips16 text labels are stored as odd. */ | |
1514 | if (mips16) | |
1515 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1516 | } |
5af96dce ILT |
1517 | |
1518 | #ifndef NO_ECOFF_DEBUGGING | |
1519 | if (ECOFF_DEBUGGING) | |
1520 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1521 | #endif | |
becfe05e | 1522 | } |
4a1cb507 ILT |
1523 | else if (prev_nop_frag != NULL) |
1524 | { | |
1525 | /* We have a frag holding nops we may be able to remove. If | |
1526 | we don't need any nops, we can decrease the size of | |
1527 | prev_nop_frag by the size of one instruction. If we do | |
1528 | need some nops, we count them in prev_nops_required. */ | |
1529 | if (prev_nop_frag_since == 0) | |
1530 | { | |
1531 | if (nops == 0) | |
1532 | { | |
1533 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1534 | --prev_nop_frag_holds; | |
1535 | } | |
1536 | else | |
1537 | prev_nop_frag_required += nops; | |
1538 | } | |
1539 | else | |
1540 | { | |
1541 | if (prev_prev_nop == 0) | |
1542 | { | |
1543 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1544 | --prev_nop_frag_holds; | |
1545 | } | |
1546 | else | |
1547 | ++prev_nop_frag_required; | |
1548 | } | |
1549 | ||
1550 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1551 | prev_nop_frag = NULL; | |
1552 | ||
1553 | ++prev_nop_frag_since; | |
1554 | ||
1555 | /* Sanity check: by the time we reach the second instruction | |
1556 | after prev_nop_frag, we should have used up all the nops | |
1557 | one way or another. */ | |
1558 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1559 | } | |
becfe05e | 1560 | } |
4a1cb507 | 1561 | |
cc5703cd ILT |
1562 | if (reloc_type > BFD_RELOC_UNUSED) |
1563 | { | |
1564 | /* We need to set up a variant frag. */ | |
1565 | assert (mips16 && address_expr != NULL); | |
1566 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1567 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1568 | mips16_small, mips16_ext, |
1569 | (prev_pinfo | |
1570 | & INSN_UNCOND_BRANCH_DELAY), | |
1571 | (prev_insn_reloc_type | |
1572 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1573 | make_expr_symbol (address_expr), (long) 0, |
1574 | (char *) NULL); | |
1575 | } | |
1576 | else if (place != NULL) | |
0dd2d296 | 1577 | f = place; |
cc5703cd | 1578 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1579 | { |
1580 | /* Make sure there is enough room to swap this instruction with | |
1581 | a following jump instruction. */ | |
1582 | frag_grow (6); | |
1583 | f = frag_more (2); | |
1584 | } | |
cc5703cd | 1585 | else |
035936da ILT |
1586 | { |
1587 | if (mips16 | |
1588 | && mips_noreorder | |
1589 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1590 | as_warn ("extended instruction in delay slot"); | |
1591 | ||
1592 | f = frag_more (4); | |
1593 | } | |
1594 | ||
becfe05e | 1595 | fixp = NULL; |
cc5703cd | 1596 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1597 | { |
5ac34ac3 | 1598 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1599 | { |
1600 | switch (reloc_type) | |
1601 | { | |
3d3c5039 | 1602 | case BFD_RELOC_32: |
670a50eb ILT |
1603 | ip->insn_opcode |= address_expr->X_add_number; |
1604 | break; | |
3d3c5039 ILT |
1605 | |
1606 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1607 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1608 | break; | |
3d3c5039 ILT |
1609 | |
1610 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1611 | if ((address_expr->X_add_number & 3) != 0) |
1612 | as_bad ("jump to misaligned address (0x%lx)", | |
1613 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1614 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1615 | break; | |
1616 | ||
cc5703cd | 1617 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1618 | if ((address_expr->X_add_number & 3) != 0) |
1619 | as_bad ("jump to misaligned address (0x%lx)", | |
1620 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1621 | ip->insn_opcode |= |
1622 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1623 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1624 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1625 | break; | |
1626 | ||
3d3c5039 | 1627 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1628 | goto need_reloc; |
3d3c5039 ILT |
1629 | |
1630 | default: | |
670a50eb | 1631 | internalError (); |
3d3c5039 | 1632 | } |
670a50eb ILT |
1633 | } |
1634 | else | |
1635 | { | |
3d3c5039 | 1636 | need_reloc: |
0dd2d296 ILT |
1637 | /* Don't generate a reloc if we are writing into a variant |
1638 | frag. */ | |
1639 | if (place == NULL) | |
867a58b3 ILT |
1640 | { |
1641 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1642 | address_expr, | |
1643 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1644 | reloc_type); | |
1645 | if (unmatched_hi) | |
1646 | { | |
1647 | struct mips_hi_fixup *hi_fixup; | |
1648 | ||
1649 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1650 | hi_fixup = ((struct mips_hi_fixup *) | |
1651 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1652 | hi_fixup->fixp = fixp; | |
1653 | hi_fixup->seg = now_seg; | |
1654 | hi_fixup->next = mips_hi_fixup_list; | |
1655 | mips_hi_fixup_list = hi_fixup; | |
1656 | } | |
1657 | } | |
3d3c5039 ILT |
1658 | } |
1659 | } | |
becfe05e | 1660 | |
16262668 | 1661 | if (! mips16) |
cc5703cd | 1662 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1663 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1664 | { | |
1665 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1666 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1667 | } | |
cc5703cd ILT |
1668 | else |
1669 | { | |
1670 | if (ip->use_extend) | |
1671 | { | |
1672 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1673 | f += 2; | |
1674 | } | |
1675 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1676 | } | |
670a50eb | 1677 | |
1aa6938e | 1678 | /* Update the register mask information. */ |
cc5703cd ILT |
1679 | if (! mips16) |
1680 | { | |
1681 | if (pinfo & INSN_WRITE_GPR_D) | |
1682 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1683 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1684 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1685 | if (pinfo & INSN_READ_GPR_S) | |
1686 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1687 | if (pinfo & INSN_WRITE_GPR_31) | |
1688 | mips_gprmask |= 1 << 31; | |
1689 | if (pinfo & INSN_WRITE_FPR_D) | |
1690 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1691 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1692 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1693 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1694 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1695 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1696 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1697 | if (pinfo & INSN_COP) | |
1698 | { | |
efec4a28 DP |
1699 | /* We don't keep enough information to sort these cases out. |
1700 | The itbl support does keep this information however, although | |
1701 | we currently don't support itbl fprmats as part of the cop | |
1702 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1703 | } |
1704 | /* Never set the bit for $0, which is always zero. */ | |
1705 | mips_gprmask &=~ 1 << 0; | |
1706 | } | |
1707 | else | |
1aa6938e | 1708 | { |
cc5703cd ILT |
1709 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1710 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1711 | & MIPS16OP_MASK_RX); | |
1712 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1713 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1714 | & MIPS16OP_MASK_RY); | |
1715 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1716 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1717 | & MIPS16OP_MASK_RZ); | |
1718 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1719 | mips_gprmask |= 1 << TREG; | |
1720 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1721 | mips_gprmask |= 1 << SP; | |
1722 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1723 | mips_gprmask |= 1 << RA; | |
1724 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1725 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1726 | if (pinfo & MIPS16_INSN_READ_Z) | |
1727 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1728 | & MIPS16OP_MASK_MOVE32Z); | |
1729 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1730 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1731 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1732 | } |
1aa6938e | 1733 | |
0dd2d296 | 1734 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1735 | { |
becfe05e ILT |
1736 | /* Filling the branch delay slot is more complex. We try to |
1737 | switch the branch with the previous instruction, which we can | |
1738 | do if the previous instruction does not set up a condition | |
1739 | that the branch tests and if the branch is not itself the | |
1740 | target of any branch. */ | |
1aa6938e ILT |
1741 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1742 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1743 | { |
0aa07269 | 1744 | if (mips_optimize < 2 |
19ed8960 ILT |
1745 | /* If we have seen .set volatile or .set nomove, don't |
1746 | optimize. */ | |
1747 | || mips_nomove != 0 | |
4e95866e ILT |
1748 | /* If we had to emit any NOP instructions, then we |
1749 | already know we can not swap. */ | |
1750 | || nops != 0 | |
becfe05e ILT |
1751 | /* If we don't even know the previous insn, we can not |
1752 | swap. */ | |
1753 | || ! prev_insn_valid | |
1754 | /* If the previous insn is already in a branch delay | |
1755 | slot, then we can not swap. */ | |
1756 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1757 | /* If the previous previous insn was in a .set |
1758 | noreorder, we can't swap. Actually, the MIPS | |
1759 | assembler will swap in this situation. However, gcc | |
1760 | configured -with-gnu-as will generate code like | |
1761 | .set noreorder | |
1762 | lw $4,XXX | |
1763 | .set reorder | |
1764 | INSN | |
1765 | bne $4,$0,foo | |
1766 | in which we can not swap the bne and INSN. If gcc is | |
1767 | not configured -with-gnu-as, it does not output the | |
1768 | .set pseudo-ops. We don't have to check | |
1769 | prev_insn_unreordered, because prev_insn_valid will | |
1770 | be 0 in that case. We don't want to use | |
1771 | prev_prev_insn_valid, because we do want to be able | |
1772 | to swap at the start of a function. */ | |
1773 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1774 | /* If the branch is itself the target of a branch, we |
1775 | can not swap. We cheat on this; all we check for is | |
1776 | whether there is a label on this instruction. If | |
1777 | there are any branches to anything other than a | |
1778 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1779 | || insn_labels != NULL |
777ad64d | 1780 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1781 | can not do the swap. This does not apply to the |
1782 | mips16, which uses variant frags for different | |
1783 | purposes. */ | |
1784 | || (! mips16 | |
1785 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1786 | /* If the branch reads the condition codes, we don't |
1787 | even try to swap, because in the sequence | |
1788 | ctc1 $X,$31 | |
1789 | INSN | |
1790 | INSN | |
1791 | bc1t LABEL | |
1792 | we can not swap, and I don't feel like handling that | |
1793 | case. */ | |
cc5703cd ILT |
1794 | || (! mips16 |
1795 | && mips_isa < 4 | |
d8a1c247 | 1796 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1797 | /* We can not swap with an instruction that requires a |
1798 | delay slot, becase the target of the branch might | |
1799 | interfere with that instruction. */ | |
cc5703cd ILT |
1800 | || (! mips16 |
1801 | && mips_isa < 4 | |
d8a1c247 | 1802 | && (prev_pinfo |
efec4a28 | 1803 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1804 | & (INSN_LOAD_COPROC_DELAY |
1805 | | INSN_COPROC_MOVE_DELAY | |
1806 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1807 | || (! interlocks |
b2b8c24e ILT |
1808 | && (prev_pinfo |
1809 | & (INSN_READ_LO | |
1810 | | INSN_READ_HI))) | |
cc5703cd ILT |
1811 | || (! mips16 |
1812 | && mips_isa < 2 | |
1aa6938e | 1813 | && (prev_pinfo |
8358c818 | 1814 | & (INSN_LOAD_MEMORY_DELAY |
efec4a28 | 1815 | /* Itbl support may require additional care here. */ |
8358c818 | 1816 | | INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 1817 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1818 | || (prev_pinfo |
6e8dda9c ILT |
1819 | & (INSN_UNCOND_BRANCH_DELAY |
1820 | | INSN_COND_BRANCH_DELAY | |
1821 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1822 | /* We do not swap with a trap instruction, since it |
1823 | complicates trap handlers to have the trap | |
1824 | instruction be in a delay slot. */ | |
1aa6938e | 1825 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1826 | /* If the branch reads a register that the previous |
1827 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1828 | || (! mips16 |
1829 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1830 | && insn_uses_reg (ip, |
1831 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1832 | & OP_MASK_RT), | |
cc5703cd ILT |
1833 | MIPS_GR_REG)) |
1834 | || (! mips16 | |
1835 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1836 | && insn_uses_reg (ip, |
1837 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1838 | & OP_MASK_RD), | |
cc5703cd ILT |
1839 | MIPS_GR_REG)) |
1840 | || (mips16 | |
1841 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1842 | && insn_uses_reg (ip, | |
1843 | ((prev_insn.insn_opcode | |
1844 | >> MIPS16OP_SH_RX) | |
1845 | & MIPS16OP_MASK_RX), | |
1846 | MIPS16_REG)) | |
1847 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1848 | && insn_uses_reg (ip, | |
1849 | ((prev_insn.insn_opcode | |
1850 | >> MIPS16OP_SH_RY) | |
1851 | & MIPS16OP_MASK_RY), | |
1852 | MIPS16_REG)) | |
1853 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1854 | && insn_uses_reg (ip, | |
1855 | ((prev_insn.insn_opcode | |
1856 | >> MIPS16OP_SH_RZ) | |
1857 | & MIPS16OP_MASK_RZ), | |
1858 | MIPS16_REG)) | |
1859 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1860 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1861 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1862 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1863 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1864 | && insn_uses_reg (ip, | |
1865 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1866 | insn_opcode), | |
1867 | MIPS_GR_REG)))) | |
1849d646 ILT |
1868 | /* If the branch writes a register that the previous |
1869 | instruction sets, we can not swap (we know that | |
1870 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1871 | || (! mips16 |
1872 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1873 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1874 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1875 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1876 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1877 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1878 | & OP_MASK_RT) | |
1879 | == 31)))) | |
cc5703cd ILT |
1880 | || (! mips16 |
1881 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1882 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1883 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1884 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1885 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1886 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1887 | & OP_MASK_RD) | |
1888 | == 31)))) | |
cc5703cd ILT |
1889 | || (mips16 |
1890 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1891 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1892 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1893 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1894 | == RA)))) | |
becfe05e ILT |
1895 | /* If the branch writes a register that the previous |
1896 | instruction reads, we can not swap (we know that | |
1897 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1898 | || (! mips16 |
1899 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1900 | && insn_uses_reg (&prev_insn, |
1901 | ((ip->insn_opcode >> OP_SH_RD) | |
1902 | & OP_MASK_RD), | |
cc5703cd ILT |
1903 | MIPS_GR_REG)) |
1904 | || (! mips16 | |
1905 | && (pinfo & INSN_WRITE_GPR_31) | |
1906 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1907 | || (mips16 | |
1908 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1909 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1910 | /* If we are generating embedded PIC code, the branch |
1911 | might be expanded into a sequence which uses $at, so | |
1912 | we can't swap with an instruction which reads it. */ | |
1913 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1914 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1915 | /* If the previous previous instruction has a load |
1916 | delay, and sets a register that the branch reads, we | |
1917 | can not swap. */ | |
cc5703cd ILT |
1918 | || (! mips16 |
1919 | && mips_isa < 4 | |
efec4a28 | 1920 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1921 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1922 | || (mips_isa < 2 | |
1923 | && (prev_prev_insn.insn_mo->pinfo | |
1924 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1925 | && insn_uses_reg (ip, |
1926 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1927 | & OP_MASK_RT), | |
cc5703cd | 1928 | MIPS_GR_REG)) |
d31a3f5e ILT |
1929 | /* If one instruction sets a condition code and the |
1930 | other one uses a condition code, we can not swap. */ | |
1931 | || ((pinfo & INSN_READ_COND_CODE) | |
1932 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1933 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1934 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1935 | /* If the previous instruction uses the PC, we can not | |
1936 | swap. */ | |
1937 | || (mips16 | |
1938 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1939 | /* If the previous instruction was extended, we can not | |
1940 | swap. */ | |
1941 | || (mips16 && prev_insn_extended) | |
1942 | /* If the previous instruction had a fixup in mips16 | |
1943 | mode, we can not swap. This normally means that the | |
1944 | previous instruction was a 4 byte branch anyhow. */ | |
1945 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1946 | { |
1947 | /* We could do even better for unconditional branches to | |
1948 | portions of this object file; we could pick up the | |
1949 | instruction at the destination, put it in the delay | |
1950 | slot, and bump the destination address. */ | |
1951 | emit_nop (); | |
1952 | /* Update the previous insn information. */ | |
1953 | prev_prev_insn = *ip; | |
1954 | prev_insn.insn_mo = &dummy_opcode; | |
1955 | } | |
1956 | else | |
1957 | { | |
becfe05e | 1958 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1959 | if (! mips16) |
1960 | { | |
1961 | char *prev_f; | |
1962 | char temp[4]; | |
1963 | ||
1964 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1965 | memcpy (temp, prev_f, 4); | |
1966 | memcpy (prev_f, f, 4); | |
1967 | memcpy (f, temp, 4); | |
1968 | if (prev_insn_fixp) | |
1969 | { | |
1970 | prev_insn_fixp->fx_frag = frag_now; | |
1971 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1972 | } | |
1973 | if (fixp) | |
1974 | { | |
1975 | fixp->fx_frag = prev_insn_frag; | |
1976 | fixp->fx_where = prev_insn_where; | |
1977 | } | |
1978 | } | |
cc5703cd | 1979 | else |
becfe05e | 1980 | { |
cc5703cd ILT |
1981 | char *prev_f; |
1982 | char temp[2]; | |
1983 | ||
1984 | assert (prev_insn_fixp == NULL); | |
1985 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1986 | memcpy (temp, prev_f, 2); | |
1987 | memcpy (prev_f, f, 2); | |
1988 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
1989 | { |
1990 | assert (reloc_type == BFD_RELOC_UNUSED); | |
1991 | memcpy (f, temp, 2); | |
1992 | } | |
cc5703cd ILT |
1993 | else |
1994 | { | |
1995 | memcpy (f, f + 2, 2); | |
1996 | memcpy (f + 2, temp, 2); | |
1997 | } | |
1998 | if (fixp) | |
1999 | { | |
2000 | fixp->fx_frag = prev_insn_frag; | |
2001 | fixp->fx_where = prev_insn_where; | |
2002 | } | |
becfe05e | 2003 | } |
cc5703cd | 2004 | |
becfe05e ILT |
2005 | /* Update the previous insn information; leave prev_insn |
2006 | unchanged. */ | |
2007 | prev_prev_insn = *ip; | |
2008 | } | |
2009 | prev_insn_is_delay_slot = 1; | |
2010 | ||
2011 | /* If that was an unconditional branch, forget the previous | |
2012 | insn information. */ | |
1aa6938e | 2013 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2014 | { |
2015 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2016 | prev_insn.insn_mo = &dummy_opcode; | |
2017 | } | |
a677feeb ILT |
2018 | |
2019 | prev_insn_fixp = NULL; | |
2020 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2021 | prev_insn_extended = 0; | |
becfe05e | 2022 | } |
1aa6938e | 2023 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2024 | { |
2025 | /* We don't yet optimize a branch likely. What we should do | |
2026 | is look at the target, copy the instruction found there | |
2027 | into the delay slot, and increment the branch to jump to | |
2028 | the next instruction. */ | |
2029 | emit_nop (); | |
2030 | /* Update the previous insn information. */ | |
2031 | prev_prev_insn = *ip; | |
2032 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2033 | prev_insn_fixp = NULL; |
2034 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2035 | prev_insn_extended = 0; | |
8358c818 | 2036 | } |
becfe05e | 2037 | else |
670a50eb | 2038 | { |
becfe05e ILT |
2039 | /* Update the previous insn information. */ |
2040 | if (nops > 0) | |
2041 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2042 | else | |
2043 | prev_prev_insn = prev_insn; | |
2044 | prev_insn = *ip; | |
2045 | ||
2046 | /* Any time we see a branch, we always fill the delay slot | |
2047 | immediately; since this insn is not a branch, we know it | |
2048 | is not in a delay slot. */ | |
2049 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2050 | |
2051 | prev_insn_fixp = fixp; | |
2052 | prev_insn_reloc_type = reloc_type; | |
2053 | if (mips16) | |
2054 | prev_insn_extended = (ip->use_extend | |
2055 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2056 | } |
2057 | ||
4e95866e ILT |
2058 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2059 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2060 | prev_insn_frag = frag_now; |
2061 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2062 | prev_insn_valid = 1; |
2063 | } | |
fbcfacb7 | 2064 | else if (place == NULL) |
a677feeb | 2065 | { |
fbcfacb7 | 2066 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2067 | reordering, in order to determine the base address for mips16 |
2068 | PC relative relocs. */ | |
4a1cb507 | 2069 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2070 | prev_insn = *ip; |
2071 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2072 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2073 | prev_insn_unreordered = 1; | |
a677feeb | 2074 | } |
3d3c5039 | 2075 | |
becfe05e | 2076 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2077 | mips_clear_insn_labels (); |
becfe05e ILT |
2078 | } |
2079 | ||
2080 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2081 | label. If PRESERVE is non-zero, it remembers enough information to |
2082 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2083 | |
2084 | static void | |
4a1cb507 ILT |
2085 | mips_no_prev_insn (preserve) |
2086 | int preserve; | |
becfe05e | 2087 | { |
4a1cb507 ILT |
2088 | if (! preserve) |
2089 | { | |
2090 | prev_insn.insn_mo = &dummy_opcode; | |
2091 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2092 | prev_nop_frag = NULL; | |
2093 | prev_nop_frag_holds = 0; | |
2094 | prev_nop_frag_required = 0; | |
2095 | prev_nop_frag_since = 0; | |
2096 | } | |
becfe05e ILT |
2097 | prev_insn_valid = 0; |
2098 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2099 | prev_insn_unreordered = 0; |
cc5703cd | 2100 | prev_insn_extended = 0; |
a677feeb | 2101 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2102 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2103 | mips_clear_insn_labels (); |
becfe05e ILT |
2104 | } |
2105 | ||
2106 | /* This function must be called whenever we turn on noreorder or emit | |
2107 | something other than instructions. It inserts any NOPS which might | |
2108 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2109 | kept for the previous instructions. The INSNS parameter is true if |
2110 | instructions are to follow. */ | |
becfe05e ILT |
2111 | |
2112 | static void | |
fbcfacb7 ILT |
2113 | mips_emit_delays (insns) |
2114 | boolean insns; | |
becfe05e ILT |
2115 | { |
2116 | if (! mips_noreorder) | |
2117 | { | |
4a1cb507 | 2118 | int nops; |
becfe05e | 2119 | |
4a1cb507 | 2120 | nops = 0; |
cc5703cd ILT |
2121 | if ((! mips16 |
2122 | && mips_isa < 4 | |
344a8d61 JSC |
2123 | && (! cop_interlocks |
2124 | && (prev_insn.insn_mo->pinfo | |
2125 | & (INSN_LOAD_COPROC_DELAY | |
2126 | | INSN_COPROC_MOVE_DELAY | |
2127 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 2128 | || (! interlocks |
b2b8c24e ILT |
2129 | && (prev_insn.insn_mo->pinfo |
2130 | & (INSN_READ_LO | |
2131 | | INSN_READ_HI))) | |
cc5703cd ILT |
2132 | || (! mips16 |
2133 | && mips_isa < 2 | |
8358c818 ILT |
2134 | && (prev_insn.insn_mo->pinfo |
2135 | & (INSN_LOAD_MEMORY_DELAY | |
2136 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e | 2137 | { |
efec4a28 | 2138 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2139 | ++nops; |
cc5703cd ILT |
2140 | if ((! mips16 |
2141 | && mips_isa < 4 | |
344a8d61 JSC |
2142 | && (! cop_interlocks |
2143 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2144 | || (! interlocks |
b2b8c24e ILT |
2145 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2146 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2147 | ++nops; |
2148 | ||
2149 | if (prev_insn_unreordered) | |
2150 | nops = 0; | |
becfe05e | 2151 | } |
cc5703cd ILT |
2152 | else if ((! mips16 |
2153 | && mips_isa < 4 | |
344a8d61 JSC |
2154 | && (! cop_interlocks |
2155 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2156 | || (! interlocks |
b2b8c24e ILT |
2157 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2158 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2159 | { |
efec4a28 | 2160 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2161 | if (! prev_prev_insn_unreordered) |
2162 | ++nops; | |
2163 | } | |
2164 | ||
2165 | if (nops > 0) | |
670a50eb | 2166 | { |
fbcfacb7 ILT |
2167 | struct insn_label_list *l; |
2168 | ||
4a1cb507 ILT |
2169 | if (insns) |
2170 | { | |
2171 | /* Record the frag which holds the nop instructions, so | |
2172 | that we can remove them if we don't need them. */ | |
2173 | frag_grow (mips16 ? nops * 2 : nops * 4); | |
2174 | prev_nop_frag = frag_now; | |
2175 | prev_nop_frag_holds = nops; | |
2176 | prev_nop_frag_required = 0; | |
2177 | prev_nop_frag_since = 0; | |
2178 | } | |
2179 | ||
2180 | for (; nops > 0; --nops) | |
2181 | emit_nop (); | |
2182 | ||
2183 | if (insns) | |
2184 | { | |
2185 | /* Move on to a new frag, so that it is safe to simply | |
2186 | decrease the size of prev_nop_frag. */ | |
2187 | frag_wane (frag_now); | |
2188 | frag_new (0); | |
2189 | } | |
2190 | ||
fbcfacb7 | 2191 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2192 | { |
fbcfacb7 ILT |
2193 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2194 | l->label->sy_frag = frag_now; | |
2195 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2196 | /* mips16 text labels are stored as odd. */ | |
2197 | if (mips16) | |
2198 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2199 | } |
3d3c5039 ILT |
2200 | } |
2201 | } | |
0221ddf7 | 2202 | |
fbcfacb7 ILT |
2203 | /* Mark instruction labels in mips16 mode. This permits the linker |
2204 | to handle them specially, such as generating jalx instructions | |
2205 | when needed. We also make them odd for the duration of the | |
2206 | assembly, in order to generate the right sort of code. We will | |
2207 | make them even in the adjust_symtab routine, while leaving them | |
2208 | marked. This is convenient for the debugger and the | |
2209 | disassembler. The linker knows to make them odd again. */ | |
2210 | if (mips16 && insns) | |
2211 | { | |
2212 | struct insn_label_list *l; | |
2213 | ||
2214 | for (l = insn_labels; l != NULL; l = l->next) | |
2215 | { | |
2216 | #ifdef S_SET_OTHER | |
2217 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2218 | S_SET_OTHER (l->label, STO_MIPS16); | |
2219 | #endif | |
2220 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2221 | ++l->label->sy_value.X_add_number; | |
2222 | } | |
2223 | } | |
2224 | ||
4a1cb507 | 2225 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2226 | } |
2227 | ||
670a50eb ILT |
2228 | /* Build an instruction created by a macro expansion. This is passed |
2229 | a pointer to the count of instructions created so far, an | |
2230 | expression, the name of the instruction to build, an operand format | |
2231 | string, and corresponding arguments. */ | |
2232 | ||
1dc1e798 | 2233 | #ifdef USE_STDARG |
3d3c5039 | 2234 | static void |
0dd2d296 ILT |
2235 | macro_build (char *place, |
2236 | int *counter, | |
670a50eb | 2237 | expressionS * ep, |
3d3c5039 ILT |
2238 | const char *name, |
2239 | const char *fmt, | |
2240 | ...) | |
1dc1e798 | 2241 | #else |
3d3c5039 | 2242 | static void |
0dd2d296 ILT |
2243 | macro_build (place, counter, ep, name, fmt, va_alist) |
2244 | char *place; | |
3d3c5039 ILT |
2245 | int *counter; |
2246 | expressionS *ep; | |
2247 | const char *name; | |
2248 | const char *fmt; | |
2249 | va_dcl | |
1dc1e798 | 2250 | #endif |
3d3c5039 | 2251 | { |
670a50eb ILT |
2252 | struct mips_cl_insn insn; |
2253 | bfd_reloc_code_real_type r; | |
2254 | va_list args; | |
3d3c5039 | 2255 | |
1dc1e798 | 2256 | #ifdef USE_STDARG |
670a50eb | 2257 | va_start (args, fmt); |
3d3c5039 | 2258 | #else |
670a50eb | 2259 | va_start (args); |
3d3c5039 ILT |
2260 | #endif |
2261 | ||
670a50eb ILT |
2262 | /* |
2263 | * If the macro is about to expand into a second instruction, | |
2264 | * print a warning if needed. We need to pass ip as a parameter | |
2265 | * to generate a better warning message here... | |
2266 | */ | |
0dd2d296 | 2267 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2268 | as_warn ("Macro instruction expanded into multiple instructions"); |
2269 | ||
0dd2d296 ILT |
2270 | if (place == NULL) |
2271 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2272 | |
cc5703cd ILT |
2273 | if (mips16) |
2274 | { | |
2275 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2276 | va_end (args); | |
2277 | return; | |
2278 | } | |
2279 | ||
670a50eb ILT |
2280 | r = BFD_RELOC_UNUSED; |
2281 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2282 | assert (insn.insn_mo); | |
2283 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2284 | ||
9226253a | 2285 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2286 | || insn.insn_mo->pinfo == INSN_MACRO |
2287 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2288 | && mips_isa < 2) | |
2289 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2290 | && mips_isa < 3) | |
2291 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2292 | && mips_isa < 4) | |
2293 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2294 | && ! mips_4650) | |
2295 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2296 | && ! mips_4010) | |
2297 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2298 | && ! mips_4100) |
2299 | /* start-sanitize-r5900 */ | |
2300 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2301 | && ! mips_5900) | |
2302 | /* end-sanitize-r5900 */ | |
2303 | ) | |
670a50eb ILT |
2304 | { |
2305 | ++insn.insn_mo; | |
2306 | assert (insn.insn_mo->name); | |
2307 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2308 | } |
670a50eb ILT |
2309 | insn.insn_opcode = insn.insn_mo->match; |
2310 | for (;;) | |
2311 | { | |
2312 | switch (*fmt++) | |
2313 | { | |
3d3c5039 | 2314 | case '\0': |
670a50eb | 2315 | break; |
3d3c5039 ILT |
2316 | |
2317 | case ',': | |
2318 | case '(': | |
2319 | case ')': | |
670a50eb | 2320 | continue; |
3d3c5039 ILT |
2321 | |
2322 | case 't': | |
2323 | case 'w': | |
918692a5 | 2324 | case 'E': |
670a50eb ILT |
2325 | insn.insn_opcode |= va_arg (args, int) << 16; |
2326 | continue; | |
3d3c5039 ILT |
2327 | |
2328 | case 'c': | |
2329 | case 'T': | |
2330 | case 'W': | |
670a50eb ILT |
2331 | insn.insn_opcode |= va_arg (args, int) << 16; |
2332 | continue; | |
3d3c5039 ILT |
2333 | |
2334 | case 'd': | |
918692a5 | 2335 | case 'G': |
670a50eb ILT |
2336 | insn.insn_opcode |= va_arg (args, int) << 11; |
2337 | continue; | |
3d3c5039 ILT |
2338 | |
2339 | case 'V': | |
2340 | case 'S': | |
670a50eb ILT |
2341 | insn.insn_opcode |= va_arg (args, int) << 11; |
2342 | continue; | |
3d3c5039 | 2343 | |
ff3a5c18 ILT |
2344 | case 'z': |
2345 | continue; | |
2346 | ||
3d3c5039 | 2347 | case '<': |
670a50eb ILT |
2348 | insn.insn_opcode |= va_arg (args, int) << 6; |
2349 | continue; | |
3d3c5039 ILT |
2350 | |
2351 | case 'D': | |
670a50eb ILT |
2352 | insn.insn_opcode |= va_arg (args, int) << 6; |
2353 | continue; | |
3d3c5039 | 2354 | |
918692a5 ILT |
2355 | case 'B': |
2356 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2357 | continue; | |
2358 | ||
3d3c5039 ILT |
2359 | case 'b': |
2360 | case 's': | |
2361 | case 'r': | |
2362 | case 'v': | |
670a50eb ILT |
2363 | insn.insn_opcode |= va_arg (args, int) << 21; |
2364 | continue; | |
3d3c5039 ILT |
2365 | |
2366 | case 'i': | |
2367 | case 'j': | |
2368 | case 'o': | |
9226253a | 2369 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2370 | assert (r == BFD_RELOC_MIPS_GPREL |
2371 | || r == BFD_RELOC_MIPS_LITERAL | |
2372 | || r == BFD_RELOC_LO16 | |
2373 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2374 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2375 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2376 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2377 | || (ep->X_op == O_subtract |
2378 | && now_seg == text_section | |
ecd4ca1c | 2379 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2380 | continue; |
3d3c5039 | 2381 | |
6e8dda9c | 2382 | case 'u': |
ecd4ca1c ILT |
2383 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2384 | assert (ep != NULL | |
2385 | && (ep->X_op == O_constant | |
2386 | || (ep->X_op == O_symbol | |
2387 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2388 | || r == BFD_RELOC_HI16 |
2389 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2390 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2391 | || (ep->X_op == O_subtract |
2392 | && now_seg == text_section | |
ecd4ca1c ILT |
2393 | && r == BFD_RELOC_PCREL_HI16_S))); |
2394 | if (ep->X_op == O_constant) | |
2395 | { | |
2396 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2397 | ep = NULL; | |
2398 | r = BFD_RELOC_UNUSED; | |
2399 | } | |
6e8dda9c ILT |
2400 | continue; |
2401 | ||
3d3c5039 | 2402 | case 'p': |
670a50eb ILT |
2403 | assert (ep != NULL); |
2404 | /* | |
2405 | * This allows macro() to pass an immediate expression for | |
2406 | * creating short branches without creating a symbol. | |
2407 | * Note that the expression still might come from the assembly | |
2408 | * input, in which case the value is not checked for range nor | |
2409 | * is a relocation entry generated (yuck). | |
2410 | */ | |
5ac34ac3 | 2411 | if (ep->X_op == O_constant) |
670a50eb ILT |
2412 | { |
2413 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2414 | ep = NULL; | |
2415 | } | |
2416 | else | |
2417 | r = BFD_RELOC_16_PCREL_S2; | |
2418 | continue; | |
3d3c5039 | 2419 | |
9226253a ILT |
2420 | case 'a': |
2421 | assert (ep != NULL); | |
2422 | r = BFD_RELOC_MIPS_JMP; | |
2423 | continue; | |
2424 | ||
3d3c5039 | 2425 | default: |
670a50eb | 2426 | internalError (); |
3d3c5039 | 2427 | } |
670a50eb | 2428 | break; |
3d3c5039 | 2429 | } |
670a50eb ILT |
2430 | va_end (args); |
2431 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2432 | ||
867a58b3 | 2433 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2434 | } |
2435 | ||
cc5703cd ILT |
2436 | static void |
2437 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2438 | char *place; | |
2439 | int *counter; | |
2440 | expressionS *ep; | |
2441 | const char *name; | |
2442 | const char *fmt; | |
2443 | va_list args; | |
2444 | { | |
2445 | struct mips_cl_insn insn; | |
2446 | bfd_reloc_code_real_type r; | |
2447 | ||
2448 | r = BFD_RELOC_UNUSED; | |
2449 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2450 | assert (insn.insn_mo); | |
2451 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2452 | ||
2453 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2454 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2455 | { | |
2456 | ++insn.insn_mo; | |
2457 | assert (insn.insn_mo->name); | |
2458 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2459 | } | |
2460 | ||
2461 | insn.insn_opcode = insn.insn_mo->match; | |
2462 | insn.use_extend = false; | |
2463 | ||
2464 | for (;;) | |
2465 | { | |
2466 | int c; | |
2467 | ||
2468 | c = *fmt++; | |
2469 | switch (c) | |
2470 | { | |
2471 | case '\0': | |
2472 | break; | |
2473 | ||
2474 | case ',': | |
2475 | case '(': | |
2476 | case ')': | |
2477 | continue; | |
2478 | ||
2479 | case 'y': | |
2480 | case 'w': | |
2481 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2482 | continue; | |
2483 | ||
2484 | case 'x': | |
2485 | case 'v': | |
2486 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2487 | continue; | |
2488 | ||
2489 | case 'z': | |
2490 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2491 | continue; | |
2492 | ||
2493 | case 'Z': | |
2494 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2495 | continue; | |
2496 | ||
2497 | case '0': | |
2498 | case 'S': | |
2499 | case 'P': | |
2500 | case 'R': | |
2501 | continue; | |
2502 | ||
2503 | case 'X': | |
2504 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2505 | continue; | |
2506 | ||
2507 | case 'Y': | |
2508 | { | |
2509 | int regno; | |
2510 | ||
2511 | regno = va_arg (args, int); | |
2512 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2513 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2514 | } | |
2515 | continue; | |
2516 | ||
2517 | case '<': | |
2518 | case '>': | |
2519 | case '4': | |
2520 | case '5': | |
2521 | case 'H': | |
2522 | case 'W': | |
2523 | case 'D': | |
2524 | case 'j': | |
2525 | case '8': | |
2526 | case 'V': | |
2527 | case 'C': | |
2528 | case 'U': | |
2529 | case 'k': | |
2530 | case 'K': | |
2531 | case 'p': | |
2532 | case 'q': | |
2533 | { | |
2534 | assert (ep != NULL); | |
2535 | ||
2536 | if (ep->X_op != O_constant) | |
2537 | r = BFD_RELOC_UNUSED + c; | |
2538 | else | |
2539 | { | |
15e69f98 ILT |
2540 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2541 | false, false, &insn.insn_opcode, | |
2542 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2543 | ep = NULL; |
2544 | r = BFD_RELOC_UNUSED; | |
2545 | } | |
2546 | } | |
2547 | continue; | |
2548 | ||
2549 | case '6': | |
2550 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2551 | continue; | |
2552 | } | |
2553 | ||
2554 | break; | |
2555 | } | |
2556 | ||
2557 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2558 | ||
2559 | append_insn (place, &insn, ep, r, false); | |
2560 | } | |
2561 | ||
3d3c5039 ILT |
2562 | /* |
2563 | * Generate a "lui" instruction. | |
2564 | */ | |
2565 | static void | |
0dd2d296 ILT |
2566 | macro_build_lui (place, counter, ep, regnum) |
2567 | char *place; | |
3d3c5039 ILT |
2568 | int *counter; |
2569 | expressionS *ep; | |
2570 | int regnum; | |
2571 | { | |
670a50eb ILT |
2572 | expressionS high_expr; |
2573 | struct mips_cl_insn insn; | |
2574 | bfd_reloc_code_real_type r; | |
2575 | CONST char *name = "lui"; | |
2576 | CONST char *fmt = "t,u"; | |
2577 | ||
cc5703cd ILT |
2578 | assert (! mips16); |
2579 | ||
0dd2d296 ILT |
2580 | if (place == NULL) |
2581 | high_expr = *ep; | |
2582 | else | |
2583 | { | |
2584 | high_expr.X_op = O_constant; | |
fb251650 | 2585 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2586 | } |
670a50eb | 2587 | |
5ac34ac3 | 2588 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2589 | { |
2590 | /* we can compute the instruction now without a relocation entry */ | |
2591 | if (high_expr.X_add_number & 0x8000) | |
2592 | high_expr.X_add_number += 0x10000; | |
2593 | high_expr.X_add_number = | |
2594 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2595 | r = BFD_RELOC_UNUSED; | |
2596 | } | |
2597 | else | |
0dd2d296 ILT |
2598 | { |
2599 | assert (ep->X_op == O_symbol); | |
2600 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2601 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2602 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2603 | r = BFD_RELOC_HI16_S; | |
2604 | } | |
670a50eb ILT |
2605 | |
2606 | /* | |
2607 | * If the macro is about to expand into a second instruction, | |
2608 | * print a warning if needed. We need to pass ip as a parameter | |
2609 | * to generate a better warning message here... | |
2610 | */ | |
0dd2d296 | 2611 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2612 | as_warn ("Macro instruction expanded into multiple instructions"); |
2613 | ||
0dd2d296 ILT |
2614 | if (place == NULL) |
2615 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2616 | |
2617 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2618 | assert (insn.insn_mo); | |
2619 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2620 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2621 | ||
0dd2d296 | 2622 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2623 | if (r == BFD_RELOC_UNUSED) |
2624 | { | |
2625 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2626 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2627 | } |
2628 | else | |
867a58b3 | 2629 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2630 | } |
2631 | ||
2632 | /* set_at() | |
2633 | * Generates code to set the $at register to true (one) | |
2634 | * if reg is less than the immediate expression. | |
2635 | */ | |
2636 | static void | |
6e8dda9c | 2637 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2638 | int *counter; |
2639 | int reg; | |
6e8dda9c | 2640 | int unsignedp; |
3d3c5039 | 2641 | { |
6e8dda9c | 2642 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2643 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2644 | unsignedp ? "sltiu" : "slti", |
9226253a | 2645 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2646 | else |
670a50eb | 2647 | { |
d8a1c247 | 2648 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2649 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2650 | unsignedp ? "sltu" : "slt", |
2651 | "d,v,t", AT, reg, AT); | |
670a50eb | 2652 | } |
3d3c5039 ILT |
2653 | } |
2654 | ||
6e8dda9c | 2655 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2656 | |
2657 | static void | |
19ed8960 | 2658 | check_absolute_expr (ip, ex) |
3d3c5039 | 2659 | struct mips_cl_insn *ip; |
19ed8960 | 2660 | expressionS *ex; |
3d3c5039 | 2661 | { |
19ed8960 | 2662 | if (ex->X_op != O_constant) |
670a50eb | 2663 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2664 | } |
2665 | ||
ff8716f5 JSC |
2666 | /* Count the leading zeroes by performing a binary chop. This is a |
2667 | bulky bit of source, but performance is a LOT better for the | |
2668 | majority of values than a simple loop to count the bits: | |
2669 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2670 | if ((v) & (1 << (31 - lcnt))) | |
2671 | break; | |
2672 | However it is not code size friendly, and the gain will drop a bit | |
2673 | on certain cached systems. | |
2674 | */ | |
2675 | #define COUNT_TOP_ZEROES(v) \ | |
2676 | (((v) & ~0xffff) == 0 \ | |
2677 | ? ((v) & ~0xff) == 0 \ | |
2678 | ? ((v) & ~0xf) == 0 \ | |
2679 | ? ((v) & ~0x3) == 0 \ | |
2680 | ? ((v) & ~0x1) == 0 \ | |
2681 | ? !(v) \ | |
2682 | ? 32 \ | |
2683 | : 31 \ | |
2684 | : 30 \ | |
2685 | : ((v) & ~0x7) == 0 \ | |
2686 | ? 29 \ | |
2687 | : 28 \ | |
2688 | : ((v) & ~0x3f) == 0 \ | |
2689 | ? ((v) & ~0x1f) == 0 \ | |
2690 | ? 27 \ | |
2691 | : 26 \ | |
2692 | : ((v) & ~0x7f) == 0 \ | |
2693 | ? 25 \ | |
2694 | : 24 \ | |
2695 | : ((v) & ~0xfff) == 0 \ | |
2696 | ? ((v) & ~0x3ff) == 0 \ | |
2697 | ? ((v) & ~0x1ff) == 0 \ | |
2698 | ? 23 \ | |
2699 | : 22 \ | |
2700 | : ((v) & ~0x7ff) == 0 \ | |
2701 | ? 21 \ | |
2702 | : 20 \ | |
2703 | : ((v) & ~0x3fff) == 0 \ | |
2704 | ? ((v) & ~0x1fff) == 0 \ | |
2705 | ? 19 \ | |
2706 | : 18 \ | |
2707 | : ((v) & ~0x7fff) == 0 \ | |
2708 | ? 17 \ | |
2709 | : 16 \ | |
2710 | : ((v) & ~0xffffff) == 0 \ | |
2711 | ? ((v) & ~0xfffff) == 0 \ | |
2712 | ? ((v) & ~0x3ffff) == 0 \ | |
2713 | ? ((v) & ~0x1ffff) == 0 \ | |
2714 | ? 15 \ | |
2715 | : 14 \ | |
2716 | : ((v) & ~0x7ffff) == 0 \ | |
2717 | ? 13 \ | |
2718 | : 12 \ | |
2719 | : ((v) & ~0x3fffff) == 0 \ | |
2720 | ? ((v) & ~0x1fffff) == 0 \ | |
2721 | ? 11 \ | |
2722 | : 10 \ | |
2723 | : ((v) & ~0x7fffff) == 0 \ | |
2724 | ? 9 \ | |
2725 | : 8 \ | |
2726 | : ((v) & ~0xfffffff) == 0 \ | |
2727 | ? ((v) & ~0x3ffffff) == 0 \ | |
2728 | ? ((v) & ~0x1ffffff) == 0 \ | |
2729 | ? 7 \ | |
2730 | : 6 \ | |
2731 | : ((v) & ~0x7ffffff) == 0 \ | |
2732 | ? 5 \ | |
2733 | : 4 \ | |
2734 | : ((v) & ~0x3fffffff) == 0 \ | |
2735 | ? ((v) & ~0x1fffffff) == 0 \ | |
2736 | ? 3 \ | |
2737 | : 2 \ | |
2738 | : ((v) & ~0x7fffffff) == 0 \ | |
2739 | ? 1 \ | |
2740 | : 0) | |
2741 | ||
3d3c5039 ILT |
2742 | /* load_register() |
2743 | * This routine generates the least number of instructions neccessary to load | |
2744 | * an absolute expression value into a register. | |
2745 | */ | |
2746 | static void | |
d8a1c247 | 2747 | load_register (counter, reg, ep, dbl) |
670a50eb | 2748 | int *counter; |
670a50eb ILT |
2749 | int reg; |
2750 | expressionS *ep; | |
d8a1c247 | 2751 | int dbl; |
3d3c5039 | 2752 | { |
c36a90ef ILT |
2753 | int freg; |
2754 | expressionS hi32, lo32; | |
847a01cd ILT |
2755 | |
2756 | if (ep->X_op != O_big) | |
6e8dda9c | 2757 | { |
847a01cd | 2758 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2759 | if (ep->X_add_number < 0x8000 |
2760 | && (ep->X_add_number >= 0 | |
2761 | || (ep->X_add_number >= -0x8000 | |
2762 | && (! dbl | |
2763 | || ! ep->X_unsigned | |
2764 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2765 | { |
2766 | /* We can handle 16 bit signed values with an addiu to | |
2767 | $zero. No need to ever use daddiu here, since $zero and | |
2768 | the result are always correct in 32 bit mode. */ | |
2769 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2770 | (int) BFD_RELOC_LO16); | |
2771 | return; | |
2772 | } | |
2773 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2774 | { | |
2775 | /* We can handle 16 bit unsigned values with an ori to | |
2776 | $zero. */ | |
2777 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2778 | (int) BFD_RELOC_LO16); | |
2779 | return; | |
2780 | } | |
98bfd087 ILT |
2781 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2782 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2783 | == ~ (offsetT) 0x7fffffff)) | |
2784 | && (! dbl | |
2785 | || ! ep->X_unsigned | |
2786 | || sizeof (ep->X_add_number) > 4 | |
2787 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2788 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2789 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2790 | { |
2791 | /* 32 bit values require an lui. */ | |
2792 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2793 | (int) BFD_RELOC_HI16); | |
2794 | if ((ep->X_add_number & 0xffff) != 0) | |
2795 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2796 | (int) BFD_RELOC_LO16); | |
2797 | return; | |
2798 | } | |
6e8dda9c | 2799 | } |
847a01cd ILT |
2800 | |
2801 | /* The value is larger than 32 bits. */ | |
2802 | ||
2803 | if (mips_isa < 3) | |
670a50eb | 2804 | { |
6e8dda9c | 2805 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2806 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2807 | (int) BFD_RELOC_LO16); |
847a01cd | 2808 | return; |
6e8dda9c | 2809 | } |
6e8dda9c | 2810 | |
847a01cd ILT |
2811 | if (ep->X_op != O_big) |
2812 | { | |
6e8dda9c | 2813 | hi32 = *ep; |
c36a90ef ILT |
2814 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2815 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2816 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2817 | lo32 = *ep; |
2818 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2819 | } |
847a01cd ILT |
2820 | else |
2821 | { | |
2822 | assert (ep->X_add_number > 2); | |
2823 | if (ep->X_add_number == 3) | |
2824 | generic_bignum[3] = 0; | |
2825 | else if (ep->X_add_number > 4) | |
2826 | as_bad ("Number larger than 64 bits"); | |
2827 | lo32.X_op = O_constant; | |
2828 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2829 | hi32.X_op = O_constant; | |
2830 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2831 | } | |
2832 | ||
d8a1c247 KR |
2833 | if (hi32.X_add_number == 0) |
2834 | freg = 0; | |
2835 | else | |
2836 | { | |
c36a90ef ILT |
2837 | int shift, bit; |
2838 | unsigned long hi, lo; | |
2839 | ||
fb251650 ILT |
2840 | if (hi32.X_add_number == 0xffffffff) |
2841 | { | |
2842 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2843 | { | |
c36a90ef ILT |
2844 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2845 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2846 | return; |
2847 | } | |
2848 | if (lo32.X_add_number & 0x80000000) | |
2849 | { | |
2850 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2851 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2852 | if (lo32.X_add_number & 0xffff) |
2853 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2854 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2855 | return; |
2856 | } | |
2857 | } | |
ff8716f5 | 2858 | |
c36a90ef ILT |
2859 | /* Check for 16bit shifted constant. We know that hi32 is |
2860 | non-zero, so start the mask on the first bit of the hi32 | |
2861 | value. */ | |
ff8716f5 JSC |
2862 | shift = 17; |
2863 | do | |
2864 | { | |
c36a90ef ILT |
2865 | unsigned long himask, lomask; |
2866 | ||
2867 | if (shift < 32) | |
2868 | { | |
2869 | himask = 0xffff >> (32 - shift); | |
2870 | lomask = (0xffff << shift) & 0xffffffff; | |
2871 | } | |
2872 | else | |
2873 | { | |
2874 | himask = 0xffff << (shift - 32); | |
2875 | lomask = 0; | |
2876 | } | |
2877 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2878 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2879 | { | |
2880 | expressionS tmp; | |
2881 | ||
2882 | tmp.X_op = O_constant; | |
2883 | if (shift < 32) | |
2884 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2885 | | (lo32.X_add_number >> shift)); | |
2886 | else | |
2887 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2888 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2889 | (int) BFD_RELOC_LO16); | |
2890 | macro_build ((char *) NULL, counter, NULL, | |
2891 | (shift >= 32) ? "dsll32" : "dsll", | |
2892 | "d,w,<", reg, reg, | |
2893 | (shift >= 32) ? shift - 32 : shift); | |
2894 | return; | |
2895 | } | |
ff8716f5 JSC |
2896 | shift++; |
2897 | } while (shift <= (64 - 16)); | |
2898 | ||
c36a90ef ILT |
2899 | /* Find the bit number of the lowest one bit, and store the |
2900 | shifted value in hi/lo. */ | |
2901 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2902 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2903 | if (lo != 0) | |
2904 | { | |
2905 | bit = 0; | |
2906 | while ((lo & 1) == 0) | |
2907 | { | |
2908 | lo >>= 1; | |
2909 | ++bit; | |
2910 | } | |
2911 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2912 | hi >>= bit; | |
2913 | } | |
2914 | else | |
2915 | { | |
2916 | bit = 32; | |
2917 | while ((hi & 1) == 0) | |
2918 | { | |
2919 | hi >>= 1; | |
2920 | ++bit; | |
2921 | } | |
2922 | lo = hi; | |
2923 | hi = 0; | |
2924 | } | |
2925 | ||
2926 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2927 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2928 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2929 | { |
c36a90ef | 2930 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2931 | if (shift != 0) |
2932 | { | |
c36a90ef ILT |
2933 | expressionS tmp; |
2934 | ||
2935 | /* This instruction will set the register to be all | |
2936 | ones. */ | |
ff8716f5 | 2937 | tmp.X_op = O_constant; |
c36a90ef ILT |
2938 | tmp.X_add_number = (offsetT) -1; |
2939 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2940 | reg, 0, (int) BFD_RELOC_LO16); | |
2941 | if (bit != 0) | |
ff8716f5 | 2942 | { |
c36a90ef | 2943 | bit += shift; |
ff8716f5 | 2944 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2945 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2946 | "d,w,<", reg, reg, |
c36a90ef | 2947 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2948 | } |
c36a90ef ILT |
2949 | macro_build ((char *) NULL, counter, NULL, |
2950 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2951 | "d,w,<", reg, reg, | |
2952 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2953 | return; |
2954 | } | |
2955 | } | |
c36a90ef ILT |
2956 | |
2957 | /* Sign extend hi32 before calling load_register, because we can | |
2958 | generally get better code when we load a sign extended value. */ | |
2959 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2960 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2961 | load_register (counter, reg, &hi32, 0); |
2962 | freg = reg; | |
2963 | } | |
847a01cd | 2964 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2965 | { |
2966 | if (freg != 0) | |
2967 | { | |
2968 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2969 | freg, 0); | |
2970 | freg = reg; | |
2971 | } | |
2972 | } | |
847a01cd ILT |
2973 | else |
2974 | { | |
2975 | expressionS mid16; | |
2976 | ||
fb251650 ILT |
2977 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2978 | { | |
2979 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2980 | (int) BFD_RELOC_HI16); | |
2981 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2982 | reg, 0); |
fb251650 ILT |
2983 | return; |
2984 | } | |
2985 | ||
d8a1c247 KR |
2986 | if (freg != 0) |
2987 | { | |
2988 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2989 | freg, 16); | |
2990 | freg = reg; | |
2991 | } | |
847a01cd ILT |
2992 | mid16 = lo32; |
2993 | mid16.X_add_number >>= 16; | |
2994 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2995 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2996 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2997 | reg, 16); | |
d8a1c247 | 2998 | freg = reg; |
847a01cd ILT |
2999 | } |
3000 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3001 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3002 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3003 | } |
3004 | ||
0dd2d296 ILT |
3005 | /* Load an address into a register. */ |
3006 | ||
3007 | static void | |
3008 | load_address (counter, reg, ep) | |
3009 | int *counter; | |
3010 | int reg; | |
3011 | expressionS *ep; | |
3012 | { | |
3013 | char *p; | |
3014 | ||
3015 | if (ep->X_op != O_constant | |
3016 | && ep->X_op != O_symbol) | |
3017 | { | |
3018 | as_bad ("expression too complex"); | |
3019 | ep->X_op = O_constant; | |
3020 | } | |
3021 | ||
3022 | if (ep->X_op == O_constant) | |
d9aba805 | 3023 | { |
d8a1c247 | 3024 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3025 | return; |
3026 | } | |
3027 | ||
3028 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3029 | { |
3030 | /* If this is a reference to a GP relative symbol, we want | |
3031 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3032 | Otherwise we want | |
04cb3372 | 3033 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3034 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3035 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
3036 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
3037 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
3038 | p = NULL; |
3039 | else | |
3040 | { | |
8ea7f4e8 | 3041 | frag_grow (20); |
0dd2d296 ILT |
3042 | macro_build ((char *) NULL, counter, ep, |
3043 | mips_isa < 3 ? "addiu" : "daddiu", | |
3044 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3045 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 3046 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
3047 | ep->X_add_symbol, (long) 0, (char *) NULL); |
3048 | } | |
3049 | macro_build_lui (p, counter, ep, reg); | |
3050 | if (p != NULL) | |
3051 | p += 4; | |
3052 | macro_build (p, counter, ep, | |
3053 | mips_isa < 3 ? "addiu" : "daddiu", | |
3054 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3055 | } | |
fb251650 | 3056 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3057 | { |
3058 | expressionS ex; | |
3059 | ||
3060 | /* If this is a reference to an external symbol, we want | |
3061 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3062 | Otherwise we want | |
3063 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3064 | nop | |
3065 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3066 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3067 | ex.X_add_number = ep->X_add_number; |
3068 | ep->X_add_number = 0; | |
8ea7f4e8 | 3069 | frag_grow (20); |
0dd2d296 ILT |
3070 | macro_build ((char *) NULL, counter, ep, |
3071 | mips_isa < 3 ? "lw" : "ld", | |
3072 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3073 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3074 | p = frag_var (rs_machine_dependent, 4, 0, | |
3075 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
3076 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
3077 | macro_build (p, counter, ep, | |
3078 | mips_isa < 3 ? "addiu" : "daddiu", | |
3079 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3080 | if (ex.X_add_number != 0) | |
3081 | { | |
3082 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3083 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3084 | ex.X_op = O_constant; | |
fb251650 ILT |
3085 | macro_build ((char *) NULL, counter, &ex, |
3086 | mips_isa < 3 ? "addiu" : "daddiu", | |
3087 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3088 | } | |
3089 | } | |
3090 | else if (mips_pic == SVR4_PIC) | |
3091 | { | |
3092 | expressionS ex; | |
3093 | int off; | |
3094 | ||
3095 | /* This is the large GOT case. If this is a reference to an | |
3096 | external symbol, we want | |
3097 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3098 | addu $reg,$reg,$gp | |
3099 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3100 | Otherwise, for a reference to a local symbol, we want | |
3101 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3102 | nop | |
3103 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3104 | If there is a constant, it must be added in after. */ | |
3105 | ex.X_add_number = ep->X_add_number; | |
3106 | ep->X_add_number = 0; | |
3107 | if (reg_needs_delay (GP)) | |
3108 | off = 4; | |
3109 | else | |
3110 | off = 0; | |
3111 | frag_grow (32); | |
3112 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3113 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3114 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3115 | mips_isa < 3 ? "addu" : "daddu", | |
3116 | "d,v,t", reg, reg, GP); | |
3117 | macro_build ((char *) NULL, counter, ep, | |
3118 | mips_isa < 3 ? "lw" : "ld", | |
3119 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3120 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3121 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3122 | mips_warn_about_macros), | |
3123 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
3124 | if (off > 0) | |
3125 | { | |
3126 | /* We need a nop before loading from $gp. This special | |
3127 | check is required because the lui which starts the main | |
3128 | instruction stream does not refer to $gp, and so will not | |
3129 | insert the nop which may be required. */ | |
3130 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3131 | p += 4; | |
3132 | } | |
3133 | macro_build (p, counter, ep, | |
3134 | mips_isa < 3 ? "lw" : "ld", | |
3135 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3136 | p += 4; | |
3137 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3138 | p += 4; | |
3139 | macro_build (p, counter, ep, | |
3140 | mips_isa < 3 ? "addiu" : "daddiu", | |
3141 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3142 | if (ex.X_add_number != 0) | |
3143 | { | |
3144 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3145 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3146 | ex.X_op = O_constant; | |
3147 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
3148 | mips_isa < 3 ? "addiu" : "daddiu", |
3149 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3150 | } | |
d9aba805 ILT |
3151 | } |
3152 | else if (mips_pic == EMBEDDED_PIC) | |
3153 | { | |
3154 | /* We always do | |
3155 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3156 | */ | |
3157 | macro_build ((char *) NULL, counter, ep, | |
3158 | mips_isa < 3 ? "addiu" : "daddiu", | |
3159 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3160 | } | |
3161 | else | |
3162 | abort (); | |
0dd2d296 ILT |
3163 | } |
3164 | ||
3d3c5039 ILT |
3165 | /* |
3166 | * Build macros | |
3167 | * This routine implements the seemingly endless macro or synthesized | |
3168 | * instructions and addressing modes in the mips assembly language. Many | |
3169 | * of these macros are simple and are similar to each other. These could | |
3170 | * probably be handled by some kind of table or grammer aproach instead of | |
3171 | * this verbose method. Others are not simple macros but are more like | |
3172 | * optimizing code generation. | |
3173 | * One interesting optimization is when several store macros appear | |
3174 | * consecutivly that would load AT with the upper half of the same address. | |
3175 | * The ensuing load upper instructions are ommited. This implies some kind | |
3176 | * of global optimization. We currently only optimize within a single macro. | |
3177 | * For many of the load and store macros if the address is specified as a | |
3178 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3179 | * first load register 'at' with zero and use it as the base register. The | |
3180 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3181 | * we're missing. | |
3182 | */ | |
3183 | static void | |
3184 | macro (ip) | |
3185 | struct mips_cl_insn *ip; | |
3186 | { | |
670a50eb ILT |
3187 | register int treg, sreg, dreg, breg; |
3188 | int tempreg; | |
3189 | int mask; | |
3190 | int icnt = 0; | |
3191 | int used_at; | |
670a50eb ILT |
3192 | expressionS expr1; |
3193 | const char *s; | |
8358c818 | 3194 | const char *s2; |
670a50eb | 3195 | const char *fmt; |
8358c818 ILT |
3196 | int likely = 0; |
3197 | int dbl = 0; | |
3198 | int coproc = 0; | |
b2b8c24e | 3199 | int lr = 0; |
6e8dda9c | 3200 | offsetT maxnum; |
adcf2b9d | 3201 | int off; |
9226253a | 3202 | bfd_reloc_code_real_type r; |
0dd2d296 | 3203 | char *p; |
55933a58 | 3204 | int hold_mips_optimize; |
670a50eb | 3205 | |
cc5703cd ILT |
3206 | assert (! mips16); |
3207 | ||
670a50eb ILT |
3208 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3209 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3210 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3211 | mask = ip->insn_mo->mask; | |
3212 | ||
5ac34ac3 ILT |
3213 | expr1.X_op = O_constant; |
3214 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3215 | expr1.X_add_symbol = NULL; |
3216 | expr1.X_add_number = 1; | |
3217 | ||
3218 | switch (mask) | |
3219 | { | |
6e8dda9c ILT |
3220 | case M_DABS: |
3221 | dbl = 1; | |
3d3c5039 | 3222 | case M_ABS: |
6e8dda9c ILT |
3223 | /* bgez $a0,.+12 |
3224 | move v0,$a0 | |
3225 | sub v0,$zero,$a0 | |
3226 | */ | |
3d3c5039 | 3227 | |
fbcfacb7 | 3228 | mips_emit_delays (true); |
becfe05e | 3229 | ++mips_noreorder; |
0dd2d296 | 3230 | mips_any_noreorder = 1; |
3d3c5039 | 3231 | |
670a50eb | 3232 | expr1.X_add_number = 8; |
0dd2d296 | 3233 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3234 | if (dreg == sreg) |
0dd2d296 | 3235 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3236 | else |
0dd2d296 ILT |
3237 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3238 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3239 | dbl ? "dsub" : "sub", |
3240 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3241 | |
becfe05e | 3242 | --mips_noreorder; |
670a50eb | 3243 | return; |
3d3c5039 ILT |
3244 | |
3245 | case M_ADD_I: | |
8358c818 ILT |
3246 | s = "addi"; |
3247 | s2 = "add"; | |
3248 | goto do_addi; | |
3d3c5039 | 3249 | case M_ADDU_I: |
8358c818 ILT |
3250 | s = "addiu"; |
3251 | s2 = "addu"; | |
3252 | goto do_addi; | |
3253 | case M_DADD_I: | |
6e8dda9c | 3254 | dbl = 1; |
8358c818 ILT |
3255 | s = "daddi"; |
3256 | s2 = "dadd"; | |
3257 | goto do_addi; | |
3258 | case M_DADDU_I: | |
6e8dda9c | 3259 | dbl = 1; |
8358c818 ILT |
3260 | s = "daddiu"; |
3261 | s2 = "daddu"; | |
3262 | do_addi: | |
6e8dda9c | 3263 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3264 | { |
0dd2d296 | 3265 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3266 | (int) BFD_RELOC_LO16); |
670a50eb | 3267 | return; |
3d3c5039 | 3268 | } |
d8a1c247 | 3269 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3270 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3271 | break; |
3d3c5039 ILT |
3272 | |
3273 | case M_AND_I: | |
6e8dda9c ILT |
3274 | s = "andi"; |
3275 | s2 = "and"; | |
3276 | goto do_bit; | |
3d3c5039 | 3277 | case M_OR_I: |
6e8dda9c ILT |
3278 | s = "ori"; |
3279 | s2 = "or"; | |
3280 | goto do_bit; | |
3d3c5039 | 3281 | case M_NOR_I: |
6e8dda9c ILT |
3282 | s = ""; |
3283 | s2 = "nor"; | |
3284 | goto do_bit; | |
3d3c5039 | 3285 | case M_XOR_I: |
6e8dda9c ILT |
3286 | s = "xori"; |
3287 | s2 = "xor"; | |
3288 | do_bit: | |
3289 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3290 | { |
6e8dda9c | 3291 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3292 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3293 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3294 | else |
670a50eb | 3295 | { |
0dd2d296 ILT |
3296 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3297 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3298 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3299 | treg, treg, 0); |
3d3c5039 | 3300 | } |
6e8dda9c | 3301 | return; |
3d3c5039 | 3302 | } |
6e8dda9c | 3303 | |
d8a1c247 | 3304 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3305 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3306 | break; |
3d3c5039 ILT |
3307 | |
3308 | case M_BEQ_I: | |
8358c818 ILT |
3309 | s = "beq"; |
3310 | goto beq_i; | |
3311 | case M_BEQL_I: | |
3312 | s = "beql"; | |
3313 | likely = 1; | |
3314 | goto beq_i; | |
3d3c5039 | 3315 | case M_BNE_I: |
8358c818 ILT |
3316 | s = "bne"; |
3317 | goto beq_i; | |
3318 | case M_BNEL_I: | |
3319 | s = "bnel"; | |
3320 | likely = 1; | |
3321 | beq_i: | |
670a50eb ILT |
3322 | if (imm_expr.X_add_number == 0) |
3323 | { | |
0dd2d296 ILT |
3324 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3325 | 0); | |
670a50eb ILT |
3326 | return; |
3327 | } | |
d8a1c247 | 3328 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3329 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3330 | break; |
3d3c5039 | 3331 | |
8358c818 ILT |
3332 | case M_BGEL: |
3333 | likely = 1; | |
3d3c5039 | 3334 | case M_BGE: |
670a50eb ILT |
3335 | if (treg == 0) |
3336 | { | |
0dd2d296 | 3337 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3338 | likely ? "bgezl" : "bgez", |
3339 | "s,p", sreg); | |
670a50eb | 3340 | return; |
3d3c5039 | 3341 | } |
9a7d824a ILT |
3342 | if (sreg == 0) |
3343 | { | |
0dd2d296 | 3344 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3345 | likely ? "blezl" : "blez", |
3346 | "s,p", treg); | |
9a7d824a ILT |
3347 | return; |
3348 | } | |
0dd2d296 ILT |
3349 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3350 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3351 | likely ? "beql" : "beq", |
3352 | "s,t,p", AT, 0); | |
670a50eb | 3353 | break; |
3d3c5039 | 3354 | |
8358c818 ILT |
3355 | case M_BGTL_I: |
3356 | likely = 1; | |
3d3c5039 | 3357 | case M_BGT_I: |
9a7d824a | 3358 | /* check for > max integer */ |
6e8dda9c ILT |
3359 | maxnum = 0x7fffffff; |
3360 | if (mips_isa >= 3) | |
3361 | { | |
3362 | maxnum <<= 16; | |
3363 | maxnum |= 0xffff; | |
3364 | maxnum <<= 16; | |
3365 | maxnum |= 0xffff; | |
3366 | } | |
7b777690 ILT |
3367 | if (imm_expr.X_add_number >= maxnum |
3368 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3369 | { |
3370 | do_false: | |
3371 | /* result is always false */ | |
8358c818 ILT |
3372 | if (! likely) |
3373 | { | |
3374 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3375 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3376 | } |
3377 | else | |
3378 | { | |
3379 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3380 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3381 | "s,t,p", 0, 0); | |
8358c818 | 3382 | } |
9a7d824a ILT |
3383 | return; |
3384 | } | |
670a50eb ILT |
3385 | imm_expr.X_add_number++; |
3386 | /* FALLTHROUGH */ | |
3d3c5039 | 3387 | case M_BGE_I: |
8358c818 ILT |
3388 | case M_BGEL_I: |
3389 | if (mask == M_BGEL_I) | |
3390 | likely = 1; | |
670a50eb ILT |
3391 | if (imm_expr.X_add_number == 0) |
3392 | { | |
0dd2d296 | 3393 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3394 | likely ? "bgezl" : "bgez", |
3395 | "s,p", sreg); | |
670a50eb | 3396 | return; |
3d3c5039 | 3397 | } |
670a50eb ILT |
3398 | if (imm_expr.X_add_number == 1) |
3399 | { | |
0dd2d296 | 3400 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3401 | likely ? "bgtzl" : "bgtz", |
3402 | "s,p", sreg); | |
670a50eb | 3403 | return; |
3d3c5039 | 3404 | } |
6e8dda9c ILT |
3405 | maxnum = 0x7fffffff; |
3406 | if (mips_isa >= 3) | |
3407 | { | |
3408 | maxnum <<= 16; | |
3409 | maxnum |= 0xffff; | |
3410 | maxnum <<= 16; | |
3411 | maxnum |= 0xffff; | |
3412 | } | |
3413 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3414 | if (imm_expr.X_add_number <= maxnum |
3415 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3416 | { |
3417 | do_true: | |
3418 | /* result is always true */ | |
3419 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3420 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3421 | return; |
3422 | } | |
6e8dda9c | 3423 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3424 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3425 | likely ? "beql" : "beq", |
3426 | "s,t,p", AT, 0); | |
670a50eb | 3427 | break; |
3d3c5039 | 3428 | |
8358c818 ILT |
3429 | case M_BGEUL: |
3430 | likely = 1; | |
3d3c5039 | 3431 | case M_BGEU: |
670a50eb | 3432 | if (treg == 0) |
9a7d824a ILT |
3433 | goto do_true; |
3434 | if (sreg == 0) | |
670a50eb | 3435 | { |
0dd2d296 | 3436 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3437 | likely ? "beql" : "beq", |
3438 | "s,t,p", 0, treg); | |
670a50eb | 3439 | return; |
3d3c5039 | 3440 | } |
0dd2d296 ILT |
3441 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3442 | treg); | |
3443 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3444 | likely ? "beql" : "beq", |
3445 | "s,t,p", AT, 0); | |
670a50eb | 3446 | break; |
3d3c5039 | 3447 | |
8358c818 ILT |
3448 | case M_BGTUL_I: |
3449 | likely = 1; | |
9a7d824a | 3450 | case M_BGTU_I: |
6e8dda9c | 3451 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3452 | goto do_false; |
3453 | imm_expr.X_add_number++; | |
3454 | /* FALLTHROUGH */ | |
3d3c5039 | 3455 | case M_BGEU_I: |
8358c818 ILT |
3456 | case M_BGEUL_I: |
3457 | if (mask == M_BGEUL_I) | |
3458 | likely = 1; | |
670a50eb | 3459 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3460 | goto do_true; |
670a50eb ILT |
3461 | if (imm_expr.X_add_number == 1) |
3462 | { | |
0dd2d296 | 3463 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3464 | likely ? "bnel" : "bne", |
3465 | "s,t,p", sreg, 0); | |
670a50eb | 3466 | return; |
3d3c5039 | 3467 | } |
6e8dda9c | 3468 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3469 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3470 | likely ? "beql" : "beq", |
3471 | "s,t,p", AT, 0); | |
670a50eb | 3472 | break; |
3d3c5039 | 3473 | |
8358c818 ILT |
3474 | case M_BGTL: |
3475 | likely = 1; | |
3d3c5039 | 3476 | case M_BGT: |
670a50eb ILT |
3477 | if (treg == 0) |
3478 | { | |
0dd2d296 | 3479 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3480 | likely ? "bgtzl" : "bgtz", |
3481 | "s,p", sreg); | |
670a50eb | 3482 | return; |
3d3c5039 | 3483 | } |
9a7d824a ILT |
3484 | if (sreg == 0) |
3485 | { | |
0dd2d296 | 3486 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3487 | likely ? "bltzl" : "bltz", |
3488 | "s,p", treg); | |
9a7d824a ILT |
3489 | return; |
3490 | } | |
0dd2d296 ILT |
3491 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3492 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3493 | likely ? "bnel" : "bne", |
3494 | "s,t,p", AT, 0); | |
670a50eb | 3495 | break; |
3d3c5039 | 3496 | |
8358c818 ILT |
3497 | case M_BGTUL: |
3498 | likely = 1; | |
3d3c5039 | 3499 | case M_BGTU: |
670a50eb ILT |
3500 | if (treg == 0) |
3501 | { | |
0dd2d296 | 3502 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3503 | likely ? "bnel" : "bne", |
3504 | "s,t,p", sreg, 0); | |
670a50eb | 3505 | return; |
3d3c5039 | 3506 | } |
9a7d824a ILT |
3507 | if (sreg == 0) |
3508 | goto do_false; | |
0dd2d296 ILT |
3509 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3510 | sreg); | |
3511 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3512 | likely ? "bnel" : "bne", |
3513 | "s,t,p", AT, 0); | |
670a50eb | 3514 | break; |
3d3c5039 | 3515 | |
8358c818 ILT |
3516 | case M_BLEL: |
3517 | likely = 1; | |
3d3c5039 | 3518 | case M_BLE: |
670a50eb ILT |
3519 | if (treg == 0) |
3520 | { | |
0dd2d296 | 3521 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3522 | likely ? "blezl" : "blez", |
3523 | "s,p", sreg); | |
670a50eb ILT |
3524 | return; |
3525 | } | |
9a7d824a ILT |
3526 | if (sreg == 0) |
3527 | { | |
0dd2d296 | 3528 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3529 | likely ? "bgezl" : "bgez", |
3530 | "s,p", treg); | |
9a7d824a ILT |
3531 | return; |
3532 | } | |
0dd2d296 ILT |
3533 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3534 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3535 | likely ? "beql" : "beq", |
3536 | "s,t,p", AT, 0); | |
670a50eb | 3537 | break; |
3d3c5039 | 3538 | |
8358c818 ILT |
3539 | case M_BLEL_I: |
3540 | likely = 1; | |
3d3c5039 | 3541 | case M_BLE_I: |
6e8dda9c ILT |
3542 | maxnum = 0x7fffffff; |
3543 | if (mips_isa >= 3) | |
3544 | { | |
3545 | maxnum <<= 16; | |
3546 | maxnum |= 0xffff; | |
3547 | maxnum <<= 16; | |
3548 | maxnum |= 0xffff; | |
3549 | } | |
7b777690 ILT |
3550 | if (imm_expr.X_add_number >= maxnum |
3551 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3552 | goto do_true; |
3553 | imm_expr.X_add_number++; | |
3554 | /* FALLTHROUGH */ | |
9a7d824a | 3555 | case M_BLT_I: |
8358c818 ILT |
3556 | case M_BLTL_I: |
3557 | if (mask == M_BLTL_I) | |
3558 | likely = 1; | |
670a50eb ILT |
3559 | if (imm_expr.X_add_number == 0) |
3560 | { | |
0dd2d296 | 3561 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3562 | likely ? "bltzl" : "bltz", |
3563 | "s,p", sreg); | |
670a50eb ILT |
3564 | return; |
3565 | } | |
9a7d824a | 3566 | if (imm_expr.X_add_number == 1) |
670a50eb | 3567 | { |
0dd2d296 | 3568 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3569 | likely ? "blezl" : "blez", |
3570 | "s,p", sreg); | |
670a50eb ILT |
3571 | return; |
3572 | } | |
6e8dda9c | 3573 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3574 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3575 | likely ? "bnel" : "bne", |
3576 | "s,t,p", AT, 0); | |
670a50eb | 3577 | break; |
3d3c5039 | 3578 | |
8358c818 ILT |
3579 | case M_BLEUL: |
3580 | likely = 1; | |
3d3c5039 | 3581 | case M_BLEU: |
670a50eb ILT |
3582 | if (treg == 0) |
3583 | { | |
0dd2d296 | 3584 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3585 | likely ? "beql" : "beq", |
3586 | "s,t,p", sreg, 0); | |
670a50eb | 3587 | return; |
3d3c5039 | 3588 | } |
9a7d824a ILT |
3589 | if (sreg == 0) |
3590 | goto do_true; | |
0dd2d296 ILT |
3591 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3592 | sreg); | |
3593 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3594 | likely ? "beql" : "beq", |
3595 | "s,t,p", AT, 0); | |
670a50eb | 3596 | break; |
3d3c5039 | 3597 | |
8358c818 ILT |
3598 | case M_BLEUL_I: |
3599 | likely = 1; | |
3d3c5039 | 3600 | case M_BLEU_I: |
6e8dda9c | 3601 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3602 | goto do_true; |
3603 | imm_expr.X_add_number++; | |
3604 | /* FALLTHROUGH */ | |
9a7d824a | 3605 | case M_BLTU_I: |
8358c818 ILT |
3606 | case M_BLTUL_I: |
3607 | if (mask == M_BLTUL_I) | |
3608 | likely = 1; | |
670a50eb | 3609 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3610 | goto do_false; |
3611 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3612 | { |
0dd2d296 | 3613 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3614 | likely ? "beql" : "beq", |
3615 | "s,t,p", sreg, 0); | |
670a50eb | 3616 | return; |
3d3c5039 | 3617 | } |
6e8dda9c | 3618 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3619 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3620 | likely ? "bnel" : "bne", |
3621 | "s,t,p", AT, 0); | |
670a50eb | 3622 | break; |
3d3c5039 | 3623 | |
8358c818 ILT |
3624 | case M_BLTL: |
3625 | likely = 1; | |
3d3c5039 | 3626 | case M_BLT: |
670a50eb ILT |
3627 | if (treg == 0) |
3628 | { | |
0dd2d296 | 3629 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3630 | likely ? "bltzl" : "bltz", |
3631 | "s,p", sreg); | |
670a50eb | 3632 | return; |
3d3c5039 | 3633 | } |
9a7d824a | 3634 | if (sreg == 0) |
670a50eb | 3635 | { |
0dd2d296 | 3636 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3637 | likely ? "bgtzl" : "bgtz", |
3638 | "s,p", treg); | |
670a50eb | 3639 | return; |
3d3c5039 | 3640 | } |
0dd2d296 ILT |
3641 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3642 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3643 | likely ? "bnel" : "bne", |
3644 | "s,t,p", AT, 0); | |
670a50eb | 3645 | break; |
3d3c5039 | 3646 | |
8358c818 ILT |
3647 | case M_BLTUL: |
3648 | likely = 1; | |
3d3c5039 | 3649 | case M_BLTU: |
670a50eb | 3650 | if (treg == 0) |
9a7d824a ILT |
3651 | goto do_false; |
3652 | if (sreg == 0) | |
670a50eb | 3653 | { |
0dd2d296 | 3654 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3655 | likely ? "bnel" : "bne", |
3656 | "s,t,p", 0, treg); | |
670a50eb ILT |
3657 | return; |
3658 | } | |
0dd2d296 ILT |
3659 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3660 | treg); | |
3661 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3662 | likely ? "bnel" : "bne", |
3663 | "s,t,p", AT, 0); | |
670a50eb | 3664 | break; |
3d3c5039 | 3665 | |
8358c818 ILT |
3666 | case M_DDIV_3: |
3667 | dbl = 1; | |
3d3c5039 | 3668 | case M_DIV_3: |
8358c818 ILT |
3669 | s = "mflo"; |
3670 | goto do_div3; | |
3671 | case M_DREM_3: | |
3672 | dbl = 1; | |
3d3c5039 | 3673 | case M_REM_3: |
8358c818 ILT |
3674 | s = "mfhi"; |
3675 | do_div3: | |
670a50eb ILT |
3676 | if (treg == 0) |
3677 | { | |
3678 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3679 | if (mips_trap) |
3680 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3681 | else | |
3682 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3683 | return; |
3684 | } | |
3685 | ||
fbcfacb7 | 3686 | mips_emit_delays (true); |
becfe05e | 3687 | ++mips_noreorder; |
0dd2d296 ILT |
3688 | mips_any_noreorder = 1; |
3689 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3690 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3691 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3692 | if (mips_trap) |
3693 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3694 | else | |
3695 | { | |
3696 | expr1.X_add_number = 8; | |
3697 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3698 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3699 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3700 | } | |
670a50eb | 3701 | expr1.X_add_number = -1; |
0dd2d296 | 3702 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3703 | dbl ? "daddiu" : "addiu", |
9226253a | 3704 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3705 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3706 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3707 | if (dbl) |
3708 | { | |
3709 | expr1.X_add_number = 1; | |
0dd2d296 | 3710 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3711 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3712 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3713 | 31); | |
8358c818 ILT |
3714 | } |
3715 | else | |
3716 | { | |
3717 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3718 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3719 | (int) BFD_RELOC_HI16); | |
8358c818 | 3720 | } |
8ea7f4e8 ILT |
3721 | if (mips_trap) |
3722 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3723 | else | |
3724 | { | |
3725 | expr1.X_add_number = 8; | |
3726 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3727 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3728 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3729 | } | |
becfe05e | 3730 | --mips_noreorder; |
0dd2d296 | 3731 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3732 | break; |
3d3c5039 ILT |
3733 | |
3734 | case M_DIV_3I: | |
8358c818 ILT |
3735 | s = "div"; |
3736 | s2 = "mflo"; | |
3737 | goto do_divi; | |
3d3c5039 | 3738 | case M_DIVU_3I: |
8358c818 ILT |
3739 | s = "divu"; |
3740 | s2 = "mflo"; | |
3741 | goto do_divi; | |
3d3c5039 | 3742 | case M_REM_3I: |
8358c818 ILT |
3743 | s = "div"; |
3744 | s2 = "mfhi"; | |
3745 | goto do_divi; | |
3d3c5039 | 3746 | case M_REMU_3I: |
8358c818 ILT |
3747 | s = "divu"; |
3748 | s2 = "mfhi"; | |
3749 | goto do_divi; | |
3750 | case M_DDIV_3I: | |
3751 | dbl = 1; | |
3752 | s = "ddiv"; | |
3753 | s2 = "mflo"; | |
3754 | goto do_divi; | |
3755 | case M_DDIVU_3I: | |
3756 | dbl = 1; | |
3757 | s = "ddivu"; | |
3758 | s2 = "mflo"; | |
3759 | goto do_divi; | |
3760 | case M_DREM_3I: | |
3761 | dbl = 1; | |
3762 | s = "ddiv"; | |
3763 | s2 = "mfhi"; | |
3764 | goto do_divi; | |
3765 | case M_DREMU_3I: | |
3766 | dbl = 1; | |
3767 | s = "ddivu"; | |
3768 | s2 = "mfhi"; | |
3769 | do_divi: | |
670a50eb ILT |
3770 | if (imm_expr.X_add_number == 0) |
3771 | { | |
3772 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3773 | if (mips_trap) |
3774 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3775 | else | |
3776 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3777 | return; |
3778 | } | |
3779 | if (imm_expr.X_add_number == 1) | |
3780 | { | |
8358c818 | 3781 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3782 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3783 | sreg); | |
3d3c5039 | 3784 | else |
0dd2d296 | 3785 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3786 | return; |
3787 | } | |
8358c818 ILT |
3788 | if (imm_expr.X_add_number == -1 |
3789 | && s[strlen (s) - 1] != 'u') | |
3790 | { | |
3791 | if (strcmp (s2, "mflo") == 0) | |
3792 | { | |
3793 | if (dbl) | |
0dd2d296 ILT |
3794 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3795 | sreg); | |
8358c818 | 3796 | else |
0dd2d296 ILT |
3797 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3798 | sreg); | |
8358c818 ILT |
3799 | } |
3800 | else | |
0dd2d296 | 3801 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3802 | return; |
3803 | } | |
3d3c5039 | 3804 | |
d8a1c247 | 3805 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3806 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3807 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3808 | break; |
3809 | ||
3810 | case M_DIVU_3: | |
8358c818 ILT |
3811 | s = "divu"; |
3812 | s2 = "mflo"; | |
3813 | goto do_divu3; | |
670a50eb | 3814 | case M_REMU_3: |
8358c818 ILT |
3815 | s = "divu"; |
3816 | s2 = "mfhi"; | |
3817 | goto do_divu3; | |
3818 | case M_DDIVU_3: | |
3819 | s = "ddivu"; | |
3820 | s2 = "mflo"; | |
3821 | goto do_divu3; | |
3822 | case M_DREMU_3: | |
3823 | s = "ddivu"; | |
3824 | s2 = "mfhi"; | |
3825 | do_divu3: | |
fbcfacb7 | 3826 | mips_emit_delays (true); |
becfe05e | 3827 | ++mips_noreorder; |
0dd2d296 ILT |
3828 | mips_any_noreorder = 1; |
3829 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3830 | if (mips_trap) |
3831 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3832 | else | |
3833 | { | |
3834 | expr1.X_add_number = 8; | |
3835 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3836 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3837 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3838 | } | |
becfe05e | 3839 | --mips_noreorder; |
0dd2d296 | 3840 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3841 | return; |
3d3c5039 | 3842 | |
d8a1c247 KR |
3843 | case M_DLA_AB: |
3844 | dbl = 1; | |
0dd2d296 | 3845 | case M_LA_AB: |
d9aba805 ILT |
3846 | /* Load the address of a symbol into a register. If breg is not |
3847 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3848 | |
3849 | /* When generating embedded PIC code, we permit expressions of | |
3850 | the form | |
3851 | la $4,foo-bar | |
3852 | where bar is an address in the .text section. These are used | |
3853 | when getting the addresses of functions. We don't permit | |
3854 | X_add_number to be non-zero, because if the symbol is | |
3855 | external the relaxing code needs to know that any addend is | |
3856 | purely the offset to X_op_symbol. */ | |
3857 | if (mips_pic == EMBEDDED_PIC | |
3858 | && offset_expr.X_op == O_subtract | |
3859 | && now_seg == text_section | |
847a01cd ILT |
3860 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3861 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3862 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3863 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3864 | ->sy_value.X_add_symbol) | |
3865 | == text_section))) | |
ecd4ca1c ILT |
3866 | && breg == 0 |
3867 | && offset_expr.X_add_number == 0) | |
3868 | { | |
3869 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3870 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3871 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3872 | mips_isa < 3 ? "addiu" : "daddiu", | |
3873 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3874 | return; | |
3875 | } | |
3876 | ||
0dd2d296 ILT |
3877 | if (offset_expr.X_op != O_symbol |
3878 | && offset_expr.X_op != O_constant) | |
670a50eb | 3879 | { |
0dd2d296 ILT |
3880 | as_bad ("expression too complex"); |
3881 | offset_expr.X_op = O_constant; | |
3882 | } | |
3883 | ||
3884 | if (treg == breg) | |
3885 | { | |
3886 | tempreg = AT; | |
3887 | used_at = 1; | |
3d3c5039 | 3888 | } |
670a50eb ILT |
3889 | else |
3890 | { | |
0dd2d296 ILT |
3891 | tempreg = treg; |
3892 | used_at = 0; | |
670a50eb | 3893 | } |
3d3c5039 | 3894 | |
5ac34ac3 | 3895 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3896 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3897 | else if (mips_pic == NO_PIC) |
670a50eb | 3898 | { |
0dd2d296 ILT |
3899 | /* If this is a reference to an GP relative symbol, we want |
3900 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3901 | Otherwise we want | |
3902 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3903 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3904 | If we have a constant, we need two instructions anyhow, | |
3905 | so we may as well always use the latter form. */ | |
7a15a226 | 3906 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3907 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3908 | p = NULL; |
3909 | else | |
3910 | { | |
8ea7f4e8 | 3911 | frag_grow (20); |
0dd2d296 ILT |
3912 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3913 | mips_isa < 3 ? "addiu" : "daddiu", | |
3914 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3915 | p = frag_var (rs_machine_dependent, 8, 0, | |
3916 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3917 | mips_warn_about_macros), | |
3918 | offset_expr.X_add_symbol, (long) 0, | |
3919 | (char *) NULL); | |
3920 | } | |
3921 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3922 | if (p != NULL) | |
3923 | p += 4; | |
3924 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3925 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3926 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3927 | } | |
fb251650 | 3928 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3929 | { |
3930 | /* If this is a reference to an external symbol, and there | |
3931 | is no constant, we want | |
3932 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3933 | For a local symbol, we want | |
3934 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3935 | nop | |
3936 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3937 | ||
3938 | If we have a small constant, and this is a reference to | |
3939 | an external symbol, we want | |
3940 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3941 | nop | |
3942 | addiu $tempreg,$tempreg,<constant> | |
3943 | For a local symbol, we want the same instruction | |
3944 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3945 | addiu instruction. | |
3946 | ||
3947 | If we have a large constant, and this is a reference to | |
3948 | an external symbol, we want | |
3949 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3950 | lui $at,<hiconstant> | |
3951 | addiu $at,$at,<loconstant> | |
3952 | addu $tempreg,$tempreg,$at | |
3953 | For a local symbol, we want the same instruction | |
3954 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3955 | addiu instruction. */ | |
3956 | expr1.X_add_number = offset_expr.X_add_number; | |
3957 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3958 | frag_grow (32); |
0dd2d296 | 3959 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3960 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3961 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3962 | if (expr1.X_add_number == 0) | |
3963 | { | |
3964 | int off; | |
3965 | ||
3966 | if (breg == 0) | |
3967 | off = 0; | |
3968 | else | |
3969 | { | |
3970 | /* We're going to put in an addu instruction using | |
3971 | tempreg, so we may as well insert the nop right | |
3972 | now. */ | |
3973 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3974 | "nop", ""); | |
3975 | off = 4; | |
3976 | } | |
3977 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3978 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3979 | (breg == 0 | |
3980 | ? mips_warn_about_macros | |
3981 | : 0)), | |
3982 | offset_expr.X_add_symbol, (long) 0, | |
3983 | (char *) NULL); | |
3984 | if (breg == 0) | |
3985 | { | |
3986 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3987 | p += 4; | |
3988 | } | |
3989 | macro_build (p, &icnt, &expr1, | |
3990 | mips_isa < 3 ? "addiu" : "daddiu", | |
3991 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3992 | /* FIXME: If breg == 0, and the next instruction uses | |
3993 | $tempreg, then if this variant case is used an extra | |
3994 | nop will be generated. */ | |
3995 | } | |
3996 | else if (expr1.X_add_number >= -0x8000 | |
3997 | && expr1.X_add_number < 0x8000) | |
3998 | { | |
3999 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4000 | "nop", ""); | |
4001 | macro_build ((char *) NULL, &icnt, &expr1, | |
4002 | mips_isa < 3 ? "addiu" : "daddiu", | |
4003 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4004 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4005 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4006 | offset_expr.X_add_symbol, (long) 0, | |
4007 | (char *) NULL); | |
4008 | } | |
4009 | else | |
4010 | { | |
4011 | int off1; | |
4012 | ||
4013 | /* If we are going to add in a base register, and the | |
4014 | target register and the base register are the same, | |
4015 | then we are using AT as a temporary register. Since | |
4016 | we want to load the constant into AT, we add our | |
4017 | current AT (from the global offset table) and the | |
4018 | register into the register now, and pretend we were | |
4019 | not using a base register. */ | |
4020 | if (breg != treg) | |
4021 | off1 = 0; | |
4022 | else | |
4023 | { | |
4024 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4025 | "nop", ""); | |
4026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4027 | mips_isa < 3 ? "addu" : "daddu", | |
4028 | "d,v,t", treg, AT, breg); | |
4029 | breg = 0; | |
4030 | tempreg = treg; | |
4031 | off1 = -8; | |
4032 | } | |
4033 | ||
55933a58 ILT |
4034 | /* Set mips_optimize around the lui instruction to avoid |
4035 | inserting an unnecessary nop after the lw. */ | |
4036 | hold_mips_optimize = mips_optimize; | |
4037 | mips_optimize = 2; | |
0dd2d296 | 4038 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4039 | mips_optimize = hold_mips_optimize; |
4040 | ||
0dd2d296 ILT |
4041 | macro_build ((char *) NULL, &icnt, &expr1, |
4042 | mips_isa < 3 ? "addiu" : "daddiu", | |
4043 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4045 | mips_isa < 3 ? "addu" : "daddu", | |
4046 | "d,v,t", tempreg, tempreg, AT); | |
4047 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4048 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4049 | offset_expr.X_add_symbol, (long) 0, | |
4050 | (char *) NULL); | |
4051 | used_at = 1; | |
4052 | } | |
670a50eb | 4053 | } |
fb251650 ILT |
4054 | else if (mips_pic == SVR4_PIC) |
4055 | { | |
4056 | int gpdel; | |
4057 | ||
4058 | /* This is the large GOT case. If this is a reference to an | |
4059 | external symbol, and there is no constant, we want | |
4060 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4061 | addu $tempreg,$tempreg,$gp | |
4062 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4063 | For a local symbol, we want | |
4064 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4065 | nop | |
4066 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4067 | ||
4068 | If we have a small constant, and this is a reference to | |
4069 | an external symbol, we want | |
4070 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4071 | addu $tempreg,$tempreg,$gp | |
4072 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4073 | nop | |
4074 | addiu $tempreg,$tempreg,<constant> | |
4075 | For a local symbol, we want | |
4076 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4077 | nop | |
4078 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4079 | ||
4080 | If we have a large constant, and this is a reference to | |
4081 | an external symbol, we want | |
4082 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4083 | addu $tempreg,$tempreg,$gp | |
4084 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4085 | lui $at,<hiconstant> | |
4086 | addiu $at,$at,<loconstant> | |
4087 | addu $tempreg,$tempreg,$at | |
4088 | For a local symbol, we want | |
4089 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4090 | lui $at,<hiconstant> | |
4091 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4092 | addu $tempreg,$tempreg,$at | |
4093 | */ | |
4094 | expr1.X_add_number = offset_expr.X_add_number; | |
4095 | offset_expr.X_add_number = 0; | |
4096 | frag_grow (52); | |
4097 | if (reg_needs_delay (GP)) | |
4098 | gpdel = 4; | |
4099 | else | |
4100 | gpdel = 0; | |
4101 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4102 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4103 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4104 | mips_isa < 3 ? "addu" : "daddu", | |
4105 | "d,v,t", tempreg, tempreg, GP); | |
4106 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4107 | dbl ? "ld" : "lw", | |
4108 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4109 | tempreg); | |
4110 | if (expr1.X_add_number == 0) | |
4111 | { | |
4112 | int off; | |
4113 | ||
4114 | if (breg == 0) | |
4115 | off = 0; | |
4116 | else | |
4117 | { | |
4118 | /* We're going to put in an addu instruction using | |
4119 | tempreg, so we may as well insert the nop right | |
4120 | now. */ | |
4121 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4122 | "nop", ""); | |
4123 | off = 4; | |
4124 | } | |
4125 | ||
4126 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4127 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4128 | 8 + gpdel, 0, | |
4129 | (breg == 0 | |
4130 | ? mips_warn_about_macros | |
4131 | : 0)), | |
4132 | offset_expr.X_add_symbol, (long) 0, | |
4133 | (char *) NULL); | |
4134 | } | |
4135 | else if (expr1.X_add_number >= -0x8000 | |
4136 | && expr1.X_add_number < 0x8000) | |
4137 | { | |
4138 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4139 | "nop", ""); | |
4140 | macro_build ((char *) NULL, &icnt, &expr1, | |
4141 | mips_isa < 3 ? "addiu" : "daddiu", | |
4142 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4143 | ||
4144 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4145 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4146 | (breg == 0 | |
4147 | ? mips_warn_about_macros | |
4148 | : 0)), | |
4149 | offset_expr.X_add_symbol, (long) 0, | |
4150 | (char *) NULL); | |
4151 | } | |
4152 | else | |
4153 | { | |
4154 | int adj, dreg; | |
4155 | ||
4156 | /* If we are going to add in a base register, and the | |
4157 | target register and the base register are the same, | |
4158 | then we are using AT as a temporary register. Since | |
4159 | we want to load the constant into AT, we add our | |
4160 | current AT (from the global offset table) and the | |
4161 | register into the register now, and pretend we were | |
4162 | not using a base register. */ | |
4163 | if (breg != treg) | |
4164 | { | |
4165 | adj = 0; | |
4166 | dreg = tempreg; | |
4167 | } | |
4168 | else | |
4169 | { | |
4170 | assert (tempreg == AT); | |
4171 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4172 | "nop", ""); | |
4173 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4174 | mips_isa < 3 ? "addu" : "daddu", | |
4175 | "d,v,t", treg, AT, breg); | |
4176 | dreg = treg; | |
4177 | adj = 8; | |
4178 | } | |
4179 | ||
4180 | /* Set mips_optimize around the lui instruction to avoid | |
4181 | inserting an unnecessary nop after the lw. */ | |
4182 | hold_mips_optimize = mips_optimize; | |
4183 | mips_optimize = 2; | |
4184 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4185 | mips_optimize = hold_mips_optimize; | |
4186 | ||
4187 | macro_build ((char *) NULL, &icnt, &expr1, | |
4188 | mips_isa < 3 ? "addiu" : "daddiu", | |
4189 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4190 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4191 | mips_isa < 3 ? "addu" : "daddu", | |
4192 | "d,v,t", dreg, dreg, AT); | |
4193 | ||
4194 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4195 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4196 | 8 + gpdel, 0, | |
4197 | (breg == 0 | |
4198 | ? mips_warn_about_macros | |
4199 | : 0)), | |
4200 | offset_expr.X_add_symbol, (long) 0, | |
4201 | (char *) NULL); | |
4202 | ||
4203 | used_at = 1; | |
4204 | } | |
4205 | ||
4206 | if (gpdel > 0) | |
4207 | { | |
4208 | /* This is needed because this instruction uses $gp, but | |
4209 | the first instruction on the main stream does not. */ | |
4210 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4211 | p += 4; | |
4212 | } | |
4213 | macro_build (p, &icnt, &offset_expr, | |
4214 | dbl ? "ld" : "lw", | |
4215 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4216 | p += 4; | |
4217 | if (expr1.X_add_number >= -0x8000 | |
4218 | && expr1.X_add_number < 0x8000) | |
4219 | { | |
4220 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4221 | p += 4; | |
4222 | macro_build (p, &icnt, &expr1, | |
4223 | mips_isa < 3 ? "addiu" : "daddiu", | |
4224 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4225 | /* FIXME: If add_number is 0, and there was no base | |
4226 | register, the external symbol case ended with a load, | |
4227 | so if the symbol turns out to not be external, and | |
4228 | the next instruction uses tempreg, an unnecessary nop | |
4229 | will be inserted. */ | |
4230 | } | |
4231 | else | |
4232 | { | |
4233 | if (breg == treg) | |
4234 | { | |
4235 | /* We must add in the base register now, as in the | |
4236 | external symbol case. */ | |
4237 | assert (tempreg == AT); | |
4238 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4239 | p += 4; | |
4240 | macro_build (p, &icnt, (expressionS *) NULL, | |
4241 | mips_isa < 3 ? "addu" : "daddu", | |
4242 | "d,v,t", treg, AT, breg); | |
4243 | p += 4; | |
4244 | tempreg = treg; | |
4245 | /* We set breg to 0 because we have arranged to add | |
4246 | it in in both cases. */ | |
4247 | breg = 0; | |
4248 | } | |
4249 | ||
4250 | macro_build_lui (p, &icnt, &expr1, AT); | |
4251 | p += 4; | |
4252 | macro_build (p, &icnt, &expr1, | |
4253 | mips_isa < 3 ? "addiu" : "daddiu", | |
4254 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4255 | p += 4; | |
4256 | macro_build (p, &icnt, (expressionS *) NULL, | |
4257 | mips_isa < 3 ? "addu" : "daddu", | |
4258 | "d,v,t", tempreg, tempreg, AT); | |
4259 | p += 4; | |
4260 | } | |
4261 | } | |
d9aba805 ILT |
4262 | else if (mips_pic == EMBEDDED_PIC) |
4263 | { | |
4264 | /* We use | |
4265 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4266 | */ | |
4267 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4268 | mips_isa < 3 ? "addiu" : "daddiu", | |
4269 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4270 | } | |
4271 | else | |
4272 | abort (); | |
0dd2d296 | 4273 | |
670a50eb | 4274 | if (breg != 0) |
0dd2d296 ILT |
4275 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4276 | mips_isa < 3 ? "addu" : "daddu", | |
4277 | "d,v,t", treg, tempreg, breg); | |
4278 | ||
4279 | if (! used_at) | |
4280 | return; | |
4281 | ||
4282 | break; | |
4283 | ||
4284 | case M_J_A: | |
4285 | /* The j instruction may not be used in PIC code, since it | |
4286 | requires an absolute address. We convert it to a b | |
4287 | instruction. */ | |
d9aba805 | 4288 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4289 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4290 | else | |
4291 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4292 | return; |
3d3c5039 | 4293 | |
9226253a ILT |
4294 | /* The jal instructions must be handled as macros because when |
4295 | generating PIC code they expand to multi-instruction | |
4296 | sequences. Normally they are simple instructions. */ | |
4297 | case M_JAL_1: | |
4298 | dreg = RA; | |
4299 | /* Fall through. */ | |
4300 | case M_JAL_2: | |
d9aba805 ILT |
4301 | if (mips_pic == NO_PIC |
4302 | || mips_pic == EMBEDDED_PIC) | |
4303 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4304 | "d,s", dreg, sreg); | |
4305 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4306 | { |
d9aba805 ILT |
4307 | if (sreg != PIC_CALL_REG) |
4308 | as_warn ("MIPS PIC call to register other than $25"); | |
4309 | ||
0dd2d296 ILT |
4310 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4311 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4312 | if (mips_cprestore_offset < 0) |
4313 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4314 | else | |
4315 | { | |
4316 | expr1.X_add_number = mips_cprestore_offset; | |
4317 | macro_build ((char *) NULL, &icnt, &expr1, | |
4318 | mips_isa < 3 ? "lw" : "ld", | |
4319 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4320 | } | |
9226253a | 4321 | } |
0dd2d296 | 4322 | else |
d9aba805 ILT |
4323 | abort (); |
4324 | ||
9226253a ILT |
4325 | return; |
4326 | ||
4327 | case M_JAL_A: | |
d9aba805 ILT |
4328 | if (mips_pic == NO_PIC) |
4329 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4330 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4331 | { |
fb251650 ILT |
4332 | /* If this is a reference to an external symbol, and we are |
4333 | using a small GOT, we want | |
d9aba805 ILT |
4334 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4335 | nop | |
4336 | jalr $25 | |
4337 | nop | |
4338 | lw $gp,cprestore($sp) | |
4339 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4340 | pseudo-op. If we are using a big GOT, we want |
4341 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4342 | addu $25,$25,$gp | |
4343 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4344 | nop | |
4345 | jalr $25 | |
4346 | nop | |
4347 | lw $gp,cprestore($sp) | |
4348 | If the symbol is not external, we want | |
d9aba805 ILT |
4349 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4350 | nop | |
4351 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4352 | jalr $25 | |
4353 | nop | |
fb251650 ILT |
4354 | lw $gp,cprestore($sp) */ |
4355 | frag_grow (40); | |
4356 | if (! mips_big_got) | |
4357 | { | |
4358 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4359 | mips_isa < 3 ? "lw" : "ld", | |
4360 | "t,o(b)", PIC_CALL_REG, | |
4361 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4362 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4363 | "nop", ""); | |
4364 | p = frag_var (rs_machine_dependent, 4, 0, | |
4365 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4366 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4367 | } | |
4368 | else | |
4369 | { | |
4370 | int gpdel; | |
4371 | ||
4372 | if (reg_needs_delay (GP)) | |
4373 | gpdel = 4; | |
4374 | else | |
4375 | gpdel = 0; | |
4376 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4377 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4378 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4379 | mips_isa < 3 ? "addu" : "daddu", | |
4380 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4381 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4382 | mips_isa < 3 ? "lw" : "ld", | |
4383 | "t,o(b)", PIC_CALL_REG, | |
4384 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4385 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4386 | "nop", ""); | |
4387 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4388 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4389 | 0, 0), | |
4390 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4391 | if (gpdel > 0) | |
4392 | { | |
4393 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4394 | p += 4; | |
4395 | } | |
4396 | macro_build (p, &icnt, &offset_expr, | |
4397 | mips_isa < 3 ? "lw" : "ld", | |
4398 | "t,o(b)", PIC_CALL_REG, | |
4399 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4400 | p += 4; | |
4401 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4402 | p += 4; | |
4403 | } | |
d9aba805 ILT |
4404 | macro_build (p, &icnt, &offset_expr, |
4405 | mips_isa < 3 ? "addiu" : "daddiu", | |
4406 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4407 | (int) BFD_RELOC_LO16); | |
4408 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4409 | "jalr", "s", PIC_CALL_REG); | |
4410 | if (mips_cprestore_offset < 0) | |
4411 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4412 | else | |
4413 | { | |
4414 | if (mips_noreorder) | |
4415 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4416 | "nop", ""); | |
4417 | expr1.X_add_number = mips_cprestore_offset; | |
4418 | macro_build ((char *) NULL, &icnt, &expr1, | |
4419 | mips_isa < 3 ? "lw" : "ld", | |
4420 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4421 | mips_frame_reg); | |
4422 | } | |
0dd2d296 | 4423 | } |
d9aba805 | 4424 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4425 | { |
4426 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4427 | /* The linker may expand the call to a longer sequence which | |
4428 | uses $at, so we must break rather than return. */ | |
4429 | break; | |
4430 | } | |
d9aba805 ILT |
4431 | else |
4432 | abort (); | |
4433 | ||
9226253a ILT |
4434 | return; |
4435 | ||
3d3c5039 | 4436 | case M_LB_AB: |
670a50eb ILT |
4437 | s = "lb"; |
4438 | goto ld; | |
3d3c5039 | 4439 | case M_LBU_AB: |
670a50eb ILT |
4440 | s = "lbu"; |
4441 | goto ld; | |
3d3c5039 | 4442 | case M_LH_AB: |
670a50eb ILT |
4443 | s = "lh"; |
4444 | goto ld; | |
3d3c5039 | 4445 | case M_LHU_AB: |
670a50eb ILT |
4446 | s = "lhu"; |
4447 | goto ld; | |
3d3c5039 | 4448 | case M_LW_AB: |
670a50eb ILT |
4449 | s = "lw"; |
4450 | goto ld; | |
3d3c5039 | 4451 | case M_LWC0_AB: |
670a50eb | 4452 | s = "lwc0"; |
efec4a28 | 4453 | /* Itbl support may require additional care here. */ |
8358c818 | 4454 | coproc = 1; |
670a50eb | 4455 | goto ld; |
3d3c5039 | 4456 | case M_LWC1_AB: |
670a50eb | 4457 | s = "lwc1"; |
efec4a28 | 4458 | /* Itbl support may require additional care here. */ |
8358c818 | 4459 | coproc = 1; |
670a50eb | 4460 | goto ld; |
3d3c5039 | 4461 | case M_LWC2_AB: |
670a50eb | 4462 | s = "lwc2"; |
efec4a28 | 4463 | /* Itbl support may require additional care here. */ |
8358c818 | 4464 | coproc = 1; |
670a50eb | 4465 | goto ld; |
3d3c5039 | 4466 | case M_LWC3_AB: |
670a50eb | 4467 | s = "lwc3"; |
efec4a28 | 4468 | /* Itbl support may require additional care here. */ |
8358c818 | 4469 | coproc = 1; |
670a50eb | 4470 | goto ld; |
3d3c5039 | 4471 | case M_LWL_AB: |
670a50eb | 4472 | s = "lwl"; |
b2b8c24e | 4473 | lr = 1; |
670a50eb | 4474 | goto ld; |
3d3c5039 | 4475 | case M_LWR_AB: |
670a50eb | 4476 | s = "lwr"; |
b2b8c24e | 4477 | lr = 1; |
8358c818 ILT |
4478 | goto ld; |
4479 | case M_LDC1_AB: | |
4480 | s = "ldc1"; | |
efec4a28 | 4481 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4482 | coproc = 1; |
4483 | goto ld; | |
4484 | case M_LDC2_AB: | |
4485 | s = "ldc2"; | |
efec4a28 | 4486 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4487 | coproc = 1; |
4488 | goto ld; | |
4489 | case M_LDC3_AB: | |
4490 | s = "ldc3"; | |
efec4a28 | 4491 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4492 | coproc = 1; |
4493 | goto ld; | |
4494 | case M_LDL_AB: | |
4495 | s = "ldl"; | |
b2b8c24e | 4496 | lr = 1; |
8358c818 ILT |
4497 | goto ld; |
4498 | case M_LDR_AB: | |
4499 | s = "ldr"; | |
b2b8c24e | 4500 | lr = 1; |
8358c818 ILT |
4501 | goto ld; |
4502 | case M_LL_AB: | |
4503 | s = "ll"; | |
4504 | goto ld; | |
4505 | case M_LLD_AB: | |
4506 | s = "lld"; | |
4507 | goto ld; | |
4508 | case M_LWU_AB: | |
4509 | s = "lwu"; | |
3d3c5039 | 4510 | ld: |
b2b8c24e | 4511 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4512 | { |
4513 | tempreg = AT; | |
4514 | used_at = 1; | |
4515 | } | |
4516 | else | |
4517 | { | |
4518 | tempreg = treg; | |
4519 | used_at = 0; | |
4520 | } | |
4521 | goto ld_st; | |
3d3c5039 | 4522 | case M_SB_AB: |
670a50eb ILT |
4523 | s = "sb"; |
4524 | goto st; | |
3d3c5039 | 4525 | case M_SH_AB: |
670a50eb ILT |
4526 | s = "sh"; |
4527 | goto st; | |
3d3c5039 | 4528 | case M_SW_AB: |
670a50eb ILT |
4529 | s = "sw"; |
4530 | goto st; | |
3d3c5039 | 4531 | case M_SWC0_AB: |
670a50eb | 4532 | s = "swc0"; |
efec4a28 | 4533 | /* Itbl support may require additional care here. */ |
8358c818 | 4534 | coproc = 1; |
670a50eb | 4535 | goto st; |
3d3c5039 | 4536 | case M_SWC1_AB: |
670a50eb | 4537 | s = "swc1"; |
efec4a28 | 4538 | /* Itbl support may require additional care here. */ |
8358c818 | 4539 | coproc = 1; |
670a50eb | 4540 | goto st; |
3d3c5039 | 4541 | case M_SWC2_AB: |
670a50eb | 4542 | s = "swc2"; |
efec4a28 | 4543 | /* Itbl support may require additional care here. */ |
8358c818 | 4544 | coproc = 1; |
670a50eb | 4545 | goto st; |
3d3c5039 | 4546 | case M_SWC3_AB: |
670a50eb | 4547 | s = "swc3"; |
efec4a28 | 4548 | /* Itbl support may require additional care here. */ |
8358c818 | 4549 | coproc = 1; |
670a50eb | 4550 | goto st; |
3d3c5039 | 4551 | case M_SWL_AB: |
670a50eb ILT |
4552 | s = "swl"; |
4553 | goto st; | |
3d3c5039 | 4554 | case M_SWR_AB: |
670a50eb | 4555 | s = "swr"; |
8358c818 ILT |
4556 | goto st; |
4557 | case M_SC_AB: | |
4558 | s = "sc"; | |
4559 | goto st; | |
4560 | case M_SCD_AB: | |
4561 | s = "scd"; | |
4562 | goto st; | |
4563 | case M_SDC1_AB: | |
4564 | s = "sdc1"; | |
4565 | coproc = 1; | |
efec4a28 | 4566 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4567 | goto st; |
4568 | case M_SDC2_AB: | |
4569 | s = "sdc2"; | |
efec4a28 | 4570 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4571 | coproc = 1; |
4572 | goto st; | |
4573 | case M_SDC3_AB: | |
4574 | s = "sdc3"; | |
efec4a28 | 4575 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4576 | coproc = 1; |
4577 | goto st; | |
4578 | case M_SDL_AB: | |
4579 | s = "sdl"; | |
4580 | goto st; | |
4581 | case M_SDR_AB: | |
4582 | s = "sdr"; | |
3d3c5039 | 4583 | st: |
670a50eb ILT |
4584 | tempreg = AT; |
4585 | used_at = 1; | |
3d3c5039 | 4586 | ld_st: |
efec4a28 | 4587 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4588 | if (mask == M_LWC1_AB |
4589 | || mask == M_SWC1_AB | |
8358c818 | 4590 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4591 | || mask == M_SDC1_AB |
4592 | || mask == M_L_DAB | |
4593 | || mask == M_S_DAB) | |
670a50eb | 4594 | fmt = "T,o(b)"; |
8358c818 | 4595 | else if (coproc) |
19ed8960 | 4596 | fmt = "E,o(b)"; |
670a50eb ILT |
4597 | else |
4598 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4599 | |
4600 | if (offset_expr.X_op != O_constant | |
4601 | && offset_expr.X_op != O_symbol) | |
4602 | { | |
4603 | as_bad ("expression too complex"); | |
4604 | offset_expr.X_op = O_constant; | |
4605 | } | |
4606 | ||
4607 | /* A constant expression in PIC code can be handled just as it | |
4608 | is in non PIC code. */ | |
d9aba805 | 4609 | if (mips_pic == NO_PIC |
0dd2d296 | 4610 | || offset_expr.X_op == O_constant) |
670a50eb | 4611 | { |
0dd2d296 ILT |
4612 | /* If this is a reference to a GP relative symbol, and there |
4613 | is no base register, we want | |
4614 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4615 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4616 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4617 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4618 | If we have a constant, we need two instructions anyhow, | |
4619 | so we always use the latter form. | |
4620 | ||
4621 | If we have a base register, and this is a reference to a | |
4622 | GP relative symbol, we want | |
4623 | addu $tempreg,$breg,$gp | |
4624 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4625 | Otherwise we want | |
4626 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4627 | addu $tempreg,$tempreg,$breg | |
4628 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4629 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4630 | if (breg == 0) |
4631 | { | |
7a15a226 | 4632 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4633 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4634 | p = NULL; |
4635 | else | |
4636 | { | |
8ea7f4e8 | 4637 | frag_grow (20); |
0dd2d296 ILT |
4638 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4639 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4640 | p = frag_var (rs_machine_dependent, 8, 0, | |
4641 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4642 | (mips_warn_about_macros |
4643 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4644 | offset_expr.X_add_symbol, (long) 0, |
4645 | (char *) NULL); | |
8197b589 | 4646 | used_at = 0; |
0dd2d296 ILT |
4647 | } |
4648 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4649 | if (p != NULL) | |
4650 | p += 4; | |
4651 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4652 | (int) BFD_RELOC_LO16, tempreg); | |
4653 | } | |
4654 | else | |
4655 | { | |
7a15a226 | 4656 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4657 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4658 | p = NULL; |
4659 | else | |
4660 | { | |
8ea7f4e8 | 4661 | frag_grow (28); |
0dd2d296 ILT |
4662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4663 | mips_isa < 3 ? "addu" : "daddu", | |
4664 | "d,v,t", tempreg, breg, GP); | |
4665 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4666 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4667 | p = frag_var (rs_machine_dependent, 12, 0, | |
4668 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4669 | offset_expr.X_add_symbol, (long) 0, | |
4670 | (char *) NULL); | |
4671 | } | |
4672 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4673 | if (p != NULL) | |
4674 | p += 4; | |
4675 | macro_build (p, &icnt, (expressionS *) NULL, | |
4676 | mips_isa < 3 ? "addu" : "daddu", | |
4677 | "d,v,t", tempreg, tempreg, breg); | |
4678 | if (p != NULL) | |
4679 | p += 4; | |
4680 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4681 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4682 | } |
670a50eb | 4683 | } |
fb251650 | 4684 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4685 | { |
0dd2d296 ILT |
4686 | /* If this is a reference to an external symbol, we want |
4687 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4688 | nop | |
4689 | <op> $treg,0($tempreg) | |
4690 | Otherwise we want | |
4691 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4692 | nop | |
4693 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4694 | <op> $treg,0($tempreg) | |
4695 | If there is a base register, we add it to $tempreg before | |
4696 | the <op>. If there is a constant, we stick it in the | |
4697 | <op> instruction. We don't handle constants larger than | |
4698 | 16 bits, because we have no way to load the upper 16 bits | |
4699 | (actually, we could handle them for the subset of cases | |
4700 | in which we are not using $at). */ | |
4701 | assert (offset_expr.X_op == O_symbol); | |
4702 | expr1.X_add_number = offset_expr.X_add_number; | |
4703 | offset_expr.X_add_number = 0; | |
4704 | if (expr1.X_add_number < -0x8000 | |
4705 | || expr1.X_add_number >= 0x8000) | |
4706 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4707 | frag_grow (20); |
0dd2d296 ILT |
4708 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4709 | mips_isa < 3 ? "lw" : "ld", | |
4710 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4711 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4712 | p = frag_var (rs_machine_dependent, 4, 0, | |
4713 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4714 | offset_expr.X_add_symbol, (long) 0, | |
4715 | (char *) NULL); | |
4716 | macro_build (p, &icnt, &offset_expr, | |
4717 | mips_isa < 3 ? "addiu" : "daddiu", | |
4718 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4719 | if (breg != 0) |
0dd2d296 | 4720 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4721 | mips_isa < 3 ? "addu" : "daddu", |
4722 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4723 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4724 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4725 | } |
fb251650 ILT |
4726 | else if (mips_pic == SVR4_PIC) |
4727 | { | |
4728 | int gpdel; | |
4729 | ||
4730 | /* If this is a reference to an external symbol, we want | |
4731 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4732 | addu $tempreg,$tempreg,$gp | |
4733 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4734 | <op> $treg,0($tempreg) | |
4735 | Otherwise we want | |
4736 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4737 | nop | |
4738 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4739 | <op> $treg,0($tempreg) | |
4740 | If there is a base register, we add it to $tempreg before | |
4741 | the <op>. If there is a constant, we stick it in the | |
4742 | <op> instruction. We don't handle constants larger than | |
4743 | 16 bits, because we have no way to load the upper 16 bits | |
4744 | (actually, we could handle them for the subset of cases | |
4745 | in which we are not using $at). */ | |
4746 | assert (offset_expr.X_op == O_symbol); | |
4747 | expr1.X_add_number = offset_expr.X_add_number; | |
4748 | offset_expr.X_add_number = 0; | |
4749 | if (expr1.X_add_number < -0x8000 | |
4750 | || expr1.X_add_number >= 0x8000) | |
4751 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4752 | if (reg_needs_delay (GP)) | |
4753 | gpdel = 4; | |
4754 | else | |
4755 | gpdel = 0; | |
4756 | frag_grow (36); | |
4757 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4758 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4759 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4760 | mips_isa < 3 ? "addu" : "daddu", | |
4761 | "d,v,t", tempreg, tempreg, GP); | |
4762 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4763 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4764 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4765 | tempreg); | |
fb251650 ILT |
4766 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4767 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4768 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4769 | if (gpdel > 0) | |
4770 | { | |
4771 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4772 | p += 4; | |
4773 | } | |
4774 | macro_build (p, &icnt, &offset_expr, | |
4775 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4776 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4777 | p += 4; |
4778 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4779 | p += 4; | |
4780 | macro_build (p, &icnt, &offset_expr, | |
4781 | mips_isa < 3 ? "addiu" : "daddiu", | |
4782 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4783 | if (breg != 0) | |
4784 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4785 | mips_isa < 3 ? "addu" : "daddu", | |
4786 | "d,v,t", tempreg, tempreg, breg); | |
4787 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4788 | (int) BFD_RELOC_LO16, tempreg); | |
4789 | } | |
d9aba805 ILT |
4790 | else if (mips_pic == EMBEDDED_PIC) |
4791 | { | |
4792 | /* If there is no base register, we want | |
4793 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4794 | If there is a base register, we want | |
4795 | addu $tempreg,$breg,$gp | |
4796 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4797 | */ | |
4798 | assert (offset_expr.X_op == O_symbol); | |
4799 | if (breg == 0) | |
4800 | { | |
4801 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4802 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4803 | used_at = 0; | |
4804 | } | |
4805 | else | |
4806 | { | |
4807 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4808 | mips_isa < 3 ? "addu" : "daddu", | |
4809 | "d,v,t", tempreg, breg, GP); | |
4810 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4811 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4812 | } | |
4813 | } | |
4814 | else | |
4815 | abort (); | |
0dd2d296 ILT |
4816 | |
4817 | if (! used_at) | |
4818 | return; | |
4819 | ||
4820 | break; | |
3d3c5039 ILT |
4821 | |
4822 | case M_LI: | |
19ed8960 | 4823 | case M_LI_S: |
d8a1c247 KR |
4824 | load_register (&icnt, treg, &imm_expr, 0); |
4825 | return; | |
4826 | ||
4827 | case M_DLI: | |
4828 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4829 | return; |
3d3c5039 | 4830 | |
0dd2d296 | 4831 | case M_LI_SS: |
55933a58 | 4832 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4833 | { |
d8a1c247 | 4834 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4835 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4836 | "mtc1", "t,G", AT, treg); | |
4837 | break; | |
0dd2d296 | 4838 | } |
d9aba805 | 4839 | else |
d2c71068 | 4840 | { |
55933a58 ILT |
4841 | assert (offset_expr.X_op == O_symbol |
4842 | && strcmp (segment_name (S_GET_SEGMENT | |
4843 | (offset_expr.X_add_symbol)), | |
4844 | ".lit4") == 0 | |
4845 | && offset_expr.X_add_number == 0); | |
4846 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4847 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4848 | return; |
4849 | } | |
0dd2d296 | 4850 | |
3d3c5039 | 4851 | case M_LI_D: |
d9aba805 ILT |
4852 | /* We know that sym is in the .rdata section. First we get the |
4853 | upper 16 bits of the address. */ | |
4854 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4855 | { |
4856 | /* FIXME: This won't work for a 64 bit address. */ | |
4857 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4858 | } | |
d9aba805 | 4859 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4860 | { |
4861 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4862 | mips_isa < 3 ? "lw" : "ld", | |
4863 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4864 | } | |
d9aba805 ILT |
4865 | else if (mips_pic == EMBEDDED_PIC) |
4866 | { | |
4867 | /* For embedded PIC we pick up the entire address off $gp in | |
4868 | a single instruction. */ | |
4869 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4870 | mips_isa < 3 ? "addiu" : "daddiu", | |
4871 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4872 | offset_expr.X_op = O_constant; | |
4873 | offset_expr.X_add_number = 0; | |
4874 | } | |
4875 | else | |
4876 | abort (); | |
4877 | ||
0dd2d296 | 4878 | /* Now we load the register(s). */ |
8358c818 | 4879 | if (mips_isa >= 3) |
0dd2d296 ILT |
4880 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4881 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4882 | else |
4883 | { | |
0dd2d296 ILT |
4884 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4885 | treg, (int) BFD_RELOC_LO16, AT); | |
4886 | if (treg != 31) | |
4887 | { | |
4888 | /* FIXME: How in the world do we deal with the possible | |
4889 | overflow here? */ | |
4890 | offset_expr.X_add_number += 4; | |
4891 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4892 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4893 | } | |
8358c818 | 4894 | } |
d2c71068 ILT |
4895 | |
4896 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4897 | does not become a variant frag. */ | |
4898 | frag_wane (frag_now); | |
4899 | frag_new (0); | |
4900 | ||
670a50eb | 4901 | break; |
3d3c5039 ILT |
4902 | |
4903 | case M_LI_DD: | |
55933a58 ILT |
4904 | assert (offset_expr.X_op == O_symbol |
4905 | && offset_expr.X_add_number == 0); | |
4906 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4907 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4908 | { |
0dd2d296 ILT |
4909 | if (mips_isa >= 2) |
4910 | { | |
4911 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4912 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4913 | return; | |
4914 | } | |
4915 | breg = GP; | |
4916 | r = BFD_RELOC_MIPS_LITERAL; | |
4917 | goto dob; | |
4918 | } | |
55933a58 | 4919 | else |
0dd2d296 | 4920 | { |
55933a58 ILT |
4921 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4922 | if (mips_pic == SVR4_PIC) | |
4923 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4924 | mips_isa < 3 ? "lw" : "ld", | |
4925 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4926 | else | |
4927 | { | |
4928 | /* FIXME: This won't work for a 64 bit address. */ | |
4929 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4930 | } | |
4931 | ||
0dd2d296 ILT |
4932 | if (mips_isa >= 2) |
4933 | { | |
4934 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4935 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4936 | |
4937 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4938 | that this does not become a variant frag. */ | |
4939 | frag_wane (frag_now); | |
4940 | frag_new (0); | |
4941 | ||
0dd2d296 ILT |
4942 | break; |
4943 | } | |
4944 | breg = AT; | |
4945 | r = BFD_RELOC_LO16; | |
4946 | goto dob; | |
8358c818 | 4947 | } |
9226253a | 4948 | |
3d3c5039 | 4949 | case M_L_DOB: |
9a7d824a ILT |
4950 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4951 | to adjust when loading from memory. */ | |
9226253a ILT |
4952 | r = BFD_RELOC_LO16; |
4953 | dob: | |
8358c818 | 4954 | assert (mips_isa < 2); |
0dd2d296 | 4955 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4956 | target_big_endian ? treg + 1 : treg, |
9226253a | 4957 | (int) r, breg); |
0dd2d296 ILT |
4958 | /* FIXME: A possible overflow which I don't know how to deal |
4959 | with. */ | |
670a50eb | 4960 | offset_expr.X_add_number += 4; |
0dd2d296 | 4961 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4962 | target_big_endian ? treg : treg + 1, |
9226253a | 4963 | (int) r, breg); |
d2c71068 ILT |
4964 | |
4965 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4966 | does not become a variant frag. */ | |
4967 | frag_wane (frag_now); | |
4968 | frag_new (0); | |
4969 | ||
0dd2d296 ILT |
4970 | if (breg != AT) |
4971 | return; | |
4972 | break; | |
3d3c5039 ILT |
4973 | |
4974 | case M_L_DAB: | |
670a50eb ILT |
4975 | /* |
4976 | * The MIPS assembler seems to check for X_add_number not | |
4977 | * being double aligned and generating: | |
4978 | * lui at,%hi(foo+1) | |
4979 | * addu at,at,v1 | |
4980 | * addiu at,at,%lo(foo+1) | |
4981 | * lwc1 f2,0(at) | |
4982 | * lwc1 f3,4(at) | |
4983 | * But, the resulting address is the same after relocation so why | |
4984 | * generate the extra instruction? | |
4985 | */ | |
efec4a28 | 4986 | /* Itbl support may require additional care here. */ |
4032d3f0 | 4987 | coproc = 1; |
0dd2d296 | 4988 | if (mips_isa >= 2) |
670a50eb | 4989 | { |
0dd2d296 ILT |
4990 | s = "ldc1"; |
4991 | goto ld; | |
670a50eb | 4992 | } |
0dd2d296 ILT |
4993 | |
4994 | s = "lwc1"; | |
4995 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4996 | goto ldd_std; |
4997 | ||
4998 | case M_S_DAB: | |
8358c818 | 4999 | if (mips_isa >= 2) |
8358c818 | 5000 | { |
0dd2d296 ILT |
5001 | s = "sdc1"; |
5002 | goto st; | |
8358c818 | 5003 | } |
3d3c5039 | 5004 | |
0dd2d296 ILT |
5005 | s = "swc1"; |
5006 | fmt = "T,o(b)"; | |
efec4a28 | 5007 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5008 | coproc = 1; |
5009 | goto ldd_std; | |
3d3c5039 ILT |
5010 | |
5011 | case M_LD_AB: | |
0dd2d296 | 5012 | if (mips_isa >= 3) |
670a50eb | 5013 | { |
0dd2d296 ILT |
5014 | s = "ld"; |
5015 | goto ld; | |
670a50eb | 5016 | } |
0dd2d296 ILT |
5017 | |
5018 | s = "lw"; | |
5019 | fmt = "t,o(b)"; | |
5020 | goto ldd_std; | |
5021 | ||
5022 | case M_SD_AB: | |
5023 | if (mips_isa >= 3) | |
670a50eb | 5024 | { |
0dd2d296 ILT |
5025 | s = "sd"; |
5026 | goto st; | |
670a50eb | 5027 | } |
0dd2d296 | 5028 | |
670a50eb | 5029 | s = "sw"; |
0dd2d296 ILT |
5030 | fmt = "t,o(b)"; |
5031 | ||
5032 | ldd_std: | |
5033 | if (offset_expr.X_op != O_symbol | |
5034 | && offset_expr.X_op != O_constant) | |
670a50eb | 5035 | { |
0dd2d296 ILT |
5036 | as_bad ("expression too complex"); |
5037 | offset_expr.X_op = O_constant; | |
5038 | } | |
5039 | ||
5040 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5041 | to adjust when loading from memory. We set coproc if we must | |
5042 | load $fn+1 first. */ | |
efec4a28 | 5043 | /* Itbl support may require additional care here. */ |
b9129c6f | 5044 | if (! target_big_endian) |
0dd2d296 ILT |
5045 | coproc = 0; |
5046 | ||
d9aba805 | 5047 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5048 | || offset_expr.X_op == O_constant) |
5049 | { | |
5050 | /* If this is a reference to a GP relative symbol, we want | |
5051 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5052 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5053 | If we have a base register, we use this | |
5054 | addu $at,$breg,$gp | |
5055 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5056 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5057 | If this is not a GP relative symbol, we want | |
5058 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5059 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5060 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5061 | If there is a base register, we add it to $at after the | |
5062 | lui instruction. If there is a constant, we always use | |
5063 | the last case. */ | |
7a15a226 | 5064 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 5065 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 5066 | { |
0dd2d296 ILT |
5067 | p = NULL; |
5068 | used_at = 1; | |
670a50eb ILT |
5069 | } |
5070 | else | |
0dd2d296 ILT |
5071 | { |
5072 | int off; | |
5073 | ||
5074 | if (breg == 0) | |
5075 | { | |
8ea7f4e8 | 5076 | frag_grow (28); |
0dd2d296 ILT |
5077 | tempreg = GP; |
5078 | off = 0; | |
5079 | used_at = 0; | |
5080 | } | |
5081 | else | |
5082 | { | |
8ea7f4e8 | 5083 | frag_grow (36); |
0dd2d296 ILT |
5084 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5085 | mips_isa < 3 ? "addu" : "daddu", | |
5086 | "d,v,t", AT, breg, GP); | |
5087 | tempreg = AT; | |
5088 | off = 4; | |
5089 | used_at = 1; | |
5090 | } | |
5091 | ||
efec4a28 | 5092 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5093 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5094 | coproc ? treg + 1 : treg, | |
5095 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5096 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5097 | |
5098 | /* Set mips_optimize to 2 to avoid inserting an | |
5099 | undesired nop. */ | |
5100 | hold_mips_optimize = mips_optimize; | |
5101 | mips_optimize = 2; | |
efec4a28 | 5102 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5103 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5104 | coproc ? treg : treg + 1, | |
5105 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5106 | mips_optimize = hold_mips_optimize; |
5107 | ||
0dd2d296 ILT |
5108 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5109 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 5110 | used_at && mips_noat), |
0dd2d296 ILT |
5111 | offset_expr.X_add_symbol, (long) 0, |
5112 | (char *) NULL); | |
777ad64d ILT |
5113 | |
5114 | /* We just generated two relocs. When tc_gen_reloc | |
5115 | handles this case, it will skip the first reloc and | |
5116 | handle the second. The second reloc already has an | |
5117 | extra addend of 4, which we added above. We must | |
5118 | subtract it out, and then subtract another 4 to make | |
5119 | the first reloc come out right. The second reloc | |
5120 | will come out right because we are going to add 4 to | |
5121 | offset_expr when we build its instruction below. */ | |
5122 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
5123 | offset_expr.X_op = O_constant; |
5124 | } | |
5125 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5126 | if (p != NULL) | |
5127 | p += 4; | |
5128 | if (breg != 0) | |
5129 | { | |
5130 | macro_build (p, &icnt, (expressionS *) NULL, | |
5131 | mips_isa < 3 ? "addu" : "daddu", | |
5132 | "d,v,t", AT, breg, AT); | |
5133 | if (p != NULL) | |
5134 | p += 4; | |
5135 | } | |
efec4a28 | 5136 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5137 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5138 | coproc ? treg + 1 : treg, | |
5139 | (int) BFD_RELOC_LO16, AT); | |
5140 | if (p != NULL) | |
5141 | p += 4; | |
5142 | /* FIXME: How do we handle overflow here? */ | |
5143 | offset_expr.X_add_number += 4; | |
efec4a28 | 5144 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5145 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5146 | coproc ? treg : treg + 1, | |
5147 | (int) BFD_RELOC_LO16, AT); | |
5148 | } | |
fb251650 | 5149 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5150 | { |
0dd2d296 ILT |
5151 | int off; |
5152 | ||
5153 | /* If this is a reference to an external symbol, we want | |
5154 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5155 | nop | |
5156 | <op> $treg,0($at) | |
5157 | <op> $treg+1,4($at) | |
5158 | Otherwise we want | |
5159 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5160 | nop | |
5161 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5162 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5163 | If there is a base register we add it to $at before the | |
5164 | lwc1 instructions. If there is a constant we include it | |
5165 | in the lwc1 instructions. */ | |
5166 | used_at = 1; | |
5167 | expr1.X_add_number = offset_expr.X_add_number; | |
5168 | offset_expr.X_add_number = 0; | |
5169 | if (expr1.X_add_number < -0x8000 | |
5170 | || expr1.X_add_number >= 0x8000 - 4) | |
5171 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5172 | if (breg == 0) | |
5173 | off = 0; | |
5174 | else | |
5175 | off = 4; | |
8ea7f4e8 | 5176 | frag_grow (24 + off); |
0dd2d296 ILT |
5177 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5178 | mips_isa < 3 ? "lw" : "ld", | |
5179 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5180 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5181 | if (breg != 0) |
0dd2d296 | 5182 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 5183 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5184 | "d,v,t", AT, breg, AT); |
efec4a28 | 5185 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5186 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5187 | coproc ? treg + 1 : treg, | |
5188 | (int) BFD_RELOC_LO16, AT); | |
5189 | expr1.X_add_number += 4; | |
55933a58 ILT |
5190 | |
5191 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5192 | nop. */ | |
5193 | hold_mips_optimize = mips_optimize; | |
5194 | mips_optimize = 2; | |
efec4a28 | 5195 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5196 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5197 | coproc ? treg : treg + 1, | |
5198 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5199 | mips_optimize = hold_mips_optimize; |
5200 | ||
0dd2d296 ILT |
5201 | (void) frag_var (rs_machine_dependent, 0, 0, |
5202 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5203 | offset_expr.X_add_symbol, (long) 0, | |
5204 | (char *) NULL); | |
8358c818 | 5205 | } |
fb251650 ILT |
5206 | else if (mips_pic == SVR4_PIC) |
5207 | { | |
5208 | int gpdel, off; | |
5209 | ||
5210 | /* If this is a reference to an external symbol, we want | |
5211 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5212 | addu $at,$at,$gp | |
5213 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5214 | nop | |
5215 | <op> $treg,0($at) | |
5216 | <op> $treg+1,4($at) | |
5217 | Otherwise we want | |
5218 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5219 | nop | |
5220 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5221 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5222 | If there is a base register we add it to $at before the | |
5223 | lwc1 instructions. If there is a constant we include it | |
5224 | in the lwc1 instructions. */ | |
5225 | used_at = 1; | |
5226 | expr1.X_add_number = offset_expr.X_add_number; | |
5227 | offset_expr.X_add_number = 0; | |
5228 | if (expr1.X_add_number < -0x8000 | |
5229 | || expr1.X_add_number >= 0x8000 - 4) | |
5230 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5231 | if (reg_needs_delay (GP)) | |
5232 | gpdel = 4; | |
5233 | else | |
5234 | gpdel = 0; | |
5235 | if (breg == 0) | |
5236 | off = 0; | |
5237 | else | |
5238 | off = 4; | |
5239 | frag_grow (56); | |
5240 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5241 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5242 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5243 | mips_isa < 3 ? "addu" : "daddu", | |
5244 | "d,v,t", AT, AT, GP); | |
5245 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5246 | mips_isa < 3 ? "lw" : "ld", | |
5247 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5248 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5249 | if (breg != 0) | |
5250 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5251 | mips_isa < 3 ? "addu" : "daddu", | |
5252 | "d,v,t", AT, breg, AT); | |
efec4a28 | 5253 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5254 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5255 | coproc ? treg + 1 : treg, | |
5256 | (int) BFD_RELOC_LO16, AT); | |
5257 | expr1.X_add_number += 4; | |
5258 | ||
5259 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5260 | nop. */ | |
5261 | hold_mips_optimize = mips_optimize; | |
5262 | mips_optimize = 2; | |
efec4a28 | 5263 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5264 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5265 | coproc ? treg : treg + 1, | |
5266 | (int) BFD_RELOC_LO16, AT); | |
5267 | mips_optimize = hold_mips_optimize; | |
5268 | expr1.X_add_number -= 4; | |
5269 | ||
5270 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5271 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5272 | 8 + gpdel + off, 1, 0), | |
5273 | offset_expr.X_add_symbol, (long) 0, | |
5274 | (char *) NULL); | |
5275 | if (gpdel > 0) | |
5276 | { | |
5277 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5278 | p += 4; | |
5279 | } | |
5280 | macro_build (p, &icnt, &offset_expr, | |
5281 | mips_isa < 3 ? "lw" : "ld", | |
5282 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5283 | p += 4; | |
5284 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5285 | p += 4; | |
5286 | if (breg != 0) | |
5287 | { | |
5288 | macro_build (p, &icnt, (expressionS *) NULL, | |
5289 | mips_isa < 3 ? "addu" : "daddu", | |
5290 | "d,v,t", AT, breg, AT); | |
5291 | p += 4; | |
5292 | } | |
efec4a28 | 5293 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5294 | macro_build (p, &icnt, &expr1, s, fmt, |
5295 | coproc ? treg + 1 : treg, | |
5296 | (int) BFD_RELOC_LO16, AT); | |
5297 | p += 4; | |
5298 | expr1.X_add_number += 4; | |
5299 | ||
5300 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5301 | nop. */ | |
5302 | hold_mips_optimize = mips_optimize; | |
5303 | mips_optimize = 2; | |
efec4a28 | 5304 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5305 | macro_build (p, &icnt, &expr1, s, fmt, |
5306 | coproc ? treg : treg + 1, | |
5307 | (int) BFD_RELOC_LO16, AT); | |
5308 | mips_optimize = hold_mips_optimize; | |
5309 | } | |
d9aba805 ILT |
5310 | else if (mips_pic == EMBEDDED_PIC) |
5311 | { | |
5312 | /* If there is no base register, we use | |
5313 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5314 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5315 | If we have a base register, we use | |
5316 | addu $at,$breg,$gp | |
5317 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5318 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5319 | */ | |
5320 | if (breg == 0) | |
5321 | { | |
5322 | tempreg = GP; | |
5323 | used_at = 0; | |
5324 | } | |
5325 | else | |
5326 | { | |
5327 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5328 | mips_isa < 3 ? "addu" : "daddu", | |
5329 | "d,v,t", AT, breg, GP); | |
5330 | tempreg = AT; | |
5331 | used_at = 1; | |
5332 | } | |
5333 | ||
efec4a28 | 5334 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5335 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5336 | coproc ? treg + 1 : treg, | |
5337 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5338 | offset_expr.X_add_number += 4; | |
efec4a28 | 5339 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5340 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5341 | coproc ? treg : treg + 1, | |
5342 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5343 | } | |
5344 | else | |
5345 | abort (); | |
0dd2d296 ILT |
5346 | |
5347 | if (! used_at) | |
5348 | return; | |
5349 | ||
5350 | break; | |
5351 | ||
5352 | case M_LD_OB: | |
5353 | s = "lw"; | |
5354 | goto sd_ob; | |
5355 | case M_SD_OB: | |
5356 | s = "sw"; | |
5357 | sd_ob: | |
5358 | assert (mips_isa < 3); | |
5359 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5360 | (int) BFD_RELOC_LO16, breg); | |
5361 | offset_expr.X_add_number += 4; | |
5362 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5363 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5364 | return; |
efec4a28 DP |
5365 | |
5366 | /* New code added to support COPZ instructions. | |
5367 | This code builds table entries out of the macros in mip_opcodes. | |
5368 | R4000 uses interlocks to handle coproc delays. | |
5369 | Other chips (like the R3000) require nops to be inserted for delays. | |
5370 | ||
5371 | FIXME: Currently, we require that the user handle delays. | |
5372 | In order to fill delay slots for non-interlocked chips, | |
5373 | we must have a way to specify delays based on the coprocessor. | |
5374 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5375 | What are the side-effects of the cop instruction? | |
5376 | What cache support might we have and what are its effects? | |
5377 | Both coprocessor & memory require delays. how long??? | |
5378 | What registers are read/set/modified? | |
5379 | ||
5380 | If an itbl is provided to interpret cop instructions, | |
5381 | this knowledge can be encoded in the itbl spec. */ | |
5382 | ||
5383 | case M_COP0: | |
5384 | s = "cop0"; | |
5385 | goto copz; | |
5386 | case M_COP1: | |
5387 | s = "cop1"; | |
5388 | goto copz; | |
5389 | case M_COP2: | |
5390 | s = "cop2"; | |
5391 | goto copz; | |
5392 | case M_COP3: | |
5393 | s = "cop3"; | |
5394 | copz: | |
5395 | /* For now we just do C (same as Cz). */ | |
5396 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); | |
5397 | return; | |
5398 | ||
917fae09 SS |
5399 | #ifdef LOSING_COMPILER |
5400 | default: | |
efec4a28 DP |
5401 | /* Try and see if this is a new itbl instruction. |
5402 | This code builds table entries out of the macros in mip_opcodes. | |
5403 | FIXME: For now we just assemble the expression and pass it's | |
5404 | value along as a 32-bit immediate. | |
5405 | We may want to have the assembler assemble this value, | |
5406 | so that we gain the assembler's knowledge of delay slots, | |
5407 | symbols, etc. | |
5408 | Would it be more efficient to use mask (id) here? */ | |
5409 | if (itbl_have_entries | |
5410 | && immed_expr = itbl_assemble(ip->insn_mo->name, ""), immed_expr) | |
5411 | { | |
5412 | s = ip->insn_mo->name; | |
5413 | s2 = "cop3"; | |
5414 | coproc = ITBL_DECODE_PNUM(immed_expr);; | |
5415 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5416 | return; | |
5417 | } | |
917fae09 SS |
5418 | macro2 (ip); |
5419 | return; | |
5420 | } | |
5421 | if (mips_noat) | |
5422 | as_warn ("Macro used $at after \".set noat\""); | |
5423 | } | |
5424 | ||
5425 | static void | |
5426 | macro2 (ip) | |
5427 | struct mips_cl_insn *ip; | |
5428 | { | |
5429 | register int treg, sreg, dreg, breg; | |
5430 | int tempreg; | |
5431 | int mask; | |
5432 | int icnt = 0; | |
5433 | int used_at; | |
5434 | expressionS expr1; | |
5435 | const char *s; | |
5436 | const char *s2; | |
5437 | const char *fmt; | |
5438 | int likely = 0; | |
5439 | int dbl = 0; | |
5440 | int coproc = 0; | |
adcf2b9d ILT |
5441 | int lr = 0; |
5442 | int off; | |
917fae09 SS |
5443 | offsetT maxnum; |
5444 | bfd_reloc_code_real_type r; | |
5445 | char *p; | |
5446 | ||
5447 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5448 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5449 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5450 | mask = ip->insn_mo->mask; | |
5451 | ||
5452 | expr1.X_op = O_constant; | |
5453 | expr1.X_op_symbol = NULL; | |
5454 | expr1.X_add_symbol = NULL; | |
5455 | expr1.X_add_number = 1; | |
5456 | ||
5457 | switch (mask) | |
5458 | { | |
5459 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5460 | |
8358c818 ILT |
5461 | case M_DMUL: |
5462 | dbl = 1; | |
3d3c5039 | 5463 | case M_MUL: |
0dd2d296 | 5464 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5465 | dbl ? "dmultu" : "multu", |
5466 | "s,t", sreg, treg); | |
0dd2d296 | 5467 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5468 | return; |
3d3c5039 | 5469 | |
8358c818 ILT |
5470 | case M_DMUL_I: |
5471 | dbl = 1; | |
3d3c5039 | 5472 | case M_MUL_I: |
8358c818 ILT |
5473 | /* The MIPS assembler some times generates shifts and adds. I'm |
5474 | not trying to be that fancy. GCC should do this for us | |
5475 | anyway. */ | |
d8a1c247 | 5476 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5477 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5478 | dbl ? "dmult" : "mult", |
5479 | "s,t", sreg, AT); | |
0dd2d296 | 5480 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5481 | break; |
3d3c5039 | 5482 | |
8358c818 ILT |
5483 | case M_DMULO: |
5484 | dbl = 1; | |
5485 | case M_MULO: | |
fbcfacb7 | 5486 | mips_emit_delays (true); |
8358c818 | 5487 | ++mips_noreorder; |
0dd2d296 ILT |
5488 | mips_any_noreorder = 1; |
5489 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5490 | dbl ? "dmult" : "mult", |
5491 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5492 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5493 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5494 | dbl ? "dsra32" : "sra", |
5495 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5496 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5497 | if (mips_trap) |
5498 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5499 | else | |
5500 | { | |
5501 | expr1.X_add_number = 8; | |
5502 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5503 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5504 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5505 | } | |
8358c818 | 5506 | --mips_noreorder; |
0dd2d296 | 5507 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5508 | break; |
5509 | ||
5510 | case M_DMULOU: | |
5511 | dbl = 1; | |
5512 | case M_MULOU: | |
fbcfacb7 | 5513 | mips_emit_delays (true); |
8358c818 | 5514 | ++mips_noreorder; |
0dd2d296 ILT |
5515 | mips_any_noreorder = 1; |
5516 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5517 | dbl ? "dmultu" : "multu", |
5518 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5519 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5520 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5521 | if (mips_trap) |
5522 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5523 | else | |
5524 | { | |
5525 | expr1.X_add_number = 8; | |
5526 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5527 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5528 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5529 | } | |
8358c818 ILT |
5530 | --mips_noreorder; |
5531 | break; | |
5532 | ||
3d3c5039 | 5533 | case M_ROL: |
0dd2d296 ILT |
5534 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5535 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5536 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5537 | treg); | |
5538 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5539 | break; |
3d3c5039 ILT |
5540 | |
5541 | case M_ROL_I: | |
0dd2d296 | 5542 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5543 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5544 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5545 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5546 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5547 | break; |
3d3c5039 ILT |
5548 | |
5549 | case M_ROR: | |
0dd2d296 ILT |
5550 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5551 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5552 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5553 | treg); | |
5554 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5555 | break; |
3d3c5039 ILT |
5556 | |
5557 | case M_ROR_I: | |
0dd2d296 | 5558 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5559 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5560 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5561 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5562 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5563 | break; |
3d3c5039 ILT |
5564 | |
5565 | case M_S_DOB: | |
8358c818 | 5566 | assert (mips_isa < 2); |
9a7d824a ILT |
5567 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5568 | to adjust when storing to memory. */ | |
0dd2d296 | 5569 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5570 | target_big_endian ? treg + 1 : treg, |
9226253a | 5571 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5572 | offset_expr.X_add_number += 4; |
0dd2d296 | 5573 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5574 | target_big_endian ? treg : treg + 1, |
9226253a | 5575 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5576 | return; |
3d3c5039 | 5577 | |
3d3c5039 | 5578 | case M_SEQ: |
670a50eb | 5579 | if (sreg == 0) |
0dd2d296 ILT |
5580 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5581 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5582 | else if (treg == 0) |
0dd2d296 ILT |
5583 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5584 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5585 | else |
5586 | { | |
0dd2d296 ILT |
5587 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5588 | sreg, treg); | |
5589 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5590 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5591 | } |
670a50eb | 5592 | return; |
3d3c5039 ILT |
5593 | |
5594 | case M_SEQ_I: | |
670a50eb ILT |
5595 | if (imm_expr.X_add_number == 0) |
5596 | { | |
0dd2d296 ILT |
5597 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5598 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5599 | return; |
3d3c5039 | 5600 | } |
670a50eb ILT |
5601 | if (sreg == 0) |
5602 | { | |
9a7d824a | 5603 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5604 | ip->insn_mo->name); |
0dd2d296 | 5605 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5606 | return; |
3d3c5039 | 5607 | } |
6e8dda9c | 5608 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5609 | { |
0dd2d296 ILT |
5610 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5611 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5612 | used_at = 0; |
6e8dda9c ILT |
5613 | } |
5614 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5615 | { | |
5616 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5617 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5618 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5619 | "t,r,j", dreg, sreg, |
5620 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5621 | used_at = 0; |
5622 | } | |
5623 | else | |
5624 | { | |
d8a1c247 | 5625 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5626 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5627 | sreg, AT); | |
670a50eb ILT |
5628 | used_at = 1; |
5629 | } | |
0dd2d296 | 5630 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5631 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5632 | if (used_at) |
5633 | break; | |
5634 | return; | |
3d3c5039 ILT |
5635 | |
5636 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5637 | s = "slt"; |
5638 | goto sge; | |
3d3c5039 | 5639 | case M_SGEU: |
670a50eb | 5640 | s = "sltu"; |
3d3c5039 | 5641 | sge: |
0dd2d296 ILT |
5642 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5643 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5644 | (int) BFD_RELOC_LO16); |
670a50eb | 5645 | return; |
3d3c5039 | 5646 | |
670a50eb | 5647 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5648 | case M_SGEU_I: |
6e8dda9c | 5649 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5650 | { |
0dd2d296 | 5651 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5652 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5653 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5654 | used_at = 0; |
5655 | } | |
5656 | else | |
5657 | { | |
d8a1c247 | 5658 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5659 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5660 | mask == M_SGE_I ? "slt" : "sltu", |
5661 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5662 | used_at = 1; |
5663 | } | |
0dd2d296 | 5664 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5665 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5666 | if (used_at) |
5667 | break; | |
5668 | return; | |
3d3c5039 ILT |
5669 | |
5670 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5671 | s = "slt"; |
5672 | goto sgt; | |
3d3c5039 | 5673 | case M_SGTU: |
670a50eb | 5674 | s = "sltu"; |
3d3c5039 | 5675 | sgt: |
0dd2d296 | 5676 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5677 | return; |
3d3c5039 | 5678 | |
670a50eb ILT |
5679 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5680 | s = "slt"; | |
5681 | goto sgti; | |
3d3c5039 | 5682 | case M_SGTU_I: |
670a50eb | 5683 | s = "sltu"; |
3d3c5039 | 5684 | sgti: |
d8a1c247 | 5685 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5686 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5687 | break; |
3d3c5039 | 5688 | |
670a50eb ILT |
5689 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5690 | s = "slt"; | |
5691 | goto sle; | |
3d3c5039 | 5692 | case M_SLEU: |
670a50eb | 5693 | s = "sltu"; |
3d3c5039 | 5694 | sle: |
0dd2d296 ILT |
5695 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5696 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5697 | (int) BFD_RELOC_LO16); |
670a50eb | 5698 | return; |
3d3c5039 | 5699 | |
670a50eb ILT |
5700 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5701 | s = "slt"; | |
5702 | goto slei; | |
3d3c5039 | 5703 | case M_SLEU_I: |
670a50eb | 5704 | s = "sltu"; |
3d3c5039 | 5705 | slei: |
d8a1c247 | 5706 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5707 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5708 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5709 | (int) BFD_RELOC_LO16); |
670a50eb | 5710 | break; |
3d3c5039 ILT |
5711 | |
5712 | case M_SLT_I: | |
6e8dda9c | 5713 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5714 | { |
0dd2d296 ILT |
5715 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5716 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5717 | return; |
3d3c5039 | 5718 | } |
d8a1c247 | 5719 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5720 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5721 | break; |
3d3c5039 ILT |
5722 | |
5723 | case M_SLTU_I: | |
6e8dda9c | 5724 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5725 | { |
0dd2d296 ILT |
5726 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5727 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5728 | return; |
3d3c5039 | 5729 | } |
d8a1c247 | 5730 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5731 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5732 | AT); | |
670a50eb | 5733 | break; |
3d3c5039 ILT |
5734 | |
5735 | case M_SNE: | |
670a50eb | 5736 | if (sreg == 0) |
0dd2d296 ILT |
5737 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5738 | treg); | |
670a50eb | 5739 | else if (treg == 0) |
0dd2d296 ILT |
5740 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5741 | sreg); | |
670a50eb ILT |
5742 | else |
5743 | { | |
0dd2d296 ILT |
5744 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5745 | sreg, treg); | |
5746 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5747 | dreg); | |
3d3c5039 | 5748 | } |
670a50eb | 5749 | return; |
3d3c5039 ILT |
5750 | |
5751 | case M_SNE_I: | |
670a50eb ILT |
5752 | if (imm_expr.X_add_number == 0) |
5753 | { | |
0dd2d296 ILT |
5754 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5755 | sreg); | |
670a50eb | 5756 | return; |
3d3c5039 | 5757 | } |
670a50eb ILT |
5758 | if (sreg == 0) |
5759 | { | |
9a7d824a | 5760 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5761 | ip->insn_mo->name); |
0dd2d296 | 5762 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5763 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5764 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5765 | return; |
3d3c5039 | 5766 | } |
6e8dda9c | 5767 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5768 | { |
0dd2d296 ILT |
5769 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5770 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5771 | used_at = 0; |
6e8dda9c ILT |
5772 | } |
5773 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5774 | { | |
5775 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5776 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5777 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5778 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5779 | used_at = 0; |
5780 | } | |
5781 | else | |
5782 | { | |
d8a1c247 | 5783 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5784 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5785 | sreg, AT); | |
670a50eb ILT |
5786 | used_at = 1; |
5787 | } | |
0dd2d296 | 5788 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5789 | if (used_at) |
5790 | break; | |
5791 | return; | |
3d3c5039 | 5792 | |
8358c818 ILT |
5793 | case M_DSUB_I: |
5794 | dbl = 1; | |
3d3c5039 | 5795 | case M_SUB_I: |
6e8dda9c | 5796 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5797 | { |
5798 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5799 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5800 | dbl ? "daddi" : "addi", |
9226253a | 5801 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5802 | return; |
3d3c5039 | 5803 | } |
d8a1c247 | 5804 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5805 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5806 | dbl ? "dsub" : "sub", |
5807 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5808 | break; |
3d3c5039 | 5809 | |
8358c818 ILT |
5810 | case M_DSUBU_I: |
5811 | dbl = 1; | |
3d3c5039 | 5812 | case M_SUBU_I: |
6e8dda9c | 5813 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5814 | { |
5815 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5816 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5817 | dbl ? "daddiu" : "addiu", |
9226253a | 5818 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5819 | return; |
3d3c5039 | 5820 | } |
d8a1c247 | 5821 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5822 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5823 | dbl ? "dsubu" : "subu", |
5824 | "d,v,t", dreg, sreg, AT); | |
5825 | break; | |
5826 | ||
5827 | case M_TEQ_I: | |
5828 | s = "teq"; | |
5829 | goto trap; | |
5830 | case M_TGE_I: | |
5831 | s = "tge"; | |
5832 | goto trap; | |
5833 | case M_TGEU_I: | |
5834 | s = "tgeu"; | |
5835 | goto trap; | |
5836 | case M_TLT_I: | |
5837 | s = "tlt"; | |
5838 | goto trap; | |
5839 | case M_TLTU_I: | |
5840 | s = "tltu"; | |
5841 | goto trap; | |
5842 | case M_TNE_I: | |
5843 | s = "tne"; | |
5844 | trap: | |
d8a1c247 | 5845 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5846 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5847 | break; |
3d3c5039 ILT |
5848 | |
5849 | case M_TRUNCWD: | |
5850 | case M_TRUNCWS: | |
8358c818 | 5851 | assert (mips_isa < 2); |
670a50eb ILT |
5852 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5853 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5854 | ||
5855 | /* | |
5856 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5857 | * or is there a reason for it? | |
5858 | */ | |
fbcfacb7 | 5859 | mips_emit_delays (true); |
becfe05e | 5860 | ++mips_noreorder; |
0dd2d296 ILT |
5861 | mips_any_noreorder = 1; |
5862 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5863 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5864 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5865 | expr1.X_add_number = 3; |
0dd2d296 | 5866 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5867 | (int) BFD_RELOC_LO16); |
670a50eb | 5868 | expr1.X_add_number = 2; |
0dd2d296 | 5869 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5870 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5871 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5872 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5873 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5874 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5875 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5876 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5877 | --mips_noreorder; |
670a50eb | 5878 | break; |
3d3c5039 ILT |
5879 | |
5880 | case M_ULH: | |
670a50eb ILT |
5881 | s = "lb"; |
5882 | goto ulh; | |
3d3c5039 | 5883 | case M_ULHU: |
670a50eb | 5884 | s = "lbu"; |
3d3c5039 | 5885 | ulh: |
8ea7f4e8 ILT |
5886 | if (offset_expr.X_add_number >= 0x7fff) |
5887 | as_bad ("operand overflow"); | |
670a50eb | 5888 | /* avoid load delay */ |
b9129c6f | 5889 | if (! target_big_endian) |
8ea7f4e8 | 5890 | offset_expr.X_add_number += 1; |
0dd2d296 | 5891 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5892 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5893 | if (! target_big_endian) |
8ea7f4e8 ILT |
5894 | offset_expr.X_add_number -= 1; |
5895 | else | |
5896 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5897 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5898 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5899 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5900 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5901 | break; |
3d3c5039 | 5902 | |
adcf2b9d ILT |
5903 | case M_ULD: |
5904 | s = "ldl"; | |
5905 | s2 = "ldr"; | |
5906 | off = 7; | |
5907 | goto ulw; | |
3d3c5039 | 5908 | case M_ULW: |
adcf2b9d ILT |
5909 | s = "lwl"; |
5910 | s2 = "lwr"; | |
5911 | off = 3; | |
5912 | ulw: | |
5913 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5914 | as_bad ("operand overflow"); |
b9129c6f | 5915 | if (! target_big_endian) |
adcf2b9d ILT |
5916 | offset_expr.X_add_number += off; |
5917 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5918 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5919 | if (! target_big_endian) |
adcf2b9d | 5920 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5921 | else |
adcf2b9d ILT |
5922 | offset_expr.X_add_number += off; |
5923 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5924 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5925 | return; |
3d3c5039 | 5926 | |
adcf2b9d ILT |
5927 | case M_ULD_A: |
5928 | s = "ldl"; | |
5929 | s2 = "ldr"; | |
5930 | off = 7; | |
5931 | goto ulwa; | |
5932 | case M_ULW_A: | |
5933 | s = "lwl"; | |
5934 | s2 = "lwr"; | |
5935 | off = 3; | |
5936 | ulwa: | |
5937 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5938 | if (breg != 0) |
5939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5940 | mips_isa < 3 ? "addu" : "daddu", | |
5941 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5942 | if (! target_big_endian) |
adcf2b9d ILT |
5943 | expr1.X_add_number = off; |
5944 | else | |
5945 | expr1.X_add_number = 0; | |
5946 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5947 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5948 | if (! target_big_endian) |
adcf2b9d ILT |
5949 | expr1.X_add_number = 0; |
5950 | else | |
5951 | expr1.X_add_number = off; | |
5952 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5953 | (int) BFD_RELOC_LO16, AT); | |
5954 | break; | |
5955 | ||
3d3c5039 ILT |
5956 | case M_ULH_A: |
5957 | case M_ULHU_A: | |
0dd2d296 | 5958 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5959 | if (breg != 0) |
5960 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5961 | mips_isa < 3 ? "addu" : "daddu", | |
5962 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5963 | if (target_big_endian) |
adcf2b9d ILT |
5964 | expr1.X_add_number = 0; |
5965 | macro_build ((char *) NULL, &icnt, &expr1, | |
5966 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5967 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5968 | if (target_big_endian) |
adcf2b9d | 5969 | expr1.X_add_number = 1; |
670a50eb | 5970 | else |
adcf2b9d ILT |
5971 | expr1.X_add_number = 0; |
5972 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5973 | (int) BFD_RELOC_LO16, AT); | |
5974 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5975 | treg, 8); | |
5976 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5977 | treg, AT); | |
670a50eb | 5978 | break; |
3d3c5039 ILT |
5979 | |
5980 | case M_USH: | |
8ea7f4e8 ILT |
5981 | if (offset_expr.X_add_number >= 0x7fff) |
5982 | as_bad ("operand overflow"); | |
b9129c6f | 5983 | if (target_big_endian) |
8ea7f4e8 | 5984 | offset_expr.X_add_number += 1; |
0dd2d296 | 5985 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5986 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5987 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5988 | if (target_big_endian) |
8ea7f4e8 ILT |
5989 | offset_expr.X_add_number -= 1; |
5990 | else | |
5991 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5992 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5993 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5994 | break; |
3d3c5039 | 5995 | |
adcf2b9d ILT |
5996 | case M_USD: |
5997 | s = "sdl"; | |
5998 | s2 = "sdr"; | |
5999 | off = 7; | |
6000 | goto usw; | |
3d3c5039 | 6001 | case M_USW: |
adcf2b9d ILT |
6002 | s = "swl"; |
6003 | s2 = "swr"; | |
6004 | off = 3; | |
6005 | usw: | |
6006 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6007 | as_bad ("operand overflow"); |
b9129c6f | 6008 | if (! target_big_endian) |
adcf2b9d ILT |
6009 | offset_expr.X_add_number += off; |
6010 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6011 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6012 | if (! target_big_endian) |
adcf2b9d | 6013 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6014 | else |
adcf2b9d ILT |
6015 | offset_expr.X_add_number += off; |
6016 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6017 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6018 | return; |
3d3c5039 | 6019 | |
adcf2b9d ILT |
6020 | case M_USD_A: |
6021 | s = "sdl"; | |
6022 | s2 = "sdr"; | |
6023 | off = 7; | |
6024 | goto uswa; | |
3d3c5039 | 6025 | case M_USW_A: |
adcf2b9d ILT |
6026 | s = "swl"; |
6027 | s2 = "swr"; | |
6028 | off = 3; | |
6029 | uswa: | |
0dd2d296 | 6030 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6031 | if (breg != 0) |
6032 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6033 | mips_isa < 3 ? "addu" : "daddu", | |
6034 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6035 | if (! target_big_endian) |
adcf2b9d | 6036 | expr1.X_add_number = off; |
670a50eb | 6037 | else |
adcf2b9d ILT |
6038 | expr1.X_add_number = 0; |
6039 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6040 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6041 | if (! target_big_endian) |
adcf2b9d ILT |
6042 | expr1.X_add_number = 0; |
6043 | else | |
6044 | expr1.X_add_number = off; | |
6045 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6046 | (int) BFD_RELOC_LO16, AT); | |
6047 | break; | |
6048 | ||
6049 | case M_USH_A: | |
6050 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6051 | if (breg != 0) |
6052 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6053 | mips_isa < 3 ? "addu" : "daddu", | |
6054 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6055 | if (! target_big_endian) |
adcf2b9d ILT |
6056 | expr1.X_add_number = 0; |
6057 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6058 | (int) BFD_RELOC_LO16, AT); | |
6059 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6060 | treg, 8); | |
b9129c6f | 6061 | if (! target_big_endian) |
adcf2b9d ILT |
6062 | expr1.X_add_number = 1; |
6063 | else | |
6064 | expr1.X_add_number = 0; | |
6065 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6066 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6067 | if (! target_big_endian) |
adcf2b9d ILT |
6068 | expr1.X_add_number = 0; |
6069 | else | |
6070 | expr1.X_add_number = 1; | |
6071 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6072 | (int) BFD_RELOC_LO16, AT); | |
6073 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6074 | treg, 8); | |
6075 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6076 | treg, AT); | |
670a50eb | 6077 | break; |
3d3c5039 ILT |
6078 | |
6079 | default: | |
efec4a28 DP |
6080 | /* FIXME: Check if this is one of the itbl macros, since they are |
6081 | added dynamically. */ | |
670a50eb | 6082 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6083 | break; |
3d3c5039 | 6084 | } |
670a50eb ILT |
6085 | if (mips_noat) |
6086 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
6087 | } |
6088 | ||
cc5703cd | 6089 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6090 | |
3d3c5039 | 6091 | static void |
cc5703cd | 6092 | mips16_macro (ip) |
3d3c5039 ILT |
6093 | struct mips_cl_insn *ip; |
6094 | { | |
cc5703cd ILT |
6095 | int mask; |
6096 | int xreg, yreg, zreg, tmp; | |
6097 | int icnt; | |
6098 | expressionS expr1; | |
6099 | int dbl; | |
6100 | const char *s, *s2, *s3; | |
3d3c5039 | 6101 | |
cc5703cd | 6102 | mask = ip->insn_mo->mask; |
3d3c5039 | 6103 | |
cc5703cd ILT |
6104 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6105 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6106 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6107 | |
cc5703cd | 6108 | icnt = 0; |
8358c818 | 6109 | |
cc5703cd ILT |
6110 | expr1.X_op = O_constant; |
6111 | expr1.X_op_symbol = NULL; | |
6112 | expr1.X_add_symbol = NULL; | |
6113 | expr1.X_add_number = 1; | |
8358c818 | 6114 | |
cc5703cd | 6115 | dbl = 0; |
517078c1 | 6116 | |
cc5703cd ILT |
6117 | switch (mask) |
6118 | { | |
6119 | default: | |
6120 | internalError (); | |
6121 | ||
6122 | case M_DDIV_3: | |
6123 | dbl = 1; | |
6124 | case M_DIV_3: | |
6125 | s = "mflo"; | |
6126 | goto do_div3; | |
6127 | case M_DREM_3: | |
6128 | dbl = 1; | |
6129 | case M_REM_3: | |
6130 | s = "mfhi"; | |
6131 | do_div3: | |
fbcfacb7 | 6132 | mips_emit_delays (true); |
cc5703cd ILT |
6133 | ++mips_noreorder; |
6134 | mips_any_noreorder = 1; | |
6135 | macro_build ((char *) NULL, &icnt, NULL, | |
6136 | dbl ? "ddiv" : "div", | |
6137 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6138 | expr1.X_add_number = 2; |
cc5703cd | 6139 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6140 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6141 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6142 | since that causes an overflow. We should do that as well, | |
6143 | but I don't see how to do the comparisons without a temporary | |
6144 | register. */ | |
6145 | --mips_noreorder; | |
6146 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6147 | break; | |
6148 | ||
6149 | case M_DIVU_3: | |
6150 | s = "divu"; | |
6151 | s2 = "mflo"; | |
6152 | goto do_divu3; | |
6153 | case M_REMU_3: | |
6154 | s = "divu"; | |
6155 | s2 = "mfhi"; | |
6156 | goto do_divu3; | |
6157 | case M_DDIVU_3: | |
6158 | s = "ddivu"; | |
6159 | s2 = "mflo"; | |
6160 | goto do_divu3; | |
6161 | case M_DREMU_3: | |
6162 | s = "ddivu"; | |
6163 | s2 = "mfhi"; | |
6164 | do_divu3: | |
fbcfacb7 | 6165 | mips_emit_delays (true); |
cc5703cd ILT |
6166 | ++mips_noreorder; |
6167 | mips_any_noreorder = 1; | |
6168 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6169 | expr1.X_add_number = 2; |
cc5703cd | 6170 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6171 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6172 | --mips_noreorder; | |
6173 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6174 | break; | |
6175 | ||
6176 | case M_DSUBU_I: | |
6177 | dbl = 1; | |
6178 | goto do_subu; | |
6179 | case M_SUBU_I: | |
6180 | do_subu: | |
6181 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6182 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6183 | dbl ? "daddiu" : "addiu", | |
6184 | "y,x,4", yreg, xreg); | |
6185 | break; | |
6186 | ||
6187 | case M_SUBU_I_2: | |
6188 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6189 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6190 | "x,k", xreg); | |
6191 | break; | |
6192 | ||
6193 | case M_DSUBU_I_2: | |
6194 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6195 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6196 | "y,j", yreg); | |
6197 | break; | |
6198 | ||
6199 | case M_BEQ: | |
6200 | s = "cmp"; | |
6201 | s2 = "bteqz"; | |
6202 | goto do_branch; | |
6203 | case M_BNE: | |
6204 | s = "cmp"; | |
6205 | s2 = "btnez"; | |
6206 | goto do_branch; | |
6207 | case M_BLT: | |
6208 | s = "slt"; | |
6209 | s2 = "btnez"; | |
6210 | goto do_branch; | |
6211 | case M_BLTU: | |
6212 | s = "sltu"; | |
6213 | s2 = "btnez"; | |
6214 | goto do_branch; | |
6215 | case M_BLE: | |
6216 | s = "slt"; | |
6217 | s2 = "bteqz"; | |
6218 | goto do_reverse_branch; | |
6219 | case M_BLEU: | |
6220 | s = "sltu"; | |
6221 | s2 = "bteqz"; | |
6222 | goto do_reverse_branch; | |
6223 | case M_BGE: | |
6224 | s = "slt"; | |
6225 | s2 = "bteqz"; | |
6226 | goto do_branch; | |
6227 | case M_BGEU: | |
6228 | s = "sltu"; | |
6229 | s2 = "bteqz"; | |
6230 | goto do_branch; | |
6231 | case M_BGT: | |
6232 | s = "slt"; | |
6233 | s2 = "btnez"; | |
6234 | goto do_reverse_branch; | |
6235 | case M_BGTU: | |
6236 | s = "sltu"; | |
6237 | s2 = "btnez"; | |
6238 | ||
6239 | do_reverse_branch: | |
6240 | tmp = xreg; | |
6241 | xreg = yreg; | |
6242 | yreg = tmp; | |
6243 | ||
6244 | do_branch: | |
6245 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6246 | xreg, yreg); | |
6247 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6248 | break; | |
6249 | ||
6250 | case M_BEQ_I: | |
6251 | s = "cmpi"; | |
6252 | s2 = "bteqz"; | |
6253 | s3 = "x,U"; | |
6254 | goto do_branch_i; | |
6255 | case M_BNE_I: | |
6256 | s = "cmpi"; | |
6257 | s2 = "btnez"; | |
6258 | s3 = "x,U"; | |
6259 | goto do_branch_i; | |
6260 | case M_BLT_I: | |
6261 | s = "slti"; | |
6262 | s2 = "btnez"; | |
6263 | s3 = "x,8"; | |
6264 | goto do_branch_i; | |
6265 | case M_BLTU_I: | |
6266 | s = "sltiu"; | |
6267 | s2 = "btnez"; | |
6268 | s3 = "x,8"; | |
6269 | goto do_branch_i; | |
6270 | case M_BLE_I: | |
6271 | s = "slti"; | |
6272 | s2 = "btnez"; | |
6273 | s3 = "x,8"; | |
6274 | goto do_addone_branch_i; | |
6275 | case M_BLEU_I: | |
6276 | s = "sltiu"; | |
6277 | s2 = "btnez"; | |
6278 | s3 = "x,8"; | |
6279 | goto do_addone_branch_i; | |
6280 | case M_BGE_I: | |
6281 | s = "slti"; | |
6282 | s2 = "bteqz"; | |
6283 | s3 = "x,8"; | |
6284 | goto do_branch_i; | |
6285 | case M_BGEU_I: | |
6286 | s = "sltiu"; | |
6287 | s2 = "bteqz"; | |
6288 | s3 = "x,8"; | |
6289 | goto do_branch_i; | |
6290 | case M_BGT_I: | |
6291 | s = "slti"; | |
6292 | s2 = "bteqz"; | |
6293 | s3 = "x,8"; | |
6294 | goto do_addone_branch_i; | |
6295 | case M_BGTU_I: | |
6296 | s = "sltiu"; | |
6297 | s2 = "bteqz"; | |
6298 | s3 = "x,8"; | |
6299 | ||
6300 | do_addone_branch_i: | |
6301 | ++imm_expr.X_add_number; | |
6302 | ||
6303 | do_branch_i: | |
6304 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6305 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6306 | break; | |
18e0764d ILT |
6307 | |
6308 | case M_ABS: | |
6309 | expr1.X_add_number = 0; | |
6310 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6311 | if (xreg != yreg) | |
6312 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6313 | "move", "y,X", xreg, yreg); | |
6314 | expr1.X_add_number = 2; | |
6315 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6316 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6317 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6318 | } |
6319 | } | |
6320 | ||
6321 | /* This routine assembles an instruction into its binary format. As a | |
6322 | side effect, it sets one of the global variables imm_reloc or | |
6323 | offset_reloc to the type of relocation to do if one of the operands | |
6324 | is an address expression. */ | |
6325 | ||
6326 | static void | |
6327 | mips_ip (str, ip) | |
6328 | char *str; | |
6329 | struct mips_cl_insn *ip; | |
6330 | { | |
6331 | char *s; | |
6332 | const char *args; | |
6333 | char c; | |
6334 | struct mips_opcode *insn; | |
6335 | char *argsStart; | |
6336 | unsigned int regno; | |
6337 | unsigned int lastregno = 0; | |
6338 | char *s_reset; | |
6339 | ||
6340 | insn_error = NULL; | |
6341 | ||
e2e5acfa | 6342 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6343 | continue; |
e2e5acfa JW |
6344 | if ( isspace(*s) ) |
6345 | *s++ = '\0'; | |
6346 | ||
cc5703cd ILT |
6347 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6348 | { | |
6349 | insn_error = "unrecognized opcode"; | |
6350 | return; | |
6351 | } | |
6352 | argsStart = s; | |
6353 | for (;;) | |
6354 | { | |
6355 | int insn_isa; | |
6356 | ||
6357 | assert (strcmp (insn->name, str) == 0); | |
6358 | ||
6359 | if (insn->pinfo == INSN_MACRO) | |
6360 | insn_isa = insn->match; | |
6361 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6362 | insn_isa = 2; | |
6363 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6364 | insn_isa = 3; | |
6365 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6366 | insn_isa = 4; | |
6367 | else | |
6368 | insn_isa = 1; | |
6369 | ||
6370 | if (insn_isa > mips_isa | |
16262668 ILT |
6371 | || (insn->pinfo != INSN_MACRO |
6372 | && (((insn->pinfo & INSN_ISA) == INSN_4650 | |
6373 | && ! mips_4650) | |
6374 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6375 | && ! mips_4010) | |
6376 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6377 | && ! mips_4100) | |
6378 | /* start-sanitize-r5900 */ | |
6379 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6380 | && ! mips_5900) | |
6381 | /* end-sanitize-r5900 */ | |
6382 | ))) | |
cc5703cd ILT |
6383 | { |
6384 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6385 | && strcmp (insn->name, insn[1].name) == 0) | |
6386 | { | |
6387 | ++insn; | |
6388 | continue; | |
6389 | } | |
6390 | if (insn_isa <= mips_isa) | |
6391 | insn_error = "opcode not supported on this processor"; | |
6392 | else | |
6393 | { | |
6394 | static char buf[100]; | |
6395 | ||
6396 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6397 | insn_error = buf; | |
6398 | } | |
6399 | return; | |
6400 | } | |
8358c818 | 6401 | |
670a50eb ILT |
6402 | ip->insn_mo = insn; |
6403 | ip->insn_opcode = insn->match; | |
6404 | for (args = insn->args;; ++args) | |
6405 | { | |
6406 | if (*s == ' ') | |
6407 | ++s; | |
6408 | switch (*args) | |
6409 | { | |
6410 | case '\0': /* end of args */ | |
6411 | if (*s == '\0') | |
6412 | return; | |
6413 | break; | |
3d3c5039 ILT |
6414 | |
6415 | case ',': | |
670a50eb ILT |
6416 | if (*s++ == *args) |
6417 | continue; | |
6418 | s--; | |
6419 | switch (*++args) | |
6420 | { | |
3d3c5039 ILT |
6421 | case 'r': |
6422 | case 'v': | |
670a50eb ILT |
6423 | ip->insn_opcode |= lastregno << 21; |
6424 | continue; | |
3d3c5039 ILT |
6425 | |
6426 | case 'w': | |
6427 | case 'W': | |
670a50eb ILT |
6428 | ip->insn_opcode |= lastregno << 16; |
6429 | continue; | |
3d3c5039 ILT |
6430 | |
6431 | case 'V': | |
670a50eb ILT |
6432 | ip->insn_opcode |= lastregno << 11; |
6433 | continue; | |
3d3c5039 | 6434 | } |
670a50eb | 6435 | break; |
3d3c5039 ILT |
6436 | |
6437 | case '(': | |
670a50eb ILT |
6438 | /* handle optional base register. |
6439 | Either the base register is omitted or | |
6440 | we must have a left paren. */ | |
6441 | /* this is dependent on the next operand specifier | |
6442 | is a 'b' for base register */ | |
6443 | assert (args[1] == 'b'); | |
6444 | if (*s == '\0') | |
6445 | return; | |
3d3c5039 | 6446 | |
670a50eb ILT |
6447 | case ')': /* these must match exactly */ |
6448 | if (*s++ == *args) | |
3d3c5039 | 6449 | continue; |
670a50eb ILT |
6450 | break; |
6451 | ||
6452 | case '<': /* must be at least one digit */ | |
6453 | /* | |
6454 | * According to the manual, if the shift amount is greater | |
6455 | * than 31 or less than 0 the the shift amount should be | |
6456 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6457 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6458 | */ |
6459 | my_getExpression (&imm_expr, s); | |
6460 | check_absolute_expr (ip, &imm_expr); | |
6461 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6462 | { | |
58d4951d ILT |
6463 | as_warn ("Improper shift amount (%ld)", |
6464 | (long) imm_expr.X_add_number); | |
9226253a | 6465 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6466 | } |
6467 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6468 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6469 | s = expr_end; |
6470 | continue; | |
6471 | ||
56c96faa ILT |
6472 | case '>': /* shift amount minus 32 */ |
6473 | my_getExpression (&imm_expr, s); | |
6474 | check_absolute_expr (ip, &imm_expr); | |
6475 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6476 | || (unsigned long) imm_expr.X_add_number > 63) | |
6477 | break; | |
6478 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6479 | imm_expr.X_op = O_absent; | |
6480 | s = expr_end; | |
6481 | continue; | |
6482 | ||
9226253a | 6483 | case 'k': /* cache code */ |
d8a1c247 | 6484 | case 'h': /* prefx code */ |
9226253a ILT |
6485 | my_getExpression (&imm_expr, s); |
6486 | check_absolute_expr (ip, &imm_expr); | |
6487 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6488 | { | |
d8a1c247 KR |
6489 | as_warn ("Invalid value for `%s' (%lu)", |
6490 | ip->insn_mo->name, | |
9226253a ILT |
6491 | (unsigned long) imm_expr.X_add_number); |
6492 | imm_expr.X_add_number &= 0x1f; | |
6493 | } | |
d8a1c247 KR |
6494 | if (*args == 'k') |
6495 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6496 | else | |
6497 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6498 | imm_expr.X_op = O_absent; |
6499 | s = expr_end; | |
6500 | continue; | |
6501 | ||
670a50eb ILT |
6502 | case 'c': /* break code */ |
6503 | my_getExpression (&imm_expr, s); | |
6504 | check_absolute_expr (ip, &imm_expr); | |
6505 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6506 | as_warn ("Illegal break code (%ld)", |
6507 | (long) imm_expr.X_add_number); | |
670a50eb | 6508 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6509 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6510 | s = expr_end; |
6511 | continue; | |
6512 | ||
918692a5 ILT |
6513 | case 'B': /* syscall code */ |
6514 | my_getExpression (&imm_expr, s); | |
6515 | check_absolute_expr (ip, &imm_expr); | |
6516 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6517 | as_warn ("Illegal syscall code (%ld)", |
6518 | (long) imm_expr.X_add_number); | |
918692a5 | 6519 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6520 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6521 | s = expr_end; |
6522 | continue; | |
6523 | ||
0aa07269 ILT |
6524 | case 'C': /* Coprocessor code */ |
6525 | my_getExpression (&imm_expr, s); | |
6526 | check_absolute_expr (ip, &imm_expr); | |
6527 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6528 | { | |
58d4951d ILT |
6529 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6530 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6531 | imm_expr.X_add_number &= ((1<<25) - 1); |
6532 | } | |
6533 | ip->insn_opcode |= imm_expr.X_add_number; | |
6534 | imm_expr.X_op = O_absent; | |
6535 | s = expr_end; | |
6536 | continue; | |
6537 | ||
670a50eb ILT |
6538 | case 'b': /* base register */ |
6539 | case 'd': /* destination register */ | |
6540 | case 's': /* source register */ | |
6541 | case 't': /* target register */ | |
6542 | case 'r': /* both target and source */ | |
6543 | case 'v': /* both dest and source */ | |
6544 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6545 | case 'E': /* coprocessor target register */ |
6546 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6547 | case 'x': /* ignore register name */ |
ff3a5c18 | 6548 | case 'z': /* must be zero register */ |
670a50eb ILT |
6549 | s_reset = s; |
6550 | if (s[0] == '$') | |
6551 | { | |
6552 | if (isdigit (s[1])) | |
6553 | { | |
6554 | ++s; | |
6555 | regno = 0; | |
6556 | do | |
6557 | { | |
6558 | regno *= 10; | |
6559 | regno += *s - '0'; | |
6560 | ++s; | |
6561 | } | |
6562 | while (isdigit (*s)); | |
0aa07269 ILT |
6563 | if (regno > 31) |
6564 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6565 | } |
0dd2d296 ILT |
6566 | else if (*args == 'E' || *args == 'G') |
6567 | goto notreg; | |
6568 | else | |
670a50eb | 6569 | { |
0aa07269 ILT |
6570 | if (s[1] == 'f' && s[2] == 'p') |
6571 | { | |
6572 | s += 3; | |
9226253a | 6573 | regno = FP; |
0aa07269 ILT |
6574 | } |
6575 | else if (s[1] == 's' && s[2] == 'p') | |
6576 | { | |
6577 | s += 3; | |
9226253a | 6578 | regno = SP; |
0aa07269 ILT |
6579 | } |
6580 | else if (s[1] == 'g' && s[2] == 'p') | |
6581 | { | |
6582 | s += 3; | |
9226253a | 6583 | regno = GP; |
0aa07269 ILT |
6584 | } |
6585 | else if (s[1] == 'a' && s[2] == 't') | |
6586 | { | |
6587 | s += 3; | |
9226253a | 6588 | regno = AT; |
0aa07269 | 6589 | } |
b2b8c24e ILT |
6590 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6591 | { | |
6592 | s += 4; | |
6593 | regno = KT0; | |
6594 | } | |
6595 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6596 | { | |
6597 | s += 4; | |
6598 | regno = KT1; | |
6599 | } | |
efec4a28 DP |
6600 | else if (itbl_have_entries) |
6601 | { | |
6602 | char *p, *n; | |
6603 | int r; | |
6604 | ||
6605 | p = s+1; /* advance past '$' */ | |
6606 | n = itbl_get_field(&p); /* n is name */ | |
6607 | ||
6608 | /* See if this is a register defined in an | |
6609 | itbl entry */ | |
6610 | if (r = itbl_get_reg_val(n), r) | |
6611 | { | |
6612 | /* Get_field advances to the start of the next | |
6613 | field, so we need to back rack to the end of | |
6614 | the last field. */ | |
6615 | if (p) | |
6616 | s = p-1; | |
6617 | else | |
6618 | s = strchr(s,'\0'); | |
6619 | regno = r; | |
6620 | } | |
6621 | else | |
6622 | goto notreg; | |
6623 | } | |
0aa07269 ILT |
6624 | else |
6625 | goto notreg; | |
670a50eb | 6626 | } |
9753202d ILT |
6627 | if (regno == AT |
6628 | && ! mips_noat | |
6629 | && *args != 'E' | |
6630 | && *args != 'G') | |
13fe1379 | 6631 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6632 | c = *args; |
6633 | if (*s == ' ') | |
6634 | s++; | |
6635 | if (args[1] != *s) | |
6636 | { | |
6637 | if (c == 'r' || c == 'v' || c == 'w') | |
6638 | { | |
6639 | regno = lastregno; | |
6640 | s = s_reset; | |
6641 | args++; | |
6642 | } | |
6643 | } | |
ff3a5c18 ILT |
6644 | /* 'z' only matches $0. */ |
6645 | if (c == 'z' && regno != 0) | |
6646 | break; | |
efec4a28 DP |
6647 | |
6648 | /* Now that we have assembled one operand, we use the args string | |
6649 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
6650 | switch (c) |
6651 | { | |
3d3c5039 ILT |
6652 | case 'r': |
6653 | case 's': | |
6654 | case 'v': | |
6655 | case 'b': | |
670a50eb ILT |
6656 | ip->insn_opcode |= regno << 21; |
6657 | break; | |
3d3c5039 | 6658 | case 'd': |
918692a5 | 6659 | case 'G': |
670a50eb ILT |
6660 | ip->insn_opcode |= regno << 11; |
6661 | break; | |
3d3c5039 ILT |
6662 | case 'w': |
6663 | case 't': | |
918692a5 | 6664 | case 'E': |
670a50eb | 6665 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6666 | break; |
6667 | case 'x': | |
6668 | /* This case exists because on the r3000 trunc | |
6669 | expands into a macro which requires a gp | |
6670 | register. On the r6000 or r4000 it is | |
6671 | assembled into a single instruction which | |
6672 | ignores the register. Thus the insn version | |
6673 | is MIPS_ISA2 and uses 'x', and the macro | |
6674 | version is MIPS_ISA1 and uses 't'. */ | |
6675 | break; | |
ff3a5c18 ILT |
6676 | case 'z': |
6677 | /* This case is for the div instruction, which | |
6678 | acts differently if the destination argument | |
6679 | is $0. This only matches $0, and is checked | |
6680 | outside the switch. */ | |
6681 | break; | |
efec4a28 DP |
6682 | case 'D': |
6683 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
6684 | break; | |
6685 | /* What about all other operands like 'i', | |
6686 | which can be specified in the opcode table? */ | |
3d3c5039 | 6687 | } |
670a50eb ILT |
6688 | lastregno = regno; |
6689 | continue; | |
3d3c5039 ILT |
6690 | } |
6691 | notreg: | |
670a50eb ILT |
6692 | switch (*args++) |
6693 | { | |
3d3c5039 ILT |
6694 | case 'r': |
6695 | case 'v': | |
670a50eb ILT |
6696 | ip->insn_opcode |= lastregno << 21; |
6697 | continue; | |
3d3c5039 | 6698 | case 'w': |
670a50eb ILT |
6699 | ip->insn_opcode |= lastregno << 16; |
6700 | continue; | |
3d3c5039 | 6701 | } |
670a50eb | 6702 | break; |
3d3c5039 | 6703 | |
670a50eb ILT |
6704 | case 'D': /* floating point destination register */ |
6705 | case 'S': /* floating point source register */ | |
6706 | case 'T': /* floating point target register */ | |
d8a1c247 | 6707 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6708 | case 'V': |
6709 | case 'W': | |
670a50eb ILT |
6710 | s_reset = s; |
6711 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6712 | { | |
6713 | s += 2; | |
6714 | regno = 0; | |
6715 | do | |
6716 | { | |
6717 | regno *= 10; | |
6718 | regno += *s - '0'; | |
6719 | ++s; | |
6720 | } | |
6721 | while (isdigit (*s)); | |
6722 | ||
6723 | if (regno > 31) | |
6724 | as_bad ("Invalid float register number (%d)", regno); | |
6725 | ||
9226253a ILT |
6726 | if ((regno & 1) != 0 |
6727 | && mips_isa < 3 | |
538034cf ILT |
6728 | && ! (strcmp (str, "mtc1") == 0 |
6729 | || strcmp (str, "mfc1") == 0 | |
6730 | || strcmp (str, "lwc1") == 0 | |
6731 | || strcmp (str, "swc1") == 0 | |
6732 | || strcmp (str, "l.s") == 0 | |
6733 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6734 | as_warn ("Float register should be even, was %d", |
6735 | regno); | |
6736 | ||
6737 | c = *args; | |
6738 | if (*s == ' ') | |
6739 | s++; | |
6740 | if (args[1] != *s) | |
6741 | { | |
6742 | if (c == 'V' || c == 'W') | |
6743 | { | |
6744 | regno = lastregno; | |
6745 | s = s_reset; | |
6746 | args++; | |
3d3c5039 ILT |
6747 | } |
6748 | } | |
670a50eb ILT |
6749 | switch (c) |
6750 | { | |
3d3c5039 | 6751 | case 'D': |
670a50eb ILT |
6752 | ip->insn_opcode |= regno << 6; |
6753 | break; | |
3d3c5039 ILT |
6754 | case 'V': |
6755 | case 'S': | |
670a50eb ILT |
6756 | ip->insn_opcode |= regno << 11; |
6757 | break; | |
3d3c5039 ILT |
6758 | case 'W': |
6759 | case 'T': | |
670a50eb | 6760 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6761 | break; |
6762 | case 'R': | |
6763 | ip->insn_opcode |= regno << 21; | |
6764 | break; | |
3d3c5039 | 6765 | } |
670a50eb ILT |
6766 | lastregno = regno; |
6767 | continue; | |
3d3c5039 | 6768 | } |
670a50eb ILT |
6769 | switch (*args++) |
6770 | { | |
3d3c5039 | 6771 | case 'V': |
670a50eb ILT |
6772 | ip->insn_opcode |= lastregno << 11; |
6773 | continue; | |
3d3c5039 | 6774 | case 'W': |
670a50eb ILT |
6775 | ip->insn_opcode |= lastregno << 16; |
6776 | continue; | |
3d3c5039 | 6777 | } |
670a50eb | 6778 | break; |
3d3c5039 ILT |
6779 | |
6780 | case 'I': | |
670a50eb | 6781 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6782 | if (imm_expr.X_op != O_big |
6783 | && imm_expr.X_op != O_constant) | |
6784 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6785 | s = expr_end; |
6786 | continue; | |
3d3c5039 ILT |
6787 | |
6788 | case 'A': | |
670a50eb ILT |
6789 | my_getExpression (&offset_expr, s); |
6790 | imm_reloc = BFD_RELOC_32; | |
6791 | s = expr_end; | |
6792 | continue; | |
3d3c5039 ILT |
6793 | |
6794 | case 'F': | |
19ed8960 ILT |
6795 | case 'L': |
6796 | case 'f': | |
6797 | case 'l': | |
6798 | { | |
6799 | int f64; | |
6800 | char *save_in; | |
6801 | char *err; | |
6802 | unsigned char temp[8]; | |
604633ae ILT |
6803 | int len; |
6804 | unsigned int length; | |
19ed8960 ILT |
6805 | segT seg; |
6806 | subsegT subseg; | |
6807 | char *p; | |
6808 | ||
6809 | /* These only appear as the last operand in an | |
6810 | instruction, and every instruction that accepts | |
6811 | them in any variant accepts them in all variants. | |
6812 | This means we don't have to worry about backing out | |
6813 | any changes if the instruction does not match. | |
6814 | ||
6815 | The difference between them is the size of the | |
6816 | floating point constant and where it goes. For 'F' | |
6817 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6818 | is 32 bits. Where the constant is placed is based | |
6819 | on how the MIPS assembler does things: | |
6820 | F -- .rdata | |
6821 | L -- .lit8 | |
6822 | f -- immediate value | |
6823 | l -- .lit4 | |
0dd2d296 | 6824 | |
55933a58 ILT |
6825 | The .lit4 and .lit8 sections are only used if |
6826 | permitted by the -G argument. | |
6827 | ||
6828 | When generating embedded PIC code, we use the | |
6829 | .lit8 section but not the .lit4 section (we can do | |
6830 | .lit4 inline easily; we need to put .lit8 | |
6831 | somewhere in the data segment, and using .lit8 | |
6832 | permits the linker to eventually combine identical | |
6833 | .lit8 entries). */ | |
19ed8960 ILT |
6834 | |
6835 | f64 = *args == 'F' || *args == 'L'; | |
6836 | ||
6837 | save_in = input_line_pointer; | |
6838 | input_line_pointer = s; | |
604633ae ILT |
6839 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6840 | length = len; | |
19ed8960 ILT |
6841 | s = input_line_pointer; |
6842 | input_line_pointer = save_in; | |
6843 | if (err != NULL && *err != '\0') | |
6844 | { | |
6845 | as_bad ("Bad floating point constant: %s", err); | |
6846 | memset (temp, '\0', sizeof temp); | |
6847 | length = f64 ? 8 : 4; | |
6848 | } | |
6849 | ||
6850 | assert (length == (f64 ? 8 : 4)); | |
6851 | ||
0dd2d296 | 6852 | if (*args == 'f' |
55933a58 | 6853 | || (*args == 'l' |
1dc1e798 KR |
6854 | && (! USE_GLOBAL_POINTER_OPT |
6855 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6856 | || g_switch_value < 4) |
1113140a | 6857 | )) |
19ed8960 ILT |
6858 | { |
6859 | imm_expr.X_op = O_constant; | |
b9129c6f | 6860 | if (! target_big_endian) |
19ed8960 ILT |
6861 | imm_expr.X_add_number = |
6862 | (((((((int) temp[3] << 8) | |
6863 | | temp[2]) << 8) | |
6864 | | temp[1]) << 8) | |
6865 | | temp[0]); | |
6866 | else | |
6867 | imm_expr.X_add_number = | |
6868 | (((((((int) temp[0] << 8) | |
6869 | | temp[1]) << 8) | |
6870 | | temp[2]) << 8) | |
6871 | | temp[3]); | |
6872 | } | |
6873 | else | |
6874 | { | |
0dd2d296 ILT |
6875 | const char *newname; |
6876 | segT new_seg; | |
6877 | ||
19ed8960 ILT |
6878 | /* Switch to the right section. */ |
6879 | seg = now_seg; | |
6880 | subseg = now_subseg; | |
6881 | switch (*args) | |
6882 | { | |
0dd2d296 | 6883 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6884 | case 'L': |
1113140a | 6885 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6886 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6887 | newname = ".lit8"; |
0dd2d296 ILT |
6888 | break; |
6889 | case 'F': | |
d2c71068 | 6890 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6891 | break; |
6892 | case 'l': | |
1dc1e798 KR |
6893 | assert (!USE_GLOBAL_POINTER_OPT |
6894 | || g_switch_value >= 4); | |
0dd2d296 | 6895 | newname = ".lit4"; |
19ed8960 ILT |
6896 | break; |
6897 | } | |
0dd2d296 | 6898 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6899 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6900 | bfd_set_section_flags (stdoutput, new_seg, | |
6901 | (SEC_ALLOC | |
6902 | | SEC_LOAD | |
6903 | | SEC_READONLY | |
6904 | | SEC_DATA)); | |
e2e5acfa JW |
6905 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
6906 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
6907 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
6908 | record_alignment (new_seg, 4); |
6909 | else | |
6910 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6911 | if (seg == now_seg) |
6912 | as_bad ("Can't use floating point insn in this section"); | |
6913 | ||
6914 | /* Set the argument to the current address in the | |
6e8dda9c | 6915 | section. */ |
19ed8960 ILT |
6916 | offset_expr.X_op = O_symbol; |
6917 | offset_expr.X_add_symbol = | |
6918 | symbol_new ("L0\001", now_seg, | |
6919 | (valueT) frag_now_fix (), frag_now); | |
6920 | offset_expr.X_add_number = 0; | |
6921 | ||
6922 | /* Put the floating point number into the section. */ | |
604633ae | 6923 | p = frag_more ((int) length); |
19ed8960 ILT |
6924 | memcpy (p, temp, length); |
6925 | ||
6926 | /* Switch back to the original section. */ | |
6927 | subseg_set (seg, subseg); | |
6928 | } | |
6929 | } | |
670a50eb ILT |
6930 | continue; |
6931 | ||
6932 | case 'i': /* 16 bit unsigned immediate */ | |
6933 | case 'j': /* 16 bit signed immediate */ | |
6934 | imm_reloc = BFD_RELOC_LO16; | |
6935 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6936 | if (c != '\0') |
670a50eb ILT |
6937 | { |
6938 | if (c != 'l') | |
6939 | { | |
5ac34ac3 | 6940 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6941 | imm_expr.X_add_number = |
6942 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6943 | else if (c == 'h') | |
867a58b3 ILT |
6944 | { |
6945 | imm_reloc = BFD_RELOC_HI16_S; | |
6946 | imm_unmatched_hi = true; | |
6947 | } | |
670a50eb ILT |
6948 | else |
6949 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6950 | } |
670a50eb | 6951 | } |
670a50eb ILT |
6952 | if (*args == 'i') |
6953 | { | |
344a8d61 | 6954 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6955 | || ((imm_expr.X_add_number < 0 |
6956 | || imm_expr.X_add_number >= 0x10000) | |
6957 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6958 | { |
6959 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6960 | !strcmp (insn->name, insn[1].name)) | |
6961 | break; | |
9753202d ILT |
6962 | if (imm_expr.X_op != O_constant |
6963 | && imm_expr.X_op != O_big) | |
6964 | insn_error = "absolute expression required"; | |
6965 | else | |
6966 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6967 | } |
670a50eb ILT |
6968 | } |
6969 | else | |
6970 | { | |
d9aba805 ILT |
6971 | int more; |
6972 | offsetT max; | |
6973 | ||
be22008b ILT |
6974 | /* The upper bound should be 0x8000, but |
6975 | unfortunately the MIPS assembler accepts numbers | |
6976 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6977 | we want to be compatible. We only permit this |
6978 | extended range for an instruction which does not | |
6979 | provide any further alternates, since those | |
6980 | alternates may handle other cases. People should | |
6981 | use the numbers they mean, rather than relying on | |
6982 | a mysterious sign extension. */ | |
6983 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6984 | strcmp (insn->name, insn[1].name) == 0); | |
6985 | if (more) | |
6986 | max = 0x8000; | |
6987 | else | |
6988 | max = 0x10000; | |
344a8d61 | 6989 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6990 | || ((imm_expr.X_add_number < -0x8000 |
6991 | || imm_expr.X_add_number >= max) | |
6992 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6993 | || (more |
6994 | && imm_expr.X_add_number < 0 | |
6995 | && mips_isa >= 3 | |
6996 | && imm_expr.X_unsigned | |
6997 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6998 | { |
d9aba805 | 6999 | if (more) |
99c24539 | 7000 | break; |
9753202d ILT |
7001 | if (imm_expr.X_op != O_constant |
7002 | && imm_expr.X_op != O_big) | |
7003 | insn_error = "absolute expression required"; | |
7004 | else | |
7005 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7006 | } |
3d3c5039 | 7007 | } |
670a50eb ILT |
7008 | s = expr_end; |
7009 | continue; | |
7010 | ||
7011 | case 'o': /* 16 bit offset */ | |
7012 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7013 | |
7014 | /* If this value won't fit into a 16 bit offset, then go | |
7015 | find a macro that will generate the 32 bit offset | |
7016 | code pattern. As a special hack, we accept the | |
7017 | difference of two local symbols as a constant. This | |
7018 | is required to suppose embedded PIC switches, which | |
7019 | use an instruction which looks like | |
7020 | lw $4,$L12-$LS12($4) | |
7021 | The problem with handling this in a more general | |
7022 | fashion is that the macro function doesn't expect to | |
7023 | see anything which can be handled in a single | |
7024 | constant instruction. */ | |
6f0b87c3 SS |
7025 | if (c == 0 |
7026 | && (offset_expr.X_op != O_constant | |
7027 | || offset_expr.X_add_number >= 0x8000 | |
7028 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7029 | && (mips_pic != EMBEDDED_PIC |
7030 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7031 | || now_seg != text_section |
7032 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7033 | != text_section))) | |
670a50eb | 7034 | break; |
3d3c5039 | 7035 | |
670a50eb ILT |
7036 | offset_reloc = BFD_RELOC_LO16; |
7037 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7038 | { |
7039 | assert (offset_expr.X_op == O_constant); | |
7040 | offset_expr.X_add_number = | |
7041 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7042 | } | |
cc5703cd ILT |
7043 | s = expr_end; |
7044 | continue; | |
7045 | ||
7046 | case 'p': /* pc relative offset */ | |
7047 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7048 | my_getExpression (&offset_expr, s); | |
7049 | s = expr_end; | |
7050 | continue; | |
7051 | ||
7052 | case 'u': /* upper 16 bits */ | |
7053 | c = my_getSmallExpression (&imm_expr, s); | |
7054 | if (imm_expr.X_op == O_constant | |
7055 | && (imm_expr.X_add_number < 0 | |
7056 | || imm_expr.X_add_number >= 0x10000)) | |
7057 | as_bad ("lui expression not in range 0..65535"); | |
7058 | imm_reloc = BFD_RELOC_LO16; | |
7059 | if (c) | |
7060 | { | |
7061 | if (c != 'l') | |
7062 | { | |
7063 | if (imm_expr.X_op == O_constant) | |
7064 | imm_expr.X_add_number = | |
7065 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7066 | else if (c == 'h') | |
7067 | { | |
7068 | imm_reloc = BFD_RELOC_HI16_S; | |
7069 | imm_unmatched_hi = true; | |
7070 | } | |
7071 | else | |
7072 | imm_reloc = BFD_RELOC_HI16; | |
7073 | } | |
7074 | } | |
7075 | s = expr_end; | |
7076 | continue; | |
7077 | ||
7078 | case 'a': /* 26 bit address */ | |
7079 | my_getExpression (&offset_expr, s); | |
7080 | s = expr_end; | |
7081 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7082 | continue; | |
7083 | ||
7084 | case 'N': /* 3 bit branch condition code */ | |
7085 | case 'M': /* 3 bit compare condition code */ | |
7086 | if (strncmp (s, "$fcc", 4) != 0) | |
7087 | break; | |
7088 | s += 4; | |
7089 | regno = 0; | |
7090 | do | |
7091 | { | |
7092 | regno *= 10; | |
7093 | regno += *s - '0'; | |
7094 | ++s; | |
7095 | } | |
7096 | while (isdigit (*s)); | |
7097 | if (regno > 7) | |
7098 | as_bad ("invalid condition code register $fcc%d", regno); | |
7099 | if (*args == 'N') | |
7100 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7101 | else | |
7102 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7103 | continue; | |
7104 | ||
7105 | default: | |
7106 | fprintf (stderr, "bad char = '%c'\n", *args); | |
7107 | internalError (); | |
7108 | } | |
7109 | break; | |
7110 | } | |
7111 | /* Args don't match. */ | |
7112 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7113 | !strcmp (insn->name, insn[1].name)) | |
7114 | { | |
7115 | ++insn; | |
7116 | s = argsStart; | |
7117 | continue; | |
7118 | } | |
7119 | insn_error = "illegal operands"; | |
7120 | return; | |
7121 | } | |
7122 | } | |
7123 | ||
7124 | /* This routine assembles an instruction into its binary format when | |
7125 | assembling for the mips16. As a side effect, it sets one of the | |
7126 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7127 | relocation to do if one of the operands is an address expression. |
7128 | It also sets mips16_small and mips16_ext if the user explicitly | |
7129 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7130 | |
7131 | static void | |
7132 | mips16_ip (str, ip) | |
7133 | char *str; | |
7134 | struct mips_cl_insn *ip; | |
7135 | { | |
7136 | char *s; | |
cc5703cd ILT |
7137 | const char *args; |
7138 | struct mips_opcode *insn; | |
7139 | char *argsstart; | |
7140 | unsigned int regno; | |
7141 | unsigned int lastregno = 0; | |
7142 | char *s_reset; | |
7143 | ||
7144 | insn_error = NULL; | |
7145 | ||
8728fa92 ILT |
7146 | mips16_small = false; |
7147 | mips16_ext = false; | |
cc5703cd ILT |
7148 | |
7149 | for (s = str; islower (*s); ++s) | |
7150 | ; | |
7151 | switch (*s) | |
7152 | { | |
7153 | case '\0': | |
7154 | break; | |
7155 | ||
7156 | case ' ': | |
7157 | *s++ = '\0'; | |
7158 | break; | |
7159 | ||
7160 | case '.': | |
7161 | if (s[1] == 't' && s[2] == ' ') | |
7162 | { | |
7163 | *s = '\0'; | |
8728fa92 | 7164 | mips16_small = true; |
cc5703cd ILT |
7165 | s += 3; |
7166 | break; | |
7167 | } | |
7168 | else if (s[1] == 'e' && s[2] == ' ') | |
7169 | { | |
7170 | *s = '\0'; | |
8728fa92 | 7171 | mips16_ext = true; |
cc5703cd ILT |
7172 | s += 3; |
7173 | break; | |
7174 | } | |
7175 | /* Fall through. */ | |
7176 | default: | |
7177 | insn_error = "unknown opcode"; | |
7178 | return; | |
7179 | } | |
7180 | ||
8728fa92 ILT |
7181 | if (! mips16_autoextend && ! mips16_ext) |
7182 | mips16_small = true; | |
7183 | ||
cc5703cd ILT |
7184 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7185 | { | |
7186 | insn_error = "unrecognized opcode"; | |
7187 | return; | |
7188 | } | |
7189 | ||
7190 | argsstart = s; | |
7191 | for (;;) | |
7192 | { | |
7193 | assert (strcmp (insn->name, str) == 0); | |
7194 | ||
7195 | ip->insn_mo = insn; | |
7196 | ip->insn_opcode = insn->match; | |
7197 | ip->use_extend = false; | |
7198 | imm_expr.X_op = O_absent; | |
7199 | imm_reloc = BFD_RELOC_UNUSED; | |
7200 | offset_expr.X_op = O_absent; | |
7201 | offset_reloc = BFD_RELOC_UNUSED; | |
7202 | for (args = insn->args; 1; ++args) | |
7203 | { | |
7204 | int c; | |
7205 | ||
7206 | if (*s == ' ') | |
7207 | ++s; | |
7208 | ||
7209 | /* In this switch statement we call break if we did not find | |
7210 | a match, continue if we did find a match, or return if we | |
7211 | are done. */ | |
7212 | ||
7213 | c = *args; | |
7214 | switch (c) | |
7215 | { | |
7216 | case '\0': | |
7217 | if (*s == '\0') | |
7218 | { | |
7219 | /* Stuff the immediate value in now, if we can. */ | |
7220 | if (imm_expr.X_op == O_constant | |
7221 | && imm_reloc > BFD_RELOC_UNUSED | |
7222 | && insn->pinfo != INSN_MACRO) | |
7223 | { | |
15e69f98 ILT |
7224 | mips16_immed ((char *) NULL, 0, |
7225 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7226 | imm_expr.X_add_number, true, mips16_small, |
7227 | mips16_ext, &ip->insn_opcode, | |
7228 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7229 | imm_expr.X_op = O_absent; |
7230 | imm_reloc = BFD_RELOC_UNUSED; | |
7231 | } | |
7232 | ||
7233 | return; | |
7234 | } | |
7235 | break; | |
7236 | ||
7237 | case ',': | |
7238 | if (*s++ == c) | |
7239 | continue; | |
7240 | s--; | |
7241 | switch (*++args) | |
7242 | { | |
7243 | case 'v': | |
7244 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7245 | continue; | |
7246 | case 'w': | |
7247 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7248 | continue; | |
7249 | } | |
7250 | break; | |
7251 | ||
7252 | case '(': | |
7253 | case ')': | |
7254 | if (*s++ == c) | |
7255 | continue; | |
7256 | break; | |
7257 | ||
7258 | case 'v': | |
7259 | case 'w': | |
7260 | if (s[0] != '$') | |
7261 | { | |
7262 | if (c == 'v') | |
7263 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7264 | else | |
7265 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7266 | ++args; | |
7267 | continue; | |
7268 | } | |
7269 | /* Fall through. */ | |
7270 | case 'x': | |
7271 | case 'y': | |
7272 | case 'z': | |
7273 | case 'Z': | |
7274 | case '0': | |
7275 | case 'S': | |
7276 | case 'R': | |
7277 | case 'X': | |
7278 | case 'Y': | |
7279 | if (s[0] != '$') | |
7280 | break; | |
7281 | s_reset = s; | |
7282 | if (isdigit (s[1])) | |
7283 | { | |
7284 | ++s; | |
7285 | regno = 0; | |
7286 | do | |
7287 | { | |
7288 | regno *= 10; | |
7289 | regno += *s - '0'; | |
7290 | ++s; | |
7291 | } | |
7292 | while (isdigit (*s)); | |
7293 | if (regno > 31) | |
7294 | { | |
7295 | as_bad ("invalid register number (%d)", regno); | |
7296 | regno = 2; | |
7297 | } | |
7298 | } | |
7299 | else | |
7300 | { | |
7301 | if (s[1] == 'f' && s[2] == 'p') | |
7302 | { | |
7303 | s += 3; | |
7304 | regno = FP; | |
7305 | } | |
7306 | else if (s[1] == 's' && s[2] == 'p') | |
7307 | { | |
7308 | s += 3; | |
7309 | regno = SP; | |
7310 | } | |
7311 | else if (s[1] == 'g' && s[2] == 'p') | |
7312 | { | |
7313 | s += 3; | |
7314 | regno = GP; | |
7315 | } | |
7316 | else if (s[1] == 'a' && s[2] == 't') | |
7317 | { | |
7318 | s += 3; | |
7319 | regno = AT; | |
7320 | } | |
7321 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7322 | { | |
7323 | s += 4; | |
7324 | regno = KT0; | |
7325 | } | |
7326 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7327 | { | |
7328 | s += 4; | |
7329 | regno = KT1; | |
7330 | } | |
7331 | else | |
7332 | break; | |
7333 | } | |
7334 | ||
7335 | if (*s == ' ') | |
7336 | ++s; | |
7337 | if (args[1] != *s) | |
7338 | { | |
7339 | if (c == 'v' || c == 'w') | |
7340 | { | |
7341 | regno = mips16_to_32_reg_map[lastregno]; | |
7342 | s = s_reset; | |
7343 | args++; | |
7344 | } | |
7345 | } | |
7346 | ||
7347 | switch (c) | |
7348 | { | |
7349 | case 'x': | |
7350 | case 'y': | |
7351 | case 'z': | |
7352 | case 'v': | |
7353 | case 'w': | |
7354 | case 'Z': | |
7355 | regno = mips32_to_16_reg_map[regno]; | |
7356 | break; | |
7357 | ||
7358 | case '0': | |
7359 | if (regno != 0) | |
7360 | regno = ILLEGAL_REG; | |
7361 | break; | |
7362 | ||
7363 | case 'S': | |
7364 | if (regno != SP) | |
7365 | regno = ILLEGAL_REG; | |
7366 | break; | |
7367 | ||
7368 | case 'R': | |
7369 | if (regno != RA) | |
7370 | regno = ILLEGAL_REG; | |
7371 | break; | |
7372 | ||
7373 | case 'X': | |
7374 | case 'Y': | |
7375 | if (regno == AT && ! mips_noat) | |
7376 | as_warn ("used $at without \".set noat\""); | |
7377 | break; | |
7378 | ||
7379 | default: | |
7380 | internalError (); | |
7381 | } | |
7382 | ||
7383 | if (regno == ILLEGAL_REG) | |
7384 | break; | |
7385 | ||
7386 | switch (c) | |
7387 | { | |
7388 | case 'x': | |
7389 | case 'v': | |
7390 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7391 | break; | |
7392 | case 'y': | |
7393 | case 'w': | |
7394 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7395 | break; | |
7396 | case 'z': | |
7397 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7398 | break; | |
7399 | case 'Z': | |
7400 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7401 | case '0': | |
7402 | case 'S': | |
7403 | case 'R': | |
7404 | break; | |
7405 | case 'X': | |
7406 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7407 | break; | |
7408 | case 'Y': | |
7409 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7410 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7411 | break; | |
7412 | default: | |
7413 | internalError (); | |
7414 | } | |
7415 | ||
7416 | lastregno = regno; | |
7417 | continue; | |
7418 | ||
7419 | case 'P': | |
7420 | if (strncmp (s, "$pc", 3) == 0) | |
7421 | { | |
7422 | s += 3; | |
7423 | continue; | |
7424 | } | |
7425 | break; | |
7426 | ||
7427 | case '<': | |
7428 | case '>': | |
7429 | case '[': | |
7430 | case ']': | |
7431 | case '4': | |
7432 | case '5': | |
7433 | case 'H': | |
7434 | case 'W': | |
7435 | case 'D': | |
7436 | case 'j': | |
7437 | case '8': | |
7438 | case 'V': | |
7439 | case 'C': | |
7440 | case 'U': | |
7441 | case 'k': | |
7442 | case 'K': | |
16262668 ILT |
7443 | if (s[0] == '%' |
7444 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7445 | { | |
7446 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7447 | and generate the appropriate reloc. If the text | |
7448 | inside %gprel is not a symbol name with an | |
7449 | optional offset, then we generate a normal reloc | |
7450 | and will probably fail later. */ | |
7451 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7452 | if (imm_expr.X_op == O_symbol) | |
7453 | { | |
7454 | mips16_ext = true; | |
7455 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7456 | s = expr_end; | |
7457 | ip->use_extend = true; | |
7458 | ip->extend = 0; | |
7459 | continue; | |
7460 | } | |
7461 | } | |
7462 | else | |
7463 | { | |
7464 | /* Just pick up a normal expression. */ | |
7465 | my_getExpression (&imm_expr, s); | |
7466 | } | |
7467 | ||
ebf28372 ILT |
7468 | if (imm_expr.X_op == O_register) |
7469 | { | |
7470 | /* What we thought was an expression turned out to | |
7471 | be a register. */ | |
7472 | ||
7473 | if (s[0] == '(' && args[1] == '(') | |
7474 | { | |
7475 | /* It looks like the expression was omitted | |
7476 | before a register indirection, which means | |
7477 | that the expression is implicitly zero. We | |
7478 | still set up imm_expr, so that we handle | |
7479 | explicit extensions correctly. */ | |
7480 | imm_expr.X_op = O_constant; | |
7481 | imm_expr.X_add_number = 0; | |
7482 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7483 | continue; | |
7484 | } | |
7485 | ||
7486 | break; | |
7487 | } | |
7488 | ||
cc5703cd ILT |
7489 | /* We need to relax this instruction. */ |
7490 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7491 | s = expr_end; | |
7492 | continue; | |
7493 | ||
7494 | case 'p': | |
7495 | case 'q': | |
7496 | case 'A': | |
7497 | case 'B': | |
7498 | case 'E': | |
7499 | /* We use offset_reloc rather than imm_reloc for the PC | |
7500 | relative operands. This lets macros with both | |
7501 | immediate and address operands work correctly. */ | |
670a50eb | 7502 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7503 | |
7504 | if (offset_expr.X_op == O_register) | |
7505 | break; | |
7506 | ||
cc5703cd ILT |
7507 | /* We need to relax this instruction. */ |
7508 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7509 | s = expr_end; |
7510 | continue; | |
7511 | ||
cc5703cd ILT |
7512 | case '6': /* break code */ |
7513 | my_getExpression (&imm_expr, s); | |
7514 | check_absolute_expr (ip, &imm_expr); | |
7515 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7516 | { |
cc5703cd ILT |
7517 | as_warn ("Invalid value for `%s' (%lu)", |
7518 | ip->insn_mo->name, | |
7519 | (unsigned long) imm_expr.X_add_number); | |
7520 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7521 | } |
cc5703cd ILT |
7522 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7523 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7524 | s = expr_end; |
7525 | continue; | |
3d3c5039 | 7526 | |
670a50eb ILT |
7527 | case 'a': /* 26 bit address */ |
7528 | my_getExpression (&offset_expr, s); | |
7529 | s = expr_end; | |
cc5703cd ILT |
7530 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7531 | ip->insn_opcode <<= 16; | |
670a50eb | 7532 | continue; |
3d3c5039 | 7533 | |
cc5703cd ILT |
7534 | case 'l': /* register list for entry macro */ |
7535 | case 'L': /* register list for exit macro */ | |
7536 | { | |
7537 | int mask; | |
7538 | ||
7539 | if (c == 'l') | |
7540 | mask = 0; | |
7541 | else | |
7542 | mask = 7 << 3; | |
7543 | while (*s != '\0') | |
7544 | { | |
c9167640 | 7545 | int freg, reg1, reg2; |
cc5703cd ILT |
7546 | |
7547 | while (*s == ' ' || *s == ',') | |
7548 | ++s; | |
7549 | if (*s != '$') | |
7550 | { | |
7551 | as_bad ("can't parse register list"); | |
7552 | break; | |
7553 | } | |
7554 | ++s; | |
c9167640 ILT |
7555 | if (*s != 'f') |
7556 | freg = 0; | |
7557 | else | |
7558 | { | |
7559 | freg = 1; | |
7560 | ++s; | |
7561 | } | |
cc5703cd ILT |
7562 | reg1 = 0; |
7563 | while (isdigit (*s)) | |
7564 | { | |
7565 | reg1 *= 10; | |
7566 | reg1 += *s - '0'; | |
7567 | ++s; | |
7568 | } | |
7569 | if (*s == ' ') | |
7570 | ++s; | |
7571 | if (*s != '-') | |
7572 | reg2 = reg1; | |
7573 | else | |
7574 | { | |
7575 | ++s; | |
7576 | if (*s != '$') | |
7577 | break; | |
7578 | ++s; | |
c9167640 ILT |
7579 | if (freg) |
7580 | { | |
7581 | if (*s == 'f') | |
7582 | ++s; | |
7583 | else | |
7584 | { | |
7585 | as_bad ("invalid register list"); | |
7586 | break; | |
7587 | } | |
7588 | } | |
cc5703cd ILT |
7589 | reg2 = 0; |
7590 | while (isdigit (*s)) | |
7591 | { | |
7592 | reg2 *= 10; | |
7593 | reg2 += *s - '0'; | |
7594 | ++s; | |
7595 | } | |
7596 | } | |
c9167640 ILT |
7597 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7598 | { | |
7599 | mask &= ~ (7 << 3); | |
7600 | mask |= 5 << 3; | |
7601 | } | |
7602 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7603 | { | |
7604 | mask &= ~ (7 << 3); | |
7605 | mask |= 6 << 3; | |
7606 | } | |
7607 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7608 | mask |= (reg2 - 3) << 3; |
7609 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7610 | mask |= (reg2 - 15) << 1; | |
7611 | else if (reg1 == 31 && reg2 == 31) | |
7612 | mask |= 1; | |
7613 | else | |
c9167640 ILT |
7614 | { |
7615 | as_bad ("invalid register list"); | |
7616 | break; | |
7617 | } | |
cc5703cd | 7618 | } |
c9167640 ILT |
7619 | /* The mask is filled in in the opcode table for the |
7620 | benefit of the disassembler. We remove it before | |
7621 | applying the actual mask. */ | |
7622 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7623 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7624 | } | |
7625 | continue; | |
d8a1c247 | 7626 | |
56bb6eee ILT |
7627 | case 'e': /* extend code */ |
7628 | my_getExpression (&imm_expr, s); | |
7629 | check_absolute_expr (ip, &imm_expr); | |
7630 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
7631 | { | |
7632 | as_warn ("Invalid value for `%s' (%lu)", | |
7633 | ip->insn_mo->name, | |
7634 | (unsigned long) imm_expr.X_add_number); | |
7635 | imm_expr.X_add_number &= 0x7ff; | |
7636 | } | |
7637 | ip->insn_opcode |= imm_expr.X_add_number; | |
7638 | imm_expr.X_op = O_absent; | |
7639 | s = expr_end; | |
7640 | continue; | |
7641 | ||
3d3c5039 | 7642 | default: |
670a50eb | 7643 | internalError (); |
3d3c5039 | 7644 | } |
670a50eb | 7645 | break; |
3d3c5039 | 7646 | } |
cc5703cd | 7647 | |
670a50eb | 7648 | /* Args don't match. */ |
cc5703cd ILT |
7649 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7650 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7651 | { |
7652 | ++insn; | |
cc5703cd | 7653 | s = argsstart; |
670a50eb | 7654 | continue; |
3d3c5039 | 7655 | } |
cc5703cd | 7656 | |
9753202d | 7657 | insn_error = "illegal operands"; |
cc5703cd | 7658 | |
670a50eb | 7659 | return; |
3d3c5039 ILT |
7660 | } |
7661 | } | |
7662 | ||
cc5703cd ILT |
7663 | /* This structure holds information we know about a mips16 immediate |
7664 | argument type. */ | |
7665 | ||
7666 | struct mips16_immed_operand | |
7667 | { | |
7668 | /* The type code used in the argument string in the opcode table. */ | |
7669 | int type; | |
7670 | /* The number of bits in the short form of the opcode. */ | |
7671 | int nbits; | |
7672 | /* The number of bits in the extended form of the opcode. */ | |
7673 | int extbits; | |
7674 | /* The amount by which the short form is shifted when it is used; | |
7675 | for example, the sw instruction has a shift count of 2. */ | |
7676 | int shift; | |
7677 | /* The amount by which the short form is shifted when it is stored | |
7678 | into the instruction code. */ | |
7679 | int op_shift; | |
7680 | /* Non-zero if the short form is unsigned. */ | |
7681 | int unsp; | |
7682 | /* Non-zero if the extended form is unsigned. */ | |
7683 | int extu; | |
7684 | /* Non-zero if the value is PC relative. */ | |
7685 | int pcrel; | |
7686 | }; | |
7687 | ||
7688 | /* The mips16 immediate operand types. */ | |
7689 | ||
7690 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7691 | { | |
7692 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7693 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7694 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7695 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7696 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7697 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7698 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7699 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7700 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7701 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7702 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7703 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7704 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7705 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7706 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7707 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7708 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7709 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7710 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7711 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7712 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7713 | }; | |
7714 | ||
7715 | #define MIPS16_NUM_IMMED \ | |
7716 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7717 | ||
7718 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7719 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7720 | whether an extended value is needed; if one is needed, it sets | |
7721 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7722 | If SMALL is true, an unextended opcode was explicitly requested. | |
7723 | If EXT is true, an extended opcode was explicitly requested. If | |
7724 | WARN is true, warn if EXT does not match reality. */ | |
7725 | ||
7726 | static void | |
15e69f98 ILT |
7727 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7728 | extend) | |
7729 | char *file; | |
7730 | unsigned int line; | |
cc5703cd ILT |
7731 | int type; |
7732 | offsetT val; | |
7733 | boolean warn; | |
7734 | boolean small; | |
7735 | boolean ext; | |
7736 | unsigned long *insn; | |
7737 | boolean *use_extend; | |
7738 | unsigned short *extend; | |
7739 | { | |
7740 | register const struct mips16_immed_operand *op; | |
7741 | int mintiny, maxtiny; | |
7742 | boolean needext; | |
7743 | ||
7744 | op = mips16_immed_operands; | |
7745 | while (op->type != type) | |
7746 | { | |
7747 | ++op; | |
7748 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7749 | } | |
7750 | ||
7751 | if (op->unsp) | |
7752 | { | |
7753 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7754 | { | |
7755 | mintiny = 1; | |
7756 | maxtiny = 1 << op->nbits; | |
7757 | } | |
7758 | else | |
7759 | { | |
7760 | mintiny = 0; | |
7761 | maxtiny = (1 << op->nbits) - 1; | |
7762 | } | |
7763 | } | |
7764 | else | |
7765 | { | |
7766 | mintiny = - (1 << (op->nbits - 1)); | |
7767 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7768 | } | |
7769 | ||
7770 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7771 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7772 | val /= 2; |
cc5703cd ILT |
7773 | |
7774 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7775 | || val < (mintiny << op->shift) | |
7776 | || val > (maxtiny << op->shift)) | |
7777 | needext = true; | |
7778 | else | |
7779 | needext = false; | |
7780 | ||
7781 | if (warn && ext && ! needext) | |
15e69f98 | 7782 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7783 | if (small && needext) |
15e69f98 | 7784 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7785 | |
7786 | if (small || (! ext && ! needext)) | |
7787 | { | |
7788 | int insnval; | |
7789 | ||
7790 | *use_extend = false; | |
7791 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7792 | insnval <<= op->op_shift; | |
7793 | *insn |= insnval; | |
7794 | } | |
7795 | else | |
7796 | { | |
7797 | long minext, maxext; | |
7798 | int extval; | |
7799 | ||
7800 | if (op->extu) | |
7801 | { | |
7802 | minext = 0; | |
7803 | maxext = (1 << op->extbits) - 1; | |
7804 | } | |
7805 | else | |
7806 | { | |
7807 | minext = - (1 << (op->extbits - 1)); | |
7808 | maxext = (1 << (op->extbits - 1)) - 1; | |
7809 | } | |
7810 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7811 | as_bad_where (file, line, |
7812 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7813 | |
7814 | *use_extend = true; | |
7815 | if (op->extbits == 16) | |
7816 | { | |
7817 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7818 | val &= 0x1f; | |
7819 | } | |
7820 | else if (op->extbits == 15) | |
7821 | { | |
7822 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7823 | val &= 0xf; | |
7824 | } | |
7825 | else | |
7826 | { | |
7827 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7828 | val = 0; | |
7829 | } | |
7830 | ||
7831 | *extend = (unsigned short) extval; | |
7832 | *insn |= val; | |
7833 | } | |
7834 | } | |
7835 | \f | |
3d3c5039 ILT |
7836 | #define LP '(' |
7837 | #define RP ')' | |
7838 | ||
7839 | static int | |
7840 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7841 | expressionS *ep; |
7842 | char *str; | |
3d3c5039 | 7843 | { |
670a50eb ILT |
7844 | char *sp; |
7845 | int c = 0; | |
7846 | ||
7847 | if (*str == ' ') | |
7848 | str++; | |
7849 | if (*str == LP | |
7850 | || (*str == '%' && | |
7851 | ((str[1] == 'h' && str[2] == 'i') | |
7852 | || (str[1] == 'H' && str[2] == 'I') | |
7853 | || (str[1] == 'l' && str[2] == 'o')) | |
7854 | && str[3] == LP)) | |
7855 | { | |
7856 | if (*str == LP) | |
7857 | c = 0; | |
7858 | else | |
7859 | { | |
7860 | c = str[1]; | |
7861 | str += 3; | |
7862 | } | |
7863 | ||
7864 | /* | |
7865 | * A small expression may be followed by a base register. | |
7866 | * Scan to the end of this operand, and then back over a possible | |
7867 | * base register. Then scan the small expression up to that | |
7868 | * point. (Based on code in sparc.c...) | |
7869 | */ | |
7870 | for (sp = str; *sp && *sp != ','; sp++) | |
7871 | ; | |
7872 | if (sp - 4 >= str && sp[-1] == RP) | |
7873 | { | |
7874 | if (isdigit (sp[-2])) | |
7875 | { | |
7876 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7877 | ; | |
7878 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7879 | { | |
7880 | sp--; | |
7881 | goto do_it; | |
3d3c5039 | 7882 | } |
670a50eb ILT |
7883 | } |
7884 | else if (sp - 5 >= str | |
7885 | && sp[-5] == LP | |
7886 | && sp[-4] == '$' | |
7887 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7888 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7889 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7890 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7891 | { | |
7892 | sp -= 5; | |
3d3c5039 | 7893 | do_it: |
670a50eb ILT |
7894 | if (sp == str) |
7895 | { | |
7896 | /* no expression means zero offset */ | |
7897 | if (c) | |
7898 | { | |
7899 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7900 | ep->X_op = O_absent; |
670a50eb | 7901 | expr_end = str - 3; |
3d3c5039 | 7902 | } |
670a50eb ILT |
7903 | else |
7904 | { | |
52aa70b5 | 7905 | ep->X_op = O_constant; |
670a50eb ILT |
7906 | expr_end = sp; |
7907 | } | |
7908 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7909 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7910 | ep->X_add_number = 0; |
7911 | } | |
7912 | else | |
7913 | { | |
7914 | *sp = '\0'; | |
7915 | my_getExpression (ep, str); | |
7916 | *sp = LP; | |
3d3c5039 | 7917 | } |
670a50eb | 7918 | return c; |
3d3c5039 ILT |
7919 | } |
7920 | } | |
7921 | } | |
670a50eb ILT |
7922 | my_getExpression (ep, str); |
7923 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7924 | } |
7925 | ||
7926 | static void | |
7927 | my_getExpression (ep, str) | |
670a50eb ILT |
7928 | expressionS *ep; |
7929 | char *str; | |
3d3c5039 | 7930 | { |
670a50eb | 7931 | char *save_in; |
670a50eb ILT |
7932 | |
7933 | save_in = input_line_pointer; | |
7934 | input_line_pointer = str; | |
5ac34ac3 | 7935 | expression (ep); |
670a50eb ILT |
7936 | expr_end = input_line_pointer; |
7937 | input_line_pointer = save_in; | |
eb17f56c ILT |
7938 | |
7939 | /* If we are in mips16 mode, and this is an expression based on `.', | |
7940 | then we bump the value of the symbol by 1 since that is how other | |
7941 | text symbols are handled. We don't bother to handle complex | |
7942 | expressions, just `.' plus or minus a constant. */ | |
7943 | if (mips16 | |
7944 | && ep->X_op == O_symbol | |
7945 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
7946 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
7947 | && ep->X_add_symbol->sy_frag == frag_now | |
7948 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
7949 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
7950 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
7951 | } |
7952 | ||
becfe05e ILT |
7953 | /* Turn a string in input_line_pointer into a floating point constant |
7954 | of type type, and store the appropriate bytes in *litP. The number | |
7955 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7956 | returned, or NULL on OK. */ | |
7957 | ||
3d3c5039 | 7958 | char * |
670a50eb | 7959 | md_atof (type, litP, sizeP) |
becfe05e | 7960 | int type; |
3d3c5039 ILT |
7961 | char *litP; |
7962 | int *sizeP; | |
7963 | { | |
becfe05e ILT |
7964 | int prec; |
7965 | LITTLENUM_TYPE words[4]; | |
7966 | char *t; | |
7967 | int i; | |
7968 | ||
7969 | switch (type) | |
7970 | { | |
7971 | case 'f': | |
7972 | prec = 2; | |
7973 | break; | |
7974 | ||
7975 | case 'd': | |
7976 | prec = 4; | |
7977 | break; | |
7978 | ||
7979 | default: | |
7980 | *sizeP = 0; | |
7981 | return "bad call to md_atof"; | |
7982 | } | |
7983 | ||
7984 | t = atof_ieee (input_line_pointer, type, words); | |
7985 | if (t) | |
7986 | input_line_pointer = t; | |
7987 | ||
7988 | *sizeP = prec * 2; | |
7989 | ||
b9129c6f | 7990 | if (! target_big_endian) |
becfe05e ILT |
7991 | { |
7992 | for (i = prec - 1; i >= 0; i--) | |
7993 | { | |
7994 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7995 | litP += 2; | |
7996 | } | |
7997 | } | |
7998 | else | |
7999 | { | |
8000 | for (i = 0; i < prec; i++) | |
8001 | { | |
8002 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8003 | litP += 2; | |
8004 | } | |
8005 | } | |
8006 | ||
670a50eb | 8007 | return NULL; |
3d3c5039 ILT |
8008 | } |
8009 | ||
8010 | void | |
8011 | md_number_to_chars (buf, val, n) | |
8012 | char *buf; | |
918692a5 | 8013 | valueT val; |
3d3c5039 ILT |
8014 | int n; |
8015 | { | |
b9129c6f ILT |
8016 | if (target_big_endian) |
8017 | number_to_chars_bigendian (buf, val, n); | |
8018 | else | |
8019 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8020 | } |
f3d817d8 | 8021 | \f |
e8d4d475 | 8022 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8023 | |
f3d817d8 DM |
8024 | struct option md_longopts[] = { |
8025 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8026 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8027 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8028 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8029 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8030 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8031 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8032 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8033 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8034 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8035 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8036 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8037 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8038 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8039 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8040 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8041 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8042 | {"break", no_argument, NULL, OPTION_BREAK}, |
8043 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8044 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8045 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8046 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8047 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8048 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8049 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8050 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8051 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8052 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8053 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8054 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8055 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8056 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8057 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8058 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8059 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8060 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8061 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8062 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8063 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
276c2d7d GRK |
8064 | /* start-sanitize-5900 */ |
8065 | #define OPTION_M5900 (OPTION_MD_BASE + 24) | |
8066 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8067 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8068 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
8069 | /* end-sanitize-5900 */ | |
f3d817d8 | 8070 | |
d8a1c247 | 8071 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8072 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8073 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8074 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8075 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8076 | #ifdef OBJ_ELF |
f3d817d8 | 8077 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8078 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8079 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8080 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8081 | {"32", no_argument, NULL, OPTION_32}, |
8082 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8083 | #endif |
8084 | ||
8085 | {NULL, no_argument, NULL, 0} | |
8086 | }; | |
8087 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8088 | |
8089 | int | |
f3d817d8 DM |
8090 | md_parse_option (c, arg) |
8091 | int c; | |
8092 | char *arg; | |
3d3c5039 | 8093 | { |
f3d817d8 | 8094 | switch (c) |
670a50eb | 8095 | { |
f3d817d8 DM |
8096 | case OPTION_TRAP: |
8097 | mips_trap = 1; | |
8098 | break; | |
670a50eb | 8099 | |
f3d817d8 DM |
8100 | case OPTION_BREAK: |
8101 | mips_trap = 0; | |
8102 | break; | |
8103 | ||
e8d4d475 | 8104 | case OPTION_EB: |
1dc1e798 | 8105 | target_big_endian = 1; |
e8d4d475 | 8106 | break; |
04cb3372 | 8107 | |
e8d4d475 | 8108 | case OPTION_EL: |
1dc1e798 | 8109 | target_big_endian = 0; |
f3d817d8 | 8110 | break; |
670a50eb | 8111 | |
f3d817d8 DM |
8112 | case 'O': |
8113 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8114 | mips_optimize = 1; |
8115 | else | |
8116 | mips_optimize = 2; | |
f3d817d8 | 8117 | break; |
0aa07269 | 8118 | |
f3d817d8 | 8119 | case 'g': |
22ba90ce ILT |
8120 | if (arg == NULL) |
8121 | mips_debug = 2; | |
8122 | else | |
8123 | mips_debug = atoi (arg); | |
8124 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8125 | optimizations which limit full symbolic debugging. We take | |
8126 | that to be equivalent to -O0. */ | |
8127 | if (mips_debug == 2) | |
05874c2e | 8128 | mips_optimize = 1; |
f3d817d8 | 8129 | break; |
4e95866e | 8130 | |
f3d817d8 DM |
8131 | case OPTION_MIPS1: |
8132 | mips_isa = 1; | |
4bb0cc41 ILT |
8133 | if (mips_cpu == -1) |
8134 | mips_cpu = 3000; | |
f3d817d8 | 8135 | break; |
8358c818 | 8136 | |
f3d817d8 DM |
8137 | case OPTION_MIPS2: |
8138 | mips_isa = 2; | |
4bb0cc41 ILT |
8139 | if (mips_cpu == -1) |
8140 | mips_cpu = 6000; | |
f3d817d8 | 8141 | break; |
8358c818 | 8142 | |
f3d817d8 DM |
8143 | case OPTION_MIPS3: |
8144 | mips_isa = 3; | |
4bb0cc41 ILT |
8145 | if (mips_cpu == -1) |
8146 | mips_cpu = 4000; | |
f3d817d8 | 8147 | break; |
8358c818 | 8148 | |
d8a1c247 KR |
8149 | case OPTION_MIPS4: |
8150 | mips_isa = 4; | |
8151 | if (mips_cpu == -1) | |
8152 | mips_cpu = 8000; | |
8153 | break; | |
8154 | ||
f3d817d8 DM |
8155 | case OPTION_MCPU: |
8156 | { | |
8157 | char *p; | |
8158 | ||
8159 | /* Identify the processor type */ | |
8160 | p = arg; | |
8161 | if (strcmp (p, "default") == 0 | |
8162 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8163 | mips_cpu = -1; |
f3d817d8 DM |
8164 | else |
8165 | { | |
c625fc23 JSC |
8166 | int sv = 0; |
8167 | ||
8168 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8169 | processor. */ | |
8170 | if (*p == 'v' || *p == 'V') | |
8171 | { | |
8172 | sv = 1; | |
8173 | p++; | |
8174 | } | |
8175 | ||
f3d817d8 DM |
8176 | if (*p == 'r' || *p == 'R') |
8177 | p++; | |
8358c818 | 8178 | |
4bb0cc41 | 8179 | mips_cpu = -1; |
f3d817d8 DM |
8180 | switch (*p) |
8181 | { | |
d8a1c247 KR |
8182 | case '1': |
8183 | if (strcmp (p, "10000") == 0 | |
8184 | || strcmp (p, "10k") == 0 | |
8185 | || strcmp (p, "10K") == 0) | |
8186 | mips_cpu = 10000; | |
8187 | break; | |
8188 | ||
f3d817d8 DM |
8189 | case '2': |
8190 | if (strcmp (p, "2000") == 0 | |
8191 | || strcmp (p, "2k") == 0 | |
8192 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8193 | mips_cpu = 2000; |
f3d817d8 | 8194 | break; |
8358c818 | 8195 | |
f3d817d8 DM |
8196 | case '3': |
8197 | if (strcmp (p, "3000") == 0 | |
8198 | || strcmp (p, "3k") == 0 | |
8199 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8200 | mips_cpu = 3000; |
f3d817d8 | 8201 | break; |
8358c818 | 8202 | |
f3d817d8 DM |
8203 | case '4': |
8204 | if (strcmp (p, "4000") == 0 | |
8205 | || strcmp (p, "4k") == 0 | |
8c63448a | 8206 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8207 | mips_cpu = 4000; |
c625fc23 JSC |
8208 | else if (strcmp (p, "4100") == 0) |
8209 | { | |
8210 | mips_cpu = 4100; | |
8211 | if (mips_4100 < 0) | |
8212 | mips_4100 = 1; | |
8213 | } | |
8214 | else if (strcmp (p, "4300") == 0) | |
8215 | mips_cpu = 4300; | |
8c63448a | 8216 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8217 | mips_cpu = 4400; |
8c63448a | 8218 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8219 | mips_cpu = 4600; |
b2b8c24e ILT |
8220 | else if (strcmp (p, "4650") == 0) |
8221 | { | |
8222 | mips_cpu = 4650; | |
8223 | if (mips_4650 < 0) | |
8224 | mips_4650 = 1; | |
8225 | } | |
e532b44c ILT |
8226 | else if (strcmp (p, "4010") == 0) |
8227 | { | |
8228 | mips_cpu = 4010; | |
8229 | if (mips_4010 < 0) | |
8230 | mips_4010 = 1; | |
8231 | } | |
f3d817d8 | 8232 | break; |
8358c818 | 8233 | |
517078c1 ILT |
8234 | case '5': |
8235 | if (strcmp (p, "5000") == 0 | |
8236 | || strcmp (p, "5k") == 0 | |
8237 | || strcmp (p, "5K") == 0) | |
8238 | mips_cpu = 5000; | |
276c2d7d GRK |
8239 | /* start-sanitize-r5900 */ |
8240 | else if (strcmp (p, "5900") == 0) | |
8241 | mips_cpu = 5900; | |
8242 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8243 | break; |
8244 | ||
f3d817d8 DM |
8245 | case '6': |
8246 | if (strcmp (p, "6000") == 0 | |
8247 | || strcmp (p, "6k") == 0 | |
8248 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8249 | mips_cpu = 6000; |
f3d817d8 | 8250 | break; |
55933a58 | 8251 | |
d8a1c247 KR |
8252 | case '8': |
8253 | if (strcmp (p, "8000") == 0 | |
8254 | || strcmp (p, "8k") == 0 | |
8255 | || strcmp (p, "8K") == 0) | |
8256 | mips_cpu = 8000; | |
8257 | break; | |
8258 | ||
55933a58 ILT |
8259 | case 'o': |
8260 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8261 | mips_cpu = 4600; |
55933a58 | 8262 | break; |
f3d817d8 | 8263 | } |
8358c818 | 8264 | |
517078c1 | 8265 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8266 | { |
8267 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8268 | return 0; | |
8269 | } | |
8270 | ||
4bb0cc41 | 8271 | if (mips_cpu == -1) |
f3d817d8 DM |
8272 | { |
8273 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8274 | return 0; | |
8275 | } | |
8276 | } | |
8277 | } | |
8278 | break; | |
8358c818 | 8279 | |
b2b8c24e ILT |
8280 | case OPTION_M4650: |
8281 | mips_4650 = 1; | |
8282 | break; | |
8283 | ||
8284 | case OPTION_NO_M4650: | |
8285 | mips_4650 = 0; | |
8286 | break; | |
8287 | ||
e532b44c ILT |
8288 | case OPTION_M4010: |
8289 | mips_4010 = 1; | |
8290 | break; | |
8291 | ||
8292 | case OPTION_NO_M4010: | |
8293 | mips_4010 = 0; | |
8294 | break; | |
8295 | ||
c625fc23 JSC |
8296 | case OPTION_M4100: |
8297 | mips_4100 = 1; | |
8298 | break; | |
8299 | ||
8300 | case OPTION_NO_M4100: | |
8301 | mips_4100 = 0; | |
8302 | break; | |
8303 | ||
276c2d7d GRK |
8304 | /* start-sanitize-r5900 */ |
8305 | case OPTION_M5900: | |
8306 | mips_5900 = 1; | |
8307 | break; | |
8308 | ||
8309 | case OPTION_NO_M5900: | |
8310 | mips_5900 = 0; | |
8311 | break; | |
8312 | /* end-sanitize-r5900 */ | |
8313 | ||
cc5703cd ILT |
8314 | case OPTION_MIPS16: |
8315 | mips16 = 1; | |
4a1cb507 | 8316 | mips_no_prev_insn (false); |
cc5703cd ILT |
8317 | break; |
8318 | ||
8319 | case OPTION_NO_MIPS16: | |
8320 | mips16 = 0; | |
4a1cb507 | 8321 | mips_no_prev_insn (false); |
cc5703cd ILT |
8322 | break; |
8323 | ||
f3d817d8 | 8324 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8325 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8326 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8327 | { |
8328 | as_bad ("-G may not be used with embedded PIC code"); | |
8329 | return 0; | |
8330 | } | |
5b63f465 | 8331 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8332 | break; |
d9aba805 | 8333 | |
fb251650 ILT |
8334 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8335 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8336 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8337 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8338 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8339 | { | |
8340 | as_bad ("-call_shared is supported only for ELF format"); | |
8341 | return 0; | |
8342 | } | |
d9aba805 ILT |
8343 | mips_pic = SVR4_PIC; |
8344 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8345 | { |
8346 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8347 | return 0; | |
8348 | } | |
d9aba805 | 8349 | g_switch_value = 0; |
f3d817d8 DM |
8350 | break; |
8351 | ||
8352 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8353 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8354 | { | |
8355 | as_bad ("-non_shared is supported only for ELF format"); | |
8356 | return 0; | |
8357 | } | |
d9aba805 | 8358 | mips_pic = NO_PIC; |
f3d817d8 | 8359 | break; |
8358c818 | 8360 | |
fb251650 ILT |
8361 | /* The -xgot option tells the assembler to use 32 offsets when |
8362 | accessing the got in SVR4_PIC mode. It is for Irix | |
8363 | compatibility. */ | |
8364 | case OPTION_XGOT: | |
8365 | mips_big_got = 1; | |
8366 | break; | |
8367 | ||
f3d817d8 | 8368 | case 'G': |
1dc1e798 KR |
8369 | if (! USE_GLOBAL_POINTER_OPT) |
8370 | { | |
8371 | as_bad ("-G is not supported for this configuration"); | |
8372 | return 0; | |
8373 | } | |
8374 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8375 | { |
f3d817d8 DM |
8376 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8377 | return 0; | |
670a50eb ILT |
8378 | } |
8379 | else | |
f3d817d8 | 8380 | g_switch_value = atoi (arg); |
42562568 | 8381 | g_switch_seen = 1; |
f3d817d8 | 8382 | break; |
4e95866e | 8383 | |
7f9880e5 ILT |
8384 | /* The -32 and -64 options tell the assembler to output the 32 |
8385 | bit or the 64 bit MIPS ELF format. */ | |
8386 | case OPTION_32: | |
8387 | mips_64 = 0; | |
8388 | break; | |
8389 | ||
8390 | case OPTION_64: | |
9c44af60 ILT |
8391 | { |
8392 | const char **list, **l; | |
8393 | ||
8394 | list = bfd_target_list (); | |
8395 | for (l = list; *l != NULL; l++) | |
8396 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8397 | || strcmp (*l, "elf64-littlemips") == 0) | |
8398 | break; | |
8399 | if (*l == NULL) | |
8400 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8401 | free (list); | |
8402 | mips_64 = 1; | |
8403 | } | |
7f9880e5 ILT |
8404 | break; |
8405 | ||
f3d817d8 DM |
8406 | default: |
8407 | return 0; | |
8ea7f4e8 ILT |
8408 | } |
8409 | ||
f3d817d8 | 8410 | return 1; |
8ea7f4e8 ILT |
8411 | } |
8412 | ||
f3d817d8 DM |
8413 | void |
8414 | md_show_usage (stream) | |
8415 | FILE *stream; | |
8416 | { | |
8417 | fprintf(stream, "\ | |
8418 | MIPS options:\n\ | |
8419 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8420 | -EB generate big endian output\n\ |
8421 | -EL generate little endian output\n\ | |
8422 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8423 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8424 | implicitly with the gp register [default 8]\n"); |
8425 | fprintf(stream, "\ | |
f3d817d8 DM |
8426 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8427 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8428 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8429 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8430 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8431 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8432 | -m4650 permit R4650 instructions\n\ |
8433 | -no-m4650 do not permit R4650 instructions\n\ | |
8434 | -m4010 permit R4010 instructions\n\ | |
8435 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8436 | -m4100 permit VR4100 instructions\n\ |
8437 | -no-m4100 do not permit VR4100 instructions\n"); | |
8438 | fprintf(stream, "\ | |
cc5703cd ILT |
8439 | -mips16 generate mips16 instructions\n\ |
8440 | -no-mips16 do not generate mips16 instructions\n"); | |
8441 | fprintf(stream, "\ | |
f3d817d8 DM |
8442 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8443 | -O remove unneeded NOPs and swap branches\n\ | |
8444 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8445 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8446 | #ifdef OBJ_ELF | |
8447 | fprintf(stream, "\ | |
8448 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8449 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8450 | -xgot assume a 32 bit GOT\n\ |
8451 | -32 create 32 bit object file (default)\n\ | |
8452 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8453 | #endif |
8454 | } | |
8455 | \f | |
efec4a28 DP |
8456 | |
8457 | void | |
8458 | mips_init_after_args () | |
8459 | { | |
8460 | if (itbl_have_entries) | |
8461 | { | |
8462 | /* initialize opcodes */ | |
8463 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
8464 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
8465 | } | |
8466 | } | |
8467 | ||
8468 | ||
3d3c5039 ILT |
8469 | long |
8470 | md_pcrel_from (fixP) | |
8471 | fixS *fixP; | |
8472 | { | |
1dc1e798 KR |
8473 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8474 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8475 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8476 | { | |
8477 | /* This makes a branch to an undefined symbol be a branch to the | |
8478 | current location. */ | |
8479 | return 4; | |
8480 | } | |
5b63f465 | 8481 | |
670a50eb ILT |
8482 | /* return the address of the delay slot */ |
8483 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8484 | } |
8485 | ||
abdad6bc ILT |
8486 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8487 | reloc for a cons. We could use the definition there, except that | |
8488 | we want to handle 64 bit relocs specially. */ | |
8489 | ||
8490 | void | |
8491 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8492 | fragS *frag; | |
8493 | int where; | |
8494 | unsigned int nbytes; | |
8495 | expressionS *exp; | |
8496 | { | |
bf39474f | 8497 | #ifndef OBJ_ELF |
abdad6bc | 8498 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8499 | 4 byte reloc. */ |
8500 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8501 | { |
b9129c6f | 8502 | if (target_big_endian) |
abdad6bc ILT |
8503 | where += 4; |
8504 | nbytes = 4; | |
8505 | } | |
bf39474f | 8506 | #endif |
abdad6bc | 8507 | |
7f9880e5 | 8508 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8509 | as_bad ("Unsupported reloc size %d", nbytes); |
8510 | ||
8511 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8512 | (nbytes == 2 |
8513 | ? BFD_RELOC_16 | |
8514 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8515 | } |
8516 | ||
867a58b3 ILT |
8517 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8518 | the corresponding LO reloc. This is called before md_apply_fix and | |
8519 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8520 | explicit use of the %hi modifier. */ | |
8521 | ||
8522 | void | |
8523 | mips_frob_file () | |
8524 | { | |
8525 | struct mips_hi_fixup *l; | |
8526 | ||
8527 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8528 | { | |
8529 | segment_info_type *seginfo; | |
9b61d62b | 8530 | int pass; |
867a58b3 ILT |
8531 | |
8532 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8533 | ||
8534 | /* Check quickly whether the next fixup happens to be a matching | |
8535 | %lo. */ | |
8536 | if (l->fixp->fx_next != NULL | |
8537 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8538 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8539 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8540 | continue; | |
8541 | ||
8542 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8543 | When we find one, move the %hi just in front of it. We do |
8544 | this in two passes. In the first pass, we try to find a | |
8545 | unique %lo. In the second pass, we permit multiple %hi | |
8546 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8547 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8548 | for (pass = 0; pass < 2; pass++) |
8549 | { | |
8550 | fixS *f, *prev; | |
8551 | ||
8552 | prev = NULL; | |
8553 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8554 | { |
9b61d62b ILT |
8555 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8556 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8557 | && f->fx_addsy == l->fixp->fx_addsy | |
8558 | && f->fx_offset == l->fixp->fx_offset | |
8559 | && (pass == 1 | |
8560 | || prev == NULL | |
8561 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8562 | || prev->fx_addsy != f->fx_addsy | |
8563 | || prev->fx_offset != f->fx_offset)) | |
8564 | { | |
8565 | fixS **pf; | |
867a58b3 | 8566 | |
9b61d62b ILT |
8567 | /* Move l->fixp before f. */ |
8568 | for (pf = &seginfo->fix_root; | |
8569 | *pf != l->fixp; | |
8570 | pf = &(*pf)->fx_next) | |
8571 | assert (*pf != NULL); | |
867a58b3 | 8572 | |
9b61d62b | 8573 | *pf = l->fixp->fx_next; |
867a58b3 | 8574 | |
9b61d62b ILT |
8575 | l->fixp->fx_next = f; |
8576 | if (prev == NULL) | |
8577 | seginfo->fix_root = l->fixp; | |
8578 | else | |
8579 | prev->fx_next = l->fixp; | |
867a58b3 | 8580 | |
9b61d62b ILT |
8581 | break; |
8582 | } | |
8583 | ||
8584 | prev = f; | |
867a58b3 ILT |
8585 | } |
8586 | ||
9b61d62b ILT |
8587 | if (f != NULL) |
8588 | break; | |
867a58b3 | 8589 | |
9b61d62b ILT |
8590 | if (pass == 1) |
8591 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8592 | "Unmatched %%hi reloc"); | |
8593 | } | |
867a58b3 ILT |
8594 | } |
8595 | } | |
8596 | ||
1c803e52 ILT |
8597 | /* When generating embedded PIC code we need to use a special |
8598 | relocation to represent the difference of two symbols in the .text | |
8599 | section (switch tables use a difference of this sort). See | |
8600 | include/coff/mips.h for details. This macro checks whether this | |
8601 | fixup requires the special reloc. */ | |
8602 | #define SWITCH_TABLE(fixp) \ | |
8603 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8604 | && (fixp)->fx_addsy != NULL \ | |
8605 | && (fixp)->fx_subsy != NULL \ | |
8606 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8607 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8608 | ||
5b63f465 | 8609 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8610 | relocations, in case the linker has to relax a call. We also need |
8611 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8612 | |
8613 | /*ARGSUSED*/ | |
8614 | int | |
8615 | mips_force_relocation (fixp) | |
8616 | fixS *fixp; | |
8617 | { | |
1c803e52 | 8618 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8619 | && (fixp->fx_pcrel |
8620 | || SWITCH_TABLE (fixp) | |
8621 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8622 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8623 | } |
8624 | ||
8625 | /* Apply a fixup to the object file. */ | |
8626 | ||
3d3c5039 ILT |
8627 | int |
8628 | md_apply_fix (fixP, valueP) | |
8629 | fixS *fixP; | |
918692a5 | 8630 | valueT *valueP; |
3d3c5039 | 8631 | { |
670a50eb ILT |
8632 | unsigned char *buf; |
8633 | long insn, value; | |
3d3c5039 | 8634 | |
bf39474f ILT |
8635 | assert (fixP->fx_size == 4 |
8636 | || fixP->fx_r_type == BFD_RELOC_16 | |
8637 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8638 | |
670a50eb | 8639 | value = *valueP; |
1748b9d8 ILT |
8640 | |
8641 | /* If we aren't adjusting this fixup to be against the section | |
8642 | symbol, we need to adjust the value. */ | |
8643 | #ifdef S_GET_OTHER | |
8644 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8645 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8646 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8647 | { | |
8648 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8649 | if (value != 0 && ! fixP->fx_pcrel) | |
8650 | { | |
8651 | /* In this case, the bfd_install_relocation routine will | |
8652 | incorrectly add the symbol value back in. We just want | |
8653 | the addend to appear in the object file. */ | |
8654 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8655 | } | |
8656 | } | |
8657 | #endif | |
8658 | ||
670a50eb | 8659 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8660 | |
5b63f465 ILT |
8661 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8662 | fixP->fx_done = 1; | |
8663 | ||
670a50eb ILT |
8664 | switch (fixP->fx_r_type) |
8665 | { | |
3d3c5039 ILT |
8666 | case BFD_RELOC_MIPS_JMP: |
8667 | case BFD_RELOC_HI16: | |
8668 | case BFD_RELOC_HI16_S: | |
670a50eb | 8669 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8670 | case BFD_RELOC_MIPS_LITERAL: |
8671 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8672 | case BFD_RELOC_MIPS_GOT16: |
8673 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8674 | case BFD_RELOC_MIPS_GOT_HI16: |
8675 | case BFD_RELOC_MIPS_GOT_LO16: | |
8676 | case BFD_RELOC_MIPS_CALL_HI16: | |
8677 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8678 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8679 | if (fixP->fx_pcrel) |
7b777690 ILT |
8680 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8681 | "Invalid PC relative reloc"); | |
670a50eb | 8682 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8683 | break; |
3d3c5039 | 8684 | |
cc5703cd ILT |
8685 | case BFD_RELOC_MIPS16_JMP: |
8686 | /* We currently always generate a reloc against a symbol, which | |
8687 | means that we don't want an addend even if the symbol is | |
8688 | defined. */ | |
8689 | fixP->fx_addnumber = 0; | |
8690 | break; | |
8691 | ||
ecd4ca1c ILT |
8692 | case BFD_RELOC_PCREL_HI16_S: |
8693 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8694 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8695 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8696 | { | |
8697 | /* For an external symbol adjust by the address to make it | |
8698 | pcrel_offset. We use the address of the RELLO reloc | |
8699 | which follows this one. */ | |
8700 | value += (fixP->fx_next->fx_frag->fr_address | |
8701 | + fixP->fx_next->fx_where); | |
8702 | } | |
8703 | if (value & 0x8000) | |
8704 | value += 0x10000; | |
8705 | value >>= 16; | |
0221ddf7 | 8706 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8707 | if (target_big_endian) |
ecd4ca1c ILT |
8708 | buf += 2; |
8709 | md_number_to_chars (buf, value, 2); | |
8710 | break; | |
8711 | ||
8712 | case BFD_RELOC_PCREL_LO16: | |
8713 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8714 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8715 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8716 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8717 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8718 | if (target_big_endian) |
ecd4ca1c ILT |
8719 | buf += 2; |
8720 | md_number_to_chars (buf, value, 2); | |
8721 | break; | |
8722 | ||
bf39474f ILT |
8723 | case BFD_RELOC_64: |
8724 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8725 | extended value if we are only 32 bits. */ | |
8726 | if (fixP->fx_done | |
8727 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8728 | { | |
8729 | if (8 <= sizeof (valueT)) | |
8730 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8731 | value, 8); | |
8732 | else | |
8733 | { | |
8734 | long w1, w2; | |
8735 | long hiv; | |
8736 | ||
8737 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8738 | if (target_big_endian) |
bf39474f ILT |
8739 | w1 += 4; |
8740 | else | |
8741 | w2 += 4; | |
8742 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8743 | if ((value & 0x80000000) != 0) | |
8744 | hiv = 0xffffffff; | |
8745 | else | |
8746 | hiv = 0; | |
8747 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8748 | } | |
8749 | } | |
8750 | break; | |
8751 | ||
f3645945 ILT |
8752 | case BFD_RELOC_32: |
8753 | /* If we are deleting this reloc entry, we must fill in the | |
8754 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8755 | resolved when it appears but is later defined. We also need |
8756 | to fill in the value if this is an embedded PIC switch table | |
8757 | entry. */ | |
8758 | if (fixP->fx_done | |
8759 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8760 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8761 | value, 4); | |
8762 | break; | |
8763 | ||
49ad0c4c ILT |
8764 | case BFD_RELOC_16: |
8765 | /* If we are deleting this reloc entry, we must fill in the | |
8766 | value now. */ | |
8767 | assert (fixP->fx_size == 2); | |
8768 | if (fixP->fx_done) | |
8769 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8770 | value, 2); | |
8771 | break; | |
8772 | ||
f3645945 ILT |
8773 | case BFD_RELOC_LO16: |
8774 | /* When handling an embedded PIC switch statement, we can wind | |
8775 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8776 | if (fixP->fx_done) | |
8777 | { | |
8778 | if (value < -0x8000 || value > 0x7fff) | |
8779 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8780 | "relocation overflow"); | |
0221ddf7 | 8781 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8782 | if (target_big_endian) |
f3645945 ILT |
8783 | buf += 2; |
8784 | md_number_to_chars (buf, value, 2); | |
8785 | } | |
8786 | break; | |
8787 | ||
3d3c5039 | 8788 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8789 | /* |
8790 | * We need to save the bits in the instruction since fixup_segment() | |
8791 | * might be deleting the relocation entry (i.e., a branch within | |
8792 | * the current segment). | |
8793 | */ | |
fbcfacb7 | 8794 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8795 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8796 | "Branch to odd address (%lx)", value); | |
670a50eb | 8797 | value >>= 2; |
670a50eb ILT |
8798 | |
8799 | /* update old instruction data */ | |
8800 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8801 | if (target_big_endian) |
8802 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8803 | else | |
8804 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8805 | |
8806 | if (value >= -0x8000 && value < 0x8000) | |
8807 | insn |= value & 0xffff; | |
8808 | else | |
8809 | { | |
8810 | /* The branch offset is too large. If this is an | |
8811 | unconditional branch, and we are not generating PIC code, | |
8812 | we can convert it to an absolute jump instruction. */ | |
8813 | if (mips_pic == NO_PIC | |
8814 | && fixP->fx_done | |
8815 | && fixP->fx_frag->fr_address >= text_section->vma | |
8816 | && (fixP->fx_frag->fr_address | |
8817 | < text_section->vma + text_section->_raw_size) | |
8818 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8819 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8820 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8821 | { | |
8822 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8823 | insn = 0x0c000000; /* jal */ | |
8824 | else | |
8825 | insn = 0x08000000; /* j */ | |
8826 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8827 | fixP->fx_done = 0; | |
8828 | fixP->fx_addsy = section_symbol (text_section); | |
8829 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8830 | } | |
8831 | else | |
8832 | { | |
8833 | /* FIXME. It would be possible in principle to handle | |
8834 | conditional branches which overflow. They could be | |
8835 | transformed into a branch around a jump. This would | |
8836 | require setting up variant frags for each different | |
8837 | branch type. The native MIPS assembler attempts to | |
8838 | handle these cases, but it appears to do it | |
8839 | incorrectly. */ | |
8840 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8841 | "Relocation overflow"); | |
8842 | } | |
8843 | } | |
8844 | ||
604633ae | 8845 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8846 | break; |
3d3c5039 ILT |
8847 | |
8848 | default: | |
670a50eb | 8849 | internalError (); |
3d3c5039 | 8850 | } |
5b63f465 | 8851 | |
670a50eb | 8852 | return 1; |
3d3c5039 ILT |
8853 | } |
8854 | ||
8855 | #if 0 | |
8856 | void | |
670a50eb ILT |
8857 | printInsn (oc) |
8858 | unsigned long oc; | |
3d3c5039 | 8859 | { |
670a50eb ILT |
8860 | const struct mips_opcode *p; |
8861 | int treg, sreg, dreg, shamt; | |
8862 | short imm; | |
8863 | const char *args; | |
8864 | int i; | |
3d3c5039 | 8865 | |
670a50eb ILT |
8866 | for (i = 0; i < NUMOPCODES; ++i) |
8867 | { | |
8868 | p = &mips_opcodes[i]; | |
8869 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8870 | { | |
8871 | printf ("%08lx %s\t", oc, p->name); | |
8872 | treg = (oc >> 16) & 0x1f; | |
8873 | sreg = (oc >> 21) & 0x1f; | |
8874 | dreg = (oc >> 11) & 0x1f; | |
8875 | shamt = (oc >> 6) & 0x1f; | |
8876 | imm = oc; | |
8877 | for (args = p->args;; ++args) | |
8878 | { | |
8879 | switch (*args) | |
8880 | { | |
3d3c5039 | 8881 | case '\0': |
670a50eb ILT |
8882 | printf ("\n"); |
8883 | break; | |
3d3c5039 ILT |
8884 | |
8885 | case ',': | |
8886 | case '(': | |
8887 | case ')': | |
670a50eb ILT |
8888 | printf ("%c", *args); |
8889 | continue; | |
3d3c5039 ILT |
8890 | |
8891 | case 'r': | |
670a50eb ILT |
8892 | assert (treg == sreg); |
8893 | printf ("$%d,$%d", treg, sreg); | |
8894 | continue; | |
3d3c5039 ILT |
8895 | |
8896 | case 'd': | |
918692a5 | 8897 | case 'G': |
670a50eb ILT |
8898 | printf ("$%d", dreg); |
8899 | continue; | |
3d3c5039 ILT |
8900 | |
8901 | case 't': | |
918692a5 | 8902 | case 'E': |
670a50eb ILT |
8903 | printf ("$%d", treg); |
8904 | continue; | |
3d3c5039 | 8905 | |
9226253a ILT |
8906 | case 'k': |
8907 | printf ("0x%x", treg); | |
8908 | continue; | |
8909 | ||
3d3c5039 ILT |
8910 | case 'b': |
8911 | case 's': | |
670a50eb ILT |
8912 | printf ("$%d", sreg); |
8913 | continue; | |
3d3c5039 ILT |
8914 | |
8915 | case 'a': | |
670a50eb ILT |
8916 | printf ("0x%08lx", oc & 0x1ffffff); |
8917 | continue; | |
3d3c5039 ILT |
8918 | |
8919 | case 'i': | |
8920 | case 'j': | |
8921 | case 'o': | |
8922 | case 'u': | |
670a50eb ILT |
8923 | printf ("%d", imm); |
8924 | continue; | |
3d3c5039 ILT |
8925 | |
8926 | case '<': | |
56c96faa | 8927 | case '>': |
670a50eb ILT |
8928 | printf ("$%d", shamt); |
8929 | continue; | |
3d3c5039 ILT |
8930 | |
8931 | default: | |
670a50eb | 8932 | internalError (); |
3d3c5039 | 8933 | } |
670a50eb | 8934 | break; |
3d3c5039 | 8935 | } |
670a50eb | 8936 | return; |
3d3c5039 ILT |
8937 | } |
8938 | } | |
670a50eb | 8939 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8940 | } |
8941 | #endif | |
8942 | ||
8943 | static symbolS * | |
8944 | get_symbol () | |
8945 | { | |
670a50eb ILT |
8946 | int c; |
8947 | char *name; | |
8948 | symbolS *p; | |
8949 | ||
8950 | name = input_line_pointer; | |
8951 | c = get_symbol_end (); | |
8952 | p = (symbolS *) symbol_find_or_make (name); | |
8953 | *input_line_pointer = c; | |
8954 | return p; | |
3d3c5039 ILT |
8955 | } |
8956 | ||
becfe05e ILT |
8957 | /* Align the current frag to a given power of two. The MIPS assembler |
8958 | also automatically adjusts any preceding label. */ | |
8959 | ||
8960 | static void | |
23dc1ae3 | 8961 | mips_align (to, fill, label) |
becfe05e ILT |
8962 | int to; |
8963 | int fill; | |
23dc1ae3 | 8964 | symbolS *label; |
becfe05e | 8965 | { |
fbcfacb7 | 8966 | mips_emit_delays (false); |
e2e5acfa | 8967 | frag_align (to, fill, 0); |
becfe05e | 8968 | record_alignment (now_seg, to); |
23dc1ae3 | 8969 | if (label != NULL) |
becfe05e | 8970 | { |
23dc1ae3 ILT |
8971 | assert (S_GET_SEGMENT (label) == now_seg); |
8972 | label->sy_frag = frag_now; | |
8973 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8974 | } |
8975 | } | |
8976 | ||
8977 | /* Align to a given power of two. .align 0 turns off the automatic | |
8978 | alignment used by the data creating pseudo-ops. */ | |
8979 | ||
3d3c5039 ILT |
8980 | static void |
8981 | s_align (x) | |
8982 | int x; | |
8983 | { | |
670a50eb ILT |
8984 | register int temp; |
8985 | register long temp_fill; | |
8986 | long max_alignment = 15; | |
3d3c5039 | 8987 | |
670a50eb | 8988 | /* |
3d3c5039 ILT |
8989 | |
8990 | o Note that the assembler pulls down any immediately preceeding label | |
8991 | to the aligned address. | |
8992 | o It's not documented but auto alignment is reinstated by | |
8993 | a .align pseudo instruction. | |
8994 | o Note also that after auto alignment is turned off the mips assembler | |
8995 | issues an error on attempt to assemble an improperly aligned data item. | |
8996 | We don't. | |
8997 | ||
8998 | */ | |
8999 | ||
670a50eb ILT |
9000 | temp = get_absolute_expression (); |
9001 | if (temp > max_alignment) | |
9002 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9003 | else if (temp < 0) | |
9004 | { | |
9005 | as_warn ("Alignment negative: 0 assumed."); | |
9006 | temp = 0; | |
9007 | } | |
9008 | if (*input_line_pointer == ',') | |
9009 | { | |
9010 | input_line_pointer++; | |
9011 | temp_fill = get_absolute_expression (); | |
9012 | } | |
9013 | else | |
9014 | temp_fill = 0; | |
9015 | if (temp) | |
9016 | { | |
9017 | auto_align = 1; | |
fbcfacb7 ILT |
9018 | mips_align (temp, (int) temp_fill, |
9019 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9020 | } |
670a50eb ILT |
9021 | else |
9022 | { | |
9023 | auto_align = 0; | |
3d3c5039 ILT |
9024 | } |
9025 | ||
670a50eb | 9026 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9027 | } |
9028 | ||
739708fa KR |
9029 | void |
9030 | mips_flush_pending_output () | |
becfe05e | 9031 | { |
fbcfacb7 ILT |
9032 | mips_emit_delays (false); |
9033 | mips_clear_insn_labels (); | |
becfe05e ILT |
9034 | } |
9035 | ||
3d3c5039 ILT |
9036 | static void |
9037 | s_change_sec (sec) | |
9038 | int sec; | |
9039 | { | |
88225433 | 9040 | segT seg; |
becfe05e | 9041 | |
5b63f465 ILT |
9042 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9043 | .sdata and .sbss sections. We change the .data and .rdata | |
9044 | pseudo-ops to use .sdata. */ | |
9045 | if (mips_pic == EMBEDDED_PIC | |
9046 | && (sec == 'd' || sec == 'r')) | |
9047 | sec = 's'; | |
9048 | ||
fbcfacb7 | 9049 | mips_emit_delays (false); |
670a50eb ILT |
9050 | switch (sec) |
9051 | { | |
3d3c5039 | 9052 | case 't': |
604633ae | 9053 | s_text (0); |
670a50eb | 9054 | break; |
3d3c5039 | 9055 | case 'd': |
604633ae | 9056 | s_data (0); |
670a50eb | 9057 | break; |
3d3c5039 | 9058 | case 'b': |
670a50eb | 9059 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9060 | demand_empty_rest_of_line (); |
9061 | break; | |
88225433 ILT |
9062 | |
9063 | case 'r': | |
1dc1e798 KR |
9064 | if (USE_GLOBAL_POINTER_OPT) |
9065 | { | |
9066 | seg = subseg_new (RDATA_SECTION_NAME, | |
9067 | (subsegT) get_absolute_expression ()); | |
9068 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9069 | { | |
9070 | bfd_set_section_flags (stdoutput, seg, | |
9071 | (SEC_ALLOC | |
9072 | | SEC_LOAD | |
9073 | | SEC_READONLY | |
9074 | | SEC_RELOC | |
9075 | | SEC_DATA)); | |
08e17202 ILT |
9076 | if (strcmp (TARGET_OS, "elf") != 0) |
9077 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9078 | } |
9079 | demand_empty_rest_of_line (); | |
9080 | } | |
9081 | else | |
9082 | { | |
9083 | as_bad ("No read only data section in this object file format"); | |
9084 | demand_empty_rest_of_line (); | |
9085 | return; | |
9086 | } | |
88225433 | 9087 | break; |
88225433 ILT |
9088 | |
9089 | case 's': | |
1dc1e798 KR |
9090 | if (USE_GLOBAL_POINTER_OPT) |
9091 | { | |
9092 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9093 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9094 | { | |
9095 | bfd_set_section_flags (stdoutput, seg, | |
9096 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9097 | | SEC_DATA); | |
08e17202 ILT |
9098 | if (strcmp (TARGET_OS, "elf") != 0) |
9099 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9100 | } |
9101 | demand_empty_rest_of_line (); | |
9102 | break; | |
9103 | } | |
9104 | else | |
9105 | { | |
9106 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9107 | demand_empty_rest_of_line (); | |
9108 | return; | |
9109 | } | |
3d3c5039 | 9110 | } |
88225433 | 9111 | |
670a50eb | 9112 | auto_align = 1; |
3d3c5039 ILT |
9113 | } |
9114 | ||
739708fa KR |
9115 | void |
9116 | mips_enable_auto_align () | |
9da4c5d1 | 9117 | { |
9da4c5d1 ILT |
9118 | auto_align = 1; |
9119 | } | |
9120 | ||
3d3c5039 ILT |
9121 | static void |
9122 | s_cons (log_size) | |
9123 | int log_size; | |
9124 | { | |
23dc1ae3 ILT |
9125 | symbolS *label; |
9126 | ||
fbcfacb7 ILT |
9127 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9128 | mips_emit_delays (false); | |
670a50eb | 9129 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9130 | mips_align (log_size, 0, label); |
fbcfacb7 | 9131 | mips_clear_insn_labels (); |
670a50eb | 9132 | cons (1 << log_size); |
3d3c5039 ILT |
9133 | } |
9134 | ||
3d3c5039 | 9135 | static void |
becfe05e ILT |
9136 | s_float_cons (type) |
9137 | int type; | |
3d3c5039 | 9138 | { |
23dc1ae3 ILT |
9139 | symbolS *label; |
9140 | ||
fbcfacb7 | 9141 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9142 | |
fbcfacb7 | 9143 | mips_emit_delays (false); |
670a50eb ILT |
9144 | |
9145 | if (auto_align) | |
becfe05e | 9146 | if (type == 'd') |
23dc1ae3 | 9147 | mips_align (3, 0, label); |
670a50eb | 9148 | else |
23dc1ae3 | 9149 | mips_align (2, 0, label); |
670a50eb | 9150 | |
fbcfacb7 | 9151 | mips_clear_insn_labels (); |
1849d646 | 9152 | |
becfe05e | 9153 | float_cons (type); |
3d3c5039 ILT |
9154 | } |
9155 | ||
c1444ec4 ILT |
9156 | /* Handle .globl. We need to override it because on Irix 5 you are |
9157 | permitted to say | |
9158 | .globl foo .text | |
9159 | where foo is an undefined symbol, to mean that foo should be | |
9160 | considered to be the address of a function. */ | |
9161 | ||
9162 | static void | |
9163 | s_mips_globl (x) | |
9164 | int x; | |
9165 | { | |
9166 | char *name; | |
9167 | int c; | |
9168 | symbolS *symbolP; | |
fb251650 | 9169 | flagword flag; |
c1444ec4 ILT |
9170 | |
9171 | name = input_line_pointer; | |
9172 | c = get_symbol_end (); | |
9173 | symbolP = symbol_find_or_make (name); | |
9174 | *input_line_pointer = c; | |
9175 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9176 | |
9177 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9178 | being a function is apparently labelled as being an object. */ | |
9179 | flag = BSF_OBJECT; | |
9180 | ||
c1444ec4 ILT |
9181 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9182 | { | |
9183 | char *secname; | |
9184 | asection *sec; | |
9185 | ||
9186 | secname = input_line_pointer; | |
9187 | c = get_symbol_end (); | |
9188 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9189 | if (sec == NULL) | |
9190 | as_bad ("%s: no such section", secname); | |
9191 | *input_line_pointer = c; | |
9192 | ||
9193 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9194 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9195 | } |
9196 | ||
fb251650 ILT |
9197 | symbolP->bsym->flags |= flag; |
9198 | ||
c1444ec4 ILT |
9199 | S_SET_EXTERNAL (symbolP); |
9200 | demand_empty_rest_of_line (); | |
9201 | } | |
9202 | ||
3d3c5039 ILT |
9203 | static void |
9204 | s_option (x) | |
9205 | int x; | |
9206 | { | |
dd3f1f76 ILT |
9207 | char *opt; |
9208 | char c; | |
9209 | ||
9210 | opt = input_line_pointer; | |
9211 | c = get_symbol_end (); | |
9212 | ||
dd3f1f76 | 9213 | if (*opt == 'O') |
9226253a ILT |
9214 | { |
9215 | /* FIXME: What does this mean? */ | |
9216 | } | |
dd3f1f76 | 9217 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9218 | { |
d9aba805 | 9219 | int i; |
42562568 | 9220 | |
d9aba805 ILT |
9221 | i = atoi (opt + 3); |
9222 | if (i == 0) | |
9223 | mips_pic = NO_PIC; | |
9224 | else if (i == 2) | |
9225 | mips_pic = SVR4_PIC; | |
9226 | else | |
9227 | as_bad (".option pic%d not supported", i); | |
9228 | ||
1dc1e798 | 9229 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9230 | { |
9231 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9232 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9233 | g_switch_value = 0; |
9234 | bfd_set_gp_size (stdoutput, 0); | |
9235 | } | |
9226253a | 9236 | } |
dd3f1f76 ILT |
9237 | else |
9238 | as_warn ("Unrecognized option \"%s\"", opt); | |
9239 | ||
9240 | *input_line_pointer = c; | |
670a50eb | 9241 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9242 | } |
9243 | ||
9244 | static void | |
9245 | s_mipsset (x) | |
9246 | int x; | |
9247 | { | |
670a50eb ILT |
9248 | char *name = input_line_pointer, ch; |
9249 | ||
9250 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9251 | input_line_pointer++; | |
9252 | ch = *input_line_pointer; | |
9253 | *input_line_pointer = '\0'; | |
9254 | ||
9255 | if (strcmp (name, "reorder") == 0) | |
9256 | { | |
4a1cb507 | 9257 | if (mips_noreorder && prev_nop_frag != NULL) |
4e95866e | 9258 | { |
4a1cb507 ILT |
9259 | /* If we still have pending nops, we can discard them. The |
9260 | usual nop handling will insert any that are still | |
9261 | needed. */ | |
9262 | prev_nop_frag->fr_fix -= prev_nop_frag_holds * (mips16 ? 2 : 4); | |
9263 | prev_nop_frag = NULL; | |
4e95866e | 9264 | } |
670a50eb ILT |
9265 | mips_noreorder = 0; |
9266 | } | |
9267 | else if (strcmp (name, "noreorder") == 0) | |
9268 | { | |
fbcfacb7 | 9269 | mips_emit_delays (true); |
670a50eb | 9270 | mips_noreorder = 1; |
0dd2d296 | 9271 | mips_any_noreorder = 1; |
670a50eb ILT |
9272 | } |
9273 | else if (strcmp (name, "at") == 0) | |
9274 | { | |
9275 | mips_noat = 0; | |
9276 | } | |
9277 | else if (strcmp (name, "noat") == 0) | |
9278 | { | |
9279 | mips_noat = 1; | |
3d3c5039 | 9280 | } |
670a50eb ILT |
9281 | else if (strcmp (name, "macro") == 0) |
9282 | { | |
9283 | mips_warn_about_macros = 0; | |
9284 | } | |
9285 | else if (strcmp (name, "nomacro") == 0) | |
9286 | { | |
9287 | if (mips_noreorder == 0) | |
9288 | as_bad ("`noreorder' must be set before `nomacro'"); | |
9289 | mips_warn_about_macros = 1; | |
9290 | } | |
9291 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9292 | { | |
9293 | mips_nomove = 0; | |
9294 | } | |
9295 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9296 | { | |
9297 | mips_nomove = 1; | |
9298 | } | |
9299 | else if (strcmp (name, "bopt") == 0) | |
9300 | { | |
9301 | mips_nobopt = 0; | |
9302 | } | |
9303 | else if (strcmp (name, "nobopt") == 0) | |
9304 | { | |
9305 | mips_nobopt = 1; | |
9306 | } | |
943321c0 ILT |
9307 | else if (strcmp (name, "mips16") == 0 |
9308 | || strcmp (name, "MIPS-16") == 0) | |
9309 | mips16 = 1; | |
9310 | else if (strcmp (name, "nomips16") == 0 | |
9311 | || strcmp (name, "noMIPS-16") == 0) | |
9312 | mips16 = 0; | |
1051c97f ILT |
9313 | else if (strncmp (name, "mips", 4) == 0) |
9314 | { | |
9315 | int isa; | |
9316 | ||
9317 | /* Permit the user to change the ISA on the fly. Needless to | |
9318 | say, misuse can cause serious problems. */ | |
9319 | isa = atoi (name + 4); | |
9320 | if (isa == 0) | |
9321 | mips_isa = file_mips_isa; | |
d8a1c247 | 9322 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9323 | as_bad ("unknown ISA level"); |
9324 | else | |
9325 | mips_isa = isa; | |
9326 | } | |
cc5703cd ILT |
9327 | else if (strcmp (name, "autoextend") == 0) |
9328 | mips16_autoextend = 1; | |
9329 | else if (strcmp (name, "noautoextend") == 0) | |
9330 | mips16_autoextend = 0; | |
670a50eb ILT |
9331 | else |
9332 | { | |
9333 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9334 | } | |
9335 | *input_line_pointer = ch; | |
9336 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9337 | } |
9338 | ||
9226253a ILT |
9339 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9340 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9341 | ||
9342 | static void | |
9343 | s_abicalls (ignore) | |
9344 | int ignore; | |
9345 | { | |
d9aba805 | 9346 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9347 | if (USE_GLOBAL_POINTER_OPT) |
9348 | { | |
9349 | if (g_switch_seen && g_switch_value != 0) | |
9350 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9351 | g_switch_value = 0; | |
9352 | } | |
d9aba805 | 9353 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9354 | demand_empty_rest_of_line (); |
9355 | } | |
9356 | ||
9357 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9358 | PIC code. It sets the $gp register for the function based on the | |
9359 | function address, which is in the register named in the argument. | |
9360 | This uses a relocation against _gp_disp, which is handled specially | |
9361 | by the linker. The result is: | |
9362 | lui $gp,%hi(_gp_disp) | |
9363 | addiu $gp,$gp,%lo(_gp_disp) | |
9364 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9365 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9366 | |
9367 | static void | |
9368 | s_cpload (ignore) | |
9369 | int ignore; | |
9370 | { | |
9371 | expressionS ex; | |
9372 | int icnt = 0; | |
9373 | ||
d9aba805 ILT |
9374 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9375 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9376 | { |
9377 | s_ignore (0); | |
9378 | return; | |
9379 | } | |
9380 | ||
9381 | /* .cpload should be a in .set noreorder section. */ | |
9382 | if (mips_noreorder == 0) | |
9383 | as_warn (".cpload not in noreorder section"); | |
9384 | ||
9226253a ILT |
9385 | ex.X_op = O_symbol; |
9386 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9387 | ex.X_op_symbol = NULL; | |
9388 | ex.X_add_number = 0; | |
9389 | ||
fb251650 ILT |
9390 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9391 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9392 | ||
0dd2d296 ILT |
9393 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9394 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9395 | (int) BFD_RELOC_LO16); |
9396 | ||
0dd2d296 ILT |
9397 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9398 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9399 | |
9400 | demand_empty_rest_of_line (); | |
9401 | } | |
9402 | ||
9403 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9404 | offset from $sp. The offset is remembered, and after making a PIC | |
9405 | call $gp is restored from that location. */ | |
9406 | ||
9407 | static void | |
9408 | s_cprestore (ignore) | |
9409 | int ignore; | |
9410 | { | |
9411 | expressionS ex; | |
9412 | int icnt = 0; | |
9413 | ||
d9aba805 ILT |
9414 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9415 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9416 | { |
9417 | s_ignore (0); | |
9418 | return; | |
9419 | } | |
9420 | ||
9226253a ILT |
9421 | mips_cprestore_offset = get_absolute_expression (); |
9422 | ||
9423 | ex.X_op = O_constant; | |
9424 | ex.X_add_symbol = NULL; | |
9425 | ex.X_op_symbol = NULL; | |
9426 | ex.X_add_number = mips_cprestore_offset; | |
9427 | ||
0dd2d296 | 9428 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9429 | mips_isa < 3 ? "sw" : "sd", |
9430 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9431 | ||
9432 | demand_empty_rest_of_line (); | |
9433 | } | |
9434 | ||
0dd2d296 ILT |
9435 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9436 | code. It generates a 32 bit GP relative reloc. */ | |
9437 | ||
9438 | static void | |
9439 | s_gpword (ignore) | |
9440 | int ignore; | |
9441 | { | |
23dc1ae3 | 9442 | symbolS *label; |
0dd2d296 ILT |
9443 | expressionS ex; |
9444 | char *p; | |
9445 | ||
9446 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9447 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9448 | { |
9449 | s_cons (2); | |
9450 | return; | |
9451 | } | |
9452 | ||
fbcfacb7 ILT |
9453 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9454 | mips_emit_delays (true); | |
0dd2d296 | 9455 | if (auto_align) |
23dc1ae3 | 9456 | mips_align (2, 0, label); |
fbcfacb7 | 9457 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9458 | |
9459 | expression (&ex); | |
9460 | ||
9461 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9462 | { | |
9463 | as_bad ("Unsupported use of .gpword"); | |
9464 | ignore_rest_of_line (); | |
9465 | } | |
9466 | ||
9467 | p = frag_more (4); | |
9468 | md_number_to_chars (p, (valueT) 0, 4); | |
9469 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9470 | BFD_RELOC_MIPS_GPREL32); | |
9471 | ||
9472 | demand_empty_rest_of_line (); | |
9473 | } | |
9474 | ||
9475 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9476 | tables in SVR4 PIC code. */ | |
9477 | ||
9478 | static void | |
9479 | s_cpadd (ignore) | |
9480 | int ignore; | |
9481 | { | |
9482 | int icnt = 0; | |
9483 | int reg; | |
9484 | ||
9485 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9486 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9487 | { |
9488 | s_ignore (0); | |
9489 | return; | |
9490 | } | |
9491 | ||
9492 | /* Add $gp to the register named as an argument. */ | |
9493 | reg = tc_get_register (0); | |
9494 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9495 | mips_isa < 3 ? "addu" : "daddu", | |
9496 | "d,v,t", reg, reg, GP); | |
9497 | ||
9498 | demand_empty_rest_of_line (); | |
9499 | } | |
9500 | ||
ed3eb786 ILT |
9501 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9502 | mips16 mode. This permits the linker to handle them specially, | |
9503 | such as generating jalx instructions when needed. We also make | |
9504 | them odd for the duration of the assembly, in order to generate the | |
9505 | right sort of code. We will make them even in the adjust_symtab | |
9506 | routine, while leaving them marked. This is convenient for the | |
9507 | debugger and the disassembler. The linker knows to make them odd | |
9508 | again. */ | |
9509 | ||
9510 | static void | |
9511 | s_insn (ignore) | |
9512 | int ignore; | |
9513 | { | |
9514 | if (mips16) | |
9515 | { | |
9516 | struct insn_label_list *l; | |
9517 | ||
9518 | for (l = insn_labels; l != NULL; l = l->next) | |
9519 | { | |
9520 | #ifdef S_SET_OTHER | |
9521 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9522 | S_SET_OTHER (l->label, STO_MIPS16); | |
9523 | #endif | |
9524 | ++l->label->sy_value.X_add_number; | |
9525 | } | |
9526 | ||
9527 | mips_clear_insn_labels (); | |
9528 | } | |
9529 | ||
9530 | demand_empty_rest_of_line (); | |
9531 | } | |
9532 | ||
9226253a | 9533 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9534 | to parse .frame. The argument is non-zero if this is the frame |
9535 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9536 | |
3d3c5039 | 9537 | int |
0dd2d296 ILT |
9538 | tc_get_register (frame) |
9539 | int frame; | |
3d3c5039 ILT |
9540 | { |
9541 | int reg; | |
9542 | ||
9543 | SKIP_WHITESPACE (); | |
9544 | if (*input_line_pointer++ != '$') | |
9545 | { | |
9546 | as_warn ("expected `$'"); | |
0dd2d296 | 9547 | reg = 0; |
3d3c5039 | 9548 | } |
0dd2d296 | 9549 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9550 | { |
9551 | reg = get_absolute_expression (); | |
9552 | if (reg < 0 || reg >= 32) | |
9553 | { | |
9554 | as_warn ("Bad register number"); | |
9555 | reg = 0; | |
9556 | } | |
9557 | } | |
9558 | else | |
9559 | { | |
9560 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9561 | reg = FP; |
3d3c5039 | 9562 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9563 | reg = SP; |
3d3c5039 | 9564 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9565 | reg = GP; |
3d3c5039 | 9566 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9567 | reg = AT; |
3d3c5039 ILT |
9568 | else |
9569 | { | |
9570 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9571 | reg = 0; |
3d3c5039 ILT |
9572 | } |
9573 | input_line_pointer += 2; | |
9574 | } | |
0dd2d296 ILT |
9575 | if (frame) |
9576 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9577 | return reg; |
9578 | } | |
9579 | ||
0dd2d296 ILT |
9580 | valueT |
9581 | md_section_align (seg, addr) | |
9582 | asection *seg; | |
9583 | valueT addr; | |
9584 | { | |
9585 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9586 | ||
cf32394d ILT |
9587 | #ifdef OBJ_ELF |
9588 | /* We don't need to align ELF sections to the full alignment. | |
9589 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9590 | byte boundary. We don't bother to align the sections if we are |
9591 | targeted for an embedded system. */ | |
9592 | if (strcmp (TARGET_OS, "elf") == 0) | |
9593 | return addr; | |
943321c0 ILT |
9594 | if (align > 4) |
9595 | align = 4; | |
10a14e36 | 9596 | #endif |
cf32394d ILT |
9597 | |
9598 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9599 | } |
9600 | ||
d8a1c247 KR |
9601 | /* Utility routine, called from above as well. If called while the |
9602 | input file is still being read, it's only an approximation. (For | |
9603 | example, a symbol may later become defined which appeared to be | |
9604 | undefined earlier.) */ | |
22ba90ce ILT |
9605 | |
9606 | static int | |
9607 | nopic_need_relax (sym) | |
d8a1c247 KR |
9608 | symbolS *sym; |
9609 | { | |
9610 | if (sym == 0) | |
9611 | return 0; | |
9612 | ||
1dc1e798 KR |
9613 | if (USE_GLOBAL_POINTER_OPT) |
9614 | { | |
9615 | const char *symname; | |
9616 | int change; | |
9617 | ||
9618 | /* Find out whether this symbol can be referenced off the GP | |
9619 | register. It can be if it is smaller than the -G size or if | |
9620 | it is in the .sdata or .sbss section. Certain symbols can | |
9621 | not be referenced off the GP, although it appears as though | |
9622 | they can. */ | |
9623 | symname = S_GET_NAME (sym); | |
9624 | if (symname != (const char *) NULL | |
9625 | && (strcmp (symname, "eprol") == 0 | |
9626 | || strcmp (symname, "etext") == 0 | |
9627 | || strcmp (symname, "_gp") == 0 | |
9628 | || strcmp (symname, "edata") == 0 | |
9629 | || strcmp (symname, "_fbss") == 0 | |
9630 | || strcmp (symname, "_fdata") == 0 | |
9631 | || strcmp (symname, "_ftext") == 0 | |
9632 | || strcmp (symname, "end") == 0 | |
9633 | || strcmp (symname, "_gp_disp") == 0)) | |
9634 | change = 1; | |
9635 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9636 | && (0 |
9637 | #ifndef NO_ECOFF_DEBUGGING | |
9638 | || (sym->ecoff_extern_size != 0 | |
9639 | && sym->ecoff_extern_size <= g_switch_value) | |
9640 | #endif | |
1dc1e798 KR |
9641 | || (S_GET_VALUE (sym) != 0 |
9642 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9643 | change = 0; | |
9644 | else | |
9645 | { | |
9646 | const char *segname; | |
d8a1c247 | 9647 | |
1dc1e798 KR |
9648 | segname = segment_name (S_GET_SEGMENT (sym)); |
9649 | assert (strcmp (segname, ".lit8") != 0 | |
9650 | && strcmp (segname, ".lit4") != 0); | |
9651 | change = (strcmp (segname, ".sdata") != 0 | |
9652 | && strcmp (segname, ".sbss") != 0); | |
9653 | } | |
9654 | return change; | |
9655 | } | |
9656 | else | |
9657 | /* We are not optimizing for the GP register. */ | |
9658 | return 1; | |
d8a1c247 KR |
9659 | } |
9660 | ||
cc5703cd ILT |
9661 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9662 | extended opcode. SEC is the section the frag is in. */ | |
9663 | ||
9664 | static int | |
9665 | mips16_extended_frag (fragp, sec, stretch) | |
9666 | fragS *fragp; | |
9667 | asection *sec; | |
9668 | long stretch; | |
9669 | { | |
9670 | int type; | |
9671 | register const struct mips16_immed_operand *op; | |
9672 | offsetT val; | |
9673 | int mintiny, maxtiny; | |
f74ba7a3 | 9674 | segT symsec; |
cc5703cd | 9675 | |
8728fa92 ILT |
9676 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9677 | return 0; | |
9678 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9679 | return 1; | |
9680 | ||
cc5703cd ILT |
9681 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9682 | op = mips16_immed_operands; | |
9683 | while (op->type != type) | |
9684 | { | |
9685 | ++op; | |
9686 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9687 | } | |
9688 | ||
9689 | if (op->unsp) | |
9690 | { | |
9691 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9692 | { | |
9693 | mintiny = 1; | |
9694 | maxtiny = 1 << op->nbits; | |
9695 | } | |
9696 | else | |
9697 | { | |
9698 | mintiny = 0; | |
9699 | maxtiny = (1 << op->nbits) - 1; | |
9700 | } | |
9701 | } | |
9702 | else | |
9703 | { | |
9704 | mintiny = - (1 << (op->nbits - 1)); | |
9705 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9706 | } | |
9707 | ||
f74ba7a3 ILT |
9708 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9709 | a particular frag address. */ | |
9710 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9711 | { | |
9712 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9713 | + fragp->fr_symbol->sy_frag->fr_address); | |
9714 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9715 | } | |
9716 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9717 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9718 | == O_constant)) | |
9719 | { | |
9720 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9721 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9722 | + fragp->fr_symbol->sy_value.X_add_number | |
9723 | + fragp->fr_symbol->sy_frag->fr_address); | |
9724 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9725 | } | |
9726 | else | |
9727 | return 1; | |
cc5703cd ILT |
9728 | |
9729 | if (op->pcrel) | |
9730 | { | |
9731 | addressT addr; | |
9732 | ||
9733 | /* We won't have the section when we are called from | |
9734 | mips_relax_frag. However, we will always have been called | |
9735 | from md_estimate_size_before_relax first. If this is a | |
9736 | branch to a different section, we mark it as such. If SEC is | |
9737 | NULL, and the frag is not marked, then it must be a branch to | |
9738 | the same section. */ | |
9739 | if (sec == NULL) | |
9740 | { | |
9741 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9742 | return 1; | |
9743 | } | |
9744 | else | |
9745 | { | |
f74ba7a3 | 9746 | if (symsec != sec) |
cc5703cd ILT |
9747 | { |
9748 | fragp->fr_subtype = | |
9749 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9750 | ||
9751 | /* FIXME: We should support this, and let the linker | |
9752 | catch branches and loads that are out of range. */ | |
9753 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9754 | "unsupported PC relative reference to different section"); | |
9755 | ||
9756 | return 1; | |
9757 | } | |
9758 | } | |
9759 | ||
9760 | /* In this case, we know for sure that the symbol fragment is in | |
9761 | the same section. If the fr_address of the symbol fragment | |
9762 | is greater then the address of this fragment we want to add | |
9763 | in STRETCH in order to get a better estimate of the address. | |
9764 | This particularly matters because of the shift bits. */ | |
9765 | if (stretch != 0 | |
9766 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9767 | { | |
9768 | fragS *f; | |
9769 | ||
e2e5acfa JW |
9770 | /* Adjust stretch for any alignment frag. FIXME: This |
9771 | doesn't handle the fr_subtype field, which specifies a | |
9772 | maximum number of bytes to skip when doing an alignment. */ | |
cc5703cd ILT |
9773 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) |
9774 | { | |
9775 | assert (f != NULL); | |
9776 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9777 | { | |
9778 | if (stretch < 0) | |
9779 | stretch = - ((- stretch) | |
9780 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9781 | else | |
9782 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9783 | if (stretch == 0) | |
9784 | break; | |
9785 | } | |
9786 | } | |
9787 | val += stretch; | |
9788 | } | |
9789 | ||
a677feeb ILT |
9790 | addr = fragp->fr_address + fragp->fr_fix; |
9791 | ||
9792 | /* The base address rules are complicated. The base address of | |
9793 | a branch is the following instruction. The base address of a | |
9794 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
9795 | is in a delay slot (in which case it can not be extended) use |
9796 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 9797 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
9798 | { |
9799 | addr += 2; | |
319305a7 ILT |
9800 | |
9801 | /* If we are currently assuming that this frag should be | |
9802 | extended, then, the current address is two bytes | |
9803 | higher. */ | |
9804 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9805 | addr += 2; | |
9806 | ||
fbcfacb7 ILT |
9807 | /* Ignore the low bit in the target, since it will be set |
9808 | for a text label. */ | |
9809 | if ((val & 1) != 0) | |
9810 | --val; | |
9811 | } | |
a677feeb ILT |
9812 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9813 | addr -= 4; | |
9814 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9815 | addr -= 2; | |
cc5703cd | 9816 | |
cc5703cd ILT |
9817 | val -= addr & ~ ((1 << op->shift) - 1); |
9818 | ||
9819 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9820 | if (type == 'p' || type == 'q') | |
9821 | val /= 2; | |
9822 | ||
9823 | /* If any of the shifted bits are set, we must use an extended | |
9824 | opcode. If the address depends on the size of this | |
9825 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9826 | use an extended opcode. We only check this when we are in |
9827 | the main relaxation loop, when SEC is NULL. */ | |
9828 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9829 | { | |
9830 | fragp->fr_subtype = | |
9831 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9832 | return 1; | |
9833 | } | |
9834 | ||
9835 | /* If we are about to mark a frag as extended because the value | |
9836 | is precisely maxtiny + 1, then there is a chance of an | |
9837 | infinite loop as in the following code: | |
9838 | la $4,foo | |
9839 | .skip 1020 | |
9840 | .align 2 | |
9841 | foo: | |
9842 | In this case when the la is extended, foo is 0x3fc bytes | |
9843 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9844 | the la must be extended. To avoid this loop, we mark the | |
9845 | frag as extended if it was small, and is about to become | |
9846 | extended with a value of maxtiny + 1. */ | |
9847 | if (val == ((maxtiny + 1) << op->shift) | |
9848 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9849 | && sec == NULL) | |
cc5703cd ILT |
9850 | { |
9851 | fragp->fr_subtype = | |
9852 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9853 | return 1; | |
9854 | } | |
9855 | } | |
41a0ed22 ILT |
9856 | else if (symsec != absolute_section && sec != NULL) |
9857 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9858 | |
9859 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9860 | || val < (mintiny << op->shift) | |
9861 | || val > (maxtiny << op->shift)) | |
9862 | return 1; | |
9863 | else | |
9864 | return 0; | |
9865 | } | |
9866 | ||
9867 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9868 | mips16, we are not really relaxing here, and the final size is | |
9869 | encoded in the subtype information. For the mips16, we have to | |
9870 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9871 | |
0dd2d296 ILT |
9872 | /*ARGSUSED*/ |
9873 | int | |
9874 | md_estimate_size_before_relax (fragp, segtype) | |
9875 | fragS *fragp; | |
9876 | asection *segtype; | |
9877 | { | |
9878 | int change; | |
9879 | ||
cc5703cd ILT |
9880 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9881 | { | |
9882 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9883 | { | |
9884 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9885 | return 4; | |
9886 | } | |
9887 | else | |
9888 | { | |
9889 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9890 | return 2; | |
9891 | } | |
9892 | } | |
9893 | ||
d9aba805 | 9894 | if (mips_pic == NO_PIC) |
0dd2d296 | 9895 | { |
d8a1c247 | 9896 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9897 | } |
d9aba805 | 9898 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9899 | { |
9900 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9901 | ||
9902 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9903 | change = (symsec != &bfd_und_section | |
9904 | && symsec != &bfd_abs_section | |
9905 | && ! bfd_is_com_section (symsec)); | |
9906 | } | |
d9aba805 ILT |
9907 | else |
9908 | abort (); | |
0dd2d296 ILT |
9909 | |
9910 | if (change) | |
9911 | { | |
9912 | /* Record the offset to the first reloc in the fr_opcode field. | |
9913 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9914 | must be expanded. */ | |
9915 | fragp->fr_opcode = (fragp->fr_literal | |
9916 | + fragp->fr_fix | |
9917 | - RELAX_OLD (fragp->fr_subtype) | |
9918 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9919 | /* FIXME: This really needs as_warn_where. */ | |
9920 | if (RELAX_WARN (fragp->fr_subtype)) | |
9921 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9922 | } | |
9923 | ||
9924 | if (! change) | |
9925 | return 0; | |
9926 | else | |
9927 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9928 | } | |
9929 | ||
0d7f9025 ILT |
9930 | /* This is called to see whether a reloc against a defined symbol |
9931 | should be converted into a reloc against a section. Don't adjust | |
9932 | MIPS16 jump relocations, so we don't have to worry about the format | |
9933 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
9934 | mips16 symbols, so that the linker can find them if it needs to set |
9935 | up a stub. */ | |
0d7f9025 ILT |
9936 | |
9937 | int | |
9938 | mips_fix_adjustable (fixp) | |
9939 | fixS *fixp; | |
9940 | { | |
9941 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
9942 | return 0; | |
9943 | if (fixp->fx_addsy == NULL) | |
9944 | return 1; | |
0d7f9025 ILT |
9945 | #ifdef S_GET_OTHER |
9946 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9947 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16) | |
9948 | return 0; | |
9949 | #endif | |
9950 | return 1; | |
9951 | } | |
9952 | ||
0dd2d296 ILT |
9953 | /* Translate internal representation of relocation info to BFD target |
9954 | format. */ | |
9955 | ||
9956 | arelent ** | |
3d3c5039 ILT |
9957 | tc_gen_reloc (section, fixp) |
9958 | asection *section; | |
9959 | fixS *fixp; | |
9960 | { | |
0dd2d296 | 9961 | static arelent *retval[4]; |
3d3c5039 | 9962 | arelent *reloc; |
a8aed9dd | 9963 | bfd_reloc_code_real_type code; |
3d3c5039 | 9964 | |
0dd2d296 ILT |
9965 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9966 | retval[1] = NULL; | |
3d3c5039 ILT |
9967 | |
9968 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9969 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9970 | |
9971 | if (mips_pic == EMBEDDED_PIC | |
9972 | && SWITCH_TABLE (fixp)) | |
9973 | { | |
9974 | /* For a switch table entry we use a special reloc. The addend | |
9975 | is actually the difference between the reloc address and the | |
9976 | subtrahend. */ | |
9977 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9978 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9979 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9980 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9981 | } | |
ecd4ca1c ILT |
9982 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9983 | { | |
9984 | /* We use a special addend for an internal RELLO reloc. */ | |
9985 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9986 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9987 | else | |
9988 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9989 | } | |
9990 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9991 | { | |
9992 | assert (fixp->fx_next != NULL | |
9993 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9994 | /* We use a special addend for an internal RELHI reloc. The | |
9995 | reloc is relative to the RELLO; adjust the addend | |
9996 | accordingly. */ | |
9997 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9998 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9999 | + fixp->fx_next->fx_where | |
10000 | - S_GET_VALUE (fixp->fx_subsy)); | |
10001 | else | |
10002 | reloc->addend = (fixp->fx_addnumber | |
10003 | + fixp->fx_next->fx_frag->fr_address | |
10004 | + fixp->fx_next->fx_where); | |
10005 | } | |
1c803e52 | 10006 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10007 | reloc->addend = fixp->fx_addnumber; |
10008 | else | |
5b63f465 | 10009 | { |
1dc1e798 KR |
10010 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10011 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10012 | handling. */ | |
10013 | reloc->addend = reloc->address; | |
10014 | else | |
10015 | reloc->addend = -reloc->address; | |
5b63f465 | 10016 | } |
0dd2d296 ILT |
10017 | |
10018 | /* If this is a variant frag, we may need to adjust the existing | |
10019 | reloc and generate a new one. */ | |
10020 | if (fixp->fx_frag->fr_opcode != NULL | |
10021 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10022 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10023 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10024 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10025 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10026 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10027 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10028 | { |
10029 | arelent *reloc2; | |
10030 | ||
cc5703cd ILT |
10031 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10032 | ||
0dd2d296 | 10033 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10034 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10035 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10036 | the second one handle all of them. */ | |
0dd2d296 ILT |
10037 | if (fixp->fx_next != NULL |
10038 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10039 | { | |
fb251650 ILT |
10040 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10041 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10042 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10043 | && (fixp->fx_next->fx_r_type | |
10044 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10045 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10046 | && (fixp->fx_next->fx_r_type | |
10047 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10048 | retval[0] = NULL; |
10049 | return retval; | |
10050 | } | |
10051 | ||
10052 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10053 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10054 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10055 | retval[2] = NULL; | |
10056 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10057 | reloc2->address = (reloc->address | |
10058 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10059 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10060 | reloc2->addend = fixp->fx_addnumber; | |
10061 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10062 | assert (reloc2->howto != NULL); | |
10063 | ||
10064 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10065 | { | |
10066 | arelent *reloc3; | |
10067 | ||
10068 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10069 | retval[3] = NULL; | |
10070 | *reloc3 = *reloc2; | |
10071 | reloc3->address += 4; | |
10072 | } | |
10073 | ||
d9aba805 | 10074 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10075 | { |
10076 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10077 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10078 | } | |
d9aba805 | 10079 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10080 | { |
fb251650 | 10081 | switch (fixp->fx_r_type) |
0dd2d296 | 10082 | { |
fb251650 ILT |
10083 | default: |
10084 | abort (); | |
10085 | case BFD_RELOC_MIPS_GOT16: | |
10086 | break; | |
10087 | case BFD_RELOC_MIPS_CALL16: | |
10088 | case BFD_RELOC_MIPS_GOT_LO16: | |
10089 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10090 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10091 | break; |
0dd2d296 ILT |
10092 | } |
10093 | } | |
d9aba805 ILT |
10094 | else |
10095 | abort (); | |
0dd2d296 ILT |
10096 | } |
10097 | ||
a8aed9dd ILT |
10098 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10099 | fixup_segment converted a non-PC relative reloc into a PC | |
10100 | relative reloc. In such a case, we need to convert the reloc | |
10101 | code. */ | |
10102 | code = fixp->fx_r_type; | |
10103 | if (fixp->fx_pcrel) | |
10104 | { | |
10105 | switch (code) | |
10106 | { | |
10107 | case BFD_RELOC_8: | |
10108 | code = BFD_RELOC_8_PCREL; | |
10109 | break; | |
10110 | case BFD_RELOC_16: | |
10111 | code = BFD_RELOC_16_PCREL; | |
10112 | break; | |
10113 | case BFD_RELOC_32: | |
10114 | code = BFD_RELOC_32_PCREL; | |
10115 | break; | |
bf39474f ILT |
10116 | case BFD_RELOC_64: |
10117 | code = BFD_RELOC_64_PCREL; | |
10118 | break; | |
a8aed9dd ILT |
10119 | case BFD_RELOC_8_PCREL: |
10120 | case BFD_RELOC_16_PCREL: | |
10121 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10122 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10123 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10124 | case BFD_RELOC_PCREL_HI16_S: |
10125 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10126 | break; |
10127 | default: | |
10128 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10129 | "Cannot make %s relocation PC relative", | |
10130 | bfd_get_reloc_code_name (code)); | |
10131 | } | |
10132 | } | |
10133 | ||
d9aba805 ILT |
10134 | /* To support a PC relative reloc when generating embedded PIC code |
10135 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10136 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10137 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10138 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10139 | && mips_pic != EMBEDDED_PIC) |
10140 | reloc->howto = NULL; | |
10141 | else | |
a8aed9dd | 10142 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10143 | |
52aa70b5 JW |
10144 | if (reloc->howto == NULL) |
10145 | { | |
10146 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10147 | "Can not represent %s relocation in this object file format", |
10148 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10149 | retval[0] = NULL; |
52aa70b5 | 10150 | } |
3d3c5039 | 10151 | |
0dd2d296 | 10152 | return retval; |
3d3c5039 ILT |
10153 | } |
10154 | ||
cc5703cd ILT |
10155 | /* Relax a machine dependent frag. This returns the amount by which |
10156 | the current size of the frag should change. */ | |
10157 | ||
10158 | int | |
10159 | mips_relax_frag (fragp, stretch) | |
10160 | fragS *fragp; | |
10161 | long stretch; | |
10162 | { | |
10163 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10164 | return 0; | |
10165 | ||
10166 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10167 | { | |
10168 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10169 | return 0; | |
10170 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10171 | return 2; | |
10172 | } | |
10173 | else | |
10174 | { | |
10175 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10176 | return 0; | |
10177 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10178 | return -2; | |
10179 | } | |
10180 | ||
10181 | return 0; | |
10182 | } | |
10183 | ||
0dd2d296 ILT |
10184 | /* Convert a machine dependent frag. */ |
10185 | ||
10186 | void | |
10187 | md_convert_frag (abfd, asec, fragp) | |
10188 | bfd *abfd; | |
10189 | segT asec; | |
10190 | fragS *fragp; | |
3d3c5039 | 10191 | { |
0dd2d296 ILT |
10192 | int old, new; |
10193 | char *fixptr; | |
3d3c5039 | 10194 | |
cc5703cd ILT |
10195 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10196 | { | |
10197 | int type; | |
10198 | register const struct mips16_immed_operand *op; | |
10199 | boolean small, ext; | |
10200 | offsetT val; | |
10201 | bfd_byte *buf; | |
10202 | unsigned long insn; | |
10203 | boolean use_extend; | |
10204 | unsigned short extend; | |
10205 | ||
10206 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10207 | op = mips16_immed_operands; | |
10208 | while (op->type != type) | |
10209 | ++op; | |
10210 | ||
10211 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10212 | { | |
10213 | small = false; | |
10214 | ext = true; | |
10215 | } | |
10216 | else | |
10217 | { | |
10218 | small = true; | |
10219 | ext = false; | |
10220 | } | |
10221 | ||
f74ba7a3 | 10222 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 10223 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10224 | if (op->pcrel) |
10225 | { | |
10226 | addressT addr; | |
10227 | ||
a677feeb ILT |
10228 | addr = fragp->fr_address + fragp->fr_fix; |
10229 | ||
10230 | /* The rules for the base address of a PC relative reloc are | |
10231 | complicated; see mips16_extended_frag. */ | |
10232 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10233 | { |
10234 | addr += 2; | |
319305a7 ILT |
10235 | if (ext) |
10236 | addr += 2; | |
fbcfacb7 ILT |
10237 | /* Ignore the low bit in the target, since it will be |
10238 | set for a text label. */ | |
10239 | if ((val & 1) != 0) | |
10240 | --val; | |
10241 | } | |
a677feeb ILT |
10242 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10243 | addr -= 4; | |
10244 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10245 | addr -= 2; | |
10246 | ||
cc5703cd ILT |
10247 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10248 | val -= addr; | |
a677feeb ILT |
10249 | |
10250 | /* Make sure the section winds up with the alignment we have | |
10251 | assumed. */ | |
10252 | if (op->shift > 0) | |
10253 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10254 | } |
10255 | ||
035936da ILT |
10256 | if (ext |
10257 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10258 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10259 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10260 | "extended instruction in delay slot"); | |
10261 | ||
cc5703cd ILT |
10262 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10263 | ||
b9129c6f ILT |
10264 | if (target_big_endian) |
10265 | insn = bfd_getb16 (buf); | |
10266 | else | |
10267 | insn = bfd_getl16 (buf); | |
cc5703cd | 10268 | |
31a2c6ff ILT |
10269 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10270 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10271 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10272 | |
10273 | if (use_extend) | |
10274 | { | |
10275 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10276 | fragp->fr_fix += 2; | |
10277 | buf += 2; | |
10278 | } | |
3d3c5039 | 10279 | |
cc5703cd ILT |
10280 | md_number_to_chars (buf, insn, 2); |
10281 | fragp->fr_fix += 2; | |
10282 | buf += 2; | |
10283 | } | |
10284 | else | |
10285 | { | |
10286 | if (fragp->fr_opcode == NULL) | |
10287 | return; | |
0dd2d296 | 10288 | |
cc5703cd ILT |
10289 | old = RELAX_OLD (fragp->fr_subtype); |
10290 | new = RELAX_NEW (fragp->fr_subtype); | |
10291 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10292 | |
cc5703cd ILT |
10293 | if (new > 0) |
10294 | memcpy (fixptr - old, fixptr, new); | |
10295 | ||
10296 | fragp->fr_fix += new - old; | |
10297 | } | |
0dd2d296 | 10298 | } |
becfe05e | 10299 | |
fbcfacb7 ILT |
10300 | #ifdef OBJ_ELF |
10301 | ||
10302 | /* This function is called after the relocs have been generated. | |
10303 | We've been storing mips16 text labels as odd. Here we convert them | |
10304 | back to even for the convenience of the debugger. */ | |
10305 | ||
10306 | void | |
10307 | mips_frob_file_after_relocs () | |
10308 | { | |
10309 | asymbol **syms; | |
10310 | unsigned int count, i; | |
10311 | ||
10312 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10313 | return; | |
10314 | ||
10315 | syms = bfd_get_outsymbols (stdoutput); | |
10316 | count = bfd_get_symcount (stdoutput); | |
10317 | for (i = 0; i < count; i++, syms++) | |
10318 | { | |
10319 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10320 | && ((*syms)->value & 1) != 0) | |
10321 | { | |
10322 | (*syms)->value &= ~1; | |
10323 | /* If the symbol has an odd size, it was probably computed | |
10324 | incorrectly, so adjust that as well. */ | |
10325 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10326 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10327 | } | |
10328 | } | |
10329 | } | |
10330 | ||
10331 | #endif | |
10332 | ||
becfe05e ILT |
10333 | /* This function is called whenever a label is defined. It is used |
10334 | when handling branch delays; if a branch has a label, we assume we | |
10335 | can not move it. */ | |
10336 | ||
10337 | void | |
10338 | mips_define_label (sym) | |
10339 | symbolS *sym; | |
10340 | { | |
fbcfacb7 ILT |
10341 | struct insn_label_list *l; |
10342 | ||
10343 | if (free_insn_labels == NULL) | |
10344 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10345 | else | |
10346 | { | |
10347 | l = free_insn_labels; | |
10348 | free_insn_labels = l->next; | |
10349 | } | |
10350 | ||
10351 | l->label = sym; | |
10352 | l->next = insn_labels; | |
10353 | insn_labels = l; | |
becfe05e | 10354 | } |
22ba90ce ILT |
10355 | |
10356 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
10357 | In order to work with gcc when using mips-tfile, we must keep all | |
10358 | local labels. However, in other cases, we want to discard them, | |
10359 | since they are useless. */ | |
10360 | ||
10361 | int | |
10362 | mips_local_label (name) | |
10363 | const char *name; | |
10364 | { | |
c625fc23 | 10365 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
10366 | if (ECOFF_DEBUGGING |
10367 | && mips_debug != 0 | |
10368 | && ! ecoff_debugging_seen) | |
10369 | { | |
10370 | /* We were called with -g, but we didn't see any debugging | |
10371 | information. That may mean that gcc is smuggling debugging | |
10372 | information through to mips-tfile, in which case we must | |
10373 | generate all local labels. */ | |
10374 | return 0; | |
10375 | } | |
c625fc23 | 10376 | #endif |
22ba90ce ILT |
10377 | |
10378 | /* Here it's OK to discard local labels. */ | |
10379 | ||
3af584b4 | 10380 | return name[0] == '$'; |
22ba90ce | 10381 | } |
3d3c5039 | 10382 | \f |
739708fa | 10383 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10384 | |
0dd2d296 | 10385 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10386 | |
10387 | void | |
10388 | mips_elf_final_processing () | |
10389 | { | |
87178180 ILT |
10390 | /* Write out the register information. */ |
10391 | if (! mips_64) | |
10392 | { | |
10393 | Elf32_RegInfo s; | |
10394 | ||
10395 | s.ri_gprmask = mips_gprmask; | |
10396 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10397 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10398 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10399 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10400 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10401 | ||
10402 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10403 | ((Elf32_External_RegInfo *) | |
10404 | mips_regmask_frag)); | |
10405 | } | |
10406 | else | |
10407 | { | |
10408 | Elf64_Internal_RegInfo s; | |
10409 | ||
10410 | s.ri_gprmask = mips_gprmask; | |
10411 | s.ri_pad = 0; | |
10412 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10413 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10414 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10415 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10416 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10417 | ||
10418 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10419 | ((Elf64_External_RegInfo *) | |
10420 | mips_regmask_frag)); | |
10421 | } | |
0dd2d296 ILT |
10422 | |
10423 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10424 | sort of BFD interface for this. */ | |
10425 | if (mips_any_noreorder) | |
10426 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10427 | if (mips_pic != NO_PIC) |
0dd2d296 | 10428 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10429 | } |
10430 | ||
739708fa | 10431 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10432 | \f |
3d3c5039 ILT |
10433 | /* These functions should really be defined by the object file format, |
10434 | since they are related to debugging information. However, this | |
10435 | code has to work for the a.out format, which does not define them, | |
10436 | so we provide simple versions here. These don't actually generate | |
10437 | any debugging information, but they do simple checking and someday | |
10438 | somebody may make them useful. */ | |
10439 | ||
670a50eb ILT |
10440 | typedef struct loc |
10441 | { | |
10442 | struct loc *loc_next; | |
10443 | unsigned long loc_fileno; | |
10444 | unsigned long loc_lineno; | |
10445 | unsigned long loc_offset; | |
10446 | unsigned short loc_delta; | |
10447 | unsigned short loc_count; | |
3d3c5039 | 10448 | #if 0 |
670a50eb | 10449 | fragS *loc_frag; |
3d3c5039 | 10450 | #endif |
670a50eb ILT |
10451 | } |
10452 | locS; | |
3d3c5039 | 10453 | |
670a50eb ILT |
10454 | typedef struct proc |
10455 | { | |
3d3c5039 ILT |
10456 | struct proc *proc_next; |
10457 | struct symbol *proc_isym; | |
10458 | struct symbol *proc_end; | |
10459 | unsigned long proc_reg_mask; | |
10460 | unsigned long proc_reg_offset; | |
10461 | unsigned long proc_fpreg_mask; | |
10462 | unsigned long proc_fpreg_offset; | |
10463 | unsigned long proc_frameoffset; | |
10464 | unsigned long proc_framereg; | |
10465 | unsigned long proc_pcreg; | |
10466 | locS *proc_iline; | |
10467 | struct file *proc_file; | |
10468 | int proc_index; | |
670a50eb ILT |
10469 | } |
10470 | procS; | |
3d3c5039 | 10471 | |
670a50eb ILT |
10472 | typedef struct file |
10473 | { | |
3d3c5039 ILT |
10474 | struct file *file_next; |
10475 | unsigned long file_fileno; | |
10476 | struct symbol *file_symbol; | |
10477 | struct symbol *file_end; | |
10478 | struct proc *file_proc; | |
10479 | int file_numprocs; | |
670a50eb ILT |
10480 | } |
10481 | fileS; | |
3d3c5039 ILT |
10482 | |
10483 | static struct obstack proc_frags; | |
10484 | static procS *proc_lastP; | |
10485 | static procS *proc_rootP; | |
10486 | static int numprocs; | |
10487 | ||
10488 | static void | |
10489 | md_obj_begin () | |
10490 | { | |
670a50eb | 10491 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10492 | } |
10493 | ||
10494 | static void | |
10495 | md_obj_end () | |
10496 | { | |
10497 | /* check for premature end, nesting errors, etc */ | |
10498 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10499 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10500 | } |
10501 | ||
3d3c5039 ILT |
10502 | static long |
10503 | get_number () | |
10504 | { | |
670a50eb ILT |
10505 | int negative = 0; |
10506 | long val = 0; | |
3d3c5039 | 10507 | |
670a50eb ILT |
10508 | if (*input_line_pointer == '-') |
10509 | { | |
10510 | ++input_line_pointer; | |
10511 | negative = 1; | |
3d3c5039 | 10512 | } |
670a50eb ILT |
10513 | if (!isdigit (*input_line_pointer)) |
10514 | as_bad ("Expected simple number."); | |
10515 | if (input_line_pointer[0] == '0') | |
10516 | { | |
10517 | if (input_line_pointer[1] == 'x') | |
10518 | { | |
10519 | input_line_pointer += 2; | |
10520 | while (isxdigit (*input_line_pointer)) | |
10521 | { | |
10522 | val <<= 4; | |
3a762a0b | 10523 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10524 | } |
670a50eb ILT |
10525 | return negative ? -val : val; |
10526 | } | |
10527 | else | |
10528 | { | |
10529 | ++input_line_pointer; | |
10530 | while (isdigit (*input_line_pointer)) | |
10531 | { | |
10532 | val <<= 3; | |
10533 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10534 | } |
670a50eb | 10535 | return negative ? -val : val; |
3d3c5039 ILT |
10536 | } |
10537 | } | |
670a50eb ILT |
10538 | if (!isdigit (*input_line_pointer)) |
10539 | { | |
10540 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10541 | *input_line_pointer, *input_line_pointer); | |
10542 | as_warn ("Invalid number"); | |
10543 | return -1; | |
3d3c5039 | 10544 | } |
670a50eb ILT |
10545 | while (isdigit (*input_line_pointer)) |
10546 | { | |
10547 | val *= 10; | |
10548 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10549 | } |
670a50eb | 10550 | return negative ? -val : val; |
3d3c5039 ILT |
10551 | } |
10552 | ||
10553 | /* The .file directive; just like the usual .file directive, but there | |
10554 | is an initial number which is the ECOFF file index. */ | |
10555 | ||
10556 | static void | |
10557 | s_file (x) | |
10558 | int x; | |
10559 | { | |
670a50eb | 10560 | int line; |
3d3c5039 | 10561 | |
670a50eb | 10562 | line = get_number (); |
9a7d824a | 10563 | s_app_file (0); |
3d3c5039 ILT |
10564 | } |
10565 | ||
10566 | ||
10567 | /* The .end directive. */ | |
10568 | ||
10569 | static void | |
10570 | s_mipsend (x) | |
10571 | int x; | |
10572 | { | |
670a50eb ILT |
10573 | symbolS *p; |
10574 | ||
10575 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10576 | { | |
10577 | p = get_symbol (); | |
10578 | demand_empty_rest_of_line (); | |
10579 | } | |
10580 | else | |
10581 | p = NULL; | |
10582 | if (now_seg != text_section) | |
10583 | as_warn (".end not in text section"); | |
10584 | if (!proc_lastP) | |
10585 | { | |
10586 | as_warn (".end and no .ent seen yet."); | |
10587 | return; | |
3d3c5039 ILT |
10588 | } |
10589 | ||
670a50eb ILT |
10590 | if (p != NULL) |
10591 | { | |
10592 | assert (S_GET_NAME (p)); | |
10593 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10594 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10595 | } |
10596 | ||
670a50eb | 10597 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10598 | } |
10599 | ||
10600 | /* The .aent and .ent directives. */ | |
10601 | ||
10602 | static void | |
10603 | s_ent (aent) | |
10604 | int aent; | |
10605 | { | |
670a50eb ILT |
10606 | int number = 0; |
10607 | procS *procP; | |
10608 | symbolS *symbolP; | |
10609 | ||
10610 | symbolP = get_symbol (); | |
10611 | if (*input_line_pointer == ',') | |
10612 | input_line_pointer++; | |
dd3f1f76 | 10613 | SKIP_WHITESPACE (); |
670a50eb ILT |
10614 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10615 | number = get_number (); | |
10616 | if (now_seg != text_section) | |
10617 | as_warn (".ent or .aent not in text section."); | |
10618 | ||
10619 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10620 | as_warn ("missing `.end'"); | |
10621 | ||
10622 | if (!aent) | |
10623 | { | |
10624 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10625 | procP->proc_isym = symbolP; | |
10626 | procP->proc_reg_mask = 0; | |
10627 | procP->proc_reg_offset = 0; | |
10628 | procP->proc_fpreg_mask = 0; | |
10629 | procP->proc_fpreg_offset = 0; | |
10630 | procP->proc_frameoffset = 0; | |
10631 | procP->proc_framereg = 0; | |
10632 | procP->proc_pcreg = 0; | |
10633 | procP->proc_end = NULL; | |
10634 | procP->proc_next = NULL; | |
10635 | if (proc_lastP) | |
10636 | proc_lastP->proc_next = procP; | |
10637 | else | |
10638 | proc_rootP = procP; | |
10639 | proc_lastP = procP; | |
10640 | numprocs++; | |
3d3c5039 | 10641 | } |
670a50eb | 10642 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10643 | } |
10644 | ||
10645 | /* The .frame directive. */ | |
10646 | ||
88225433 | 10647 | #if 0 |
3d3c5039 ILT |
10648 | static void |
10649 | s_frame (x) | |
670a50eb | 10650 | int x; |
3d3c5039 | 10651 | { |
670a50eb ILT |
10652 | char str[100]; |
10653 | symbolS *symP; | |
10654 | int frame_reg; | |
10655 | int frame_off; | |
10656 | int pcreg; | |
10657 | ||
0dd2d296 | 10658 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10659 | if (*input_line_pointer == ',') |
10660 | input_line_pointer++; | |
5ac34ac3 | 10661 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10662 | if (*input_line_pointer == ',') |
10663 | input_line_pointer++; | |
0dd2d296 | 10664 | pcreg = tc_get_register (0); |
670a50eb ILT |
10665 | |
10666 | /* bob third eye */ | |
10667 | assert (proc_rootP); | |
10668 | proc_rootP->proc_framereg = frame_reg; | |
10669 | proc_rootP->proc_frameoffset = frame_off; | |
10670 | proc_rootP->proc_pcreg = pcreg; | |
10671 | /* bob macho .frame */ | |
10672 | ||
10673 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10674 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10675 | { |
10676 | if (!proc_lastP) | |
10677 | as_warn ("No .ent for .frame to use."); | |
10678 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10679 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10680 | S_SET_TYPE (symP, N_RMASK); | |
10681 | S_SET_OTHER (symP, 0); | |
10682 | S_SET_DESC (symP, 0); | |
10683 | symP->sy_forward = proc_lastP->proc_isym; | |
10684 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10685 | } |
670a50eb | 10686 | demand_empty_rest_of_line (); |
3d3c5039 | 10687 | } |
88225433 | 10688 | #endif |
3d3c5039 ILT |
10689 | |
10690 | /* The .fmask and .mask directives. */ | |
10691 | ||
88225433 | 10692 | #if 0 |
3d3c5039 ILT |
10693 | static void |
10694 | s_mask (reg_type) | |
10695 | char reg_type; | |
10696 | { | |
670a50eb ILT |
10697 | char str[100], *strP; |
10698 | symbolS *symP; | |
10699 | int i; | |
10700 | unsigned int mask; | |
10701 | int off; | |
10702 | ||
10703 | mask = get_number (); | |
10704 | if (*input_line_pointer == ',') | |
10705 | input_line_pointer++; | |
10706 | off = get_absolute_expression (); | |
10707 | ||
10708 | /* bob only for coff */ | |
10709 | assert (proc_rootP); | |
10710 | if (reg_type == 'F') | |
10711 | { | |
10712 | proc_rootP->proc_fpreg_mask = mask; | |
10713 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10714 | } |
670a50eb ILT |
10715 | else |
10716 | { | |
10717 | proc_rootP->proc_reg_mask = mask; | |
10718 | proc_rootP->proc_reg_offset = off; | |
10719 | } | |
10720 | ||
10721 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10722 | |
670a50eb ILT |
10723 | /* We don't have to write out a mask stab if no saved regs. */ |
10724 | if (!(mask == 0)) | |
10725 | { | |
10726 | if (!proc_lastP) | |
10727 | as_warn ("No .ent for .mask to use."); | |
10728 | strP = str; | |
10729 | for (i = 0; i < 32; i++) | |
10730 | { | |
10731 | if (mask % 2) | |
10732 | { | |
10733 | sprintf (strP, "%c%d,", reg_type, i); | |
10734 | strP += strlen (strP); | |
10735 | } | |
3d3c5039 | 10736 | mask /= 2; |
670a50eb ILT |
10737 | } |
10738 | sprintf (strP, ";%d,", off); | |
10739 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10740 | S_SET_TYPE (symP, N_RMASK); | |
10741 | S_SET_OTHER (symP, 0); | |
10742 | S_SET_DESC (symP, 0); | |
10743 | symP->sy_forward = proc_lastP->proc_isym; | |
10744 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10745 | } |
3d3c5039 | 10746 | } |
88225433 | 10747 | #endif |
3d3c5039 ILT |
10748 | |
10749 | /* The .loc directive. */ | |
10750 | ||
88225433 | 10751 | #if 0 |
3d3c5039 ILT |
10752 | static void |
10753 | s_loc (x) | |
10754 | int x; | |
10755 | { | |
670a50eb ILT |
10756 | symbolS *symbolP; |
10757 | int lineno; | |
10758 | int addroff; | |
3d3c5039 | 10759 | |
670a50eb | 10760 | assert (now_seg == text_section); |
3d3c5039 | 10761 | |
670a50eb | 10762 | lineno = get_number (); |
87e48495 | 10763 | addroff = frag_now_fix (); |
3d3c5039 | 10764 | |
670a50eb ILT |
10765 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10766 | S_SET_TYPE (symbolP, N_SLINE); | |
10767 | S_SET_OTHER (symbolP, 0); | |
10768 | S_SET_DESC (symbolP, lineno); | |
10769 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10770 | } |
88225433 | 10771 | #endif |