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2469cfa2 NC |
1 | /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430 |
2 | ||
13761a11 | 3 | Copyright (C) 2002-2013 Free Software Foundation, Inc. |
2469cfa2 NC |
4 | Contributed by Dmitry Diky <diwil@mail.ru> |
5 | ||
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
2469cfa2 NC |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
2469cfa2 | 22 | |
df7b86aa | 23 | #include "as.h" |
2469cfa2 | 24 | #include <limits.h> |
2469cfa2 | 25 | #define PUSH_1X_WORKAROUND |
2469cfa2 NC |
26 | #include "subsegs.h" |
27 | #include "opcode/msp430.h" | |
28 | #include "safe-ctype.h" | |
2a9a06c1 | 29 | #include "dwarf2dbg.h" |
13761a11 | 30 | #include "elf/msp430.h" |
2469cfa2 | 31 | |
79cf5950 | 32 | /* We will disable polymorphs by default because it is dangerous. |
708587a4 | 33 | The potential problem here is the following: assume we got the |
77592908 DD |
34 | following code: |
35 | ||
36 | jump .l1 | |
37 | nop | |
38 | jump subroutine ; external symbol | |
39 | .l1: | |
40 | nop | |
41 | ret | |
13761a11 | 42 | |
77592908 DD |
43 | In case of assembly time relaxation we'll get: |
44 | 0: jmp .l1 <.text +0x08> (reloc deleted) | |
45 | 2: nop | |
46 | 4: br subroutine | |
47 | .l1: | |
48 | 8: nop | |
49 | 10: ret | |
50 | ||
79cf5950 NC |
51 | If the 'subroutine' is within +-1024 bytes range then linker |
52 | will produce: | |
77592908 DD |
53 | 0: jmp .text +0x08 |
54 | 2: nop | |
55 | 4: jmp subroutine | |
56 | .l1: | |
57 | 6: nop | |
58 | 8: ret ; 'jmp .text +0x08' will land here. WRONG!!! | |
59 | ||
77592908 | 60 | The workaround is the following: |
79cf5950 | 61 | 1. Declare global var enable_polymorphs which set to 1 via option -mp. |
77592908 DD |
62 | 2. Declare global var enable_relax which set to 1 via option -mQ. |
63 | ||
64 | If polymorphs are enabled, and relax isn't, treat all jumps as long jumps, | |
65 | do not delete any relocs and leave them for linker. | |
13761a11 | 66 | |
79cf5950 | 67 | If relax is enabled, relax at assembly time and kill relocs as necessary. */ |
77592908 DD |
68 | |
69 | int msp430_enable_relax; | |
70 | int msp430_enable_polys; | |
71 | ||
13761a11 NC |
72 | /* Set linkrelax here to avoid fixups in most sections. */ |
73 | int linkrelax = 1; | |
74 | ||
f5c7edf4 AM |
75 | /* GCC uses the some condition codes which we'll |
76 | implement as new polymorph instructions. | |
13761a11 | 77 | |
f5c7edf4 AM |
78 | COND EXPL SHORT JUMP LONG JUMP |
79 | =============================================== | |
80 | eq == jeq jne +4; br lab | |
81 | ne != jne jeq +4; br lab | |
82 | ||
83 | ltn honours no-overflow flag | |
84 | ltn < jn jn +2; jmp +4; br lab | |
85 | ||
13761a11 | 86 | lt < jl jge +4; br lab |
f5c7edf4 AM |
87 | ltu < jlo lhs +4; br lab |
88 | le <= see below | |
89 | leu <= see below | |
90 | ||
91 | gt > see below | |
92 | gtu > see below | |
93 | ge >= jge jl +4; br lab | |
94 | geu >= jhs jlo +4; br lab | |
95 | =============================================== | |
96 | ||
97 | Therefore, new opcodes are (BranchEQ -> beq; and so on...) | |
98 | beq,bne,blt,bltn,bltu,bge,bgeu | |
13761a11 NC |
99 | 'u' means unsigned compares |
100 | ||
f5c7edf4 AM |
101 | Also, we add 'jump' instruction: |
102 | jump UNCOND -> jmp br lab | |
103 | ||
104 | They will have fmt == 4, and insn_opnumb == number of instruction. */ | |
105 | ||
13761a11 | 106 | struct rcodes_s |
f5c7edf4 AM |
107 | { |
108 | char * name; | |
109 | int index; /* Corresponding insn_opnumb. */ | |
110 | int sop; /* Opcode if jump length is short. */ | |
111 | long lpos; /* Label position. */ | |
112 | long lop0; /* Opcode 1 _word_ (16 bits). */ | |
113 | long lop1; /* Opcode second word. */ | |
114 | long lop2; /* Opcode third word. */ | |
115 | }; | |
116 | ||
117 | #define MSP430_RLC(n,i,sop,o1) \ | |
118 | {#n, i, sop, 2, (o1 + 2), 0x4010, 0} | |
119 | ||
13761a11 | 120 | static struct rcodes_s msp430_rcodes[] = |
f5c7edf4 AM |
121 | { |
122 | MSP430_RLC (beq, 0, 0x2400, 0x2000), | |
123 | MSP430_RLC (bne, 1, 0x2000, 0x2400), | |
124 | MSP430_RLC (blt, 2, 0x3800, 0x3400), | |
125 | MSP430_RLC (bltu, 3, 0x2800, 0x2c00), | |
126 | MSP430_RLC (bge, 4, 0x3400, 0x3800), | |
127 | MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), | |
128 | {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010}, | |
129 | {"jump", 7, 0x3c00, 1, 0x4010, 0, 0}, | |
130 | {0,0,0,0,0,0,0} | |
131 | }; | |
f5c7edf4 | 132 | |
13761a11 NC |
133 | #undef MSP430_RLC |
134 | #define MSP430_RLC(n,i,sop,o1) \ | |
135 | {#n, i, sop, 2, (o1 + 2), 0x0030, 0} | |
136 | ||
137 | static struct rcodes_s msp430x_rcodes[] = | |
138 | { | |
139 | MSP430_RLC (beq, 0, 0x2400, 0x2000), | |
140 | MSP430_RLC (bne, 1, 0x2000, 0x2400), | |
141 | MSP430_RLC (blt, 2, 0x3800, 0x3400), | |
142 | MSP430_RLC (bltu, 3, 0x2800, 0x2c00), | |
143 | MSP430_RLC (bge, 4, 0x3400, 0x3800), | |
144 | MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), | |
145 | {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000}, | |
146 | {"jump", 7, 0x3c00, 1, 0x0030, 0, 0}, | |
147 | {0,0,0,0,0,0,0} | |
148 | }; | |
149 | #undef MSP430_RLC | |
f5c7edf4 AM |
150 | |
151 | /* More difficult than above and they have format 5. | |
13761a11 | 152 | |
f5c7edf4 AM |
153 | COND EXPL SHORT LONG |
154 | ================================================================= | |
155 | gt > jeq +2; jge label jeq +6; jl +4; br label | |
156 | gtu > jeq +2; jhs label jeq +6; jlo +4; br label | |
157 | leu <= jeq label; jlo label jeq +2; jhs +4; br label | |
158 | le <= jeq label; jl label jeq +2; jge +4; br label | |
159 | ================================================================= */ | |
160 | ||
13761a11 | 161 | struct hcodes_s |
f5c7edf4 | 162 | { |
13761a11 | 163 | char * name; |
f5c7edf4 AM |
164 | int index; /* Corresponding insn_opnumb. */ |
165 | int tlab; /* Number of labels in short mode. */ | |
166 | int op0; /* Opcode for first word of short jump. */ | |
167 | int op1; /* Opcode for second word of short jump. */ | |
168 | int lop0; /* Opcodes for long jump mode. */ | |
169 | int lop1; | |
170 | int lop2; | |
171 | }; | |
172 | ||
13761a11 | 173 | static struct hcodes_s msp430_hcodes[] = |
f5c7edf4 AM |
174 | { |
175 | {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 }, | |
176 | {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 }, | |
177 | {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 }, | |
178 | {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 }, | |
179 | {0,0,0,0,0,0,0,0} | |
180 | }; | |
181 | ||
13761a11 NC |
182 | static struct hcodes_s msp430x_hcodes[] = |
183 | { | |
184 | {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 }, | |
185 | {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 }, | |
186 | {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 }, | |
187 | {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 }, | |
188 | {0,0,0,0,0,0,0,0} | |
189 | }; | |
190 | ||
2469cfa2 NC |
191 | const char comment_chars[] = ";"; |
192 | const char line_comment_chars[] = "#"; | |
870074dd | 193 | const char line_separator_chars[] = "{"; |
2469cfa2 NC |
194 | const char EXP_CHARS[] = "eE"; |
195 | const char FLT_CHARS[] = "dD"; | |
196 | ||
197 | /* Handle long expressions. */ | |
198 | extern LITTLENUM_TYPE generic_bignum[]; | |
199 | ||
200 | static struct hash_control *msp430_hash; | |
201 | ||
b18c562e NC |
202 | /* Relaxations. */ |
203 | #define STATE_UNCOND_BRANCH 1 /* jump */ | |
204 | #define STATE_NOOV_BRANCH 3 /* bltn */ | |
205 | #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */ | |
206 | #define STATE_EMUL_BRANCH 4 | |
207 | ||
208 | #define CNRL 2 | |
209 | #define CUBL 4 | |
210 | #define CNOL 8 | |
211 | #define CSBL 6 | |
212 | #define CEBL 4 | |
213 | ||
214 | /* Length. */ | |
215 | #define STATE_BITS10 1 /* wild guess. short jump */ | |
216 | #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */ | |
217 | #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */ | |
218 | ||
219 | #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) | |
220 | #define RELAX_STATE(s) ((s) & 3) | |
221 | #define RELAX_LEN(s) ((s) >> 2) | |
222 | #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1) | |
223 | ||
224 | relax_typeS md_relax_table[] = | |
225 | { | |
226 | /* Unused. */ | |
227 | {1, 1, 0, 0}, | |
228 | {1, 1, 0, 0}, | |
229 | {1, 1, 0, 0}, | |
230 | {1, 1, 0, 0}, | |
231 | ||
232 | /* Unconditional jump. */ | |
233 | {1, 1, 8, 5}, | |
234 | {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
235 | {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */ | |
236 | {1, 1, CUBL, 0}, /* state undef */ | |
237 | ||
238 | /* Simple branches. */ | |
239 | {0, 0, 8, 9}, | |
240 | {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
241 | {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */ | |
242 | {1, 1, CSBL, 0}, | |
243 | ||
244 | /* blt no overflow branch. */ | |
245 | {1, 1, 8, 13}, | |
246 | {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
247 | {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */ | |
248 | {1, 1, CNOL, 0}, | |
249 | ||
250 | /* Emulated branches. */ | |
251 | {1, 1, 8, 17}, | |
252 | {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
253 | {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */ | |
254 | {1, 1, CNOL, 0} | |
255 | }; | |
256 | ||
2469cfa2 | 257 | |
8cd5b113 | 258 | #define MAX_OP_LEN 256 |
2469cfa2 | 259 | |
638d3803 NC |
260 | typedef enum msp_isa |
261 | { | |
262 | MSP_ISA_430, | |
263 | MSP_ISA_430X, | |
264 | MSP_ISA_430Xv2 | |
265 | } msp_isa; | |
266 | ||
2469cfa2 NC |
267 | struct mcu_type_s |
268 | { | |
638d3803 NC |
269 | char * name; |
270 | msp_isa isa; | |
2469cfa2 NC |
271 | }; |
272 | ||
638d3803 NC |
273 | static struct mcu_type_s mcu_types[] = |
274 | { | |
275 | {"msp430afe221", MSP_ISA_430}, | |
276 | {"msp430afe222", MSP_ISA_430}, | |
277 | {"msp430afe223", MSP_ISA_430}, | |
278 | {"msp430afe231", MSP_ISA_430}, | |
279 | {"msp430afe232", MSP_ISA_430}, | |
280 | {"msp430afe233", MSP_ISA_430}, | |
281 | {"msp430afe251", MSP_ISA_430}, | |
282 | {"msp430afe252", MSP_ISA_430}, | |
283 | {"msp430afe253", MSP_ISA_430}, | |
284 | {"msp430c091", MSP_ISA_430}, | |
285 | {"msp430c092", MSP_ISA_430}, | |
286 | {"msp430c111", MSP_ISA_430}, | |
287 | {"msp430c1111", MSP_ISA_430}, | |
288 | {"msp430c112", MSP_ISA_430}, | |
289 | {"msp430c1121", MSP_ISA_430}, | |
290 | {"msp430e112", MSP_ISA_430}, | |
291 | {"msp430c1331", MSP_ISA_430}, | |
292 | {"msp430c1351", MSP_ISA_430}, | |
293 | {"msp430c311s", MSP_ISA_430}, | |
294 | {"msp430c312", MSP_ISA_430}, | |
295 | {"msp430c313", MSP_ISA_430}, | |
296 | {"msp430c314", MSP_ISA_430}, | |
297 | {"msp430c315", MSP_ISA_430}, | |
298 | {"msp430c323", MSP_ISA_430}, | |
299 | {"msp430c325", MSP_ISA_430}, | |
300 | {"msp430c336", MSP_ISA_430}, | |
301 | {"msp430c337", MSP_ISA_430}, | |
302 | {"msp430c412", MSP_ISA_430}, | |
303 | {"msp430c413", MSP_ISA_430}, | |
304 | {"msp430e313", MSP_ISA_430}, | |
305 | {"msp430e315", MSP_ISA_430}, | |
306 | {"msp430e325", MSP_ISA_430}, | |
307 | {"msp430e337", MSP_ISA_430}, | |
308 | {"msp430f110", MSP_ISA_430}, | |
309 | {"msp430f1101", MSP_ISA_430}, | |
310 | {"msp430f1101a", MSP_ISA_430}, | |
311 | {"msp430f1111", MSP_ISA_430}, | |
312 | {"msp430f1111a", MSP_ISA_430}, | |
313 | {"msp430f112", MSP_ISA_430}, | |
314 | {"msp430f1121", MSP_ISA_430}, | |
315 | {"msp430f1121a", MSP_ISA_430}, | |
316 | {"msp430f1122", MSP_ISA_430}, | |
317 | {"msp430f1132", MSP_ISA_430}, | |
318 | {"msp430f122", MSP_ISA_430}, | |
319 | {"msp430f1222", MSP_ISA_430}, | |
320 | {"msp430f123", MSP_ISA_430}, | |
321 | {"msp430f1232", MSP_ISA_430}, | |
322 | {"msp430f133", MSP_ISA_430}, | |
323 | {"msp430f135", MSP_ISA_430}, | |
324 | {"msp430f147", MSP_ISA_430}, | |
325 | {"msp430f1471", MSP_ISA_430}, | |
326 | {"msp430f148", MSP_ISA_430}, | |
327 | {"msp430f1481", MSP_ISA_430}, | |
328 | {"msp430f149", MSP_ISA_430}, | |
329 | {"msp430f1491", MSP_ISA_430}, | |
330 | {"msp430f155", MSP_ISA_430}, | |
331 | {"msp430f156", MSP_ISA_430}, | |
332 | {"msp430f157", MSP_ISA_430}, | |
333 | {"msp430f1610", MSP_ISA_430}, | |
334 | {"msp430f1611", MSP_ISA_430}, | |
335 | {"msp430f1612", MSP_ISA_430}, | |
336 | {"msp430f167", MSP_ISA_430}, | |
337 | {"msp430f168", MSP_ISA_430}, | |
338 | {"msp430f169", MSP_ISA_430}, | |
339 | {"msp430f2001", MSP_ISA_430}, | |
340 | {"msp430f2002", MSP_ISA_430}, | |
341 | {"msp430f2003", MSP_ISA_430}, | |
342 | {"msp430f2011", MSP_ISA_430}, | |
343 | {"msp430f2012", MSP_ISA_430}, | |
344 | {"msp430f2013", MSP_ISA_430}, | |
345 | {"msp430f2101", MSP_ISA_430}, | |
346 | {"msp430f2111", MSP_ISA_430}, | |
347 | {"msp430f2112", MSP_ISA_430}, | |
348 | {"msp430f2121", MSP_ISA_430}, | |
349 | {"msp430f2122", MSP_ISA_430}, | |
350 | {"msp430f2131", MSP_ISA_430}, | |
351 | {"msp430f2132", MSP_ISA_430}, | |
352 | {"msp430f2232", MSP_ISA_430}, | |
353 | {"msp430f2234", MSP_ISA_430}, | |
354 | {"msp430f2252", MSP_ISA_430}, | |
355 | {"msp430f2254", MSP_ISA_430}, | |
356 | {"msp430f2272", MSP_ISA_430}, | |
357 | {"msp430f2274", MSP_ISA_430}, | |
358 | {"msp430f233", MSP_ISA_430}, | |
359 | {"msp430f2330", MSP_ISA_430}, | |
360 | {"msp430f235", MSP_ISA_430}, | |
361 | {"msp430f2350", MSP_ISA_430}, | |
362 | {"msp430f2370", MSP_ISA_430}, | |
363 | {"msp430f2410", MSP_ISA_430}, | |
364 | {"msp430f247", MSP_ISA_430}, | |
365 | {"msp430f2471", MSP_ISA_430}, | |
366 | {"msp430f248", MSP_ISA_430}, | |
367 | {"msp430f2481", MSP_ISA_430}, | |
368 | {"msp430f249", MSP_ISA_430}, | |
369 | {"msp430f2491", MSP_ISA_430}, | |
370 | {"msp430f412", MSP_ISA_430}, | |
371 | {"msp430f413", MSP_ISA_430}, | |
372 | {"msp430f4132", MSP_ISA_430}, | |
373 | {"msp430f415", MSP_ISA_430}, | |
374 | {"msp430f4152", MSP_ISA_430}, | |
375 | {"msp430f417", MSP_ISA_430}, | |
376 | {"msp430f423", MSP_ISA_430}, | |
377 | {"msp430f423a", MSP_ISA_430}, | |
378 | {"msp430f425", MSP_ISA_430}, | |
379 | {"msp430f4250", MSP_ISA_430}, | |
380 | {"msp430f425a", MSP_ISA_430}, | |
381 | {"msp430f4260", MSP_ISA_430}, | |
382 | {"msp430f427", MSP_ISA_430}, | |
383 | {"msp430f4270", MSP_ISA_430}, | |
384 | {"msp430f427a", MSP_ISA_430}, | |
385 | {"msp430f435", MSP_ISA_430}, | |
386 | {"msp430f4351", MSP_ISA_430}, | |
387 | {"msp430f436", MSP_ISA_430}, | |
388 | {"msp430f4361", MSP_ISA_430}, | |
389 | {"msp430f437", MSP_ISA_430}, | |
390 | {"msp430f4371", MSP_ISA_430}, | |
391 | {"msp430f438", MSP_ISA_430}, | |
392 | {"msp430f439", MSP_ISA_430}, | |
393 | {"msp430f447", MSP_ISA_430}, | |
394 | {"msp430f448", MSP_ISA_430}, | |
395 | {"msp430f4481", MSP_ISA_430}, | |
396 | {"msp430f449", MSP_ISA_430}, | |
397 | {"msp430f4491", MSP_ISA_430}, | |
398 | {"msp430f477", MSP_ISA_430}, | |
399 | {"msp430f478", MSP_ISA_430}, | |
400 | {"msp430f4783", MSP_ISA_430}, | |
401 | {"msp430f4784", MSP_ISA_430}, | |
402 | {"msp430f479", MSP_ISA_430}, | |
403 | {"msp430f4793", MSP_ISA_430}, | |
404 | {"msp430f4794", MSP_ISA_430}, | |
405 | {"msp430fe423", MSP_ISA_430}, | |
406 | {"msp430fe4232", MSP_ISA_430}, | |
407 | {"msp430fe423a", MSP_ISA_430}, | |
408 | {"msp430fe4242", MSP_ISA_430}, | |
409 | {"msp430fe425", MSP_ISA_430}, | |
410 | {"msp430fe4252", MSP_ISA_430}, | |
411 | {"msp430fe425a", MSP_ISA_430}, | |
412 | {"msp430fe427", MSP_ISA_430}, | |
413 | {"msp430fe4272", MSP_ISA_430}, | |
414 | {"msp430fe427a", MSP_ISA_430}, | |
415 | {"msp430fg4250", MSP_ISA_430}, | |
416 | {"msp430fg4260", MSP_ISA_430}, | |
417 | {"msp430fg4270", MSP_ISA_430}, | |
418 | {"msp430fg437", MSP_ISA_430}, | |
419 | {"msp430fg438", MSP_ISA_430}, | |
420 | {"msp430fg439", MSP_ISA_430}, | |
421 | {"msp430fg477", MSP_ISA_430}, | |
422 | {"msp430fg478", MSP_ISA_430}, | |
423 | {"msp430fg479", MSP_ISA_430}, | |
424 | {"msp430fw423", MSP_ISA_430}, | |
425 | {"msp430fw425", MSP_ISA_430}, | |
426 | {"msp430fw427", MSP_ISA_430}, | |
427 | {"msp430fw428", MSP_ISA_430}, | |
428 | {"msp430fw429", MSP_ISA_430}, | |
429 | {"msp430g2001", MSP_ISA_430}, | |
430 | {"msp430g2101", MSP_ISA_430}, | |
431 | {"msp430g2102", MSP_ISA_430}, | |
432 | {"msp430g2111", MSP_ISA_430}, | |
433 | {"msp430g2112", MSP_ISA_430}, | |
434 | {"msp430g2113", MSP_ISA_430}, | |
435 | {"msp430g2121", MSP_ISA_430}, | |
436 | {"msp430g2131", MSP_ISA_430}, | |
437 | {"msp430g2132", MSP_ISA_430}, | |
438 | {"msp430g2152", MSP_ISA_430}, | |
439 | {"msp430g2153", MSP_ISA_430}, | |
440 | {"msp430g2201", MSP_ISA_430}, | |
441 | {"msp430g2202", MSP_ISA_430}, | |
442 | {"msp430g2203", MSP_ISA_430}, | |
443 | {"msp430g2210", MSP_ISA_430}, | |
444 | {"msp430g2211", MSP_ISA_430}, | |
445 | {"msp430g2212", MSP_ISA_430}, | |
446 | {"msp430g2213", MSP_ISA_430}, | |
447 | {"msp430g2221", MSP_ISA_430}, | |
448 | {"msp430g2230", MSP_ISA_430}, | |
449 | {"msp430g2231", MSP_ISA_430}, | |
450 | {"msp430g2232", MSP_ISA_430}, | |
451 | {"msp430g2233", MSP_ISA_430}, | |
452 | {"msp430g2252", MSP_ISA_430}, | |
453 | {"msp430g2253", MSP_ISA_430}, | |
454 | {"msp430g2302", MSP_ISA_430}, | |
455 | {"msp430g2303", MSP_ISA_430}, | |
456 | {"msp430g2312", MSP_ISA_430}, | |
457 | {"msp430g2313", MSP_ISA_430}, | |
458 | {"msp430g2332", MSP_ISA_430}, | |
459 | {"msp430g2333", MSP_ISA_430}, | |
460 | {"msp430g2352", MSP_ISA_430}, | |
461 | {"msp430g2353", MSP_ISA_430}, | |
462 | {"msp430g2402", MSP_ISA_430}, | |
463 | {"msp430g2403", MSP_ISA_430}, | |
464 | {"msp430g2412", MSP_ISA_430}, | |
465 | {"msp430g2413", MSP_ISA_430}, | |
466 | {"msp430g2432", MSP_ISA_430}, | |
467 | {"msp430g2433", MSP_ISA_430}, | |
468 | {"msp430g2444", MSP_ISA_430}, | |
469 | {"msp430g2452", MSP_ISA_430}, | |
470 | {"msp430g2453", MSP_ISA_430}, | |
471 | {"msp430g2513", MSP_ISA_430}, | |
472 | {"msp430g2533", MSP_ISA_430}, | |
473 | {"msp430g2544", MSP_ISA_430}, | |
474 | {"msp430g2553", MSP_ISA_430}, | |
475 | {"msp430g2744", MSP_ISA_430}, | |
476 | {"msp430g2755", MSP_ISA_430}, | |
477 | {"msp430g2855", MSP_ISA_430}, | |
478 | {"msp430g2955", MSP_ISA_430}, | |
479 | {"msp430l092", MSP_ISA_430}, | |
480 | {"msp430p112", MSP_ISA_430}, | |
481 | {"msp430p313", MSP_ISA_430}, | |
482 | {"msp430p315", MSP_ISA_430}, | |
483 | {"msp430p315s", MSP_ISA_430}, | |
484 | {"msp430p325", MSP_ISA_430}, | |
485 | {"msp430p337", MSP_ISA_430}, | |
486 | {"msp430tch5e", MSP_ISA_430}, | |
487 | ||
488 | {"msp430cg4616", MSP_ISA_430X}, | |
489 | {"msp430cg4617", MSP_ISA_430X}, | |
490 | {"msp430cg4618", MSP_ISA_430X}, | |
491 | {"msp430cg4619", MSP_ISA_430X}, | |
492 | {"msp430f2416", MSP_ISA_430X}, | |
493 | {"msp430f2417", MSP_ISA_430X}, | |
494 | {"msp430f2418", MSP_ISA_430X}, | |
495 | {"msp430f2419", MSP_ISA_430X}, | |
496 | {"msp430f2616", MSP_ISA_430X}, | |
497 | {"msp430f2617", MSP_ISA_430X}, | |
498 | {"msp430f2618", MSP_ISA_430X}, | |
499 | {"msp430f2619", MSP_ISA_430X}, | |
500 | {"msp430f47126", MSP_ISA_430X}, | |
501 | {"msp430f47127", MSP_ISA_430X}, | |
502 | {"msp430f47163", MSP_ISA_430X}, | |
503 | {"msp430f47173", MSP_ISA_430X}, | |
504 | {"msp430f47183", MSP_ISA_430X}, | |
505 | {"msp430f47193", MSP_ISA_430X}, | |
506 | {"msp430f47166", MSP_ISA_430X}, | |
507 | {"msp430f47176", MSP_ISA_430X}, | |
508 | {"msp430f47186", MSP_ISA_430X}, | |
509 | {"msp430f47196", MSP_ISA_430X}, | |
510 | {"msp430f47167", MSP_ISA_430X}, | |
511 | {"msp430f47177", MSP_ISA_430X}, | |
512 | {"msp430f47187", MSP_ISA_430X}, | |
513 | {"msp430f47197", MSP_ISA_430X}, | |
514 | {"msp430f46161", MSP_ISA_430X}, | |
515 | {"msp430f46171", MSP_ISA_430X}, | |
516 | {"msp430f46181", MSP_ISA_430X}, | |
517 | {"msp430f46191", MSP_ISA_430X}, | |
518 | {"msp430f4616", MSP_ISA_430X}, | |
519 | {"msp430f4617", MSP_ISA_430X}, | |
520 | {"msp430f4618", MSP_ISA_430X}, | |
521 | {"msp430f4619", MSP_ISA_430X}, | |
522 | {"msp430fg4616", MSP_ISA_430X}, | |
523 | {"msp430fg4617", MSP_ISA_430X}, | |
524 | {"msp430fg4618", MSP_ISA_430X}, | |
525 | {"msp430fg4619", MSP_ISA_430X}, | |
526 | ||
527 | {"msp430f5418", MSP_ISA_430Xv2}, | |
528 | {"msp430f5419", MSP_ISA_430Xv2}, | |
529 | {"msp430f5435", MSP_ISA_430Xv2}, | |
530 | {"msp430f5436", MSP_ISA_430Xv2}, | |
531 | {"msp430f5437", MSP_ISA_430Xv2}, | |
532 | {"msp430f5438", MSP_ISA_430Xv2}, | |
533 | {"msp430f5418a", MSP_ISA_430Xv2}, | |
534 | {"msp430f5419a", MSP_ISA_430Xv2}, | |
535 | {"msp430f5435a", MSP_ISA_430Xv2}, | |
536 | {"msp430f5436a", MSP_ISA_430Xv2}, | |
537 | {"msp430f5437a", MSP_ISA_430Xv2}, | |
538 | {"msp430f5438a", MSP_ISA_430Xv2}, | |
539 | {"msp430f5212", MSP_ISA_430Xv2}, | |
540 | {"msp430f5213", MSP_ISA_430Xv2}, | |
541 | {"msp430f5214", MSP_ISA_430Xv2}, | |
542 | {"msp430f5217", MSP_ISA_430Xv2}, | |
543 | {"msp430f5218", MSP_ISA_430Xv2}, | |
544 | {"msp430f5219", MSP_ISA_430Xv2}, | |
545 | {"msp430f5222", MSP_ISA_430Xv2}, | |
546 | {"msp430f5223", MSP_ISA_430Xv2}, | |
547 | {"msp430f5224", MSP_ISA_430Xv2}, | |
548 | {"msp430f5227", MSP_ISA_430Xv2}, | |
549 | {"msp430f5228", MSP_ISA_430Xv2}, | |
550 | {"msp430f5229", MSP_ISA_430Xv2}, | |
551 | {"msp430f5304", MSP_ISA_430Xv2}, | |
552 | {"msp430f5308", MSP_ISA_430Xv2}, | |
553 | {"msp430f5309", MSP_ISA_430Xv2}, | |
554 | {"msp430f5310", MSP_ISA_430Xv2}, | |
555 | {"msp430f5340", MSP_ISA_430Xv2}, | |
556 | {"msp430f5341", MSP_ISA_430Xv2}, | |
557 | {"msp430f5342", MSP_ISA_430Xv2}, | |
558 | {"msp430f5324", MSP_ISA_430Xv2}, | |
559 | {"msp430f5325", MSP_ISA_430Xv2}, | |
560 | {"msp430f5326", MSP_ISA_430Xv2}, | |
561 | {"msp430f5327", MSP_ISA_430Xv2}, | |
562 | {"msp430f5328", MSP_ISA_430Xv2}, | |
563 | {"msp430f5329", MSP_ISA_430Xv2}, | |
564 | {"msp430f5500", MSP_ISA_430Xv2}, | |
565 | {"msp430f5501", MSP_ISA_430Xv2}, | |
566 | {"msp430f5502", MSP_ISA_430Xv2}, | |
567 | {"msp430f5503", MSP_ISA_430Xv2}, | |
568 | {"msp430f5504", MSP_ISA_430Xv2}, | |
569 | {"msp430f5505", MSP_ISA_430Xv2}, | |
570 | {"msp430f5506", MSP_ISA_430Xv2}, | |
571 | {"msp430f5507", MSP_ISA_430Xv2}, | |
572 | {"msp430f5508", MSP_ISA_430Xv2}, | |
573 | {"msp430f5509", MSP_ISA_430Xv2}, | |
574 | {"msp430f5510", MSP_ISA_430Xv2}, | |
575 | {"msp430f5513", MSP_ISA_430Xv2}, | |
576 | {"msp430f5514", MSP_ISA_430Xv2}, | |
577 | {"msp430f5515", MSP_ISA_430Xv2}, | |
578 | {"msp430f5517", MSP_ISA_430Xv2}, | |
579 | {"msp430f5519", MSP_ISA_430Xv2}, | |
580 | {"msp430f5521", MSP_ISA_430Xv2}, | |
581 | {"msp430f5522", MSP_ISA_430Xv2}, | |
582 | {"msp430f5524", MSP_ISA_430Xv2}, | |
583 | {"msp430f5525", MSP_ISA_430Xv2}, | |
584 | {"msp430f5526", MSP_ISA_430Xv2}, | |
585 | {"msp430f5527", MSP_ISA_430Xv2}, | |
586 | {"msp430f5528", MSP_ISA_430Xv2}, | |
587 | {"msp430f5529", MSP_ISA_430Xv2}, | |
588 | {"cc430f5133", MSP_ISA_430Xv2}, | |
589 | {"cc430f5135", MSP_ISA_430Xv2}, | |
590 | {"cc430f5137", MSP_ISA_430Xv2}, | |
591 | {"cc430f6125", MSP_ISA_430Xv2}, | |
592 | {"cc430f6126", MSP_ISA_430Xv2}, | |
593 | {"cc430f6127", MSP_ISA_430Xv2}, | |
594 | {"cc430f6135", MSP_ISA_430Xv2}, | |
595 | {"cc430f6137", MSP_ISA_430Xv2}, | |
596 | {"cc430f5123", MSP_ISA_430Xv2}, | |
597 | {"cc430f5125", MSP_ISA_430Xv2}, | |
598 | {"cc430f5143", MSP_ISA_430Xv2}, | |
599 | {"cc430f5145", MSP_ISA_430Xv2}, | |
600 | {"cc430f5147", MSP_ISA_430Xv2}, | |
601 | {"cc430f6143", MSP_ISA_430Xv2}, | |
602 | {"cc430f6145", MSP_ISA_430Xv2}, | |
603 | {"cc430f6147", MSP_ISA_430Xv2}, | |
604 | {"msp430f5333", MSP_ISA_430Xv2}, | |
605 | {"msp430f5335", MSP_ISA_430Xv2}, | |
606 | {"msp430f5336", MSP_ISA_430Xv2}, | |
607 | {"msp430f5338", MSP_ISA_430Xv2}, | |
608 | {"msp430f5630", MSP_ISA_430Xv2}, | |
609 | {"msp430f5631", MSP_ISA_430Xv2}, | |
610 | {"msp430f5632", MSP_ISA_430Xv2}, | |
611 | {"msp430f5633", MSP_ISA_430Xv2}, | |
612 | {"msp430f5634", MSP_ISA_430Xv2}, | |
613 | {"msp430f5635", MSP_ISA_430Xv2}, | |
614 | {"msp430f5636", MSP_ISA_430Xv2}, | |
615 | {"msp430f5637", MSP_ISA_430Xv2}, | |
616 | {"msp430f5638", MSP_ISA_430Xv2}, | |
617 | {"msp430f6433", MSP_ISA_430Xv2}, | |
618 | {"msp430f6435", MSP_ISA_430Xv2}, | |
619 | {"msp430f6436", MSP_ISA_430Xv2}, | |
620 | {"msp430f6438", MSP_ISA_430Xv2}, | |
621 | {"msp430f6630", MSP_ISA_430Xv2}, | |
622 | {"msp430f6631", MSP_ISA_430Xv2}, | |
623 | {"msp430f6632", MSP_ISA_430Xv2}, | |
624 | {"msp430f6633", MSP_ISA_430Xv2}, | |
625 | {"msp430f6634", MSP_ISA_430Xv2}, | |
626 | {"msp430f6635", MSP_ISA_430Xv2}, | |
627 | {"msp430f6636", MSP_ISA_430Xv2}, | |
628 | {"msp430f6637", MSP_ISA_430Xv2}, | |
629 | {"msp430f6638", MSP_ISA_430Xv2}, | |
630 | {"msp430f5358", MSP_ISA_430Xv2}, | |
631 | {"msp430f5359", MSP_ISA_430Xv2}, | |
632 | {"msp430f5658", MSP_ISA_430Xv2}, | |
633 | {"msp430f5659", MSP_ISA_430Xv2}, | |
634 | {"msp430f6458", MSP_ISA_430Xv2}, | |
635 | {"msp430f6459", MSP_ISA_430Xv2}, | |
636 | {"msp430f6658", MSP_ISA_430Xv2}, | |
637 | {"msp430f6659", MSP_ISA_430Xv2}, | |
638 | {"msp430f5131", MSP_ISA_430Xv2}, | |
639 | {"msp430f5151", MSP_ISA_430Xv2}, | |
640 | {"msp430f5171", MSP_ISA_430Xv2}, | |
641 | {"msp430f5132", MSP_ISA_430Xv2}, | |
642 | {"msp430f5152", MSP_ISA_430Xv2}, | |
643 | {"msp430f5172", MSP_ISA_430Xv2}, | |
644 | {"msp430f6720", MSP_ISA_430Xv2}, | |
645 | {"msp430f6721", MSP_ISA_430Xv2}, | |
646 | {"msp430f6723", MSP_ISA_430Xv2}, | |
647 | {"msp430f6724", MSP_ISA_430Xv2}, | |
648 | {"msp430f6725", MSP_ISA_430Xv2}, | |
649 | {"msp430f6726", MSP_ISA_430Xv2}, | |
650 | {"msp430f6730", MSP_ISA_430Xv2}, | |
651 | {"msp430f6731", MSP_ISA_430Xv2}, | |
652 | {"msp430f6733", MSP_ISA_430Xv2}, | |
653 | {"msp430f6734", MSP_ISA_430Xv2}, | |
654 | {"msp430f6735", MSP_ISA_430Xv2}, | |
655 | {"msp430f6736", MSP_ISA_430Xv2}, | |
656 | {"msp430f67451", MSP_ISA_430Xv2}, | |
657 | {"msp430f67651", MSP_ISA_430Xv2}, | |
658 | {"msp430f67751", MSP_ISA_430Xv2}, | |
659 | {"msp430f67461", MSP_ISA_430Xv2}, | |
660 | {"msp430f67661", MSP_ISA_430Xv2}, | |
661 | {"msp430f67761", MSP_ISA_430Xv2}, | |
662 | {"msp430f67471", MSP_ISA_430Xv2}, | |
663 | {"msp430f67671", MSP_ISA_430Xv2}, | |
664 | {"msp430f67771", MSP_ISA_430Xv2}, | |
665 | {"msp430f67481", MSP_ISA_430Xv2}, | |
666 | {"msp430f67681", MSP_ISA_430Xv2}, | |
667 | {"msp430f67781", MSP_ISA_430Xv2}, | |
668 | {"msp430f67491", MSP_ISA_430Xv2}, | |
669 | {"msp430f67691", MSP_ISA_430Xv2}, | |
670 | {"msp430f67791", MSP_ISA_430Xv2}, | |
671 | {"msp430f6745", MSP_ISA_430Xv2}, | |
672 | {"msp430f6765", MSP_ISA_430Xv2}, | |
673 | {"msp430f6775", MSP_ISA_430Xv2}, | |
674 | {"msp430f6746", MSP_ISA_430Xv2}, | |
675 | {"msp430f6766", MSP_ISA_430Xv2}, | |
676 | {"msp430f6776", MSP_ISA_430Xv2}, | |
677 | {"msp430f6747", MSP_ISA_430Xv2}, | |
678 | {"msp430f6767", MSP_ISA_430Xv2}, | |
679 | {"msp430f6777", MSP_ISA_430Xv2}, | |
680 | {"msp430f6748", MSP_ISA_430Xv2}, | |
681 | {"msp430f6768", MSP_ISA_430Xv2}, | |
682 | {"msp430f6778", MSP_ISA_430Xv2}, | |
683 | {"msp430f6749", MSP_ISA_430Xv2}, | |
684 | {"msp430f6769", MSP_ISA_430Xv2}, | |
685 | {"msp430f6779", MSP_ISA_430Xv2}, | |
686 | {"msp430fr5720", MSP_ISA_430Xv2}, | |
687 | {"msp430fr5721", MSP_ISA_430Xv2}, | |
688 | {"msp430fr5722", MSP_ISA_430Xv2}, | |
689 | {"msp430fr5723", MSP_ISA_430Xv2}, | |
690 | {"msp430fr5724", MSP_ISA_430Xv2}, | |
691 | {"msp430fr5725", MSP_ISA_430Xv2}, | |
692 | {"msp430fr5726", MSP_ISA_430Xv2}, | |
693 | {"msp430fr5727", MSP_ISA_430Xv2}, | |
694 | {"msp430fr5728", MSP_ISA_430Xv2}, | |
695 | {"msp430fr5729", MSP_ISA_430Xv2}, | |
696 | {"msp430fr5730", MSP_ISA_430Xv2}, | |
697 | {"msp430fr5731", MSP_ISA_430Xv2}, | |
698 | {"msp430fr5732", MSP_ISA_430Xv2}, | |
699 | {"msp430fr5733", MSP_ISA_430Xv2}, | |
700 | {"msp430fr5734", MSP_ISA_430Xv2}, | |
701 | {"msp430fr5735", MSP_ISA_430Xv2}, | |
702 | {"msp430fr5736", MSP_ISA_430Xv2}, | |
703 | {"msp430fr5737", MSP_ISA_430Xv2}, | |
704 | {"msp430fr5738", MSP_ISA_430Xv2}, | |
705 | {"msp430fr5739", MSP_ISA_430Xv2}, | |
706 | {"msp430bt5190", MSP_ISA_430Xv2}, | |
707 | {"msp430fr5949", MSP_ISA_430Xv2}, | |
708 | {"msp430fr5969", MSP_ISA_430Xv2}, | |
709 | {"msp430sl5438a", MSP_ISA_430Xv2}, | |
710 | ||
711 | /* Generic names. */ | |
712 | {"msp430", MSP_ISA_430}, | |
713 | {"msp430X", MSP_ISA_430X}, | |
714 | {"msp430Xv2", MSP_ISA_430Xv2}, | |
715 | ||
716 | {NULL, 0} | |
717 | }; | |
718 | ||
719 | static struct mcu_type_s default_mcu = { "msp430x11", MSP_ISA_430 }; | |
720 | static struct mcu_type_s msp430x_mcu = { "msp430x", MSP_ISA_430X }; | |
721 | static struct mcu_type_s msp430xv2_mcu = { "msp430xv2", MSP_ISA_430Xv2 }; | |
722 | ||
723 | static struct mcu_type_s * msp430_mcu = & default_mcu; | |
724 | ||
725 | static inline bfd_boolean | |
726 | target_is_430x (void) | |
727 | { | |
728 | return msp430_mcu->isa >= MSP_ISA_430X; | |
729 | } | |
730 | ||
731 | static inline bfd_boolean | |
732 | target_is_430xv2 (void) | |
733 | { | |
734 | return msp430_mcu->isa == MSP_ISA_430Xv2; | |
735 | } | |
13761a11 NC |
736 | |
737 | /* Generate a 16-bit relocation. | |
738 | For the 430X we generate a relocation without linkwer range checking | |
739 | if the value is being used in an extended (ie 20-bit) instruction. | |
740 | For the 430 we generate a relocation without assembler range checking | |
741 | if we are handling an immediate value or a byte-width instruction. */ | |
742 | #undef CHECK_RELOC_MSP430 | |
743 | #define CHECK_RELOC_MSP430 \ | |
638d3803 | 744 | (target_is_430x () \ |
13761a11 NC |
745 | ? (extended_op ? BFD_RELOC_16 : BFD_RELOC_MSP430X_ABS16) \ |
746 | : ((imm_op || byte_op) \ | |
747 | ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16)) | |
748 | ||
749 | /* Generate a 16-bit pc-relative relocation. | |
750 | For the 430X we generate a relocation without linkwer range checking. | |
751 | For the 430 we generate a relocation without assembler range checking | |
752 | if we are handling an immediate value or a byte-width instruction. */ | |
753 | #undef CHECK_RELOC_MSP430_PCREL | |
754 | #define CHECK_RELOC_MSP430_PCREL \ | |
638d3803 | 755 | (target_is_430x () \ |
13761a11 NC |
756 | ? BFD_RELOC_MSP430X_PCR16 \ |
757 | : (imm_op || byte_op) \ | |
758 | ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL) | |
2469cfa2 | 759 | |
b18c562e NC |
760 | /* Profiling capability: |
761 | It is a performance hit to use gcc's profiling approach for this tiny target. | |
762 | Even more -- jtag hardware facility does not perform any profiling functions. | |
763 | However we've got gdb's built-in simulator where we can do anything. | |
764 | Therefore my suggestion is: | |
765 | ||
766 | We define new section ".profiler" which holds all profiling information. | |
767 | We define new pseudo operation .profiler which will instruct assembler to | |
768 | add new profile entry to the object file. Profile should take place at the | |
769 | present address. | |
770 | ||
771 | Pseudo-op format: | |
772 | ||
773 | .profiler flags,function_to_profile [, cycle_corrector, extra] | |
774 | ||
775 | where 'flags' is a combination of the following chars: | |
776 | s - function Start | |
777 | x - function eXit | |
778 | i - function is in Init section | |
779 | f - function is in Fini section | |
780 | l - Library call | |
781 | c - libC standard call | |
782 | d - stack value Demand (saved at run-time in simulator) | |
783 | I - Interrupt service routine | |
784 | P - Prologue start | |
785 | p - Prologue end | |
786 | E - Epilogue start | |
787 | e - Epilogue end | |
788 | j - long Jump/ sjlj unwind | |
789 | a - an Arbitrary code fragment | |
790 | t - exTra parameter saved (constant value like frame size) | |
791 | '""' optional: "sil" == sil | |
792 | ||
793 | function_to_profile - function's address | |
794 | cycle_corrector - a value which should be added to the cycle | |
795 | counter, zero if omitted | |
796 | extra - some extra parameter, zero if omitted. | |
797 | ||
798 | For example: | |
799 | ------------------------------ | |
800 | .global fxx | |
801 | .type fxx,@function | |
802 | fxx: | |
803 | .LFrameOffset_fxx=0x08 | |
804 | .profiler "scdP", fxx ; function entry. | |
805 | ; we also demand stack value to be displayed | |
806 | push r11 | |
807 | push r10 | |
808 | push r9 | |
809 | push r8 | |
810 | .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point | |
811 | ; (this is a prologue end) | |
79cf5950 | 812 | ; note, that spare var filled with the frame size |
b18c562e NC |
813 | mov r15,r8 |
814 | .... | |
815 | .profiler cdE,fxx ; check stack | |
816 | pop r8 | |
817 | pop r9 | |
818 | pop r10 | |
819 | pop r11 | |
820 | .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter | |
821 | ret ; cause 'ret' insn takes 3 cycles | |
822 | ------------------------------- | |
823 | ||
824 | This profiling approach does not produce any overhead and | |
825 | absolutely harmless. | |
826 | So, even profiled code can be uploaded to the MCU. */ | |
827 | #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */ | |
828 | #define MSP430_PROFILER_FLAG_EXIT 2 /* x */ | |
829 | #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */ | |
830 | #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */ | |
831 | #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */ | |
832 | #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */ | |
833 | #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */ | |
834 | #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */ | |
835 | #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */ | |
836 | #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */ | |
837 | #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */ | |
838 | #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */ | |
839 | #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */ | |
840 | #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */ | |
841 | #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */ | |
842 | #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */ | |
2469cfa2 | 843 | |
b18c562e NC |
844 | static int |
845 | pow2value (int y) | |
2469cfa2 | 846 | { |
b18c562e NC |
847 | int n = 0; |
848 | unsigned int x; | |
2469cfa2 | 849 | |
b18c562e | 850 | x = y; |
2469cfa2 | 851 | |
b18c562e NC |
852 | if (!x) |
853 | return 1; | |
2469cfa2 | 854 | |
b18c562e NC |
855 | for (; x; x = x >> 1) |
856 | if (x & 1) | |
857 | n++; | |
858 | ||
859 | return n == 1; | |
860 | } | |
861 | ||
862 | /* Parse ordinary expression. */ | |
863 | ||
864 | static char * | |
865 | parse_exp (char * s, expressionS * op) | |
2469cfa2 | 866 | { |
b18c562e NC |
867 | input_line_pointer = s; |
868 | expression (op); | |
869 | if (op->X_op == O_absent) | |
870 | as_bad (_("missing operand")); | |
871 | return input_line_pointer; | |
872 | } | |
2469cfa2 | 873 | |
b18c562e NC |
874 | |
875 | /* Delete spaces from s: X ( r 1 2) => X(r12). */ | |
2469cfa2 NC |
876 | |
877 | static void | |
b18c562e | 878 | del_spaces (char * s) |
2469cfa2 | 879 | { |
b18c562e NC |
880 | while (*s) |
881 | { | |
882 | if (ISSPACE (*s)) | |
883 | { | |
884 | char *m = s + 1; | |
2469cfa2 | 885 | |
b18c562e NC |
886 | while (ISSPACE (*m) && *m) |
887 | m++; | |
888 | memmove (s, m, strlen (m) + 1); | |
889 | } | |
890 | else | |
891 | s++; | |
892 | } | |
893 | } | |
2469cfa2 | 894 | |
b18c562e NC |
895 | static inline char * |
896 | skip_space (char * s) | |
897 | { | |
898 | while (ISSPACE (*s)) | |
899 | ++s; | |
900 | return s; | |
901 | } | |
2469cfa2 | 902 | |
708587a4 | 903 | /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */ |
b18c562e NC |
904 | |
905 | static char * | |
906 | extract_operand (char * from, char * to, int limit) | |
907 | { | |
908 | int size = 0; | |
909 | ||
910 | /* Drop leading whitespace. */ | |
911 | from = skip_space (from); | |
912 | ||
913 | while (size < limit && *from) | |
914 | { | |
915 | *(to + size) = *from; | |
916 | if (*from == ',' || *from == ';' || *from == '\n') | |
917 | break; | |
918 | from++; | |
919 | size++; | |
920 | } | |
921 | ||
922 | *(to + size) = 0; | |
923 | del_spaces (to); | |
924 | ||
925 | from++; | |
926 | ||
927 | return from; | |
2469cfa2 NC |
928 | } |
929 | ||
b18c562e NC |
930 | static void |
931 | msp430_profiler (int dummy ATTRIBUTE_UNUSED) | |
2469cfa2 | 932 | { |
b18c562e NC |
933 | char buffer[1024]; |
934 | char f[32]; | |
935 | char * str = buffer; | |
936 | char * flags = f; | |
937 | int p_flags = 0; | |
938 | char * halt; | |
939 | int ops = 0; | |
940 | int left; | |
941 | char * s; | |
942 | segT seg; | |
943 | int subseg; | |
944 | char * end = 0; | |
945 | expressionS exp; | |
946 | expressionS exp1; | |
947 | ||
948 | s = input_line_pointer; | |
949 | end = input_line_pointer; | |
950 | ||
951 | while (*end && *end != '\n') | |
952 | end++; | |
953 | ||
954 | while (*s && *s != '\n') | |
955 | { | |
956 | if (*s == ',') | |
957 | ops++; | |
958 | s++; | |
959 | } | |
2469cfa2 | 960 | |
b18c562e NC |
961 | left = 3 - ops; |
962 | ||
963 | if (ops < 1) | |
964 | { | |
965 | as_bad (_(".profiler pseudo requires at least two operands.")); | |
966 | input_line_pointer = end; | |
967 | return; | |
968 | } | |
969 | ||
970 | input_line_pointer = extract_operand (input_line_pointer, flags, 32); | |
971 | ||
972 | while (*flags) | |
973 | { | |
974 | switch (*flags) | |
975 | { | |
976 | case '"': | |
977 | break; | |
978 | case 'a': | |
979 | p_flags |= MSP430_PROFILER_FLAG_FRAGMENT; | |
980 | break; | |
981 | case 'j': | |
982 | p_flags |= MSP430_PROFILER_FLAG_JUMP; | |
983 | break; | |
984 | case 'P': | |
985 | p_flags |= MSP430_PROFILER_FLAG_PROLSTART; | |
986 | break; | |
987 | case 'p': | |
988 | p_flags |= MSP430_PROFILER_FLAG_PROLEND; | |
989 | break; | |
990 | case 'E': | |
991 | p_flags |= MSP430_PROFILER_FLAG_EPISTART; | |
992 | break; | |
993 | case 'e': | |
994 | p_flags |= MSP430_PROFILER_FLAG_EPIEND; | |
995 | break; | |
996 | case 's': | |
997 | p_flags |= MSP430_PROFILER_FLAG_ENTRY; | |
998 | break; | |
999 | case 'x': | |
1000 | p_flags |= MSP430_PROFILER_FLAG_EXIT; | |
1001 | break; | |
1002 | case 'i': | |
1003 | p_flags |= MSP430_PROFILER_FLAG_INITSECT; | |
1004 | break; | |
1005 | case 'f': | |
1006 | p_flags |= MSP430_PROFILER_FLAG_FINISECT; | |
1007 | break; | |
1008 | case 'l': | |
1009 | p_flags |= MSP430_PROFILER_FLAG_LIBCALL; | |
1010 | break; | |
1011 | case 'c': | |
1012 | p_flags |= MSP430_PROFILER_FLAG_STDCALL; | |
1013 | break; | |
1014 | case 'd': | |
1015 | p_flags |= MSP430_PROFILER_FLAG_STACKDMD; | |
1016 | break; | |
1017 | case 'I': | |
1018 | p_flags |= MSP430_PROFILER_FLAG_ISR; | |
1019 | break; | |
1020 | case 't': | |
1021 | p_flags |= MSP430_PROFILER_FLAG_EXTRA; | |
1022 | break; | |
1023 | default: | |
1024 | as_warn (_("unknown profiling flag - ignored.")); | |
1025 | break; | |
1026 | } | |
1027 | flags++; | |
1028 | } | |
1029 | ||
1030 | if (p_flags | |
1031 | && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY | |
1032 | | MSP430_PROFILER_FLAG_EXIT)) | |
1033 | || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART | |
1034 | | MSP430_PROFILER_FLAG_PROLEND | |
1035 | | MSP430_PROFILER_FLAG_EPISTART | |
1036 | | MSP430_PROFILER_FLAG_EPIEND)) | |
1037 | || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT | |
1038 | | MSP430_PROFILER_FLAG_FINISECT)))) | |
1039 | { | |
79cf5950 | 1040 | as_bad (_("ambiguous flags combination - '.profiler' directive ignored.")); |
b18c562e NC |
1041 | input_line_pointer = end; |
1042 | return; | |
1043 | } | |
1044 | ||
1045 | /* Generate temp symbol which denotes current location. */ | |
79cf5950 | 1046 | if (now_seg == absolute_section) /* Paranoia ? */ |
b18c562e NC |
1047 | { |
1048 | exp1.X_op = O_constant; | |
1049 | exp1.X_add_number = abs_section_offset; | |
79cf5950 | 1050 | as_warn (_("profiling in absolute section?")); |
b18c562e NC |
1051 | } |
1052 | else | |
1053 | { | |
1054 | exp1.X_op = O_symbol; | |
1055 | exp1.X_add_symbol = symbol_temp_new_now (); | |
1056 | exp1.X_add_number = 0; | |
1057 | } | |
1058 | ||
1059 | /* Generate a symbol which holds flags value. */ | |
1060 | exp.X_op = O_constant; | |
1061 | exp.X_add_number = p_flags; | |
1062 | ||
1063 | /* Save current section. */ | |
1064 | seg = now_seg; | |
1065 | subseg = now_subseg; | |
1066 | ||
1067 | /* Now go to .profiler section. */ | |
1068 | obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0); | |
1069 | ||
1070 | /* Save flags. */ | |
1071 | emit_expr (& exp, 2); | |
1072 | ||
1073 | /* Save label value. */ | |
1074 | emit_expr (& exp1, 2); | |
1075 | ||
1076 | while (ops--) | |
1077 | { | |
1078 | /* Now get profiling info. */ | |
1079 | halt = extract_operand (input_line_pointer, str, 1024); | |
1080 | /* Process like ".word xxx" directive. */ | |
1081 | parse_exp (str, & exp); | |
1082 | emit_expr (& exp, 2); | |
1083 | input_line_pointer = halt; | |
1084 | } | |
1085 | ||
1086 | /* Fill the rest with zeros. */ | |
1087 | exp.X_op = O_constant; | |
1088 | exp.X_add_number = 0; | |
1089 | while (left--) | |
1090 | emit_expr (& exp, 2); | |
1091 | ||
1092 | /* Return to current section. */ | |
1093 | subseg_set (seg, subseg); | |
2469cfa2 NC |
1094 | } |
1095 | ||
1096 | static char * | |
b18c562e | 1097 | extract_word (char * from, char * to, int limit) |
2469cfa2 | 1098 | { |
2469cfa2 NC |
1099 | char *op_end; |
1100 | int size = 0; | |
1101 | ||
1102 | /* Drop leading whitespace. */ | |
1103 | from = skip_space (from); | |
1104 | *to = 0; | |
1105 | ||
1106 | /* Find the op code end. */ | |
87975d2a | 1107 | for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);) |
2469cfa2 NC |
1108 | { |
1109 | to[size++] = *op_end++; | |
1110 | if (size + 1 >= limit) | |
1111 | break; | |
1112 | } | |
1113 | ||
1114 | to[size] = 0; | |
1115 | return op_end; | |
1116 | } | |
1117 | ||
b18c562e | 1118 | #define OPTION_MMCU 'm' |
77592908 DD |
1119 | #define OPTION_RELAX 'Q' |
1120 | #define OPTION_POLYMORPHS 'P' | |
13761a11 NC |
1121 | #define OPTION_LARGE 'l' |
1122 | static bfd_boolean large_model = FALSE; | |
1123 | #define OPTION_NO_INTR_NOPS 'N' | |
1124 | static bfd_boolean gen_interrupt_nops = TRUE; | |
638d3803 | 1125 | #define OPTION_MCPU 'c' |
b18c562e | 1126 | |
2469cfa2 | 1127 | static void |
638d3803 | 1128 | msp430_set_arch (int option) |
2469cfa2 NC |
1129 | { |
1130 | char *str = (char *) alloca (32); /* 32 for good measure. */ | |
1131 | ||
1132 | input_line_pointer = extract_word (input_line_pointer, str, 32); | |
1133 | ||
638d3803 NC |
1134 | md_parse_option (option, str); |
1135 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, | |
1136 | target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11); | |
2469cfa2 NC |
1137 | } |
1138 | ||
b18c562e NC |
1139 | static void |
1140 | show_mcu_list (FILE * stream) | |
1141 | { | |
1142 | int i; | |
1143 | ||
1144 | fprintf (stream, _("Known MCU names:\n")); | |
1145 | ||
1146 | for (i = 0; mcu_types[i].name; i++) | |
13761a11 | 1147 | { |
638d3803 | 1148 | fprintf (stream, "%14.14s", mcu_types[i].name); |
13761a11 NC |
1149 | if ((i % 6) == 5) |
1150 | fprintf (stream, "\n"); | |
1151 | } | |
b18c562e NC |
1152 | |
1153 | fprintf (stream, "\n"); | |
1154 | } | |
1155 | ||
2469cfa2 | 1156 | int |
b18c562e | 1157 | md_parse_option (int c, char * arg) |
2469cfa2 NC |
1158 | { |
1159 | int i; | |
1160 | ||
1161 | switch (c) | |
1162 | { | |
1163 | case OPTION_MMCU: | |
638d3803 NC |
1164 | if (arg == NULL) |
1165 | as_fatal (_("MCU option requires a name\n")); | |
1166 | ||
2469cfa2 | 1167 | for (i = 0; mcu_types[i].name; ++i) |
638d3803 | 1168 | if (strcasecmp (mcu_types[i].name, arg) == 0) |
2469cfa2 NC |
1169 | break; |
1170 | ||
638d3803 | 1171 | if (mcu_types[i].name == NULL) |
2469cfa2 NC |
1172 | { |
1173 | show_mcu_list (stderr); | |
1174 | as_fatal (_("unknown MCU: %s\n"), arg); | |
1175 | } | |
1176 | ||
638d3803 NC |
1177 | /* Allow switching to the same or a lesser architecture. */ |
1178 | if (msp430_mcu == &default_mcu || msp430_mcu->isa >= mcu_types[i].isa) | |
13761a11 | 1179 | msp430_mcu = mcu_types + i; |
2469cfa2 | 1180 | else |
638d3803 | 1181 | as_fatal (_("redefinition of mcu type '%s' to '%s'"), |
2469cfa2 NC |
1182 | msp430_mcu->name, mcu_types[i].name); |
1183 | return 1; | |
13761a11 | 1184 | |
638d3803 NC |
1185 | case OPTION_MCPU: |
1186 | if (strcmp (arg, "430") == 0) | |
1187 | msp430_mcu = & default_mcu; | |
1188 | else if (strcmp (arg, "430x") == 0 | |
1189 | || strcmp (arg, "430X") == 0) | |
1190 | msp430_mcu = & msp430x_mcu; | |
1191 | else if (strcasecmp (arg, "430xv2") == 0) | |
1192 | msp430_mcu = & msp430xv2_mcu; | |
1193 | else | |
1194 | as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg); | |
1195 | ||
1196 | return 1; | |
1197 | ||
77592908 | 1198 | case OPTION_RELAX: |
13761a11 | 1199 | msp430_enable_relax = 1; |
77592908 | 1200 | return 1; |
13761a11 | 1201 | |
77592908 DD |
1202 | case OPTION_POLYMORPHS: |
1203 | msp430_enable_polys = 1; | |
1204 | return 1; | |
13761a11 NC |
1205 | |
1206 | case OPTION_LARGE: | |
1207 | large_model = TRUE; | |
1208 | return 1; | |
1209 | ||
1210 | case OPTION_NO_INTR_NOPS: | |
1211 | gen_interrupt_nops = FALSE; | |
1212 | return 1; | |
2469cfa2 NC |
1213 | } |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
2469cfa2 | 1218 | |
b18c562e | 1219 | const pseudo_typeS md_pseudo_table[] = |
2469cfa2 | 1220 | { |
638d3803 NC |
1221 | {"arch", msp430_set_arch, OPTION_MMCU}, |
1222 | {"cpu", msp430_set_arch, OPTION_MCPU}, | |
b18c562e NC |
1223 | {"profiler", msp430_profiler, 0}, |
1224 | {NULL, NULL, 0} | |
1225 | }; | |
2469cfa2 | 1226 | |
638d3803 | 1227 | const char *md_shortopts = "mm:,mP,mQ,ml,mN"; |
2469cfa2 | 1228 | |
b18c562e | 1229 | struct option md_longopts[] = |
2469cfa2 | 1230 | { |
b18c562e | 1231 | {"mmcu", required_argument, NULL, OPTION_MMCU}, |
638d3803 | 1232 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
77592908 DD |
1233 | {"mP", no_argument, NULL, OPTION_POLYMORPHS}, |
1234 | {"mQ", no_argument, NULL, OPTION_RELAX}, | |
13761a11 NC |
1235 | {"ml", no_argument, NULL, OPTION_LARGE}, |
1236 | {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS}, | |
b18c562e NC |
1237 | {NULL, no_argument, NULL, 0} |
1238 | }; | |
2469cfa2 | 1239 | |
b18c562e | 1240 | size_t md_longopts_size = sizeof (md_longopts); |
2469cfa2 | 1241 | |
b18c562e NC |
1242 | void |
1243 | md_show_usage (FILE * stream) | |
2469cfa2 | 1244 | { |
b18c562e NC |
1245 | fprintf (stream, |
1246 | _("MSP430 options:\n" | |
638d3803 NC |
1247 | " -mmcu=<msp430-name> - select microcontroller type\n" |
1248 | " -mcpu={430|430x|430xv2} - select microcontroller architecture\n")); | |
77592908 DD |
1249 | fprintf (stream, |
1250 | _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n" | |
1251 | " -mP - enable polymorph instructions\n")); | |
13761a11 NC |
1252 | fprintf (stream, |
1253 | _(" -ml - enable large code model\n")); | |
1254 | fprintf (stream, | |
1255 | _(" -mN - disable generation of NOP after changing interrupts\n")); | |
2469cfa2 | 1256 | |
b18c562e NC |
1257 | show_mcu_list (stream); |
1258 | } | |
2469cfa2 | 1259 | |
b18c562e NC |
1260 | symbolS * |
1261 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
1262 | { | |
13761a11 | 1263 | return NULL; |
2469cfa2 NC |
1264 | } |
1265 | ||
1266 | static char * | |
b18c562e | 1267 | extract_cmd (char * from, char * to, int limit) |
2469cfa2 NC |
1268 | { |
1269 | int size = 0; | |
1270 | ||
1271 | while (*from && ! ISSPACE (*from) && *from != '.' && limit > size) | |
1272 | { | |
1273 | *(to + size) = *from; | |
1274 | from++; | |
1275 | size++; | |
1276 | } | |
1277 | ||
1278 | *(to + size) = 0; | |
1279 | ||
1280 | return from; | |
1281 | } | |
1282 | ||
2469cfa2 | 1283 | char * |
b18c562e | 1284 | md_atof (int type, char * litP, int * sizeP) |
2469cfa2 | 1285 | { |
499ac353 | 1286 | return ieee_md_atof (type, litP, sizeP, FALSE); |
2469cfa2 NC |
1287 | } |
1288 | ||
1289 | void | |
b18c562e | 1290 | md_begin (void) |
2469cfa2 | 1291 | { |
b18c562e | 1292 | struct msp430_opcode_s * opcode; |
2469cfa2 NC |
1293 | msp430_hash = hash_new (); |
1294 | ||
1295 | for (opcode = msp430_opcodes; opcode->name; opcode++) | |
1296 | hash_insert (msp430_hash, opcode->name, (char *) opcode); | |
1297 | ||
638d3803 NC |
1298 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
1299 | target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11); | |
2469cfa2 NC |
1300 | } |
1301 | ||
13761a11 NC |
1302 | /* Returns the register number equivalent to the string T. |
1303 | Returns -1 if there is no such register. | |
1304 | Skips a leading 'r' or 'R' character if there is one. | |
1305 | Handles the register aliases PC and SP. */ | |
1306 | ||
1307 | static signed int | |
b18c562e | 1308 | check_reg (char * t) |
2469cfa2 | 1309 | { |
13761a11 | 1310 | signed int val; |
2469cfa2 | 1311 | |
13761a11 NC |
1312 | if (t == NULL) |
1313 | return -1; | |
2469cfa2 | 1314 | |
13761a11 NC |
1315 | if (*t == 'r' || *t == 'R') |
1316 | ++t; | |
1317 | ||
1318 | if (strncasecmp (t, "pc", 2) == 0) | |
1319 | return 0; | |
2469cfa2 | 1320 | |
13761a11 | 1321 | if (strncasecmp (t, "sp", 2) == 0) |
b18c562e | 1322 | return 1; |
2469cfa2 | 1323 | |
13761a11 NC |
1324 | if (strncasecmp (t, "sr", 2) == 0) |
1325 | return 2; | |
1326 | ||
1327 | if (*t == '0') | |
1328 | return 0; | |
2469cfa2 | 1329 | |
13761a11 NC |
1330 | val = atoi (t); |
1331 | ||
1332 | if (val < 1 || val > 15) | |
1333 | return -1; | |
1334 | ||
1335 | return val; | |
1336 | } | |
2469cfa2 | 1337 | |
b18c562e NC |
1338 | static int |
1339 | msp430_srcoperand (struct msp430_operand_s * op, | |
13761a11 NC |
1340 | char * l, |
1341 | int bin, | |
1342 | int * imm_op, | |
1343 | bfd_boolean allow_20bit_values, | |
1344 | bfd_boolean constants_allowed) | |
2469cfa2 | 1345 | { |
b18c562e | 1346 | char *__tl = l; |
2469cfa2 | 1347 | |
b18c562e NC |
1348 | /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */ |
1349 | if (*l == '#') | |
2469cfa2 | 1350 | { |
b18c562e NC |
1351 | char *h = l; |
1352 | int vshift = -1; | |
1353 | int rval = 0; | |
2469cfa2 | 1354 | |
b18c562e NC |
1355 | /* Check if there is: |
1356 | llo(x) - least significant 16 bits, x &= 0xffff | |
1357 | lhi(x) - x = (x >> 16) & 0xffff, | |
1358 | hlo(x) - x = (x >> 32) & 0xffff, | |
1359 | hhi(x) - x = (x >> 48) & 0xffff | |
1360 | The value _MUST_ be constant expression: #hlo(1231231231). */ | |
2469cfa2 | 1361 | |
b18c562e | 1362 | *imm_op = 1; |
2469cfa2 | 1363 | |
b18c562e NC |
1364 | if (strncasecmp (h, "#llo(", 5) == 0) |
1365 | { | |
1366 | vshift = 0; | |
1367 | rval = 3; | |
1368 | } | |
1369 | else if (strncasecmp (h, "#lhi(", 5) == 0) | |
1370 | { | |
1371 | vshift = 1; | |
1372 | rval = 3; | |
1373 | } | |
1374 | else if (strncasecmp (h, "#hlo(", 5) == 0) | |
1375 | { | |
1376 | vshift = 2; | |
1377 | rval = 3; | |
1378 | } | |
1379 | else if (strncasecmp (h, "#hhi(", 5) == 0) | |
1380 | { | |
1381 | vshift = 3; | |
1382 | rval = 3; | |
1383 | } | |
1384 | else if (strncasecmp (h, "#lo(", 4) == 0) | |
1385 | { | |
1386 | vshift = 0; | |
1387 | rval = 2; | |
1388 | } | |
1389 | else if (strncasecmp (h, "#hi(", 4) == 0) | |
1390 | { | |
1391 | vshift = 1; | |
1392 | rval = 2; | |
1393 | } | |
2469cfa2 | 1394 | |
b18c562e NC |
1395 | op->reg = 0; /* Reg PC. */ |
1396 | op->am = 3; | |
1397 | op->ol = 1; /* Immediate will follow an instruction. */ | |
1398 | __tl = h + 1 + rval; | |
1399 | op->mode = OP_EXP; | |
2469cfa2 | 1400 | |
b18c562e NC |
1401 | parse_exp (__tl, &(op->exp)); |
1402 | if (op->exp.X_op == O_constant) | |
2469cfa2 | 1403 | { |
b18c562e | 1404 | int x = op->exp.X_add_number; |
2469cfa2 | 1405 | |
b18c562e | 1406 | if (vshift == 0) |
2469cfa2 | 1407 | { |
b18c562e NC |
1408 | x = x & 0xffff; |
1409 | op->exp.X_add_number = x; | |
1410 | } | |
1411 | else if (vshift == 1) | |
1412 | { | |
1413 | x = (x >> 16) & 0xffff; | |
1414 | op->exp.X_add_number = x; | |
1415 | } | |
1416 | else if (vshift > 1) | |
1417 | { | |
1418 | if (x < 0) | |
1419 | op->exp.X_add_number = -1; | |
2469cfa2 | 1420 | else |
b18c562e NC |
1421 | op->exp.X_add_number = 0; /* Nothing left. */ |
1422 | x = op->exp.X_add_number; | |
2469cfa2 | 1423 | } |
2469cfa2 | 1424 | |
13761a11 NC |
1425 | if (allow_20bit_values) |
1426 | { | |
1427 | if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < - (0x7ffff)) | |
1428 | { | |
1429 | as_bad (_("value 0x%x out of extended range."), x); | |
1430 | return 1; | |
1431 | } | |
1432 | } | |
1433 | else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768) | |
b18c562e NC |
1434 | { |
1435 | as_bad (_("value %d out of range. Use #lo() or #hi()"), x); | |
1436 | return 1; | |
1437 | } | |
2469cfa2 | 1438 | |
b18c562e NC |
1439 | /* Now check constants. */ |
1440 | /* Substitute register mode with a constant generator if applicable. */ | |
2469cfa2 | 1441 | |
13761a11 NC |
1442 | if (!allow_20bit_values) |
1443 | x = (short) x; /* Extend sign. */ | |
2469cfa2 | 1444 | |
13761a11 NC |
1445 | if (! constants_allowed) |
1446 | ; | |
1447 | else if (x == 0) | |
2469cfa2 | 1448 | { |
b18c562e NC |
1449 | op->reg = 3; |
1450 | op->am = 0; | |
1451 | op->ol = 0; | |
1452 | op->mode = OP_REG; | |
1453 | } | |
1454 | else if (x == 1) | |
1455 | { | |
1456 | op->reg = 3; | |
1457 | op->am = 1; | |
1458 | op->ol = 0; | |
1459 | op->mode = OP_REG; | |
1460 | } | |
1461 | else if (x == 2) | |
1462 | { | |
1463 | op->reg = 3; | |
1464 | op->am = 2; | |
1465 | op->ol = 0; | |
1466 | op->mode = OP_REG; | |
1467 | } | |
1468 | else if (x == -1) | |
1469 | { | |
1470 | op->reg = 3; | |
1471 | op->am = 3; | |
1472 | op->ol = 0; | |
1473 | op->mode = OP_REG; | |
1474 | } | |
1475 | else if (x == 4) | |
1476 | { | |
1477 | #ifdef PUSH_1X_WORKAROUND | |
1478 | if (bin == 0x1200) | |
1479 | { | |
1480 | /* Remove warning as confusing. | |
20203fb9 | 1481 | as_warn (_("Hardware push bug workaround")); */ |
b18c562e NC |
1482 | } |
1483 | else | |
1484 | #endif | |
1485 | { | |
1486 | op->reg = 2; | |
1487 | op->am = 2; | |
1488 | op->ol = 0; | |
1489 | op->mode = OP_REG; | |
1490 | } | |
1491 | } | |
1492 | else if (x == 8) | |
1493 | { | |
1494 | #ifdef PUSH_1X_WORKAROUND | |
1495 | if (bin == 0x1200) | |
1496 | { | |
1497 | /* Remove warning as confusing. | |
20203fb9 | 1498 | as_warn (_("Hardware push bug workaround")); */ |
b18c562e NC |
1499 | } |
1500 | else | |
1501 | #endif | |
1502 | { | |
1503 | op->reg = 2; | |
1504 | op->am = 3; | |
1505 | op->ol = 0; | |
1506 | op->mode = OP_REG; | |
1507 | } | |
2469cfa2 | 1508 | } |
2469cfa2 | 1509 | } |
b18c562e NC |
1510 | else if (op->exp.X_op == O_symbol) |
1511 | { | |
1512 | op->mode = OP_EXP; | |
1513 | } | |
1514 | else if (op->exp.X_op == O_big) | |
1515 | { | |
1516 | short x; | |
1517 | if (vshift != -1) | |
1518 | { | |
1519 | op->exp.X_op = O_constant; | |
1520 | op->exp.X_add_number = 0xffff & generic_bignum[vshift]; | |
1521 | x = op->exp.X_add_number; | |
1522 | } | |
1523 | else | |
1524 | { | |
1525 | as_bad (_ | |
1526 | ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "), | |
1527 | l); | |
1528 | return 1; | |
1529 | } | |
2469cfa2 | 1530 | |
b18c562e NC |
1531 | if (x == 0) |
1532 | { | |
1533 | op->reg = 3; | |
1534 | op->am = 0; | |
1535 | op->ol = 0; | |
1536 | op->mode = OP_REG; | |
1537 | } | |
1538 | else if (x == 1) | |
1539 | { | |
1540 | op->reg = 3; | |
1541 | op->am = 1; | |
1542 | op->ol = 0; | |
1543 | op->mode = OP_REG; | |
1544 | } | |
1545 | else if (x == 2) | |
1546 | { | |
1547 | op->reg = 3; | |
1548 | op->am = 2; | |
1549 | op->ol = 0; | |
1550 | op->mode = OP_REG; | |
1551 | } | |
1552 | else if (x == -1) | |
1553 | { | |
1554 | op->reg = 3; | |
1555 | op->am = 3; | |
1556 | op->ol = 0; | |
1557 | op->mode = OP_REG; | |
1558 | } | |
1559 | else if (x == 4) | |
1560 | { | |
1561 | op->reg = 2; | |
1562 | op->am = 2; | |
1563 | op->ol = 0; | |
1564 | op->mode = OP_REG; | |
1565 | } | |
1566 | else if (x == 8) | |
1567 | { | |
1568 | op->reg = 2; | |
1569 | op->am = 3; | |
1570 | op->ol = 0; | |
1571 | op->mode = OP_REG; | |
1572 | } | |
1573 | } | |
79cf5950 | 1574 | /* Redundant (yet) check. */ |
b18c562e NC |
1575 | else if (op->exp.X_op == O_register) |
1576 | as_bad | |
1577 | (_("Registers cannot be used within immediate expression [%s]"), l); | |
1578 | else | |
1579 | as_bad (_("unknown operand %s"), l); | |
2469cfa2 | 1580 | |
b18c562e NC |
1581 | return 0; |
1582 | } | |
2469cfa2 | 1583 | |
b18c562e NC |
1584 | /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */ |
1585 | if (*l == '&') | |
1586 | { | |
1587 | char *h = l; | |
2469cfa2 | 1588 | |
b18c562e NC |
1589 | op->reg = 2; /* reg 2 in absolute addr mode. */ |
1590 | op->am = 1; /* mode As == 01 bin. */ | |
1591 | op->ol = 1; /* Immediate value followed by instruction. */ | |
1592 | __tl = h + 1; | |
1593 | parse_exp (__tl, &(op->exp)); | |
1594 | op->mode = OP_EXP; | |
1595 | if (op->exp.X_op == O_constant) | |
2469cfa2 | 1596 | { |
b18c562e | 1597 | int x = op->exp.X_add_number; |
2469cfa2 | 1598 | |
13761a11 NC |
1599 | if (allow_20bit_values) |
1600 | { | |
1601 | if (x > 0xfffff || x < -(0x7ffff)) | |
1602 | { | |
1603 | as_bad (_("value 0x%x out of extended range."), x); | |
1604 | return 1; | |
1605 | } | |
1606 | } | |
1607 | else if (x > 65535 || x < -32768) | |
b18c562e | 1608 | { |
13761a11 | 1609 | as_bad (_("value out of range: 0x%x"), x); |
b18c562e NC |
1610 | return 1; |
1611 | } | |
2469cfa2 | 1612 | } |
b18c562e NC |
1613 | else if (op->exp.X_op == O_symbol) |
1614 | ; | |
1615 | else | |
2469cfa2 | 1616 | { |
79cf5950 | 1617 | /* Redundant (yet) check. */ |
b18c562e NC |
1618 | if (op->exp.X_op == O_register) |
1619 | as_bad | |
1620 | (_("Registers cannot be used within absolute expression [%s]"), l); | |
2469cfa2 | 1621 | else |
b18c562e NC |
1622 | as_bad (_("unknown expression in operand %s"), l); |
1623 | return 1; | |
2469cfa2 | 1624 | } |
b18c562e NC |
1625 | return 0; |
1626 | } | |
2469cfa2 | 1627 | |
b18c562e NC |
1628 | /* Check if indirect register mode @Rn / postincrement @Rn+. */ |
1629 | if (*l == '@') | |
1630 | { | |
1631 | char *t = l; | |
1632 | char *m = strchr (l, '+'); | |
1633 | ||
1634 | if (t != l) | |
2469cfa2 | 1635 | { |
b18c562e NC |
1636 | as_bad (_("unknown addressing mode %s"), l); |
1637 | return 1; | |
2469cfa2 NC |
1638 | } |
1639 | ||
b18c562e | 1640 | t++; |
2469cfa2 | 1641 | |
13761a11 | 1642 | if ((op->reg = check_reg (t)) == -1) |
2469cfa2 | 1643 | { |
13761a11 | 1644 | as_bad (_("Bad register name %s"), t); |
b18c562e | 1645 | return 1; |
2469cfa2 | 1646 | } |
2469cfa2 | 1647 | |
b18c562e NC |
1648 | op->mode = OP_REG; |
1649 | op->am = m ? 3 : 2; | |
1650 | op->ol = 0; | |
2469cfa2 | 1651 | |
b18c562e NC |
1652 | return 0; |
1653 | } | |
2469cfa2 | 1654 | |
b18c562e NC |
1655 | /* Check if register indexed X(Rn). */ |
1656 | do | |
1657 | { | |
1658 | char *h = strrchr (l, '('); | |
1659 | char *m = strrchr (l, ')'); | |
1660 | char *t; | |
2469cfa2 | 1661 | |
b18c562e | 1662 | *imm_op = 1; |
2469cfa2 | 1663 | |
b18c562e NC |
1664 | if (!h) |
1665 | break; | |
1666 | if (!m) | |
1667 | { | |
1668 | as_bad (_("')' required")); | |
1669 | return 1; | |
1670 | } | |
2469cfa2 | 1671 | |
b18c562e NC |
1672 | t = h; |
1673 | op->am = 1; | |
1674 | op->ol = 1; | |
2469cfa2 | 1675 | |
13761a11 NC |
1676 | /* Extract a register. */ |
1677 | if ((op->reg = check_reg (t + 1)) == -1) | |
b18c562e NC |
1678 | { |
1679 | as_bad (_ | |
1680 | ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"), | |
1681 | l); | |
1682 | return 1; | |
1683 | } | |
2469cfa2 | 1684 | |
13761a11 | 1685 | if (op->reg == 2) |
b18c562e | 1686 | { |
13761a11 | 1687 | as_bad (_("r2 should not be used in indexed addressing mode")); |
b18c562e NC |
1688 | return 1; |
1689 | } | |
b18c562e NC |
1690 | |
1691 | /* Extract constant. */ | |
1692 | __tl = l; | |
1693 | *h = 0; | |
1694 | op->mode = OP_EXP; | |
1695 | parse_exp (__tl, &(op->exp)); | |
1696 | if (op->exp.X_op == O_constant) | |
1697 | { | |
1698 | int x = op->exp.X_add_number; | |
1699 | ||
13761a11 NC |
1700 | if (allow_20bit_values) |
1701 | { | |
1702 | if (x > 0xfffff || x < - (0x7ffff)) | |
1703 | { | |
1704 | as_bad (_("value 0x%x out of extended range."), x); | |
1705 | return 1; | |
1706 | } | |
1707 | } | |
1708 | else if (x > 65535 || x < -32768) | |
2469cfa2 | 1709 | { |
13761a11 | 1710 | as_bad (_("value out of range: 0x%x"), x); |
b18c562e | 1711 | return 1; |
2469cfa2 | 1712 | } |
b18c562e NC |
1713 | |
1714 | if (x == 0) | |
2469cfa2 | 1715 | { |
b18c562e NC |
1716 | op->mode = OP_REG; |
1717 | op->am = 2; | |
1718 | op->ol = 0; | |
1719 | return 0; | |
2469cfa2 NC |
1720 | } |
1721 | } | |
b18c562e NC |
1722 | else if (op->exp.X_op == O_symbol) |
1723 | ; | |
2469cfa2 NC |
1724 | else |
1725 | { | |
79cf5950 | 1726 | /* Redundant (yet) check. */ |
b18c562e NC |
1727 | if (op->exp.X_op == O_register) |
1728 | as_bad | |
1729 | (_("Registers cannot be used as a prefix of indexed expression [%s]"), l); | |
1730 | else | |
1731 | as_bad (_("unknown expression in operand %s"), l); | |
1732 | return 1; | |
2469cfa2 | 1733 | } |
2469cfa2 | 1734 | |
b18c562e | 1735 | return 0; |
2469cfa2 | 1736 | } |
b18c562e | 1737 | while (0); |
2469cfa2 | 1738 | |
13761a11 NC |
1739 | /* Possibly register mode 'mov r1,r2'. */ |
1740 | if ((op->reg = check_reg (l)) != -1) | |
b18c562e | 1741 | { |
13761a11 NC |
1742 | op->mode = OP_REG; |
1743 | op->am = 0; | |
1744 | op->ol = 0; | |
1745 | return 0; | |
b18c562e | 1746 | } |
b18c562e NC |
1747 | |
1748 | /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */ | |
1749 | do | |
1750 | { | |
b18c562e NC |
1751 | op->mode = OP_EXP; |
1752 | op->reg = 0; /* PC relative... be careful. */ | |
13761a11 NC |
1753 | /* An expression starting with a minus sign is a constant, not an address. */ |
1754 | op->am = (*l == '-' ? 3 : 1); | |
b18c562e NC |
1755 | op->ol = 1; |
1756 | __tl = l; | |
1757 | parse_exp (__tl, &(op->exp)); | |
1758 | return 0; | |
1759 | } | |
1760 | while (0); | |
1761 | ||
1762 | /* Unreachable. */ | |
1763 | as_bad (_("unknown addressing mode for operand %s"), l); | |
1764 | return 1; | |
2469cfa2 NC |
1765 | } |
1766 | ||
b18c562e | 1767 | |
2469cfa2 | 1768 | static int |
13761a11 NC |
1769 | msp430_dstoperand (struct msp430_operand_s * op, |
1770 | char * l, | |
1771 | int bin, | |
1772 | bfd_boolean allow_20bit_values, | |
1773 | bfd_boolean constants_allowed) | |
2469cfa2 NC |
1774 | { |
1775 | int dummy; | |
13761a11 NC |
1776 | int ret = msp430_srcoperand (op, l, bin, & dummy, |
1777 | allow_20bit_values, | |
1778 | constants_allowed); | |
b18c562e | 1779 | |
2469cfa2 NC |
1780 | if (ret) |
1781 | return ret; | |
1782 | ||
1783 | if (op->am == 2) | |
1784 | { | |
1785 | char *__tl = "0"; | |
1786 | ||
1787 | op->mode = OP_EXP; | |
1788 | op->am = 1; | |
1789 | op->ol = 1; | |
1790 | parse_exp (__tl, &(op->exp)); | |
b18c562e | 1791 | |
2469cfa2 NC |
1792 | if (op->exp.X_op != O_constant || op->exp.X_add_number != 0) |
1793 | { | |
1794 | as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"), | |
1795 | op->reg, op->reg); | |
1796 | return 1; | |
1797 | } | |
1798 | return 0; | |
1799 | } | |
1800 | ||
1801 | if (op->am > 1) | |
1802 | { | |
1803 | as_bad (_ | |
1804 | ("this addressing mode is not applicable for destination operand")); | |
1805 | return 1; | |
1806 | } | |
1807 | return 0; | |
1808 | } | |
1809 | ||
1810 | ||
13761a11 NC |
1811 | /* Attempt to encode a MOVA instruction with the given operands. |
1812 | Returns the length of the encoded instruction if successful | |
1813 | or 0 upon failure. If the encoding fails, an error message | |
1814 | will be returned if a pointer is provided. */ | |
1815 | ||
1816 | static int | |
1817 | try_encode_mova (bfd_boolean imm_op, | |
1818 | int bin, | |
1819 | struct msp430_operand_s * op1, | |
1820 | struct msp430_operand_s * op2, | |
1821 | const char ** error_message_return) | |
1822 | { | |
1823 | short ZEROS = 0; | |
1824 | char *frag; | |
1825 | int where; | |
1826 | ||
1827 | /* Only a restricted subset of the normal MSP430 addressing modes | |
1828 | are supported here, so check for the ones that are allowed. */ | |
1829 | if (imm_op) | |
1830 | { | |
1831 | if (op1->mode == OP_EXP) | |
1832 | { | |
1833 | if (op2->mode != OP_REG) | |
1834 | { | |
1835 | if (error_message_return != NULL) | |
1836 | * error_message_return = _("expected register as second argument of %s"); | |
1837 | return 0; | |
1838 | } | |
1839 | ||
1840 | if (op1->am == 3) | |
1841 | { | |
1842 | /* MOVA #imm20, Rdst. */ | |
1843 | bin |= 0x80 | op2->reg; | |
1844 | frag = frag_more (4); | |
1845 | where = frag - frag_now->fr_literal; | |
1846 | if (op1->exp.X_op == O_constant) | |
1847 | { | |
1848 | bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8; | |
1849 | bfd_putl16 ((bfd_vma) bin, frag); | |
1850 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1851 | } | |
1852 | else | |
1853 | { | |
1854 | bfd_putl16 ((bfd_vma) bin, frag); | |
1855 | fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE, | |
1856 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
1857 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1858 | } | |
1859 | ||
1860 | return 4; | |
1861 | } | |
1862 | else if (op1->am == 1) | |
1863 | { | |
1864 | /* MOVA z16(Rsrc), Rdst. */ | |
1865 | bin |= 0x30 | (op1->reg << 8) | op2->reg; | |
1866 | frag = frag_more (4); | |
1867 | where = frag - frag_now->fr_literal; | |
1868 | bfd_putl16 ((bfd_vma) bin, frag); | |
1869 | if (op1->exp.X_op == O_constant) | |
1870 | { | |
1871 | if (op1->exp.X_add_number > 0xffff | |
1872 | || op1->exp.X_add_number < -(0x7fff)) | |
1873 | { | |
1874 | if (error_message_return != NULL) | |
1875 | * error_message_return = _("index value too big for %s"); | |
1876 | return 0; | |
1877 | } | |
1878 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1879 | } | |
1880 | else | |
1881 | { | |
1882 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1883 | fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE, | |
1884 | op1->reg == 0 ? | |
1885 | BFD_RELOC_MSP430X_PCR16 : | |
1886 | BFD_RELOC_MSP430X_ABS16); | |
1887 | } | |
1888 | return 4; | |
1889 | } | |
1890 | ||
1891 | if (error_message_return != NULL) | |
1892 | * error_message_return = _("unexpected addressing mode for %s"); | |
1893 | return 0; | |
1894 | } | |
1895 | else if (op1->am == 0) | |
1896 | { | |
1897 | /* MOVA Rsrc, ... */ | |
1898 | if (op2->mode == OP_REG) | |
1899 | { | |
1900 | bin |= 0xc0 | (op1->reg << 8) | op2->reg; | |
1901 | frag = frag_more (2); | |
1902 | where = frag - frag_now->fr_literal; | |
1903 | bfd_putl16 ((bfd_vma) bin, frag); | |
1904 | return 2; | |
1905 | } | |
1906 | else if (op2->am == 1) | |
1907 | { | |
1908 | if (op2->reg == 2) | |
1909 | { | |
1910 | /* MOVA Rsrc, &abs20. */ | |
1911 | bin |= 0x60 | (op1->reg << 8); | |
1912 | frag = frag_more (4); | |
1913 | where = frag - frag_now->fr_literal; | |
1914 | if (op2->exp.X_op == O_constant) | |
1915 | { | |
1916 | bin |= (op2->exp.X_add_number >> 16) & 0xf; | |
1917 | bfd_putl16 ((bfd_vma) bin, frag); | |
1918 | bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2); | |
1919 | } | |
1920 | else | |
1921 | { | |
1922 | bfd_putl16 ((bfd_vma) bin, frag); | |
1923 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1924 | fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE, | |
1925 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
1926 | } | |
1927 | return 4; | |
1928 | } | |
1929 | ||
1930 | /* MOVA Rsrc, z16(Rdst). */ | |
1931 | bin |= 0x70 | (op1->reg << 8) | op2->reg; | |
1932 | frag = frag_more (4); | |
1933 | where = frag - frag_now->fr_literal; | |
1934 | bfd_putl16 ((bfd_vma) bin, frag); | |
1935 | if (op2->exp.X_op == O_constant) | |
1936 | { | |
1937 | if (op2->exp.X_add_number > 0xffff | |
1938 | || op2->exp.X_add_number < -(0x7fff)) | |
1939 | { | |
1940 | if (error_message_return != NULL) | |
1941 | * error_message_return = _("index value too big for %s"); | |
1942 | return 0; | |
1943 | } | |
1944 | bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2); | |
1945 | } | |
1946 | else | |
1947 | { | |
1948 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1949 | fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE, | |
1950 | op2->reg == 0 ? | |
1951 | BFD_RELOC_MSP430X_PCR16 : | |
1952 | BFD_RELOC_MSP430X_ABS16); | |
1953 | } | |
1954 | return 4; | |
1955 | } | |
1956 | ||
1957 | if (error_message_return != NULL) | |
1958 | * error_message_return = _("unexpected addressing mode for %s"); | |
1959 | return 0; | |
1960 | } | |
1961 | } | |
1962 | ||
1963 | /* imm_op == FALSE. */ | |
1964 | ||
1965 | if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP) | |
1966 | { | |
1967 | /* MOVA &abs20, Rdst. */ | |
1968 | if (op2->mode != OP_REG) | |
1969 | { | |
1970 | if (error_message_return != NULL) | |
1971 | * error_message_return = _("expected register as second argument of %s"); | |
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | if (op2->reg == 2 || op2->reg == 3) | |
1976 | { | |
1977 | if (error_message_return != NULL) | |
1978 | * error_message_return = _("constant generator destination register found in %s"); | |
1979 | return 0; | |
1980 | } | |
1981 | ||
1982 | bin |= 0x20 | op2->reg; | |
1983 | frag = frag_more (4); | |
1984 | where = frag - frag_now->fr_literal; | |
1985 | if (op1->exp.X_op == O_constant) | |
1986 | { | |
1987 | bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8; | |
1988 | bfd_putl16 ((bfd_vma) bin, frag); | |
1989 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1990 | } | |
1991 | else | |
1992 | { | |
1993 | bfd_putl16 ((bfd_vma) bin, frag); | |
1994 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1995 | fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE, | |
1996 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
1997 | } | |
1998 | return 4; | |
1999 | } | |
2000 | else if (op1->mode == OP_REG) | |
2001 | { | |
2002 | if (op1->am == 3) | |
2003 | { | |
2004 | /* MOVA @Rsrc+, Rdst. */ | |
2005 | if (op2->mode != OP_REG) | |
2006 | { | |
2007 | if (error_message_return != NULL) | |
2008 | * error_message_return = _("expected register as second argument of %s"); | |
2009 | return 0; | |
2010 | } | |
2011 | ||
2012 | if (op2->reg == 2 || op2->reg == 3) | |
2013 | { | |
2014 | if (error_message_return != NULL) | |
2015 | * error_message_return = _("constant generator destination register found in %s"); | |
2016 | return 0; | |
2017 | } | |
2018 | ||
2019 | if (op1->reg == 2 || op1->reg == 3) | |
2020 | { | |
2021 | if (error_message_return != NULL) | |
2022 | * error_message_return = _("constant generator source register found in %s"); | |
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | bin |= 0x10 | (op1->reg << 8) | op2->reg; | |
2027 | frag = frag_more (2); | |
2028 | where = frag - frag_now->fr_literal; | |
2029 | bfd_putl16 ((bfd_vma) bin, frag); | |
2030 | return 2; | |
2031 | } | |
2032 | else if (op1->am == 2) | |
2033 | { | |
2034 | /* MOVA @Rsrc,Rdst */ | |
2035 | if (op2->mode != OP_REG) | |
2036 | { | |
2037 | if (error_message_return != NULL) | |
2038 | * error_message_return = _("expected register as second argument of %s"); | |
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | if (op2->reg == 2 || op2->reg == 3) | |
2043 | { | |
2044 | if (error_message_return != NULL) | |
2045 | * error_message_return = _("constant generator destination register found in %s"); | |
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | if (op1->reg == 2 || op1->reg == 3) | |
2050 | { | |
2051 | if (error_message_return != NULL) | |
2052 | * error_message_return = _("constant generator source register found in %s"); | |
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | bin |= (op1->reg << 8) | op2->reg; | |
2057 | frag = frag_more (2); | |
2058 | where = frag - frag_now->fr_literal; | |
2059 | bfd_putl16 ((bfd_vma) bin, frag); | |
2060 | return 2; | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | if (error_message_return != NULL) | |
2065 | * error_message_return = _("unexpected addressing mode for %s"); | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
638d3803 NC |
2070 | #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0) |
2071 | ||
b18c562e NC |
2072 | /* Parse instruction operands. |
2073 | Return binary opcode. */ | |
2074 | ||
2075 | static unsigned int | |
2076 | msp430_operands (struct msp430_opcode_s * opcode, char * line) | |
2469cfa2 | 2077 | { |
b18c562e | 2078 | int bin = opcode->bin_opcode; /* Opcode mask. */ |
13761a11 | 2079 | int insn_length = 0; |
b18c562e NC |
2080 | char l1[MAX_OP_LEN], l2[MAX_OP_LEN]; |
2081 | char *frag; | |
2082 | int where; | |
2083 | struct msp430_operand_s op1, op2; | |
2084 | int res = 0; | |
2085 | static short ZEROS = 0; | |
2086 | int byte_op, imm_op; | |
13761a11 NC |
2087 | int op_length = 0; |
2088 | int fmt; | |
2089 | int extended = 0x1800; | |
2090 | bfd_boolean extended_op = FALSE; | |
2091 | bfd_boolean addr_op; | |
2092 | const char * error_message; | |
2093 | static signed int repeat_count = 0; | |
2094 | bfd_boolean fix_emitted; | |
2469cfa2 | 2095 | |
b18c562e NC |
2096 | /* Opcode is the one from opcodes table |
2097 | line contains something like | |
2098 | [.w] @r2+, 5(R1) | |
2099 | or | |
2100 | .b @r2+, 5(R1). */ | |
2469cfa2 | 2101 | |
b18c562e NC |
2102 | /* Check if byte or word operation. */ |
2103 | if (*line == '.' && TOLOWER (*(line + 1)) == 'b') | |
2469cfa2 | 2104 | { |
b18c562e NC |
2105 | bin |= BYTE_OPERATION; |
2106 | byte_op = 1; | |
2469cfa2 | 2107 | } |
b18c562e NC |
2108 | else |
2109 | byte_op = 0; | |
2469cfa2 | 2110 | |
13761a11 NC |
2111 | /* "Address" ops work on 20-bit values. */ |
2112 | if (*line == '.' && TOLOWER (*(line + 1)) == 'a') | |
2113 | { | |
2114 | addr_op = TRUE; | |
2115 | bin |= BYTE_OPERATION; | |
2116 | } | |
2117 | else | |
2118 | addr_op = FALSE; | |
2119 | ||
2120 | /* skip .[aAbwBW]. */ | |
b18c562e NC |
2121 | while (! ISSPACE (*line) && *line) |
2122 | line++; | |
2469cfa2 | 2123 | |
13761a11 NC |
2124 | if (opcode->fmt != -1 |
2125 | && opcode->insn_opnumb | |
2126 | && (!*line || *line == '\n')) | |
2469cfa2 | 2127 | { |
b18c562e NC |
2128 | as_bad (_("instruction %s requires %d operand(s)"), |
2129 | opcode->name, opcode->insn_opnumb); | |
2130 | return 0; | |
2131 | } | |
2469cfa2 | 2132 | |
b18c562e NC |
2133 | memset (l1, 0, sizeof (l1)); |
2134 | memset (l2, 0, sizeof (l2)); | |
2135 | memset (&op1, 0, sizeof (op1)); | |
2136 | memset (&op2, 0, sizeof (op2)); | |
2469cfa2 | 2137 | |
b18c562e | 2138 | imm_op = 0; |
2469cfa2 | 2139 | |
13761a11 NC |
2140 | if ((fmt = opcode->fmt) < 0) |
2141 | { | |
638d3803 | 2142 | if (! target_is_430x ()) |
13761a11 NC |
2143 | { |
2144 | as_bad (_("instruction %s requires MSP430X mcu"), | |
2145 | opcode->name); | |
2146 | return 0; | |
2147 | } | |
638d3803 | 2148 | |
13761a11 NC |
2149 | fmt = (-fmt) - 1; |
2150 | extended_op = TRUE; | |
2151 | } | |
2152 | ||
2153 | if (repeat_count) | |
2154 | { | |
2155 | /* If requested set the extended instruction repeat count. */ | |
2156 | if (extended_op) | |
2157 | { | |
2158 | if (repeat_count > 0) | |
2159 | extended |= (repeat_count - 1); | |
2160 | else | |
2161 | extended |= (1 << 7) | (- repeat_count); | |
2162 | } | |
2163 | else | |
2164 | as_bad (_("unable to repeat %s insn"), opcode->name); | |
2165 | ||
2166 | repeat_count = 0; | |
2167 | } | |
2168 | ||
2169 | switch (fmt) | |
b18c562e NC |
2170 | { |
2171 | case 0: /* Emulated. */ | |
2172 | switch (opcode->insn_opnumb) | |
2469cfa2 | 2173 | { |
b18c562e NC |
2174 | case 0: |
2175 | /* Set/clear bits instructions. */ | |
13761a11 NC |
2176 | if (extended_op) |
2177 | { | |
2178 | if (!addr_op) | |
2179 | extended |= BYTE_OPERATION; | |
2180 | ||
2181 | /* Emit the extension word. */ | |
2182 | insn_length += 2; | |
2183 | frag = frag_more (insn_length); | |
2184 | bfd_putl16 (extended, frag); | |
2185 | } | |
638d3803 | 2186 | |
13761a11 NC |
2187 | insn_length += 2; |
2188 | frag = frag_more (insn_length); | |
b18c562e | 2189 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2190 | |
2191 | if (gen_interrupt_nops | |
638d3803 NC |
2192 | && target_is_430xv2 () |
2193 | && (is_opcode ("eint") || is_opcode ("dint"))) | |
13761a11 NC |
2194 | { |
2195 | /* Emit a NOP following interrupt enable/disable. | |
2196 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
2197 | insn_length += 2; | |
2198 | frag = frag_more (2); | |
2199 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
2200 | } | |
13761a11 | 2201 | dwarf2_emit_insn (insn_length); |
b18c562e | 2202 | break; |
13761a11 | 2203 | |
b18c562e NC |
2204 | case 1: |
2205 | /* Something which works with destination operand. */ | |
2206 | line = extract_operand (line, l1, sizeof (l1)); | |
13761a11 | 2207 | res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE); |
b18c562e NC |
2208 | if (res) |
2209 | break; | |
2469cfa2 | 2210 | |
13761a11 NC |
2211 | /* Compute the entire instruction length, in bytes. */ |
2212 | insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); | |
2213 | frag = frag_more (insn_length); | |
b18c562e | 2214 | where = frag - frag_now->fr_literal; |
638d3803 | 2215 | |
13761a11 | 2216 | if (extended_op) |
2469cfa2 | 2217 | { |
13761a11 NC |
2218 | if (!addr_op) |
2219 | extended |= BYTE_OPERATION; | |
2220 | ||
2221 | if (op1.ol != 0 && ((extended & 0xf) != 0)) | |
2222 | { | |
2223 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2224 | extended &= ~ 0xf; | |
2225 | } | |
638d3803 | 2226 | |
13761a11 NC |
2227 | if (op1.mode == OP_EXP) |
2228 | { | |
2229 | if (op1.exp.X_op == O_constant) | |
2230 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2231 | ||
2232 | else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
2233 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2234 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2235 | else | |
2236 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2237 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2238 | } | |
638d3803 | 2239 | |
13761a11 NC |
2240 | /* Emit the extension word. */ |
2241 | bfd_putl16 (extended, frag); | |
2242 | frag += 2; | |
2243 | where += 2; | |
2244 | } | |
2245 | ||
2246 | bin |= (op1.reg | (op1.am << 7)); | |
2247 | bfd_putl16 ((bfd_vma) bin, frag); | |
2248 | frag += 2; | |
2249 | where += 2; | |
2250 | ||
2251 | if (op1.mode == OP_EXP) | |
2252 | { | |
2253 | if (op1.exp.X_op == O_constant) | |
2254 | { | |
2255 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2256 | } | |
2469cfa2 | 2257 | else |
13761a11 NC |
2258 | { |
2259 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2260 | ||
2261 | if (!extended_op) | |
2262 | { | |
2263 | if (op1.reg) | |
2264 | fix_new_exp (frag_now, where, 2, | |
2265 | &(op1.exp), FALSE, CHECK_RELOC_MSP430); | |
2266 | else | |
2267 | fix_new_exp (frag_now, where, 2, | |
2268 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2269 | } | |
2270 | } | |
2271 | } | |
2272 | ||
2273 | if (gen_interrupt_nops | |
638d3803 NC |
2274 | && target_is_430xv2 () |
2275 | && is_opcode ("clr") | |
13761a11 NC |
2276 | && bin == 0x4302 /* CLR R2*/) |
2277 | { | |
2278 | /* Emit a NOP following interrupt enable/disable. | |
2279 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
2280 | insn_length += 2; | |
2281 | frag = frag_more (2); | |
2282 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
2469cfa2 | 2283 | } |
13761a11 NC |
2284 | |
2285 | dwarf2_emit_insn (insn_length); | |
b18c562e | 2286 | break; |
2469cfa2 | 2287 | |
b18c562e | 2288 | case 2: |
13761a11 NC |
2289 | /* Shift instruction. */ |
2290 | line = extract_operand (line, l1, sizeof (l1)); | |
2291 | strncpy (l2, l1, sizeof (l2)); | |
2292 | l2[sizeof (l2) - 1] = '\0'; | |
2293 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE); | |
2294 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE); | |
2295 | ||
2296 | if (res) | |
2297 | break; /* An error occurred. All warnings were done before. */ | |
2298 | ||
2299 | insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2); | |
2300 | frag = frag_more (insn_length); | |
2301 | where = frag - frag_now->fr_literal; | |
2302 | ||
638d3803 NC |
2303 | /* Issue 3831743. */ |
2304 | if (op1.mode == OP_REG | |
2305 | && op1.reg == 0 | |
2306 | && (is_opcode ("rlax") | |
2307 | || is_opcode ("rlcx") | |
2308 | || is_opcode ("rla") | |
2309 | || is_opcode ("rlc"))) | |
2310 | { | |
2311 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
2312 | return 0; | |
2313 | } | |
2314 | ||
13761a11 NC |
2315 | if (extended_op) |
2316 | { | |
2317 | if (!addr_op) | |
2318 | extended |= BYTE_OPERATION; | |
2319 | ||
2320 | if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0)) | |
2321 | { | |
2322 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2323 | extended &= ~ 0xf; | |
2324 | } | |
638d3803 | 2325 | |
13761a11 NC |
2326 | if (op1.mode == OP_EXP) |
2327 | { | |
2328 | if (op1.exp.X_op == O_constant) | |
2329 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2330 | ||
2331 | else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
2332 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2333 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2334 | else | |
2335 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2336 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2337 | } | |
2338 | ||
2339 | if (op2.mode == OP_EXP) | |
2340 | { | |
2341 | if (op2.exp.X_op == O_constant) | |
2342 | extended |= (op2.exp.X_add_number >> 16) & 0xf; | |
2343 | ||
2344 | else if (op1.mode == OP_EXP) | |
2345 | fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE, | |
2346 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST | |
2347 | : BFD_RELOC_MSP430X_PCR20_EXT_ODST); | |
2348 | else | |
2349 | fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE, | |
2350 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST | |
2351 | : BFD_RELOC_MSP430X_PCR20_EXT_DST); | |
2352 | } | |
2353 | ||
2354 | /* Emit the extension word. */ | |
2355 | bfd_putl16 (extended, frag); | |
2356 | frag += 2; | |
2357 | where += 2; | |
2358 | } | |
2359 | ||
2360 | bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); | |
2361 | bfd_putl16 ((bfd_vma) bin, frag); | |
2362 | frag += 2; | |
2363 | where += 2; | |
2364 | ||
2365 | if (op1.mode == OP_EXP) | |
2366 | { | |
2367 | if (op1.exp.X_op == O_constant) | |
2368 | { | |
2369 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2370 | } | |
2371 | else | |
2372 | { | |
2373 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2374 | ||
2375 | if (!extended_op) | |
2376 | { | |
2377 | if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
2378 | fix_new_exp (frag_now, where, 2, | |
2379 | &(op1.exp), FALSE, CHECK_RELOC_MSP430); | |
2380 | else | |
2381 | fix_new_exp (frag_now, where, 2, | |
2382 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2383 | } | |
2384 | } | |
2385 | frag += 2; | |
2386 | where += 2; | |
2387 | } | |
2388 | ||
2389 | if (op2.mode == OP_EXP) | |
2390 | { | |
2391 | if (op2.exp.X_op == O_constant) | |
2392 | { | |
2393 | bfd_putl16 (op2.exp.X_add_number & 0xffff, frag); | |
2394 | } | |
2395 | else | |
2396 | { | |
2397 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2398 | ||
2399 | if (!extended_op) | |
2400 | { | |
2401 | if (op2.reg) /* Not PC relative. */ | |
2402 | fix_new_exp (frag_now, where, 2, | |
2403 | &(op2.exp), FALSE, CHECK_RELOC_MSP430); | |
2404 | else | |
2405 | fix_new_exp (frag_now, where, 2, | |
2406 | &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2407 | } | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | dwarf2_emit_insn (insn_length); | |
2412 | break; | |
2413 | ||
2414 | case 3: | |
2415 | /* Branch instruction => mov dst, r0. */ | |
2416 | if (extended_op) | |
2417 | { | |
2418 | as_bad ("Internal error: state 0/3 not coded for extended instructions"); | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | line = extract_operand (line, l1, sizeof (l1)); | |
2423 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE); | |
2424 | if (res) | |
2425 | break; | |
2426 | ||
2427 | byte_op = 0; | |
2428 | imm_op = 0; | |
2429 | bin |= ((op1.reg << 8) | (op1.am << 4)); | |
2430 | op_length = 2 + 2 * op1.ol; | |
2431 | frag = frag_more (op_length); | |
2432 | where = frag - frag_now->fr_literal; | |
2433 | bfd_putl16 ((bfd_vma) bin, frag); | |
2434 | ||
2435 | if (op1.mode == OP_EXP) | |
2436 | { | |
2437 | if (op1.exp.X_op == O_constant) | |
2438 | { | |
2439 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2); | |
2440 | } | |
2441 | else | |
2442 | { | |
2443 | where += 2; | |
638d3803 | 2444 | |
13761a11 NC |
2445 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); |
2446 | ||
2447 | if (op1.reg || (op1.reg == 0 && op1.am == 3)) | |
2448 | fix_new_exp (frag_now, where, 2, | |
2449 | &(op1.exp), FALSE, CHECK_RELOC_MSP430); | |
2450 | else | |
2451 | fix_new_exp (frag_now, where, 2, | |
2452 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2453 | } | |
2454 | } | |
2455 | ||
2456 | dwarf2_emit_insn (insn_length + op_length); | |
2457 | break; | |
2458 | ||
2459 | case 4: | |
2460 | /* CALLA instructions. */ | |
2461 | fix_emitted = FALSE; | |
2462 | ||
2463 | line = extract_operand (line, l1, sizeof (l1)); | |
2464 | imm_op = 0; | |
2465 | ||
2466 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, | |
2467 | extended_op, FALSE); | |
2468 | if (res) | |
2469 | break; | |
2470 | ||
2471 | byte_op = 0; | |
2472 | ||
2473 | op_length = 2 + 2 * op1.ol; | |
2474 | frag = frag_more (op_length); | |
2475 | where = frag - frag_now->fr_literal; | |
2476 | ||
2477 | if (imm_op) | |
2478 | { | |
2479 | if (op1.am == 3) | |
2480 | { | |
2481 | bin |= 0xb0; | |
2482 | ||
2483 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2484 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
2485 | fix_emitted = TRUE; | |
2486 | } | |
2487 | else if (op1.am == 1) | |
2488 | { | |
2489 | if (op1.reg == 0) | |
2490 | { | |
2491 | bin |= 0x90; | |
2492 | ||
2493 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2494 | BFD_RELOC_MSP430X_PCR20_CALL); | |
2495 | fix_emitted = TRUE; | |
2496 | } | |
2497 | else | |
2498 | bin |= 0x50 | op1.reg; | |
2499 | } | |
2500 | else if (op1.am == 0) | |
2501 | bin |= 0x40 | op1.reg; | |
2502 | } | |
2503 | else if (op1.am == 1) | |
2504 | { | |
2505 | bin |= 0x80; | |
2506 | ||
2507 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2508 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
2509 | fix_emitted = TRUE; | |
2510 | } | |
2511 | else if (op1.am == 2) | |
2512 | bin |= 0x60 | op1.reg; | |
2513 | else if (op1.am == 3) | |
2514 | bin |= 0x70 | op1.reg; | |
638d3803 | 2515 | |
13761a11 NC |
2516 | bfd_putl16 ((bfd_vma) bin, frag); |
2517 | ||
2518 | if (op1.mode == OP_EXP) | |
2519 | { | |
2520 | if (op1.ol != 1) | |
2521 | { | |
2522 | as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol); | |
2523 | return 0; | |
2524 | } | |
2525 | ||
2526 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
2527 | ||
2528 | if (! fix_emitted) | |
2529 | fix_new_exp (frag_now, where + 2, 2, | |
2530 | &(op1.exp), FALSE, BFD_RELOC_16); | |
2531 | } | |
2532 | ||
2533 | dwarf2_emit_insn (insn_length + op_length); | |
2534 | break; | |
2535 | ||
2536 | case 5: | |
b18c562e | 2537 | { |
13761a11 NC |
2538 | int n; |
2539 | int reg; | |
2540 | ||
2541 | /* [POP|PUSH]M[.A] #N, Rd */ | |
b18c562e | 2542 | line = extract_operand (line, l1, sizeof (l1)); |
13761a11 | 2543 | line = extract_operand (line, l2, sizeof (l2)); |
2469cfa2 | 2544 | |
13761a11 NC |
2545 | if (*l1 != '#') |
2546 | { | |
638d3803 | 2547 | as_bad (_("expected #n as first argument of %s"), opcode->name); |
13761a11 NC |
2548 | return 0; |
2549 | } | |
2550 | parse_exp (l1 + 1, &(op1.exp)); | |
2551 | if (op1.exp.X_op != O_constant) | |
2552 | { | |
2553 | as_bad (_("expected constant expression for first argument of %s"), | |
2554 | opcode->name); | |
2555 | return 0; | |
2556 | } | |
2469cfa2 | 2557 | |
13761a11 NC |
2558 | if ((reg = check_reg (l2)) == -1) |
2559 | { | |
2560 | as_bad (_("expected register as second argument of %s"), | |
2561 | opcode->name); | |
2562 | return 0; | |
2563 | } | |
2469cfa2 | 2564 | |
13761a11 NC |
2565 | op_length = 2; |
2566 | frag = frag_more (op_length); | |
b18c562e | 2567 | where = frag - frag_now->fr_literal; |
13761a11 NC |
2568 | bin = opcode->bin_opcode; |
2569 | if (! addr_op) | |
2570 | bin |= 0x100; | |
2571 | n = op1.exp.X_add_number; | |
2572 | bin |= (n - 1) << 4; | |
638d3803 | 2573 | if (is_opcode ("pushm")) |
13761a11 NC |
2574 | bin |= reg; |
2575 | else | |
2576 | { | |
2577 | if (reg - n + 1 < 0) | |
2578 | { | |
2579 | as_bad (_("Too many registers popped")); | |
2580 | return 0; | |
2581 | } | |
638d3803 NC |
2582 | |
2583 | /* Issue 3831713: CPU21 parts cannot use POPM to restore the SR register. */ | |
2584 | if (target_is_430x () | |
2585 | && (reg - n + 1 < 3) | |
2586 | && reg >= 2 | |
2587 | && is_opcode ("popm")) | |
2588 | { | |
2589 | as_bad (_("Cannot use POPM to restore the SR register")); | |
2590 | return 0; | |
2591 | } | |
2592 | ||
13761a11 NC |
2593 | bin |= (reg - n + 1); |
2594 | } | |
2595 | ||
b18c562e | 2596 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2597 | dwarf2_emit_insn (op_length); |
2598 | break; | |
2599 | } | |
2600 | ||
2601 | case 6: | |
2602 | { | |
2603 | int n; | |
2604 | int reg; | |
2605 | ||
2606 | /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */ | |
2607 | if (extended & 0xff) | |
2608 | { | |
2609 | as_bad (_("repeat count cannot be used with %s"), opcode->name); | |
2610 | return 0; | |
2611 | } | |
2612 | ||
2613 | line = extract_operand (line, l1, sizeof (l1)); | |
2614 | line = extract_operand (line, l2, sizeof (l2)); | |
2615 | ||
2616 | if (*l1 != '#') | |
2617 | { | |
2618 | as_bad (_("expected #n as first argument of %s"), opcode->name); | |
2619 | return 0; | |
2620 | } | |
2621 | parse_exp (l1 + 1, &(op1.exp)); | |
2622 | if (op1.exp.X_op != O_constant) | |
2623 | { | |
2624 | as_bad (_("expected constant expression for first argument of %s"), | |
2625 | opcode->name); | |
2626 | return 0; | |
2627 | } | |
2628 | n = op1.exp.X_add_number; | |
2629 | if (n > 4 || n < 1) | |
b18c562e | 2630 | { |
13761a11 NC |
2631 | as_bad (_("expected first argument of %s to be in the range 1-4"), |
2632 | opcode->name); | |
2633 | return 0; | |
2634 | } | |
b18c562e | 2635 | |
13761a11 NC |
2636 | if ((reg = check_reg (l2)) == -1) |
2637 | { | |
2638 | as_bad (_("expected register as second argument of %s"), | |
2639 | opcode->name); | |
2640 | return 0; | |
b18c562e NC |
2641 | } |
2642 | ||
638d3803 NC |
2643 | /* Issue 3831743. */ |
2644 | if (reg == 0) | |
2645 | { | |
2646 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
2647 | return 0; | |
2648 | } | |
2649 | ||
13761a11 NC |
2650 | op_length = 2; |
2651 | frag = frag_more (op_length); | |
2652 | where = frag - frag_now->fr_literal; | |
2653 | ||
2654 | bin = opcode->bin_opcode; | |
2655 | if (! addr_op) | |
2656 | bin |= 0x10; | |
2657 | bin |= (n - 1) << 10; | |
2658 | bin |= reg; | |
2659 | ||
2660 | bfd_putl16 ((bfd_vma) bin, frag); | |
2661 | dwarf2_emit_insn (op_length); | |
2662 | break; | |
2663 | } | |
2664 | ||
2665 | case 7: | |
2666 | { | |
2667 | int reg; | |
2668 | ||
2669 | /* RRUX: Synthetic unsigned right shift of a register by one bit. */ | |
2670 | if (extended & 0xff) | |
b18c562e | 2671 | { |
13761a11 NC |
2672 | as_bad (_("repeat count cannot be used with %s"), opcode->name); |
2673 | return 0; | |
2674 | } | |
b18c562e | 2675 | |
13761a11 NC |
2676 | line = extract_operand (line, l1, sizeof (l1)); |
2677 | if ((reg = check_reg (l1)) == -1) | |
2678 | { | |
2679 | as_bad (_("expected register as argument of %s"), | |
2680 | opcode->name); | |
2681 | return 0; | |
2682 | } | |
2683 | ||
638d3803 NC |
2684 | /* Issue 3831743. */ |
2685 | if (reg == 0) | |
2686 | { | |
2687 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
2688 | return 0; | |
2689 | } | |
2690 | ||
13761a11 NC |
2691 | if (byte_op) |
2692 | { | |
2693 | /* Tricky - there is no single instruction that will do this. | |
2694 | Encode as: RRA.B rN { BIC.B #0x80, rN */ | |
2695 | op_length = 6; | |
2696 | frag = frag_more (op_length); | |
2697 | where = frag - frag_now->fr_literal; | |
2698 | bin = 0x1140 | reg; | |
2699 | bfd_putl16 ((bfd_vma) bin, frag); | |
2700 | dwarf2_emit_insn (2); | |
2701 | bin = 0xc070 | reg; | |
2702 | bfd_putl16 ((bfd_vma) bin, frag + 2); | |
2703 | bin = 0x0080; | |
2704 | bfd_putl16 ((bfd_vma) bin, frag + 4); | |
2705 | dwarf2_emit_insn (4); | |
2706 | } | |
2707 | else | |
2708 | { | |
2709 | /* Encode as RRUM[.A] rN. */ | |
2710 | bin = opcode->bin_opcode; | |
2711 | if (! addr_op) | |
2712 | bin |= 0x10; | |
2713 | bin |= reg; | |
2714 | op_length = 2; | |
2715 | frag = frag_more (op_length); | |
2716 | where = frag - frag_now->fr_literal; | |
2717 | bfd_putl16 ((bfd_vma) bin, frag); | |
2718 | dwarf2_emit_insn (op_length); | |
638d3803 | 2719 | } |
b18c562e NC |
2720 | break; |
2721 | } | |
b18c562e | 2722 | |
13761a11 NC |
2723 | case 8: |
2724 | { | |
2725 | bfd_boolean need_reloc = FALSE; | |
2726 | int n; | |
2727 | int reg; | |
2728 | ||
2729 | /* ADDA, CMPA and SUBA address instructions. */ | |
2730 | if (extended & 0xff) | |
2731 | { | |
2732 | as_bad (_("repeat count cannot be used with %s"), opcode->name); | |
2733 | return 0; | |
2734 | } | |
2735 | ||
2736 | line = extract_operand (line, l1, sizeof (l1)); | |
2737 | line = extract_operand (line, l2, sizeof (l2)); | |
2738 | ||
2739 | bin = opcode->bin_opcode; | |
2740 | ||
2741 | if (*l1 == '#') | |
2742 | { | |
2743 | parse_exp (l1 + 1, &(op1.exp)); | |
2744 | ||
2745 | if (op1.exp.X_op == O_constant) | |
2746 | { | |
2747 | n = op1.exp.X_add_number; | |
2748 | if (n > 0xfffff || n < - (0x7ffff)) | |
2749 | { | |
2750 | as_bad (_("expected value of first argument of %s to fit into 20-bits"), | |
2751 | opcode->name); | |
2752 | return 0; | |
2753 | } | |
2754 | ||
2755 | bin |= ((n >> 16) & 0xf) << 8; | |
2756 | } | |
2757 | else | |
2758 | { | |
2759 | n = 0; | |
2760 | need_reloc = TRUE; | |
2761 | } | |
2762 | ||
2763 | op_length = 4; | |
2764 | } | |
2765 | else | |
2766 | { | |
2767 | if ((n = check_reg (l1)) == -1) | |
2768 | { | |
2769 | as_bad (_("expected register name or constant as first argument of %s"), | |
2770 | opcode->name); | |
2771 | return 0; | |
2772 | } | |
2773 | ||
2774 | bin |= (n << 8) | (1 << 6); | |
2775 | op_length = 2; | |
2776 | } | |
2777 | ||
2778 | if ((reg = check_reg (l2)) == -1) | |
2779 | { | |
2780 | as_bad (_("expected register as second argument of %s"), | |
2781 | opcode->name); | |
2782 | return 0; | |
2783 | } | |
2784 | ||
2785 | frag = frag_more (op_length); | |
2786 | where = frag - frag_now->fr_literal; | |
2787 | bin |= reg; | |
2788 | if (need_reloc) | |
2789 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2790 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
2791 | ||
2792 | bfd_putl16 ((bfd_vma) bin, frag); | |
2793 | if (op_length == 4) | |
2794 | bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2); | |
2795 | dwarf2_emit_insn (op_length); | |
b18c562e | 2796 | break; |
13761a11 | 2797 | } |
638d3803 | 2798 | |
13761a11 | 2799 | case 9: /* MOVA, BRA, RETA. */ |
b18c562e | 2800 | imm_op = 0; |
13761a11 | 2801 | bin = opcode->bin_opcode; |
b18c562e | 2802 | |
638d3803 | 2803 | if (is_opcode ("reta")) |
13761a11 NC |
2804 | { |
2805 | /* The RETA instruction does not take any arguments. | |
2806 | The implicit first argument is @SP+. | |
2807 | The implicit second argument is PC. */ | |
2808 | op1.mode = OP_REG; | |
2809 | op1.am = 3; | |
2810 | op1.reg = 1; | |
2811 | ||
2812 | op2.mode = OP_REG; | |
2813 | op2.reg = 0; | |
2814 | } | |
2815 | else | |
2816 | { | |
2817 | line = extract_operand (line, l1, sizeof (l1)); | |
2818 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, | |
2819 | &imm_op, extended_op, FALSE); | |
b18c562e | 2820 | |
638d3803 | 2821 | if (is_opcode ("bra")) |
13761a11 NC |
2822 | { |
2823 | /* This is the BRA synthetic instruction. | |
2824 | The second argument is always PC. */ | |
2825 | op2.mode = OP_REG; | |
2826 | op2.reg = 0; | |
2827 | } | |
2828 | else | |
2829 | { | |
2830 | line = extract_operand (line, l2, sizeof (l2)); | |
2831 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, | |
2832 | extended_op, TRUE); | |
2833 | } | |
638d3803 | 2834 | |
13761a11 NC |
2835 | if (res) |
2836 | break; /* Error occurred. All warnings were done before. */ | |
2837 | } | |
2838 | ||
2839 | /* Only a restricted subset of the normal MSP430 addressing modes | |
2840 | are supported here, so check for the ones that are allowed. */ | |
2841 | if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2, | |
2842 | & error_message)) == 0) | |
2469cfa2 | 2843 | { |
13761a11 NC |
2844 | as_bad (error_message, opcode->name); |
2845 | return 0; | |
2846 | } | |
2847 | dwarf2_emit_insn (op_length); | |
2848 | break; | |
2849 | ||
2850 | case 10: /* RPT */ | |
2851 | line = extract_operand (line, l1, sizeof l1); | |
2852 | /* The RPT instruction only accepted immediates and registers. */ | |
2853 | if (*l1 == '#') | |
2854 | { | |
2855 | parse_exp (l1 + 1, &(op1.exp)); | |
2856 | if (op1.exp.X_op != O_constant) | |
2857 | { | |
2858 | as_bad (_("expected constant value as argument to RPT")); | |
2859 | return 0; | |
2860 | } | |
2861 | if (op1.exp.X_add_number < 1 | |
2862 | || op1.exp.X_add_number > (1 << 4)) | |
2863 | { | |
2864 | as_bad (_("expected constant in the range 2..16")); | |
2865 | return 0; | |
2866 | } | |
2867 | ||
2868 | /* We silently accept and ignore a repeat count of 1. */ | |
2869 | if (op1.exp.X_add_number > 1) | |
2870 | repeat_count = op1.exp.X_add_number; | |
2871 | } | |
2872 | else | |
2873 | { | |
2874 | int reg; | |
b18c562e | 2875 | |
13761a11 NC |
2876 | if ((reg = check_reg (l1)) != -1) |
2877 | { | |
2878 | if (reg == 0) | |
2879 | as_warn (_("PC used as an argument to RPT")); | |
2880 | else | |
2881 | repeat_count = - reg; | |
2882 | } | |
2469cfa2 | 2883 | else |
13761a11 NC |
2884 | { |
2885 | as_bad (_("expected constant or register name as argument to RPT insn")); | |
2886 | return 0; | |
2887 | } | |
2469cfa2 | 2888 | } |
b18c562e | 2889 | break; |
13761a11 NC |
2890 | |
2891 | default: | |
2892 | as_bad (_("Illegal emulated instruction ")); | |
2893 | break; | |
2469cfa2 | 2894 | } |
b18c562e | 2895 | break; |
2469cfa2 | 2896 | |
b18c562e NC |
2897 | case 1: /* Format 1, double operand. */ |
2898 | line = extract_operand (line, l1, sizeof (l1)); | |
2899 | line = extract_operand (line, l2, sizeof (l2)); | |
13761a11 NC |
2900 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE); |
2901 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE); | |
2469cfa2 | 2902 | |
b18c562e NC |
2903 | if (res) |
2904 | break; /* Error occurred. All warnings were done before. */ | |
2469cfa2 | 2905 | |
13761a11 | 2906 | if (extended_op |
638d3803 | 2907 | && is_opcode ("movx") |
13761a11 NC |
2908 | && addr_op |
2909 | && msp430_enable_relax) | |
2910 | { | |
2911 | /* This is the MOVX.A instruction. See if we can convert | |
2912 | it into the MOVA instruction instead. This saves 2 bytes. */ | |
2913 | if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2, | |
2914 | NULL)) != 0) | |
2915 | { | |
2916 | dwarf2_emit_insn (op_length); | |
2917 | break; | |
2918 | } | |
2919 | } | |
2920 | ||
2921 | /* Compute the entire length of the instruction in bytes. */ | |
2922 | insn_length = | |
2923 | (extended_op ? 2 : 0) /* The extension word. */ | |
2924 | + 2 /* The opcode */ | |
2925 | + (2 * op1.ol) /* The first operand. */ | |
2926 | + (2 * op2.ol); /* The second operand. */ | |
b18c562e | 2927 | |
13761a11 | 2928 | frag = frag_more (insn_length); |
b18c562e | 2929 | where = frag - frag_now->fr_literal; |
638d3803 | 2930 | |
13761a11 NC |
2931 | if (extended_op) |
2932 | { | |
2933 | if (!addr_op) | |
2934 | extended |= BYTE_OPERATION; | |
2935 | ||
2936 | if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0)) | |
2937 | { | |
2938 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2939 | extended &= ~ 0xf; | |
2940 | } | |
2941 | ||
2942 | /* If necessary, emit a reloc to update the extension word. */ | |
2943 | if (op1.mode == OP_EXP) | |
2944 | { | |
2945 | if (op1.exp.X_op == O_constant) | |
2946 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2947 | ||
2948 | else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
2949 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2950 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2951 | else | |
2952 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2953 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2954 | } | |
638d3803 | 2955 | |
13761a11 NC |
2956 | if (op2.mode == OP_EXP) |
2957 | { | |
2958 | if (op2.exp.X_op == O_constant) | |
2959 | extended |= (op2.exp.X_add_number >> 16) & 0xf; | |
2960 | ||
2961 | else if (op1.mode == OP_EXP) | |
2962 | fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE, | |
2963 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST | |
2964 | : BFD_RELOC_MSP430X_PCR20_EXT_ODST); | |
638d3803 | 2965 | |
13761a11 NC |
2966 | else |
2967 | fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE, | |
2968 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST | |
2969 | : BFD_RELOC_MSP430X_PCR20_EXT_DST); | |
2970 | } | |
2971 | ||
2972 | /* Emit the extension word. */ | |
2973 | bfd_putl16 (extended, frag); | |
2974 | where += 2; | |
2975 | frag += 2; | |
2976 | } | |
2977 | ||
2978 | bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); | |
b18c562e | 2979 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2980 | where += 2; |
2981 | frag += 2; | |
b18c562e NC |
2982 | |
2983 | if (op1.mode == OP_EXP) | |
2469cfa2 | 2984 | { |
13761a11 NC |
2985 | if (op1.exp.X_op == O_constant) |
2986 | { | |
2987 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2988 | } | |
b18c562e | 2989 | else |
13761a11 NC |
2990 | { |
2991 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2992 | ||
2993 | if (!extended_op) | |
2994 | { | |
2995 | if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
2996 | fix_new_exp (frag_now, where, 2, | |
2997 | &(op1.exp), FALSE, CHECK_RELOC_MSP430); | |
2998 | else | |
2999 | fix_new_exp (frag_now, where, 2, | |
3000 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
3001 | } | |
3002 | } | |
3003 | ||
3004 | where += 2; | |
3005 | frag += 2; | |
2469cfa2 | 3006 | } |
b18c562e NC |
3007 | |
3008 | if (op2.mode == OP_EXP) | |
2469cfa2 | 3009 | { |
13761a11 NC |
3010 | if (op2.exp.X_op == O_constant) |
3011 | { | |
3012 | bfd_putl16 (op2.exp.X_add_number & 0xffff, frag); | |
3013 | } | |
b18c562e | 3014 | else |
13761a11 NC |
3015 | { |
3016 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
3017 | ||
3018 | if (!extended_op) | |
3019 | { | |
3020 | if (op2.reg) /* Not PC relative. */ | |
3021 | fix_new_exp (frag_now, where, 2, | |
3022 | &(op2.exp), FALSE, CHECK_RELOC_MSP430); | |
3023 | else | |
3024 | fix_new_exp (frag_now, where, 2, | |
3025 | &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
3026 | } | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | if (gen_interrupt_nops | |
638d3803 NC |
3031 | && target_is_430xv2 () |
3032 | && ( (is_opcode ("bic") && bin == 0xc232) | |
3033 | || (is_opcode ("bis") && bin == 0xd232) | |
3034 | || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))) | |
13761a11 NC |
3035 | { |
3036 | /* Emit a NOP following interrupt enable/disable. | |
3037 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
3038 | insn_length += 2; | |
3039 | frag = frag_more (2); | |
3040 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
2469cfa2 | 3041 | } |
13761a11 NC |
3042 | |
3043 | dwarf2_emit_insn (insn_length); | |
b18c562e NC |
3044 | break; |
3045 | ||
3046 | case 2: /* Single-operand mostly instr. */ | |
3047 | if (opcode->insn_opnumb == 0) | |
2469cfa2 | 3048 | { |
b18c562e | 3049 | /* reti instruction. */ |
13761a11 | 3050 | insn_length += 2; |
b18c562e NC |
3051 | frag = frag_more (2); |
3052 | bfd_putl16 ((bfd_vma) bin, frag); | |
13761a11 | 3053 | dwarf2_emit_insn (insn_length); |
b18c562e | 3054 | break; |
2469cfa2 | 3055 | } |
2469cfa2 | 3056 | |
b18c562e | 3057 | line = extract_operand (line, l1, sizeof (l1)); |
13761a11 NC |
3058 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, |
3059 | &imm_op, extended_op, TRUE); | |
b18c562e NC |
3060 | if (res) |
3061 | break; /* Error in operand. */ | |
2469cfa2 | 3062 | |
638d3803 NC |
3063 | /* Issue 3831743. */ |
3064 | if (op1.mode == OP_REG | |
3065 | && op1.reg == 0 | |
3066 | && (is_opcode ("rrax") | |
3067 | || is_opcode ("rrcx") | |
3068 | || is_opcode ("rra") | |
3069 | || is_opcode ("rrc"))) | |
3070 | { | |
3071 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
3072 | return 0; | |
3073 | } | |
3074 | ||
13761a11 NC |
3075 | insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); |
3076 | frag = frag_more (insn_length); | |
b18c562e | 3077 | where = frag - frag_now->fr_literal; |
638d3803 | 3078 | |
13761a11 NC |
3079 | if (extended_op) |
3080 | { | |
638d3803 | 3081 | if (is_opcode ("swpbx") || is_opcode ("sxtx")) |
13761a11 NC |
3082 | { |
3083 | /* These two instructions use a special | |
3084 | encoding of the A/L and B/W bits. */ | |
3085 | bin &= ~ BYTE_OPERATION; | |
3086 | ||
3087 | if (byte_op) | |
3088 | { | |
3089 | as_bad (_("%s instruction does not accept a .b suffix"), | |
3090 | opcode->name); | |
3091 | return 0; | |
3092 | } | |
3093 | else if (! addr_op) | |
3094 | extended |= BYTE_OPERATION; | |
3095 | } | |
3096 | else if (! addr_op) | |
3097 | extended |= BYTE_OPERATION; | |
3098 | ||
3099 | if (op1.ol != 0 && ((extended & 0xf) != 0)) | |
3100 | { | |
3101 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
3102 | extended &= ~ 0xf; | |
3103 | } | |
3104 | ||
3105 | if (op1.mode == OP_EXP) | |
3106 | { | |
3107 | if (op1.exp.X_op == O_constant) | |
3108 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
638d3803 | 3109 | |
13761a11 NC |
3110 | else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ |
3111 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
3112 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
3113 | else | |
3114 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
3115 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
3116 | } | |
638d3803 | 3117 | |
13761a11 NC |
3118 | /* Emit the extension word. */ |
3119 | bfd_putl16 (extended, frag); | |
3120 | frag += 2; | |
3121 | where += 2; | |
3122 | } | |
3123 | ||
3124 | bin |= op1.reg | (op1.am << 4); | |
b18c562e | 3125 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
3126 | frag += 2; |
3127 | where += 2; | |
b18c562e NC |
3128 | |
3129 | if (op1.mode == OP_EXP) | |
2469cfa2 | 3130 | { |
13761a11 NC |
3131 | if (op1.exp.X_op == O_constant) |
3132 | { | |
3133 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
3134 | } | |
b18c562e | 3135 | else |
13761a11 NC |
3136 | { |
3137 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
3138 | ||
3139 | if (!extended_op) | |
3140 | { | |
3141 | if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ | |
3142 | fix_new_exp (frag_now, where, 2, | |
3143 | &(op1.exp), FALSE, CHECK_RELOC_MSP430); | |
3144 | else | |
3145 | fix_new_exp (frag_now, where, 2, | |
3146 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
3147 | } | |
3148 | } | |
2469cfa2 | 3149 | } |
13761a11 NC |
3150 | |
3151 | dwarf2_emit_insn (insn_length); | |
b18c562e | 3152 | break; |
2469cfa2 | 3153 | |
b18c562e NC |
3154 | case 3: /* Conditional jumps instructions. */ |
3155 | line = extract_operand (line, l1, sizeof (l1)); | |
3156 | /* l1 is a label. */ | |
3157 | if (l1[0]) | |
2469cfa2 | 3158 | { |
b18c562e NC |
3159 | char *m = l1; |
3160 | expressionS exp; | |
2469cfa2 | 3161 | |
b18c562e NC |
3162 | if (*m == '$') |
3163 | m++; | |
2469cfa2 | 3164 | |
b18c562e | 3165 | parse_exp (m, &exp); |
2469cfa2 | 3166 | |
b18c562e | 3167 | /* In order to handle something like: |
2469cfa2 | 3168 | |
b18c562e NC |
3169 | and #0x8000, r5 |
3170 | tst r5 | |
3171 | jz 4 ; skip next 4 bytes | |
3172 | inv r5 | |
3173 | inc r5 | |
3174 | nop ; will jump here if r5 positive or zero | |
2469cfa2 | 3175 | |
b18c562e | 3176 | jCOND -n ;assumes jump n bytes backward: |
2469cfa2 | 3177 | |
b18c562e NC |
3178 | mov r5,r6 |
3179 | jmp -2 | |
2469cfa2 | 3180 | |
b18c562e NC |
3181 | is equal to: |
3182 | lab: | |
3183 | mov r5,r6 | |
3184 | jmp lab | |
3185 | ||
3186 | jCOND $n ; jump from PC in either direction. */ | |
2469cfa2 | 3187 | |
b18c562e NC |
3188 | if (exp.X_op == O_constant) |
3189 | { | |
3190 | int x = exp.X_add_number; | |
2469cfa2 | 3191 | |
b18c562e NC |
3192 | if (x & 1) |
3193 | { | |
3194 | as_warn (_("Even number required. Rounded to %d"), x + 1); | |
3195 | x++; | |
3196 | } | |
2469cfa2 | 3197 | |
b18c562e NC |
3198 | if ((*l1 == '$' && x > 0) || x < 0) |
3199 | x -= 2; | |
2469cfa2 | 3200 | |
b18c562e NC |
3201 | x >>= 1; |
3202 | ||
3203 | if (x > 512 || x < -511) | |
3204 | { | |
3205 | as_bad (_("Wrong displacement %d"), x << 1); | |
3206 | break; | |
3207 | } | |
3208 | ||
13761a11 NC |
3209 | insn_length += 2; |
3210 | frag = frag_more (2); /* Instr size is 1 word. */ | |
3211 | ||
b18c562e NC |
3212 | bin |= x & 0x3ff; |
3213 | bfd_putl16 ((bfd_vma) bin, frag); | |
3214 | } | |
3215 | else if (exp.X_op == O_symbol && *l1 != '$') | |
2469cfa2 | 3216 | { |
13761a11 NC |
3217 | insn_length += 2; |
3218 | frag = frag_more (2); /* Instr size is 1 word. */ | |
b18c562e NC |
3219 | where = frag - frag_now->fr_literal; |
3220 | fix_new_exp (frag_now, where, 2, | |
3221 | &exp, TRUE, BFD_RELOC_MSP430_10_PCREL); | |
3222 | ||
3223 | bfd_putl16 ((bfd_vma) bin, frag); | |
2469cfa2 | 3224 | } |
b18c562e | 3225 | else if (*l1 == '$') |
2469cfa2 | 3226 | { |
b18c562e | 3227 | as_bad (_("instruction requires label sans '$'")); |
2469cfa2 | 3228 | } |
b18c562e | 3229 | else |
13761a11 NC |
3230 | as_bad (_ |
3231 | ("instruction requires label or value in range -511:512")); | |
3232 | dwarf2_emit_insn (insn_length); | |
2a9a06c1 | 3233 | break; |
2469cfa2 | 3234 | } |
b18c562e NC |
3235 | else |
3236 | { | |
3237 | as_bad (_("instruction requires label")); | |
3238 | break; | |
3239 | } | |
3240 | break; | |
2469cfa2 | 3241 | |
b18c562e | 3242 | case 4: /* Extended jumps. */ |
77592908 DD |
3243 | if (!msp430_enable_polys) |
3244 | { | |
20203fb9 | 3245 | as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); |
77592908 DD |
3246 | break; |
3247 | } | |
638d3803 | 3248 | |
b18c562e NC |
3249 | line = extract_operand (line, l1, sizeof (l1)); |
3250 | if (l1[0]) | |
2469cfa2 | 3251 | { |
b18c562e NC |
3252 | char *m = l1; |
3253 | expressionS exp; | |
2469cfa2 | 3254 | |
b18c562e NC |
3255 | /* Ignore absolute addressing. make it PC relative anyway. */ |
3256 | if (*m == '#' || *m == '$') | |
3257 | m++; | |
2469cfa2 | 3258 | |
b18c562e NC |
3259 | parse_exp (m, & exp); |
3260 | if (exp.X_op == O_symbol) | |
2469cfa2 | 3261 | { |
b18c562e NC |
3262 | /* Relaxation required. */ |
3263 | struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb]; | |
3264 | ||
638d3803 | 3265 | if (target_is_430x ()) |
13761a11 NC |
3266 | rc = msp430x_rcodes[opcode->insn_opnumb]; |
3267 | ||
3268 | /* The parameter to dwarf2_emit_insn is actually the offset to | |
3269 | the start of the insn from the fix piece of instruction that | |
3270 | was emitted. Since next fragments may have variable size we | |
3271 | tie debug info to the beginning of the instruction. */ | |
3272 | insn_length += 8; | |
3e470ab5 | 3273 | frag = frag_more (8); |
2a9a06c1 | 3274 | dwarf2_emit_insn (0); |
3e470ab5 DD |
3275 | bfd_putl16 ((bfd_vma) rc.sop, frag); |
3276 | frag = frag_variant (rs_machine_dependent, 8, 2, | |
13761a11 NC |
3277 | /* Wild guess. */ |
3278 | ENCODE_RELAX (rc.lpos, STATE_BITS10), | |
b18c562e NC |
3279 | exp.X_add_symbol, |
3280 | 0, /* Offset is zero if jump dist less than 1K. */ | |
3281 | (char *) frag); | |
3282 | break; | |
2469cfa2 NC |
3283 | } |
3284 | } | |
b18c562e NC |
3285 | |
3286 | as_bad (_("instruction requires label")); | |
3287 | break; | |
3288 | ||
3289 | case 5: /* Emulated extended branches. */ | |
77592908 DD |
3290 | if (!msp430_enable_polys) |
3291 | { | |
20203fb9 | 3292 | as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); |
77592908 DD |
3293 | break; |
3294 | } | |
b18c562e NC |
3295 | line = extract_operand (line, l1, sizeof (l1)); |
3296 | if (l1[0]) | |
2469cfa2 | 3297 | { |
b18c562e NC |
3298 | char * m = l1; |
3299 | expressionS exp; | |
3300 | ||
3301 | /* Ignore absolute addressing. make it PC relative anyway. */ | |
3302 | if (*m == '#' || *m == '$') | |
3303 | m++; | |
3304 | ||
3305 | parse_exp (m, & exp); | |
3306 | if (exp.X_op == O_symbol) | |
3307 | { | |
3308 | /* Relaxation required. */ | |
3309 | struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb]; | |
3310 | ||
638d3803 | 3311 | if (target_is_430x ()) |
13761a11 NC |
3312 | hc = msp430x_hcodes[opcode->insn_opnumb]; |
3313 | ||
3314 | insn_length += 8; | |
3e470ab5 | 3315 | frag = frag_more (8); |
2a9a06c1 | 3316 | dwarf2_emit_insn (0); |
3e470ab5 DD |
3317 | bfd_putl16 ((bfd_vma) hc.op0, frag); |
3318 | bfd_putl16 ((bfd_vma) hc.op1, frag+2); | |
3319 | ||
3320 | frag = frag_variant (rs_machine_dependent, 8, 2, | |
b18c562e NC |
3321 | ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */ |
3322 | exp.X_add_symbol, | |
3323 | 0, /* Offset is zero if jump dist less than 1K. */ | |
3324 | (char *) frag); | |
3325 | break; | |
3326 | } | |
2469cfa2 NC |
3327 | } |
3328 | ||
b18c562e NC |
3329 | as_bad (_("instruction requires label")); |
3330 | break; | |
2469cfa2 | 3331 | |
b18c562e | 3332 | default: |
79cf5950 | 3333 | as_bad (_("Illegal instruction or not implemented opcode.")); |
b18c562e | 3334 | } |
2469cfa2 | 3335 | |
b18c562e NC |
3336 | input_line_pointer = line; |
3337 | return 0; | |
3338 | } | |
2469cfa2 | 3339 | |
b18c562e NC |
3340 | void |
3341 | md_assemble (char * str) | |
3342 | { | |
3343 | struct msp430_opcode_s * opcode; | |
3344 | char cmd[32]; | |
3345 | unsigned int i = 0; | |
2469cfa2 | 3346 | |
b18c562e NC |
3347 | str = skip_space (str); /* Skip leading spaces. */ |
3348 | str = extract_cmd (str, cmd, sizeof (cmd)); | |
2469cfa2 | 3349 | |
b18c562e NC |
3350 | while (cmd[i] && i < sizeof (cmd)) |
3351 | { | |
3352 | char a = TOLOWER (cmd[i]); | |
3353 | cmd[i] = a; | |
3354 | i++; | |
2469cfa2 | 3355 | } |
2469cfa2 | 3356 | |
b18c562e | 3357 | if (!cmd[0]) |
2469cfa2 | 3358 | { |
b18c562e NC |
3359 | as_bad (_("can't find opcode ")); |
3360 | return; | |
3361 | } | |
2469cfa2 | 3362 | |
b18c562e | 3363 | opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd); |
2469cfa2 | 3364 | |
b18c562e NC |
3365 | if (opcode == NULL) |
3366 | { | |
3367 | as_bad (_("unknown opcode `%s'"), cmd); | |
3368 | return; | |
2469cfa2 | 3369 | } |
2469cfa2 | 3370 | |
b18c562e NC |
3371 | { |
3372 | char *__t = input_line_pointer; | |
2469cfa2 | 3373 | |
b18c562e NC |
3374 | msp430_operands (opcode, str); |
3375 | input_line_pointer = __t; | |
3376 | } | |
3377 | } | |
2469cfa2 NC |
3378 | |
3379 | /* GAS will call this function for each section at the end of the assembly, | |
3380 | to permit the CPU backend to adjust the alignment of a section. */ | |
3381 | ||
3382 | valueT | |
b18c562e | 3383 | md_section_align (asection * seg, valueT addr) |
2469cfa2 NC |
3384 | { |
3385 | int align = bfd_get_section_alignment (stdoutput, seg); | |
3386 | ||
3387 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
3388 | } | |
3389 | ||
3390 | /* If you define this macro, it should return the offset between the | |
3391 | address of a PC relative fixup and the position from which the PC | |
3392 | relative adjustment should be made. On many processors, the base | |
3393 | of a PC relative instruction is the next instruction, so this | |
3394 | macro would return the length of an instruction. */ | |
3395 | ||
3396 | long | |
b18c562e | 3397 | md_pcrel_from_section (fixS * fixp, segT sec) |
2469cfa2 NC |
3398 | { |
3399 | if (fixp->fx_addsy != (symbolS *) NULL | |
3400 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
3401 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
3402 | return 0; | |
3403 | ||
3404 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
3405 | } | |
3406 | ||
77592908 DD |
3407 | /* Replaces standard TC_FORCE_RELOCATION_LOCAL. |
3408 | Now it handles the situation when relocations | |
13761a11 | 3409 | have to be passed to linker. */ |
77592908 | 3410 | int |
13761a11 | 3411 | msp430_force_relocation_local (fixS *fixp) |
77592908 | 3412 | { |
13761a11 NC |
3413 | if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL) |
3414 | return 1; | |
13761a11 NC |
3415 | if (fixp->fx_pcrel) |
3416 | return 1; | |
77592908 DD |
3417 | if (msp430_enable_polys |
3418 | && !msp430_enable_relax) | |
3419 | return 1; | |
13761a11 NC |
3420 | |
3421 | return (!fixp->fx_pcrel | |
3422 | || generic_force_reloc (fixp)); | |
77592908 DD |
3423 | } |
3424 | ||
3425 | ||
2469cfa2 NC |
3426 | /* GAS will call this for each fixup. It should store the correct |
3427 | value in the object file. */ | |
2469cfa2 | 3428 | void |
55cf6793 | 3429 | md_apply_fix (fixS * fixp, valueT * valuep, segT seg) |
2469cfa2 | 3430 | { |
b18c562e | 3431 | unsigned char * where; |
2469cfa2 NC |
3432 | unsigned long insn; |
3433 | long value; | |
3434 | ||
3435 | if (fixp->fx_addsy == (symbolS *) NULL) | |
3436 | { | |
3437 | value = *valuep; | |
3438 | fixp->fx_done = 1; | |
3439 | } | |
3440 | else if (fixp->fx_pcrel) | |
3441 | { | |
3442 | segT s = S_GET_SEGMENT (fixp->fx_addsy); | |
3443 | ||
3444 | if (fixp->fx_addsy && (s == seg || s == absolute_section)) | |
3445 | { | |
18af0b39 NC |
3446 | /* FIXME: We can appear here only in case if we perform a pc |
3447 | relative jump to the label which is i) global, ii) locally | |
3448 | defined or this is a jump to an absolute symbol. | |
3449 | If this is an absolute symbol -- everything is OK. | |
3450 | If this is a global label, we've got a symbol value defined | |
3451 | twice: | |
3452 | 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset | |
3453 | from this section start | |
3454 | 2. *valuep will contain the real offset from jump insn to the | |
3455 | label | |
3456 | So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep); | |
3457 | will be incorrect. Therefore remove s_get_value. */ | |
3458 | value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep; | |
2469cfa2 NC |
3459 | fixp->fx_done = 1; |
3460 | } | |
3461 | else | |
3462 | value = *valuep; | |
3463 | } | |
3464 | else | |
3465 | { | |
3466 | value = fixp->fx_offset; | |
3467 | ||
3468 | if (fixp->fx_subsy != (symbolS *) NULL) | |
3469 | { | |
3470 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
3471 | { | |
3472 | value -= S_GET_VALUE (fixp->fx_subsy); | |
3473 | fixp->fx_done = 1; | |
3474 | } | |
2469cfa2 NC |
3475 | } |
3476 | } | |
3477 | ||
77592908 DD |
3478 | fixp->fx_no_overflow = 1; |
3479 | ||
638d3803 | 3480 | /* If polymorphs are enabled and relax disabled. |
13761a11 | 3481 | do not kill any relocs and pass them to linker. */ |
638d3803 | 3482 | if (msp430_enable_polys |
77592908 | 3483 | && !msp430_enable_relax) |
2469cfa2 | 3484 | { |
638d3803 | 3485 | if (!fixp->fx_addsy || (fixp->fx_addsy |
77592908 | 3486 | && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)) |
79cf5950 | 3487 | fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */ |
77592908 DD |
3488 | else |
3489 | fixp->fx_done = 0; | |
2469cfa2 NC |
3490 | } |
3491 | ||
3492 | if (fixp->fx_done) | |
3493 | { | |
3494 | /* Fetch the instruction, insert the fully resolved operand | |
8cd5b113 | 3495 | value, and stuff the instruction back again. */ |
2132e3a3 | 3496 | where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where; |
2469cfa2 NC |
3497 | |
3498 | insn = bfd_getl16 (where); | |
3499 | ||
3500 | switch (fixp->fx_r_type) | |
3501 | { | |
3502 | case BFD_RELOC_MSP430_10_PCREL: | |
3503 | if (value & 1) | |
3504 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3505 | _("odd address operand: %ld"), value); | |
3506 | ||
3507 | /* Jumps are in words. */ | |
3508 | value >>= 1; | |
3509 | --value; /* Correct PC. */ | |
3510 | ||
3511 | if (value < -512 || value > 511) | |
3512 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3513 | _("operand out of range: %ld"), value); | |
3514 | ||
3515 | value &= 0x3ff; /* get rid of extended sign */ | |
3516 | bfd_putl16 ((bfd_vma) (value | insn), where); | |
3517 | break; | |
3518 | ||
13761a11 | 3519 | case BFD_RELOC_MSP430X_PCR16: |
b18c562e | 3520 | case BFD_RELOC_MSP430_RL_PCREL: |
2469cfa2 NC |
3521 | case BFD_RELOC_MSP430_16_PCREL: |
3522 | if (value & 1) | |
3523 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3524 | _("odd address operand: %ld"), value); | |
13761a11 | 3525 | /* Fall through. */ |
2469cfa2 NC |
3526 | |
3527 | case BFD_RELOC_MSP430_16_PCREL_BYTE: | |
3528 | /* Nothing to be corrected here. */ | |
3529 | if (value < -32768 || value > 65536) | |
3530 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3531 | _("operand out of range: %ld"), value); | |
13761a11 | 3532 | /* Fall through. */ |
2469cfa2 | 3533 | |
13761a11 NC |
3534 | case BFD_RELOC_MSP430X_ABS16: |
3535 | case BFD_RELOC_MSP430_16: | |
3536 | case BFD_RELOC_16: | |
3537 | case BFD_RELOC_MSP430_16_BYTE: | |
2469cfa2 NC |
3538 | value &= 0xffff; /* Get rid of extended sign. */ |
3539 | bfd_putl16 ((bfd_vma) value, where); | |
3540 | break; | |
3541 | ||
3542 | case BFD_RELOC_32: | |
3543 | bfd_putl16 ((bfd_vma) value, where); | |
3544 | break; | |
3545 | ||
13761a11 NC |
3546 | case BFD_RELOC_MSP430_ABS8: |
3547 | case BFD_RELOC_8: | |
3548 | bfd_put_8 (NULL, (bfd_vma) value, where); | |
3549 | break; | |
3550 | ||
3551 | case BFD_RELOC_MSP430X_ABS20_EXT_SRC: | |
3552 | case BFD_RELOC_MSP430X_PCR20_EXT_SRC: | |
3553 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); | |
638d3803 | 3554 | value >>= 16; |
13761a11 NC |
3555 | bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where); |
3556 | break; | |
3557 | ||
3558 | case BFD_RELOC_MSP430X_ABS20_ADR_SRC: | |
3559 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
638d3803 | 3560 | value >>= 16; |
13761a11 NC |
3561 | bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where); |
3562 | break; | |
3563 | ||
3564 | case BFD_RELOC_MSP430X_ABS20_EXT_ODST: | |
3565 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6); | |
3566 | value >>= 16; | |
3567 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3568 | break; | |
3569 | ||
3570 | case BFD_RELOC_MSP430X_PCR20_CALL: | |
3571 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
3572 | value >>= 16; | |
3573 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3574 | break; | |
3575 | ||
3576 | case BFD_RELOC_MSP430X_ABS20_EXT_DST: | |
3577 | case BFD_RELOC_MSP430X_PCR20_EXT_DST: | |
3578 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); | |
3579 | value >>= 16; | |
3580 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3581 | break; | |
3582 | ||
3583 | case BFD_RELOC_MSP430X_PCR20_EXT_ODST: | |
3584 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6); | |
3585 | value >>= 16; | |
3586 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3587 | break; | |
3588 | ||
3589 | case BFD_RELOC_MSP430X_ABS20_ADR_DST: | |
3590 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
3591 | value >>= 16; | |
3592 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
2469cfa2 | 3593 | break; |
638d3803 | 3594 | |
2469cfa2 NC |
3595 | default: |
3596 | as_fatal (_("line %d: unknown relocation type: 0x%x"), | |
3597 | fixp->fx_line, fixp->fx_r_type); | |
3598 | break; | |
3599 | } | |
3600 | } | |
3601 | else | |
3602 | { | |
3603 | fixp->fx_addnumber = value; | |
3604 | } | |
2469cfa2 NC |
3605 | } |
3606 | ||
13761a11 NC |
3607 | static bfd_boolean |
3608 | S_IS_GAS_LOCAL (symbolS * s) | |
3609 | { | |
3610 | const char * name; | |
3611 | unsigned int len; | |
3612 | ||
3613 | if (s == NULL) | |
3614 | return FALSE; | |
3615 | name = S_GET_NAME (s); | |
3616 | len = strlen (name) - 1; | |
638d3803 | 3617 | |
13761a11 NC |
3618 | return name[len] == 1 || name[len] == 2; |
3619 | } | |
3620 | ||
7be1c489 AM |
3621 | /* GAS will call this to generate a reloc, passing the resulting reloc |
3622 | to `bfd_install_relocation'. This currently works poorly, as | |
3623 | `bfd_install_relocation' often does the wrong thing, and instances of | |
3624 | `tc_gen_reloc' have been written to work around the problems, which | |
3625 | in turns makes it difficult to fix `bfd_install_relocation'. */ | |
2469cfa2 NC |
3626 | |
3627 | /* If while processing a fixup, a reloc really needs to be created | |
3628 | then it is done here. */ | |
3629 | ||
13761a11 | 3630 | arelent ** |
b18c562e | 3631 | tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp) |
2469cfa2 | 3632 | { |
13761a11 NC |
3633 | static arelent * no_relocs = NULL; |
3634 | static arelent * relocs[MAX_RELOC_EXPANSION + 1]; | |
3635 | arelent *reloc; | |
2469cfa2 | 3636 | |
b18c562e | 3637 | reloc = xmalloc (sizeof (arelent)); |
2469cfa2 NC |
3638 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3639 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
13761a11 | 3640 | |
2469cfa2 NC |
3641 | if (reloc->howto == (reloc_howto_type *) NULL) |
3642 | { | |
3643 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3644 | _("reloc %d not supported by object file format"), | |
3645 | (int) fixp->fx_r_type); | |
13761a11 NC |
3646 | free (reloc); |
3647 | return & no_relocs; | |
3648 | } | |
3649 | ||
3650 | relocs[0] = reloc; | |
3651 | relocs[1] = NULL; | |
3652 | ||
3653 | if (fixp->fx_subsy | |
3654 | && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
3655 | { | |
3656 | fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy); | |
3657 | fixp->fx_subsy = NULL; | |
2469cfa2 NC |
3658 | } |
3659 | ||
13761a11 NC |
3660 | if (fixp->fx_addsy && fixp->fx_subsy) |
3661 | { | |
3662 | asection *asec, *ssec; | |
3663 | ||
3664 | asec = S_GET_SEGMENT (fixp->fx_addsy); | |
3665 | ssec = S_GET_SEGMENT (fixp->fx_subsy); | |
3666 | ||
3667 | /* If we have a difference between two different, non-absolute symbols | |
3668 | we must generate two relocs (one for each symbol) and allow the | |
3669 | linker to resolve them - relaxation may change the distances between | |
3670 | symbols, even local symbols defined in the same section. | |
3671 | ||
3672 | Unfortunately we cannot do this with assembler generated local labels | |
3673 | because there can be multiple incarnations of the same label, with | |
3674 | exactly the same name, in any given section and the linker will have | |
3675 | no way to identify the correct one. Instead we just have to hope | |
3676 | that no relaxtion will occur between the local label and the other | |
3677 | symbol in the expression. | |
3678 | ||
3679 | Similarly we have to compute differences between symbols in the .eh_frame | |
3680 | section as the linker is not smart enough to apply relocations there | |
3681 | before attempting to process it. */ | |
3682 | if ((ssec != absolute_section || asec != absolute_section) | |
3683 | && (fixp->fx_addsy != fixp->fx_subsy) | |
3684 | && strcmp (ssec->name, ".eh_frame") != 0 | |
3685 | && ! S_IS_GAS_LOCAL (fixp->fx_addsy) | |
3686 | && ! S_IS_GAS_LOCAL (fixp->fx_subsy)) | |
3687 | { | |
3688 | arelent * reloc2 = xmalloc (sizeof * reloc); | |
2469cfa2 | 3689 | |
13761a11 NC |
3690 | relocs[0] = reloc2; |
3691 | relocs[1] = reloc; | |
2469cfa2 | 3692 | |
13761a11 NC |
3693 | reloc2->address = reloc->address; |
3694 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, | |
3695 | BFD_RELOC_MSP430_SYM_DIFF); | |
3696 | reloc2->addend = - S_GET_VALUE (fixp->fx_subsy); | |
3697 | ||
3698 | if (ssec == absolute_section) | |
3699 | reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; | |
3700 | else | |
3701 | { | |
3702 | reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3703 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); | |
3704 | } | |
3705 | ||
638d3803 | 3706 | reloc->addend = fixp->fx_offset; |
13761a11 NC |
3707 | if (asec == absolute_section) |
3708 | { | |
3709 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
3710 | reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; | |
3711 | } | |
3712 | else | |
3713 | { | |
3714 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3715 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
3716 | } | |
3717 | ||
3718 | fixp->fx_pcrel = 0; | |
3719 | fixp->fx_done = 1; | |
3720 | return relocs; | |
3721 | } | |
3722 | else | |
3723 | { | |
3724 | char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal; | |
3725 | ||
3726 | reloc->addend = (S_GET_VALUE (fixp->fx_addsy) | |
3727 | - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset); | |
3728 | ||
3729 | switch (fixp->fx_r_type) | |
3730 | { | |
3731 | case BFD_RELOC_8: | |
3732 | md_number_to_chars (fixpos, reloc->addend, 1); | |
3733 | break; | |
3734 | ||
3735 | case BFD_RELOC_16: | |
3736 | md_number_to_chars (fixpos, reloc->addend, 2); | |
3737 | break; | |
3738 | ||
3739 | case BFD_RELOC_24: | |
3740 | md_number_to_chars (fixpos, reloc->addend, 3); | |
3741 | break; | |
3742 | ||
3743 | case BFD_RELOC_32: | |
3744 | md_number_to_chars (fixpos, reloc->addend, 4); | |
3745 | break; | |
3746 | ||
3747 | default: | |
3748 | reloc->sym_ptr_ptr | |
3749 | = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr; | |
3750 | return relocs; | |
3751 | } | |
3752 | ||
3753 | free (reloc); | |
3754 | return & no_relocs; | |
3755 | } | |
3756 | } | |
3757 | else | |
3758 | { | |
3759 | #if 0 | |
3760 | if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16 | |
3761 | && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section) | |
3762 | { | |
3763 | bfd_vma amount = S_GET_VALUE (fixp->fx_addsy); | |
3764 | char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal; | |
3765 | ||
3766 | md_number_to_chars (fixpos, amount, 2); | |
3767 | free (reloc); | |
3768 | return & no_relocs; | |
3769 | } | |
3770 | #endif | |
3771 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3772 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
3773 | reloc->addend = fixp->fx_offset; | |
3774 | ||
3775 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
3776 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3777 | reloc->address = fixp->fx_offset; | |
3778 | } | |
3779 | ||
3780 | return relocs; | |
2469cfa2 NC |
3781 | } |
3782 | ||
b18c562e NC |
3783 | int |
3784 | md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, | |
3785 | asection * segment_type ATTRIBUTE_UNUSED) | |
3786 | { | |
3787 | if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
3788 | { | |
3789 | /* This is a jump -> pcrel mode. Nothing to do much here. | |
3790 | Return value == 2. */ | |
3791 | fragP->fr_subtype = | |
3792 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10); | |
3793 | } | |
3794 | else if (fragP->fr_symbol) | |
3795 | { | |
3796 | /* Its got a segment, but its not ours. Even if fr_symbol is in | |
79cf5950 | 3797 | an absolute segment, we don't know a displacement until we link |
b18c562e NC |
3798 | object files. So it will always be long. This also applies to |
3799 | labels in a subsegment of current. Liker may relax it to short | |
3800 | jump later. Return value == 8. */ | |
3801 | fragP->fr_subtype = | |
3802 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD); | |
3803 | } | |
3804 | else | |
3805 | { | |
3806 | /* We know the abs value. may be it is a jump to fixed address. | |
79cf5950 | 3807 | Impossible in our case, cause all constants already handled. */ |
b18c562e NC |
3808 | fragP->fr_subtype = |
3809 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF); | |
3810 | } | |
2469cfa2 | 3811 | |
b18c562e NC |
3812 | return md_relax_table[fragP->fr_subtype].rlx_length; |
3813 | } | |
3814 | ||
3815 | void | |
3816 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, | |
3817 | asection * sec ATTRIBUTE_UNUSED, | |
3818 | fragS * fragP) | |
2469cfa2 | 3819 | { |
b18c562e NC |
3820 | char * where = 0; |
3821 | int rela = -1; | |
3822 | int i; | |
3823 | struct rcodes_s * cc = NULL; | |
3824 | struct hcodes_s * hc = NULL; | |
3825 | ||
3826 | switch (fragP->fr_subtype) | |
3827 | { | |
3828 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10): | |
3829 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10): | |
3830 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10): | |
3831 | /* We do not have to convert anything here. | |
3832 | Just apply a fix. */ | |
3833 | rela = BFD_RELOC_MSP430_10_PCREL; | |
3834 | break; | |
3835 | ||
3836 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD): | |
3837 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF): | |
3838 | /* Convert uncond branch jmp lab -> br lab. */ | |
638d3803 | 3839 | if (target_is_430x ()) |
13761a11 | 3840 | cc = msp430x_rcodes + 7; |
638d3803 NC |
3841 | else |
3842 | cc = msp430_rcodes + 7; | |
b18c562e NC |
3843 | where = fragP->fr_literal + fragP->fr_fix; |
3844 | bfd_putl16 (cc->lop0, where); | |
3845 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3846 | fragP->fr_fix += 2; | |
3847 | break; | |
3848 | ||
3849 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD): | |
3850 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF): | |
3851 | { | |
3852 | /* Other simple branches. */ | |
3853 | int insn = bfd_getl16 (fragP->fr_opcode); | |
3854 | ||
3855 | insn &= 0xffff; | |
3856 | /* Find actual instruction. */ | |
638d3803 | 3857 | if (target_is_430x ()) |
13761a11 NC |
3858 | { |
3859 | for (i = 0; i < 7 && !cc; i++) | |
3860 | if (msp430x_rcodes[i].sop == insn) | |
3861 | cc = msp430x_rcodes + i; | |
3862 | } | |
3863 | else | |
3864 | { | |
3865 | for (i = 0; i < 7 && !cc; i++) | |
3866 | if (msp430_rcodes[i].sop == insn) | |
3867 | cc = & msp430_rcodes[i]; | |
3868 | } | |
3869 | ||
b18c562e NC |
3870 | if (!cc || !cc->name) |
3871 | as_fatal (_("internal inconsistency problem in %s: insn %04lx"), | |
3872 | __FUNCTION__, (long) insn); | |
3873 | where = fragP->fr_literal + fragP->fr_fix; | |
3874 | bfd_putl16 (cc->lop0, where); | |
3875 | bfd_putl16 (cc->lop1, where + 2); | |
3876 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3877 | fragP->fr_fix += 4; | |
3878 | } | |
3879 | break; | |
3880 | ||
3881 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD): | |
3882 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF): | |
638d3803 | 3883 | if (target_is_430x ()) |
13761a11 | 3884 | cc = msp430x_rcodes + 6; |
638d3803 NC |
3885 | else |
3886 | cc = msp430_rcodes + 6; | |
b18c562e NC |
3887 | where = fragP->fr_literal + fragP->fr_fix; |
3888 | bfd_putl16 (cc->lop0, where); | |
3889 | bfd_putl16 (cc->lop1, where + 2); | |
3890 | bfd_putl16 (cc->lop2, where + 4); | |
3891 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3892 | fragP->fr_fix += 6; | |
3893 | break; | |
3894 | ||
3895 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10): | |
3896 | { | |
3897 | int insn = bfd_getl16 (fragP->fr_opcode + 2); | |
3898 | ||
3899 | insn &= 0xffff; | |
638d3803 | 3900 | if (target_is_430x ()) |
13761a11 NC |
3901 | { |
3902 | for (i = 0; i < 4 && !hc; i++) | |
3903 | if (msp430x_hcodes[i].op1 == insn) | |
3904 | hc = msp430x_hcodes + i; | |
3905 | } | |
3906 | else | |
3907 | { | |
3908 | for (i = 0; i < 4 && !hc; i++) | |
3909 | if (msp430_hcodes[i].op1 == insn) | |
3910 | hc = &msp430_hcodes[i]; | |
3911 | } | |
b18c562e NC |
3912 | if (!hc || !hc->name) |
3913 | as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), | |
3914 | __FUNCTION__, (long) insn); | |
3915 | rela = BFD_RELOC_MSP430_10_PCREL; | |
3916 | /* Apply a fix for a first label if necessary. | |
3917 | another fix will be applied to the next word of insn anyway. */ | |
3918 | if (hc->tlab == 2) | |
3919 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
13761a11 | 3920 | fragP->fr_offset, TRUE, rela); |
b18c562e NC |
3921 | fragP->fr_fix += 2; |
3922 | } | |
3923 | ||
3924 | break; | |
3925 | ||
3926 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD): | |
3927 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF): | |
3928 | { | |
3929 | int insn = bfd_getl16 (fragP->fr_opcode + 2); | |
3930 | ||
3931 | insn &= 0xffff; | |
638d3803 | 3932 | if (target_is_430x ()) |
13761a11 NC |
3933 | { |
3934 | for (i = 0; i < 4 && !hc; i++) | |
3935 | if (msp430x_hcodes[i].op1 == insn) | |
3936 | hc = msp430x_hcodes + i; | |
3937 | } | |
3938 | else | |
3939 | { | |
3940 | for (i = 0; i < 4 && !hc; i++) | |
3941 | if (msp430_hcodes[i].op1 == insn) | |
3942 | hc = & msp430_hcodes[i]; | |
3943 | } | |
b18c562e NC |
3944 | if (!hc || !hc->name) |
3945 | as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), | |
3946 | __FUNCTION__, (long) insn); | |
3947 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3948 | where = fragP->fr_literal + fragP->fr_fix; | |
3949 | bfd_putl16 (hc->lop0, where); | |
3950 | bfd_putl16 (hc->lop1, where + 2); | |
3951 | bfd_putl16 (hc->lop2, where + 4); | |
3952 | fragP->fr_fix += 6; | |
3953 | } | |
3954 | break; | |
3955 | ||
3956 | default: | |
3957 | as_fatal (_("internal inconsistency problem in %s: %lx"), | |
3958 | __FUNCTION__, (long) fragP->fr_subtype); | |
3959 | break; | |
3960 | } | |
3961 | ||
3962 | /* Now apply fix. */ | |
3963 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
3964 | fragP->fr_offset, TRUE, rela); | |
3965 | /* Just fixed 2 bytes. */ | |
3966 | fragP->fr_fix += 2; | |
2469cfa2 NC |
3967 | } |
3968 | ||
b18c562e NC |
3969 | /* Relax fragment. Mostly stolen from hc11 and mcore |
3970 | which arches I think I know. */ | |
2469cfa2 | 3971 | |
b18c562e NC |
3972 | long |
3973 | msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP, | |
3974 | long stretch ATTRIBUTE_UNUSED) | |
2469cfa2 | 3975 | { |
b18c562e NC |
3976 | long growth; |
3977 | offsetT aim = 0; | |
3978 | symbolS *symbolP; | |
3979 | const relax_typeS *this_type; | |
3980 | const relax_typeS *start_type; | |
3981 | relax_substateT next_state; | |
3982 | relax_substateT this_state; | |
3983 | const relax_typeS *table = md_relax_table; | |
3984 | ||
3985 | /* Nothing to be done if the frag has already max size. */ | |
3986 | if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF | |
3987 | || RELAX_STATE (fragP->fr_subtype) == STATE_WORD) | |
3988 | return 0; | |
3989 | ||
3990 | if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10) | |
3991 | { | |
3992 | symbolP = fragP->fr_symbol; | |
3993 | if (symbol_resolved_p (symbolP)) | |
3994 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
3995 | __FUNCTION__); | |
3996 | /* We know the offset. calculate a distance. */ | |
3997 | aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix; | |
3998 | } | |
3999 | ||
77592908 DD |
4000 | if (!msp430_enable_relax) |
4001 | { | |
4002 | /* Relaxation is not enabled. So, make all jump as long ones | |
13761a11 | 4003 | by setting 'aim' to quite high value. */ |
77592908 DD |
4004 | aim = 0x7fff; |
4005 | } | |
638d3803 | 4006 | |
b18c562e NC |
4007 | this_state = fragP->fr_subtype; |
4008 | start_type = this_type = table + this_state; | |
4009 | ||
4010 | if (aim < 0) | |
4011 | { | |
4012 | /* Look backwards. */ | |
4013 | for (next_state = this_type->rlx_more; next_state;) | |
3e470ab5 | 4014 | if (aim >= this_type->rlx_backward || !this_type->rlx_backward) |
b18c562e NC |
4015 | next_state = 0; |
4016 | else | |
4017 | { | |
4018 | /* Grow to next state. */ | |
4019 | this_state = next_state; | |
4020 | this_type = table + this_state; | |
4021 | next_state = this_type->rlx_more; | |
4022 | } | |
4023 | } | |
4024 | else | |
4025 | { | |
4026 | /* Look forwards. */ | |
4027 | for (next_state = this_type->rlx_more; next_state;) | |
3e470ab5 | 4028 | if (aim <= this_type->rlx_forward || !this_type->rlx_forward) |
b18c562e NC |
4029 | next_state = 0; |
4030 | else | |
4031 | { | |
4032 | /* Grow to next state. */ | |
4033 | this_state = next_state; | |
4034 | this_type = table + this_state; | |
4035 | next_state = this_type->rlx_more; | |
4036 | } | |
4037 | } | |
4038 | ||
4039 | growth = this_type->rlx_length - start_type->rlx_length; | |
4040 | if (growth != 0) | |
4041 | fragP->fr_subtype = this_state; | |
4042 | return growth; | |
2469cfa2 | 4043 | } |
13761a11 NC |
4044 | |
4045 | /* Return FALSE if the fixup in fixp should be left alone and not | |
4046 | adjusted. We return FALSE here so that linker relaxation will | |
4047 | work. */ | |
4048 | ||
4049 | bfd_boolean | |
4050 | msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED) | |
4051 | { | |
4052 | /* If the symbol is in a non-code section then it should be OK. */ | |
4053 | if (fixp->fx_addsy | |
4054 | && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0)) | |
4055 | return TRUE; | |
638d3803 | 4056 | |
13761a11 NC |
4057 | return FALSE; |
4058 | } | |
4059 | ||
4060 | /* Set the contents of the .MSP430.attributes section. */ | |
4061 | ||
4062 | void | |
4063 | msp430_md_end (void) | |
4064 | { | |
4065 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA, | |
638d3803 | 4066 | target_is_430x () ? 2 : 1); |
13761a11 NC |
4067 | |
4068 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model, | |
4069 | large_model ? 2 : 1); | |
4070 | ||
4071 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model, | |
4072 | large_model ? 2 : 1); | |
4073 | } | |
4074 | ||
4075 | /* Returns FALSE if there is a msp430 specific reason why the | |
4076 | subtraction of two same-section symbols cannot be computed by | |
4077 | the assembler. */ | |
4078 | ||
4079 | bfd_boolean | |
4080 | msp430_allow_local_subtract (expressionS * left, | |
4081 | expressionS * right, | |
4082 | segT section) | |
4083 | { | |
4084 | /* If the symbols are not in a code section then they are OK. */ | |
4085 | if ((section->flags & SEC_CODE) == 0) | |
4086 | return TRUE; | |
4087 | ||
4088 | if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol)) | |
4089 | return TRUE; | |
4090 | ||
4091 | if (left->X_add_symbol == right->X_add_symbol) | |
4092 | return TRUE; | |
4093 | ||
4094 | /* We have to assume that there may be instructions between the | |
4095 | two symbols and that relaxation may increase the distance between | |
4096 | them. */ | |
4097 | return FALSE; | |
4098 | } |